(Invited) Physical Understanding of HfZrO2/Si FeFET Memory and Its AI Applications
Authors: Takagi Shinichi , Toprasertpong Kasidit , Cai Zuocheng , Nako Eishin , Nakane Ryosho , Takenaka Mitsuru 
Published: February 2024

Since the discovery of ferroelectricity in HfO2-based dielectric films in 2011 [1], FeFETs using HfO2-based ferroelectric films as gate dielectrics have attracted strong interest and have been intensively studied in the worldwide research community for various applications including memory, logic, and AI computing. In this paper, we present our recent activities on HfZrO2 (HZO)/Si FeFETs memory [2-6] and FeFET reservoir computing [7-9] for low-power memory and AI applications.

HZO-based FeFETs are currently expected for a variety of applications such as embedded nonvolatile memory, cross-bar Commutation-in-Memory (CiM), and so on. However, the device operation has not been quantitatively understood yet. One of the fundamental questions in FeFETs is a mismatch between areal surface carrier concentration (Ns) in MOSFETs, ~1013 cm-2 at maximum, and typical polarization (P) values, ~10-20 mC/cm2. These polarization values correspond to Ns higher than 1014 cm-2 and induce an electric field across an interfacial layer (IL) of 30 MV/cm or higher, which could cause oxide breakdown. On the other hand, when a large amount of traps is included in an HZO film or an HZO/IL interface, sufficient P values can be obtained without too high Ns and the electric field [2, 4-6]. Thus, it is very important to experimentally characterize P, Ns, and trapped charge density, which were evaluated by P-V, quasi-static split C-V, and Hall measurements, respectively, [2, 3, 6] for 10-nm-thick HZO/Si n- and p-FeFETs with 0.7-nm-thick SiO2 IL. As a result, it has been found that a high trap density of around 1014 cm-2 is observed in n-FeFETs, while there is almost no hole trapping in p-FeFETs. This high electron trap density leads to the high electric field across the HZO film and resulting high P values in n-FeFETs, which is in contrast to p-FETs. Thus, the larger memory window in n-FeFETs than that in p-FeFET is attributed to the difference in P values with applying the positive and negative gate voltages.

On the other hand, we have proposed and demonstrated reservoir computing, which is one of AI calculations using a recurrent neural network, by using HZO/Si FeFETs [7-9]. Reservoir computing has recently been attracting strong attention as a method to realize real-time learning of time-series data at the edge. Furthermore, when this reservoir is represented by hardware that has input-history-dependent and nonlinear dynamics (physical reservoir), we can expect significant improvement in the energy efficiency of AI calculations. In our FeFET reservoir, the time response of a drain current of Si FeFETs was utilized as the virtual nodes. We have experimentally demonstrated high classification accuracy in speech recognition by using this HZO/Si FeFET reservoir computing with parallel data processing [9]. The spoken digit recognition task, which is an example of speech recognition applications, was performed on a basis of multiple frequency channel (cochleagram) data, which were input to multiple FeFETs. The final inference was conducted by a majority vote of the multiple FeFET reservoirs. We introduced several approaches in the proposed FeFET reservoir computing system, such as optimization of the number of virtual nodes per time step, analog and digital input waveforms, the utilization of other currents than the drain current, and the combination of different frequency channels, in order to improve the classification accuracy. The choice of a combination of frequency channels was effective in improving recognition accuracy. Also, combining the time responses of the drain, source, and substrate currents was also important. These various methods additively improved the recognition accuracy. As a result, we have experimentally demonstrated a classification accuracy of 95.9 % in the task to classify the audio waveforms of ‘0’ to ‘9’ spoken digits.

This work was supported by JST CREST (JPMJCR20C3) and JSPS KAKENHI (21H01359).

References [1] T. S. Boscke et al., Appl. Phys. Lett. 99, 102903 (2011) [2] K. Toprasertpong et al., IEDM, 570 (2019) [3] K. Toprasertpong et al., IEEE Electron Device Lett. 41, 1588 (2020) [4] K. Toprasertpong et al., Symp. VLSI Tech., TF1.5 (2020) [5] K. Toprasertpong et al., IEEE Trans. Electron Devices. 69, 7113 (2022) [6] K. Toprasertpong et al., Appl. Phys. A. 128, 1114 (2022) [7] E. Nako et al., Symp. VLSI Tech., TN1.6 (2020) [8] K. Toprasertpong et al., Comm. Eng. 1, 21 (2022) [9] E. Nako et al., Symp. VLSI Tech. and Circ., 220 (2022)