(Invited) Design of SiO2/4H-SiC Formation Process with H2O Annealing to Improve MOSFET Performance
Authors: Kita Koji , Hirai Hirohisa , Nishida Mizuki , Sakuta Ryota 
Published: February 2020

4H-SiC has attractive properties for power devices of high voltage applications, however, the performance of MOSFETs is often severely limited by the poor SiO2/SiC interface quality. One of the common techniques to passivate the interface defects is the nitrogen introduction by NO annealing [1] while introduction of wide variety of impurity elements have also been studied [2]. It has been pointed out that SiC MOS characteristics are significantly different between dry-oxidized and wet-oxidized interfaces, and wet-oxidation of SiC often results in a dramatic reduction of interface defect density [3].

To consider the possible reason of the benefit of oxidation by H2O, it should be noticed that the remained carbon at the interface as the thermal oxidation byproduct causes various kinds of interface defects formation. We found that H2O-oxidation does not leave CO-related defect structures near the interface [4]. At the same time H2O-oxidation results in the formation of less-strained SiO2 at the interface than O2-oxidation, which was clarified from the difference of the Si-O-Si vibration mode frequencies in FTIR spectra [3]. Since the formation of near-interface oxide traps of electrons with long time constants is one of the serious causes of the poor MOSFET channel properties, such improvement of near-interface structure would be an advantage of H2O-oxidation. Based on these considerations, we have demonstrated the benefit of the post-oxidation annealing in H2O (H2O-POA) after a simple dry-oxidation, as the way to improve the performance of NMOSFETs formed on 4H-SiC (0001). In this study the H2O-POA ambient was produced by bubbling of O2 or N2 flowing gas through hot water kept at ~97oC to have H2O vapor pressure of ~0.9 atm. It should be noted that this process effectively works with only < 1nm additional growth of oxide at the interface during H2O-annealing [5]. The peak channel mobility ~ 50 cm2/Vs was observed for the channel of ~ 5×1015 cm-3 doping concentration, or that ~35 cm2/Vs for the channel of ~1.3×1016 cm-3 doping concentration, which were higher values than the typical results of conventional NO-passivation processes.

We also investigated the combined passivation process of the NO annealing and the low-temperature H2O-annealing on 4H-SiC (0001), to take the advantages of both the nitrogen passivation and the interface structural modification by H2O-oxidation [6]. After the growth of ~30 nm-thick SiO2 layer in dry-O2, the annealing in NO:N2 =1:2 ambient at 1150oC (NO-POA) and the additional annealing in 0.9 atm-H2O ambient at 800oC (H2O post nitridation annealing; H2O-PNA) were sequentially conducted. From XPS analysis on SiC surface after removal of oxides by HF etching, it was found that most of the surface-terminating nitrogen atoms still remained at the interface after a short-time H2O-PNA to cause the growth of limited amount of SiO2 around a few angstroms. The interface state density (Dit) of SiO2/SiC MOS interface was minimized by such short-time H2O-PNA, while an excess time of PNA resulted in rather increase of Dit probably because a part of the surface-terminating nitrogen atoms was removed by H2O-oxidation. A significant improvement of NMOSFET mobility was also successfully demonstrated for the cases of short-time H2O-PNA.

Finally the effects of oxygen partial pressure (pO2) in H2O-annealing ambient were studied for the case of H2O-PNA. The impact of pO2 in the ambient on channel mobility was not significant as long as the amount of additional SiO2 growth during H2O-PNA was limited to around a few angstroms. However, a significant difference was observed when positive gate bias stress was applied to the stack. When ~+3 MV/cm constant voltage stress was applied, increase of flatband voltage shift was clearly observed for the samples annealed with pO2 in PNA ambient above ~0.1 atm, which is suggesting deterioration of SiO2 bulk film quality. In contrast, such deterioration was efficiently suppressed when we employed H2O-PNA ambient without any intentional introduction of O2, probably because O2 in H2O-ambient has a role to assist an additional unwanted reaction to form oxide traps in SiO2 bulk layer. These results indicates that the oxide quality on SiC would be quite sensitive to pO2 when the stack was annealed in H2O-ambient.

References

[1] J. Rozen et al., IEEE Trans. Electron Dev. 58, 3808 (2011).

[2] D. J. Lichtenwalner et al., Appl. Phys. Lett. 105, 182107 (2014).

[3] H. Hirai and K. Kita, Appl. Phys. Lett. 110, 152104 (2017).

[4] H. Hirai and K. Kita, Appl. Phys. Express 8, 021401 (2015).

[5] H. Hirai and K. Kita, Appl. Phys. Lett. 113, 172103 (2018).

[6] M. Nishida, R. Sakuta, H. Hirai, and K. Kita, ECSCRM 2018, Birmingham.