(Invited) Self-Heating in Advanced CMOS-Compatible and 2-Dimensional Semiconductor Devices
Authors: Aksamija Zlatan 
Published: May 2020

For many years the computer industry has relied for progress on the stellar rate of scaling of MOSFETs in integrated circuits. The usual expectation, based on Moore's law, is that the number of transistors packed on a chip doubles every eighteen months. Sustaining this pace requires aggressive research into the numerous bottlenecks that threaten to slow it down. In the past decade, an issue has emerged that threatens to impose an absolute limit on how many transistors can be packed onto a die. This is the issue of heat dissipation. The persistent down-scaling of nanostructures, electronic devices, sensors, and NEMS increases the surface-to-volume ratio and introduces atomic-scale disorder at boundaries and interfaces, which scatters heat carriers (phonons) and increases thermal resistance.

In this invited talk, I will present my recent work on numerical simulation and modeling of heat dissipation and phonon transport in a broad range of nanostructures, focusing primarily on extrinsic and disorder effects such as grain/sample boundaries, interfaces, edges, and alloy mass disorder. The talk revolves around the phonon Boltzmann transport equation (pBTE), while the salient feature of the work is that it employs a full phonon dispersion computed from first principles and combined with a momentum-dependent model of electron and phonon scattering. I will show that the thermoelectric response of SOI and Si-membrane-based nanostructures can be improved by employing the anisotropy of the lattice thermal conductivity, revealed in ultrathin SOI nanostructures due to the interplay between the anisotropy of the phonon dispersion and the strong boundary scattering. Next, I explore the consequences of nanostructuring on silicon/germanium and Si/Si-Ge alloy superlattices, and show that the drastic reduction and high anisotropy of thermal conductivity comes from the increased interaction of lattice waves with rough interfaces and boundaries. I will close the loop with applications of my phonon transport models to thermal effects in ultrascaled gate-all-around and junctionless MOS devices.

Going beyond silicon CMOS, two-dimensional (2D) materials have tremendous potential for next-generation nano- and optoelectronics. However, heat dissipation and its removal from hot spots in the monolayer remains a critical concern to the design of 2D-based devices. When a 2D material is supported by a substrate, the interfacial area formed between it and the substrate is often far larger than the lateral source/drain contact area. Thus, the majority of heat is removed across the 2D-substrate interface and then via the substrate. Interfaces formed between 2D vdW materials and 3D substrates are fundamentally different than same-dimension 3D-3D and 2D-2D interfaces due to the presence of a vdW gap and the different dimensionalities of the phase spaces on either side of the interface. In this invited talk, I will review the progress in understanding lattice thermal transport, both in-plane and cross-plane, in 2D mono and few-layer materials.

Several recent papers measured the TBC between various monolayers and mostly the silicon dioxide (SiO2) substrate, reporting a wide range of values due to inconsistent sample quality. Therefore, it is imperative to build predictive methods for quantifying the TBC between MLs and various substrates. Here, we use a combination of phonon dispersions from first-principles density functional perturbation theory simulations and our 2D-3D TBC model. We investigate the TBC between combinations of six atomic layers (h-BN, graphene, MoS2, MoSe2, WS2, and WSe2) and six substrates (SiO2, AlN, GaN, 6H-SiC, diamond, and Al2O3). We show that TBC is higher for softer substrates with smaller speed of sound, but of the 6 substrates we compared, amorphous SiO2 consistently produced higher TBC than crystalline substrates.

Another route to improving mobility and boosting drive current in 2D devices is to replace the monolayer with few-layered (FL) TMDs. Despite recent advances on demonstrating improved electrical performance of FL TMD FETs, there has been less attention towards their thermal management, which is crucial for modern nanoelectronic devices. We study heat dissipation in FL-WSe2 stacks using a coupled electro-thermal model and Raman thermometry experiments. The resulting rise in temperature is obtained from a FL-TBC model to shed light on self-heating and heat dissipation in such devices. We find that the temperature rise in the top layers is significantly larger than the bottom layers because the bottom layers have higher TBC and conduct heat more efficiently to the substrate. The higher temperature of top layers, in turn, significantly reduces their mobility, causing the electrical current to reroute toward the bottom layers where the TBC is higher. This rerouting improves heat removal and limits mobility degradation. We conclude that the optimal number of layers is 6-9 and that FL TMD devices are inherently thermally resilient.