(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling
Authors: Colombeau Benjamin P , Bauer Matthias , Wood Bingxi Sun , Chung Hua , Hebb Jeffrey , Huang Yi-Chiau , Tao Xianzhi , Chopra Saurabh , Dube Abhishek , Chudzik Michael , Chu Schubert 
Published: February 2020

In the past decade, the surge of demand for mobile devices has been tremendous, and has been a key growth engine for the semiconductor market. These novel devices have all capabilities for sophisticated mobile communication, as well as capabilities for gaming, computing, etc. To address the stringent requirements in terms of battery lifetime, device speed, and scaling, the design and manufacturing processes of mobile devices needs constant innovation.  Historically, Group IV epitaxial processes such as e-SiGe source/drain have played a critical role in meeting the needs for device scaling and performance in planar devices. One dramatic change that has taken place to address device scalability is the move to the multigate architecture of the FinFET (Fin Field Effect Transistor), which enables the virtual increase of the gate length and dramatically improved electrostatic performance.  Beyond FinFET, the GAA (Gate All around Transistors) device structure is one of the most promising paths for offering another disruptive leap in device scaling.  This paper discusses the increasingly critical role of epitaxy applications for enabling both of these new device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices. 

We first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, Channel mobility, sub-fin isolation, sidewall doping as well as contact resistance reduction.  

Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Examples of these SiGe channel integration approaches include SiGe replacement channel, STI last SiGe formation, cladded SiGe and SiGe condensation. There are significant integration challenges for each of these approaches from the perspective of epitaxial growth and related processes. For example, each of SiGe channel formation schemes have some specific requirements not only on the pre-clean and/or epi growth but also on the overall CMOS integration scheme (alleviation of SiGe oxidation, recess, Fin shaping, junction formation etc.). Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of  high performance, low power devices.  These topics will be explored in detail for several of the integration approaches mentioned above.

Finally, we will discuss the potentially disruptive transition to a new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.