bluuebunny/crossref_metadata_2025 huggingface dataset:
The use of expert systems in total quality management: An exploratory study
Authors: Crossfield R. T. , Dale B. G.
Published: July 2007

This paper explores the potential for the use of expert systems in total quality management (TQM). The study was carried out under the auspices of the first multi‐company programme of research into TQM. Among the findings are that it is feasible to run expert systems on personal (and other) computers in order to assist with aspects of TQM such as statistical process control, quality costing, goods receiving, corrective action procedures, supplier development, quality function deployment and field failure analysis, and that the potential application of expert systems to TQM was received with some degree of enthusiasm by the personnel with whom the concept was discussed. It is also pointed out that the most difficult task in producing an expert system is acquisition of knowledge, and that knowledge elicitation can be facilitated by use of the quality assurance mapping technique—Q‐MAP.
Process monitoring in real time: Empirical bayes approach—discrete case
Authors: Yousry M. A. , Sturm G. W. , Feltz C. J. , Noorossana R.
Published: July 2007

In this paper an empirical Bayes model is developed to monitor and analyse discrete data generated in a manufacturing process for printed circuit boards. A key feature of this analysis is the use of the current observation at time t and the posterior estimates of the distribution of the proportion nonconforming at time t – 1 to obtain a new, updated estimate of the posterior distribution at time t. The derived approach is widely applicable to statistical process control and provides a simple and fast algorithm for updating.
Electron beam testing
Authors: Wolfgang E. , Görlich S. , Kölzer J.
Published: July 2007

Electron‐beam testing (EBT) is currently used at two stages in the development and manufacture of integrated circuits (ICs), namely for chip verification and failure analysis. These are explained with the aid of two examples. EBT is, however, only one of many diagnostic tools. In order to classify it more usefully, a scenario is described that takes account of trends in chip development and packaging, and the linking of EBT with CAD (computer‐aided design) and CAT (computer‐aided testing). The conclusion is reached that EBT will remain an indispensable diagnostic tool. In future, it will probably be used under increasingly more difficult conditions, however, due primarily to the greater complexity of specimen preparation and test stimuli generation.
Photon emission as a tool for esd failure localization and as a technique for studying ESD phenomena
Authors: Hannemann Marcel , Amerasekera Ajith
Published: July 2007

Photon emission microscopy gives the opportunity for non‐destructive localization of failure sites on VLSI chips. Failures that can be detected using photon emission microscopy are gate‐oxide breakdown, latch‐up, junction breakdown and intermetal oxide failures. This makes it a valuable evaluation technique of failures in ESD protection circuits.

Real‐time photon emission observations of reverse‐biased transistors showed that this technique is also an important tool in the evaluation and development of ESD protection circuits.
Hot carrier degradation in MOSFETs in the temperature range of 77–300 K
Authors: Maes H. E. , Heremans P. , Bellens R. , Groeseneken G.
Published: July 2007

In this paper the DC hot carrier degradation ofn‐channel andp‐channel MOSFETs is treated in the temperature range of 77–300 K. A thorough analysis of the degradation mechanisms is made possible by an extensive use of the charge pumping technique for the determination of the interface properties of the MOS devices prior to and after degradation in this temperature range, in addition to the more conventional techniques based on shifts and/or distortions of the current–voltage characteristics. The physical processes responsible for the transistor degradation are identified in each voltage regime for the two types of transistor.
The long‐term stability ofn‐AlGaAs/InGaAs/GaAs pseudomorphic HEMTs
Authors: Saunders N. L. , Rezazadeh A. A. , Morgan D. V. , Thomas H. , Hipwood L. G.
Published: July 2007

Ageing tests on PHEMTs, ohmic contacts and heterojunction test samples have been performed. During moderate temperature life tests (< 170°C) the degradation is related to the ohmic and gate contacts. At higher test temperatures (> 210°C) a third degradation mechanism is evident, possibly attributed to field enhanced instabilities in the AlGaAs/InGaAs heterojunction or to Si diffusion, at the drain edge of the gate. A worst case activation energy of 1.49 eV has been deduced.
Degradation mechanisms in 2 W MESFETs
Authors: Canali C. , Magistrali F. , Paccagnella A. , Sangalli M. , Tedesco C. , Zanoni E.
Published: July 2007

Biased life tests and thermal storage at different temperatures have been performed on 2 W GaAs MESFETs from two different suppliers. Failure modes and mechanisms are correlated to device technology and are thermally activated. In samples with Au/Pd/Ti gate metallization we observed a decrease of Idss current and an increase of the gate diode reverse current. The former is related to the gate‐semiconductor interaction, whereas annealing of GaAs surface states is responsible for the latter, which can cause the device burn‐out. These degradations exhibit activation energies of 1 eV and 1.5 eV, respectively. In samples with Al gate metallization, we measured an increase of parasitic resistances possibly deriving from a degradation of the ohmic contacts.
A two‐stage sampling plan for bogey tests
Authors: Wang C. Julius , Lu Ming‐Wei
Published: July 2007

When accelerated life tests can be applied to simulate the normal product operating conditions, engineers usually terminate the test upon successfully running to a multiple of a prespecified bogey without any failure to demonstrate a required minimum reliability level. This testing philosophy is called ‘bogey test’ (or extended test) in the automotive industry and is a subset of type I censored tests in standard reliability literature. Sometimes engineers encounter the difficulty of using this reliability demonstration approach when incidents do occur during the test. The incident might be a legitimate failure or a withdrawal caused by external forces such as a broken fixture of a non‐functional power supply. This paper derives a two‐stage sampling plan for possible back‐up solution on planning and running a bogey test with possible occurrence of incidents. A Weibull distribution with a given shape parameter is assumed for the underlying life characteristic.
Use of a cmos static memory array as a technology test vehicle
Authors: Schmitt‐Landsiedel D. , Winnerl J. , Neuendorf G. , Kölzer J.
Published: July 2007

A static memory array is described for use as a test vehicle in CMOS process development. Design guidelines are given for a large operating range and good testability. Address paths are defined for efficient comparison of access time measurements and simulations. the functional yield of SRAMs is correlated with defect density results from test structures to identify the relevant yield limiting defects. It is shown that an SRAM is a suitable test vehicle for yield prediction of complex CMOS random logic circuits.
Failure analysis of multilevel metallized lsi using optical beam induced current
Authors: Mitsuhashi J. , Komori S. , Tsubouchi N.
Published: July 2007

In order to analyse failures caused in multilevel metallized LSI devices. we developed the OBIC (optical beam induced current) observation technique using an infrared laser incident upon a backside of the chip which appears from a plastic package by being lapped and polished.

We analysed the electrical rejects in the reliability stressing of surface mount plastic packages with this technique. The latch‐up phenomenon in 4Mbit dynamic RAM with retrograded‐well fabricated by a high energy (MeV) ion‐implantation was also examined. The high latch‐up immunity of the device with retrograded‐well is confirmed by this analysis.
Stability of interfaces in pseudomorphic ingaas hemts
Authors: Audren P. , Dumas J. M. , Mottet S. , Vuchener C. , Paugam J. , Favennec M. P.
Published: July 2007

Considerable progress is now reported on pseudomorphic InGaAs high mobility transistors (PM. HEMTs). However, structures which exhibit the best performances are thermodynamically metastable. The stabilities of commercially available devices have been studied. Investigations of both GaAs InGaAs and AlGaAs/InGaAs interface vicinities have been performed through deep level characterizations. Life‐testing experiments have then been carried out in order to assess the stability of the InGaAs buried strained layer and related interfaces during operation. Deep level studies together with electrical parameter measurements indicate that interfaces of InGaAs strained quantum well HEMTs do not induce particular degradations after 3000 hours into biased ageing tests.
Economical design of reliable systems—some practical situations
Authors: Aggarwal K. K.
Published: July 2007

Designing reliability into a system is one of the most important objectives of a system disigner. A system normally consists of several components, and the possibility that each component is available in the market in different categories with various specifications, reliability values and costs requires serious consideration while designing a system. Therefore, the difficulty which the system designer always comes across is how to choose an appropriate combination of components so that the achieved system reliability is maximum for the given cost.

The present paper aims at investigating an efficient approach which generates directly those combinations of components which guarantee the maximum system reliability at a specified cost. Also, if the system designer wants to increase his resources, the proposed method provides a way of selecting a configuration with higher reliability if it exists. Based on the developed algorithm an interactive package has been prepared, which also permits the user to exercise options such as minimum acceptable reliability value, maximum affordable cost, duty ratios for components which work for a period less than the mission time, and criticality values for components which are not fully critical. A complete example illustrating all these features is also discussed.
Applications of hazard rate profile to software reliability prediction. Growth modelling and allocation
Authors: Friedman Michael A.
Published: July 2007

The concept of a computer program's ‘hazard rate profile’ is introduced. A software fault's hazard rate is the amount the fault contributes to the overall program failure rate. The hazard rate profile describes the relationship between the program's failure rate and fault content by summarizing the relative proportion of software fault hazard rates that fall into different hazard rate classes. The usefulness of the hazard rate profile concept is shown by applying it to the tasks of software reliability prediction, growth modelling and allocation.
Assuring quality of the human–computer interface
Authors: Kohoutek Henry J.
Published: July 2007

The issue of human–computer interface quality has been brought currently into focus due to (a) a change in the character of users who dominate the computer market, (b) the availability of expertise in design for usability and its assurance, and (c) the finally recognized business benefits for vendors of user friendly equipment. Because the underlying human factors expertise belongs to the category of enabling generic quality assurance technologies, the quality management and engineering communities must master this new issue, and related knowledge and methods. The objective of this review article is to aid the quality professionals to respond successfully to this challenge by presenting the fundamentals of human factors engineering, its role in the design for usability process, and the associated methods of assuring quality of the human–computer interface.
Using the economic point of truncation process for new product introduction
Authors: Zurn James T.
Published: July 2007

Proper validation and release of a newly developed product into the market‐place at the minimum supplier cost requires a robust deterministic system. It must characterize cost elements and recommend optimum introduction points in support of total quality management. The economic point of truncation (EPOT) process fulfils the requirements for this system. It integrates pre‐ and post‐release problem resolution costs with the rates of problem discovery, latent problems and product shipping into a product life cycle model. The model simulates the cost accrual for problem resolution during the validation, release and product shipment periods. Model execution results in a characterized life cycle indicating the optimum duration of product validation that minimizes total problem resolution costs.
System reliability analysis using factorization techniques
Authors: Kendall M. Stephen , Koslov Judith W. , Wood Robert B.
Published: July 2007

Fault tolerant systems provide challenges to the reliability prediction process. This paper introduces a prediction method based on the identification of factors affecting system reliability, and on categorization of system performance classes. Computational methods are presented for analysis of factor levels and system reliability performance. Examples and application results are provided.
Fault impact and fault tolerance in multiprocessor interconnection networks
Authors: Menezes Bernard , Johnson Allen M. , Malek Miroslaw , Jenevein Roy , Yau Kitty H.
Published: July 2007

Growing complexity of parallel machines coupled with increasing chip densities escalates the need for fault tolerance and recovery in these systems. In pursuit of the goal of fault‐tolerant multiprocessors, many techniques have been proposed. Since methods for designing fault‐tolerant processors and memories are relatively mature, the techniques considered in this paper focus on the interconnection network (ICN) linking the processors. The impact of faults on non‐fault‐tolerant ICNs is contrasted with that in fault‐tolerant networks. Fault tolerance in ICNs is addressed at two levels, inter‐node or switch level and system level. Inter‐node or switch level pertains to data and control integrity and system level deals with maintaining network connectivity and adequate performance levels in the presence of faults. Fault‐tolerant schemes at the switching element level warrant some form of concurrent error detection such as the use of codes usually combined with a full handshake protocol. Space–time trade‐offs involved in the use of various codes and protocols are investigated. At the system level, several augmented multi‐stage switching ICNs, tree and ring networks are studied. The combined provision for fault tolerance together with improved performance in the non‐fault condition is emphasized. Finally, strategies for network reconfiguration and rerouting after system failure are presented.
Reliability and robustness of thin film composite resistor networks
Authors: Sachaf A. , Klein I. E.
Published: July 2007

Reliability of composite NiCr–tantalum nitride resistors was tested according to MIL STD 883 procedures. It was shown analytically and experimentally that these resistors are robust and stable, and they can thus be recommended for use in precise and reliable integrated circuits.
Formal methods: The next generation of system design tools
Authors: Schofield Mike
Published: July 2007

Because of the growing demand for increasingly complex computer‐based systems there is now an urgent need to provide tools to assist during the design of such systems.

Formal specifications and formal methods provide such assistance but their widespread adoption has been hindered by the so‐called ‘math fear’ and the perception that the tools are too difficult, too time consuming and too costly to use in a commercial environment.

The aim of this article is to dispel the mystery surrounding the topic and to explain what formal methods are, how and why they are used, the benefits that accrue and why the technology should be accepted on a broader front.

The application of formal methods to the design of computer‐based systems will be discussed without resorting to jargon or mathematics. The discussion will concentrate more on the software content of systems but the arguments apply equally well to hardware.

Some of the available tools will also be introduced.
Spc of a near zero‐defect process subject to random shocks
Authors: Xie M. , Goh T. N.
Published: July 2007

In this paper we study the problem of monitoring and control of a type of process in which long series with no non‐conformities are observed together with occasional samples containing a large number of non‐conformities. We call this a near zero‐defect process subject to random shocks. Such processes occur often in practice, and a model is proposed for the identification of real non‐random variations of process characteristics. Based on the statistical analysis carried out for this model, a procedure for decision‐making in the control of this type of process is suggested, and analysis of some actual cases presented.
Maximum likelihood estimation from record‐breaking data for the weibull distribution
Authors: Hoinkes Lori A. , Padgett W. J.
Published: July 2007

In destructive stress testing, industrial quality control, or other situations, data may consist only of record setting values, such as successive values that are smaller than all previous ones observed. Here, for a two‐parameter Weibull distribution, the performance of the maximum likelihood estimators (MLEs) from record‐breaking data is studied by computer simulations. Comparison of the biases and mean squared errors of these estimators with those of the MLEs for complete samples from the Weibull distribution is discussed and some examples are presented.
Integration of efforts for the reliability of microelectronic devices
Authors: Gerling W.
Published: July 2007

The expected levels of product reliability will no longer be measurable at product qualification. The control of reliability must be completely changed to proactive measures. This requires close customer‐vendor relationships in early phases of specification and qualification, basic solutions by robust design and tough manufacturing engineering with zero defect targets. This changing situation is illustrated by some examples in the very diverse field of contributions to reliability. Improved cooperation is required for more efficient reliability progress.
Testability enhancement of a basic set of CMOS cells
Authors: Rullán M. , Oliver J. , Ferrer C. , Blom F. C.
Published: July 2007

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design.
Application of defect simulation as a tool for more efficient failure analysis
Authors: Griep S. , Khare B. , Lemme R. , Papenberg U. , Schmitt‐Landsiedel D. , Maly W. , Walker D. M. H. , Winnerl J. , Zettler T.
Published: July 2007

In modern VLSI processes, increasing process complexity has resulted in an exponential rise in the costs of thorough failure analysis. In this paper, we present a defect simulation‐based failure analysis methodology, which can be used to significantly reduce both costs and turn‐around time for failure analyses. The methodology is based on the ability to generate a defect dictionary, which can relate defect characteristics to some easily measurable symptoms of defect occurrence.
A practical example for reduction of the call rate level
Authors: Rimmen Peter
Published: July 2007

This is a description of a practical way to develop a new product with a built‐in robustness for many parameters. This has reduced the field call rate. The field call rate is measured using the superimposed renewal process M(t). This work has resulted in developing ‘stronger solder joints’ and it has also reduced the amount of resolder joints in PCB assembly.
Quantified risk assessment in railway system design and operation
Authors: Haile J. P.
Published: July 2007

Over the last few years quantified risk assessment (QRA), a technique developed in the process industries, has moved into the railway and mass transport arenas. Many quantified risk assessments are now appearing covering varying aspects of railway operation and design.

This paper highlights the strengths and weaknesses of the QRA technique, with specific reference to its use in railway system design and operation. Suggestions are made as to how best to manage and present a QRA, and these are illustrated in a section explaining the systematic approach of Cross Rail, a joint London Underground/British Rail/Railtrack £2 billion railway for London.

Throughout this paper it is stressed that good QRA comes from management of the process and not of the ‘final figure’. The paper concludes with a listing of recommendations that are considered to be the minimum needed for the future progress of railway QRAs. Consequently the paper will be of special interest to those railway organizations undertaking or managing a QRA for the first time. Special reference is made to the use of QRAs in the presentation of Railway Safety Cases and project design.
A fast algorithm for template pattern matching based on probability of occurrence of subpatterns
Authors: Shima Yoshihiro , Kashioka Seiji , Ejiri Masakazu
Published: July 2007

The template matching method is utilized in the document information processing and industrial visio n. It is a method to extract from the given image patterns similar to the specified patter n. With the increase of the size of the image and the kinds of template patterns, however, the high‐speed realization of the method becomes a proble m. In this paper, a new high‐speed pattern matching method is described for the binary image, based on the sequential similarity detection algorithm (SSDA), which is known as a means of high‐speed realizatio n. In the first part, the expected computation time by SSDA is calculated using the occurrence probability of the subpattern in the templat e. Then a method is proposed in which the order of pixel comparison is determined based on the occurrence probability of the blockwise subpatterns in the given image .A detailed discussion is made for the case where no matching error is permitted in the metho d. The method is applied to the case of two‐dimensional IC chip pattern, indicating the effectiveness of the method in the high ‐speed realization of the pattern matching.
Spline approximation of line images by modified dynamic programming
Authors: Ishimura Nobumichi , Hashimoto Takeshi , Tsujimoto Shuichi , Arimoto Suguru
Published: July 2007

The image data generally requires a large memory area and it is often necessary to improve the processing efficiency by compressing the data. This paper discusses a method of data compression in which two kinds of cubic spline functions of classes C1 and C0 are used to approximate the line image and the image data are replaced by the parameter set of the spline function. A method is proposed to optimize the knot positions of the spline function by dynamic programming. The effect of the different continuity conditions of the spline functions on the data compression is discussed. In general, dynamic programming requires a large amount of computation. A modified dynamic programming is also proposed which can decrease the computation time without substantially affecting the accuracy of approximation. Such methods are robust, being independent of the image features and are expected to be generally applicable to various kinds of line images.
Iterative Gradient Method for Movement Estimation
Authors: Wada Masahiro , Yamaguchi Hirohisa
Published: July 2007

In the processing and coding of moving images, the movement of the image is one of the most important parameters. In the realtime processing, it is desirable that the movement be estimated with less computation and simple hardware. From such a viewpoint, this paper proposes a movement estimation method with less computation and satisfactory estimation accuracy. In the proposed method, the gradient method is applied iteratively to the pixel blocks, improving the accuracy of estimation while retaining the merit of the gradient method. This paper describes first the principle of the gradient method, indicating the deterioration of the accuracy. The trend is demonstrated by experiment. Then the principle of the proposed method is described, and it is shown by theoretical discussion and simulation experiment that the accuracy of estimation can be improved. Finally, from the standpoint of motion‐compensation coding, a comparison is made with other methods based on the interframe error entropy. As a result, it is shown that estimated movement among adjacent blocks can be utilized in the proposed method, and a motion‐compensation performance can be obtained which is as stable as in the matching method, which requires a larger amount of computation.
Some techniques for document and image preparation
Authors: Suenaga Yasuhito
Published: July 2007

As a preliminary to the coming era of new media, editing and preparation techniques for document and image are becoming more important. This paper discusses various kinds of technqiues needed in the realization of more powerful and convenient document‐image systems. The topics discussed in this paper are: (i) facsimile‐based document and image editing using auxiliary mark recognition; and (ii) construction of videotex image by electronic pen/eraser. As an example, of (i), the construction and operation of FLEX (a Facsimile‐based manuscript Layout and Editing system by auxiliary mark recognition) are described. This system receives through facsimile the handwritten or printed text and graphic manuscript as the source information, together with the auxiliary marks for correction, and recognizing marks perform the automatic editine. Some experimental results of document and image editing are shown. As an example of (ii), an experimental system for a picture drawing and coloring system using electronic pen/eraser is presented, together with an experimental result of color image preparation. A method for editing and preparation of videotex image is outlined. Finally, a discussion is made on the characteristics required in the future document‐image editing and preparation system.
Process assignment on multiprocessor with communication contentions
Authors: Shimojo Shinji , Miyahara Hideo , Takashima Kensuke
Published: July 2007

This paper discusses the process assignment problem in the multiprocessor system with communication contentions due to interprocess communications (IPCs). As a model for the multiprocessor system, a system is considered in which the processing elements (PEs) with local memory (LM) are connected through a communication network (CN). As a model for the distributed‐type algorithm realized on such a system, a scheme is considered in which the process assigned on a PE is executed with IPC with other processes. Based on these models, a problem is formulated where a set of processes is assigned on the multiprocessor system so that the overall processing time is minimized. Especially, for the problem where a single common bus is used as the CN and the processes are assumed as uniform, the optimum number of PEs is determined by introducing an approximation to the waiting time for the CN. The strict solution obtained by exhaustive search is compared with the approximate solution, and the validity of the approximate solution is evaluated.
Embedding area of d‐way shuffle graph on a VLSI model
Authors: Wada Koichi , Hagihara Ken'Ichi , Nobuki  , Tokura
Published: July 2007

An important problem in the design of a VLSI chip is that of determining how much area is taken to embed a graph G into a planar grid when the VLSI chip is modeled using a graph called a planar grid and a circuit is expressed by a graph G representing wiring connections between elements. Discussed for various graphs will be the upper and lower bounds on the planar grid area into which a graph is embedded. In this paper we consider the problem of embedding a d‐way shuffle graph into a planar grid, using a model which has been extended so that a graph with degree five or more can be embedded. d‐way shuffle graphs are also of theoretical interest since data exchange can be done in high speed like a shuffle exchange graph and a CCC. By using a relationship between the number of crossings of a graph and its area, we show that for the infinite number of d and k an area proportional to dk+1/k)2 is required to embed a dk‐vertex, d‐way shuffle graph. Using this result, the previous lower bound of the area can be improved. Further, for an embedding of a graph G we present an embedding method of G which uses a graph with a known embedding area. By using this result we show that if d is a power of 2, a dk‐vertex, d‐way shuffle graph can be embedded in an area proportional to (dk+1/2)2.
A geographic information overlay method for regional analysis
Authors: Tsurutani Tateyuki , Kasahara Yutaka , Miyashita Toshiaki
Published: July 2007

A geographic information overlay method is defined whereby the intersection of figures caused by overlaid maps is detected and socio‐economic information about the detected region is restructured. By this method map information compiled with the different social attributes can be compared and their consistency can be checked for regional analysis. This method can be used as an alternative simulation model in generating indices for certain problems. For given map data geometric figure intersections are treated by intersection calculus theory in computational geometry. For socio‐economic information, integration and distribution of numerical data and representation of attributes are implemented from the practical point of view. As a case study, this method is applied to the overlay of geological and administrative maps in earthquake disaster prevention. It is found that the method is effective in achieving consistency between maps with different attributes and can be an alternative method to calculation of risk factors by complex algorithms.
ALU control code assignment
Authors: Takagi Shigeru
Published: July 2007

The number of gates in the ALU decoder depends on the control code assignment in the specification of the functions. This paper presents an assignment method which achieves the quasi‐minimum number of gates in the decoder. The ALU functions are specified by the function identifiers and the relations between the data input and output terminals. The logical structure model for ALU is constructed and together with the function specifications, leads to the logical expression for the decoder. The obtained logical expression is the logical disjunction of the function identifiers. The function identifiers are replaced by the control codes, and the code assignment is made so that the number of product terms is the quasi‐minimum when the simplification is made. The assignment time for the control codes of ALU with 32 function is approximately 160 s in the 2 MIPS computer.
Automatic position detection method for mounting ic parts on high‐density printed circuit boards
Authors: Shima Yoshihiro , Kashioka Seiji , Sakou Hiroshi , Suzuki Kunio
Published: July 2007

In the automatic mounting system, which mounts electronic parts on a printed board, a problem is that the object printed circuit board is becoming of higher density and the parts have a fine lead structure. It is necessary that the positions of the part and the printed board should be detected with a high accuracy. It also became important to cope with the diversified parts with different shapes. This paper proposes a new practical method of automatic position detection to solve those problems. The proposed system is composed of the position detection process for the part and the position detection process for the printed board. In the process for position detection of parts, the positions of more than one lead are detected by the pattern matching, determining the similarity between partial images, and the position and the inclination of the part are calculated based on the result of matching. The viewing field is set so that only several leads are observed by the TV camera, and the object lens is moved to X and J directions so that the viewing field can be shifted to any desired position. In the position detection of the printed board, the positions of the two marks printed on the board are detected, and the position and the inclination of the printed board are calculated based on the mark positions. To evaluate the effectiveness of the proposed method, the position detection experiment was performed for the actual part and printed board, indicating that the position can be detected with a high accuracy.
3‐D measurement of polyhedron position and orientation using multiple binary images
Authors: Hisano Atushi , Yamaguti Yoshinori , Masaki Toshimiti , Saka Kazuhiko
Published: July 2007

This paper describes the measurement system for the three‐dimensional position and orientation of a polyhedron by binary image processing. In the proposed system, to simplify the binary image processing, the shadow is eliminated by a coaxial illumination and the contrast of the image is enhanced by placing a retroreflector in the background. The three‐dimensional position and the orientation of the polyhedron is calculated from the three‐dimensional coordinates of the feature points obtained by the triangulation principle. The trinocular vision is employed to cope with the correspondence problem. The labelling of the feature points is executed with high speed by the maximal clique method. The accuracy of the position measurement in the proposed system is 1.0 percent of the visual field, indicating the usefulness of the method.
Decoding method for shortened fire codes and its application to VLSI processor
Authors: Iwasaki Kazuhiko , Funabashi Tsuneo , Ueno Tatsuaki
Published: July 2007

The disc system is one of the areas of applications for the error‐correcting code. For this purpose, a Fire code with the generating polynomial G(x) = (xc + 1) × p(x) is frequently used. This paper considers the shortened Fire code, where the length of the code can be reduced according to the length of the record used. A decoding method suitable for VLSI is proposed. It is noted that the content of the feedback shift register with p(x) as the divider returns to the original pattern when it is shifted by the period e of p(x), and the speed is improved by ignoring the integer multiple shifts of e. This decoding method requires less hardware (i. e., shift registers and counters), and has the merits of easiness in design and expandability, according to the record length. The principle is expanded to the general cyclic code. The proposed decoding method is implemented on the hard disc controller (peripheral LSI for HDC 16 bit microcomputers). A 32‐bit Fire code is used. For a typical record length of 512 bits in the disc system, the speed was comparable to that of the high‐speed decoding. The error‐correcting part is composed of 6700 Tr, which is 5.2% of the whole system (129 kTr). This figure demonstrates the practical usefulness of the proposed method in VLSI design.
A method to reconstruct shape and position of three‐dimensional objects using photometric stereo system
Authors: Hong Hai , Kawashima Toshio , Aoki Yoshinao
Published: July 2007

This paper proposes a reconstruction method for the shape of a three‐dimensional object. The proposed method is the intensity‐difference stereo method utilizing several gray‐scale images obtained by a fixed camera and a light source with varying position. In the earlier method, the surface shape of the object is restored based on the gradient of the object surface determined by the intensity‐difference stereo method, where other methods must be combined in order to determine the three‐dimensional position of the object. In the proposed method, the shadow information is combined with the intensity‐difference stereo method, and an algorithm is proposed which can determine not only the three‐dimensional shape, but also the absolute coordinate in the three‐dimensional space with the plane carrying the object as the reference. As a result of experiment, it was verified that the proposed method can be applied to the case where more than one object is involved.
Transformation of orthogonal coordinates into polar coordinates using DDA‐computation of the angle of rotation of an object
Authors: Ueno Masayuki , Hama Hiromitsu , Yamashita Kazumi
Published: July 2007

This paper describes the algorithm which directly processes the gray‐level image to determine the rotational angle. A complex computation is required to transform the orthogonal coordinates into the polar coordinates. In this paper, a transformation algorithm is proposed using DDA, which is a high‐speed algorithm to generate the digital segment. To evaluate the usefulness of the proposed algorithm, a computer experiment was performed using several input images from a TV camera. The mean error of the rotational angle was ±0.8 deg, and the maximum error was ±3.9 deg, which is quite satisfactory.
Verification system for freedom from deadlock of communicating sequential processes
Authors: Murakami Masaki , Inagaki Yasuyoshi
Published: July 2007

The communicating sequential processes (CSP) proposed by Hoare are a model for parallel computation in which the processes do not share a variable and perform the interprocess information exchange and synchronization by the communication instruction function. This paper first extends the verification system for the partial validity of CSP previously proposed by the authors and an axiomatic system is presented by implementing part of the inference rules which can deal with the deadlock‐free property of CSP. The soundness of the system is shown. The system previously proposed by the authors can provide the inferences in a concurrent way independently of the processes, without following the sequential procedure of proving a property for a process and proving a certain relation between processes. The system proposed in this paper employs a similar procedure and verification is made in parallel for the partial validity and deadlock‐free property of CSP.
Computer classification of rosette‐forming cells from microscope images
Authors: Ohta Hiroki , Ozawa Shinji , Miyauchi Minami , Takata Hajime , Sonoda Akira , Iri Hisami
Published: July 2007

This paper presents a method of rosette‐forming cell classification by image processing. This method is useful in the field of clinical immunology in dividing lymphocytes into some subpopulations and quantifying each component. The “Rosette Formation Test” is one of the most popular methods of classifying lymphocytes which consist of the different functional subsets. However, the rosette‐nonrosette judgment has been done by a human expert using a microscope. Considerable manpower is needed to judge rosette/non‐rosette cells. To solve this problem, we present a computer classification system of rosette‐forming cells in the microscopic image. The system constructs an accumulative gray‐level histogram for each cell, extracts features from histograms, and then classifies cells with the discriminant function.

To confirm the effectiveness, we examined the classification system for several images. As a result with learning data (991 cells), the accuracy of classification is 84.5 percent, and the correct rate of resetted and nonrosetted cells is 86.6 percent. With unknown data (509 cells), the accuracy of classification is 84.1 percent, and the correct rate of resetted and nonrosetted cells is 86.2 percent.
Extraction of Nth‐order features of line patterns considering redundant information
Authors: Nishiyama Norifusa , Inoue Kazuo
Published: July 2007

The extraction of geometric features is a basic and significant process for pattern recognition. This paper proposes a method of extracting geometric feature by referring redundant information around the feature point.

For written or oral information, even if some information is unable to be understood, we can infer meaning by knowing redundant information. Using the same principle as mentioned in the opening paragraph, this paper introduces a method to extract the geometric feature by detecting redundant information around the feature point.

Finally, to verify the usefulness and effectiveness of this method, computer simulation experiment is performed on test patterns and handwritten numerals.
Descriptive power of synchronized shuffle expressions
Authors: Uoi Hirotaka , Araki Toshiro , Tokura Nobuki
Published: July 2007

As a model to describe the concurrent system with a synchronization mechanism, Holenderski has proposed the synchronized shuffle expression (SSE). SSE is a shuffle expression obtained by adding a synchronized shuffle operator with its closure and projection operator. This paper considers various subclasses of SSE. It is shown that the class of languages represented by the subclass excluding the projection operator is the same as the class of recursively enumerable languages. The hierarchical relations among the subclasses are described.
Three‐dimensional motion analysis of scene containing multiple moving objects from image sequence and depth
Authors: Yamamoto Masanobu
Published: July 2007

Optical flow analysis is a powerful means to extract an object from the dynamic image. Not only can it extract an object, but it can also recover the three‐dimensional structure. However, in practice, there are many cases where the optical flow is difficult to obtain or the motion of the object does not permit a unique interpretation. Based on the gradient method, this paper proposes a method of three‐dimensional motion analysis for multiple moving objects which may include an object for which a unique interpretation of the motion is difficult. By the gradient method, the three‐dimensional motion parameters of a rigid object can be estimated without using the optical flow as a least‐square‐error solution for the system of linear equations, if the three‐dimensional structure of the object is already given. Based on the residual square‐sum error in the estimation, the image plane is segmented if it contains regions of different motions. If the motions are recognized as being similar, the regions are merged. Thus, the object is extracted by iterating the segmentation and merge on the image plane. The uniqueness of the motion is evaluated by the condition number for the coefficient matrix of the system equations. If the motion of the extracted object can be interpreted uniquely, the displacement vector can be determined accurately by iterating the estimation of the object motion.
Finding of objects moving against a static environment by a moving observer
Authors: Yagi Yasushi , Asada Minoru , Tsuji Saburo
Published: July 2007

This paper describes a method by which a robot with vision can detect moving objects or obstacles in an environment, by analyzing the consecutive images obtained during its movement in an artificial environment such as inside of a building or a plant. In this paper, it is assumed that the environment is a corridor in a building, which satisfies the following two conditions.

(1) The wall of the corridor is planar and is vertical to the floor, and (2) the floor is flat. Under these two assumptions, the optical flow pattern can be estimated for the background (corridor). Assuming that the moving object is performing a parallel translation, the moving object can be extracted from the background by comparing the relative magnitudes of their optical flows, providing the necessary informations to the moving robot. The proposed method has a versatility since no geometrical model is employed which is composed of numerical data. The method utilizes only those properties which are valid in most cases of the artificial environment. An experimental example, the result of analysis for a corridor in a building is shown.
Pattern‐separating function of two‐layered random nerve‐net receiving a fixed number of inputs
Authors: Torioka Toyoshi
Published: July 2007

The pattern‐separating function of the two‐layered random nerve‐net, which has forward inhibitory connections, depends on the input structure of the second layer. Among the nerve‐nets with various input structures, the nerve‐net with the fixed number of input connections exhibits a very interesting property that under a certain condition, the input patterns are separated uniformly, independently of the overlapping rate of the patterns. This paper derives the theoretical expression for this property as a polynomial of the overlapping rate among the input patterns. Based on the theoretical expression, the condition is derived for the input patterns to be separated uniformly, independently of the overlapping rate among patterns. Then an example is considered and the condition is examined in detail. The effects of the input pattern and the firing rate of the second layer on the separation are discussed. As a result, it is shown that the pattern separation can be improved by controlling the firing rate of the second layer to a small value, and the patterns with larger firing rates are better separated.
Avoiding peaking phenomenon of the quadratic discriminant function
Authors: Kimura Fumitaka , Takashina Kenji , Tsuruoka Shinji , Miyake Yasuji
Published: July 2007

The performance of the discriminant function is degraded if the parameters used contain estimation errors. A peaking phenomenon is known in which the classification rate reaches the maximum for a certain feature dimension, but decreases with the further increase of the feature dimension. This paper reports the result of experimental examination of the relations of the classification rates of the Euclid distance, the quadratic discriminant function [1] to the feature dimension. It is shown that the modified quadratic discriminant function corresponds to the discriminant function where the maximum‐likelihood estimation for the covariance matrix of the quadratic discriminant function is replaced by a kind of pseudo‐Bayes estimation, and suppresses the peaking phenomenon.