(Invited) Microfluidic Electroless Interconnection (MELI) Process for Low-Temperature, Pressureless Chip Stacking Applications
Authors: Kao C Robert , Hung H. T. , Chen Y. H. 
Published: February 2020

Increasing demands for high-performance miniaturized electronic devices have driven the semiconductor industry toward finer pitch and higher interconnect density. Copper pillar has been widely adopted and is rapid becoming the mainstream bumping technology for high-density interconnections, such as 2.5D and 3D IC packaging. Thermo-compression bonding has been widely used for high-density copper pillar bumps because of its highly accuracy alignment and placement. However, the high heat and high force applied to the components during the bonding process often induce high thermal-mechanical stress that causes severe damage to the devices and low-k dielectric layers. Because the mechanical properties of porous, low-k materials decreases with lower dielectric constants, this issue will become more severe in the future when lower dielectric constant materials are employed. Therefore, it is imperative to develop a low-temperature, low-pressure bonding process.

To address this issue, a novel Cu-to-Cu bonding process called microfluidic electroless interconnection has been developed. This novel process forms electroless metal interconnections as a replacement for solders, which eliminates all the reliability concerns involved with soldering. Specifically, the process is able to bond copper pillars at a low temperature without applied any pressure. The operating temperature of the process is around 80 °C, which is considerably lower than most bonding processes. Also, there is no need to apply any bonding pressure throughout the bonding process due to the proposed bonding scheme structure. In this way, the thermo-mechanical stress can be largely reduced to maintain the structural stability of packaging. Furthermore, the most exciting aspect of this new approach is the integration of microfluidic technology with the electroless plating process, which allows to precise control the flow of fluids in and out the stacked chip to achieve better bonding performance. The flow rate can quantitatively determined and the fluid flow can be adjusted for either batch or continuous-flow operations.

The main objective of this work was to investigate the feasibility of the microfluidic electroless interconnection process in joining copper pillars as a promising route for a low-temperature, pressureless bonding process. First, the overall plating uniformity across the entire die surface at different stand-off heights of the stacked chips was investigated. Preliminary results demonstrated that, by selecting a proper flow rate, a high level of plating uniformity across the die was obtained regardless of the standoff heights. In addition to the electrolessly bonded joints, when the bonding interface was examined by scanning electron microscopy (SEM) and focus ion beam (FIB), it was confirmed that no voids or seams appeared on the bonding interface between the pillars, indicating that the two electroless Ni layers that grew on the opposite sides had merged completely into a single structure. The growth and bonding mechanism of the electroless interconnection process was investigated and characterized fully. The bonding interface and phosphorus distribution in the electroless Ni bonds were examined by an electron probe micro-analyzer (EPMA) to ascertain the effect of batch and continuous flow processing. Moreover, the results of direct shear test shows that the bond strength of the electroless Ni between the copper pillars was greater than the adhesion strength of the Cr layer. Further, it was found that the process has the ability to compensate not only for non-uniform copper surfaces, but also for the misalignment and height mismatch of copper pillars, which provides a competitive edge over other bonding methods. This innovative low-temperature, pressureless electroless bonding approach shows considerable promise for applications that require low stress and low thermal budget process.