bluuebunny/crossref_metadata_2025 huggingface dataset:
A Study on Fluorine-Induced Corrosion on Microchip Aluminum Bondpads
Authors: Hua Y. N. , Redkar S. , Dickinson Ron , Peh S. L. , Shirley
Published: December 2020

In the authors' previous paper, we studied the defects from Fluorine-Induced Corrosion on microchip Al bondpads using SEM, EDX, TEM, AES, IC, XPS and TOF-SIMS techniques. An unknown F-Al compound was found and identified as [AlF6]3-. In this paper, we will further study the chemical mechanisms of Fluorine-Induced Corrosion on microchip Al bondpads and propose a theoretical electrochemical model to reveal the secrets of Fluorine-Induced Corrosion on Al bondpads. To support this new theoretical model, we will provide substantiating data from TOFSIMS analysis and other failure analysis techniques. According to the theoretical model of Fluorine-induced Corrosion proposed, fluorine contamination on Al bondpads will cause two types of corrosions. First, fluorine reacts with Al and forms a complex compound [AlF6]3- on the affected area, which we will refer to as Fluorine Corrosion. Once the compound of [AlF6]3- forms on Al bondpads, it will form an Anode and cause further electrochemical reactions from O2, N2 and H2O (moisture) at the Cathode. The new products of further electrochemical reactions will be [OH]- and [NH4]+ ions. The new product of [OH]- ions will react with Al and cause further Al corrosion on bondpads and form corrosive product consisting of Al(OH)3, which we will refer to as [OH]- Corrosion. The new product of [NH4]+ ions will combine with [AlF6]3- and form a corrosive complex compound (NH4)3(AlF6). This proposed corrosion mechanism results in non-stick bondpad problem.
Advanced Process Defect Detection by Using Dynamic Bias Condition and MCT Camera
Authors: Wu Ching-Wei , Lee Jeng-Han
Published: December 2020

In this paper, a failure analysis case, which uses a dynamic operation technique and MgCdTe (MCT) camera to isolate single scan-chain failed cell is demonstrated. Improved results obtained using the MgCdTe (MCT) camera is compared with traditional Si CCD camera. Scan-chain cell schematic and failure mechanism is also presented to explain why static bias conditions are insufficient to detect this failure.
ESD Failure Signature Differences in the Devices Core Logic and Protection Structures - A Case Study
Authors: Henry Leo G.
Published: December 2020

For certain programmable logic type devices, the electrical, morphological and failure location differences in the ESD signatures between ICC failures and I/O leakage failures have been identified. Based on these electrical, morphological and physical failure signature locations, this case study confirms that distinctions can be made between the signatures associated with the likely stress modes for pin combinations like I/O-to-Vss, I/O-to-Vcc, I/O-to-I/O, Vss-to-Vcc and Vcc-to-Vss. This separation also facilitated the correct identification of core failures which are mostly due to the supply-to-supply pin combination stress, but in some cases are due to the pin-to-supply tests.
Photoemission and OBIRCH Analysis with Solid Immersion Lens (SIL)
Authors: Arata Ikuo , Sakamoto Shigeru , Yokoyama Yoshiyuki , Terada Hirotoshi
Published: December 2020

SIL(Solid Immersion Lens) is well investigated for optical pickup application because of its capability of high resolution. We applied this technique to microscopy, especially for precise observation of semiconductors. And also we applied it to fault isolation techniques like emission microscopy , OBIRCH(Optical Beam Induced Resistance Change) and TIVA,SEI. We found significant enhancement of resolution and sensitvity by using SIL. Applying this technique to emission microscopy, we should be aware of optical absorption charactristics of SIL lens materials. We investigated proper SIL lens materials for emission microscopy and laser scanning applications, and checked performance of Si(Silicon)-SIL and GaP(Gallium phosphide)-SIL. We also compared combinations of some kinds of SILs and detectors like C-CCD(cooled CCD) camera, MCT(HgCdTe) camera and position sensitive detector with InGaAs photo cathode II(image intensifier).
Laser Stimulation Applied to Dynamic IC Diagnostics
Authors: Beaudoin Félix , Desplats Romain , Perdu Philippe , Firiti Abdellatif , Haller Gerald , Dufayard Lionel , Vedagarbha Praveen , Lang Trung , Lewis Dean
Published: December 2020

Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.
Speed Path Analysis: A Connection Between Speed Degradation, Silicon Dislocations, and Light Induced Voltage Alteration
Authors: Davis D.
Published: December 2020

The failure analyst is often times challenged with the analysis of devices that fail due to speed degradation. These are units that pass the entire standard test program as long as the speed at which the device is tested is kept below a certain level. Many times, these units are binned and sold to customers at reduced prices. The unresolved rate for these types of failures is often sporadic and at times there isn’t any defect that is physically observable or detectable with global EFA (electrical failure analysis) techniques. These devices are usually from an advanced process where a shift in performance such as current, voltage, and speed (frequency) is common.
Quantitative Interpretation of Scanning Capacitance Microscope Images as Two-Dimensional Dopant Profiles
Authors: Kopanski J. J. , Marchiando J. F.
Published: December 2020

Scanning capacitance microscopy (SCM) is used as a qualitative analysis tool with multiple applications for failure analysis. SCM can measure the shape of dopant profiles, can ascertain if certain implants have been completed, can verify the conduction type of implanted regions, and can look for unexpected shorts or opens in doped regions of a device. To obtain quantitative two-dimensional dopant profiles from SCM images of silicon devices requires careful attention to the data acquisition conditions and processing of the measured SCM image using quantification software. This paper discusses the operational subtleties of the scanning capacitance microscope required to produce images amenable to quantitative interpretation as dopant profiles. Two approaches to quantitative dopant profile extraction are discussed: the calibration curve method and the regression method. The structure and use of the FASTC2D software for dopant profile extraction from SCM images developed at the National Institute of Standards and Technology is described. Finally, two-dimensional dopant profiles from some simple structures and a discussion of the quality of the extracted profiles are presented.
Newly Developed Scanning Laser-SQUID Microscope
Authors: Nikawa K. , Sakai S.
Published: December 2020

The scanning laser-SQUID microscope can detect electrical defects in a chip without requiring electrical contacts to the chip. Using our new system, we can get magnetic flux images of a 300mmɸ wafer in air. Experiments with 256Mbit-DRAM chips showed that IDDS testing results are correlated well with laser-SQUID images, and that the spatial resolution is 0.59 µm in an intensity image, and 0.54 µm in a phase image. We have also succeeded in localizing the open site in a whole chip area of a 90nm-node logic IC chip.
Silver-on-Silver versus Tin-on-Silver Electrical Connectors for High Current and High Vibration Applications
Authors: Singh Prabjit , Palmer Larry , Demarest James , Fischer Larry , Hutt George , Thompson Gary , Brodsky William , Lloyd James R.
Published: December 2020

Contrary to known art, we have discovered that lubricated tin-silver connectors have better electrical performance and are more reliable than lubricated silver-silver connectors under high-current and high-vibration conditions. The antifretting lubricant, that enhances the performance and reliability of the tin-silver connectors, is a grease consisting of a hydrocarbon oil in a nano-sized silica-particle base. Focused ion beam and scanning electron microscopy were used to understand the contact degradation mechanism. The superior electrical performance and reliability of the lubricated tin-silver connectors is due to a mechanism that replaces the tin plating from the contact surface with a coating of silver. The removal of the tin plating may be due to wear and the replacement by the silver coating may be due to an electrochemical displacement reaction.
Analysis of Al-over-Cu Bond Pad Hillock and Pit Hole Defects
Authors: Cavasin Daniel , Yassine Abdullah
Published: December 2020

Bond pad metal corrosion was observed during assembly process characterization of a 0.13um Cu microprocessor device. The bond pad consisted of 12kÅ of Al-0.5%Cu atop 9kÅ of Cu, separated by a thin Ta diffusion barrier. The corrosion was first noted after the wafer dicing process. Analysis of the pad surface revealed pitting-type corrosion, consistent with published reports of classic galvanic cell reactions between Al2Cu (theta phase) particles and the surrounding Al pad metal. Analysis of the bond pads on samelot wafers which had not been diced showed higher-thanexpected incidence of hillock and pit hole defects on the Al surface. Statistically designed experiments were formulated to investigate the possibility that the observed pre-saw pad metal defects act as nucleation sites for galvanic corrosion during the sawing process. Analyses of the experimental samples were conducted using optical and scanning electron microscopy, along with focused ion beam deprocessing and energy dispersive X-ray. This paper explores the relationship between the presence of these pre-existing defects and the propensity for the bond pads to corrode during the dicing process, and reviews the conditions under which pit hole defects are formed during the final stages of the Cu-metallized wafer fabrication process. Indications are that strict control of wafer fab backend processes can reduce or eliminate the incidence of such defects, resulting in elimination of bond pad corrosion in the wafer dicing process.
Die Edge Thin Film Delamination on the Bottom Die of a Stacked Chip Scale Package (SCSP)
Authors: De la Rama Lito P. , Nuarin Dante G. , Nery Marilin H.
Published: December 2020

The increasing demand for high end electronic devices incorporating multiple functions in a small form factor leads to the widespread use of Stacked Chip Scale Packaging (SCSP) in the semiconductor industry. Multiple die stacking in various combinations have been achieved. However, new failure mechanisms are being observed due to new package stress characteristics. This paper will present a unique failure mechanism observed on the bottom die of a multiple die stack package. A detailed discussion of the failure mechanism showing the interaction between the presence of a high die attach adhesive fillet and the die singulation damage initiating a thin film delamination from the die edge towards the active circuit area causing electrical failures will be presented.
Multi-Point Probing on 65nm Silicon Technology using Static IREM-based Methodology
Authors: Bockelman Daniel R. , Rahman Asifur , Wan Ifar , Chen Steven Y. C. , Ettinger Scott M.
Published: December 2020

As silicon manufacturing processes move to smaller feature sizes, new silicon fault isolation and debug challenges arise. This paper presents a methodology for silicon fault isolation/debug that allows for simultaneous probing of multiple locations on the die using static infrared emission logic state imaging. Recent tool enhancements leading to more efficient fault isolation and debug are reviewed. Cases are presented from debug of 65nm products showing how this methodology was used to achieve very low throughput times on a variety of complex new failure mechanisms.
Novel and Practical Method of Through Silicon FIB Editing of SOI Devices
Authors: Jain R.K. , Lundquist T.R. , Antolik M.E. , Thompson M.A.
Published: December 2020

Circuit edit techniques have been developed for silicon-on-insulator (SOI) devices using a coaxial photon-ion column. Novel trenching, navigation and milling methods, utilizing sub pico-Amp beam currents provide enhanced capability for editing devices with decreased geometries including buried (Box) thickness. Flat trenches 200x200µm were obtained using real time optical fringe monitoring with 125nm accuracy with 950nm λ and FIB bit map milling to adjust for parallelism to the ILD0. This bit map milling technique controlled the etch rate to maintain trench flatness by correlating the optical fringes to the bit map grayscales to vary the dwell time of the ion beam across the trench floor. Through highly accurate, CAD directed beam deflection control, beam placement accuracy in the sub 20nm regime can readily be accomplished, sub pA beam currents provide ultracontrolled etch rates and high aspect ratio (HAR) capability. Complete process definitions, techniques and results are reported. These techniques have proven successful in circuit edit below 90nm, and are expected to meet future technology circuit edit requirements down to 45nm.
Complementary Optical Techniques for Advanced IC Failure Analysis – Case Study
Authors: Liao Joy Y. , Marks Howard Lee , Deslandes Herve
Published: December 2020

We investigated and demonstrated the advantages and limitations of several optical methodologies as valuable silicon failure analysis techniques, and how they could be used in a complementary manner to assist in shortening the diagnostic time.
Dynamic Laser Delay Variation Mapping (DVM) Implementations and Applications
Authors: Sanchez Kevin , Desplats Romain , Perdu Philippe , Beaudoin Felix , Dudit Sylvain , Woods Gary , Lewis Dean
Published: December 2020

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.
Soft Defect Localization Techniques without a Synchronization Signal to the Laser Scanning Module
Authors: Mitro Diana M. , Glaeser Dawn , Howard Clifford
Published: December 2020

Soft Defect Localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across a die.[1,2,3,4] The technique has proven its usefulness for quickly locating failing nodes for functional fails that are temperature, frequency, and/or voltage dependant. The localized heating from the laser can toggle the pass/fail condition as it sweeps over failing nodes with the aforementioned sensitivity. The technique is instrumental in identifying latent defect locations on conditional fails even though they seldom produce light emissions or liquid crystal hot spots. These fails often manifest themselves after reliability stress or at the customer. The technique can also be applied to support design groups with first silicon analysis of timing race conditions and identification of signals that are speed path limiters. The main challenges associated with the technique are in synchronizing the tester with the Laser Scanning Module (LSM) and ensuring the laser can heat the device enough to overcome the pass/fail threshold temperature of the failing node.
Analysis Methods for Characterizing Drop Test Robustness of Lead-Free FBGAs
Authors: Walter J. , Fischer R. , Birzer C.
Published: December 2020

During the last few years the drop test has become more and more important for electronic handheld components. Drop test reliability for lead-free solder interconnects is an extreme challenge today. Thus, the need for improved micro structural diagnostics of new material combinations and crack detection methods has increased. The target of this paper is to summarize detection and analysis methods for solder joint cracks, material characterization [1] and preparation methods of assembled printed circuit boards (PCB) after a drop test to completely understand lead-free solder interconnect reliability in fine pitch ball grid array packages (FBGA). In particular, we will introduce the outstanding advantages of embedded cross-sections combined with ion beam polishing (IBP), dye- or rather resin-penetration, selective tin etch and micro-hardness measurements.
Analysis of a Microcircuit Failure using SQUID and MR Current Imaging
Authors: Felt Frederick S.
Published: December 2020

SQUID and MR magnetic sensors have separately been used for fault isolation of shorts and resistive opens in integrated circuits and packages. These two technologies were once considered to be mutually exclusive, although recent studies [1] rather pointed to their complementary character. This paper shows, for the first time, the use of these two sensors together to isolate a low resistance short in a Quad-NAND gate microcircuit. Electrical test confirmed low resistance shorts between three of the device pins. However, internal optical inspection found no evidence of failure. The low resistance of the shorts was deemed insufficient for liquid crystal analysis. Magnetic current imaging with a SQUID sensor confirmed current flow through the package lead frame and isolated the defect to the microcircuit. Due to package design and the resulting distance of the scan plane, the SQUID was unable to resolve the current path on the microcircuit. In parallel with the SQUID, a magnetoresistive (MR) probe was employed to fit inside the device cavity, make direct contact with the microcircuit, and map high-resolution current images. Two sites with high-current density were accurately identified by MCI in input transistors. Subsequent deprocessing revealed that the defects were located under a broad sheet of aluminum metallization which blocked optical detection, and rendered detection by thermal emission difficult.
Single Device Characterization by Nano-probing to Identify Failure Root Cause
Authors: Wu Chao-Chi , Lee Jon C. , Chuang Jung-Hsiang , Li Tsung-Te
Published: December 2020

In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in nonvisible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization in order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.
Analysis of DRAM Standby Current Failure due to Hot Electron Induced Punch-through (HEIP) of PMOS transistor
Authors: Cho M. H. , Kim Y. I. , Choi J. , Woo D. S. , Lee K. P. , Park Y. J. , Lee W. S. , Ryu B. I.
Published: December 2020

A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.
Method of Failure Site Isolation for Flash Memory Device Using FIB, Passive Voltage Contrast Techniques
Authors: Yuan Caiwen , Li Susan , Gray Andy
Published: December 2020

Current VLSI devices have very complicated circuit designs and very small feature size. As a result, fault isolation on failing devices becomes a more and more challenging task. Although backside photoemission technique is commonly used to detect the failure site covered with multiple metal layers, it has the disadvantages of more time consumption and less success rate. Without a localized failure site, it will be very difficult, sometime even impossible, to find the physical evidence for the failures. This article describes a method that has been successfully used for isolating the wordline leakage on a memory FLASH device using FIB cutting and passive voltage contrast on the leaky wordline. The concept of this article is not just limited to this application; rather it can be used for all similar types of fault isolation work for other applications.
Increasing Planarity for Failure Analysis Using Blocked Reactive Ion Etching Combined with Planar Polish
Authors: Weldy Mary Elizabeth , Serrano Leslie
Published: December 2020

Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper presents a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. The novel method combines both a blocked reactive ion etching and a standard planar polish. It has proven to be a successful delayering technique and helpful in facilitating further analysis. This method has been verified on dies, wafer pieces, and dies thinned and attached to blank silicon for support. It is useful for increasing overall planarity and particularly helpful for the extreme edge.
Automated Sample Preparation of Low-k Dielectrics for FESEM
Authors: Cerchiara R. R. , Cook H. A. , Fischione P. E. , Gronsky J. J. , Matesa J. M. , Robins A. C. , Smith D. W. , Beach E. R. , Wood C. J. , Rozeveld S.J. , Waeterloos J.
Published: December 2020

The SiLK resins, composed of aromatic hydrocarbons, are a family of highly cross-linked thermoset polymers with isotropic dielectric properties. Patterning of SiLK for high aspect ratio copper interconnects has depended on reactive ion etching with oxygen/nitrogen gas mixtures. Reactive ion etching is therefore also accomplished with reducing plasmas such as nitrogen/hydrogen. An additional plasma cleaning step can be inserted after the reactive ion etching (RIE) step, so that any residual contamination is removed prior to imaging or final sputter coating. Automated sample preparation of microelectronic materials containing high and low-k dielectrics for FESEM is accomplished in this article by combining these techniques: plasma cleaning, ion beam etching, and reactive ion etching. A single RIE chemistry was effective in etching both dielectrics as well as delineating the other phases present.
A Novel Method to Observe the Silicide in TEM
Authors: Liu Pan
Published: December 2020

In modern IC fabrication technology, metal silicide technology in microelectronics has been a standard process to reduce contact resistance. The thickness of metal silicide is an important parameter in reducing the contact resistance, especially, the 130nm, 90nm, and beyond technology. The traditional method to measure the thickness of silicide, however, has a dilemma as to whether to obtain the clear interface or to get the true thickness. This paper reports a novel method to improve the interface contrast and get a true thickness by changing the substrate single crystal contrast. Polishing and ion milling method were used to get thin transmission electron microscopy samples. In this paper, the substrate scattering probability is changed by tilting the samples. Using the method, a clear interface can be developed between the silicide and substrate single crystal silicon can be obtained without affecting the accuracy of the measured silicide thickness.
Thermal Imaging Product Power-up: Metrology for Capturing Thermal Defects on Live Units Not Visible on Any Other Technique
Authors: Zamora Nova T. , Chong Kam Meng , Gupta Ashish
Published: December 2020

This paper presented the recent application of die powerup in Thermal Imaging as applied to the detection of defects causing thermal failure on revenue products or units not being captured using other available techniques. Simulating the condition on an actual computer setup, the infrared (IR) camera should capture images simultaneously as the entire bootup process is being executed by the processor, thus revealing a series of images and thermal information on each and every step of the startup process. This metrology gives the failure analyst a better approach to acquire a set of information that substantiate in the conduct of rootcause analysis of thermal-related failure in revenue units, especially on customer returns. Defective units were intentionally engineered in order to collect the thermal response data and eventually come up with a plot of all known thermal-related defects.
Strategies for the Analysis of Single Unit Failures in Low Failure Rate Applications
Authors: Kolasa Ted , Kopycinski Jay , Mendoza Alfredo
Published: December 2020

Many manufacturers in the microelectronics industry supply customers who increasingly demand ultra-low product failure rates. However, one of the least desirable scenarios for the microelectronic failure analyst is when analysis is required on a single failed unit. In these cases, the analyst loses the luxury of having “disposable” failing units in the analysis process. In the following discussion we present strategies to help the analyst more effectively find the failure mechanism for single unit failures.
Improvement of Electrical Contacts in the Failure Analysis for in-depth Characterization of Structures and Products
Authors: Huettinger Michael , Touzel Jérôme
Published: December 2020

The electrical interface, in terms of a reliable, low ohmic and defined connection with the device or die is the most relevant aspect in the characterization of products. Bad or undefined contacts inhibit an exact assessment of the functionality. This paper describes different contact related failures analyzed in our lab and gives the solutions we used to solve the problems. Especially an electroless (nickel)-gold plating method has been optimized and is described in details. Low ohmic and reliable contacts can be produced; the paper shows several applications to improve the contact quality in different domains of the failure analysis business
Failure Analysis of Electronic and Microelectronic Components with a New Automatic Target Preparation System
Authors: Reiter Katja , Bundgaard Hans
Published: December 2020

Based on the requirements regarding target, reproducibility, and specimen surface quality, an automatic system for controlled material removal and target preparation has been developed. The tool is for metallographic failure analysis of electric and microelectronic components, and provides an accuracy of 5 micrometer. This article presents details of sample preparation and device evaluation methods. The images presented show typical objects of examination in the analysis of microstructures and materials in the electronics packaging industry with brief comments. For automatically controlled material removal and preparation, the tool offers alignment and measuring of the sample prior to the preparation. The desired preparation layers were achieved precisely and reproducibly with several specimens of the same kind. The automatic preparation system allowed the preparation of critical samples within a short time, with high precision and with excellent reproducibility.
An Atlas of ESD Failure Signatures in Vertical Cavity Surface Emitting Lasers
Authors: Mathes D.T. , Guenter J. , Hawkins B. , Hawthorne B. , Johnson C.
Published: December 2020

AOC herein describes a collection of material degradation features observed in Vertical Cavity Surface Emitting Lasers (VCSELs) that have been intentionally degraded with a range of electrostatic discharge (ESD) stress conditions. Failure analysis techniques employed include emission microscopy, Focused Ion Beam (FIB) microscopy and Transmission Electron Microscopy (TEM). The results have enabled higher confidence in root-cause determination for failed VCSEL devices.
3D Observation of Elemental Distribution of Si-Device using a Dedicated FIB/STEM System
Authors: Yaguchi T. , Konno M. , Kamino T. , Ogasawara M. , Kaji K. , Ohnishi T. , Watanabe M.
Published: December 2020

A technique for preparation of a pillar shaped sample and its multi-directional observation of the sample using a focused ion beam (FIB) / scanning transmission electron microscopy (STEM) system has been developed. The system employs an FIB/STEM compatible sample rotation holder with a specially designed rotation mechanism, which allows the sample to be rotated 360 degrees [1-3]. This technique was used for the three dimensional (3D) elemental mapping of a contact plug of a Si device in 90 nm technology. A specimen containing a contact plug was shaped to a pillar sample with a cross section of 200 nm x 200 nm and a 5 um length. Elemental analysis was performed with a 200 kV HD-2300 STEM equipped with the EDAX genesis Energy dispersive X-ray spectroscopy (EDX) system. Spectrum imaging combined with multivariate statistical analysis (MSA) [4, 5] was used to enhance the weak X-ray signals of the doped area, which contain a low concentration of As-K. The distributions of elements, especially the dopant As, were successfully enhanced by MSA. The elemental maps were reconstructed from the maps.
Burn-In Acceleration Considerations in 130nm and 90nm Products
Authors: Wakai Nobuyuki , Kobira Yuji , Setoya Takashi , Oishi Tamotsu , Yamasaki Shinichi
Published: December 2020

An effective procedure to determine the Burn-In acceleration factors for 130nm and 90 nm processes are discussed in this paper. The relationship among yield, defect density, and reliability, is well known and well documented for defect mechanisms. In particular, it is important to determine the suitable acceleration factors for temperature and voltage to estimate the exact Burn- In conditions needed to screen these defects. The approach in this paper is found to be useful for recent Cu-processes which are difficult to control from a defectivity standpoint. Performing an evaluation with test vehicles of 130nm and 90nm technology, the following acceleration factors were obtained, Ea>0.9ev and β (Beta)>-5.85. In addition, it was determined that a lower defect density gave a lower Weibull shape parameter. As a result of failure analysis, it is found that the main failures in these technologies were caused by particles, and their Weibull shape parameter “m” was changed depending of the related defect density. These factors can be applied for an immature time period where the process and products have failure mechanisms dominated by defects. Thus, an effective Burn-In is possible with classification from the standpoint of defect density, even from a period of technology immaturity.
Impact of Metal Pad Etch-Induced Plasma Damage on Dynamic Retention Time Degradation during High Temperature Stress in High Density DRAM Technology
Authors: Kim D-J , Kim I-G , Noh J-Y , Lee H-J , Park S-H , Lee J-H , Lee S-W , Yang K-H , Park Joosung , Shin Dongho , Oh Kyungseok
Published: December 2020

As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability. In this paper, the possible effects of floating potential at the source/drain junction of cell transistor during high-field charge injection are reported, and regarded as high-priority issues to further understand charging damage during the metal pad etching. The degradation of block edge dynamic retention time during high temperature stress, not consistent with typical reliability degradation model, is analyzed. Additionally, in order to meet the satisfactory reliability level in volume manufacture of high density DRAM technology, the paper provides the guidelines with respect to plasma damage. Unlike conventional model as gate antenna effect, the cell junction damage by the exposure of dummy BL pad to plasma, was revealed as root cause.
Effect of Ash Chemistries on TDDB Lifetime of Cu/ULK Interconnects
Authors: Chen L. -C. , Lai J. B. , Yang J. L. , Huang Renee , Huang R. L. , Su David H. , Tsai J. S. , Shieh J. H. , Jang S. M. , Liang M. S.
Published: December 2020

The effect of ash chemistries, N2/H2 and H2, on time-dependent dielectric breakdown (TDDB) lifetime has been investigated for Cu damascene structure with a carbon-doped CVD ultra low-k (ULK, k=2.5) intermetal dielectric. Two failure modes, interfacial Cu-ion-migration and Cu diffusion through the bulk intermetal ULK were attributed to the TDDB degradation for the H2 ash.The interfacial Cu-ion-migration was the only dominated failure mode for the N2/H2 ash. The nitrogen species in the N2/H2 plasma proved to be capable of forming a nitrided protection layer on the surface of the ULK. This nitrided layer suppressed further plasma damage during the ash process and thus lessened the TDDB degradation by preventing Cu diffusion through the bulk ULK.
Unique Autoclave Stress Induced Failure Mechanism
Authors: Butchko John , Gillette Bruce T.
Published: December 2020

Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.
Development of High Accuracy Automatic Magnification Calibration Function for Scanning Transmission Electron Microscope
Authors: Inada Hiromi , Terauchi D. , Takane A. , Aizawa S. , Tanaka H. , Tsuneta R. , Nakamura K. , Konno M. , Ozawa M.
Published: December 2020

In the field of semiconductor development and failure analysis, metrology of layers such as gate oxide layer is one of the important analysis due to determine semiconductor itself characteristics. The number of requirements of metrology is increasing by using both scanning and transmission electron microscopy. High accurate metrology depends on accuracy of magnification of electron microscope. We developed accurate magnification calibration for scanning transmission microscope. This method is carried out by using micro scale specimen and silicon single crystal lattice fringe images. We achieved absolute magnification error of less than 2% for all magnification. This microscope provides high accuracy metrology for semiconductor device. We describe an automatic magnification calibration function for the high magnification range required to accurately measure features from a few to tens of nm in size.
An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors
Authors: Tsai Pei Y. , Lee Junedong , Ronsheim Paul , Burns Lindsay , Murphy Richard , Almonte Marlene , Pfeiffer Gerd , Kleinhenz Richard , Guse Michael , Hovel H.J. , Sadana D.K.
Published: December 2020

A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.
Integration of Package Analysis Tools to Solve Discontinuity Failures
Authors: Tan Kevan V. , Hsiung Steve K.
Published: December 2020

Driven by ever increasing pin-counts and device performance, analyses of multi-layer package substrate failures are increasingly challenging. The tried method of global deprocessing delivers diminishing returns. Increasingly, an entire suite of specialized package analysis tools is needed to complement each other and achieve root-cause.
The Study and Methodology of Defects Isolation For Contacts of Non-Isolated Active Region on New Logic Designs
Authors: Wang C. H. , Shen C. M. , Lin C. J. , Lee Z. H. , Chou J. H.
Published: December 2020

With the advancement in technology and lower operating voltage, new standards have evolved in circuit layout and design. Some of these new standards have increased the difficulties of the physical failure analysis process, especially on the front-end. The phenomenon described in this paper is the unusual voltage contrast (VC) and conductive atomic force microscope (C-AFM) curve on a non-isolated active region. The model and mechanism are demonstrated for front-end failure analysis. Based on this, the solution for analysis is investigated.
Sectioning Integrated Circuit Ceramic Packages for Improved Electromigration Failure Analysis
Authors: Tracy Bryan , Barragan Jonnie , Grimberg Ilana , Raz Efrat
Published: December 2020

This article presents a step-by-step sample preparation method for the cross sectioning of silicon die in a ceramic package without the need for die removal or epoxy encapsulation. The sample preparation includes sawing the package, sample mounting to the polishing stub, and FIB cutting the area of interest and SEM Exam. In addition, a discussion on an automatic polishing method is included. This method is applicable for a broad range of silicon (Si) die package technologies and has also been successfully used on "TSOP" and state-of-the-art microprocessor packages which include the "organic" substrate, the Si die, and the massive copper die lid. The entire failure analysis is done at room temperature, eliminating any questions about sample preparation artifacts. Because the sample is imaged in the SEM at 90 degrees, much improved layer detail and voids microstructure is present in the final image.
THE EFFECT OF INCOME STABILISATION TOOL ON SLOVAK AGRICULTURE
Authors:   Slovak University of Agriculture in Nitra, Tr. A. Hlinku 2, 94976 Nitra, Slovakia, Boháčiková Andrea , Bencová Tatiana ,   Slovak University of Agriculture in Nitra, Tr. A. Hlinku 2, 94976 Nitra, Slovakia, Kapustová Zuzana ,   Slovak University of Agriculture in Nitra, Tr. A. Hlinku 2, 94976 Nitra, Slovakia
Published: December 2020

Managing income risk in agriculture is one of the important issues for farmers and policy makers nowadays. There exist a set of instruments and mechanisms for farmers to face the income volatility, including the individual or public support. Under II Pillar, the Common Agricultural Policy (CAP) offers the support for less favoured farms in the way of insurance, mutual fund, and Income stabilisation tool. The Income Stabilisation Tool (IST) represents the compensation to farmers for a “severe drop” in income, if the farm experienced an income loss of more than 30% compared to the 3-years average or the Olympic average of the preceding five-year income realizations. However, none of the EU countries has been currently using the tool operationally. The main objective of the paper is to investigate the potential effect of the Income Stabilisation Tool on mitigation of income risk in Slovak agriculture. The results of the paper show the existing possibility to improve financial situation and reduce the income inequality of particular Slovak farms in the future.
THE ECONOMIC VIABILITY OF THE ENERGY PRODUCTION FROM BIOMASS VIA ANAEROBIC DIGESTION
Authors:   Slovak University of Agriculture in Nitra, Faculty of Economics and Management, Department of Economics, Tr. A. Hlinku 2, 949 76 Nitra, Slovakia, Kapustová Zuzana , Boháčiková Andrea ,   Slovak University of Agriculture in Nitra, Faculty of Economics and Management, Department of Economics, Tr. A. Hlinku 2, 949 76 Nitra, Slovakia, Lajda Ján ,   Land technologies s.r.o., Hlohovecká 11, 951 41 Lužianky, Slovakia
Published: December 2020

Anaerobic digestion is a microbial process that occurs in the absence of oxygen where a community of microbial species breaks down both complex and simple organic materials, ultimately producing methane and carbon dioxide. Biogas refers to a secondary energy carrier that can be produced out of many different kinds of organic materials and its options for utilization can be equally versatile - biogas can be used to generate electricity, heat and biofuels. It is clear that introduction of the subsidies in 2009 for BGPs initiated usage of the AD technology for generating electric energy. The sharpest increase in number of BGPs was recorded in 2013; however, there was a major downsizing in their installation in 2014 due to change in the subsidy system. The main aim of the paper is to forecast economic viability of biogas plants in Slovakia based on the net present value indicator, estimation of payback period of the technology and assessment of the maximum economic price of input material.
THE EFFICIENCY OF PUBLIC HIGHER EDUCATION INVESTMENT ON ECONOMIC GROWTH IN VIETNAM
Authors:   Bucharest University of Economic Studies, Bucharest, Piața Romană 6, Romania, Trinh Nguyen Thi Hoai , Kieu Viet An ,   Technical University of Civil Engineering of Bucharest, Bulevardul Lacul Tei 124, Bucharest, Romania, Nhung Dao Thi Cam ,   Hue College of Economics - Hue University, Hue City, Thua Thien Hue Province, Vietnam
Published: December 2020

The purpose of this article is to evaluate the efficiency of public higher education investment in Vietnam’s economic growth through data reports from the Ministry of Education and Training, Ministry of Finance, the General Statistics Office, and the primary investigation of the authors. The paper focuses on an in-depth analysis of the costs of investing in higher education, such as state budget spending on higher education, the impact of budget expenditure on growth, individual investment (household) investment in public higher education, social costs for higher education public study, and average social cost for one learner. From the above analysis, the authors will present employment status and the impact of the problem on both economic growth and the average income of workers by technical expertise. Besides, the authors will compare the situation of investment in higher education and the economic growth rate of Vietnam to some countries in Southeast Asia. From there, the authors will determine the limitations of this impact process. Based on that, the authors will propose some solutions to improve the efficiency of investment in public higher education for Vietnam’s economic growth.
THE INFLUENCE OF DEVIANT FORMS OF DEVELOPMENT OF ENTREPRENEURIAL ENVIRONMENT ON THE ECONOMIC SECURITY OF UKRAINIAN ENTERPRISES
Authors: Grinko A.P.  , Bakalar D.
Published: December 2020

The article reveals the role of permanent monitoring of the exogenous environment for deviant forms of business environment development in order to develop and adjust the mission, strategy, operational measures of anti-inflation and anti-crisis nature to ensure economic security of economic entities. For this purpose, the evolution and essence of corruption are considered, as this fact not only reflects the negative trends in society, but also hinders the full progressive economic and political development of the state. Also, the existence of corruption and the generation of huge corruption losses in the course of corrupt interaction of corrupt officials with entrepreneurs and citizens can lead not only to direct social losses, but also to distort the institutional foundations of society, which negatively affects the economic security of enterprises. The analysis of deviant forms of business environment development is carried out and it is established that corruption is the most significant problem for business development in Ukraine. The consequences of this problem have been identified, which include the shadowing of business, the prevalence of illegal schemes and means of influence, the despair of a large number of entrepreneurs, which threatens the public system with destruction and leveling of the domestic legal system.
ALTERNATIVE SOURCES OF INFORMATION TO SUPPORT A SET OF STATISTICAL INDICATORS OF THE BOOK PUBLISHING
Authors: Olena Horobets
Published: December 2020

Issues of supporting the book publishing as an economic activity by a set of statistical indicators are investigated. It is found out that the existing set of statistical indicators does not meet the needs of researchers and practitioners, which is the case of not only Ukraine, but the global book publishing area. The case of the Ukrainian book publishing is taken for analysis to identify core problems faced by this industry. It is emphasized that a comprehensive study of the book publishing industry and presentation of the statistical information with high level of quality and aggregation requires the involvement of new alternative sources of data, of which big data should be highlighted. The component of scientific novelty is that an updated system of statistical indicators is proposed for the first time, with eight modules of sources of statistical information as alternative ones: questionnaires, electronic books, digital libraries, websites of publishers and bookstores, electronic diaries of reading (Goodreads as an example), social networks (Instagram, Facebook, Telegram (open channels)), video hosts (YouTube being the most popular one), and blogs. It is stressed that all the modules of alternative data must be involved for obtaining reliable data, where output data will be processed anew and have direct and reverse links, which will require the use of neural networks with efferent type of links. This statistical support to the book publishing industry is an innovation designed to meet urgent needs of the public and official statistics.