(Invited) UV and Gate Stress Induced Defects in Amorphous Indium Gallium Zinc Oxide Thin Film Transistors and Self-Repair
Authors: Jiang Jingxin , Kuo Yue 
Published: December 2020

In spite of its high field effect mobility, the a-IGZO TFT’s instability induced by the light illumination and the gate voltage (Vg
) stress is a crucial concern in many electrical and optical applications [1-4]. The wavelength of the illumination light affects the subthreshold swing (S) and threshold voltage (Vth
) [5,6]. In this paper, authors study the defects generation and self-repair phenomena in the a-IGZO TFT under the UV illumination and gate bias stress condition.

The inverted, staggered, tri-layer a-IGZO TFT was fabricated on a glass substrate, as shown in Figure 1. The SiOx gate dielectric layer was deposited by PECVD. The 50 nm-thick a-IGZO semiconductor layer was sputtered deposited from an In2O3:Ga2O3:ZnO (1:1:1 mole ratio) target at room temperature. The etch stopper (ES) layer was composed of SiOx (200 nm-thick)/AlOx (20 nm-thick). The source and drain electrodes were made of the Ti/Al/Ti stack. The passivation layer was made of PECVD SiOx (100 nm-thick)/SiNx (100 nm-thick).

The a-IGZO TFT was stressed under UV (λ = 395 nm, 0.3 mW cm−2) for 30 min, i.e., UVS (no Vg
bias), PBUVS (Vg
= 20V, Vd
= 0V), or NBUVS (Vg
= -20V, Vd
= 0V) for 30 minutes at room temperature. Then, the TFT was stored in dark at room temperature or heated to 200°C, followed by measurement of transfer characteristics at V
DS = 0.1 V periodically. Figure 2 shows curves of DS vs. relaxation time, i.e., time after releasing the stress condition, at room temperature. Without gate bias, the DS drop was large at the beginning and small later on, i.e., 92% vs. 4%. For the PBUVS stressed TFT, the DS vs. time curve overlaps with that of the UVS stressed TFT. Therefore, defects on the gate dielectric interface were of two types, i.e., quickly or slowly self-repaired. For the NBUVS stressed TFT, defects were recovered in three stages. In the first 5 minutes, they were reduced by 59%. In the next 330 minutes, they were slightly reduced. After 200 hr, they were completely removed. Although at the beginning, the DS of the NBUVS TFT was smaller than that of the UVS or PBUVS TFT, the defect recovery rate of the former was much slower than that of the latter. Separately, the DS vs. relaxation time curve was measured at 200°C. For the UVS or PBUVS stressed TFTs, the S was restored to the original, unstressed value in less than 5 minutes. However, for the NBUVS stressed TFT, the restoring of S progressed in two stages from different mechanisms.

The UV illumination caused the negative shift of the V
th and increase of S. Defects were created and saturated at the gate dielectric interface as well as in the bulk a-IGZO layer within a short period of UV exposure. The addition of the positive Vg
did not affect the mechanism of the defect-generation. Majority of these defects were loosely trapped and could be self-repaired after being stored shortly in dark at room temperature. Defects generated by the NBUVS were difficult to self-repair. At 200°C, all defects were removed in a short period of time.

In summary, under the UV illumination condition, the polarity of the bias Vg
determines the type of defects generated in the TFT. More detailed discussions on mechanisms of defects generation and repair will be presented. This study provides important information on the reliability the a-IGZO TFT, which is critical to real world applications.

Authors acknowledge Prof. Ting-chang Chang, Department of Physics of National Sun Yat-sen University, Kaohsiung, for providing samples. Jingxin Jiang thanks the Doctoral Scientific Research Foundation of Liaoning Province (project No. 201601156), National Natural Science Foundation of China (project No. 6187011861), and China Scholarship Council for proving financial support for her visit to Thin Film Nano and Microelectronics Laboratory, Texas A&M University through the Postdoctoral Research Program.

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[2] J. Jiang, et al., Appl. Phys. Express
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[3] H. Lu, et al., IEEE J. Electron Devices Soc.
5, 504 (2017).

[4] T. C. Fung, et al., J. Inf. Display
9, 21 (2008).

[5] X. Huang, et al., Appl. Phys. Lett.
100, 243505 (2012).

[6] T. Chen, et al., J. Phys. D: Appl. Phys.
50, 42LT02 (2017).

Figure 1