(Invited) Evaluation of Few-Layer MoS2 Transistors with a Top Gate and HfO2 Dielectric
Authors: Young Chadwin D , Zhao Peng , Bolshakov-Barrett Pavel , Azcatl Angelica , Hurley P. K. , Gomeniuk Y. Y. , Schmidt Michael , Hinkle Christopher L , Wallace Robert M 
Published: February 2020

Currently, transition metal dichalcogenides (TMDs) are under intense investigation due to their potential uses. [1] One reason for the interest is because TMDs exhibit a bandgap. This provides a key aspect that can enable their use in future transistors as alternative channel materials with high mobility values while also providing robust on/off ratios. Because of the need to overcome the short channel effects and lower the power consumption of field effect transistors (FETs) as their dimensions scaled down drastically, extensive research has been done on layer-by-layer TMDs over the past few years. [2-4] Furthermore, due to the variety of TMDs, which results in different bandgaps and overall offsets [5], there are theoretical predictions suggesting that TMDs are best introduced in “broken gap” tunneling field effect transistors (TFETs). Some of these device designs include dielectrics in contact with TMD material.

As we wait for advances in TMD materials growth, researchers are investigating relevant TMDs with most transistor structures being bottom gate devices for the ease of integration with an emphasis on the TMD material. However, there have been very few studies to investigate high-k dielectrics on these TMD materials. [6-8] Furthermore, even fewer studies are done on the interface characterization between dielectric and TMD, with even fewer still on the evaluation of this interface electrically [9, 10] and the implications to device performance and reliability. An obstacle of integrating high-k dielectrics on these two-dimensional (2-D) materials is the lack of bonds available at the surface that enables thin film deposition. On the other hand, the research on metal/TMD contacts is also important to improve the transistor performance. To reduce the contact resistance, the metal selection [2], doping techniques [11] and the understanding of carrier transport near the metal/TMD interface [12] still require scientific investigation.

Therefore, in this work, we will demonstrate top-gated few-layer MoS2 transistors with HfO2 dielectric and the subsequent electrical characterization. Few-layer MoS2 flakes were exfoliated from commercial natural MoS2 crystals and transferred onto the SiO2 /Si substrate. Using photolithography with a lift-off process, the source and drain of the transistor were formed with Au / Ti. Thereafter, a 15-minutes in-situ UV-O3 surface functionalization [6] was performed, and HfO2 was deposited at 200˚C using atomic layer deposition (ALD) immediately after the treatment. The final step of fabrication was deposition and patterning of Au / Cr metal gate. Electrical measurements were performed using a Keithley 4200 SCS and an Agilent E4980A LCR meter. The interface between MoS2 and HfO2 was studied by capacitance-voltage (C-V) measurements. Interface trap density (Dit) was extracted using the conventional high-low frequency method.

From the characterization results of a MoS2 transistor, the IDS-VGS exhibited an Ion/Ioff ratio of 106, and an ultra-low leakage current (~10-14 A) indicating a continuous dielectric thin film. In C-V measurements, a “hump” was observed in the depletion region, which indicates a large number of interface traps in the gate stack. It explains the SS degradation in the I-V measurements. The IDS-VDS curves show a non-linear region at low VDS, which are caused by non-optimized contacts. Moreover, we extracted the Dit, where a peak value of 1.2×1013 cm-2eV-1 was extracted. More physical characterization and analysis are needed to understand the origin of these interface traps. With this transistor test structure; however, the ability to study other TMDs beyond MoS2, HfO2, and Au/Ti contacts are possible.

This work is partially funded by National Science Foundation (NSF) award 1407765.

References: [1] Q. H. Wang, et al., Nat. Nano., 7, p. 699, 2012. [2] S. Das, et al., Nano Letters, 13, p. 100, 2012. [3] H. Liu et al., IEEE EDL, 33, p. 546, 2012. [4] B. Radisavljevic, et al., Nat Nano, 6, p. 147, 2011. [5] C. Gong, et al., APL, 103, p. 053513, 2013. [6] A. Azcatl, et al., APL,
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