bluuebunny/crossref_metadata_2025 huggingface dataset:
Direct Observation of Stress Relaxation Process in 4H-SiC Homoepitaxial Layers via In Situ Synchrotron X-Ray Topography
Authors: Guo Jian Qiu , Yang Yu , Raghothamachar Balaji , Dudley Michael , Weit Swetlana , Danilewsky Andreas N. , McNally Patrick J. , Tanner Brian R.
Published: June 2018

During 4H silicon carbide (4H-SiC) homoepitaxy and post-growth processes, the development of stress relaxation has been observed, in which interfacial dislocations (IDs) are formed at the epilayer/substrate interface, relaxing the misfit strain induced by the nitrogen doping concentration difference between the epilayer and substrate. It is widely believed that an interfacial dislocation is created by the glide of a mobile segment of a basal plane dislocation (BPD) in the substrate or epilayer towards the interface, leaving a trailing edge component right at the interface. However, direct observation of such mechanisms has not been made in SiC before. In this work, we present an in situ study of the stress relaxation process, in which a specimen cut from a commercial 4H-SiC homoepitaxial wafer undergoes the stress relaxation process during a high-temperature heat treatment while sequential synchrotron white beam X-ray topographs were recorded simultaneously. Based on the dynamic observation of this process, it can be concluded that thermal stress plays a role in the relaxation process while the increased misfit strain at elevated temperature most likely drives the formation of an interfacial dislocation.
X-Ray Topography Analysis of 4H-SiC Crystals Grown by the High-Temperature Gas Source Method
Authors: Kamata Isaho , Hoshino Norihiro , Tokuda Yuichiro , Makino Emi , Kanda Takahiro , Sugiyama Naohiro , Kuno Hironari , Kojima Jun , Tsuchida Hidekazu
Published: June 2018

Synchrotron X-ray topography was carried out for 4H-SiC crystals grown by high-temperature gas source method, and transmission topography analysis with g= or 0004 was carried out for the cross-sectional samples. Dislocation contrasts extended in the growth direction were observed and the propagation behavior of threading screw dislocations (TSDs), threading edge dislocations (TEDs), basal plane dislocations (BPDs) and stacking faults (SFs) in the facet and step-flow regions were discussed. The propagation of dislocations in the fast grown crystal with a growth rate of 3.1mm/h was also evaluated by cross-sectional topography.
Analysis of Compensation Effects in Aluminum-Implanted 4H-SiC Devices
Authors: Weisse Julietta , Hauck Martin , Sledziewski Tomasz , Tschiesche Mattias , Krieger Michael , Bauer Anton J. , Mitlehner Heinz , Frey Lothar , Erlbacher Tobias
Published: June 2018

In this work, we analyze compensating defects which are formed after implantation of aluminum (Al) into n-type 4H-SiC epitaxial layers and subsequent thermal annealing. These defects reduce the expected free charge carrier density by 84% for a low doped layer with [Al]impl ≈ 9·1016 cm-3 and by 27 % for a high doped layer with [Al]impl ≈ 2·1019 cm-3. Furthermore, an electrical activation ratio of implanted aluminum ions of 100 % is calculated. The ionization energy of implanted aluminum as measured by Hall effect and admittance spectroscopy ranges from 101 meV to 305 meV depending on the doping concentration.
Investigation of Run-to-Run Fluctuation in Growth Conditions of Physical Vapor Transport Growth of 4H-SiC Crystals
Authors: Matsumoto Nana , Shinya Hiroaki , Ashida Koji , Kaneko Tadaaki , Ohtani Noboru , Katsuno Masakazu , Tsuge Hiroshi , Sato Shinya , Fujimoto Tatsuo
Published: June 2018

We investigated the run-to-run fluctuation in growth conditions of physical vapor transport growth of 4H-SiC boules through observations of surface morphology on the (000-1) facet of the boules. The boules, which were grown under the same macroscopic growth conditions, exhibited slightly different surface morphologies. This indicates that some microscopic growth parameters that influence the surface morphology fluctuate between growth runs. We have considered the C/Si ratio of the vapor sublimed from the source material as a major parameter and discussed the associated variations in the physical and surface properties of the grown crystals.
Modeling and Simulation of Electrical Activation of Acceptor-Type Dopants in Silicon Carbide
Authors: Šimonka Vito , Hössinger Andreas , Weinbub Josef , Selberherr Siegfried
Published: June 2018

We propose an empirical model to predict electrical activation ratios of aluminium- and boron-implanted silicon carbide with respect to various annealing temperatures. The obtained parameters and model extensions are implemented into Silvaco’s Victory Process simulator to enable accurate predictions of post-implantation process steps. The thus augmented simulator is used for numerous simulations to evaluate the activation behavior of p-type dopants as well as for the full process simulation of a pn-junction SiC diode to extract the carrier and acceptor depth profiles and compare the results with experimental findings.
Diffusion of the Carbon Vacancy in a-Cut and c-Cut n-Type 4H-SiС
Authors: Bathen Marianne E. , Ayedh Hussein M. , Vines Lasse , Farkas Ildiko , Janzén Erik , Svensson Bengt Gunnar
Published: June 2018

The diffusion of the carbon vacancy (VC) in n-type 4H-SiC has been studied using Deep Level Transient Spectroscopy (DLTS). Samples grown along two different crystallographic planes, (0001) or c-cut and (11-20) or a-cut, have been utilized. The samples were implanted with 4.0 MeV C ions to generate VC’s and subsequently annealed at temperatures between 200 and 1500 °C. Following each annealing stage, concentration versus depth profiles of the VC were obtained. The VC is essentially immobile in both the c-cut and a-cut samples up to at least 1200 °C. The 1400 °C annealing stage, however, resulted in considerable migration, predominantly along the a-direction. Using half the difference in the Full Width at Half Maximum (FWHM) of the initial and diffused concentration profiles as a measure of the diffusion length, we deduced the diffusivity of the VC at 1400 °C to be approximately (3.8±1.1)×10-14 cm2/s along the c-axis and (4.1±1.2)×10-13 cm2/s along the a-axis, indicating a substantial anisotropy for the VC diffusion in 4H-SiC.
Influence of Dislocations to the Diamond SBD Reverse Characteristics
Authors: Akashi Naoya , Seki Akinori , Saito Hiroaki , Kawai Fumiaki , Shikata Shinichi
Published: June 2018

Several studies have been carried out regarding the influence of dislocations on device characteristics; however, most of them had been limited to pseudo-vertical structures using high pressure high temperature (HPHT) insulating material as the substrate. In this study, we have investigated the influence of dislocations to the devices using vertical structure SBD on p+ HPHT substrate. SBDs were selectively fabricated on specific dislocation areas. The SBD fabricated on the threading dislocation area indicated fatal influence of the dislocation on the device characteristics.
Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC
Authors: Hallén Anders , Suvanam Sethu Saveda
Published: June 2018

The radiation hardness of two dielectrics, SiO2 and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011 cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3 can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.
Kinetics Modeling of the Carbon Vacancy Thermal Equilibration in 4H-SiC
Authors: Ayedh Hussein M. , Nipoti Roberta , Hallén Anders , Svensson Bengt Gunnar
Published: June 2018

The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.
High Resolution Optical Spectroscopy of Free Exciton and Electronic Band Structure near the Fundamental Gap in 4H SiC
Authors: Klahold Walter M. , Choyke Wolfgang J. , Devaty Robert P.
Published: June 2018

We use thick, relatively high purity 4H SiC boule material to measure the wavelength modulated absorption spectrum with improved wavelength resolution and sensitivity with respect to previous work. We observe several small 0.6 ± 0.1 meV splittings, which we attribute to electron mass anisotropy and electron-hole exchange interaction. In addition, we identify several features in the absorption spectrum as signatures of nonparabolicity in the free exciton dispersion relations, the primary origin of which is likely the nonparabolic energy dispersion of the valence bands, as revealed by published band structure calculations based on density functional theory.
The Effects of Illumination on Point Defects Detected in High Purity Semi-Insulating 4H-SiC
Authors: Alfieri Giovanni , Kranz Lukas , Knoll Lars , Sundaramoorthy Vinoth
Published: June 2018

The electrical characterization of high-purity semi-insulating 4H-SiC is carried out by means of current deep level transient spectroscopy (I-DLTS). Measurements are performed by employing either an electrical or optical pulse (below/above bandgap). The study performed on as-grown material, either annealed or oxidized, reveals the presence of six levels with ionization energies in the 0.4-1.3 eV range.
Microscopic FCA System for Depth-Resolved Carrier Lifetime Measurement in SiC
Authors: Mae Shinichi , Tawara Takeshi , Tsuchida Hidekazu , Kato Masashi
Published: June 2018

For high voltage SiC bipolar devices, carrier lifetime is an important parameter, and for optimization of device performance, we need to control distribution of the carrier lifetime in a wafer. So far, there have been limited systems for depth-resolved carrier lifetime measurements without cross sectional cut. In this study, we adopted a free carrier absorption technique and made local overlapping of the probe laser light with excitation laser light to develop depth-resolved carrier lifetime measurements. We named the developed system a microscopic FCA system and demonstrated measurement results for samples with and without intentional carrier lifetime distribution.
The Effect of Stepped Wall of the Graphite Crucible in Top Seeded Solution Growth of SiC Crystal
Authors: Choi Su Hun , Kim Young Gon , Shin Yun Ji , Jeong Seong Min , Lee Myung Hyun , Lee Chae Young , Choi Jeong Min , Park Mi Seon , Jang Yeon Suk , Lee Won Jae
Published: June 2018

The crucible design having a stepped wall was introduced for increasing the growth rate of SiC crystal without metal addition in top-seeded solution growth (TSSG) method. The numerical simulation confirmed that new crucible design to increase the solvent-crucible interface could definitely change the temperature distribution and increase the carbon concentration. The simulation result, SiC single crystals were grown with Si solvent at 1900°C using a normal crucible and a stepped crucible to investigate the effect of crucible design having a stepped wall. Grown SiC layers were analyzed using Optical microscopy and Raman spectra. The growth rate in the stepped crucible was finally 66um/h observed.
Characterization of Inhomogeneity in Thermal Oxide SiO2 Films on 4H-SiC Epitaxial Substrates by a Combination of Fourier Transform Infrared Spectroscopy and Cathodoluminescence Spectroscopy
Authors: Yoshikawa Masanobu , Inoue Keiko , Sameshima Junichiro , Seki Hirohumi
Published: June 2018

We measured Fourier transform infrared (FT-IR) and cathodoluminescence (CL) spectra of SiO2 films with a various thickness, grown on 4H-SiC substrates. The peak frequency of the transverse optical (TO) phonon mode was blue-shifted by about 5 cm−1 as the oxide-layer thickness decreased from 50-60 nm to 10 nm. The blue shift of the TO mode is considerd to be caused by interfacial compressive stresses in the oxide-layer. On the other hand, the TO phonon mode was found to dramatically decrease as the oxide-layer thickness decreased from 10 nm to 1.7 nm. The CL measurement indicates that the intensity of the CL peaks at about 460 and 490 nm attributed to oxygen vacancy centers (OVCs) for No.2 become stronger than that for No.1. From a comparison between FT-IR and CL measurements, we concluded that the red-shift of the TO phonon with decreasing the oxide-layer thickness can mainly be attributed to an increase in inhomogeneity at the SiO2/SiC interface with decreasing oxide-layer thickness.
Annealing Behavior of Electrical Resistivities Perpendicular and Parallel to the Basal Plane of Heavily Nitrogen-Doped 4H-SiC Crystals
Authors: Okawa Kiyo , Mannen Yuina , Shioura Kentaro , Ohtani Noboru , Katsuno Masakazu , Tsuge Hiroshi , Sato Shinya , Fujimoto Tatsuo
Published: June 2018

The annealing behavior of electrical resistivities perpendicular and parallel to the basal plane of heavily nitrogen-doped 4H-SiC crystals was investigated. The temperature dependencies of the resistivities exhibited characteristic behaviors after multiple rounds of high-temperature annealing (1100°C, 30 min). High-temperature annealing induced stacking fault formation to various extents in heavily nitrogen-doped 4H-SiC crystals. Based on these results, we discuss the cause and mechanism of the observed annealing-induced changes in electrical resistivities of the crystals.
Electrical Challenges of Heteroepitaxial 3C-Sic on Silicon
Authors: Pradeepkumar Aiswarya , Gaskill D. Kurt , Iacopi Francesca
Published: June 2018

Epitaxial cubic silicon carbide films on silicon have attracted extensive interest for semiconductor device applications such as high-voltage, high-frequency diodes, and hetero-junction bi-polar transistors [1]. This is because they can offer access to the properties of the SiC material such as its wide band gap and high thermal conductivity on the more conventional silicon substrates [2]. Rahimi et al. have shown, however, that the substantial tensile strain generated from the lattice and thermal expansion coefficient mismatch between 3C-SiC and silicon, may reduce the band gap in the SiC epitaxial films [3]. Nevertheless, the impact of this phenomenon on the electrical and electronic performance of the epitaxial SiC films on silicon has not been fully elucidated to date; such information is vital to obtain the optimal performance of devices fabricated from these strained heterojunctions.
Structural Quality, Polishing and Thermal Stability of 3C-SiC/Si Templates
Authors: Zielinski Marcin , Monnoye Sylvain , Mank Hugues , Moisson Catherine , Chassagne Thierry , Michon Adrien , Portail Marc
Published: June 2018

First objective of present contribution is to supply a compact description of two thickness-dependent characteristics of state of the art as-grown 3C-SiC/Si templates: structural quality and surface morphology. Second objective is to point out the benefits of surface planarization and indicate the temperature limits of thermal treatment that can be applied to polished 3C-SiC/Si templates without deterioration of planarization results. We believe that this kind of overview, based on our long term experience in fabrication of 3C-SiC/Si templates, may be useful for the scientific community working on future applications of cubic silicon carbide polytype.
Development of Solvent Inclusion Free 4H-SiC Off-Axis Wafer Grown by the Top-Seeded Solution Growth Technique
Authors: Kusunoki Kazuhiko , Seki Kazuaki , Kishida Yutaka , Kaido Hiroshi , Moriguchi Koji , Daikoku Hironori , Kado Motohisa , Shirai Takayuki , Akita Mitustoshi , Saito Hiroaki
Published: June 2018

This study reports our newly developed technology for SiC solution growth. In particular, we succeed in completely suppressing solvent inclusions, which have been a serious technological problem peculiar to the solution growth method. Then, we fabricate two-inch-diameter 4° off-axis SiC wafers without solvent inclusions. Moreover, we performed their crystal defects evaluation. It was found that our wafers were low resistance n-type 4H-SiC and contain almost no basal plane dislocation. As a result, the superior quality of our solution-grown crystal was confirmed.
Infrared Reflectance Study of the Graphene/Semi-Insulating 6H-SiC(0001) Heterostructure
Authors: Auge Manuel , Hähnlein Bernd , Pezoldt Joerg
Published: June 2018

The optical response of graphene on 6H-SiC was investigated by means of IR-reflectance measurements. Thereby, the anisotropy of the substrate is considered and its influence was studied by performing measurements with s- and p-polarized light. The anisotropy causes a splitting of the reststrahlen band in p-polarization, but does not affect spectra recorded with s-polarization. In both cases a thin film approximation was used to simulate the reflectance spectra. A model consisting of SiC, graphene and air enables the extraction of the graphene layer count.
Application of Si-Vapor Ambient Anneal for Post Ion Implantation Anneal and Simultaneous Improvement of Trench Sidewall Smoothness
Authors: Yabuki Norihito , Torimi Satoshi , Nogami Satoru , Kitabatake Makoto , Kaneko Tadaaki
Published: June 2018

We propose the Si-vapor ambient anneal as a cap-free activation annealing (A/A) method for Silicon Carbide (SiC) using Tantalum Carbide / Tantalum composite materials (TaC/Ta). This method prevents the roughening of SiC surface by controlling the process function without conventional Carbon (C)-cap [1,2]. In this report, we evaluated the warping behavior of SiC wafer to confirm the effect of ion implantation (I/I) temperature (TI/I) and epi-ready treatment using Si-vapor ambient anneal. Wafer warp suppressing effect of high temperature I/I was confirmed and large wafer warpage occurred due to thinning of the wafer thickness. Furthermore we also observed the simultaneous improvement of the sharp edge shape and sidewall roughness of the trench under the appropriate conditions of the Si-vapor ambient anneal. It is possible to shape the round shape of the trench edge and to improve the roughness of trench sidewall by Si-vapor ambient anneal simultaneously with activation annealing process.
Characterization of pn-Diode Fabricated from Surface Damage-Free 4H-SiC Wafer Using Si-Vapor Etching Process
Authors: Torimi Satoshi , Yabuki Norihito , Sakaguchi Takuya , Shinohara Masato , Teramoto Yoji , Nogami Satoru , Kitabatake Makoto , Senzaki Junji
Published: June 2018

We investigate electrical characteristics of the pn-diode fabricated using the epitaxial films on the surface damage-free 4H-SiC (0001) Si-face 4° off-cut wafers prepared by the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. The forward and reverse current-voltage (I-V) characteristics of pn-diodes correlated to the epitaxial defects are discussed. The device at the defect-free area includes 11 % failed diodes on the chemo-mechanical polishing (CMP) wafer while 0 % on the Si-VE wafer. The latent scratches and mechanical damages, which increase the forward and reverse leakage current of the pn-diodes, are completely removed by the Si-VE. The Si-VE exposes the carbon inclusions in the wafer to form the small bump which ends up with the larger bump defect on the epitaxial surface. These bumps cause leak current of the forward characteristics while all of the reverse characteristics are normal. The epitaxial film on the Si-VE surface has less density of the basal plane dislocations (BPDs) than the conventional CMP. It is hard to recognize the safe device on the CMP wafer without additional reliability test. The Si-VE wafer shows the apparent breakdown voltage fail on every small-number diode including BPDs under the simple test. It is considered that the Si-VE is possible to reduce ambiguity of the device characteristics under the relationship with the defects in comparison with the CMP.
Effect of Ion Implantation-Induced Defects on Leakage Current Characteristics of IEMOS
Authors: Furukawa Yukihiro , Suzuki Hideo , Tani Noriaki , Kobayashi Yusuke , Ohse Naoyuki , Harada Shinsuke , Fukuda Kenji
Published: June 2018

We investigated the relationship between ion implantation-induced defects and electrical characteristics, especially focusing on the leak failure rate in SiC IEMOSs and PN diodes. It was found that dislocation exists in each leakage point by analyzing identical leak-failed IEMOS by emission microscopy and refraction X-ray topography. The leak failure rate of the PN diodes and IEMOS was improved with an increase in the ion implantation temperature under the implantation and annealing conditions used in this experiment. It is considered that ion implantation-induced defects lead to an increase in leak failure rates, and also enable a decrease in leak failure rates by raising the implantation temperature up to 600 deg.C.
Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design
Authors: Jiang Yi Fan , Baliga B. Jayant , Huang Alex Q.
Published: June 2018

This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.
4H-Silicon Carbide Wafer Surface after Chlorine Trifluoride Gas Etching
Authors: Okuyama Shogo , Kurashima Keisuke , Nakagomi Ken , Habuka Hitoshi , Takahashi Yoshinao , Kato Tomohisa
Published: June 2018

In order to develop the high etching rate reactor for silicon carbide, the 50-mm-diameter C-face 4H-silicon carbide wafer was etched using the chlorine trifluoride gas at 500 °C. By the deep etching, the concentric-circle-shaped valleys were formed at the positions corresponding to the radii of the pin-hole arrays of the gas distributor, as predicted by the calculation. The etching rate profile of 4H-silicon carbide was concluded to have a relationship with the local chlorine trifluoride gas supply . The wafer bow was small, even the wafer was very thin, about 160 μm thick.
Surface Erosion of Ion-Implanted 4H-SiC during Annealing with Carbon Cap
Authors: Linnarsson Margareta K. , Ayedh Hussein M. , Hallén Anders , Vines Lasse , Svensson Bengt Gunnar
Published: June 2018

The stability/ erosion of the interface between a C-cap and 4H-SiC have been studied by secondary ion mass spectrometry (SIMS). Aluminum implantation has been used to monitor the position of the moving interface as well as to investigate the influence on the interface stability by the crystal quality of the 4H-SiC. After Al implantation a C-cap has been deposited by pyrolysis of photoresist. Subsequent annealing has been performed at 1900 and 2000 °C with durations between 15 minutes and 1 hour. SIMS measurements have been performed without removal of the C-cap. The surface remains smooth after the heat treatment, but a large amount of SiC material from the uppermost part of the wafer is lost. The amount of lost material is related to for instance annealing temperature, ambient conditions and ion induced crystal damage. This contribution gives a brief account of the processes governing the SiC surface decomposition during C-cap post implant annealing.
Study of Ti/Al/Ni Ohmic Contacts to p-Type Implanted 4H-SiC
Authors: Vivona Marilena , Greco Giuseppe , Bongiorno Corrado , Di Franco Salvatore , Lo Nigro Raffaella , Scalese Silvia , Rascunà Simone , Saggio Mario , Roccaforte Fabrizio
Published: June 2018

This work reports on the electrical and microstructural properties of Ti/Al/Ni contacts to p-type implanted 4H-SiC obtained by rapid thermal annealing of a metal stack of Ti (70 nm)/Al (200 nm)/Ni (50 nm). The contact characteristics were monitored at increasing value of the annealing temperature. The Ohmic behavior of the contact, with a specific contact resistance value of 2.3×10-4 Ω·cm2, is obtained for an annealing at 950 °C. The structural analyses of the contact, carried out by XRD and TEM, reveal the occurrence of reactions, with the detection of the Al3Ni2 and AlTi phases in the upper part of the contact and of an epitaxially oriented TiC layer at the interface. These reactions are considered the key factors in the formation of an Ohmic contact in our annealed Ti/Al/Ni system. The temperature-dependence study of the electrical characteristics reveals a predominant thermionic field emission (TFE) mechanism for the current conduction through the contact, with a barrier height of 0.56 eV.
Pt:Ti Diffusion Barrier, Interconnect, and Simultaneous Ohmic Contacts to n- and p-Type 4H-SiC
Authors: Okojie Robert S. , Lukco Dorothy
Published: June 2018

We report the initial results of using co-sputtered Pt:Ti 80:20 at. % composition ratio metallization as a diffusion barrier against gold (Au) and oxygen (O), as an interconnect layer, as well as forming simultaneous ohmic contacts to n-and p-type 4H-SiC. Having a single conductor with such combined multi-functional attributes would appreciably reduce the fabrication costs, processing time and complexity that are inherent in the production of SiC based devices. Auger Electron Spectroscopy, Focused Ion Beam-assisted Field Emission Scanning Electron Microscopy and Energy Dispersive Spectroscopy analyses revealed no Au and O migration to the SiC contact surface and minimal diffusion through the Pt:Ti barrier layer after 15 minutes of exposure at 800 oC in atmosphere, thus offering potential long term stability of the ohmic contacts. Specific contact resistance values of 7 x 10-5 and 7.4 x 10-4 Ω-cm2 were obtained on the n (Nd=7 x 1018 cm-3) and p (Na=2 x 1020 cm-3) -type 4H-SiC, respectively. The resistivity of 75 μΩ-cm was obtained for the Pt:Ti layer that was sandwiched between two SiO2 layers and annealed in pure O ambient up to 900 °C, which offers promise as a high temperature interconnect metallization.
Ni-Al-Ti Ohmic Contacts with Preserved Form Factor and Few 10- 4 Ωcm2 Specific Resistance on 0.1-1 Ωcm p-Type 4H-SiC
Authors: Nipoti Roberta , Puzzanghera Maurizio , Canino Mariaconcetta , Sozzi Giovanna , Fedeli Paolo
Published: June 2018

This study shows that a thin Ni film on Al/Ti/4H-SiC metal pads allows to preserve the pad form factor during a 1000 °C/2 min treatment, provided that the Al and Ti film thicknesses are sufficiently thin. Moreover, by reducing the Al to Ti thickness ratio, droplet formation in the contact area is avoided and a mirror-like appearance is obtained. This optimal contact morphology corresponds to a specific contact resistance of few 10-4 Ωcm2 at room temperature on p-type 4H-SiC with resistivity in the range 0.1 – 1 Ωcm.
Formation of the Uniform Interface Ni/4H-SiC Ohmic Contact with Titanium as Barrier Layer
Authors: Na Moon Kyong , Kang In Ho , Moon Jeong Hyun , Bahng Wook
Published: June 2018

Nickel (Ni) is the most widely used metal for the formation of ohmic contact on n-type SiC. However, the irregular contact can potentially cause degradation in the device performance. To form the uniform ohmic interface, titanium (Ti) was applied as a barrier layer. Ni/Ti/SiC and Ti/Ni/SiC contact metal structures were prepared, and ohmic contacts were formed using a rapid thermal annealing process. The interfacial properties of both contact metal structures were enhanced by applying the Ti layer. The specific contact resistance of ohmic contacts showed a slightly lower or similar value (~ low 105 Ωcm2) compared with the specific contact resistance values formed from only the Ni contact metal.
Extremely Thermal Stable Ni/W/TaSi2/Pt Simultaneous Ohmic Contacts to n-Type and p-Type 4H-SiC
Authors: Li Yan Liang , Zhang Yi Meng , Tang Xiao Yan , Guo Tao , Zhang Yu Ming
Published: June 2018

Studying the ohmic contacts formed on ion-implanted SiC layers is fundamental to understand and to predict the behavior of practical devices. Ohmic contacts to n- (1×1019 cm−3) and p-type (1×1020 cm−3) ion-implanted 4H-SiC using Ni/W/TaSi2/Pt were investigated. No degradation of the specific contact resistance nor a minute change of the surface morphologies was observed after 300 h of 500 oC thermal treatment in air. From auger electron spectroscopy (AES) depth profiles, it was found that the oxidation of the protective platinum silicide overlayer significantly slowed down further migration of oxygen to the SiC interface. In addition, Pt and W played the role of mutual blocking, which guarantees the stability of the contact. This research suggests that the contacts are very promising for applications in harsh environments, where the simultaneously completed both on n-and p-type stability ohmic contacts is crucial.
Electrical Property Study of Ni/Nb Contact to n-Type 4H-SiC
Authors: Liu Xue Chao , Zhuo Shi Yi , Chen Wei Bin , Dai Chong Chong , Shi Er Wei
Published: June 2018

A sandwich structure of Ni/Nb/4H-SiC was prepared and annealed at different temperature from 750°C to 1050°C. The electrical property and crystalline structure of Ni/Nb electrode was characterized by transmission line method and X-ray diffraction. It was found that the annealing temperature and the thickness of Ni/Nb layer played an important role in obtaining Ohmic contact. A low specific contact resistance of 1.1×10-5 Ω·cm2 was obtained when the Ni(50nm)/Nb(50nm) electrode was annealed at 1050°C. The Ohmic contact mechanism of Ni/Nb/4H-SiC was proposed.
Formation of Ohmic Contacts to n-Type 4H-SiC at Low Annealing Temperatures
Authors: Sundaramoorthy Vinoth , Minamisawa Renato Amaral , Kranz Lukas , Knoll Lars , Alfieri Giovanni
Published: June 2018

The formation of Ohmic contacts to n-type 4H-SiC layers at low annealing temperature using dopant segregation technique is reported. n-SiC epilayer was implanted with phosphorous and subsequently activated at 1700 °C. Ni metal contacts fabricated on phosphorous implanted and annealed epilayers produced Ohmic contacts with a specific contact resistivity (ρc) of ~7.2x10-5 Ω.cm2 at an annealing temperature of 550 °C. ρc decreased with further annealing temperature reaching a value of ~2.1x10-5 Ω.cm2 at 1000 °C. XRD analysis showed that nickel silicide phase was formed at both 550 °C and 1000 °C.
Investigation on the Effect of Ge Co-Doped Epitaxy on 4H-SiC Based MPS Diodes and Trench MOSFETs
Authors: Heidorn Christian , Esteve Romain , Höchbauer Tobias , Rupp Roland
Published: June 2018

The incorporation of Germanium (Ge) in 4H-SiC has recently being reported as enabling an increase of the electron mobility in n-type doped layers. The present work aims at evaluating the impact of the Ge doping on two types of SiC devices: Merged PiN-Schottky (MPS) diodes and Trench MOSFETs.
4H-SiC pMOSFETs with Al-Doped S/D and NbNi Silicide Ohmic Contacts
Authors: Kajihara Jun , Kuroki Shin Ichiro , Ishikawa Seiji , Maeda Tomonori , Sezaki Hiroshi , Makino Takahiro , Ohshima Takeshi , Östling Mikael , Zetterling Carl Mikael
Published: June 2018

4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200 °C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni, NbNi alloy, Ni and Nb/Ti were investigated, and the Nb/Ni silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.
Lifetime Enhancement of 4H-SiC PiN Diodes Using High Temperature Oxidation Treatment
Authors: Bonyadi Yeganeh , Gammon Peter Michael , Alatise Olayiwola , Bonyadi Roozbeh , Mawby Philip  Andrew
Published: June 2018

In this paper, the application of a high temperature thermal oxidation and annealing process to 4H-SiC PiN diodes with 35 μm thick drift regions is explored, the aim of which was to increase the carrier lifetime in the 4H-SiC. Diodes were fabricated using 4H-SiC material and underwent a thermal oxidation in dry pure O2 at 1550◦C followed by an argon anneal at the same temperature. Reverse recovery tests indicated a carrier lifetime increase of around 42% which is due to increase of excessive minority carriers in the drift region. The switching results illustrate that the use of this process is a highly effective and efficient way of enhancing the electrical characteristics of high voltage 4H-SiC bipolar devices.
Isotropic Oxidation by Plasma Oxidation and Investigation of RIE Induced Effects for Development of 4H-SiC Trench MOSFETs
Authors: Jayawardena Asanka , Ahyi Ayayi Claude , Liu Gang , Shaw Rob G. , Dhar Sarit
Published: June 2018

In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO2/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.
Oxygen Pressure Controlled Oxidation for Gate Insulator Process of SiC MOSFETs
Authors: Kobayashi Keisuke , Shimizu Haruka , Shima Akio
Published: June 2018

For the improvement of a SiC/SiO2 interface of SiC-MOSFET, we examined O2 partial pressure (PO2) controlled (OPC) oxidation process for the gate oxide formation. The OPC oxidation process has a potential to reduce interface state density (Dit) at SiC/SiO2 interface by using appropriate PO2 and oxidation temperature. However the process requires rapid thermal annealing which is not suitable for mass production. Thus we investigated the process using furnace. First, we optimized the OPC oxidation process for the furnace to realize low interface defect density. Secondly, we confirmed that reduction of Dit was determined by desorption of excess carbon in OPC process by the C–ψs measurement and X-ray photoelectron spectroscopy. Finally, a DMOSFET was fabricated using optimized OPC process. We measured the transfer characteristics, and found that the drain current with OPC was larger than without OPC process.
Novel Gate Insulator Process by Nitrogen Annealing for Si-Face SiC MOSFET with High-Mobility and High-Reliability
Authors: Asaba Shunsuke , Schimizu Tatsuo , Nakabayashi Yukio , Fukatsu Shigeto , Ito Toshihide , Iijima Ryosuke
Published: June 2018

The gate insulator process for SiC-MOSFET was examined and high-quality interface was realized by employing the pre-annealing process before high-temperature N2 annealing. The pre-annealing evidently activated the interface to introduce nitrogen, and then field-effect mobility exceeded 50 cm2/Vs. The fabricated sample also demonstrated superior bias temperature instability (BTI) and excellent breakdown electric field of 11.7 MV/cm.
Improvement of SiO2/4H-SiC(0001) Interface Properties by H2 and Ar Mixture Gas Treatment Prior to SiO2 Deposition
Authors: Tsuji Hidenori , Hosoi Takuji , Terao Yutaka , Shimura Takayoshi , Watanabe Heiji
Published: June 2018

We investigated the impact of high-temperature H2/Ar mixture gas treatment of 4H-SiC(0001) surfaces before SiO2 deposition on the electrical properties of SiO2/SiC interfaces. Physical characterizations revealed that the SiC surface treated by the H2/Ar mixture gas exhibited a (√3×√3)R30° structure composed of Si-O bonds, indicating that a well-ordered and stable silicate adlayer was formed by the treatment to passivate SiC(0001) surface. Electrical defects at the CVD-grown SiO2/SiC interface was significantly reduced by the treatment. Consequently, a peak electron mobility in SiC-MOSFETs with the deposited gate oxides was enhanced to 24.9 cm2/Vs.
Effects of CF4 Surface Etching on 4H-SiC MOS Capacitors
Authors: Kobayakawa Kiichi , Muraoka Kosuke , Sezaki Hiroshi , Ishikawa Seiji , Maeda Tomonori , Kuroki Shin Ichiro
Published: June 2018

Effects of CF4 etching on 4H-SiC MOS capacitor were investigated. Fluorine atoms were introduced to surface of 4H-SiC using CF4 dry etching process as a surface treatment, and 4H-SiC MOS capacitors with dry-oxide were fabricated with this treatment. As the results, breakdown electric field of the MOS capacitors was increased and variation of the characteristics became lower than that of MOS capacitor without this treatment.
The Effect of Nitrogen on the 4H-SiC/SiO2 Interface Studied with Variable Resonance Frequency Spin Dependent Charge Pumping
Authors: Anders Mark A. , Lenahan Patrick M. , Lelis Aivars J.
Published: June 2018

In this work, we study the effects of NO anneals on the interface of 4H-SiC MOSFETs via spin dependent charge pumping, an electrically detected magnetic resonance technique. We make measurements at high and ultra-low resonance frequencies. Our results indicate that the NO anneals both change the silicon vacancy energy levels as well as induces disorder at the interface. In addition, our results indicate that the changes in energy levels involve N atoms very close to VSi sites.
Temperature-Dependence Study of the Gate Current SiO2/4H-SiC MOS Capacitors
Authors: Fiorenza Patrick , Vivona Marilena , Iucolano Ferdinando , Severino Andrea , Lorenti Simona , Roccaforte Fabrizio
Published: June 2018

We present a temperature-dependence electrical characterization of the oxide/semiconductor interface in MOS capacitors with a SiO2 layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The post deposition annealing process in N2O allowed to achieve an interface state density Dit  9.0×1011cm-2eV-1 below the conduction band edge. At room temperature, an electron barrier height (conduction band offset) of 2.8 eV was measured using the standard Fowler-Nordheim tunneling model. The electron conduction through the SiO2 insulating layer was evaluated by studying the experimental temperature dependence of the gate current. In particular, the Fowler-Nordheim electron barrier height showed a negative temperature coefficient (dφB/dT = - 0.98 meV/°C), which is very close to the expected value for an ideal SiO2/4H-SiC system. This result, obtained for deposited SiO2 layers, is an improvement compared to the values of the temperature coefficient of the Fowler-Nordheim electron barrier height reported for thermally grown SiO2. In fact, the smaller dependence of φB on the temperature observed in this work represents a clear advantage of our deposited SiO2 for the operation of MOSFET devices at high temperatures.
Correlation between Field Effect Mobility and Accumulation Conductance at 4H-SiC MOS Interface with Barium
Authors: Muraoka Kosuke , Ishikawa Seiji , Sezaki Hiroshi , Maeda Tomonori , Kuroki Shin Ichiro
Published: June 2018

A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO2 and a conventional dry SiO2. The field effect mobility was enhanced by introducing the barium-introduced SiO2. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO2 had a lower interface state density of 2×1011 cm-2eV-1 than that of the conventional dry SiO2.
Improved Threshold Voltage Instability in 4H-SiC MOSFETs with Atomic Layer Deposited SiO2
Authors: Kang Min Seok , Lee Bong Mook , Misra Veena
Published: June 2018

This study reports the electrical characteristics and reliability of the atomic layer deposited SiO2 on the 4H-SiC substrate. By controlling the thickness of SiO2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO2 dielectrics as well as reduction in interface state density at SiC/SiO2 interface.
SEMI Standards for SiC Wafers
Authors: Oliver James D. , Kremer Russ , Weber Arnd Dietrich , Nguyen Kevin , Amano James
Published: June 2018

SEMI Standards charter is to develop standards that benefit the semiconductor industry. The SEMI organization has evolved over the last 40 years into an international organization with covering all aspects of semiconductor and flat panel materials and devices. SEMI Standards provides the framework for the development of consensus based standards documents. At present there are two published standards specific to silicon carbide, the first dealing with dimensions, properties and ordering information for SiC wafers, and the second defining a nomenclature for defects found on SiC: SEMI M55-0817 Specification for Polished Monocrystalline Silicon Carbide Wafers SEMI M81-0611 Guide to Defects Found on Monocrystalline Silicon Carbide Substrates Additional standards applicable to various semiconductor wafers also are available and new SiC related standards are being developed based on industry needs and volunteer participation.
Borosilicate Glass (BSG) as Gate Dielectric for 4H-SiC MOSFETs
Authors: Zheng Yong Ju , Isaacs-Smith Tamara , Ahyi Ayayi Claude , Dhar Sarit
Published: June 2018

In this work, we investigate the effect of borosilicate glass (BSG) as gate dielectric on dielectric/4H-SiC interface traps and channel mobility in 4H-SiC MOSFETs. The interface trap characterization by C−ψs analysis and I-V characterization show lower fast interface trap density (Dit) as well as significant improvement of channel field-effect mobility on devices with BSG than that on devices with standard NO anneal. In addition, the results indicate interface trap density decreases with increasing B concentration at the interface of BSG/4H-SiC, which in turn, results in higher channel mobility.
MOCVD Compatible Atomic Layer Deposition Process of Al2O3 on SiC and Graphene/SiC Heterostructures
Authors: Eckstein Marco , Koppka Christian , Thiele Sebastian , Mi Yan , Xu Rui , Lei Yong , Hähnlein Bernd , Schwierz Frank , Pezoldt Joerg
Published: June 2018

Aluminium oxide was deposited on silicon, silicon carbide and epitaxial graphene grown on silicon carbide by atomic layer deposition using a standard MOCVD equipment. The morphology and the electrical properties of the aluminium oxide layers on both substrates were determined and compared to aluminium oxide layers deposited with a standard atomic layer deposition equipment. The high-k material fabricated with the developed MOCVD process show comparable or better properties compared to the standard atomic layer deposition process.
Solution Growth of SiC from the Crucible Bottom with Dipping under Unsaturation State of Carbon in Solvent
Authors: Taishi Toshinori , Takahashi Masaru , Tsuchimoto Naomichi , Suzuki Koki , Hyun Koang Yong
Published: June 2018

SiC crystals are grown using a Si-Cr-based solvent by a top-seeded solution growth (TSSG) method by changing the dipping time after when the growth temperature is reached. Step-flow-like curve morphologies were observed for a dipping time after 15 min, while polycrystallization occurred at the periphery for that after 120 min, which corresponded to the dipping under unsaturated and supersaturated carbon in the solvent, respectively. Furthermore, the solution growth of SiC with dipping under unsaturated carbon was easily realized by the growth from the crucible bottom, step-flow-like growth was achieved. Using this technique, dominant polytypes of SiC in various growth conditions after stable seed dipping under the unsaturation in the solvent can be demonstrated.
Incoming and Inline Defectivity Control Solutions for Silicon Carbide Manufacturing
Authors: Arias Daniel , Coppola Mario , Piluso Nicolo , Lorenti Simona , Coco Marcello , di Salvo Antonella , Anoop S. , Parisi Paolo , Arena Giuseppe , Franco Giovanni
Published: June 2018

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ide
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C
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ring is transitioning from 4 inch wafers to 6 inch wafers for production line devices. The main obstacle for SiC manufacturing high yield is defect control. Defectiveness inline control is well established for silicon power device. However, there are two main challenges related to SiC technology. The first challenge is incoming 4H-SiC substrates defectivity and epi layer crystallographic defects. The second challenge is inline defect detection at process steps such as implantation and annealing activation [,]. Defect detection and classification are difficult with current defect inspection tools because of substrate transparency at visible light, color variation, roughness, and wafers’ high warpage. In addition, SiC device integration has been requesting specific optimization. In this paper, collaboration studies have been done to develop solutions to these challenges. Yield correlation analyses have validated the process control flow set to address these two major challenges and to enable the fast ramp of the 6” production line of SiC devices.
Regional Manufacturing Cost Structures and Supply Chain Considerations for SiC Power Electronics in Medium Voltage Motor Drives
Authors: Reese Samantha , Horowitz Kelsey , Remo Timothy , Mann Margaret
Published: June 2018

With the growth in wide bandgap (WBG) semiconductors, specifically Silicon Carbide (SiC), the technology has matured enough to highlight a need to understand the drivers of manufacturing cost, regional manufacturing costs, and plant location decisions. Further, ongoing research and investment, necessitates analytical analysis to help inform development of wide bandgap technologies. The paper explores the anticipated device, module, and motor drive cost at volume manufacturing. It additional outlines the current regional contributors to the supply chain and proposes how the base models can be used to evaluate the cost reduction potential of proposed research advances.