bluuebunny/crossref_metadata_2025 huggingface dataset:
Additive Packaging for Bare Die and Additively Integrated Antenna
Authors: Areias Christopher , Lamport Emily , Piro Yuri , Cason Michael , Armiento Craig , Akyurtlu Alkim
Published: May 2023

This paper presents the use of Additive Manufacturing (AM) in packaging applications. Specifically, the

design, fabrication, and test of an AM packaged receiver phased array front-end will be shown. As part of

this work, an LNA and phase shifter bare die will be directly integrated on board with the antenna array.

The bare die integration is conducted through attaching the die to a pocket milled into the dielectric of a

copper laminate. Filet bridges between the chip and board are then applied using a photocurable dielectric

ink, and aerosol-jet silver conductors are printed overtop. Rigorous modeling of the phase shifter and LNA

die are conducted and compared to measured data. The two-element array will be printed alone with

spacing and amplitude/phase excitation for broadside radiation and the measured results for the antenna

will be compared with simulated results from Ansys HFSS modeling tool. Finally, the fully integrated

system will be assembled on a single substrate and tested
Finding a Happy Medium for Heterogeneous Cache Integration using M-Series Fan-out Technology
Authors: San Jose Benedict , Davis Robin , Bishop Craig , Olson Tim
Published: May 2023

For high performance computing, it is desirable to disintegrate the cache memory from the monolithic SoC

and reintegrate it through heterogenous integration technologies. Relocating the cache out of the monolithic

SoC leads to the reduction of the advanced silicon die size leading to higher yield and lower cost. In this

study, we evaluate ways to bridge the gap between high-end 3D silicon interconnect solutions and low-end

substrate solutions with Deca’s molded M-Series™ embedded cache fan-out solutions. Deca’s M-Series Chips

First Face up FOWLP planarized structure is an ideal platform to build an embedded interposer for the

heterogenous integration of the processor chiplets, cache memory, and deep trench capacitors. Deca’s

Adaptive Patterning® allows for scaling to high density interconnect between the processor chiplet and the

cache memory. Three different configurations of the embedded cache interposer are considered. The

vertically stacked face-to-face configurations minimize the interconnect length between the processor and

the cache, while the lateral configuration provides a copper to copper build up interconnect between the

chiplet and cache enabling further scaling down of the interconnect pitch. Both configurations have their

specific benefits and disadvantages which are described in detail in this work.
Fabrication of Panel-Level Glass Substrates with Complete Design Freedom using LIDE
Authors: Santos Rafael , Anspach Nils , Ambrosius Norbert , Schmidt Stephan , Ostholt Roman
Published: May 2023

In this work, we present examples of highly reproducible, accurate and extremely cost-effective wafer- and

panel-level fabrication of glass interposers, free of any process-dependent design limitations where any

distribution and density of Through-Glass Vias (TGV) with any cross-section geometries and aspect-ratios,

is possible.

Glass has recently garnered significant interest for its many applications in the semiconductor packaging

industry, particularly as a core substrate material for interposer applications. Glass has a unique set of

material properties with great relevance for this industry, such as very high electrical resistivity, low loss

tangent and low dielectric constant. Glass also exhibits low warpage due to its relatively low Young‘s

Modulus while still being compatible with Silicon in terms of CTE and, when processed using a technology

that doesn’t induce the generation of any defects such as microcracks or thermally-induced stress, it is

highly reliable during processing and operation. Laser Induced Deep Etching (LIDE®) technology is a

2.5D glass processing technology with complete design freedom purposedly developed for cost-effective,

high-volume fabrication of defect-free glass components.

Despite its many advantages as an interposer material in relation to Si, its application has been hindered by

the lack of reliable, precise, and cost-effective processing technologies. LIDE® consists of a two-step

process: i) a very fast maskless and direct-write laser process induces subtle and very localized

modification in the glass substrate, requiring a single laser pulse to modify the whole glass thickness; and

1. ii) a wet-etching process done in batch, where the whole glass substrate is subjected to the action of an

etchant and where the removal of glass occurs at an accelerated rate in the laser-modified regions. This

process flow allows LIDE to fabricate several thousands of TGV per second, completely free of any

defects, with a sub-micron point-to-point accuracy and ± 5 µm accuracy (cumulative) across a 510 mm x

515 mm glass panel (Cp > 1.33), in any glass type, with aspect-ratios from 1:10 to 1:50 (diameter:depth).
Study on CPI behaviors of X Dimension Fan-Out Integration (XDFOI) packages
Authors: Chen Haijie , Hu Zhen , Wang Chen , He Ming , Xie Jielei , Lin Yaojian , Lee Choon Heung
Published: May 2023

XDFOITM (X Dimension Fan Out Integration) is a package family designed for fan out packages

and heterogeneous integration, as XDFOI offers great flexibility to let single die or multi-functional

chips, such as logic, memory, power management, RF and passive components, to be packaged by

technology evolutions. Based on the approaches of “chip first” and “chip last” processes, XDFOI is

designed with the high density I/O and multi-layer metals, polyimide and encapsulation materials like

ABF, underfill or molding compound. Various materials applied in the full process flow brings lots of

combination of CTE (coefficient of thermal expansion) and meanwhile the CTE mismatch may

generate stress on the dielectric materials to influence the performance requirements.

It is widely known that manufacturing procedures of heterogeneous integration make the

boundaries of foundry backend process of line (BEOL) and bumping process fuzzy. In this paper, three

package members in XDFOI family are introduced and the respective process flows are illustrated

detailed in order to exhibit the differences between the solutions. Finite-element analysis is integrated

along with package building process to predict the stress performances. The simulation results of

XDFOI packages divided by packages provide a guideline for estimating maximum stress on the

dielectric materials. In order to provide proper guideline to chip packages, data from theoretical

calculation are collected, analyzed and merged into design rules for further process optimization and

new product introduction. It is considered that the study can greatly improve the overall innovation

level and process capabilities.
Thermal Performance of Liquid Metal Pastes Containing low Content of Metal Particles for Thermal Interface Materials in IC Module Electronics
Authors: Fan Guangyu , Kurish Jeff , Tagliaferri Sofia , Green Kyle , LaBarbera Christine
Published: May 2023

In recent years, considerable attention has been paid to gallium-based liquid metal alloys

in their use as thermal interface materials for GPU, APU, and HPC in PC and super

computers due to its considerably high thermal conductivity and low contact thermal

resistance. Gallium-based Liquid metal paste containing low content of metal particles

(LMP-MPs) to enhance thermal performance and controllable BLT of the prepared liquid

metal composites for thermal interface materials (TIMs) prepared by in-situ introducing

gallium oxide into the liquid metal alloys will be reported in our recent research. In this

paper, we will report effect of the composition, particle size/types, and bond line

thickness on thermal properties of the LMP-MPs. Thermal properties of the LMP-MPs

were measured at 50o

C using a thermal tester, TIMA5, based on ASTM-D5470 test

methodology. It was found in the present study that the composition and types of metal

particles, and BLT have significant influence on thermal conductivity, and the

conductivity values increase with an increase of the content of metal particles and BLT.

However, thermal resistance varies with the change of composition and BLT of LMP-MPs. Scanning electron microscope (SEM) was used to characterize microstructure of

LMP-MPs with different metal particles and sizes. Micrographic morphology of the

LMPs-MPs shows continuous frame structure observed with SEM, which could keep

liquid metals from spreading out and stabilize the phase. We eventually found the LMP-MPs have the better wetting and adhesion properties on bare Cu, glass and bare Si surface

than liquid metal alloys that endows good printability to the LMP-MPs. Continuous

monitoring of thermal resistance of LMP-MPs at 45o

C and 89o

C using a house-made

thermal tester shows stable thermal resistance after a few months, which indicates LMP-MPs have excellent thermal reliability in ambient atmosphere.
Smaller than MLCC: CCW (Ceramic Capacitor Wire)
Authors: Park Soojae , Lee Jonghyun , Cho Chulhyung , Kim Namhoon , Kim Jaehoon , Park Soomoon
Published: May 2023

The world’s smallest discrete capacitor was invented in a cylindrical form factor for high-frequency power

delivery, contrary to a planar capacitor such as MLCC. A dielectric layer of Al2O3 (5~50nm ALD) was deposited on

conventional Au metal wires (18~40µm), and subsequently, a 2nd electrode metal (0.5~1µm) was sputtered on the Al2O3

layer. Advanced wire bonding was used to assemble CCW to PCB pads for electrical connections required capacitors.

Electrical simulations were used to characterize CCW in terms of electrical performances. The capacitance

measurements were compared between CCW & MLCC in conjunction with electrical simulation at high frequencies

for RF & HPC applications. CCW can also be embedded into PCB and integrated into package chips.
Printed Microstrip Interconnects for Improved RF Performance in mm-Wave Packaging
Authors: Christenson Kurt , Bourassa Justin , Hamre John , Dean Mike
Published: May 2023

Printed microstrip interconnects are gaining attention as designers seek a more-compact, lower-loss scheme

to replace wire bonds. Aerosol Jet® printed interconnects have the potential to lower insertion losses by

creating conductors with arbitrary geometries and zero loop height. Printed dielectric and conductor materials

typically have inferior electrical properties compared to bulk-deposited materials. There is a question whether

these properties will produce unacceptable S21 losses in printed interconnects. This work presents

calculations of the effect of the printed material’s properties on S21.

HFSS modeling from 0.1 to 100 GHz was conducted on two representative interconnect structures. A

trench in an RF substrate filled with dielectric and a dielectric ramp from a substrate up to a GaAs die. The

microstrip (or transmission) line over a filled trench represents the filled region around a die that sits down

in a “pocket” in the dielectric and contacts the ground plane. Conductors modeled include a pure copper

reference along with conductors with four and ten times the resistivity of bulk silver. The dielectric

constant of the insulator varied from 2.8 to 4.3 and the loss tangent varied from 0.004 to 0.04. For

simplicity, an unpatterned GaAs die was used in place of an RF IC.

The work focuses on estimating any degradations in performance of an ideal reference circuit caused by the

material properties of real printed materials. Also presented are the dielectric properties of our current

materials along with properties of candidate materials that have better thermo-mechanical properties

(shrink, CTE, Tg…).
Simple Solution to Estimating and Predicting Transient Current in Small Signal AC Circuits
Authors: Ganescu, PhD Virgil C.
Published: May 2023

Transient current through a small signal RLC series ac circuit is investigated. The current is calculated analytically from the

governing differential equation of the circuit. Furthermore, the analytical solution is compared and validated, for the steady state,

against the numerical solution generated by Multisim. Lastly, results and discussions are focused on the transient analysis (t —>

0s), when currents peak.
Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types
Authors: Farris Glenn
Published: May 2023

The semiconductor industry is driving to enable high volume integration of disparate die types via

Heterogeneous Integration. These die can come from a range of wafer sizes fabricated in different

technology nodes. This emerging package type creates new challenges regarding assembly efficiency and

yield. Traditionally, flip-chip assembly process flows have utilized a single placement tool for the

placement of the single die type onto the target substrate. For applications with multiple die types, a series

of placement tools have been configured in a production line, with each tool dedicated to the placement of a

specific die type. This paper and presentation explore the implications of this type of solution in the era of

Heterogeneous Integration. Impacts on product yield, throughput, manufacturing efficiency, and overall

cost of assembly will be explored for a broad range of Heterogeneous Integration die configurations. Based

on a sensitivity analysis for the range of die types expected in these applications, a novel approach to

optimization of overall assembly economics will be proposed. Appropriateness of this novel approach will

be explored for a range of packaging solutions, including Flip-Chip, 2.5D, 3D, and Fan-Out.
Inspection Solution for 2μm RDL from Wafer-Level to Panel-Level Fan-out Process
Authors: Lin Leon , Liu Anderson , Chen Jay , Wu Maruko , Kim Cheolkyu , Liu Zhuan
Published: May 2023

In the advanced packaging industry, both fan-out wafer-level packaging (FOWLP) and fan-out panel-level

packaging (FOPLP) have grown quickly in recent years since they are compatible with largescale, low-cost

manufacturing and are key enablers for ultra-thin and high-density packages. However, the

commercialization of the fan-out process continues to face technical challenges with the rapid adoption of

finer pitch and width of the Cu redistribution layer (RDL) in die-first or die-last integration approaches. AOI

has been widely used in the advanced packaging industry as a major tool for defect inspection during various

process steps. The conventional bright field and dark field imaging techniques suffer from a high nuisance

rate for RDL inspection; in many cases, the RDL metal grain size could be larger than the defect of interest,

and the interferences from underneath the pattern, such as bottom RDL layers or molding compounds, can

increase the difficulties of defect detection. In this paper, we present Onto Innovation’s innovative

fluorescence technology to enhance contrasts between organic material, such as polyimide, or photoresists

and metals that enable fine-pitch RDL inspection with increased accuracy by eliminating nuisance defects.

By using powerful fluorescence technology, in conjunction with higher resolution, high-definition inspection

(HDI) technology, fine-pitch RDL defect inspections on both wafer-level and panel-level packaging were

studied and shown to enable accelerated development cycles in the R&D stage, as well enable rapid yield

enhancements in the HVM environment.
Influence of Rigid Carrier Substrate and its Release Layer on Warpage of Fan-out chip last WLPs & PLPs
Authors: Matsuura Yoshinori , Yoshida Tatsuya , Komiya Yukiko , Nakamura Toshimi , Yanai Takenori , Okuyama Kazuhiro , Kitabatake Yukiko , Ishii Rintaro , Hayashi Katsuyuki , Kubota Takashi , Fujii Joji
Published: May 2023

In recent years, the need for ultra-high density chip packaging devices and heterogenous integration

devices require strategic placement of various components for high-performance computing (HPC), artificial

intelligence (AI), etc. The fan-out chip last process with redistribution layer (RDL) first is expected as a

solution to assemble these modules in advanced packages, which is essential for avoiding the risk of known

good die (KGD) loss.

During the assembly of the fan-out chip last WLP, elimination or minimizing warpage is an inherent

challenge. It is caused by a thermal mismatch between various organic-inorganic – metallic – non-metallic –

composite materials used in different layers of the package. If not controlled, then warpage from stresses

induces alignment mismatch impacting package yield loss and reliability related issues. Warpage is

minimized by using a rigid carrier substrate to build the RDL layers. The selection of this rigid carrier and

its release layer influence the package warpage during the fan-out chip last WLP fabrication process.

This paper focuses on the influence of rigid carrier substrate and its release layer on the warpage of fan-out chip last WLPs. Further, a solution towards controlling warpage has been provided using a novel material

set referred to as HRDP® (High Resolution Debondable Panel). This is a drop-in approach compatible with

the existing assembly flow. One of the important features of the HRDP® carrier is that it is offered in various

dimensions and thicknesses. The HRDP® carrier is available for round wafers as well as for

square/rectangular panel shapes in glass or silicon substrates to match the coefficient of thermal expansion

(CTE) of the metal RDL, dielectric material, and Epoxy molding compound (EMC). This contributes to

optimizing CTE related interfacial stresses and minimizes assembly warpage. Another key attribute of the

HRDP® is its ease of debonding. Contrary to conventional debonding/release polymer layers, the HRDP®

structure is composed of 100% inorganic material. It improves processing capability during RDL

manufacturing, showing better chemical resistance and heat resistance than alternate technologies such as

laser lift-off (LLO) type carrier
An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging
Authors: Bahena Joel A. , Tyler Phillip , Taddei John , Sankarapandian Muthumanickam , Prudhomme Jamie , Pillai Karthikeyan , Said Abdullahi , Carr Christopher , Goldfarb Dario , Waskiewicz Chris , Chen Qianwen
Published: May 2023

With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a

critical processing step. As the process has matured, significant efforts have been made for optimization in

terms of both production and cost. This is especially true for photoresist stripping, since thick photoresists

are needed to pattern high aspect ratios and must be removed in subsequent steps to expose underlying metal

films. In this study, the removal of a thick negative tone photoresist with solder pillar plated wafers were

investigated using a dimethyl sulfoxide blend with a quaternary ammonium hydroxide. Emphasis was placed

on exploring the feasibility of an extended bath life beyond 7 days. Coupon level beaker tests were used to

provide insight into the swelling and dissolution mechanisms with fresh and aged chemistry. Additionally,

several chemistries were compared to examine the effect of the quaternary ammonium hydroxide. Based on

these findings, chemical aging studies were performed on 300 mm wafers using a highly customizable single

wafer processing tool that combined soaking and a high-pressure spray processing to potentially prolong the

bath age even further. In addition to stripping efficiency at extended bath life, the compatibly with pillar

structures and seed layers is investigated. Results from the study highlight potential methods to extend bath

life while maintaining photoresist stripping efficiency.
Development of a Photopolymer-Based Dielectric Nanocomposite for High Resolution Direct-Write Processes
Authors: Piro Yuri , Aerias Christopher , Luce Andrew , Lamport Emily , Li Yibo , Trulli Susan , Akyurtlu Alkim
Published: May 2023

A UV curable dielectric ink composition, which enables adaptable and high-resolution direct ink writing, is

presented. The UV curable dielectric ink composition is designed using non-hazardous, low cost,

commercially available ingredients. The ink manufacturing procedure was devised to require only

fundamental lab equipment, without the need for complex reaction conditions or harmful processes. The UV

dielectric ink composition was engineered to meet a range of direct ink writing application specific needs.

These needs include a tailored rheology, cured film rigidity, dielectric performance, and adhesive ability. The

versatility of this ink composition is demonstrated through the fabrication of dielectric bridges for printed

coplanar waveguides, bare die chip integration, and interconnects between printed circuit board regions.
Advancements, Versatility, and Flexibility of Dual-Layer Material System for Advanced Packaging Applications
Authors: Jones Andy , Bai Dongshun , Koch Matt , Prenger Luke
Published: May 2023

Integrated circuits (IC) have seen a major shift in development within the past 10-20 years with traditional

lithography methods showing a drastic increase in development time for more advanced nodes, as well as an

exponential increase in cost to achieve the same performance gains as before. The increase in cost and the

decline in development in lithography have resulted in looking at advanced packaging technologies to

achieve the same performance gains by changing the way IC design is approached. The look towards

advanced packaging technologies for the future in terms of increasing performance for a substantially lower

cost has resulted in considering the IC as a system of components working intertwined with each other rather

than as individual components. This shift in mindset has resulted in technologies such as system in package

(SiP), package on package (PoP), and fan-out wafer-level packaging (FOWLP). One advanced packaging

technology that plays a critical role enabling these aforementioned technologies is temporary bond and

debond (TB/DB). TB/DB’s crucial role in advanced packaging is due to the enablement of backside

processing such as wafer thinning, bumping of the wafer, die stacking, and chemical vapor

deposition/physical vapor deposition (CVD/PVD)–type processes by the use of a support carrier wafer. The

support carrier wafer also allows for the use of highly warp-prone materials such as epoxy mold compound

(EMC), which are critical in FOWLP applications, by reducing the overall warpage of the entire wafer stack.

To utilize the support carrier wafer, a robust material solution is required to allow for the wafers to be bonded

together and subsequently released after backside processing by one of the primary separation methods of

thermal slide, mechanical, or laser debond.

Brewer Science has designed and developed a dual-layer temporary bonding system. This system consists

of two materials, a thermoplastic layer that is typically coated on the device, and a thermoset layer which is

typically coated on the carrier. The materials developed for the dual-layer system demonstrate very good

performance in very high temperature applications, EMC wafer handling, and device thinning to sub-20 µm.

In this paper, we will summarize their capabilities and introduce how adhesion between the two temporary

layers can be adjusted by material design. We will also cover a new feature of the thermoset layer that can

be patterned to allow for the use of a patterned bonding material for TB/DB-type applications.
A Novel Printed Circuit Board Laminate for High Frequency Electronics
Authors: Lin James , Owen Geraint , Orsley Tim
Published: May 2023

A novel PCB material that is advantaged at the 10-100+ GHz range has been developed. It consists of a 3

layer laminate, nominally with a total thickness of 140 microns, and individual laminates can be stacked to

make multilayer boards. The outer two layers of the laminate consist of the polymer Topas, 50 microns

thick and the middle layer is Corning’s ribbon alumina, 40 microns thick. For brevity, the laminate is

called “TAT”.

The permittivities of the Topas and alumina are 2.5 and 10 respectively, and that of the 50/40/50 TAT

laminate is 3.2 in a direction transverse to the plane of the laminate. The individual loss tangents are about

0.0002, and the loss tangent of the TAT laminate has about the same value. Thus, TAT has significantly

lower loss with a lower effective permittivity than other PCB materials currently available. These

dielectric properties have been measured experimentally at 10 and 15 GHz. The permittivity and loss

tangents can also be predicted accurately using extremely simple analytical formulae. This makes

predicting the properties of TAT structures with different dimensions very easy. A TAT strip line has been

modeled and found to have an effective permittivity of 2.3.

The machining of TAT is somewhat incompatible with conventional PCB shop practice. However, laser

drilling and cutting are perfectly practicable. In-house processes have been successfully developed, and an

external vendor has also developed these capabilities. Copper sheet adheres strongly to the TAT, and the

conductivity of the resulting traces is high. Boards for a 77 GHz radar demonstrate the manufacturability

of TAT.

Mechanical testing of TAT has been carried out, and the measured flexural modulus and stress at failure

compare well with calculations. Environmental tests at 80 °C and 80% humidity indicate that TAT is quite

robust. Moreover, it is quite possible that TAT itself may satisfy the UL94 criteria, since the alumina may

act as a flame retardant. The feasibility of loading Topas with ceramic or fluoropolymer powders to reduce

flammability has been investigated, and it has been found that the addition of these powders causes

negligible dielectric loss.

In summary, laminates of this type are plausible extreme low loss candidates for PCBs for very advanced

applications such as 5G and 6G devices.
Maskless direct write lithography for 3D wafer-level-system-integration
Authors: Windrich Frank , Preuß Sven , Jehle Achim
Published: May 2023

This publication presents lithography results for 3D wafer-level system integration applications using a

reticle free maskless lithography system VPG+ 400 from Heidelberg Instruments. The focus is on high

density Cu redistribution layer (RDL) formation with <2µm L/S used in polymer RDL stacks, overlay

accuracy determination better than ±150nm and hybrid bond interconnect formation for 2µm interconnects,

all processed on 300mm wafer size substrates.
Electromigration Risk Assessment and Circuit Optimization using Innovative Multiphysics Modeling
Authors: Cai Chongyang , Yang Zhi , Li Yuan , Jain Padam , Kang Terry , Mellachervu Krishna
Published: May 2023

With smaller and denser transistors, the physical flow of electrons may inhibit the performance of the device

over time by forming voids and cracks at interconnects due to Electro-Migration (EM). Circuit designs that

fail to meet EM specifications may lead to catastrophic failures and SI/PI performance degradation. One way

of mitigating EM is to use multiple vias between layers of copper traces to reduce the current crowding effect.

However, the quantities of vias may affect the current density and current redistribution inside critical joints.

Current studies mainly focus on predicting the EM time-to-failure (TTF) based on the empirical Black’s

equation. However, this method may not give enough insights about void formation and crack propagation

and reflects the current redistribution that could impact the TTF. In this study, we compared the EM lifetime

of Ball Grid Array (BGA) test vehicles with different structural designs and developed a methodology to

consider the diffusion of atoms in solder joints based on Multiphysics field migration to study the current

redistribution influence of vias. Moreover, crack propagation was also simulated to understand the failure

mechanism. BGA traces without vias and with 8 vias are stressed under 5A, 7A, and 9A at 150C to compare

the EM performance. Moreover, each test structure is manufactured with two different surface finishes: A

and B. Based on the experimental results, Finite Element Analysis (FEA) simulations based on Atom Flux

Divergence (AFD) were performed to compare with the experiment results. It was found that the current

crowding effect could be significantly reduced by 8 vias compared to daisy chained traces. The study shows

better EM resistance with 8 and 4 vias than no-via traces and helps predict the EM life of different structures

to provide guidance for design optimization
On Excess CO2 within a Hermetically Sealed 14-Pin Butterfly Package: Solubility of CO2 within Fluorocarbon Liquids
Authors: De Luna Mark M. , Uramoto Todd
Published: May 2023

In this paper, we examine the presence of excess CO2 found within a hermetically sealed 14-pin butterfly

package. Excess CO2 within a hermetically sealed package can suggest that the internal structures of the

package have degraded significantly over the lifetime of the package. The level of CO2 discovered within the

butterfly package was inconsistent with the controlled sealing gas environmental composition, and the gas

composition of concurrently sealed packages. A literature review of industry technical papers and academic

studies show that fluorocarbon liquids preferentially absorb CO2 at levels 4-5 times greater than other gasses

such as oxygen and nitrogen. Previous experimental and computational methods found that fluorocarbon

liquids can absorb CO2 at levels of 1.5-1.6 mol%, which is greater than the calculated maximum amount of

absorbed CO2 (0.91 mol%) found within the butterfly package. The Internal Gas Analysis (IGA) of the

butterfly package confirmed that it is highly likely that when butterfly package ingested the fluorocarbon

liquid, the CO2 was absorbed in solution and thus ingested into the device. Given that the butterfly package

was initially filled with 12% ppmv of helium and it retained the helium at a significant level, the phenomenon

of a one-way leaker preserved the evidence of CO2 absorbed in the fluorocarbon liquid.
Simulation and Experimental Study on Edge Bonding Shape for Reliable BGA Packages
Authors: Kato Yasuhiko , Hamagami Hiroyuki , Shibata Tomoaki , Seki Kohei , Sato Ryota
Published: May 2023

In order to ensure thermal reliability including temperature cycling, semiconductor chips and packages

mounted on a BGA substrate need a reinforced structure with adhesive resin. In this study, the relationship

between reliability and the applied shape of the edge bond (EB) material was verified based on thermal stress

simulation and actual experimental results. In consequence, the test vehicle with the cross-sectional area of

0.62 mm2 showed higher reliability than the one of 1.04 mm2

, and maintained the electrical continuity over

3100 cycles. This result showed that there was an optimal cross-sectional area of EB material to obtain high

reliability.
A high-uniformity, high-purity copper pillar ECP process with limited acid concentration
Authors: Ye Pingping , Letize Adam , Han Jianwen , Braye Stephan , Kuppersmith Ashley , Whitten Kyle , Richardson Thomas , Najjar Elie
Published: May 2023

The requirements for wafer-level packaging (WLP) are becoming more and more stringent both from a

sustainability perspective and process performance. For instance, there is a demand for continuous process

improvement for within die uniformity (WID) and operating in a low acid environment for copper pillar

plating. Antagonistic these requests are; however, we must devise novel ECP techniques and additive designs

to meet such ambitious targets. The additives consist of an accelerator, suppressor, and leveler. The

systematic use of Linear Sweep Voltammetry (LSV) aided the study of the electrochemical response to screen

the additives and determine the Wagner number (Wa) in the current density region of interest. In addition,

the rigorous use of the Design of Experiment (DOE) enabled us to determine the concentrations for

combining this new leveler and suppressor with the accelerator. Owing to designing the right leveler and

suppressor, we controlled the free acid concentration at 10% (100 g/L) while maintaining the WID below

2.5% and controlling the within-feature (WIF) less than 1µm (~2.0%), using a deposition rate of

approximately 2.0 µm/min, to various wafer patterns with various aspect ratios and layouts. Lastly, the

resulting film properties are as crucial as ECP performance. SIMS studies support a deficient level of

inclusion in the copper film with a total impurity of 3.1 ppm, including C, O, N, S, and Cl. Therefore, when

studied with a solder cap, the Kirkendall void performance was outstanding based on minimal voids post

10X reflow cycles and high-temperature storage. The shear stress test measuring the bonding between the

copper and its pad on the wafer is 18.4 gf/mil2.
Board Level Reliability of Flipchip Package
Authors: Lakhera Nishant , Benson Mollie , Mawer Andrew
Published: May 2023

In the world of electronic materials, solder is a critical material that plays an important role in the first level

(silicon to package substrate) and second level (package to printed circuit board) interconnection. As a

joining material in electronic assemblies, solder provides electrical and mechanical connections. The

increasing need for reliable electronic devices for harsh environment triggers the need for reliable solder

joints. This study focuses on reliability of second level interconnections between package and printed

circuit boards.

Board level temperature cycling and mechanical drop performance of a 15 mm x 15 mm FCBGA test

vehicle were evaluated with different package construction (lidded vs non-lidded), and BGA solder alloys

(SA1, SA2, and SA3). Daisy chain packages were assembled on 1.0 mm thick PCB. Mounted units were

thermally cycled between from -40C to 125C. Additional samples were evaluated in mechanical drop test

conditions following JEDEC standards. Results showed that packages with SA2, and SA3 BGA had

significantly higher board-level thermal cycling life compared to SA1. The best drop performance was

achieved with SA1 solder. The performance trend among different solder alloys was found to be similar

between lidded vs non lidded package. However, lidded package showed improved board-level reliability

performance compared to a non-lidded package.
Die-embedded packaging using Corning® multi-layered glass
Authors: Kim Choon-Kon , Xiao Yu , Yook Jong-Min , Chang Hyun-Je , Moon Hyung-Soo
Published: May 2023

Die-embedded (DE) packaging technologies in recent years have ventured into advanced packaging

structures, such as fan-out wafer level packages (FOWLPs) or package-on-packages (PoPs). They offer

higher density at lower costs, despite many challenges, such as the die-shift and warpage problems often

observed during the molding process, caused by the high shrinkage and high coefficients of thermal

expansion (CTEs) of the molding materials. This in turn makes it difficult to accurately mount the high-density fine-pitch bumps and adversely affects the overall yield, especially in processes using large-size

substrates.

Glass, known for its superior dimensional and thermal stability and its low or tunable CTEs, can be

advantageous in reducing die-shift and warpages as opposed to other alternative material solutions for the

molding process. In this paper, we propose a packaging solution based on a glass substrate incorporating a

plurality of precisely dimensioned cavities, with a chip positioned in each cavity to prevent them from shifting

during processing. Corning® Adaptive Formed Glass (AFG), a laminate glass with a unique clad/core/clad

structure, allows for effectively forming cavities with high dimensional precision and positional accuracies

as well as surface flatness through a wet etch process.

Using a 0.5mm thick laminate Corning® AFG glass, we successfully designed and fabricated three types of

DE packages with lab scale tools at Korea Electronics Technology Institute (KETI): single- and double-sided

DE packages, and package-on-packages (POPs). High etching selectivity over 20:1, which was achieved by

carefully designing the core and clad glass compositions, enabled a wet-etch cavity forming process with

accurate cavity depths and flat bottom surfaces (< ± 2.5μm) with relative ease. A double-sided DE package

with a total thickness of 600μm was fabricated with two 125μm-thick IC chips, one embedded on each side

of the substrate, and connected by metallized through glass vias (TGVs). A POP measured at 5.1×5.1×1.27

mm3 was also successfully demonstrated by using two built-in double-sided DE packages joined by flip-chip

bonding, equivalent to stacking four layers of conventional single-sided DE packages. The double-sided DE

packages and POPs presented in this paper are believed to be the world’s first demonstration on glass. The

work also manifests the immense potential of Corning® AFG glass in enabling higher density IC packaging

and large-size panel-level (or wafer-level) packaging.
Glass Substrate for Co-Packaged Optics
Authors: Brusberg Lars , Zakharian Aramais R. , Grenier Jason R. , Paddock Barry J. , Levesque Daniel W. , Sutton Cliff G. , Force Robin M. , Yeary Lucas W. , Bellman Robert A. , Terwilliger Chad C. , Johnson Betsy J.
Published: May 2023

Co-packaged optics leads to significant power reduction by placing the electronic and photonic chiplets in a

single package. An integrated electro-optical substrate made of glass with optical waveguides, through vias

and electrical redistribution layers inside a single-sided cavity enables fine-line electrical routing and low-cost assembly. Existing glass and thin film technologies were evaluated and combined into a single process

stream including photonic assembly. Photonic chips with silicon nitride waveguides were optically coupled

to integrated low-loss (<0.1 dB/cm) glass waveguides with minimum loss of 0.65 dB achieved by fiducial

alignment and pick-and-place assembly.
Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors
Authors: Sharma Gaurav , Lakhera Nishant , Shantaram Sandeep , Huang Willy
Published: May 2023

Automobiles have witnessed rapid proliferation of infotainment, driver assistance and autonomous driving

features which have led to significant increase in semiconductor content per car. However, this has also

required increased integration of device functionality to meet the new automotive requirements for in-vehicle

networking, autonomous driving, infotainment, and sensor integration. Advance technology/packages are

needed to provide ideal solutions for automotive grade reliability, high electrical performance, and multi-function integration for automotive application processors. To address these requirements, innovative

packages including Flip Chip Ball Grid Array (FCBGA) are the potential solutions. In this study FCBGA

packages are developed for automotive processor application and qualified for AEC2 qualification tier. To

achieve higher performance and reliability, different package substrate materials such as core dielectric and

build-up dielectric were evaluated. Mechanical modelling and simulation of package reliability and influence

of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E) and glass

transition temperature (Tg) was used to provide guidance for the selection of substrate and assembly

materials. Developed packages met all the product performance requirements and passed package qual

conditions of high temperature storage life (150°C, 500 hours), temperature cycling (-55 °C to 125 °C, 1000

cycles), temperature humidity bias (85 °C, 85% RH, 1000 hours) and board level temperature cycling (-40

°C to 125 °C, 1000 cycles).
Impact of FCBGA substrate stack-up on BLR performance
Authors: Williamson Jaimal , Suzuki Yutaka , Eller Ron
Published: May 2023

Board level reliability (BLR) temperature cycling is a metric for FCBGA field performance, where it is

imperative to understand process variation holistically covering both substrate and / or assembly

manufacturing process and its impact to product margin. This study focuses on technical reasoning a common

FCBGA design manufactured with an identical substrate material set (i.e. core, dielectric, solder mask),

assembly bill-of-materials (i.e. underfill, lid, etc.) and assembly site demonstrated different cycles to first

failure during BLR testing. Although results far exceeded JESD22-A104 condition G requirements, BLR

performance based on identical substrate designs (manufactured at different points in time) proved TV1 (test

vehicle 1) performed ~2x better than its TV2 (test vehicle 2) counterpart. To elucidate the primary factor of

the disparity in BLR performance, supplier feedback as well as a detailed package construction analysis

ensued to compare build-up substrate layer thickness dimensions between TV1 and TV2. Discovery

demonstrated a slightly larger volume of a specific layer in the build-up stack within TV2 that generated a

higher degree of out-of-plane displacement as compared to TV1. Reproducing the cycles to first failure with

the superior TV1 device via the TV1a and impact of substrate warpage was investigated as a factor in the

BLR findings driving root cause.
High Robustness of Coated-Ag Wire Bonding
Authors: Murali Sarangapani , Evonne Lim Yee Weon , Mariyappan Dhayalan , Wan Lo Miew , Joanne Chong Mei Hoe , Kumar Balasubramanian Senthil , Sungsig SS Kang
Published: May 2023

Formation of free air ball (FAB) within the range of certain processing parameters leads to

excellent bondability (distributed intermetallic coverage (IMC) at the center and periphery

of the bonded ball interface, bonded ball concentricity, etc.) on bonding to aluminum (Al)

bond pad and Au/Ag plated surfaces. The wire revealed zero stoppage and 0.8M bond

touchdowns when tested under laboratory conditions. Thermal aging of bonded interface

showed absence of Kirkendall voids until 192h at 250°C where Al diffuses into Ag bonded

ball up to a depth of 5.3µm, consuming the complete Al bond pad and thus transforming

into silver-aluminide containing 5 to 12wt% of Al and rest silver (Ag). Traces of coated

gold (Au) and alloyed palladium (Pd) are noticed at the bond interface.
Digital Twins and Smart Manufacturing for Wire Bonding
Authors: Milton Basil , Cathcart Ray , Kwon Odal , Shusharin Pavel , Qin Ivy
Published: May 2023

Low cost, excellent flexibility, and high yield rate have long been the drivers of wire bonding technology.

In the past decade, advancements in wire bonding technology have significantly improved wire bond

reliability and strengthened the adoption of the technology while maintaining its competitive advantage.

Digital twins of wire bonding can now simulate and optimize 3D wire loop shapes to facilitate design-for-manufacturing (DFM), increase design flexibility, reduce product development time, and improve overall

package yields. In particular, the benefits of digital twins have been realized in system-in-package (SiPs),

large stack-die memory applications, and complex high pin count packages with multiple looping tiers. With

increasing package complexity and modular package configurations, the need for smarter functionalities is

imperative.

More recently, technological developments in wire bonding have been targeted toward furthering design,

quality, and time-to-market (TTM) from an Industry 4.0 smart manufacturing perspective. In this paper, we

will introduce new digital twin simulation techniques to detect potential interference between wire bond

capillaries and wire loops, various dies, passive components, and other structures within the package. These

advanced capabilities are demonstrated on a real application and shown to help in the detection of design

issues early in the product cycle and aid in the selection of capillary, wire, as well as optimization of the

package layout. All these factors significantly improve the overall TTM of semiconductor packages.

Technologies that provide improvements via autonomous monitoring and optimization are also strongly

desired. We will also explore new on-bonder process monitoring capabilities to detect wire sway such that

wire shorts and resultant yield losses can be minimized. Additionally, vision-guided enhancements to on-bonder loop height monitoring capabilities will also be discussed. These new advancements significantly

improve production quality and yield, paving the way for smarter factories
Metal Oxide Removal Using Atmospheric Pressure Plasma Technology for Electronic Applications
Authors: Pappas Daphne , Sy Andrew , Robinson Ryan , Burke Richard
Published: May 2023

Copper is one of the most commonly used metals in the electronics industry. For example, it is extensively

used as a lead frame material in integrated circuit packaging due to its superior thermal and electrical

conductivity and low production cost. However, the formation of a native oxide on the surface along with

the presence of organic contaminants hinder wire bond strength.

The work presented here will focus on a novel approach to remove copper and other oxide layers using a

nitrogen/hydrogen (95%/5%) gas plasma chemistry that does not require a vacuum environment. The

processes are run at temperature conditions lower than 200°C, and at speed up to 150 mm/s which make the

technology attractive for industrial upscaling. Results from the elemental analysis using scanning electron

microscopy (EDS-SEM) of the plasma-treated versus as-received copper surfaces will be presented. Also, a

brief analysis of the gas plasma-surface interactions, process parameters leading to oxide reduction of various

metals (Cu, Sn) and equipment details will be discussed. Aside from improving wire bond strength to lead

frames and pads, plasmas can be used to improve die attachment to various metal solder materials for flip

chip and other electronic applications.
Decrease on malaria clinical cases from 2017 to 2019 in Franceville, Southeast Gabon, Central Africa
Authors: Boundenga Larson , Bignoumba Michelle , Dibakou Serge-Ely , Mombo Landry E. , Moukagni-Mussadji Clauve J. , Wora Dorothé M. , Kassa-Kassa Fabrice , Bisseye Cyrille , Onanga Richard
Published: May 2023

Background: In Gabon, malaria remains a major public health problem. All malaria cases with axillary temperature ≥ 37.5°C with a parasites density ≥ 1200/μL are serious cases and must be treated as a medical emergency. Thus, early diagnosis is essential for successful treatment. Because of the impact of malaria on the population, the surveillance of malaria infections in hospitals is urgently needed. The aim of this study was to to assess of clinical cases of malaria in a private health structure in Franceville between 2017 and 2019.Methods: For that, we conducted a retrospective study using data on malaria cases recorded in a private medical analysis laboratory in Franceville, southeast Gabon. Malaria was diagnosed in this laboratory using a Rapid Diagnostic Test and confirmed by microscopic analysis. Results: Analysis of 2518 patient forms revealed an increase in malaria prevalence in Franceville between 2017-2019. The global clinical cases was 26.1% (658/2015). Children under 5 years (44.0%) and patients aged 5-14 years (40.1%) were more affected than patients aged ≥15 years (18.8%, P=0.0001). Malaria infection was also significantly dependent on season and gender. We observed at least three Plasmodium species and the predominant Plasmodium species was P. falciparum 80.0%, followed by P. ovale (19.5%) and P. malariae (17.8%). Conclusion: Our study showed that malaria remains a public health priority for the population of Franceville and that the prevalence of clinical cases of malaria at the laboratory decrease between 2017 and 2019. Our results highlight the need for strategies to control malaria in Franceville, adapted to epidemiological contexts and environmental constraint.