bluuebunny/crossref_metadata_2025 huggingface dataset:
Lithography Solutions in Novel High Frequency SiGe HBT Device
Authors: Wang Lei , Chen Fucheng , Su Bo , Liu Donghua , Qian Zhigang , Li Dunran , Meng Honglin , Guo Xiaobo , Ji Wei , Xiao Sheng'An
Published: March 2012

Advanced vertical NPN SiGe HBT device integrated in a CMOS technology are widly used in RF application such as LNA, PA, Mixer circuit. It can be fabricated by different architectures. HHNEC novel SiGe HBT device with non-EPI collector, borderless emitter and deep contact structures is one of them. It can offer scalable break down volatages, smaller device area and low manufactering cost. For SiGe HBT device, SiGe base, EW (emmitter window) and EP (Emitter poly) are most critical. The device performance is very sensitive to their CD, pattern fidelity and miss-alignment. On the other sides, SiGe film optical characteristics are very sensitive to its formulation process such as Ge concentration, thermal temperature, crystal lattice and so on. How to setup a robust base to emmiter loop is most important. In this paper, we will introduce our study result on 150G high frequency SiGe HBT device. The key design rule is comprable to sub 110nm design rule. Pure KrF process with maximum 0.82NA scanner tools is used. SiGe film impact to lithograhpy process is studied. New lithography and OPC solutoins are demostrated. The device sensitivity is aslo discussed with different solutions.
Single Wafer Wet Clean Challenges and Solution for 32nm
Authors: Toshima Takayuki , Nishikido Shouuichi , Yamasaka Miyako , Suni Kang
Published: March 2012

Until recently, many semiconductor companies had been using batch cleaning systems, regarding surface cleaning as wet process. However, the adoption of single wafer cleaning systems has become mainstream for cleaning processes because process control and flexibility are considered to be superior to that of batch systems. With single wafer systems we observed many reactions occurring on the wafer surface, which indicated the importance and difficulty of "wafer surface preparation" rather than simply "cleaning". From these observations we will report on the problems and challenges that have to be addressed as device geometry and die sizes continue to shrink.
BEOL Solvent Clean Process Study Using Fluoride Containing and Hydroxylamine Based Stripper
Authors: Luo Victor , Chang Jason , Shi Kevin , Zhan Willim , Zhang Jason , Peng Libbert , Zhang David W.
Published: March 2012

Solvent clean is a critical process for BEOL post Etch/Asher residue removal technology in AlCu device. Well-controlled metal galvanic corrosion, smooth metal sidewall, metal corrosion prevention before dielectric deposition and free polymer residue remaining are basic requirements of solvent clean process. In this paper, solvent clean process was studied in detail using one fluoride containing stripper and a typical hydroxylamine (HDA) based stripper by the pattern wafers of 0.15um and 0.18um node technology. Those key parameters, including residue removal performance, pattern profile, defectivity, resistivity and reliability, were evaluated. The data showed process optimization was necessary to achieve comparable performance from the stripper's intrinsic property points of view.
Effect of De-ionized Water Rinse in AlCu Line Post Etch Asher Residue Removal Process Using Fluoride Containing Stripper
Authors: Luo Victor , Chang Jason , Shi Kevin , Pang James , Ni Justin , Zhang Jason , Peng Libbert , Zhang David Wei
Published: March 2012

Compared with hydroxylamine-based stripper process, De-ionized water rinse becomes more critical due to intermediate solvent rinse elimination in the fluoride containing stripper process. In this paper, an integrated AlCu line photoresist strip de-ionized water rinse process utilizing a fluoride containing stripper is studied systematically in following aspects: a. CO2 bubble flow rate effects to metal galvanic corrosion, metal sidewall roughness and electromigration; b. de-ionized water rinse time effects to metal post-corrosion in wet box and metal electromigration; c. de-ionized water dump time effects to metal resistivity and electromigration. The data show de-ionized water rinse optimization along with CO2 bubble flow rate fine-tuning is essential to provide effective metal corrosion prevention, smooth metal sidewall and good electro-migration.
Gate Line Width Roughness Control for Advanced Logic Technologies
Authors: Meng Xiao-Ying , Huang Yi , He Qi-Yang , Han Qiu-Hua , Zhang Hai-Yang , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2012

As critical dimensions (CD) of semiconductor devices continue to be scaled down, line width roughness (LWR), the looming critical index, needs to be well-controlled within 8% of gate line CD for advanced logic technology nodes as ITRS states. In this contribution, we investigated the impacts of different patterning schemes, post Barc-open treatment, process parameters in Barc (bottom anti-reflective coating) and Darc (Dielectric Anti-Reflect Coating) open steps on the post-etch LWR of poly-silicon gate. Results demonstrate the amorphous carbon based hard-mask approach outperforms other two typical patterning schemes. Post Barc-open treatment emerges as a feasible method. The effect of process parameters in Barc-open step highly depends on the specific gas combination and patterning scheme. LWR is insensitive to process parameters in amorphous carbon etch step.
A Study of Dry Etching Process for Sigma-Shaped Si Recess
Authors: Sui Yun-Qi , Han Qiu-Hua , Wei Qing-Song , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2012

The fabrication of sigma-shaped silicon recess normally consists of dry etch process to shape the silicon trench and post etch treatment to form the sigma-shaped cavity within bulk silicon substrate. Here we are dedicated to the optimization of silicon recess dry etch process and its effect on the final sigma-shaped SiGe physical performance. Results show the isotropic ratio of horizontal over vertical direction could be doubled. This caters much larger process window for the desired strain introduction at the hetero-junction of SiGe/Si. Besides, the corresponding dry etching solutions are also disclosed from the point of view of tip depth adjustment and tip horizontal pull-back control. Both physical indexes could be independently controlled to deliver the required sigma-shaped Si recess trench.
Kinetics Investigation of RIE Lag Phenomenon by GaAs ICP Etching
Authors: Jiang Wenjing , Guan Baolu , Guo Xia , Ou Wen
Published: March 2012

In this paper, according to the relationships of the etch-rate with the FWs from 2μm to 100μm and of the etch-rate changes with etch-time for a particular FW, obtained by our experiments, a possible etching process model were proposed. When the etch-time was relatively short, it was the reaction limited process. With the etch-time going on, the fresh reactive gas was difficult to get through the etching trench to the fresh reaction interface, the etch-rate decreased, which was called the residual removing limited process. Our mathematic fitting results proved the above etching model and pointed that for the reaction limited process, the etch depth linearly increase with the etch time. While it got into the residual removing limited process, the etch-rate decreased.
The Critical Role of Dielectric Trench Etch in Enhancing Cu/low-k Dielectric Reliability for Advanced CMOS Technologies
Authors: Zhou Jun-Qing , Hu Min-Da , Zhang Hai-Yang , Wang Dong-Jiang , Wang Xin-Peng , Zhang Cheng-Long , Song Xing-Hua , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2012

In this work, we focused on the via-first approach and studied the impacts of trench etch on the electrical reliability of copper interconnects in terms of electro migration (EM), stress migration (SM), time dependent dielectric breakdown (TDDB) and chip package interaction (CPI). The huge micro-trench formed during trench etch could lead to the inter-layer voltage break-down, thus triggering CPI failure. Polymer and bombardment have been well managed in trench etch to solve this issue without degrading TDDB performance. Besides, post-etch treatment (PET) has been proven effective and critical in enhancing EM, SM and TDDB performance but it direct extension to M1 etch need reassess for the sake of trench etch recipe and substrate difference.
Novel Strip Process Strategy for Metal Gate
Authors: Diao Li , Ross Stephen , Elliston Bob , Hou Li , Kadavanich Andreas
Published: March 2012

A new strategy was developed for processes targeting production of devices using high-k metal gate (HKMG). An oxygen (O2)-containing reducing chemistry, such as O2/hydrogen (H2) or O2/ammonia (NH3), can be used for post-etch descum when sacrificial oxidation is required. Tungsten (W)/poly gate (post-etch) employed for 1x nanometer (nm) NAND was stripped with O2-containing reducing chemistries and polymer was removed completely with no critical dimension (CD) loss contributed by W oxidation. Breakdown fields of the gate oxide were at the same level with or without plasma exposure. Substrate silicon (Si) was repaired by sufficient oxidation. Similar processes worked well for advanced patterning film (APF) removal. Further tuning of such processes meet the requirements of challenging high-dose implant strip (HDIS). Residue-free results were obtained combined with a wet strip scheme. The results from this study provide a novel and cost-effective process package for advanced metal gate strip.
The Effect of Via Patterning Scheme and Metal Hard-Mask Based All-In-One Etch on Contact Resistance of Cu/low-k Interconnects
Authors: Hu Min-Da , Zhou Jun-Qing , Wang Dong-Jiang , Zhang Cheng-Long , Wang Xin-Peng , Zhang Hai-Yang , Mo Zhou , Shindo Toshihiko , Chen Li-Hung
Published: March 2012

The impact of via patterning scheme and all-in-one (AIO) etch on contact resistance (Rc) is extensively investigated in this contribution. The addressed tri-layer via patterning schemes consist of CVD-based approach I and spin-on-based approach II. The self-aligned via (SAV) etch method is considered and compared with punch-through (PT) method for the sake of via encroachment concern. Results show both etch methods could deliver the on-target Rc performance with approach I if the overlay shift is strictly controlled and SAV is quite sensitive to overlay shift and could degrade the overall Rc performance if coupled with approach II. The importance of via circularity, trench-etch and post etch treatment (PET) also needs special attention. Besides, wet etch still plays a critical role in achieving the desired Rc. It's imperative to use the alternative wet method other than traditional dilute HF.
Characterization of Tetrahedral Amorphous Carbon (Ta-C) Thin Films with >6GPa Compressive Stress and Application in Sub-32nm p-MOSFET Strain Engineering
Authors: Ma Xiaolong , Fu Zuozhen , Yin Huaxiang , Zhang Haiqiang , Zhang Xu
Published: March 2012

Tetrahedral Carbon (Ta-C) films with extremely high compressive stress (5~10GPa) were fabricated using double 90o-bend Filtered Cathodic Vacuum Arc (FCVA) technique. Sp3-bonding content in the film was estimated to be >65% determined by multi-wavelength Raman spectra and XPS analysis and it confirms the high quality of the deposited film. In comparison to conventional silicon nitride stress-liner, Ta-C is expected to generate several times higher compressive stress in the channel of sub-32nm p-MOSFET. The electrical performance enhancement induced by extremely high stress liner was investigated through TCAD simulations. The results indicate that a thin Ta-C stress-liner with extremely high compressive stress provides one promising solution for suppressing performance-enhancement degradation in conventional p-MOSFET structure while scaled into sub-32nm node.
Ultra-High Tensile Stress Capping Layer Using Novel Excimer Laser Annealing Technology for 32nm nMOSFET and Beyond
Authors: Qin Changliang , Yin Huaxiang
Published: March 2012

A novel processing technology for stressed capping-layer by 248nm KrF excimer laser is reported. The treated tensile capping layer is composed of silicon nitride fabricated by normal PECVD. The effects of laser annealing with different conditions on tensile nitride are extensively investigated. The number of excimer laser pulses is from 3 to 15 and energy density from 500mJ/cm2 to 800mJ/cm2. Different from conventional post-processing techniques applied in current mainstream CMOS technology for tensile SiN curing, the excimer laser annealing demonstrated much higher energy efficency and as a result, the laser annealing broke more silicon-hydrogen and nitrogen-hydrogen bonds within a much shorter time during film curing. The maximum stress of this cured layer is about 2.2GPa through typical Raman spectroscopy measuring, which much larger than that just after tensile nitride film deposition. This new process supplies one of promising solution for stress-enhancement degradation in sub-32nm CMOS technology.
Highly Scaled Poly-Silicon Channel Vertical SONOS Cell for Ultra High Density NAND Technology
Authors: Kar Gouri S. , Van den Bosch Geert , Arreghini Antonio , Debusschere Ingrid , Van Houdt Jan , Altimime Laith
Published: March 2012

Highly scaled vertical cylindrical cell with 22nm diameter bi-layer poly-silicon channel for 3D NAND Flash memory is successfully developed. A thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole was introduced. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells. We also explore, what is the equivalent feature size (FEQ) that can be reached by layer stacking, taking the inevitable process restrictions into consideration.
Low Stress TiN as Metal Hard Mask for Advance Cu-Interconnect
Authors: Liechao Luo , Kang Jian , Wen James
Published: March 2012

As VLSI technology scaled down to 65nm-node and beyond, BD (Black Diamond) and BD II are widely used as the dielectric. The BD and BD II are porous and soft, the CD (Critical Dimension) will distort and change after etch and line slant without enough support. Metal Hard Mask is an effective solution. And TiN is a good candidate as metal hard mask materials for its high hardness. With traditional PVD (Physical Vapor Deposition) TiN stress is very high. It will cause CD distortion and Cu line void, too. In this paper, new PVD TiN process was developed and the film formation mechanism is studied based on TiN MD diagram. Experiment results show chamber pressure, process Ar flow, sputter power and deposition rate during processing can affect TiN film stress. Low stress TiN film with these new process used as Metal Hard Mask can avoid BD materials distortion and overcome Cu metal void formation due to Metal Hard mask process introduction.
The Contributions of Barrier Resputter for BEOL Integration
Authors: He Weiye , Zhang Beichao , Kang Jian , Jin Jennifer , Bao Wayne , Luo Jeff , Wu Grant , Zhang Daniel
Published: March 2012

For Cu interconnect, Ta(N) barrier is widely used. In this work barrier resputter process was studied. Related wafer acceptance test (WAT), via pouch through, profile of Dual Damascene structure and via electron migration (EM) was investigated. Resputter removes the high resistive Ta(N) from the bottom to lower the via Rc. Barrier first process, including Ta(N) deposition and aggressive resputter, is widely used. Aggressive resputter enlarges top CD of trench and via. That makes gap fill easier and even lower via Rc. Aggressive resputter is helpful to via clean and enhances downstream electro migration (EM) performance. Resputter can change the geometry of dual damascene structure. Such a geometry change has large impact on the upstream electro migration (EM) performance. Barrier resputter also has its shortcoming and limitation. For punch through process, Cu sputtered from the bottom redeposits on the side wall, which may have negative impact on upstream EM performance. Resputter also causes damage to low-k material, with such damage metal line capacitance and reliability may become problem. For Cu interconnect, to manage resputter properly is a key factor to the succeed of back end of line (BEOL).
Texture and Electric Properties of BN Films Deposited on Different Electrodes by RF Magnetron Sputtering
Authors: Wang Fang , Yang Baohe , Zhao Jinshi , Hao Yinzhao , Zhang Kailiang
Published: March 2012

Boron nitride thin films were deposited on different bottom electrodes (BE) by radio frequency (RF) magnetron sputtering. Morphology and structure of films were characterized by atomic force microscopy (AFM) and X-ray diffraction (XRD); Electric properties of BN films were investigated by piezoresponse force microscopy (PFM) and current sensing atomic force microscopy (CSAFM). XRD results show that cubic BN (cBN) film was deposited on copper under an optimized process parameter. The cBN film with a flat surface and uniform particles was confirmed by AFM. In the case of copper electrode, cBN film shows obviously piezoelectric properties. The other two did not show any piezoelectric properties. All the results suggest that cBN on Cu electrode will be one of the promising piezoelectric materials.
Purification and Characterization of Carbon Nanotubes Synthesized by RF-PECVD
Authors: Di Hairong , Li Mingji , Li Hongji , Huang Baokun , Yang Baohe
Published: March 2012

In this research, Ni/MgO is used as catalyst and CNTs were synthesized by radio-frequency plasma enhanced chemical vapor deposition (RF-PECVD), and then liquid oxidation method was used to purify CNTs. Scanning electron microscopy (SEM), transmission electron microscopy (TEM), Raman spectroscope and infrared spectroscopy were used to study the influences of purification time on morphology and microstructure of CNTs. The results show that CNTs synthesized by RF-PECVD contain a great amount of impurities. With the increasing of purification time, the impurities decreased. Meanwhile, carboxyl oxygen-containing groups introduced on the surface of CNTs are also gradually increasing along with purification time. And the crystallization properties of CNTs increased first but decreased then with the introduction of a large amount of oxygen-containing groups. The surface modification of CNTs has very important significance for the applications of CNTs in the field of electrochemical biosensor.
Wafer Backside Arcing Prevention in SIP Ti/TiN Process
Authors: Huang Hupin , Lin Paul-Chang , Gui Kun , Wang William , Li Terry , Ji Justin , Jiang Jian-Yong
Published: March 2012

Self Ionized Plasma (SIP) Ti/TiN Process is used for barrier and glue layer before tungsten deposition in backend-of-the-line (BEOL). Long Throw technology and AC Bias are applied to gain better step coverage. But wafer backside arcing case happened frequently due to AC power side impact during SIP Ti/TiN deposition process. In this paper, the wafer backside arcing mechanism is studied and some effective improvement methods are proposed.
Overcome Challenges in Si/Cu CMP for Back Side TSV
Authors: Xu Sunny , Wang Yuchun
Published: March 2012

TSV (through silicon via), as an enabling technology for 3D IC manufacturing, has attracted intensive attention in most recent years. It usually includes multiple CMP processes during TSV via formation. For backside TSV, after silicon grinding processes, Si surface may contain heavy defects; backside Si/Cu CMP process ensures a smooth surface finish for next step bonding. Due to its intrinsic nature of the via size and the amount of via filling materials, the technical requirements in TSV CMP are very much different than those in conventional IC CMP technology. The conventional IC Si slurry only cares about Si removal, and conventional Cu slurry only care about Cu removal, neither of this slurry can meet the new requirement for Si/Cu CMP in TSV backside CMP. Apart from that, Si surface in most cases is negative charged, while Cu surface in most cases are positive charged, which may result Cu smearing defect after Si/Cu CMP. These technical differences form the new challenge for CMP users during TSV CMP process in 3D IC manufacturing. In this work, some challenges such as Cu smearing defect in Si/Cu CMP will be discussed in details. It is shown Cu smearing defect can be minimized via slurry formation in backside TSV CMP applications.
Two-Component Corrosion Inhibitor Working Mechanism on Cu Surface
Authors: Chao Ching-Hsun , Wang J. F. , Ye Q. , Wu S. H. , Chi B. , Chen Sean Y. , Yu W. C. , Liu P. C.
Published: March 2012

Cu CMP slurries are typically composed of abrasive particles, oxidants, etchants and corrosion inhibitors. The Cu surface is planarized by the CMP process via a repetitive process of oxidation by oxidants, followed by the corrosion inhibitor absorption on the Cu surface and the polish behavior generated by the etchant and abrasive particles. Benzotriazole (BTA) is a commonly used corrosion inhibitor in Cu CMP slurries to effectively prevent Cu from being etched by forming a passivation layer of Cu-BTA. However, benzotriazole exhibits poor solubility in water that can contribute to increased organic residue defect on the wafer surface. In this paper, we describe how we added Component A to be a corrosion inhibitor that was linked with benzotriazole by H-bonding to protect the Cu surface. We investigated the working mechanism for controlling Cu removal rate.
CMP Process Control for Advanced CMOS Device Integration
Authors: Huey Sidney , Chandrasekaran Balaji , Bennett Doyle , Tsai Stan , Xu Kun , Qian Jun , Dhandapani Siva , David Jeff , Swedek Bogdan , Karuppiah Lakshmanan
Published: March 2012

New CMP steps are required to define the structures for new integration schemes for high-k metal gate and FinFET. The performance and yield of these new devices directly depend on CMP control of film thickness variation. As a consequence, CMP requirements are becoming increasingly stringent. This paper highlights the new process control technologies which enable efficient and cost-effective solutions for the new CMP steps, including FullVision® endpoint & in situ profile control (ISPC) for dielectric and poly CMP, and real-time profile control (RTPC) for aluminum, tungsten, and copper CMP.
Cu Corrosion during Post-CMP Clean - Cause and Prevention
Authors: Li Sen-Hua (Samuel) , Liu Jun , Tran Cuong , Tan EngHoe , Li Qiang , Yan Roc
Published: March 2012

Copper dual damascene is becoming the standard process for sub-quarter micron microelectronic interconnects. Photo-induced anodic corrosion could occur on a copper p-n junction sctructure during PCMP cleaning process and the prevention of such corrosion is critical for reducing defects and improving overall yield of copper integration. The electron/hole pairs are photo-generated in the p-n junction inducing potential difference. p+ diffused region has a built-in potential of 0.2~0.5 volts against n+ diffused region. Therefore, copper oxidation and etching happen on the p-side and copper re-deposition and growth are shown on the n-side. Tafel curve measurements can be used to provide accelerated corrosion rate data at certain voltage biases that can be charateristic of copper anodic corrosion. From the PCMP cleaning chemistry perspective, increasing copper inhibitor concentration and/or decreasing copper chelator levels are found to protect copper from anodic corrosion at voltage bias. In addition, using additional additives in the PCMP process can further reduce copper anodic corrosion in a PCMP environment.
A New Image Processing Method to Characterize Pad Foam Morphology in Chemical Mechanical Polishing
Authors: Baisie Emmanuel , Lin Bin , Zhang Xiaohong , Li Zhichao
Published: March 2012

The polishing pad, typically made of rigid microporous polyurethane foam, plays a primary role in the Chemical mechanical polishing (CMP) process. The pad's mechanical response (such as pad deformation and wear) to polishing and conditioning is is highly related to the foam morphology. This is crucial to the fundamental understanding of the material removal mechanism of CMP. Reported methods of characterizing CMP pad foam morphology are based on intricate and expensive procedures in microtomography, microscopy, spectrometry, etc. This study presents a new image processing method as an alternative for the characterization of the morphological and mechanical properties of CMP pads. Two types of CMP pads (IC1000 and IC1400) are chosen to demonstrate the feasibility of the method. Simulation results prove that the proposed method is effective to determine pad foam characteristics (such as pore shape, size, density as well as dispersion) important to the design of high performance pads.
Green Flipper Dual-Sided CMP Conditioner
Authors: Hwang Taewook , Vedantham Rama , Puthanangady Thomas
Published: March 2012

Green Flipper, a dual-sided CMP conditioner, provides dual functional surfaces to condition the pad during cmp process. Compared to a regular cmp conditioner with only one conditioning surface, the Green Flipper can be used twice. The operator uses one side first, flips over the disk and uses the other side as a second side. In addition to two times use with economical benefits, there are technical benefits such as improved flatness and increased active working diamonds which improve disk repeatability and wafer performance in terms of removal rate stability and defects.
Study on Storage Hard Disk NiP Polishing Performance by Colloidal Silica Abrasive
Authors: Li Weiwei , Diao Jianxin
Published: March 2012

Chemical Mechanical Polishing is the best method for planarization of storage hard disk. CMP slurry is the critical factor of CMP technology. The polishing experiment for storage hard disk NiP was carried out with colloidal silica slurry. The abrasive particles of the slurry were investigated used TEM and DLS. The influences of abrasive particle size, particle number, surfactant and oxidant on removal rate and disk roughness have been analyzed.
Extend Millisecond Anneal to Nickel Silicidation Process
Authors: Wang Chenyu , Tang Ji Yue , Zhao Ganming
Published: March 2012

As the transistor device is scaling down to 40nm, 32nm and beyond, Nickel silicide (NiSi) is used to create low resistance ohmic contacts between CMOS transistors and interconnects due to its low resistivity, line-width effect and low thermal budget request. Traditionally, Nickel silicides have been formed typically by two steps lamp-based RTP anneals including a low temperature RTP-1 (220-300°C) and a high temperature RTP-2 (400-500°C). In this paper, AMAT Astra dynamic surface anneal (DSA), a scanning laser-based millisecond anneal system is used for RTP-2 step. The sheet resistance by 4-point probe, SEM, and TEM were used to characterize NiSi agglomeration and microstructures on blanket wafers. The results show that DSA millisecond salicidation anneal delays the onset of NiSi agglomeration, maintains a smooth surface and NiSi/Si interface.
Two Steps Post Nitridation Anneal Study
Authors: Zhao Zhibiao , Tang Ji Yue , Zhao Ganming
Published: March 2012

In sub-micrometer devices, nitrogen is incorporated into the gate-oxide to reduce gate leakage current density and prevent boron penetration. This gate-stack technology includes base-oxide growth, decoupled plasma nitridation (DPN), and post nitridation anneal (PNA) which stabilizes the nitrogen into SiON chemical bonds. The effect of the PNA in reducing the gate leakage and improving the device reliability by raising the annealing temperature has been previously demonstrated. A two-steps PNA process has been developed which can achieve the requisite of device properties, such like leakage, threshold voltage and NBTI, gate oxide integrity (GOI), etc., while enabling EOT scaling. In this paper, the two-steps PNA process parameters impact on interface-traps density, and Idsat is presented.
Overlay Mitigation in RTO Process
Authors: Zhou Qinggang , Tang Ji Yue , Zhao Ganming
Published: March 2012

Across wafer thermal gradients induce distortions that may cause large overlay issues in subsequent lithography process. Misalignment between the gate capacitor and deep trench results in a small contact landing area and much higher contact resistance, impacting the subsequent die yield, especially in the wafer edge area. Product wafer distortion induced by center and edge temperature differences have a small process window at high temperature and thus are a challenge to control. The isolated and dense areas also have different emissivities generating thermal non-uniformity compared to a blanket wafer. Systematic methods were tested to improve the overlay performance. Adjustment of the edge temperature offset can be used to optimize the high temperature step, greatly minimizing the overlay issues.
A Novel Shallow Trench Isolation Liner Dielectric to Enhance NMOS Performance toward 45nm and Beyond
Authors: He Yonggen , Yu Guobing , Wu Bing , Chen Yong , Liu HaiLong , Yue Longyi , Ye Bin , Yu Tzu Chiang , Dai Haibo , Lu Wei , Wu Jinggang
Published: March 2012

In the present work, a novel RTON (Rapid Thermal Oxidation and Nitridation) was investigated as STI (Shallow Trench Isolation) liner dielectric in 45-nm CMOS. Compare with conventional ISSG (In-Situ Steam Generation) oxide, this RTON liner demonstrate better device performance for NMOS transistors both in long channel and short channel. It shown >4% Ioff/Ion improvement and exhibit more tighten SRAM standby leakage distribution. These performance gains can be explained by RTON liner contribution to NMOS channel tensile stress enhancement as well as its excellent capability to prevent channel doping diffusion.
Carbon Nanotubes in Electronics Interconnect Applications with a Focus on 3D-TSV Technology
Authors: Jiang Di , Wang Teng , Ye Li-Lei , Jeppson Kjell , Liu Johan
Published: March 2012

High density electronics integration at the system level, supported by advanced packaging solutions, is expected to be the main driving force for the future shrinking of electronics. One recent focus in the field of electronics packaging is the use of through-silicon-via (TSV) to form three-dimensional (3D) integration. A central task in developing 3D-TSV integration is to build reliable and efficient electrical interconnects for signal transfer and power distribution among the stacked layers. Carbon nanotubes (CNTs) are supposed to be a promising material to build future interconnects due to their many attractive electrical and mechanical properties. This paper reviews the state-of-art in CNT integration technology, with a focus on the 3D-TSV interconnect. The simplicity and manufacturability of fabricating and stacking CNT TSVs presented in this paper indicate a great application potential of CNTs as an interconnection material in future 3D integrated electronics.
Recent Innovations in Leading-Edge Silicon Devices
Authors: James Richard W.
Published: March 2012

The first 45-nm logic devices were introduced in 2007, followed more recently by 40-nm and 32/28-nm products. These nodes are notable for the introduction of high-k dielectrics and metal gate into the transistor structure, and the adoption of second-generation low-k dielectric layers. Soon we expect to see the first 22-nm FinFET products. Also, we are now in the era of 20-nm flash memory and 30-nm DRAM. Chipworks, as a supplier of competitive intelligence to the semiconductor and electronics industries, monitors the evolution of chip processes as they come into commercial production. The paper illustrates (with SEM and TEM imaging) some of the materials and structural changes that have taken place in recent years as silicon heads towards its intrinsic performance limits. It will deal with the evolution of the transistor structure from the 45-nm to the 28-nm generations, and review the latest 3x-nm DRAM technology and 2x-nm flash devices.
Measurement and Simulation of Thermal-Induced Stress in C2W 3D Integration with Template Alignment
Authors: Chen Qianwen , Wu Dong , Zhang Dingyou , Lu James , Wang Zheyao
Published: March 2012

This paper presents the experimental and theoretical investigation of the thermal stress development in the C2W 3D integration with template alignment and the impact of fabrication parameters on the thermal stress. The experimental approach is accompanied with an optical profilometer, while the theoretical study is based on COMSOL FEM analysis. It is found that the thermal stress is primarily induced in the polymer hard curing process, and is accumulated within the cooling process due to the mismatch of coefficients of thermal expansion (CTE) with substrate. The thermal stress highly depends on the polymer thickness and the treatment temperature, and could be partially released by polymer etching. The measurement and simulation results indicate that the template alignment technology is compatible with semiconductor fabrication by optimizing the fabrication parameters. The feasibility of C2W 3D integration with template alignment is furthered demonstrated.
Study on the Solution of via Bottom Void in 90nm Technology
Authors: Zhou Dong-Yi , He Peng , Sun Ri-Hui , Yang Yi , Kang Xiao-Chun , Jiang Jian-Yong , Lin Paul-Chang
Published: March 2012

Via bottom void is one of the problems related to the metal interconnections in semiconductor devices. In 0.13μm technology, Novellus Sabre serial is wildly applied as copper(Cu) electro chemical plating (ECP) tool, but the problem of high hit ratio of via bottom void in 90nm CMOS technology makes it difficult to perform as well as in the 0.13μm technology. In this paper, the mechanism of the formation of via bottom void of Cu interconnection was analyzed and the solution of the problem in the 90nm technology was studied. A series of experiments were carried out and the result shown that the via bottom void can be eliminated by increasing the plating current during the initial period of Cu plating process.
An Etchant for Delineation of Flow Pattern Defects in Heavily Doped n-type Silicon Wafers
Authors: Xu Tao , Zhang Xinpeng , Ma Xiangyang , Yang Deren
Published: March 2012

Secco etchant was conventionally used for delineation of flow pattern defects (FPDs) in lightly-doped Czochralski (Cz) silicon wafers. However, the FPDs in heavily doped n-type silicon wafers cannot be well delineated by Secco etchant. Herein, an etchant based on CrO3-HF-H2O system, with an optimized volume ratio of V(CrO3): V(HF)=1:1, where the concentration of CrO3 is 0.25 M, has been developed for delineation of FPDs with well-defined morphologies for the heavily As- or P-doped n-type silicon wafers.
Investigation of Surface Blistering and Exfoliation in Germanium Induced by Hydrogen Molecular Ion Implantation
Authors: Chien Chi-Chen , Chao Der-Sheng , Liang Jenq-Horng , Lin Chih-Ming
Published: March 2012

This study investigated the effects of thermal budget on the surface blistering and exfoliation behavior in germanium due to hydrogen molecular ion implantation. Germanium wafers were implanted with 200 keV H2+ ions to a fluence of 2.5×1016 ions/cm2 and followed by furnace annealing treatments with various thermal budget. Characteristic analyses were conducted using optical microscopy (OM), secondary ion mass spectroscopy (SIMS), and cross-sectional transmission electron microscopy (XTEM). The results of the OM-measured average number density, diameter, and covered-area fraction of both optically-detectable blisters and craters suggested an optimal condition of 410 oC, 1 hr. The XTEM-examined images and the SIMS-measured hydrogen and oxygen depth profiles also confirmed that the average depth of micro-cracks correlated closely to the positions of peak hydrogen-trapping concentration and peak oxygen-trapping concentration rather than that of peak hydrogen concentration.
Characterization of Advanced Gate Architecture Stress on 22nm Gate-Last CMOS Device
Authors: Fu Zuozhen , Ma Xiaolong , Yin Huaxiang
Published: March 2012

In this paper, the characteristics of gate strain enginnering on 22nm High-k/Metal-Gate-last (HK/MG-last) CMOS device are studied through a process and device simulation by Sentarus TCAD tools. In addition, we proposed novel gate electrode architecture with trapezoid profile and investigated its special strain effect on channel. We also proposed one new integration approach for stressed dummy gate fabrication.
Fab Environment Effect on Crescent Pits Defect in Cu Metallization Process
Authors: Kang Xiao-Chun , Lin Paul-Chang , He Peng , Sun Ri-Hui , Yang Yi , Zhou Dong-Yi , Jiang Jian-Yong , Xing Charles
Published: March 2012

Copper (Cu) material is being widely used in the advance ultra large-scale integration (ULSI) in the metallization process due to its low resistivity and good performance on EM in 130nm and below technology node. In Cu metallization process of 130nm, crescent pits defect on wafer edge is often scanned and found post Cu CMP process. Thus interconnect reliability and yield loss become key issue to ensure device quality and performance. In the filed, some studies focus on the Cu plating wetting ability improvement to reduce pits defect. In this paper, atmosphere VOC (Vapor Organic Compound) effect is studied to reduce crescent pits formation.
Bumpless Through-Dielectrics-Silicon-Via (TDSV) Technology for Wafer-Based Three-Dimensional Integration (3DI)
Authors: Ohba Takayuki
Published: March 2012

This paper describes wafer-on-wafer (WOW) technology using bumpless through-dielectrics-silicon-via (TDSV) and dual-damascene interconnects for three-dimensional integration (3DI). Trends in conventional scaling compared with bumpless processes, the characteristics of devices after thinning the wafers to less than 10 um, and applications, including closed-channel-cooling systems (C3S), are discussed.
Applications Driving Adoption of Direct Bond Technology
Authors: Enquist Paul
Published: March 2012

The high bond energy at low temperature capability of direct bond technology results in bonded structures and 3D ICs with the lowest distortion, highest density of 3D interconnects and thinnest form factor. These attributes and compatibility with industry standard manufacturing have led to the adoption of this technology in the supply chain for volume manufacturing of backside illuminated (BSI) image sensors. The establishment of this technology in the supply chain will reduce the adoption barrier for other applications including 3D BSI, RF front ends, 3D memory, and pico projectors.
Concurrent and Collaborative Design in Package and Surrounding System, the Good Way to Make High-End SoC Design Successful: A Case Study of Availink SoC Package and System Board Design, Interactively with Die Physical Design
Authors: Ye Samuel , Zou Tong , Zeng HongBo
Published: March 2012

In complex SoC design, the higher performance and compact package would often cause tremendous problems with signal integrity - simultaneous switching noise issues, crosstalk issues, and resonance issues. Therefore, to design the chip, the package and its system concurrently can draw out all critical constraints simultaneously to all parties (chip, package and system design teams). In the process, a single interactive database is essential to allow design teams perform high speed interconnect analysis at both physical and electrical levels and make optimization tradeoffs among all levels. Meanwhile, the methodology also supports collaborative designs among fabless design house, package house and printed circuit board design suppliers. A case study of Availink SoC package and system board design listed the issues faced and explored the methodology described above and compared both critical signals simulation and physical test results. Finally a general flow of concurrent and collaborative design with simple analysis, as a comparison to conventional way, is given.
Effective Gap Filling via Magnetic Field Simulation Assisted on Longthrow Sputtering PVD of Side Magnet Designs and Arrangements for 3DIC Application
Authors: Li Tomi T. , Chen H. T. , Yeh J. S. , Yang Thomas C. K. , Yang S. W. , Liu H. H. , Chiang Leo
Published: March 2012

This study used Finite Volume Method to simulate the magnetic profile of PVD (physical vapor deposition) chamber. For this longthrow PVD, the adaptor of the gap filling chamber has 120 mm height and 44 sets of side magnets around the adaptor. The polarity of the side magnets is the same as the top magnets of the chamber. These side magnets can very effectively increase electron mobility and collision frequency with sputtered atoms. The plasma simulation result shows that ionization rate on sputtered atoms can be up to 12% from such a PVD system along with such a magnet arrangement. Therefore, it shows a significant improvement on bottom side-wall coverage of via hole up to 45%. The deposition rate increases by 40%. In addition, the adjustment of RF bias and resputtering power can result in further improvement on 3/4 depth of side-wall coverage by 30% and corner step coverage by 70%. This study uses a simple method to apply 3DIC gap filling capability for an increase of aspect ratio (AR).
LED Cost and Performance: How to Enable Massive Adoption in General Lighting
Authors: Virey Eric H. , Yannou J. M. , Roussel P. , Mukish P.
Published: March 2012

General lighting is the next and largest ever market for LED light sources. However, for most segments, LEDs are still too expensive compared to incumbent technologies in term of both upfront and total ownership cost. The LED industry still has plenty of room for cost improvement. A more than 10x reduction in both $/lum and $/lumen.hour is expected at the packaged LED level [1]. This can be achieved through a combination of technology and manufacturing improvements at both the frontend and backend levels. We will review the main opportunities for cost reduction and focus on the most recent and promising trends to give a complete overview of how innovation and manufacturing efficiency will help enabling massive adoption of solid state lighting.
Advanced TPMS Packaging Solutions in a Pre-Molded Cavity Leadframe
Authors: Guirit Lynn , Cabatbat Edmund , Ng YS , Chin S. K.
Published: March 2012

The worldwide demand for a Tire Pressure Monitoring System (TPMS) has grown due to the dangers posed by widespread tire safety abuse. The National Highway Traffic Safety Administration (NHTSA) estimates that 23,000 accidents and 535 fatalities per year involves flat tires or blowout both of which can be the result of improperly inflated tires. To further enhance vehicular safety, US government and Europe mandated the use of TPMS for all passenger cars by year 2008 and 2012 respectively. This prepare illustrates the packaging of a low cost yet complex TPMS device that involves MEMS (pressure sensing and accelerometer devices) and Controller chips integrated as one in a low cost Pre-molded Leadframe Cavity Package. Advanced solutions to resolve process challenges and material difficulties have paved the way to successfully qualify the product meeting all the intensive automotive requirements.
Study of Factors Contributing to Robust Copper Wire Bond on QFN
Authors: Wei Tan Boo , Niu Ken
Published: March 2012

Copper wire interconnect is gaining momentum in mass production at rapid speed as the industry continue to mature into more robust copper wire bond process capability and at the same time has realized its cost benefits over gold wire interconnect . QFN (Quad Flat No-Lead packaging) has been in mass production for longer period in industry to support trend towards smaller packaging technologies, replacing other lead frame base or even substrate base packaging solution at rapid speed. Typical QFN 's thermal and electrical performance has been improved over the traditional lead frame base packaging and has become popular choice among designers to take advantage of the reduced form factors for application in cell phones, power management ICs and other portable consumer electronics.
Characterization of CNT Enhanced Conductive Adhesives in Terms of Thermal Conductivity
Authors: Zhang Zhfei , Ye Li-Lei , Kukovecz Akos , Konya Zoltan , Bielecki Johan , Liu Johan
Published: March 2012

CNTs have excellent thermal, electrical and mechanical properties. They can be used in various ways. One researched field of application is CNT-polymer composites which combine common technologies with advanced materials. This paper will focus on the thermal property of CNT-Ag-filled adhesives and compares the new materials with conventional, electrical Ag-filled conductive adhesives. Several analytical methods, FTIR, Raman analysis, SEM and TEM have been carried out to examine the different surface conditions after physicval and chemical modification of CNTs. The thermal conductivities of composites containing different types of CNTs were investigated. The incorporation of CNTs into polymers resulted in enhancement of the thermal conductivity compared to Ag-filler. The increase of thermal conductivity with addition of CNT filler is obvious, especially for the purified CNT. The value of thermal conductivity is about two times higher than the Ag-filled conductive adhesive. However, improvement on thermal conductivity of the surface modified CNT-filled conductive adhesives is not so obvious. Since the thermal conduction in CNT is by phonon transfer, the nanometric size and the huge interface lead to strong phonon-scattering at the interface. Thus, a relatively low interfacial area, weak interfacial adhesion promotes the conduction of phonons and minimizes coupling losses. According to this, the non-treated MWCNTs seem to have the highest potential to improve the thermal conductivity of epoxies.
Scan Based Silicon Debug
Authors: Huang Yu
Published: March 2012

Silicon debug is very important to make a VLSI product quickly available to the market and meet time-to-volume requirement. With designs becoming more complicated, the time spent for silicon debug is taking more fraction of the whole design cycle. Many silicon bugs are found at system level or at chip level while applying a functional test sequence. Comparing to scan test failures, debugging the functional failures is more time-consuming. Scan-based diagnosis is more mature in the recent years and already widely used by many semiconductor companies as defect localization and yield ramp up tool. Meanwhile people have already started to adopt the scan-based diagnosis in silicon debug. Nevertheless, since the objective and application are different in manufacturing diagnosis and silicon debug, their application flows could be also different. In this paper, we will discuss the challenge and possible solutions for using scan-based diagnosis flow on silicon debug.
Pattern Sensitivity Study for Non-Volatile Memory Data Retention Test
Authors: Fan Weihai , Yu Lisa , Hu Shaha
Published: March 2012

The pattern sensitivity for the data retention test of non-volatile memory was investigated. Through kinds of examples and combing theory analysis, it's found no universal sensitive pattern is capable to detect all kinds of process weakness, the selection of test pattern depends on the failure mechanism we most concern. Basically 00H or FFH state is the worst case to detect the intrinsic isolating ability of vertical dielectric, and CKBD (checkerboard, '0' and '1' state are alternated programmed) pattern can check not only vertical isolating effect, while half possibility when comparing to 00H or FFH, but also lateral cross-bit effect. Data retention pattern selection method during reliability test plays a critical role when applying more and more advanced technology to guarantee NVM (Non-Volatile Memory) product storage lifetime.
Application of SEM API on PWQ Wafer SEM Review
Authors: Khor S. C. , Luo Xiao J.
Published: March 2012

Process Window Qualification (PWQ) is a good and well-established method to find systematic defects with high sensitivity and to qualify new masks and OPC revisions. The PWQ methodology is utilized to provide an extensive defectivity characterization to determine the absolute best conditions for focus and dose. This is achieved by taking into account the defectivity in the whole die and capturing all potential systematic defects. [1] This in turn had driven to more and more SEM review on this kind of PWQ wafer in wafer foundry. Manual SEM review of this PWQ wafer is time consuming and spending a lot of man power. In this paper, a new method of reviewing the PWQ wafer with API method and how it helps to resolve the current manual SEM review limitations is introduced.