bluuebunny/crossref_metadata_2025 huggingface dataset:
An algorithm for updating skeleton matrix of a reachability matrix model
Authors: Kase Satoshi , Ohuchi Azuma , Kaji Ikuo
Published: July 2007

A reachability matrix M is a binary matrix with a reflexive and transitive property, i.e., M + I = M and M2 = M, where I is the identity matrix. A skeleton matrix S is a nonredundant matrix of M. the skeleton matrix has the following properties: SK‐2 ≠ SK‐1 Sk M, and any binary matrix B ≠ S which satisfies the forementioned equation will also satisfy B > S, where the super scripts on S are exponents and the operations are Boolean. an algorithm for updating the skeleton matrix is proposed. the proposed algorithm is much more efficient than the previous algorithm used to perform the same task.
Variable rate sampling technique for images based on successive approximation vector quantization
Authors: Yamada Yoshio , Tazaki Saburo
Published: July 2007

The monochromatic static image can be represented as a scalar‐valued function f(u, v), for the brightness or density at point (u, v) on the two‐dimensional coordinate space T. For the color image, the image is represented by a vector‐valued function composed of such signal components as red, green, blue or luminance, chrominance and saturation. The sampling of an image can be considered as derivation of a sequence {fi} of spatially discrete sampled values by dividing the coordinate space T. Denoting the partitioning of the coordinate space by {Si}, the sampled value fi is a scalar or vector value, which is determined uniquely by the subimage {f(u, v) |(u, v) ϵ Si}.

This paper proposes a new variable rate sampling method which partitions the multidimensional coordinate space efficiently based on the vector quantization method. A high‐speed region partitioning algorithm is also shown which is based on the successive approximation vector quantization. The usefulness of the proposed method is demonstrated by simulation. Using those results, the sampling process is reformulated as the vector quantization in the coordinate space. Thus, a new development is made for the variable rate sampling method.
A regression analysis method matched to the prediction of probability distribution with less information loss and its application to the acoustic environment (in the case with continuous value observation)
Authors: Ohta Mitsuo , Chang Bing , Takaki Naomitsu
Published: July 2007

In the study of acoustic environment, the well‐known regression analysis is applied based on the measured data for the predictor variable and the criterion variable. Standard methods are employed in the usual regression analysis, such as the assumption of Gaussian distribution of the variable, the mean‐square evaluation of the error, and the prediction based on the transformation of regression function. This paper concentrates on the derivation of a new methodology, avoiding as much as possible such a traditional artificial simplification, and predicts the overall distribution of the fluctuation of the predictor variables based on the criterion variables with arbitrary fluctuation distribution. Based on the standard method of regression analysis, a discussion is made as to what higher‐order processing should be introduced to achieve the goal of prediction of the fluctuation distribution. A method of regression analysis matched to the complexity of the phenomenon, and a new prediction method for the response distribution based on the regression are proposed. More precisely, three kinds of regression models are derived which reflect as comprehensively as possible various linear and nonlinear correlation information between two kinds of variables. It is shown that the well‐known regression analysis based on the least mean‐square evaluation is included in the proposed method as a special case. The proposed regression model and the prediction method are applied to the actually measured data for the acoustic environment, indicating experimentally although partially the practical usefulness of the proposed method.
Modified two‐dimensional AR lattice filter and its application to spectral analysis
Authors: Watanabe Tsutomu , Taguchi Akira , Hamada Nozomu
Published: July 2007

As a generalization of a one‐dimensional (1D) AR (Autoregressive) lattice filter structure, Parker et al. proposed a two‐dimensional (2D) AR lattice filter with three reflection coefficients in each stage for the linear prediction of a given random signal.

This paper shows that Parker's lattice model is not sufficient to realize any 2D AR process. Hence, we will use a more general lattice filter whose stage has six reflection coefficients. The determination procedures of reflection coefficients, and the algorithm for deriving an AR transfer function, a sufficient condition of filter stability, are considered. In the example shown, the proposed model is seen to be more general than that of Parker's. Finally, a new power spectral estimation method using the proposed lattice filter is considered.
Switched‐capacitor circuit analysis program SCNODAL and its application to SC filter design
Authors: Inoue Takahiro , Ueno Fumio , Sonobe Satoru , Matsumoto Tetsuya
Published: July 2007

A general‐purpose circuit analysis software such as SPICE, and an SC‐specified circuit analysis software such as SWITCAP, are both available for analysis of SC circuits. However, the former requires additional pre‐and post‐processings because the analysis is performed by converting SC circuits into equivalent continuous‐time circuits such as active‐RC circuits. As to the latter, the present limitation on the kind of OS environments is severe for users in Japan. SCNODAL proposed in this paper is developed for the purpose of providing an SC circuit analysis tool which is easy to use and is implementable on general‐purpose or personal computers popular in Japan. Since SCNODAL has many functions, it is useful as a semi‐general‐purpose SC circuit analysis tool. SCNODAL has an input format which is best suited for an analysis of parasitic‐insensitive SC filters. Since nine‐standard building blocks are built in the program, a compact representation of the input data is possible. Furthermore, SCNODAL has many user‐oriented functions with regard to a clock‐pattern input form, an input form for a tracking pattern of elements, and an option for an output form. Thus, one can easily perform a variety of analyses such as amplitude response analysis and sensitivity analysis. In this paper, SCNODAL is described based on the formulations of the nodal equation and other equations used in each analysis to the actual usage of this software, by illustrating an SCF design.
SC immittance simulation circuits using ugbs and their applications to filters
Authors: Hyogo Akira , Sekine Keitaro
Published: July 2007

As switched capacitor (SC) immittance simulation circuits based on the bilinear z transformation, circuits are proposed that realize the inductor (L) as the linear system of s, and the FDNC (D) and FDNR (M) as the quadratic systems. The circuit configuration is separated into the feedback circuit and the immittance realization unit and their realizations are constructed. Since the UGB (Unity Gain Buffer) with a simple circuit is used in the active circuit for these units, one can expect low power consumption, small chip areas and high‐speed operation. All the proposed circuits can be constructed with a binary phase clock. The element values can be determined only by one capacitance value comprising the feedback circuit and the sampling period. With respect to the inductor and the FDNC, the parallel resistance and capacitance generated by the choice of the capacitance value are investigated. With respect to FDNR, it is shown that an M‐L‐C‐R parallel circuit with arbitrary values of M and L can be obtained by simply adding one set of feedback circuits. Finally, as an application of the proposed circuit, a low‐pass filter, a bandpass filter and a high‐pass filter are constructed. Their operations are confirmed by the experiments using individual components.
Finite element simulation of steady‐state heat problem in electrostrictive vibrators
Authors: Ando Ei'Ichi , Kagawa Yukio
Published: July 2007

Ultrasonics is utilized widely for industrial application. An electrostrictive transducer is used widely for this purpose because of its high electromechanical conversion efficiency. In actual use, the transducer usually is operated under the mechanical vibration of large amplitude, and the mechanical loss of the vibrating body is responsible for the heat.

Since the transducer is also excited at high voltage, the dielectric loss in a ferroelectric body must be considered for the heat. These losses should be taken into account in the design. However, the temperature distribution and the influence of the temperature caused by the heat are not always clear. The heat design of the transducers depends on the experiments which at present, are made on a trial‐and‐error basis.

This paper describes the application of the finite element method to simulating a steady‐state heat diffusion problem in electrostrictive vibrators. The simulation is made to evaluate the temperature distribution caused by the heat which is generated by the mechanical vibratory loss in the elastic body and the dielectric loss in the ferroelectric body, and then the influence of the temperature distribution on the transducer characteristic is examined. Simulation is an experiment on computer and could be used as a means of CAD. Among others, the capability of the visualization of the temperature distribution and the thermal stress distribution helps to design the ultrasonic transducers. A numerical demonstration is made whose results are compared with the experimental results. The technique is proved to be useful in solving problems of this kind.
Variations of vertex potentials by short‐circuiting two vertices in resistance networks
Authors: Sato Kimio
Published: July 2007

In the resistance network N, the potential of each vertex determined in reference to one vertex of the input vertex‐pair, where a unit current source is placed, can be expressed by using the topological formula as the ratio of the conditional 2‐tree conductance product sum to the tree conductance product sum of N. It is a well‐known empirical law that the potential of the input vertex (equi‐valently, the input resistance) does not increase if any two vertices of N are short‐circuited. However, no rigorous and simple algebraic proof including the potential variation of the input vertex is available, and such studies on an arbitrary vertex as its generalization have not been carried out. In this paper, the variations of vertex potentials by short‐circuiting two vertices of N are formulated by using the topological process. If the formula obtained here is used, a necessary and sufficient condition can be provided for increase (or decrease) of any vertex potentials by short‐circuiting two vertices of N besides a proof of the fore‐mentioned empirical law. In addition, the following can readily be verified. If the potentials of two vertices of N are equal, the potentials of any vertices do not change by short‐circuiting the two vertices. Even if a specific vertex potential does not change after short‐circuiting two vertices, the potentials of these two vertices are not necessarily equal.
Numerical analysis of switching transformation matrices for SC circuits
Authors: Hanagata Osamu , Tanaka Mamoru
Published: July 2007

In equations describing switched‐capacitor (SC) circuits, the switching equation of some switching instant is represented by v+c = F · v−c + G · u+. Historically, the transformation matrices F and G have been obtained by the limiting method, in which each switching resistance approaches infinity or zero. This method derives the transformation matrices F and G directly. But it has numerical instability for large‐scale SC circuits, because Frame's method is used. In this paper, we propose two methods to obtain the transformation matrix F from a characteristic matrix C. The first method is the Danielevsky's method, and the second is the backward Euler method. We also propose another method to transform F to G by means of characteristic matrices given by circuit topology, by relation of zero input and the zero state responses. The results of the simulation are represented by a simulator.
Measurement of the complex relative permittivity frequency characteristics of the body using pulse—reflection
Authors: Higashi Tsunehito , Ishihara Khoshi
Published: July 2007

From the measurement of a reflected voltage waveform from a biological body for a step‐like voltage waveform, the frequency characteristics of the complex relative permittivity are studied and the following results are obtained: (1) if the blood flow and sweating are normal, the value of tanδ in the mouth is 4 ‐ 6 at about 10 MHz because electrochemical materials are contained in a large quantity. At frequencies below 100 MHz, the value is larger than those at the face, upper arms, legs and torso and its decrease with respect to frequency is larger. The back of the foot and the thenar have relative permittivities and tanδ's lower than other parts and hence are suitable for measurement of emotion functions; (2) in a physical exercise which causes a change in blood condition without sweating, the value of tanδ in the moving part increases as the number of motions is increased. In addition, the frequency characteristics below 1 GHz change significantly. The value of tanδ in the portion not related to the motion increases even after termination of the motion. Hence, the effect of the exercise can be evaluated from tanδ; and (3) as sweating progresses, the reduction of the permittivity becomes significant at frequencies below 100 MHz while the increase of tanδ is significant below 1 GHz. Hence, the sweating activity can be evaluated from the complex relative permittivity.
A unified approach to multiobjective linear programming problems with fuzzy parameters
Authors: Sakawa Masatoshi , Yano Hitoshi
Published: July 2007

This paper considers multi‐objective programming problems with fuzzy parameters, and newly defines the concepts of four types of α‐feasibility and β‐Pareto optimality. The relations between these concepts is discussed in some detail. Four types of (α, β) Pareto optimal solutions, which simultaneously consider the proposed α‐feasibility and β‐Pareto optimality, are introduced. The possibility of deriving these solutions using linear programming is shown. The relationship of this approach to the already proposed extended concept of the Pareto optimal solution is also discussed.
Orthogonal projection algorithm for block adaptive signal processing and some of its properties
Authors: Furukawa Toshihiro , Kubota Hajime , Tsujii Shigeo
Published: July 2007

With the progress of hardware technology, the development of real‐time adaptive algorithms is becoming more and more important. The essential questions concerning adaptive algorithms are: 1) increasing the speed of the algorithm; and 2) speeding up the convergence. It seems that the block signal processing and the orthogonal projection on the subspace of state‐vectors are effective methods to solve the forementioned questions 1) and 2), respectively.

This paper proposes a block orthogonal projection algorithm (BOPA) which combines the block processing with the orthogonal projection operation. Next, an analysis of this algorithm is presented and the fundamental properties of the relation between the block length and the convergence characteristics are shown. Also, the efficiency of the proposed algorithm is verified by computer simulation. This algorithm is based on a block‐by‐block adaptation where the operation of orthogonal projection on the state‐vector space is performed repetitively for arbitrary blocks.
An efficient user interface based on maximizing shared information
Authors: Suzuki Joe , Matsushima Toshiyasu , Hirsawa Shigeichi , Inazumi Hiroshige
Published: July 2007

In designing systems with a human‐computer interface with a minimum number of interactions, there are two issues to consider: the determination of a proper sequence of questions by the user, and proper termination by the computer system, based on previous instructions. In short, these issues are those of feature selection ordering and a stopping rule for pattern recognition processes. Conventional treatments of these problems have been investigated from the viewpoint of an average error rate. When the number of patterns is large, however, and the number of instructions to be terminated is large, from the point of view of user interface efficiency, and the average error rate is not an effective indicator at the intermediate stage. In this paper, a new method is proposed for determining feature selection ordering and a stopping rule which focuses on the remaining patterns at each stage, and which maximizes the value of mutual information between the user's responses and the required pattern. Important properties associated with this scheme have been demonstrated while evaluating its performance via computer simulation. One is that the average information gain at each stage decreases monotonically, and another is that this scheme produces the minimum error rate.
Logic design system with evaluation‐redesign mechanism
Authors: Maruyama Fumihiro , Kakuda Taeko , Matsunaga Yusuke , Kawato Nobuaki , Minoda Yoriko , Sawada Shuho
Published: July 2007

Sophisticated CAD (Computer‐Aided Design) systems that can produce quality designs quickly are anticipated to keep pace with the remarkable advance of VLSI technology. This paper presents a cooperative logic design system, co‐LODEX, in the two streams of design, datapath design and control design. The feature of co‐LODEX is its evaluation‐redesign mechanism using assumption‐based reasoning, which automates the evaluate‐redesign cycle under constraints. As constraints co‐LODEX takes those on area and speed.

Design alternatives are considered as assumptions and constraint violations as contradictions. Redesign was implemented as contraction resolution. Here, justifications are defined for constraint violations whose forms are independent of actual constraint values, and the evaluation‐redesign mechanism based on these justifications is described.

An experimental system was implemented and it was observed that it could correctly carry out the evaluation‐redesign mechanism. It enables the user to specify constraints in terms of numbers and obtain a circuit satisfying all of them. It also allows the user to obtain a variety of circuits efficiently with different characteristics conforming to the same specification by changing constraints.
A Communications Network Reliability Specification Based on the Failure Effect
Authors: Watanabe Hitoshi
Published: July 2007

One method used in the reliability design of a switching system is the determination of the unavailability target according to the scale of a failure. This method has already been applied to the design of digital switching systems. The basic idea of this approach is the following. The effect produced by a failure in a switching system depends on the scale of the failure. Consequently, in order to achieve a balance between economy and reliability, the target of reliability should be set according to the scale of the failure. A similar idea can be applied to a link in a communications network. This paper presents the basic concepts involved in setting the unavailability target in the link of a communications network based on the scale of the failure. The effect of a link failure is formulated in terms of the degradation of the channel capacity, and is introduced as the network loss. A method is presented, wherein the unavailability target is set so that the loss is a reasonable value. In contrast to the case of a switching system, for a network it is a difficult problem to determine the unavailability target of a link. This is because a link is often a common path between different node pairs, and a strict reliability design should consider all the paths between nodes. This paper presents a simple method for dealing with this problem, in which the unavailability target is set taking into account only the scale of the link, and not the individual paths between the nodes. It is shown that the proposed reliability design method is quite useful in practice.
Algorithms for finding maximum and selecting median on a processor array with separable global buses
Authors: Maeba Takashi , Tatsumi Shoji , Sugaya Mitsuyoshi
Published: July 2007

A problem has been considered in which the maximum among N data should be determined by providing a global bus in a processor array. As a solution to this problem, various kinds of global bus configurations have been proposed from the viewpoint of improving the computation time. This paper considers the processor array with global buses, which includes several switching units and can be separated by the switching control from the processors.

Parallel algorithms are constructed which can solve efficiently the semigroup computation such as maximum determination and the median selection problems. The computational complexity of the proposed algorithm is evaluated to indicate that the proposed method has an asymptotically desirable property. Furthermore, to verify that the separable global buses can be embedded efficiently in a VLSI chip, the area‐time complexity is evaluated as a performance measure for the VLSI circuit. Comparing the result with the case of the processor arrays with the traditional global bus configuration, the proposed algorithms are shown to be more VLSI‐oriented.
The dead‐zone conductor hyperchaos generator
Authors: Saito Toshimichi
Published: July 2007

This paper discusses a simple four‐dimensional autonomous hyperchaos generator. This circuit includes only one nonlinear element: a dead‐zone conductor (serially connected Zener diodes) and the circuit dynamics is described by a piecewise‐linear canonical equation. Regarding the dead‐zone conductor as a switch, the circuit equation can be simplified and hence a two‐dimensional Poincaré map can be defined. This simplification is proved to be reasonable for an n‐dimensional canonical form. The Poincaré map and its Lyapunov exponents can be calculated by using exact solutions and they explicate the generation of hyperchaos and related phenomena.
A method to measure the area function from distribution of complex sound pressure in the nonuniform acoustic tube
Authors: Motoki Kunitoshi , Miki Nobuhiro , Nagai Nobuo
Published: July 2007

Determination of the area function of the vocal tract is an important problem for the speech production model. This paper proposes a method to measure the area function from the distribution of complex sound pressure in the nonuniform acoustic tube. The area is obtained with the calculation procedure of the cascade matrix at each measuring point under the assumptions of plane‐wave propagation and the losslessness of the non‐uniform tube. Discussions are also presented on the experiments for axially symmetric tubes and replicas of oral cavities. The proposed method is useful in investigating the influence from the complicated shapes of the oral cavities by using their replicas.
An adaptive LMS algorithm with a quick tracking property for time‐varying parameter estimation
Authors: Usui Shiro , Abe Kenichi , Qiu Zhong‐Qi
Published: July 2007

This paper proposes a method which estimates time‐varying parameters of a nonstationary signal such as a biological one in real time. This method is based on a local quasi‐stationary concept in the block processing and on the standard LMS algorithm in the recursive processing. That is, we consider a first‐order approximation to the time‐varying parameters for a short period of time, and estimate coefficients of the constant and the first‐order variation terms by the standard LMS algorithm. At the end of each period the estimated values are renewed.

This approach does not require calculating matrix inversion and It uses only input values at each time to estimate time‐varying parameters adaptively. Also, it can be implemented because of its simplicity. The most attractive point of this approach is that the coefficients of the first‐order variation terms are estimated at each time, and thus quick tracking of time‐varying parameters can be achieved. This improves the tracking performance drastically.

A convergence property of the proposed algorithm is discussed theoretically. Finally, simulation results are presented to illustrate the tracking performance of the proposed algorithm compared with that of the standard LMS algorithms.
LSI logic synthesis expert system
Authors: Kurosawa Yuichi , Nishio Seiichi , Masubuchi Yoshio , Miyata Misao
Published: July 2007

This paper describes the expert system which automatically generates the logic circuit composed of elements registered in the cell library, receiving the functional description at the register transfer level of the hardware as the input. The features of the system are that it includes the dedicated circuit data structure, the rule description language, and the corresponding processing system, which can generate a high‐quality large‐scale circuit in a short processing time.

In other words, by introducing the technology‐independent functional elements into the data structure, the circuit can be generated by effectively utilizing the high‐level functional library elements. By including the mechanism for the local transformation into the system and by other sophistications, a practical processing speed is realized. The knowledge depending on the library and the user, is formulated into rules. This is useful in providing the system with flexibility. The system has already been applied to the development of more than 30 kinds of practical products. Using a large‐scale computer with 15 MIPS, a circuit with several thousands of gates can be generated automatically in 4 to 12 min.
A knowledge based system for embedding DFT‐methodologies
Authors: Furuya Kiyoshi , Shinoda Shoji , Koguchi Kazuhito
Published: July 2007

The application of the DFT (design for testability) technique to VLSI circuits is a difficult procedure, since it requires the knowledge concerning the application environment, effectiveness and cost of individual techniques. This paper discusses an automatic embedding system for DFT techniques, dealing with the circuit at the functional block level. The system is constructed with the goal of easy implementation and modification of DFT functions. The use of a generalpurpose inference engine is assumed. DFT techniques as well as circuit structures are represented by a structured database, and the rules to be applied are represented by a rule base. When more than one DFT technique can be applied to a block to be tested, the one minimizing the cost function is adopted. The selection of the generator and compressor is accelerated by the use of a heuristic method. As DFT techniques, the exhaustive testing, locally exhaustive testing and random testing are implemented for combinational circuits. Universal testing, memory random testing and built‐in memory testing are implemented for PLAs. OPS83 was used as the tool for construction.
Analysis for singular equation in search process for operating state of transistor network
Authors: Mizutani Hikaru , Tanaka Mamoru
Published: July 2007

This paper describes a method to avoid the singular problem at the “S‐control” algorithm. The “S‐control” is proposed to determine the correct operating state in any bipolar transistor network (BTN). Each diode of the Ebers‐Moll model is replaced with a directional switch called an S‐branch which has “on” and “off” states. The switch status is changed by the S‐control algorithm. However, the matrix singular problem occurs in the process of the S‐control. The singular matrix is formed by a cutset of only current sources or a loop of only voltage sources. The singular problem is solved by the signdiscrimination method by which the sign of each node voltage is judged by the introduction of small immittances in cutset (loop) of only current (voltage) sources formed in process of the S‐control. The S‐control algorithm will be continued to obtain the next switch state unless the limit cycle is not generated.
Systolic array implementation of 2‐D digital filters using 2‐D block processing
Authors: Hirano Yasuhiro , Takebe Tsuyoshi
Published: July 2007

The requirements of high‐speed filtering are more serious in 2‐D digital filters than in 1‐D digital filters because the former must perform many more operations and deal with considerably more data. This paper proposes a systolic array implementation of 2‐D digital filters using 2‐D block processing.

First, an extension of systolic array implementation for 1‐D block processing into 2‐D block processing is shown and then the circuit is decreased by improving it. This systolic array has a disadvantage in that the number of processing elements per sample increases in proportion to the processing speed.

To improve this situation, we present an implementation method for obtaining the throughput proportional to the number of arrays by using multiple systolic arrays having multilayer structures. This circuit behaves like a 3‐D systolic array.
Design of fresnel‐zone IDT pattern and two‐dimensional acoustic field
Authors: Shiokawa Showko , Matsumoto Shigeo
Published: July 2007

The following theoretical results were obtained in a previous paper. A focused acoustic field can be obtained by dividing the interdigital transducer (IDT) in the form of a Fresnel‐zone type in the aperture direction. The focal point obtained by a geometric method and the computed result by the angular spectrum of plane wave (ASPW) method do not coincide. A new design method based on the clarification of the cause of disagreement was proposed. The electrode based on this design method was called the Bessel‐type Fresnel‐zone IDT. It was shown that the computed value and the design value agree.

In this paper, the proposed design method is confirmed experimentally. Hence, a Fresnel‐zone IDT was fabricated on a PZT piezoelectric substrate and the amplitude was measured by an optical probe. The theoretical and experimental result agreed and the validity of the theory was confirmed. Based on these results, the characteristics of the two‐dimensional acoustic field excited by a normalized IDT were studied.
Design of three‐dimensional IIR digital filters with complex coefficients using spectral transformations
Authors: Sekiguchi Takashi , Takahashi Shin‐Ichi
Published: July 2007

This paper describes a design method of three‐dimensional recursive digital filters with complex coefficients by means of spectral transformations applied to one‐dimensional recursive digital filters with complex coefficients. In multidimensional filters with complex coefficients having an analytic input signal, characteristics can be made arbitrary in the regions in which an input signal frequency component does not exist. Therefore, the degrees of freedom in design increase significantly. Since complex coefficient filters are introduced in the one‐dimensional prototype filter and the spectral transformation function (subfilter), there is no restriction on the cutoff radius in the spherically symmetric filters. In three‐dimensional recursive symmetric fan filters, (cone filters) the design of a passband with an almost arbitrary solid angle becomes possible by the direct transformation from one dimension to three. Also, the stability of the resulting filters is always guaranteed.
Extended pareto optimality concept for multiobjective linear programming problems with fuzzy parameters and its properties
Authors: Sakawa Masatoshi , Takahashi Junya , Yano Hitoshi
Published: July 2007

In order to handle multiobjective linear programming problems containing fuzzy parameters, the authors have already proposed four kinds of α‐feasibility and β‐Pareto optimality, based on the four kinds of index introduced by Dubois et al. This paper discusses the proposed concepts of four kinds of β‐Pareto optimality in further detail, in order to indicate problems with β‐Pareto optimality. As a means of coping with those problems, four kinds of γ‐Pareto optimal solutions are introduced. Then the concept of (α, γ)‐Pareto optimal solution is introduced, by considering simultaneously the α‐feasibility and the γ‐Pareto optimality. It is shown that the set of (α, γ)‐Pareto optimal solutions, which can be regarded as the most optimistic and the most pessimistic, can be found using linear programming.
Design of separable‐denominator two‐dimensional digital filters based on the reduced‐dimensional decomposition of frequency domain specifications
Authors: Deng Tian‐Bo , Kawamata Masayuki
Published: July 2007

This paper proposes a new technique for design of separable‐denominator two‐dimensional digital filters (2DDF·s) in the frequency domain. The technique is based on decomposing both the transfer function of a separable‐denominator 2DDF and the given 2DDF frequency domain specification into a product of two one‐dimensional ones. By these decompositions, the design problem of a separable‐denominator 2DDF can be reduced to the design of two IDDF·s. The technique makes it possible to design separable‐denominator 2DDF·s by utilizing IDDF design techniques directly. Thus stable separable‐denominatro 2DD·s satisfying the given specifications can be designed efficiently.
Functional simulation of color signal processor for VTR by digital dynamics simulation language
Authors: Hayashi Shin‐Ichi , Watanabe Toshinori , Furihata Makoto , Yamamoto Norihisa
Published: July 2007

With the development of semiconductor integration, the technology has arrived at the stage of the system‐on‐chip. With the widespread use of application specific IC (ASIC), the small‐quantity production of diversified types is required. Then it is important to reduce the design period for the mixed analog/digital circuit.

VTR color signal processing LSI is a typical mixed analog/digital circuit. It has the scale of 500 analog elements and 800 digital elements, and it is too time‐comsuming to simulate the operation of the whole LSI by the conventional circuit simulator. Thus, a functional simulator is required for the large‐scale mixed analog/digital LSI.

This paper proposes a functional simulation, employing techniques of continuous system simulation. The technique is applied to the design of a mixed analog/digital circuit, where the conventional method has been unsatisfactory, and the method is shown to be useful in the Functional design of the circuit. The method is based on the modeling of the mixed analog function/circuit, and can be applied to the VTR color signal processing LSI.

The functional simulation can easily be performed with the complete knowledge of the analog function. Consequently, the method can contribute greatly to the quality improvement of the design and the reduction of the design period.
A 64‐points switched‐capacitor discrete fourier transform circuit for high‐speed inverse discrete fourier transform circuit
Authors: Ogihara Akio , Yoneda Shojiro
Published: July 2007

The Discrete Fourier Transform (DFT) and Inverse Discrete Fourier Transform (IDFT) are used for solution of various problems in communications, signal processing and many fields of science. This paper proposes a new method to execute DFT which enables one to realize a high‐speed IDFT circuit with small circuit configuration. In this method, multiplying the DFT equation by the exponential term of the IDFT equation beforehand, IDFT processing is carried out only by addition without increasing the complexity of DFT processing. Using this method, a 64‐points DFT‐IDFT circuit is made on an experimental basis by the switched‐capacitor (SC) technique. In addition, the SC DFT‐IDFT circuit is applied to the recognition of Japanese vowels, and its validity is verified experimentally.
An efficient algorithm for the linear assignment problem
Authors: Yamada Shoichiro , Kasai Tamotsu
Published: July 2007

Although numerous exact algorithms have been proposed so far for the linear assignment problem, they are not necessarily satisfactory from the viewpoint of computation time when considered for application to practical large‐scale problems.

This paper proposes a new algorithm which can reduce the expected computation time needed to find an exact solution for the linear assignment problem by limiting the search space as much as possible within the scope in which no optimal solution is missed.

Here, first, an equation is derived to give an upper bound of the search space so as not to miss an optimal solution in the process of finding an alternating path. Next, data structure is described for developing an operation to limit the search space based on this equation and an assignment algorithm is derived. As the results of experiments, the expected computation time of the algorithm O(n2) for preprocessing and 0(nl.6) for the process of finding an assignment of points were found. In addition, it was shown that the algorithm can be applied to large‐scale problems since in the planar assignment problem for which an assignment cost function is defined in the plane, the expected computation time is 0(n1.6) including preprocessing.
Problems in computer‐aided simulation and design of analog integrated circuits–stability of analog integrated circuits
Authors: Fujii Nobuo
Published: July 2007

This paper describes the problems, mainly from a standpoint of circuit stability, in the case in which we analyze and design analogue integrated circuits using a computer simulation program. Although a fundamental condition of an analogue circuit is whether DC bias can be determined stably or not, computer simulation is not good at this stability check and it is pointed out that an unstable circuit is sometimes checked to be stable accidentally. In the circuit partitioning process used in large‐scale integrated circuits, a risk that is shown in examples is that, depending on the manner of partition, its subcircuit may become unstable and it makes analysis of the whole circuit impossible. As an example we take SPICE, a representative program for analogue circuit simulation, to discuss the problem of default values in the program, direct current bias analysis, one that inside of a computer is assumed to be ideal, and the necessity of transient analysis. Then it clarifies the importance of correct modeling of circuit elements and careful usage of a simulation program after good understanding of its properties.
Sequential analysis for transistor networks including distributed‐constant circuits
Authors: Mizutani Hikaru , Tanaka Mamoru
Published: July 2007

With the recent development of integrated circuit technology, high‐density and high‐speed integrated circuits are produced. Then the wiring capacitance and wiring resistance of the circuit cannot be ignored, and it is necessary to develop a new circuit simulation method considering the parasitic effects of the wiring. The parasitic effect is represented by a distributed‐constant circuit, and a partial differential equation representing the distributed‐constant circuit must be solved to analyze the parasitic effects.

When a partial differential equation is discretized by applying the finite‐element method, however, the analysis of the circuit is reduced to the analysis of the higher‐order equation which requires a tremendous computation time and memory capacity. This paper attempts to avoid this problem, and presents a method in which the circuit is analyzed equivalently without increasing the number of unknowns by applying the sequential analysis to replace the distributed‐constant circuit by three resistors and two current sources.
Analysis of switched networks based on virtual state equation for avoiding singularity problem
Authors: Mizutani Hikaru
Published: July 2007

This paper considers the switched (S) network obtained from the bipolar network by replacing each transistor by its Ebers‐Moll model and further replacing the diode in the model by the switch and the voltage source. The switching (S) control is proposed as a method to determine the operational state of such a network; S control is a method where the S network is analyzed under the assumed switching state S−, and the new switching state S+ is determined based on the result of analysis. The procedure is iterated until S+ = S− is valid.

However, the analysis by S control contains several problems in its execution, such as the singularity problem, where the coefficient matrix of the network equation becomes singular, or the limit cycle problem, where several S states are circulated.

This paper presents a method of analysis for the S network, where virtual capacitors and inductors are added between switch terminals, and the solution is obtained as the steady‐state solution obtained by the numerical integration of the state equation. The singularith problem is dissolved by the proposed method.

It is shown also that some networks, in which the limit cycle phenomenon arises by the conventional method, can be analyzed by the proposed method without the problem. By appropriately setting the values of the capacitors and inductors in the proposed method, the calculation of the inverse matrix can be eliminated in the numerical integration steps, and the high‐speed computation composed only of the additions and multiplications of matrices can be realized.
Separation of mixed voices by acoustic parameter optimization
Authors: Morita Tatsuya
Published: July 2007

The human auditory response is highly adaptable to the environment, enabling voices to be recognized even in a noisy environment. This ability is due primarily to the language processing function in the central auditory nervous system, but the binaural sound locating function also seems to play an important role. From such a viewpoint, the author has presented a method which estimates the sound source locations and separates the voices from more than one speaker using the position information.

A problem in this method is that the acoustic space is assumed as a free space, and the voice is separated based on the sound field model. Consequently, in the actual sound space, the estimation of the source location may be incorrect, thereby making the voice separation inaccurate.

This study proposes a method whereby the separation index is estimated using the evaluation function based on the cross correlation of the separated voices, and the sound parameters are sought in the direction to minimize the evaluation function to improve the voice separation. The effectiveness of the method is verified by an experiment.
Stationary performance of series‐parallel‐type adaptive digital filter based on a logarithmic estimation
Authors: Kobayashi Masaki , Itoh Yosio
Published: July 2007

The series‐parallel ADF is constructed for the unknown system by placing the logarithmic estimation ADF in series and the transversal ADF in parallel. Its features are that the examination of the stability is unnecessary since the transfer function as well as its inverse transfer function of the logarithmic estimation ADF are stable, and the number of taps can be reduced compared to the conventional transversal ADF.

This paper presents the analysis and verification for the steady‐state estimation accuracy for the tap coefficient and the echo elimination, for the case where an additive noise exists at the near end of the series‐parallel ADF. The construction of ADF and the adaptive algorithm based on the LMS method is described first. Using the Taylor series expansion near the solution, the steady‐state algorithm is discussed. Finally, the derived result is verified by a computer simulation indicating that the theory and simulation agree well.
Performance improvement of LMS algorithm
Authors: Takahashi Kiyoshi
Published: July 2007

With the recent rapid progress of VLSI, digital signal processing is used in a wide variety of areas. Recently, the adaptive system has been used widely in many applications.

This paper describes a new algorithm to improve the rate of the adaptation of the LMS (Least Mean Square) algorithm, which is used most commonly as the adaptive filtering algorithm. The new algorithm is based on the dynamics of the network in the Hopfield model, which is the one of the neural networks.

Also, in the new algorithm, the coefficients are updated a few times on each sampled datum. The rate of adaptation of the new algorithm is faster than the rate of the well‐known LMS algorithm. However, the use of the new algorithm requires more operations than the standard LMS algorithm, and it is easy to implement. A system with the rate of the adaptation which does not converge in the conventional LMS algorithm can be realized.
Floating‐point error analysis for recursive least‐square algorithm using ud factorization
Authors: Tsubokawa Hiroshi , Kubota Hajime , Tsujii Shigeo
Published: July 2007

The real‐time processing of the recursive least‐square algorithm is difficult to execute by the conventional Neumann‐type processor because of its large computational complexity. On the other hand, it is known that the recursive least‐square algorithm based on the UD decomposition, which is equivalent to the recursive least‐square algorithm, can be realized by the systolic array proposed by Kung. The systolic array to execute this algorithm is difficult to realize since it requires a tremendous number of elements and corrections.

In the construction of the dedicated hardware, in general, the word length of the processor affects the processing speed and the hardware area. From such a viewpoint, it is important in the construction of the systolic array to execute the recursive least‐square algorithm based on the UD decomposition that the word length of the processor should be minimized. To evaluate the word length, an error analysis is required for the finite word length operation of the recursive least‐square algorithm based on the UD decomposition.

This paper presents the finite word length floating‐point error analysis for the recursive least‐square algorithm, based on the UD decomposition, and evaluates the operation error. Then the convergence of the algorithm and the number of updates of the algorithm are evaluated anlytically. Finally, by a computer simulation, the validity of the theoretical analysis for the convergence and the number of updates is verified.
Number of segments of rectilinear drawings of a graph whose vertices are fixed on a plane
Authors: Takahashi Toshihiko , Kajitani Yoji
Published: July 2007

The graph in which vertices are assigned different coordinates on the xy‐plane is called a rivetted graph. When a rivetted graph G is drawn so that each edge is composed of horizontal and/or vertical segments, it is called a rectilinear drawing of G. This study is an attempt to evaluate the total number of segments l(G) necessary and sufficient for the rectilinear drawing of a rivetted graph G. As a major result, it is shown that l(G)⩽4m and especially, l(G)⩽3m, if a vertex pair does not exist with the same x or y coordinate, using a construction algorithm with the computational complexity of O(m + ξ), where m is the number of edges and ξ is the number of isolated vertices in the graph. For examples of G, nontrivial lower bounds for l(G) also are considered.
Real time signal detection in communication system with additive non‐gaussian noise
Authors: Amano Masaaki
Published: July 2007

Gaussian noise usually is considered as additive noise in the communication system. This paper considers the general communication system with non‐Gaussian noise, and discusses the real‐time detection of the random signal in the system from the stand‐point of the theory of Markov process and Bayes decision. A simulation example is presented for the detection of a phase‐modulated signal.