bluuebunny/crossref_metadata_2025 huggingface dataset:
The design of a multi-micro-computer system
Authors: Fuller S. H. , Siewiorek D. P. , Swan R. J.
Published: July 2004

Continuing advances in semiconductor technology now makes practical the construction of multi-micro-processor systems with tens to hundreds of processors. We are currently involved in the design and construction of a multi-micro-processor system to experimentally investigate the problems of building and programming systems with a large number of processors. The LSI-11 microcomputer is the basic “computer module” that provides processing power and primary memory. The interconnection scheme between the computer modules allows the processors to cooperate in a true multiprocessor fashion: they can share and efficiently access all of primary memory. A number of working groups are now investigating the central problems facing the design and successful application of reliable multi-micro-processor systems and these problems will also be discussed.
Distribution of functions and control in RPCNET
Authors: Franchi Paolo
Published: July 2004

This paper describes the general characteristics and architecture of RPCNET, a distributed computer network for use in the Education and Research area which is being developed in Italy. This project is a joint undertaking of the National Research Council, IBM Scientific Center and a number of Universities and Research Institutes.

In order to match the variety of needs and contraints inherent in the environment in which the network must be developed and made operational, a functional rather than a system approach has been followed in the designing of the Network. The present architecture includes some modifications to the original design which were necessary in order to establish a more definite boundary between applications, interface and communication subnetwork.

The mapping of these functions into physical components is also presented as well as some types of applications.
Tagged architecture and the semantics of programming languages
Authors: Feustel E. A.
Published: July 2004

This research note suggests that before we design hardware or software for the task of problem solving, we re-evaluate the task of problem solving in terms of the linguistic constituents which will be required and the manner in which these linguistic constituents will be combined. Utilizing the principles of composition and abstraction-to-specifics, we conclude that all data and programs might be realized in a structured format called messages. We conclude with a few preliminary thoughts and questions as to how an architecture designed for such structured operands and operators might be designed.
Design data for Algol-60 machines
Authors: Batson A. P. , Brundage R. E. , Kearns J. P.
Published: July 2004

The performance of a high-level language machine will depend upon the characteristics of its workload. Equally, the design for such a machine should be guided by some understanding of the work which it will be called upon to perform. We present here some behavioral properties of a large Algol-60 program in terms of the requests they represent for the various processing resources of an Algol-60 machine. The data provide insight into the behavior of such machines, particularly with respect to dynamic memory requirements and the procedure activation rates associated with direct Algol-60 execution. The data can thus be of value to designers of high-level language machines in view of their implications for the performance of such systems.
Cache memories for PDP-11 family computers
Authors: STRECKER WILLIAM D.
Published: July 2004

This paper gives a summary of the research which led to the design of the cache memory in the DEC PDP-11/70. The concept of cache memory is introduced together with its major organizational parameters: size, associativity, block size, replacement algorithm, and write strategy. Simulation results are given showing how the performance of the cache varies with changes in these parameters. Based on these simulation results the design of the 11/70 cache is justified.
Improving the throughput of a pipeline by insertion of delays
Authors: Patel Janak H. , Davidson Edward S.
Published: July 2004

A pipeline is defined to be a collection of resources, called
segments
which can be kept busy simultaneously. A task once initiated, flows from segment to segment for its execution. A
collision
occurs if two or more tasks attempt to use the same segment at the same time.

The collision characteristics of a pipeline with respect to a schedule of task initiations are investigated. A methodology is presented for modifying the collision characteristics with the insertion of delays so as to increase the utilization of segments and hence the throughput under appropriate scheduling.
A character-oriented context-addressed segment-sequential storage
Authors: Healy Leonard D.
Published: July 2004

The
C
ontext-
A
ddressed
S
egment-
S
equential
S
torage (CASSS) described in this paper provides a solution to the problem of data retrieval from a large, nonpreorganized file. It provides this capability entirely by hardware, eliminating the need for special data structuring solely for the purpose of reducing search time. The major features of the architecture of a character-oriented CASSS system are described, including the basic hardware configuration selected to implement such a system and the set of search instructions chosen to provide a wide variety of search operations useful in information retrieval. Of particular importance in this application is the method of quasi-parallel instruction execution, which allows a full string search of the entire data base in a single cycle of the sequential storage device used.
Price/performance comparison of C.mmp and the PDP-10
Authors: Fuller Samuel H.
Published: July 2004

The analysis in this paper shows a multiprocessor like C.mmp to have a factor of three to four cost/performance advantage over uniprocessor systems such as the PDP-10 when implementations using similar technologies are considered. This comparison is shown to be very sensitive to memory prices and considerable attention is given to normalizing memory costs between C.mmp and the PDP-10.

An important part of this analysis is a comparison of the PDP-10 architecture with the PDP-11 architecture (i.e. the architecture of the processors of C.mmp). When the limited address space of the PDP-11 is not a problem, we see that to a close approximation it takes the same number of PDP-11 instructions (average length 25 bits) as PDP-10 instructions (length 36 bits) to represent a program.

While the comparison in this paper explicitly considers multiprocessor degradation factors such as memory interference, it does not address the problem of writing software systems capable of taking full advantage of the multiprocessor structures. The comparisons in this paper are primarily ofcused on comparing the hardware structures of uniprocessors and multiprocessors. Work is now in progress at CMU that is attempting to evaluate the effectiveness of both individual multiprocessor structures application programs and multiprogrammed systems operating on C.mmp.
The reconfigurable arithmetic processor
Authors: Fiske S. , Dally W. J.
Published: July 2004

The Reconfigurable Arithmetic Processor (RAP) is an arithmetic processing node for a message-passing, MIMD concurrent computer. It incorporates on one chip several serial, 64 bit floating point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units the RAP reduces the amount of off chip data transfer: in the examples we have simulated off chip I/O can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. Simulations predict a peak performance of 20M Flops with 800Mbit/sec off chip bandwidth in a 2μm CMOS process.
A partial-multiple-bus computer structure with improved cost effectiveness
Authors: Jiang H. , Smith K. C.
Published: July 2004

This paper addresses the design and performance analysis of partial-multiple-bus interconnection networks. One such structure, called processor-oriented partial-multiple-bus (or PPMB), is proposed. It serves as an alternative to the conventional structure called memory-oriented partial-multiple-bus (or MPMB) and is aimed at higher system performance at less or equal system cost. PPMB's structural feature, which distinguishes itself from the conventional, is to provide every memory module with
B
paths to processors (where
B
is the total number of buses). This in contrast to the mere
B/g
paths provided in the conventional MPMB structure (where
g
is the number of groups), suggests a potential for higher system bandwidth. This potential is fully fulfilled by the load-balancing arbitration mechanism suggested, which in turn highlights the advantages of the proposed structure. As a result, it has been shown, both analytically and by simulation, that a substantial increase in system bandwidth (up to 20%) is achieved by the PPMB structure over the MPMB structure. In addition to the fact that the cost of PPMB is less than, or equal to, that of MPMB, its reliability is shown to be slightly increased as well.
Toward a dataflow/von Neumann hybrid architecture
Authors: Iannucci R. A.
Published: July 2004

Dataflow architectures offer the ability to trade program level parallelism in order to overcome machine level latency. Dataflow further offers a uniform synchronization paradigm, representing one end of a spectrum wherein the unit of scheduling is a single instruction. At the opposite extreme are the von Neumann architectures which schedule on a task, or process, basis.

This paper examines the spectrum by proposing a new architecture which is a
hybrid
of dataflow and von Neumann organizations. The analysis attempts to discover those features of the dataflow architecture, lacking in a von Neumann machine, which are essential for tolerating latency and synchronization costs. These features are captured in the concept of a
parallel machine language
which can be grafted on top of an otherwise traditional von Neumann base. In such an architecture, the units of scheduling, called
scheduling quanta
, are bound at compile time rather than at instruction set design time. The parallel machine language supports this notion via a large synchronization name space.

A prototypical architecture is described, and results of simulation studies are presented. A comparison is made between the MIT Tagged-Token Dataflow machine and the subject machine which presents a model for understanding the cost of synchronization in a parallel environment.
Resource requirements of dataflow programs
Authors: Culler D. E. , Arvind
Published: July 2004

Parallel execution of programs requires more resources and more complex resource management than sequential execution. If concurrent tasks can be spawned dynamically, programs may require an inordinate amount of resources when the potential parallelism in the program is much greater than the amount of parallelism the machine can exploit. We describe
loop bounding
, a technique for dynamically controlling the amount of parallelism exposed in dataflow programs. The effectiveness of the technique in reducing token storage requirements is supported by experimental data in the form of
parallelism profiles
and
waiting-token profiles
. Comparisons are made throughout with more conventional approaches to parallel computing.
A kernel-independent, pipelined architecture for real-time 2-D convolution
Authors: Shukla S. B. , Agrawal D. P.
Published: July 2004

Existing architectures for 2-D convolution suffer from such drawbacks as inflexibility with respect to image and/or kernel sizes (systolic arrays) or data distribution and collection overhead (SIMD processor arrays). This paper introduces a pipelined architecture that maps different sizes and shapes of kernels on a fixed size array of computing elements using a single pass of the input data. It is shown that the array can be operated at its highest throughout for any kernel size. Interfacing this architecture with the host requires receiving and outputting data in a simple raster-scan fashion.
Multiprocessor cache analysis using ATUM
Authors: Sites R. L. , Agarwal A.
Published: July 2004

The design of high-performance multiprocessor systems necessitates a careful analysis of the memory system performance of parallel programs. Lacking multiprocessor address traces, previous multiprocessor performance studies using analytical models had to make an inordinate number of assumptions about the underlying memory reference patterns. We previously developed a scheme called ATUM - Address Tracing Using Microcode - to get reliable operating system and multiprogramming traces on single processors. This paper briefly describes the multiprocessor extension of ATUM and its implementation on a VAX 8350 multiprocessor. We also report on our use of the resulting traces to analyze physical versus virtual addressing of large caches, process-identifier hashing in virtual caches, cache interference between multiple processes, cache interference between multiple CPUs, process affinity, and semaphore usage in writeback caches.
Trade-offs between devices and paths in achieving disk interleaving
Authors: Ng S. , Lang D. , Selinger R.
Published: July 2004

There is a continuing need to improve the performance of disk subsystems, and one of the key factors of a disk subsystem's performance is the data transfer rate. While it is clear that increasing the data transfer rate would reduce the service time for those applications that move large amounts of data per I/O, the amount of data transferred per I/O in many of today's typical commercial applications is relatively small. The benefit of a higher data rate in these environments was not well understood, but is explored here and is found to be larger than expected.

One way to increase the data rate of the disk subsystem is through a technique generally known as striping. Using this approach, multiple conventional disks are grouped together and function as if they were a single one, with the data spread among the multiple disks and transferred in parallel. In this paper, we study four alternative implementations for achieving higher data rates in a disk subsystem, focusing on the trade-offs between the number of devices and the number of data paths, keeping the number of physical devices constant (which may keep the cost roughly constant). The performance advantages and limitations of the alternative implementations are analyzed using an analytic queuing model and compared to a conventional disk subsystem.
The white dwarf: a high-performance application-specific processor
Authors: Wolfe A. , Breternitz M. , Stephens C. , Ting A. L. , Kirk D. B. , Bianchini R. P. , Shen J. P.
Published: July 2004

This paper presents the design and implementation of a high-performance special-purpose processor, called The White Dwarf, for accelerating finite element analysis algorithms. The White Dwarf CPU contains two Am29325 32-bit floating-point processors and one Am29332 32-bit ALU, and employs a wide-instruction word architecture in which the application algorithm is directly implemented in microcode. The entire system is VME-bus compatible and interfaces with a SUN 31160 host. The system's potential peak performance is 20 MFLOPS; a sustained computation rate in excess of 15 MFLOPS is expected. A potential speedup of between one and two orders of magnitude is possible. With a fully populated memory subsystem, the White Dwarf can accommodate finite element problems involving up to half a million nodes. The system is designed using an approach called Application-Specific Processor Design. A retargetable compiler has been developed which is capable of generating highly parallel and efficient code for the White Dwarf and other processors with similar architecture. System debuglintegration is in progress; a highly useful system is expected
.
Solving partial differential equations in a data-driven multiprocessor environment
Authors: Gaudiot J. L. , Lin C. M. , Hosseiniyar M.
Published: July 2004

Partial differential equations can be found in a host of engineering and scientific problems. The emergence of new parallel architectures has spurred research in the definition of parallel PDE solvers. Concurrently, highly programmable systems such as data-flow architectures have been proposed for the exploitation of large scale parallelism. The implementation of some Partial Differential Equation solvers (such as the Jacobi method) on a tagged token data-flow graph is demonstrated here. Asynchronous methods (chaotic relaxation) are studied and new scheduling approaches (the Token No-Labeling scheme) are introduced in order to support the implementation of the asynchronous methods in a data-driven environment. New high-level data-flow language program constructs are introduced in order to handle chaotic operations. Finally, the performance of the program graphs is demonstrated by a deterministic simulation of a message passing data-flow multiprocessor. An analysis of the overhead in the data-flow graphs is undertaken to demonstrate the limits of parallel operations in data-flow PDE program graphs.
An evaluation of directory schemes for cache coherence
Authors: Agarwal A. , Simoni R. , Hennessy J. , Horowitz M.
Published: July 2004

The problem of cache coherence in shared-memory multiprocessors has been addressed using two basic approaches: directory schemes and snoopy cache schemes. Directory schemes have been given less attention in the past several years, while snoopy cache methods have become extremely popular. Directory schemes for cache coherence are potentially attractive in large multiprocessor systems that are beyond the scaling limits of the snoopy cache schemes. Slight modifications to directory schemes can make them competitive in performance with snoopy cache schemes for small multiprocessors. Trace driven simulation, using data collected from several real multiprocessor applications, is used to compare the performance of standard directory schemes, modifications to these
schemes, and snoopy cache protocols
.
Performance tradeoffs in cache design
Authors: Prybylski S. , Horowitz M. , Hennessy J.
Published: July 2004

Cache memories have become common across a wide range of computer implementations. To date, most analyses of cache performance have concentrated on time independent metrics, such as miss rate and traffic ratio. This paper presents a series of simulations that explore the interactions between various organizational decisions and program execution time. We investigate the tradeoffs between cache size and CPU/Cache cycle time, set associativity and cycle time, and between block size and main memory speed. The results indicate that neither cycle time nor cache size dominates the other across the entire design space. For common implementation technologies, performance is maximized when the size is increased to the 32KB to 128KB range with modest penalties to the cycle time. If set associativity impacts the cycle time by more than a few nanoseconds, it increases overall execution time. Since the block size and memory transfer rate combine to affect the cache miss penalty, the optimum block size is substantially smaller than that which minimizes the miss rate. Finally, the interdependence between optimal cache configuration and the main memory speed necessitates multi-level cache hierarchies for high performance uniprocessors.
A characterization of sharing in parallel programs and its application to coherency protocol evaluation
Authors: Eggers S. J. , Katz R. H.
Published: July 2004

In this paper we use trace-driven simulation to analyze the memory reference patterns of write shared data in several parallel applications. We first develop a characterization of write sharing (based on the notion of a write run), and then examine the traces, using metrics derived from the characterization. The results indicate that the amount of write sharing in all programs is small; and that it is characterized by short to medium sequences of per processor references, with little contention for either data or locks.

We determine to what extent this analysis can be used to predict the coherency overhead of write-invalidate and write-broadcast protocols. We develop a simple model of write sharing from the write run characterization. By applying the results of the sharing analysis to the model, weighted by machine-specific cycle costs for carrying out coherency-related bus operations, we can estimate relative protocol performance. We compare these results to those from detailed architectural simulations.

The simulation results indicate that (1) neither protocol dominates in performance; and that (2) the write run model is a good predictor of protocol performance when the unit of the coherency operations matches that in the sharing analysis. This is the case for the write-broadcast protocols, in which one word is broadcast for each write to shared data. However, in Berkeley Ownership, a write-invalidate protocol, the unit of coherency is an entire cache block. When the block size is large, performance for this protocol is quite sensitive to the memory reference patterns within the block.
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
Authors: Goodman J. R. , Woest P. J.
Published: July 2004

The
Wisconsin Multicube
, is a large-scale, shared-memory multiprocessor architecture that employs a snooping cache protocol over a grid of buses. Each processor has a conventional (SRAM) cache optimized to minimize memory latency and a large (DRAM) snooping cache optimized to reduce bus traffic and to maintain consistency. The large snooping cache should guarantee that nearly all the traffic on the buses will be generated by I/O and accesses to shared data.

The programmer's view of the system is like a multi -- a set of processors having access to a common shared memory with no notion of geographical locality. Thus writing software, including the operating system, should be a straightforward extension of those techniques being developed for multis.

The interconnection topology allows for a cache-coherent protocol for which most bus requests can be satisfied with no more than twice the number of bus operations required of a single-bus multi. The total symmetry guarantees that there are no topology-induced bottlenecks. The total bus bandwidth grows in proportion to the product of the number of processors and the average path length.

The proposed architecture is an example of a new class of interconnection topologies -- the
Multicube
-- which consists of

N =n
k

processors, where each processor is connected to
k
buses and each bus is connected to
n
processors. The hypercube is a special case where
n
=2. The Wisconsin Multicube is a two-dimensional Multicube (
k
=2), where
n
scales to about 32, resulting in a proposed system of over 1,000 processors.
Markov chain models for analyzing memory interference in multiprocessor computer systems
Authors: Bhandarkar Dileep P. , Fuller Samuel H.
Published: July 2004

This paper discusses various analytical techniques for studying the extent of memory interference in a multiprocessor system with a crosspoint switch for processor-memory communication. Processor behavior is simplified to an ordered sequence of a memory request followed by an interval of processing time. The system is assumed to be bus bound; in other words, by the time the processor-memory bus completes servicing a processor's request the processor is ready to initiate another request and the memory module is ready to accept another request. The techniques discussed include discrete and continuous time Markov chain models as well as several approximate analytic methods.
Interconnecting a distributed processor system for avionics
Authors: Anderson George A.
Published: July 2004

This paper describes the interconnection scheme devised for an advanced Air Force system concept called Distribution Processor/Memory (DP/M) in which topologically irregular networks of small computers are used to perform avionics processing. The interconnection scheme involves the use of a combination of global and point-to-point busses to handle message traffic in predominantly homogeneous systems of from 5 to 20 computers. The major features of the scheme are the use of biphase bit-serial transmission, associatively addressed messages, and a method for reconfiguration of the point-to-point communications paths under program control. It is expected that the scheme may have general applicability to other distributed processing systems, particularly other real-time systems employing limited-capability processors.
Structure of digital system description languages
Authors: Jordan Harry F. , Smith Burton J.
Published: July 2004

Several languages have been developed for or applied to the problem of describing digital hardware systems. This paper points out some of the problems encountered in hardware descriptions, particularly where they are distinct from concepts appearing in programming languages.
VDL—a Definition system for all levels
Authors: Lee John A. N.
Published: July 2004

The VDL system for the description of programming languages which was originally used for the definition of PL/I is extended to the description of processors. This paper shows the relationship between the language of definition and the abstract machine over which the semantics of the language are specified. It is demonstrated that the level of description can be chosen to suit the various needs of the computing community, each level being well nested within its outer level, whilst using only one language of definition.

From the point of view of processor design, indications are given of the means by which a description can be transformed into an implementable system of data paths, registers and drivers.
A methodology for parallel processing design tradeoffs
Authors: Radoy Charles H. , Copeland George P. , Lipovski G. J.
Published: July 2004

A methodology is developed for determining how much parallelism is optimal if a given job stream is to be executed without multiprogramming. Qualitative design tradeoffs are inferred from the cost-performance effect of parallelism on different hardware subsystems. Measures of software parallelism are analytically related to measures of hardware performance. It is shown that an increase in hardware parallelism may be desirable even though it causes an increase in job processing cost and/or a decrease in hardware efficiency.
DAP—a distributed array processor
Authors: Reddaway S. F.
Published: July 2004

An array of very simple processing elements is described each with a local semiconductor store. The array may also be used as main storage.

Bit-organisation gives great flexibility, including the minimisation of word length. Use of MSI and LSI is helped by the simplicity of the serial design. Using 15-bit fixed point, the theoretical performance of a 72 × 128 array is about 10
8
multiplications or 10
9
additions per second. Comparisons are made with other architectures.

Meteorology is considered as an application. It is attractive to have the whole problem in the array storage.
Maximal rate pipelined solutions to recurrence problems
Authors: Kogge Peter M.
Published: July 2004

An m
th
order recurrence problem is defined as the computation of X
1
, . . . X
N
, where X
i
=f (
a
i
, X
i-1
, . . X
i-m
) and
a
i
is a set of parameters. On a pipelined computer, where the total stage delay in computing f is d
f
time units, the solution output rate is one new X
i
each d
f
time unit. This paper describes a method for increasing this rate to 1 per time unit when the function f has certain simple functional properties. The total stage delay and complexity of the resulting pipelines are also described.
Flowware—a flow charting procedure to describe digital networks
Authors: Omohundro Wayne E. , Tracey James H.
Published: July 2004

FLOWWARE is an interactive, graphical language to aid in the understanding and design of digital networks. The language is based upon the concept of flow charting. The user specifies the register layout of the network and the sequential operation in the form of a flow chart on a graphics terminal. The flow chart allows a user who is unfamiliar with the network to easily understand the function and operation of the network.
Automated exploration of the design space for register transfer (RT) systems
Authors: Barbacci Mario R. , Siewiorek Daniel P.
Published: July 2004

A Design Automation System for the RT level of design is described. The System explores the design space by finding alternative implementations for a user given behavioral specification. The alternative solutions are obtained by transformations on a graph model. These transformations effect trade-offs between the cost of the hardware and the speed of the algorithm. Heuristic routines are used to reduce the design space by exploring only those alternatives whose characteristics approach a user given set of goals.
Implementation aspects of the symbol hardware compiler
Authors: Laliotis T. A.
Published: July 2004

One of the most outstanding features of the SYMBOL computer is its high level hardware compiler. This paper presents some aspects of the hardware implementation including the network characteristics of the communication scheme between compiler, system supervisor, and Memory Controller, the functional breakdown into distinct sections for implementation, the support hardware (registers, tables, etc.,), the Name Table structure, and some of the linking techniques for the structured output of the compiler.
The architecture of CASSM
Authors: Copeland George P. , Lipovski G. J. , Su Stanley Y.W.
Published: July 2004

This paper presents the architecture of a context-addressed cellular system for non-numeric information processing, using an inexpensive, large-capacity circulating memory device. The system allows data to be represented in a structure very close to the form as the user perceives it (information structure) and allows the search operations of high level queries to be implemented directly. The information structures currently used in existing information systems are described. Then the architecture of the system as a whole is presented, as well as the implementation of these information structures as basic data types and hardware management of storage allocation and garbage collection.

The paper intends to demonstrate that distributing intelligence throughout a rotating memory device can decrease the time required for search operations in large data bases. And that the search strategy and storage management functions can be efficiently carried out in hardware, greatly simplifying the software of information systems. Thus, data not only becomes faster but easier to access, verify, insert and delete.
Deriving design guidelines for diagnosable computer systems
Authors: Hemphill John M. , Szygenda S. A.
Published: July 2004

Diagnosable computer systems are designed to detect and isolate the faults that occur during system operation. A number of techniques are available to the system designer of diagnosable systems. This paper examines a number of these techniques and derives a set of design guidelines incorporating them.
Design of fault-tolerant associative processors
Authors: Parhami Behrooz , Avizienis Algirdas
Published: July 2004

Recent advances in computer technology have made the design of large and very flexible associative processors possible. Such systems are extremely complex and must be adequately protected against failures if they are to be used in critical application areas such as air traffic control or for performing control functions in fault-tolerant computers. This paper summarizes the results of a study which has indicated the techniques that are applicable in the design of fault tolerant associative processors. Associative processors are divided into four classes of fully parallel, bit-serial, word-serial, and block-oriented systems. A technique for modularizing the design of an associative processor is given. The detection of errors within modules is discussed for the four classes mentioned above. Several schemes for reconfiguration are discussed which allow us to establish an appropriate inter-communication pattern after replacing the faulty module by a spare. The design of a fault-tolerant associative processor, which uses some of the techniques discussed previously, is presented.
A fault tolerant multiprocessor architecture for real-time control applications
Authors: Fischler M. A. , Firschein O.
Published: July 2004

This paper presents a fault tolerant multiprocessor architecture suitable for real time control applications requiring an extremely high degree of reliability. The architecture satisfies the following requirements:

l) Ability to deal with software as well as hardware faults: The proposed architecture is based on the assignment of distinct but redundant software modules to each task.

2) Efficient use of resources: The proposed architecture is a multiprocessor using time redundancy for fault correction. Thus, redundancy (beyond that needed for fault detection) is invoked only when a fault is detected. In normal operation, this extra capacity is available as an additional computing resource.

3) No hard core: In addition to the usual replication of system components, a partitioned system executive and a unique communication facility is defined which insures that the available redundancy will not be lost through a “domino” effect.

4) Interaction of computing units with sensors and effectors: The manner in which system architecture must be responsive to the amount and type of redundancy provided by the sensors and effectors is shown.

5) Use of current technology: The proposed architecture is based on the use of currently available hardware for the major system components.

After a detailed description of the architecture and the method of system operation, the system is related to existing fault tolerant systems, and unique characteristics of the present design are indicated.
Simulation exercises for computer architecture education
Authors: Knoke P. J.
Published: July 2004

In a case studies approach to computer architecture education, there is a need for small-scale simulation exercises to illustrate significant concepts and to provide hands-on student experience with architectural tradeoffs. Two such exercises are discussed, and one is described in some detail. The exercises cover virtual memory and multiprogramming systems' architecture, and are suitable as projects students can do within a ten-week academic quarter. Some hindsight based on student reaction to these exercises is provided, together with estimated costs to the educator and students for exercise development and execution.
Review of the workshop on computer architecture education
Authors: Rossmann George
Published: July 2004

This paper reviews the presentations and discussions of the participants in the Workshop on Education and Computer Architecture held in Atlanta, Georgia on 30 August 1973.
Computer Modules
Authors: Fuller S. H. , Siewiorek D. P. , Swan R. J.
Published: July 2004

This paper describes the architecture of Computer Modules, or CMs. They are large digital modules of about minicomputer complexity that are specifically designed to take advantage of the rapidly advancing semiconductor technology. These modules are intended to be interconnected into systems that implement a wide range of computational structures. The main features of a CM include a small processor as the primary control element and memory distributed among the CMs in the system rather than centralized into memory modules as in current multiprocessors. CMs are interconnected into a network via buses that each have their own virtual address space to facilitate efficient inter-module memory sharing. This paper includes an ISP description of the address translation mechanisms as well as a discussion of several important implementation issues such as the avoidance of deadlocks in CM networks and the width of the inter-CM buses.
Design of a fully variable-length structured minicomputer
Authors: Vranesic Z. G. , Hamacher V. C. , Leung Y. Y.
Published: July 2004

Binary-based and fixed-length structure computers are often inconvenient and wasteful of resources. In this paper we present a design for a fully variable-length structured minicomputer. Since all parameters (instructions and data) are unrestricted in length, their boundaries and interpretation are effected by special delimiter codes. For practical reasons (dictated by current technology) the machine utilizes a binary-coded decimal number representation.
Happe Honeywell Associative Parallel Processing Ensemble
Authors: Marvel Orin E.
Published: July 2004

Many problems, inherent in air traffic control, weather analysis and prediction, nuclear reaction, missile tracking, and hydrodynamics have common processing characteristics that can most efficiently be solved using parallel “non-conventional” techniques. Because of high sensor data rates, these parallel problem solving techniques cannot be economically applied using the standard sequential computer.

The application of special processing techniques such as parallel/associative processing are still resisted because it is a change from the norm. Past implementations utilized special hardware, custom circuits and complex designs. The Honeywell Associative Parallel Processing Ensemble (HAPPE) was built to demonstrate the basic simplicity of hardware concepts inherent in parallel associative processing. HAPPE is implemented with the same standard circuit building blocks (MSI's, ROM's, and RAM's) that are used in all conventional computers. By using standard building blocks a long time objection to associative memory systems, that of requiring special purpose (low usage) circuits is overcome.

The parallel/associative processing element can be both powerful and versatile. The HAPPE architecture proves that one processor element can perform both correlation (associative) and arithmetic processing. The HAPPE demonstrator has become a valuable tool in training system designers and programmers to recognize that new “thinking” can be applied to advanced processing system implementations.
A computer architecture and its programming language
Authors: Schaffner Mario R.
Published: July 2004

Computer architectures and programming languages are traditionally developed indepen
d
ently. Through suitable computer architecture, for instance, one can attempt to speed up the processing of a stream of data and instructions, leaving to the software the burden of preparing these streams. Through a suitable programming language, one aims at efficiently describing many classes of problems, in a phrase-structure form that is machine indepen
d
ent. This approach has led to the ever-increa
s
ing application of computers, but it has also brought about a growing complexity in the sof
t
ware systems. As a consequence of the latter, there is a new trend toward extending hardware implementation to replace the software ones, especially in view of the new technology of large scale integration.
Transactional lock-free execution of lock-based programs
Authors: Rajwar Ravi , Goodman James R.
Published: July 2004

This paper is motivated by the difficulty in writing correct high-performance programs. Writing shared-memory multi-threaded programs imposes a complex trade-off between programming ease and performance, largely due to subtleties in coordinating access to shared data. To ensure correctness programmers often rely on conservative locking at the expense of performance. The resulting serialization of threads is a performance bottleneck. Locks also interact poorly with thread scheduling and faults, resulting in poor system performance.We seek to improve multithreaded programming trade-offs by providing architectural support for optimistic lock-free execution. In a lock-free execution, shared objects are never locked when accessed by various threads. We propose
Transactional Lock Removal
(TLR) and show how a program that uses lock-based synchronization can be executed by the hardware in a lock-free manner, even in the presence of conflicts, without programmer support or software changes. TLR uses timestamps for conflict resolution, modest hardware, and features already present in many modern computer systems.TLR's benefits include improved programmability, stability, and performance. Programmers can obtain benefits of lock-free data structures, such as non-blocking behavior and wait-freedom, while using lock-protected critical sections for writing programs.
Speculative synchronization
Authors: Martínez José F. , Torrellas Josep
Published: July 2004

Barriers, locks, and flags are synchronizing operations widely used programmers and parallelizing compilers to produce race-free parallel programs. Often times, these operations are placed suboptimally, either because of conservative assumptions about the program, or merely for code simplicity.We propose
Speculative Synchronization,
which applies the philosophy behind Thread-Level Speculation (TLS) to explicitly parallel applications. Speculative threads execute past active barriers, busy locks, and unset flags instead of waiting. The proposed hardware checks for conflicting accesses and, if a violation is detected, offending speculative thread is rolled back to the synchronization point and restarted on the fly. TLS's principle of always keeping a
safe thread
is key to our proposal: in any speculative barrier, lock, or flag, the existence of one or more safe threads at all times guarantees forward progress, even in the presence of access conflicts or speculative buffer overflow. Our proposal requires simple hardware and no programming effort. Furthermore, it can coexist with conventional synchronization at run time.We use simulations to evaluate 5 compiler- and hand-parallelized applications. Our results show a reduction in the time lost to synchronization of 34% on average, and a reduction in overall program execution time of 7.4% on average.
Temporally silent stores
Authors: Lepak Kevin M. , Lipasti Mikko H.
Published: July 2004

Recent work has shown that silent stores--stores which write a value matching the one already stored at the memory location--occur quite frequently and can be exploited to reduce memory traffic and improve performance. This paper extends the definition of silent stores to encompass sets of stores that change the value stored at a memory location, but only temporarily, and subsequently return a previous value of interest to the memory location. The stores that cause the value to revert are called temporally silent stores. We redefine multiprocessor sharing to account for temporal silence and show that in the limit, up to 45% of communication misses in scientific and commercial applications can be eliminated by exploiting values that change only temporarily. We describe a practical mechanism that detects temporally silent stores and removes the coherence traffic they cause in conventional multiprocessors. We find that up to 42% of communication misses can be eliminated with a simple extension to the MESI protocol. Further, we examine application and operating system code to provide insight into the temporal silence phenomenon and characterize temporal silence by examining value frequencies and dynamic instruction distances between temporally silent pairs. These studies indicate that the operating system is involved heavily in temporal silence, in both commercial and scientific workloads, and that while detectable synchronization primitives provide substantial contributions, significant opportunity exists outside these references.
Bytecode fetch optimization for a Java interpreter
Authors: Ogata Kazunori , Komatsu Hideaki , Nakatani Toshio
Published: July 2004

Interpreters play an important role in many languages, and their performance is critical particularly for the popular language Java. The performance of the interpreter is important even for high-performance virtual machines that employ just-in-time compiler technology, because there are advantages in delaying the start of compilation and in reducing the number of the target methods to be compiled. Many techniques have been proposed to improve the performance of various interpreters, but none of them has fully addressed the issues of minimizing redundant memory accesses and the overhead of indirect branches inherent to interpreters running on superscalar processors. These issues are especially serious for Java because each bytecode is typically one or a few bytes long and the execution routine for each bytecode is also short due to the low-level, stack-based semantics of Java bytecode. In this paper, we describe three novel techniques of our Java bytecode interpreter,
write-through top-of-stack caching (WT), position-based handler customization (PHC), and position-based speculative decoding (PSD),
which ameliorate these problems for the PowerPC processors. We show how each technique contributes to improving the overall performance of the interpreter for major Java benchmark programs on an IBM POWER3 processor. Among three, PHC is the most effective one. We also show that the main source of memory accesses is due to bytecode fetches and that PHC successfully eliminates the majority of them, while it keeps the instruction cache miss ratios small.
Understanding and improving operating system effects in control flow prediction
Authors: Li Tao , John Lizy Kurian , Sivasubramaniam Anand , Vijaykrishnan N. , Rubio Juan
Published: July 2004

Many modern applications result in a significant operating system (OS) component. The OS component has several implications including affecting the control flow transfer in the execution environment. This paper focuses on understanding the operating system effects on control flow transfer and prediction, and designing architectural support to alleviate the bottlenecks. We characterize the control flow transfer of several emerging applications on a commercial operating system. We find that the exception-driven, intermittent invocation of OS code and the user/OS branch history interference increase the misprediction in both user and kernel code.We propose two simple OS-aware control flow prediction techniques to alleviate the destructive impact of user/OS branch interference. The first one consists of capturing separate branch correlation information for user and kernel code. The second one involves using separate branch prediction tables for user and kernel code. We study the improvement contributed by the OS-aware prediction to various branch predictors ranging from simple Gshare to more elegant Agree, Multi-Hybrid and Bi-Mode predictors. On 32K entries predictors, incorporating OS-aware techniques yields up to 34%, 23%, 27% and 9% prediction accuracy improvement in Gshare, Multi-Hybrid, Agree and Bi-Mode predictors, resulting in up to 8% execution speedup.