bluuebunny/crossref_metadata_2025 huggingface dataset:
A Robust SOI Gain-Boosted Operational Amplifier Targeting High Temperature Precision Applications up to 300°C
Authors: Schmidt Alexander , Marzouk Abdel Moneim , Kappert Holger , Kokozinski Rainer
Published: October 2015

Data acquisition and signal processing at elevated temperatures are facing various problems due to a wide temperature range operation, affecting the accuracy of the circuits' references and elementary building blocks. As the most commonly used analog building block, the operational amplifier (op-amp) with its various limitations has to be enhanced for wide temperature range operation. Thereby major effort is put into maximizing signal gain and simultaneously reaching high gain-bandwidth also for high temperatures. Future robust design approaches have to consider a growing operating temperature range and increasing device parameter mismatch due to the downsizing of integrated circuits. Addressing one of the major problems in circuit design for the next decades, compensating these effects through new design approaches will have a lasting impact on circuit design. In this paper we present a high gain operational amplifier with a folded-cascode and gain-boosted input stage, fabricated in a 1.0 μm SOI CMOS process. The operational amplifier was designed for an operating temperature range of −40…300°C. Major effort was put into a robust design approach with reduced sensitivity to temperature variations, targeting high precision applications in a high temperature environment. With a supply voltage of 5 V, the maximum simulated current consumption of the op-amp is 210 μA which leads to overall maximum power consumption of 1.05 mW. The open loop DC gain of the amplifier is expected to reach a minimum of 108 dB and a unity-gain-frequency of 1.02 MHz at a temperature of 300°C. For all temperatures the phase margin varies from 55…70 degrees for a 3 pF load.
High Temperature Endurance of Packaged SOI Devices for Signal Conditioning and Processing Applications
Authors: Riches S T , Johnston C , Sousa M , Grant P
Published: October 2015

Silicon on Insulator (SOI) device technology is fulfilling a niche requirement for electronics that functions satisfactorily at operating temperatures of >200°C. Most of the reliability data on the high temperature endurance of the devices is generated on the device itself with little attention being paid to the packaging technology around the device. Similarly, most of the reliability data generated on high temperature packaging technologies uses testpieces rather than real devices, which restricts any conclusions on long term electrical performance.

This paper presents results of high temperature endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 7,056 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C. Different die attach and wire bond options have been included in the study and the performance of multiplexers, transistors, bandgap voltage, oscillators and voltage regulators functional blocks have been characterised.

This work formed part of the UPTEMP project which was set-up with support from UK Technology Strategy Board and the EPSRC. The project brought together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.
Investigation into the Role of Different Substrate Ni Compositions and Plating Methods on Die Attach Reliability
Authors: Cui Jinzi , Johnson R. Wayne , Hamilton Michael C.
Published: October 2015

Nickel is a commonly used diffusion barrier for direct bond copper (DBC) substrates used in high temperature, high power applications. The Ni can be deposited by electroless or electrolytic plating and may be pure Ni, Ni:P, Ni:B or Ni:Co. The reactivity of these different Ni layers with AuGe and BiAgX® solder is explored. Specifically the reaction to form Ni-Ge intermetallics and NiBi3 during high temperature storage and the impact on die shear strength and failure mode are discussed.
“Turning ceramic on its head” – a polymer based packaging system for operation over 175°C
Authors: Tremlett Piers R.
Published: October 2015

A polymer based electronic packaging system has been developed that is capable of operating at temperatures over 175°C and up to 225°C. This system is being developed to be a lead free, non-hermetic and able to deliver miniature or functionally dense circuits. It will be suitable for sensor systems where amplification, signal digitisation and autonomy are important whilst operating in a harsh environment such as high temperature.
High-Temperature Trench Capacitors, Using Thin-Film ALD Dielectrics
Authors: Dietz Dorothee , Celik Yusuf , Goehlich Andreas , Vogt Holger , Kappert Holger
Published: October 2015

High-temperature passive electronic becomes more and more important, e.g. in the field of deep drilling, aerospace or in automobile industry. For these applications, capacitors are needed, which are able to withstand temperatures up to 300 °C, which exhibit a low leakage current at elevated temperatures, a breakdown voltage above the intended operating voltage and a high capacitive density value.

In this paper, investigations of 3D-integration and atomic layer deposition (ALD) techniques to achieve these features are presented. A highly n-doped Si-substrate acts as a bottom electrode. Medium- and high-k dielectrics represent the insulator and the upper electrode consists of Ru, TiN or TiAlCN. The materials can be used at elevated temperatures. At room temperature, the leakage current is less than 10 pA/mm2 without showing a soft-breakdown up to ± 15 V, indicating the absence of Fowler-Nordheim tunneling. At 300 °C and at 3 V the leakage current amounts about 1 nA/mm2 and at 5 V a soft-breakdown is detected.
Inorganic Insulated Metal Substrates
Authors: Shashkov Pavel , Curtis Steven , Humpston Giles
Published: October 2015

Insulated metal substrates (IMS) are gaining ground in electronics applications thanks to their high thermal conductivity and low cost. However, the organic dielectrics (such as epoxy or polyimide based material) traditionally used on IMS are limited by their maximum operating temperature, generally to below 150–200 °C. Thus in high temperature applications manufacturers are restricted to using expensive inorganic substrates such as alumina (Al2O3), aluminium nitride (AlN) or silicon nitride (Si3N4). A cost-effective IMS with an inorganic dielectric would be an attractive alternative for high temperature electronics.

Cambridge Nanotherm has developed an electrochemical process for building inorganic dielectric ceramic onto a metal base. Nanotherm ceramic material is nanocrystalline alumina with a grain size of 20 to 60 nanometres. This grain size plays a critical role in providing the dielectric layer with its unique combination of properties such as high thermal conductivity (6–7 W/mK), high dielectric strength (>50 V/um) and formability when applied on thin, foil-type substrates. The Nanoceramic layer can be built from 3 to 50 microns thick, depending on the breakdown voltage required. This avoids excessive dielectric thickness that unnecessarily increases the thermal resistance of the system. The electric circuit is built onto the ceramic surface using either PVD metal sputtering followed by galvanic metal build up or conventional thick film processing. The result is a cost-effective, easy to process and use inorganic substrate with a thermal conductivity around 150 W/mK and a maximum working temperature above 350 °C.

This paper will present an overview of the key electrical and thermal properties of Nanoceramic aluminium substrates and their manufacturing process. Potential use in the thermal management of high temperature electronic devices will be discussed with reference to some applications.
High Temperature (225 °C) SiC – Based Wireless Power Demonstrator
Authors: Kegley L.E. , Garrett J. , Minden S. , Fraley J.
Published: October 2015

A high temperature, SiC-based wireless power demonstrator has been demonstrated by APEI engineers under Air Force Research Lab (AFRL) funding. The system consists of high temperature (> 225 °C) assembly processes and materials, including the ceramic substrate, die attach, and components. The wireless power transfer is demonstrated at different distances with respect to temperature. This system has significant implications for extreme environment applications which would benefit from condition-based monitoring.
Multi-bit memory cell using long-range non-anchored actuation for high temperature applications
Authors: Elyasi Mehrdad , Lee Chengkuo , Hsieh Cheng-Yu , Kwong Dim-Lee
Published: October 2015

A novel micro-electro-mechanical (MEM) based non-volatile memory (NVM) is proposed. The storage principle is based on Lorentz's transduction, utilizing long-range motion of a non-anchored element which has current carrying sliding contact with a conductive path. Position of the moving element indicates the stored data in the multi-bit cell. Data is written in the cell with displacing the moving element by Lorentz's force, is read by utilizing differential port resistances, and is held by adhesion forces. Data writing at up to 300°C, and data retention and reading for higher temperatures are reliable.
Demonstration of a 300°C Capable Directional Drilling Steering Tool (DM300)
Authors: MacGugan D
Published: October 2015

Honeywell Aerospace, along with Applied Physics Systems, Sunnyvale, CA, has developed 300°C capable directional sensor technology in support of the U.S. Department of Energy's Enhanced Geothermal Technologies initiative. The development has culminated in fabrication of custom silicon-on-insulator IC's, fabrication and assembly of ceramic hybrid electronics, and the directional sensors, accelerometers and flux-gate magnetometers, all capable of operating at temperatures up to 300°C. The sensors and supporting hybrid electronics have been integrated into a non-magnetic chassis designed for inclusion in a directional drilling bottom-hole assembly. This paper presents the technology approach, material selection decisions, processing techniques, final sensor and electronics configuration, and initial testing of the integrated directional module.
Experimental Investigation of Electro-thermal Stress Impact on SiC-BJTs Electrical Characteristics
Authors: Chailloux Thibaut , Calvez Cyril , Bevilacqua Pascal , Planson Dominique , Tournier Dominique
Published: October 2015

The aim of this study consists in investigating the effects of electrical and thermal stresses on SiC n-p-n bipolar junction transistors (BJTs). The stability of the electrical characteristics of BJTs is inspected under switching operation, DC operation, temperature cycling and continuous thermal stress up to 225°C. While switching operation and temperature cycling for several hours lead to significant changes at 25°C, the electrical characteristics were little degraded at high temperature. Besides, DC operation and continuous thermal stress did not result in significant degradation at all, both at room temperature and at high temperature.
Advanced microfluidic packaging for molecular diagnostics
Authors: Palmieri M. , Barbuzzi T. , Maierna A. , Marchi M. , Montalbano G. , Panvini G. , Rodenfels T. , Stoeters W.
Published: October 2015

STMicroelectronics has teamed up with Boehringer Ingelheim microParts GmbH to develop the In-Check™ Lab-on-Chip microfluidic disposable cartridge. In-Check™ is a ST proprietary platform dedicated to the in-vitro molecular diagnostics, e.g. biological analysis based on nucleic acid targets such as DNA, RNA. Its first generation has been released to commercial applications such as virus or bacteria borne infectious diseases. The second generation described herein will further enhance the platform customer experience by means of an innovative design of its disposable component. Indeed the new format represents a substantial step forward in the system integration and easy-of-use. This advanced microfluidics package enables fully automated application protocols such as analyte and reagents input, management and disposal. In-Check™ cartridge is a plastic-based self-contained embodiment which integrates a variety of design elements and components, including liquid loading and waste reservoirs, connecting micro-channels, two sets of valves one set to tight-seal biochemical reactors and the other set for fluid routing, hydrophobic membranes, fluorescent read-out window. Such microfluidic platform married with integrated Micro Electo Mechanical System (MEMS) device and software algoritms provides a highly flexible system to run complex biological assays as RNA Reverse Transcription (RT), DNA Polimerase Chain Reaction (PCR), Probe Hybridization and Detection. This paper will present the disposable product concept, key components and functionality together with the design and manufacturing challenge.
Achieving Ceramic-like RF Capacitor Requirements with Organic-based Materials
Authors: Hwang Jin-Hyun , Andresakis John , Carter Bob , Kageyama Yuji , Kuwako Fujio
Published: October 2015

New and novel organic-based composite materials for the use of embedded RF capacitors have been developed to address the important material issues by means of functional filler and resin chemistry. Combining different fillers with appropriate chemistries, the net composite can be made thermally stable while retaining the high dielectric constant and low loss. These composites attained dielectric constant of above 7 without compromising the quality factor in GHz frequency range. In addition, measurement of capacitance variation as a function of temperature (TCC) showed flatter TCC profile, resulting in TCC of ±30 ppm/°C over the temperature range −55°C to 125°C. It can be incorporated into organic chip package and, unlike ceramic-based LTCC they can utilize large area processing that is typical, and available in high volume manufacturing. This material is formulated for RF module designers to successfully implement embedded RF capacitors into their organic chip package designs and thus improve form factor, electrical performance and possibly reduce overall costs.
Validated High Speed Pull and Shear Test Methodologies to Evaluate Pb-Free BGA Mechanical Strength
Authors: Ahmad Mudasir , Assudani Ravi , Nelson Drew , Youssef Amir
Published: October 2015

The conversion to lead free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. Lead-free solder joints are generally stiffer than tin-lead solder joints, and mechanically induced failures have become more prevalent in lead-free solder assemblies. Traditionally, assembly bend and shock testing is performed to evaluate mechanical assembly reliability. However, bend and shock tests are expensive, cumbersome and not feasible for evaluating lot-to-lot variations in mechanical strength.

Consequently, there is a need for a validated, component level test method that can be used as an accurate indicator of assembly level mechanical strength. Several publications have been written to evaluate the efficacy of high speed pull and shear testing as a viable reliability indicator [1 – 10].

In this study, a comprehensive Gauge R&R study was performed to evaluate the accuracy of the test equipment, including high speed video calibration. Then, test studies were performed to compare the accuracy of the results, spread across different package constructions, solder metallurgies, ball pitch and surface finish. In addition, the effect of parameters like multiple reflows and aging on specific metallurgies and surface finishes was studied. The results were generated over more than 2000 test runs.

Finally, the study rank orders all critical test parameters and articulates what precise steps can be taken to generate relevant data for standard and custom devices during early evaluation stages and during high volume manufacturing.
Interconnect Failure Rate Estimation Based on the Extreme Value Distribution
Authors: Plucinski Mark , Hoffmeyer Mark
Published: October 2015

Evaluating and predicting the failure rate of interconnect is a time consuming and expensive process. Non parametric techniques to analyze the qualification data, such as employing the Chi-square distribution require large sample sizes to achieve an accurate estimate.

Recently there has been a resurgence in the use of extreme value theory (EVT). Increases in temperature records, the numbers of strong storms, and flooding events have fueled this interest. A novel method that is based on EVT and an accelerated degradation model for estimating the failure rate from a set of stress data is proposed and described.

There are many advantages of this technique, and recommendations on sample size are discussed. Advice is given as to how the total sample should be sectioned before the maximum is taken of each subset. Interconnect examples are given, generated from Monte Carlo simulations of known distributions, and used for a comparison of the extreme value technique versus Chi-square and Johnson distribution methods.
Improvements in Solid State Lighting Applications with the use of Traditional Thick Film Technology.
Authors: Groman Sarah , Jones Neil
Published: October 2015

As the LED market continues to grow and overtake many other lighting technologies such as incandescent and compact fluorescent bulbs (CFL), there are many challenges that LED manufacturers face. As demand for higher power and longer life continue to drive LED adoption in lighting applications, manufacturers must be able to find ways to increase thermal efficiency while reducing cost for LED package designs.

In this paper, the benefits of a new Pb Free smooth-print thick film Ag conductor are examined in comparison to more traditional die attach methods, which include plated thin films, and polymer based die attach adhesives. A smooth print thick film conductor can offer the best of both worlds as cost and process simplicity are comparable to a polymer system, while thermal efficiency and solderability are comparable to plated thin film systems. As surface smoothness increases, there is also the benefit of reduced solder voiding and material usage; solder voiding is a major contributor to thermal inefficiency. In the case of high cost solders such as Au/Sn, the reduction in material usage can translate to significant cost savings. Thermal efficiency, solderability, and manufacturing complexity must all be considered as new LED package designs are sought that reduce overall cost while increasing thermal efficiency and effective operational life.

This paper evaluates these benefits as they apply to wire bonding, thermal dissipation, surface smoothness, and voiding at the die-package interface. Each of these properties can affect thermal efficiency of the package, which in turn affects the light output and effective operational life of the LED. A new option for LED package design is presented, and this packaging can allow for cost-effective manufacturing while keeping up with industry demands of higher power, maximum efficiency, and greater effective operational life.
Underfill For Ultra-Low Bumped (10μ) 3D Package
Authors: Liu Mary , Yin Wusheng
Published: October 2015

3D package has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize device and meet the demand of high speed, more memory, more function and low cost. With the advancement of 3D package, the bump height is now down from 80μ to 10 μ. When the bump diameter is 20–40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however it is very difficult for traditional flip chip underfill or board level underfill flow into 10μ multi-layer of 3D package without process and reliability issues. A unique flip chip underfill series has been successfully developed, which not only function as traditional underfill such as flip chip but also work very well for 10μ bump height 3D package application. YINCAE underfill series allow fast flow into 3D package and fast cure. After underfilling and cure, there are no voids observed in underfill. In this paper, a total of four different underfills have been studied. Compared to the other flip chip underfill, YINCAE underfill has demonstrated both excellent workability and outstanding reliability. In terms of workability and reliability, the four different flip chip underfills can be ranked in the following order from best to worst: A underfill > B underfill > C underfill > D underfill.
Cost-Effective Alternatives to Palladium Activation – A Study on Autocatalytic Electroless Copper Deposition
Authors: Steinhäuser Edith , Magaya T.A.
Published: October 2015

Electroless copper plating is the most important and critical step for through-hole metallization of printed circuit boards. Conventional electroless copper solutions contain formaldehyde as the standard reducing agent. Due to the toxic nature of formaldehyde, there is a need to change to a reducing agent that is more environmentally friendly and safer to use. Many reducing compounds have been proposed to replace formaldehyde. For example, glyoxylic acid has been described in the literature as an especially attractive alternative because of its relative safety. In preparation for electroless copper plating, substrates are typically catalyzed by the adsorption of palladium. However, a change in the reducing agent can also lead to a change in the activation process, primarily because there is no single metal that appears to be a good catalyst for the oxidation of all reducing agents that have been employed for electroless deposition. In the present study, electrochemical measurements were carried out in order to obtain information about the catalytic activity of copper, silver, nickel and palladium in the oxidation reaction of formaldehyde as well as glyoxylic acid. Metals with high catalytic activity for each reductant oxidation can be determined by using cyclic voltammetry. These metals are candidates for an improved activation process. Electrochemical measurements showed that palladium does not have the highest catalytic activity of all tested metals. Therefore, more cost-effective, alternative metals were examined as catalysts for electroless copper plating reactions. The paper presents the results of a PhD thesis, which included tests on cheaper alternatives to palladium for activation of autocatalytic electroless copper deposition. It also includes production scale studies and conclusions on possible replacement of formaldehyde as a reducing agent for electroless copper deposition.
Study of Grounding Schemes Utilized in Conformal Shielding Applications
Authors: Morris Scott , Carey Dan
Published: October 2015

There are many different shielding technologies available for electromagnetic interference (EMI) shielding in radio frequency (RF) applications. We will investigate various EMI shielding technologies, one of which is RFMD's MicroShield™ Integrated RF Shielding technology's conformal plating process that encapsulates the device with a solid sheet of metal. This novel technology provides improvements in form factor, ease of use, and lower cost as compared to traditional shielding approaches.

We will compare ground designs within the substrate to determine maximum EMI shield performance. An examination of ground structures, layer grounding, and external ground connections will be analyzed. The test device structure will be comprised of a radiating element on the top surface of the laminate. A thorough look at the advantages and limitations between these different EMI grounding configurations will be discussed. This data will be used to quantify grounding effectiveness which will, in turn, be used to generate design guidelines.
Ink-jetting for Electronic Assembly
Authors: Meyer-Berg Georg , Beer Gottfried , Pressel Klaus
Published: October 2015

We report experimental results on applying ink-jetting to dedicated system-in-package technologies. Special focus is on die-attach, vertical and horizontal interconnects. Our experiments on die attach experiments demonstrate that today we have still too high expenses to adapt materials, filler size and viscosity. The filling experiments of 150μm diameter vertical through encapsulant vias for package-on-package applications with ink-jetting showed void formation, which requires still smaller ink jet drops in the future. For formation of horizontal interconnects, e.g. for rerouting, by ink-jetting we observe that a functionalization of the surfaces e.g. with plasma or sulfur acid is required. Based on these project results and experience we suggest a roadmap for ink-jetting using parallel nozzles and single nozzles.
Electrical Analysis and Modeling of 3D Through-Strata-Vias (TSVs) and Pads
Authors: Xu Zheng , Beece Adam , Rose Kenneth , Lu Jian-Qiang
Published: October 2015

Through-strata-via (TSV) is one of the most attractive3D integration solutions in that it offers a massive number of short interstrata connects, high data bandwidth, reduced delay and power consumption, small footprint, improved yield, heterogeneous integration and reduced volume-production cost. This work attempts to investigate the TSV signal integrity and, particularly, compares the performance among different TSV and pad combinations. Transient analysis, eye diagram and bathtub curves show a good behavior of TSV signal integrity in the time domain. Regarding to frequency response, the set of circular TSV and circular pad offers a slightly better performance than other shapes. When a misalignment is so large that the TSV does not land completely within the pad, the TSV frequency response is affected considerably. A big pad size degrades performance and decreases trace density, while a thinner pad would enhance process throughput and reduce cost. Simulation results also indicate that rather than using multiple small TSVs connecting to a common pad, it is better to implement one single big TSV because of less parasitics and coupling. Furthermore, the TSV component is carefully modeled, and the results from electromagnetic simulation and a broadband SPICE model are in a very good agreement.
A Novel TSV Etching using NLD and VHF CCP Plasma For 3-D Stacked Devices.
Authors: Morikawa Yasuhiro , Murayama Takahide , Yoshii Manabu , Suu Koukou
Published: October 2015

In this study, the etch development of high etch rate and high aspect ratio for the fabrication of various diameters of thru silicon via is described. There are a lot of applications about TSV's methods. There TSV need to meet strict requirements with respect to high etch rate, sidewall roughness and undercut. For diameter of vias down to 10um a SiO2 hard mask based SF6/O2 etch approach is used by magnetic neutral loop discharge plasma (NLD plasma). This system can be used for oxide etching and Si etching. In the case of oxide etching, some magnetic coil currents are applied to generate magnetic neutral loop in the vacuum chamber in order to high density plasma in the low pressure below 1 Pa. On the other hand, in the case of Si etching, the pressure is raised up to 2∼10 Pa. As a result, an etched profile of TSV with diameter of 1.5 um and the etched depth of 11.5 um, aspect ratio is 7.6, was achieved. The etch rate is about 4.5 um/min. For diameter of vias up to 10um, a resist mask based and SF6/O2 etch approach is also used by very high frequency coactivity coupled plasma. VHF CCP etching system was used to high-pressure process, more than 50Pa, as a purpose to high etch rate of up to 10um pattern's TSV etching. As a result, a vertical profile of TSV with diameter of 50 um and the etched depth of 50 um, aspect ratio is 1.0, was achieved. The etch rate is about 45 um/min. NLD and VHF CCP processes are non-cycle etch methods, and to successfully smooth pattern TSV.
2nd Level Reliability Improvement on WLCSP
Authors: Park Seungwook , Hong Jupyo , Lee Changbae , Moon Sunhee , Kim Jinsoo , Jeon Hyungjin , Yoo Dojae , Kweon Youngdo
Published: October 2015

Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. The wafer level chip scale package is one of them, which has the solution of the market needs above. However, WLCSP technology is still not fully accepted on the large device size that is larger than 5mm × 5mm. It needs to overcome 2nd level reliability issue on both solder joint and drop reliability test. To improve 2nd level reliability, we need to apply the longer stand–off design such as Cu –post and double solder ball instead of single solder ball, and low modulus material on polymer layer under the solder pad for releasing thermal stress which result in the solder joints crack due to CTEs (Coefficient of Thermal Expansion) mismatch between organic PCB and WLCSP. In this paper, the double ball structure is introduced as one of them can provide the longer stand off. In addition of improving 2nd level reliability and drop test it may need to apply different solder ball component properties to increase Thermal cycling and drop test. The WLCSP structured a double solder ball showed a better 2nd level reliability result. This paper describes the molding process for double ball process and 2nd level reliability by solder property variation.
Mask and mask-less injection molded solder (IMS) technology for fine pitch substrate bumping
Authors: Nah Jae-Woong , Gruber Peter A. , Lauro Paul A. , Feger Claudius
Published: October 2015

We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for fine pitch organic substrates. Pure molten solder is injected through a reusable film mask (mask IMS) or directly injected without a mask (mask-less IMS) on the pads of an organic substrate to overcome the limitation of current pre-solder bumping technologies such as solder paste stencil printing and micro-ball mounting.

In the case of mask IMS, targeted solder height over the solder resist (SR) is designed into the mask which has desirable thickness and hole sizes. Three different solder bump heights such as 30, 50, and 70 microns over SR were demonstrated for commercial organic substrates which have a pitch of 150 μm for 5,000 area array pads. To show the extendibility of the mask IMS bumping method to very fine pitch applications, 100 μm pitch bumping of 10,000 pads and 80 μm pitch bumping of 15,000 pads were demonstrated.

In mask-less IMS, the pure molten solder is directly filled into the opening volume of the SR. After the injection of molten solder, solidification of the solder under low oxygen leads to solder protrusions above the SR surface because 100 % pure solder is filled into the whole SR opening volume. For a 150 μm pitch commercial substrate, we demonstrated minimum bump heights of 15 μm over the 20 μm thick SR. Since there is no need to align mask and substrate, the maskless IMS method lowers process costs and makes the process more reliable. By manipulating the opening in the SR, it is possible to enable variations in the height of the solder bumps.

Flux or formic acid is not needed during solder injection of both described processes, but a low oxygen environment must be maintained.

In this paper, we will discuss laboratory scale processes and bump inspection data, along with the discussion of manufacturing strategies for IMS solder bumping technology for fine pitch organic substrates.
Advances in Wafer Level Processing and Integration for CIS Module Manufacturing
Authors: Kim Bioh , Matthias Thorsten , Kreindl Gerald , Dragoi Viorel , Wimplinger Markus , Lindner Paul
Published: October 2015

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.
Using In situ Capacitance Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies
Authors: Gaynes Michael , Chainer Timothy , Yarmchuk Edward , Torok John , Edwards David , Olson David , Pizzolato Katie
Published: October 2015

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface.

This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process.

The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area.

Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.
Silicon Micro-Fabrication Technologies for Micro-Filters
Authors: Majeed Bivragh , De Malsche Wim , Zhang Lei , Fiorini Paolo , Tezcan Deniz Sabuncuoglu , Soussan Philippe
Published: October 2015

Silicon micro-fabrication techniques allow for the development of microfluidic systems with very accurate control of size and uniformity of structures. In this paper we report on the silicon fabrication process of micro-filters for versatile application in fluidics systems. Micro-filters are composed of an ordered array of pillars and supply channels. Depending on pillar pitch, they can be used for, e.g., electrophoresis, chromatography and purification of biological mixtures. In this paper we focus on high performance liquid chromatography. The process that we have developed for micropillar fabrication consists of defining first 1μm diameter pillars with an inter-pillar distance of 1μm or less in an oxide hard mask with a DUV stepper, stitching is used to form few cm long patterns across the 200mm wafers. Second, the supply channels are defined with 1× alignment lithography. After definition of supply channels, deep reactive ion etching of silicon is performed with an optimised recipe to etch submicron pillars and supply channels of 100μm wide at the same time. The simultaneous etch of both structures avoids complex lithography steps otherwise necessary to protect the pillars while etching the supply channels or vice versa as would be done conventionally. Wafers are then anodically bonded to 200mm Pyrex wafers in order to seal the channels. Pyrex wafer also allows the use of optical detection system. Feed through holes for accessing the supply channels are etched on the backside of Si wafer. Filter characterization has been performed: a plate height of 1μm was measured and successful separation of 3 coumarin dyes is achieved.
Understanding Cleaning of Vias Fabricated Using Micro Mechanical Punching in Liquid Crystal Polymer (LCP) Substrate
Authors: Chowdhury Mohammad K. , Sun Li , Cunningham Shawn J. , Malshe Ajay P.
Published: October 2015

The objective of the research is to understand the effect of chemical treatment's etching times on via wall roughness; and the direct current (DC) and reverse pulse plating (RPP) of vias fabricated using micro mechanical punching process on liquid crystal polymer (LCP) substrate. One major drawback of micro mechanical punching process is the formation of LCP and copper burrs. Sequential wet chemical etching and oxygen plasma cleaning techniques were developed as an effective tool for the removal of these burrs. The wet chemical process required a sequential oxidation, etching, and acid neutralization treatment for the effective removal of LCP and copper burrs. These treatments have an effect on the surface roughness of the through via wall. Under this research time dependent experimental matrices were designed to observe the effect of the wet chemical etching on the via wall surface roughness. Sequential oxidation, etching, and acid neutralization treatments were done, where only one treatment time was varied for 1, 5, and 10 minutes keeping the other treatment times constant at 5 minutes. After examining three different experimental matrices for via wall roughness using a scanning electron microscope (SEM), it was observed that the longer treatment time using chemical etchant will make the surface rougher. In addition, it was also observed that the oxidation treatment time of greater than 5 minutes produced the same roughness irrespective of treatment time variation. The neutralization treatment time does not have any effect on the roughness of the LCP via wall. Two different approaches named - DC and reverse pulse plating (RPP) were used to plate the vias. It was found that the RPP does not result in good via filling, because it produced high current concentration at the edges and consequently over plating at the edge compared to the inside of the via. In stark contrast, DC plating delivers completely plated vias after 4.5 hours, which is a 7 μm/hr plating rate.
High-Dielectric-Constant PLZT Films on Metal Foils for Embedded Passives
Authors: Ma Beihai , Narayanan Manoj , (Balu) Balachandran U.
Published: October 2015

Ceramic film capacitors with high dielectric constant and high breakdown strength would result in advanced power electronic devices with higher performance, improved reliability, and enhanced volumetric and gravimetric efficiencies. We have grown ferroelectric films of lead lanthanum zirconate titanate (PLZT) on base metal foils by chemical solution deposition. Their dielectric properties were characterized over the temperature range between −50 and 150°C. We measured a dielectric constant of ≈700 and dielectric loss of ≈0.07 at −50°C and a dielectric constant of ≈2200 and dielectric loss of ≈0.06 at 150°C. At room temperature, we measured a leakage current density of ≈6.6 × 10−9 A/cm2, mean breakdown strength of 2.6 MV/cm, and energy density >85 J/cm3. A series of highly accelerated lifetime tests (HALT) was performed to determine the reliability of these PLZT film-on-foil capacitors under high temperature and high field stress conditions. Samples were exposed to temperatures ranging from 100 to 150°C and electric fields ranging from 8.7 × 105 V/cm to 1.3 × 106 V/cm during the HALT testing. Breakdown behavior of the samples was evaluated by Weibull analysis. The mean time to failure was projected to be >3000 h at 100°C with a dc electric field of ≈2.6 × 105 V/cm.
Characterization of Black Pad Defect on Electroless Nickel- Immersion Gold (ENIG) Plated Circuits
Authors: Mortensen Adam W. , Devaney Roger M.
Published: October 2015

The advent of the RoHS legislation, which mandated lead-free solders, and the rise in popularity of the BGA package, have resulted in ENIG becoming a popular choice for surface finish due to its excellent long term solderability and surface planarity. One of the pitfalls of this surface finish is the possibility of creating a layer of overly elevated phosphorous content between the electroless nickel and immersion gold, known as black pad defect. Most of the available literature suggests black pad defect is caused by accelerated reduction (corrosion) of the nickel in the nickel- phosphorus (Ni-P) layer during the immersion gold step of the ENIG process. Black pad defect can manifest as corrosion spikes at the nodule boundaries in the Ni-P and can progress to an abnormally thick high phosphorus region at the top of the Ni-P. One failure mechanism associated with black pad defect is the brittle failure of well wetted solder joints from the underlying Ni-P layer due to the presence of the high phosphorus region. In severe cases, black pad defect can cause solderability issues and retard the formation of tin-nickel intermetallic preventing good wetting of the solder joint. We have had the opportunity to examine many different cases of black pad, from severe to mild, and have a large amount of knowledge to share. This paper will give the reader a basic understanding of how to recognize black pad and subsequently determine its severity.
Nanomaterials for “Green” Electronics
Authors: Das Rabindra N. , Papathomas Konstantinos I. , Poliks Mark D. , Markovich Voya R.
Published: October 2015

This paper examines the use of nanomaterials in the area of “green” technology. A variety of green materials for advanced organic packaging have been developed. These include capacitors and resistors as embedded passives, resin coated Cu (RCC) as buildup layers, highly conducting nano-micro media for Z-interconnects, lead free assembly paste, ZnO based additives, magnetic materials, inductors and thermal interface materials (TIM). Nanocomposites can provide high capacitance densities, ranging from 5 nf/inch2 to 25 nF/inch2, depending on composition, particle size and film thickness. The electrical properties of capacitors fabricated from BaTiO3-epoxy nanocomposites showed a stable capacitance over a temperature range from 20°C to 120 °C. A variety of printable discrete resistors with different sheet resistances, ranging from 1 ohm to 120 Mohm, processed utilizing a large panel format (19.5 × 24 inches) have been fabricated. Low resistivity nanocomposites, with volume resistivity in the range of 10−4 ohm-cm to 10−6 ohm-cm depending on composition, particle size, and loading can be used as conductive joints for high frequency and high density interconnect applications. A variety of metals including Cu, Ag, LMP (low melting point) and LMP-coated Cu fillers have been used to make halogen free, lead free electrically conducting adhesive technology as an alternative to solders. Halogen free resin modified with ceramics/organic particles can produce low Dk resin coated Cu (RCC) with Dk value in the range between 4.2 and 2.5. Similarly, low loss RCC materials can be produced by combining HF resin with low loss fillers. The mechanical strength of the various RCC was characterized by a 90 degree peel test and measurement of tensile strength. RCC exhibited peel strength with Gould's JTC-treated Cu as high as 6 lbs/inch for halogen free RCC. These halogen free RCC materials exhibit coefficients of thermal expansion (CTE), ranging from 27 ppm/°C to 32ppm/°C. The paper also describes a nanoparticle dispersion approach to prepare nanogels and nanofluids as thermal interface materials. Altogether, this is a new direction in the development of Green Packages and more specifically in the development of coreless substrates for semiconductor packaging.
A Novel Metal Core Substrate with Simplified Manufacturing Process and High Adhesion Conformal Dielectric and Circuitry Metal for High Density Chip-Scale Packaging Applications
Authors: Ahmad Syed Sajid , Jacobson John , Johnson Zane , Mattson Kevin , Reinholz Aaron , Schneck Nathan , Scholz Bernd , Strommen Greg
Published: October 2015

Substrates play a critical role in the quality and reliability of electronic packages and systems. Metal core substrates provide opportunities with respect to strength, heat dissipation, and speed over common organic substrates. The metal core provides an opportunity for grounding enhancements in RF circuits.

This paper presents the results of the development of a metal core substrate design which has advantages over conventional competitive designs. The manufacturing flow developed in this work has fewer process steps, uses fewer materials and shows interfacial adhesion strength above industry requirements.

The work outlines material evaluations to enhance the interfacial adhesion and corrosion resistance. The results of the evaluation of mechanical, chemical, and other methods to enhance interfacial adhesion are presented and compared. The enhanced interface shows significant adhesion increase for the circuitry metal over and beyond industry requirement.
A Method to Quickly Measure the Thickness of Aluminum Bond Pad on Silicon Substrate
Authors: Nguyen Son , Delalic Z. Joan , Clauberg Horst
Published: October 2015

In wire bonding, the thickness of the aluminum pad under the bonds needs to be measured for bonding process optimization purposes. In Cu wire bonding, the deformation of the Al bond pad is larger than in Au wire bonding. Because of this, the uniformity and thickness of Al that remains under the ball is often used as a metric in the process optimization. The thickness of the Al pads can be inspected with manual cross sectioning or FIB (Focused Ion Beam). However, these two methods are time consuming and expensive. This paper presents a method that helps to quickly measure the aluminum pad, which involves creating a graph of penetration of electron beam at different EDS (Energy Dispersive Spectroscopy) voltages versus Al thickness.

The method basically consists of: a) crafting Al layers of different thicknesses, b) obtaining EDS for each layer at different EDS voltages, c) performing cross sectioning of those layers and measuring the thickness of the layers, d) generating the metric based on the acquired data, and e) testing the acquired metric.
Identifying and Working with Government Regulations
Authors: Raia Kelly
Published: October 2015

Regulations regarding exports from the United States are abundant. In reviewing the regulations how does one discern whether our company should be following the Export Administration Regulations, Office of Foreign Asset Control (OFAC) Regulations, Foreign Trade Regulations, International Traffic in Arms Regulations, none of these or all of these?