bluuebunny/crossref_metadata_2025 huggingface dataset:
Experimental and Numerical Study in Denting Resistance of 6111-T4 Aluminium Alloy
Authors: Peixinho Nuno , Pinho António
Published: March 2009

This study presents results of denting resistance of 6111-T4 aluminium alloy.
Experimental results of dynamic denting were compared with numerical simulations performed using
LS-DYNA software. The experimental tests were performed on 1mm thick plates clamped in a
circular area with a diameter of 80mm. Dynamic denting was accomplished by dropping different
indenters from heights ranging from 0.36 to 1.7 m. The obtained results indicate a high suitability of
the aluminium alloy for use in automotive panels. The results of the numerical simulations display a
good correlation with experiments if dynamic effects are introduced in the constitutive equation of
the material through the Cowper-Symonds coefficients.
Effect of Microstructure on Crack of Al-Mg-Si Alloy Extrusions during Axial Compression
Authors: Morita Keiji , Yoshihara Shinji , Oka Takashi
Published: March 2009

Effect of microstructure on micro-cracking behavior of Al-Mg-Si alloy extrusions during axial
compressive deformation was studied. Extrusions of Al-Mg-Si alloys with two different
compositions were used for the mechanical tests and microstructure observation. Compressive loads
were applied parallel to the axes of the tubular specimens with rectangular cross section. As
deformation proceeded, the specimens changed their shape into bellows-like ones. Specimens with
finer grains showed higher critical strength and strain for crack initiation. Microscopic observation
showed that cracks initiated at the bulge surface of the bellows and propagated into the depth. The
observed behavior of crack initiation and propagation was interpreted in connection with those in
simple tensile tests. The stress and strain at the crack initiation site of the bulge were assumed to
correspond to the tensile strength of the alloy. The effect of grain size on the crack behavior was
well explained by the grain size dependence of stress concentration at grain boundaries due to
dislocation pile-ups. The effects of over-aging on the microstructure and crack initiation behavior
were also discussed.
An Analysis on the Force Requirement of Combined Operations for Forward and Backward Tube Forming
Authors: Hwang Beong Bok , Lee G.M. , Lee Y.H. , Ok J.H. , Kim S.H.
Published: March 2009

In the present study, the finite element analysis has been conducted to investigate the
deformation characteristics of forward and backward can extrusion process using AA 1100 aluminum
alloy tubes in terms of maximum forming load and extruded length ratio in a combined material flow.
A commercially available code is used to conduct rigid-plastic FEM simulation. Hollow tubes are
selected as initial billets and the punch geometries follow the recommendation of ICFG. Selected
design parametrs involved in simulation includes punch nose radius, die corner radius, frictional
condition, and punch face angle. The investigation is foucused on the analysis of deformation pattern
and its characteristics in a forward tube extrusion combined simultaneously with backward tube
extrusion process main in terms of force requirements for this operation according to various punch
nose radii and backward tube thickness. The simulation results are summarized in terms of
load-stroke relationships for different process parameters such as backward tube thickness, die corner
radii, and punch face angle, respectively, and pressure distributions exerted on die, and comparison of
die pressure and forming load between combined extrusion and two stage extrusion process in
sequencial operation. Extensive analyses are also made to investigate the relationships between
process parameters and extruded lengths in both forward and backward directions. It has been
concluded from simulation results that a) the combined operation is superior to multi-stage extrusion
process in sequential operation in terms of maximum forming load and maximum pressure exerted on
die, b) the length of forward extruded tube increases and that of backward extruded tube decreases as
the thickness ratio decreases, and c) the forming load is influenced much by the thickness ratio and
the other design factors such as die corner radius and punch face angle does not affect much on the
force requirement for the combined extrusion process.
The Forming Characteristics of AA 2024 Aluminium Alloy in Radial Extrusion Process Combined with Backward Extrusion
Authors: Jang Dong Hwan , Ok J.H. , Lee G.M. , Hwang Beong Bok
Published: March 2009

Numerical analysis of radial extrusion process combined with backward extrusion has
been performed to investigate the forming characteristics of an aluminum alloy in a combined
extrusion process. Various variables such as gap size, die corner radius and frictional conditions are
adopted as design or process parameters for analysis in this paper. The main investigation is focused
on the analysis of forming characteristics of AA 2024 aluminum alloy in terms of material flow into
backward can and radial flange sections. Due to various die geometries and process conditions such
as frictional conditions, the material flow into a can and flange shows different patterns during the
combined extrusion process and its characteristics are well summarized quantitatively in this paper in
terms of forming load, volume ratio etc. Extensive simulation work leads to quantitative relationships
between process conditions and the forming characteristics such as volume ratio of flange to can and
the size of can and flange in terms of the can height extruded backward. It is easily seen from the
simulation results that the volume ratio, which is defined as the ratio of flange volume to can volume,
increases as the gap size and/or die corner radius increase. However, it is interesting to note that the
frictional condition has little influence on the forming load and the deformation patterns. Usually, the
frictional condition is a greatest process variable in normal forging operation. It might be believed
from the simulation results that the frictional conditions are not a major process parameter in case of
combined extrusion processes. It is also found that the can size, which is defined as the height of billet
after forming, turns out to be even smaller than that of initial billet under a certain condition of die
geometry.
Phase Equilibria of the Nickel-Aluminium-Chromium System at 1150°C
Authors: Kitajima Yuri , Hayashi Shigenari , Narita Toshio
Published: March 2009

Phase equilibria in the Ni-Al-Cr system at 1150°C were investigated by using annealed
ternary alloys and diffusion couples. The phase constitutions, microstructures, and tie-lines were
determined by conventional techniques, including X-ray diffraction, scanning electron microscopy
and electron probe microanalysis. The solubility limits of Cr was found to be about 9at.% in the γ’
and 17at.% in the β phase. The size of second or third phase precipitates in the alloys was found to
affect the determination of the tie-lines by the micro probe analysis.
Isothermal Oxidation of Pt Modified and Ru Modified Aluminide Coating on a Fourth Generation Single Crystal Superalloy
Authors: Matsuoka Yuki , Matsunaga Yasuo , Nakagawa Kiyokazu , Taniguchi Shigeji
Published: March 2009

Isothermal oxidation behavior of a 4th generation Ni-base single crystal superalloy with
Pt-modified and Ru-modified aluminide coating was examined in a temperature range 1223 to 1373
K in air. Both Pt and Ru modification improve the oxidation resistance of a simple aluminide
coating, especially above 1273 K. They allow thin protective and continuous Al2O3 scales to be
intact for at least 500 h at temperatures up to 1323 K. However, the Pt modification drastically
accelerates the formation of a secondary reaction zone (SRZ). This suggests that Pt promotes the
formation of a topologically close-packed phase by lowering the solubility of refractory elements in
γ-Ni. In contrast, the Ru modification reduces the SRZ, and is expected to enhance the phase
stability under the coating by preventing the depletion of Ru due to its outward diffusion.
Development of an Oxidation Resistant Coating on Nb-Based Ultra-High Temperature Alloy
Authors: Saito Kosuke , Hayashi Shigenari , Narita Toshio , Iwanaga Isao , Tanaka Ryohei
Published: March 2009

A coating with a duplex layer structure, outer β-NiAl and inner σ-Re-Cr-Ni layers, was formed
on the third generation Nb-5Mo-15W-16Si- 5Hf-5C alloy by using successively Re-pack
cementation, electroplating of Re-Ni film, and Cr/Al pack cementation. The duplex layer coating
changed during high temperature oxidation to form a coating with a four layer structure: an
outermost Ni2Al3, an outer Ni, an inner σ-Re-Cr-Ni, and an innermost χ-Re-Nb. The Re-pack
cementation was carried in an alumina crucible where the specimen was buried in Re metal powder,
in vacuum at 1573K to form a Re film, and then a Re-Ni film was electroplated onto the Re-pack
treated alloy. The coated alloy formed a protective α-Al2O3 scale when oxidized at 1573K in air for
14.4ks. It was concluded that the σ-Re-Cr-Ni phase can act as a diffusion-barrier against both
inward Al diffusion and outward diffusion of alloying elements from the alloy substrate to the
β-NiAl.
Micro- /Nano-Crystal Aluminized ODS Coatings
Authors: Zhan Zhao Lin , He Ye Dong , Wang De Ren , Gao Wei
Published: March 2009

A novel technique has been developed to prepare micro-/nano-crystal aluminized ODS coatings on stainless steel and nickel-base superalloy. In this technique, the pack aluminizing is combined with the repeated ball impact. Pure Al powder is mixed with 1wt% Y2O3 powder by ball milling. The ultrafine Y2O3 powder is well dispersed in Al particles. The modified Al particles are welded to the surface of metals by ball impact, causing the refinement of coarse grains and acceleration of atomic diffusion. Micro-/nano-crystal alloy layer with Y2O3 grows outward at a much low temperature (below 600°C) and in short treatment duration, compared with conventional pack aluminizing. The effects of processing temperature and duration on formation of the coatings have been analyzed. The microstructure of the coatings is studied using the methods of SEM, AMF, EDS, XRF and XRD. The results indicate that the aluminized ODS coatings appear to be dense, homogeneous, micro-/nano-crystal structure, and consist mainly of Al-rich phases, such as Fe2Al5, FeAl3 NiAl3 and7 CrAl5. High temperature oxidation tests show that the coatings enhance the oxidation resistance.
Strains in Thermally Growing Alumina Films Measured In-Situ Using Synchrotron X-Rays
Authors: Hou Peggy Y. , Paulikas A.P. , Veal B.W.
Published: March 2009

Strains in thermally grown oxides have been measured in-situ, as the oxides develop and evolve. Extensive data have been acquired from oxides grown in air at elevated temperatures on different model alloys that form Al2O3. Using synchrotron x-rays at the Advanced Photon Source (Beamline 12BM, Argonne National Laboratory), Debye-Scherrer diffraction patterns from the oxidizing specimen were recorded every 5 minutes during oxidation and subsequent cooling. The diffraction patterns were analyzed to determine strains in the oxides, as well as phase changes and the degree of texture. To study a specimen's response to stress perturbation, the oxidizing temperature was quickly cooled from 1100 to 950oC to impose a compressive thermal stress in the scale. This paper describes this new experimental approach and gives examples from oxidized β-NiAl, Fe-20Cr-10Al, Fe-28Al-5Cr and H2- annealed Fe-28Al-5Cr (all at. %) alloys to illustrate some current understanding of the development and relaxation of growth stresses in Al2O3.
Isothermal Oxidation of Sintered β-FeSi2 in Air
Authors: Nanko Makoto , Chang Se Hun , Matsumaru Koji , Ishizaki Kozo , Takeda Masatoshi
Published: March 2009

High-temperature oxidation of sintered β-FeSi2 doped with Mn and Co was evaluated at 800°C in air. Amorphous SiO2 was developed as an oxide scale. Granular ε-FeSi also appeared below the SiO2 scale as a result of consumption of Si in β-FeSi2. Growth of the oxide scale on doped FeSi2 followed a parabolic law and its rate was similar to oxidation of undoped samples. Thermoelectric properties of sintered β-FeSi2 were also evaluated before and after oxidation at 800°C for 7 days. There was no significant change in thermoelectric properties after high-temperature oxidation on β-FeSi2 sintered bodies.
In Situ X-Ray Diffraction Study of Load Partitioning and Microyielding for the Super Duplex Stainless Steel SAF2507 (UNS S32750)
Authors: Peng Ru Lin , Gibmeier J. , Eulert Sebastian , Johansson Sten , Chai Guo Cai
Published: March 2009

The deformation behaviour of the super duplex stainless steel SAF2507 (UNS S32750)
under successive uniaxial tensile loading-unloading was investigated with respect to load sharing
and inter-phase interactions. The steel consists of 58% austenite and 42% ferrite in volume. By insitu
X-ray diffraction experiment the evolution of phase-specific stresses with applied load was
monitored for three successive loading-unloading cycles with the maximum total strains being
0.34%, 0.75% and 1.63%, respectively. It was found that yielding occurred earlier in the austenitic
phase than in the ferritic phase during the first loading cycle. In the followed loading cycles, both
phases yielded under larger but similar applied stresses. Due to a similar behavior of the phases in
the elasto-plastic regime inter-phase interactions were relatively weak. Low microstresses induced
by the plastic straining resulted in somewhat larger stresses in the ferritic phase.
Stress Determination during the Mechanically-Induced Martensite Phase Transformation in the Superelastic Alloy CuAlBe by Neutron Diffraction
Authors: Malard B. , Pirling Thilo , Inal Karim , Patoor Etienne , Berveiller Sophie
Published: March 2009

This paper focuses on the study of the superelastic behavior associated to the stress
induced martensite transformation in a Cu-12.5%Al-0.5%Be [wt. %] shape memory alloy. Neutron
diffraction was used to track the evolution of stress in the (β1) austenitic phase during the onset of
the stress-induced martensite phase change. A thin flat and a cylindrical specimen was analyzed,
allowing us firstly to evaluate the stress evolution in the austenite phase during martensitic
transformation with laboratory X-ray and neutron diffraction and secondly to compare differences
between methods (sin2ψ, principal stress) for in-situ neutron diffraction experiments.
The Measurement of Stresses within Oxides Produced on Austenitic and Ferritic Steels Using Raman Spectroscopy
Authors: Hilson Gabrielle , Hallam K.R. , Flewitt Peter E.J.
Published: March 2009

Raman spectroscopy has been used by various workers to provide a measure of the stresses within
the oxides grown on metal substrates at high temperatures. In this paper, we consider thermally
grown oxides produced on a Type 316 austenitic stainless steel and an iron 3% silicon ferritic steel.
The oxides were grown in air at temperatures of 950oC and 650oC respectively over a range of
times. These oxides have been characterised by producing cross-sections using focused ion beam
milling. The variation of the Raman spectra wave number (He, Ne laser; λ = 633nm) for the oxides
produced on the polycrystalline austenitic stainless steel and the ferritic steel were measured as a
function of oxide thickness. This shift in wave number was a function of stress. For a fixed oxide
thickness on the stainless steel substrate the specimen has been subject to a bending force. A back
face strain gauge fixed to the metal substrate provided a measure of the applied strain. The peak
wave number varied with applied strain. The results are discussed with respect to the potential to
characterise the stresses produced in thermally grown oxides and as a tool to monitor applied stress.
Relative Importance of Main Influence Factors In Sink Erosion (EDM) Determination
Authors: Diéguez Jose L. , Corbacho L. , Ares E.
Published: March 2009

The present paper studies the process of electro discharge machining, estimating the
relative importance of main influence factors.
The first step is to evaluate the possibilities of a design of experiments based on an orthogonal
array, an appropriated method to systems with multiple factors changing in numerous levels
After of the realization of the experiences the theory of grey systems is used to know which
combination of factors optimize all of the variables.
Finally the analysis of the variance is applied to investigate which of the factors significantly
affects the global answer of the system.
Study of Drawing Processes by Analytical and Finite Element Methods
Authors: Camacho A.M. , Rubio Alvir E.M. , Gaya Cristina González , Sebastián M.A.
Published: March 2009

The Finite Element Method (FEM) has become an indispensable tool in metal forming analysis [1,2]. Contrary to the traditional methods, FEM allows to analyze more realistic situations, either geometric and tensional. On the other hand, the drawing process is one of the most ancient metal forming operations and, nowadays, this process is widely used in industrial field. However, the influence of the main parameters in the mechanics and efficiency of the process has been scarcely studied. Drawing processes have been analysed by FEM, assuming plane strain and axisymmetrical conditions in order to check the possibility of extrapolating results from one case to another. Besides, this numerical method is compared with analytical and experimental methods. Also, FEM is used for studying the influence of several technological parameters on variables such as the drawing force or the die pressure, and for obtaining results of stresses and strains in certain regions of the model.
Analysis of Stress and Strain in the Equal Channel Angular Drawing Process
Authors: León Javier , Luis-Pérez C.J.
Published: March 2009

The equal channel angular drawing (ECAD) process is an innovative method to obtain materials with high plastic strain in a continuous way. This deformation is higher than the deformation achieved by a conventional wire drawing process, for the same reduction of the cross section, so if an adequate thermal treatment is employed later, it could be possible to obtain an initial material with high value that could be useful in conventional manufacturing processes. This process consists in drawing a material through a die where two circular channels intersect at an angle between 90º and 135º. In this work a study using finite element of the plastic strain and the stresses that appear for one aluminium alloy AA-1370 has been carried out. Two ECAD passes have been made, where for the second pass the billet has been rotated 180º along the longitudinal axis. Finally, a calibrated pass has been carried out in order to obtain the billet with homogeneous dimensions in all the cross section. All the simulations have been calculated at room temperature and by using good conditions of lubrication. In order to perform the FEM simulations, a three dimensional geometry has been used. To analyze by FEM the second ECAD pass and the calibration pass, the deformations and stresses achieved in the previous passes have been taken into consideration. This has been done with the aim of achieving higher accuracy. Moreover, a comparative analysis with experimental results has been carried out.
Study of Stress and Geometry during the Manufacturing of Joint Bellows by FEM
Authors: Estrems Manuel , Franco Patricio , Fernández Ramon
Published: March 2009

The main objective of this work is the analysis of hydroforming for the manufacture of
joint bellows of AISI 316 steel for different values of diameter. The initial thickness of the metallic
tube is of 1 mm and diameters between 500 and 1200 mm are considered. The Finite Element
Method is applied to study the tensile stress and thickness reduction at the wave peak of the final
part. The numerical results are compared to the recommendations given by the EJMA standard.
More critical values of wave thickness and tensile stress are predicted by simulation.
Avoiding Instability on the Milling of Parts with Thin Features
Authors: Campa Francisco Javier , López de Lacalle Luis Norberto , Herranz S. , Lamikiz Aitzol , Rivero A.
Published: March 2009

In this paper, a 3D dynamic model for the prediction of the stability lobes of high speed
milling is presented, considering the combined flexibility of both tool and workpiece. The main aim
is to avoid chatter vibrations on the finish milling of aeronautical parts, which include thin walls and
thin floors. In this way the use of complex fixtures is eliminated. Hence, an accurate selection of
both axial depth of cut and spindle speed can be accomplished. The model has been validated by
means of a test device that simulates the behaviour of a thin floor.
Observation of Deep-Level Centers in 4H-Silicon Carbide Metal Oxide Semiconductor Field Effect Transistors by Spin Dependent Recombination
Authors: Dautrich Morgan S. , Lenahan Patrick M. , Lelis Aivars J.
Published: March 2009

In this study we report on spin-dependent recombination-detected electron spin resonance
of interface/near interface defects in 4H-SiC metal oxide semiconductor field effect transistors with
thermally grown SiO2 gate stacks. We demonstrate a distribution of performance-limiting defects
which extends beyond the SiC/SiO2 boundary into the SiC bulk. Our results strongly indicate that
the defects are intrinsic and we tentatively identify them as silicon vacancy-like centers on the basis
of strong, but imprecisely-resolved, 29Si hyperfine sidepeaks in the magnetic resonance spectrum.
High Inversion Channel Mobility of 4H-SiC MOSFETs Fabricated on C(000-1) Epitaxial Substrate with Vicinal (Below 1º) Off-Angle
Authors: Fukuda Kenji , Kato Makoto , Harada Shinsuke , Kojima Kazutoshi
Published: March 2009

SiC power MOSFETs are expected to be normally-off type fast switching devices. The
on-resistance of SiC power MOSFETs is much higher than the value predicted from the physical
properties of SiC. This is caused by the low channel mobility due to high interface state density
(Dit). We have already reported that 4H-SiC MOSFETs on the C(0001 _
) face had higher
inversion-channel mobility. However, there is the SiO2/SiC interface roughness problem in SiC
MOSFETs. There are many steps at the SiO2/SiC interface because a high off-angle is necessary for
SiC epitaxial growth. These steps might make SiO2/SiC interfaces rough, which leads to reduction
of channel mobility. In this work, we have investigated the effect of the SiO2/SiC interface
roughness caused by the off-angle on the inversion channel mobility of 4H-SiC MOSFETs
fabricated on the C(0001 _
) face. The inversion-channel mobility of MOSFETs fabricated on the
4H-SiC C(0001 _
) face substrate with the vicinal off-angle(0.8°) is higher than that of MOSFETs
fabricated on the 4H-SiC C(0001 _
) face substrate with the 8° off-angle. Reduction of the off-angle is
very useful for improvement of channel mobility. A C(0001 _
) epitaxial substrate with the vicinal
off-angle would be suitable for SiC DMOSFETs.
Modelling of the Anomalous Field-Effect Mobility Peak of O-Ta2Si/4H-SiC High-k MOSFETs Measured in Strong Inversion
Authors: Pérez-Tomás Amador , Vellvehi Miquel , Mestres Narcis , Millan José , Vennegues P. , Stoemenos J.
Published: March 2009

A high field-effect mobility peak (50 cm2/Vs) has been extracted in (0001) Si face 4HSiC
MOSFETs with oxidized Ta2Si (O-Ta2Si) high-k dielectric (k~20) as gate insulator, with their
gates in the strong inversion regime. The interface state density (Dit) has not been particularly
reduced in O-Ta2Si capacitors. This anomalous mobility enhancement is explained in terms of
Coulomb scattering reduction and quantified using a physical model based on the Lombardi
mobility model. The anomalous mobility increase is closely related to the leakage current, and also
to the gate breakdown mechanism. We propose a model for which the observed interfacial SiO2
tunnel current combined with Poole-Frenkel mechanisms at the O-Ta2Si gate generates a
sufficiently low abrupt transition in gate breakdown to obtain an effective passivation of the
interface traps. Under these conditions, the increase of free carriers in the inversion layer induced
by the gate leakage diminishes the effect of the interface trap Coulomb scattering.
Experimental and First-Principles Studies of the Band Alignment at the HfO2/4H-SiC (0001) Interface
Authors: Tanner Carey M. , Choi Jong Woo , Chang Jane P.
Published: March 2009

The electronic properties of HfO2 films on 4H-SiC were investigated to determine their
suitability as high-κ dielectrics in SiC power MOS devices. The band alignment at the HfO2/4HSiC
interface was determined by X-ray photoelectron spectroscopy (XPS) and supported by density
functional theory (DFT) calculations. For the experimental study, HfO2 films were deposited on ntype
4H-SiC by atomic layer deposition (ALD). XPS analysis yielded valence and conduction band
offsets of 1.69 eV and 0.75 eV, respectively. DFT predictions based on two monoclinic HfO2/4HSiC
(0001) structures agree well with this result. The small conduction band offset suggests the
potential need for further interface engineering and/or a buffer layer to minimize electron injection
into the gate oxide.
Electrical Properties of the La2O3/4H-SiC Interface Prepared by Atomic Layer Deposition Using La(iPrCp)3 and H2O
Authors: Moon Jeong Hyun , Eom Da Il , No Sang Yong , Song Ho Keun , Yim Jeong Hyuk , Na Hoon Joo , Lee Jae Bin , Kim Hyeong Joon
Published: March 2009

The La2O3 and Al2O3/La2O3 layers were grown on 4H-SiC by atomic layer deposition
(ALD) method. The electrical properties of La2O3 on 4H-SiC were examined using
metal-insulator-semiconductor (MIS) structures of Pt/La2O3(18nm)/4H-SiC and
Pt/Al2O3(10nm)/La2O3(5nm)/4H-SiC. For the Pt/La2O3(18nm)/4H-SiC structure, even though the
leakage current density was slightly reduced after the rapid thermal annealing at 500 oC,
accumulation capacitance was gradually increased with increasing bias voltage due to a high leakage
current. On the other hand, since the leakage current in the accumulation regime was decreased for
the Pt/Al2O3/La2O3/4H-SiC MIS structure owing to the capped Al2O3 layer, the capacitance was
saturated. But the saturation capacitance was strongly dependent on frequency, indicating a leaky
interfacial layer formed between the La2O3 and SiC during the fabrication process of
Pt/Al2O3(10nm)/ La2O3(5nm)/ 4H-SiC structure.
Preparation and Evaluation of Damage Free Surfaces on Silicon Carbide
Authors: Everson W.J. , Heydemann V.D. , Gamble Rick D. , Snyder David , Goda G. , Skowronski Marek , Grim J.R. , Berkman E. , Redwing Joan M. , Acord J.D.
Published: March 2009

A new chemical mechanical polishing process (ACMP) has been developed by the Penn
State University Electro-Optics Center for producing damage free surfaces on silicon carbide
substrates. This process is applicable to the silicon face of semi-insulating, conductive, 4H, 6H, onaxis
and off-axis substrates. The process has been optimized to eliminate polishing induced
selectivity and to obtain material removal rates in excess of 150nm/hour. The wafer surfaces and
resultant subsurface damage generated by the process were evaluated by white light
interferometery, Transmission Electron Microscopy (TEM), Atomic Force Microscopy (AFM), and
epitaxial layer growth. Residual surface damage induced by the polishing process that propagates
into the epitaxial layer has been significantly reduced. Total dislocation densities measured on the
ACMP processed wafers are on the order of the densities reported for the best as grown silicon
carbide crystals [1]. Characterization of high electron mobility transistors (HEMTs) grown on these
substrates indicates that the electrical performance of the substrates met or exceeded current
requirements [2].
Selectivity and Residual Damage of Colloidal Silica Chemi-Mechanical Polishing of Silicon Carbide
Authors: Grim J.R. , Skowronski Marek , Everson W.J. , Heydemann V.D.
Published: March 2009

The selectivity, material removal rate, and the residual subsurface damage of colloidal
silica (CS) chemi-mechanical polishing (CMP) of silicon carbide substrates was investigated using
atomic force microscopy (AFM) and plan view transmission electron microscopy (TEM). Silica
CMP, in most process conditions, was selective. In the damage region surrounding remnant
scratches, the vertical material removal rate exceeded the planar material removal rate, which
resulted in an enhancement of the scratches over the duration of the polishing process. The material
removal rate was low, about 20 nm / hr. In addition, the selectivity leads to a slow removal of
residual subsurface damage from mechanical polishing. The silica CMP polished surface exhibits
significant subsurface damage observed by plan view TEM even after prolonged polishing of 16
hours.
Gas Fed Top-Seeded Solution Growth of Silicon Carbide
Authors: Chaussende Didier , Pons Michel , Madar Roland
Published: March 2009

The growth of SiC crystals or epilayers from the liquid phase has already been reported
for many years. Even if the resulting material can be of very high structural quality and the
possibility to close micropipes was demonstrated, handling the liquid phase still is a challenge.
Moreover, it is highly difficult to stabilize the C dissolution front and then to stabilize the growth
front over a long growth time. Based on the Vapour-Liquid-Solid mechanism, we present a new
configuration for the growth of SiC single crystal which should allow first to simplify the liquid
handling at high temperature and second to precisely control the crystal growth front. The process
consists in a modified top seeded solution growth method, in which the liquid is held under electromagnetic
levitation and fed from the gas phase. In a Co-Si solution fed from a propane flow at
1350°C, thick epitaxial layers of 4H-SiC have been grown at 28 0m/h. The potentiality of this new
process will be discussed in the paper.
Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET
Authors: Kelley Robin L. , Brignac T. , Mazzola Michael S. , Casady Jeff B.
Published: March 2009

The power junction field effect transistor (JFET) is the second most mature SiC device,
after the SiC Schottky diode, and is commonly associated with normally on functionality; but this
feature is often viewed problematically for off-line dc-to-dc converter applications. Two inherently
safe, single-switch dc-dc converter designs have been developed that put into practice pure SiC
JFET devices (i.e., without cascoded devices) that possess enhancement-mode functionality and
bias-enhanced blocking. These ‘Quasi-Off’ devices are designed to block half of the rated blocking
voltage at zero gate bias and achieve full rated blocking voltage with a modest negative bias,
typically between 0 and -5 V. Inherent safety is provided by utilizing the enhancement mode
functionality of these devices as well as appropriate gate driver design. Bias enhanced blocking
matches the dynamic stress encountered by modern high-frequency power supply topologies to the
ratings of the device while recognizing that the larger dynamic stress is typically encountered only
when the power supply (and especially the gate driver) is functioning properly.
Switching Characteristics of SiC-MOSFET and SBD Power Modules
Authors: Imaizumi Masayuki , Tarui Yoichiro , Kinouchi Shin Ichi , Nakatake Hiroshi , Nakao Yukiyasu , Watanabe Tomokatsu , Fujihira Keiko , Miura Naruhisa , Takami Tetsuya , Ozeki Tatsuo
Published: March 2009

Prototype SiC power modules are fabricated using our class 10 A, 1.2 kV SiC-MOSFETs
and SiC-SBDs, and their switching characteristics are evaluated using a double pulse method.
Switching waveforms show that both overshoot and tail current, which induce power losses, are
suppressed markedly compared with conventional Si-IGBT modules with similar ratings. The total
switching loss (MOSFET turn-ON loss, turn-OFF loss and SBD recovery loss) of SiC power modules
is measured to be about 30% of that of Si-IGBT modules under the generally-used switching
condition (di/dt ~250A/μs). The three losses of SiC modules decrease monotonically with a decrease
in gate resistance, namely switching speed. The result shows the potential of unipolar device SiC
power modules.
Recent Progress of SiC Hot-Wall Epitaxy and Its Modeling
Authors: Nishizawa Shin Ichi , Pons Michel
Published: March 2009

From the engineering point of view, SiC hot-wall epitaxy is a very important process in
SiC semiconductor processes. There are lots of experimental reports on SiC hot-wall epitaxy. They
discussed the growth rate, surface morphology, doping concentration, etc. Recently, the effect of
face polarity is also made clear. However, each report mentioned the particular results that strongly
depend on the experimental conditions and reactor design. In addition, the discussion with inlet
condition such as source gas C/Si ratio, not the depositing surface condition, leads to the confusion.
In order to understand and try to design and optimize the hot-wall CVD reactor, a numerical approach
is attempted. The authors have tried to make it clear that depositing surface condition might be a
universal parameter of SiC CVD, and the numerical simulation could predict the growth rate, surface
morphology and doping concentration by taking account of the depositing surface condition. In this
study, at first, the recent progress of SiC hot-wall epitaxy in experiment is summarized. Then, the
present status of its numerical modeling is explained.
Fabrication of 4H-SiC DIMOSFETs by High-Temperature (>1400°C) Rapid Thermal Oxidation and Nitridation Using Cold-Wall Oxidation Furnace
Authors: Kosugi Ryouji , Suzuki Kenji , Takao Kazuto , Hayashi Yusuke , Yatsuo Tsutomu , Fukuda Kenji , Ohashi Hiromichi , Arai Kazuo
Published: March 2009

A passivation annealing in nitric oxide (NO) ambient significantly reduces the interfacial
defects of the SiO2/4H-SiC interface and improves the inversion MOS channel mobility. Effects of
the nitridation in NO ambient become more pronounced at high temperatures in general. However,
the maximum process temperature in a standard hot-wall oxidation furnace is restricted around
1200oC due to the softening point of quartz. Meanwhile, by use of a cold-wall oxidation furnace, high
temperature and short time thermal processes become possible. In this study, we have developed an
extremely high temperature (>1400oC) rapid thermal processing for the gate oxidation in the 4H-SiC
DIMOSFET fabrication process. The peak MOS channel mobility of lateral MOSFETs on the
DIMOSFET chip shows as high as 19cm2/Vs. The specific on-resistance of the device was
12.5mcm2 and the blocking voltage was 950V with gate shorted to the source.
Evolution of Drift-Free, High Power 4H-SiC PiN Diodes
Authors: Das Mrinal K. , Sumakeris Joseph J. , Hull Brett A. , Richmond Jim
Published: March 2009

The PiN diode is an attractive device to exploit the high power material advantages of
4H-SiC. The combination of high critical field and adequate minority carrier lifetime has enabled
devices that block up to 20 kV and carry 25 A. Furthermore, these devices exhibit fast switching
with less reverse recovery charge than commercially available Si PiN diodes. The path to
commercialization of the 4H-SiC PiN diode technology, however, has been hampered by a
fundamental problem with the forward voltage stability resulting from stacking fault growth
emanating from basal plane screw dislocations (BPD). In this contribution, we highlight the
progress toward producing stable high power devices with sufficient yield to promote commercial
interest. Two independent processes, LBPD1 and LBPD2, have been shown to be effective in
reducing the BPD density and enhancing the forward voltage stability while being compatible with
conventional power device fabrication. Applying the LBPD1 and LBPD2 processes to 10 kV (20 A
and 50 A) 4H-SiC PiN diode technology has resulted in a dramatic improvement in the total device
yield (forward, reverse, and forward drift yields) from 0% to >20%. The LBPD1 process appears to
be more robust in terms of long term forward voltage stability.
Demonstration of a 4H SiC Betavoltaic Cell
Authors: Chandrashekhar M.V.S. , Thomas Christopher I. , Li Hui , Spencer Michael G. , Lal Amit
Published: March 2009

A betavoltaic cell in 4H SiC is demonstrated. An abrupt p-n diode structure was used to
collect the charge from a 1mCi Ni-63 source. An open circuit voltage of 0.95V and a short circuit
current density of 8.8 nA/cm2 were measured in a single p-n junction. An efficiency of 3.7% was
obtained. A simple photovoltaic type model was used to explain the results. Good correspondence
with the model was obtained. Fill factor and backscattering effects were included. Efficiency was
limited by edge recombination and poor fill factor.
Dynamic Characteristics of 4H-SiC pin Diode on (000-1)C-Face with Small Forward Degradation
Authors: Nakayama Koji , Sugawara Yoshitaka , Ishii R. , Tsuchida Hidekazu , Miyanagi Toshiyuki , Kamata Isaho , Nakamura Tomonori
Published: March 2009

Forward voltage degradation has been reduced by fabricating diodes on the (000-1)C-face.
The reverse recovery characteristics of the 4H-SiC pin diode on the (000-1)C-face have been
investigated. The pin diode on the C-face has superior potential to that on the Si-face among all
parameters of the reverse recovery characteristics. The pin diode on the Si-face after conducting a
current stress test tends to exhibit a fast turn-off as compared with that before conducting the stress
test. On the C-face, however, there is little difference in reverse recovery characteristics between
before and after conducting the current stress test.
High Power Photoconductive Switch of 4H-SiC with Damage-Free Electrodes by Using n+-GaN Subcontact Layer
Authors: Zhu K. , Li G. , Johnstone D. , Fu Y. , Leach J.H. , Ganguly B. , Litton Cole W. , Morkoç Hadis
Published: March 2009

4H SiC high power photoconductive semiconductor switching devices were fabricated. A
highly doped n+-GaN subcontact epilayer was grown on SiC by organometallic vapor phase epitaxy
in order to improve ohmic contact and avoid contact damage or degradation due to current
filamentation, under high power operation. With an n+-GaN subcontact layer, the contact resistance
was reduced and current crowding alleviated. Therefore the electrodes were not damaged or
degraded at high power operation. Photocurrent up to 200 A and breakdown voltage up to 2900 V
have been observed for the devices.
Simulation of High-Voltage Injection-Enhanced 4H-SiC N-Channel IGBTs with Forward Drop Approaching that of a PiN Junction Rectifier
Authors: Zhu Lin , Chow T. Paul
Published: March 2009

For SiC devices capable of blocking very high voltages (>4kV), it becomes
imperative to use bipolar devices because of unacceptably large on-state losses of unipolar
devices. The IGBT offers the potential for high current density operation and ease of turn off
using a MOS gate structure. In this work, 15kV 4H-SiC n-channel UMOS PT (Punch
Through) IGBTs with injection enhancement effect near the top emitter and transparent pemitter
structure at the collector have been demonstrated to have a forward drop approaching
that of a PiN junction rectifier. With proper design, a PiN-like carrier distribution in the drift
region can be achieved, which allows a better trade-off between collector-emitter saturation
voltage (VCE(sat)) and turn-off loss (Eoff) than conventional SiC UMOS IGBTs.
4H-SiC Bipolar Transistors with UHF and L-Band Operation
Authors: Perez-Wurfl Ivan , Zhao Feng , Huang Chih Fang , Torvik John , Van Zeghbroeck Bart
Published: March 2009

We report for the first time on RF SiC BJTs fabricated on semi-insulating (SI) substrates
with L-band performance. Small-periphery (4x150μm) devices were tested using on-wafer load-pull
measurements up to 1.5GHz. Under pulsed conditions, the devices exhibited 10dB of power gain at
1GHz and a peak power density of 2.3W/mm (1.4W) with a 100μs pulse width and a 1% duty cycle.
The power gain decreased to 8dB at 1GHz under CW conditions at a power density of 1.6W/mm
(1W). The load-pull measurements were performed up to 125oC, which resulted in a 1 dB reduction
of power gain compared to the room temperature performance. Results at 0.5 and 1.5 GHz are
presented as well.
Asymmetric Interface Densities on n and p Type GaN MOS Capacitors
Authors: Huang W. , Khan T. , Chow T. Paul
Published: March 2009

Both n-type and p-type GaN MOS capacitors with plasma-enhanced CVD-SiO2 as the
gate oxide were characterized using both capacitance and conductance techniques. From a n type
MOS capacitor, an interface state density of 3.8×1010/cm2-eV was estimated at 0.19eV near the
conduction band and decreases deeper into the bandgap while from a p type MOS capacitor, an
interface state density of 1.4×1011/cm2-eV 0.61eV above the valence band was estimated and
decreases deeper into the bandgap. Unlike the symmetric interface state density distribution in Si,
an asymmetric interface state density distribution with lower density near the conduction band and
higher density near the valence band has been determined.
Electron Injection from GaN to SiC and Fabrication of GaN/SiC Heterojunction Bipolar Transistors
Authors: Suda Jun , Nakano Yuki , Shimada Syouta , Amari Koichi , Kimoto Tsunenobu
Published: March 2009

Characterization of n+-GaN/p−-SiC and n+-GaN/p+-SiC heterojunctions as well as
fabrication of GaN/SiC heterojunction bipolar transistors (HBTs) using these heterojunctions is
presented. The electroluminescence spectrum from n+-GaN/p+-SiC heterojunction diodes under
forward bias clearly indicates electron injection from n+-GaN into p+-SiC. HBTs consisting of
n+-GaN emitter /p+-SiC base/n−-SiC collector/n+-SiC substrate have been fabricated. Although clear
common-base properties were obtained, the current gain was very low (10-4). SiC homojunction
bipolar junction transistors (BJT) using the same base-collector junction exhibited a current gain
value of 0.5, suggesting the low current gain of GaN/SiC HBTs originates from low emitter
efficiency.
SNOM Investigation of Surface Morphology Changes during Cr/Au Contact Fabrication on Single-Crystal CVD Diamond
Authors: Doneddu D. , Guy Owen James , Baylis R.M. , Chen L. , Dunstan P.R. , Mawby Philip  Andrew , Pirri C. Fabrizio , Ferrero Sergio , Twitchen D. , Tajani A. , Schwitters M.
Published: March 2009

The formation of metal/diamond Ohmic contacts is essential to most electronic devices.
In order to form a good Ohmic contact to diamond a carbide-forming metal such as Ti or Cr is
necessary. In this study, Cr/Au contacts to heavily boron-doped single crystal CVD diamond were
fabricated by subsequent deposition of Cr and Au. The surface morphology and specific contact
resistance of diamond/Cr/Au contacts has been investigated. The reaction between the Cr metal and
the diamond during annealing gives an improved specific contact resistance. However, this reaction
also causes a significant change in the surface morphology. The surface morphology of singlecrystal
diamond is shown to greatly influence the properties of metal contacts to diamond. Shearforce
mode atomic force microscopy (AFM) investigations have been used to examine the diamond
surface before metallization, and after removing the metal contact. The initial diamond surface was
predominantly smooth, apart from some scratches from the polishing process. Surface RMS
roughness values of around 0.4nm were found. Correlation between surface morphology and
contact resistance has been found, with rougher surfaces exhibiting a barrier to conduction. An
understanding of the contact formation process is an essential step in achieving high quality Ohmic
contacts which are vital in the fabrication of high quality diamond devices.
SiC Warm-Wall Planetary VPE Growth on Multiple 100-mm Diameter Wafers
Authors: Burk Albert A. , O'Loughlin Michael  J. , Paisley Michael J. , Powell Adrian R. , Brady M.F. , Leonard R.T. , McClure D.A.
Published: March 2009

Experimental results are presented for SiC epitaxial layer growth employing a large-area,
up to 8x100-mm, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been
optimized for the growth of uniform 0.01 to 80-micron thick, specular, device-quality SiC epitaxial
layers with low background doping concentrations of <1x1014 cm-3 and intentional p- and n-type
doping from ~1x1015 cm-3 to >1x1019 cm-3. Intrawafer layer thickness and n-type doping uniformity
(σ/mean) of ~2% and ~8% have been achieved to date in the 8x100-mm configuration. The total
range of the average intrawafer thickness and doping within a run are approximately ±1% and ±6%
respectively.
Homoepitaxial Growth of 4H-SiC Using a Chlorosilane Silicon Precursor
Authors: MacMillan Mike F. , Loboda Mark J. , Chung Gil Yong , Carlson E.P. , Wan Jian Wei
Published: March 2009

Epitaxial growth of SiC films was performed on 4H SiC n+ substrates utilizing a
chlorosilane/propane chemistry in both single wafer and batch CVD systems. Variations of
the chlorosilane flow under fixed conditions of gas composition, temperature and pressure
resulted in growth rates between 4 to 20 μm/hr. Fixing the chlorosilane flow rate to achieve a
growth rate of approximately 4 μm/hr, the effects of temperature, pressure and gas
composition on background dopant incorporation, epitaxial layer uniformity and epitaxial
defect generation were investigated. Intentional n and p-type doping has been demonstrated
over the carrier range 1×1018-1×1020/cm3. This paper presents the first reported of use of
chlorosilane precursors to grow high quality undoped, n and p doped SiC epilayers.
SiC-4H Epitaxial Layer Growth Using Trichlorosilane (TCS) as Silicon Precursor
Authors: Leone Stefano , Mauceri Marco , Pistone Giuseppe , Abbondanza Giuseppe , Portuese F. , Abagnale Giovanni , Valente Gian Luca , Crippa Danilo , Barbera Milo , Reitano Ricardo , Foti Gaetano , La Via Francesco
Published: March 2009

4H-SiC epitaxial layers have been grown using trichlorosilane (TCS) as the silicon
precursor source together with ethylene as the carbon precursor source. A higher C/Si ratio is
necessary compared with the silane/ethylene system. This ratio has to be reduced especially at
higher Si/H2 ratio because the step-bunching effect occurs. From the comparison with the process
that uses silane as the silicon precursor, a 15% higher growth rate has been found using TCS
(trichlorosilane) at the same Si/H2 ratio. Furthermore, in the TCS process, the presence of chlorine,
that reduces the possibility of silicon droplet formation, allows to use a high Si/H2 ratio and then to
reach high growth rates (16 *m/h). The obtained results on the growth rates, the surface roughness
and the crystal quality are very promising.
Properties of Thick n- and p-Type Epitaxial Layers of 4H-SiC Grown by Hot-Wall CVD on Off- and On-Axis Substrates
Authors: Hassan Jawad , Hallin Christer , Bergman Peder , Janzén Erik
Published: March 2009

Thick epitaxial layers of 4H-SiC both n- and p-type were grown using horizontal Hot-
Wall CVD (HWCVD). No large difference in the carrier lifetime was observed for the layers grown
on n- and p-type substrates. The carrier lifetime usually increases with the increasing thickness of
the epilayer. To investigate if the growth conditions and material properties are changing during the
longer growth time a sample was prepared with uniformly varying epilayer thickness from 20μm on
one side to 110μm on other side. Results of optical and electrical measurements, the variation in
background impurities and other deep levels are discussed. Furthermore, the properties of thick
layers grown on on-axis substrates are presented.