bluuebunny/crossref_metadata_2025 huggingface dataset:
RELAXATION METHOD FOR NAVIER–STOKES EQUATION
Authors: DE OLIVEIRA P. M. C.
Published: February 2012

The motivation for this work was a simple experiment [P. M. C. de Oliveira, S. Moss de Oliveira, F. A. Pereira and J. C. Sartorelli, preprint (2010), arXiv:1005.4086], where a little polystyrene ball is released falling in air. The interesting observation is a speed breaking. After an initial nearly linear time-dependence, the ball speed reaches a maximum value. After this, the speed finally decreases until its final, limit value. The provided explanation is related to the so-called von Kármán street of vortices successively formed behind the falling ball. After completely formed, the whole street extends for some hundred diameters. However, before a certain transient time needed to reach this steady-state, the street is shorter and the drag force is relatively reduced. Thus, at the beginning of the fall, a small and light ball may reach a speed superior to the sustainable steady-state value.

Besides the real experiment, the numerical simulation of a related theoretical problem is also performed. A cylinder (instead of a 3D ball, thus reducing the effective dimension to 2) is positioned at rest inside a wind tunnel initially switched off. Suddenly, at t = 0 it is switched on with a constant and uniform wind velocity [Formula: see text] far from the cylinder and perpendicular to it. This is the first boundary condition. The second is the cylinder surface, where the wind velocity is null. In between these two boundaries, the velocity field is determined by solving the Navier–Stokes equation, as a function of time. For that, the initial condition is taken as the known Stokes laminar limit V → 0, since initially the tunnel is switched off. The numerical method adopted in this task is the object of the current text.
A NOTE ON THE UNIFIED FIRST LAW IN f(R) GRAVITY THEORY
Authors: ZHANG YI , GONG YUNGUI , ZHU ZONG-HONG
Published: February 2012

Because of the dynamical equivalence between the f(R) gravity and the Brans-Dicke theory, the dynamical equation in the f(R) gravity is suggested to be derived from a view point of thermodynamics here. By a conformal transformation, the Brans–Dicke theory in the Jordan frame could be expressed as a minimal coupling scalar field theory in Einstein frame. Using the entropy-area relation [Formula: see text], the correct Friedmann equations could be gotten in both frames. Furthermore, we also discuss the corresponding generalized Misner–Sharp energies for theoretical consistence.
ON OCTONIONIC GRAVITY, EXCEPTIONAL JORDAN STRINGS AND NONASSOCIATIVE TERNARY GAUGE FIELD THEORIES
Authors: CASTRO CARLOS
Published: February 2012

Novel nonassociative octonionic ternary gauge field theories are proposed based on a ternary bracket. This paves the way to the many physical applications of exceptional Jordan Strings/Membranes and Octonionic Gravity. The old octonionic gravity constructions based on the split octonion algebra Os (which strictly speaking is not a division algebra) is extended to the full fledged octonion division algebra O. A real-valued analog of the Einstein–Hilbert Lagrangian [Formula: see text] involving sums of all the possible contractions of the Ricci tensors plus their octonionic-complex conjugates is presented. A discussion follows of how to extract the Standard Model group (the gauge fields) from the internal part of the octonionic gravitational connection. The role of exceptional Jordan algebras, their automorphism and reduced structure groups which play the roles of the rotation and Lorentz groups is also re-examined. Finally, we construct (to our knowledge) generalized novel octonionic string and p-brane actions and raise the possibility that our generalized 3-brane action (based on a quartic product) in octonionic flat backgrounds of 7,8 octonionic dimensions may display an underlying E7, E8 symmetry, respectively. We conclude with some final remarks pertaining to the developments related to Jordan exceptional algebras, octonions, black-holes in string theory and quantum information theory.
CLIFFORD MODULES AND SYMMETRIES OF TOPOLOGICAL INSULATORS
Authors: ABRAMOVICI GILLES , KALUGIN PAVEL
Published: February 2012

We complete the classification of symmetry constraints on gapped quadratic fermion hamiltonians proposed by Kitaev. The symmetry group is supposed compact and can include arbitrary unitary or antiunitary operators in the Fock space that conserve the algebra of quadratic observables. We analyze the multiplicity spaces of real irreducible representations of unitary symmetries in the Nambu space. The joint action of intertwining operators and antiunitary symmetries provides these spaces with the structure of Clifford module: we prove a one-to-one correspondence between the ten Altland–Zirnbauer symmetry classes of fermion systems and the ten Morita equivalence classes of real and complex Clifford algebras. The antiunitary operators, which occur in seven classes, are projectively represented in the Nambu space by unitary "chiral symmetries". The space of gapped symmetric hamiltonians is homotopically equivalent to the product of classifying spaces indexed by the dual object of the group of unitary symmetries.
A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process
Authors: Kiumarsi Hamid , Mizuochi Yutaka , Ito Hiroyuki , Ishihara Noboru , Masu Kazuya
Published: February 2012

A three-stage inverter-based stacked power amplifier (PA) in complementary metal oxide semiconductor (CMOS) process is proposed to overcome low breakdown voltage problem of scaled CMOS technologies. Unlike previous reported stacked PAs which radio frequency choke (RFC) was inevitable, we proposed stacked nMOS and pMOS transistors which effectively eliminates use of RFC. By properly setting self-biased circuits' and transistors' parameters, output impedance could reach up to 50 Ω which together with not employing the RFC makes this topology very appealing for the scalable PA realization. As a proof of concept, a three-stage PA using 65 nm CMOS technology is implemented. With a 6 V power supply for the third stage, the fabricated PA shows a small-signal gain of 36 dB, a saturated output power of 16 dBm and a maximum power added efficiency of 10% at 1 GHz. Using a 7.5 V of power supply, saturated output power reaches 18 dBm. To the best of our knowledge, this is the first reported inverter-based stacked PA.
Characteristics of Hot Hole Injection, Trapping, and Detrapping in Gate Oxide of Polycrystalline Silicon Thin-Film Transistors
Authors: Kamakura Yoshinari , Himukashi Takashi , Tsuji Hiroshi , Taniguchi Kenji
Published: February 2012

The characterization and modeling of the hysteresis phenomenon observed in the off-state regime of n-channel polycrystalline thin-film transistors are presented. The shift in I
d–V
g characteristics between upward and downward scan were measured under various bias conditions and ambient temperatures. The localized positive charge build-up induced by band-to-band hot hole injection is responsible for the mechanism for reducing the off-leakage current, and it is recovered through the thermal emission of trapped holes, which is enhanced by self-heating of the device during the on-current conduction. On the basis of this model, the internal device characteristics related to the thermal and oxide trap properties are analyzed.
Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Mao Ke , Mizutani Tomoko , Kumar Anil , Saraya Takuya , Hiramoto Toshiro
Published: February 2012

In this paper, the variabilities of threshold voltage (V
TH), drain-induced barrier lowering (DIBL), and current onset voltage (COV) in intrinsic channel silicon nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) were evaluated and compared with those of conventional bulk and fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. The random component of variability is extracted by a “within-device” variability method to exclude the systematic component. It is found that the within-device variabilities of DIBL and COV as well as V
TH are extremely small in intrinsic channel nanowire MOSFETs owing to the non-intentionally doped channel and small gate workfunction variability. The intrinsic channel nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression.
Characterization of Oxide Tarps in 28 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Tip-Shaped SiGe Source/Drain Based on Random Telegraph Noise
Authors: Wang Bo Chin , Wu San Lein , Huang Chien Wei , Lu Yu Ying , Chang Shoou Jinn , Lin Yu Min , Lee Kun Hsien , Cheng Osbert
Published: February 2012

In this study, the impact of embedded tip-shaped SiGe in the source/drain (S/D) region on individual trap behavior such as activation energy and depth from the SiO2/Si interface of the 28 nm p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) has been investigated on the basis of drain current random telegraph noise (RTN). The purpose of implementing tip-shaped SiGe S/D is to further increase channel stress because it provides a closer proximity of embedded SiGe to the channel. By characterizing RTN, we found that the pMOSFETs underwent uniaxial compressive strain that was provided by tip-shaped SiGe S/D, and the trap energy level being close to the channel valence band resulted in the trap located close to the Si/SiO2 interface, as compared with the control device without embedded SiGe S/D.
Investigation of Hot-Carrier Stress Effect on High-Frequency Performance of Laterally Diffused Metal–Oxide–Semiconductor Transistors
Authors: Chen Kun-Ming , Mou Zong-Wen , Kuo Hao-Chung , Chiu Chia-Sung , Chen Bo-Yuan , Liu Wen-De , Chen Ming-Yi , Yang Yu-Chi , Wang Kai-Li , Huang Guo-Wei
Published: February 2012

The hot-carrier stress effects on the high-frequency performance characteristics of laterally diffused metal–oxide–semiconductor (LDMOS) transistors were investigated. A constant bias channel hot-carrier stress was applied at room temperature. After applying 3 h of hot-carrier stress, the on-resistance and saturation drain current degradations are 18 and 9%, respectively. However, the degradations of the cutoff frequency and maximum oscillation frequency were less than 2% when the devices were biased before the onset of quasi-saturation. In addition, we found that the degradations of high-frequency parameters are not related to the change in transconductance but to the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress were also examined in this study. The observations of S-parameter variations are important for RF power amplifier design.
Impact of Dynamic Stress on Reliability of Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with SiON Gate Dielectric Operating in a Complementary Metal–Oxide–Semiconductor Inverter at Elevated Temperature
Authors: Lee Nam-Hyun , Kim Hyung-wook , Kang Bongkoo
Published: February 2012

This paper investigates the impact of dynamic stress on the reliability of a nanoscale n-channel metal–oxide–semiconductor field effect transistor (nMOSFET) with a SiON gate dielectric operating in a complementary metal–oxide–semiconductor (CMOS) inverter at an elevated temperature T. Experimental results indicate that the shift of threshold voltage V
th by dynamic stress is much larger than that by various static stresses in short channel nMOSFETs. Under a dynamic stress, the OFF-state stress generated interface traps and unfilled electron traps because of the OFF-state hot carrier effect due to drain induced barrier lowering (DIBL) at high T. Although the subsequent ON-state did not produce any new defects, it filled the electron traps, which increased the V
th abruptly. Consecutive application of OFF- and ON-state stresses caused a buildup of recoverable and permanent electron traps, and interface traps, thereby resulting in the significant increase in V
th. In addition, the dynamic stress degradation was frequency-independent up to 500 kHz and its impact on nMOSFET lifetime depends strongly on gate lengths. These results indicate that OFF-state induced defects are the main cause for dynamic stress degradation and can impose a significant limitation on CMOS device scaling.
Impact of Gate Poly Depletion on Evaluation of Channel Temperature in Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with Four-Point Gate Resistance Measurement Method
Authors: Beppu Nobuyasu , Takahashi Tsunaki , Ohashi Teruyuki , Uchida Ken
Published: February 2012

Self-heating effects (SHEs) in silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is evaluated and an accurate measurement method for device temperature is developed using the four-point gate resistance measurement method. Although the method of using a polysilicon gate as a temperature sensor was proposed more than 20 years ago, the accuracy of the technique has not been checked. In this work, it is demonstrated that the channel temperature estimated by the conventional method is not accurate under some special conditions. The measurements of gate resistance under various biases revealed that the depletion of the polysilicon gate had a significant impact on gate resistance. We propose a method of accurately evaluating channel temperature, where the effect of poly depletion is successfully subtracted. At an input power of 5 mW the increase in channel temperature is approximately 30 K, corresponding to a thermal resistance of 6.0 K W-1 m-1.
High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction
Authors: Ohsawa Takashi , Iga Fumitaka , Ikeda Shoji , Hanyu Takahiro , Ohno Hideo , Endoh Tetsuo
Published: February 2012

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).
A Compact Half Select Disturb Free Static Random Access Memory Cell with Stacked Vertical Metal–Oxide–Semiconductor Field-Effect Transistor
Authors: Na Hyoungjun , Endoh Tetsuo
Published: February 2012

In this paper, a half select disturb free compact static random access memory (SRAM) cell with the stacked vertical metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed, and the impacts on its cell size, stability and speed performance are evaluated. The proposed SRAM cell has a small cell size, which is 67% of the conventional eight-transistor (8T) SRAM cell, because of its stacked vertical MOSFET structure. It realizes a half select disturb free SRAM operation; therefore, a larger static noise margin of 5.9 times is achieved in comparison with the conventional 8T SRAM cell. It suppresses the degradation of the write margin, thus its write margin is 84.2% of the conventional 8T SRAM cell. Furthermore, it suppresses the degradation of the write time by 39% (0.249 ns). The proposed compact SRAM cell with the stacked vertical MOSFET is a suitable SRAM cell with a small cell size, immunity to the half select disturb, wide write margin and fast write time.
Practical Consideration of Both Endurance and Performance for Sub-90 nm Embedded Two Transistor Fowler–Nordheim Tunneling Flash Memory
Authors: Lee Yong Kyu , Seo Boyoung
Published: February 2012

Practical consideration about performance and endurance of two transistor Fowler–Nordheim tunneling (2T-FN) embedded flash cell has been suggested to expand its application not only for subscriber identity module (SIM) but also new various uses in smart-phone. We present practical 35% improvement on endurance characteristics (ΔV
th) without any performance degradation.
Effect of Resistance Drift on the Activation Energy for Crystallization in Phase Change Memory
Authors: Ahn Chiyui , Lee Byoungil , Jeyasingh Rakesh G. D. , Asheghi Mehdi , Hurkx Fred , Goodson Kenneth E. , Wong H.-S. Philip
Published: February 2012

The crystallization properties of phase-change memory (PCM) in the presence of thermal disturbances are investigated with a novel micro-thermal stage. It is found that the recrystallization time due to thermal disturbances significantly varies depending on how the PCM cell drifts. The longer crystallization time is obtained following additional resistance drift, which can be described by an increase of the effective activation energy for crystallization. The possibility of achieving better retention in a PCM cell by allowing the PCM cell to drift for a longer time is demonstrated in this work. The activation energy changes at a rate of more than 1 eV/decade with varying time intervals below a second. As the ambient temperature gets higher, the effect of resistance drift on the crystallization process is diminished with respect to the dominant crystallization process which has a higher crystal growth rate at elevated ambient temperatures.
Through-Silicon-Via Design with Clustering Structure and Adaptive Through-Silicon-Via Control for Three-Dimentional Solid-State-Drive Boost Converter System
Authors: Johguchi Koh , Hatanaka Teruyoshi , Takeuchi Ken
Published: February 2012

This paper presents a through-silicon-via (TSV) design methodology for three-dimentional solid-state-drive (3D-SSD) system with the 20 V boost converter. Although TSV technologies give compact packaging and high performance compared to the conventional wire-bonding technology, the parasitic resistors and capacitors of TSVs may cause the performance degradation. Additionally, since the number of the activated NAND chip is dynamically changed as access patterns from real processor, the optimum design point for the boost converter is also moved according to the situation. Then, the clustering method with two different sizes of Cu-TSVs and the adaptive TSV number controlling technique for polycrystalline silicon TSVs are proposed to reduce the parasitic resistors and capacitors. With the cluster structure and Cu-TSVs, the performance of the proposed 3D-SSD is improved by ∼10%. Furthermore, the adaptive TSV number controller enhances the performance up to 2 times higher for poly-Si TSV case by reducing the parasitic elements due to TSVs.
1.2–17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor
Authors: Lee Sang-yeop , Ito Hiroyuki , Amakawa Shuhei , Tanoi Satoru , Ishihara Noboru , Masu Kazuya
Published: February 2012

A wide-frequency-range phase-locked loop (PLL) with subharmonic injection locking is proposed. The PLL is equipped with a wide tunable ring-type voltage-controlled oscillator (ring VCO), frequency dividers, and a doubler in order to the widen injection-locked tuning range (ILTR). In addition, high-frequency injection signals are used to improve phase noise, which is supposed to be generated by a reference PLL. The proposed circuit is fabricated by using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. The measured frequency tuning range is from 1.2 to 17.6 GHz with a frequency doubler and dividers. The phase noise at 14.4 GHz (=32×450 MHz) with injection locking was -109 dBc/Hz, which shows a 21-dB reduction compared with that in the case without injection locking.
Efficient Image-Vector-Generation Processor for Edge-Based Complementary Feature Representations
Authors: Yamashita Naoya , Shibata Tadashi
Published: February 2012

A digital processor dedicated to edge-based image vector generation has been developed aiming at real-time image recognition. The processor consists of an on-chip memory and 16 single instruction multiple data (SIMD) processing elements. The capacity of the on-chip memory as well as the overhead for starting the processing have been minimized by introducing a seamless data transferring scheme from memory to processing elements. The 16 SIMD processing elements work together either as accumulators or as shift registers, thus achieving a very efficient generation of two different kinds of feature vector: projected principal-edge distribution (PPED)[3,4] and averaged principal-edge distribution (APED).[5] Concurrent use of these two vectors is shown to be very important for robust image recognition.[5] The chip was fabricated using 0.18-µm complementary metal oxide semiconductor (CMOS) technology and the generation of 64-dimension PPED and APED vectors at 84.7 and 83.9 fps, respectively, from video graphics array (VGA) size images was demonstrated at 62.5 MHz.
Asynchronous Pulse Transmitter for Power Reduction in Inductive-Coupling Link
Authors: Saito Mitsuko , Miura Noriyuki , Kuroda Tadahiro
Published: February 2012

An asynchronous pulse transmitter is proposed to achieve low power in inductive-coupling link. The conventional asynchronous transmitter, H-bridge inductive-coupling transmitter, consumes large static (DC) current consumption. Therefore the transmit power dissipation is dominant in the total inductive-coupling power dissipation. The proposed pulse inductive-coupling transmitter eliminates the static (DC) current consumption. It provides linear power scalability which significantly reduces the power consumption especially at low data rate operation for low-power mobile applications. To verify the proposed technique, we designed and fabricated test chips in TSMC 0.18 µm complementary metal oxide semiconductor (CMOS) technology. Both proposed pulsed transmitter and conventional H-bridge transmitter is implemented in the test chip for comparison. Power reduction to 1/4 at 1.5 Gbps and 1/60 at 100 Mbps is achieved compared to the conventional transmitter. Also a crosstalk immune inductive-coupling receiver is presented for low-power relayed transmission using the proposed pulse transmitter. Crosstalk guard circuit is implemented in the receiver to ignore crosstalk. Data is successfully transferred using relayed transmission with proposed transceiver at up to 400 Mbps.
Nonvolatile Low Power 16-bit/32-bit Magnetic Tunnel Junction Based Binary Counter and Its Scaling
Authors: Togashi Shuta , Ohsawa Takashi , Endoh Tetsuo
Published: February 2012

We propose a nonvolatile 16-bit/32-bit magnetic tunnel junction (MTJ) based binary counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-bit/32-bit counter is 59.1 and 72.5% smaller in case of 45 and 16 nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) counter at low frequency (100 Hz). The proposed nonvolatile 32-bit counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16 nm node, respectively, in comparison with the conventional CMOS counter. Moreover, we propose a hybrid 32-bit counter that is constructed with CMOS counter units for the beginning stages and nonvolatile MTJ based counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS counter for 16 nm node. As a result, clear scalability of the proposed MTJ based multi-bit counter is obtained from the viewpoint of suppressing power.
Reduced-Ripple p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump Circuit with Small Filtering Capacitance
Authors: Jaw Boy-Yiing , Lin Hongchin
Published: February 2012

This paper presents a two-stage, two-phase, p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) charge pump with special two-step clocks for ripple reduction. The ripple voltage can be reduced by adjusting the overdrive voltage during charge transfer. The charge pump including the circuit of the proposed clocks and 5 pF boosting capacitance was fabricated using 0.35 µm complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) technology in an area of 0.182 mm2. With the new clock scheme, high voltage gain and driving capacity without overstress of the transistors are preserved. The experimental results reveal that the output voltage ripple is reduced from 23.2 to 12.8 mV for an output current of 36 µA at a frequency of 10 MHz and a supply voltage of 1.8 V, which indicates a 45% ripple reduction without increasing filtering capacitance.
Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Suleiman Sumarlina Azzah Bte , Lee Sungjoo
Published: February 2012

Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal–oxide–semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel–Poole emission at high electric field. This Frenkel–Poole emission is associated with energy trap levels of ∼0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3×1019 cm-3 and the average activation energy given as ∼0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel–Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley–Read–Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From I
d∝T
-0.37 observed for passivated device, in comparison to I
d∝T
-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.
Characteristics of 4H-SiC n- and p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ion-Implanted Buried Channel
Authors: Okamoto Mitsuo , Iijima Miwako , Nagano Takahiro , Fukuda Kenji , Okumura Hajime
Published: February 2012

We investigated the electrical characteristics of 4H-SiC n- and p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with ion-implanted buried channels. The effects of the impurity concentrations of the buried channel (C
bc) on their electrical characteristics were quite different. In the case of n-channel MOSFETs, the threshold voltage decreased and the channel mobility increased with an increase in C
bc. On the other hand, in the case of p-channel MOSFETs, the threshold voltage and the maximum channel mobility were almost independent of C
bc. The conduction mechanism of the buried-channel MOSFETs is discussed in this paper.
Ge/Ni–InGaAs Solid-State Reaction for Contact Resistance Reduction on n+ In0.53Ga0.47As
Authors: Guo Hua Xin , Kong Eugene Yu Jin , Zhang Xingui , Yeo Yee-Chia
Published: February 2012

We investigate a solid state reaction between Ge and Ni–InGaAs on n+ In0.53Ga0.47As and its effects on the contact resistance of Ni-based contacts on InGaAs. This reaction was performed by isochronous annealing of Ge on Ni–InGaAs at temperatures ranging from 400 to 600 °C in N2 ambient. It was found that a regrown InGaAs layer rich in Ge was formed below the metal contact. Compared with Ni–InGaAs contact, more than 60% reduction in contact resistance on Si-implanted n-In0.53Ga0.47As was achieved after annealing at 600 °C. This contact structure was characterized by secondary ion mass spectroscopy, high resolution transmission electron microscopy, X-ray diffraction, and scanning electron microscopy.
Reduced Threshold Current and Enhanced Extinction Ratio in a Magnetically Controllable Fe50Co50–InGaAlAs/InP Nonreciprocal Semiconductor Laser
Authors: Shimizu Hiromasa , Uehara Keishi , Tazawa Komei , Sakanishi Shohei
Published: February 2012

We report on reduced threshold current and enhanced extinction ratio of a magnetically controllable Fe50Co50–InGaAlAs/InP nonreciprocal semiconductor laser. The improved device performance was consistent with calculated results for the modified layer structure and the use of ferromagnetic metal (Fe50Co50). The fabricated laser showed a threshold current 2.0 times smaller than our previous device having Fe. The extinction ratio, defined as the change in light intensity upon magnetization reversal, increased upon the appearance of the first-order transverse mode and reached 46% at a current of 100 mA. The reduced threshold current and enhanced extinction ratio should be useful for realizing low-operating-current, all-optical, robust signal processing devices using nonreciprocal semiconductor lasers.
Inverted InAlAs/InGaAs Avalanche Photodiode with Low–High–Low Electric Field Profile
Authors: Nada Masahiro , Muramoto Yoshifumi , Yokoyama Haruki , Shigekawa Naoteru , Ishibashi Tadao , Kodama Satoshi
Published: February 2012

We propose a new p-down inverted avalanche photodiode (APD) structure suitable for a scaled APD with smaller junctions. The inverted APD structure has an edge-field buffer layer to prevent undesirable edge breakdown and suppress the excess surface leakage current associated with the InGaAs mesa surface. The fabricated back-illuminated InAlAs/InGaAs APDs show excellent multiplication characteristics without edge breakdown. An f
3dB of 27 GHz and a GB product of 220 GHz are obtained for these APDs.
Responsivity Characteristics of InP/InGaAs Heterojunction Phototransistor with a Strained InAs/InGaAs Multiquantum Well Absorption Layer in the Base or Collector
Authors: Fukano Hideki , Egusa Hiroshi , Taue Shuji , Sato Tomonari , Mitsuhara Manabu
Published: February 2012

The responsivity characteristics of heterojunction phototransistors (HPTs) with a strained InAs/InGaAs multiquantum well (MQW) absorption layer inserted in the base or collector are investigated. It is shown that although the hetero-emitter injects hot electrons into the base, the effective electron diffusion length in the base with MQWs becomes five times lower than that of a base without MQWs. This results in higher current gain for HPTs with MQWs in the collector. In addition, enhanced absorption coefficient due to excitonic absorption is observed only on HPT with MQW in the collector. Due to these two factors, a high responsivity of more than 10 A/W is realized at a wavelength around 2.35 µm for the device with MQWs in the collector.
Optimisation of Coupling between Photonic Crystal and Active Elements in an Epitaxially Regrown GaAs Based Photonic Crystal Surface Emitting Laser
Authors: Williams David M. , Groom Kristian M. , Stevens Ben J. , Childs David T. D. , Taylor Richard J. E. , Khamas Salam , Hogg Richard A. , Ikeda Naoki , Sugimoto Yoshimasa
Published: February 2012

The waveguide design of a GaAs based, epitaxially regrown photonic crystal surface emitting laser is discussed so as to optimise the coupling of the photonic crystal and the mode overlap with the quantum wells. Design criteria include the positioning of the quantum well and the photonic crystal layers, and the effect of varying aluminium composition in the lower cladding layer. Room-temperature, pulsed laser oscillation is demonstrated.
Energy Transfers between Er3+ Ions Located at the Two Crystalographic Sites of Er2O3 Grown on Si(111)
Authors: Omi Hiroo , Tawara Takehiko
Published: February 2012

Films of Er2O3 grown on Si(111) substrates by rf-magnetron sputtering were characterized by synchrotron radiation X-ray diffraction and photoluminescence spectroscopy in spectral and time domains. We measured the photoluminescence and the intensity ratio of the peaks in the photoluminesence as a function of temperature at the excitation wavelength of 800 nm. We determined the energy levels of Er3+ ions in poly crystal Er2O3 and revealed energy transfers from C
2 to C
3i
sites in the Er2O3 on the basis of a simple theory.
Characterization of Wavelength-Tunable Quantum Dot External Cavity Laser for 1.3-µm-Waveband Coherent Light Sources
Authors: Yamamoto Naokatsu , Akahane Kouichi , Kawanishi Tetsuya , Sotobayashi Hideyuki , Yoshioka Yuki , Takai Hiroshi
Published: February 2012

A sandwiched sub-nano separator (SSNS) growth technique of producing high-density, high-quality InAs/InGaAs quantum dot (QD) structures on GaAs substrates is proposed. The SSNS technique achieved a density of 8.2 ×1010/cm2 by suppressing giant dot formation. The QD structures fabricated by the SSNS technique were used to form a ridge-type waveguide QD optical gain chip for O-band optical gain. With this chip, we successfully demonstrated the generation of a wavelength-tunable fine-tooth optical frequency comb in the O-band from a QD optical frequency comb laser (QD-CML), and synchronized short-optical-pulse generation (∼14 ps) with gigahertz-order repetition from a hybrid mode-locked QD-CML. We also successfully demonstrated a wavelength tunable QD-ECL with a wide wavelength tuning range (1265–1320 nm) and a narrow linewidth (210 kHz) in the O-band. It is expected that these QD coherent light sources will become attractive photonic devices for many scientific applications in the 1.0–1.3 µm waveband.
Growth of Nitrogen-Polar 2H-AlN on Step-Height-Controlled 6H-SiC(0001̄) Substrate by Molecular-Beam Epitaxy
Authors: Okumura Hironori , Kimoto Tsunenobu , Suda Jun
Published: February 2012

200-nm-thick N-polar AlN layers were grown on 6H-SiC(0001̄) substrates with 6-bilayer-high steps by molecular-beam epitaxy. During N-polar AlN growth, multinucleation growth occured easily, increasing the surface roughness of AlN. By reducing supersaturation (nucleation probability), the surface roughness was improved. The FWHMs of (0002) and (011̄2̄) ω-scan diffraction peaks of the AlN layer were 120 and 210 arcsec, respectively. The formation of stacking-mismatch boundaries (SMBs) was successfully suppressed by step-height control of the SiC substrate and the initial layer-by-layer growth. Most of the threading dislocations (TDs) were generated at the step edges of the SiC surfaces. The density of TDs in the AlN layers was 2×109 cm-2.
Effects of Initial In Coverage for Preparation of InSb Bilayer on Electrical Properties of InSb Films Grown By Surface Reconstruction Controlled Epitaxy
Authors: Mori Masayuki , Yasui Yuichiro , Nakayama Koji , Nakatani Kimihiko , Maezawa Koichi
Published: February 2012

We investigated the effects of initial In coverage for the preparation of InSb bilayer on electrical properties of InSb films grown by surface reconstruction controlled epitaxy. The electron mobility of the InSb films was affected by the initial In coverage of the In-induced surface reconstruction on Si(111) surface. Electron mobility increased with the increase in the initial In coverage up to 1.5 monolayers (ML), and decreased with further increase in In coverage. The InSb film grown with an optimal initial In coverage of 1.5 ML has a high electron mobility of about 40,000 cm2/(V·s) at room temperature. This may be due to the reduction of the 2×1-Sb surface phase or In islands on the surface after the preparation of the InSb bilayer, which cause dislocations in the film. Therefore, the perfectness of the order of atomic planes in Si–Sb–In is very important for a uniform InSb/Si interface formation before the subsequent InSb molecular beam epitaxy (MBE) growth.
Growth of ZnMgTe/ZnTe Waveguide Structures and Analysis of the Light Polarization with the Electric Field
Authors: Kumagai Yuki , Kobayashi Masakazu
Published: February 2012

The electro-optical (EO) effect of the ZnMgTe/ZnTe waveguide structure grown on (001) ZnTe single crystal substrates using molecular beam epitaxy (MBE) was studied. The EO properties of ZnTe were investigated by optical confinement with an electric field. The effect of the applied electric field and the rotation of polarization wave effect are discussed.
Multi-Electron Wave Packet Dynamics in Applied Electric Field
Authors: Takada Yukihiro , Yoon Young Taek , Shiokawa Taro , Konabe Satoru , Arikawa Mitsuhiro , Muraguchi Masakazu , Endoh Tetsuo , Hatsugai Yasuhiro , Shiraishi Kenji
Published: February 2012

We investigated multi-electron wave packet dynamics considering Coulomb interaction under applied electric field by solving the time-dependent Hartree–Fock equation. We confirm that the Coulomb interaction works to prolong the lifetime of the wave packets. Moreover, we find that the applied electric field also prolongs the wave packet lifetime. This indicates that the particle nature of electrons will be dominant in future nanodevices under high electric field.
Tri-Gate Polycrystalline Silicon Thin-Film Transistors Fabricated by Continuous-Wave Laser Lateral Crystallization with Improved Electron Transport Properties
Authors: Fujii Shuntaro , Kuroki Shin-Ichiro , Kawasaki Yuya , Kotani Koji
Published: February 2012

Tri-gate channel structures were applied to polycrystalline silicon (poly-Si) thin-film transistors (TFTs) fabricated by continuous-wave (CW) laser lateral crystallization (CLC). We had two objectives in using tri-gate structures in CLC poly-Si TFTs. One was the enhancement of effective electron mobility (µeff) by using the tensile strain induced by the CLC process and the lateral-strain-relaxation effect in tri-gate structures. The other was the reduction of µeff variation caused by increasing the number of surfaces with different crystal orientations by up to a factor of three. By applying tri-gate structures to CLC poly-Si TFTs, both 8% µeff enhancement and 41% reduction of µeff variation were achieved at the surface carrier density of 5×1012 cm-2. These results are expected to be useful for the device size shrinkage of high-performance poly-Si TFT circuits.
Steady-State Solution for Dark States Using a Three-Level System in Coupled Quantum Dots
Authors: Tanamoto Tetsufumi , Ono Keiji , Nori Franco
Published: February 2012

Quantum dots (QDs) are one of the promising candidates of interconnection between electromagnetic field and electrons in solid-state devices. Dark states appear as a result of coherence between the electromagnetic fields and the discrete energy levels of the system. Here, we theoretically solve the steady-state solutions of the density matrix equations for a thee-level double QD system and investigate the condition of the appearance of a dark state. We also numerically show the appearance of the dark state by time-dependent current characteristics.
Effects of Interface Grading on Electronic States in Columnar Type-II Quantum Dots
Authors: Kawazu Takuya
Published: February 2012

Columnar type-II GaSb quantum dots (QDs) in GaAs are studied theoretically to clarify how electronic states are affected by the interface grading caused by the interdiffusion of Sb and As. Truncated-cone-shaped QD stacks are analyzed as a function of the diffusion length L
d, where the stacking dot number N is varied from 1 to 4. The energies of heavy- and light-hole ground states E
hh and E
lh, respectively are calculated. The heavy hole is the lowest state when N = 1 and 2, and E
lh is lower than E
hh for N = 4. When N = 3, the lowest state changes from light holes to heavy holes as L
d increases. We also evaluate the overlap Θ between the electron and hole wave functions, which determines the strength of optical transition. It is found that Θ changes by 2–3 orders of magnitude depending on N and L
d.
Efficient Structure for Deep-Ultraviolet Light-Emitting Diodes with High Emission Efficiency: A First-Principles Study of AlN/GaN Superlattice
Authors: Kamiya Katsumasa , Ebihara Yasuhiro , Kasu Makoto , Shiraishi Kenji
Published: February 2012

We investigate an efficient structure for the near-band-edge C-plane emission of a deep-ultraviolet light-emitting diode using first-principles calculations based on density functional theory. We find that a negative crystal-field splitting in the AlN bulk is converted to a positive one in the AlN/GaN superlattice with more than one GaN monolayer. The quantum-confinement Stark effect is minimized by decreasing the GaN thickness down to 1–2 monolayers. The optical matrix element of such superlattices is 57% relative to the GaN bulk, and its C-plane component accounts for the majority of the total; the emission wavelength is found to be 224 nm. The reverse of the negative ΔCR in the AlN/GaN superlattice is ascribed mainly to two factors: quantum confinement effects and the internal parameter u. Our calculations demonstrate that using the AlN/GaN superlattices with one or two GaN monolayers significantly improves the near-band-edge C-plane emission of deep-UV light-emitting diodes.
Electron Emission Properties of GaAsN/GaAs Quantum Well Containing N-Related Localized States: The Influence of Illuminance
Authors: Hsieh Meng-Chien , Wang Jia-Feng , Wang Yu-Shou , Yang Cheng-Hong , Chiang Chen-Hao , Chen Jenn-Fang
Published: February 2012

This study elucidates the electron emission properties of GaAsN/GaAs quantum well containing N-related localized states under illumination. The N-related localized states in a GaAsN quantum well (QW) are identified as both optical and electrical electron trap states. The mechanisms for the responses of current–voltage (I–V) measurement under illumination and photocapacitance are investigated. N-related localized states in GaAsN QW can extend response range and response sensitivity on photocapacitance, and produce an additional current path for photo-generated electron–hole pairs. Furthermore, exactly how illumination influences the electron emission rate of GaAsN QW electron state is examined. The electron emission rate of GaAsN QW electron state can be modulated by different incident photon energy, which is due to the modulation of depletion width of the bottom GaAs.
p-Type Tunneling Transistors with Polycrystalline Silicon by Sequential Lateral Solidification Growth Technique
Authors: Lee Min-Hung , Weng Ssu-Chieh
Published: February 2012

p-Type tunneling transistors with polycrystalline silicon were fabricated, and their electrical characteristics were studied. The temperature dependence of the tunneling current proves that the current of our device is indeed due to the band-to-band tunneling effect, rather than to the avalanche effect. The reliability of the polycrystalline silicon (poly-Si) tunneling transistors with a grain direction effect due to the active layer formed by the sequential lateral solidification (SLS) growth technique was examined. The device with a channel parallel to the grains has a high band-to-band tunneling current, low leakage current, and threshold voltage stability with constant current stress. Promising poly-Si tunneling transistors with a gate-controlled current and a low off-current have attracted attention for some applications such as in display backplanes, three-dimensional integrated circuits (3D-ICs), and microwave circuits in the future.
Deposition of Transparent Indium Molybdenum Oxide Thin Films and the Application for Organic Solar Cells
Authors: Chang Heng-Jui , Chen Wen-Fan , Huang Kuo-Min , Ho Chong-Long , Wu Meng-Chyi
Published: February 2012

In this study, we systematically investigate the effects of post-annealing on the structural, electrical, and optical characteristics of indium molybdenum oxide (IMO) films. The incorporation of IMO films into organic solar cells (OSCs) is further studied. The optimum content of Mo is 2.36 wt %. Furthermore, a significant improvement in crystallinity, surface morphology, electrical resistivity, and optical transmittance is observed after thermal annealing. The lowest resistivity is obtained with post annealing at 300 °C for 140 s. The OSC utilizing the IMO electrode shows an efficiency of up to 3.77%, which is higher than that of the OSC utilizing the ITO electrode. The diffusion length of the carriers in the OSC is approximately 10 nm. Thus, the higher efficiency can be explained by the smoother surface morphology of the post annealed IMO electrode. These results indicate that the novel IMO films with superior material properties have enormous potential applications for solar cells.
Application of Inorganic/Organic Stacked Hole Transporting Layer in Organic Solar Cells
Authors: Su Shui-Hsiang , Lin Wen-Kai , Chiang Wang-Ta , Lin Yan-Fu , Yokoyama Meiso
Published: February 2012

The high fill factor (FF) and high power conversion efficiency (PCE) of organic solar cells (OSCs) were investigated using an inorganic/organic stacked hole-transporting layer (HTL) of vanadium oxide (V2O5)/poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) between indium–tin oxide (ITO) and an active layer. The OSC configuration comprises ITO/V2O5/PEDOT:PSS/poly(3-hexylthiophene):phenyl C61-butyric acid methylester (P3HT:PCBM)/LiF/Al. The FF and PCE are 44 and 2.67% under simulated AM1.5G illumination of 100 mW/cm2, which are approximately double and tenfold, respectively, greater than those of a conventional device without the buffer layer. The V2O5/PEDOT:PSS stacked HTL provides a smooth film surface for coating the P3HT:PCBM active layer, in addition to its stepwise hole-transporting configuration, subsequently increasing charge carrier transporting capability and extracting holes from the active layer.
Effects of Film Thickness on the Photocurrent Generation from Polythiophene–Fullerene Thin Films Containing Silver Nanoparticles
Authors: You Jing , Takahashi Yukina , Yonemura Hiroaki , Akiyama Tsuyoshi , Yamada Sunao
Published: February 2012

We have investigated the incident-photon-to-current conversion efficiency (IPCE) of thin films of poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methylester (PCBM) as a function of film thickness, in the presence or absence of silver nanoparticles (AgPs) between the films and the indium–tin-oxide (ITO) electrode. The thickness of the film was evaluated by atomic force microscopy. The absorption and photocurrent action spectra of the films were measured to investigate the effect of the thickness of the P3HT:PCBM film. The results show that IPCE increased steeply in thinner films and the optimal range of thicknesses of the P3HT:PCBM film was 50–120 nm. In this optimal range, the IPCEs were 1.5–1.8 times larger in the presence of AgPs.