bluuebunny/crossref_metadata_2025 huggingface dataset:
Electrodeposition of Ca₃Zr₂S₇ Films with Structure Type Perovskita in Layers Ruddlesden-Popper
Authors: Solis Cortazar Juan Carlos , Rojas-Blanco Lizeth , Perez-Hernandez Germán , Ponce-Recinos Edith , Silva-Martínez Susana , Zamudio-Torres Ildefonso , Ramirez Morales Erik
Published: February 2020

The Ca₃Zr₂S₇ films were deposited by electrodeposition by means of linear voltammetry with a potential applied in the range of -0.1 to -3.0 V vs. SCE. The precursors used for Ca, Zr and S were calcium acetate, zirconium acetate and sodium sulfite, respectively. The films were characterized optically, morphologically and structurally. The presence of Ca, Zr and S elements was verified by energy dispersion spectroscopy analysis. The results of the X-ray diffraction showed the presence of peaks related to a structure belonging to the perovskite family, and the chemical bonds were confirmed by photoelectron spectroscopy emitted by X-rays. The electrical resistivity in the dark and light was also measured. The surface roughness of the Ca₃Zr₂S₇ film was estimated at 3.05 nm with a thickness of 600 nm. It was found that the material absorbs in the visible region of the electromagnetic spectrum with a wavelength of less than 500 nm. The Ca₃Zr₂S₇ film also exhibits ferroelectric properties at room temperature.
Design and Preliminary Implementation of Onsite Electrochemical Wastewater Treatment and Recycling Toilets for the Developing World
Authors: Cid Clement , Qu Yan , Hoffmann Michael R
Published: February 2020

Self-contained toilet wastewater treatment system prototypes based on electrochemical oxidation of feces and urine using bi-layered semiconductor anodes ([Bi2O3]z[TiO2]1-z/IrxTayO2/Ti) have been designed, constructed, and implemented in regions where access to proper and sufficient sanitation is limited. Prototypes were designed to fit in shipping containers in order to provide toilets and onsite wastewater treatment with clean water recycling. Units were designed to handle the waste of 25 users per day (or 130 L of toilet wastewater). The first prototype was tested on the Caltech campus (Pasadena, California) followed by improved second-generation prototypes that were subsequently installed in India (Ahmedabad, Gujarat and Kottayam, Kerala) and China (Yixing, Jiangsu) for open use in various public settings. The prototypes were able to provide for the disinfection of pathogens (<10 MPN Total coliforms and <1 MPN Fecal coliform indicator organisms per 100 mL), reduction of chemical oxygen demand (<100 mg O2 L-1), ammonia (<10 mg N L-1), and color at an average energy consumption of 35 Wh L-1. The treated wastewater was recycled for use as toilet flushing water.

Figure 1
Sonoelectrochemical Reduction of Tetrabromobisphenol-a at Silver Cathodes in Dimethylformamide
Authors: McKenzie Eric C.R. , Peters Dennis G
Published: February 2020

First reported in the early 1930s, sonoelectrochemistry is an analytical technique that seeks to incorporate ultrasound into electrochemical experiments. Compton and co-workers reviewed the numerous advantages of sonoelectrochemistry over “silent” experiments without ultrasound, including increased mass transport and electrode surface roughening.1 Presently, there is a lack of research employing sonoelectrochemistry to study environmental remediation, a topic of particular interest in our group. As a beginning inquiry into the various factors that optimize sonoelectrochemical reduction, a comparative study into the reduction of the flame retardant 3,3',5,5'-tetrabromobisphenol-A (TBBPA) was undertaken with the aid of cyclic voltammetry, controlled-potential (bulk) electrolysis, and sonoelectrochemistry. Cyclic voltammograms of TBBPA at silver cathodes in dimethylformamide containing 0.10 M tetramethylammonium tetrafluoroborate (TMABF4) show three irreversible cathodic peaks with peak potentials of –0.50 V, –0.70 V, and –1.34 V versus a cadmium-saturated mercury amalgam reference electrode (Cd(Hg)). However, bulk electrolyses of TBBPA at –1.50 V versus Cd(Hg) under the same conditions show minimal debromination as a result of competitive reduction pathways between the carbon–bromine bonds and the phenolic hydrogens within the molecule. To improve debromination, two alternate pathways are explored: the methylation of TBBPA (MeTBBPA) to prevent O–H reduction and the introduction of ultrasound to electrochemical analysis. Cyclic voltammograms of MeTBBPA show two irreversible cathodic peaks (–0.70 V and –0.90 V versus Cd(Hg)) and bulk electrolyses at –1.50 V versus Cd(Hg) show complete debromination in TMABF4–DMF. Similarly, sonoelectrochemical bulk electrolysis experiments at –1.50 V vs. Cd(Hg) show a substantial increase in debromination compared to electrolyses under “silent” conditions.

1 R. G. Compton, J. C. Eklund, F. Marken, Electroanalysis
1997, 9, 509–522.
(Invited) Thermal-Expansion Matched and CMOS Fab-Friendly Engineered Substrates Enabling Unmatched Cost, Performance & Application Scale for GaN Devices
Authors: Odnoblyudov Vladimir
Published: February 2020

GaN is a miracle wide bandgap semiconductor material with unique properties, enabling many critical energy-efficient and novel applications such as LED lighting, next generation of small-size and efficient power devices, high frequency RF electronics, sensors, and more. At the same time, the lack of suitable large diameter and scalable substrates solutions, thereby cost effective and high performance manufacturing platforms, has been slowing down widespread adoption of GaN-based devices for decades, and keeping GaN device manufacturing in small diameter (2-inch, 4-inch, 6-inch) compound semiconductor fabs with limited yield, poor process control and high cost, whereas mainstream semiconductor industry has far moved on to highly automated and cost-efficient 8-inch and 12-inch diameter manufacturing platforms.

In this talk, we will be presenting (1) a revolutionary and validated CMOS fab-friendly 8-inch diameter QST®
(QROMIS Substrate Technology) substrates, which are scalable to 12-inch, for very high quality (bulk-like) and crack-free GaN epitaxial growth, including enablement of large diameter free-standing GaN substrates via growing very thick GaN epitaxy layers (>100 µm), and (2) QST®-based GaN device results enabling an unmatched cost, performance, and application scale. The QST® substrates, with a compliant Si <111> growth surface, have a thermal expansion coefficient matched to GaN epitaxial layers; and this unique feature alleviates the fundamental challenges in (a) economies of scale, (b) performance scale and (c) applications scale which are inherent to GaN-on-Si, GaN-on-SiC, GaN-on-GaN and other proposed solutions.

Various wafer bonding technologies play a key role in large diameter GaN device manufacturing on QST® substrates. Different types of commercial bonding techniques are used in QST® substrate manufacturing, device fabrication and backend processes. In this talk, we will zoom into key wafer bonding techniques and processes which are currently being used (or to be used) in high volume and advanced GaN device manufacturing, such as for LEDs, power and RF devices in lateral, vertical and wafer-level chip scale package forms and architectures.

Figure 1
(Invited) A Moore’s Law for Packaging and the Role of Bonding
Authors: Iyer Subramanian
Published: February 2020

While Silicon has scaled aggressively by over a factor of a few thousand over the last six decades the progress in packaging has been more modest – a linear factor 4-5 in most cases. In this talk, we will examine the reasons for this lag and what we are doing to fix this imbalance. Packaging is undergoing a renaissance where chip-to-chip interconnects can approach the densities of on-chip interconnects. We will discuss the technologies that are making this happen and how these can change our thinking on architecture and future manufacturing. Specifically, we will discuss two embodiments: Silicon as the next generation packaging substrate, and Flexible electronics using fan-out wafer level processing. We will highlight the role of thermal compression bonding and fusion bonding. Finally, we’ll discuss how these developments can help put some intelligence into Artificial Intelligence and bring about changes in Medical Engineering.
Room Temperature Bonding of Wafers Using Si and Ge Films with Extremely Low Electrical Conductivity
Authors: Uomoto Miyuki , Muraoka Arina , Shimatsu Takehito
Published: February 2020

Atomic diffusion bonding of wafers is a promising process to achieve room-temperature wafer bonding: Metal films are fabricated using sputter deposition on two flat wafers’ surfaces, with subsequent bonding of the two films on the wafers in vacuum (Figure (A)) (1, 2). This bonding technique is applicable to any mirror-polished wafer, with bonding using almost any metal film. However, metal films used for bonding are electrically conductive. Therefore, this process is not used directly for wafers with electric devices fabricated on a wafer surface.

One solution for this difficulty is bonding using very thin films of a few angstroms on each side. The electrical conductivity of such thin films is extremely low, especially on oxide wafers because of the thin reactive oxide layer formed between the thin metal films and wafers (2,3). Post-bonded annealing enhanced the oxidation (insulation) of thin films. This process is actually used for electronic device fabrication (4). Another solution is bonding using semi-metals such as Si and Ge because of their markedly low electrical conductivity. The technical potential of the atomic diffusion bonding process using amorphous Si (a–Si) and amorphous Ge (a–Ge) films is presented herein.

Panels (B) and (C) of the figure respectively present cross-section images of bonded a–Si(20 nm)–a–Si(20 nm) films and a-Ge(20 nm)–a-Ge(20 nm) films, as observed using transmission electron microscopy (TEM). Films were deposited on Si wafers. The bonded interface is slightly visible in image (B) for bonded a-Si films, but no vacancy was observed. No interface corresponding to the original films surfaces is apparent in the image (C) for bonded a-Ge films, indicating that the a-Ge film bonding performance is greater than that obtained using a-Si films.

Both images showed that the Si wafer surface was damaged and changed to amorphous because the surface oxide layers of Si wafers were removed by dry-etching using fast atom bombardment (FAB) before film deposition to enhance the adhesion strength of a-Si and a-Ge films on the wafers. However, even if a-Si or a-Ge films were deposited directly on synthetic quartz crystal wafers with no surface treatment, surface free energy at the bonded interface greater than 1 J/m2 was obtained for bonded a-Si films and a-Ge films. No marked difference in the wafer bonding strength was observed between the use of a-Si and a-Ge films.

T. Shimatsu and M. Uomoto, J. Vac. Sci. Technol., B 28, 706 (2010).

T. Shimatsu and M. Uomoto, ECS Trans., 33 (4), 61 (2010).

T. Shimatsu, M. Uomoto, and H. Kon, ECS Trans., 64 (5) 317 (2014).

T. Takai. Y. Takamine, H. Iwamoto, M. Koshino, T. Wada, M. Hiramoto, IMS2016, WE2C-2, San Francisco, May 25 (2016).

Figure 1
Fast Intercalation Reaction of Pseudocapacitive T-Nb2O5 Anode Material at Low Potentials
Authors: Kuai Xiaoxiao , Zhao Jianqing , Gao Lijun
Published: February 2020

Pseudocapacitive materials such as transition metal oxides can exhibit electrochemical capacitive properties through Faradaic redox reactions. These materials feature increased specific capacity in comparison to activated carbon materials which have limited charge storage through double layer capacitance. Pseudocapacitive materials can also maintain high power and long cycle performance, thus making them promising supercapacitor materials. T-Nb2O5 has demonstrated capacitive properties showing square shapes in cyclic voltammetries (CV) at high scan rates [1,2]. The CVs are typically measured in the potential range of 1V - 3V (vs. Li/Li+). In this work, we studied T-Nb2O5 material as anode material in the low potential region, pseudocapacitive behavior was observed with high rate charge and discharge and long cycle life. Below 1V, fast intercalation of Li+ still occurs in the T-Nb2O5 without going through conversion reaction. Fig.1 showS the CV of T-Nb2O5 in Li+ electrolyte in the potential range of 0.1V - 2.5V (vs. Li/Li+), in situ XRD measurements also confirm the unchanged crystal structure of T-Nb2O5 below 1V. This pseudocapacitive property enables wider voltage window for a supercapacitor full cell using T-Nb2O5 anode.

[1] V. Augustyn, J. Come, M.A. Lowe, J.W. Kim, P.-L. Taberna, S.H. Tolbert, H.D. Abruna, P. Simon, B. Dunn, “High-rate electrochemical energy storage through Li+ intercalation pseudocapacitance”. Nature Mater.,
12, 518-522 (2013).

[2] X. Wang, G. Li, Z. Chen, V. Augustyn, X. Ma, G. Wang, B. Dunn, Y. Lu, “High Performance Supercapacitors Based on Nanocomposites of Nb2O5 Nanocrystals and Carbon Nanotubes. Adv. Energy Mater., 1, 1089-1093 (2011).

Figure 1
In-Situ Quantification of Gas Evolution in Pouch Cell Supercapacitors and Its Effect on Device Performance and Operation
Authors: Roberts Alexander John , Bhagat Rohit
Published: February 2020

Valuable insight into the degradation mechanisms, lifetimes and state of health of supercapacitor devices can be obtained through the understanding and quantification of gas evolution during use. In typical commercial cylindrical devices, the hard casing can withstand the pressure build up resulting from the evolution of gases to pressures as high as 8-12 bar, but with detrimental effects on ESR and capacitance observed through the lifetime of device. In typical pouch cells, a small increase in pressure can result in the ballooning of cells and significant loss of performance. This is managed in some cases by the inclusion of pressure release valves and the like.

Although supercapacitors typically produce gas throughout their lifetime, the rate of gas production varies significantly depending on the point in their lifetime and the potentials and charge/discharge rates that they experience. In order to maximise the lifetime and performance of supercapacitor devices, a “burn-in“ period is usually applied, during which time the evolution of gases is likely to be at its highest. After such a burn-in for pouch cells, this gas can be removed with ease before performing a final seal on cells, as is common with battery devices, and can have a significant positive effect on the cell lifetime.

The evolution (and consumption) of gas in supercapacitors can be attributed to various processes including decomposition of carbon-surface functional groups, solvent splitting (hydrogen and oxygen evolution reactions, including decomposition of trace water) and chemical/electrochemical gas consumption[1,2]. In this work, the rate and amount of gas evolved in pouch cell supercapacitors and its effect on device performance has been studied through the use of calibrated mass load cells. Small format pouch cells (70x50mm) constructed in-house, consisting of YP50-F (Kuraray, Japan) activated carbon electrodes and TEABF4 in acetonitrile electrolyte have been suspended from calibrated load cells into oil and have been subjected to various charge–discharge conditions and floating at different potentials over different temperatures. The buoyancy of the cells as derived from the load cell has been used to calculate the gas evolved at various potentials / conditions. Through observation of the rate and quantity of gas evolved, insight into the optimal burn-in conditions (float potential, time and temperature) for new cells and impact on performance in operation have been observed. Furthermore, the effect of contaminant water concentration in electrolyte on gas production has been investigated at various points in the cell lifetime.

[1] S. Phadke, S. Amara and M. Anouti, Chem Phys Chem., 18, 2364, 2017

[2] M. He, K. Fic. E. Frackowiak, P. Novak and E. J. Berg, Energy Environ. Sci., 9, 623, 2016
(Invited) Advanced Hybrid Supercapacitors with “Water-in-Salt” Electrolyte and Protected Lithium Anode
Authors: Zhang Ming , Makino Sho , Mochizuki Dai , Sugimoto Wataru
Published: February 2020

Aqueous supercapacitors are attracting increasing attention owing to their high power density, cyclability and environmental friendliness. However, thermodynamic limit of water electrolysis limits the cell voltage and window of common aqueous supercapacitors, restricting the energy density. We have previously demonstrated that advanced hybrid supercapacitors that employ aqueous electrolyte with a multi-layered water-stable protected negative electrode consisting of laminated metallic lithium or lithiated graphite, polymer electrolyte and water-stable lithium ion conducting solid electrolyte Li1+x+yTi2-xAlxSiyP3-yO12 (LTAP), can extend the negative electrode potential close to 0 V vs Li/Li+, thus providing a cell voltage close to 4 V with aqueous catholytes. In this work this hybrid supercapacitor concept is further extended to high concentration electrolytes or “water-in-salt (WIS)” electrolytes. We will demonstrate that 4 V-class cell voltage with wide voltage window can be delivered for advanced hybrid supercapacitors with capacitive or pesudocapacitive positive electrodes in WIS electrolytes combined with a protected Li anode. A typical advanced hybrid supercapacitor with MnO2 electrode shows a 4.4 V maximum cell voltage with a 1.5 V window, an energy density of 405 Wh/(kg-MnO2) at a power density of 0.88 kW kg/(kg-MnO2). A high energy density of 163 Wh kg/(kg-MnO2) is maintained at a power density of 16.7 kW kg/(kg-MnO2). These advanced hybrid supercapacitors show acceptable cycle stability and good energy retentions (around 90% within 3000 cycles).

Fig. Galvanostatic charge/discharge curves for advanced hybrid supercapacitor with MnO2 in 21m LiTFSI and protected lithium negative electrode at (a) a current density of 0.1 mA/cm2 and U
cell varized from 1.0 to 1.5 V (U
min = 2.9 V and U
max = 3.9→4.4 V) and (b) a fixed U
cell = U
max – U
min = 4.4 – 2.9 V = 1.5 V) and various current densities (Left axis: cell voltage; Right axis: electrode potentials of MnO2 electrode and multi-layered water-stable protected lithium anode). (c) Specific capacity (1) and capacitance (2) extracted from the discharge curves of MnO2 electrode from advanced hybrid supercapacitor with MnO2 in 1 M Li2SO4 at U
cell = U
max – U
min = 4.3 – 3.3 V = 1.0 V. Specific capacity (3) and capacitance (4) extracted from the discharge curves of MnO2 electrode from advanced hybrid supercapacitor with MnO2 in 21 m LiTFSI at the U
cell = U
max – U
min = 4.4 – 2.9 V = 1.5 V.

Figure 1
Synthesis of 3D Porous Nanostructured Platinum Using Atomic Layer Deposition
Authors: Dendooven Jolien , Geerts Lisa , Pulinthanathu Sree Sreeprasanth , Ramachandran Ranjith K. , Bals Sara , Martens Johan , Detavernier Christophe
Published: February 2020

Platinum is known for its catalytic efficiency, exceptional electrical and electrochemical properties, and high resistance to corrosion. Pt nanostructures exposing large surface areas are widely used in catalytic converters, chemical production, and gas sensing and energy conversion technologies. Engineering porosity into Pt nanomaterials is an explored route to maximize the surface over volume ratio and to enhance the performance while reducing the Pt content and cost. It is well established that the properties of 3D-structured Pt nanomaterials are closely related to their geometrical configuration. Synthesis approaches that can produce well-defined porous Pt nanostructures are therefore attractive.

Here, we present the creation of micrometer sized porous Pt nanostructures using atomic layer deposition (ALD) [1]. Robust and easy to handle porous Pt is fabricated by replication of an ordered mesoporous silica with a special pore architecture. After ALD of Pt in the unique 3D channel system of the silica material and digestion of the template, a fully connected ordered porous Pt network is obtained with a 3D structure corresponding to that of the host matrix, as revealed with high-resolution scanning transmission electron microscopy and electron tomography. The Pt nanostructure consists of hexagonal Pt rods (with a diameter of ca. 11 nm) originating from the straight mesopores of the host structure and linking features resulting from Pt replication of interconnecting slits. The Pt replica is evaluated for its potential use as electrocatalyst for the hydrogen evolution reaction (HER), one of the half-reactions of water electrolysis. The high activity displayed by the material is attributed to the 3D ordered, mesoporous structure with large surface area.
(Invited) Etching of Advanced Semiconductor Devices
Authors: Lill Thorsten
Published: February 2020

Plasma etching or Reactive Ion Etching (RIE) is the workhorse for patterning of semiconductor devices since the early 1980-ies when it replaced wet etching in manufacturing. Today, RIE is reaching levels of performance which were unimaginable back then. At the same time, etching technologies such as Atomic Layer Etching (ALE), radical, dry vapor and Ion Beam Etching are finding their way into manufacturing for certain applications.

We will present an overview of dry etching technologies used in semiconductor manufacturing. The emphasis is on the elementary surface processes and how they impact the performance on the wafer. We will start from less complex etching technologies which use just one kind of etching species, such as neutrals, radicals or ions. Then we combine these techniques into cycling processes which leads to the discussion of ALE. The highest level of complexity is reached in RIE with simultaneous species fluxes. Reactor designs for the various etching technologies and process control will be covered. Finally, and an outlook into the future of semiconductor device etching will be given.
(Invited) Using Amorphous Carbon to Enable Area-Selective Atomic Layer Deposition for Advanced Patterning Applications
Authors: Stevens Eric C , Tomczak Yoann , Chan B. T. , Altamirano-Sánchez Efraín , Parsons Gregory N. , Delabie Annelies
Published: February 2020

The demand for transistors and memory devices with smaller feature sizes and increasingly complex architectures furthers the need for advanced thin film patterning techniques. A pre-patterned, sacrificial layer can be used as a template for bottom-up fill of new materials which would otherwise be difficult to pattern using traditional top-down lithographic methods. This work investigates initial growth of TiN, TiO2, and HfO2 thin films during thermal atomic layer deposition (ALD) onto a high density, amorphous carbon (aC) sacrificial layer. ALD of TiN by TiCl4/NH3 at 390oC, TiO2 by Ti(OCH3)4/H2O at 250oC, and HfO2 by HfCl4/H2O at 300oC on as-deposited aC films resulted in uninhibited, continuous thin film growth. We find that carbon surface reduction and passivation using a H2 plasma resulted in delayed film coalescence for TiN, TiO2, and HfO2 on the aC. After 200 TiN cycles on H2 plasma-treated aC, Rutherford backscattering spectrometry shows Ti levels below the detection limit (8×1013 at/cm2), whereas SiO2 or Si3N4 substrates show TiN growth of ~6 nm, corresponding to a selectivity of ~200:1. Exposing plasma-treated aC to H2O induces nucleation for TiN ALD, consistent with favorable nucleation on hydroxyl sites. Therefore, the H2O co-reagent in TiO2 and HfO2 ALD contributes to loss of selectivity compared to TiN ALD using NH3. Furthermore, we demonstrate the use of the Avrami Equation to model the nucleation behavior on plasma-treated aC, providing useful insights into process improvements for increased selectivity. We confirm scaling of selectivity to sub 50 nanometer patterns using 45 nm aC/Si3N4 line/space patterns, where 3.5 nm TiO2 and 5.8 nm TiN films are deposited on Si3N4 with minimal particle formation on aC, with selectivity loss primarily on feature corners and edges. We conclude that improved scaling of selectivity to nanometer scale patterns can be achieved by optimizing surface loading and extent of plasma exposure, and by further understanding shape effects in nanoscale surface plasma modification.
New Process Concepts Towards Area-Selective Atomic Layer Deposition and Atomic Layer Etching of Zinc Oxide
Authors: Mameli Alfredo , Verheijen Marcel A. , Karasulu Bora , Mackus Adriaan J.M. , Kessels W.M.M. , Roozeboom Fred
Published: February 2020

Area-Selective Atomic Layer Deposition, AS-ALD, can be initiated by local area-activation1,2 or -deactivation.3 We studied the maskless growth of ZnO from diethyl zinc and water. The method is based on the different nucleation delays that arise from precursor adsorption on OH-terminated versus that on H-terminated Si-substrate.

TEOS (tetraethyl orthosilicate) and H2O were used to deposit a SiO2 seed layer by EBID (e-beam-induced deposition) in a pattern of 500x500 nm2 dots on H-terminated a-Si:H substrate. After this local activation the substrate was coated with a ZnO film in a conventional ALD reactor using 80 cycles of diethyl zinc and water vapor. In situ spectroscopic ellipsometry (Fig. 1), SEM, cross-sectional TEM and energy dispersive X-ray spectroscopy (EDX) showed good areal selectivity with ZnO growth only occurring on the SiO2 dots. This observation was corroborated by Density functional theory calculations suggesting a kinetically hindered surface reaction between diethyl zinc and H-terminated Si.

Atomic Layer Etching, ALE, was also tested on a ZnO case. Current ALE technology is emerging in both thermal, isotropic and plasma-based, anisotropic approaches.4 In this presentation we will demonstrate a plasma-assisted ALE-process driven by radicals, and therefore being isotropic.

The ALE-process was tested at temperatures between 150 and 250 °C. We used alternating doses of acetylacetone (Hacac) and O2-plasma intermitted by Ar-purging. The ZnO-layer thickness as measured by spectroscopic ellipsometry decreased linearly with the number of cycles. In a synergy test, we proved that only the alternated dosing of Hacac and O2-plasma caused ZnO etching, whereas Hacac and O2-plasma alone did not (Fig. 2). Preliminary infrared studies suggest that Hacac forms volatile complexes by metal oxide surface chelation (e.g. Zn(acac)2), whereas the O2-plasma step removes non-reactive Hacac fragments to refresh the surface for the next etching cycle.5

TEM- and XPS-inspection indicated no damage of the ZnO surface, good preservation of the ZnO-stoichiometry throughout the etching process, and no distinct contamination. Furthermore, we demonstrated this ALE-process to be selective over SiO2. We believe that this novel plasma-assisted ALE-concept can be extended to several other materials.

[1] A. J. M. Mackus et al., Nanoscale, 4, 4477 (2012).

[2] R. Chen et al.,
Adv. Mater., 18, 1086 (2006).

[3] A. Mameli et al., Chem. Mater.
29, 921 (2017).

[4] D. R. Zywotko, et al., Chem. Mater.
29, 1183 (2017).

[5] M. A. George, et al.,
J. Electrochem.
Soc.,
143, 3257 (1996).

Figure 1
(Invited) Strain-Engineered Low-Threshold Group IV Lasers for Photonic-Integrated Circuits
Authors: Jung Yongduck , Luo Manlin , Qi Zhipeng , Sun Hao , Nam Donguk
Published: February 2020

Photonic-integrated circuits (PICs) are a key enabler for the ultimate miniaturization of next-generation optical computers that can fit in the palm of your hand. However, the realization of fully functional PICs is currently limited by the absence of an efficient light source on silicon (Si), thus making a practical Si-compatible light source the Holy Grail. Especially, it has been thus far considered close to impossible to create a practical on-chip laser using Si-compatible group IV semiconductor materials (e.g. germanium (Ge)) owing to their indirect bandgap nature. Strain-engineered Ge material has recently garnered much attention for the dramatic reduction of the lasing threshold of group IV lasers because large tensile strain fundamentally alters the Ge’s bandstructure.

Here, we present our recent research works on highly strained group IV materials on a Si chip for the realization of low-threshold on-chip lasers. In the first part, we will introduce our innovative strain engineering platforms that can create direct bandgap Ge nanowires by inducing >5% elastic tensile strain. In the second part, we will present the first experimental observation of low-threshold optically pumped lasing in highly strained Ge nanowires. The strain engineering of direct bandgap germanium-tin will also be described for the ultimate reduction of the lasing threshold.
(Invited) The Scaling-Down and Performance Optimization of InAs Nanowire Field Effect Transistors
Authors: Chen Qing , Yang Wenyuan
Published: February 2020

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue for short channel nanowire (NW) field-effect transistors (FETs), especially for semiconductors with narrow bandgap such as InAs. To suppress the OFF-state current and find way to improve the properties of short channel NW FETs based on semiconductors with narrow bandgap, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG).

While compared with full-gate (FG) FET fabricated on the same NW, PGFET shows better OFF-state characteristics. Through studying the devices with different length of PG, different measurement conditions and fabrication processes, we find the excess OFF-state leakage current is mainly induced by the BTBT caused by the high-field at the drain-end of the channel, which can be obviously suppressed by the ungated region of PGFET. Through statistic study, we find BTBT effect can be more serious in the devices with better gate-control.
(Invited) Development of Si-Based Sigesn Technique Towards Short-Wave and Mid-Infrared Applications
Authors: Yu Shui-Qing , Du Wei , Ghetmiri Seyed Amir , Mosleh Aboozer , Margetis Joe , Tolle John , Liu Jifeng , Mortazavi Mansour , Sun Greg , Soref Richard , Li Baohua
Published: February 2020

Silicon-based emitters and detectors have long been desired owing to the possibility of monolithic integration of photonics with high-speed Si electronics and the aspiration of broadening the reach of Si technology by expanding its functionalities well beyond electronics. To overcome the intrinsic problem of bandgap indirectness in the group-IV semiconductors of Si, Ge, and SiGe alloys, a new group-IV material platform Silicon-Germanium-tin alloy (SiGeSn) has been investigated, which features: 1) the industry scalable growth; 2) compatible with current Si complementary metal-oxide semiconductor (CMOS) process; 3) capability of monolithic integration on Si; 4) the identified group-IV based direct bandgap materials; and 5) the tunable bandgap allowing the optoelectronic devices operation covers broad wavelength in near- and mid-infrared ranges. For the past decade, plenty of promising results have been reported, such as GeSn lasers based on direct bandgap GeSn alloys, GeSn light emitting diodes (LEDs) and detectors operating in 2~3 µm. With tremendous novel electrical, optical, and mechanical properties, the newly developed GeSn devices could dramatically change the landscape of future microelectronics and photonics.

In this work, the following aspects have been reported: 1) The material growth of SiGeSn by commercially available reduced pressure chemical vapor deposition (CVD) system. The maximum Sn composition of 22% was achieved; 2) The demonstration of GeSn optically pumped laser. The lasing coverage from 2 to 3 μm was achieved at Sn composition ranging from 8.0 to 22%; 3) The investigation of GeSn-based PIN photodiodes, based on which the light emitting diodes (LEDs) and photodetectors were characterized. The specific detectivity (D*) of GeSn detector is only one order of magnitude lower than current market dominating detectors that are made from III-V materials.
Fabrication of Homogeneous Ultra-Thin Sige-on-Insulator Layer for Thermoelectric Applications
Authors: Goyal Chandra Prakash , Omprakash M. , Mutoh K. , Nishino S. , Matsuki T. , Navaneethan M. , Watanabe Takanobu , Shimura Y. , Takeuchi T. , Ponnusamy S. , Hayakawa Y. , Ikeda H.
Published: February 2020

SiGe nanostructures has attracted much attention in recent years in order to realize high-efficient thermoelectric devices due to carrier confinement effect and alloying effect [1,2]. For this purpose, in the present study, we fabricated a compositionally-homogeneous thin SGOI (SiGe on insulator) substrate by simple sputtering and physical evaporation techniques and characterized its crystallographic properties and thermal conductivity. A 30-nm-thick Si layer was sputtered on a thermally-oxidized Si wafer (SiO2 thickness: 103 nm), followed by the deposition of a thin Ge film with a thickness of 30 nm, at room temperature. Afterwards, Si-Ge diffusion was carried out by a rapid thermal annealing process at 880oC for 10 and 120 min. The prepared SGOI substrates were characterized by means of XRD, SEM, EPMA, Raman spectroscopy, XPS, and AFM, which showed the formation of a compositionally-homogeneous poly-crystalline Si1-xGex layer with x=0.45 (thickness: 60 nm). The thermal conductivity was determined by a picosecond time-domain thermoreflectance (TDTR) method at room temperature and shown in the figure, as a function of annealing time. For a reference, the measured values of our as-deposited Ge/Si layer and a commercial single-crystalline SGOI substrate (x=0.5) are also plotted. It is found that our poly-crystalline SGOI layer has lower thermal conductivity of 0.87 W/mK, compared with that of a single-crystalline SGOI 1.43 W/mK.

[1] H. Kim, I. Kim, H.-J. Choi, and W. Kim, Appl. Phys. Lett., 96 (2010) 233106.

[2] R. Basu, S. Bhattacharya, R. Bhatt, M. Roy, S. Ahmad, A. Singh, M. Navaneethan, Y. Hayakawa, D. K. Aswal, and S. K. Gupta, J. Mater. Chem. A, 2 (2014) 6922.

Figure 1
In-Plane Solid-Liquid-Solid Growth and Engineering of Si and Si/Ge Nanowires for Integratable High Performance Fin-like Thin Film Transistors
Authors: Yu Linwei
Published: February 2020

Self-assembly growth of quasi-1D nanowires (NWs) has been a popular, high yield and low cost technology to fabricate ideal semiconducting channels for fin-like field effect transistors or thin film transistors (TFTs). However, a technical challenge to implementing this approach for large scale electronic applications arises from the fundamental difficulty in collecting and positioning these tiny 1D building blocks into precise locations for convenient electric connection and integration. This is particularly true when the SiNWs were grown with gas-feeding vapor-liquid-solid (VLS) approach, where the as-produced SiNWs are typically standing ones on substrate, and thus require further delicate manipulations to arrange them on planar architecture. Fortunately, this challenge can be addressed by adopting a self-assembly in-plane solid-liquid-solid (IPSLS) growth of Si nanowires (SiNWs), where a thin film of amorphous Si (a-Si) is fed as precursor layer to drive the indium (In) or tin (Sn) nano-droplets to move and produce well-defined crystalline SiNWs behind.[1] Remarkably, a precise control of the location, the growth routine and the geometry of the SiNW channels can be accomplished via a simple low temperature (<350 oC) process in conventional plasma enhanced chemical vapor deposition (PECVD) system. We will first demonstrate a reliable batch-manufacturing of parallel SiNW arrays upon glass substrates, which can serve as high mobility channels in fin-like thin film transistors (Fin-TFTs) for large area display application. Specifically, the SiNWs Fin-FETs achieve a high hole mobility of >150 cm2V–1s–1, on/off ratio >106 and excellent subthreshold swing of 120 mV/dec. In addition, the tiny SiNWs, of ~60 nm in diameter and 2 μm apart grown on glass substrate, are transparent to visible light.[2] Furthermore, we will show that the geometry degree of freedom can also be programmed during the in-plane growth of SiNWs.[3,4,5] Finally, an alloy mixture or amorphous bilayer feeding control will be presented, which can help to achieve a self-automated phase-separation and diameter modulation in a unique Si/Ge superlattice nanowire structure. There results could indicate a promising strategy to tailor the Si or SiGe nanowires for high perfomance large area electronics.

References

[1] L. Yu, et al., Phys. Rev. Lett. 102, 125501 (2009).

[2] M. Xu et al., Nanoscale 9, 10350 (2017).

[3] Z. Xue et al., Adv. Func. Mater. 26, 5352 (2016).

[4] Z. Xue et al., Nature commun. 7, 12836 (2016).

[5] Z. Xue et al., Nano Lett. 17, 7638 (2017)
(Invited) Advanced CMOS Scaling: Challenges, Metrology and Characterization Needs
Authors: Liao Szuya Sandy
Published: February 2020

Over the past decade, CMOS device and integrated circuit technology has rapidly evolved toward the use of complex 3D structures that are fabricated using new materials and processes with ever decreasing dimensions. FinFET transistor is now the dominant microprocessor device architecture, and the challenges associated with its 3D nature of all measurements are amplified by shrinking dimensions. This paper reviews the device physics and key front end wafer fabrication challenges of the state-of-the-art FinFET technology. It highlights the area of metrology and characterization that is needed to enable process development, fast ramping in pilot lines and start-ups, reducing time-to-market for new products and yield improvement in mature factories
Ascertaining the Nature and Distribution of Extended Crystalline Defects in Emerging Semiconductor Materials Using Electron Channeling Contrast Imaging
Authors: Schulze Andreas , Han Han , Strakos Libor , Vystavel Tomas , Porret Clement , Loo Roger , Caymax Matty
Published: February 2020

The most recent wave of digital transformation reshapes nearly all aspects of human society and is currently driven by innovations in areas such as AI and machine learning, AR/VR, autonomous driving, cloud and edge computing, 5G etc. All of these applications require emerging technologies across various fields such as high performance computing (e.g. advanced CMOS), storage, high-bandwidth data communication (Photonics, Analog/RF circuits) and sensing (lasers, detectors...). Undoubtedly, the requirements of these diverse technologies cannot be met by a single semiconductor material but instead demand the heterogenous integration of different materials such as (Si)Ge alloys, III-V compounds like (In)GaAs, In(Al)As, (In)GaSb etc. However, the integration of these materials on Si substrates is particularly challenging due to the large lattice mismatch leading to plastic relaxation and hence extended crystalline defects such as dislocations as well as stacking faults and nanotwins. Such extended defects can degrade the material properties, lead to significantly increased leakage or dark currents and moreover cause secondary effects such as dopant and impurity segregation, thereby severely limiting device performance and reliability. Hence, defect metrology enabling a precise and statistically relevant characterization of these heterostructures with low detection limit is crucial. In this presentation we will demonstrate that electron channeling contrast imaging (ECCI) can close this apparent metrology gap by enabling a fast, reliable and non-destructive assessment of the density and nature of extended crystalline defects in confined semiconductor heterostructures using a scanning electron microscope. After discussing the fundamental aspects of the technique, we will present its direct application toward a number of different material systems and structures. In this context we will highlight the technique’s capability to (1) understand strain relaxation and defect formation mechanisms at the nanoscale and, moreover, (2) assist process engineers to unravel the crystalline quality of their materials thereby facilitating process development and device fabrication.
(Invited) Determining Si Composition in SiGe Alloys with < 1% Si concentrations using Raman Spectroscopy
Authors: De Wolf Ingrid , Simons Veerle , Srinivasan Srinivasan Ashwyn , Verheyen Peter , Loo Roger
Published: February 2020

Raman spectroscopy is often used to determine the composition and strain in Si1-xGex films and structures. It is a fast, non-destructive technique that can give results with a spatial resolution at the micron-scale, and even information on nm-sized structures. In principle, the intensity and frequency of the three Raman peaks associated with vibrations of Ge-Ge, Si-Ge and Si-Si bonds offer information on strain and composition. However, this is only straightforward for compositions where all three, or minimal two of these three Raman peaks can be detected, typically between x = 0.2 and 0.8. And even for that case, although there is consensus about the equations to be used, various publications give different values for the constants to be used in these equations. In addition, the Si-Ge Raman peak makes the evaluation difficult, because its position and shape depends on the number and position of the nearest neighbors of a Ge or Si atom in a Si or Ge host lattice, respectively. There is not one, but there are several different kinds of Si-Ge Raman peaks. If less than 1% Si atoms are present in Ge, there is a localized Si phonon mode related to vibrations of an isolated Si atom surrounded entirely by Ge atoms, and a different method has to be used in Raman spectroscopy to obtain information on composition and strain (see figure). This talk discusses these challenges and proposes potential solutions.

Figure 1
HfO2/Al2O3 Nanolaminate on Si0.7Ge0.3(100) Surface by Thermal Atomic Layer Deposition
Authors: Kwak Iljo , Kavrik Mahmut , Thomson Emily , Liang Yu-Chia , Ueda Scott T , Tang Kechao , Hou Vincent , Lee Chung-Yang , Aoki Toshihiro , Kim Moon , Fruhberger Bernd , Taur Yuan , McIntyre Paul C. , Kummel Andrew C
Published: February 2020

Silicon germanium (SiGe) channels for CMOS are favorable due to high intrinsic carrier mobility and band gap tunability[1] To utilize the superior properties of SiGe, low interface defect density (Dit) must be obtained at the SiGe-high k interface. Germanium oxide (GeOx) is the primary source of interface defects[2]. In comparison with GeOx, SiOx has a higher heat of formation. Using this difference, it is possible to reduce interface defects with selective reduction or diffusion of GeOx by employing an oxygen-scavenging metal as a gate material[4,5] such as aluminum. ALD was performed with TDMAH and H2O to grow 50 cycles (5nm) of HfO2 at 250C. 50 nm thick, 150 um diameter Ni or Al gate metal was deposited by thermal evaporation. C-V measurement were employed to characterized the electronic defects. The interface trap density (Dit) integrated across the band gap was more than an order of magnitude lower for Al vs Ni gated MOSCAPs. From TEM-EELS-EDS measurement, Al gated MOSCAPs were observed to have a very thin interfacial oxide layer (<0.5 nm) with high-k oxide atoms almost directly bonded with the SiGe surface atoms with just a thin SiOx interlyer. Selective scavenging of Ge-O vs Si-O bonds is consistent with a DFT model showing HfO2/SiOx/SiGe interfaces can be defect-free. DFT models also show that two 3- and 5-fold coordinated interfacial Si atoms do not create any mid-gap or band-edge states. These results indicate the need to form a SiOx interface between HfO2 and SiGe, but the same interface may be created with other techniques. The alternative techniques include a selective oxidation of SiGe form SIOx using remote O3 oxidation and ALD of an Si rich layer on SiGe. The key issue is which of the three techniques is manufacturable and can produce both a scale oxide and scaled interlayer.

[1] Liu, C. et. al, MRS Bull. 39, 658–662 (2014).

[2] Zhang, L. et al, ACS Appl. Mater. Interfaces 8, 19110–19118 (2016).

[3] Zhang, L. et al, ACS Appl. Mater. Interfaces 7, 20499–20506 (2015).

[4] Kim, H. et al, J. Appl. Phys. 96, 3467–3472 (2004).

[5] Frank, M. et al, ECS Solid State Lett. 2, N8–N10 (2012).

[6] Sardashti, K. et al. Appl. Surf. Sci. 366, 455–463 (2016)
(Invited) Heterogeneous Liquid Metal Particle Composites for Thermal Interface Materials
Authors: Wang Robert Y.
Published: February 2020

Thermal interface materials (TIMs) improve thermal transport away from computer chips by filling micro air gaps between the rough surfaces of adjacent components (e.g., between the computer chip and heat spreader). TIMs typically consist of a polymer or grease with solid particle additives that have high thermal conductivity such as diamond, silver, aluminum nitride, etc. Despite these efforts, TIM conductivities are still usually below 2 W m-1 K-1 because the small point-like contacts between solid filler particles lead to large thermal contact resistances that bottleneck thermal transport.

I present my group’s ongoing work to use heterogeneous liquid metal (LM) particles to overcome thermal transport bottlenecks in polymer composites. The central premise behind this effort is that LM-coated particles will have enlarged particle-particle contact regions relative to the point-like contacts between non-coated particles. In effect, the LM functions as a thermally conductive “solder” between particles.

I first present our work on Cu particles coated in LM (eutectic Ga-In-Sn). Using these particles, we achieve effective thermal conductivities up to ~ 10 W m-1 K-1 under certain circumstances. This Cu-LM system also benefits from a room-temperature reaction between the Cu and LM. Cu-LM mixtures initially start as a slurry and can be processed accordingly. However, this slurry transforms into a conductive solid within a practical time frame (e.g., tens of minutes). During this process, Ga leaches out of the LM and reacts with the Cu to form CuGa2. This also shifts the LM away from its eutectic Ga-In-Sn composition and the LM itself solidifies. In this sense, the LM can be viewed as a solder that is molten at room temperature, but then solidifies via chemical reaction (as opposed to freezing). Another important byproduct of this reaction is that it sequesters the Ga and prevents Ga-induced corrosion of neighboring components.

I next present our ongoing efforts to develop LM-coated Al and LM-coated W particles. These metals have low reduction potentials, which creates opportunities to transform their surface for LM-coatings via galvanic replacement reactions. Additionally, I present our modeling concepts for LM-coated heterogenous nanowires that can enable TIMs that are simultaneously thermally conductive and electrically insulating.
(Invited) Development of Thermoelectric Materials and Thermal Interface Materials By Pulsed Electroplating
Authors: Xu Dongyan
Published: February 2020

In this talk, I will share our recent research effort on development of thermoelectric materials and devices as well as thermal interface materials by using the pulsed electroplating method. We systematically studied the effects of deposition parameters on the composition, microstructure, and thermoelectric properties of the electroplated Bi2Te3 thin films. Our results show that the thermoelectric figure of merit of the electroplated Bi2Te3 films can be enhanced by increasing the pulse off-to-on ratio, which is mainly due to the reduced thermal conductivity and the increased Seebeck coefficient. Based on the fundamental materials research, we further developed cross-plane micro-thermoelectric generators (TEG) based on the electroplated Bi2Te3 and Sb2Te3 micropillars. A power density of 9.2 mW/cm2 is achieved at a temperature difference of 52.5 K for a TEG with 127 thermoelectric pairs. Recently, we are developing thin thermal interface materials by combining pulsed electroplating with microfabrication processes. I will introduce the fabrication process of thermal interface materials and our preliminary results on thermal resistance measurements.