Investigation of Tm2O3 As a Gate Dielectric for Ge MOS Devices
Authors: Žurauskaitė Laura , Jones Leanne , Dhanak Vinod R. , Mitrovic Ivona Z. , Hellström Per-Erik , Östling Mikael 
Published: February 2020

Germanium (Ge) has been intensively investigated as a high-mobility channel material alternative to silicon (Si). A high quality Ge/dielectric interface with interface state density Dit compared to Si is required for competitive device performance. GeO2 has been identified as potential candidate for an interfacial layer (IL) due to effective Ge surface passivation with Dit in the range of 1011 cm-2eV-1 [1]. However, in order to achieve scaled effective oxide thickness (EOT) a combination of GeO2 IL and a high-k dielectric is needed. Low interface state density in the range of 1011 cm-2eV-1 has been achieved while employing Al2O3 barrier [2] as well as rare earth oxides such as Y2O3 [3]. Rare-earth thulium oxide (Tm2O3) provides high dielectric constant k~16 [4] and sufficient valence (3.05 eV) and conduction (2.05 eV) band offsets [5] for a high-k dielectric layer on Ge. In this work Ge/GeOx/Tm2O3 interface quality and the impact of post deposition anneal ambient are investigated.

Metal oxide semiconductor (MOS) capacitors were fabricated to evaluate Ge/GeOx/Tm2O3 gate stacks. After n-Ge substrate clean (acetone, propanol and O2 plasma) and native germanium oxide removal with aqueous HF and HCl solutions the samples were immediately loaded into the rapid thermal anneal (RTA) chamber where oxidation was carried out at 550 °C for 5 s to 5 min. The temperature in the chamber is controlled by a pyrometer which is calibrated to a Si wafer, and oxidation is performed by placing a Ge substrate piece on a Si carrier wafer. The temperature of the Ge sample is thus lower than that of the Si wafer. After oxidation the samples were loaded to atomic layer deposition (ALD) chamber where 40 cycles (~7 nm) of Tm2O3 were deposited using TmCp3 and H2O as precursors. Then Ge/GeO2/Tm2O3 gate stacks were annealed in different ambient (O2, O3, N2 and H2/N2) and temperatures (400 - 550 °C). Reference samples without Tm2O3 deposition or without post deposition anneal (PDA) were also fabricated. Al gate metal was deposited by physical vapor deposition and patterned. MOS capacitors were electrically characterized with capacitance-voltage (CV) measurements. Interface state density in the midgap was evaluated from CV curves using a method described in [6]. X-ray photoelectron spectroscopy (XPS) was performed on some samples using Al Kα X-ray (1486.6 eV) source and PSP Vacuum Technology electron energy analyser.

Electrical properties of thermally grown Ge/GeO2 interfaces were evaluated and low interface state density Dit < 5·1011 cm-2eV-1 in the midgap was extracted from CV measurements. The influence of Tm2O3 deposition on high-quality Ge/GeO2 interfaces was then determined. A degradation of the interface quality after the deposition was observed as displayed in Fig. 1. Dit is higher for thinner underlying GeOx layer and seems to saturate to ~9·1011 cm-2eV-1 for thick layers. A series of post deposition anneals in different ambient and temperatures were performed on Ge/GeOx/Tm2O3 gate stacks in order to investigate the influence on the interface state density and capacitance equivalent thickness (CET). The results are shown in Fig. 2. It can be seen that a temperature of 500 °C or higher and O2 ambient is needed to sufficiently reduce Dit, when values as low as 2·1011 cm-2eV-1 can be reached. XPS measurement was performed on Ge/GeOx/Tm2O3 gate stack with O2 PDA at 500 °C and the obtained spectrum is shown in Fig. 3. The difference between the GeOx 3d5/2 peak and Ge0 3d5/2 peak is 2.7 eV which corresponds to Ge3+ oxidation state. This result is consistent with previously reported XPS results on Ge/GeOx/Al2O3 stacks [7] and suggests that Ge3+ oxidation state provides the low Dit values of Ge/GeOx/Tm2O3 gate stacks.

Tm2O3 integrated with GeO2 and O2 PDA is a viable candidate for Ge MOS devices due to low interface state density of ~2·1011 cm-2eV-1 which is correlated to Ge3+ oxidation state. A further investigation of O2 PDA time in terms of the trade-off between Dit and CET will be reported.

References

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[6] L. Zurauskaite et al., EDTM, pp. 164–166, 2017.

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Figure 1