bluuebunny/crossref_metadata_2025 huggingface dataset:
Effect of Ge Metal–Insulator–Semiconductor Interfacial Layers on Interface Trap Density near the Conduction Band Edge
Authors: Taoka Noriyuki , Mizubayashi Wataru , Morita Yukinori , Migita Shinji , Ota Hiroyuki , Takagi Shinichi
Published: April 2010

The interface structures and electrical interface properties near the conduction band edge (CBE) of Ge metal–insulator–semiconductor (MIS) capacitors with Si or GeO2interfacial layers (ILs) were systematically investigated using physical analysis and the Gray–Brown (GB) method. The accuracy of the values of interface trap density (Dit) obtained by the GB method was confirmed by comparing these with the values obtained by the conductance method. The GB method revealed that Ge MIS capacitors with a Si IL have a large number of interface traps near the CBE, and that the dislocations introduced at a Si IL/Ge interface have an insignificant effect onDitnear CBE. On the other hand, theDitof the GeO2IL capacitors was lower by almost one order of magnitude than that of the Si IL capacitors. In addition, theDitof the GeO2IL/Ge interface was also reduced by high-temperature oxidation during post metallization annealing. These results indicate that ILs have a strong influence onDitnear the CBE, and that the GeO2IL and high-temperature oxidation are quite effective in reducingDitnear the CBE.
Mobility Behavior of Ge1-xSnxLayers Grown on Silicon-on-Insulator Substrates
Authors: Nakatsuka Osamu , Tsutsui Norimasa , Shimura Yosuke , Takeuchi Shotaro , Sakai Akira , Zaima Shigeaki
Published: April 2010

We have investigated the behaviors of the carrier mobility and concentration of the undoped Ge1-xSnxlayers epitaxially grown on silicon-on-insulator (SOI) substrates. Hall measurement revealed the conduction of holes excited from acceptor levels related to vacancy defects whose concentration was as high as 1018cm-3in Ge1-xSnxlayers. The temperature dependences of the carrier mobility and concentration in the valence band was estimated by reducing the parallel conduction component in the impurity band. The incorporation of Sn at a content lower than 4.0% hardly degraded the hole mobility of heteroepitaxial Ge1-xSnxlayers. In contrast, the mobility of the Ge1-xSnxlayers was improved by reducing the carrier concentration of the Ge1-xSnxlayers by Sn incorporation compared with that of the Ge layer formed under the same growth and annealing conditions. This result suggests that the incorporation of Sn into Ge leads to reducing the hole concentration of the electrically active vacancy defects due to the formation of Sn-vacancy pairs.
Crystalline Structures and Electrical Properties of High-Nitrogen-Content Hf–Si–N Films
Authors: Miyamoto Kazuaki , Kondo Hiroki , Zaima Shigeaki
Published: April 2010

The crystalline structures and electrical properties of high-nitrogen (N)-content Hf–Si–N films were investigated. When the N2 concentration of a sputtering ambient increases from 9.0 to 13.0%, Hf–Si–N resistivity increases by a factor of more than 105 despite the almost constant N content of the film. According to X-ray diffraction profiles and X-ray photoelectron spectra, such high-N-content Hf–Si–N films consist of Hf3N4 and Si3N4, and have energy band gaps. These results indicate that Hf3N4 and high-N-content Hf–Si–N including Hf3N4 have semiconducting features. In Pt/Hf–Si–N/Pt structures with high-N-content Hf–Si–N, nonlinear current–voltage characteristics and hysteresis behaviors are also observed, which markedly change depending on N2 concentration and postdeposition annealing temperature. Although the elemental composition and crystalline structure hardly change, the phase separation and segregation of nanocrystallites clearly develop. Therefore, these unique electrical characteristics are attributed to current conduction at grain boundaries or Pt/Hf–Si–N interfaces.
Properties of LaAlO Film after Waterless Process Using Organic Solvent Containing Anhydrous Hydrofluoric Acid
Authors: Honjo Masatomo , Komatsu Naoyoshi , Masuzumi Takuro , Aoki Hidemitsu , Watanabe Daisuke , Kimura Chiharu , Sugino Takashi
Published: April 2010

Lanthanum (La)-based oxide films have been studied as high-k (high dielectric constant) gate dielectrics. However, moisture absorption is a serious problem for oxide films containing La. We have attempted to use waterless solutions instead of water-based solutions to remove high-k films to suppress the moisture absorption of the lanthanum aluminate (LaAlO) film. We report the effect of an anhydrous hydrofluoric acid (AHF) and isopropyl alcohol (IPA) mixed solution as an etching solution and hydrofluoro-ether (HFE) as a rising solution on the properties of LaAlO films. We have succeeded in suppressing the moisture absorption of LaAlO films by using waterless solutions for a front end of line (FEOL) process. In addition, the selectivity (LaAlO/SiO2), the etching ratio of LaAlO to SiO2, was improved using this process. It is considered that this technology will be useful for the next-generation devices with lanthanum-based oxide films.
Formation of Pr Oxide Films by Atomic Layer Deposition Using Pr(EtCp)3 Precursor
Authors: Kondo Hiroki , Matsui Hirotaka , Furuta Kazuya , Sakashita Mitsuo , Zaima Shigeaki
Published: April 2010

The formation of Pr oxide films by an atomic layer deposition (ALD) technique using Pr(EtCp)3 and H2O was investigated in this study. The ALD-mode growth of Pr oxide films at a rate of 0.07 nm/cycle and a thickness variation of less than 2% on 3-in. Si wafers was achieved. Transmission electron microscopy (TEM) images and transmission electron diffraction (TED) patterns revealed that polycrystalline cubic Pr2O3 films were grown on Si(001) substrates. On the other hand, epitaxial growth of the cubic Pr2O3 film was clearly observed on a Si(111) substrate. According to X-ray photoelectron spectroscopy (XPS) analyses, the C content of the ALD-Pr oxide film grown at 130 °C is 1.6%. Relatively fine capacitance–voltage curves were observed for the Al/ALD-Pr oxide/Si(001) capacitors. The interface state density between the 130 °C-grown ALD-Pr oxide film and the Si(001) substrate is about 1×1011 cm-2 eV-1. The dielectric constant of the ALD-Pr oxide film grown at 250 °C was determined to be about 18, assuming that the dielectric constant of the interlayers is similar to that of SiO2.
Thermally Stable NiSi Gate Electrode with TiN Barrier Metal for High-Density NAND Flash Memory Devices
Authors: Whang Sung-Jin , Joo Moon-Sig , Seo Bo-Min , Chang Kyoung-Eun , Kim Won-Kyu , Jung Tae-Woo , Kim Gyu-Hyun , Lim Jung-Yeon , Kim Ka-Young , Hong Kwon , Park Sung-Ki
Published: April 2010

As a gate word line, Ni silicide with a TiN barrier metal has been investigated and demonstrated for NAND flash memory devices with a 24 nm technology node. In addition, physical vapor deposition (PVD) and atomic layer deposition (ALD) TiN layers are compared as diffusion barrier metals. Results show that the carbon impurity in the TiN barrier layer may be one of the factors that affect the quality of the barrier layer at 900 °C. It is also found that Ni diffusion and the discontinuity of Ni silicide induced by the grain growth of polycrystalline silicon (poly-Si) are effectively suppressed by the PVD TiN layer of 20 nm inserted into the control gate. As a result, no significant sheet resistance increase is observed even at a narrow gate line of 24 nm width, and its thermal stability is maintained up to 900 °C.
Comprehensive Modeling of Threshold Voltage Variability Induced by Plasma Damage in Advanced Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Eriguchi Koji , Nakakubo Yoshinori , Matsuda Asahiko , Kamei Masayuki , Takao Yoshinori , Ono Kouichi
Published: April 2010

Threshold voltage shift (ΔVth) and its variation induced by plasma processing were investigated in detail. Two damage mechanisms occurring in an inductively coupled plasma reactor were focused on in this study; the charging damage induced by the conduction current from plasma and the physical damage attributed to the bombardment of high-energy ions. Regarding the charging damage, ΔVthwas found to show a power-law dependence on antenna ratio for both SiO2and high-kgate dielectrics in metal–oxide–semiconductor field-effect transistors (MOSFETs). The observed dependence was also confirmed from the results of a constant-current stress test, indicating that the plasma plays the role of the current source in terms of the charging damage. As for the physical damage, the recess structure in source/drain extension regions was focused on as a possible cause of ΔVth. The depth of the recess (dR) formed by the physical damage was studied using Si wafers exposed to various plasma conditions and subsequently analyzed for surface damage. The recess depth determined from the experiments and classical molecular dynamics simulations exhibits a power-law dependence on potential drop across the sheath between the plasma and the device surface (Vp-Vdc), which is used as a practical measure of the damage. On the basis of the above results, ΔVthdue to the physical damage was calculated by technology computer-aided design (TCAD) device simulation for n- and p-channel MOSFETs with the recess structure. ΔVthshows a linear dependence on recess depth for both n- and p-channel MOSFETs, resulting in the power-law dependence on (Vp-Vdc) viadR. These findings provide a simple relationship among the variations of ΔVth, antenna ratio, and plasma parameters. By taking into account the findings that the MOSFET with high-kdielectrics shows a larger ΔVthdue to the charging than that with SiO2, and that the MOSFETs with a smaller gate length indicate a larger ΔVthdue to the Si recess structure, we can conclude that larger amount of plasma damage induces the larger ΔVthvariations, i.e., theVthvariability induced by the plasma damage is difficult to suppress and will become crucial to the fabrication of future advanced devices. The proposed relationship is useful as a guideline to suppress the ΔVthvariations caused by plasma damage.
In situ Si Wafer Surface Temperature Measurement during Flash Lamp Annealing
Authors: Yamada Yoshiro , Aoyama Takayuki , Chino Hajime , Hiraka Kensuke , Ishii Juntaro , Kadoya Satoru , Kato Shinichi , Kiyama Hiroki , Kondo Hideki , Kuroiwa Tohru , Matsuo Kaoru , Owada Tatsushi , Shimizu Takao , Yokomori Takehiko
Published: April 2010

Automatic emissivity compensating radiation thermometry based on polaradiometry was applied to in situ wafer surface temperature measurement on a flash lamp annealing prototype system. The developed temperature measurement system consists of a dual polarization radiation thermometer and a modulating reference light source, which were mounted on two opposing ports of the process chamber. The intense background radiation from the flash lamp was successfully suppressed by introducing a water flow layer beneath the flash lamp unit and measuring at the water absorption band of 1.95 µm. Millisecond heating and cooling of the wafer was measured for various operating conditions of the flash lamp and for various silicon wafers including wafers with microstructures. The peak temperature was compared with the sheet resistance after treatment and device properties after fabrication. Good correlation was confirmed between sheet resistance and measured peak temperature for various flash lamp intensities irrespective of the surface emissivity or heating conditions. Transistor threshold voltage showed similar correlation, which verifies the applicability of the developed thermometer system to in situ measurement during production.
Room-Temperature Bonding Using Mechanical Caulking Effect of Compliant Bumps for Chip-Stack Interconnection
Authors: Watanabe Naoya , Asano Tanemasa
Published: April 2010

We propose room-temperature three-dimensional (3D) chip-stacking using the mechanical caulking effect of compliant bumps. The compliant bumps were cone-shaped bump made of Au. By caulking Au cone bumps with doughnut-shaped electrodes also made of Au, high-density large-number inter-chip connections were realized even at room temperature in ambient air. The number of inter-chip connections realized was 30,600 with 20 µm pitch. Material analysis revealed that Au cone bumps bonded to Au doughnut-shaped electrodes at the atomic level.
Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects
Authors: Kume Ippei , Inoue Naoya , Saito Shinobu , Furutake Naoya , Kawahara Jun , Hayashi Yoshihiro
Published: April 2010

A highly reliable Cu dual-damascene interconnect (DDI) was developed in a molecular-pore-stack (MPS) SiOCH film (k = 2.5) with precise taper angle control at the top and bottom of via holes. The durable MPS film with the carbon-rich composition revealed no reliability deterioration in the time-dependent dielectric breakdown (TDDB) between the 140-nm pitched lines. The stres-induced voiding (SiV) was suppressed completely by precise taper angle control both at the top and bottom of via holes. A shallow-tapered via and a stepped via, in which these top taper angles (θtop) were greater than 45° while keeping the bottom angle (θbtm) steep at approximately 90°, improved the SiV reliability referred to a deep-tapered via with θbtm≪90°. Finite element method (FEM) simulation well explains the dependence of SiV reliability on both θtop and θbtm; the increment of θtop reduces the stress gradient under the via, while the decrease in θbtm enlarges the stress gradient. Namely, the precise taper angle control of both the top and bottom via is very important to improve the SiV reliability, and the shallow-tapered and the stepped vias in the MPS film were confirmed to achieve high endurance against the SiV due to relaxation of the stress gradient under the via.
Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM
Authors: Demuynck Steven , Huffman Craig , Claes Martine , Suhard Samuel , Versluijs Janko , Volders Henny , Heylen Nancy , Kellens Kristof , Croes Kristof , Struyf Herbert , Vereecke Guy , Verdonck Patrick , Roest David De , Beynet Julien , Sprey Hessel , Beyer Gerald P.
Published: April 2010

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.
Effects of Pore Sealing on Self-Formation of Ti-Rich Barrier Layers in Cu(Ti)/Porous-Low-k Samples
Authors: Kohama Kazuyuki , Ito Kazuhiro , Sonobayashi Yutaka , Tanaka Tomohisa , Mori Kenichi , Maekawa Kazuyoshi , Shirai Yasuharu , Murakami Masanori
Published: April 2010

To investigate effects of pore seals on self-formation of Ti-rich barrier layers, Cu(1 at. % Ti) alloy films were deposited on porous SiO
x
C
y
H (low-k) dielectric layers in samples with and without about 6.5-nm-thick SiCN pore seals. Self-formed Ti-rich barrier layers were formed on the porous low-k layers after annealing in Ar for 2 h at 400–600 °C. The samples without pore sealing had a rough interface, indicating that Ti atoms reacted with the porous low-k layers at the pore surfaces. In contrast, the pore-sealed samples had a smooth interface. The Ti-rich barrier layers in the samples consisted of amorphous Ti oxides. In addition, polycrystalline TiC and amorphous TiN and TiC were observed to be formed beneath the Cu(Ti) alloy films in the annealed samples without pore sealing and pore-sealed samples, respectively. Note that Ti segregation at the interface was divided into two layers, suggesting that the Ti-rich barrier layers self-formed by the reaction of Ti atoms with the pore sealing and porous low-k layers are separated. The resistivity of the pore-sealed samples was lower than that of the samples without pore sealing. This is attributed to lower residual Ti atoms in the alloy films and coarser columnar grains in the pore-sealed samples.
Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor
Authors: Murata Tatsunori , Miyagawa Yoshihiro , Nishida Yukio , Yamamoto Yoshiki , Yamashita Tomohiro , Matsuura Masazumi , Asai Koyu , Miyatake Hiroshi
Published: April 2010

We have investigated the characteristics of silicon oxide films deposited by plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) as offset spacer films of high-k/metal gate stacks. From the results of bonding structure analysis, the silicon oxide film deposited by PEALD has been found to be composed of a Si–O bond network of the stoichiometric silicon oxide film. On the other hand, the silicon oxide film deposited by PECVD is considered to contain suboxide bond structures. From the results of physical and mechanical evaluations, the silicon oxide film deposited by PEALD exhibits a lower wet etch rate, a higher film density, a lower dielectric constant, a smaller amount of water in the film, and a higher elastic modulus than that deposited by PECVD. PEALD showed excellent thickness controllability. From these results, the silicon oxide film deposited by PEALD has higher quality and is more suitable for use as an offset spacer than that deposited by PECVD. X-ray photoelectron spectroscopy showed that the surface oxidation of a titanium nitride film, which is used as a metal gate electrode, during PEALD can be suppressed by using a lower PEALD temperature. Finally, we have demonstrated that the drain current of a high-k/metal gate transistor with a silicon oxide offset spacer deposited by PEALD is markedly increased, compared with that with a high-temperature-deposited silicon oxide offset spacer.
Helium Ion Secondary Electron Mode Microscopy For Interconnect Material Imaging
Authors: Ogawa Shinichi , Thompson William , Stern Lewis , Scipioni Larry , Notte John , Farkas Lou , Barriss Louise
Published: April 2010

The recently developed helium ion microscope (HIM) is now capable of 0.35 nm secondary electron (SE) mode image resolution. When low-k dielectrics or copper interconnects in ultra large scale integrated circuits (ULSI) interconnect structures were imaged in this mode, it was found that unique pattern dimension and fidelity information at sub-nanometer resolution was available for the first time. This paper will discuss the helium ion microscope architecture and the SE imaging techniques that make the HIM observation method of particular value to the low-k dielectric and dual damascene copper interconnect technologies.
Novel Particle-Reduction System in Plasma-Enhanced Chemical Vapor Deposition Process of Interlayer Dielectrics
Authors: Sato Michio , Ohtake Hiroto , Samukawa Seiji
Published: April 2010

The new particle-reduction system for tetraethoxysilane (TEOS) plasma-enhanced chemical vapor deposition (CVD), TEOS plasma-enhanced CVD was developed. It was found that the successive sparks in the plasma-enhanced CVD chamber caused the abnormal discharge (arc). Based on these findings, the new system for avoiding the transfer to the abnormal discharge by cutting the RF power was proposed. In this system, the RF power-cut was triggered by the successive sparks, which were detected by the electromagnetic sensors. When the RF power was cut at the successive sparks within 20 µs, the generation of abnormal discharge was eliminated, resulting in the drastic decrease of number of particles. Consequently, it is considered that this particle reduction system is very effective tools for stable production of TEOS plasma-enhanced CVD SiO2 dielectrics.
Threshold Voltage Dependence of Threshold Voltage Variability in Intrinsic Channel Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with Ultrathin Buried Oxide
Authors: Lee Chiho , Putra Arifin Tamsir , Shimizu Ken , Hiramoto Toshiro
Published: April 2010

Threshold voltage (V
th) variability due to random dopant fluctuations in intrinsic channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) with an ultrathin buried oxide is investigated by three-dimensional device simulation. It is found that, in contrast to bulk and doped channel SOI MOSFETs, V
th variations in intrinsic channel SOI MOSFETs decrease with increasing V
th. A device design guideline for intrinsic channel SOI MOSFETs is also discussed.
Impact of Interface Roughness on Threshold-Voltage Variation in Ultrasmall Gate-All-Around and Double-Gate Field-Effect Transistors
Authors: Mori Nobuya , Minari Hideki
Published: April 2010

Effects of interface roughness on the threshold-voltage variation of nanometer-size gate-all-around (GAA) and double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated using three-dimensional non-equilibrium Green's function formalism. It is found that DG MOSFETs have better robustness to the interface roughness compared to GAA MOSFETs. This is attributed to the fact that the GAA structure has additional quantum conferment along the gate-width direction of the DG structure. From numerical simulations, a simple analytical formula is derived, which describes the threshold-voltage variation in terms of the subband energy change and reduction in the transmission function.
Comparative Study of Multigate and Multifin Metal–Oxide–Semiconductor Field-Effect Transistor
Authors: Cheng Hui-Wen , Li Yiming
Published: April 2010

In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field-effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR ≡ fin height (H
fin)/fin width (W
fin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation results are experimentally validated. The multi-fin FinFET (AR = 2) has better channel controllability than the multifin trigate (AR = 1) and multi-fin quasi-planar (AR = 0.5) FETs. A six-transistor (6T) static random access memory (SRAM) using multi-fin FinFETs also provides the largest static noise margin because it supports the highest transconductance in FinFETs. Although FinFETs have a large effective device width and driving current, their large gate capacitance limits gate delay. The transient characteristics of an inverter with multi-fin transistors are further examined, and compared with those of an inverter with single-fin transistors. The multi-fin inverter has a shorter delay because it is dominated by the driving current of the transistor. With respect to random-dopant-induced fluctuations, the multifin FinFET suppresses not only the surface potential but also its variation because it has a more uniform surface potential than the multifin trigate and quasi-planar FET, and so the effects of random dopants on the circuits are attenuated. The results of this study provide insight into the DC, and circuit characteristics of multifin transistors and associated random dopant fluctuations.
Investigation of Novel Si/SiGe Heterostructures and Gate Induced Source Tunneling for Improvement of p-Channel Tunnel Field-Effect Transistors
Authors: Virani Hasanali G. , Rao Rama Bhadra , Kottantharayil Anil
Published: April 2010

This paper presents optimization techniques for 20 nm channel length novel Si/SiGe heterojunction p–i–n p-channel tunnel field-effect transistors using extensive device simulations. Three different device architectures are compared. It is shown that depending on the Ge mole fraction in SiGe and the gate voltage, the tunneling could be from the channel to source or within the source only. Due to this, a very careful optimization of the Ge mole fraction is required to achieve optimum performance. It is also shown for the first time that a vertical gate induced source tunneling is present in the devices and that this could be utilized for improving ON state current by increasing the gate–source overlap. Of the three device architectures compared, the structure with SiGe channel and Si source/drain is found to give better ON state current. Gate length scalability is found to be superior for the structure with SiGe source, and Si channel/drain.
New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices
Authors: Mizuno Tomohisa , Mizoguchi Naoki , Tanimoto Kotaro , Yamauchi Tomoaki , Hasegawa Mitsuo , Sameshima Toshiyuki , Tezuka Tsutomu
Published: April 2010

We have studied new abrupt-source-relaxed/strained semiconductor-heterojunction structures for quasi-ballistic complementary metal–oxide–semiconductor (CMOS) devices, by locally controlling the strain of a single strained semiconductor. Appling O+ ion implantation recoil energy to the strained semiconductor/buried oxide interface, Raman analysis of the strained layers indicates that we have successfully relaxed both strained-Si-on-insulator (SSOI) substrates for n-MOS and SiGe-on-insulator (SGOI) substrates for p-MOS without polycrystallizing the semiconductor layers, by optimizing O+ ion implantation conditions. As a result, it is considered that the source conduction and valence band offsets ΔE
C and ΔE
V can be realized by the energy difference in the source Si/channel-strained Si and the source-relaxed SiGe/channel-strained SiGe layers, respectively. The device simulator, considering the tunneling effects at the source heterojunction, shows that the transconductance of sub-10 nm source heterojunction MOS transistors (SHOT) continues to increase with increasing ΔE
C. Therefore, SHOT structures with the novel source heterojunction are very promising for future quasi-ballistic CMOS devices.
Investigation of Low-Energy Tilted Ion Implantation for Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistor Extension Doping
Authors: Liu Yongxun , Matsukawa Takashi , Endo Kazuhiko , O'uchi Shinich , Sakamoto Kunihiro , Tsukada Junichi , Ishikawa Yuki , Yamauchi Hiromi , Masahara Meishoku
Published: April 2010

The low-energy tilted ion implantation (I/I) for fin-type double-gate metal–oxide–semiconductor field-effect transistor (FinFET) source–drain (SD) extension doping is systematically investigated experimentally by fabricating a series of n+-polycrystalline silicon (poly-Si) gate n-channel FinFETs under different I/I conditions. The on-state current (I
ON) versus off-state current (I
OFF) and the SD parasitic resistance (R
p) are used for benchmarking the performance of the fabricated devices to investigate the optimal extension I/I conditions, including dose (D) and tilted angle (θ), at a fixed low energy of 5 keV. It is experimentally found that the best extension I/I conditions are D = 4×1014 cm-2 and θ= 60°. With further increasing D, the device performance deteriorates owing to the incomplete recrystallization of amorphous regions in the thin extension regions. In the case of θ= 0°, marked increment and fluctuations in R
p are observed because the implant atoms scatter out randomly from each extension region. The R
p value of the FinFETs fabricated under the above best I/I conditions is comparable to that of devices fabricated by the solid-phase diffusion of phosphors from phosphosilicate glass (PSG). This indicates that the extension I/I conditions of D = 4×1014 cm-2 and θ= 60° are almost optimal and is very effective for high-performance FinFET fabrication.
Impact of Attractive Ion in Undoped Channel on Characteristics of Nanoscale Multigate Field Effect Transistors: A Three-Dimensional Nonequilibrium Green's Function Study
Authors: Kamakura Yoshinari , Mil'nikov Gennady , Mori Nobuya , Taniguchi Kenji
Published: April 2010

A rigorous simulation study of the impact of a single attractive ion in undoped channel multigate field-effect transistors is presented using a new three-dimensional nonequilibrium Green's function technique. A single donor induces threshold voltage shift, and its impact is most significant when the donor is located at the top of the potential barrier. On the other hand, on-current is not affected so much because of the electrostatic screening by the electron bound around the positively charged ion. To reduce the intrinsic device parameter fluctuation, a gate-all-around structure has better robustness than the double gate structure.
Comprehensive Study of Electron Mobility and Band Gap in Tensile-Strained Bulk Ge
Authors: Ono Mizuki , Tezuka Tsutomu
Published: April 2010

In this study, electron mobility and band-gap energy in bulk Ge for arbitrary current directions under both biaxial and uniaxial tensile strains are thoroughly investigated by numerical calculations in order to identify the optimum strain configuration and channel direction. The results revealed a trade-off between a high electron mobility and a wide band gap. The maximum electron mobility of 5,680 cm2 V-1 s-1 was obtained under isotropic biaxial tensile strain in the (111) plane, while the narrowest band gap of 0.436 eV was obtained. In order to study cases with more realistic strain configurations such as process-induced strain, electron mobility and band-gap energy under anisotropic biaxial and uniaxial strains were also studied. It was shown that a combination of the [110] channel direction with uniaxial tensile strain parallel to the channel provides the most technically preferable solution, realizing an electron mobility of 5,626 cm2 V-1 s-1 and a band-gap energy of 0.512 eV.
Study of a Negative Threshold Voltage Shift in Positive Bias Temperature Instability and a Positive Threshold Voltage Shift the Negative Bias Temperature Instability of Yttrium-Doped HfO2 Gate Dielectrics
Authors: Sato Motoyuki , Kamiyama Satoshi , Matsuki Takeo , Ishikawa Dai , Ono Tetsuro , Morooka Tetsu , Yugami Jiro , Ikeda Kazuto , Ohji Yuzuru
Published: April 2010

We have studied unusual V
th shifts in the positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) of yttrium-doped HfO2 gate dielectrics. Both positive and negative stress conditions introduce shifts in opposite directions for yttrium-doped HfO2 in the low stress region. That is, a negative shift under a positive bias and a positive shift under a negative bias were observed. This is due to yttrium-related defects, with electron detrapping for PBTI and electron trapping for NBTI. Such defect formation can be suppressed by incorporating nitrogen into HfO2.
Defect Generation and Severity Comparison of Negative Bias Temperature Stress-Induced Degradation on 90 nm p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Different Oxide Thicknesses
Authors: Chen Shuang-Yuan , Tu Chia-Hao
Published: April 2010

The aim of this study is to investigate negative bias temperature (NBT) stress-induced p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) degradation in 90 nm complementary metal–oxide–semiconductor (CMOS) technology. The study especially focuses on the effects of NBT stress on the pMOSFETs with different oxide thicknesses, such as 16, 31, and 68 Å, and on its degree of severity compared with the degradation induced by drain avalanche hot-carrier (DAHC) stress and channel hot-carrier (CHC) stress at the same biased voltage and temperature. We find that although NBT-induced damage is more serious in devices with a thicker silicon oxynitride (SiON) dielectric, the predicted lifetimes reveal that the pMOSFETs with thinner oxide layers will be more critical in meeting the reliability requirements. Very similar results are also found for the comparison of NBT stress and CHC stress, i.e., although CHC stress is more severe than NBT stress under the test conditions, NBT stress is more critical under operational conditions, while DAHC stress only causes very minor degradation. Additionally, it is always interesting and important to understand degradation mechanisms. Therefore the gated-diode (GD) method is used in this study to determine the cause of NBT stress-induced degradation. Many insights are found by analyzing the results of the GD measurements and are reported in this work.
Seed Layer and Multistack Approaches to Reduce Leakage in SrTiO3-Based Metal–Insulator–Metal Capacitors Using TiN Bottom Electrode
Authors: Menou Nicolas , Popovici Mihaela , Opsomer Karl , Kaczer Ben , Pawlak Malgorzata A. , Adelmann Christoph , Franquet Alexis , Favia Paola , Bender Hugo , Detavernier Christophe , Elshocht Sven Van , Wouters Dirk J. , Biesemans Serge , Kittl Jorge A.
Published: April 2010

Leakage reduction is crucial for metal–insulator–metal (MIM) capacitors for future dynamic random access memory (DRAM) nodes. In previous investigations we showed that increasing the Sr-content would result in leakage reduction of SrTiO3 (STO) films deposited on TiN. [1,2] In this work we demonstrate for thin (10 nm) stoichiometric SrTiO3 films that the leakage properties can be significantly lowered (while keeping high capacitance densities) by using stacking approaches such as seed layer (thin STO layer crystallized before the “bulk” STO deposition) and multistack SrTiO3/GdAlO3/SrTiO3. In this work, SrTiO3 films are deposited using a low temperature ALD process enabling the use of low-cost, manufacturable-friendly TiN-bottom electrode.
Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory
Authors: Mizukami Makoto , Nishihara Kiyohito , Ishida Hirokazu , Aiso Fumiki , Iguchi Tadashi , Ichinose Daigo , Fukumoto Atsushi , Aoki Nobutoshi , Kondo Masaki , Izumida Takashi , Tanimoto Hiroyoshi , Enda Toshiyuki , Watanabe Hiroshi , Toriyama Shuichi , Suzuki Takashi , Mizushima Ichiro , Arai Fumitaka
Published: April 2010

To reduce the short-channel effect for memory cell transistors beyond 2× nm cell size for NAND electrically erasable programmable read only memories (EEPROMs), we propose a depletion-type cell transistor fabricated on a self-manufactured partial silicon-on-insulator (SOI) substrate by conventional LSI process and solid-phase epitaxy. The memory cell transistors with stack-gate show good program/erase properties and have the good S-factor of 309 mV/decade, wide enough threshold voltage (V
th) window of 15 V between program and erase state, and fast enough program and erase time of 100 µs and 100 µs. And we observed no significant V
th-window narrowing and increase in V
th of about 1 V after 1000 cycling test. Operation bias sets of the depletion-type NAND EEPROM are as same as the sets of conventional NAND EEPROM and no peripheral circuit design change is needed. The short-channel effect is reduced substantially to available level for 2× nm size NAND EEPROM.
A 1.2 V Power Supply, 2.43 Times Power Efficient, Adaptive Charge Pump Circuit with Optimized Threshold Voltage at Each Pump Stage for Ferroelectric-NAND Flash Memories
Authors: Noda Shinji , Hatanaka Teruyoshi , Miyaji Kousuke , Yajima Ryoji , Takahashi Mitsue , Sakai Shigeki , Takeuchi Ken
Published: April 2010

A 1.2 V power supply adaptive charge pump for the low voltage and low power ferroelectric (Fe)-NAND flash memory is proposed. The proposed circuit is fabricated with the complementary metal–oxide–semiconductor (CMOS) compatible ferroelectric-gate field-effect transistors (FeFETs) process for Fe-NAND flash memories. By using FeFETs as diodes in the charge pump and optimizing the threshold voltage (V
TH) of FeFETs at each pump stage, the power efficiency of the charge pump circuit to generate the program voltage increases from 21.7 to 52.7% without the circuit area and the process step penalty. The V
TH optimization of FeFETs is realized by repeating the program and the monitor operations during the testing after the fabrication. During the testing, the power efficiency is monitored to detect the optimal V
TH which maximizes the power efficiency at each pump stage. FeFETs in proposed circuits are immune to the disturb and a highly reliable circuit operation is experimentally demonstrated.
A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell
Authors: Tsai Yi-Hung , Yang Hsiao-Lan , Lin Wun-Jie , Lin Chrong Jung , King Ya-Chin
Published: April 2010

This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 Å for 90 nm complementary metal–oxide–semiconductor (CMOS) node and beyond.
Elevated-Confined Phase-Change Random Access Memory Cells
Authors: Koon Lee , Guan Shi , Chong Li
Published: April 2010

A new elevated-confined phase-change random access memory (PCRAM) cell structure to reduce power consumption was proposed. In this proposed structure, the confined phase-change region is sitting on top of a small metal column enclosed by a dielectric at the sides. Hence, more heat can be effectively sustained underneath the phase-change region. As for the conventional structure, the confined phase-change region is sitting directly above a large planar bottom metal electrode, which can easily conduct most of the induced heat away. From simulations, a more uniform temperature profile around the active region and a higher peak temperature at the phase-change layer (PCL) in an elevated-confined structure were observed. Experimental results showed that the elevated-confined PCRAM cell requires a lower programming power and has a better scalability than a conventional confined PCRAM cell.
Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs
Authors: Lai Erh-Kun , Chien Wei-Chih , Chen Yi-Chou , Hong Tian-Jue , Lin Yu-Yu , Chang Kuo-Pin , Yao Yeong-Der , Lin Pang , Horng Sheng-Fu , Gong Jeng , Tsai Shih-Chang , Lee Ching-Hsiung , Hsieh Sheng-Hui , Chen Chun-Fu , Shih Yen-Hao , Hsieh Kuang-Yeu , Liu Rich , Lu Chih-Yuan
Published: April 2010

A complementary metal oxide semiconductor (CMOS)-compatible WO
x
based resistive memory has been developed. The WO
x
memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (∼2 ns) and the programming voltage (<1.4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 108-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO
x
resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications.
Improved Bipolar Resistive Switching of HfOx/TiN Stack with a Reactive Metal Layer and Post Metal Annealing
Authors: Chen Pang-Shiu , Lee Heng-Yuan , Chen Yu-Sheng , Chen Frederick , Tsai Ming-Jinn
Published: April 2010

Improvement of a reactive metal layer (AlCu, Ti, or Ta) for the bipolar resistance switching (BRS) performance of HfO
x
based resistive memory (RM) with TiN as electrodes are studied in this work. After appropriate post metal annealing (PMA), the reactive metal layer with high oxygen content serves as an embedded resistor and modifies the insulator properties of theses stacked layers, which show stable repetitive switching through by the migration of oxygen ions in HfO
x
layer during operation. The Gibbs free energy for the oxidation of the reactive metal with respect to that of HfO2 dominates the optimal PMA temperature for the devices with stable BRS. Except for the reduction of forming voltage and leakage current, the AlCu layer with high resistance after PMA of 500 °C is beneficial for the devices with successive BRS and on/off ratio of 4. The forming voltage of the Ti devices seems insensitive on the PMA. Compared with the Ta device, the Ti/HfO
x
RM device after the PMA of 450 °C for 5 min exhibits a different current–voltage behavior during the first RESET voltage sweep and a higher resistance ratio (>40). These results are attributed to the higher affinity of oxygen in the Ti capping layer. The combination of HfO
x
with a reactive metal and an enough PMA shows great potential for future nonvolatile memory application.
Physical Model for Reset State of Ta2O5/TiO2-Stacked Resistance Random Access Memory
Authors: Sakotsubo Yukihiro , Terai Masayuki , Kotsuji Setsu , Sakamoto Toshitsugu , Hada Mitsuhiro
Published: April 2010

We investigated the conduction mechanism of a Ta2O5/TiO2-stacked resistance random access memory (ReRAM) device and found that its highly resistive state can be attributed to tunnel barriers induced in the filament, since single-electron tunneling phenomena was observed in the current–voltage characteristics at low temperatures and the resistance depended only slightly on temperature. We also found that the largest tunnel barrier, whose resistance is more than 1000 times larger than the second largest one, is located at the interface between the Ta2O5layer and TiO2layer and that variation in the resistance was caused by variation in the tunnel barrier width.
Reference Complementary Metal–Oxide–Semiconductor Circuits and Test Structures for Evaluation of Dynamic Noise in Power Delivery Networks
Authors: Matsuno Tetsuro , Kosaka Daisuke , Nagata Makoto
Published: April 2010

A loop shift register (SR) circuit represents power noise generation of sequential logic operation in a given complementary metal–oxide–semiconductor (CMOS) technology. Reference experiments on noises over power delivery networks have been conducted in 0.18 µm 1.8 V, 90 nm 1.2 V, and 90 nm 1.0 V technologies. It is consistently shown that power and ground noises exhibit universal dependency on circuit activity and follow to equivalent circuit simulation based on capacitance charging modeling of active devices, along with static impedances derived from power delivery networks of a test structure.
White–Red–Green–Blue Lateral Overflow Integration Capacitor Complementary Metal–Oxide–Semiconductor Image Sensor with Color-Independent Exposure and Widely-Spectral High Sensitivity
Authors: Kawada Shun , Sakai Shin , Tashiro Yoshiaki , Sugawa Shigetoshi
Published: April 2010

A high sensitivity white–red–green–blue (WRGB) complementary metal–oxide–semiconductor (CMOS) image sensor is proposed with color-independent saturation exposure based on lateral overflow integration capacitor (LOFIC) architecture. In case of conventional WRGB image sensors, the W pixels saturate in lower illuminance than the other pixels due to the same saturation exposure of all pixels. This WRGB LOFIC CMOS image sensor solves this problem by optimizing the size of LOFICs for each pixel color according to its sensitivity. The white (W) pixels have about 2.3 times higher sensitivity than the green (G) pixels and have 102-dB dynamic range (DR). Moreover, W pixels without infrared (IR) cut filter have high sensitivity for luminance through visible light band to near IR wave band. This image sensor realize that good color reproductivity imaging for the visible waveband and high sensitivity imaging for a wide waveband by one image sensor.
Stable Readout Circuit for Ferroelectric Random Access Memory Using Complementary Metal–Oxide–Semiconductor-Inverter-Based Capacitive-Feedback Charge-Integration Scheme
Authors: Kotani Koji , Koshimoto Yohei , Ito Takashi
Published: April 2010

A capacitive-feedback charge-integration circuit composed of a simple complementary metal–oxide–semiconductor (CMOS) inverter amplifier was applied to a stable readout operation of a low-power low-voltage ferroelectric random access memory (FeRAM). Plate-line driving voltage can be fully applied to a ferroelectric capacitor, and readout signal voltage is independent of bitline capacitance owing to the negative feedback effect. Fluctuations in CMOS inverter amplifier characteristics can be compensated for by an autozeroing mechanism. A CMOS inverter amplifier operating point shift induced by a charge injection mechanism is very effective for increasing signal voltage amplitude. The circuit configuration and operation of the proposed scheme are very simple. A test circuit was fabricated and its operation was confirmed by measurement. The compensation for the threshold voltage fluctuation and the low-power operation of the proposed circuit were also demonstrated by simulation.
A 3.5–4.5 GHz Complementary Metal–Oxide–Semiconductor Ultrawideband Receiver Frontend Low-Noise Amplifier with On-Chip Integrated Antenna for Interchip Communication
Authors: Azhari Afreen , Kimoto Kentaro , Sasaki Nobuo , Kikkawa Takamaro
Published: April 2010

Chip-to-chip ultrawideband (UWB) wireless interconnections are essential for reducing resistance capacitance (RC) delay in wired interconnections and three-dimensional (3D) highly integrated packaging. In this study, we demonstrated a wireless interchip signal transmission between two on-chip meander antennas on printed circuit board (PCB) for 1 to 20 mm transmission distances where the low power gain of each antenna due to a lossy Si substrate has been amplified by a low-noise amplifier (LNA). The measured result shows that the LNA produces 26 dB of improvement in antenna power gain at 4.5 GHz on a lossy Si substrate. Moreover, a Gaussian monocycle pulse with a center frequency of 2.75 GHz was also received by an on-chip antenna and amplified by the LNA. The LNA was integrated with an on-chip antenna on a Si substrate with a resistivity of 10 Ω·cm using 180 nm complementary metal–oxide–semiconductor (CMOS) technology. The investigated system is required for future single chip transceiver front ends, integrated with an on-chip antenna for 3D mounting on a printed circuit (PC) board.
Design of On-Chip High Speed Interconnect on Complementary Metal Oxide Semiconductor 180 nm Technology
Authors: Oshita Takao , Amakawa Shuhei , Ishihara Noboru , Masu Kazuya
Published: April 2010

Equalization is the technology to improve the performance of the on-chip or input/output (I/O) serial link, and the finite/infinite impulse response (FIR/IIR) filter based design is often used as an approximation to the analog filter for equalization, due to the ease of implementation with complementary metal oxide semiconductor (CMOS) technology. However, it has a significant challenge on this application with the analytical approach to the design parameter optimization, due to the severe non-linearity of the circuit. This paper shows how the analytical approach can be achieved to the very simple equalizer application. The analytical model was built and the parameter optimization method was proposed. The model was compared with the actual circuit, and the validity and the limitation of the model were discussed. The test structure was manufactured to prove the method, while the direction was identified on how the model should be improved to extend the analytical approach to this application.