bluuebunny/crossref_metadata_2025 huggingface dataset:
Reliability Assessment of Advanced Flip-Chip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (−190 and −120°C)
Authors: Ramesham Rajeshuni
Published: October 2015

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated, and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep-space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (−55 to 100°C), extreme cold Martian (−120 to 115°C) and asteroid Nereus (−180 to 25°C) environments. The resistance of daisy-chained, flip-chip interconnects was measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (−190 to 85°C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This paper will describe the experimental test results of flip-chip testing under extreme temperatures.
Global-to-Local Modeling and Experiment Investigation of HFCBGA Package Board-Level Solder Joint Reliability
Authors: Chen C.I. , Wu S.C. , Liu D.S. , Ni C.Y. , Yuan T. D.
Published: October 2015

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance flip-chip ball grid array (HFCBGA) package case was studied with the provided experimental data. According to FEM results, the predicted solder ball life is close to that observed experimentally. Therefore, the global-to-local modeling technique can be concluded to provide an efficient methodology for evaluating very high pin count HFCBGA package reliability.
An Improved Closed-Form Solution for Shearing and Peeling Stresses of Trimaterial Assembly in Electronic Packaging
Authors: Sujan D. , Murthy M.V.V. , Hassan A.Y. , Seetharamu K.N.
Published: October 2015

Closed-form solutions for shearing and peeling stresses of trimaterial assembly were initially provided by Schmidt in 1999 [1] and Suhir in 2001 [2]. However, there exist some contradictions and inconsistencies the solutions of both Schmidt and Suhir. The contradiction arises in consideration of the exponent parameter k in the characteristic equation. Both Schmidt and Suhir showed that the exponent parameter k in the shearing stresses contains two roots, but for both cases they considered only one root for k; as a consequence, it leads to a mathematical inconsistency in the solution. In the present paper, a model for shearing stress for uniform temperature change is presented that considers both roots for k. Subsequently, a model for peeling stress is presented that considers moment equilibrium combined with the improved shearing stress model described above. The contradictions in Schmidt's and Suhir's solutions are highlighted in this paper. Analytical and FEM solutions are presented for the same trimaterial package as used by Suhir (cf. Journal of Applied Physics, ibid.) for comparison. The improved analytical results and the numerical simulation indicate better agreement compared with the solutions provided by Schmidt and Suhir.
Photoimageable Thick-Film Components for a Ceramic Analytical Microsystem
Authors: Dziurdzia Barbara , Magonski Zbigniew , Nowak Stanislaw
Published: October 2015

This paper presents ceramic microfluidic components—a meander capillary column and a flame ionization detector—which have been designed and fabricated using photoimageable thick-film dielectric Fodel QM44F combined with low-temperature cofired ceramic tape. The components are integrated on a single piece of alumina substrate of dimensions 65 × 50 mm and have incorporated thick-film platinum heaters to ensure their temperature control. Details of the technological process as well as the application set-up for the tested components are presented. The samples of analyte were detected by a flame ionization detector after passage through a capillary column.
Maximum Attainable Deflections of Shape Memory Alloy-Layered Microcantilever
Authors: Majumder P. , Bhattacharyya A.
Published: October 2015

Finite element modeling of a shape memory alloy (SMA)-layered microcantilever is reported herein. It is assumed that the SMA layer is “two-way–trained,” such that alternate heating and cooling of the SMA layer will cause a phase transformation in the SMA layer and deform the cantilever out-of-plane and back. For a nickel–titanium (NiTi) layer on a glass substrate, computational results indicate that a uniform 4% two-way strain along the length of a SMA layer spanning the full length of a 100-μm cantilever translates to a tip deflection of 29.5 μm, and a sweep of approximately 30° from the flat “rest” state. As well, 40% of the cantilever surface (measured from its free end) is flat and can be used as a flat reflective surface for micromirror applications. A “worse-case” analysis is presented where only 50% of the SMA length is able to undergo phase transformation, resulting in deflections of about 10 μm with a 12° sweep. Finally, it is shown that deflections are about two orders of magnitude higher than what would be possible if the SMA layer did not undergo phase transformations (but underwent pure thermal expansion only). One possible area of application could be in the area of continuously rotating micromirrors, suitable for surveillance systems.
Laser Sintering of Silver Nanomaterial on Polymer Substrates
Authors: Khan Adeyl , Rasmussen Nicholas , Marinov Valery , Swenson Orven F.
Published: October 2015

Direct-write lines deposited on polyimide substrates using silver nanoparticle inks were laser-sintered and compared with similar samples sintered on a hot plate. The lines—30- to 60-μm wide, about 2.4 mm long, and less than a micrometer thick—were laser-sintered by scanning the fundamental wavelength of a continuous-wave Nd:YAG laser along the line. Deposited energy was varied by changing the laser power in addition to the scanning speed, and the resulting bulk resistivity was measured to determine the unsintered, transitional, sintered, and peel-off energy per volume of nanoparticle ink ranges. The bulk resistivity reported was comparable to or better than typical screen-printed conductors, and the elemental composition suggested no thermal damage of the substrate.
Effect of Design Factors on Microvia Reliability of Flip Chip Ball Grid Array Polymeric Substrates
Authors: Leung Dennis , Selvaduray Guna
Published: October 2015

Microvia failures in flip chip ball grid array (FCBGA) polymeric substrates have been a major concern in the development of reliable packages for high-performance and high-density chips. To determine the relationship between reliability and design factors of the microvias, a 10-layer substrate was used to investigate these contrasting design factors: “stack-on-core” vs. “non–stack-on-core,” “high” vs. “low” aspect ratio, “stacked” vs. “staggered,” and “fillet” vs. “non-fillet.” Temperature cycling was used to generate stresses on the microvias. Electrical resistance was measured and analyzed, using design of experiment (DOE), to determine the effects of these design factors on microvia reliability. The significant single factors for a robust microvia were “non–stack-on-core” and “staggered.” Cross-sectioning was employed to understand the failure pattern. Cracks occurred on “stack-on-core” and “stacked” designs only. All the cracks were located at the interface between the capture pad and the bottom of the microvia, where stress is the highest due to the CTE mismatch of different materials.
High Layer Count in LTCC Dual Band Antenna for Galileo GNSS
Authors: Uhlig Peter , Manteuffel Dirk , Malkmus Stefan
Published: October 2015

The adaptation of the LTCC (Low Temperature Cofired Ceramics) process for an unusually high number of layers (up to 50) will be described and explained in this paper. Special attention will be paid to lamination, debindering, and cofiring of the LTCC stack. The influence of necessary process variations on electrical properties such as permittivity will be studied. Very often the number of layers is determined by the complexity of the circuit. Here a minimum substrate height is required for the electrical performance of a patch antenna, particularly in terms of bandwidth. A dual band antenna for two Galileo bands at 1.58 GHz and 1.18 GHz was realized as a combination of two coupled patches. Circular polarization was attained by separately feeding each patch with a hybrid coupler. These features add further layers to an already considerable substrate height.
Power Inductors in Ceramic Multilayer Circuit Boards
Authors: Matz Richard , Götsch Dieter , Goßner Thomas , Karmazin Roman , Männer Ruth , Siessegger Bernhard
Published: October 2015

Power electronic inductors, with values of several μH, have been integrated into thermally stable ceramic multilayer circuit boards by the use of NiZnCu and MnZn ferrite tapes in low temperature cofired ceramic (LTCC) technology. These ferrites are particularly attractive for switched mode power supplies in automation, drives, and consumer applications, where the miniaturization of modules is triggered by advances in transistor technology and switching frequencies. The small signal analysis of embedded individual inductors and coupled transformer coils reveals the generic design rules for these components and additional materials properties beyond those accessible by ring core measurements. In the process of adapting the materials to LTCC, the distinct differences between the two materials become blurred, for example, they can be engineered to exhibit similar cutoff frequencies. NiZnCu ferrite, which is sinterable in air, may even achieve higher permeability than MnZn ferrite. The latter, however, shows higher saturation flux density and current capacity of buried inductors for power line filters. The coupled inductor design in a transformer is particularly ruled by the shunt capacitance inside the coils and by the fact that Maxwell equations preclude strong magnetic coupling between ferrite-embedded conductor lines. While parasitic capacitances remain tolerable for standard dielectric layer material up to several MHz, the need for magnetic coupling requires a fabrication process for magnetic vias.
Morphological and Electrical Properties of Silver Thin Films Sputter Deposited on LTCC Substrates
Authors: Bittner A. , Bohnenberger T. , Engel R. , Seidel H. , Schmid U.
Published: October 2015

Screen printed noble metal thick films are commonly used as metallization on LTCC (low temperature cofired ceramics) substrates. When, however, geometries with a lateral resolution below 20 μm are needed for the realization of devices, alternative techniques are needed, and they are provided by standard thin film technology. To minimize conduction losses, silver (Ag) is favored due to a low bulk resistivity. To evaluate the potential of Ag as metallization, thin films are sputter deposited on glass and LTCC substrates under varying conditions (i.e., plasma power) with different film thicknesses ranging up to 1.75 μm. The microstructure of the Ag films is analyzed applying techniques such as scanning electron microscopy, focused ion beam, and x-ray diffraction. With the latter approach, a mean grain size of about 33 nm is measured independent of plasma power used for Ag deposition. In contrast, the texture strongly varies with deposition parameters resulting in an enhanced generation of (111) planes at higher plasma powers due to an increased adatom mobility. Furthermore, a higher degree in (111) orientation results in a lower resistivity of the Ag films. When the Ag films are postdeposition annealed at 500°C, the resistivity decreases by a factor of 2 compared with the “as deposited” state due to grain growth. Further, sublimation and agglomeration effects dominate leading to an increase in surface roughness and resistivity above average.
Second- and Third-Level BGA Solder Joint Reliability of High-End Flip Chip System in Package (FCSiP)
Authors: Kim Sang Ha , Kakegawa Chika , Tabuchi Hiroshi , Park Han
Published: October 2015

The major concerns posed by system-in-package (SiP) designs for network applications are the interconnection reliability between the memory plastic ball grid array (PBGA) package and the SiP module, which we refer to as 2nd-level interconnection, and between the SiP module and the system board, which we refer to as 3rd-level interconnection, induced by thermomechanical stress to the large SiP module, i.e., 55 × 55 mm2 package body size. In this paper, finite element analysis (FEA) and design of experiment (DOE) case studies were used to evaluate the 2803-pin flip chip SiP (FCSiP) and to determine the best construction of the SiP module and optimize the assembly material set. Heat spreader (lid) thickness, heat spreader material, and under-fill implementation were considered in the stress and fatigue lifetime FEA case studies and long-term solder joint reliability, which was accelerated thermal cycle (ATC) tested at operating temperatures from 0 to 100°C. Another important factor in the system-level reliability is an external heat sink, and its compressive force effect was also investigated in the ATC test. In addition, short-term mechanical reliability tests, such as the 4-point monotonic bend test based on the IPC-9702 specification and mechanical shock test based on the JESD22-B110A standard, were also evaluated for the 2803-pin FCSiP qualification. Finally, the results of these experiments were compared with the FEA data in a correlation process.
Validation of Alternative RoHS Compliant Au Pastes for the DuPont LTCC 951 System
Authors: Mussler Bernhard , Schwanke Dieter
Published: October 2015

The restriction of the use of certain hazardous substances (RoHS) came into force on July 1, 2006. Equipment producers will need to obtain materials declarations or certificates of compliance from their suppliers. Certain exemptions from this regulation, for example, RF ports and certain medical applications, still allow for the manufacture of LTCC products with non-RoHS-compliant materials. However, there is a continuously growing demand for LTCC products without cadmium or lead. Since the end of 2006 DuPont has been offering Cd-free Au pastes as possible replacements for established products. For cofiring internal and external conductors, Au paste type 5734 is frequently used by LTCC manufacturers. The alternative RoHS compliant paste is type CDF34. For pin, tab, and frame brazing, a combination of Au pastes 5062D (adhesion layer) and 5063D (barrier layer) are currently the first choice for according LTCC parts at MSE. The Cd-free versions are types 5062E and 5063E. MSE is validating all three new pastes according to a comprehensive test plan that includes five different test layouts for CDF34 and another two for 5062E and 5063E. Simultaneously, corresponding reference parts are built to have exact comparison possibilities. The validation of CDF34 includes the investigation of bondability and the reliability of resistor terminations, vias, and adhesive bonded components. Furthermore, the lateral migration (insulation resistance) is tested. The 5062E and 5063E validation includes the reliability of soldered components, vias in soldered pads, and soldering of frames and base plates. The different test cells include visual inspection, cross sections, initial measurements, and results after thermal cycling, thermal shock, temperature, and humidity exposure.
Miniaturized Embossed Low Resistance Fine Line Coils in LTCC
Authors: Perrone R. , de Torres H. Bartsch , Hoffmann M. , Mach M. , Müller J.
Published: October 2015

Embedded ceramic coils stand out because of their excellent dielectric, thermal, and RF properties. However the relatively high sheet resistance (low thickness) of printed thick-film conductors restricts their functionality for applications where current values of several amps are needed. Using embossed structures it is possible to manufacture conductors with increased thickness and low resistance on LTCC tapes. The manufacturing process for wide conductors with high dimensional accuracy was shown in previous publications. In this work fine line embossed structures with line widths and spaces of 50 and 75 μm respectively were realized. The cross section of the embossed channels was about 50 μm. The fine line screen printing, stencil printing, and the photo definable Fodel® processes were used to fill the small structures with thick-film ink. The whole process was used to manufacture several types of low resistance coils in LTCC that can be used for current values up to approximately 3 A. They were realized as embedded as well as SMD components. Thus, the functionality of LTCC modules and LTCC SMD coils was increased. In this paper, the filling and patterning characteristics of all structuring methods are compared and the results discussed. Furthermore, the advantages of this process are shown by electrical, thermal, and RF measurements.
Two-Dimensional Mapping of the Mechanical Properties of Pb-Free Solders for Reliability Optimization
Authors: Marques V. , Johnston C. , Grant P.S.
Published: October 2015

The development of thermomechanical models of Pb-free solders is more complex than for Pb-Sn solders as a result of their higher reactivity and processing temperature that leads to the continuous evolution of stiff and angular intermetallics in the microstructure. In this paper, nanoindentation has been explored for its potential to characterize mechanically the complex microstructure of Pb-free solder joints. Hardness and Young's modulus of the various microphases in a Sn-Ag-Cu/Cu solder joint were characterized at 25°C and averages were obtained from nanoindentation maps composed of 100–200 indentations. The possibility to map mechanical property gradients across the various solder joint interfaces and to differentiate between different presentations of the same phase, including in situ at elevated temperatures, has been suggested to be useful in extending the available data for constitutive models used in reliability simulations of Pb-free solders.
Mechanically Amplified Piezoelectric Microactuators for Laminar-Turbulent Transition Control on Airfoils
Authors: Bolzmacher C. , Riedl X. , Leuckert J. , Engert M. , Bauer K. , Nitsche W.
Published: October 2015

Drag reduction on airfoils using arrays of micro-actuators is one application of so-called Aero-MEMS. These microactuators interact with TS instabilities (Tollmien-Schlichting waves) inside a transitional boundary layer by superimposing artificially generated counterwaves in order to delay the transition process. These actuators need to exhibit a relatively large stroke at relatively high operational frequencies when operated at high Mach numbers. For this purpose, a novel micromachined mechanical amplification unit for increasing the stroke of piezoelectric microactuators up to high frequencies is proposed. The mechanical lever is provided by a sliced nickel titanium membrane. In this work, the actuator is explained in detail and wind tunnel experiments are carried out to investigate the effect of this mechanically amplified piezoelectric microactuator on thin transitional boundary layers. The experiments have been carried out in the transonic wind tunnel facility of the Berlin University of Technology on an unswept test wing with an NACA 0004 leading edge. The effectiveness of the actuator for flow control applications is determined in an open-loop setup consisting of one actuator having a relevant spanwise extension and a microstructured hot film sensor array located downstream. The aerodynamic results at Mach 0.33 are presented and discussed. It is shown that the actuator influences TS wave specific frequencies between 2.5 kHz and 7.4 kHz. The actuator amplitude is large enough to influence a transitional boundary layer significantly without bypassing the natural transition process which makes this type of micromachined actuator a candidate for high speed TS-control.
Helmholtz Resonance Based Micro Electrostatic Actuators for Compressible Gas Control: A Microjet Generator and a Gas Micro Pump
Authors: Kim Hanseup , Najafi Khalil , Bernal Luis P.
Published: October 2015

This paper reports Helmholtz-resonance based micro electrostatic actuators to control compressible gaseous fluids in the micro scale. Particularly, it discusses design, fabrication, and testing results of two electrostatic actuators: a micro jet generator and an integrated peristaltic multistage micro pump. These electrostatic actuators vibrate a micro membrane in a micro chamber at a high frequency (>10 kHz), and easily induce the resonant behavior of compressible gases in the chamber. Such resonant behavior, often called the Helmholtz resonance, can repeatedly create instantaneous pressure in equilibrium between the inside and outside of the chamber and cause gas to rapidly exit the chamber, forming a collimated jet. The developed micro jet generator consists of multiple acoustic chambers in parallel; produces directional gas momentum from each chamber by utilizing the Helmholtz resonance; and collectively entrains nearby gas molecules to form a gas stream. The fabricated micro jet generator has a footprint of 1.6 × 1.6 cm2 and contains 25 acoustic micro thrusters. It operates using a 140 V and 70 kHz sinusoidal signal and produces a thrust of 55.6 μN, a maximum air velocity of 1.2 m/s, and consumes power of 3.11 mW. The developed micro pump consists of multiple acoustic chambers in series and produces a high total pressure by accumulating pressures across the multiple chambers, while maintaining high flow rates utilizing the fluidic resonance of each pumping chamber. The fabricated 18-stage pump produces the maximum air flow rate of 4.0 sccm and maximum pressure differentials of 17.5 kPa with total power consumptions of only 57 mW. Its total package volume is 25.1 × 19.1 × 1 mm3. It is notable that these electrostatic actuators, with their actuation membranes, acoustic chambers, fluidic channels, and micro valves, are fabricated into a single silicon chip by developing low temperature wafer bonding techniques to protect the polymer structures inside.
Pb-Free Synthesis: Decision Matrix as a Tool for Alloy Selection
Authors: Quintero Pedro O. , Valentín Ricky , Ma David
Published: October 2015

For aerospace products, there is no current legislation or directive that sets a schedule for transitioning to Pb-free electronics; however, the aerospace industry is likely to be swept along because of its dependence on the larger commercial electronics industry which has already changed its materials, components, and assemblies to Pb-free. In this article, we present a synthesis of Pb-free solders along with critical factors affecting selection and deployment. A decision matrix methodology is introduced as a valuable tool to assist the alloy selection process based on specific criteria and life cycle conditions.
Development and Characterization of Tapered Silicon Etch Process by Topography Modeling for TSV Application
Authors: Ranganathan N. , Malar A. , Lee D.Y. , Prasad K. , Pey K.L.
Published: October 2015

A dual-etch via tapering technology has been presented which combines Bosch process and isotropic etch process. It has been shown that the dual-etch process technology provides a high degree of process flexibility to the user by independently controlling and optimizing the etch rate and profile tapering process. Based on experimental work, RIE process models have been set up using ELITE simulation software from Silvaco. Detailed DOE has been done to optimize the RIE models so that the experimental and simulation results match over a wide range of via geometries and aspect ratios. The optimized models have been further used to predict the aspect ratio induced RIE lag effects.
Inkjet Printing of Fine-Line Thick-Film Inductors
Authors: Wassmer Marcel , Diel Waldemar , Krueger Klaus
Published: October 2015

Inkjet printing is the emerging technology for the deposition of a variety of particles. The reliable printing of nano-silver inks shows the possibilities of digital fabrication of microelectronic circuits and raises the question for further use with other particles. To compete with common thick-film screen printing as a production method it is consequential and necessary to investigate the inkjet printing of all passive electronic thick-film components. Inductors are frequently required in electronic circuits, yet they represent a main challenge for thick-film printing. With the development of new materials, which are suitable for low-temperature cofired ceramic processes, the integration of passive components promises new applications.

In a first step, different ferrite particle compositions are dispersed to stabilized inks that can be used with a commercial inkjet print head. The stability of the ink is fundamental for reliable drop formation. In addition, the viscosity must fit to the print heads' operational ranges and the magnetic properties must be taken into account. In a second step, the effect of substrate coating and drop volume variation toward the shape of the printed structures are defined and shown. The fundamental construction methods of inkjet-printed inductors on fired ceramic are investigated. First, silver coils are printed without ferrite to optimize the printing pattern. Subsequently, coils are embedded in inkjet printed ferrite layers.

Depending on the geometrical layout, several drying and firing steps are necessary, leading to a more complex production process and influencing the electrical properties. Finally, it is shown that inkjet printing is very effective for built-up of multilayer thick-film inductors, and the high accuracy of the printing process promises accurate electrical values.
Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill
Authors: Li Zhaozhi , Lee Sangil , Lewis Brian J. , Houston Paul N. , Baldwin Daniel F. , Stout Eugene A. , Tessier Theodore G. , Evans John L.
Published: October 2015

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity.

No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process.

This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.
Advanced SiP Packaging Technologies of IPD for Mobile Applications
Authors: Prashant Meenakshi , Yoon Seung Wook , Kim GeunSik , Liu Kai , Carson Flynn
Published: October 2015

Integrated passive device (IPD) technology was originally developed as a way to replace bulky discrete passive components, but it is now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon submounts, and digital and mixed-signal devices. IPD is a device realized by resistors, inductors, capacitors, filters, and so on, for electrical functions such as matching and transforming, among others. Passive devices essentially optimize overall device performance. The key benefits offered by IPDs, as compared with LTCC and laminate-embedded passive devices, are primarily a smaller form factor and higher performance. IPDs are finding applications wherever it is desirable to reduce space on the application board or to reduce cost at the system level.
Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive
Authors: Huffman Alan , Gregory Christopher , Lueck Matthew , Reed Jason , Temple Dorota , Stapleton Russ
Published: October 2015

We present the results of a study to evaluate the use of a fluxing adhesive developed by LORD Corp. in the bonding of Cu/Sn-Cu bump structures for interconnection in 3D integration structures. Using an area-array daisy chain test vehicle with a bump pitch of 25 μm, samples are prepared using our standard bonding methodology and also with the fluxing adhesive and then evaluated through electrical measurements and cross section SEM analysis. The results show that the use of the fluxing underfill material results in a well-formed bond between the Cu and Cu/Sn bumps and encapsulates the interconnects to provide environmental protection and additional mechanical strength to the interconnect array.
Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs
Authors: Tezcan Deniz S. , Majeed Bivragh , Civale Yann , Soussan Philippe , Beyne Eric
Published: October 2015

Imec is developing two TSV flavors for Si thicknesses of 50 and 100 μm for various wafer level packaging (WLP) applications where thin dice are stacked and electrically connected to each other through post CMOS processed TSVs and microbumps. As a differentiator, these TSV technologies use spin-on dielectric polymers as the insulating liner. A three-mask process sequence is implemented for fabrication of both TSV types; however, the TSV shape, the process flow, and the Si thickness are different for each one of them. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for post CMOS compatibility. For both TSV types, electrically yielding TSV connected daisy chains are measured on the fabricated wafers and the reliability of the TSVs while undergoing thermal cycle tests is analyzed.
Design of a High Temperature EMI Input Filter for a 2 kW HVDC-Fed Inverter
Authors: Robutel Rémi , Martin Christian , Morel Hervé , Buttay Cyril , Gazel Nicolas , Bergogne Dominique
Published: October 2015

In this article, a high temperature EMI input filter for a SiC JFET inverter is designed and tested in operating conditions at 200°C. Inverter EMI issues, design procedure, and characterizations of selected components are presented in detail. The feasibility based on industrially available materials and components is demonstrated with a low temperature dependence of the EMI spectrum.
An Investigation of the Process Stability of RF SiP Made of DuPont 943 and 9K7
Authors: Bartnitzek Thomas , Purtova Tatyana , Rusch Christian , Kaminski Slawomir , Feger Till
Published: October 2015

RF packaging is one of the most challenging but also the fastest growing topic in low temperature cofired ceramic (LTCC) technology. Today LTCC is particularly useful for advanced packages and systems-in-package because of its electrical, functional, and thermomechanical properties as well as its excellent long-term stability and reliability. LTCC combines the potential for miniaturization and low loss handling of high frequencies up to 110 GHz and it also offers the opportunity to integrate additional features. Therefore it has to go through various manufacturing steps and several refirings without any performance degradation or loss of dimensional accuracy.

This article discusses the impact of thermal postprocessing on RF characteristics and geometric properties of LTCC. Ceramic substrates with radar front ends, calibration structures, and other test vehicles made of DuPont Green Tape® 943 and 9K7 were cofired following the recommended conditions and refired several times in order to investigate and compare the influence of the postfiring. The flatness, dimensions, and RF performance of the ceramics up to 110 GHz were evaluated and compared.
A Novel Design of Substrate Integrated Waveguide (SIW) E-Plane Inductive Strip Filter Implemented Using LTCC
Authors: Abousaif Ehab , Elshabini Aicha , Barlow Fred
Published: October 2015

Low-temperature cofired ceramic (LTCC) was used for a novel band-pass filter design. The filter is based on metallic strips parallel to the E-plane and mounted in a substrate-integrated waveguide (SIW). A new iterative technique based on the variation principle was used to obtain the inductive reactance of equivalent T-network of the metallic strip. The design method of the filter was derived by applying the equivalent network of the metallic strip to the usual method of the filter design. A set of curves relating the various filter parameters is introduced. This filter was designed such that it is electromagnetically isolated inside the SIW and excited using grounded coplanar waveguide (GCPW) to SIW transitions; therefore, it can be easily integrated with MMICs. The design steps are explained and verified by examples and results. Three-dimensional electromagnetic field modeling and simulation was carried out using a high frequency structure simulator (HFSS). A comparison between different types of SIW is presented showing the resulting S-parameter curves for each case. By following the design steps, similar filters for various frequency bands using any dielectric material can be easily designed.
Design and Characterization of a Biocompatible Packaging Concept for Implantable Electronic Devices
Authors: de Beeck Maaike Op , Qian Karen , Fiorini Paolo , Malachowski Karl , Van Hoof Chris
Published: October 2015

A biocompatible packaging process for implantable electronic systems is described, combining biocompatibility and hermeticity with extreme miniaturization. In Phase 1 of the total packaging sequence, all chips are encapsulated in order to realize a bidirectional diffusion barrier, preventing body fluids from leaching into the package, which would cause corrosion, and preventing IC materials such as Cu from diffusing into the body, which would cause various adverse effects. For cost-effectiveness, this hermetic chip sealing is performed as a postprocessing step at the wafer level using modifications of standard clean room (CR) fabrication techniques. Well-known conductive and insulating CR materials are investigated with respect to their biocompatibility, diffusion barrier properties, and sensitivity to corrosion.

In Phase 2 of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme using, for example, gold or platinum. For electrodes in direct contact with the tissue after implantation, IrOx metallization is proposed.

Phase 3 of device assembly is the final packaging step, during which all system components, such as electronics, passives, a battery, among others, will be interconnected. To provide sufficient mechanical support, all these components are embedded using a biocompatible elastomer such as PDMS.
Use of Wafer Applied Underfill for 3D Stacking
Authors: La Manna Antonio , Rebibis K. J. , Gerets C. , Beyne E.
Published: October 2015

A key element for improving 3D IC stacking and packaging reliability is the choice of the right underfill (UF) material. The underfill is a specialized adhesive whose main purpose is locking together the top and bottom dice; it must fill the gap between bumps and between dice, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (i.e., capillary dispensing), or before flip chip operation with no need of reflow (no flow underfill, NUF). In case of 3D stacking, such processes present some limitations: the need for a dispensing area (die size increase); material flow (spacing between dice), and cost (low throughput). After an introduction on typical underfill applications such as die-to-package and die-to-die assembly, we report the work done to assess the properties of several wafer applied underfill (WAUF) materials and their integration in 3D stacking. These materials were initially applied on silicon wafers in order to assess the minimum achievable thickness and material uniformity. The wafers were coated with different methods: spin coating and film lamination. After this initial assessment, the most promising materials were used for 3D stacking. The test vehicle used has Cu/Sn microbumps with a pitch of 40 μm. The quality of the materials is judged by electrical test, SAM (surface acoustic microscope), and X-SEM (scanning electron microscope).
Studying the Impact of Return Current Path on the EM Simulation of High-Speed Package and Board Designs
Authors: Kostka Darryl , Scogna Antonio Ciccomancini
Published: October 2015

Three-dimensional electromagnetic simulation models are often simplified in order to reduce simulation time and memory requirements without sacrificing the accuracy of the results. A commonly adopted methodology in the simulation of complex electronic package and board designs is to truncate the size of the model, leaving only a few important features surrounding the nets of interest. In this paper we demonstrate that this simplification can have a significant impact on the simulation results if it is not performed carefully, and it can introduce spurious nonphysical resonances. The interaction between cavities and signals is first studied using a simple coupled differential via test structure. It is demonstrated that the return currents generated by these vias excite cavity resonances in power-ground plane pairs causing them to behave as parallel-plate waveguides. The role of interplane shorting vias in suppressing cavity resonances is then investigated and the impact of boundary conditions on the simulation results of package models is also shown and discussed.

The focus is then shifted to PCB/package cosimulation and the impact of different truncation schemes is discussed through the simulation of test structures of varying complexity. A simulation methodology is then proposed and is verified for a combined model of a realistic complex multilayer package and board and it is demonstrated that accurate results can be obtained through proper truncation of the geometry.
Reliability of Embedded Ultrathin Chips Subjected to Cyclic Stresses
Authors: Sarwar Ferdous , Marinov Val R.
Published: October 2015

Recently, ultra-thin embedded die technology has garnered much attention for its ability to produce assemblies in two or three dimensions with reduced footprint, low profile, low weight, and conformity. The embedded die technology can be successfully utilized in the development of flexible printed circuits to satisfy the demand for reliable and high density packaging solutions. With tremendous application potential in wearable and disposable electronics, the reliability of the flexible embedded die package is of paramount importance. Presented are results from the experimental study on the electrical performance of ultrathin (≤50 μm) silicon dice embedded into a polymer substrate and bumped using three different techniques—electroplating, wire bonding, and sputtering. The reliability of different packages was evaluated through a series of thermal and mechanical cyclic stress tests. The results suggested that the reliability of all embedded dice was high regardless of the bumping technology. However, compared with the other two methods, wire bonded stud bumps provided better and more consistent performance.
Die-Attach Technologies for Ultraviolet LED Multichip Module Based on Ceramic Substrate
Authors: Burkhardt T. , Hornaff M. , Acker A. , Peschel T. , Beckert E. , Suphan K.-H. , Mensel K. , Jirak S. , Eberhardt R. , Tünnermann A.
Published: October 2015

A high power UV light emitting diode (LED) multichip module package based on aluminum nitride (AlN) and alumina (Al2O3) is presented. The AlN substrate with a high thermal conductivity of up to 180 W/(m·K) and LED chips based on a copper alloy provide superb thermal management and heat extraction. Efficient cooling is an important prerequisite for the increase of extractable optical power and for the reduction of thermally induced wavelength shift. A design of a stackable module featuring arrays of 7×2 indium-gallium-aluminum-nitride UV LED chips at 395 nm is developed. This configuration of submodules allows for the scalable assembly of line sources with different lengths. Applications using UV LEDs cover market segments such as curing of adhesives, inks, and coatings, sterilization of medical equipment, and treatment of potable water, as well as various uses in chemical detection, biochemical analytics, and spectroscopy.

Thermal and thermomechanical modeling of the submount is conducted using finite element analysis. Die attach using eutectic gold-tin solder, lower melting tin-lead solder, and silver-filled adhesive are compared with respect to optical output power and wavelength drift. Mechanical strength and structure of the resulting joints are investigated using shear force measurements, cross-sectioning, and microtomography. An optical output power of 7.7 W is achieved using a cluster of 14 LED chips at 1050 mA, resulting in a peak irradiance of 33.9 W/cm2 at the LED surface with respect to the footprint and pitch of the attached chips.
Inkjet Printing of Multilayer Capacitors
Authors: Jeschke D. , Ahlfs E. , Krüger K.
Published: October 2015

Capacitors are widely used passive components. Taking account of micro hybrid circuits, printed capacitors are desirable. However, today's screen printing technology results in very low specific capacitance per area, thus SMD components are usually preferred. In order to achieve a higher specific capacitance, simple plate capacitors are stacked to form multilayer components. Maskless inkjet printing allows for realization of such structures. To keep the process simple, in-between sintering is avoided; the entire component is cofired in one final step.

To define the geometry of the components, the general processability of the used material combination is first examined. Among other things, the extent to which the structures can be decreased in size without affecting their functionality is determined. In further experiments, the effects of thermal expansion and sinter shrinkage are analyzed.

To create multilayer capacitors, a second step takes place in which the design is completed. Vias are embedded to bypass the dielectric layer or the opposing electrode. When increasing the height of the structure, the aspect ratio that can be achieved by the printing process is considered.
Design and Fabrication of an LTCC Structure for a Microceramic Combustor
Authors: Belavic Darko , Hrovat Marko , Dolanc Gregor , Makarovic Kostja , Zarnik Marina Santo
Published: October 2015

Advanced microsystems or macrosystems are in some cases made with multilayer ceramic technology. Low-temperature cofired ceramic (LTCC) technology is considered to be one of the more suitable technologies for the fabrication of ceramic microsystems that integrate screen-printed, thick-film electronic components as well as three-dimensional buried structures, for example, cavities and channels. One of the applications is a ceramic combustor. The chemical energy of the fuel is converted into thermal energy in a chemical microcombustor through a burning process, while the accompanying high temperatures and, frequently, high pressures, impose harsh conditions on the combustor structure. Therefore, the combustor must be carefully designed not only from the functional, thermal, and chemical points of view, but also with respect to the mechanical strength.

The combustor device was prepared by lamination of Du Pont 951PX LTCC green tapes. The fabricated 3D LTCC structures with buried cavities and channels including two inlets (for fuel and air), the evaporator for the fuel, the mixing system of the channels (for mixing the evaporated fuel and air), the distribution channels and eight microburners were realized. The main parts are eight microburners realized as buried cavities. In the burners, a platinum-based catalyst was deposited to assist the oxidation, that is, the burning, of the methanol with the air. Thick-film, platinum-based heaters and temperature sensors are incorporated within the structure. The device was tested with different flow rates of liquid methanol (1 mL/h to 5 mL/h) and air (7 L/h to 15 L/h). The temperatures obtained were between 250°C and 450°C.
All-Dielectric Metamaterials for New Areas of Application
Authors: Semouchkina Elena , Semouchkin George , Lanagan Michael
Published: October 2015

The properties and novel applications of ceramic all-dielectric metamaterials are described. In particular, meta-materials composed of arrays of identical ceramic resonators are shown to provide for negative refraction and backward wave propagation. It is also demonstrated that arrays of ceramic elements can be used as nonresonant metamaterials to form gradient index media. Employment of such media in antenna substrates is shown to provide antenna miniaturization without deteriorating antenna performance. The development of a microwave transmission cloak composed of identical low-loss ceramic resonators to conceal an object with dimensions far exceeding the wavelength of incident radiation is also presented.
Utilizing Modeling in a Reliability Study of ACA Joints in Humidity Tests
Authors: Saarinen Kirsi , Frisk Laura
Published: October 2015

Radio frequency identification tags (RFID) with anisotropic conductive adhesive (ACA) joints are used in various applications where the environmental conditions may impair their reliability. Thus the effects of different environmental stresses on reliability need to be investigated. The purpose of this work was to study whether a relatively simple shear stress model can be utilized in reliability prediction of anisotropically conductive paste (ACP) joints in an accelerated humidity test on the basis of the information obtained from another humidity test. If modeling gives accurate results when studying reliability, the need for actual testing would decrease and thereby time and cost savings could be achieved. In this study, finite element models were made to calculate shear stresses in ACP joints induced by two different humidity tests. Additionally, experimental tests were performed and the results were compared with those of modeling. The test samples were RFID tags whose microchips were attached with ACP. A constant humidity test was used to study the effects of high humidity level and a humidity cycling test was used to examine the effects of constantly varying humidity. In the modeling it was observed that the selection of the stress-free temperature has a significant effect on the results. With three different stress-free temperatures, three different sets of results were obtained. Although the tags saturated in the extreme conditions of the humidity cycling test, according to modeling, the change in relative humidity level in the humidity cycling test did not increase the harshness of the test. However, the temperature change in the humidity cycling test increased the harshness.