bluuebunny/crossref_metadata_2025 huggingface dataset:
Combined Electron Beam Induced Current Imaging (EBIC) and Focused Ion Beam (FIB) Techniques for Thin Film Solar Cell Characterization
Authors: Altmann Frank , Schischka Jan , Ngo Vinh Van , Stone Stacey , Kwakman Laurens F. Tz. , Lehmann Ralf
Published: December 2020

A novel analytical method applying combined electron beam induced current (EBIC) imaging based on scanning electron microscopy (SEM) and focused ion beam (FIB) cross sectioning in a SEM/FIB dualbeam system is presented. The method is demonstrated in several case studies for process characterization and failure analysis of thin film technology based Solar cells, including Silicon (CSG), Cadmium Telluride (CdTe) and Copper Indium Selenide (CIS) absorbers. While existing techniques such as electro-, photoluminescence spectroscopy and lock-in thermography are able to locate the larger, electrically active defects reasonably fast on a large area, the FIB-SEM EBIC system is uniquely capable of detecting sub-micron, sub-surface defects and of analysing these defects in the same system. In combination with a FIB, the localized region of interest can be easily cross sectioned and additional EBIC analysis can be applied for a three dimensional analysis of the p/n junction.
A Novel Technique for Localization of Low Level Leakage in Integrated Circuits
Authors: Chiang A. , Wu H. , Nguyen H. , Pratchayakun W. , Le P.
Published: December 2020

Electrical leakage can be either the cause or the effect of circuit failures. Existing detection tools that rely on heat (liquid crystal and fluorescent microthermal imaging) or near-infra-red radiation (thermal imager and emission microscope) associated with the leakage can be fairly effective provided that the ‘hot spot’ is not blocked by metal and, more importantly, the level of leakage is high enough to generate the heat or radiation above certain detection threshold. Using a unique property created by the knock-in implantation of oxygen, we introduce a novel technique that can be used to identify localized leakage at previously unattainable low levels.
Infrared and Visible—Near Infrared Electroluminescence Developments for FA in AlGaN/GaN HEMTS on SiC
Authors: Bouya M. , Carisetti D. , Clement J.C. , Malbert N. , Labat N. , Perdu P.
Published: December 2020

HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. They are crucial components for the development of base stations in the telecommunications networks and for civil, defense and space radar applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by standard (Visible-NIR) and Infrared (range of wavelength: 3-5 µm) electroluminescence techniques. Its complementarities and efficiency have been demonstrated through two case studies.
Scan Chain Debug Using Dynamic Lock-In Thermography
Authors: Forli L. , Picart B. , Reverdy A. , Schlangen R.
Published: December 2020

In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.
Effective Fault Isolation Using Memory BIST and Logic BIST Diagnostic Techniques
Authors: Kinger Rakesh , Tong Chuck , Chaudhry Ayyaz , Chowdhury Vijay , Sun Wenzhen , Deng Hongqi , Smith Steve
Published: December 2020

As device technologies are shrinking, developing new techniques for fault isolation and defect localization is becoming a crucial challenge. In this paper, we have shown that by using memory and logic BIST diagnostic techniques, we are able to isolate the defect to two suspected nets. Thirdparty electronic design automation (EDA) tools were used for both MBIST and LBIST hardware implementation and for running diagnostics on the failing part. Using experienced and sophisticated failure analysis support, we were able to confirm with confidence that the stuck-at zero type of defect was caused by a signal line short at metal-5 to the ground line at metal-6.
Non-Visible Defect Analysis of OTP Device
Authors: Chen C.Q. , Ang G.B. , Xing Z.X. , Hua Y.N. , Mo Z.Q. , Ramesh Rao , Li Y.
Published: December 2020

Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.
A Study of a Characteristics Variability Evaluation in an Actual LSI Circuit with Nanoprobing Technique
Authors: Fukui Munetoshi , Nara Yasuhiko , Tsunomura Takaaki , Nishida Akio , Fuse Junichi
Published: December 2020

In this paper, we propose an evaluation method of characteristics variability of MOS transistors in an actual circuit with the nanoprobing technique. Based on the result of correlation with data of a parametric tester, we verified that the nanoprobing had ability for variability evaluations and its precision of is 7 mV in threshold voltage and 0.5 mA in saturation current respectively. As the result of the trial evaluation of variability of SRAM cells in an actual LSI die, we confirmed that variations of threshold voltage and saturation current are normal distributions.
Impacts of Sample Preparation Methodology on TEM Failure Analysis of Advanced Semiconductor Devices
Authors: Zhou Yongkai , Zhu Jie , Teo Han Wei , Quah ACT , Zhu Lei , Du Anyan , Hua Younan
Published: December 2020

In this paper, two failure analysis case studies are presented to demonstrate the importance of sample preparation procedures to successful failure analyses. Case study 1 establishes that Palladium (Pd) cannot be used as pre-FIB coating for SiO2 thickness measurement due to the spontaneously Pd silicide formation at the SiO2/Si interface. Platinum (Pt) is thus recommended, in spite of the Pt/SiO2 interface roughness, as the pre-FIB coating in this application. In the second case study, the dual-directional TEM inspection method is applied to characterize the profile of the “invisible” tungsten residue defect. The tungsten residue appears invisible in the planeview specimen due to the low mass-thickness contrast. It is then revealed in the cross-sectional TEM inspection.
High-Frequency TSV Failure Detection Method with Z Parameter
Authors: Kim Joohee , Jung Daniel H. , Cho Jonghyun , Pak Jun So , Kim Joungho , Yook Jong Min , Kim Jun Chul
Published: December 2020

As the TSV count increases, chip yield can be severely degraded due to failures during the TSV or die-stacking processes. This paper will present and discuss on the usage of failure masks designed to detect and differentiate failure types such as connection failure and insulator failure based on frequency-domain one point probing measurement. The failure masks are proposed on the basis of the frequency domain analysis of TSV failures with Z11 magnitudes.
Enhanced Failure Analysis on Open TSV Interconnects
Authors: Altmann F. , Schmidt C. , Beyersdorfer J. , Simon-Najasek M. , Große C. , Schrank F. , Kraft J.
Published: December 2020

In this paper different methods and novel tools for failure localisation and high resolution material analysis for open TSV interconnects will be discussed. The paper shows the application of enhanced methods for the localisation of sidewall shorts in open TSV structures by adapted Photoemission Microscopy (PEM), Lock-in Thermography (LIT) and Electron Beam Absorbed Imaging (EBAC). In addition, a new highly efficient target preparation technique is presented, which allows the combination of Laser and FIB milling, in order to access TSV sidewall defects. Finally the use of this technique is demonstrated in a failure analysis case study.
Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device
Authors: Sienkiewicz Magdalena , Rousseille Philippe
Published: December 2020

This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.
STEM EDX Mappings and Tomography for Process Characterization and Physical Failure Analysis of Advanced Devices
Authors: Lepinay Kevin , Lorut Frederic , Pantel Roland , Epicier Thierry
Published: December 2020

In the context of the increasing complexity of materials used in semiconductor device processes, the STEM EDX technique is now used routinely. It can be used to discriminate stacked layers in advanced devices where STEM HAADF Z-contrast is not sufficient. Moreover, it allows a new use of planar preparation for layer investigation. The complexity of analyzed structures drives a need for 3D information which can also be obtained with the chemical information of the EDX analysis.
SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis
Authors: Paul Erik , Herzog Holger , Jansen Sören , Hobert Christian , Langer Eckhard
Published: December 2020

This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.
Failure Analysis on Lifted Ball Bond and Micro Lateral Crack Using Fractography Approach
Authors: Khong Yong Foo , Marks Michael Raj
Published: December 2020

This paper demonstrates the application of fractography on ductile fracture in gold wire bonding and brittle fracture in micro lateral crack of silicon chip. Different separation mode of a lifted wire ball was mapped through the study of various sizes of dimples, ductile zone and non-welded area. Multiple Focus Ion Beam (FIB) cuts were required at lateral crack area in order to expose the horizontal fracture features to determine the crack propagation direction.
A Comprehensive Approach to Lifted Bond Balls Package Failure
Authors: Nguyen Dat , Karki Sagar
Published: December 2020

Lifted bond balls in Integrated Circuit (IC) have numerous failure mechanisms. A simple external curve can confirm the open, and with package decapsulation, lifted balls can be readily observed. However, the exact cause can be difficult to identify. Most often, a cross section through the balls was performed, but it is far from being able to reveal the reason for lifted bond balls. A comprehensive FA approach is needed. Performing failure analysis through the back side of the die using Scanning Acoustic Microscopy (C-SAM) and Infra Red (IR) inspection helps to observe the conditions of the bond pads. Pulling the die from the mold compound can provide a pristine view of the bond ball-bond pad interface. This allows the detection of contaminants, both organic and inorganic, which cross sections cannot provide.
Advanced FIB Application—Automated, Precision Deprocessing for Failure Analysis
Authors: Wang Dandan , Feng Hua , Tan Pik Kee , Low Guorong , Chong Khiam Oh , Lam Jeffrey , Mai Zhihong
Published: December 2020

Focused Ion Beam is widely used in semiconductor industry for critical applications such as TEM sample preparation and circuit edit. In this paper, we introduce an automated failure analysis technique for high precision polishing at the wafer level. Using FIB, it is possible to precisely mill at a region of interest, capture images at the region of interest simultaneously and cut into the die directly to expose the exact failure without damaging other sections of the specimen.
Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains
Authors: Gaudestad J. , Orozco A. , De Wolf I. , Wang T. , Webers T. , Kelley R. , Morrison T. , Madala S.
Published: December 2020

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).
Root Cause Analysis Techniques Using Picosecond Time Resolved LADA
Authors: Bodoh Dan , Erington Kent , Dickson Kris , Lange George , Wu Carey , Crawford Tom
Published: December 2020

Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.
Analysis of Two Electrical Failures Caused by Die Attach of Exposed Pad Package
Authors: Li Jinglong , Masuda Motohiko , Che Yi , Wu Miao
Published: December 2020

Die attach is well known in die bonding process. Its electrical character is simple. But some failures caused by die attach are not so simple. And it is not proper to analyze by a generic analysis flow. The analysis of two failures caused by die attach are presented in this paper.
New Ion Source for High Precision FIB Nanomachining and Circuit Edit
Authors: Steele Adam V. , Knuffman Brenton , McClelland Jabez J.
Published: December 2020

We present a review of the Low Temperature Ion Source (LoTIS): its aims, design, performance data collected to date, and focused spot size projections when integrated with a FIB. LoTIS provides a Cs+ beam that has been measured to have high brightness (> 107Am-2sr-1eV-1), and low-energy spread (< 0.5 eV). These source characteristics enable a prediction of subnm focused spot sizes. A FIB with the capabilities enabled by LoTIS would be well-suited to addressing FIB failure analysis tasks such as nanomachining, circuit edit, and site-specific SIMS.
Imaging Performance of aSIL Microscopy on Subsurface Imaging of SOI Chips
Authors: Uyar Aydan , Yurt Abdulkadir , Cilingiroglu T. Berkin , Goldberg Bennett B. , Ünlü M. Selim
Published: December 2020

The demand for high resolution has raised interest for the use of aplanatic solid immersion lenses (aSIL) for backside optical inspection and failure analysis of integrated circuits due to its high numerical aperture capability. This work investigates the performance of aSIL microscopy in imaging of fully depleted silicon on insulator (SOI) chips and explores the effect of the buried oxide (BOx) thickness on the spatial resolution and photon collection efficiency. Three different cases, namely, bulk silicon, SOI with an ultrathin BOx of 10 nm, and SOI with a standard BOx thickness of 145 nm, are studied. It is observed that there is a 15% drop in the collection efficiency for ultra-thin BOx compared to bulk silicon and up to 80% decrease in the collection efficiency and 30% increase in the spot-size for standard Box.
To Eliminate Curtain Effect of FIB TEM Samples by a Combination of Sample Dicing and Backside Milling
Authors: Luo Jian-Shing , Lee Hsiu Ting
Published: December 2020

Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.
Will Tomorrow’s Failure Analysis Lab Operate More Like Today’s Fab?
Authors: Templeton Todd , Brogden Valerie
Published: December 2020

Efficiencies in operation are achieved largely in advanced failure analysis (FA) labs because routine steps or processes have been automated and the need for operator interaction minimized. Very few operators are required to run a fully automated, "lights out" type Fab. This paper discusses the various automation components which are available to labs as they look to streamline the FA process to support the Fab's ever increasing demand for more process data. These include iFast Automation software and automated recipes to create the thick lamella. The development of automation software and integrated accessories for FA equipment is now bringing more Fab-like activities and processes into the FA lab. As more and more automation moves into the FA lab, one should not be surprised in a few years to see very few operators sitting in front of tools with blinking green lights scattered throughout the lab.
Vacuum Assisted Ex Situ Lift Out for Manipulation of FIB Prepared Specimens
Authors: Giannuzzi Lucille A. , Hess Dustin , Clark Trevor
Published: December 2020

Ex situ lift out (EXLO) is performed outside of the FIB instrument on a system basically consisting of a light optical microscope, stage, and manipulator. EXLO may be used to lift out very large specimens prepared using plasma FIB instruments. This paper combines a vacuum micropipetting module with an EXLO station, making use of both suction vacuum forces and adhesion forces for the pick and place of a FIB milled free specimen onto a slotted EXpressLO grid. The geometry for manipulation to EXpressLO grids is detailed in this paper. It is observed that the vacuum assisted lift out optimizes specimen positioning for easy placement on the novel EXpressLO grid. Once on the new grid, an electron transparent specimen may be analyzed directly by S/TEM or other analytical techniques. The specimen on this grid can also be further FIB milled or processed prior to analysis.
Turning Sample Into (Re)Solution—Focused Ion Beam Shaped Solid Immersion Lenses
Authors: Scholz Philipp , Sadowski Michael , Boit Christian , Kupijai Sebastian , Henniges Marvin , Theiss Christoph , Meister Stefan , Stolarek David , Richter Harald H. , Boostandoost Mahyar
Published: December 2020

This work is a unique solution for enhancing optical failure analysis and optical signal transmission. Optical failure analysis remains to be a vital part of the analysis process, despite shrinking feature sizes and challenging package technologies. The presented optical signal transmission supports the development of photonic integrated circuits. The key component is a Focused Ion Beam (FIB) process which shapes optical lenses out of the sample material leading to an improvement in lateral resolution and signal transmission. Two cases are shown that demonstrate these improvements. The first case is an optical backside analysis in a spatially confined opening of a package where other Solid Immersion Lens (SIL) systems could not be applied. It offers an improvement in spatial resolution by a factor of 2, down to a FWHM of 387 nm. The second case is a novel application for FIB shaped lenses aiming at photonic integrated circuits. This lens is created out of the isolating frontside and improves the grating coupler efficiency by a factor of 4.1.
Failure Analysis of Yellow Banding on Optically Bonded Touch Screen
Authors: Gu Qing , Lewis J. , Xu Danhua
Published: December 2020

Yellow banding is a phenomenon occurring at an edge(s) in an electronic optical touch screen when the display module emits certain background light. Although it is commonly recognized that the discoloration turns yellowish due to display liquid crystal (LC) cell gap change, the mechanism to create the color change can be different depending on the display designs. This paper discusses an approach to investigate a particular mechanism of forming yellow banding caused by uncured edge fill UV adhesive.
Detection and Measurement of Intermetallic Thin Films Using EDX Line Scanning
Authors: Nail Carl
Published: December 2020

Elementally characterizing intermetallic compounds (IMCs) to identify phases has routinely required relatively expensive transmission electron microscopy (TEM) analysis. A study was done characterizing IMCs using less expensive energydispersive x-ray (EDX) spectroscopy tools to investigate it as a practical alternative to TEM. The study found that EDX line scanning can differentiate phases by tracking changes in count rate as the electron beam of a scanning electron microscope (SEM) passes from one phase to another.
3D Integrated Power—A Discrete Perspective
Authors: Kearney Ian , Brink Stephen
Published: December 2020

The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.
Magnetic Current Imaging Power Short Localization
Authors: Gaudestad J. , Rusli F. , Orozco A. , Pun M.C.
Published: December 2020

A Flip Chip sample failed short between power and ground. The reference unit had 418Ω and the failed unit with the short had 16.4Ω. Multiple fault isolation techniques were used in an attempt to find the failure with thermal imaging and Magnetic Current Imaging being the only techniques capable of localizing the defect. To physically verify the defect location, the die was detached from the substrate and a die cracked was seen using a visible optical microscope.
Logic LIVA Fault Isolation in Synthesized Logic
Authors: Pifer T. , Eiles T.M.
Published: December 2020

Infrared emission microscopy (IREM) is often the simplest and fastest fault isolation technique. In contrast to emission microscopy, laser-based techniques, such as thermally induced voltage alteration and light induced voltage alteration (LIVA), are not as dependent on leakage or the specific voltage of the defect to provide localization but are able to observe variations in the defective current drawn by the defect. This paper describes a method of applying LIVA to synthesized logic connected to large-scale power plane by controlling the amount of decoupling capacitance on the power supply. This has proven to provide very useful fault isolation beyond what is possible with emission microscopy. The logic LIVA result allowed the determination of locations of the two emissions seen in the IREM image as well as the word-line driver. This result provides a complete picture of the failure exact word-line driver-simplified physical failure analysis.
Strategies to Address Low DPPM Failure Mechanisms on Automotive Grade Wi-Fi Radio Frequency Devices
Authors: Wang Kai , Lone Sadia , Thomas Colin , Weaver Rhys
Published: December 2020

System suppliers in the automotive market have an expectation that their IC suppliers provide products with low defective parts per million (DPPM) and have methodologies in place to drive towards 0ppm (Zero Parts Per Million). IC suppliers to the automotive market have supply chains and test methodologies in place to achieve such low DPPMs, but the systems suppliers will still require root cause analysis on every failure. The IC supplier is expected to demonstrate a containment, corrective action and continuous improvement in a very tight time frame. This additional demand of automotive customers poses a challenge to the quality of IC devices and the concept of cross departmental failure analysis. In this paper, we look at a complex Wi-Fi design with multiple IEEE specific radios, and how to address the few parts that escape the rigorous testing by IC supplier to improve the quality for the automotive IC.
Acid Decapsulation for Silver Wire Bonded Package
Authors: Suzuki Satoshi , Yamaguchi Mamiko
Published: December 2020

Decap methods which have been used for copper wire packages are not effective for silver wire packages, and the authors recognized the need for the development of a novel method. This paper discusses the development of various processes to decap silver wire packages with acid. The first decap method developed for a silver wire package was to add hydrochloric acid to fuming nitric acid. This method proved insufficient to prevent silver wire from dissolving when solution temperature is 60 degree. The authors then developed the Saturation Etch method for decapsulating silver wire packages using a chemical solution. When dissolution amount of silver wire put in normal fuming HNO3 is defined as 100%, the authors were able to achieve its reduction to less than 3% by using saturated acid. This method is also effective for copper wire packages, and damages to wires can be minimized by dissolving copper into acid.
What Happens to Electrostatic Sensitive Devices in Case of Direct ESD from Plastics?
Authors: Jacob Peter
Published: December 2020

The judgment of ESDS risks by direct electrostatic discharge from plastics is a challenge due to the variety of possible discharge scenarios. This paper discusses physical backgrounds of the different discharge scenarios from plastics and tries to rank ESDS related risks. It includes specific hints for ESD prevention in plastics lamination processes as RFID cards, smart cards or contactless money cards, where ESD-sensitive devices (ESDS) are at specific high risk for ESD discharge from plastics. Also further process-related risks and package issues are discussed.
Capturing Defects in Flip-Chip CMOS Devices Using Backside EBAC Technique and SEM Microscopy
Authors: (Jane) Li Yuanjing , Aguada John , Lu Jiafang , Yang Jessica , Ng Roy , Marks Howard Lee
Published: December 2020

This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.
In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards
Authors: Colvin Jim , Hazeldine Timothy , Patel Heenal
Published: December 2020

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.
FIB on Test Board
Authors: Suzuki Eiji , Adams Josh , Ball Calvin , McCready Tim , Robinson Sonya
Published: December 2020

This paper offers an alternative solution in dealing with Focused Ion Beam (FIB) circuit edit debug of RF products that often required soldering the device onto a test board to enable sensitive RF characterization. Performing FIB circuit edit while the device is soldered on a test board not only eliminates signal degradation and inconsistency caused by a socket; but also, it allows for adding additional FIB edits on the same device. The conventional way of RF product debug of devices in a wire bond package was to characterize the device in a socket, perform the FIB circuit edit, encapsulate the cavity to protect the device from physical & thermal damage, solder the device onto the test board, and then perform post-FIB characterization. This is a very long, one-way process and needs multiple devices for design debug. For RF products in flip chip package, this approach was extremely difficult to almost impossible, because thermal stress of soldering device would significantly deform thinned die. All characterization had to be done with a socket, which often introduced changes of the same magnitude of the parameters of interest as well as repeatability issues. The purpose of this paper is to outline steps to allow for the RF FIB and characterization cycle to be done in a way to decrease throughput time and increase measurement accuracy. True characterization of highly sensitive RF circuit modifications is achieved through: soldering the device to the test board, performing sample preparation, preforming pre-FIB characterization, preforming FIB, and finally preforming post FIB characterization. Elimination of the need to solder a thinned device to a test board allows for the edit location to remain open enabling additional FIB edits to be performed on the same device. This eliminates redundant steps in the device sample preparation and enables quicker throughput times.
Conductive-AFM for Scan Logic Failure Analysis at Advanced Technology Nodes
Authors: Zhang Chuan , Khiam Oh Chong , Chen Esther P.Y.
Published: December 2020

The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge nodes, novel FA techniques have to be explored and incorporated into the routine FA flow. One of the novel techniques incorporated into the presented scan logic FA flow is the conductive-atomic force microscopy (CAFM) technique. This paper demonstrates CAFM technique as a powerful and efficient solution for scan logic failure analysis at advanced technology nodes. Several failure modes in scan logic FA are used as examples to illustrate how CAFM provides excellent solutions to some of the very challenging FA problems. The gate to active short in nFET devices, resistive contact, and open defect on gate contact are some modes used.
Innovative Nondestructive Compositional Mapping of Trace-Elements and Contaminants at Micron-Scale in Wafers and Packaging
Authors: Lau S.H. , Yun Wenbing , Lewis Sylvia JY , Stripe Benjamin , Kirz Janos , Lyon Alan , Reynolds David , Chen Sharon , Semenov Vladimir , Spink Ian
Published: December 2020

We describe a technique for mapping the distribution and concentrations of trace elements, most notably with capabilities of achieving 1-10 parts per million sensitivities within 1 second and at <8 μm resolution. The technique features an innovative, high flux microstructured x-ray source and a new approach to x-ray optics comprising a high efficiency twin paraboloidal x-ray mirror lens. The resulting ability to acquire dramatically higher sensitivities and resolution than conventional x-ray fluorescence approaches, and at substantially higher throughput enables powerful compositional mapping for failure analysis, process development, and process monitoring.
Charging Reduction Method for Auger Analysis on Imide Surface
Authors: Zakaria Nurhanani
Published: December 2020

This paper outlines a method that has been found to effectively reduce the charging effect on imide surfaces during Auger analysis. This methodology enables in-house Auger analysis on insulators in the semiconductor industry. The compositional analysis at the imide surface is as critical as analysis at the bond pad surface due to its impact on the reliability of the product. Current practice is the use of a thin Au/Pd coating to reduce the charging effect, but there are some drawbacks such as the creation of artifacts due to the presence of Au/Pd peaks in the spectrum. Apart from that, the signal to noise ratio (S/N) is reduced, masking the desired signal. When this scenario occurs, we implement a new combination method of a low angle incident beam along with special sample preparation. This method provides a spectrum with good S/N and no charging effects and eliminates the Au/Pd peak artifacts.
Use of Second Harmonic and Thermal Effects of Laser Voltage Probing for Better Fault Isolation
Authors: Yeluri Ramya , Thirugnanasambandam Ravishankar , Wagner Cameron , Urtecho Jonathan , Neirynck Jan M.
Published: December 2020

Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.
Improved Method of ROI Encapsulation during Axis Conversion of Cross-Sectional S/TEM Lamellae
Authors: Senowitz Corey , Endrinal Lesly , Nguyen Hieu , Ranganathan Lavakumar , Vollrath Ruby , Yuan Caiwen
Published: December 2020

Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact physical location of the defect. The default technique for isolating the defect location for this type of device is to start with a plan view S/TEM lamellae. Once the defect is located in plan view, the lamellae can be converted to cross-section (if necessary) for further characterization. However, if the defect is not detectable in plan view S/TEM analysis, an alternative approach is to examine the device in cross-section along either the x- or y- axis. Once the defect is located in the initial cross-sectional lamellae, it can be converted to the orthogonal axis if the initial cross-sectional lamellae did not provide adequate information for characterization. However, in converting a cross-sectional lamellae to the orthogonal axis, the initial lamellae must be exceedingly thin due to the dimensions of devices on 1x nm FinFET technologies, else other structures on the sample can obscure the view in the S/TEM. This can lead to structural integrity (warping) issues for the converted lamellae. In this paper, a novel solution to the warping issue is presented.
Nondestructive Bond Pull and Ball Shear Failure Analysis Based on Real Structural Properties
Authors: Asadizanjani Navid , Forte Domenic , Tehranipoor Mark
Published: December 2020

Bond pull testing, a well-known method in the failure analysis community, is used to evaluate the integrity of an electronic microchip as well as to detect counterfeit ICs. Existing bond pull tests require that the microchip be de-capsulated in order to obtain physical access to the bond wires in the IC package. Bond pull analysis based on simulation and finite element methods also exists but relies on the original model for a bond wire from a CAD design. In this work, we introduce X-ray tomography imaging with 700nm imaging resolution to acquire the 3D geometry details of bond wires non-destructively. Such information can be used to develop more accurate models for finite element analysis based on real size and structure. Therefore, one can test the bond wire strength as a proof of concept for virtual mechanical testing and counterfeit detection in microchips.
Nondestructive Visualizations of Short Circuits in Ball Grid Arrays by Magnetic Field Imaging and Three-Dimensional X-Ray Microscopy
Authors: Suzuki Kazuhiro , Tsutsumi Masayoshi , Saito Masako , Toda Makoto , Yamamoto Kouzou , Terui Yuji
Published: December 2020

It is important to locate a short circuit failure in semiconductor devices, and powerful tools such as lock-in thermography and optical beam induced resistance change are used. However, those tools are inappropriate for investigating the device covered with the impenetrable substance to light, because the covering substance blocks the light from the defect point in the device and also prevents the optical beam from outside of the device. We demonstrate that a subsurface short circuit in a ball grid array device can be located by magnetic field imaging (MFI) and the electromagnetic field reconstruction method (EM-FRM), which makes it possible to calculate a magnetic field in the immediate vicinity of the current that is the source of the field from a measured magnetic field at a distance. Moreover, we visualize the short circuit by three-dimensional X-ray microscopy. MFI is also applied to visualization of a magnetic field created by a current flowing inside a printed circuit board and a light emitting diode package.
Study on Development Behavior and Mechanism of Delamination by NCF Material under uHAST Test Condition
Authors: Kim Ju Young , Kim Hyoung-Ryeun , Hahn Dong Woo , Hwang Sung Min
Published: December 2020

NCF (Non Conductivity Film) is a material used for under-fill purpose in the TSV (Through Silicon Via) process, and is a key material for ensuring TSV 3D Package (PKG) reliability. Among the types of defects generated by the NCF, the most typical type is delamination. Particularly in NCF delamination frequently occurs during reliability test, we analyzed chemical state change of NCF according to reliability test step/condition by utilizing FTIR and TMA. Through these studies, we clarify the cause of Delamination.
Failure Analysis of Variable Resistor
Authors: Iwai Yasunobu , Imai Yasuo
Published: December 2020

Three failed modules were found during routine inspection of industrial equipment after several years of service. We investigated failure causes of them. As a result of the investigation, we show that there are different failure modes for each type of variable resistors (cermet type, carbon composition type, wire wound type). (1)Cermet type: The wiper was unstable because the wiperfixing was weak already during manufacturing. (2)Carbon composition type: The R12 (resistance between #1 and #2 terminals) was unstable because of extraneous materials in manufacturing or zinc whiskers. (3)Wire wound type: The R13 (resistance between #1 and #3 terminals) was broken by the scratch in manufacturing.
A Case Study of Trapped Charge Induced Surface Leakage
Authors: Wang Xiang-Dong , Cheng Xu , Stefanov Evgueniy , Godek William
Published: December 2020

In many cases, the leakage is relatively small and tends to spread out over a relatively large area. While diagnostic techniques using laser stimulation, such as OBIRCH, or photoemission are powerful in identifying localized defects in silicon crystal and backend metal layers, they are found to be not as sensitive in isolating charge induced leakage. This paper presents a case study of dielectric charge induced leakage in a high voltage ESD device. In this case, conventional photoemission and laser probing diagnostic techniques were not able to localize leakage sites. By using atomic force probing for detailed electrical characterization of individual devices, experimenting with UV radiation, and SCM 2D dopant profiling analysis, it showed that trapped charges in dielectric layers cause leakage near silicon surface. Based on the finding, the FAB fixed the issue by implementing UV bake in the process.
EBAC for Isolating Partially-Localized FEOL Electrical Shorts on Test Structures during Sub-14 nm Technology Development
Authors: Masnik John , Saujauddin Noor Jehan , Davidson Kevin , Chen Esther P.Y. , Beaudoin Felix
Published: December 2020

EBAC is a high-resolution, static technique that can be used for isolating electrical shorts, but it begins to fail for large, interconnected, test structures. In such cases, localization can be achieved when combined with optical localization techniques such as OBIRCH. This paper presents two case studies of subtle, FEOL shorts on a sub-14nm technology that required the resolution of EBAC.
Nanoprobing Beyond 14 nm with Latest Generation SEM-Based Nanoprobers
Authors: Saujauddin Noor Jehan , Chen Esther P.Y. , Beaudoin Felix
Published: December 2020

As the technology scales down, SEM (Scanning Electron Microscope) based nanoprobing faces challenges. Transistors are more susceptible to electron beam damage. As SEM energy decreases to prevent damage, imaging resolution degrades, making it increasingly more difficult to position the probe tips on the contacts. Once landed, the probe stability is important to maintain a good electrical connection throughout the measurement time. We review how well one of the latest generation nano probers addresses these challenges on sub 14nm transistors. Results are compared with a previous generation tool to illustrate the improved imaging and stability capabilities.
Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging
Authors: Sheridan Lucile C. Teague , Conohan Linda , Oh Chong Khiam
Published: December 2020

Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.