bluuebunny/crossref_metadata_2025 huggingface dataset:
Fine pitch Copper Pillar interconnection with C4 (Mass Reflow) Processing
Authors: Roa Fernando
Published: October 2015

Flip chip interconnection design and process capability has been extended with the use of copper pillar, specially for finer pitches, beyond what was possible with area array and standard C4 reflow and solder bumps. Many trends in device packaging are fueling this trend, specially the needs for thin packaging, increased function integration, challenging thermal, mechanical and physical specifications.

In terms of processing, devices using Cu Pillar are most commonly assembled using thermo-compression bonding due to sizable challenges in extending the conventional mass reflow solution, typical for solder bumps. TC is specially recommended for handling very thin die in sparse or peripheral bump layouts, which are a predominant share of all devices converting to Cu pillar, where a bonding head is used to both hold the die flat and in true alignment with the substrate while supplying the thermal energy necessary to complete the interconnection. This process most often also requires the use of a non-conductive paste/film for stress absorption in recognition to the fact that underfill materials have great limitations in filling the underdie cavity.

In this paper, we explore avenues to extend the current processing envelope for Cu pillar bumped devices using C4 reflow. Benefits of this approach are shown as decreased cost of ownership for materials, lower fixed costs due to using mostly depreciated equipment. Yet, challenges in defining new design rules, reformulating materials and extending process flows are among some of the barriers for further adoption of this solution in production
Wafer Dicing Using Dry Etching on Standard Tapes and Frames
Authors: Lishan David , Lazerand Thierry , Mackenzie Kenneth , Pays-Volard David , Martinez Linnell , Grivna Gordy , Doub Jason , Tessier Ted , Burgess Guy
Published: October 2015

To meet the changing demands of consumer product form factors, there has been a steady shift to thinner and smaller semiconductor die, both of which increase the challenges for die singulation. The traditional approach of saw dicing is facing new limitations due to die damage and throughput. Compounding these issues is the finite width of saw blades, saw blade loading from clearing multiple materials, and orthogonal layout restrictions. Laser dicing has been introduced to address some of these issues, but faces other limitations such as damage from the heat affected zone, ablation residues, throughput, and material incompatibilities (changes in transparency and absorption in the street). In some cases, a combination of both saw and laser has been utilized to surmount some of the technical obstacles.

The recently introduced approach of front-side plasma singulation circumvents many of the limitations of saws and lasers. The technology presented in this work uses standard dicing tape and frames, is through-wafer complete die separation, and does not involve a subsequent wafer thinning or die cleaving step. Our approach utilizes lithographically defined singulation lines with typical widths of 10–15μm, and delivers chip/crack-free edges with low-stress rounded corners. The parallel nature of this singulation method enables non-orthogonal and non-linear singulation streets allowing die layout and design flexibility not achievable by saws and/or lasers. As a consequence, plasma singulation produces increased good die per wafer through better wafer area utilization, lower die failure (reduced corner stress with rounded geometry), and flexibility in die placement near wafer edge on larger die. One of the unique advantages is that this technology can be implemented without addition of any new masking layers but instead the use of the existing passivation, metals and/or upper dielectrics as masks.

Implementing this technology across a wide range of die applications such as power, memory, logic, imaging sensors, LEDs, and MEMS must address a diverse range of variables such as compatible materials, bond pads/bumps, and backmetal. For dies with backside metal, a non-etch based method to allow full die separation while the dies are still attached to tape has been demonstrated.
SOLDERABLE ANISOTROPIC CONDUCTIVE ADHESIVES FOR 3D PACKAGE APPLICATIONS
Authors: Liu Mary , Yin Wusheng
Published: October 2015

3D packaging has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize devices and meet the demand of high speed, provide more memory, more function and low cost. With the advancement of 3D packaging, the bump height is now down from 80μ to 10μ. When the bump diameter is 20–40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however underfill won't help assembly process. In order to resolve some difficulties that 3D packaging faces, YINCAE Advanced Materials, LLC has developed solderable anisotropic conductive adhesives for 3D package applications. In this paper we will discuss the assembly process and reliability in detail.
PMV (Plating Mold Via) interconnection development in molded SiP modules
Authors: Yoo Do-Jae , Ryu Jong-In , Oh Gyu-Hwan , Park Yong-Choon , Lee Ki-Ju , Kim Jin-Su , Choi Jong-Woo , Kim Ki-Chan , Lee Il-Hyeong , Kang Tae-Sung , Lim Peter
Published: October 2015

Recently, there are increasing demands of a size reduction and a fine interconnection technology, especially for System-in-Package (SiP) module and Package on Package (POP) module in a smart phone and a wearable electronic device.

In this study, we presented the Plating Mold Via (PMV) interconnection technology as an innovative fine pitch interconnection solution between substrate I/O pads and package I/O pads in molded System-in-Package (SiP) modules. Similar to the Through Mold Via (TMV), the laser mold via process is first performed to produce a through-via in the Epoxy Mold Compound (EMC) mold, but plating and Soldering process are used simultaneously to produce the metallurgical interconnection to embody the I/O pins of the over-molded surface. After the PMV technology is described, a study of PMV in the molded packaging module is followed. The study is conducted using a test vehicle of SiP module that contains flip chips, Quad Flat Non-leaded (QFN) packages and passives. It is focused on several interface reliability issues, including the interfacial strength of PMV to substrate metal pad as well as to the laser projected area of EMC, and the study of IMC at the plating metal and solder interfaces.

The study clearly shows that the PMV technology is a promising fine pitch interconnect solution for various SiP modules.
Development of a stress compensation layer for thin pixel modules 3D assembly
Authors: Pares G. , McMullen T. , Tomé S. , Vignoud L. , Bates R. , Buttar C.
Published: October 2015

The pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in CERN LHC facility. They consist in their basic form of a silicon sensor that is flip-chipped bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach towards low mass modules and thus reducing radiation length. From the module perspective this can be achieved by using advanced 3D technology processes that includes the formation of copper and solder micro-bumps on top of the ROIC front-side, the thinning of both the sensor and the CMOS ROIC and finally the flip chip assembly of the 2 chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage due to bad co-planarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100um, the chip bow varies from − 100 μm at room temperature to + 175 μm at reflow temperature resulting of CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the back-side of the wafer. Utilising our material thermo-mechanical database coupled with a proprietary analytical simulator and measuring the bow of the ROIC at die level we are able to reduce the bow magnitude by approximately a factor of 3 by the introduction of the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. This amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the backside deposition conditions are on-going where the target is to control the room temperature bow close to zero and reducing the bow magnitude throughout the full solder reflow temperature range hence conserving bump yield. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach in mind should we integrate this technology in the future.
Capacitive-Based, Closed-Loop Frequency Control of Substrate-Integrated Cavity Tunable Filters
Authors: Saeedi Shahrokh , Wilson William S. , Ashley Tyler R. , Sigmarsson Hjalti H. , Lee Juseop
Published: October 2015

In this paper, we present an integrated capacitive sensing technique that can be used to achieve closed-loop feedback control of variable capacitors. The technique is well suited for diaphragm-based actuators that can be used to tune the center frequency of microwave reconfigurable filters. A commercially available capaci-tance-to-digital converter is used to measure the capacitance of a custom-made monitoring capacitor. This capacitor is completely external to the filter structure and does not contribute to any added losses. A tunable, second-order, bandpass filter –using substrate-integrated, evanescent-mode cavity resonators– is created to demonstrate the concept. The frequency tuning is achieved using piezoelectric actuators to displace a flexible copper diaphragm that forms the top part of the loading capacitor. The monitoring capacitor consists of a second cavity that is mounted above the actuator forming a second air-filled, metal-insulator-metal capacitor. There exists a direct relationship between the monitoring capacitance and the loading capacitance in the evanescent-mode cavity. Therefore, by tracking the monitoring capacitance the center frequency of the filter can be monitored, which allows for direct in-situ closed-loop control of the filter. An algorithm for the tuning operation is presented, which includes an automatic calibration technique to initialize the controller. The effectiveness and repeatability of the technique is evaluated as the filter is tuned from 3.3 GHz to 3.7 GHz. Having stable feedback control integrated with this type of evanescent-mode cavity filters, brings the technology one step closer to actual fielding.
BENEFITS OF TRANSMISSION LINE METAL-INSULATOR-METAL CAPACITORS IN MASS PRODUCTION OF RF CIRCUITS
Authors: ATALAN Cenk , TONGEL Eyup
Published: October 2015

Coupling capacitors or DC blocks are essential tuning elements in RF/microwave applications. Their role becomes imperative in cascade amplifiers to isolate drain voltages of preceding MMIC from the gate voltage of the following chip where both RF and DC signals are carried through the same line. The purpose of this study is to explain the benefits of a newly designed thin film coupling capacitor called as transmission line metal-insulator-metal capacitor (TL MIM Cap), which serves as a DC block capacitor in microwave circuits. This novel structure provides a unique solution, which cannot be achieved with traditional single layer ceramic capacitor (SLC) structure. It combines two discrete circuit elements into one: “Microstrip transmission line of required length and width” with a “serially attached coupling capacitor”. Thin film capacitive layers ranged from 0.5pF to 50pF, which are typically needed for microwave frequencies within 1–40 GHz, constructed and embedded into 50 Ohm impedance transmission lines in series. Substrates like quartz, glass, or alumina can be used to minimize losses and to achieve higher RF/microwave performance. We used copper traces as conductive layers for optimal conductivity.

After manufacturing TL MIM Caps, we tested several capacitance values for 1pF, 5pF, 15pF and 30pF corresponding to a wide frequency range. The RF tests we performed showed that TL MIM Caps exhibited a minimum of 20dB return loss and a maximum of 0.3 dB insertion loss at 1–40GHz range. We also found our technique comes with some workmanship advantages in high frequency circuit assembly as follows: Traditional coupling capacitor attachment with silver epoxy on top of a microstrip transmission line is a manual operation, which requires well trained and experienced technicians. In contrast, using the TL MIM Caps in our high frequency hybrid modules, we found that the process caused errors were eliminated such as the micro short circuit effect caused by conductive epoxy. Therefore we improved yield in assembly stage of the circuits. In addition, improvements are observed in production processes such as less consumption of adhesives (epoxy), no technician failure caused wastes, elimination of extra curing process to attach capacitors, no short circuit inspection, rework, or re-cure operations to fix assembly errors. Last but not least, blocking capacitors are embedded into the microstrip transmission lines in TL MIM Caps. This ensures that having the lowest possible impedance since very short wire bond exists from the bond pad of the TL MIM Cap to the adjacent circuit element.
Analysis method of tool topography change and identification of wear indicators for heavy copper wire wedge bonding
Authors: Eichwald Paul , Sextro Walter , Althoff Simon , Eacock Florian , Unger Andreas , Meyer Tobias , Guth Karsten
Published: October 2015

One of the main cost factors in the wire bonding process are consumables such as bonding tools. The technological transition to copper as wire material causes significant wear on the millimeter size effective contact area of the bonding tool. This wear leads to a reduction of the number of reliable interconnections which can be produced using a single tool by a factor of 30 replacing the wire material from aluminum to copper. To reduce setup time in the production and minimize costs, an increase in bonding tool lifetime is desired. Consequently a better understanding of the wear and recognition of wear pattern is required. This paper presents a method to analyze tool topography change of a heavy wire bonding tool by using a confocal laser scanning microscope. Furthermore, this paper discusses the identification of the main wear indicators by help of the change in topography.

Wear test has been carried out by choosing typical parameters of the production line. This topography change is compared to the topography change caused by increasing the ultrasonic voltage. To evaluate whether the quality requirement of the bond connections made by a single tool cannot be fulfilled, shear tests of the source bond were made in predefined intervals. All worn tools show dominant areas of wear especially for plastic deformation and accordingly abrasion. These wear mechanisms can be referred to the change of main parts of the groove geometry like the rounding of the front and back radius. The most loss in height was identified in the lower part of the tool flanks or rather at the transition from groove flank to the front or back radius. Furthermore the observation of the center of the groove flank shows just a little change. All in all, the identification of the wear indicators will be discussed with the objective of increasing the tool lifetime by optimizing the tool geometry without losses in bond quality and reliability.
Silver plating for LED applications, technology, processes and production experience.
Authors: Burling Steven , Nicholls Gary , Christensen Peter , Nagatomo Sadayuki , Shiokawa Kazuhiko
Published: October 2015

How the metal finishing (plating) market is meeting the technical demands of this LED market will be the subject of this paper. Specially designed Silver Plating processes for LED in order to achieve high brightness (1.8 GAM or higher) whilst also giving deposits with high reflectance will be discussed. The use of specially developed Drum Plating (Stripe plating) equipment enabling spot plating with high brightness and wider current density area will be documented as well as how these products are moving towards more Environmentally Friendly low and non-cyanide systems.
Measurement of Electrical Conductivity of Direct Digital Printed Conductive Traces Using Near-Field Microwave Microscopy
Authors: Córdoba-Erazo María F. , Rojas-Nastrucci Eduardo A. , Weller Thomas. M.
Published: October 2015

Non-contact measurement of electrical conductivity of direct digital manufactured traces using a dielectric resonator-based near-field microwave microscope (NFMM) operating at 5.73 GHz is reported. The NFMM uses a set of printed samples with known conductivity to build a calibration data set which correlates measured quality factor (Q) data with electrical conductivity (σ). Direct print additive manufacturing is used to produce the 10 mm x 10 mm calibration samples using CB028 silver ink and glass as the substrate. Conductivity of calibration samples ranges from 1.70e6 S/m to 3.22e6 S/m and it is measured using a commercially available four-point probe. Conductivity measurement of the calibration samples using NFMM reveals that the microscope is sensitive to printed samples with different conductivities and that it is able to resolve differences in conductivities as small as 0.38e6 S/m in the range 2.20e6 S/m ≤ σ ≤2.53e6 S/m. Conductivity and topography images of a printed trace are acquired simultaneously over a scan area of 100 μm x 100 μm using the non-contact NFMM at a distance of 3 μm from the sample. Conductivity images reveal that the conductivity is not constant over the scan area and that it varies from 0.6 S/m to 2 S/m. Roughness calculated from NFMM topography shows good agreement with the values computed from profilometer data.
Advanced Process Technology for 3D and 2.5D Applications
Authors: Shelton Doug , Kume Tomii , Wang Charles , Hubbard Alex , Murray Cody , DeLancey Rob
Published: October 2015

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies.

In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.
Comparison of Measured and Modeled Lithographic Process Capabilities for 2.5D and 3D Applications Using a Step and Repeat Camera
Authors: Webb James , McCleary Roger , Lopez Gerald , Tan Qing
Published: October 2015

Increasing volume using larger substrates with decreasing process margins create new challenges for advanced packaging applications. Key step and repeat camera technology continues being introduced for the mass production of high density interconnects used for 2.5D and 3D technologies that will provide solutions for the challenges encountered.

A 2X reduction stepper with unique features achieves the tighter specifications needed for many advanced packaging applications printed on large substrates. A large field-of-view optical projection system utilizes the 350–450nm light spectrum from a mercury arc to expose the circuit patterns from a reticle mask onto a substrate and image features with the optimal fidelity required for advanced packaging technologies. The imaging field prints a large 52mm x 66mm area or 59.4mm x 59.4mm in a single exposure. These features enable a system to process larger substrates in fewer shots which result in higher throughput using lower power.

Details of the camera and the adjustments that are provided to extend the range of use for both high power and high fidelity applications are discussed.

An extensive evaluation of measured and modeled lithographic capabilities of the step and repeat camera to achieve critical dimensions with precise image placement is provided. Limiting resolution and depth of focus results sampled over the imaging field will be provided and supported with simulation. Results of thin and thick resist patterning will be presented and compared to simulated 3D resist profiles using the MACK4 model.
Efficient Non-reagent Metrology for Modern TSV Baths
Authors: Pavlov Michael , Lin Danni , Shalyt Eugene
Published: October 2015

Through-silicon via (TSV) technology is gaining popularity in 3D packaging and 3D integrated circuits. TSV baths are formulated with highly stable electrolytes that contain copper and sulfuric acid. Other components introduced into the bath in relatively small amounts are organic additives and chloride ions. This article will focus on a non-reagent metrology to efficiently monitor these components.

The chloride concentration is determined from the chloride oxidation current using specific voltammetric parameters. Similar to analysis of suppressor, the measurement is made directly in the undiluted plating bath. Results for non-reagent analysis for acid and copper were reported earlier. Electrochemistry and spectroscopy are employed in on-line monitoring of various TSV baths.

The concentrations of organic additives are determined from the rate of the copper deposition. The new techniques differ from conventional CVS procedures. The advantages of these newly developed electrochemical procedures are speed (results are obtained within one minute), accuracy and reproducibility. Our new non-reagent techniques do not use special reagents for analysis and require only standard solution used for automatic system calibration and validation.
PWB Z Interconnect Technology - Electrical Performance
Authors: Carver Chase , Seastrand Norman , Welte Robert
Published: October 2015

Driven mainly by Moore's law, there is an ever accelerating drive for smaller, lighter, higher function, and lower power electronics. For PWBs this translates into higher wiring and component densities with ever increasing electrical performance requirements. As high speed serial data rates reach 30 Gbps and beyond, design considerations to promote signal integrity become ever more important. These tighter signal integrity constraints put increased emphasis on via stub effects, via to trace crosstalk in BGA escapes, and adequate ground stitch vias around layer transition vias. With the maturation of sintered paste VIAs in PWBs, VIA structures can be assembled to span only the layers to be connected. This paste technology allows vias to be specifically tailored to only connect the required layers. VIA stubs and their adverse SI effects for high speed signaling are completely eliminated. The elimination of via stubs also makes PWB fabrication easier by removing the need to backdrill or counterbore high speed signal vias. This increases yields and reduces costs associated with this complex and tight tolerance process. In addition to manufacturing advantages provided by Z technology, increased wireability is enabled by opening up area above and below the layers being connected, as well as the ability to use smaller diameter VIAs. These smaller vias also help to reduce crosstalk between high speed wiring channels. Z Interconnect technology also reduces BGA escape crosstalk by the ability to route in areas where via stubs have been removed, and also allows for the tailoring of ground stitch vias to only connect the ground planes associated with the specific stripline environments. However, Z VIAs usually require more pads within the padstack than conventional VIAs (cannot strip pads from non-connection layers) and the resistivity of the paste can be as much as 30 times greater than copper. This paper will quantify the high frequency signal characteristics associated with a PWB design using i3 Electronics sintered paste Z-VIAs. Results are presented based on modeling which is correlated with test vehicle measurements. Modeling also addresses manufacturing tolerances. Suggestions are made for optimizing passive channel structures to use this technology in support of high speed serial interconnects. Integration of i3's 2s1p Cores into new compact high speed stripline structures, which can be built without expensive subassemblies and sequential lamination processes, is also presented. These cores implement the positive aspects of Z Interconnect technology to eliminate via stubs and increase wireability in dense areas. Comparisons of Z Interconnect technology are also made to alternate methods of PWB construction to explain the risks and benefits of this technology.
Thermal and EMI Performance of Composite Plastic Molded Heat Sinks and Hybrid TIM Materials
Authors: Bhobe Alpesh , Chu Herman , Comiskey Lynn , Jiao Xiangyang , Li Xiao
Published: October 2015

Heat sinks are widely used in thermal management of electronics. However, it is also well established that a heat sink can couple and radiate electro-magnetic (EM) energy from the same component that it is cooling. As the frequency of these devices continues to increase, it is more crucial to try to suppress the EM radiation at the source. The component suppliers for thermal management and EMI products have been developing materials that are thermally conductive and also have EM absorbing properties. The thermal and EMI material properties of the additives can change the properties of the final material and they may not always be complementary between thermal and EM absorbing behaviors. In this paper, two such hybrid solutions are investigated to understand the thermal and EM absorbing characteristics and interactions. These are: (1) heat sinks made of composite plastic materials; and (2) hybrid RF/thermal interface materials (HRTIMs).

For the heat sink study, three heat sinks of the same physical design (40mm square x 8.25mm tall) but with different materials are tested and analyzed. Two of the heat sinks are molded from two different composite plastics (Materials A and B), while the third one is constructed from aluminum and used as the baseline heat sink for comparison. The results presented in Figure 7 show EMI improvement for composite material heat sinks over the traditional aluminum heat sink. Material A provides a broadband reduction of 2–3 dB power whereas Material B heat sink provides significant reduction at lower frequency range of 1–8 GHz. The thermal performance results are plotted in Figure 11 – Figure 14, and the results show that the composite plastic materials are more suitable for applications that have lower power and power density.

For the HRTIMs, two different base materials at different thicknesses are investigated and the material details are given in Table 2 . Similar to the heat sink EMI study, Total Radiated Power (TRP) measurements are performed for the HRTIMs in an Electromagnetic Reverberation Chamber in the frequency range of 5–40 GHz show improvement for material TIM 1. The EMI results are plotted in Figure 9 and Figure 10. For thermal performance characterizations, an ASTM D-5470 compliance test stand (Figure 6) is used. The thermal impedance results of these materials are plotted in Figure 15.
Size Effect of Particulate Filler on Electrical Resistivity of Carbon Nanotube Polymer Composites: Transition of Excluded Volume Effects
Authors: Park Sung-Hoon , Hwang Jinyoung , Yun Dong-Jin , Lee Sangeui , Lee Sang Hyun , Han InTaek
Published: October 2015

Hybrid Carbon nanotube (CNT) composites consisting more than two different kind fillers have received considerable attention which could improve electrical conductivity and mechanical properties. Incorporation of micro-scale second filler, excluded volume is created that effectively creates a segregated network of nanotube. Even if there were successful trials with theoretical model in second filler composite system, it was not fully understood how the electrical conductivity increase with respect to shape (or size) of second filler. Aim of the present research is an understanding of size effect of particulate filler on electrical resistivity of carbon nanotube polymer composites. Depending on size of particulate filler, conductivity of carbon nanotube polymer composites are changed (increase or decrease) indicating there is transition of excluded volume effects. For example, enhanced conductivity was observed in cooperation with micro-size second filler while decreased conductivity was observed for nano-size filler.
Reliability Assessment of Flip-chip Assembly of Al Bumps
Authors: TANISAWA Hidekazu , HIYAMA Kohei , ANZAI Takeshi , TAKAHASHI Hiroki , MURAKAMI Yoshinori , SATO Shinji , WATANABE Kinuyo , KATO Fumiki , SATO Hiroshi
Published: October 2015

This paper reports on a flip-chip bonding technology using an aluminum bump at high temperatures, such as for SiC semiconductors. In recent years, double-sided mounting structures have been proposed for the purposes of miniaturization and low inductance. The surface mounting method requires durability to withstand high temperatures. We propose a new technique for the flip-chip bonding of an Al bump made from bonding wire. The recrystallization temperature of aluminum is under 250 °C. As a result, there is an expectation of mitigating mechanical stress between the chip and bonded substrate. A high-temperature exposure test at 250 °C for 3000 hours and a thermal-cycle test between −40 and 250 °C for 3000 cycles have been executed. Results indicate that shear strength of the Al bump meets the requirements set forth in the IEC60749-19 guideline until 2000 cycles at room temperature.
Thick Film Technology For Today's Hearing Products
Authors: Dzarnoski John , Johansson Susie
Published: October 2015

There has been continuous worldwide effort to increase the volumetric efficiency of electronic packaging. Much of this effort has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality. The hearing aid business has always had the need to use extremely small electronic packaging because hearing aids pack electronics into the ear canal. The first commercial product using the transistor in 1952 was a hybrid vacuum tube-transistor hearing instrument. Today's hearing aids, such as Starkey's 3-Series product, have significant computing power and run complex hearing algorithms that have enormous impact on a patient's quality of life. The industry trend is to put more memory, more signal processing capability and more wireless capability into hearing aids to increase functionality and to improve performance. In order to achieve this increase in performance, the hearing business has had to develop and execute 3D packaging well ahead of other industries.

This paper will examine the history of ceramic hybrid packaging at Starkey. The challenges and drivers for major technology steps will be addressed. The following technical advancements, transitions, considerations and limitations will be examined: changing ASIC technologies, impact of chip metallization, solder interconnect temperature hierarchy, impact of RoHS legislation, overcoming routing design limits, miniaturization realized by flip chip attach, impact of chip stacking on size, migration to stacked thick film ceramic interconnect layers using vertical interconnect channels, advances in thick film materials to support higher interconnect density, and incorporation of integrated passive devices.
Packaging Design and Assembly for Ultrahigh Energy Density Microbatteries
Authors: Bjune Caroline K. , Marinis Thomas F. , Chiang Yet-Ming
Published: October 2015

For commercially available lithium ion batteries, the package structures can accounts for as much as 70 percent of its volume. In a multi-year effort, we have developed designs, fabrications, and assembly processes for ultrahigh energy density micro batteries of 5 and 1 cubic millimeter. Over the course of the research, the packaging system evolved due to changes or limitation specific to the battery system itself. During the study, improvements in the construction of the housing for the cathodes were made. Anodized aluminum cans fabricated through our in-house micro-machining facility replaced the electroformed gold cans used in earlier experiments. Throughout the iteration of the can design, a flange around its open end, which would be used for sealing, was present, and both designs were fabricated as arrays. The ability to fabricate the housings in an array format lends it to be implemented into a scalable production assembly process. Materials evaluated for the cover ranged from copper foil to the final design of metalized sapphire with a plated though via. One area which needed to be addressed was reducing the temperature of the assembly process due to a change in the cell materials. This resulted in developing a low temperature hermetic sealing process. The seal between the cover and can was made using a novel composite ring of indium and epoxy. The indium provided the hermeticity needed for the battery chemistry and the epoxy provided mechanical robustness. Most of our experience was with sealing temperatures of 100°C, but the sealing temperature is only limited by the cure temperature of the epoxy. One experiment was conducted to look at the reliability of the seal. A dozen one cubic-millimeter cells were filled with lithium and sealed. They were aged in laboratory ambient environment and periodically weighed. There was no weight gain in any of the cells over the course of several months, but one cell which was opened at the end of the experiment rapidly gained weight as the lithium corroded. The micro-battery cell developed in this program used a lithium cobalt oxide cathode in the form of a porous sintered compact. Its bottom surface was coated with a gold film so that it could be thermocompression bonded to a gold bump on the bottom of the can. Following bonding, the cathode assembly was spray coated with a polymer separator. The anode was a piece of lithium metal bonded to the battery cover. After the cover was sealed to the battery can, the cell was filled with electrolyte and charged. Then a plug was inserted in the via through the cover to seal the battery. Batteries assembled in this manner exhibited energy densities in excess of 200 Wh/l for the smaller volumetric package.
Reliability of PCB Solder Joints Assembled with SACm™ Solder Paste
Authors: Dasgupta Arnab , Zhou Fengying , LaBarbera Christine , Liu Weiping , Bachorik Paul , Lee Ning-Cheng
Published: October 2015

The solder alloy SACm™0510 has been reported to be a superior alloy when used as BGA balls, exhibiting not only an outstanding drop test performance when compared to SAC105, but also as having high thermal fatigue reliability when compared to high Ag SAC solders. In this study, SACm0510 solder was evaluated as a solder paste. The voiding behavior of SGA solder joints was comparable for SACm0510, SAC105, and SC305. When evaluating SGA assemblies on a customized drop test, SACm0510 outperformed SAC105 considerably, which in turn was much better than SAC305. The drop test performance was found to improve upon thermal aging at 150°C, and the difference between the alloys reduced significantly. This was explained by the speculated grain coarsening which resulted in a softened solder joint, and consequently, a shift of fracture mode from brittle failure toward ductile failure. This model was supported by the observation of the fractured surface moving away from the interface upon thermal aging. The improvement in drop test performance upon thermal aging can be further explained by the large solder joint size of the SGA employed in this study, where the bulk property of solder weighed more than a small solder joint. When the assembled chip resistors were evaluated with a −55°C/+125°C TCT test, no failure was observed after 369 cycles for all three alloys. SAC305 appeared to be the best in maintaining the integrity of the interfacial IMC layer. SACm0510 showed a few crack lines, but less than that of SAC105. SACm0510 solder paste was found to be very compatible with BGAs with SAC305 solder joints, and no abnormal microstructure was observed after thermal aging at 150°C for 1000 hours.
Comparison of Fabrication Process Capability and Electrical Performance with Silicon and Glass Interposers
Authors: Kuramochi Satoru , Koiwa Sumio , Takano Takamasa , Akazawa Miyuki , Mawatari Hiroshi , Suzuki Kousuke , Fukuoka Yoshitaka
Published: October 2015

As electronic product becomes smaller and lighter with an increasing number of function ↚ the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of TSV interposers and TGV interposers with fine pitch high aspect ratio through vias.
Development of Glass Interposer with Fine-Pitch Micro Bumps and Warpage Study Depending on Several Glass Substrates with Different CTE's
Authors: Mori Kenichi , Koizumi Naoyuki , Murayama Kei , Aizawa Mitsuhiro , Nagai Koji , Koyama Toshinori
Published: October 2015

This paper describes the development of a Glass-Interposer (Glass-IP) with 40um-pitch Cu micro- bumps. It features fine Cu wiring on the front side, Through-hole Glass-Vias (TGV), and a Re-distribution layer (RDL) on back side. After first explaining our process flow, we discuss the warpage of the fully assembled Glass-IP. The focus was on the CTE differences between the Glass-IP and the laminated substrate. The result was the lower CTE of the laminated substrate gave the assembly a lower warpage, while the CTE of Glass-IP had hardly any influence at all. Furthermore, we evaluated two assembly processes for the Glass-IP. One is called “Chip First Process” in which the chips are mounted on Glass-IP first. The other is called “Chip Last Process” where the Glass-IP is mounted on the laminated substrate first. It was confirmed by X-ray observation that the connectivity after full assembly is good for both processes.
Glass Substrates for Advanced Packaging
Authors: Shorey Aric , Pollard Scott
Published: October 2015

There has been substantial work done in the past few years to apply glass solutions for Advanced Packaging. Advantages of glass based solutions create significant opportunities by leveraging economies of scale, forming substrates at design thickness and leveraging thermal and electrical properties.

A lot of work is being done to validate the value of glass as an interposer substrate. The ability to leverage both wafer and panel-based metallization strategies for filling glass vias has been shown. Transitioning these processes to cost-effectiveness and high throughput has shown great promise. The electrical performance of glass relative to silicon at high frequencies makes glass solutions very attractive, particularly in RF applications. Electrical models and characterization have demonstrated the advantages of the insulating properties of glass, and its positive impact on functional performance. Reliability tests show that glass solutions can meet device requirements. The substantial progress and readiness in these areas will be presented.

Glass based solutions in panel format provide exciting and cost effective industry opportunities by leveraging economies of scale and glass forming technology. Existing technologies can be used to fill glass vias in a panel format, as well as apply redistribution layers. We will present the status of leveraging panel based technology to enable glass interposers.
Adhesion Enabling Technology for Reliable Metallization and Patterning of Glass Interposers
Authors: Hunegnaw Sara , Brandt Lutz , Fu Hailuo , Liu Zhiming , Magaya Tafadzwa
Published: October 2015

In this study a thin-film adhesive metal oxide layer is described that forms chemical bonds with glass, and mechanically anchors to copper to create strong, reliable adhesion between the glass substrate and the deposited metal. A modified sol-gel deposition process followed by sintering was used to create the thin, transparent film that then enables electroless, and electrolytic copper plating directly onto glass. With this new approach, a copper film thickness of over 50μm can be applied without delamination from the smooth glass. Adhesion at 15μm Cu thickness as measured by 90° peel strength tests can achieve values of ≥5 N/cm. This is compared in the study to mechanical roughening and a control with no adhesion promoter applied. Thermal stress tests using lead free reflow conditions and Highly Accelerated Stress Testing (HAST) were carried out without significant adhesion loss. Through hole adhesion was demonstrated inside the Through Glass Vias (TGV's) without issues of blistering or delamination from the walls. The study also looks at filling of the TGV's with electrolytic copper. Photolithography of fine-lines as small as 5/5 μm was feasible, with very small undercut observed. Electro migration and high frequency tests were also conducted to test material compatibility for RDL patterning, showing no loss in surface insulation or signal integrity.
How Can Millions of Aligned Graphene Layers Cool High Power Microelectronics?
Authors: Fan Wei , Rape Aaron , Liu Xiang
Published: October 2015

Thermal management is an increasingly critical problem in today's microelectronics industry. As power requirements increase and size requirements decrease, innovative materials with high thermal conductivity (TC), light weight, and many times low coefficient of thermal expansion (CTE) are desired to solve these thermal challenges. Thermal Pyrolytic Graphite (TPG*), a unique synthetic material produced by Momentive via chemical vapor deposition, contains millions of layers with highly-oriented stacked graphene planes and exhibits excellent in-plane thermal conductivity (>1500 W/m-K) and very low density (2.25g/cm3). In order to take advantage of its superior properties for thermal management, various forms of TPG-metal composite products were developed in the past few years. TPG composite with metal encapsulation simultaneously achieves high thermal conductivity from the TPG core and high mechanical strength from the metal shell. Momentive's proprietary bonding technology enables an intimate and strong joint between TPG and dissimilar metals, including Al, Cu, Sn, WCu, MoCu, AlSiC, and AlBe. In addition, the variety of compatible metals adds new functionalities to the TPG composite, such as platability and solderability for direct die attachment, CTE matching to semiconductor, and flexibility for off-plane connectivity. Also in this paper, three TPG composite categories, i.e.: TC1050* Heat Spreader, TPG Heat Sink and TPG Laminate, will be discussed in detail. Individually, their design guidance, performance, reliability, and application examples will be shared with the reader. With these three TPG composite products, Momentive has translated our extensive experience and success in thermal management at the system level, with TC1050 Heat Spreaders, to the device level, with TPG Heat Sinks and TPG Laminates.
The Impact of Hydrogen Gas Evolution on Blister Formation in Electroless Copper Films
Authors: Bernhard Tobias , Brüning Frank , Brüning Ralf , Sharma Tanu , Brown Delilah , Zarwell Sebastian , Bishop Craig
Published: October 2015

Electroless copper plating is a key process to provide electrically conductive layers on insulating substrates for the subsequent copper electroplating of printed circuit boards (PCBs). Recently introduced substrate materials are prone to spontaneous delamination failure (blistering) of the electroless layer during deposi-tion. A higher nickel content in electroless copper baths prevents delamination failure by increasing the internal tensile stress in the copper layer. This effect is achieved by suppressing copper self-diffusion through the incorporation of small amounts of nickel in the grain boundaries and the grain boundary junc-tions. Whether the hydrogen gas that evolves inevitably during electroless copper deposition, and that is potentially trapped in the deposit may cause blistering is still under debate. Here we test this hypothesis by quantifying the generated hydrogen gas volume during copper deposition in baths with nickel concentra-tions between 0 and 1000 ppm, and observing the rate of blister formation in the deposit. We find a con-stant molar ratio of 0.65±0.05 mol H2/mol Cu independent of the nickel content in the bath, in contrast to a systematic and substantial change of the blister probability. From this lack of a correlation between the blister rate and hydrogen evolution, we rule out hydrogen evolution as a determining factor for blister for-mation.
Fast Etching of Microscale Structures by Bombardment with Electrosprayed Nanodroplets
Authors: Grustan-Gutierrez Enric , Borrajo-Pelaez Rafael , Gamero-Castaño Manuel
Published: October 2015

In this article Si substrates protected by Shipley 1827 and Au masks are sputtered with electrosprayed nanodroplets to produce microscale structures. Silicon is used as a benchmark to assess the effect of the physical sputtering of nanodroplets on more interesting chemically inert materials such as SiC and GaN.

The use of Shipley 1827 as a patterning mask provides a virtually infinite etching selectivity between substrate and photoresist at the cost of non-perpendicular wall profiles and debris redeposition. After 60 minutes of processing the target at a sputtering rate of 244 nm/min, a fraction of the sputtered material deposits back on the substrate forming a protective layer that stops any further sputtering.

In a second set of experiments the selectivity between Si and Au to be used as a potential mask is studied. The maximum selectivity is 64.17, and is obtained at an etching rate of 385 nm/min. An increase of the etching rate produces a sharp drop on the selectivity between Au and Si.
Effects on the Reliability of Lead-Free Solder Joints under Harsh Environment
Authors: Hai Zhou , Zhang Jiawei , Shen Chaobo , Zhao Cong , Evans John L. , Bozack. Micheal. J.
Published: October 2015

Pb-free solder joints undergo microstructural and mechanical evolution due to alloy coarsening and growing intermetallic compounds which degrade the joint electrical performance. Electronics assemblies containing solder joints are frequently exposed to elevated temperatures for prolonged periods of time. The purpose of the study is to discover the effect of isothermal aging on the reliability of Sn-Ag-Cu (SAC) assemblies. After studied different surface finishes, we employed Immersion Ag (ImAg), Immersion Sn (ImSn), Electroless Ni/Immersion Au (ENIG) and Electroless Ni/Electroless Pd/Immersion Au (ENEPIG) which have potential for higher reliability and better performance and received increased attention for both packaging and subtracted applications. A full experiment matrix with varying aging temperatures and solder alloys was considered. Package sizes ranged from 19mm, 0.8mm pitch ball grid arrays (BGAs) to 5mm, 0.4mm pitch μBGAs and in additional, 0.65mm MLF and 2512 resistors be particularly tested. Storage condition are temperatures leveling up from 25°C, 55°C, 85°C, 100°C and 125 °C with aging over time periods of 0, 21 days, 6 months, 12 months and 24 months. Afterwards, the specimens all subjected to accelerated thermally cycled from −40°C to 125°C with 15 min dwell times at the high and low peak temperature. The paper presents the experimental data to justify the investigation of the degradation on the characteristic lifetime of SAC alloy on ImAg and ImSn surface finish in elevated temperature environments.