bluuebunny/crossref_metadata_2025 huggingface dataset:
Recent Progress and Challenges in Enabling Embedded Si:C Technology
Authors: Yang B F. , Ren Zhibin , Takalkar Rohit , Black Linda R. , Dube Abhishek , Weijtmans J. W. , Li John , Chan K , Souza J P de , Madan Anita , Xia G. , Zhu Zhengmao , Faltermeier J. , Reznicek A. , Adam Thomas N. , Chakravarti Ashima , Pei G , Pal Rohit , Yang B , Harley Eric C. , Greene B , Gehring A , Cai M , Sadana D , Park D , Mocuta D , Schepis Dominic J. , Maciejewski E , Luning S , Leobandung E
Published: October 2008

This paper discusses the fundamental challenges and reports the recent progress in enabling embedded Si:C (eSi:C) nMOS source/drain stressor technology. A thick oxide (SiON, Toxgl ~ 26Aå) long channel (Lgate in the range of 80nm-110nm, gate-pitch =336nm) nMOS device was used as the main test structure to evaluate the impact of eSi:C stressor to the device electrical characteristics, such as channel mobility and drive current. It was demonstrated that modifying the conventional Si CMOS fabrication process to accommodate the intrinsically meta-stable eSi:C material property is crucial in keeping carbon in its substitutional site thus to preserve strain in the eSi:C stressor throughout the device fabrication process. Significant channel mobility and drive current enhancement was demonstrated in the thick-oxide long-channel nMOS devices using in situ phosphorus-doped (ISPD) epitaxial eSi:C source/drain material.
The Impact of Carbon on the Warpage of e-SiGe Wafers During Laser Anneal
Authors: Riley Deborah J. , Bu Haowen , Jain Amitabh , Khamankar Rajesh
Published: October 2008

When wafers with embedded SiGe (e-SiGe) are laser annealed, serious wafer warpage can result. This warpage will lead to registration error when patterning is attempted to create contacts, and can make subsequent processing of the wafers impossible. If relatively low levels of carbon are introduced into the SiGe prior to laser anneal, wafer warpage is reduced. Carbon can be introduced through implantation or by co-deposition during the epitaxial growth of the SiGe. This paper illustrates the impact that laser anneal has on e-SiGe wafers, and explores the impact of carbon on these effects. Mechanisms by which carbon influences warpage are discussed, and the manufacturing impact of this introduction is reviewed. Finally, species other than carbon are examined for their ability to modify wafer warpage in laser annealed e-SiGe wafers.
Growth and Thermal Stability of SiGe/Si Superlattices on Bulk Si Wafers
Authors: Hartmann Jean-Michel , Papon Anne-Marie , Colonna Jean-Philippe , Ernst Thomas , Billon Thierry
Published: October 2008

Deals with (i) the growth and thermal stability of large number or periods SiGe/Si superlattices on bulk Si and (ii) the impact of B and P doping and of C alloying of SiGe on the growth kinetics of SiGe/Si superlattices.
Simultaneous Optimization of the Material Properties, Uniformity and Deposition Rate of Polycrystalline CVD and PECVD Silicon-Germanium Layers for MEMS Applications
Authors: Bryce George , Severi Simone , Du Bois Bert , Willegems Myriam , Claes Gert , Van Hoof Rita , Haspeslagh Luc , Decoutere Stefaan , Witvrouw Ann
Published: October 2008

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work an optimized process to deposit high quality crystalline poly-SiGe layers with low stress, low strain gradient and good within-wafer uniformity at a manufacturable throughput is developed. The process used to deposit the layers is based on a combination of CVD and PECVD SiGe depositions. Firstly, the CVD SiGe process has been extensively characterized to the extent that the influence of thickness, Ge concentration and B concentration on film stress and strain gradient is now well understood. Then the interaction between the PECVD SiGe and the underlying CVD layer has been investigated. This combined knowledge enables specific tailoring of the CVD-PECVD SiGe stack to give the desired strain gradient for a certain layer thickness.
Integrating Selective Epitaxy in Advanced Logic & Memory Devices
Authors: Kuppurao Satheesh , Kim Yihwan , Cho Yonah , Chopra Saurabh , Ye Zhiyuan , Sanchez Errol , Chu Schubert
Published: October 2008

In this paper, we review integration of selective epitaxy in advanced logic and memory devices. Embedded SiGe epitaxy has been adapted for logic pMOSFET fabrication from the 90 nm technology node and device performance continues to scale with higher [Ge] in the epitaxial SiGe layer. For nMOSFET performance boost, use of embedded silicon carbon (Si:C) epitaxial layer has been considered. Recent improvements in crystal quality of selective in-situ phosphorus doped Si:C epitaxy enables significant transistor drive current increase. For integration of Si:C epitaxy, effect of various thermal annealing processes on substitutional carbon incorporation and NiSi formation on Si:C epitaxy are described. Also, heavy phosphorus doping in Si and Si:C layers is discussed in terms of film resistivity and strain contribution. Selective epitaxy is being used to form elevated source/drain in DRAM memory devices where it provides immunity against short channel effects and results in improved retention time.
Etch Rates of Ge, GaAs and InGaAs in Acids, Bases and Peroxide Based Mixtures
Authors: Sioncke Sonja , Brunco David P. , Meuris Marc , Uwamahoro Olivier , Van Steenbergen Jan , Vrancken Evi , Heyns Marc M.
Published: October 2008

Si has dominated semiconductor industry for decades. However, new materials are appearing in this field such as Ge, GaAs and InxGa1-xAs. In semiconductor processing several wet chemical steps are used including cleaning, etching and stripping. Knowledge of etch rates in these solutions is of great importance. In this paper, an etch rate study was performed for Ge, GaAs and InxGa1-xAs in several wet chemical cleaning solutions. The chemistries studied include acids (HCl, HF, HNO3, H2SO4, H3PO4, H2O2) and bases (NH4OH) and peroxide based mixtures. It has been found that etch rates are much higher than for Si due to the formation of soluble oxides. Therefore, "fine-tuning" of the chemistries is a prerequiste when introducing these materials in microelectronic industry.
Selective Epitaxial Growth of Si(Ge) for High Performance MOSFET Applications
Authors: Mizushima Ichiro
Published: October 2008

Selective epitaxial growth of Si and SiGe films has been applied to the fabrication of many high-performance MOSFETs, because new device structures can be realized by selective epitaxial growth. Selective growth of Si(Ge) at the source/drain region is the most well-known example. Precise control of the selective epitaxial process enables the best performance with the desired structure. Control of the selectivity is also important for a robust manufacturing process. Selective epitaxial growth is essential for next-generation MOSFETs, such as FinFETs. Innovation of selective epitaxial growth will spur the continuous progress of MOSFETs.
SiGe Selective Epitaxy: Morphology and Thickness Control for High Performance CMOS Technology
Authors: Holt Judson R. , Harley Eric C. , Adam Thomas N. , Jeng Shwu-Jen , Tabakman Keith , Pal Rohit , Nayfeh Hasan M. , Black Linda R. , Kempisty Jeremy J. , Stoker Matthew W. , Dube Abhishek , Schepis Dominic J.
Published: October 2008

Embedded SiGe (eSiGe) has become a widely used method to enhance device performance. The key step in this process is the selective epitaxial growth of a SiGe film in the source/drain region of the transistor. In the present study, we describe how the epitaxial growth may be controlled on multiple levels. On a microscopic level, the morphology is a function of the process conditions and the structure in which the epitaxial film is grown. On a macroscopic level, the loading effect can be characterized by a simple empirical model based on gas phase reactant depletion. Finally, on a global level, the within-wafer thickness variation can be controlled by temperature-based uniformity tuning, and the run-to-run growth rate drift can be controlled by an advanced process control (APC) feedback loop.
Vapor Phase Doping with N-type Dopant into Silicon by Atmospheric Pressure Chemical Vapor Deposition
Authors: Takeuchi Shotaro , Nguyen Ngoc D. , Leys Frederik E. , Loo Roger , Conard Thierry , Vandervorst Wilfried , Caymax Matty
Published: October 2008

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si-cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.
Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates
Authors: Malm B G. , Hallstedt Julius , Hellström Per-Erik , Ostling Mikael
Published: October 2008

It was found that for strained Si channel layers of supercritical thickness on relaxed SiGe virtual substrates, the 1/f noise on average is maintained at the same level as in unstrained devices. Short gate length nMOSFETs were analyzed statistically and the noise level variation, across a large number of samples, was similar in strained and unstrained devices. The obtained noise level variation was partly related to gate length fluctuations across the wafer, which was evident from a small VT fluctuation.
Epitaxial Growth of Ge Thick Layers on Nominal and 6oC off Si(001); Ge Surface Passivation by Si
Authors: Hartmann Jean-Michel , Grampeix Helen , Clavelier Laurent
Published: October 2008

In the first part of this paper, we have quantified the surface roughness, the degree of strain relaxation and the defect density in thick Ge layers grown using a low temperature / high temperature approach on nominal and 6oC off (towards one of the <110> directions) Si(001) substrates. In the second part, we have succinctly described the Si passivation process we use on Ge prior to gate stack formation in order to obtain high performance p-type metal oxide semiconductor field effect transistors.
High-speed, Monolithic CMOS Receivers with Ge on Si Waveguide Photodetectors
Authors: Masini Gianlorenzo , Sahni Subal , Analui Behnam , Capellini Giovanni , Witzens Jeremy , Gunn Cary
Published: October 2008

This paper describes Luxtera's approach to the monolithic integration of Germanium photodetectors with CMOS electronics for high speed optical transceivers. Insertion of the Germanium module into a CMOS process and its impact on the design of the detectors is discussed. The deployment of the devices in 4x10 Gbps receivers is also described, wherein an optical sensitivity of - 19 dBm for a bit error rate of 1e-12 is demonstrated. The optimization of the transimpedance amplifier to take advantage of the reduced capacitance (<20fF) of the waveguide detectors is also discussed.
A Multiscale Model of The Low-Temperature CVD of Silicon
Authors: Cavallotti Carlo , Barbato Alessandro
Published: October 2008

Among the semiconductor materials, silicon stands out for its technological, industrial, and scientific relevance. Its growth process has been widely studied, theoretically and experimentally, so that it's surface and gas phase kinetics are mostly known. In this work this knowledge was exploited to develop a 3D Kinetic Monte Carlo model that, combined consistently with a detailed fluid dynamic analysis of a CVD reactor and ab initio simulations of relevant surface processes, was used to investigate the surface and gas phase dynamics active during the film growth. The proposed mathematical model is thus able to link information coming from the atomic scale, such as the diffusion of hydrogen and silicon adatoms and dimers, with the surface microstructural evolution (density and shape of islands), and, finally, with the reactor operating parameters, such as pressure, temperature and gas phase composition.
Ab-initio Simulation of Formation and Diffusion Energies of Intrinsic Point Defects in Ge
Authors: Spiewak Piotr , Vanhellemont Jan , Sueoka Koji , Kurzydlowski Krzysztof , Romandic Igor
Published: October 2008

Density functional theory with local density approximation including on-site Coulomb interaction has been used to calculate the formation and migration energy of the neutral and charged vacancy and self-interstitial in germanium.
Atomic Layer Deposition of High-k Dielectric Layers on Ge and III-V MOS Channels
Authors: Delabie Annelies , Alian A. , Bellenger Florence , Brammertz Guy , Brunco David P. , Caymax Matty , Conard Thierry , Franquet A. , Houssa Michel , Sioncke Sonja , Van Elshocht S. , Van Hemmen J. L. , Keuning W. , Kessels W. M. , Avanasiev Valery , Stesmans Andre , Heyns Marc M. , Meuris Marc
Published: October 2008

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied Atomic Layer Deposition (ALD) of high-k dielectric layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidation in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidation states lower than 4+. Still, electrical results indicate that small amounts of Ge in oxidation states lower than 4+ are not detrimental for device performance. Partial intermixing was observed for high-k dielectric and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates.
Interface and Defect Control for Group IV Channel Engineering
Authors: Sakai Akira , Ohara Yuji , Ueda Takaya , Toyada Eiji , Izunome Koji , Takeuchi Shotaro , Shimura Yosuke , Nakatsuka Osamu , Ogawa Masaki , Zaima Shigeaki , Kimura Shigeru
Published: October 2008

New structures and materials alternative to conventional bulk-Si(001) substrates are now under consideration for their application to CMOS channel layers on a Si platform. However, mismatch of lattice parameter between the alternative channel material and the Si substrate inevitably causes defect introduction which is one of crucial issues when implementing the formation of channels on Si. In this work, we perform interface and defect engineering for group IV semiconductor materials; Si with hybrid crystal orientation, Ge, and Sn. Engineered channel crystals formed with the wafer direct bonding and heteroepitaxy technologies are characterized in terms of crystalline quality and strain.
Prospects for Top-Down Fabricated Uniaxial Strained Nanowire MOSFETs
Authors: Hoyt Judy , Hashemi Pouya , Gomez Leonardo
Published: October 2008

Multi-gate and "Gate-all-around" (GAA) MOSFETs are attractive for deeply-scaled CMOS as their geometry improves electrostatic control, which promises enhanced scalability, and enables lower channel doping, reducing random dopant fluctuations which are a significant source of variation for scaled bulk planar CMOS. Performance boosters such as the use of strain and alternate channel materials to improve carrier transport are essential for future CMOS technologies. In this evening panel discussion we present prospects and challenges for top-down fabricated uniaxial strained nanowire MOSFETs.
Novel Metal-Germinade Schottky Barrier Contacts for Si-Photonics Application
Authors: Lo Guo-Qiang P. , Ang Kah-Wee , Yu Mingbin , Kwong Dim-Lee
Published: October 2008

To reap the full benefits of superior transport and optical properties of germanium, a low-resistance metal-germanides contact that is compatible with existing Si CMOS process technology would be highly desirable. In this abstract, we report the developments of nickel-germanide (NiGe) contact technology and its combination with Schottky barrier engineering techniques (e. g., dopants and valence-mending absorbate segregations) for contact resistance improvement. In addition, we explore the application of these techniques in NiGe Schottky barrier metal-Ge-metal (MSM) photodetector for low dark current and high speed photodetection applications, such as through Si:C (Metal direct contact on Ge) or Sincorporation (for NiGe). Sulfur is used as example in the valencenmending absorbate scheme in this work. In both cases, significant suppression of dark current (~103 to 104 ×) was observed, with the enhanced hole Schottky barrier heights to 0.49eV (S-incorporated) or 0.52eV (thin Si:C layer). In both surface-illuminated and waveguided schemes, 12-15GHz speed were obtained with 1V operating bias.
Very High-k Tetragonal ZrO2 on Ge with GeO2 Passivating Interfacial Layer
Authors: Tsipas Polychronis , Mavrou Georgia , Volkos Stelios N , Sotiropoulos Andreas , Galata Sotiria , Panayiotatos Yerassimos , Dimoulas Athanasios
Published: October 2008

Passivation of Ge surface is the biggest challenge in the effort to develop Ge MOS technology. We present ZrO2 on Ge with GeO2 passivating interfacial layer prepared by atomic oxygen beam deposition. Electrical data show that ZrO2 has a high-k value around ~44, indicative of tetragonal phase crystallization. This is also supported by x-ray diffraction data. The dielectric permittivity of GeO2 interfacial layer was estimated about ~4.9, which is very close to the lowest boundary for stoichiometric GeO2 reported in literature.
Why and How Atom Intermixing Proceeds at Metal/Si Interfaces; Silicide Formation vs. Random Mixing
Authors: Nakayama Takashi , Shinji Sho , Sotome Shinichi
Published: October 2008

Atom intermixing at metal/semiconductor interfaces is studied using the first-principles theoretical calculations. In this paper, by demonstrating atom-diffusion potentials and electronic structures of Au/Si, Al/Si, Au/GaN, Au/HfO2, Ni_xSi_y/Si and Au_xSi_y/Si systems, we answer various elementary questions concerning to the intermixing; what is the motive force of intermixing, how the intermixing proceeds, what are relevant factors to prevent the intermixing, what origins distinguish silicide formation from random alloying, why the silicide stoichiometry is limited on Si substrate, and how and why the Schottky barrier changes with varying the silicide stoichiometry.
Chemical Vapor Deposition Epitaxy of Silicon-based Materials using Neopentasilane
Authors: Sturm James C. , Chung Keith H.
Published: October 2008

Neopentasilane (Si5H12) has been used as a precursor for the chemical vapor deposition epitaxy of silicon and Si1-yCy alloys at temperatures from 550 to 700 oC. This paper summarizes the experimental findings of high growth rates of high quality epitaxy and planar films and then proposes mechanisms to support these observations. Concerted mechanisms, which can lead to growth without the usual requirement of open sites on an otherwise hydrogen covered surface are described as they relate to high -order silanes.
Selective Epitaxial Growth of Germanium on Si Wafers with Shallow Trench Isolation: An Approach for Ge Virtual Substrates
Authors: Wang Gang , Leys Frederik E. , Souriau Laurent , Loo Roger , Caymax Matty , Brunco David P. , Geypen Jef , Bender Hugo , Meuris Marc , Vandervorst Wilfried , Heyns Marc M.
Published: October 2008

Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.
Selective Epitaxial Growth of Ge-on-Si for Photodiode Applications
Authors: Kim Meekyung , Olubuyide Oluwamuyiwa , Yoon Jung , Hoyt Judy
Published: October 2008

The goal of this work is to study and optimize the growth parameters for Ge-on-Si for photodiodes operating at 1.55 um. Approximately 1 um-thick, relaxed Ge is grown in exposed Si regions on oxide-patterned Si wafers. Germanium selectivity, faceting, morphology, and threading dislocation density are investigated as a function of growth and processing conditions. Ge faceting was reduced by increasing the growth temperature and germane partial pressure, and at the optimized growth condition of 750{degree sign}C and 10T, an RMS surface roughness of 1.3 nm was obtained for 10 x 10 um AFM scans. Threading dislocation density was reduced for structures smaller than 5 um, but the dislocation density depends on post-growth annealing conditions and Ge film thickness.
Ge Quantum Well Modulators on Si
Authors: Miller David , Schaevitz R. K. , Roth J. E. , Ren Shen , Fidaner Onur
Published: October 2008

We discuss the physics and device structures of optical modulators using germanium quantum wells grown on silicon substrates. These exploit the recently discovered strong electroabsorption mechanism in such wells, and promise high performance optical modulators on silicon.
Si/SiGe Bound-to-Continuum Quantum Cascade Emitters
Authors: Paul Douglas J. , Matmon Guy , Lever Leon , Ikonic Zoran , Kelsall Robert , Chrastina Daniel , Isella Giovanni , Von Känel Hans , Müller Elisabeth , Neels Antonia
Published: October 2008

Si/SiGe bound-to-continuum quantum cascade emitters designed by self-consistent 6-band k.p modeling and grown by low energy plasma enhanced chemical vapour deposition are presented demonstrating electroluminescence between 1.5 and 3 THz. The electroluminescence is Stark shifted by an electric field and demonstrates polarized emission consistent with the design. Transmission electron microscopy and x-ray diffraction are also presented to characterize the thick heterolayer structure.
High Ge Content SiGe alloys: Doping and Contact Formation
Authors: Kasper Erich , Oehme Michael , Lupaca-Schomber Jaime
Published: October 2008

High Ge content SiGe alloys or pure Ge are essential components of future microelectronics (high performance p-channels) and optoelectronics/microelectronics (on-chip and chip to chip communication) integration scenarios. The successful integration with Si based circuits requires process compatibility. Here we report specifically on recent results with high n and p doping of Ge and contact formation with Al and silicide/germanide metals. Highly Sb and B doped epitaxial layers (/cm3) are grown at low temperatures (< 400oC) and complete electrical activation of dopants is proven by SIMS and TLM measurements. Metal contacts on p-Ge are easily fabricated as Ohmic ones, whereas n-Ge contacts are more critical. We explain this by the Fermi level pinning near the valence band, and the strong influence of thin interface layers on the strength of Fermi level pinning.
New Heating Method for Polycrystallization of Amorphous Si Using Microwave Plasma Irradiation
Authors: Nakagawa Kiyokazu
Published: October 2008

We have found a phenomenon that the metal is heated up to 1150° by exposure to the hydrogen microwave plasma. It is thought that the heating is caused by the relief of the binding energy when the hydrogen atoms recombine and make molecules on the metal surface. For device application, Ni was deposited on a source area of a FET, and the activation of the implanted atoms and poly-crystallization of the channel area were performed at the same time by using this method, and the fabricated TFT shows good I-V characteristics.
Low Temperature Boron Activation in Amorphous Germanium for Three Dimensional Integrated Circuits (3D-ICs) using Ni-induced Crystallization
Authors: Park Jin-Hong , Tada Munehiro , Yu Hyun-Yong , Kuzum Duygu , Na Yeul , Saraswat Krishna
Published: October 2008

In this work, we present very low temperature boron activation technique in amorphous (α)-Ge using Ni-induced crystallization. Ni not only successfully crystallize α-Ge film, it also facilitates activation of the respective boron atoms in the α-Ge during the crystallization process at temperatures as low as 360ºC. The feasibility of the low temperature activation technique has successfully been demonstrated for a Ge gate electrode in a Si P-MOSFET using Schottky Ni silicide source/drain.
Dry Etch Challenges in Gate All Around Devices for sub 32 nm Applications
Authors: Barnola Sebastien , Vizioz Christian , Vulliet Nathalie , Dupré Cécilia , Ernst Thomas , Gautier Pauline , Arvet Christian , Guillaumot Bernard , Bernard Emilie , Pauliac-Vaujeour S. , Comboroure Corine , Hartmann Jean-Michel , Borel Stephan , Chevolleau Thierry , Maffini-Alvaro V , Becu S
Published: October 2008

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.
Spin-Polarized Electron Transport in Silicon
Authors: Appelbaum Ian
Published: October 2008

Spin transport in semiconductors holds promise for beyond-CMOS logic processing because the orientation of spin (coupled to the electron's intrinsic magnetic moment) can encode a binary state. However, the experimental difficulties of achieving coherent spin-polarized electron transport in the most prevalent semiconductor, Silicon, were overcome for the first time only recently. I will present our solution to this long-standing problem, including observations of exceptionally long spin lifetimes and transit lengths, which confirms Silicon's status as the ideal semiconductor for spintronics.
SiGe Tunnel Field Effect Transistors
Authors: Eisele Ignaz , Lochner Helmut , Schlosser Martin
Published: October 2008

For conventional MOSFETs band-to-band tunnelling has to be avoided because it causes unintentional leakage currents. On the other hand the Tunnel FET, which basically consists of a gated pin-diode, takes advantage of tunnelling. The influence of technological parameters on device performance as well as scaling rules will be discussed. Finally it will be shown that band gap engineering with SiGe and the incorporation of high-k dielectrics strongly improve current slope and maximum ON current. A future device performance comparable or even better than the conventional MOSFET is predicted.
SiCP Selective Epitaxial Growth in Recessed Source/Drain Regions yielding to Drive Current Enhancement in n-channel MOSFET
Authors: Bauer Matthias , Machkaoutsan Vladimir , Zhang Yangting , Weeks Doran , Spear Jennifer , Thomas Shawn , Verheyen Peter , Kerner C. , Clemente F. , Bender Hugo , Shamiryan D. , Loo Roger , Hikavyy A. , Hoffmann T. , Absil Philipe , Biesemans Serge
Published: October 2008

In this paper we demonstrate the successful integration of in-situ doped embedded Si:C stressors epitaxially grown in the source and drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process. These layers have substitutional C content ranging between 1% and 2% with potential of achieving even higher substitutional carbon concentration. Another distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We demonstrate superior performance of strained nMOS devices with embedded Si:C showing up to 12.5% on-state current improvement over the unstrained reference process. We report on material characterization results of embedded Si:C stressors, in particular, strain retention properties as a function of subsequent post-epitaxy processing.
Monolithic III-V/Si Integration
Authors: Fitzgerald Eugene A. , Bulsara M. T. , Bai Y. , Cheng C. , Liu W. K. , Lubyshev D. , Fastenau J. M. , Wu Y. , Urtega M. , Ha W. , Bergman J. , Brar B. , Drazek C. , Daval N , Leterte F. , Hoke W. E. , LaRoche J. R. , Herrick Katherine J. , Kazior T. E.
Published: October 2008

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.
Strain Loss in Epitaxial Si:C Films Induced by Phosphorus Diffusion
Authors: Yang Bin , De Souza Joel , Saenger Katherine , Bedell Steve , Reznicek A. , Adam Thomas N. , Hopstaken Marinus , Sadana D
Published: October 2008

The influence of P diffusion on the thermal stability of epitaxial Si:C films has been studied. P diffusion is shown to greatly contribute to the strain loss in epitaxial Si:C films. It is proposed that the strain loss is mainly caused by the interaction of Si interstitial atoms injected by P diffusion with substitutional C atoms, driving them to non-substitutional lattice sites.
Ge Interface Passivation Techniques and Their Thermal Stability
Authors: Kuzum Duygu , Krishnamohan Tejas , Pethe Abhijit , Oshima Yasuhiro , Sun Yun , McVittie James , McIntyre Paul , Pianetta Piero , Saraswat Krishna
Published: October 2008

Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this work, we introduce ozone-oxidation and low temperature plasma nitridation to engineer Ge/insulator interface. Density of interface states (Dit) across the bandgap and close to conduction band edge was extracted using conductance technique at low temperatures. Electrical qualities of Ge-GeO2 and Ge-GeON interfaces are investigated. Thermal stabilities and desorption pathways of those passivation techniques are investigated through Ge 3d spectra measurements. Low Dit advantage of ozone-oxidation technique is combined with thermal stability provided by plasma nitridation.
Solid-Phase Epitaxial Regrowth of Phosphorus Implanted Amorphized Germanium
Authors: Simoen Eddy R. , Brugere Antoine , Satta Alessandra , Van Daele Benny , Brijs Bert , Richard Olivier , Geypen Jan , Meuris Marc , Vandervorst Wilfried
Published: October 2008

This paper reports on the Solid Phase Epitaxial Regrowth (SPER) of phosphorus implanted pre-amorphized p-type germanium at 350 oC using Rapid Thermal Annealing and focuses more specifically on the P concentration dependence of the regrowth velocity. This is studied by a combination of Rutherford Backscattering in the channeling mode (RBS-C) and Secondary Ion Mass Spectrometry (SIMS). As will be shown, different regimes can be distinguished whereby for chemical concentrations up to 4-5x1020 cm-3 an enhanced recrystallization occurs compared with undoped amorphized Ge. Above this metastable solid solubility limit, the regrowth is retarded, due to the redistribution and snow plow of the excess P across the amorphous/crystalline interface. It will also be demonstrated that during SPER at 350 oC, limited P-diffusion occurs even at the highest implantation dose studied.
SiGe HBT featuring fT > 600GHz at Cryogenic Temperature
Authors: Zerounian Nicolas , Ramirez Garcia Eloy , Aniel Frédéric , Chevalier Pascal , Geynet Boris , Chantre Alain
Published: October 2008

A comparison of electrical performances of state-of-the-art SiGe heterojunction bipolar transistors at low temperature is presented. The performances increase results from the diminution of transit times thanks to the rise of non-stationary transport, the relative increase of the transconductance with the reduction of self-heating effects, and the decrease of access resistances.
3-D Regional Transit Time Analysis of SiGe HBTs on Thin-Film SOI
Authors: Bellini Marco , Cressler J. , Turowski Marek , Avenier Grégory , Chantre Alain , Chevalier Pascal
Published: October 2008

The regional transit time analysis technique is extended from 1-D to 3-D and used to investigate the AC performance of a SiGe HBT-on-SOI fabricated with a novel contact layout. As confirmed by TCAD simulations, the relocation of the base contacts out-of-plane with respect to the emitter and the collector results in a true 3-D current flow. Consequently, AC analysis and optimization cannot be performed with conventional 1-D regional transit time analysis.
Ultra-Low-Power SiGe HBTs using High-Precision RT-CVD Epitaxial Growth
Authors: Oda Katsuya , Miura Makoto , Shimamoto Hiromi , Washio Katsuyoshi
Published: October 2008

A high-precision RT-CVD epitaxial growth technique has been successfully developed for fabricating ultra-low-power SiGe HBTs. Extremely high-concentration doping with abrupt profiles in the Si/SiGe layers was achieved without high-temperature activation annealing. Furthermore, good crystallinity of the grown layer was also achieved, which results in low resistivity. A major advantage of the technique is that SiGe HBTs fabricated using it have high cutoff frequencies at low current density (50 GHz at JC = 0.2 mA/μm2), which makes them highly suitable devices for use in future low-power high-speed communication systems.
Applications of Potential Theory in Cathodic Protection
Authors: Nisancioglu Kemal , Orazem Mark
Published: October 2008

Modern cathodic protection design applications involve the use of the potential theory for estimating the current and potential distribution on complex steel structures immersed in seawater and buried in soil. Solution of Laplace's equation to satisfy nonlinear, time-dependent boundary conditions is achieved by use of Green's third identity, which reduces the problem for the electrolyte volume to that of the structure surface, allowing numerical solution of the surface equation by the boundary element method. The paper summarizes the theoretical background, the numerical approach and case studies for cathodic protection design applications.
Science and Technology for the Development of Electrochemical Industry
Authors: Hine Fumio
Published: October 2008

Electrochemical industry is a chemical process industry, which utilizes electric energy as the driving force for chemical reaction. Electrochemical reaction is a heterogeneous two-dimensional process, i.e., oxidation and reduction of chemical species may take place at the anode and the cathode in contact with electrolyte, respectively. Diaphragms and/or membranes are often utilized to separate the anolyte and the catholyte. Therefore, continuous research and development of these functional materials and utilization are required. Design and operation under optimum conditions are also indispensable.
Mathematical Modeling of Lithium Ion Batteries
Authors: Santhanagopalan Shriram , Long Cai , White R. E.
Published: October 2008

Lithium ion batteries play an increasingly important role as high energy, high-rate power sources for power tools, hybrid electric vehicles, military applications and electronic gadgets. A crucial step in enhancing the performance of these batteries is to understand the performance of the battery under a variety of load conditions. This process is carried out by estimating the state of charge, making life predictions and recommending optimal load sharing in a battery. With an increase in the size of battery packs, performance and safety constraints demand more and more accurate predictions for volatile load profiles. Such demands in turn require expedition of the computational times for the models as well as the estimation techniques. A summary of recent advances in this area is presented here.
Modeling Resistive-Reactant and Phase-Change Materials in Battery Electrodes
Authors: Thomas-Alyea Karen E.
Published: October 2008

Much attention has been paid to a class of lithium-iron-phosphate materials which are coated with a conductive coating to compensate for the low intrinsic conductivity of the LFP. The presence of holes in the conductive coating leads to a nonuniform current distribution around the surface of the particle. This nonuniform current distribution causes a distinctive set of behavior. 1. During galvanostatic discharge or charge, the slope of the voltage vs. coulomb passed is higher for materials with less uniform conductive coating. 2. A Nyquist plot of the ac impedance shows a charge-transfer loop that is semi-circular, with the width of the semicircle being larger for materials with less uniform conductive coating. The behavior of the resistive reactant can be modeled by considering the effect of the distributed ohmic drop as electrons travel from the conductive matrix to react with lithium ions about the surface of the particle.
Hysteresis and Phase Change in Electrochemical Materials
Authors: Meyers Jeremy P.
Published: October 2008

The optimization of electrochemical energy devices can assisted greatly by mathematical modeling; models generally capture a subset of the totality of the phenomena that occur, namely those phenomena which are relevant under the conditions and the timeframe of the period of operation of the device. In order for models to be predictive, however, there must be sufficient information about the conditions under which the cell of interest is operating. It is generally assumed that a simple set of constitutive variables will be sufficient to describe the system, but in many electrochemical systems, multiple phases can exist, which implies that something else about the state of the system must be specified further. If multiple phases are possible, information about the extent and arrangement of those phases must be specified before the model can have predictive capability. In this paper, we examine some common problems and discuss how to describe the system.
Layer-by-Layer Nano Self-Assembly of pH Sensors Based on Polyelectrolytes and Carboxylated Carbon Nanotubes
Authors: Lee Dongjin , Cui Tianhong
Published: October 2008

A new pH sensor using single-walled carbon nanotube (SWNT) multilayers based on layer-by-layer (LbL) self-assembly with polyelectrolytes is presented. SWNTs are functionalized and assembled with polycation, poly(diallyldimethyammonium chloride, PDDA) on the microfabricated metal electrodes. Current-voltage (I-V) characteristics show the conductance of the fabricated SWNT multilayer resistor increases with pH decrease without poly(methyl methacrylate, PMMA) on top of the multilayer as a passivation layer. The SWNT multilayer resistor with PMMA shows increased conductance at higher pH, showing an opposite pH-dependent behavior.
Mechanical Properties of Polycrystalline Silicon formed by Al-2%Si Induced Crystallization
Authors: Lai Joanna , King Liu Tsu-Jae
Published: October 2008

Due to their low thermal process budget, polycrystalline silicon (poly-Si) films formed by Al-2%Si induced crystallization (AIC) are potentially attractive for monolithic integration of MEMS with CMOS electronics using a "MEMS-last" process flow. In this work, the mechanical properties of AIC poly-Si films formed with a maximum substrate temperature of 350C are investigated. Residual stress, Young's modulus, and strain gradient are extracted from pull-in voltage measurements of cantilever and clamped-clamped beams. A post-AIC pulsed excimer laser annealing (ELA) treatment is found to be beneficial for completing the Al-2%Si and Si layer exchange process, although it results in a larger strain gradient within the poly-Si layer. The mechanical properties of AIC poly-Si films compare favorably with those of low-thermal-budget poly-Si0.4Ge0.6 films, so that AIC poly-Si is a promising structural material for MEMS.
Large-Scale Polycrystalline SiC Micromachining Technologies
Authors: Roper Christopher , Howe Roger , Maboudian Roya
Published: October 2008

This work describes two key polycrystalline silicon carbide micromachining technologies, large-scale thin film deposition and room-temperature wet etching. Large-scale deposition of uniform films on 100 and 150 mm diameter wafers is achieved with residual stress under 300 MPa tensile. Electrical resistivity of the deposited films is controlled over seven orders of magnitude. Room temperature wet etching of polycrystalline silicon carbide in the mixed acid solution of 1:1 HF:HNO3 with etch rates as high as 50 Aå/min is achieved. The combination of these techniques yields a large-scale microfabrication method for SiC MEMS for harsh environments.
The Development of Metal Oxide Chemical Sensing Nanostructures
Authors: Hunter G. , Vander Wal R. , Xu J. , Evans L. , Berger G. , Kullis M.
Published: October 2008

This paper discusses sensor development based on metal oxide nanostructures and microsystems technology. While nanostructures such as nanowires show significant potential as enabling materials for chemical sensors, a number of significant technical challenges remain. This paper discusses development to address each of these technical barriers: 1) Improved contact and integration of the nanostructured materials with microsystems in a sensor structure; 2) Control of nanostructure crystallinity to allow control of the detection mechanism; and 3) Widening the range of gases that can be detected by fabricating multiple nanostructured materials. A sensor structure composed of three nanostructured oxides aligned on a single microsensor has been fabricated and tested. Results of this testing are discussed and future development approaches are suggested. It is concluded that while this work lays the foundation for further development, these are the beginning steps towards realization of repeatable, controlled sensor systems using oxide based nanostructures.
Evaluation of Alkyl-chain-length Dependency for Localized Surface Plasmon Resonance Optical Characteristics
Authors: Kawakami Yukari , Endo Tatsuro , Yanagida Yasuko , Hatsuzawa Takeshi , Tamiya Eiichi
Published: October 2008

In this study, the alkyl-chain-length dependency for the localized surface plasmon resonance (LSPR) optical characteristics using core-shell structured nanoparticle layer substrate was evaluated. For evaluation of the LSPR optical characteristics, the self-assembled monolayer (SAM) was formed onto the core-shell structured nanoparticle layer substrate surfaces using thiols. And then the optical characteristics were evaluated. As a result, the optical characteristics change which depends on the alkyl-chain-length could be observed.
Li[Ni1/3Mn1/3Co1/3]O2-based Electrodes for PHEV Applications: An Optimization
Authors: Zheng Honghe , Liu Gao , Song Xiangyun , Battaglia Vince
Published: October 2008

Li[Ni1/3Mn1/3Co1/3]O2 cathodes of approximately the same loading of active material with different amounts of inactive materials were fabricated and calendared to different porosity. EV and HPPC tests revealed that Li[Ni1/3Mn1/3Co1/3]O2 cathode performance is a strong function of inactive material amount and porosity with respect to energy density, pulse power, and cycling capability. Li[Ni1/3Mn1/3Co1/3]O2 laminates containing 2% PVdF and 1.6% acetylene black at 30% porosity exhibits the best overall electrochemical properties including energy density, pulse power, and cycleability. Combined with an MCMB anode, the full cell delivers an energy density of 520 Wh/L which well exceeds the 40-mile energy-density goal announced by FreedomCar of 207 Wh/L. The result illustrates that proper engineering of the cell, module, and pack design may meet the PHEV 40-mile goal.
Li/CFx Medical Battery Development
Authors: Zhu Hui Jian , Gavril Marcela , Feng Li , Karpinet Daniela
Published: October 2008

Eagle Picher Medical Power (EPMP) is engaged in the development of high energy density and specific energy, light weight battery for medical applications. The paper will present electrical performance data of a Li/CFx cell developed for low current applications. Rate capability data, impedance spectroscopy and microcalorimetry data will be presented. The influence of carbon additives on battery performance will also be described.
Cathode Extenders as Capacity Enhancers in Alkaline EMD Cells
Authors: Bushong William C. , Davidson Greg , Destephen Mario , Jin Zhihong , Mortensen Erik , Ndzebet Ernest , Ramaswami Karthik , Vu Viet , Boone David , Gilbert Deb
Published: October 2008

Significant increases in cathode discharge efficiency and capacity provide overall cell capacity increases to alkaline EMD cells when cathode extender materials with high volumetric and gravimetric energy densities, such as CuO, are used. This secondary cathodic metal oxide is added to the cathode compartment of an EMD alkaline cell to provide a simple and low cost means to extend the discharge performance of the cell. Use of such a compatible metal oxide as a cathode extender material in combination with improved cell balancing and design increases the utilization of the MnO2.
Study on Synthesizing a Novel Sn/MC Composite as Anode Material in Lithium-ion Battery
Authors: Wang Hongqian , Yan Zhixiong , Li Qingyu , Yang Jianhong , Huang Youguo
Published: October 2008

A novel process was proposed to prepare Sn/mesophase carbon(Sn/MC) composite anode material for lithium-ion battery for the first time. The Sn/MC composite was successfully prepared by dispersing Sn(OH)4 in coal tar picth, followed by polymerization, carbonization and carbothermal reduction in an inert atmosphere. X-ray diffraction(XRD), scanning electron microscopy(SEM) and transmission electron microscopy(TEM) were employed to determine the structure and configuration. The results show that the metallic Sn was encapsulated within the carbon matrix uniformity by carbothermal reduction. The electrochemical performance was examined. It exhibits a stable capacity of 400 mAh g-1 after 60 cycles and the first reversible capacity was as high as 600 mAh g-1 , showing excellent cycle performance and higher capacity. The proposed process paves an effective way to prepare high-performance and higher capacity Sn/C composite anode material for lithium-ion battery.
Multifunctional Properties of Structural Gel Electrolytes
Authors: Nguyen Phuong-Anh T. , Snyder James
Published: October 2008

Multifunctional structural gel electrolytes were prepared by the integration of conductive pathways using non-aqueous solvents into structural resin networks. Poly(ethylene) glycol (200 MW) and propylene carbonate were used as non-aqueous solvents while vinyl ester and epoxy resin were used as structural resins. The monomer and solvents were incorporated together and polymerized to create conductive pathways in crosslinked networks. The impact of chemistry and weight fraction of both liquid and resin were investigated on the electrochemical-mechanical response of the resulting system. The addition of liquid solvent generally improves the performance of electrochemical properties relative to solid state polymer electrolytes, although at the expense of mechanical robustness. Crosslinking the polymer matrix is employed to improve mechanical performance. The ionic conductivity and compressive modulus were measured by AC impedance and compression respectively. Dynamic Mechanical Analysis was utilized to validate the processing conditions and material characterization.