bluuebunny/crossref_metadata_2025 huggingface dataset:
Zoom in on Life: Using Biological Processes to Teach the Public about Nanotechnology
Authors: Wade Maya , Tinker Beth , Greenberg Andrew , Redwing Ronald Dean
Published: April 2011

Through a partnership between the NSF-funded Material Research Science and Engineering Center, Center for Nanoscale Science, at Penn State University and Philadelphia's science museum The Franklin Institute the "Nano-Bio: Zoom in on Life!" program has been produced and distributed to 20 science and children museums in the United States and one science museum in Canada. Distributed shows include the materials needed to perform the demonstration, supplies for a year and additional information including educational materials and a training video. This cart based program includes interactive demonstrations that highlight processes in the human body that occur at the nanoscale and how scientists are exploring natural processes to develop new nanotechnology and nanomaterials. This show is the second in a series of collaborations to create programs for the informal science education world. A development team including Penn State University faculty, postdoctoral fellows, graduate students and Franklin Institute staff worked over two years to develop the show. Instrumental in the development were graduate students who were part of a jointly run Penn State-Franklin Institute NSF-funded Internships in Public Science Education (IPSE) program. These science education graduate students helped create, test, and enhance the demonstrations for the Zoom in on Life program.
Scanning Force Microscopy in the Classroom
Authors: Zypman Fredy
Published: April 2011

We describe a strategy to efficiently introduce concepts of scanning force microscopy in introductory science and engineering classes. Particular emphasis is placed in qualitative understanding via intuition building with numerical trial and error. In addition, model development is introduced and used to perform quantitative predictions of force-separation curves.
Electronic Characterization and Light-Induced Degradation in nc-Si:H Solar Cells
Authors: Hugger P. G. , Datta Shouvik , Erslev P. T. , Yue Guozhen , Ganguly Gautam , Yan Baojie , Yang Jeffrey , Guha Subhendu , Cohen J. D.
Published: April 2011

The electronic properties of working nanocrystalline silicon (nc-Si:H) solar cell devices with conversion efficiencies up to 8.6% were studied using junction capacitance methods. The set of devices examined were deposited on both specular stainless steel substrates and Ag/ZnO textured back reflectors. These devices included nc-Si:H grown under constant H2 dilution, and also with profiled H2 dilution to control the crystallite sizes and volume fraction. Transient photocapacitance and transient photocurrent spectroscopies were used to obtain sub-band-gap optical spectra. A comparison of these two kinds of spectra also allowed us to deduce the minority carrier collection fractions as a function of temperature and light-induced degradation. Light-soaking was found to cause a distinct decrease in minority carrier collection, as well as a consistent decrease in defects responding to drive-level capacitance profiling. A tentative microscopic model is proposed that accounts for these degradation effects in nc-Si:H.
Surface Roughening Transition in Si1-xGex:H Thin Films
Authors: Podraza Nikolas J. , Wronski Christopher R. , Horn Mark W. , Collins Robert W.
Published: April 2011

In this study, the amorphous-phase roughening transition thickness has been determined as a function of process variables in plasma-enhanced chemical vapor deposition (PECVD) of hydrogenated amorphous silicon-germanium alloys (a Si1-xGex:H). Among the process variables include the H2-dilution gas flow ratio, the alloying flow ratio, the electrode configuration (anode vs. cathode), and the He-dilution ratio. One clear feature of this study is a maximum in the amorphous roughening transition thickness (and hence surface stability) at a H2-dilution ratio just below the transition from amorphous to mixed-phase (amorphous+microcrystalline) (a+μc) growth. A second feature for high Ge content films is a significant increase in the roughening transition thickness for cathode PECVD (with a self-bias of ~ −20 V) relative to anode PECVD. Additional features of interest involve suppression of the mixed-phase transition to (a+μc) for (i) alloying with Ge, (ii) cathodic substrate biasing, and (iii) diluting the gas with He. The close correlation of high surface stability with enhanced short-range order and overall electronic performance has led to a simple model for the transition in terms of a competition between roughening due to the atomic size and smoothening due to precursor surface diffusion. It is proposed that diffusing precursors are immobilized by surface defects (or by other diffusing precursors), and the pre-existing (or resulting) defects are ultimately incorporated in the bulk.
Research on Amorphous Silicon Thin-Film Structure and Growth Processes Using Nonlinear Dynamics Methods
Authors: Bodyagin Nikolay Viktorovich , Vikhrov Sergey Pavlovich , Larina Tatiana Gennadievna , Mursalov Stanislav Mursalovich
Published: April 2011

There proved a possibility of applying the self-organization theory to the growth of noncrystalline thin-films and to the detection of ordering in their structure. Methods of analyzing the dynamics of complex systems are modified so as to investigate the structure of noncrystalline thin films. There offered new principles of the construction of material growth control systems.
Grain Nucleation and Grain Growth During Crystallization of HWCVD a-Si:H Films
Authors: Ahrenkiel S. P. , Roy B. , Mahan A. H. , Ginley D. S.
Published: April 2011

Hydrogenated amorphous silicon (a-Si:H) films of high and low hydrogen content were deposited directly on molybdenum, carbon-coated TEM grids by hot-wire chemical vapor deposition. The material was annealed at 600°C and 630°C for variable times to achieve various degrees of crystallinity. The films thickness of 100-nm allowed characterization by TEM without additional thinning. The grain growth in such thin films is nearly two-dimensional, allowing clear identification of crystalline and amorphous regions. Thus, the crystalline volume fraction can be tracked by simple image-processing methods. The evolution of crystallization by grain nucleation and growth for these films is accurately described by classical phase-change kinetics. Analysis of the randomly distributed grains at early stages of crystallization also provides the average areal grain number density and grain size. From the image analysis, we determine the grain nucleation rate and the grain growth velocity. The final grain size is then estimated by extrapolation to the fully crystallized state, assuming the kinetic parameters remain constant after the onset of crystallization.
The Influence of Thermophoresis Effects During Deposition of Hydrogenated Amorphous Silicon Thin Films with Nanocrystalline Silicon Inclusions
Authors: Blackwell C. , Anderson C. , Deneen J. , Carter C. B. , Kortshagen U. , Kakalios J.
Published: April 2011

Silicon cluster formation is known to occur within silane plasmas when a capacitively-coupled deposition reactor is operated at high gas chamber pressures. These clusters are sensitive to the thermophoretic forces that will, depending on the sign of the thermal gradient, direct them toward or away from the silicon film's growing surface. We have developed a dual-chamber deposition system that produces nanocrystalline silicon particles (roughly 3-5 nm in diameter) in a flow-through reactor, and injects these particles into a separate capacitively-coupled plasma chamber where the amorphous film is produced. The structural, optical and electronic properties of these mixed-phase materials are investigated as a function of the controllable thermal gradient applied across the silane plasma during deposition.
Influence of Annealing on Crystallinity and Conductivity of p-type Nanocrystalline Si films
Authors: Panda Durga P. , Dalal Vikram
Published: April 2011

Nanocrystalline p-type Si:H layers are important for photovoltaic and MOSFET devices. A high conductivity in these layers leads to better voltages in PV devices and to lower series resistance in both PV and MOSFET devices. The lower resistance results in higher channel mobility in MOSFET devices and higher fill factors in PV devices. In this work, we discuss the improvement in conductivity and crystallinity of p-type nanocrystalline Si:H layers by the use of post-deposition annealing. The p layers were deposited at ~ 180C from mixtures of silane, hydrogen, helium and diborane using ECR plasma deposition techniques. It was found that addition of He to H at first improved both the conductivity and crystallinity, but too much He led to an amorphous phase and lower conductivity. The as-grown films were measured for their crystallinity using both Raman spectroscopy and x-ray diffraction. The conductivity and activation energies were also measured. The films were then successively annealed at temperatures of 250, 300, 350 and 400C. The crystallinity and grain size were found to increase as the annealing temperature increased. The greatest relative increase was during the initial annealing stages. The conductivity of the films increased significantly as a consequence of the annealing. Conductivities as large as 20 S/cm were obtained in very thin films (~50-150 nm). The corresponding activation energies were in the range of 0.03 eV. When these annealed layers were used for MOSFET and PV devices, there was an appreciable increase in performance characteristics.
The Concentration of (SiH2)n Sites in Low and High Defect Density a-Si:H
Authors: Bobela David C. , Su T. , Taylor P. C. , Madan A. , Ganguly G.
Published: April 2011

The concentration of polysilane chains (SiH2)n, where n≥1, is estimated for higher quality hydrogenated amorphous silicon (a-Si:H) by pulsed proton nuclear magnetic resonance techniques (1H NMR). Our measurements indicate the minimum hydrogen content of approximately 10% of the total hydrogen is in the (SiH2)n configuration. Similar measurements in a high defect density sample (1017 silicon dangling bond defects cm-3) show that (SiH2)n sites account for ~ 15% of the total hydrogen. While the (SiH2)n infrared absorption (IR) modes are observed in the highly defective sample, no such modes are seen in the higher quality material. The results indicate that a significant amount of the total hydrogen content exists as (SiH2)n regardless of film quality.
Enlargement of Grain Size and Location Control of Grain in Excimer-laser Crystallization of Si Film
Authors: Yeh Wenchang , Ke Dunyuan , Zhuang Chunjun
Published: April 2011

A technique for enlargement of grain size were shown and a technique for location controlled super lateral growth (SLG) grain in excimer laser annealing (ELA) were proposed and realized. In the technique for grain size enlargement, the grain size was enlarged to 10£gm that is more than 10 times larger than that in conventional method(~0.8£gm). The proposed sample structure was Si film/light absorptive film/Glass structure with applying the laser light from the back side of glass substrate. Time resolved(~1ns) optical measurement (TROM) revealed that the melt duration of Si film was increased to 800ns that is also 10 times longer than that in conventional method. As for the grain location control technique, a new method contains pre seeding process and post growth process were proposed and realized. In the pre seeding process, micro light beam(£g-light beam) was exposed to Si film to form a grain within the crystallized spot. £g-light beam was formed by micro-lens-array(MLA). After post growth process, single grain array with the diameters of 6£gm was formed in a period of 10£gm.
Periodic Alignment of Silicon Dot Fabricated by Linearly Polarized Nd:YAG Pulse Laser
Authors: Nishioka Kensuke , Horita Susumu
Published: April 2011

Periodically aligned submicron Si dots were fabricated by only irradiating linearly polarized Nd:YAG pulse laser to the amorphous silicon (a-Si) thin film deposited on silicon dioxide (SiO2) film. Interference between the incident beam and the scattered surface wave leads to the spatial periodicity of beam energy density distribution on the surface of the irradiated samples. The a-Si thin film was melted by laser beam, and then, the molten thin Si film was split and condensed due to its surface tensile according to the periodic energy density distribution. The polycrystalline Si (poly-Si) fine lines were formed periodically. After the first irradiation, the sample was rotated by 90o, and the laser beam was irradiated. The periodic energy density distribution was generated on the Si fine lines. Then, the lines were split off and condensed according to the periodic energy density distribution, and the periodically aligned submicron Si dots were fabricated on the SiO2 film.
Physics of Solid-Phase Epitaxy of Hydrogenated Amorphous Silicon for Thin Film Si Photovoltaics
Authors: Stradins Paul , Yan Yanfa , Reedy Robert , Young David L. , Teplin Charles W , Iwaniczko Eugene , Xu Yueqin , Jones Kim , Teeter Glenn , Mahan A. Harv , Branz Howard M. , Wang Qi
Published: April 2011

Solid state crystallization of hydrogenated amorphous silicon (a-Si:H) prepared by hot-wire CVD is studied in solid phase epitaxy mode. By using a novel optical method combined with cross-sectional TEM and SIMS, a reduction of epitaxial growth speed is observed with increase in a-Si:H film thickness. Namely, in films thinner that 0.5 micron, solid phase epitaxy velocity depends linearly on film thickness. As the film thickness increases beyond 1 micron, the average velocity of solid phase epitaxy decreases considerably with respect to that in thinner films. In this regime, its velocity becomes also time-dependent: initial slow propagation of crystallization front gets considerably accelerated after the front has traveled above 400nm. SIMS thickness profiles of hydrogen shows considerably more residual hydrogen in thicker films after the start of solid phase epitaxy. In addition, prolonged pre-dehydrogenation at lower temperatures results in the increase in the average epitaxy speed in thicker films. These phenomena are likely related to delayed hydrogen outdiffusion in thicker films, which also leads to time-dependent speed of the solid-phase epitaxy front. We conclude that excess residual hydrogen reduces the rate of solid-phase crystalline growth.
Hot-wire CVD a-Si:H TFT on Plastic Substrates
Authors: Taghibakhsh Farhad , Karim K.S.
Published: April 2011

Fabrication of hot-wire chemical vapor deposition (HWCVD) of amorphous silicon (a-Si) thin film transistors (TFT) on thin polyamide sheets is reported. A single graphite filament at 1500 °C was used for HWCVD and device quality amorphous silicon films were deposited with no thermal damage to plastic substrate. Top-gate staggered thin film transistors (TFTs) were fabricated at 150°C using hot-wire deposited a-Si channel, Plasma enhanced chemical vapor deposition (PECVD) silicon nitride gate dielectric, and microcrystalline n+ drain/source contacts. Low leakage current of 5×10-13 A, high switching current ratio of 1.3×107, and small sub threshold swing of 0.3 V/dec was obtained for TFTs with aspect ratio of 1300μm/100μm. The field effect mobility was extracted to be 0.34 cm2/V.s.
Mechanisms for Defect Creation and Removal in Hydrogenated and Deuterated Amorphous Silicon Studied using Thin Film Transistors
Authors: Flewitt Andew , Lin Shufan , Milne William I , Wehrspohn Ralf B , Powell Martin J
Published: April 2011

It has been widely observed that thin film transistors (TFTs) incorporating an hydrogenated amorphous silicon (a-Si:H) channel exhibit a progressive shift in their threshold voltage with time upon application of a gate bias. This is attributed to the creation of metastable defects in the a-Si:H which can be removed by annealing the device at elevated temperatures with no bias applied to the gate, causing the threshold voltage to return to its original value. In this work, the defect creation and removal process has been investigated using both fully hydrogenated and fully deuterated amorphous silicon (a-Si:D) TFTs. In both cases, material was deposited by rf plasma enhanced chemical vapour deposition over a range of gas pressures to cover the a-g transition. The variation in threshold voltage as a function of gate bias stressing time, and annealing time with no gate bias, was measured. Using the thermalisation energy concept, it has been possible to quantitatively determine the distribution of energies required for defect creation and removal as well as the associated attempt-to-escape frequencies. The defect creation and removal process in a-Si:H is then discussed in the light of these results.
Analytical Studies of the Capping Layer Effect on Aluminum Induced Crystallization of Amorphous Silicon
Authors: Abu-Safe Husam , Sajjadul-Islam Abul-Khair M. , Naseem Hameed A. , Brown William D.
Published: April 2011

The effect of capping layer on metal induced crystallization of amorphous silicon was studied. Three sets of samples were prepared in this study. All samples had the basic layer structure of amorphous silicon layer deposited on a glass substrate. This was followed by a thin aluminum layer deposition. The second and third sets, however, had a third layer of amorphous silicon with thicknesses of 20 and 50 nm, respectively. These layers were deposited on top of the aluminum. The samples were annealed at 400°C for 15, 30 and 45 minutes. The crystallization fraction in the resultant films was analyzed using X-Ray diffraction, scanning electron microscopy, energy dispersive x-ray spectroscopy, and atomic force microscopy. It was observed that the capping layer reduces nodule formation improving the smoothness of the crystallized polysilicon films.
Fabrication of Crystallized Si Film Deposited on a Polycrystalline YSZ Film/Glass Substrate at 500°C
Authors: Horita Susumu , Kanazawa Keisuke , Nishioka Kensuke , Higashimine Koichi , Koyano Mikio
Published: April 2011

We used a polycrystalline YSZ film deposited on the quartz substrate as a seed layer to enhance crystallization of the Si film deposited on it. The YSZ film was deposited by reactive sputtering at less than 50°C and the preferential orientation was (111). The 60-nm-thick Si film was deposited by e-beam evaporation method on the substrate with and without the YSZ film. It was found that the crystallization of the Si film deposited on the YSZ film occurs but not without the YSZ film at the temperature of 515°C. The SEM image of the Secco-etched Si film showed that the crystallized Si film consisted of ~50-nm-size grains and, from the TEM image, it is supposed that the Si grains are grown directly from the YSZ film.
Improvement of Threshold Voltage Degradation Characteristics of a-Si:H TFT by Pre-Electrical Bias-Aging for Amoled Display
Authors: Lee Jae-Hoon , Park Sang-Geun , Shin Kwang-Sub , Han Min-Koo , Goh Joon-Chul , Huh Jong-Moo , Choi Joonhoo , Chung Kyuha
Published: April 2011

We propose a pre-electrical bias aging to reduce threshold voltage (Vth) shift of hydrogenated- amorphous silicon thin-film transistor (a-Si:H TFT) for AMOLED display. The quantity of Vth shift in the sample subjected to a bias-aging is reduced due to the reduction of created dangling bond density, compared with a sample without a bias-aging. When an identical stress duration of 50,000 sec is applied to a-Si:H TFT with or without a pre-electrical bias-aging, the created dangling bond density (ΔNDB) after a pre-electrical bias-aging is decreased from 1.38 × 1011/cm2 to 0.685 × 1011/cm2. Our experimental results indicate that after the pre-electrical bias aging, a newly created dangling bond during an electrical stress is decreased because a weak bond density and hydrogen diffusion may be decreased.
Silicon Etching Study in a RT-CVD Reactor with the HCl/H2 Gas Mixture
Authors: Loubet Nicolas , Talbot Alexandre , Dutartre Didier
Published: April 2011

A promising candidate to etch silicon totally selective against the dielectrics is here studied. This paper reports a detailed study of the silicon chemical vapor etch with HCl/H2 mixtures. Kinetics measurements on (001)-oriented wafers permitted us to extract apparent activation energies varying from 95.2kcal/mol and 73.9kcal/mol, depending on the HCl dilution in the chamber. On the other hand, etch rates measurements as a function of the HCl partial pressure are found to follow a sub-linear behavior indicating complex mechanisms occurring with the use of the HCl/H2 gas mix. In a second part, thanks to SEM cross-section observations, morphological analysis permitted us to point out that the {311} facet behave differently as compared to the {111} and {100} planes. To conclude, we extracted rugosity data after HCl treatment from AFM measurements and all these results permitted us to validate the potential industrialization of this etching process for the formation of localized cavities or junctions on patterned wafers.
17.8%-efficient Amorphous Silicon Heterojunction Solar Cells on p-type Silicon Wafers
Authors: Wang Qi , Page Matt P. , Iwancizko Eugene , Xu Yueqin , Yan Yanfa , Roybal Lorenzo , Levi Dean , Bauer Russell , Branz Howard M. , Wang Qi
Published: April 2011

We have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.
The Carbon Co-implant with Spike RTA Solution for Boron Extension
Authors: Pawlak Bartek , Augendre Emmanuel , Severi Simone , Eyben Pierre , Janssens Tom , Falepin Annelies , Absil Philippe , Vandervorst Wilfried , Felch Susan , Collart Erik , Schreutelkamp Robert , Cowern Nick
Published: April 2011

We present B junction extensions that are extremely abrupt and shallow manufactured by amorphization, C co-implantation and conventional rapid thermal annealing (RTA). Resulting junctions have abruptnesses of 2 nm/dec better than as-implanted profiles. The most shallow B junction that has been manufactured is 15 nm deep and Rs = 626 Ω/sq. Successful implementation of these junctions is straightforward for P-MOS 30 nm gate length devices.
Enhanced Activation of Standard and Cocktail Spike Annealed Junctions with Additional Sub-melt Laser Anneal
Authors: Severi Simone , Augendre Emmanuel , Pawlak Bartek , Eyben Pierre , Noda Taiji , Felch Susan , Falepin Annelies , Parihar Vijay , Schreutelkamp Robert , Vandervorst Wilfried , De Meyer Kristin
Published: April 2011

The advantages of fluorine co-implantation on reducing the deep P junction profile is investigated and commented as a possible valuable solution for further scaling of the NMOS transistors spacer length. On PMOS transistors, Ge+C+B cocktail junctions lead to improved short channel effects control, S/D resistance and performance over the conventional approaches. Additional laser annealing induces a partial dissolution of the doping clusters in the junction and lower the S/D transistors resistance. A performance improvement is demonstrated both for NMOS and PMOS with cocktail junctions activated by spike RTA and additional laser annealing.
Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator
Authors: Hamilton Justin J , Collart Erik JH , Colombeau Benjamin , Bersani Massimo , Giubertoni Damiano , Kah Max , Cowern Nicholas EB , Kirkby Karen J
Published: April 2011

Formation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.
Room Temperature Boron Diffusion in Amorphous Silicon
Authors: Jacques Jeannette M. , Jones Kevin S. , Law Mark E. , Robertson Lance S. , Rubin Leonard M. , Napolitani Enrico
Published: April 2011

As millisecond annealing is increasingly utilized, the as-implanted profile dominates the final dopant distribution. We characterized boron diffusion in amorphous silicon prior to post-implantation annealing. SIMS confirmed that both fluorine and germanium enhance boron motion in amorphous materials. The magnitude of boron diffusion in germanium amorphized silicon scales with increasing fluorine dose. Boron atoms are mobile at concentrations approaching 1x1019 atoms/cm^3. It appears that defects inherent to the structure of amorphous silicon can trap and immobilize boron atoms at room temperature, but that chemical reactions involving Si-F and Si-Ge eliminate potential trapping sites. Sequential Ge+, F+, and B+ implants result in 80% more boron motion than do sequential Si+, F+, and B+ implants. The mobile boron dose and trapping site concentration change as functions of the fluorine dose through power law relationships. As the fluorine dose increases, the trapping site population decreases and the mobile boron dose increases. This reduction in trap density can result in as-implanted “junction depths” that are as much as 75% deeper (taken at 1x1018 atoms/cm-3) for samples implanted with 500 eV, 1x1015 atoms/cm2 boron.
PN Junction Formation for High-Performance Insulated Gate Bipolar Transistors (IGBT); Double-Pulsed Green Laser Annealing Technique
Authors: Kudo Toshio Joshua , Wakabayashi Naoki
Published: April 2011

In order to form the deep PN junction demanded for the next generation IGBTs, the double-pulsed laser annealing technique as the low-thermal budget heat treatment has been introduced to activate a B-implant layer and a P-implant layer within the wafer surface to the depth 2μm. The double-pulsed laser annealing is characterized by the deep penetration depth due to a green wavelength of DPSS lasers and precisely and widely controlling of the annealing temperature and time. In the IGBT's structure the deep PN junction at a collector (the rear face) should be formed without damaging thermally circuit elements made of low melting point materials at a gate and an emitter (the front face).

Ion-implant samples using eight-inch (100) Si wafers were prepared as follows: Boron (B) implant was performed at a dose of 1E+15/cm2 at an energy of 40keV and/or phosphorus (P) implant at 1E+13/cm2 at an energy of 400keV. The double-pulsed laser irradiation was carried out at the constant first and second pulse energy density E1=E2=1.8J/cm2 at the delay time td= 0-500ns and the overlap ratio OR=67-90%. The melt depth was up to about 0.3μm. The electrical activation ratio of the B-implant layer within the depth of about 0.6μm was improved from 91% to about 100% with the delay time increase of 0ns to 500ns. The activation ratio of the P-implant layer within the depth of about 2μm was drastically improved from 48% to 82% with the same delay time increase and the carriers in the P-implant layer were distributed deeply from the depth 1.1μm to 1.8μm. Furthermore, with the overlap ratio increase of 67% to 90% the carriers in the P-implant layer were distributed deeply from the depth 1.8μm to 1.9μm and the high activation ratio of 82% was maintained. The high ratio of electrical activation is supported by the defect-free epitaxial regrowth where the majority of the B dopants was diffused in the liquid phase and that of the P dopants in the solid phase.
Schottky Source/Drain Transistor on Thin SiGe on Insulator Integrated with HfO2/TaN Gate Stack
Authors: Gao Fei , Lee S.J. , Li Rui , Balakumar S. , Tung Chih-Hang , Chi Dong-Zhi , Kwong Dim-Lee
Published: April 2011

We report thin SGOI (Silicon Germanium on Insulator) with 65% Ge concentration p- MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) using Ni-germanosilicide Schottky S/D (source/drain) and HfO2/TaN gate stack integrated with conventional self-aligned top gate process. Unlike high temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic, low gate leakage current and hence, well-behaved transistor performance. In addition, SOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current of the MOSFET.
Visualisation of Ge Condensation in SOI
Authors: Fobelets Kristel , Vincent Benjamin , Ahmad Munir , Christofi Astolfi , McPhail David
Published: April 2011

We use a novel technique CABOOM – Characterisation of Alloy concentration via Beveling, Oxidation and Optical Microscopy – to visualize the change of the Ge concentration sandwiched between two SiO2 layers during the Ge condensation process. CABOOM is very sensitive to variations in the gradient of the Ge concentration in the SiGe layer and thus gives a fast and simple way to interpret the condensation process. We present a systematic study of Ge condensation in a 120nm thick Si0.92Ge0.08 layer on a 60 nm Si body SOI (silicon-on-insulator) as a function of oxidation temperature and time, using CABOOM, SIMS and XRD. CABOOM shows the non-linear variation of the Ge diffusion as a function of process time.
Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features
Authors: Ortolland Claude , Morin Pierre , Arnaud Franck , Orain Stephane , Reddy Chandra , Chaton Catherine , Stolk Peter
Published: April 2011

In this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: <110> and <100>. This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.
Thermal Stability of Thin Virtual Substrates for High Performance Devices
Authors: Olsen Sarah H , Bull Steve J , Dobrosz Peter , Escobedo-Cousin Enrique , Agaiby Rimoon , O'Neill Anthony G , Coulson Howard , Claeys Cor , Loo Roger , Delhougne Romain , Caymax Matty
Published: April 2011

Detailed investigations of strain generation and relaxation in Si films grown on thin Si0.78Ge0.22 virtual substrates using Raman spectroscopy are presented. Good virtual substrate relaxation (>90%) is achieved by incorporating C during the initial growth stage. The robustness of the strained layers to relaxation is studied following high temperature rapid thermal annealing typical of CMOS processing (800-1050 °C). The impact of strained layer thickness on thermal stability is also investigated. Strain in layers below the critical thickness did not relax following any thermal treatments. However for layers above the critical thickness the annealing temperature at which the onset of strain relaxation occurred appeared to decrease with increasing layer thickness. Strain in Si layers grown on thin and thick virtual substrates having identical Ge composition and epilayer thickness has been compared. Relaxation through the introduction of defects has been assessed through preferential defect etching in order to verify the trends observed. Raman signals have been analysed by calibrated deconvolution and curve-fitting of the spectra peaks. Raman spectroscopy has also been used to study epitaxial layer thickness and the impact of Ge out-diffusion during processing. Improved device performance and reduced self-heating effects are demonstrated in thin virtual substrate devices when fabricated using strained layers below the critical thickness. The results suggest that thin virtual substrates offer great promise for enhancing the performance of a wide range of strained Si devices.
Quantum Well Nanopillar Transistors
Authors: Hu Shu-Fen , Sung Chin-Lung
Published: April 2011

We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.
Effect of Spacer Scaling on PMOS Transistors
Authors: Lau Wai Shing , Eng Chee Wee , Vigar David , Chan Lap , Siah Soh Yun
Published: April 2011

Our observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.
Low Temperature Silicon Dioxide Deposition and Characterization
Authors: Chatham Hood , Mogaard Martin , Okuyama Yoshi , Treichel Helmuth
Published: April 2011

Although much effort has been expended toward developing alternate dielectrics for use in fabricating ULSI circuits, there is still a need for high quality SiO2 films. In particular, process temperature restrictions have increased the demand for high quality, low temperature SiO2 films.[1] Such films have multiple applications in microelectronics, including use as passivation coatings, interlevel dielectrics, gate dielectrics in metal oxide semiconductor field effect transistors (MOSFETs), thin film transistors, and in devices using dual spacers.[2] Advanced devices at the 65-nm node and beyond are typically fabricated with nickel silicided electrodes—which enable lower junction silicon consumption, lower sheet resistance, and reduced agglomeration, but require subsequent process temperatures to be below 550°C. Also, to prevent movement of the ultra shallow junctions (USJs) during a subsequent thermal cycle, the temperatures for process steps after USJ formation must be kept below 600°C. To meet these needs, we have developed a low temperature (<500°C) SiO2 process that results in excellent dielectric quality.

This paper presents results on high-quality chemical vapor deposition (CVD) SiO2 films deposited at temperatures from 200°C to 450°C using a novel proprietary and versatile silicon precursor using oxygen as the oxidizer. Composition, film stress, deposition rate, leakage current density, and step coverage results are presented.
Introduction of Airgap Deeptrench Isolation in STI Module for High Speed SiGe : C BiCMOS Technology
Authors: Kunnen Eddy , Choi Li Jen , Van Huylenbroeck Stefaan , Piontec Andreas , Vleugels Frank , Dupont Tania , Devriendt Katia , Shi Xiaoping , Vanhaelemeersch Serge , Decoutere Stefaan
Published: April 2011

The impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.

The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.
Low Temperature Selective Si and Si-Based Alloy Epitaxy For Advanced Transistor Applications
Authors: Kim Yihwan , Zojaji Ali , Ye Zhiyuan , Lam Andrew , Dalida Nicholas , Sanchez Errol , Kuppurao Satheesh
Published: April 2011

We have developed low temperature selective Si and Si-based alloy (SiGe and Si:C) epitaxy processes for advanced transistor fabrications. By lowering epitaxy process temperature (≤ 700 °C), we have demonstrated elevated source/drain formation on ultra-thin (< 50 Å) body SOI transistors without Si agglomeration, smooth morphology of selective SiGe epitaxy with high [Ge] (>30 %) and [B] (>2E20 cm-3) concentrations, and selective Si:C epitaxy with high substitutional C concentration (>1 %). Also, we have increased growth rate of low temperature selective epitaxy processes by optimizing process parameters by adapting non-conventional deposition method.
TCAD Modeling of Strain-Engineered MOSFETs
Authors: Smith Lee
Published: April 2011

The rapid rise of standby power in nanoscale MOSFETs is slowing classical scaling and threatening to derail continued improvements in MOSFET performance. Strain-enhancement of carrier transport in the MOSFET channel has emerged as a particularly effective approach to enable significant performance improvements at similar off-state leakage. In this paper we describe how strain effects are modeled within the context of TCAD process and device simulation. We also use TCAD simulations to review some of the common approaches to engineer strain in MOSFETs and to explain how strain impacts device and circuit characteristics.
Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects
Authors: Xu Xiaopeng , Pramanik Dipu , Rollins Greg
Published: April 2011

The layout dependence of process stress in Cu/low k interconnects are examined using various stress sources and layout patterns. The anisotropic grain growth stress model is compared with the conventional isotropic intrinsic stress model and the latter is found to underestimate stress concentrations in the dielectric regions near metal line ends. Both the grain growth stress in copper and the thermal mismatch stress in copper and low k dielectrics are considered in the layout dependence study. The results demonstrate that accurate stress evaluation in interconnect structures has to employ geometrical models that include layout variations. Capabilities are developed to extract these geometrical models directly from layout analysis.
Evaluation of Damages and Pore-sealing Capabilities of Oxidizing and Reducing Etch Plasmas for Single and Dual Damascene Patterning of Porous Ultra-Low-k Materials
Authors: Ollier Emmanuel , Clain Mathieu , Fox Robert , Brun Philippe , Jullian Stephane
Published: April 2011

This paper presents the evaluation of oxidizing and reducing plasmas for post etch pore-sealing treatments during patterning of interconnections in a porous Ultra Low-k (ULK) material. Morphological and chemical characterizations as well as electrical results (resistance, capacitance, leakage, yield) are presented for both single and dual-damascene integrations.
In-Situ Characterizarion of Interfaces-Induced Resistivity in Nanometric Dimensions
Authors: Marom Hagay , Eizenberg Moshe
Published: April 2011

To improve the speed of integrated circuits it is highly important to minimize the electrical resistivity of their interconnects. However, as the dimensions of the interconnects approach the mean free path of the electrons, a substantial rise in resistivity occurs due to additional electron scatterings from grain boundaries and interfaces. To investigate the role of interfaces, in-situ resistivity measurements were preformed for thin copper films on which different materials were deposited. The resistivity was monitored before and after the deposition, enabling to observe the changes as a new top interface was created. Among the materials tested, tantalum resulted in the highest resistivity increase. This fact is of special importance since this material and its nitride serve today as the common diffusion barrier for copper metallization. Titanium resulted in a smaller resistivity increase, but still higher than that of a free copper surface in vacuum. The developed approach enables to test the influence of different diffusion barriers on copper resistivity. With the continuously shrinking dimensions of copper interconnects, this factor will have an increasing importance in future technology nodes.
The Stepwise Cross-sectional Crystalline Analysis of the Stress Induced Voiding in Cu Interconnect
Authors: Lee Hyo-Jong , Han Heung Nam , Kang Suk Hoon , Sun Jeong-Yun , Oh Kyu Hwan
Published: April 2011

In a crystallographic study of stress induced voiding of copper interconnect, the planar electron backscattered diffraction analysis showed that the void was initiated at the triple junction of the grain boundaries, not at the junction of the twin boundary and grain boundary. By using stepwise cross-sectional crystalline investigation for the void, it was possible to rebuild 3D crystalline structure near the void. From the stress calculation based on the measured crystalline structures, the hydrostatic stress was highly concentrated at the triple junction of the twin boundary and grain boundary, but experimentally, there was no voiding at that. The voiding in the copper interconnect may depend mainly on the boundary instability.
Improvement of Barrier Properties of TaN Film by Plasma Enhanced Atomic Layer Deposition
Authors: Baek In Cheol , Lee Han Choon , Sim Cheonman , Han Jae Won , Kim Kee Ho , Kim Soo Hyun , Lee Sahng Kyoo
Published: April 2011

The barrier metal properties of Plasma Enhanced ALD (PEALD) TaN deposited on low-k dielectric film (SiCOH) with a k value of 3.0 at a deposition temperature of 300°C by using pentakis (ethylmethylamino) tantalum (PEMAT) and various plasma gases was investigated. The film resistivity of TaN is about 1000 μΩ.cm under the plasma power of 200 W and the frequency of 400 KHz, respectively. The resistivity was significantly reduced by approximately 360 μΩ.cm for the optimized condition of 300 W and 13.56 MHz. In addition, good uniformity was obtained by applying two-step plasma treatment process. The film thickness per cycl of the TaN using two-step plasma was decreased from 1.0 Å to 0.65 Å by reducing a base pressure, indicating the increase of the film density. The PEALD TaN with almost 100% coverage in this paper's dual damascene structure has a contact resistance of about 1.6 Ω /chain at via size of 0.19um.
Routes to the Formation of Air Gap Structures Using PECVD
Authors: Vrtis Raymond N. , Wu Dingjun , O'Neill Mark L , Haas Mary K. , Weigel Scott J. , Karwacki Eugene J.
Published: April 2011

Fabrication of air gap features have been achieved by three processes utilizing the diffusion of materials through a porous OSG layer. The first process involves the decomposition of a PECVD deposited organic material, either thermally or via UV anneal, to create a void with the decomposition by-products diffusing through the porous OSG layer. The second process uses the etch selectivity of XeF2 or BrF3 towards silicon versus OSG to diffuse through the porous OSG layer to etch the underlying silicon. Finally the water solubility of films such as GeO2 or B2O3, which can be easily deposited by PECVD, can be utilized for void formation via dissolution of the sacrificial inorganic layer through the porous OSG.
Fine Keyed Alignment and Bonding for Wafer-Level 3D ICs
Authors: Lee Sang Hwui , Niklaus Frank , McMahon J. Jay , Yu Jian , Kumar Ravi J. , Li Hui-feng , Gutmann Ronald J. , Cale Timothy S. , Lu J.-Q.
Published: April 2011

Precise wafer-to-wafer alignment accuracy is crucial to interconnecting circuits on different wafers in three dimensional integrated circuits. We discuss the use of fabricated structures on wafer surfaces to mechanically achieve higher alignment accuracy than can be achieved with our existing (baseline) alignment protocol. The keyed alignment structures rely on structures with tapered side-walls that can slide into each after two wafers are “pre-aligned” using our baseline alignment protocol. Results indicate that alignment accuracy is about a quarter micron, well below the one micron alignment accuracy obtained in our baseline alignment procedure using commercial state-of-the-art wafer alignment equipment. In addition to improving alignment, the alignment structures also hinder undesirable bonding-induced misalignment. The keyed alignment structures are also promising for nano-imprint lithography.