Análise da mobilidade em transistores SOI de canal gradual visando simulações de circuitos
Authors:   , Silva L. M. B. 
Published: March 2021

The GC (Graded-Channel) SOI (Silicon-On-Insulator) MOSFET (Metal-OxideSemiconductor Field Effect Transistor) transistor is a SOI transistor whose channel is divided into two regions: a highly doped region and a lightly doped region. The reduction of the doping concentration in the channel region near the drain allows GC SOI transistors to present a series of advantages over the conventional uniformly doped transistor, showing better analog characteristics, such as higher current level, increased transconductance, reduction of drain conductance, which implies higher Early voltage, and higher breakdown voltage. The association of these characteristics shows that GC SOI MOSFET has great potential for applications in analog integrated circuits. One of the steps in the design of integrated circuits is the simulation of these circuits. To allow for reliable simulations, analytical models that describe the electronic devices are required. Although a proposed model has been presented for the GC SOI transistor, it is not implemented in commercial simulators. To circumvent this, some works demonstrate the simulation of GC transistors through the association of two uniformly doped SOI transistors with different doping concentrations and short-circuited gates. However, the adoption of this strategy makes necessary to use twice as many transistors in the simulated circuit. Additionally, the use of two transistors increases the source and drain capacitances of the intermediate point between the two devices. Aiming at simulating and designing analog circuits using a graded-channel structure, this work presents a study of the effective mobility of GC SOI transistors. The objective is to simulate the graded channel transistor using available models in commercial simulators for uniformly doped SOI transistors, by adjusting its parameters, which would became dependent on the lengths and doping concentrations of the two regions of the channel. This work demonstrates that using mobility parameters such as low field mobility (µ0), linear (?1) and quadratic (?2) degradation factors, extracted by Y-Function method and making adjustments to the PCLM parameter, included in the BSIM-SOI model and which is related to the channel modulation effect, it is possible to reproduce the behavior in the drain current (IDS) and transconductance (gm) curves as a function of the gate voltage (VGS) and in the drain current (IDS) and output conductance (gD) curves as a function of drain voltage (VDS) using a single uniformly doped SOI MOSFET transistor in a SPICE simulator. The results showed a maximum error of 5.26% and 10.34% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for low drain voltage (VDS) in GC transistors with channel length (L) of 1 µm and 2 µm. For high drain voltage (VDS), the errors obtained were 10.68% and 14.08% in the drain current (IDS) and transconductance (gm) curves, respectively, as a function of the gate voltage (VGS) for 2 µm GC transistors. The drain current curves (IDS) as a function of drain voltage (VDS) showed an error of less than 5.4% with overdrive voltage (VGT) ranging from 200mV to 600mV. The output conductance (gD) as a function of the drain voltage (VDS) was reproduced, showing a better approximation with the experimental data by adjusting the PCLM parameter. The best results were obtained for low overdrive voltage (VGT) in the saturation region. The adjustment of the PCLM parameter together with the mobility parameters, (µ0), (?1) and (?2), allowed simulating the behavior of the GC transistor with good approximation, which can make this an interesting approach for an initial step of analytical simulation of analog integrated circuits using the GC SOI MOSFET transistor