(Invited) Nanostructured Silicon Integrated Circuit Thermoelectric Generators with High Specific Power Generation Capacity
Authors: Lee Mark , Hu Gangyi , Edwards Hal 
Published: February 2020

Microelectronic thermoelectric (TE) devices aimed at integrated circuit (IC) and sensor applications such as on-chip thermal management, bio-thermal power for wearable electronics, and microwatt level sustainable power sources for internet-of-things (IoT) sensors have grown in recent interest. While silicon CMOS by far dominates microelectronics technology, Si has historically not been considered as a viable TE material because bulk Si has a very low TE figure-of-merit ZT ~ 10–3 to 10–2 near room temperature. By contrast, modern “high ZT” materials such as the (Bi,Sb)2(Se,Te)3 family have ZT ≈ 1. However, these materials are incompatible with Si CMOS processing and so have not gained widespread adoption into microelectronic ICs. In 2008 two groups [Hochbaum, et al. Nature
451, 163; Boukai, et al. Nature
451, 168] reported that Si nanowires (NWs) can have ZT up to 0.6. Nevertheless, numerous efforts to develop microelectronic TE generators (TEG) using Si NWs or other nano-structured Si thermopiles have not achieved efficiencies better than what is consistent with ZT ~ 10–2.

In practice, efficiency is not necessarily the primary concern in many applications but rather how much power a TEG of given size generates from a temperature difference ∆T, as well as cost per Watt generated. Since the maximum power P
max generated is proportional both to (∆T)2 and to cross-sectional area A for heat flow, a performance metric of more direct practical interest is the specific power generation capacity Γ
P = P
max/[A·(∆T)2], as this measures TEG output power scaled to device size and to ∆T. Γ
P is an extrinsic device metric that can be engineered by circuit design and management of parasitic impedances, in contrast to ZT which is an intrinsic material characteristic.

In this presentation we will describe IC TEGs using nanostructured silicon thermopiles fabricated on an industrial “65 nm” technology node Si CMOS process line following standard CMOS process design rules. The thermopile elements are nanostructured n- and p-type Si “blades” nominally 80 nm wide x 750 nm long x 320 nm tall, with a typical total thermopile area of 48 µm x 36 µm. Depending on design layout and doping, these Si IC TEGs show high Γ
P, up to 29 µW·cm–2K–2, with most designs having Γ
P near 8.5 µW·cm–2K–2 using a cold side heat sink at room temperature. In terms of power generation ability a Γ
P of order 10 µW·cm–2K–2 makes these Si IC TEGs competitive with (Bi,Sb)2(Se,Te)3 based TEGs, although the net efficiency of these Si IC TEGs is still low. Engineering a high Γ
P despite low efficiency results from the ability of Si CMOS processing to fabricate a high areal density of thermocouples while still maintaining a low areal packing fraction, that is, to make uniformly a very large number of very small things in a given area, and to carefully control both intrinsic and parasitic electrical and thermal impedances. We find that TEG power increases significantly with decreasing thermocouple width, giving a fabrication path to further improvements. Unlike (Bi,Sb)2(Se,Te)3 TEGS, these Si IC TEGs can be seamlessly integrated into large scale Si CMOS microelectronic circuits at very low marginal cost.