bluuebunny/crossref_metadata_2025 huggingface dataset:
Development of APDL Program for Analysis of Composite Material Multicell Beams
Authors: Tariq M. Mushtaq , Pasha Mustafa , Ahmed Malik , Munir Azhar
Published: May 2012

Comparison of finite elements and comparison of ANSYS with MSC Patran Nastran, for analysis of composite material multicell beams, is the main idea of this paper. The Finite Element Analysis (FEA) is a valuable tool of modeling and simulation in development, processing, production and application of modern hi-tech materials and structures for reliable design. Multicell beams have important industrial applications in the automotive and aerospace sectors. ANSYS Parametric Design Language (APDL) is an important language in parametric modeling and analysis of structures with simple to complex geometry. Its major advantage is virtual prototyping which can be used to analyze and compare different materials. This work introduces core techniques required for APDL using the case study of composite multicell beams subjected to constrained torsional loading. The published results using MSC NASTRAN have been verified using ANSYS and the corresponding arising issues and notes are the focus of this research study. The details of geometry, material and boundary conditions have been explained in order to construct Finite Element (FE) model. This FE model was simulated several times in ANSYS by the authors using various options of APDL language. A step-wise flowchart was used to detect and reduce problems in iterations of analysis in APDL programming.
Results of FEA largely depend on FE model and software used. These issues become prominent while trying to verify results of MSC NASTRAN with ANSYS. The author has introduced three error criteria to select an equivalent finite element of one FEA package (ANSYS) for an equivalent element of other FEA package (MSC NASTRAN). These criteria are the relative error criterion, the absolute error criterion and the combined error criterion. The results from this research provide an insight into finite elements for reliability in design of composite materials. The practical milestones for research to develop FE model and APDL programs related to material research field are also manifested through this paper.
Effects on Structural, Electronic Transport & Optical Properties of Doped & Undoped ZnTe Thin Films for CdTe/CdS Solar Cells
Authors: Tariq G.H. , Anis-ur-Rehman Muhammad
Published: May 2012

To overcome the naturally existing Schottky barrier problem between p-CdTe and any metal, an intermediate semiconductor thin buffer layer is a better choice prior to the final metallization for contact. Among many investigated back contact materials the ZnTe is suitable as a buffer layer. ZnTe thin films were deposited onto glass substrates by the thermal evaporation technique under vacuum ~2×10-5mbar. Undoped ZnTe thin films are highly resistive, extrinsic doping of Cu was made to improve the electrical conductivity. Films were doped by immersing in Cu NO32.5H2O solutions for Cu doping. To optimize the growth parameters the prepared films were characterized using various techniques. The structural analysis of these films was performed by X-ray diffraction (XRD) technique and optical transmission. X-ray diffraction identified the phases present in these films and also observed that the prepared films were polycrystalline. Also the spectral dependence of absorption coefficient was determined from spectrophotometer. Energy band gap index were calculated from obtained optical measurements data.
Computational Model of Phase Transformations in Thermo-Chemical Cathodes Using Kinetic Approach
Authors: Kavokin A.A. , Kazmi I.H. , Munir B.
Published: May 2012

The paper presents the results of modeling of the processes of phases transformations occurring in cathode of plasmatron with zirconium insertion. Model describes temperature and liquid-solid phase transformation in cathode considering kinetics of transformation in accordance with a state diagram. The comparison between one-dimensional mathematical models was exploited for estimation of the kinetics coefficient. First model is based on well-known heat equation with Stefans condition on the free boundary between liquid and solid phases [. The standard analytical self-similar solution for two-phase case is applied. In the second model, for heat equation instead of Stefans conditions, differential equations of kinetics are used.
The Effect of Double Pass GMAW Process on Microstructure and Mechanical Properties of Aa 6061-T6 Joining Plates
Authors: Bakar S.R.S. , Ahmad M.Y. , Ibrahim Muhammad Faizol Ahmad , Jalar A. , Djalil S.J.S. , Othman Norinsan Kamil
Published: May 2012

This paper presents an investigation on microstructure and mechanical properties of welded AA 6061-T6 plate using filler metal ER 4043 in the Gas Metal Arc Welding (GMAW) process. Double pass welding technique on both sides of 5 mm thick plate or more is required to provide sufficient weld pool in the joint. The weld metal of the first welding pass exhibits finer microstructure than the second welding pass. The size of Mg2Si precipitations in the heat-affected zone (HAZ) region is larger than in the base metal due to the welding process that reheats the alloy from the T6 condition above the eutectic temperature. Rapid cooling of the first pass and moderate cooling rate for the second pass during weld metal solidification eventually resulted in significantly change the shape and size in the microstructure that had affected the hardness and mechanical properties. Comparisons made to the base metal on the hardness test results found that the hardness of first pass weld metal dropped by 15%, and by 37.5% for the second weld metal, while the hardness at the boundaries of the first and second weld metals dropped by 32.5%. The ultimate tensile strength and strain of the weld joint with ER 4043 also decreased by 48% and 94% respectively. Based on the findings of the study, it is concluded that even though the double sided welding technique is able to overcome shallow weld penetration to avoid stress concentration that leads to the fatigue failure, the metallurgical changes eventually contributes to degradation of mechanical properties.
Effect of Surface Morphology on the On-State Resistance of SiC Photoconductive Semiconductor Switches
Authors: Liu Xue Chao , Huang Wei , Chang Shao Hui , Zhu Ming Xing , Yang Jian Hua , Shi Er Wei
Published: May 2012

The photoconductive semiconductor switches (PCSS) were fabricated on V-doped semi-insulating 6H-SiC. We studied the effect of surface morphology on the on-state resistance of SiC PCSS. The SiC wafers with quite similar physical properties were processed by mechanical polishing, chemical mechanical polishing and H2 etching for producing different surface morphologies. All the SiC PCSS were excited by a 355 nm laser with a frequency of 10 Hz and a pulse intensity of 132 μJ/mm2. We found that the surface morphology had an obvious effect on the on-state resistance. The PCSS fabricated on mechanical polished SiC wafer with an average surface roughness (rms) of 1.0 nm showed the largest on-state resistance of 45.6 ohms, while a low value of 13.3 ohms was observed for the wafer processed by H2 etching at high temperature of 1550 °C.
Novel Low VON Poly-Si/4H-SiC Heterojunction Diode Using Energy Barrier Height Control
Authors: Yamagami Shigeharu , Hayashi Tetsuya , Hoshi Masakatsu
Published: May 2012

We experimentally investigated a method of controlling the energy barrier height (ΦB) of polycrystalline silicon (poly-Si)/4H-SiC heterojunction diodes (HJDs) and conducted a numerical simulation of a novel low Von and low reverse recovery current diode using ΦB control. The ΦB of the HJD with arsenic-doped n+-poly-Si was 0.79 eV and that of the HJD with boron-doped p+-poly-Si was 1.59 eV. The ΦB can be controlled over a wide range by varying the dopant and ion implantation dose of poly-Si. A novel merged HJD (M-HJD) with two different ΦB values obtained by using ΦB control is also presented. The numerical simulation results show that the M-HJD reduces Von without increasing reverse leakage current at high reverse voltage.
Recovery of Bipolar-Current Induced Degradations in High-Voltage Implanted-Gate Junction Field Effect Transistors
Authors: Veliadis Victor , Hearne Harold , Chang W. , Caldwell Joshua D. , Stewart Eric J. , Snook Megan , Howell R.S. , Urciuoli Damian , Lelis Aivars J. , Scozzie C.
Published: May 2012

Electron-hole recombination-induced stacking faults have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effects of bipolar injection induced stacking faults on the electrical characteristics of p+ ion-implanted high-voltage vertical-channel JFETs with 100-μm drift epilayers. The JFETs were stressed at a fixed gate-drain bipolar current density of 100 A/cm2 for five hours, which led to degradation of the forward gate-drain p-n junction and on-state conduction. The degradation was fully reversed by annealing at 350 °C for 96 hours. Forward and reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Non-degraded characteristics remain unaffected by annealing events. Consequently, should minority carrier injection occur in JFETs operating at elevated temperatures no stacking fault induced degradations are expected. This eliminates the need for specialty substrates with suppressed densities of basal plane dislocations in the fabrication of high-voltage SiC JFETs for high temperature applications.
Demonstration of SiC Vertical Trench JFET Reliability
Authors: Speer Kevin M. , Chatty Kiran , Bondarenko Volodymyr , Sheridan David C. , Matocha Kevin , Casady Jeff B.
Published: May 2012

This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.
Avalanche Breakdown Energy in Silicon Carbide Junction Field Effect Transistors
Authors: Hinojosa Miguel , Bayne Stephen , Veliadis Victor , Urciuoli Damian
Published: May 2012

The energy dissipation capabilities of a 1200 V, 0.1 cm2 JFET operating in blocking mode were investigated. These devices, which are used in bidirectional circuit breaker applications, can conduct a current of 13 A in forward-conduction mode, and typically block a voltage up to 1200 V in blocking mode. In this document, the blocking limits of the device were pushed slightly to the point where avalanche breakdown occurs. A high voltage pulse generator was designed and constructed to drive the JFET into this state and to monitor the dissipated energy. The devices were able to handle up to 18.14 mJ.
Packaging Technologies for 500°C SiC Electronics and Sensors
Authors: Chen Liang Yu , Johnson R. Wayne , Neudeck Philip G. , Beheim Glenn M. , Spry David J. , Meredith Roger D. , Hunter Gary W.
Published: May 2012

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500°C silicon carbide (SiC) electronics and sensors, and test results of packaged SiC JFETs and capacitive pressure sensors at 500°C.
High Voltage SiC Vertical JFET for High Power RF Applications
Authors: Hecht Christian , Elpelt Rudolf , Schörner Reinhold , Irsigler Roland , Heid Oliver
Published: May 2012

We present the optimization of a standard lateral channel vertical JFET for high-frequency high-power applications. It will be shown that SiC JFETs are well suited to fulfill the requirements of certain RF applications when compared to silicon devices. Simulations covering the electrical characteristics will be given together with calculations considering the self-heating of the chip in pulsed-power applications and the corresponding decrease in saturation current. The gate-signal propagation will be analyzed for different chip layouts and the effect on switching speed will be described. Electrical results will demonstrate that the optimized JFET is suitable for RF-transmitter applications, like e.g. solid state RF modules as Klystron replacements in linear accelerators.
Development of Vertical 3×2〞LPCVD System for Fast Epitaxial Growth on 4H-SiC
Authors: Zhao Wan Shun , Sun Guo Sheng , Wu Hai Lei , Yan Guo Guo , Zheng Liu , Dong Lin , Wang Lei , Liu Xing Fang , Yang Li Jun
Published: May 2012

A vertical 3×2〞low pressure chemical vapor deposition (LPCVD) system has been developed to realize fast epitaxial growth of 4H-SiC. The epitaxial growth process was optimized and it was found that the growth rate increases with increasing C/Si ratio and tends to saturate when C/Si ratio exceeded 1. Mirror-like thick 4H-SiC homoepitaxial layers are obtained at 1500 °C and C/Si ratio of 0.5 with a growth rate of 25 μm/h. The minimum RMS roughness is 0.20 nm and the FWHM of rocking curves of epilayers grown for 1 hour and 2 hours are 26.2 arcsec and 32.4 arcsec, respectively. These results indicate that high-quality thick 4H-SiC epilayers can be grown successfully on the off-orientation 4H-SiC substrates.
Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications
Authors: Ryu Sei Hyung , Cheng Lin , Dhar Sarit , Capell Craig , Jonas Charlotte , Callanan Robert , O'Loughlin Michael  J. , Burk Albert A. , Lelis Aivars J. , Scozzie Charles J. , Agarwal Anant K. , Palmour John W.
Published: May 2012

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.
690V, 1.00 mΩcm2 4H-SiC Double-Trench MOSFETs
Authors: Nakano Yuki , Nakamura R. , Sakairi H. , Mitani Shuhei , Nakamura T.
Published: May 2012

The trench gate structure MOSFET, with its lack of JFET resistance, is one of the structures able to achieve low on-state resistance [1,2]. In 2008, this group succeeded in fabricating 790V SiC trench MOSFETs with the lowest Ron,sp (1.7 mΩcm2) at room temperature. However these devices had issues regarding oxide destruction at the trench bottom during high drain-source voltage application. In order to improve this problem, this group developed the double-trench MOSFET structure. This structure has both source trenches and gate trenches. This paper compares two kinds of trench MOSFETs: the conventional, single trench structure and a double-trench structure. Also, the latest characteristics are presented.
Material Defects and Rugged Electrical Power Switching in Semiconductors
Authors: Shenai Krishna , Neudeck Philip G. , Dudley M. , Davis Robert F.
Published: May 2012

A paradigm shift in the development and utilization of power semiconductor switch technology is proposed. This new "top down" approach begins with the field-reliability of a power semiconductor switch in a power converter circuit is subjected to long-term repetitive-switching under stressful field-operating conditions. This approach is derived from extensive field-reliability data collected on state-of-the-art silicon power MOSFETs in compact computer/telecom power supplies that clearly suggests that power MOSFET field-failures were primarily caused by bulk material defects. A careful survey of power switch technologies reported to-date in Silicon Carbide (SiC) and Gallium Nitride (GaN) further suggests that excessive bulk material defects have predominantly hindered the development and commercialization of cost-effective, high-performance, and reliable high-power devices. A reliability-driven approach is likely to "unlock" the vast potential of SiC (and GaN for moderate power levels) power device technology for high-voltage and high-power switching electronics in order to impact transformative changes.
Comparative Study of SiC MOSFETs in High Voltage Switching Operation
Authors: Funaki Tsuyoshi , Nakano Yuki , Nakamura Takashi
Published: May 2012

SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.
4H-SiC MOSFETs with a Stable Protective Coating for Harsh Environment Applications
Authors: Daves Walter , Krauss A. , Häublein V. , Bauer A.J. , Frey L.
Published: May 2012

In this work we present 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with a stable protective coating for harsh environment applications. Both inversion channel (IC) and buried channel (BC) MOSFETs were realized on n-4H-SiC substrates with a p-epilayer. Stacked ONO gate dielectric and Ti/TiN/Pt/Ti interconnect were used. Ni and Ti ohmic contacts in combination with a-SiOx/a-SiNy and a-SiOx/a-SiC protective coatings were compared. The MOSFETs showed excellent transistor characteristics up to 600 °C and exceptional stability during long-term aging at 600 °C in air and during accelerated aging at 700 °C including temperature cycling and air/moisture environment.
SiC-MOSFET Structure Enabling Fast Turn-On and -Off Switching
Authors: Hino Shiro , Miura Naruhisa , Furukawa Akihiko , Watanabe Shoyu , Nakao Yukiyasu , Nakata Shuhei , Imaizumi Masayuki , Sumitani Hiroaki , Oomori Tatsuo
Published: May 2012

High speed switching is desired to reduce switching losses of SiC-MOSFETs. In order to realize SiC-MOSFETs capable of high speed switching, we numerically evaluated the electric field induced in SiC-MOSFETs during switching using an equivalent circuit model. Based on the evaluation, we designed a SiC-MOSFET, which successfully demonstrated high speed switching with a dV/dt of over 70 V/ns.
4H-SiC MOSFETs with Si-Like Low-Frequency Noise Characteristics
Authors: Rumyantsev Sergey L. , Shur Michael S. , Levinshtein Michael E. , Ivanov Pavel A. , Palmour John W. , Agarwal Anant K. , Dhar Sarit
Published: May 2012

4H-SiC MOSFETs with an epitaxial channel and NO postoxidation annealing have Si-like dependencies of noise on gate voltage. Such dependencies indicate that the density of the negatively charged oxide traps responsible for 1/f noise, Ntv, does not depend on the position of the Fermi level. The Ntv was found to be ~ 2×1019 cm-3eV-1. This value is considerably smaller than previously measured for transistors with ion implanted channels.
High Temperature Performance of 3C-SiC MOSFETs with High Channel Mobility
Authors: Uchida Hidetsugu , Minami Akiyuki , Sakata Toyokazu , Nagasawa Hiroyuki , Kobayashi Motoki
Published: May 2012

Transistor performances of lateral and vertical 3C-SiC MOSFETs are investigated in the temperature range of 25 °C to 300 °C. Both types of MOSFETs operate up to 300 °C and the lateral MOSFETs possess peak channel mobility of more than 100 cm2/(Vs) even at 300 °C for the [110]- and [-110]-channel directions. In both MOSFETs, on-currents decrease monotonically and threshold voltages shift negatively as the temperature increases. The temperature dependence of on-currents in the lateral MOSFETs is weaker than that in the vertical MOSFETs. The leakage current at the negative gate voltage increases at above 200 °C. The activation energies calculated from the leakage currents at 200 °C and 300 °C are about half of the 3C-SiC bandgap energy of 2.3 eV.
Dependence of the Channel Mobility in 3C-SiC n-MOSFETs on the Crystal Orientation and Channel Length
Authors: Zippelius Bernd , Hauck Martin , Beljakowa Svetlana , Weber Heiko B. , Krieger M. , Nagasawa Hiroyuki , Uchida Hidetsugu , Pensl Gerhard , Schöner Adolf
Published: May 2012

The channel mobility in 3C-SiC n-MOSFETs is investigated by current-voltage and Hall-effect measurements. For comparison, these techniques are also applied to 3C-SiC bulk rods. It turns out that the channel mobility depends on the orientation of the crystal and channel length. The observed results are traced back to the influence of Si-terminated stacking faults (Si-SFs), to the resistance of the drain/source contact and to the warping of the wafer caused by the special growth technique.
Chloride-Based CVD of 4H-SiC at High Growth Rates on Substrates with Different Off-Angles
Authors: Leone Stefano , Pedersen Henrik , Beyer Franziska Christine , Andersson Sven , Kordina Olof , Henry Anne , Canino Andrea , La Via Francesco , Janzén Erik
Published: May 2012

A review of recently achieved results with the chloride-based CVD on 8° and 4° off axis and nominally on-axis 4H-SiC wafers is done to clarify the epitaxial growth mechanisms on different off-angle substrates. The process conditions selected for each off-axis angle become even more difficult when running at growth rates of 100 µm/h or more. A fine-tuning of process parameters mainly temperature, C/Si ratio and in situ surface preparation is necessary for each off-angle. Some trends related to the surface properties and the effective C/Si ratio existing on the surface prior to and during the epitaxial growth can be observed.
An Investigation of Material Limit Characteristics of SiC IGBTs
Authors: Hatakeyama Tetsuo , Fukuda Kenji , Okumura Hajime
Published: May 2012

The impact of device concepts of Si insulated gate bipolar transistors (IGBTs) such as injection-enhanced IGBT (IEGT), high-conductivity IGBT (HiGT), and Si-limit IGBT on the performance of SiC IGBTs is examined. We first show that the forward characteristics of the original type of planer SiC IGBTs are much worse than those of SiC PiN diodes, even if the carrier lifetime is improved. Next, we show that the forward characteristics of SiC IEGTs and SiC HiGTs are comparable to those of SiC PiN diodes. Thus, device concepts of Si IGBTs are effective in improving the device performance of SiC IGBTs. Finally, it is shown that a SiC-limit IGBT can be realized when the mesa width is less than 0.5 μm.
12 kV, 1 cm2 SiC GTO Thyristors with Negative Bevel Termination
Authors: Zhang Q. Jon , Agarwal Anant K. , Capell Craig , Cheng L. , O'Loughlin Michael  J. , Burk Albert A. , Palmour John W. , Rumyantsev Sergey L. , Saxena T. , Levinshtein Michael E. , Ogunniyi A. , O'Brien Heather , Scozzie Charles
Published: May 2012

In this paper, for the first time, we report 12 kV, 1 cm2 SiC GTOs demonstrated with a novel negative bevel termination, which improves the breakdown voltage by >3.5 kV compared to the conventional multiple-zone Junction Termination Extension (JTE). The significant improvement in the blocking voltage was attributed to the elimination of the electrical field crowding in the periphery of the mesa with conventional JTE termination. This new termination has been used in both electrically and optically triggered SiC GTOs. An ultrafast turn-on speed of 70 ns has been measured on 12 kV, 1 cm2 SiC light triggered GTOs.
Comparison of SiC Thyristors with Differently Etched JTEs
Authors: Pâques Gontran , Scharnholz Sigo , Dheilly Nicolas , Planson Dominique , De Doncker Rik W.
Published: May 2012

This paper presents results attained with SiC GTO thyristors terminated by a single step and a graded etched JTE. The comparison of both types of devices reveals no significant difference in the on-state and switching characteristics but a higher blocking capability of some thyristors with the latter kind of termination. The best devices showed a forward breakdown voltage of nearly 6 kV, which is a distinct progress as against previous results of thyristors with a graded etched JTE. Furthermore, such GTO thyristors have been characterized dynamically for the first time.
Bipolar Degradation in 4H-SiC Thyristors
Authors: Soloviev Stanislav I. , Losee Peter A. , Arthur Stephen , Stum Zachary , Garrett Jerome L. , Elasser Ahmed
Published: May 2012

Bipolar degradation in 4H-SiC thyristors subjected to high current density stress is reported. The thyristor device structure, its fabrication process as well as testing conditions are described. The Electron Beam Induced Current (EBIC) technique was used for defect analysis in testing of both degraded and non-degraded devices. Possible nucleation sites responsible for the generation of observed defects in degraded devices are discussed
A Theoretical and Experimental Comparison of 4H- and 6H-SiC MSM UV Photodetectors
Authors: Lim Jang Kwon , Östlund Ludwig , Wang Qin , Kaplan Wlodek , Reshanov Sergey A. , Schöner Adolf , Bakowski Mietek , Nee Hans Peter
Published: May 2012

This paper reports on fabrication and modeling of 4H- and 6H-SiC metal-semiconductor-metal (MSM) photodetectors (PDs). MSM PDs have been fabricated on 4H-SiC and 6H-SiC epitaxial layers, and their performance analyzed by MEDICI simulation and measurements. The simulations were also used to optimize the sensitivity by varying the width and spacing of the interdigitated electrodes. The fabricated PDs with 2 µm wide metal electrodes and 3 µm spacing between the electrodes exhibited, under UV illumination, a peak current to dark current ratio of 105 and 104 in 4H-SiC and 6H-SiC, respectively. The measured spectral responsivity of 6H-SiC PDs was higher compared to that of 4H-SiC PDs, with a cutoff at 407 nm compared to 384 nm in 4H-SiC PDs. Also the peak responsivity occurred at a shorter wavelength in 6H material. A high rejection ratio between the photocurrent and dark current was found in both cases. These experimental results were in agreement with simulation.
In-Grown Stacking Faults in SiC-CVD Using Dichlorosilane and Propane as Precursors
Authors: Song Hai Zheng , Omar Sabih U. , Rana Tawhid , Chandrashekhar M.V.S. , Sudarshan Tangali S.
Published: May 2012

In-grown stacking faults (IGSFs) were studied in 4H-SiC homoepitaxial growth from a SiH2Cl2-C3H8-H2 system. Most of the IGSFs, start from the epilayer/substrate interface, and exhibit photoluminescence emission peak at 2.58 eV (480 nm) indicating of 8H polytype. The growth parameters, including growth temperature, growth pressure, growth rate, hydrogen etching, et al., varied around the regular growth condition do not show a significant effect on the IGSF generation. Reactor furniture is identified to be a major reason of IGSF formation, especially when the insulation part of the furnace is not completely isolated from the growth zone. Dusting of insulation material is crucial in the formation of IGSFs. When using graphite felt as the insulation material, the IGSF density in the epilayer can be as high at ~104 cm-2. Improvement of the insulation material by using graphite foil reduces the density to 30-100 cm-2. Further reduction of IGSF density to less than 10 cm-2 is achieved by mild pretreatment of the substrate in molten KOH-NaOH eutectic.
High Temperature Silicon Carbide Power Modules for High Performance Systems
Authors: Lostetter Alexander B. , Hornberger J. , McPherson B. , Bourne J. , Shaw R. , Cilio E. , Cilio W. , Reese B. , Heinrichs E. , McNutt Ty , Schupbach Marcelo
Published: May 2012

The demands of modern high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of silicon carbide (SiC) are well known, including high temperature operation, high voltage blocking capability, high speed switching, and high energy efficiency. In this discussion, APEI, Inc. presents two newly developed high performance SiC power modules for extreme environment systems and applications. These power modules are rated to 1200V, are operational at currents greater than 100A, can perform at temperatures in excess of 250 °C, and are designed to house various SiC devices, including MOSFETs, JFETs, or BJTs.
A Compact 5-nH One-Phase-Leg SiC Power Module for a 600V-60A-40W/cc Inverter
Authors: Matsui Kohei , Zushi Yusuke , Murakami Yoshinori , Tanimoto Satoshi , Sato Shinji
Published: May 2012

We have developed a small-volume, high-power-output inverter with a high output power density using SiC power devices. To fully utilize the advantages of SiC power devices, it is necessary to reduce the inductance of the power module. This is done by using a double-layer ceramic substrate, attaining a low inductance of 5 nH. A double pulse test was carried out up to 60 A under a DC voltage of 600 V. The low inductance greatly reduced the surge voltage and the oscillation at the switching transient. The SiC inverter with a volume of 250 cc was assembled using three of the power modules. The cooling performance of the inverter was evaluated at a loss equivalent to an output power of 10 kW, and it was found that the inverter can output 10 kW at a junction temperature (Tj) of about 200°C.
Performance of a 25kW 700V Galvanically Isolated Bidirectional DC-DC Converter Using 1.2kV Silicon Carbide MOSFETs and Schottky Diodes
Authors: Jain Amit K. , McIntosh David , Jones Matt , Ratliff Brian
Published: May 2012

This paper presents the development and experimental evaluation of a 25kW, 700V galvanically isolated bidirectional converter based on silicon carbide (SiC) MOSFETs and Schottky diodes. Compared with a similarly rated silicon (Si) IGBT version, the SiC converter exhibits a 3% improvement in peak efficiency, 2.6 times reduction in total losses, and three times improvement in power density.
Switching Losses in a SiC-Based DC-DC Multilevel Boost Converter
Authors: Mostaghimi Omid , Wright Nicolas G. , Horsfall Alton B.
Published: May 2012

In the aerospace industry where the weight and power density are important design parameters, high frequency operation results in smaller passive components. Furthermore, to achieve a large voltage conversion ratio, which is a goal for payload systems, the use of transformers increases the size and power losses of the system. To fulfill the space and weight requirements, a transformer-less SiC-based DC-DC multilevel converter providing high voltage conversion ratios without an extremely high duty cycle has been realized. The experimental high switching frequency and low current results for a conventional, 3-level and 4-level converter utilizing Si and SiC based COTS diodes are presented. SiC-based multilevel converters show a higher efficiency due to the low reverse recovery and fast switching of the diodes, which results in a higher voltage conversion ratio. This translates to a lower duty cycle to obtain the required output voltage, whilst eliminating the need for complex filtering even under light load conditions.
High Voltage SiC Schottky Diodes in Rectifiers for X-Ray Generators
Authors: Lürkens Peter , Guimaraes P. , Godignon Philippe , Millán José
Published: May 2012

Silicon-Carbide-based semiconductors offer realization of efficient high voltage components, with high switching speed and low conduction losses. SiC Schottky diodes with safe blocking capability of at least 4 kV were produced and characterized. A simulation model for loss determination was developed. Real losses were determined on a small scale test setup and chip temperature distribution was obtained from that, combined with FEM calculation. A full-size rectifier 100 kW/140 kV-SiC-rectifier module with six times higher power density than with conventional Si-technology was realized.
SiC Solid-State Disconnect for High Power System Applications
Authors: Li Xue Qing , Alexandrov Peter , Fursin Leonid , Dries Christopher , Zhao Jian Hui
Published: May 2012

This paper reports the design and experimental demonstration of a novel bi-directional solid-state disconnect (SSD) based on Silicon Carbide (SiC) depletion-mode junction field effect transistors (JFETs) for protecting critical sensitive components in high power systems. The SSD is able to provide a fast disconnect action upon receiving a preset trip current flowing through it and has a very low insertion loss, which makes it suitable for high power applications. For the application in 150kW six-phase power inverter systems, an insertion loss of less than 0.91% and a current fall time of less than 20μs for trip currents of about 800A have been demonstrated experimentally. To the best of our knowledge, there are no other solid-state disconnects available of comparable parameters.
Bipolar Integrated OR-NOR Gate in 4H-SiC
Authors: Lanni Luigia , Ghandi Reza , Zetterling Carl Mikael , Malm B. Gunnar , Östling Mikael
Published: May 2012

An integrated bipolar OR-NOR gate based on emitter coupled logic (ECL) is demonstrated in 4H-SiC. Operated from 27 up to 300 °C on –15 V supply voltage the logic gate exhibits stable noise margins (NMs) of about 1 V in the entire temperature range.
Reliability of Silicon Carbide Integrated Circuits at 300°C
Authors: Vert Alexey V. , Andarawis Emad , Chen Cheng Po
Published: May 2012

Silicon carbide based integrated circuits (ICs) have the potential to operate at temperatures exceeding that of conventional semiconductors such as silicon and silicon on insulator. Analog and digital silicon carbide (SiC) based circuits were fabricated and characterized at room temperature and 300°C. An operational amplifier and a ring oscillator were tested for prolonged period of time to evaluate their stability and reliability at 300°C. More than 1,000 hours was achieved with the operational amplifier without failures and the ring oscillator operated for almost 300 hours.
Conversion of Si Nanowires into SiC Nanotubes
Authors: Ollivier Maelig , Latu-Romain Laurence , Bano Edwige , Mantoux Arnaud , Baron Thierry
Published: May 2012

Carburization of silicon nanowires (NWs), with diameters of about 800 nm and lengths of about 10 µm, under methane at high temperature in order to obtain silicon carbide (SiC) nanostructures is reported here. The produced SiC nanostructures display a tubular shape and are polycrystalline. The as-prepared silicon carbide nanotubes (NTs) were characterized and studied by scanning electron microscopy (SEM), dual focused ion beam – scanning electron microscope (FIB-SEM), transmission electron microscopy (TEM) and Raman spectroscopy. The formation of nanotubes can be explained by the out-diffusion of Si through the SiC during the carburization process.
Growth of SiC Nanowires on Different Planes of 4H-SiC Substrates
Authors: Thirumalai Rooban Venkatesh K.G. , Krishnan Bharat , Levin Igor , Davydov Albert , Sundaresan Siddarth G. , Merrett Joseph Neil , Koshka Yaroslav
Published: May 2012

Growth of SiC nanowires (NWs) on monocrystalline 4H-SiC substrates was conducted to investigate a possibility of NW alignment and polytype control. The growth directions of the NWs on the top surfaces and the vertical sidewalls of 4H-SiC mesas having different crystallographic orientations were investigated. The majority of the NWs crystallize in the 3C polytype with the growth axis. Six orientations of the 3C NWs axis with respect to the substrate were obtained simultaneously when growing on the (0001) plane. In contrast, no more than two NW axis orientations coexisted when growing on a particular mesa sidewall. Growth on a particular {10-10} plane resulted in only one NW axis orientation, giving well-aligned NWs.
Control of the Growth Habit in the Na Flux Growth of GaN Single Crystals
Authors: Imade Mamoru , Konishi Yusuke , Takazawa Hideo , Murakami Kosuke , Imabayashi Hiroki , Todoroki Yuma , Kitamoto Akira , Matsuo Daisuke , Maruyama Mihoko , Yoshimura Masashi , Kitaoka Yasuo , Sasaki Takatomo , Mori Yusuke
Published: May 2012

Seeded growth of gallium nitride (GaN) crystals on a spontaneously nucleated small GaN by the Na flux method was performed. In this study, we attempted to control the growth habit by changing the flux composition (Ga/Na) and by introducing a small amount of additives (Ca and Li). Our experiment clarified that a low Ga composition was preferred to grow high-crystallinity prismatic GaN crystals with a high growth rate. Furthermore, the transparent GaN single crystals with prism shape could be grown by the addition of Ca and Li.
Evolution of Structural and Electrical Properties of Au/Ni Contacts onto P-GaN after Annealing
Authors: Greco Giuseppe , Roccaforte Fabrizio , Lo Nigro R. , Bongiorno C. , Di Franco S. , Prystawko P. , Leszczyński M. , Raineri Vito
Published: May 2012

In this paper the structural and electrical evolution of Au/Ni contacts to p-type gallium nitride (GaN) upon annealing in different atmospheres was monitored. Rapid annealing of the contacts in an oxidizing atmosphere (N2/O2) resulted into a lower specific contact resistance (ρc) with respect to annealing in non-reacting ambient (Ar). The formation of a nickel oxide (NiO) layer was observed on the surface of the sample annealed in N2/O2 ,while was not present at the interface with p-GaN. The improvement of the contacts was associated with a reduction of the Schottky barrier height from 1.07 eV (Ar annealing) to 0.71 eV (N2/O2 annealing), as determined by the temperature dependence of the ρc. Local electrical measurements demonstrated the formation of inhomogeneous barriers. The electrical measurements were correlated with the different microstructure of the annealed contacts.
Large GaN p-n Junction Diodes of 3 mm in Diameter on Free-Standing GaN Substrates with High Breakdown Voltage
Authors: Nomoto Kazuki , Nakamura Tohru , Kaneda Naoki , Kawano Toshihiro , Tsuchiya Tadayoshi , Mishima Tomoyoshi
Published: May 2012

This report describes the first to fabricate GaN p-n junction diodes on free-standing GaN substrates with a 3mm diameter. For the diode of 3 mm in diameter, the specific on-resistance and the breakdown voltage were 124 mΩ•cm2 (at 4.0 V) and -450 V, respectively. Consequently, combination of our material and device processing revealed a record fabricated device size with a high breakdown voltage and low forward leakage current in GaN vertical diodes.
Growth of High Quality 4H-SiC Crystals in Controlled Temperature Distributions of Seed Crystals
Authors: Tsuge Hiroshi , Sato Shinya , Katsuno Masakazu , Fujimoto Tatsuo , Ohashi Wataru
Published: May 2012

Large diameter 4H-SiC single crystal wafers with higher quality are required to improve the yields of devices fabricated onto the SiC wafers. For crystal growths with higher quality, it is important to prepare seed crystals with lower defect densities. In particular, the edge part of the seed has to be prepared with considerable care because the crystallinity of the enlarged part of grown crystals depends much upon the surface condition of the seed crystal during radial expansion growth. We found that growth with fewer defect and micropipe densities, specifically at the periphery of the crystal, is possible by utilizing in-situ etching process for the seed crystal surface. We have also performed intense numerical calculations of the temperature distribution around the seed surface, and discussed growth conditions which cause the in-situ etching effective to improvement of the crystallinity in enlarged crystals.
Electrical Characterisation of Defects in Polycrystalline B-Doped Diamond Films
Authors: Elsherif Osama S. , Vernon-Parry Karen D. , Evans-Freeman Jan H. , May Paul W.
Published: May 2012

Admittance spectroscopy (AS) and deep level transient spectroscopy (DLTS) have been applied to B-doped thin polycrystalline diamond films deposited on p+-silicon by hot filament chemical vapour deposition. Films with two boron concentrations (1.5×10^19 cm-3 and 4×10^19 cm-3) were selected to study the effect of B concentration on the electronic states in CVD-diamond. We have investigated whether these deep states arise from point or extended defects. DLTS and AS find two hole traps, E1 (0.29±0.03 eV) and E2 (0.53±0.07 eV), in both films. A third level, E3 (0.36±0.02 eV) was also detected in the more highly doped film. The defect levels E1 and E2 exhibited behaviour typical of extended defects, which we suggest may be due to B segregated to the grain boundaries. In contrast, the defect level E3 exhibited behaviour characteristic of an isolated point defect, which we attribute to B-related centres in bulk diamond.
Fabrication and Characterization of n-ZnO/p-SiC Heterojunction Diode
Authors: Guziewicz M. , Jung W. , Kruszka R. , Domagala J. , Piotrowska Anna B. , Gołaszewska K. , Wachnicki L. , Guziewicz E. , Godlewski Marek
Published: May 2012

ZnO as well as SiC are wide bangap materials with prospective electronic applications. Very good lattice matching of the materials allowed formation a n-ZnO/p-SiC heteroepitaxial junction. The n˗ZnO film was epitaxially grown onto the p-SiC substrate using the atomic layer deposition method. The fabricated p-n diode was studied by I-V and C-V characteristics as well as by impedance spectroscopy. The diode shows a high rectifying ratio of 107 and an ideality factor of 1.21.
Effects of Substrate Temperature on the Electrical and the Optical Properties of N-Type ZnO/P-Type 4H-SiC
Authors: Jung Ji Chul , Kim Ji Hong , Do Kang Min , Moon Byung Moo , Joo Sung Jae , Bahng Wook , Kim Sang Cheol , Kim Nam Kyun , Koo Sang Mo
Published: May 2012

We investigated the effect of the substrate temperature on the electrical and the optical properties of ZnO/4H-SiC structures. The n-type ZnO layer was grown on p-type 4H-SiC substrate by pulsed laser deposition to form p-n hetero-junction diode structure. The n-type ZnO thin films were deposited by pulsed laser deposition at different temperatures of 200, 400, and 600 °C, respectively. It was shown from transmission line method (TLM) and auger electron spectroscopy (AES) data that the sheet resistance of ZnO on SiC was increases from ~760 Ω/square to ~4000 Ω/square as the deposition temperature increases and the oxygen outdiffusion decreases. The I-V characteristics with and without illumination has also been studied.
Use of Vanadium Doping for Compensated and Semi-Insulating SiC Epitaxial Layers for SiC Device Applications
Authors: Krishnan Bharat , Thirumalai Rooban Venkatesh K.G. , Kotamraju Siva Prasad , Merrett Joseph Neil , Koshka Yaroslav
Published: May 2012

Vanadium doping from SiCl4 source during epitaxial growth with chlorinated C and Si precursors was investigated as a mean of achieving compensated and semi-insulating epitaxial 4H-SiC layers for device applications. Thin epilayers were grown at 1450°C with a growth rate of ~6 μm/h. Experiments at 1600°C resulted in the growth rates ranging from 60 to 90 µm/h producing epilayers with thickness above 30 µm. V concentrations up to about 1017cm-3 were found safe for achieving defect-free epilayer surface morphology, however certain degradation of the crystalline quality was detected by XRD at V concentrations as low as 3-5x1015 cm-3. Controllable compensation of nitrogen donors with V acceptors provided low-doped and semi-insulating epitaxial layers. Mesa isolated PiN diodes with V-acceptor-compensated n- epilayers used as drift regions showed qualitatively normal forward- and reverse-bias behavior.
Progress in Growth of Thick Epitaxial Layers on 4 Degree Off-Axis 4H SiC Substrates
Authors: Zhang Jie , Chung Gil Yong , Sanchez Edward , Loboda Mark J. , Sundaresan Siddarth G. , Singh Ranbir
Published: May 2012

This paper reports the progress of the thick epitaxy development at Dow Corning. Epiwafers with thickness of 50 – 100 m have been grown on 4° off-axis 76mm 4H SiC substrates. Smooth surface with RMS roughness below 1nm and defect density down to 2 cm-2 are achieved for 80 - 100 m thick epiwafers. Long carrier lifetime of 2 – 4 s are routinely obtained, and low BPD density in the range of 50 down to below 10 cm-2 is confirmed. High voltage JBS diodes have been successfully fabricated on these wafers with thick epitaxial layers.
Surface Morphology Evolution after Epitaxial Growth on 4°Off-Axis 4H-SiC Substrate
Authors: Jegenyes Nikoletta , Soulière Véronique , Cauwet François , Ferro Gabriel
Published: May 2012

Chemical vapour deposition in a cold wall reactor working at atmospheric pressure was used to study the homoeptaxial growth of 4H-SiC on 4°ff misoriented substrates from silane and propane precursors. The effect of various growth parameters (temperature 1450-1650°C, C/Si ratio 1-7, thickness 2.5-10 µm) were studied in order to determine the best conditions for obtaining smooth surfaces after epitaxy. It is shown that the main source of roughness is surface undulation which easily appears during growth, especially at low C/Si ratios and high temperature (up to 1600°C). Temperatures above 1600°C and C/Si ratio of 1 give the best results. When reducing temperature, a trade-off has to be found between defects formation and surface undulation.
Study of the Impact of Growth and Post-Growth Processes on the Surface Morphology of 4H Silicon Carbide Films
Authors: Camarda Massimo , Canino Andrea , Fiorenza Patrick , Bongiorno Corrado , Severino Andrea , Raineri Vito , La Magna Antonino , La Via Francesco , Mauceri Marco , Abbondanza Giuseppe , Pecora Antonino , Crippa Danilo
Published: May 2012

In this paper we study the surface morphology of <11-20> 4° degree off, silicon terminated, 4H Silicon Carbide (4H-SiC) in terms of growth parameters and post growth argon thermal annealing. We find that out-of-equilibrium conditions favor the reduction of the surface roughness. Furthermore, we find preliminary indications that the same growth parameters that lead to the reduction of the surface roughness promote also a reduction of (1,3) and (4,4) stacking faults density.
Behavior of Particles in the Growth Reactor and their Effect on Silicon Carbide Epitaxial Growth
Authors: Rana Tawhid , Song Hai Zheng , Chandrashekhar M.V.S. , Sudarshan Tangali S.
Published: May 2012

Formation of particles and their effect on SiC epitaxial growth in the CVD reactor is investigated. Particle induced defects in the epilayer at different gas decomposition conditions are discussed. A higher number of pits with larger diameters are observed in the epilayer for conditions where gases decompose later in the gas injector tube (i.e. nearer to the substrate). On the other hand, the number and size of these pits reduce for the condition where gas decomposes earlier in the tube. To investigate the effect of particles during the growth, various particles with different size, shape and compositions are intentionally placed on the substrate surface before epitaxial films are grown. Samples are mapped and compared at similar locations in the pre-growth, post growth and post-etch (by molten KOH) conditions. It is found that the nature of particle induced defects depends primarily on size and shape of particles.
Influence of Growth Mechanism on Carrier Lifetime in On-Axis Homoepitaxial Layers of 4H-SiC
Authors: Hassan Jawad , Lilja Louise , Booker I.D. , Bergman Peder , Janzén Erik
Published: May 2012

In this report we present homoepitaxial growth of 4H-SiC on Si-face, nominally on-axis substrates with diameters up to 76 mm in a hot-wall chemical vapor deposition reactor. A comparatively low carrier lifetime has been observed in these layers; local variations in carrier lifetime are different from standard epilayers on off-cut substrates. The properties of the layers were studied with focus on charge carrier lifetime and its correlation with starting growth conditions, inhomogeneities of surface morphology and different growth mechanisms.