(Invited) Multiscale Modeling of Atom Scale Defects for Electronic Devices Engineering
Authors: Larcher Luca , Nardi Federico , Pramanik Dipankar , Padovani Andrea 
Published: May 2020

We present in this paper a multiscale modeling platform that is used to study the effect of atomic level defects on the electrical characteristics of nanoscale devices. This allows identifying ways to engineer material (and defects) and device properties to achieve optimum performance and reliability in logic and memory circuits.

Atom scale defects in multilayer thin film material stacks have a profound effect on the electrical performance and reliability of nanoscale electronic devices. These defects include both point defects such as vacancies and interstitial ions as well as extended defects such as grain boundaries, dislocations.

We developed a multiscale modeling platform connecting the atomic material properties to the electrical device performance, which allows understanding the optimum material characteristics for different types of logic devices and memory cells. These include logic devices, conventional memories (e.g. DRAM, 3D-NAND) as well as emerging devices (e.g. RRAM, PCM). The simulations allow learning how to scale these technologies through material and process improvement and how to co-optimize materials and devices.

I. MULTISCALE MODELING

Figure 1 shows the flowchart of the multiscale multiphysics simulation platform along with its main blocks [1]. The ab-initio material properties relevant for the electrical device performances (e.g. bandgap, permittivity, defects energies, defect diffusion barrier ...) are computed using DFT calculations (gray portion). These material properties are then used for the device level simulations (green portion), and the output device electrical characteristics allows calibrating the circuit simulations (yellow portion). The device simulator couples classical and quantum charge transport mechanisms with stress induced material changes (e.g. atomic breakage, creation and diffusion of ions/vacancies), whose occurrence probability is calculated by accounting for the temperature increase and power dissipation associated with the current.

The charge transport mechanisms include drift/diffusion in conduction band (CB) or valence band (VB), which is the primary carrier transport mode in semiconductors, and Trap Assisted Tunneling (TAT), which is the dominant mechanism in dielectrics and amorphous semiconductors. Defects with energy levels in the bandgap play a crucial role in the conduction, assisting electron transfer. The charge transport is coupled to the kinetics of atomic level material modifications caused by electrical and thermal stresses encompassing distortion and breakage of bonds, diffusion of vacancies and interstitial ions leading to changes in local fields, stoichiometry and phase changes including ferroelectricity. This allows modeling the reliability of devices to be calculated in addition to static electrical characteristics as well as the device variability.

In this presentation, we will show how this multiscale simulation platform can be used to extract defect properties for advanced logic stack as well as to understand the physics of operation of RRAM devices.

II. UNDERSTANDING DEFECT IMPACT ON LOGIC STACKS

The multiscale approach presented in Section II can be used to characterize and understand the role of the dielectric defects on device electrical characteristics and reliability. Oxide defects are at the bases of the most relevant reliability phenomena in both logic and memory devices, e.g. Random Telegraph Noise (RTN), Bias Temperature Instabilities (BTI), Stress Induced Leakage Currents (SILC) and breakdown (BD). Identifying their nature and their spatial/energy distributions in the dielectric stack is crucial for process optimization and device operation/reliability improvement. The developed simulation framework implements a fast defect spectroscopy (DS) technique based on the modeling and simulation of the charge transport within the dielectric. This technique is applied to identify the defects responsible for I-V, CV. GV in a variety of different stack configurations.

III. UNDERSTANDING RRAM OPERATIONS

We used this modeling platform proposed to investigate the kinetics of the operation processes of HfO2-based RRAM devices. Forming, set and reset operations are consistently described within the modeling framework described in Section II, accounting for species (i.e. O ions and vacancies) generation, recombination and diffusion.

Simulations can reproduce the evolution of the current simulated for a full cycle comprised by forming, reset and set operations. The simulated current exhibits the expected features: an abrupt jump at forming, a gradual reduction in reset, and a lower set voltage compared to forming. The evolution of potential, temperature and generated oxygen vacancies and ions during simulations can be monitored to gain insights on the mechanisms controlling device operations, including the structural changes such as the creation and disruption of the conductive filament, as well as the high temperature reached during forming.

IV. REFERENCES

[1] GINESTRATM , http://www.mdlsoft.com

Fig 1: Schematic flow chart describing the main blocks of multiscale simulation platform.

Figure 1