(Invited) Epitaxial Process Development and Challenges for Advanced SiGe BiCMOS
Authors: Deprat Fabien , Vives Jeremy , Gauthier Alexis , Frauenrath Marvin , Lespiaux Justine , Verdier Stephane , Ferrandon Alice , Oudot Evan , Ribot Pascal George , Chevalier Pascal 
Published: December 2024

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) are used daily, mainly in the communication field. Their co-integration with Complementary Metal Oxide Semiconductor (CMOS) technology, i.e. BiCMOS, enables versatile microchips that combine analog, radio-frequency and digital functions. Applications that drive the development of BiCMOS technologies today are Low Earth Orbit (LEO) satellite communications, for which the minimum noise figure of SiGe HBT (NFMIN) between 10 and 30 GHz is one of the most critical figures of merit on the receiver side. It is expected that BiCMOS will play a significant role in the 6G infrastructure, in particular for communications in the D-band spectrum (110-170 GHz), for which the challenge at HBT level is to demonstrate maximum oscillation frequency fMAX > 500 GHz.

Benefitting from mature CMOS technologies, the smallest CMOS node used in BiCMOS chips is the 45 nm partially depleted silicon on insulator [1]. STMicroelectronics has been using the 55 nm node since 2014 [2]. These nodes are today sufficient to address the digital content of the targeted circuits, while offering the right performance/cost trade-off. Although the HBT performance depends on lateral scaling too, it is mainly driven by the 1D dopant profile. Multiple Si and SiGe layers are grown by Reduced Pressure-Chemical Vapor Deposition (RP-CVD) epitaxy, defining the core of the device. For a self-aligned architecture such as STMicroelectronics’ EXBIC architecture, four epitaxy steps with different doping levels are required (Fig. 1) [3]. Improvement of key electrical parameters such as NFMIN and fMAX depends on the optimization of these epitaxies.

Specifically, the collector epitaxy can be performed by non-selective or selective epitaxy, each with its advantages and drawbacks. Non-selective epitaxy is performed early in the BiCMOS process flow, with no thermal budget impact on the CMOS process. This kind of epitaxy is also cheaper but can cause auto-doping at the epitaxial interface [4] and put constraints on the collector integration, that are solved by the selective epitaxy of the collector. This scheme is used in the latest devices from both STMicroelectronics [3] and GlobalFoundries [5].

The transit time of electrons through the base is determined by its thickness and its composition. Significant performance gains have been achieved by switching from pure Si to a graded SiGe base architecture. The bandgap variation due to the graded SiGe composition creates a pseudo-electric field that accelerates the minority carriers transport through the base and limits electron-hole recombination. The addition of carbon into the base limits the boron diffusion and reduces the base thickness, further improving performance. However, only substitutional carbon atoms are required while interstitial carbon atoms must be avoided. The amount of carbon, incorporated in fully substitutional sites, is controlled by the silicon precursor used during RP-CVD epitaxy. At a given temperature it has been shown that a more reactive silicon precursor allows for better substitutional carbon incorporation. By switching from SiH2Cl2 (DCS) to SiH4, the amount of substitutional carbon atoms was increased by 250 % [6]. Following this idea, Si2H6 has been introduced as a silicon precursor to achieve even better substitutional carbon incorporation due to its higher reactivity [7].

The emitter process is usually performed by non-selective Si:As epitaxy. This type of epitaxy produces polycrystalline Si:As with a monocrystalline Si:As core above the crystalline base. The emitter resistance can be reduced by processing a fully monocrystalline emitter. A possible solution involving low temperature deposition and solid phase epitaxial regrowth is proposed [8].

An overview of the existing problems for each epitaxy step will be given, outlining potential solutions to increase HBT performance to meet customer requirements.

[1] J. Pekarik et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 1-4 (2021)

[2] P. Chevalier et al., IEEE International Electron Devices Meeting (IEDM),77-79 (2014)

[3] A. Gauthier et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 187-190 (2023).

[4] P. Jerier and D. Dutartre, J. Electrochem. Soc. 146 ,331 (1999)

[5] J. Pekarik et al., ECS Transactions, 109, 141 (2022)

[6] F. Brossard et al., International SiGe Technology and Device Meeting (ISTDM), 1-2 (2006)

[7] J. Vives et al., ECS Transactions, 109 (4), 237-248 (2022)

[8] F. Deprat et al., ECS Transactions, 109, 159 (2022)

Figure 1