(Invited) Bottom-up Silicon Nanostructures: A Toolbox for Integrated on-Chip Edlcs
Authors: Gaboriau Dorian , Brachet Mylène , Boniface Maxime , Aradilla David , Aldakov Dmitry , Bidan Gerard , Le Bideau Jean , Brousse Thierry , Gentile Pascal , Sadki Said 
Published: February 2020

The current trend towards miniaturized and autonomous electronic devices requires innovative energy storage solutions. For instance, autonomous micro-sensor networks or implantable medical devices would need a robust power source with an extended cyclability as well as a large power density, which might be out of the scope of conventional battery technologies. For such applications, Electrochemical Double Layer Capacitors (EDLCs) are promising alternatives, and their integration “on-chip” could allow tremendous innovations to emerge.1 However, finding a suitable “on-chip” EDLC technology implies addressing key challenges, such as temperature resistance, silicon industry compatibility and good electrochemical performances on a small footprint.

Although often considered as an “unconventional” supercapacitive electrode material, bottom-up, highly-doped nanostructured silicon offers extremely promising characteristics, both as bare electrode material in EDLCs2, 3 or as current collector for pseudo-capacitive materials.4 The fine morphological tuning of the nanostructure allowed by the bottom-up approach permits a careful design of the electrodes’ architectures, with considerable freedom compared to other techniques. Such latitude allows the optimization of porosity as well as ionic and electronic pathways while keeping robust mechanical performances, depending on the target application and other requirements such as the electrolyte, functionalization by pseudo-capacitive materials or other surface modifications. Moreover, using silicon as EDLC electrode material instead of carbon allows developments towards “on-chip” integration and potential production scale-up considerably easier using standard silicon industry processes for small micro-sized energy storage devices.

Nanostructures such as silicon nanowires (Si-NWs) or nanotrees (Si-NTrs) demonstrated excellent cyclability with more than 1 million cycles of galvanostatic charge/discharge under a 4 V wide electrochemical windows in EMI-TFSI ionic liquid, with large power densities and good capacitance values.2,3 The aim of the present study is to provide insight on the potentialities of bottom-up silicon nanostructures as a toolbox for designing “on-chip” energy storage devices, by addressing several key challenges.

In particular, the accessible surface area of electrodes can be greatly improved through careful optimization of the nanostructure morphologies, resulting in larger capacitances. A systematic study was conducted over different growth parameters, leading to interestingly diverse morphologies ranging from hyper branched Si-NTrs to a 3D interpenetrated highly conductive silicon nanowires network. We demonstrated capacitance values as high as 1.7 mF.cm-2 in a 3 electrodes cell and excellent energy and maximum power densities for symmetric 2 electrodes devices (respectively 2.8 mJ.cm-2 and 235 mW.cm-2) while retaining 80 % of the capacitance after 106 galvanostatic charge/discharge cycles. Additionally, a quasi-ideal capacitive behavior was retained throughout long term cycling, with linear and symmetric galvanostatic profiles even after millions of cycles.

Furthermore, surface modification of the silicon nanostructures by Atomic Layer Deposited thin Al2O3 films boosted electrochemical performances, allowing symmetric 2 electrode devices to reach an unprecedented cell voltage of 5.5 V, improving energy and maximum power densities compared to unmodified nanostructured silicon. The cyclability was also largely enhanced, with only 3% capacitance fade after 106 galvanostatic charge/discharge cycles at 4 V, and no further degradation even after several subsequent 105 cycles over 5 V.

Finally, “on-chip” integrated devices were designed by growing optimized nanostructures on an interdigitated electrode pattern, demonstrating the compatibility of our material with standard micro-patterning processes. In combination with a solid-state ionogel electrolyte, the devices can also display remarkable electrochemical performances over a wide temperature range (between 15° C and 100° C), and a resistance to the “solder reflow” conditions, paving the way to fully integrated “on-chip” micro-supercapacitors which fulfill the key challenges for future applications.

(1) Beidaghi, M.; Gogotsi, Y. Energy & Environ. Sci.
2014, 7 (3), 867-884

(2) Thissandier, F. ; Gentile, P. ; Pauc, N. ; Brousse, T. ; Bidan, G. ; Sadki, S. Nano Energy
2014, 5, 20-27

(3) Thissandier, F. ; Gentile, P. ; Brousse, T. ; Bidan, G. ; Sadki, S. J. Power Sources
2014, 269, 740-746

(4) Aradilla, D. ; Gaboriau, D. ; Bidan, G. ; Gentile, P. ; Boniface, M. ; Dubal, D. ; Gómez-Romero, P. ; Wimberg, J. ; Schubert, T.J.S. ; Sadki, S. J. Mater.
Chem. A
2015, 3, 13978-13985

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