bluuebunny/crossref_metadata_2025 huggingface dataset:
Optimizing Middle of Line (MoL) Contact Cleaning to Preserve Tungsten (W) Integrity in Advanced Technology Nodes
Authors: Singh SherJang , Muralidhar Pranesh , Das Kakoli , Scott Silas
Published: October 2015

Advanced node (sub 2Xnm) chip manufacturing employs new fabrication techniques as well as materials. This work is focused on the Middle of Line (MoL) contact cleaning. An advanced cleaning process is developed based on the electrochemical compatibility and interactions between the chosen chemistry and exposed layers as well as contaminants to be removed. The cleaning efficacy in the trenches is verified by measuring contact resistance as well as particle/flake inspections. Tungsten integrity is verified with bright field microscopy and damage to inter layer dielectrics is monitored by measuring trench and contact critical dimensions. Other structural interactions were studied with TEM imaging. The new cleaning process yielded substantially higher number of functional die as compared to POR (Process of Record).
Enhanced Point of Use Filtration for Cleaning without Small Particle Addition
Authors: Kweskin Sasha J , Chen Pippen , Ham SunYoung , Phely-Bobin Thomas , Patel Ami
Published: October 2015

Enhanced liquid filtration for critical cleans is essential for particle and contamination reduction. Tighter and cleaner base membranes offer a path for reduced defect adders. Particle adsorption is investigated on an immersed wafer surface in dilute HF and rinse applications. Systematic studies of immersion time, bath life and high volume wafer production data are required to isolate the particle contribution and quantify process improvements. Wet particle defectivity of a cleaning process was evaluated before and after filter installation. Little difference in filter performance is observed at >37 nm, while clear improvements are found at smaller bin sizes <37 nm. Point of use filtration with increased retention efficiency translates into better performance, especially for very small particles.
(Invited) Silicon-Based Nanocomposites for Thermoelectric High Temperature Waste Heat Recovery
Authors: Schierning Gabi , Wiggers Hartmut , Schmechel Roland
Published: October 2015

Thermoelectric generators can recover waste heat from high temperature heat sources. Given a scalable and affordable technology, this may be part of a future energy mix. For this, suitable thermoelectric converter materials need to be indentified and their efficiency improved. Besides, thermoelectric generators may also be further developed for high temperature applications. We here present results on silicon-based nanocomposites and thermoelectric generators which can meet these criteria.
(Invited) Electrodeposited Micro Thermoelectric Module Design for Hybrid Semiconductor Laser Cooling on a Silicon Photonics Platform
Authors: Enright Ryan , Lei Shenghui , Mathews Ian , Cunningham Graeme , Frizzell Ronan , Shen Alexandre
Published: October 2015

Integrated silicon photonics has emerged as a scalable solution to meet the demands for increased bandwidth in communication networks. However, integration introduces new thermal challenges for active photonic device performance. Traditionally, temperature sensitive devices have been isolated and cooled using centimeter-scale thermoelectric modules. An alternative approach is to integrate thermoelectric temperature control at the device level that simultaneously provides targeted cooling for individual temperature sensitive devices and reduces the footprint of the thermal solution to enable full optoelectronic integration. Here we present the design of a micro thermoelectric cooler based on electrodeposited bismuth telluride integrated around a hybrid laser. We briefly outline the thermal requirements to ensure good hybrid laser performance. We then develop a multiphysics numerical model of the hybrid laser with integrated μTEC and assess our design in terms of system-level relevant operating temperatures. Our results suggest that electrodeposited μTECs can meet the thermal requirements of active photonics devices in silicon photonics under realistic operating conditions.
(Invited) Smartphones: Driving Technology to More than Moore 3-D Stacked Devices/Chips and More Moore FinFET 3-D Doping with High Mobility Channel Materials from 20/22nm Production to 5/7nm Exploratory Research
Authors: Borland John O
Published: October 2015

3-D bulk-FinFET at 22nm node uses (551) 8o tapered Fin sidewall with 45o high tilt implantation for doping, eSiGe S/D for PMOS channel compressive strain and amorphous implant SPC (solid phase crystallization) dislocation defects for NMOS channel tensile strain. For 14nm node taller Fins with vertical sidewalls and partial recess embedded n+ S/D was added. 7/10nm node will use direct high mobility channel materials 50% SiGe to 100% Ge. To avoid CVD Ge or SiGe epi defects liquid phase crystallization (LPC) by laser melt annealing is an alternative using amorphous-Ge dose control deposition by ion implantation and at 5nm node gate-all-around (GAA) nano-wire. Residual implant damage into Ge material creates high level of acceptors up to 7E19/cm3 requiring high temperature annealing above 600oC to annihilate and establish stable p+ or n+ dopant activation for ultra-shallow junctions. For USJ n+ junctions in Ge, melt controlled junction depth using Sb dopant results in highest dopant activation >1E21/cm3 at sub-10nm junction depth. Si-capping layer offers lowest n+ Ge junction leakage and Sn co-implantation enables surface strain-Ge engineering for higher channel mobility.
(Invited) Temporary Bonding with Polydimethylglutarimide for Residue-Free Layer Transfer and 3-D Integration
Authors: Matsumae Takashi , Koehler Andrew D. , Greenlee Jordan D , Anderson Travis J , Baumgart Helmut , Jernigan Glenn G , Hobart Karl D , Kub Francis J
Published: October 2015

Bonding of lift off resist (LOR) was performed to realize temporary wafer bonding without residue. Bonding process conditions such as spin speed, pre-bake temperature, and bonding temperature were optimized to obtain a large bonded area with high bond strength. Under optimized process conditions, a bonded area covering over 98% of the wafer surface, with a room temperature bond strength of nearly 5 J/m2 is achieved. During razor blade testing, fracture often occurs at the Si wafer. Moreover, debonding using an N-Methyl-2-pyrrolidone (NMP)-based solvent left the wafer surface extremely small amount of residue. Thus, the optimized bonding processed developed in this research is suitable for a clean temporary bonding process.
(Invited) Si Photonics and Recent Challenges for on-Chip WDM
Authors: Wada Kazumi , Zhang Z. , Yako M. , Ju K. , Kawai N.J.
Published: October 2015

The present paper proposes a new platform of Si photonics for on-chip dense wavelength division multiplexing (DWDM). The proposed SiNx platform deposited by physical vapor deposition (PVD-SiNx) is robust against thermal fluctuation on a Si chip because of its small thermo-optics coefficient of SiNx. The presented platform can be fabricated in the CMOS back-end-of-line and only needs bulk Si wafers.
(Invited) Multifunctional Technology with Monolithic Integrated THz-, Photonic- and µ-Fluidic Modules
Authors: Mai Andreas , Lischke Stefan , Wietstruck Matthias , Zimmermann Lars , Kaynak Mehmet , Tillack Bernd
Published: October 2015

In this paper we present a multifunctional technology platform with different monolithic integrated modules like THz devices, i.e. complementary SiGe heterojunction bipolar transistors, silicon photonics components in particular Ge-PIN photo detectors and finally the wafer-level integration of µ-fluidic channels for sensor applications. Challenges during the monolithic integration of these different modules were reviewed and necessary process adaptations discussed in order to enable a co-integration.
(Invited) Electrical Properties of Group 4 Metal-Nitride/Ge Contacts and the Application to Ge Optoelectronic Devices
Authors: Nakashima Hiroshi , Yamamoto Keisuke , Wang Dong
Published: October 2015

Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS devices, the source/drain (S/D) junctions are desired to be composed by metal/Ge contacts. However, the Fermi-level pinning impedes the embodiments, by which the formation of a contact with a low electron barrier height (ΦBN) is very difficult. We have found that a TiN/Ge contact deposited by sputtering is useful for a low ΦBN contact. In this paper, we present the electrical properties and interfacial structures of the TiN/Ge contact. Furthermore, we also present the electrical properties and interfacial structures of ZrN/Ge and HfN/Ge contacts, which are in the same group-4 transition-metal nitrides. As an application to the optical device, we present the fabrication and device performance of light emission diodes with lateral TiN/Ge/HfGe structures.
Self-Assemble Formation of Ge Dots on Si(100) via C/Ge/C/Si Structure
Authors: Itoh Yuhki , Kawashima Tomoyuki , Washio Katsuyoshi
Published: October 2015

Formation of Ge dots via C2/Ge/C1/Si structure through solid-phase epitaxy by subsequent annealing at 650C in a molecular beam epitaxy chamber was investigated. The dot density increased with C1 coverage similar to the case of Ge/C1/Si structure. This suggests that Si-C bonds at Ge/Si interface are effective to form small and dense Ge dots. The smallest and densest dots were formed for C1 = 0.5 ML and C2 = 0.1 ML with mean diameter and dot density of 28.3 nm and 9.6 × 1010 cm-2, respectively. However, the dot size and density of C2/Ge/C1/Si structure was 1.3 times lager and 0.6 times lower than those of Ge/C1/Si structure in the case of C1 = 0.5 ML. As a result, it was found that Ge dots became large due to interference with the effect of reducing dot size in Ge/C1/Si structure.
(Invited) Challenges of Energy Band Engineering with New Sn-Related Group IV Semiconductor Materials for Future Integrated Circuits
Authors: Zaima Shigeaki , Nakatsuka Osamu , Yamaha Takashi , Asano Takanori , Ike Shinichi , Suzuki Akihiro , Kurosawa Masashi , Takeuchi Wakana , Sakashita Mitsuo
Published: October 2015

We report our recent researches and developments of Ge1−x
Sn
x
and related group-IV semiconductor materials for the device integration on an Si nanoelectronics platform. We investigated the energy band engineering and crystal growth technology for thin films of Ge1−x
Sn
x
, Si1−x
Sn
x
, and related ternary alloys. The energy band structure and band alignment of these semiconductor materials have been experimentally evaluated and discussed. Also, the effect of a Ge1−x
Sn
x
interlayer on the electronic property at the metal/Ge interface has been investigated.
(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions
Authors: Tomioka Katsuhiro , Fukui Takashi , Motohisa Junichi
Published: October 2015

Tunnel field-effect transistors (TFETs) have been attracting much attention as building-blocks for future low-power integrated circuits. Here we report recent progress in TFETs with surrounding-gate architecture and III-V nanowire/Si heterojunctions. We also discuss guidelines or obtaining steep-slope turn-on behavior in these devices.
(Invited) Material and Device Integration for Hybrid III-V/SiGe CMOS Technology
Authors: Deshpande Veeresh Vidyadhar , Djara Vladimir , Caimi Daniele , O'Connor Eamon , Sousa Marilyne , Czornomaz Lukas , Fompeyrine Jean
Published: October 2015

A dense co-integration of nano-scaled InGaAs n-FETs and SiGe p-FETs is envisaged for future low power and high performance CMOS in sub-10 nm regime. It is, therefore, essential to have a scalable material and device integration scheme for such a hybrid CMOS. In this paper we report InGaAs integration methods on large scale Si substrates through wafer bonding or selective epitaxy. We then show high performance InGaAs-OI device integration routes. Based on these integration schemes, we further discuss strategies for scaled InGaAs/SiGe hybrid CMOS in 2D and 3D integration platforms.
(Invited) Scavenging Kinetics of Interfacial SiO2 in HfO2/SiO2/Si Gate Stacks
Authors: Toriumi Akira , Li Xiuyan
Published: October 2015

Scavenging kinetics of ultra-thin-SiO2 interface layer (IL) in HfO2/SiO2/Si stacks has been investigated by paying attention to both oxygen (O) and silicon (Si) atom movements and to SiO2/Si interface reaction. SiO2/Si interface serves as a stage that the oxygen vacancy (VO) is converted to Si release from SiO2 with the help of Si substrate. It is strongly suggested that the substrate is not consumed, and that Si in SiO2 does not grow on the substrate in the scavenging.
(Invited) High-Resolution Photoemission Study of High-k Dielectric Bilayer Stack on Ge(100)
Authors: Miyazaki Seiichi , Ohta Akio
Published: October 2015

Precise determination of energy band alignment of high-k dielectric bilayer stack on Ge(100) has been demonstrated based on the analysis of the photoemission spectra. In the analysis of energy loss signals of O 1s photoelectrons, both elimination of overlapped signals such as Hf 4s and Ge-LMM Auger lines and discrimination of signals from each layer based on photoelectron take-off angle dependence are crucial for accurate determination of energy band gaps. The combination of the analyses of valence band spectra and of energy loss signals of primary core-line(s) taken at different photoelectron take-off angles enables us to determine the energy band offsets and band line-ups of multiple heterojunctions in a non-distractive way.
(Invited) Negative Capacitance Using Ferroelectrics for Future Steep-Slope MOSFETS
Authors: O'Neill Anthony
Published: October 2015

Effective negative capacitance has been postulated in ferroelectrics because there is hysteresis in plots of polarization-electric field. In future integrated circuits, the incorporation of negative capacitance into MOSFET gate stacks would reduce the sub-threshold slope, enabling low power operation and reduced self-heating. As a step towards meeting this challenge, effective negative capacitance is demonstrated at room temperature in metal-insulator-metal capacitors, where it is stabilized by the presence of a paraelectric material.
(Invited) Effect of Individual Dopants in Nano-SOI-MOSFETs and Nano-pn-Diodes
Authors: Tabe Michiharu , Moraru Daniel , Samanta Arup , Tyszka Krzysztof , Tan Hoang Nhat , Takasu Yuki , Jablonski Ryszard , Anh Le The , Mizuta Hiroshi , Mizuno Takeshi
Published: October 2015

Recently, individual dopant atoms have been utilized as naturally-created quantum dots (QDs) that allow the control of single-carrier tunneling transport in field-effect transistors (FETs), typically at low temperatures. It has been also reported that a few coupled-dopants can form a relatively larger and more complex QD, which may be, however, more practical than a single-dopant QD in terms of fabrication processes and/or elevated-temperature operation. Such discreteness of dopants in nanostructures, down to the level of individuality of dopants, has been observed not only in FETs, but also in nanoscale pn-diodes. Here, we outline results of single-electron tunneling transport via donors in FETs in the regime of low concentration (individual donors) and high concentration (clustered or coupled donors). We also show basic results of current enhancement in low-dimensional Esaki diodes due to tunneling through dopants. Finally, observation of dopant potentials by Kelvin probe force microscopy is described.
(Invited) Silicon Field Emitter Array Photocathode
Authors: Shimawaki Hidetaka , Nagao Masayoshi , Neo Yoichiro , Mimura Hidenori , Wakaya Fujio , Takai Mikio
Published: October 2015

Photo-assisted electron emission from a p-type silicon field emitter array (FEA) excited by laser pulses with 405 nm wavelength is investigated for generating electron bunches at high frequency. By using a volcano structure, the photoresponse of the current pulses is less than 2 ns, which is limited by the response time of a used current amplifier. It demonstrates that an optimally designed volcano-structured silicon FEA is a promising photocathode for the applications of vacuum electronic devices based on short electron beam.
Process Optimization on Self-Aligned Double Patterned Fin Formation
Authors: Zhang Haiyang , Wang Yan , Xiao Fangyuan
Published: October 2015

In this work, we focused on self-aligned-double-patterning (SaDP) Fin etch process and investigated some well-known issues such as dense-isolated loading, pitch-walking performance and line width roughness (LWR) from the point of view of various advanced plasma techniques. Results indicate the introduction of bias pulsing scheme and mixed mode pulsing (MMP) could rigorously control the loading between dense and isolated patterns for the formation of both mandrel and Fin. The synchronous pulsing scheme has also been demonstrated to play an important role on the formation of almost flat spacer top in spacer etch. This could definitely benefit the subsequent pitch walking performance. Besides, we also attempted various techniques such as core material, plasma ribbon beam and chemical down-stream etch (CDE) to improve mandrel LWR. Finally, we demonstrated Fin formation could be greatly improved.
(Invited) Performance of Graphene and Beyond Graphene 2D Semiconductor Devices
Authors: Schwierz Frank
Published: October 2015

During the past 10 years, 2D materials have found significant attention in the electronic device community. The first 2D material explored for electronic applications was graphene and the beginning of graphene research was hallmarked by great enthusiasm. It soon turned out, however, that the missing bandgap of graphene causes problems for proper transistor operation and limits the potential of graphene transistors. Therefore researchers have extended their work to 2D materials beyond graphene recently. Meanwhile a variety of different 2D materials are under investigation and part of them has already successfully been used to realize 2D transistors. In the present paper, we introduce the most important 2D materials and evaluate those of their properties relevant for transistors. We review the current state-of-the-art of 2D transistors, compare their performance to that of conventional transistors, and discuss potential applications for 2D transistors.
(Invited) Observation of Stress Responses of Bacteria Confined in a MEMS Microfluidic Chip
Authors: Nishimura Yusuke , Ishida Makoto , Sawada Kazuaki , Ishii Hiromu , Machida Katsuyuki , Masu Kazuya , Wang Changle , Iida Kenichiro , Saito Mitsumasa , Yoshida Shinichi
Published: October 2015

This work describes the new and simple method for observing bacterial behavior of stress response such as to light irradiation in a polydimethylsiloxane (PDMS) -based MEMS microfluidic chip. The fluorescence was observed from Legionella cells confined in small spaces among microbeads. Ultraviolet (UV) light irradiation was found to be a trigger for producing fluorescent material. Confining bacteria in the small spaces made by the MEMS technique is an effective way for investigating their stress response.
Increase in Oxide Trap Density Due to the Implementation of High-k and Al2O3 Cap Layers in Thick-Oxide Input-Output Transistors for DRAM Applications
Authors: Simoen Eddy , Ritzenthaler Romain , Cho Moon Ju , Schram Tom , Horiguchi Naoto , Aoulaiche Marc , Spessot Alessio , Fazan Pierre , Claeys Cor
Published: October 2015

The impact of the implementation of a high-k/metal-gate (HKMG) stack on the oxide integrity of input-output (I/O) pMOSFETs for DRAM periphery applications is investigated by means of low-frequency (LF) noise spectroscopy. It is shown that the predominant 1/f noise is governed by number fluctuations, irrespective of the details of the gate stack. However, the trap density in the 5 nm SiO2 gate oxide, derived from the noise power spectral density is significantly increased by the application of the HKMG and/or Al2O3 cap and the subsequent diffusion anneal at 900 oC.
Resistive Switching Characteristics of Si-Rich Oxides with Embedding Ti Nanodots
Authors: Kato Yusuke , Arai Takashi , Ohta Akio , Makihara Katsunori , Miyazaki Seiichi
Published: October 2015

We have studied a formation of Ti nanodots (NDs) by remote-H2 plasma (H2-RP) treatment and an impact of Ti-NDs embedding into Si-rich oxide (SiOx) on the resistive switching behaviors because it is expected that NDs can trigger the formation of the conductive filament path in SiOx. Atomic force microscope (AFM) analysis shows that a combination of a Ge(~20 nm)/Ti(~3 nm) stacked layer with subsequent H2-RP exposure is effective to form the high-density Ti-NDs, where Ge layer is used as a barrier layer against oxidation of the ultrathin Ti layer. From X-ray photoelectron spectroscopy (XPS) analysis, an etching of Ge layer by H2-RP exposure and surface oxidation of Ti-NDs by air exposure are observed. After fabrication of SiOx-ReRAMs with the NDs, resistive switching characteristics are measured from current-voltage (I-V) curves and compared to the results obtained from the diodes without the NDs.
(Invited) Visualization of Conductive Filament of ReRAM during Resistive Switching by in-situ TEM
Authors: Takahashi Yasuo , Kudo Masaki , Arita Masashi
Published: October 2015

Performance of in-situ-transmission electron microscopy (TEM) applied to analysis of the resistive random access memory (ReRAM) is reported. Recent progress of ReRAMs makes it indispensable to understand the resistive switching mechanism in order to guarantee the reliability of ReRAMs. Since the TEM provides a high resolution images of the nanostructure, in-situ TEM should be a powerful tool for the analysis if electrical characteristics of ReRAMs can be measured in the TEM. The two sample fabrication methods are applied to two different ReRAM devices. Switching characteristics, which are almost the same as those measured at the outside of TEM by the use of conventional ReRAM cells, are achieved together with clear images of formation and rupture of conductive filaments corresponding to the low and high resistance states. In addition, retention characteristics longer than 106 s, and SET/RESET pulse operation more than 100k times are confirmed during TEM observation. These results indicate that the in-situ TEM will be a powerful tool to analyze the reliability of ReRAMs.
Dummy Poly Gate Removal Process Optimization with Pulsing Plasma Application
Authors: Ji Shi-Liang , Huang Rui-Xuan , Zhang Cheng-Long
Published: October 2015

High-K metal gate (HKMG) approach has been introduced to enhance the device performance via lowering device current leakage. Dummy poly gate removal (DPGR) process is introduced in HKMG process to form the metal gate with different work functions for n/p-MOS. However, the introduction of this technology does bring many new challenges to process, especially for etch process. Before the second dummy gate is removed, the first dummy gate has been replaced with metal materials. This definitely requires soft etch process to avoid the damage of gate channel and the first metal gate while meet all the physical targets. In this paper, we leveraged synchronous pulsing/source pulsing scheme to fulfill the precise geometry definition and achieve the requirement of device performance.
(Invited) Silver Sinter Joining and Stress Migration Bonding for WBG Die-Attach
Authors: Suganuma Katsuaki , Nagao Shijo , Sugahara Toru , Yokoi Emi , Zhang Hao , Jiu Jinting
Published: October 2015

Power electronics play an important role in the generation-storage-distribution conversion cycle of the electric energy. Wide band gap semiconductors such as SiC and GaN have attracted many researchers recently because both of their excellent energy conversion efficiency and of capability of device downsizing. The performance of interconnection, especially die-attach, has one of the essential roles for achieving high performance. Among various proposals for die-attach materials and processes, Ag sinter joining is a promising method for power semiconductors as well as for power LEDs, providing excellent heat-resistance to achieve stable joint structures be-yond 200 °C. This paper summarizes the present status of the Ag sinter joining and of the new approach with Ag film bonding, both of which have developed by the authors’ group.
(Invited) Enabling SiC Yield and Reliability through Epitaxy and Characterization
Authors: Das Hrishikesh , Sunkari Swapna , Domeij Martin , Konstantinov Andrei , Allerstam Fredrik , Neyer Thomas
Published: October 2015

Reliability and cost are the major factors facing large scale adoption of SiC power devices. The push to reduce costs with 150mm diameter wafers comes with lower crystal quality and higher defects, thus prompting reliability concerns. In this work we present ways for comprehensive detection and screening of bipolar degradation causing defects and other crystal defects to alleviate reliability concerns.
Direct Determination of Burgers Vectors of Threading Mixed Dislocations in 4H-SiC c-Plane Wafers Grown by PVT Method
Authors: Guo Jianqiu , Yang Yu , Wu Fangzhen , Goue Ouloide Yannick , Raghothamachar Balaji , Dudley Michael
Published: October 2015

A systematic method is developed and demonstrated here to determine the Burgers vectors of threading mixed dislocations in4H-SiC c-plane offcut wafers grown by PVT method. Both Synchrotron Monochromatic X-ray Topography and Ray Tracing Simulations are used in this method. Measurements confirm that in a commercial offcut wafer the majority of the threading dislocations with screw component are actually mixed type dislocations.
Double Shockley Stacking Fault Formation in Higher Doping Regions of PVT-Grown 4H-SiC Wafers
Authors: Yang Yu , Guo Jianqiu , Goue Ouloide Yannick , Wang H , Wu F , Raghothamachar Balaji , Dudley Michael , Chung G , Quast J , Sanchez E , Manning I , Hansen Darren
Published: October 2015

In this study of 4H-SiC wafers, we report the observation of overlapping Shockley stacking faults generated from residual surface scratches in regions of higher doping concentration after the wafers have been subjected to heat treatment. The stacking faults are rhombus shaped and are bound by partial dislocations. The process is driven by the fact that a faulted crystal containing double Shockley faults is more stable than perfect 4H–SiC crystal at the high temperatures (>1000 C) that our samples have been subjected to during heat treatment. We have developed a model for the formation mechanism of the rhombus shaped stacking faults and the partial dislocation configuration has been verified using back reflection synchrotron topography. Our studies show that double Shockley faults can be generated in regions where dislocation sources are presents (eg. scratches or low angle boundaries) and when the nitrogen doping concentration exceeds a certain level when the crystals are subjected to heat treatment.
(Invited) Baseplate Materials for Securing Reliability of Wide Band Gap Power Semiconductor Module Operating at High Temperatures
Authors: Takahashi Hiroki , Anzai Takeshi , Kato Fumiki , Sato Shinji , Tanisawa Hidekazu , Murakami Yoshinori , Watanabe Kinuyo , Sato Hiroshi
Published: October 2015

Baseplate material properties for realizing high temperature resistant power modules are investigated. Power modules should have a tolerance for heavy thermal cycle load and retain their original performance. Therefore, it is important to improve the reliability of the heat dissipation path, which is the soldered joint between the baseplate and ceramic substrate. This study aimed to improve reliability by appropriately selecting the baseplate material and relaxing the thermal stress in the soldered joint. We conducted a series of verification tests using four types of baseplate material. Our results clarified that a smaller mismatch of coefficient of thermal expansion (CTE) between the baseplate and ceramic substrate contributes to an improvement in reliability, especially in case of W–Cu as the baseplate material. Conversely, the results also clarified that baseplate plastic deformation contributes to an improvement in reliability even if the CTE mismatch is large, in the case of Al.
(Invited) Radiation-Induced Defect Mechanisms in GaN HEMTs
Authors: Koehler Andrew D. , Anderson Travis J , Specht Petra , Weaver Brad D , Greenlee Jordan D , Tadjer Marko J , Shahin David I , Hobart Karl D , Kub Francis J
Published: October 2015

GaN high electron mobility transistors (HEMTs) have the potential to be extremely tolerant of space and weapons of mass destruction radiation found in space and resulting from weapons of mass destruction. AlGaN/GaN HEMTs were fabricated on Si substrates and passivated with plasma enhanced chemical vapor deposition (PECVD) SiN, also HEMTs with in situ SiN and additional PECVD SiN were compared. These samples were exposed to 2 MeV protons, up to 6x1014 cm-2, which resulted in decreased mobility, decreased sheet carrier density, and an increase in dynamic ON-resistance. High resolution scanning transmission electron microscopy revealed roughening of the AlGaN/GaN interface. Off-state pulsed quiescent voltage stress was used to investigate the dynamic ON-resistance of GaN HEMTs before and after radiation. HEMTs with in situ SiN plus PECVD SiN shows improved radiation hardness for dynamic ON-resistance.
4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K
Authors: Spry David J , Neudeck Phil G , Chen Liangyu , Chang Carl W , Lukco Dorothy , Beheim Glenn M.
Published: October 2015

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 °C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C).
Physical and Electrical Properties of Ag Contacts on MoS2
Authors: Yuan Hui , Pan Minghu , Cheng Guangjun , Richter Curt A. , Li Qiliang
Published: October 2015

We first compared the electrical characteristics of MoS2 field-effect transistors with Ag source/drain contacts with those with Ti. MoS2 FETs with Ag contacts show more than 60 times higher on-state current than those with Ti contacts. Meanwhile, scanning electron microscopy, atomic force microscopy and Raman spectroscopy were carried out on 5nm Au / 5nm Ag or 5nm Au / 5nm Ti film deposited onto MoS2 mono- and few-layers. The results shows that Au/Ag forms smoother and denser film, and that Ag or Ti is in direct contact with MoS2. It confirms that the metal-MoS2 interface is crucial to the device performance. Then, gate assisted contact-end Kelvin test structures and gate assisted 4-probe structures were used to measure the field effects of the transfer length and contact resistivity in source/drain contacts of top-gate MoS2 FETs. It indicates that the contact performance also contributes to the switching of the MoS2 transistors.
(Invited) A Metal Oxide Antifuse-Diode Device
Authors: Kuo Yue
Published: October 2015

A new type of high-k dielectric based device that has both antifuse and diode functions is reported. The device has a large "programmed" to "unprogrammed" leakage current ratio suitable for "one-time programmed" memory operation. It can limit the current flow direction, which is good for switching purpose. This metal-resistor-semiconductor device has the "gray-scale" capability similar to that of the MOSFET. The operation principle and parameters influencing the device performer have been discussed. There are many possible applications of this new type of device.
ZnCdSe-Sensitized WO3 and TiO2 based Photoelectrodes: A Comparative Study
Authors: Gakhar Ruchi , Chidambaram Dev
Published: October 2015

This study compares the characteristics of photoelectrodes obtained by sensitization of two different oxide semiconductors (TiO2 and WO3) with same ternary quantum dots for the first time. TiO2 nanotube arrays were obtained using electrochemical anodization technique while the porous WO3 thin film was spray deposited onto SnO2:F substrate. The ZnCdSe quantum dots were tethered to the oxide substrates employing successive ionic layer adsorption and reaction technique. The influence of the number of deposition cycles on photoelectrochemical properties of sensitized oxide films was investigated. The results obtained show that ZnCdSe sensitized TiO2 nanotube array based photoelectrodes exhibit superior performance compared to ZnCdSe sensitized WO3 films under similar conditions.
Lift-Off Patterning of Nano-Crystalline Quantum Dot Films
Authors: Sabeeh Ala , Thakur Yash , Ruzyllo Jerzy
Published: October 2015

The paper is concerned with the effectiveness of the lift-off process in pattern definition of ultra-thin nanocrystalline quantum dot (NQD) films. The lift-off process is implemented and investigated in conjunction with mist deposition and spin coating of NQD films. The lift-off process is preformed in gas-phase (oxygen plasma exposure) and liquid-phase (acetone immersion). The results of NQD patterned films using lift-off process are presented and discussed in terms of performance of the lift-off medium (dry and wet), resolution of the pattern transfer process, as well as photoresist thickness. It demonstrates that while fully compatible with the mist deposition, the patterning scheme proposed is not compatible with spin coating of NQDs films.
Multiple-Input Multiple-Output Optical Integrator Design by Non-Interacting Control via Dynamic Extension
Authors: Williams Stephen Hayden , Xue Xiaojia , Thitsa Makhin
Published: October 2015

The design of a multiple-input multiple-output optical integrator using a semiconductor optical amplifier is proposed. The design is based on non-interacting state feedback control through dynamic extension, which is a well established technique in nonlinear dynamical system theory. First it is shown the dynamical equations of a semiconductor optical amplifier with two inputs and two outputs has a well-defined vector relative degree of [1,1] in a large range of operating points. It is demonstrated that such a device can be transformed into an integrator by applying state feedback. The design is verified by simulating the closed loop device in MATLAB Simulink.
Characterization of InN - In0.25Ga0.75N Quantum Well Laser Structure for 1330 nm Wavelength
Authors: Polash Md. Mobarak Hossain , Alam M. Shah
Published: October 2015

A nitride based wurtzite-strained QW laser with 12Å InN well layer, 15Å In0.25Ga0.75N barrier layer and GaN SCH layer has been designed and characterized at 1330nm wavelength. To determine the electronic properties, a self-consistent method with 6-bands k.p formalism considering valence-band mixing effect, strain and polarization effect followed by Poisson's equation has been used. The interband momentum matrix elements, optical gain, spontaneous emission rate, and radiative current density have been calculated to analyze the optical properties of the laser. Due to the strain effect, the wave-function overlap integral was obtained as 43.27%. The structure is TE polarized with C1-HH1 and C1-LH1 dominating transitions, while the spontaneous emission rate per energy interval per unit volume was 7.21×1027 s-1cm-3eV-1 at 1329.55nm. Furthermore, the radiative recombination rate and the radiative current density were 7.77×1029 s-1cm-3 and 149.19 Acm-2, respectively. The optical gain of the structure is 5261.52cm-1 at 1336.7nm for TE-polarization.
Optical Gain Optimization of Al0.8Ga0.2N-Delta-GaN Quantum Well Laser in Ultraviolet Spectra Using Genetic Algorithm
Authors: Polash Md. Mobarak Hossain , Alam M. Shah
Published: October 2015

An AlGaN based quantum well laser with GaN delta layer and AlN barrier layers has been designed and characterized for obtaining electronic and optical characteristics. The band structure was calculated with self-consistent 6-band k.p formalism including valence-band mixing effect, strain and polarization effect. A Genetic Algorithm based optimization has been performed to optimize the optical gain taking well width, delta width and barrier width into consideration. The Optimization of both TE and TM polarized optical gain exhibits good improvement than previously published work. The peak optical gain as obtained in analysis is 3589.5 cm−1 while the peak spontaneous emission rate is 12.94×1028 s-1cm-3eV-1 at 246.89nm for 5×1019cm-3 carrier density. The optimum TE optical gain is found to be 6479.1 cm-1 for 11Å QW with 7Å delta layer at 279nm wavelength and optimum TM gain is found to be 116.95 cm-1 for 20Å QW with 3Å delta layer at 289.8nm wavelength.
(Invited) The Next Generation Biochip
Authors: Yang Yuh-Shyong
Published: October 2015

Biochip in the form of microarray is an ingenious way to collect large amount of biochemical information. This method is especially suited for the current big data era when large amount of genomic and proteomic information are analyzed to answer many medical questions including aging, chronical diseases and personal medicine. However, applications of traditional biochip array are facing some major limitations, such as labeling requirement, specificity and sensitivity issues, and cost, which prevent many of its biomedical applications. Current technologies available in semiconductor and electronics industries may help to eliminate most, if not all, of these barriers. We propose the development of a Next Generation bioChip (NGC) that fulfills the unmet needs of current biochip to face the growing demand in health care. By using polysilicon nanowire field effect transistor base biosensor, we demonstrate that the NGC can be achieved with current technologies and can be built in the near future.
Simulation of the pH Sensing Capability of an Open-Gate GaN-Based Transistor
Authors: Patrick Erin , Choudhury Mohua , Law Mark E
Published: October 2015

Given their nontoxicity and chemical inertness in biological or corrosive environments, heterostructure transistors based on the AlGaN/GaN material structure are advantageous for chemical and biological sensors. They offer notably high sensitivity as a result of the very large gain and transconductance. Prior research on this technology has demonstrated its potential applications in prostate and breast cancer detection and pH sensing. However, due limited modeling and simulation support, the device design has not been optimized. We build upon a TCAD simulation framework (FLOODS) specifically suited for III-V device simulation that is capable of coupling reaction-dependent physics at the electrolyte/semiconductor interface to the physics governing semiconductor device performance. This paper outlines the simulation methodology for a pH sensor using an open-gate AlGaN/GaN High Electron Mobility Transistor (HEMT).
Cultivation of Rat Nerve Cells on Nanoimprinted Microstructures on Polydimethylsiloxane Sheets
Authors: Koshinuma Eiki , Maenosono Hirotaka , Endo Daisuke , Nishioka Yasushiro
Published: October 2015

Regenerative medical research has attracted much attention in recent years. Here, we fabricated micro trench structures with varying widths of 15 and 150 μm and depths of 30 and 60 μm using the nanoimprint technique on a 100 μm thick polydimethylsiloxane culture sheet used as a biocompatible polymer culture sheet. Rat neurons were observed to grow after 3 days selectively within those micro trenches with widths larger than 15 μm, and they were coated with polylysine.
Propagation of Nanopores and Formation of Nanoporous Domains during Anodization of n-InP in KOH
Authors: Buckley D. Noel , Lynch Robert P , Quill Nathan , O'Dwyer Colm
Published: October 2015

Anodization of highly doped (1018 cm-3) n-InP in 2 – 5 mol dm-3 KOH under potentiostatic or potentiodynamic conditions results in the formation of a nanoporous sub-surface region. Pores originate from surface pits and an individual, isolated porous domain is formed beneath each pit in the early stages of anodization. Each such domain is separated from the surface by a thin non-porous layer (typically ~40 nm) and is connected to the electrolyte by its pit. Pores emanate from these points along the <111>A crystallographic directions to form domains with the shape of a tetrahedron truncated symmetrically through its center by a plane parallel to the surface of the electrode. We propose a three-step model of electrochemical pore formation: (1) hole generation at pore tips, (2) hole diffusion and (3) electrochemical oxidation of the semiconductor to form etch products. Step 1 determines the overall etch rate. However, if the kinetics of Step 3 are slow relative to Step 2, then etching can occur at preferred crystallographic sites leading to pore propagation in preferential directions.
Terahertz Spectroscopy: Studying Carrier Dynamics in Semiconductor Nanostructures
Authors: Titova Lyubov V. , Xu Sijia , Baribeau Jean-Marc , Lockwood David J , Hegmann Frank
Published: October 2015

Understanding the ultrafast dynamics of photoexcited carriers in semiconductor nanostructures and their dependence on sample morphology is crucial for their incorporation into photonic devices. Time-resolved terahertz (THz) spectroscopy (TRTS) is an all-optical, contact-free technique that directly measures the transient mobile carrier dynamics and terahertz conductivity in materials over picosecond time scales, and is uniquely suited as a probe of conductivity in nanomaterials. Using low temperature MBE-grown silicon films as an example, we show how TRTS can be used to probe microscopic photoconductivity as well as obtain crucial insights into sample morphology. The thin silicon films consist of a mixture of amorphous and crystalline phases, and their relative content changes drastically with growth temperature. Photoexcited carrier dynamics in these films are determined by film crystallinity: in the amorphous phase, carriers are trapped in bandtail states on sub-picosecond time scales, while the carriers excited in crystalline grains remain free for tens of picoseconds. The complex THz conductivity spectra obtained from the TRTS measurements show that the long range conductivity is significantly higher in films grown at higher temperatures that contain a larger fraction of crystalline material with larger crystal grain sizes.
Crystalline Tetrahedral Phases Al1-xBxPSi3 and Al1-xBxAsT3 (T = Si, Ge) Via Reactions of Al(BH4)3 and M(TH3)3 (M = P, As)
Authors: Sims Patrick , Aoki Toshihiro , Menendez Jose , Kouvetakis John
Published: October 2015

Crystalline (III-V)1-y(IV2)y hybrid semiconductors Al1-xBxPSi3 and Al1-xBxAsSi3 have been grown on Si(001) substrates via reactions of Al(BH4)3 and M(SiH3)3 (M = P, As). These films are characterized for structure, composition, and phase morphology The materials form by interlinking III-V-IV3 tetrahedral units that construct a cubic lattice with average diamond-like symmetry containing isolated III-V pairs. This synthetic approach was extended to alloy systems in which the III-V pairs are imbedded in a Ge-matrix using As(GeH3)3. These materials are grown on Ge/Si(001) platforms and a comparative study of two growth methods is presented. One describes a low pressure CVD route via reactions of Al(BH4)3 and As(GeH3)3, and the other is a gas-source MBE technique combining Al atoms from an effusion cell with the germyl-arsene precursor. Both sets of films are studied using aberration-corrected STEM. Globally the results show that Al(BH4)3 acts as a carbon-free source of Al compatible with CVD protocols.
Study of the Effects of GaN Buffer Layer Quality on the dc Characteristics of AlGaN/GaN High Electron Mobility Transistors
Authors: Ahn Shihyun , Zhu Weidi , Dong Chen , Hwang Ya-Hsi , Kim Byung-Jae , Ren Fan , Pearton Stephen J. , Lind Aaron Gregg , Jones Kevin Scott , Kravchenko Ivan
Published: October 2015

The influence of different buffer layer quality on AlGaN/GaN high electron mobility transistors (HEMTs) dc characteristics was investigated. Dc measurement by parameter analyzer and gate pulse measurement were performed to compare two different buffer layer quality samples. The same Al concentrations of AlGaN with 2µm and 5µm GaN buffer layers on sapphire substrates from two different vendors were used. The defect densities of 2 µm and 5 μm GaN buffer layer’s HEMTs structures measured by transmission electron microscopy (TEM) were 7 × 109
cm-2 and 5 × 108 cm-2, respectively. There was small difference in drain saturation current and transfer characteristics in HMETs for these two types of buffer. Non-passivated HEMT with 5 µm GaN buffer layer showed no dispersion in gate-lag pulsed measurement at 100 kHz but HEMT with 2 µm GaN buffer layer showed 71% drain current reduction at 100 kHz gate-lag pulsed measurement.
Effect of Buffer Oxide Etchant (BOE) on Ti/Al/Ni/Au Ohmic Contacts for AlGaN/GaN Based HEMT
Authors: Hwang Ya-Hsi , Ahn Shihyun , Dong Chen , Zhu Weidi , Kim Byung-Jae , Ren Fan , Lind Aaron Gregg , Jones Kevin Scott , Pearton Stephen J. , Kravchenko Ivan
Published: October 2015

The effects of buffer oxide etchant on Ti/Al/Ni/Au Ohmic contacts for AlGaN/GaN high electron mobility transistor were studied. Scanning electron microscopy (SEM), energy dispersive spectrum (EDX), and Auger electron spectroscopy (AES) were performed to investigate the degradation after treatment. Contact resistance increase from 1×10-4 to 2.5×10-4 ohm/cm2 after treatment. Ohmic metals were found out to be divided into three regions including islands, rings surround the islands, and the remaining field area. The islands were found to be shorter and the rings thinner after treatment. Besides, Ti, Al and Ni were found to be etched by BOE and caused Au to peel off from the Ohmic metals. The etching of Ti, Al and Ni was believed to be the reason of degradation.
Simulating RF Performance of Proton Irradiated AlGaN/GaN High Electron Mobility Transistors (HEMT)s
Authors: Mukherjee Shrijit , Patrick Erin , Law Mark E
Published: October 2015

AlGaN/GaN High Electron Mobility Transistors (HEMTS) subjected to proton irradiation of fluence up to 1014 cm-2 were simulated to observe the impact on small signal and RF characteristics. While a lot of work has covered dc degradation of HEMTs, very few studies exist which focus exclusively on RF degradation despite their high frequency applications. This work establishes a simulation framework capable of frequency domain device simulation up to 10 GHz. The role of defects generated by proton irradiation will be studied by carrying out low frequency transconductance simulation and current gain frequency sweeps to examine degradation of cut-off frequency. The primary objective will be to understand the role of partially ionized donor traps near the AlGaN/GaN interface and how their bias dependence and capture time constants may significantly impact cut-off frequency and current gain estimations at high frequencies.
Enhanced Performance Designs of Group-IV Light Emitting Diodes for Mid IR Photonic Applications
Authors: Gallagher James Dennis , Senaratne Charutha , Xu Chi , Wallace Patrick M , Menendez Jose , Kouvetakis John
Published: October 2015

This paper describes Ge1-y
Sn
y
(y
= 0.0-0.11) light emitting diodes (LEDs) with a broad range of compositions extending from pure Ge to Sn concentrations where the alloy becomes a direct gap material (y = 0.09) and beyond. The devices are grown on Si(100) platforms using ultra-low temperature depositions of highly reactive Ge and Sn hydrides. The device fabrication adopts two new photodiode designs. The first employs n-Ge/i-Ge1-y
Sn
y
/p-Ge1-y
’
Sn
y

’
hetero-structure stacks possessing a single defected interface between the n-Ge and i-Ge1-y
Sn
y
layers. The second consists of a homo-structure n-Ge1-y
Sn
y
/i-Ge1-y
Sn
y
/p-Ge1-

y
Sn
y
design. The devices show low dark currents and the electroluminescence (EL) spectra show concomitant redshifts of the peak emission position and intensity increase near direct gap Sn compositions. The EL of the homo-structure design displays a large efficiency enhancement relative to the hetero-structure devices. The fabrication of ternary Ge1-x-y
Si
x
Sn
y
diodes with ~9% Sn and 3-9% Si contents is also discussed.