bluuebunny/crossref_metadata_2025 huggingface dataset:
(Invited) Advance of Dye-Sensitized Solar Cells with Organic Dyes
Authors: Murakami Takurou N , Koumura Nagatoshi
Published: October 2015

The recombination reactions may substantially decrease the open circuit voltage (V
oc) in the dye-sensitized solar cells (DSSCs), especially in the case of employing the cobalt redox electrolyte. To find the effective structure of organic dyes for the recombination inhibition, we investigated the effects of the size and position of the steric hindrance in carbazole dyes, and the effects of the donor type, such as carbazole, coumarin, and triphenylamine, on recombination reaction. There was a positive relationship between V
oc and the bulkiness of the additional groups in the donor segment, and shorter alkyl chains in the thiophene linker moiety in the carbazole dye. Also, free rotatable phenyl groups in triphenylamine donor played a role as the steric hindrance to inhibit the recombination reactions. We reviewed our study for the organic dye development to inhibit the recombination reaction in DSSCs.
PTB7:PC71BM Bulk Heterojunction Solar Cells with Multiple Additives
Authors: Ohzeki Masaya , Qiu Jiayu , Fujii Shunjiro , Kataura Hiromichi , Nishioka Yasushiro
Published: October 2015

We fabricated bulk-hetero junction organic solar cells based on 1,2- dichlorobenzene solutions of poly[[4,8-bis[(2- ethylhexyl)oxy]benzo[1,2-b:4,5-b′] dithiophene-2,6-diyl] [3-fluoro-2-　[(2-ethylhexyl)　carbonyl]thieno [3,4-b]- thiophenediyl]　(PTB7): [6,6]-phenyl- C71-butyric-acid-methyl-ester (PTB7:PC71BM) with additional surfactants of diiodooctane (DIO) and dimethyl sulfoxide (DMSO). The weight ratios of DIO and DMSO relative to the total weight of PTB7:PC71BM were optimized to be 3% and 13%, respectively, and found that the solar cells with the optimized weight ratios of the DIO and DMSO additives exhibited an open circuit voltage of 0.72 V, short circuit current density of 15.63 mA/cm2, fill factor of 0.49, and power conversion efficiency of 5.47%. The significant structural changes were found from the surface morphology observation of the active layer as observed by atomic force microscopy.
Solution-Derived NiO Hole Transport Layers on the PTB7:PC71BM Organic Solar Cells
Authors: Kiriishi Koudai , Hashiba Kousei , Qiu Jiayu , Fujii Shunjiro , Kataura Hiromichi , Nishioka Yasushiro
Published: October 2015

Nickel oxide (NiO) has become attractive as a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT :PSS) substitute in solar cells’ hole transport layers (HTLs). However, solar cells with NiO HTLs based on poly[[4,8-bis[(2-ethylhexyl)oxy]benzo [1,2-b:4,5-b']dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]-thiophenediyl] (PTB7) and [6,6]-phenyl C71 butyric acid methyl ester (PC71BM) remain poorly characterized. We report the effects of NiO-layer thickness on the performance of glass/ITO/NiO/PTB7:PC71BM/LiF/Al-structured solar cells. Thickness was optimized by changing nickel acetate tetrahydrate concentration in 2-methoxyethanol solution used for spin-coating deposition. We achieved a power conversion efficiency of 3.78% at 0.2 M of nickel acetate tetrahydrate.
Inverted Organic Solar Cells Based on PTB7:PC71BM with PFN Electron Transport Layer on ITO-Free Flexible PEN Substrate
Authors: Hashiba Kousei , Nagata Ryo , Kiriishi Koudai , Kataura Hiromichi , Fujii Shunjiro , Nishioka Yasushiro
Published: October 2015

Organic solar cells are expected to have superior performance with flexibility and low cost fabrication. However, conventional organic solar cells usually have issues of using rare earth ITO and inferior long term reliability. To seek possible solutions for these issues, we fabricated an inverted solar cell with a structure of PEN/PEDOT:PSS/PFN/PTB7:PC71BM/MoO3/Au, and found that these devices had much improved long-term reliability when they were stored in air without any surface passivation layer. The resultant conversion efficiency of the solar cell was 1.88%, and the conversion efficiency continued to be almost independent of time even after 100 h of storage in air.
Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications
Authors: Islam Rabiul , Uddin Md. Mohi , Matin Mahmud Abdul
Published: October 2015

An optimized InSb QWFET with a very high electron mobility 4.42 m2V-1s-1 and density 1.47×1015 m-2 at V
g= 0V have been calculated using quantum corrected Schrödinger-Poisson (QCSP) solution which is at least ~180 times greater than that of Si NMOS. Particularly noteworthy is that the 2DEG in 20 nm QW is completely depleted by a very small V
g= -0.25V (pinch-off voltage V
p). A giant gate controllability ratio of dn
s/dV
g is found to be ~ 5.2×1015 m-2 V-1. It indicates that the Fermi level E
F is smoothly tuned by the Vg due to a very low interface state density D
it (7.8×1014-3.7×1016 m-2eV-1) at the interface between Al2O3 and Al0.1In0.9Sb top layer of the InSb QWFET, resulting a giant dn
s/dV
g. The minimum value of capacitance in the C-V curve has also been confirmed V
p=-0.25V where the channel is in off-state.
HfO2/Al2O3/InGaAs MOSCAP Structures and InGaAs Plasma Nitridation Elaborated in a 300mm Pilot Line
Authors: Billaud Mathilde , Duvernay Julien , Grampeix Helen , Pelissier Bernard , Martin Mickael , David Sylvain , Vallée Christophe , Chalupa Zdenek , Boutry Hervé , Baron Thierry , Cassé Mickaël , Ernst Thomas , Vinet Maud , Reimbold Gilles , Faynot Oliver
Published: October 2015

We report on electrical characteristics of HfO2/Al2O3 gate dielectric on InGaAs as a function of Al2O3 ALD cycles. We also investigate the effect of a NH3 treatment in a 300mm PEALD chamber equipped with a capacitive plasma. It is shown that 8 Al2O3 cycles are required to achieve a high level capacitance (1.75μF/cm²) and an interface trap density (Dit) around 6×1012cm-²eV-1. The NH3 plasma treatment through an Al2O3 layer is able to integrate nitrogen at the InGaAs interface and to form an oxynitride GaOxNy.without deterioration of the C-V characteristics.
(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options
Authors: Peralagu Uthayasankaran , Li Xu , Ignatova Olesya , Fu Yen-Chun , Millar David Alan John , Steer Matthew J , Povey Ian M , Hossain Khalid , Jain Manish , Golding Terry G , Droopad Ravi , Hurley P. K. , Thayne Iain G
Published: October 2015

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.
(Invited) Border Trap Density in Al2O3/InGaAs MOS: Dependence on Hydrogen Passivation and Bias Temperature Stress
Authors: Tang Kechao , Droopad Ravi , McIntyre Paul C.
Published: October 2015

We report on the role of hydrogen (forming gas) post-metal annealing to passivate border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and of bias temperature stress treatments to generate/depassivate such traps. Experiments are carried out with Pd metal gates that efficiently dissociate molecular hydrogen during forming gas annealing, and they make use of InGaAs epitaxial layer substrates that are capped with arsenic after completion of their growth, to avoid unintentional oxide formation and disorder at the channel surface prior to atomic layer deposition of the Al2O3 gate dielectric. We find that forming gas anneal (FGA) greatly reduces both the interface trap density and border trap density measured in the gate stacks, but that the effectiveness of FGA for border trap passivation saturates for anneals with thermal budgets greater than 450°C/30 min. Both negative and positive bias temperature stress treatments are found to have no effect on the extracted border trap densities compared to non-treated capacitors.
(Invited) Topological States in Multi-Orbital Honeycomb Lattices of HgTe (CdTe) Quantum Dots
Authors: Beugeling Wouter , Kalesaki Efterpi , Delerue Christophe , Niquet Yann-Michel , Vanmaekelbergh Daniel , Morais Smith Cristiane
Published: October 2015

We summarize recent theoretical works on artificial graphene realized by honeycomb lattices of semiconductor (CdSe, HgTe, CdTe) quantum dots forming a two-dimensional single-crystalline sheet. In the case of CdSe, we predict conduction bands with Dirac cones at two distinct energies and nontrivial flat bands. An analogous behavior is found in HgTe but, in addition, the strong spin-orbit coupling opens large topologically nontrivial gaps, leaving a flattened band detached from the others. We deduce that honeycomb lattices of HgTe quantum dots may constitute promising platforms for the observation of a fractional Chern insulator or a fractional quantum spin Hall phase. Similar predictions are made for CdTe but with smaller nontrivial gaps.
Enhanced Charge-Transport Behavior on PbS Nanocrystals Capped with Atomic Ligands
Authors: Yoon Seongwon , Ha Jae Un , Cho Jangwhan , Chung Dae Sung
Published: October 2015

In order to enhance charge-transport nanocrystal (NC) arrays, long and insulating ligands have to be replaced by short and electronically transparent ligands. Traditionally, benzene dithiol or mercaptopropionic acid have been frequently used as such surface ligands to overcome low charge-carrier mobility issues that affect colloidal NCs. However, the resulting devices usually exhibit a limited enhanced mobility of ~0.01 cm2/Vs. In this study, to realize a high charge-carrier mobility over 0.1 cm2/Vs, we demonstrate the utilization of atomic ligands such as halide anions (X-, X : Cl, Br, I) as electrically transparent ligands for lead chalcogenide NCs. We discuss the origin of such improved charge-transport behavior, which results from the introduction of atomic ligands, as well as various characterization results.
(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)
Authors: Triyoso Dina , Carter Rick , Kluth Jon , Luning Scott , Child Amy , Wahl Jeremy , Mulfinger Bob , Punchihewa Kasun , Kumar Anil , Kang Laegu , Sporer Ryan , Chen Xiaobo , Straub Sherry , Bohra Girish , Patil Suraj , Zhang Xing , Chen Alex , Togo Mitsuhiro , Pal Rohit
Published: October 2015

After decades of research, high-k metal gate has been successfully integrated into CMOS starting with the 45nm node. To continue scaling, the industry has chosen two integration approaches: FINFET with gate last and FDSOI with gate first. The FINFET with gate last integration was introduced into production at the 22nm node by Intel. The FDSOI with gate first integration was introduced into production at 28nm node by ST Microelectronics. There are some common factors impacting threshold voltage (Vt) on both integrations such as the high-k/metal gate film thickness and composition as well as the doping concentration. Beyond that, each integration approach has its own unique challenges that must be overcome to achieve targeted Vt and maintain Vt control. In this work we will highlight those unique challenges and discuss what knobs can be used to achieve the targeted Vt and maintain Vt control.
(Invited) Intrinsic Unipolar SiOx-Based Resistive Switching Memory: Characterization, Mechanism and Applications
Authors: Chang Yao-Feng , Fowler Burt , Zhou Fei , Lee Jack C.
Published: October 2015

Intrinsic unipolar SiOx-based Resistive-RAM (ReRAM) characterization, mechanism and applications have been investigated. We investigate device structures, material compositions and electrical characteristics to realize ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using CMOS compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical controlling and external factors for understanding resistive switching (RS) mechanism. Modeling of RS mechanism, including temperature effect, pulse response and carrier transport behaviors are performed, to develop a compact model in energy diagram, trap-level information in SiOx RS layer, even for computer-aided design (CAD) in very-large-scale integration (VLSI) design. Finally, synapse-based neuromorphic system is demonstrated in SiOx-based ReRAM, combining with bio-inspiration and biomimetics process illustrations. This work presents the comprehensively investigation of SiOx-based resistive switching characteristics, mechanisms, applications for future post-CMOS devices era.
Negative Gate Transconductance in MIS Tunnel Diode Induced by Peripheral Minority Carrier Control Mechanism
Authors: Liao Chien-Shun , Hwu Jenn-Gwo
Published: October 2015

Negative Gate Transconductance (NGT) in the tunneling current of a metal-insulator-semiconductor (MIS) tunnel diode gated by an MIS tunnel gate capacitor is demonstrated in this work. The mechanism is that the effective Schottky barrier height of the MIS tunnel diode can be modulated by controlling the substrate surface minority carriers concentration with the gate bias of the MIS tunnel gate capacitor. Since the tunneling current of a reverse biased MIS tunnel diode is exponentially dependent on the effective Schottky barrier height, the signal of the rise and fall of minority carriers concentration can be read out by the tunneling current and therefore an NGT behavior appears.
Nanoscale Potential Fluctuation in Non-Stoichiometric Hafnium Suboxides
Authors: Orlov Oleg M. , Krasnikov Gennady Ja. , Gritsenko Vladimir A. , Kruchinin Vladimir N. , Perevalov Timofey V. , Aliev Vladimir Sh. , Islamov Damir R. , Prosvirin Igor P.
Published: October 2015

We study the structure of nonstoichiometric HfO
x
films with variable composition using methods of X-ray photoelectron spectroscopy and spectroscopic ellipsometry. HfO
x
, to a first approximation, is a mixture of HfO2 and Hf metal with a small amount (~10–15%) of hafnium sub-oxide HfO
y
(y < 2).
Enhancement of Material Quality of (Si)GeSn Films Grown by SnCl4 Precursor
Authors: Mosleh Aboozar , Alher Murtadha A. , Cousar Larry , Abusafe Husam , Dou Wei , Grant Perry , Al-Kabi Sattar , Ghetmiri Seyed Amir , Alharthi Bader , Tran Huong , Du Wei , Benamara Mourad , Li Baohua , Mortazavi Mansour , Yu Shui-Qing , Naseem Hameed A
Published: October 2015

The (Si)GeSn films have been grown with and without carrier gases on Si substrate using a cold-wall ultra-high vacuum chemical vapor deposition system. Material characterization of the films grown with Ar carrier gas using X-ray diffraction and transmission electron microscopy shows achievement of higher quality films. Optical characterization of the films with photoluminescence shows enhancement in material quality of the films at 350 and 400ºC growth temperatures. Increase in the pressure results in higher Sn incorporation and higher photoluminescence intensity. Spectroscopic ellipsometry data confirms the change in the GeSn bandgap towards lower energies.
(Invited) Effects of Ge Substrate Annealing in H2 on Electron Mobility as well as on Junction Leakage in n-channel Ge MOSFETs
Authors: Toriumi Akira , Lee Choonghyun , Nishimura Tomonori
Published: October 2015

This paper discusses H2 annealing effect of Ge substrate on carrier mobility and junction leakage current in Ge MOSFETs. We found that H2 annealing of Ge wafer improved the electron mobility in Ge n-channel MOSFETs, while it degrades n+/p junction leakage current. Although we have not clarified the mechanisms causing such significant effects, we have found that the oxygen content in Ge surface region is phenomenologically related to above effects of Ge in H2 annealing.
Non-Thermal Equilibrium Formation of Ge1-xSnx (0≤x≤0.2) Crystals on Insulator by Pulsed Laser Annealing
Authors: Moto Kenta , Matsumura Ryo , Chikita Hironori , Sadoh Taizoh , Ikenoue Hiroshi , Miyao Masanobu
Published: October 2015

To realize high-speed thin film transistors, we investigated formation of Ge1-xSnx (0≤x≤0.2) crystals on quartz by pulsed laser annealing. The process-window necessary for crystallization was found to be significantly expanded by introducing Sn, i.e., 16 mJ/cm2 for Ge, ~130 mJ/cm2 for GeSn. Moreover, Ge0.8Sn0.2 samples had high substitutional Sn concentration (~7%) after the growth. These results are expected to be useful to realize high-speed thin film transistors and multi-functional devices.
(Invited) Fabrication of High-Quality Ge-on-Insulator Structures by Lateral Liquid Phase Epitaxy
Authors: Shimura Takayoshi , Suzuki Yuichiro , Matsue Masahiro , Kajimura Keiko , Tominaga Kohei , Amamoto Takashi , Hosoi Takuji , Watanabe Heiji
Published: October 2015

Back-gate Ge-on-insulator metal–oxide–semiconductor field-effect transistors were fabricated using Ge wires grown by lateral liquid phase epitaxy. They exhibited a very high peak hole mobility of 511 cm2/Vs and an on/off current ratio of 106 due to the superior crystalline quality of the Ge wires. The optical properties of the Ge wires were also investigated by micro-photoluminescence spectroscopy, and a direct band gap shrinkage of 45 meV was observed due to the introduction of 0.4% tensile strain.
Towards Quantification of Contaminants in Electrodeposited Cu Films
Authors: Hai N. T. M. , Grimaudo Valentine , Moreno-García Pavel , Broekmann Peter
Published: October 2015

By means of linear sweep voltammetry (LSV) we studied the tendency of various suppressor additives towards the formation of stable adducts with Cu(I)-MPS intermediates which form as by-products of the SPS reaction cycle during an additive-assisted Cu electrodeposition. These LSVs demonstrate a gradual transition from a pure antagonistic SPS/suppressor interplay (superfill capabilities) to a pure synergistic SPS/suppressor interplay (leveling capabilities). SIMS depth profiling experiments on electroplated Cu films indicate that the MCs+ detection mode is superior to the conventional negative SIMS detection mode for the analysis of the N content in those Cu films.
Combined Surface-Activated Bonding Technique for Low-Temperature Cu/SiO2 Hybrid Bonding
Authors: He Ran , Fujino Masahisa , Yamauchi Akira , Suga Tadatomo
Published: October 2015

This work develops a combined surface-activated bonding (SAB) technique for low-temperature SiO2-SiO2 and Cu-Cu bonding at 200 °C. The combined SAB technique involves combinations of surface activation by using surface bombardment by neutralized Ar ion beam containing Si atoms, water vapor exposure, and prebonding attach/detach prior to wafer bonding in vacuum. Bonding strength close to Si bulk fracture energy was achieved for both SiO2-SiO2 and Cu-Cu bonding pairs. We suggest the enhanced –OH (both Si–OH and Cu–OH) chemisorption on the wafers and pre-bonding removal of excess H2O from the interface/surfaces are the key factors involved in the present low-temperature bonding technique. This technique is promising for 3D integration through Cu/SiO2 hybrid bonding at no more than 200 °C.
Electrografted P4VP as Dielectric in High Aspect Ratio TSV: Surface Preparation and Thermomechanical Consideration
Authors: Dequivre Thomas , Al Alam Elias , Plathier Julien , Ruediger Andreas , Brisard Gessie , Charlebois Serge
Published: October 2015

A challenge to most 3D integration approaches is the deposition of the Through-Silicon-Via (TSV) dielectric layer. A TSV is traditionally electrically insulated from the silicon substrate by a thin SiO2 film. As TSV aspect ratio gets higher, conformal SiO2 dielectric deposition becomes much more challenging. Alchimer has proposed as dielectric, the use of a highly conformal organic (poly-4-vinylpyridine, P4VP) as dielectric, electrografted through electrochemical reduction of diazonium salts in aqueous media. Surface cleaning prior to electrografting process is a challenge, especially in via last approach. Moreover, the thermomechanical behavior of P4VP coated TSVs remains unknown. This information is most relevant for the layout optimization of 3D integrated microsystems. We will discuss the TSV surface preparation challenge prior to the electrografting process and present the first measurements of the stress induced in the silicon substrate around TSV insulate by P4VP.
Thermal Decomposition of Tungsten Nitrido Precursors for Low Temperature MOCVD of WNxCy
Authors: Kim Seo Young , Koley Arijit , Bonsu Richard , Nolan Michelle , McElwee-White Lisa , Anderson Tim
Published: October 2015

Tungsten nitrido complexes of the type WN(NR2)3 have been demonstrated to serve as single-source precursors for metal organic chemical vapor deposition (MOCVD) of WNxCy barrier layers. To elucidate the thermal decomposition mechanisms for WN(NMe2)3 and to optimize conditions for deposition of WNxCy films, in-situ Raman spectroscopy experiments were carried out in an up-flow, cold-wall MOCVD reactor. In this study, Raman spectra were detected at temperatures from 159 oC to 474 oC. Density Functional Theory (DFT) calculations were also performed to assess possible steps in the mechanistic pathway.
(Invited) Atomic Layer Deposition of Core-Shell Nanowires for Solar Energy Conversion Devices
Authors: Bielinski Ashley R. , Dasgupta Neil P.
Published: October 2015

Semiconductor nanowires (NWs) have several advantages for solar energy conversion devices resulting from strong light absorption and anti-reflective properties, efficient charge transport properties, and large surface areas to drive chemical reactions. However, precise control of surfaces and interfacial properties is crucial to maximize charge-transfer efficiency across interfaces, while minimizing side reactions and recombination. One technique for surface and interfacial engineering is Atomic Layer Deposition (ALD), which allows for conformal deposition of a wide variety of materials with precision and tunable thickness and composition. Core-shell structures can be fabricated by coating NWs with ALD, facilitating precise tuning of the electronic, optical, and chemical properties to optimize their interfaces. We present several examples of ALD core-shell structures for energy conversion, with an emphasis on solar applications. Examples include quantum-dot sensitized NWs, earth abundant core-shell NWs, passivation layers and co-catalysts for photoelectrochemical water splitting, and control of heterogeneous interfaces in hierarchical nanomaterial synthesis.
Opportunities of Atomic Layer Deposition for Perovskite Solar Cells
Authors: Zardetto Valerio , Di Giacomo Francesco , Mohammed Mahir Asif , Lucarelli Giulia , Razza Stefano , D'Epifanio Alessandra , Licoccia Silvia , Kessels W.M.M. , Di Carlo Aldo , Brown Thomas M. , Creatore Mariadriana
Published: October 2015

The fabrication of different functional layers by means of atomic layer deposition is proposed for the novel organo-lead halide perovskite solar cells. A plasma- assisted process at 150 °C was adopted to deposit an efficient TiO2 compact blocking layer on ITO-polymer substrates. Efficient flexible devices were obtained already with layers as thin as 10 nm. A Thermal ALD Al2O3 process at 150 °C was successfully applied on a mesoscopic anatase TiO2 structure: an improvement of the overall performance of the solar cell (+13%) was measured with only 1 ALD cycle compared to devices without over-layer. Interestingly, a drastic reduction of the performance was observed when increasing the number of the cycles
Understanding Photovoltage in Insulator-Protected Water-Splitting Half-Cells
Authors: Scheuermann Andrew G. , Chidsey Christopher E.D. , McIntyre Paul C.
Published: October 2015

In the pursuit of a photosynthetic and efficient water splitting device, efforts have focused on optimizing specific aspects of the whole: catalysis, electronic conductivity, cathode and anode stability, and kinetics among other aspects. Improvement in one aspect can, however, often require fundamental tradeoffs affecting others. The photovoltage required to achieve a current density of interest for a water splitting device is an especially important metric. High solar-to-hydrogen efficiency is the ultimate goal of water splitting research, but reporting efficiency in a half cell can be misleading. This report investigates the photovoltage in insulator-protected water splitting cells using ALD-TiO2 protected silicon anodes as a case study and looks in depth at how it is correctly determined from typical electrochemical analysis and how this relates to the underlying solid-state carrier transport. Finally, the photovoltage at 10 mA/cm2 operating current referenced to the thermodynamic potentials is reviewed from several leading research reports, allowing for a direct comparison of cell performance.
(Invited) ALD Materials for the Integration of III-V Based Transistors
Authors: Givens Michael , Tang Fu , Xie Qi , Maes Jan Willem
Published: October 2015

III-V compound semiconductors are promising transistor channel materials to enable scaling beyond Si technology due to their high bulk electron mobility values. Engineering the III-V / high-k gate stack remains one of the main technical challenges to integration of these materials in CMOS technology, with Atomic Layer Deposition (ALD) continuing to play an enabling role. In this work, multiple approaches for interfacial sulfur passivation prior to high-k gate stack deposition are explored, with passivated samples exhibiting improved C-V characteristics and reduced Dit values for planar MOSCAPS. Various III-V channel / high-k metal oxide interface layers (ILs) deposited by ALD have also been evaluated in order to reduce the impact of oxide traps while also maintaining a low Dit. A novel ALD interfacial layer material has been developed which demonstrates the potential to meet challenging requirements for III-V channel transistor integration.
ALD TaN Barrier for Enhanced Performance with Low Contact Resistance for 14nm Technology Node Cu Interconnects
Authors: Nag Joyeeta , Cohen Brian , Choi Samuel , Ogino Atsushi , Oh Minseok , Yan Yan , Liang Jim , Christiansen Cathryn , Kim Andrew , Li Baozhen , DeHaven Patrick , Madan Anita , Krishnan Siddarth , Simon Andrew H
Published: October 2015

We report on an alternative atomic layer deposited (ALD) TaN barrier process for Cu interconnects for 14nm technology node and beyond. ALD films provide ultrathin, conformal barrier with reduced overhang and bottom thickness in contrast to physical vapor deposited (PVD) films. This enables via-contact resistance reduction and improved gap-fill while maximizing Cu volume in a trench/via structure. Blanket film studies show that ALD films are 10-15% less dense compared to Ta-rich PVD films, and more importantly only desired low-resistance a-Ta nucleates on ALD films vs. thin PVD films. To maximize density while protecting low-k dielectric during deposition and maintaining low-contact resistance, we explored different flavors and combinations of thermal (tALD) and plasma-enhanced ALD (PEALD). We achieved via contact resistance reduction of 25-35%, with equivalent or better performance for yield, defectivity and electromigration (EM), time-dependent dielectric breakdown (TDDB) and stress migration (SM) reliability.
(Invited) Metallic Nanocoatings on Optical Fibers as a Sensor Platform
Authors: Mandia David J. , Zhou Wenjun , Wells Adam , Albert Jacques , Barry Sean Thomas
Published: October 2015

Deposition of gold metal on a tilted fiber Bragg grating (TFBG) demonstrates the utility of this optical fiber as a sensor for the conditions at the fiber's surface, including the continuity of a deposited metal film. Two precursors for the deposition of metallic gold are contrasted: gold(I) N'N'-dimethyl N,N”-diisopropylguanidinate (1) and gold(I) tert-butyl-imino-2,2-dimethylpyrrolidinate (2). Characterization of the deposition by optical fiber spectroscopy highlights the difference in thermal stability and growth rate of these two compounds. Compound 1 has a tremendous growth rate (220 nm/min) but is very thermally unstable, while 2 is much more thermally stable, and shows a lower growth rate of 1 nm/min.
Synthesis of ALD Tungsten Trioxide Thin Films from W(CO)6 and H2O Precursors
Authors: Zhang Kai , McCleese Christopher , Lin Pengtao , Chen Xin , Morales Monica , Cao Wei , Seo Felix J. , Burda Clemens , Baumgart Helmut
Published: October 2015

Tungsten oxide (WO3) was successfully deposited by atomic layer deposition (ALD) usingtungsten hexacarbonyl [W(CO)6] and DI water [H2O]. A saturated growth rate is of 0.2 Å perALD cycle was determined at a growth temperature of 300 °C. The as-deposited ALD WO3 filmswere found to be amorphous, which was corroborated by X-ray diffraction. Post-depositionthermal annealing at an elevated temperature transformed the WO3 phase to a monoclinic crystalstructure. The optical measurement confirmed that the ALD WO3 thin film possessed a band-gapof ~ 3.28 eV.
(Invited) Atomic Layer Etching Using Thermal Reactions: Atomic Layer Deposition in Reverse
Authors: Lee Younghee , DuMont Jaime W. , George Steven M.
Published: October 2015

Atomic layer etching (ALE) can remove thin films with atomic layer control based on sequential, self-limiting surface reactions. ALE can be viewed as atomic layer deposition (ALD) in reverse. This paper reviews Al2O3 ALE using sequential, self-limiting thermal reactions. In the proposed mechanism for thermal Al2O3 ALE, fluorination reagents, such as HF, fluorinate the Al2O3 substrate to form an AlF3 surface layer and volatile H2O. A metal precursor, such as Sn(acac)2, subsequently accepts fluorine from the AlF3 surface layer and donates an acac ligand to the aluminum in the AlF3 surface layer to form volatile Al(acac)3 or AlF(acac)2 reaction products. These fluorination and ligand-exchange reactions with HF and Sn(acac)2 lead to temperature-dependent etching rates of Al2O3 from 0.14 Å/cycle at 150°C to 0.61 Å/cycle at 250°C. This reaction mechanism can be extended to a variety of other materials including metal nitrides, metal phosphides, metal arsenides and elemental metals.
(Invited) Ultrapure Water for Advance Semiconductor Manufacturing: Challenges and Opportunities
Authors: Libman Slava , Wilcox Daniel , Zerfas Bernard
Published: October 2015

Increasing complexity driven by “Moore and More” continuously challenges Ultrapure water (UPW) process capabilities. The “killer” particle size has shrunk to 10nm for the most advanced semiconductor processes, which is beyond the capability of most UPW treatment technologies. Recent data suggests that particles in UPW may exceed current industry requirements. New industry standards have been developed recently to better understand and mitigate the defectivity challenge, which is escalating as the killer particle size approaches limitations of the best available filtration technology. In addition to particles, other trace contaminants pose risks to the most advanced manufacturing. This includes hydrogen peroxide generated in Ultraviolet treatment as well as dissolved organic contaminants, either originating from incoming city water or introduced by UPW system materials. Better understanding of the effects of UPW impurities to the manufacturing process can help to mitigate risks to yield loss and thereby reduce costs.
Oxygen Control Challenge for Advanced Wet Processing
Authors: Yoshida Yukifumi , Otsuji Masayuki , Takahashi H. , Snow Jim , Sebaai Farid , Holsteyns Frank , Mertens Paul W. , Sato Masanobu , Shirakawa Hajime , Uchida H.
Published: October 2015

A control of Dissolved Oxygen (DO) in liquids and oxygen concentration in ambient atmosphere for semiconductor processing is described. The effects of low DO in wet processing for galvanic corrosion and water mark formation were evaluated using various oxygen concentration conditions with HF or HCl mixtures. It was found that the low DO concentration condition (25ppb) prevented the occurrence of defects (voiding, trenching or water marks). The results from processing a device sample showed that low DO concentration condition is required for advanced CMOS processing.
Prevention of Metal Contamination in Sub 50 Nm SC1 Cleaning Process
Authors: Kim Hyun-Tae , Park Gun-Ho , Cho Byoung-Jun , Lee Jung-Hwan , Kim Min-Su , Kim Jin-Yong , Park Jin-Goo
Published: October 2015

In this study, we investigated the relationship between particle removal efficiency (PRE), surface etch rate and removal of metal contaminant with various concentrations of SC1 cleaning solution. To identify the relationship between etch rate and the formation of defect, etch depth was measured for various compositions of SC-1 solution by using atomic force microscopy. Si wafers were contaminated with Cu ions and particles by dipping method. Cu precipitate and particles on Si surface were counted by using atomic force microscopy and a dark field optical microscope respectively to evaluate cleaning efficiency of SC1 solutions. The effect of SC1 compositions on Si etching was also investigated. It is observed that with increase in H2O2 concentration both Cu contamination and PRE decreases. This study suggests that the SCl cleaning solution needs to be optimized in order to achieve lower Cu contamination with a high PRE.
Behavior of Nickel Deposition on Silicon Wafers from TMAH and Ammonia based SC1 Cleaning Process
Authors: Sinha Drew
Published: October 2015

Behavior of nickel adsorption on silicon wafer from SC1 process, based on TMAH, is studied as a function of TMAH concentration, etch rate, residence time in solution. Deposition behavior of nickel on wafer surface is also investigated, from SC1 and dilute hydrochloric acid solution, intentionally contaminated with nickel. Temperature dependence in the behavior of nickel deposition from Ammonia based and TMAH based SC1 solution, is investigated. Finally, characterization of surface-deposited nickel on the wafer surface from the SC1 solution is carried out to provide possible mechanism and nature of deposited nickel.
Submicron Particle Removal during FPD Oxide TFT Process
Authors: Lee Jun , Kim Min-Su , Kim Hyun-Tae , Choi In-Chan , Kim Woo-Young , Lim Dae-Seung , Park Jin-Goo
Published: October 2015

In panel manufacturing processes, cleaning process was not considered to be critical thus far. However, as pixel size is becoming smaller nowadays, the number of pixels per unit area is gradually increasing due to the high resolution. Consequently, an influence of submicron sized contaminated particles is increasing, and hence attention needs to be given to cleaning process. For a large area and high resolution panel with a good production yield, a research on an effective cleaning process which can remove the contaminated particles deposited on the Cu, SiO2 and ITO surfaces is required. Generally, physical cleaning processes are used to remove the submicron particles in FPD (Flat Panel Display) process. In this study, we have optimized these cleaning processes to remove the submicron particles from the substrate surface. Here, we achieved a high cleaning efficiency of above 95% in the EIW megasonic cleaning process on all the substrates.
Effect of Particle Contamination on Extreme Ultraviolet (EUV) Mask and Megasonic Cleaning Process for Its Removal
Authors: Kim Min-Su , Ji Hye-Rim , Choi In-Chan , Kim Hyun-Tae , Jang Sung-Hae , Lee Jun , Kim In-Seon , Kim Jung-Hwan , Oh Hye-Keun , Ahn Jin-Ho , Park Jin-Goo
Published: October 2015

Particle contaminants on EUV mask surface can cause CD error during EUV lithography process. These contaminants should be removed from EUV mask. The critical size of defect which can cause 10 % CD error is about 23~38 nm with various materials. Among them, critical defect size of SiO2 is about 30 nm. To remove this 30 nm fine silica particle, megasonic cleaning was adapted with various megasonic frequencies and with various cleaning solutions such as dilute alkali solution and gas dissolved water. At high megasonic frequency (2 MHz), though bubble cavitation effect is decreased, cavitation threshold value is higher even with the addition of gases into cleaning solution. As a result, higher particle removal efficiency of 30 nm silica particles and lower damages on PR pattern is achieved at 2 MHz megasonic cleaning in a cleaning solution of H2 gas and dilute NH4OH as compared with 1 MHz megasonic cleaning.
Removing Organic Residues Using Backside Brush Scrubber Clean
Authors: Chauhan Kripa Nidhan , Sih Vincent , Bhat Talapady , Kang Min Hyo , Kabutoya Eiji , Cheng Gordon
Published: October 2015

In 2X nm devices, high-k metal gate have become an essential part of emerging devices. Wet cleaning plays an important part of advanced semiconductor manufacturing process. As the technology node advances, it has become more and more challenging. Presence of organic residues and cluster of particles on product wafers can cause lot of issues. These clusters of particles and organic residues are found to be die killers and hence, reduce the yield of the product. In this work, we will focus on root cause finding for the organic residue and clusters. The proposed solution demonstrates the improvement of 11X and yield gain of 3.5% as compare to product wafers, and cost savings for HVM (high volume manufacturing).
Effect of Surface Energy Reduction for Nano-Structure Stiction
Authors: Koide Tatsuhiko , Kimura Shinsuke , Iimori Hiroyasu , Sugita Tomohiko , Sato Katsuhiro , Sato Yohei , Ogawa Yoshihiro
Published: October 2015

Nano-structure stiction during drying has often occurred due to scaling of semiconductor devices. For less stiction drying technology, lower surface tension liquids such as isopropyl alcohol (IPA) or super critical fluid (SCF) have been developed, but are lacking in enough performance or maturity for 300 mm leading-edge device wafer treatment. Thus, we have focused on the surface energy reduction process which enables separation of the once adhering structures. We have evaluated the effect of the surface energy on the stiction with both calculation and experimental data, and have successfully demonstrated that the surface energy reduction process can suppress high aspect-ratio nano-structure stiction.
(Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture
Authors: Wostyn Kurt , Sebaai Farid , Rip Jens , Mertens Hans , Witters Liesbeth , Loo Roger , Hikavyy Andriy Yakovitch , Milenin Alexey , Horiguchi Naoto , Collaert Nadine , Thean Aaron , Mertens Paul W. , De Gendt Stefan , Holsteyns Frank
Published: October 2015

The Gate All-Around device architecture requires the formation of semiconductor nanowires. As an example SiGe nanowires can be formed by the selective removal of rSi in a Si-SiGe fin-shaped stack. In this paper we will show how alkaline solutions can be used for the selective removal of Si to SiGe and SiGe to Ge. We will also show that the anisotropy of the SiGe alkaline etch is not an extension of Si, even at low to moderate Ge concentrations (Ge ≤ 50%).
Advanced Wet-Etch-Only Process for Complete Tri-Layer Rework
Authors: Steinke Philipp , Calvo Jesús , Uhlig Benjamin
Published: October 2015

A tri-layer patterning technique is used for high numerical aperture immersion lithography at 28 nm node. The tri-layer consists of a photoresist (PR) deposited on a silicon-containing anti-reflective coating (SiARC) above an organic planarization layer (OPL). Defective PR processes (e.g. overlay, over-exposure, residues) are repeatedly being reworked in high volume manufacturing. Due to the different chemical composition of the three layers, multiple etch processes are necessary. In this work, we investigate a wet-etch-only tri-layer rework approach that has the advantage of lower material damage, cost reduction and increased throughput. Complete stack removal and low defect levels on patterned 300 mm wafers could be achieved.
Wet Etchant Diffusion through Photoresist during Gate Oxide Patterning
Authors: Neyens Marc , Garnier Philippe , Garach Manon , Rochat Nevine , Licitra Christophe , Tiron Raluca
Published: October 2015

Gate oxide patterning during integrated circuits manufacturing can be defined by a photolithography and wet etch sequence. Wet etching process can be at risk. Indeed, during this step, liquid molecules can penetrate through resist layer to reach and damage the underlying material. The key parameter to know is the maximum duration that a given resist can ensure an effective protection. This study shows in the first time how to evaluate etching molecules diffusion thanks to ATR-FTIR technology and a gravimetric approach. Then a two-steps diffusion model has been established. Finally, differences are observed between four different commercial resists.
Post Salicidation Clean: Removal of Unreacted Pt from High Pt Content NiPt Silicide
Authors: Sehgal Akshey , Derderian Garo , Muralidhar Pranesh
Published: October 2015

Silicides are used for providing stable ohmic contacts on gate, source and drain areas. After the silicide is formed, unreacted silicide is removed by using strongly oxidizing wet clean solutions. For 2x nm technologies, Ni Pt has been used as a salicide with progressively higher amounts of Pt used for each advanced node. Complete removal of unreacted Ni Pt was found to have become became intermittent when the Pt content in the silicide exceeded 10%. The residual unreacted Ni Pt stringers were found to be pure Pt. A wet clean process was developed to remove unreacted Pt in all cases and its manufacturability determined for a semiconductor high volume manufacturing production line.
Dual-Fluid Spray Process for Particle and Fluorocarbon-Polymer Removal in BEOL Applications
Authors: Iwasaki Akihisa , Higuchi Ayumi , Komori Kana , Sato Masanobu , Shirakawa Hajime
Published: October 2015

Surface cleaning of patterned wafers by single wafer cleaning processing has become increasingly challenging as semiconductor fabrication makes deep inroads into sub-20 nm technology nodes. One of the most critical challenges for BEOL is a post-etch-residue cleaning in the trenches and vias without causing pattern damage and k-value change of low-k materials. Not only the chemical step but also rinse step is required to completely remove post dry-etch residue, which is fluorocarbon-based polymer residue in the structure. In this paper, a novel dual-fluid spray process for post-etch-residue cleaning has been developed. An optimized process could enable simultaneous higher particle removal efficiency and CF-polymer residue removal efficiency. A certain chemical/DIW mixture made smaller diameter droplets with higher velocities, in addition to excellent CF-polymer dissolved characteristics compared to conventional DIW Nanospray2.
Development of a Cu and W Compatible PERR Clean in BEOL Advanced Interconnect Patterning
Authors: Kesters Els , Le Quoc Toan , Decoster Stefan , Vega Gonzalez Victor , Holsteyns Frank , De Gendt Stefan
Published: October 2015

Low-k integration for 22 nm ½ pitch technology requires continuous development of compatible cleaning processes. In this paper the use of acidic (pH:0.5-3) and alkaline (pH:8-13.5) aqueous based chemistries are demonstrated for the removal of post-etch residues after low-k etch and the aim to remove the TiN HM. These chemistries are also compatible with W and Cu, respectively. At the same time, no decrease in CD was observed, which means that the exposed low-k material was not attacked by the cleaning processes used.
Nanoscale Etching: Dissolution of III-As and Ge in HCl/H2O2 Solutions
Authors: van Dorp Dennis H. , Weinberger David , Van Wonterghem Simon , Arnauts Sophia , Strubbe Katrien , Holsteyns Frank , De Gendt Stefan
Published: October 2015

In this work the etching kinetics of (100) III-As is studied at the nanoscale with ICP-MS for various HCl/H2O2 mixtures. It is shown that the etch rate is controlled by both the concentration of the acid and the oxidizing agent. The surface termination during etching has strong impact on the etching kinetics. A similar effect was observed for Ge. The Ge (100) surface is sensitive to surface roughening during etching and reoxidation after native oxide removal.
Chemical Passivation of In0.53Ga0.47As(100) Using Ammonium Sulfide and Thiols
Authors: Contreras Yissel , Muscat Anthony J.
Published: October 2015

Dilute solutions of (NH4)2S in water and of 1-eicosanethiol (ET) in ethanol were used to deposit a protective layer to prevent the reoxidation of clean In0.53Ga0.47As(100) substrates. The surface composition of the InGaAs after oxide etching in 0.3 M HF, and after immersion in (NH4)2S or ET solutions was studied using XPS. Immersing clean InGaAs substrates in 4.0 mM ET for 20 h protected the surface for 4 min, after which oxide states were detected by XPS. A 20 min immersion in 3 mM (NH4)2S in a glove box slowed down the reoxidation process. After 1 h of atmosphere exposure, the amount of InGaAs oxides on the surface treated in (NH4)2S were lower than those of a control sample after only 4 min of air exposure. The sulfur layer deposited from aqueous ammonium sulfide and the self-assembled eicosanethiol layer blocked reoxidation and chemically passivated the surface only for brief ambient exposures.
Dissolution of Germanium in Sulfuric Acid Based Solutions
Authors: Gan Nobuko , Ogawa Yuichi , Nagai Tatsuo , Masaoka Toru , Wostyn Kurt , Sebaai Farid , Holsteyns Frank , Mertens Paul W.
Published: October 2015

The phenomenon and mechanism of germanium (hereinafter Ge) dissolution in sulfuric acid based solutions were studied. The sulfuric acid concentration, the presence of an oxidizer and the treatment time were varied as parameters of these tests. It was clarified that Ge surface is covered by two layers: germanium dioxide (hereinafter GeO2) and germanium monoxide (hereinafter GeO). GeO2 dissolves easily in water and in the sulfuric acid solutions with high water fraction. On the other hand, the dissolution of GeO and Ge is influenced strongly by the sulfuric acid concentration in the solution and the treatment time when oxidizer is present in the solution.
Surface Cleaning of SiGe(100) and Passivation of Ge(100) with Aqeuous Ammonium Sulfide
Authors: Heslop Stacy Lynn , Engesser Philipp , Okorn-Schmidt Harald F. , Muscat Anthony J.
Published: October 2015

The effect of standard aqueous cleans including SC-1, HCl, HF, and HCl/HF mixtures on SiGe(100) surfaces with 50, 75 and 85% Ge molar ratios was characterized with x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry. HF was most effective at removing both Ge and Si oxides and reduced the carbon contamination. SC-1 selectively depleted Ge from the surface. Passivation of Ge(100) surfaces with aqueous (NH4)2S was characterized with XPS as a function of the solution concentration and with the addition of H2O2. The passivation process was independent of the (NH4)2S concentration and approximately 3 Å of S was deposited or about one layer based on XPS. Addition of H2O2 to very dilute (NH4)2S oxidized the surface while addition to higher concentrations showed similar effects as a sequential HCl/H2O2 treatment.
Evaluation of InGaAs and InP Compatibility with Alkaline Photoresist Stripping Formulations
Authors: Westwood Glenn
Published: October 2015

The compatibility of InGaAs and InP with a series of proprietary and non-proprietary stripping formulations was investigated. Acidic and aqueous alkaline chemistries were found to be compatible, but semi-aqueous alkaline formulations displayed a variety of compatibilities, from the most compatible to least compatible chemistries tested. For semi-aqueous alkaline solutions, solvent selection and water content have a large impact on InGaAs and InP compatibility, but alkali selection was determined to be the most critical component for InGaAs and InP compatibility.