bluuebunny/crossref_metadata_2025 huggingface dataset:
Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation
Authors: Kiyan T. , Boit C. , Brillert C.
Published: January 2021

In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.
Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation
Authors: Shaw Jonathan , McMahon Christopher , Ng Yin Shyang , Beaudoi Félix
Published: January 2021

This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.
Mixed Frequency Detection of Thermal Laser Stimulation (MF-TLS) and Its Application in Failure Analysis
Authors: Qian Zhongling , Brillert Christof , Burmer Christian
Published: January 2021

A new localization method called MF-TLS is introduced and applied in failure analysis praxis. The method combines local periodic thermal stimulation technique with periodic excitation of the electrical fails. The mixed frequency signal is detected by a lockin amplifier. MF-TLS was demonstrated on fabricated opens in a metal line and shown to be in semi-quantitative agreement with a capacitance modulation model. The technique was also applied to a scan shift problem and produced a higher sensitivity compared with other dynamic TLS methods. Limits and prospects of this new methodology are described.
Analysis of Deep Trench Node Leakage Depth by Applying Current Imaging Technique at Silicon Level
Authors: Doering S. , Seitz M. , Zimmermann U. , Rodger P. , Werner W.
Published: January 2021

In case of a node leakage failure in DRAM products, the location of the defect can be spread over the entire deep trench depth of up to six microns, making it very difficult to precisely localize the defects. In addition, the use of surface area enlarging techniques makes it even more difficult to pinpoint the node leakage defect. In this study, first, the node leakage was verified at contact level using the nano-probing technique. In the second step, the sample was deprocessed into the p well level and a current image was obtained, confirming the node leakage to be located below this level. In the third step, the sample was further deprocessed to the edge of the n well level. AFM-based probing provided additional information regarding the location of the node leakage. With these three measurements, the authors confined the node leakage to the small n well region.
Laser Scanning Localization Technique for Fast Analysis of High Speed DRAM Devices
Authors: Versen Martin , Schramm Achim , Schnepp Jan , Hoch Sascha , Vikas Tapan , Diaconescu Dorina
Published: January 2021

Soft defect localization (SDL) is a method of laser scanning microscopy that utilizes the changing pass/fail behavior of an integrated circuit under test and temperature influence. Historically the pass and fail states are evaluated by a tester that leads to long and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before. This new method speeds up significantly the turn-around time in the failure analysis (FA) process compared to knowledge based FA.
Novel Application of the OBIRCh Amplifier for Timing Failure Localization
Authors: Sienkiewicz M. , Perdu P. , Brule S. , Firiti A. , Crepel O.
Published: January 2021

Soft defects localization by laser techniques on dynamically working ICs is widely used for Failure Analysis (FA). In this context, many AC signal-oriented analysis methods have been introduced to date (SDL, LADA…) or are under development (xVM…). Sophisticated tools are available to localize these kinds of failures but not every FA laboratory has them. By fully exploiting the capabilities of static localization tools, it is possible to deal with timing issues. In this paper, we propose a novel application of the OBIRCh amplifier related to the timing issues on a real case study (mixed-mode device). This novel and very simple application makes the analysis flow time-attractive and enlarges the application field of mapping techniques on the existing tools.
Novel Sample Preparation Technique for Backside Analysis of Singulated Die
Authors: Elliott S. , LaPierre M. , Plourde P.
Published: January 2021

A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
Innovative Method & Use of UV Technologies for Dye Penetrant Sample Preparation
Authors: McDonald Todd R.
Published: January 2021

Today’s high volume FA labs are constantly looking for ways to improve the data to customer cycle. Current dye & pull sample preparation materials and methods have some time to completion requirements that cannot be avoided without compromising data. This paper demonstrates that significant improvements in data cycle time and quality can be realized by using a combination of the latest UV cure adhesives, masks, and complimentary equipment such as LED cure lights and gantry dispensing robots.
Next Generation Laser Voltage Probing
Authors: Ng Yin S , Lo William , Wilsher Kenneth
Published: January 2021

We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].
A Study of the Photoelectric Effect Caused by a Laser Beam Used in a Beam Bounce Technique in a C-AFM System
Authors: Lin Hung-Sung , Wu Mong-Sheng
Published: January 2021

The use of a scanning probe microscope (SPM), such as a conductive atomic force microscope (C-AFM) has been widely reported as a method of failure analysis in nanometer scale science and technology [1-6]. A beam bounce technique is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for a beam bounce also gives rise to the photoelectric effect while we are measuring the electrical characteristics of a device, such as a pn junction. In this paper, the photocurrent for a device caused by photon illumination was quantitatively evaluated. In addition, this paper also presents an example of an application of the C-AFM as a tool for the failure analysis of trap defects by taking advantage of the photoelectric effect.
Applications of C-AFM and CBED Techniques to the Characterization of Substrate Dislocations Causing SRAM Soft Single-Column Failure Contained in a Wafer with (001) Plane/[100] Notch
Authors: Lin Hung-Sung , Chen Tung-Hung , Shu Wen-Cheng
Published: January 2021

SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture. However, the success rate of defect detection, especially for soft single-column failures, is decreasing when traditional physical failure analysis (PFA) with only the bitmap is available for guidance. This is due to a variety of invisible or undetectable defects that cause leakage in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, a Conductive Atomic Force Microscope (C-AFM) [1-4] is introduced to perform junction-level fault isolation prior to attempting PFA. According to J. P. Morniroli [5], crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations to allow further characterization of these defects. In this study quantified data extracted using the C-AFM is also used to establish a connection between the failure mechanism discovered and the soft single column failure mode.
Electroluminescence Analysis by Precise Tilt Polish Technique of Edge-Emitting Laser Diode
Authors: Ichikawa Hiroyuki , Sasaki Kouichi , Hamada Kotaro , Yamaguchi Akira
Published: January 2021

We have employed electroluminescence (EL) analysis of an edge-emitting laser diode (LD) to detect possible defects. To extract EL emission from a LD, we developed a tilt polish technique of the bottom electrode. We can successfully observed clear EL emission. A high yield of 99.2 % was achieved by the introduction of the precise tilt polish technique.
Development of PECS Application for Sample Preparation
Authors: Chen Xianfeng , Li Ming , Guo Qiang , Kary Chien W.T.
Published: January 2021

Cross-sectional polishing has been widely used in the semiconductor industry. As demand for higher throughput increases, the time spent manually performing a final polish is an improper method for cross-section preparation. Etching is the major function of Precise Etching and Coating System (PECS). In this article, the focus is on Ar plasma cleaning performance on a sample after rough polishing and a sample after a short time final polishing using PECS. To evaluate performance of Ar plasma cleaning, two samples were prepared for SEM observation. X-SEM images before and after Ar plasma cleaning revealed that Ar plasma cleaning is not an effective method to correct micro scratches. The combination of final polishing and stain into one step was found to improve sample quality and throughput. PECS Ar plasma was found to be an effective sample cleaning method when compared to the time spent on final polishing.
Automated Sample Preparation of Packaged Microelectronics for FESEM
Authors: Cerchiara R. R. , Fischione P. E. , Boccabella M. F. , Robins A. C.
Published: January 2021

A packaged device based on a ball grid array or other design presents a challenge to the failure analyst. Accessing one of the metal levels from the topside requires decapsulation by either a wet, predominantly dry (RIE) or a completely dry (mechanical) treatment. To reveal the details of the gate including the gate oxide, new approaches to selective etch delineation by RIE are required. This article presents an automated sample preparation method for packaged microelectronic materials by combining plasma cleaning, ion beam etching, reactive ion etching and ion beam sputter coating. A single etch gas chemistry was effective in phase delineation by RIE. Future work to further delineate the gate oxides could support accurate metrology by means of FESEM rather than field emission transmission electron microscope.
Studies of Fluorine-Induced Corrosion and Defects on Microchip Al Bondpads and Elimination Solutions
Authors: Younan Hua , Rao Nistala Ramesh , Jennifer Teong
Published: January 2021

In this paper, a comprehensive study of Fluorine-induced Aluminum bondpad corrosion will be presented. Fluorine corrosion is detrimental to Al pad quality resulting in non-stick on pad (NSOP). In wafer fabrication, NSOP refers to lift-off of Au wire-bond from the surface of Al bondpad due to its poor adhesion to the contaminated pad surface. It will be shown that besides the well-known corrosion mechanism that causes NSOP, namely, via the formation of Al fluoride defect ([AlFx](x-3)-), it can also happen due to Al fluoride oxide defect, AlxOyFz. Unlike the Al fluoride defect, which has a unique “flower-like” shape, Al fluoride oxide defects exist in a variety of shapes: “Crystal-like”, “Oxide-like” and “Cloud-like”. The physical dimensions of these defects (including Al fluoride) can be dramatically different, varying all the way from micron to nanometer. In this paper, each of these morphological shapes and their respective failure mechanisms will be covered. Solutions to mitigate F-corrosion and ways to control/monitor contamination on Al pad surface in wafer fab will be presented.
Optimization of SEM Analytical Conditions for Low K and Ultra Low K Dielectric Materials
Authors: Binghai Liu , Zhiqiang Mo , Younan Hua , Jennifer Teong
Published: January 2021

Electron beam induced radiation damage presents great challenges for the electron microscopy analysis of low k and ultra low k dielectrics due to their beam sensitive nature. In order to minimize the radiation damage, it is necessary to understand the mechanisms behind the damage. This work presents detailed studies regarding the mechanisms behind the effects of probe currents, accelerating voltage and anticharging coating layers on the radiation damage to low/ultralow K dielectrics. The results indicate that the probe current shows a stronger dependence on the size of the condenser lens aperture than the accelerating voltage. Therefore, in terms of the probe current, the condenser lens aperture plays a decisive role in affecting the radiation damage process. In order to minimize the radiation damage, SEM imaging should be conducted with not only a low accelerating voltage but also a small condenser lens aperture to reduce probe current. Based on simulation results, the effects of a coating layer and accelerating voltage are related to the interaction volume and the penetration depth of the electron beam. Pt coating can act as not only an anti-charging layer, but also an effective barrier layer for reducing electron flux that interacts with the low/ultra-low dielectrics.
Using Cross-Triggering in Oscilloscope for Debugging Multiphase Converter Circuit of Personal Computer (PC) Motherboard
Authors: Nguyen Binh , Diaz Orlando
Published: January 2021

Analyzing a failure on multiphase converter circuit on PC motherboards presents significant challenges due to the high number of nodes and the timing relationship between them. Typically a standard 4-channel oscilloscope can not capture the necessary timing relationship to effectively analyze the whole circuit. This article presents a simple and low-cost solution that can effectively help the users overcome the challenges of debugging multiphase converter circuit of PC motherboards.
Doping Profile Measurements in a 65-nm Commercial Product Using Atom Probe Tomography
Authors: Klibanov Lev , James Dick , Isheim Dieter
Published: January 2021

Doping profile measurements in extremely small features like transistor gates or source/drain regions is a challenging task for the semiconductor industry. In our article, we successfully used an atom probe tomography (APT) tool to measure the doping concentration and profile of the dopant elements in a commercial 65 nm product. APT not only delivers doping concentrations but also gives the highest spatial resolution (sub-1 nm) three-dimensional compositional information of any microscopy technique.
Failure Analysis of Nitride-Trapping Memory Cell Failures
Authors: Chen Wen-Rong , Chen Yu-Ju , Chang I-Cheng , Chiang Hsin-Hsu , Kuo Li-Kuang , Yin Shaw , Lu Chih-Yuan
Published: January 2021

The 2-bit/cell nitride-trapping device (NROM/Nbit) is an important type of NVM (Non-Volatile Memory). The NROM/Nbit is a potential candidate for replacing FG-type NVM devices below the 45nm node. In this study, electrical and physical failure analyses (PFA) were used. The failure mechanisms and root causes of failure for the test vehicle, a 130nm NBit device, were determined. Because cell dimensions and spacing requirements for high-density memory are quite aggressive, these observations help to optimize process and improve yield.
Advanced Methodologies for Backside Circuit Edit
Authors: O’Donnell E. , Scott D. , Malik T. , Jain R. , Lundquist T. , Schlangen R. , Kerst U. , Boit C.
Published: January 2021

Editing inside an integrated circuit (IC) is critical to debug new devices. Current flipchip circuit edit techniques are limited by spot resolution and chemistry constraints of Focused Ion Beam (FIB) systems. The newly proposed technique for circuit edit (CE) employs FIB to contact circuit nodes directly on transistor level, offering a wide range of applications since it allows accessing every signal on a chip. The general functionality and the influence on chip performance are evaluated for an Intel 65nm process technology.
High Precision Ion Beam Milling with Time of Flight Compensation
Authors: Holtermann Theresa , Graupera Anthony , Rosenberg Steve , DiBattista Michael
Published: January 2021

Advanced semiconductor process technologies demand that patterns are milled precisely and without beam overshoot, which could damage adjacent transistors or expose neighboring interconnects. As mill box size becomes small enough and contains fewer pixels, the probability of the beam landing accurately at any given pixel for the prescribed pixel time becomes low. This has forced operators to employ higher than desired pixel times in order to preserve pattern acuity at the expense of optimized gas enhancement. In this article, the authors demonstrate the ability to machine and fill 50nm vias in advanced semiconductor process technologies. This capability is enabled directly by time of flight (ToF) operations. ToF compensation provides a significant advantage for patterning accuracy in advanced circuit edit applications. It enables FIB operators to use drastically shorter dwell times and pixel rates to enhance gas milling and deposition activities.
Applications of In-situ Sample Preparation and Modeling of SEM-STEM Imaging
Authors: Young R.J. , Buxbaum A. , Peterson B. , Schampers R.
Published: January 2021

Scanning transmission electron microscopy with scanning electron microscopes (SEM-STEM) has become increasing used in both SEM and dual-beam focused ion beam (FIB)-SEM systems. This paper describes modeling undertaken to simulate the contrast seen in such images. Such modeling provides the ability to help understand and optimize imaging conditions and also support improved sample preparation techniques.
Sample Preparation Technique for Bond Pad IMD (Inter-Metal Dielectric) Damage Observation
Authors: Huan Y. S. , Kuo Y. L. , Lin Y.T. , Chen Jeff , Lee K.Y.
Published: January 2021

Wire bonding is the most highly used interconnection technology in the packaging of integrated circuits. One of the potential risks of wire bonding is the damage on the oxide layers underneath the bond pad. Oxide damage monitoring is necessary to ensure bonding has no impact on the oxide layers under the bond pad. Since the oxide layer is not seen by visual inspection, bond pad stripping is necessary. Three bond pad stripping chemicals KOH, Aqua regia, and phosphoric acid were investigated in this study. Results obtained by dipping the chemicals at different temperatures, and time scales will be given. An optical microscope (OM) and scanning electron microscope (SEM) are used to observe the oxide conditions from the top view. To understand the mechanism of the oxide damage caused by wire bonding, a focused ion beam was used to observe the cross-section of the defect.
Latent Flash Single Bit and Multiple Bits Systematic Approach to Failure Analysis
Authors: To Hoang-Yen , Nguyen Dat , Dunn Clyde , Davis Detric
Published: January 2021

The flash considered for failure analysis in this paper is a non volatile memory with a NOR architecture in the array and a stacked gate for the bit cell. The flash failure was from data gain reported from various stages and at different temperatures after leaving the wafer fabrication. The failure can be single bit failure (SBF) or multiple bit failure (MBF). The FA process is comprised of two steps termed electrical failure analysis (EFA) and physical failure analysis (PFA). This paper discusses the method to differentiate failure modes and the efforts of fault isolation. Micro probing and nano probe characterization were important in the understanding of the failure mechanism. As seen in the EFA/PFA section, the reported SBF/MBF failures were actually due to a defect in the Mux and not at the bit cell.
Laser Failure Isolation Techniques Demonstrated On Test Structures
Authors: Arnold Frank S.
Published: January 2021

To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.
Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages
Authors: Schwindenhammer P. , Murray H. , Descamps P. , Poirier P.
Published: January 2021

Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.
Improving Fault Isolation Using Iterative Diagnosis
Authors: Gearhardt Kevin , Schuermyer Chris , Guo Ruifeng
Published: January 2021

This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysts to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.
Evaluating PICA Capability for Future Low Voltage SOI Chips
Authors: Stellari Franco , Song Peilin , Vickers Jim , Shaw Chris , Kasapi Steven , Ispasoiu Radu
Published: January 2021

In this paper we evaluate the possibility of extending Time Resolved Emission (TRE) technology towards future low voltage SOI technologies. In particular, we investigate and quantify the gain offered by the InGaAs detector improvements devised by Credence Corp., now DCG Systems, the manufacturer of the Emiscope III PICA system used in this analysis. Experiments on a test chip fabricated in the IBM SOI 65 nm technology will demonstrate that the improved tool guarantees the same Signal-to-Noise Ratio (SNR) even at ~90 mV lower supply voltages. In the second part of the paper we also discuss various other acquisition optimizations of the system. Although the analysis presented here refers to a specific tool, the large majority of the results and discussions can easily be generalized and applied to other PICA systems and detectors, as well as low voltage bulk silicon technologies.
An Application of a Nanoprobe Technique in the Characterization of Advanced SRAM Devices
Authors: Lin Hung-Sung , Chen Chun-Ming
Published: January 2021

The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.
Oxidation of TiN ARC Layer as a Reliability Issue for ICs
Authors: McVeigh Martin , Raz Avi , Kindt Willem J. , Gomes Alfred , Wong Kar Yee , Inamine Tricia , Bold Thomas J.
Published: January 2021

During moisture-and-bias reliability stress tests of THBT (temperature and humidity biased test) and HAST (highly accelerated stress test) extensive electrochemical oxidation of a TiN ARC layer is seen to occur. This oxidation proceeds at the nominal temperatures and humidity levels associated with such THBT and HAST tests; excessive heating due to EOS (electrical overstress) or other anomalous electrical conditions was not involved. The oxidation rate increases with applied voltage. Metal line width also affects the spread of oxidation. Oxidation requires the presence of adequate humidity to act as an electrolyte, and therefore is seen to propagate wherever moisture penetration can occur in the passivation dielectrics. The presence of a silicone gel die coating is found to render the die more susceptible to TiN oxidation. Electrical failures – typically open circuits or increased resistance due to corrosion – are found to occur as a consequence of this oxidation and its effect on the surrounding structures. This mechanism is a concern for integrated circuits with TiN in the upper metal layers, operating at voltages >5V in humid conditions. Two approaches at reducing this electrochemical reaction are offered.
Timing Problems Due to Spacer Bridging in a Sub-100 nm Product
Authors: van Hassel Jan
Published: January 2021

In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.
A Study to Remove Heavy Polymer Remain on Thick Metal (> 3 micron) Sidewall Profile after Metal Etch Solvent Clean Step
Authors: Liew S. F. , Mohammad K. A. , Liu L. J. , Chong S.F. , Lee D. G. , Lee S.F. , Lee B.C.
Published: January 2021

Heavy polymer residue has been observed on the sidewall of thick metal during the process release. The thickness of metal line is more than 3 micron. This thick polymer residue on the aluminum metal sidewall is seen from tilt Scanning Electron Microscope (SEM) profile analysis. This polymer residue on the metal sidewall with chlorine (Cl2) trapped will result in metal corrosion. The focus on this paper is on the removal of this polymer residue on the thick metal sidewall. The experiments were run with splits of varying the chemical dispensing time and the rinsing time in the process. The success criteria are determined by passing the Defect Source Analysis (DSA) and tilt SEM profile analysis. These wafers are sent for electrical test, wet box test (corrosion test) and electrical sort test to ensure the reliability of the post metal cleaning condition.
Yield Enhancement Using a Combination of Wafer Level Failure Analysis and Defect Isolation Software: Case Studies
Authors: Simon Pierre , Thétiot Michel , Picart Bernard , Kardach Cathy , Deslandes Herve , Dudkiewicz Fabien , Roux Jean-Philippe
Published: January 2021

Yield enhancement has always been an important topic but even more when processes are moving towards smaller geometries. Today, latest FA flow intends to check wafer quality to monitor production in real-time. The purpose is to adjust any derivation coming from the process as fast as possible. The Atmel-CIMPACA laboratory located in Rousset, France, can do Failure Analysis on wafer, thanks to its wafer prober designed to work on DCG systems equipment and integrated CAD software (Meridian, Emiscope, NEXS software suite). Wafer level yield analysis typically requires long setup and multiple dies analysis. Each of the die can be studied with a set a failure analysis (FA) techniques (photo or thermal) emission microscopy [1], laser stimulation techniques [2] or even dynamic probing using time resolved emission [3],[4] or laser based techniques, for the most common ones [5].
A Procedure for Identifying the Failure Mechanism Responsible for a Pin-To-Pin Short Within Plastic Mold Compound Integrated Circuit Packages
Authors: Nail Carl , Rocha Jesus , Wong Lawrence
Published: January 2021

Packaging-based short circuits are inherently difficult to analyze due to the unprotected nature of the shorting material in the package. A combination of SQUID, low-power x-ray and OBIRCH techniques were used in conjunction with parallel grinding to identify the location of the short and reveal it for subsequent characterization. This procedure can reliably identify metal-based shorts in most plastic packaging material.
Mis-identified Failures in FETs
Authors: Gores Mark
Published: January 2021

Several recent failure analyses have found that what appeared to be typical source to drain over current damage, was actually caused by intermittently open circuited gate bonds. In power switching applications, such as inverters and switching power supplies, the timing of the transistor’s turn ons and turn offs can be critical. For example in an inverter if the transistor between the positive supply and phase A does not turn off before the transistor between the negative supply and phase A turns on there will be a short circuit between the positive and negative supplies resulting in a high current condition and the failure of both transistors. The original cause of the failure can be masked after the catastrophic failure of the die. The gate does not necessarily remain open circuited. It can reestablish continuity due to the short circuiting of the gate on the die, which causes arcing at the open bond. It is easy to overlook this mechanism in the normal FA process, since there is obvious and sometimes spectacular damage to the die and usually pressure to make a rapid determination of the root cause of failure. The gate wires are more likely to become open circuited because there is usually only 1 wire and it is sometimes a much smaller wire. The wires can become open circuited for a variety of reasons: Mechanical damage to the leads. Inadequate bonds at either end of the wire. Excessive intermetallic formation. Several case histories of open gate wires as well as other open bonds, how they were discovered, and possible screening methods will be discussed.
Intermittent Failures, Challenges and Strategies Involved with Finding Root Cause
Authors: Konkol Nicholas
Published: January 2021

It is often difficult to find the root cause of motherboards that exhibit intermittent failures. This is due to irregularity and inconsistency. When failures occur at irregular intervals or symptoms are inconsistent, it poses challenges to effectively discovering root cause. This article presents strategies that can be used to analyze motherboards that involve failure irregularity, symptom inconsistency, or both. It also discusses the challenges faced in the analyses.
3D STEM Tomography Based Failure Analysis of 45 nm CMOS Devices
Authors: Lorut Frederic , Delille Dominique
Published: January 2021

For a certain class of defects substantial time has to be invested to be able to pinpoint the exact electrical failure location and to perform an accurate and conclusive physical characterization. This article shows that 3D scanning transmission electron microscopy (STEM) tomography in conjunction with an original sample preparation method is a valuable technique to tackle this class of defects and that it can provide very accurate and useful information on these defects. The developed method is applied to analyze several failing devices that are all designed with 45nm design rules and fabricated using a 45 nm technology, and is illustrated with 3 different case studies, each referring to one fault localization method. It is concluded that 3D STEM tomography can provide conclusive 3-dimensional analytical and morphological information on the localized defect, provided that special care is taken to prepare a well-adapted sample.
SEM Si Dopant Contrast Enhancement Using Sample Charging
Authors: Hsieh Yi-Wei , Russell Jeremy D. , Chen Pei-Yi
Published: January 2021

One of the approaches to visualize dopant regions is to use SEM dopant contrast. In silicon, the technique is rather more problematical, presumedly because typical pn-junction built-in potentials are three times smaller. Dapor et al. have reviewed the literature, and made Monte Carlo simulations of dopant contrast. This paper shows that a surface insulator can be used to improve the dopant contrast between p- and n-regions obtainable on SEMs equipped with in-lens SE detectors. Based on the experimental results, it is clear that an organic material can enhance the dopant contrast effect by around 10%, provided that it is exposed to the electron beam. It is therefore reasonable to assume that the dopant contrast enhancement is due to charging of the insulator. Dopant contrast is also influenced by imaging position and scanning time. The method is easy, repeatable, and obtains clear results quickly, solving analysis cases which are quite intractable.
КОМПЛЕКС ПРОФІЛАКТИЧНИХ ЗАХОДІВ ДЛЯ ВАГІТНИХ ПІСЛЯ ДРТ З ВИСОКИМ РИЗИКОМ ПРЕЕКЛАМПСІЇ
Authors: Камінський В’ячеслав Володимирович  , Коломійченко Тетяна Василівна  , Жданович Олексій Ігоревич  , Рогава Ірина Володимирівна
Published: January 2021

The purpose of the study: to evaluate the effectiveness of the proposed set of preventive measures for pregnant women after ART with a high risk of preeclampsia. Material and methods. To test the effectiveness of the proposed set of prophylactic measures, 60 pregnant women after ART were selected, which were randomly divided into 2 groups: 30 women who received the recommended complex (main group) and 30 women (comparison group), whose preeclampsia was prevented by order of the Ministry of Health. № 417 "Guidelines for the provision of outpatient obstetric and gynecological care." Results. The use of the recommended measures improves lipid metabolism (significant reduction of triglycerides and low density cholesterol), eliminates vitamin D deficiency, balances the cytokine profile (reduction of proinflammatory focus), reduces the prothrombotic potential of the hemostasis system (reduction of D-dimer and background marker damage). Improving the general condition and the use of psychotherapy can reduce the manifestations of vegetative-vascular dystonia, anxiety and improve quality of life. Such changes provide a more favorable background for the development of gestation. The incidence of preeclampsia decreased by 43.8% (from 26.7 to 15.0%), and mainly due to early preeclampsia, the incidence of which decreased by 78%, no cases of severe preeclampsia were reported. The frequency of placental insufficiency, fetal distress and growth retardation is reduced. The frequency of birth of children in a state of asphyxia is reduced by 2 times (up to 20.0 vs. 46.7%), severe asphyxia is not observed. Significantly lower and the frequency of violations of the period of neonatal adaptation (30.0 vs. 53.3%). Conclusions. The use of treatment and prophylactic complex to prevent preeclampsia in pregnant women after ART can improve a woman's homeostasis, balance vegetative-vascular regulation, reduce the incidence of preeclampsia by 43.8% (from 26.7 to 15.0%) and other complications of pregnancy and childbirth, improve perinatal outcomes. Proven medical, social and economic efficiency of the developed complex allows to recommend it for implementation in medical practice.
ОПТИМІЗАЦІЯ ТАКТИКИ ВЕДЕННЯ ВАГІТНОСТІ ПІСЛЯ ГРИПУ, ПЕРЕНЕСЕНОГО НА РАННІХ ТЕРМІНАХ ВАГІТНОСТІ
Authors: Камінський В’ячеслав Володимирович  , Коломійченко Тетяна Василівна  , Жданович Олексій Ігоревич  , Деркач Андрій Дмитрович  , Сербенюк Анастасія Валеріївна
Published: January 2021

The obtained results created a theoretical basis for optimizing the tactics of pregnancy management in such patients by applying a pathogenetically sound set of treatment and prevention measures. The proposed complex includes assessment of risk factors, additional examinations, monitoring of the condition of the pregnant woman and fetus, treatment measures to prevent placental insufficiency and reduce the negative effects of hyperimmune response (aspirin, dipyridamole, progestogens, intravenous immunoglobulin, vitamin D).To test the effectiveness of the proposed set of treatment and prevention measures, 80 pregnant women were selected after influenza, transmitted in early pregnancy, with a high risk of placental dysfunction. Patients were randomly divided into 2 groups: 40 women whose pregnancies were performed according to optimized tactics (main group) and 40 women (comparison group) whose pregnancies were managed according to the clinical protocols of the Ministry of Health.Testing the effectiveness of the proposed set of measures showed its positive effect on hormonal function of the placenta (normalization of progesterone and estradiol levels), immune status (reduction of NK-cytotoxicity, balance of cytokine profile), elimination of vitamin D deficiency and reduction of procoagulation potential of the hemostasis system.Creating favorable conditions for the development of gestation has reduced the incidence of placental insufficiency by almost 2 times to 35.0% vs. 62.5%. Against the background of the recommended tactics of pregnancy after influenza, the frequency of complications of pregnancy, disorders of the fetus and newborn has decreased significantly.
IDENTIFICATION OF SPECIFIC CEPHALOMETRIC MARKS IN PATIENTS WITH LATERAL CONDYLAR POSITION TEMPOROMANDIBULAR JOINT
Authors: Vovk Viktorija
Published: January 2021

Relevance. Temporomandibular joint dysfunction is one of the most widely spread and common disease nowadays. It includes disorders on different levels of whole body and multi symptom as clinical manifestation. There is still less of evidence in ethiopathology of Temporomandibular dysfunction(TMD).Objective. The research aimed to find new etiological factors impacting the formation of TMJ, recorded growth and developmental disorders of the facial skull in the experimental group. Materials and methods. The sample group consisted of 59 patients. The experimental group included 38 patients with lateral joint displacement; the control group included 21 patients. Subjects were examined with functional probes, occlusion diagnosis with articulation paper Baush 200,100,8 microns, cephalometryc analysis by Grummons, computed tomography of temporomandibular joint, licensed software application Planmeca Romexis Viewer, statistical analyses with program IBM SPSS Statistic Base v.22.Results. 91.6% of patients with dentofacial deformities of the maxilla (ddm) also have TMJ with lateral displacement of the articular heads of the mandible. Patients without maxillary dentofacial deformities experience lateral displacement of the articular heads with a frequency of 8.7% and probable risk of 10.5 (95% CI 2.79-39.8). Patients in 1group (63,16%) experiences asymmetric inclination of the angles of the right and left upper jaw and occlusal plane around tooth number 6 and 7, 79.94% of patients in the experimental group recorded a displacement of the mandible <89 ° dental deformity. There is a specifically, ramifications of the pathological factors via rotational, simultaneous, one-sided, and three-level move with a delay in the horizontal growth of the dental apparatus.
تطور كتابة قصة سيدنا يوسف عليه السلام في التراث العربي
Authors: بن يعقوب عدلي , بنت دين روسما
Published: January 2021

ملخص البحث

تناول هذا البحث تطور كتابة قصة سيدنا يوسف عليه السلام في التراث العربي من عصر صدر الإسلام إلى العصر الحديث. فقصته عليه السلام واردة ضمن قصص الأنبياء في كثير من المخطوطات وكتب التاريخ والتفسير،كما ورد اسمه في دواوين الشعر. وهناك دراسات وبحوث للكشف عن شخصيته وجماله وصبره تجاه كل الابتلاءات التي مرّ بها في مراحل حياته المختلفة إلى أن آتاه الله الملك. ويهدف هذا البحث إلى جمع وترتيب أسماء الرواة والمؤرخين والمفسرين والشعراء والأدباء العرب وإنتاجهم الشعري والنثري، بالإضافة إلى الدراسات العلمية حول قصة سيدنا يوسف عليه السلام، والكشف عن التطور الذي طرأ على كتابة هذه القصة. ويعتمد البحث على المنهج الوصفي، كما يستعين بالمنهج التحليلي لمناقشة الآراء المتصلة بالموضوع وتحليلها، وتلاحظ الباحثة أن كتابة قصة سيدنا يوسف عليه السلام عملية مستمرة مر العصور، كتب عنها المفسرون والمؤرخون والباحثون والأدباء والشعراء، ورتبتهم الباحثة حسب العصور، كما أن بعض الدارسين قاموا بدراسة هذه القصة من عدة نواح خاصة الاقتصادية والتربوية، بالإضافة إلى أن هذه القصة طرأت عليها تطورات عديدة وهي الترجمة والدراسات المقارنة إلى أن صدرت منها مسرحية ومسلسل في العصر الحديث. وقد أورد المفسرون والمؤرخون القصة بأكملها، ومنهم من اعتمد على الإسرائيليات، ومنهم من فرق بين الصحيح منها، وبين الأساطير والموضوع. أما الأدباء والشعراء فكانت عنايتهم بحدث من أحداث القصة، وكان حب امرأة العزيز ومراودتها ليوسف عليه السلام هو الحدث الأبرز الذي التفت إليه الأدب والشعر.  

 

الكلمات الافتتاحية: التراث العربي، المخطوطات، التطور، الترجمة، الإسرائيليات.
دراسة مقارنة بين تعليمات الحوكمة الصادرة من مصرف قطر المركزي ونظام الحوكمة الصادر من هيئة قطر للأسواق المالية (A Comparison Study Between Governance instructions issued by Qatar Central Bank and Governance System issued by Qatar Financial Markets Authority)
Authors: القره داغي أسماء , علي عارف عارف , حسن عزنان , الملاهي عبد الله علي
Published: January 2021

أصبحت الحوكمة إحدى الركائز الأساسية التي يجب على جميع الوحدات الاقتصادية أن تطبق مبادئها ومعاييرها وذلك للحد من تعرض الشركات والبنوك للفشل المالي. تهدف هذه الدراسة لتوضح الاختلافات الأساسية بين تعليمات الحوكمة الصادرة من مصرف قطر المركزي وتعليمات الحوكمة الصادرة من هيئة قطر للأسواق المالية، وذلك من خلال بيان مفهوم الحوكمة وإطارها التشريعي والتاريخي، وأبرز السلطات الرقابية والإشرافية العالمية والإسلامية التي اهتمت وأصدرت معايير للحوكمة، ثم ناقشت المعايير الصادرة من أبرز سلطتين رقابيتين في قطر وهما مصرف قطر المركزي وهيئة قطر للأسواق المالية، والفرق بينهما وأيهما أولى بالتطبيق من قبل المصارف القطرية سواء الإسلامية أو التقليدية، واتبع الباحثون المنهج الوصفي من خلال دراسة الإطار النظري للدراسة، وتوضيح الاختلافات الأساسية من خلال المقارنة النظرية بين مبادئ الحوكمة للسلطات الرقابية والإشرافية القطرية، ونتج عن الدراسة أن هناك وجود فروق أساسية فيما يخص المصارف وأن تعليمات مصرف قطر أولى بالتطبيق بالنسبة للمصارف.
الكلمات المفتاحيّة: الحوكمة، مصرف قطر المركزي، تعليمات الحوكمة، هيئة قطر للأسواق المالية، نظام الحوكمة.
Abstract
This study aims to clarify the Fundamental differences between Governance instructions issued by Qatar Central Bank and Governance System issued by Qatar Financial Markets Authority. Moreover, concept of corporate governance, legislative and historical framework, most important supervisory authorities whether global, Islamic or in Qatar are discuss. Then, it discusses the main differences between standards which issued by Qatar Central Bank and Qatar Financial Markets Authority, and whichever is Islamic Banks in Qatar should apply their Standards. The researcher used the descriptive analytical method to address the main principals. The analytical approach was also used by analyze the Governance instructions issued by Qatar Central Bank and Governance System issued by Qatar Financial Markets Authority. The result of the study, there are basic differences with regard to banks, and that Qatar Bank’s instructions are first to be applied with regard to banks.
Keywords: Corporate Governance, Qatar Central Banks, Governance Instructions, Qatar Financial Markets Authority, Governance System.