bluuebunny/crossref_metadata_2025 huggingface dataset:
A Comprehensive Failure Analysis Method and Mechanism Study on Ultra-Low-K Film Adhesion Failure
Authors: Shuting Chen , Lei Zhu , Wei Teo Han , Binghai Liu , Yanhua Huang , Kenny Ong , Zhiqiang Mo , Younan Hua , Zhaoxin Yuan , Seng Heng Yong , Yong Li Chao
Published: December 2020

The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.
TEM Failure Analysis and Root Cause Understanding of Nitride Spacer Bridging in 45 nm Semiconductor Manufacturing Processes
Authors: Binghai Liu , Zhiqiang Mo , Ping Zhao Si , Yuan Yao , Hong Teo Kim , Ye Chen , Irene Tee , Li Lee Gek , Changqing Chen , Boon Ang Ghim , Yogaspari  , Tan Robin
Published: December 2020

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.
First in Operando SEM Observation of Electromigration-Induced Voids in TSV Structures
Authors: Gousseau Simon , Moreau Stéphane , Bouchu David , Farcy Alexis , Montmitonnet Pierre , Inal Karim , Bay François
Published: December 2020

Since the early beginning of the integrated circuits, electromigration is a reliability issue of first interest. In 3-dimensional structures, electromigration is responsible for the formation of voids in lines connected to the Through Silicon Via (TSV). To our knowledge, this paper presents the first in operando electromigration experiment in a Scanning Electron Microscope (SEM) performed for 3D integration. The experimental protocol, including sample preparation and temperature regulation, is detailed. A current of 25 mA is injected in a structure heated at 350 °C for about 900 h. The evolution of voids is monitored and explained. Void growth occurs step by step, so that the microstructure may be assumed to play a major role in the depletion mechanism. The behavior of the electrical resistance is analyzed using the SEM micrographs.
Automatic Registering and Stitching of TEM/STEM Image Mosaics
Authors: Lin Chung-Ching , Stellari Franco , Gignac Lynne , Song Peilin , Bruley John
Published: December 2020

Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.
Device Characterization Using AFP Nanoprobing for the Localization of New Product Design Weakness
Authors: Ang Ghim Boon , Quah Alfred , Chen Changqing , Zhao Si Ping , Nagalingam Dayanand , Li Yan , Neo Soh Ping , Shailesh Redkar
Published: December 2020

This paper illustrated the beauty of AFP nano-probing as the critical failure analysis tool in localizing new product design weakness. A 40nm case of HTOL Pin Leakage due to Source/Drain punch-through at a systematic location was discussed. The root cause and mechanism was due to VDS overdrive testing issue. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.
A Study of Electron Beam Irradiation Influence on Device Contact Junction Characteristics of Advanced DRAM Using Atomic Force Probing
Authors: Wang Wei-Chih , Luo Jian-Shing
Published: December 2020

In this paper, we revealed p+/n-well and n+/p-well junction characteristic changes caused by electron beam (EB) irradiation. Most importantly, we found a device contact side junction characteristic is relatively sensitive to EB irradiation than its whole device characteristic; an order of magnitude excess current appears at low forward bias region after 1kV EB acceleration voltage irradiation (Vacc). Furthermore, these changes were well interpreted by our Monte Carlo simulation results, the Shockley-Read Hall (SRH) model and the Generation-Recombination (G-R) center trap theory. In addition, four essential examining items were suggested and proposed for EB irradiation damage origins investigation and evaluation. Finally, by taking advantage of the excess current phenomenon, a scanning electron microscope (SEM) passive voltage contrast (PVC) fault localization application at n-FET region was also demonstrated.
Adaptive Optics Compensation of Aberrations Introduced by Sample Thickness Error in aSIL Confocal Scanning Microscopy
Authors: Lu Y. , Bifano T.G. , Ünlü M.S. , Goldberg B.B.
Published: December 2020

We report on aberration compensation in an aplanatic solid immersion lens microscope used for high-resolution backside inspection of silicon integrated circuits. The imaging quality of aplanatic SIL microscope is shown to be significantly degraded by aberrations, especially when the silicon integrated circuit samples have thicknesses that are more than a few micrometers thicker or thinner than ideal. We describe and demonstrate a technique to recover near-ideal imaging quality by compensating those aberrations using a MEMS deformable mirror. The mirror, located in an optical plane conjugate to the microscope objective, is shaped in a way that counteracts spherical aberration errors associated with non-ideal sample thickness.
An Effective SIMS Methodology for GOI Contamination Analysis
Authors: Huang Yanhua , Zhu Lei , Ong Kenny , Teo Hanwei , Hua Younan
Published: December 2020

Contamination in the gate oxide layer is the most common effect which cause the gate oxide integrate (GOI) issue. Dynamic Secondary Ion Mass Spectrometry (SIMS) is a mature tool for GOI contamination analysis. During the sample preparation, all metal and IDL layers above poly should be removed because the presence of these layers added complexity for the subsequent SIMS analysis. The normal delayering process is simply carried out by soaking the sample in the HF solution. However, the poly surface is inevitably contaminated by surroundings even though it is already a practice to clean with DI rinse and tape. In this article, TOFSIMS with low energy sputter gun is used to clean the sample surface after the normal delayering process. The residue signals also can be monitored by TOF SIMS during sputtering to confirm the cross contamination is cleared. After that, a much lower background desirable by dynamic SIMS. Thus an accurate depth profile in gate oxide layer can be achieved without the interference from surface.
Die Level Defect Analysis Using Combined Techniques of AFP with Electron Microscopes
Authors: Yin Lee Lan , Haonan Bai , Keng Chua Kok , Meng Chow Yew , Tan Grace
Published: December 2020

With the device geometries shrinking, defect isolation becomes more challenging with the reduction of operating voltage and current levels. In this failure analysis study, a combination of AFP current contrast imaging and nanoprobing at the contact layer successfully isolated the defect location to a specific poly feature, where prior PVC analysis had been unsuccessful. The diagnosis was validated with subsequent high beam SEM inspection and TEM analysis, which revealed residual material beneath the suspected failing poly feature causing the poly to N+ diffusion short failure.
Enabling Scanning Acoustic Microscopy Inspection of Materials Underneath the Chamfer of the Package
Authors: Cajita Melanie S. , Grancapal Marlyn C. , Sia Rudolf A.
Published: December 2020

This paper describes how scanning acoustic microscopy can be used to inspect materials under the chamfer of electronic device packages. The technique involves the use of copper tape to locate the areas affected by the chamfer during X-ray radiography. The results are then correlated with known critical package and assembly geometries to determine how far parallel lapping should proceed to ensure that the areas of interest will become observable under acoustic microscopy without interfering with the functionality of the device.
High Resolution C-Mode Scanning Acoustic Microscope Techniques for the Failure Analysis of Microelectronic Packages
Authors: Li Yan , Hu Liang , Li Gang , Dias Rajen , Goyal Deepak
Published: December 2020

Fault isolation and failure analysis for Si related issues in microelectronic packages need non-destructive and high resolution techniques to reduce the analysis time. This paper illustrates non-destructive and high resolution CSAM techniques, which are shown to be very effective in subtle thin film defect and die edge defect CSAM imaging.
Localization of a Complex Failure by Combining ATPG and Customer-Oriented Application Testing
Authors: Wang Kai , Weaver Rhys , Johnson David
Published: December 2020

A systemic analysis was chosen to evaluate a real case Bluetooth (BT) radio failure in the aspects of RF communication, digital design, firmware, application software, semiconductor device physics and processing, and failure analysis. This paper explores the range of testing, including customer application testing, required to confirm and localize a BT RF communication failure. It shows that the radio communication failure was not, as expected, caused by faulty radio hardware; it was rather linked to problematic encryption hardware at the assistance of the Synergy BT to mobile application. The paper also explores that the digital fault can only be detected by the timing sensitive transition fault scan patterns and how to obtain the physical failure location. Thus, the combination of ATPG and application testing provides a consistency between electrical diagnostics which yields a higher success rate at subsequent physical failure analysis of complex modern RF System on a Chip.
Micro-Abrasive Blasting—A Novel Approach to Local Silicon and Mold Compound Material Removal
Authors: Sun Zhenzhou , Bosio Alberto , Dilillo Luigi , Girard Patrick , Todri Aida , Mulholland Matthew M. , Nguyen Hien
Published: December 2020

Post silicon validation techniques on Integrated Circuits (IC) specifically FIB circuit editing require backside sample preparation done by local mold compound and silicon machining. Conventional methods such as Computer Numerically Controlled (CNC) machining and chemical etching preparation platforms are commonly used. This paper will investigate a simple alternative approach to local sample preparation by using micro-abrasive blasting. This approach will display its simple natured set-up along with extremely quick process duration.
Study of Static Noise Margin and Circuit Analysis on Advanced Technology Node SRAM Devices by Nanoprobing
Authors: Dawood M.K. , Ng T.H. , Tan P.K. , Tan H. , James S. , Limin P.S. , Huang Y. , Lam J. , Mai Z.H.
Published: December 2020

With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.
High-Resolution Backside GMR Magnetic Current Imaging on a Contour-Milled Globally Ultrathin Die
Authors: Vallett D. , Gaudestad J. , Richardson C.
Published: December 2020

Magnetic current imaging (MCI) using superconducting quantum interference device (SQUID) and giant-magnetoresistive (GMR) sensors is an effective method for localizing defects and current paths [1]. The spatial resolution (and sensitivity) of MCI is improved significantly when the sensor is as close as possible to the current paths and associated magnetic fields of interest. This is accomplished in part by nondestructive removal of any intervening passive layers (e.g. silicon) in the sample. This paper will present a die backside contour-milling process resulting in an edge-to-edge remaining silicon thickness (RST) of < 5 microns, followed by a backside GMR-based MCI measurement performed directly on the ultra-thin silicon surface. The dramatic improvement in resolving current paths in an ESD protect circuit is shown as is nanometer scale resolution of a current density peak due to a power supply shortcircuit defect at the edge of a flip-chip packaged die.
Correlation of Thin Film Measurement Techniques for Device Packaging Processes
Authors: Walter J. , Mack W. , Lee C.Y. , Gspan C.
Published: December 2020

The analysis of thin layers in semiconductor components represents a central point in the quality control of semiconductor companies. Not only to control production processes, but to successfully operate also reverse engineering, reliable thin-film measurement methods are essential. In this work, non-destructive thin film EDX (energy dispersive X-ray micro analysis) software and μXRF (micro x-ray fluorescence analysis) were compared with TEM analysis. These methods ensure a high lateral resolution which is essential in the analysis of semiconductor structures. As an example, four different, for the semiconductor industry interesting, very thin coating systems in the nanometer range have been tested. In the individual cases best TEM detector contrast settings could be found, as well as optimum fluorescence lines settings on the EDX to minimize the errors. The TEM measurements, in thickness and composition, were compared to the thin film EDX software and the μXRF method results to determine their accuracy. It turns out that depending on the layer system recalibration with multilayer standards or at least with elemental standards is recommended. It could be shown that with μXRF and thin film EDX a reliable, rapid and non-destructive layer analysis is possible.
Failure Mechanism Studies and Root Cause Identification of Nonstick on Pad on Microchip Al Bondpads
Authors: Younan Hua , Yongkai Zhou , Yixin Chen , Chao Fu , Xiaomin Li
Published: December 2020

It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.
Pulsed Laser Stimulation Coupled with Optical Failure Analysis Technique—A Methodology to Help Space Application Electrical Designers
Authors: Bascoul G. , Sanchez K. , Perez G. , Bezerra F. , Chauvin H.
Published: December 2020

Pulsed laser for radiation sensitivity evaluation has become a common tool used in research and industrial laboratory. This paper aims to highlight an approach to understand weaknesses of a component under radiation environment using a short pulsed width laser beam coupled to thermography technique, heavy ions test inputs and physical analysis. This paper is based on a study of a PWM device embedded on voltage converter.
WISE and ICARUS—New X-Ray Algorithms to Improve the Detection of Counterfeit Components
Authors: Cardoso Bill
Published: December 2020

The drive towards miniaturization has created increasing challenges to the overall failure analysis and quality inspection of electronic devices. This trend has equally challenged the image quality of x-ray inspection systems – engineers need to see more details in each inspection. Image quality is paramount to the ability of making actionable decisions on the information acquired from an x-ray machine. Previous generations of x-ray technologies have focused on hardware improvements – better x-ray sources and better x-ray sensors. Although further improvements can still be achieved in hardware, our focus will be on the latest wave of technology breakthroughs and innovation in radiography systems: algorithms.
Materials Analyses for Parts Validation
Authors: Wolfgong W. John , Izzo James
Published: December 2020

The most common methodologies for determining whether a component should be judged suspect counterfeit, or not, rely on visual examination, electrical test, and X-ray examinations. While these are commonly sufficient at such determinations, more thorough examinations may be pursued - in particular materials characterizations. In this paper, examples are given in which such “non-standard” methods are employed. Additionally, the results of an investigation as to the applicability of such methods towards detection of surface alteration to facilitate repackaging are described.
Comparison of Magnetic Field Imaging and Thermal Laser Stimulation for Detecting Electrically Shorting Defects within a Die BEOL
Authors: Distelhurst Kevin A.
Published: December 2020

Magnetic Field Imaging (MFI) and Thermal Laser Stimulation (TLS) failure analysis (FA) techniques (e.g. OBIRCH, XIVA, ect.) both have advantages and disadvantages. The obstacles encountered from these techniques may hinder further fault isolation (FI), lengthen turn-around-time and/or detract from actionable results. MFI using a Giant Magneto Resistance (GMR) sensor is compared to TLS techniques to understand the capability of the MFI technique at finding shorting defects. A short within a capacitor bank is successfully isolated using both techniques.
TEM Sample Preparation Tricks for Advanced DRAMs
Authors: Sung Ching Shan , Lee Hsiu Ting , Luo Jian Shing
Published: December 2020

Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.
Failure Induced by a Progressive Defect in Memory Device
Authors: Nam Incheol , Ryu Hodong , Kim Jinseon , Lee Kwangwon , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung
Published: December 2020

System failure due to a progressive defect in memory cell-array of DRAM was studied with automated test equipment. In order to find out relationship correctable single-bit fault and system failure, memory cells with single-bit fault by a cross-defect were selected. After high voltage and temperature stress, a soft cross-defect was changed into a hard cross-defect. Consequentially, invalid operation by a degraded cross-defect causes array-failure. Based on the failure analysis, methods to prevent array-failure are proposed, and applied to DRAM successfully.
Electrical and Nanoprobing Analysis on the Implantation-Related Invisible Defect
Authors: Chen C.Q. , Ng P.T. , Ang G.B. , Rivai Francis , Quah A.C.T. , Ng H.P. , Ang P.C. , Lam J. , Mai Z.H.
Published: December 2020

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.
Case Study—Failure Analysis of a Multiplexer
Authors: Woo Michael , Campos Marcos , Aranda Luigi
Published: December 2020

A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.
Successful Identification of a Subtle Oxide Defect in between Tungsten Plug and Titanium Liner in a Bipolar Transistor
Authors: Mendaros Raymond G. , Calanog Richard , Bawlady Raghavendra
Published: December 2020

Analog Devices General Trias (ADGT) received a challenging customer return unit (CRU) for failure analysis (FA). The CRU is a frequency synthesizer failing to lock at the customer’s application frequency at cold temperature condition. The failure has been simulated during bench testing at the ADGT FA laboratory at ambient temperature with VDD supply voltage lowered to 2.38V from nominal value of 3.0V. Series of fault isolation analyses using Light Emission Microscopy (LEM) and Optical Beam Induced Resistance Change (OBIRCH) localized the failure to a bipolar transistor (NPN) in the feedback divider block of the frequency synthesizer. Circuit level spice simulation replicated the functionality failure when a 2.6K-ohms resistance is connected to the emitter of the transistor. Physical failure and elemental analyses found traces of native oxide in the Nitrogen (N2) rich Titanium Nitride (TiN) layer between the Tungsten (W) plug and Titanium (Ti) liner in the emitter plug of the failing transistor. The oxide interface acts as a barrier to the flow of charge carriers in the emitter leading to the temperature dependency failure; failing at cold temperature and passing at ambient temperature. Corrective actions have been put in-place as a result of the successful identification of the defect.
Light-Induced Capacitance Alteration for Nondestructive Fault Isolation in TSV Structures for 3D Integration
Authors: Jacobs K.J.P. , Khaled A. , Stucchi M. , Wang T. , Gonzalez M. , Croes K. , De Wolf I.
Published: December 2020

We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).
Implementing Time Resolved Laser Assisted Device Alteration Using Pulse on Demand Nanosecond Laser Diode
Authors: Ravikumar V.K. , Ranganathan G. , Phoa S.L. , Chin J.M. , Pey K.L. , Yang J.K.W. , Kok W.L. , Koh L.S.
Published: December 2020

Time-resolved laser assisted device alteration (TR-LADA) has interesting applications to reduce the spatial spread of LADA site, as well as benefit device design debug. This paper describes an implementation using a 1063nm wavelength nanosecond pulse-on-demand laser diode to obtain a timing resolution of 1-2 tester cycles and spatial resolution enhancements to LADA sites. We also present potential capabilities of TR-LADA in the debug of analog circuitry.
Experimental Demonstration of the Effects of Laser Pulse Duration on SEU and LADA in CMOS Devices
Authors: Goh S.H. , Yeoh B.L. , Hao Hu , Chan Y.H. , Lin Zhao , You G.F. , Lam Jeffrey , Koh L.S. , Chua C.M.
Published: December 2020

This paper proves the effects of laser pulse width on the lowering of LADA and SEU threshold laser energy. The soft failure rate is found to increase with reducing pulse widths from 100 μs to 2 μs. The results obtained suggest that pulsed-LADA for soft defect characterization and localization could offer notably improved SNR and turnaround time. This is because it is no longer critical to assign the test point close to the shmoo boundary which is well known to give rise to spurious signals. With a less noisy signal image, the overall debug cycle time can be shortened since multiple frames average is not required. Further driven by the motivation to seek a viable alternative to overcome the challenge of weak LADA signals due to poor transmittance of 1064 nm wavelength laser through full wafer thickness and a solid immersion lens, preliminary results based on 1122 nm wavelength laser is also presented. It is observed that though the OBIC quantum efficiency at 1122 nm is 80% lower than at 1064 nm, it is 25% higher when a solid immersion lens is used.
Plasma-FIB Sample Preparation for X-Ray Tomography of 3D-IC Interconnects
Authors: Audoit G. , Bleuet P. , Delpy G. , Kwakman L.
Published: December 2020

Prior to x-ray tomography, cylindrically-shaped samples are obtained using an innovative milling strategy on a Plasma-FIB. The method presented consists of tuning the ion dose as a function of pixel coordinates along with optimization of the scan geometries, drastically reducing the preparation time and significantly improving the overall workflow efficiency.
Challenges of System Level Failure Analysis of Electronics in the Automotive Industry
Authors: Hevesi Bence
Published: December 2020

In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.
Battelle Barricade—Microelectronic Device Authentication and Counterfeit Detection Utilizing Power Analysis
Authors: Liszewski Katie , Bergman Thomas
Published: December 2020

Battelle has developed a technology to nondestructively classify electronic components as authentic or counterfeit. The technology uses a method that creates feature vectors for each class of devices using a reconfigurable side channel power analysis test fixture. This test fixture monitors the power fluctuations of the device either via connection to a power or a ground pin while test signals are sent to the device. Power waveforms are processed, undergo dimensionality reduction techniques, and the resultant data is plotted in Principal Component Analysis (PCA) space to reveal information related to the authenticity of the device under test. To scale this technology to the full catalog of parts available to a production test house, unique tools have been created that provide automated test generation and scoring of feature vectors.
Acceptable Laser Dose of 28 nm FDSOI Technology—Correlation of Experiment and Simulation
Authors: Penzes Maxime , Dudit Sylvain , Parrassin Thierry , Lewis Dean , Perdu Philippe
Published: December 2020

Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. In this paper the area of interaction between the laser and the device has been measured more finely by frequency mapping. Then a simulation is used to predict the threshold of degradation. To reinforce the correlation between the simulation and the experiments, we also make a comparison with the area defined in the previous study. Finally, we give the areas of interaction in function of the temperature and show how it can change in function of the device (geometry and metal layers).
In-Situ Carbon Deposition in FIB for Reducing TEM Lamella Curtains Caused by Air Gaps in NAND Flash Memory
Authors: Hsu Hsin-Cheng , Lin Chun-Hung , Ku Huai-San , Zhuang Dun-Fan , Lin Ru-Hui , Chen Yi-An , Hsiao Wei-Ming , Yeh Chin-Chih , Lian N.-T. , Yang Ta-Hone , Chen K.-C
Published: December 2020

An in situ air gaps fill-in approach was investigated by conducting a convenient way in dual-beam FIB. We employed a well-controlled deposition to precisely fill carbon into air gaps. It greatly reduced formation of the artifacts and avoided the profiles of air gaps by reducing striations and damages during FIB milling. Generally, the effect of air gaps between wordlines or between metal lines, as well as some unexpected defect voids can be eliminated in most cases if this ideal method is applied.
Automated Schematic Transformation to Enhance Circuit Failure Design Debug
Authors: Gupta Varun , Lau Wee Yee Wendy , Goh S.H. , Ho H.W. , Yeoh B.L. , Hao Hu , Dawood Khalid , Lam Jeffrey
Published: December 2020

In a failure event, circuit schematic analysis usually follows after fault isolation to increase the success rate. However, analyzing an extracted netlist of the isolated sub-circuit can be messy. Manual circuit translation from layout where the analyst is in control of the cell instance placement is one way to overcome this challenge. Although it is neater and intuitive for analysis, it can be time consuming to create the schematic. To analyze circuits in a systematic manner, cross-mapping between layout and schematic contents is the most commonly recognized approach. However, at times, cross-mapping alone is insufficient and some further simplification procedures are favorable. This paper describes the challenges and illustrates using real case studies, how schematics re-ordering and substitutions can be useful to simplify and enhance circuit analysis. These procedures can be implemented in an automated manner to enhance turnaround time for analysis.
Root Cause Analysis and Correction of Single Metal Contact Open-Induced Scan Chain Failure in 90 nm Node VLSI
Authors: Ting Chao-Cheng , Liu Ya-Chi , Chen Hsuan-Hsien , Tsai Chung-Ching , Shih Liwen
Published: December 2020

In this paper, the localization of open metal contact for 90nm node SOC is reported based on Electron Beam Absorbed Current (EBAC) technique and scan diagnosis for the first time. According to the detected excess carbon, silicon and oxygen signals obtained from X-ray energy dispersive spectroscopy (EDX), the failure was deemed to be caused by the incomplete removal of silicate photoresist polymer formed during the O2 plasma dry clean before copper plating. Based on this, we proposed to replace the dry clean with diluted HF clean prior to the copper plating, which can significantly remove the silicate polymers and increase the yield.
Influence of Sample Preparation on Intrinsic Stress Inside a Model Chip—Comparison of Results from Electric Read-Out and Raman Spectroscopy
Authors: Schaffus T. , Pfaff H. , Albert P. , Schaffus M. , Kroninger F. , Krumschmidt J. , Debie D. , Breuer W. , Mack W.
Published: December 2020

The given project is to benchmark typical preparation methods under the aspect of the influence of initial intrinsic stresses inside electric components. Raman spectroscopy has been applied as well as the piezo resistive readout on a specifically designed model stress monitoring chip.
Combining Volume Scan Diagnosis and Dynamic Failure Analysis for Precise Isolation of Manufacturing Defects
Authors: Jakati A.M. , Deshpande R. , Serrels K.A. , Babighian P. , Dabney G. , Kalarikkal A.
Published: December 2020

Advances in semiconductor manufacturing technologies have led to newer types of defects that are difficult to identify, causing longer yield ramp times. Traditionally, yield has been limited to random particle defects but layout systematic defects are increasingly dominating the fail paretos on advanced technologies. Identifying systematic defects precisely and rapidly is a must. This paper codifies a methodology that combines volume scan diagnosis and non-destructive electrical fault isolation techniques such as photon-emission microscopy, soft defect localization and laser voltage imaging/probing to debug manufacturing defects precisely.
Confocal Laser Scanning Microscopy (CLSM), A Tool for Counterfeit Detection
Authors: Simard-Normandin M. , Rahman R.
Published: December 2020

This paper explains the CLSM technique and presents surface roughness measurement data from several groups of known authentic and suspect counterfeit parts. Surface roughness is an important characteristic of plastic encapsulated or metal lidded parts because counterfeit parts are often blacktopped or re-polished and remarked.
Automated Contactless Defect Analysis Technique Using Computer Vision
Authors: Stellari Franco , Lin Chung-Ching , Wassick Thomas , Shaw Thomas , Song Peilin
Published: December 2020

In this paper, an automated contactless defect analysis technique using Computer Vision (CV) algorithms is presented. The proposed method includes closed-loop control of optical tools for automated image collection, as well as advanced image analysis methods to improve image quality and detect potential defects. As an example, the technique was successfully used to identify delamination defects along the perimeter of a large test chip.
Case Study of ESD-induced Pin Leakage Failure Solved Using Novel Powered TIVA Technique
Authors: Mishra Sneta , Bockelman Daniel R.
Published: December 2020

A case study is presented of a core CPU product where FA/FI debug is performed for an ESD-related pin leakage issue on an IO family to root cause and qualify the product. A Powered TIVA technique is used to localize the damage to the termination resistor circuitry of the affected IO block when the pin is tristated using a device tester. Failure characterization shows a gate to drain short on the transistor, with nanoprobing confirming a solid short on gate to drain and TEM finding a short at the location indicated by the TIVA hits.
Localization of Embedded Memories using EeLADA
Authors: Thor M.H. , Goh S.H. , Zhao Lin , Yeoh B.L. , Ngow Y.T. , Hao Hu , Chan Y.H. , Lam Jeffrey
Published: December 2020

Bitmapping based on memory built-in self-test is the most efficient method to locate embedded memory defects in system-on-chips. Although this is the preferred approach to memory yield improvement, the procedure to enable bitmapping can be both time and resource-consuming. Therefore, it is not supported on chips that are not produced in high volume due to the low return on investment. EeLADA was explored as an alternative. Although its feasibility has been proven in a previous report, the localization capability or diagnostic resolution is limited to at best failing bit-lines. This work enhances this technique to achieve a resolution down to bit-cell level with an accuracy of less than 5 µm.
Comparative Assessment of Optical Techniques for Semi-Invasive SRAM Data Read-out on an MSP430 Microcontroller
Authors: Kiyan Tuba , Lohrke Heiko , Boit Christian
Published: December 2020

This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.
Thermal Transient Phenomenon Analysis for Design Debug
Authors: Mousnier M. , Bascoul G. , Lombardi T. , Faure A. , Goxe J. , Turpin P. , Kamamen H. , Zirilli T. , Ng C.C. , Bley V. , Lebey T.
Published: December 2020

Thermal issues management is a daily design challenge for teams working with analog mixed-signal technologies such as “SmartMOS”, with the integration of analog circuitry, high power density devices and logic control. A case study based on an NXP new product introduction will illustrate the use of Thermography as a complementary technique to standard Design debug activities, leading to the demonstration of a thermal crosstalk phenomenon in the analyzed analog mixed signal device. Based on InfraRed Thermography principle and specific Trigger Delay and Thermal Mapping modes, a transient thermal event was fully characterized, in addition to more common techniques such as Design and Layout study, electrical characterization, simulation, Microprobing, and Thermal Laser Stimulation. The added value of the thermography, as well as the limitations of the technique, will be discussed in that paper.
V-Pulse Technique For Optical Isolation Of Latchup Triggers In Sub-14 nm Standard-Cell Logic And Memory
Authors: Lo William , Gupta Puneet , Lin Yen-Tzu , Venkatesh Rakshith , Schlangen Rudolf , Li Jane , Zhang Chuan , Marks Howard , Cory Bruce
Published: December 2020

High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.
Speeding up Chip Layer Imaging with a Multi-Beam SEM
Authors: Eberle A. L. , Garbowski T. , Nickell S. , Zeidler D.
Published: December 2020

Reverse engineering of today’s integrated circuits requires proper sample preparation, high speed imaging and data processing capabilities. The electron-optical design and the data handling architecture of our multi-beam scanning electron microscopes are scalable over a large range of beam numbers, providing sufficient imaging speed - also for the foreseeable future. A first step in data processing for reverse engineering on images acquired with a multi-beam scanning electron microscope has been successfully shown in preliminary tests.
Nests of some representatives of hymenoptera (Hymenoptera, Aculeata) in stationary artificial nesting structures on the territory of the botanical garden NUBIP of Ukraine
Authors:   Institute of Evolutionary Ecology of the National Academy of Sciences of Ukraine, Koniakin S.N. , Honchar H.Yu. ,   Institute of Evolutionary Ecology of the National Academy of Sciences of Ukraine, Kumpanenko A.S. ,   Institute of Evolutionary Ecology of the National Academy of Sciences of Ukraine, Kolesnichenko O.V. ,   National University of Life and Environmental Sciences of Ukraine, Povoznikov M.G. ,   National University of Life and Environmental Sciences of Ukraine
Published: December 2020

Green areas of the city (remnants of the natural landscape, parks, squares, etc.) are a refuge for most diverse organisms, include insects too. Such places provide them with fodder and nesting resources under certain conditions. However, as a result of the sanitary measures of a care, the simplification of the vegetation, etc., these places become unattractive to biota, which leads to the reduction of the most common urbotolerant species of insects. In order to preserve and maintain populations of some insect species, artificial nesting structures are installed in the most attractive and safe areas. We studied the trap nest (a set of reed tubes) for insects, which was located on the territory of the botanical garden NUBIP of Ukraine. As a result of the study of 50 separate nests, the species composition of individual groups of the wild bees and wasps inhabiting such nests was described. Measurements of individual nests (diameter and length of the reed tube) were made and it was found that the population of the insects, in particular Osmia bicornis (Linnaeus, 1758) (Apoidea, Megachilidae) and the wasps of the genus Trypoxylon Latreille, 1896 (Crabronidae) is almost 95 % with dominance of O. bicornis (78 %). It was determined that Osmia are not preferred to the nest with tubes of larger diameter or length, but the diameter and length of the reed tubes are positively correlated with the number of the bees larvae in the nest (the correlation coefficients are 0.44 and 0.48, p = 0.05, respectively). The wasps (Trypoxylon sp.) was preferred to the tubes with a diameter of mainly 0.5-0.7 cm (r = 0.56, p = 0.05). In addition, the composition of kleptoparasites, which lead to the death of the bee larvae, was studied. Thus, 20 % of Osmia nests were infected with flies Cacoxenus indagator Loew, 1858 (Diptera, Drosophilidae), and 10 % of the nests contained pollen mite Chaetodactylus osmiae (Dufour, 1839) (Arachnida, Sarcoptiformes).