bluuebunny/crossref_metadata_2025 huggingface dataset:
A New Chemical Method of Wright Etch in the Delineation of Stacking Faults and Crystalline Defects in Fabrication Silicon Wafer Substrate
Authors: Hua Y. , Fong S.Y.
Published: December 2020

In wafer fabrication (fab), stacking faults (SF) & crystalline defects in the silicon substrate will affect the yield. Wright Etch is the most common chemical etching method used to delineate SF on both (100) & (111) silicon surface. However, when Wright Etch is used directly, no SF could be revealed, even if the fab wafers are etched up to 40 mins. The reason is that the fab wafers have thin films deposited on it. After delayering by using dry & wet etches and subsequently Wright Etch, the SF were revealed. But this method is tedious & time consuming as it requires a long time to delayer. Thus in this paper the possibility of using HF (aq) to deprocess fab wafer prior to Wright Etch is investigated. A new chemical etching method - 155 Wright Etch has been proposed. This method has been applied to failure analysis for two years in our FA labs. The analytical results show that it is a rapid & reliable method and is effective in the delineation of SF or crystalline defects on fab silicon wafers due to high temperature oxidation, junction spiking, silicon precipitation, contamination, charging damage, BVGO failure and contact chain failure during fab processes.
Gain Reduction in Silicon Phototransistors Induced by Metallization Mask Misalignment
Authors: Malberti P. , Ciappa M.
Published: December 2020

Silicon planar phototransistors in hermetic pig-tail metallic package for airborne system application failed the acceptance test because of low responsivity. No significant difference between the electrical characteristics of good and defective devices could be detected by systematic investigation of focusing lens, anti-reflecting coating, optical alignment, and by internal electrical microprobing. EBIC inspection instead revealed that all defective phototransistors were affected by an anomalous region with a very high photo-carrier generation rate. This effect was produced by the misalignment of the emitter metallization which partially exposed the emitter-base junction. Partial exposition of the emitter diffusion to impinging radiation generates an induced photocurrent in the emitter-base junction which has opposite direction with respect to the photocurrent induced in the base-collector junction. The extra photocurrent in the base-emitter junction reduces the emitter-base forward polarization and, as direct consequence, the phototransistor responsivity is lower.
Comparison Precision XTEM Specimen Preparation Techniques for Semiconductor Failure Analysis
Authors: Hunt C. A.
Published: December 2020

Transmission electron microscopy (TEM) is now commonly employed in semiconductor device quality control and failure analysis. Precision cross-section specimens (PXTEM) are often required - these are samples that isolate an extremely small volume such as a single failed transistor. PXTEM samples are among the most difficult TEM samples to prepare. It is important for laboratories that perform PXTEM to master a variety of techniques so that the issues of cost, quality, and risk can be properly balanced. This paper addresses these issues while explaining the most common methods of PXTEM preparation along with an illustrative case study.
The Application of FIB Voltage-Contrast Technique Combining with TEM on Subtle Defect Analysis: Via Delamination After TC
Authors: Yang X. , Song X.
Published: December 2020

Novel Focused Ion Beam (FIB) voltage-contrast technique combined with TEM has been used in this study to identify a certain subtle defect mechanism that caused reliability stress failures of a new product. The suspected defect was first isolated to a unique via along the row through electrical testing and layout analysis. Static voltage contrast of FIB cross-section was used to confirm the suspected open defect at the via. Precision Transmission Electron Microscope (TEM) was then used to reveal the detail of the defect. Based on the result, proper process changes were implemented. The failure mode was successfully eliminated and the reliability of the product was greatly improved.
Failure Analysis Challenges of Surface Micromachined Accelerometers
Authors: Saltmarsh M. P.
Published: December 2020

As more micro-electro-mechanical systems (MEMS) are going into volume production, unique challenges are being presented to the failure analyst. Although traditional electrical components have always had some degree of non-electrical concerns (e.g., chemical contamination, mechanical bond failure), MEMS components, which generally sense non-electrical signals, by their nature require more emphasis on their physical properties. This paper will discuss new applications of existing techniques, notably high resolution infrared and visible laser scanning microscopy to examine and obtain topological (3 axis) information of a silicon encapsulated micromachined accelerometer, both prior to and following decapsulation. The utilization of low intrusion electrical measurement instruments are discussed. A technique for removing a single polysilicon plate with minimal disturbance to an underlying polysilicon plate spaced less than a few microns apart is presented.
Novel Failure Analysis Technique “Light Induced State Transition (LIST)” Method Using an OBIC System
Authors: Nishikawa A. , Odani C. , Miura N. , Kohno Y. , Shimizu M.
Published: December 2020

This paper describes a new technique, called the Light-Induced State Transition (LIST) method, that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows the user to locate a low signal line shortcircuited to a GND bus (or a high signal line shortcircuited to a VDD bus) in stand-by condition, which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by a experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS failure analysis, and has proved useful for finding a failure location rapidly.
Voltage Contrast Application on 1M SRAM Single Bit Failure Analysis
Authors: Luo D. , Song X.
Published: December 2020

A single bit failure is the most common and the most difficult failure mode to analyze in a Static Random Access Memory (SRAM). As chip feature sizes decrease, the difficulties compound. Traditional failure analysis techniques are often ineffective, particularly for high temperature operating life (HTOL) failures, because HTOL failures are most often caused by subtle physical defects. A new analysis approach, using Focused Ion Beam (FIB) cross-sectioning combined with FIB passive voltage contrast (PVC), greatly enhances the analysis success rate. In this paper, we outline the use of these new techniques and apply them to a technologically important problem.
The RAC Data Sharing Consortium: Sharing Test, Field and Failure Analysis Data
Authors: David Dylis D.
Published: December 2020

Many organizations perform component and equipment testing to ensure that parts in various applications and environments are robust and will operate reliably in the field. In addition, failure analyses are often performed to identify the cause of failures resulting from device testing and/or field usage. The Reliability Analysis Center (RAC) Data Sharing Consortium (DSC) accumulates data from these sources and assembles this data into a repository accessible to its members. This article discusses the purpose of the DSC, the benefits of DSC, and the data sharing agreement. It presents a list of organizations who are members of the DSC consortium and of organizations which are in the process of reviewing membership requirements. RAC's mission, the awards it has received, and its efforts towards developing and maintaining effective DoD systems are also covered.
Thermally Assisted Photoemission for CMOS Device Analysis
Authors: Symonds K. , Wilson J.
Published: December 2020

Enhancement of Existing Fault Isolation Techniques for CMOS VLSI Failure Analysis is important in keeping pace with device design and process technologies. Recently, we enhanced our photoemission microscopy capability by applying heat to the device during analysis1. This provided greater defect related light emission from nSRAM test structures and allowed identification of subtle failure modes not observable during room temperature inspection. In the present work, we investigate the theoretical dependencies of emission mechanisms and analyze experimental data to identify the dominant physical mechanisms involved with thermally assisted photoemission. We introduce a thermal factor to help quantify the effect from various light emitting structures. Experimentally, we find that emission mechanisms involving leaky and forward junctions are enhanced by temperature, and propose that the dominant factor for increased signal may be an increasing contribution from phonon absorption rather than phonon emission-based recombination. For emission mechanisms based on impact ionization; however, we find that the emission response is inversely proportional to temperature, and show that mobility degradation is the dominant limiting factor at higher temperatures.
Aluminum Interconnect Response to Electrical Overstress
Authors: Vinson J.E.
Published: December 2020

The response of aluminum interconnect to electrical overstress (EOS) is an important component of semiconductor reliability. Proper modeling of the fusing characteristics are necessary to build more robust circuits without wasting die area and allow estimation of the events that cause failures. This paper reviews previous work on aluminum EOS and presents experimental evidence of the mechanisms involved in aluminum EOS. From this evidence a simplified model is proposed based on the physical characteristics of the structure.
Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology
Authors: Liang Victor , Sur Harlan , Bothra Subhas
Published: December 2020

Three case studies in which the passive voltage contrast technique (PVC) was used in-fab during the development of a 0.25μm ASIC CMOS technology for rapid characterization and failure isolation are presented. The first case involved using the PVC technique to evaluate the gate oxide quality at different points of the process, allowing for quick identification of the process steps that were damaging the gate oxide and the relative magnitude of the damage that each process step contributed. PVC was then used to perform in-line evaluation of the split lots that were ran to address the problem without having to pull wafers off the line for electrical testing. In the second case study, PVC was used in-line to identify the source of siliciderelated gate-to-source/drain leakage. At this point of the process, electrical probing was not possible, and PVC circumvented this problem. The third case involved using PVC to help identify a new failure mechanism for tungsten plug vias that manifested itself due to plasma charging and layout peculiarities related to deep submicron design rules.
Auto-Fault-Locating-System for Mounting Boards
Authors: Nikaido M. , Yojima M. , Iida M.
Published: December 2020

In the process of fabricating high density mounting boards, locating faults in boards rejected in a functional test requires special circuit knowledge and skills, so it has been becoming more and more difficult to find the faults in a limited time. To address this problem, we have developed an Auto-Fault-Locating-System for mounting boards using a simple comparison technique and faulty net tracing algorithm. In the system, net-propagated faults are detected by comparing pulse-counts and voltages in good boards and faulty ones under full power supply. Faulty nets, which include the fault origin, are detected by tracing backward via a faulty propagation path using the input-output attribute of terminals. Measurements require 2.5 seconds per net (i.e., about 40 minutes for 1,000 nets), and searching faulty nets requires 10-20 seconds. The system successfully located the fault origin in 22 out of 25 boards rejected in a functional test. The located fault origins were found to be IC problems, pattern errors, open terminals and shorts between nets.
A Study on Discolored Bondpads and Galvanic Corrosion
Authors: Younan Hua
Published: December 2020

Discolored bondpads failure was investigated. SEM & EDX techniques were used to identify the root causes. The results show that discolored bondpads are caused by many holes on bondpads due to galvanic corrosion. It is most severe at power-line pads and less severe on rest of pads in the die. These bondpad holes have led to poor contact between the wire & integrated circuits and faulty computer chips. The holes are most likely to be caused by galvanic corrosion as there is a nucleus centered inside almost all holes. EDX results on the nucleus show high Cu concentration comparing to that on normal area. It is concluded that galvanic corrosion was due to DI water problem during wafer sawing at assembly. In this paper, the mechanism of galvanic corrosion will be further discussed.
The Logic Mapper
Authors: Smith Shawn
Published: December 2020

The Logic Mapper software created by Knights Technology bridges the gap between traditional yield enhancement techniques in the wafer fab and analytical failure techniques in the failure analysis (FA) laboratory. With Logic Mapper, fabs can test logic devices as easily as memory devices. Traditional logic chip yield enhancement techniques within product engineering and wafer fab yield enhancement organizations rely heavily on binsort functional test correlation to anticipate and correct semiconductor process issues. Some of the key shortcomings of these techniques are: · The inability to relate a particular bin’s fallout to a suspect process level. · The inability to distinguish a defect-driven yield issue from a device-integration issue. · The inability to establish a clear link between large populations of failed die. Logic Mapper resolves these key shortcomings by taking the output from functional testers and translating it from a list of failed scan chains into a list of suspected netlist nodes. Using Merlin’s FrameworkTM software, the netlist can be used to identify the X, Y coordinates of a suspected failing node; the failure analysis and yield enhancement engineers have created a starting point for investigating failures. These nodes can then be crossmapped from the circuit design onto the chip’s layout over multiple photomask layers within the design. The ability to translate a logic device’s binsort functional test fail data to defect traces is an advancement in the quality of test information provided for failure analysis and yield enhancement.
High-Yield and High-Throughput TEM Sample Preparation Using Focused Ion Beam Automation
Authors: Young R.J. , Carleson P.D. , Da X. , Hunt T. , Walker J.F.
Published: December 2020

Recent advances in the methods of preparing transmission electron microscope (TEM) samples using the focused ion beam (FIB) are presented. In particular, automation of TEM sample preparation is described. These automation methods, coupled with advances in ion column design, make it possible to prepare samples more efficiently and with less user involvement, thereby increasing FIB system utilization. Issues relating to sample handling and process-induced artifacts are also discussed.
Reduced Device Life Caused by Flux Entrapment During the Construction Process
Authors: Pierce James V. , Shuniak Lawrence F.
Published: December 2020

Devices that are sealed with a process using flux (all solder seals, some brazed seals some weld seals, etc.) will have residual flux entrapped. Devices with an internal construction such that areas exist where solvents can not completely clean surfaces exposed to flux vapor will also have residual flux entrapped. This entrapped flux will cause these devices to be susceptible to electromigration induced failure prior to the normal end-of-life of the device. If solder flux is trapped within a device, elevated temperature operation will shorten the life of the device. At elevated temperature, the activators in the flux will become a vapor and act as a catalyst for electromigration. Metal will be distributed across the surface between the "anode" and the "cathode" of the applied potential. The metal will be pulled from the "anode" to the "cathode". The electromigration can be stopped (or slowed) by reducing the maximum temperature the device will be exposed to when a potential is applied. If the amount of entrapped flux is not sufficient to bridge the gap between the "anode" and the "cathode" of the potential when in a non-vapor state (liquid or solid), the electromigration will be stopped when the temperature is below that needed for the flux activators to be in a vapor state. This paper contains details of this failure mode in hermetically sealed EMI filters and includes life test data (insulation resistance at elevated temperature), life reduction calculations, and photographs of the electromigration.
Application of Standard Metallurgical Analytical Techniques to Improve High Temperature Operational Life Performance of Bump Interconnect Technology of Flip Chip Packaging
Authors: Wills Kendall Scott , Abbott John , Carty Chris , Raghunathan Rohini , Simon Philip , Todd Charles , Vance Andy , Zhu Jianbai
Published: December 2020

Flip Chip packaging requires an understanding of the solder bump metallurgy and its aging characteristics. In this paper we demonstrate how standard failure analysis techniques can help determine aging characteristics and, how an understanding of bump age can be successfully employed to enhance bump reliability.
A Study of Effects of Backside Thinning on Integrated Circuits Using a Precision Diamond Wheel Apparatus
Authors: Roberts S.P. , Patterson J.M.
Published: December 2020

Recent advances in integrated circuit technologies and in interconnect methodologies to external electronics have made it extremely difficult to conduct failure analysis from the top side of the die (1,2). Therefore analysis techniques are being developed that allow analysis from the backside of the die. The first step in this process involves gaining access to the back of the die through the packaging material. Most backside analysis techniques require that the die then be thinned and polished. This paper describes specialized equipment and procedures to meet those requirements. The equipment is relatively inexpensive compared to other approaches.
OBIC Endpointing Method for Laser Thinning of Flip-Chip Circuits
Authors: Silverman Scott , Aucoin Richard , Ehrlich Daniel , Nill Kenneth
Published: December 2020

Laser microchemical etching systems provide enhanced through-wafer IR viewing and provide access for focused ion beam (FIB) tools and e-beam testers on flip-chip packaged die [1]. In demanding applications, laser etching is directed at rates of 100,000 cubic micrometers per second and must be stopped within 10 to 15 micrometers (thickness remaining) of the active flip-chip circuit. In cases where the initial die thickness is known, the laser process is sufficiently reproducible and system depth of focus is sufficiently narrow to place the laseretched floor within an accuracy of about plus or minus 5 micrometers relative to the initial surface of the die. However, greater accuracy is often desired to minimize FIB etch time. In addition, the laser step is often proceeded by a mechanical thinning operation on the die. This mechanical process introduces an uncertainty in initial part thickness, as well as part wedge and bowing. In this paper we describe an optical beam induced current (OBIC) method for accurate closed-loop endpointing with direct reference to the active device surface on the flipped die. The method relies on an exponentially increasing current that is induced by the laser as the device is thinned. Because of the strong absorption of the silicon bulk at visible wavelengths, the signal is sensitive to submicrometer thickness changes and, hence, may be used to stop the laser etching process with high accuracy at the desired 10 to 15 micrometer distance from the active circuit. The new technique has been studied on commercially available devices and shown to be insensitive to localized device junction density. Hence, endpointing is not highly dependent on the circuit design or exact placement of circuit elements. We outline the substrate and circuit properties that are most relevant to accurate implementation of the technique. The laser-etch process dependency of the OBIC signal has also been characterized. Simple high-speed closed loop electronics have been developed in order to apply the method for in situ endpointing New failure analysis/circuit debug techniques, including spectroscopic photoemission and picosecond time-resolved methods rely on observation of weak optical signals through the wafer. These would optimally be viewed though a remaining silicon thickness of a few micrometers or less. The limits of the OBIC endpointing method have been explored for the high-speed preparation of ultra thin local viewing windows in support of these new techniques.
Non-Invasive Backside Failure Analysis of Integrated Circuits by Time-Dependent Light Emission: Picosecond Imaging Circuit Analysis
Authors: Kash J.A. , Tsang J.C. , Knebel D.R. , Vallett D.P.
Published: December 2020

A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.
Detecting Power Shorts from Front and Backside of IC Packages Using Scanning SQUID Microscopy
Authors: Knauss L. A. , Frazier B. M. , Christen H. M. , Silliman S. D. , Harshavardhan K. S. , Fleet E. F. , Wellstood F. C. , Mahanpour M. , Ghaemmaghami A.
Published: December 2020

As process technologies of integrated circuits become more complex and the industry moves toward flipchip packaging, present tools and techniques are having increasing difficulty in meeting failure analysis needs. One of the most common failures in these types of ICs and packages is power shorts, both during fabrication and in the field. Many techniques such as Emission Microscopy and Liquid Crystal are either not able to locate power shorts or are inhibited in their effectiveness by multiple layers of metal and flip-chip type packaging. A scanning SQUID microscope can overcome some of these difficulties. A SQUID (Superconducting Quantum Interference Device) is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current density distribution in the sample can then be calculated from the magnetic field image, and resolutions approaching 5 times the near field limit can be obtained. We present here the application of a SQUID microscope to physical failure analysis and compare it with other techniques to detect shorted current paths in flip-chip mounted ICs and packages.
Picosecond Imaging Circuit Analysis of the IBM G6 Microprocessor Cache
Authors: McManus Moyra , Sanda Pia , Steen Steven , Knebel Dan , Manzer Dennis , Polonsky Stas , Huott Bill , Wilson Steve , Pelella Tony , Chan Yuen
Published: December 2020

Picosecond Imaging Circuit Analysis (PICA) is a new technique shown here to be applicable to the analysis of complex VLSI circuits. PICA was used to diagnose a timing failure in the early design of the G6 microprocessor chip. The fault occurred at high frequencies upon consecutive writes. Using PICA, combined with programmable array built-in self test (RAMBIST) techniques, the problem was traced to a race condition in the write control circuits. This allowed timely correction of the design for product implementation.
Automated Translation of Final Test Programs to Inexpensive FA Testers
Authors: Bodoh Dan J.
Published: December 2020

To isolate defects in microprocessors, the failure analyst must exercise the device under the failing conditions. Exercising the device with a tester and the final test program is a natural choice. However, populating a lab with production testers can be prohibitively expensive. Bench top testers are an inexpensive alternative. The constraints of these testers make automated test program translation tools hard or impossible to use. In this paper, we describe an automated translation tool that approximates the original test program with very small engineering time, taking into account the target bench top tester's constraints. The tool consists of three parts. First, the production test is simulated, creating a file that represents the waveforms an oscilloscope would see at the device pins. The second step is the most complex and unique part of the tool. It guesses the setup and hold time built into the production test, and manipulates the timing to fit within the constraints of the bench top tester. The final step reduces vector memory requirements and does the final format translation.
Characterization and Fault Identification of Copper BEOL sub-0.25μm Six Level Metal Microprocessor Designs
Authors: Kane T. L. , DeVries K. L. , Tenney M. T. , Patel A. K.
Published: December 2020

Characterizing and fault localizing sub 0.25μm six level copper BEOL microprocessor RISC designs operating above 450 MHz clock speeds pose significant challenges in functional defect localization and identification. The flip chip designs of these microprocessors with high numbers of I/O outputs can involve backside and frontside fault localization techniques such as emission microscopy, OBIC (Optical Beam Induced Current) using I.R. laser scanning microscopy, LIVA (Light Induced Voltage Alteration) [1,2], and PICA (Picosecond Imaging Circuit Analysis)[3,4], to identify the source of functional failures. Refined backside thinning techniques have been applied to optimize I.R. laser scanning microscopy and PICA localization of functional failures. In addition, products using highly structured test methods such as LSSD(Level Sensitive Scan Design) lend themselves to a highly software diagnosable category [5,6]. Such software diagnostics (LSSD diagnostics) when combined with image based fault localization has proven highly effective in pinpointing defects causing functional failures. Examples of electrical and physical characterization of functional logic failures in the six levels electroplated copper BEOL microprocessors will be described. In addition, the electrical characterization of submicron sized SRAM transistor devices using FIB (Focused Ion Beam Microscopy)deposited probe pads [7] will be detailed along with SEM and TEM micrographs of defects identified in this manner.
Analysis of Ohmic Contact Metal Deposition Defect Using FIB/SEM for a GaAs MESFET Clock Buffer IC Device
Authors: Tsai Pei Y. , Bornstein William
Published: December 2020

A major yield detractor in wafer final testing and outgoing production testing of a vendor supplied high frequency Gallium Arsenide (GaAs) clock buffer was encountered. The electrical failure modes are open, short, high Idd and gross functional fails. Physical analysis revealed the ohmic contact extrusion with a burst of Gallium from the substrate (GaAs) like a “mushroom” at the ohmic contact of the active layers of the MESFET and the MIM capacitors. The anomaly was not induced by ESD as it was proved by the ESD simulation test. The ESD test showed a much worse catastrophic damage than the extrusion anomaly. EDAX analysis identified high concentration of Ga in the extrusion. Focused Ion Beam (FIB) and Scanning Electron Microscopy (SEM) analysis of the extrusion showed large voids under the contact area at the defect location. Mis-alignment of interconnect metal to ohmic contact (Au-Ge-Ni) and pinholes in ohmic contact metal to active layers in substrate were found throughout the analysis. The pinholes causes the diffusion area to contact directly to the first level gold (Au) interconnect metal (M1). This results in Au-GaAs interdiffusion (mainly Ga) leaving a large void in the bulk substrate similar to kirkendahl voiding. Additional defects were found when the device was electrically biased. The problem was quickly fixed by slightly adjusting an angle in the sputtering process to provide a complete ohmic contact metal coverage on the diffusion contact and subsequently a yield improvement was resulted.
Identification of Yield Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology
Authors: Henderson Christopher L. , Hembree Charles E. , Soden Jerry M. , Headley Thomas J. , Draper Bruce L.
Published: December 2020

During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island.
A Combined Infrared/Visible Photoemission Microscope
Authors: Trigg A.D.
Published: December 2020

The photoemission microscope (PEM) is a powerful and widely used tool for location and identification of failure sites on integrated circuit (IC) chip and wafers. A PEM operating in the infrared (IRPEM) offers several advantages over systems operating in the visible part of the spectrum.. A combined PEM/IRPEM has been built having a cooled (77K) mercury cadmium telluride (MCT) focal plane array (FPA) sensitive in the range 800 to 2500 nm, an intensified charge coupled device (CCD) camera sensitive in the range 350 to 900 nm and a conventional, colour CCD camera. A cooled filter wheel enables the user to select the spectral range of the FPA. Direct comparison of photoemission images obtained in the IR and visible parts of the spectrum is straightforward, while the colour camera permits easy navigation around the device and facilitates probing of wafers. Comparing the sensitivity of the IRPEM with a conventional PEM camera (GEN III intensifier) indicates that for forward bias emission and NMOS emission the IRPEM is approximately 500 times more sensitive. Applications of the system to failure analysis in ICs, sensor devices and electronics packaging are described.
Correlation of Electronic and Thermal Properties of Short Channel nMOSFETS
Authors: Palaniappan M. , Ng V. , Heiderhoff R. , Phang J.C.H. , Fiege G.B.M. , Balk L.J.
Published: December 2020

Light emission and heat generation of Si devices have become important in understanding physical phenomena in device degradation and breakdown mechanisms. This paper correlates the photon emission with the temperature distribution of a short channel nMOSFET. Investigations have been carried out to localize and characterize the hot spots using a spectroscopic photon emission microscope and a scanning thermal microscope. Frontside investigations have been carried out and are compared and discussed with backside investigations. A method has been developed to register the backside thermal image with the backside illuminated image.
Failure Analysis of Flip-Chip Bumps After Thermal Stressing
Authors: Hooghan Tejpal K. , Hooghan Kultaransingh , Nakahara Sho , Wolf Robert K. , Privette Robert W. , Moyer Ralph S.
Published: December 2020

This paper describes a new diagnostic technique for analyzing microstructural changes occurring to flip chip joints after accelerated thermal tests. Flip chip reliability was assessed at high temperatures, with and without the application of electrical bias. A combination of standard metallurgical polishing techniques and the use of a focused ion beam (FIB) lift out technique was employed to make site-specific samples for transmission electron microscopy (TEM) cross-sections. We studied evaporated 95Pb/5Sn bumps, on sputtered Cr/CrCu/Cu/Au as the under bump metallization (UBM). Thermally stressed samples were tested for electrical continuity and evaluated using 50 MHz C-mode scanning acoustic microscopy (C-SAM). Failed samples were crosssectioned and large voids at the UBM were observed optically. TEM specimens taken from the predefined UBM region of degraded flip chip devices provided critical microstructural information, which led to a better understanding of a cause of degradation occurring in the flip chip joints.
Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology
Authors: Zhigang Song , Khim Loh Sock , Redkar Shailesh
Published: December 2020

With further miniaturization of MOS devices, the thickness of gate oxides becomes thinner and thus more sensitive to damage. Emission microscopy has shown its capability in analysis of these failures. However, emission site is not always the exact location of the physical defect. High-density devices with multi-metal layers make the situation worse. But when it is combined with Passive Voltage Contrast (PVC) technique, the success rate of isolating such failures can be greatly increased. In a case study, a unit of 1M bits Static Random Access Memory (SRAM), fabricated by 0.25 µm technology with 5 metal layers, failed after 500 hours burn-in. We successfully isolated the leaky poly and subsequently found gate oxide pinholes with the combination of PVC technique and emission analysis.
Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device
Authors: Hsiung Steve , Chan Victer
Published: December 2020

With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.
Antireflection Coatings for Semiconductor Failure Analysis
Authors: Davis Brennan , Chi Wilson
Published: December 2020

The use of an antireflection coating for backside semiconductor failure analysis is discussed. The process of selecting an appropriate coating is described. Several known coatings are also described in regards to imaging quality, material properties, and the benefits to device analysis applications.
Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs
Authors: Kane T. , Cambra M. , Tenney M. , McGinnis P. , Domenicucci A. , Wang Y. , Falcon D.
Published: December 2020

This paper discusses the challenges involved in testing microprocessors incorporating silicon-on-insulator (SOI) technology and assesses new characterizations tools, such as scanning capacitance microscopy (SCM), focused ion beam (FIB) analysis, and AFM electrical probing, that show promise when used to examine SOI device anomalies and failure modes.
Polarization Difference Probing: A New Phase Detection Scheme for Laser Voltage Probing
Authors: Lo William , Nataraj Nagamani , Boiadjieva Nina , Vedegarbha Praveen , Wilsher Kenneth
Published: December 2020

A novel laser based technique for waveform probing of integrated circuits is presented. This new technique exploits polarization-dependent opto-electronic effects in silicon integrated circuits to give phase sensitivity via a simple common-path interferometer design. The system utilizes a 10 ps pulse-width mode-locked laser to generate equivalent-time sampling pulses. A custom wavelength-tunable and spectrally matched external-cavity laser diode source is used for noise cancellation. A 20-GHz intrinsic system bandwidth with a 2x lower noise-floor, in comparison to current laser voltage probing technology, is shown.
Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices
Authors: Nguyen Dat , To Thao , Harrison Ray , Phan Cuong , Drummond John
Published: December 2020

Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.
Improved Electrical Failure Analysis/Fault Isolation Tool Development on Server Motherboard Platforms Based on Historic Failure Modes
Authors: Opdahl Patrick G.
Published: December 2020

Electrical fault isolation constitutes the first steps in characterizing and isolating the failure modes and root causes of a failing motherboard. Ideally the Failure Analysis Test tools provide complete coverage of all motherboard buses and silicon devices. Time and resource constraints for tool development prevent complete coverage, however, so the challenge is to provide the highest level of debug test coverage in the shortest development schedule. A simplified Fault Isolation process has been created based on historical failure analysis data to reduce the development time and resources to create tools which allow diagnosing failure root causes on high-end server motherboards. This strategy prioritizes the most common types of electrical failure modes and the types of Electrical Failure Analysis / Fault Isolation (EFA-FI) tools best suited to diagnose these modes. The benefits of this strategy include shorter EFA-FI development times, equivalent success rates in failure root cause, lower costs, and more effective EFA-FI tools that can be used within the Design Team and at either OEM or Contract Manufacturing sites.
Analysis of 0.13 μm CMOS Technology Using Time Resolved Light Emission
Authors: Ouimet Peter , Goertz Jason , Rinaudo Olivier , Long Lousinda , Yeung Simon
Published: December 2020

This paper describes case histories of 0.13 um bulk CMOS technology analyses using Time Resolved Light Emission (TRLEM). Using this technique, scan chain, timing, and logic failures are shown to be quickly and decisively identified thereby meeting the need for rapid feedback on 1st silicon failures and process excursions.
Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing
Authors: Shuttleworth David M. , Drummond Roby Mary
Published: December 2020

Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.
Semiconductor Inter-Material Analysis Using an FIB Sample Preparation Method and Auger Depth Profiling
Authors: Mulder Randal , Subramanian Swaminathan , Chrastecky Tony , Laberge Paul , Howard Cliff
Published: December 2020

The identification of foreign material at metal-oxide interface or at the poly-substrate interface by means energy dispersive spectroscopy (EDS) is very difficult. Auger depth profiling can be used as an alternative method to cross-section EDS analysis for the identification of very thin layers of foreign material in semiconductor devices. This article presents a sample preparation method adapted from a planar transmission electron microscopy sample preparation method so that Auger depth profiling can be used as a practical tool for identifying very thin layers of foreign materials at interfaces buried deep within semiconductor devices. The discussion covers the advantages, applications, and the procedure for performing the analysis. The high degree of control provided by the method gives an analyst the ability to easily thin down material layers to less than 100nm of a target layer, thereby significantly reducing sample preparation time as well as analysis time on the Auger tool.
Scanning Capacitance Microscopy at Transistor Contact Level
Authors: Ramanujachar Kartik
Published: December 2020

Traditionally, planar scanning capacitance microscopy has been conducted on samples which have been deprocessed to the level of the substrate and an oxide re-grown over the sample. However, HF used to etch the sample to the substrate can also dissolve shallow junctions. This article documents the ability of scanning capacitance microscopy to be utilized at the level of the contacts leaving the pre-metal dielectric intact. It demonstrates the scalability of this technique across three process generations spanning 0.18 micron, 0.13 micron, and 90 nm nodes. The article documents preliminary data on anomalous contrast observed in contacts at both 0.13 micron node and 90 nm node products. It also demonstrates the ability to distinguish between contacts going to a n-type diffusion, p-type diffusion, and transistor gate. The article also presents a simple model for the CV curves of defective contacts to source/drain diffusions.
Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement
Authors: Kong Chia Ling , Islam Mohammed R.
Published: December 2020

Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.
Integrating Logical and Physical Analysis Capabilities for Diagnostics
Authors: Bartenstein Thomas , Koenemann Bernd , Todd Lee , Vallerie Lisa
Published: December 2020

This paper describes and shows some anticipated application examples for an integrated logical/physical analysis environment that utilizes the public-domain OpenAccess database as a key infrastructure element. Using an electronic design automation (EDA) database makes it possible to enrich the failure analysis and debug environment with useful EDA-type utilities and applications. The article introduces the industry-standard OpenAccess data base and illustrates how this database can be used for better integration of a more comprehensive postsilicon debug, diagnostics, and characterization environment. It provides a summary of OpenAccess and highlights the possible role for OpenAccess/Unified Data Model as a complementary technology that captures the more static information about a product's design, design analysis, and design intent information. An initial integrated logical/physical analysis environment for logic diagnostics has been established for prototyping purposes. The article also presents examples of logical/physical analysis: signal interaction analysis and probing and circuit edit.
Single Cell Failures Caused by a Lateral Gate Effect
Authors: Versen M. , Schramm A. , Beer P. , Lindolf J.
Published: December 2020

A single cell failure (SCF) is a common fail signature in dynamic random access memories (DRAMs). Generally write and read problems can be observed if a cell capacitor is not connected properly to its bitline. If the critical resistance of this connection exceeds a given threshold a failure might occur. In this analysis this threshold can be varied by a lateral gate effect of neighboring trenches. The first section gives a short introduction to the problem. An experimental analysis follows in the second section. Simulation results are presented in the third part and a short summary is given at the end.
Sample Preparation and Preservation for TEM Analysis of Copper Interconnect Integrated Circuit
Authors: Gao Qiang , Zhang Mark , Li Ming , Niou Chorng , Kary Chien W.T.
Published: December 2020

This paper examines copper-interconnect integrated circuit transmission electron microscope (TEM) sample contamination. It investigates the deterioration of the sample during ion milling and storage and introduces prevention techniques. The paper discusses copper grain agglomeration issues barrier/seed step coverage checking. The high temperature needed for epoxy solidifying was found to be harmful to sidewall coverage checking of seed. Single beam modulation using a glass dummy can efficiently prevent contamination of the area of interest in a TEM sample during ion milling. Adoption of special low-temperature cure epoxy resin can greatly reduce thermal exposure of the sample and prevent severe agglomeration of copper seed on via sidewall. TEM samples containing copper will deteriorate when stored in ordinary driers and sulphur contamination was found at the deteriorated point on the sample. Isolation of the sample from the ambient atmosphere has been verified to be very effective in protecting the TEM sample from deterioration.