bluuebunny/crossref_metadata_2025 huggingface dataset:
PRESSURELESS SINTERING OF NANO- AG PASTE WITH LOW POROSITY FOR DIE ATTACH
Authors: Chen Sihai , Fan Guangyu , Yan Xue , LaBarbera Chris , Kresge Lee , Lee Ning-Cheng
Published: October 2015

A novel nano-Ag sintering paste C has been developed for a pressureless sintering process under air. Paste C was sintered at 250°C (C1) and 280°C (C2), respectively; C1 showed a slightly higher porosity but higher shear strength after aging at 250°C for 840 hours. Both C1 and C2 exhibited a microstructure much more stable than the control solder 92.5Pb/5Sn/2.5Ag, which suffered both IMC spalling after thermal aging and voiding. Ag migration toward the DBC to form a dense layer of AgCuNi(Au) was observed for all nano-Ag pastes that were studied, with C1 and C2 being more moderate in the migration rate. The Ag migration could be attributed to the tendency of Ag to form an alloy with Au, with abundant Ni and Cu at the DBC side, and appeared to be affected by the chemistry of nano-Ag paste. A liquid to liquid thermal shock test from −45°C to 240°C was attempted, and was considered too harsh for the die/DBC system employed in this study.
Design and Direct Assembly of 2.5D/3D Rigid Silicon Interposer on PCB
Authors: Yazdani Farhang
Published: October 2015

Silicon interposer is emerging as a vehicle for integrating dies with sub 50um bump pitch in 2.5D/3D configuration. Benefits of 2.5D/3D integration are well explained in the literature, however, cost and reliability is a major concern especially with the increase in interposer size. Among the challenges, reliability issues such as warpage, cracks and thermal-stresses must be managed, in addition, multi-layer build-up flip chip substrate cost and its impact on the overall yield must be considered. Because of these challenges, 2.5D/3D silicon interposer has developed a reputation as a costly process.

To overcome the reliability challenges and cost associated with typical thin interposer manufacturing and assembly, a rigid silicon interposer type structure is disclosed. In this study, interposer with thickness of greater than 300um is referred to as rigid interposer. Rigid silicon interposer is directly assembled on PCB without the need for intermediary substrate. This eliminates the need for an intermediary substrate, thin wafer handling, wafer bonding/debonding procedures and Through Silicon Via (TSV) reveal processes, thus, substantially reducing the cost of 2.5D/3D integrated products while improving reliability.

A 10X10mm2 rigid silicon interposer test vehicle with 310um thickness was designed and fabricated. BGA side of the interposer with 1mm ball pitch was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50X50mm2 FR-4 PCB. We present design and direct assembly of the rigid silicon interposer on PCB followed by temperature cycle results using CSAM images at 250, 500, 750 and 1000 cycles. It is shown that all samples successfully passed the temperature cycle stress test.
A New Approach for Reliable and Compact 3D Integration of mmW Transceivers on Silicon Using High-Impedance Surface Antennas
Authors: EL BOUAYADI Ossama , LAMY Yann , DUSSOPT Laurent , SOULIER Brigitte
Published: October 2015

3D integration of heterogeneous modules including RF and millimeter-wave (mmW) functionalities is opening new challenges for packaging developers to conciliate between electrical performance, thermal behavior and mechanical reliability using cost-effective technologies. This paper deals with innovative integrated antenna solutions within the particular context of 3D heterogeneous integration on silicon interposer using a disruptive design approach. Novel integration schemes of antennas using a high-impedance surface (HIS) reflector are presented. Then, the design steps of a 60-GHz folded dipole antenna for short-range communications are detailed. Simulation and measurement results show promising performances in terms of gain and radiation efficiency. Process and fabrication issues are addressed with specific Back-End processing developments and an experimental validation is proposed.
Qualification of Automotive RF-IC Packages
Authors: Bora Mumtaz Y.
Published: October 2015

The use of electronic components in the automotive industry is growing at an accelerated pace due to the transition from mechanical systems to electronic assemblies to meet the needs for automotive safety, comfort, connectivity and infotainment. The major drivers contributing to this growth are electronics systems that support engine controls, airbag systems, crash sensors, remote keyless entries, climate control and telematics. Qualification of automotive components requires compliance to demanding performance, environmental and reliability standards. Specialized manufacturing flows, materials and inspection protocols are required in some cases to meet the requirements of automotive standards. The paper summarizes the qualification of an RF switch per the AEC Q100 standard and reviews the x-sectional analysis and tests conducted to ensure performance and long term reliability.
Influence of Fabrication Process Parameters and Material Properties on Process Yield Performance on RF and Microwave Thin Film based Termination Resistors
Authors: Rahman Akhlaq , Olinger Fred , Howieson Michael
Published: October 2015

Ever-rising pressure of improving frequency domain performance of RF and Microwave components to improve the signal integrity as well as to reduce component package size consistently challenge design engineers not only with signal integrity and size constraints, but also the power integrity and thermal constraints concurrently. To achieve excellent signal and power integrity performance for microwave frequency application, components need to have superior voltage standing wave ratio (VSWR) characteristics as well as outstanding power handling capability. Addition to the brilliant component performance, manufacturers need to achieve excellent fabrication yield performance to keep the project viable. Process engineers face many challenges on each fabrication steps, which could significantly degrade the fabrication yield. Few challenges could originate from material sets, while others could arise from the process variations. In this work, we extensively studied the influence of many different parameters that considerably diminish the fabrication yield performance. We analyzed different parameters to design RF and Microwave termination resistors using thin film materials. One of the essential parameters, which significantly reduce the fabrication yield, is the inconsistency of surface roughness throughout the wafer. We studied the variations of the thin film materials microstructure and the sensitivity of film resistivity in response to surface roughness inconsistency. We experimented anneal drift of the material and effects of the temperature compensation of resistor (TCR) due to substrate surface roughness and existence of powder contamination on the surface. We compared Lapped and As-Fired substrates roughness and researched the inconsistence roughness effects on the thin film material. We studied the deposition rate of sputtered copper over the life of the target, from machine to machine and across the pallet, and analyzed the effects on the thin film material component. We studied the moisture related long time drift based on electro migration effect and the temperature dependence drift based on the materials sheet resistance. We analyzed the alteration of current density due to thin film resistor trimming and yield loss due to resistor value tolerance and trim variation by studying the sensitivity of the resistor area variation through trimming process. By analyzing different fabrication factors and material parameter properties, we realized the fact that most sensitive parameter that degrades the process yield is the existence of inconsistent surface roughness throughout the substrate. Based on the research study, we developed high power RF and Microwave 50 ohm termination resistors with excellent fabrication process yield performance.
Microstructural investigations of aluminum and copper wire bonds
Authors: Eacock Florian , Schaper Mirko , Althoff Simon , Unger Andreas , Eichwald Paul , Hengsbach Florian , Zinn Carolin , Holzweissig Martin Joachim , Guth Karsten
Published: October 2015

Ultrasonic wire bonding is a widely used technology to interconnect chips in the packaging industry. It is known that the bond quality depends on the microstructure prevalant in the bond. Similarly, the materials used as well as the bonding parameters depend also on the microstructure. However, the actual used materials such as aluminum and gold are either characterized by poor conductivity or high costs. Due to the outstanding properties of copper, it is a promising candidate for wire bonds. Nevertheless, a thorough investigation on the interrelationship between the material combinations, the processing parameters and the resulting microstructure for copper and aluminum wire bonds need to be conducted. Facing these unresolved issues, samples of aluminum and copper wires were extracted during various states of the bonding procedure. The samples were analyzed to gather information about microstructural influences on the bonding parameters. As a result a conclusion can be drawn regarding the ultrasonic wire bond strength/load subject to the bonding parameters. Furthermore, the different deformation behaviour of copper and aluminum will be depicted by employing the following analytical methods: hardness tests, light microscopy, and scanning electron microscopy.
p3D Micro Dispensing & Photonic Curing of Silver Nanoparticle Inks on Low Thermal Stability Molded Plastic Parts
Authors: Mastropietro Michael , Rawson Ian , Akhavan Vahid , Chen Xudong , Church Ken
Published: October 2015

In this paper, we describe an additive processing technique that would enable fast and reliable processing of conductive circuits upon a wide range of thermally molded plastics. Precise patterns of silver nanoparticle based pastes are printed on to 3D injection molded plastic parts and other 3D surfaces using a nScrypt micro dispensing tool and then processed in seconds using a NovaCentrix PulseForge flash lamp photonic curing system. The additive digital printing technique enables rapid manufacturing of intricate designs with quick turnaround time from design to production. The non-equilibrium heating technology enables sintering the nanoparticle based inks into high performance conductor circuits directly on 3D and 2D low thermal sensitive polymer materials. It will be demonstrated that the nanoparticle based pastes have a superior performance to the conventional polymer thick film pastes and that they are also more cost effective.

Specific examples will be shown demonstrating how the combination of the two tools and processes could result in a versatile and cost effective additive manufacturing process. As of right now, there is no tool or combination of tools that could provide such a versatile design and production environment. The new process is faster, more cost effective, and more environmentally friendly compared to conventional processing techniques.
Multi-scale X-ray tomography for process and quality control in 3D TSV packaging
Authors: Zschech Ehrenfried , Niese Sven , Löffler Markus , Wolf M. Jürgen
Published: October 2015

Advanced packaging processes and the resulting 3D products challenge process and quality control. X-ray imaging and X-ray computed tomography (XCT) provide non-destructive characterization capabilities on specimens across a range of length scales, observing features with sizes spanning from millimeters over micrometers down to several 10 nanometers. They are the techniques of choice for two- or three-dimensional inspection of medium and small sized objects with a resolution down to several 10 nm. In this paper, the potential and the limits of XCT for process development, process monitoring, and failure analysis in 3D TSV stacks are described. It is shown that a multi-scale approach, i.e. using imaging techniques with several resolution ranges, is necessary for these particular tasks. Since sub-micron XCT and nano XCT are very useful techniques with a promising prospect for the future, we focus on the capabilities of two lab-based XCT tools with sub-micron resolution (Zeiss Versa) and with < 50 nm resolution (Zeiss Ultra).

We demonstrate the capabilities for nondestructive imaging of multi-die stacks with TSVs and AgSn microbumps. Major filling defects in TSVs are clearly visualized. An analysis of individual bumps reveals mismatches in relative positioning, micron-size pores, and the distribution of intermetallic phases. This information provides important information regarding the respective process steps (process control) and the product quality (quality control). In addition, TSV etch profiles and small voids in Cu TSVs are visualized. Since deviations from the targeted geometry and defects are difficult to locate precisely from a two-dimensional image, X-ray computed tomography has to be applied.
Ceramic Process Variation Impact on Electrical Design Of High Frequency Components
Authors: Aguirre Jerry , Tallo Heather , Shigenobu Hide , Uyesugi Joe
Published: October 2015

The design and operation of high frequency microwave components and high-speed interconnects depends strongly on well characterized material technologies for robust, consistent, and repeatable performance from part to part. While characterization of the electrical and mechanical material properties is extremely important, the processing of the material into making structures is equally important. The process ultimately determines structure dimensional tolerances that will impact electrical performance, especially at high speed digital signal and high frequency applications. Understanding these tolerances, and their RF impact, can assist in selecting a material set based on process in addition to the published material electrical properties. This paper examines key electrical performance properties of two ceramic microwave components, a tapped line filter and an edge coupled microstrip filter, as a function of structure variations by use of a combination of a full-wave electromagnetic simulation tool and a pseudo-Monte Carlo analysis. These microwave components have been fabricated and measured to examine variations in RF performance as function of location on ceramic panel and to compare measured variations to expected variation predicted by simulation and analysis.
Causality Enforcement of High-Speed Interconnects via Periodic Continuations
Authors: Barannyk Lyudmyla L. , Aboutaleb Hazem A. , Elshabini Aicha , Barlow Fred
Published: October 2015

Causality verification and enforcement is of great importance for performance evaluation of electrical interconnects. We present two techniques based on Kramers-Krönig dispersion relations, also called Hilbert transform relations, and construction of causal periodic continuations. The first method employes periodic polynomial continuations, while the second approach constructs Fourier continuations using a regularized singular value decomposition (SVD) method. Given a transfer function sampled on a bandlimited frequency interval, non-periodic in general, both approaches construct an accurate approximation on the given frequency interval by allowing the function to be periodic on an extended domain. This allows one to significantly reduce (for polynomial continuations) or even completely remove (for Fourier continuations) boundary artifacts that are due to the bandlimited nature of frequency responses. Using periodic continuations eliminates the necessity of approximating the transfer function behavior at infinity in order to compute Hilbert transform. The methods can be used to verify and enforce causality before the frequency responses are employed for macromodeling. The performance of the methods is analyzed and compared using moderately and highly non-smooth functions.
Effect of Process Parameters on Free Air Ball Integrity in Copper and Palladium-coated Copper Bonding Wires
Authors: Araki Noritoshi , Ichiyama Yasutomo , Oishi Ryo , Haibara Teruo , Yamada Takashi
Published: October 2015

The Free Air Ball (FAB) formation processes of fine diameter Cu wires were observed, and the effects of process parameters were studied on the basis of high-speed camera observation. It was revealed that the FAB formation process is characterized by preheating before melting, melting that accompanies ball rising, and solidification periods. The relationships between the electronic flame-off (EFO) condition and the FAB formation were summarized for both bare Cu and palladium-coated Cu wires. Further study was performed on the changes in FAB shape with different EFO conditions, wire types, and FAB sizes. Off-centered FABs were observed in the bare Cu wire whereas they were rarely observed in the Pd-coated Cu wire. The off-center tended to be affected by shielding gas condition, EFO torch gap, and FAB size. The mechanisms of the off-centered FAB formation were proposed through the high speed camera observations. The optimization of process parameters to achieve defect-free, consistent FAB is discussed based on these findings, which is useful for the next generation high density packaging.
Mechanical reliability of ceramic packages for active implantable medical devices - The IEC hammer test
Authors: Kohler F. , Stieglitz T. , Schuettler M.
Published: October 2015

Implantable neural prostheses have to fulfill manifold requirements, from the technological side as well as legally. One particular normative demand for active implantable medical devices (AIMDs) which are intended to be implanted in the skull, is withstanding a mechanical impact of 2.5 J, defined by BS EN 45502-2-3:2010 and IEC 60068-2-75:1997. This article shows two computational approaches based on finite element modeling to evaluate the influence of geometrical variations on a brain-computer interfaces' mechanical package stability and the likelihood of withstanding mechanical impact. The presence of a fillet at inner edges (>0.5 mm) as well as a minimum wall thickness of 1 mm could be identified as a mandatory design requirements for axially symmetric packages to avoid extensively high stress levels. Mechanical event simulation (MES) predicted a passing of the hammer test if additional protective material (silicone rubber) is used. This however is postulated by the EN 45502-2-3 standard. The computational findings could be confirmed in a laboratory setup of the impact test.
Heavy-Wire Bond Manipulation with Laser to Increase Reliability and as Enabler for Thermography based On-line Process Control
Authors: Middendorf Andreas , Lang Klaus Dieter
Published: October 2015

Investigations regarding the failure behavior of heavy wire bonds show a significant decrease of cycles in strength with increasing wire diameter. The article explains the reasons theoretically. Based on the theory, possibilities to increase reliability are discussed. The innovation about this is the shaping of a chute on the bonding surface. This has to happen in a way that the current ampacity is not reduced. A laser will therefore cut across the bonding surface crosswise to the course of the wire. Previously the particular depth of cut is determined by simulation. The simulations prove the theoretically predicted enhancement of the reliability true. In addition, the method can be used as "non-destructive" in-situ measurement for quality assurance, since the crack growth can be derived from the thermography directly in the notches. The notches work as a magnifier for the thermography camera and eliminate the black coloring as a precondition in typical thermography.

The research work is carried out within the project RoBE partially which is funded by BmBF; the manufacturing method and the geometric shapes have been patented.
Air-Cooled Heat Exchanger for High-Temperature Power Electronics
Authors: Waye Scot K. , Lustbader Jason , Musselman Matthew , King Charles
Published: October 2015

This work demonstrates a direct air-cooled heat exchanger strategy for high-temperature power electronic devices with an application specific to automotive traction drive inverters. We present experimental heat dissipation and system pressure curves versus flow rate for baseline and optimized sub-module assemblies containing two ceramic resistance heaters that provide device heat fluxes. The maximum allowable junction temperature was set to 150°C, 175°C, and 200°C. Results were extrapolated to the inverter scale and combined with balance-of-inverter components to estimate inverter power density and specific power.
Precision Jetting of Solder Paste – A Versatile Tool for Small Volume Production
Authors: Becker K.-F. , Koch M. , Voges S. , Thomas T. , Fliess M. , Bauer J. , Braun T. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D.
Published: October 2015

During the last years, jetting processes for higher viscosity materials have gained widespread interest in microelectronics manufacturing. Main reasons for this interest are high throughput/productivity of jetting, contactless material deposition, high volume precision and freely designable deposition patterns.

In previous studies [i,ii] we have demonstrated the jetability of different resin-based materials, being exemplary for unfilled adhesive, for low viscous Underfill resin and for higher viscosity Glob Top materials. The focus of our previous work was on the dosing of various encapsulants - Underfill material with low viscosity and near Newtonian behaviour and Glob Top resins, being non-Newtonian fluids due to higher matrix viscosity and higher filler content (up to 70 wt %) with resulting increased filer/filler and filler/matrix interaction. During the last years jetting has become widely used and has been applied to the dosing of much more complex materials, combining high viscosity matrix materials with odd shaped and compressive particles. Examples for these materials are conductive adhesives and also solder pastes, where the jetting system developed by Swedish company Mydata set's the current standard for solder paste jetting.

In a technological study solder paste jetting using different jetting systems has been investigated in comparison to solder paste dispensing and solder paste printing, especially material rheological behaviour and the correspondence to processability have been evaluated in detail. To illustrate the potential of solder paste jetting as a flexible and powerful tool for electronic system prototyping, a test vehicle has been designed, containing areas for SMD soldering and for process reproducibility. To determine process quality not only basic process data on droplet diameter, resulting material depot size and positioning accuracy have been evaluated, but also statistical means have been employed to determine process homogeneity and stability depending on the respective parameter set.

Summarized this paper gives an insight into solder jet process development and describes material rheology demands and limitations and thus allows the optimized use of advanced solder jetting technology for electronics assemblies.
Analyses of PBGA Packaging under Strong Vibration
Authors: Kim Yeong K. , Hwang Do Soon
Published: October 2015

Experimental and numerical analyses on the solder joint reliability of plastic ball grid array under harsh random vibration were presented. The chips were assembled on the daisy chained circuit boards for the test samples preparation, and a half of the samples were processed for underfill to investigate the underfill effects on the solder failures. Two consequential steps of the random vibrations, named as acceptance and qualification levels, were applied. Overall controlled RMS of the power spectrum densities of the steps were 22.7 Grms and 32.1 Grms, respectively. It was found that the samples did not show any solder failure during the tests, demonstrating the robustness of the packaging structure for potential avionics and space applications. Finite element analyses were performed to calculate the sample vibration behaviors and the solder stresses, and the results were compared with the test data.
Quality Monitors and Inspection Criteria for Bare Die Flip Chip Ball Grid Array and Bare Die PoP Packages.
Authors: Vanam Kiran , Newman Anthony , Poustinchi Mori , Stewart Stephen
Published: October 2015

Package form factor and cost are one of the key drivers in smart phone and tablet landscape. In order to meet these requirements hand held market has seen emergence of bare die flip chip ball grid array (BD FCBGA) and bare die package on package (BD PoP). As the name implies, these packages don't have a mold cap or heat spreader surrounding the silicon die resulting in lower cost and smaller form factor. Further package thickness reduction is possible by thinning of silicon die without significantly affecting high temperature (HT) warpage or coplanarity. One of the main concerns with aforementioned bare die package (BDP) configurations is die crack failure during assembly, testing, shipping or surface mount operation (SMT). The propensity of die crack failures further increases as thinner die is employed to meet overall package height requirements. This work focusses on evaluating various inspection tools for detecting gross die cracks to fine line cracks up to ~ 0.7 μm wide. Some of the key considerations for inspection tools, at assembly and test operations will be presented.
Large Form Factor Hybrid LGA Interconnects; Recent Applications and Technical Learning
Authors: Torok John , Beaman Brian , Brodsky William , Canfield Shawn , Eagle Jason , Lewis Theron , Hoffmeyer Mark , Sinha Arvind , Yu Yuet-Ying
Published: October 2015

Recent high-end server design trends have continued to challenge electronic packaging engineers to design and integrate larger form factor land grid array (LGA) attached modules within their assemblies. These trends have included the application of larger, denser, organic packaged modules whose electrical performance and postencapsulation physical characteristics have been enabled by both the continued development of hybrid LGA connectors as well as new module actuation hardware designs. In this paper, we'll discuss these recent trends, including the specific technical attributes and challenges that need to be addressed to ensure a repeatable and reliable assembly design is developed. Initially, overviews of the latest connector and module design trends, including styles and physical sizes and their implications to the module's bottom surface metallurgy (BSM) flatness requirements, etc. are provided. Pursuant to this, recent system integration trending is reviewed; including both the module quantity per system assembly as well as module to module physical placements and how each of these impact printed wiring board (PWB) design (i.e., layer count, LGA site flatness, etc.) as well as the PWB assembly's solder processing characteristics (i.e., LGA pre- and post-solder attach contact co-planarity, etc.). Completing the application portion, is a description of some recent LGA actuation hardware and module external cooling apparatus designs (e.g., air-cooled heats sinks and water-cooling cold-plates and thermal interface materials (TIMs), etc.). The remaining portion of the paper is dedicated to the description of the mechanical analysis efforts completed to provide a fundamental understanding of the design's “as-assembled” attributes and a review of the associated evaluation completed to verify the integrated assembly's reliability characteristics. From the analysis methodology perspective, both the means of including each of the integrated assembly's key attributes (e.g., module mechanical construction and as encapsulated flatness, LGA contact compliance and stiffness as well as soldered contact coplanarity, TIM stiffness, actuation hardware, heat sink and cold-plate mechanical construction, etc.) and the resulting estimation of the predicted module internal TIM and hybrid-LGA's Pb-free soldered interface strains, actuation hardware stresses and LGA contact load variation are provided. Completing the discussion is a review of the variety of testing executed to validate the design's intended reliability. Included in this is a description of the test vehicle's design, the environmental stress testing conducted (i.e., mechanical pre-conditioning, accelerated thermal cycling (ATC), mixed flowing gas (MFG) and heat aging (HA), etc.) and the resulting data.
Development of 3D System-in-Package with TSV Technology
Authors: Miki Shota , Yamano Takaharu , Ichikawa Sumihiro , Sanada Masaki , Tanaka Masato
Published: October 2015

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack.

The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice.

For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached.

The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.
Cost and Yield Comparison of Wafer-to-Wafer, Die-to-Wafer, and Die-to-Die Bonding
Authors: Palesko Amy , Palesko Chet
Published: October 2015

There are multiple process options and technologies to consider when creating a product that requires 3D integration. Bonding two wafers (or two die) can be accomplished in various ways, such as with thermocompression, fusion, or adhesive bonding. However, the best assembly process cannot be determined by only studying the pros and cons of the bonding technology itself. There are also three main process flows to consider when pursuing 3D assembly: wafer-to-wafer, die-to-wafer, and die-to-die bonding. This paper will compare the cost and yield for each of these process flows, all of which have advantages and disadvantages depending on the application.

Activity based cost modeling will be used to construct three basic process flows, one for each bonding option. The process flows will each be divided into a series of activities, and the total cost of each activity will be accumulated. A variety of cost and yield trade-offs will be conducted using these process flows. The variables the trade-offs will focus on will include die size, throughput, incoming wafer cost, incoming wafer defect density, and residual die defect density. The goal of this analysis is to understand the variables that impact cost and yield when bonding wafers and/or die for a product that requires 3D assembly.
Optical Characterization and Defect inspection for 3D stacked IC technology
Authors: Fresquet Gilles , Piel Jean-Philippe
Published: October 2015

Advanced packaging technologies are rapidly evolving and 3D architectures requires new inspection and metrology techniques. Existing techniques need to be improved but new techniques must be developed to address new challenges induced by the last fabrication processes.

To increase the development speed, it is a big advantage that metrology and defect inspection need to be present on the same platform and a flexible tool, with multi sensors, to be more versatile facing the different step of the process will be presented in this paper

As 3D IC devices utilize TSVs for direct interconnect, the depth, top and bottom CD (critical diameter) of such TSVs with a diameter as small as 5 μm with a high aspect ratio is characterized.

During wafer temporary bounding, which is an handling technique that allows wafer thinning with a thickness of less than 100 μm, by selecting the most sensitive sensor, determination of the thickness of each layer of the stack could be determined at the same time: silicon substrate, thin glue layer of few microns only and carrier which could be silicon or glass.

After back-side processing and wafer thinning, the determination of the remaining silicon thickness (RST) below the TSV could be determined. Moreover back side roughness after grinding is also determined.

After wafer thinning process, the TSVs are revealed at the back side of the wafer, leaving to appear copper pillars. The pillars height and co-planarity measurements are then addressed.

Post CMP process control will be addressed by full field interferometry especially prior Copper to Copper direct bonding.

Concerning the defect inspection, the NIR microscopy is used to control die to wafer stacking process, to reveal voids in the glue and cracks on the grinded silicon substrate.

In this paper, we will present fast and nondestructive optical sensors based on low coherence infrared and white light interferometry and spectrometry techniques. These different sensors mounted on the same tool allow characterizing specifically and with an excellent sensitivity the different process steps described above. Concerning the defect inspections, techniques based on infrared microscopy and images techniques processing will be detailed and results will be presented to illustrate the possibilities of this inspection by microscopy.
Perfect Edge 3D™: Enabling Root-Cause Failure Analysis
Authors: Costello Suzanne , McCracken Stewart
Published: October 2015

This paper presents a novel technique used to prepare samples in cross-section using ion beam technology, MCS Perfect Edge™ and Perfect Edge 3D™. The resulting surfaces are deformation-free allowing high magnification and high resolution analysis of subtle nanometer scale features and material changes across a representative sample size (mm's rather than microns). This unique process can be used to prepare most material types and combinations of materials including metals, ceramics, plastics, organics, as well as samples combining hard and soft, thick and thin material layers with zero deformation. True sample structure and key forensic evidence is revealed allowing accurate analysis of early stage failure mechanisms and therefore diagnosis of root-cause. MCS Ltd have also developed a novel process which enables the same deformation-free cross-section whilst retaining access to the sample surface allowing high magnification and resolution analysis in three dimensions, MCS Perfect Edge 3D™. This process has transformed failure analysis capabilities by enabling direct correlation of surface appearance and crosssection condition.
FAILURE ANALYSIS OF DISCOLORED ENIG PADS IN THE MANUFACTURING ENVIRONMENT
Authors: Marciniak Monika , Meagher Michael , Davis Jon , Josefowicz Jack
Published: October 2015

Manufacturing of electronic assemblies using printed circuit boards (PCBs) with electroless nickel/immersion gold (ENIG) surface finishes requires front-end PCB evaluation that will guarantee that good quality product enters the assembly line. The most common is an IPC-4552 mandated plating thicknesses verification of 3-6μm and a minimum of 0.05μm for nickel and gold, respectively. Coupled with visual examination, this verification method suffices for general PCB acceptance but may not be robust enough in cases where ENIG plating in PCBs is compromised. That poses challenges in the manufacturing environment, where resulting latent defects are detected in downstream processes but not at upfront incoming inspection.

Manifestation of such latent anomaly was observed in the form of ENIG pad discoloration with variations from yellow, red or grey discolored surfaces to a more pronounced plating degradation, such as corrosive pitting. The launched failure analysis involved evaluation of manufacturing processes suspected to contribute to the cause of the condition. Effects of thermal processes, cleaning methods, soldering, parylene deposition and factory cleanliness were examined thoroughly. Concurrently, metallurgical analysis of ENIG pads was performed, where samples were subjected to scanning electron microscopic/energy dispersive x-ray spectroscopic (SEM/EDX) cross section analysis, Auger electron spectroscopy (AES) and gold (Au) and electroless nickel (Ni) surface examination. The resulting analysis revealed a highly porous electroless nickel coating with deep crevasses and fissures penetrating down to the base copper (Cu) layer. These open nickel boundaries were attributed to the corrosive environment within ENIG plating, which resulted in the pad surface discoloration. The root cause of ENIG pad discoloration and pitting was traced back to poor ENIG line process controls. Subsequent introduction of a nickel controller into the ENIG line were the implemented countermeasures. To mitigate the effects of discoloration at the electronic assembly level, a tinning process was implemented to prevent nickel plating oxidation and to ensure that good wettability for reliable solder joints was maintained.
Determination of LTCC Shrinkage Variations from Tape Manufacturer to Consumer
Authors: Kupferschmidt James , Girardi Michael , Duncan Brent , Whitlock Daren
Published: October 2015

Low Temperature Cofired Ceramic (LTCC) technology can be applied in numerous functions due to a wide variety of benefits, particularly related to flexibility of applications. Controlling the LTCC shrinkage tolerances in the x, y, and z dimensions is critical during manufacturing and avoids an assortment of down-stream issues that will affect yields. All manufacturers of LTCC tape provide a Certificate of Analysis (COA), which contains the results of the manufacturer's shrinkage testing so production variation can be established from lot to lot. Data from this COA is generally used as a starting point in the shrinkage predictions for manufacturing purposes; however, verification of this data must be performed prior to initiating an LTCC build. This paper investigates validation of one manufacturer's COA data and explains how shrinkage differences can occur between the COA data and the data collected during the verification process. The tracking of this data is also presented as a means to ensure proper controls are in place, and the type and style of lamination and cofiring are shown to be significant contributors to these differences. Data will then be presented in association with characterization prior to and after relocation of LTCC fabrication equipment. Additionally, the COA data can be incorporated into shrinkage estimates that will be utilized to set up process parameters, tolerances, and a control plan.
Thermal analysis, design, and characterization of a reconfigurable switch matrix based on LTCC technology for satellite communications
Authors: Kaleem S. , Rentsch S. , Welker T. , Müller J. , Hein M.A.
Published: October 2015

The thermal characteristics of a reconfigurable switch matrix (RSM) module based on low temperature co-fired ceramic (LTCC) technology are presented. Owing to the PIN-diodes based design, a static power of 1.6 W is dissipated on the ceramic package; the double-sided mounting and integrated bias circuitry demands determination of the temperature distribution within the module. A finite-element thermal simulation model was validated by an infrared (IR) thermograph; the steady-state temperature distribution on the surface of the package estimated by the simulation model differs to the IR measurements by < 1%. This temperature distribution is the result of the thermal interaction among components on the multi-die package with different electrical power dissipation. The temperature on the multi-throw switch monolithic microwave integrated circuit (MMIC) is elevated by ~36.7 K relative to the ambient temperature. The peak temperature occurs on the current-limiting resistors in the bias circuitry; the peak temperature is estimated to be ~45 K above the ambient. In a later version of the RSM, the bias current was reduced by 50%, current-limiting resistor was replaced by two parallel resistors, and additional thermal vias and conductive pads were introduced on the ceramic package. The cumulative effect is a temperature distribution on the package with lowered values. Compared to its predecessor, the temperatures at the current-limiting resistor and the MMIC are reduced by ~20 K and ~14 K, respectively.

With one heat source active on the ceramic package at a time, the resulting steady-state temperatures on this source and the remaining heat sources provided an estimate of the self- and transfer-thermal resistances, respectively. The reciprocity of the heat flow on the package and the three-dimensional symmetric layout required only ‘4’ thermal simulations to determine the symmetric thermal resistance matrix. The significantly reduced values of the computed matrix for the later version of the RSM module demonstrated lower thermal resistance to the ambient, compared to its predecessor. Lastly, the results of thermal measurements conducted with a vacuum wafer prober are presented, in order to validate RSM functionality for vacuum pressures (≤ 1 mPa) and temperatures between 248 K and 338 K; the control current and the transmission coefficient demonstrated variations of ≤ 0.5% and −0.015 dB/K, respectively.
Advancements in Phenomenological Understanding of Thinning and Planarization Processes for TSV-Enabled 2.5-3D Device Fabrications
Authors: Wei Frank
Published: October 2015

Innovations and novel development in substrate thinning and planarization processes driven by advanced packages fabrications are surveyed. For direct 3D die-stacking process approach, a novel methodology for bonded wafer grinding has been put in place based on feedforward wafer thickness metrology and in-situ Auto-TTV Adjustment grinding. This scheme can minimize post-thinning RST variations leading to downstream TSV process improvements. For over-mold facilitated, multi-functional packages and wafer-level fan-out packages, grinding process improved in ways of fixed abrasives and equipment automation. For glass devices processing, new grinding and polishing have been developed on existing Si-compatible equipment. For ductile materials planarization, the surface planer process is presented.
Sandwich Structured Power Module for High Temperature SiC Power Semiconductor Devices
Authors: ANZAI Takeshi , MURAKAMI Yoshinori , SATO Shinji , TANISAWA Hidekazu , HIYAMA Kohei , TAKAHASHI Hiroki , KATO Fumiki , SATO Hiroshi
Published: October 2015

A high temperature sandwich structured power module for high temperature SiC power semiconductor devices has been accomplished. Problems were found in the high temperature building-up process of the module caused by excess warpage of the ceramic substrate. Also the high temperature operation of the power module brings an excess warpage of the structure caused by parts having different coefficients of thermal expansion (CTEs) from each other. In this paper, some countermeasures to overcome the problems are demonstrated.
Soft Computing Methods for Disulfide Connectivity Prediction
Authors: Márquez-Chamorro Alfonso E. , Aguilar-Ruiz Jesús S.
Published: October 2015

The problem of protein structure prediction (PSP) is one of the main challenges in structural bioinformatics. To tackle this problem, PSP can be divided into several subproblems. One of these subproblems is the prediction of disulfide bonds. The disulfide connectivity prediction problem consists in identifying which nonadjacent cysteines would be cross-linked from all possible candidates. Determining the disulfide bond connectivity between the cysteines of a protein is desirable as a previous step of the 3D PSP, as the protein conformational search space is highly reduced. The most representative soft computing approaches for the disulfide bonds connectivity prediction problem of the last decade are summarized in this paper. Certain aspects, such as the different methodologies based on soft computing approaches (artificial neural network or support vector machine) or features of the algorithms, are used for the classification of these methods.
Fundamental Rights in EU Internal Market Legislation
Authors: Kosta Vasiliki
Published: October 2015

This book attempts to systematise the present interrelationship between fundamental rights and the EU internal market in the field of positive integration. Its intention is simple: to examine the way in which, and the extent to which, fundamental rights protection is realised through EU internal market legislation. To that end, the analysis is conducted around four rights or sets of rights: data protection, freedom of expression, fundamental labour rights and the right to health. The book assesses not only what substantive level of protection is achieved for these fundamental rights, but it also estimates whether there is a ‘fundamental rights culture’ that informs current legislative practice. Finally, it asks the overarching question whether the current state of harmonisation amounts to a ‘fundamental rights policy’.

The book offers a much more varied picture of the EU’s fundamental rights policy in and through the EU internal market than perhaps initially expected. Moreover, it builds the case for a more conscious approach to dealing with and enhancing fundamental rights protection in and through internal market legislation, and advocates a leading role for the legislature in the establishment of an internal market that is firmly based on respect for fundamental rights.