3D High Density: technology, roadmap and applications
Authors: Arnaud Lucile , Cheramy Severine , Jouve Amandine , Arnaud Lucile , Fenouillet Claire , Batude Perrine , Vinet Maud 
Published: September 2017

After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moore's law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions.

Additionally, difficulty of associating in a same 2D wafer heterogeneous processes (ie: combining Cmos device with “exotic” material, with low temperature dielectric) also gives an opportunity for a high density 3D approach rather than a 2D one.

As an example, back-side illuminated imagers (BSI Imagers) players have recently released such 3D density (pitch in the range of 5 to 10 micron) [1] ï¿½ From now, thinking about a 3D industrial integration within the range of few microns pitch is not anymore a dream. This specific application may raise some interest for other products such as memory denser stacking, partitioning of a large SoC ï¿½

The objective of the paper is to describe 2 complementary technologies developed at CEA-Leti which address such high density of 3D integration: Hybrid Bonding in the range of few ï¿½ms; Coolcube in the range of few 100e of nms.

We will first take some time to describe both technologies and recent CEA-Leti's results. The positioning of each technologies in terms of pitch and performance will be given.

1 - 3D parallel integration: hybrid bonding

Hybrid bonding integration scheme has been first developed on a wafer scale approach. A test vehicle, with several BEOL layers and connected by the implementation of hybrid bonding, has been designed. Morphological and electrical data will be given leading to the conclusion that the process is very reliable and robust [1], [2].

Contact resistance per contact pads has been measured at few mOhms, which is relatively low compared to tens or even hundreds of mOhms for more classical interconnection technologies (copper pillar, bump, Cu-Cu thermos-compression).

Nevertheless, for cost reason, as well as for multi dies stacking, the need for Die-To-Wafer approach remains true, while keeping a high density of interconnect [3]. The process flow as well as test vehicle designed for this approach will be described.

Major challenges including handling of the dies after sawing and till the bonding itself will be addressed in the paper: wafer handler, wafer preparation and pick & place. Deep characterization is proposed.

2 - 3D sequential integration: CoolCube

An alternative approach to conventional planar integration for future nodes is the monolithic 3D integration (3DVLSI). Monolithic offers the possibility to stack devices with a lithographic alignment precision enabling 3D contacts introduction at the device level (up to 100 million vias per mmï¿½ with 14nm ground rules). 3DVLSI can by routed either at gate or transistor levels. The partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. Partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [4–5]) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III–V nFETs above SiGe pFETs [6–7]. These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI, with its high contact density, can also be seen as a powerful solution for heterogeneous co-integrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [8–9] or highly miniaturized imagers [10].

3- Comparison and roadmap

This paper will also provide features that give some applications' meaning for the development of both technologies in parallel. Particularly, both technologies will be compared in terms of possible pitch reachable. Main comparison features rely on advanced interconnection: dimension & pitch resistance, parasite.

A thermal simulation comparison study will also be included.