bluuebunny/crossref_metadata_2025 huggingface dataset:
Reduced Graphene Oxide Sheets Attached Tin Oxalate Dihydrate As a High Capacity Anode for Lithium Ion Rechargeable Batteries
Authors: Park Jae sang , Myung Seung-Taek
Published: February 2020

Lithium ion batteries have been widely applied as power sources for electronic devices to electric vehicle because of their high energy density, and long cycle life. Commercial graphite is the most commonly used as the anode material for lithium ion batteries. However graphite has its low theoretical capacity (372 mAh g-1). Therefore, to satisfy the growing power requirements, we need to explore alternative materials to replace graphite anode. For these reason, the silicon-based materials, transition metal oxides have been intensively investigated to replace the commercial graphite due to their high capacities, 700 ~ 1000 mAh g-1. Metal oxalate MC2O4 (M : Mn, Fe, Co, Ni, Sn, Cu, Zn) are also interesting because of high capacity. In this study, we synthesize tin oxalate by hydrothermal reaction, of SnCl2ㆍ6H2O (0.001 M), NaC2O4 (0.005 M), distilled water (9 ml), and ethylene glycol (EG, 16 ml) were mixed in a beaker and the mixed solution was stirred at room temperature for 6 h to form transparent solution. This solution was filled in a Teflon-lined autoclave (100ml capacity). This autoclave was sealed and heated at 100 oC - 200 oC for 12 h. After then, the autoclave was cooled to room temperature. The reacted solution were filtered and washed several times with de-ionized water and then dried at 80 oC for 24 h in a convection oven. Also, various contents of rGO were attached by layer by layer method. The obtained powder was analyzed by X-Ray diffraction (XRD, Rigaku, D-max 2000) using CuKα radiation. The XRD data were obtained with 0.03 step size and a 1 s count time. The particle morphologies of the products were analyzed by scanning electron microscopy (SEM, Hitachi, S-4700) and transmission electron microscopy (TEM, Hitachi, H-800). Electrochemical properties were measured in 2032 coin type cell. Electrodes were fabricated from a mixture of the prepared SnC2O4ㆍ2H2O powders (80 wt%), ketjen black (5 wt%), super-P (5 wt%) and polyacrylic acid (10 wt%) in distilled water. The obtained slurry was then applied onto Copper foil and dried in a vacuum oven at 80 oC for 1 h. The electrode was further dried over night at 80 oC under vacuum. The used electrode solution was 1M LiPF6 in a 3 : 7 volume mixture of ethylene carbonate (EC) and dimethyl carbonate (DMC) mixture.

The XRD pattern of the products showed single phase SnC2O4ㆍ2H2O and rGO attached both were obtained without impurity. The fabricated cells were charged and discharged in the range of 0 - 3 V applying a constant current of 100 mAg-1 at 25 oC. The bare sample delivered capacity approximately 643 mAh g-1 at initial charge. Also, the delivered capacities increased to 1170, 1220, 1440 mAh g-1 with increasing the amount of rGO (10, 20, 30 wt%). The rate capability demonstrate that the 30 wt% rGO composite SnC2O4ㆍ2H2O / rGO electrode delivered 467 mAh g-1 at 10 C-rate.

Figure 1
Modeling and Simulation of Negative Capacitance Gate on Ge FETs
Authors: Liao Yu-Hung , Fan Sheng-Ting , Liu C. W.
Published: February 2020

In this work, a polysilicon-ferroelectric (FE) gate capacitor is proposed to be stacked on the Ge-MOSFET to simultaneously maintain the stability and the potential amplification in the sub-threshold region of a Negative Capacitance Field Effect Transistor (NCFET). Hence, the non-hysteresis ID-VG characteristics with sub-60mV/dec subthreshold slope (SS) can be designed. Based on the simulation results, a small signal capacitance model (Fig.1(b)) which includes the effects of gate-to-source/drain overlap, interface trap states at oxide/Ge, and polysilicon/FE/metal is presented.

In the sub-threshold region, the value of -CFE should be as close (but larger) to CMOS as possible to achieve large potential amplification. However, when the strong inversion of the MOS occurs and CMOS increases rapidly, -CFE > CMOS is still required to stabilize the NCFET.[1] The desirable properties can be achieved by utilizing the polysilicon capacitance (Cpoly) which is a function of the applied voltage. The magnitude of the effective CFE’ (=1/(1/CFE + 1/Cpoly)) approaches to CMOS capacitance closely at the subthreshold region and increases when strong inversion of Ge-MOSFET occurs (Fig.2(a)). Hence, a hysteresis-free steep SS NCFET is obtained.

The optimized hysteresis-free polysilicon-FE NCFET achieves SS as low as 43mV/dec in the simulation (Fig.2(b)). Its optimized SS is further improved when the direct S/D overlap with floating metal of Ge-MOSFET increases (Fig.2(b)). On the other hand, the trapped charges in the FE interface will compensate the polarization of the ferroelectric material, and thus degrade the negative capacitance. By tuning the FE thickness and adding fixed charges, its effect on CFE can be balanced through our optimization approach.

Reference:

[1] S. Salahuddin and S. Datta, Nano letters, vol. 8, no. 2, pp. 405–410 (2008).

Figure 1
Effects of Etching Variation on Ge/Si Channel Formation and Resulted Device Behavior
Authors: Chu Chun-Lin , Chen Bo-Yuan Chen , Luo Guang-Li , Li Mei-Yi
Published: February 2020

As CMOS technology scales down to 22nm, traditional planar transistor architectures have reached a fundamental limit for the required short channel control necessary to continue scaling. For good channel control, 3D transistors such as FinFET, tri-gates, and gate-all-around (GAA) FETs are the preferred devices for the sub-20nm CMOS technologies and beyond. Beside the Si channel, Ge-based systems remain the most interesting for emergent device integration. The Ge epichannel directly on Si can be a low-cost solution for the future Si technology nodes, beside the bulk Ge and the SiGe graded buffer technologies. Ge integrated with Si is not straightforward since the 4% lattice mismatch between Ge and Si generates the misfit and threading dislocations. The misfits of the bottom Ge can be removal by anisotropic etching with sensitivity to the defects. The nearly defect-free Ge channel can be formed for GAA transistors. This work reviews the two major remaining challenges that Ge/Si based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, adjusting the HBr/Cl2 plasma ratio and bias power, different fin-like field-effect transistor structures can be fabricated. This process allowed for better gate control than conventional rectangular fins due to the GAA Ge/Si Channel fabricated using the process. Etching decided that Ge is compared to Si materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge/Si device architectures, including surface channel and device behavior configurations, are reviewed. Finally, state-of-the-art Ge/Si device results and future prospects are also discussed.
(Invited) Selective Epitaxial Growth of High-P Si:P for Source/Drain Formation in Advanced Si nFETs
Authors: Rosseel Erik , Dhayalan Sathish Kumar , Hikavyy Andriy Yakovitch , Loo Roger , Profijt Harald Benjamin , Kohen David , Kubicek Stefan , Chiarella Thomas , Yu Hao , Horiguchi Naoto , Mocuta Dan , Barla Kathy , Thean Aaron , Bartlett Gregory , Margetis Joe , Bhargava Nupur , Tolle John
Published: February 2020

As CMOS transistors are scaled down beyond N10, the metal/semiconductor contact resistance becomes a dominant contributor to the total parasitic resistance of the FinFET or Nanowire FET. The utilization of highly-P doped Si:P for the selective source/drain epitaxy was previously shown to be a key enabler to achieve a low contact resistivity in combination with a Ti silicide direct contact and Ge pre-amorphization1.

In this paper, we report on the microscopic properties of strained Si:P epitaxial layers with P concentrations up to ~ 4.6 %. We discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing is modifying the microstructure and leads to an enhanced P activation and diffusion. 

In a second part, we zoom in on the different integration aspects of the Si:P layer for advanced bulk finFETs with a sub 10nm fin width and 45nm fin pitch. We discuss the role of the different epi parameters and the benefit of the high-P concentration for the final device performance2.

Acknowledgements

The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support.

References

[1] H. Yu et al., 2015 Technical Digest – International Electron Devices Meeting, 2015, Vol. 21.7, p. 592.

[2] T. Chiarella et al., submitted to ESSDERC 2016

Figure 1
(Invited) Surface Chemical Choreography of Si/Ge Nanowire Hetero- and Quantum-Structures
Authors: Sivaram Saujan , Hui Ho Yee , de la Mata Maria , Arbiol Jordi , Filler Michael A
Published: February 2020

The placement of distinct functional blocks along the length of semiconductor nanowires is central to their promise as next generation building blocks. This task remains challenging in many systems, including group IV materials. In this talk, I will discuss our recent efforts to fundamentally connect surface chemical bonding and Si/Ge nanowire structure. I will show how we use this insight to choreograph the synthesis of high quality Si/Ge nanowires containing axial hetero- and quantum-structures.
Remote Coulomb Scattering in Ge MOSFET with GeOx/Al2O3 Gate Dielectrics
Authors: Xu Haoyu , Wang Xiaolei , Zhang Jing , Wei Shuhua , Wang Wenwu
Published: February 2020

Remote Coulomb scatterings (RCS) on electron mobility degradation are experimentally investigated in Ge based metal-oxide-semiconductor field-effect-transistor (MOSFETs) with GeOx/Al2O3 gate stacks. The mobility is found increased with thicker GeOx (7.8-20.8 Å). The physical origin of this mobility dependence on GeOx thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeOx/Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks are studied. The charge distributions in GeOx/Al2O3 gate stacks are experimentally evaluated. The bulk charges in Al2O3 and GeOx are found negligible. The density of interfacial charge is +3.2×1012 cm-2 at GeOx/Ge interface, and -2.3×1012 cm-2 at Al2O3/GeOx interface. The electric dipole at Al2O3/GeOx interface is found +0.15 V, corresponding to areal charge density of 1.9×1013 cm-2. The origin of this mobility dependence on GeOx thickness is attributed to the RCS due to electric dipole at Al2O3/GeOx interface. And this remote dipole scattering is found play a significant role on mobility degradation. The discovery of this new scattering mechanism indicates that engineering of Al2O3/GeOx interface is key for mobility enhancement and device performance improvement. These results are helpful to understanding and engineering the Ge mobility enhancement.

Figure 1
AlGaN/GaN High Electron Mobility Transistor Grown and Fabricated on Lattice Matched Metallic Layers
Authors: Ren Fan , Pearton Stephen J. , Ahn Shihyun , Lin Yi-Hsuan , Machuca Francisco , Weiss Robert , Welsh Alex , Smith David , Kravchenko Ivan
Published: February 2020

AlGaN/GaN high electron mobility transistors (HEMTs) showed its promising features in high power and high frequency applications such as inverter units in hybrid electric vehicles, advanced radar systems, and satellite-based communication networks with its high density of sheet carrier concentration, high electron mobility, and radiation hardness. In order to lower the cost of HEMTs, larger diameters substrates are needed. Currently, the HEMT structures are grown on non-native sapphire, SiC and Si substrates or on native substrate of vapor phase epitaxy (VPE) GaN wafers. HEMTs grown on sapphire substrate suffer from poor heat dissipation and higher defect density due to the relative larger lattice mismatch to GaN. SiC has a very good thermal conductivity and is less lattice mismatch to GaN, but high quality semi-insulating SiC substrates are quite expensive. Although, Si substrates are fair low cost and available for larger diameter substrates, due to larger lattice mismatch to GaN, it requires to grow thick complex AlGaN buffers prior to the growth of GaN layer to reduce the threading dislocation density. These thick AlGaN layers are very defective and thermal resistive, which will hinder device heat dissipation. VPE grown GaN wafers are limited to 2-3” diameter and very expensive. Recently, it was reported that high quality GaN layers were grown by RF plasma-assisted molecular beam epitaxy (PA-MBE) or metal organic chemical vapor deposition (MOCVD) on high-quality, single crystal ZrTi refractory metal alloys deposited by plasma sputtering on c-plane sapphire and Si substrates. These ZrTi refractory metal alloys are not only lattice match to GaN, but have a similar coefficient of thermal expansion (CTE) as the CTE of GaN [1]. By employing these ZrTi alloys, there is no need to grow thick AlGaN buffer, both photonic and electronic GaN based device structure can be grown on large area Si substrates to achieve low cost GaN based device fabrication.

In this work, we have demonstrated AlGaN/GaN HEMTs grown on ZrTi refractory metal alloys, which were deposited on both Si and sapphire substrates. HEMTs with a gate dimension of 1 µm × 100 um were fabricated and characterized. Both dc and rf performance of AlGaN/GaN HEMTs fabricated on the ZrTi metal alloys will be presented.

1. “Epitaxial Growth of High Quality GaN Films on Lattice Matched Metallic Layers”, A.M. Dabiran, F. Machuca, I. De, and R. Weiss, ECS Trans. 66, 113-117 (2015).
Direct Detection of Low Concentration DNA in High Ionic Strength Solution with AlGaN/GaN High Electron Mobility Transistors
Authors: Chen Yen Wen , Wang Yu-Lin
Published: February 2020

In this research, the direct detection of DNA sequences in physiological salt concentration by FET based biosensor has been investigated. Traditionally, most of the DNA detection methods are optical measurements, such as fluorescence or Raman spectroscopy which are always expensive, bulky and hard to quantify. In contrast with the traditional method, we use AlGaN/GaN high electron mobility transistor (HEMT) to detect the target ssDNA. The III-IV compound semiconductor based transistor is chemically inert and possess really high resistivity to high salt environment and has low possibility of corrosion. The HEMT device is fabricated with four mask: MESA, SD metal, final metal and gate opening and presents a 3D structure which isolates the transistor channel and gold sensing region.(fig 1.) Moreover, with the isolated gold sensing area, the transistor can be extremely small as the gold sensing region stays in the large area. This kind of FET having high transconductance gain, can significantly improve the S/N ratio and sensitivity. Current measured in PBS buffer serves as the baseline of the biosensor. Probe ssDNA is immobilized on the gold gate electrode positioned at a fixed distance from the transistor channel. Device is operated with 2V drain voltage and a tunable gate pulse voltage. As the complementary DNA concentration, ranging from 1fM to 100nM, is introduced, the current gain of the device changes accordingly. The sensor can efficiently detect target DNA down to a low concentration of 100 fM. This ultrahigh sensitivity and low S/N ratio characteristics exhibited by the sensor makes it a competitive alternate choice compared to the traditional existing sensors. The miniaturized device design and ease of fabrication and testing indicate the potential of the sensor to be used as a commercial DNA biosensor.

Figure 1
(Invited) Towards Topological Antiferromagnetic Spintronics
Authors: He Qinglin , Pan Lei , Murata Koichi , Wang Kang L.
Published: February 2020

Magnetic topological insulators in the tetradymite family, such as Cr/V doped Bi2Se3, Bi2Te3, Sb2Te3, and their ternary compounds, provide a new route for realizing the novel time-reversal symmetry-breaking physics [1, 2]. To effectively manipulate these versatile quantum states, various heterostructures are demonstrated by utilizing the unique Néel order in an antiferromagnet CrSb and the topological order in a magnetic topological insulator Cr-doped (Bi,Sb)2Te3 [3-5] grown by molecular beam epitaxy. It is shown that emergent interfacial magnetic interactions can be tailored through deliberate artificial structural engineering. By investigating bilayers, trilayers, and superlattices made of these two components, interfacial exchange coupling and antiferromagnetic exchange coupling were shown to affect the topological magnetism as mediated by the massive Dirac fermions. The relationship of magnetic spin textures of the antiferromagnet to that of the magnetic topological insulator was further explored through polarized neutron reflectometry/diffraction, magneto-electrical transport measurements as well as the control of the mass of Dirac fermions by using different Cr doping concentrations. From these studies, the antiferromagnet is shown to be an efficient interfacial- and interlayer- exchange coupling layer for the massive Dirac fermions of the magnetic topological insulator, which additionally gives rise to a giant enhancement in magnetic ordering. This work provides a new framework for new topological antiferromagnetic spintronics.

*The work was in part supported by the SHINES Center, an Energy Frontier Research Center funded by the U.S. Department of Energy, Office of Science, Basic Energy Sciences under Award # S000686, National Science Foundation, Army Research Office program under contract 15-1-10561, TANMS, FAME Center, and a Semiconductor Research Corporation program sponsored by MARCO and DARPA. References:

[1] Y. L. Chen et al., Science
329, 659 (2010).

[2] X.-L. Qi, T. L. Hughes, and S.-C. Zhang, Physical Review B
78, 195424 (2008).

[3] X. Kou et al., Nature Communications
6, 8474 (2015).

[4] X. Kou et al., Physical Review Letters
113, 137201 (2014).

[5] Y. Fan et al., Nature Materials
13, 699 (2014).
(Invited) Monolithic Integration of n-In0.53Ga0.47As and p-Ge FinFETs on Si
Authors: Chang Shih-Pang , Lin Kun-Lin , Wu Chien-Ting , Chen Cheng-Yu , Chen Mon-Yang , Lee Rong-Ren , Hsu Wen-Da , Chen Shih-Hong , Su Chun-Jung , Luo Guang-Li , Lee Shih-Chang , Hsu Ta-Cheng , Yeh Wen-Kuan , Chyi Jen-Inn
Published: February 2020

With continuous increase in transistor count and clock frequency, the power density of current Si integrated circuits has reached a level that calls for a revolutionary change in transistor technology. High hole mobility Ge and high electron mobility InGaAs have been considered to be the most promising channel materials for p-channel and n-channel MOSFETs, respectively. Selective-area growth (SAG) on nano-trenches has been quite popular in integrating III-V materials with Si substrates. Since there exists a high lattice mismatch between III-V materials and Si, obtaining defect-free epilayer is still a great challenge. In this work, we demonstrate selective area growth of InGaAs on Ge trenches aiming at integrating n-channel InGaAs FinFETs and p-channel Ge FinFETs side by side on a Si substrate for CMOS applications.

The Ge templates, which were grown on Si by chemical vapor deposition, were prepared by etching through an oxide mask using a dilute H2O2 solution to create Ge linear trench structures with embedded {111} facets at the bottom of the trenches for facilitating the regrowth of III-V materials. The III-V materials were selectively grown on the patterned Ge templates by metal-organic vapor phase epitaxy. An InGaP buffer layer, which has a wide bandgap and is beneficial for electrical isolation between the channel and substrate, was grown onto the Ge trenches. Undoped InGaAs was grown on InGaP as the n-channel material.

High resolution transmission microscopy investigations show that very few dislocations are present near the Ge/InGaP interface in the trenches. It is found that In content of InGaP increases from 50 % to about 70 % with growth as evidenced by energy-dispersive x-ray spectroscopy (EDX). Interestingly, composition grading is also observed on the subsequently grown InGaAs. It begins from an In0.21Ga0.79As layer, which has good lattice match to the In0.7Ga0.3P layer beneath, then changes to the nominal In0.71Ga0.29As layer near the top of the fin. The strain in InGaAs is partially released through the generation of dislocations near the InGaAs/InGaP interface, leading to a nearly defect-free region at the top of the fin. A growth mechanism is proposed to account for the correlation between strain accommodation, composition grading, and defects generation.
Behaviors of GaSb and InSb III-V Semiconductor Surfaces in the Wet Chemical Solutions
Authors: Lim Sangwoo , Seo Dongwan , Na Jihoon , Oh Eunseok
Published: February 2020

III–V compound semiconductors can be used as new channel materials because of their high carrier mobilities and low power consumption. Among various III–V compound semiconductor materials, Sb-based III-V semiconductors such as gallium antimonide (GaSb) and indium antimonide (InSb) are also gaining attention as a channel material, because they have extremely high carrier mobilities and an excellent lattice matches with various III–V ternary and quaternary compounds. However, Sb-based III-V semiconductors are easily oxidized by atmospheric oxygen and forms native oxide layers. Therefore, effective surface preparation with an understanding of its surface chemistry is required. However, the reaction kinetics in the cleaning / surface preparation process and the mechanisms of etching and oxidation in the overall process have not yet been elucidated. In the current study, the effect of representative wet treatments in acidic and basic solutions on the GaSb and InSb surface behavior is studied.

When GaSb and InSb were treated in acidic hydrochloric acid - hydrogen peroxide mixture (HPM) solutions, the etching rates and oxide layer thicknesses of both GaSb and InSb surfaces decreased, and the contact angles increased as the H2O2 concentration was decreased by dilution. In addition, the results of the XPS measurements confirmed that the XPS Ga3d and In3d5
/2 peak area ratios of Ga2O3/GaSb and In2O3/InSb decreased with decreasing H2O2 concentration in HPM. Based on the observed results, it is suggested that H2O2 serves as a strong oxidant in acidic HPM solutions and the overall surface reaction of GaSb and InSb in HPM solution depends on the surface oxidation by H2O2. In addition, the Sb 3d3/2 peak area ratios of Sb2O3/GaSb (or Sb2O3/InSb) were not significantly changed with H2O2 concentration in HPM. Therefore, it is thought that the surface oxidation behavior of Sb-based materials is determined by the group III elements, Ga and In, rather than the group V element, Sb. On the other hand, in basic ammonium hydroxide - hydrogen peroxide mixture (APM) solutions, H2O2 tends to decompose into OH-, etching species, so that Ga atoms on the GaSb surface or in the Ga oxide can be etched by OH- to form aqueous H2GaO3
- ions. Therefore, H2O2 cannot contribute to the oxidation of GaSb in basic APM solutions, but the surface oxidation of GaSb is accelerated as the solution is diluted by H2O. In APM solution, H2O works as an oxidant on the GaSb and InSb surfaces.
Characterization of Aggregated Carbon Compounds at SiO2/SiC Interface after Plasma Oxidation at Near Room Temperature
Authors: Arima Kenta , Hosoo Kohei , Ito Ryota , Saito Naoki , Kawai Kentaro , Sano Yasuhisa , Morita Mizuho
Published: February 2020

Si sublimation from a silicon carbide (SiC) surface at elevated temperatures is a convenient and simple method of forming graphene [1]. The increase in carbon concentration at the monolayer scale on SiC prior to graphene growth is the key to obtaining graphene with reduced pit density. There have been some attempts to achieve this, one example of which is the use of vacuum evaporation from a solid carbon source [2, 3]. We have proposed a novel chemical route to enrich the carbon concentration on SiC. Namely, we have found that aggregated carbon compounds with a few monolayers are formed when an initial hexagonal SiC surface is treated by plasma oxidation at near room temperature and then the oxide layer (SiO2) with a thickness of ~10 nm is stripped off by HF etching [4, 5]. No additional carbon clusters were formed in the conventional thermal oxidation of SiC at 1000°C. Neither the composition of the aggregated compounds nor the mechanism of the generation of such carbon species by the plasma-assisted procedure is clear, however.

In this study, we reveal that, after the plasma oxidation followed by wet etching, the SiC surface is more hydrophobic than the initial SiC surface terminated by hydroxyls. Taking the electronegativities of Si, C and O atoms into account, this result indicates the formation of C-O and C-C, which is confirmed by the chemical-shift analyses of O1s and C1s spectra taken by X-ray photoelectron spectroscopy.

In thermal oxidation, it is widely accepted that the reaction (2SiC+3O2 -> 2SiO2+2CO) forms a SiO2 layer whereas CO molecules diffuse into the oxide and are finally emitted in the gas phase. However, it has also been reported that CO molecules can diffuse a high-quality SiO2 film at temperatures higher than 900°C [6]. It is reasonable to suppose that, in the case of plasma oxidation at near room temperature, CO molecules reside at the SiO2/SiC interface and form carbon compounds. In addition, a consideration based on thermodynamics implies the direct formation of solid carbon clusters during oxidation at low temperatures by the reaction SiC+O2 -> SiO2+C(s) [7]. These growth kinetics of SiO2 on SiC well explain the obtained results described in the previous paragraph.

Such a carbon residue at the SiO2/SiC interface can degrade the performance of metal-oxide-semiconductor (SiC) devices. But it may serve as an additional carbon source for epitaxial graphene growth on SiC.

 

[1] C. Berger et al., J. Phys. Chem. B, 108, 19912 (2004).

[2] A. Al-Temimy et al., Appl. Phys. Lett., 95, 231907 (2009).

[3] J. Park et al., Adv. Mater., 22, 4140 (2010).

[4] N. Saito, K. Arima et al., Carbon, 80, 440-445 (2014).

[5] N. Saito, K. Arima et al., ECS Transactions, 64, 17, 23 (2014).

[6] O.H. Krafcsik et al., Jpn. J. Appl. Phys. 40, 2197 (2001).

[7] K. Kita et al., ECS Transactions, 64, 8, 23 (2014).
The Roles of Band Bending, Surface Misorientation, and Passivation on Electrical Transport Across III-V Bonded Structures
Authors: Yee Matthew , Liao Michael , Seal Mark , Goorsky Mark S.
Published: February 2020

The electrical conductivity across a variety of III-V semiconductor wafer pairs can be assessed through an understanding of the surface band bending expected prior to bonding as well as the role that interfacial defects play. With results from bonding of several different materials combinations, surface orientations, and passivation treatments, as well as an assessment of barrier heights reported in the literature for transport in polycrystalline III-V materials as well as for other III-V bonded materials combinations, a general model has emerged. Lattice mismatch does not play a major role in limiting conductivity across an interface; however, misalignment (through twist or tilt) produces interfaces with increased resistance. Passivation techniques are most important for systems with significant surface band-bending; for III-V surfaces that do not exhibit signifncant band-bending there is only a slight improvement associated with a sulfur-based pre-bonding passivation step. The electrical characteristics of a grain boundary, whether in polcrystalline material or at a bonded interface, are determined by the presence of defect states and interfacial charge which creates band bending and Fermi level pinning. The barrier heights and widths from zero bias conductance vs bias measurements over a wide range of temperatures and for different materials can be matched to band structure simulations of bonded semiconductor heterojunctions with resultant I-V curves showing good agreement between experiment and theory. Based on this study which combines experimental results and transport modelling, it is expected that narrow bandgap III-V semiconductors such as GaSb, InAs, and InSb would be ideal candidates for direct wafer bonding, even when bonded to materials with significant surface band bending, such as GaAs.
III-V/Si Hybrid Laser Array with Dbr on Si Waveguide
Authors: Zhao Ran Guang , Li Tao , Yanping Li , Chen Weixi , Pan Jiaoqing , Yuan Lijun
Published: February 2020

We report an eight-channel silicon evanescent laser array operating at continuous wave and room temperature conditions using selective-area metal bonding technique. The laser array is realized by evanescently coupling the optical gain of InGaAsP multi-quantum wells to the silicon waveguides of varying widths and patterned with distributed Bragg reflector (DBR) gratings. The lasers have emission peak wavelengths in range of 1537 and 1543 nm with a wavelength spacing of about 1.0 nm. The thermal impedance ZT of these hybrid lasers are evidently lower than those DFB counterparts.
(Invited) Thermomechanical Finite Element Modeling of Cu-SiO2 Direct Hybrid Bonding with a Dishing Effect on Cu Surfaces
Authors: Estevez Rafael , Beilliard Y. , Parrr G. , McGarry P. , Coudrain P. , Di Cioccio L.
Published: February 2020

Copper direct bonding technology is considered to be one of the most promising approaches for matching the miniaturization needs in future tridimensional integrated high performance circuits (3D-IC). However, the bonding mechanisms of copper surfaces with an initial dishing effect, induced by the polishing step, must be investigated in order to optimize the adhesion process and prevent further reliability issues. In this study, we present thermo-mechanical finite element simulations of Cu-SiO2 hybrid bonding with account for the annealing step and various amplitudes of the initial dishing. A cohesive interaction model that mimics nonlinear interactions between Cu/Cu and SiO2/SiO2 interfaces with related bonding mechanism is implemented within a nonlinear contact strategy. The overall bonding process along with the influence of the annealing conditions and the copper plastic response on the closure of the Cu/Cu interface are investigated. 

Figure 1
Impact of Water Edge Absorption on Silicon Oxide Direct Bonding Energy
Authors: Fournel Frank , Tedjini Marwan , Larrey Vincent , Rieutord François , Morales Christophe , Bridoux Claudine , Moriceau Hubert
Published: February 2020

Direct bonding of silicon and silicon dioxide thin films is now widely used in industry for SOI (Silicon on Insulator) elaboration for instance or in some backside imager manufacturing processes which are now at a stage of mass production processes. Silicon oxide capping layer is very often used as a convenient bonding layer allowing efficient topography planarization with classical CMP (Chemical Mechanical Planarization) process. Thus silicon oxide//silicon oxide direct bonding has been very developed when bonding interface behaviour deserves to be deeply studied. The bonding energy evolution is one of the key parameters and has been widely studied for many years [1,2,3]. Notably, water edge penetration at the bonding interface after the direct bonding was reported recently [4,5]. This work is then focused on the impact of water edge penetration on silicon oxide direct bonding energy values.

200 mm <001> silicon wafers are thermally oxidized at 950 °C under steam atmosphere in order to growth 145 nm of silicon dioxide thin film. After classical RCA cleaning, these wafers are bonded at room temperature and ambient pressure. Just after the bonding, they are diced into 2 cm wide beams and annealed at 300 °C for bonding energy measurement under anhydrous atmosphere [3]. But after the dicing, the atmospheric water can start to penetrate the direct bonding interface. Two times are then considered: t1 is the time between the dicing and the annealing steps and t2 is the time between the annealing and the energy measurement. The bonding energy dependence regarding t1 and t2 is studied.

It will be shown that increasing t1 is beneficial for the oxide/oxide bonding energy in contrary to t2 increase. A mechanism for bonding evolution will be proposed to explain these results mainly based on water stress corrosion influence. The annealing atmosphere will also be pointed out to explain some behaviours.

Recommendations for storage time and atmosphere as well as for annealing conditions could then be formulated to make bonding energy values at the wafer edge suitable for subsequent device elaborations.

 

REFERENCES

[1] G. Kräuter, A. Schumacher, U. Gösele, Sensors and Actuators A: Physical, Vol. 70 (3), 271–275 (1998).

[2] F. Fournel, C. Martin-Cocher, V. Larrey, H. Moriceau, F. Rieutord, WaferBond International Conference Brunswick Germany (2015)

[3] F. Fournel, L. Continni, C. Morales, J. Da Fonseca, H. Moriceau, F. Rieutord, A. Barthelemy, I. Radu, J. Appl. Phys., 111, 104907 (2012)

[4] M. Tedjini, F. Fournel, V. Larrey, F. Rieutord, WaferBond International Conference, Brunswick Germany (2015)

[5] M. Tedjini, F. Fournel, H. Moriceau, V. Larrey, D. Landru, O. Kononchuk, S. Tardif, F. Rieutord, Submitted to Journal of Applied Physics.
(Invited) Locally Measuring the Adhesion of InP Membranes Directly Bonded on Silicon
Authors: Patriarche Gilles , Pantzas Konstantinos , Le Bourhis Eric , Beaudoin Gregoire , Talneau Anne
Published: February 2020

Direct bonding of III-V semiconductors on silicon has recently become a promising technology for the fabrication of hybrid photonic integrated circuits (PICs). In such hybrid PICs, active optical functions (amplification, emission) are ensured by the direct-gap III-V semiconductor and passive functions (guiding, switching) by the Si guiding layer. One particularly attractive feature of hybrid III-V/Si platforms is the possibility to densely integrate a variety of advanced optical functions in the guiding layer using sub-100 nm patterns in the silicon. Nano-patterning the silicon surface may, however, weaken the adhesion of the III-V semiconductor to silicon, potentially making the hybrid bonded stack subject to debonding in subsequent processing steps, such as cleaving. In this context, quantitatively assessing the adhesion of the III-V to Si in a patterned area and comparing it against the adhesion in a nearby unpatterned area can provide one with feedback useful for improving the patterning , post-patterning surface preparation, or bonding processes. Ultimately, such measurements can allow one to propose optimal designs for advanced embedded optical functions in hybrid III-V/Si PICs. Instrumented nanoindentation, Atomic Force Microscopy and Scanning Transmission Electron Microscopy have been combined ex situ to study the adhesion of thin InP membranes to bulk (100) silicon substrates but also to sub-100nm patterned (100) silicon substrates. Three distinct regimes are identified in the deformation of the InP/Si stacks during these experiments: the first is plastic flow of InP at low loads; the second is elastic debonding of the InP membrane, far from the indented zone at medium loads; lastly, the local amorphisation of the underlying Si substrate at high loads. The regime of intermediate loads is shown to be particularly useful in the evaluation of the surface bonding energy of InP to Si [1,2]. 

[1] K. Pantzas, E. Le Bourhis, G. Patriarche, A. Itawi, G. Beaudoin, I. Sagnes and A. Talneau Eur. Phys. J. Appl. Phys. 65 (2014) 20702 

[2] K. Pantzas, E. Le Bourhis, G. Patriarche, D. Troadec, G. Beaudoin, A. Itawi, I. Sagnes and A. Talneau Nanotechnology 27 (2016) 115707
High Efficiency Cleaning Processes for Direct Wafer Bonding
Authors: Dussault Donald , Rothballer Jan , Kurz Florian , Reichardt Make , Dragoi Viorel
Published: February 2020

Permanent direct wafer bonding has been an enabling technology for many years, especially in the areas of engineered substrates such as SOI, and in various MEMS or backside illuminated CMOS image sensors (BSI) process flows. With the emergence of new and more challenging bonding requirements and materials, precision and surface condition becomes more critical.

One key requirement for a void free and reliable bond is a particle free surface. Residual particulate remaining in the bonding interface can lead to post-bond voids, bond defects and loss of yield. The optimal post cleaning condition is zero particles, and in fact, one of the basic requirements of pre-bond cleaning methods is to be particle neutral, leaving no additional particles after the cleaning process. Historically the critical particle sizes were in the 1um range, but due to continuous feature size reduction, this critical size is today in the area of 90 nm with a strong pressure to reduce below 20 nm.

In prior work (reference 1) we have demonstrated a particle neutral cleaning process on 200 mm wafers in a laboratory environment. The cleaning method and MegPie® megasonic apparatus used in prior work is comparable to that used in the current experiments. In the prior experiments, the wafers were intentionally contaminated with large numbers of silicon nitride particles so that particle removal efficiency could be measured and compared to industry standards.

In this current work we have moved from laboratory generated artificial contamination to real word production conditions, including the unknown type and quantity of particulate that would be typical to incoming pre bond substrates. The results demonstrate the suitability and repeatability of this non contact cleaning method in real world production consitions.

The cleaning tests were performed on an EVG Gemini®FB fully automated fusion bonding system using for cleaning a large area megasonic transducer MegPie®

Particle measurement was performed using the KLA-Tencor SP1 Particle Counter and post bond performance was performed using the SAM450 from PVA Tepla Analytical Systems.

Reference

1. F. Fournel, L. Bally, D. Dussault, and V. Dragoi, Innovative megasonic cleaning technology evaluated through direct wafer bonding. (ECS 2010)
(Invited) Present and Future of LTPS Technology
Authors: Kaneko Toshiki , Nakamura Takashi , Kimura Hiroyuki
Published: February 2020

Japan Display Inc. has developed excellent quality TFT-LCD displays based on precise LTPS technology and progressive LCD-cell technology [1]. Their advantages are less than half the power consumption and a contrast ratio of 2000:1 using unique RGBW technology, photoalignment technology, and an in-cell touch panel technology with 1mmΦstylus input simultaneously.

We have recently developed two high resolution displays with more than 500-ppi which one can realize higher response rate with higher frame rate driving and another can reduce the power consumption by 30% with a lower frame rate driving. One is the 17.3-inches 8K4K display with 550ppi and 120-Hz frame rate driving and another is the 8-inches 4K2K with 510-ppi with 30-Hz frame rate driving.

We adopted two technologies for the LTPS backplanes, one was a 1.5-µm high resolution process, and the other was an increase of the pixel capacitance. Figure 1 shows the cross sectional SEM image of a poly-Si layer. I-line photolithography was adopted and the dry etching condition of the poly-Si patterning process was optimized in order to obtain poly-Si islands 1.5-µm wide with a good taper angle.

In addition, a thinner insulator for the storage capacitance Cs was fabricated almost by half to increase the CSvalue with care in terms of coverage over other layers.

The adoption of a 1.5-µm short channel LTPS process and thinner insulator thickness can contribute two benefits. One is a decrease in load capacitance which is considerably increased as the number of pixels increase up to 8K4K. Another is a decrease in feed through voltage ΔVth which is described by equation (1), which causes cross talk especially on higher resolution display. The developed 17.3-inches 8K4K LTPS-LCD with 510-ppi resolution in collaboration with NHK is shown in Figure 2 [2]. We realized uniform transmittance distribution and sufficiently small cross talk much less than 2% on this prototype display which attributes its small load capacitance and small feed through voltage.

We also developed 8-inches 4K2K display with 510-ppi. By adopting the same LTPS technologies, we also realized 30-Hz frame rate driving with acceptable flicker level which is defined as the range of the maximum and minimum liminance. We could decrease the total power consumption for drinving by 32% adopting 30-Hz frame rate driving as shown in Figure 3.

Reference:

[1] T. Kaneko, et al., "Innovative 5-inch FHD and 7-inch WQXGA Displays for Next Generation Smartphones and Tablets", Proc. SID'13, 2013, pp693-296.

[2] K. Mochizuki, et al., "A 510-ppi 8K4K LTPS TFT-LCD with 120-Hz Frame Rate Driving" SID'16, Digest paper, 67.2, 2016

Figure 1
(Invited) Microcrystalline Silicon Based TFTs and Resistors for Reliable Flexible Electronics
Authors: Kervran Yannick , Kandoussi Khalid , Dong Hanpeng , Janfaoui Sabri , Coulon Nathalie , Simon Claude , Jacques Emmanuel , Mohammed-Brahim Tayeb
Published: February 2020

Silicon based flexible electronics is shown here as the right way when considering the reproducibility of the process and the long-term reliability, the only way leading to commercially available products. Microcrystalline silicon films are deposited directly on plastic substrates (PEN and Polyimide) at low temperature. Films are highly crystallized. Crystalline volume is higher than 73% for 50nm thick film as calculated from Raman spectra.

Using such film, resistances are fabricated and checked as deformation gauges. The mechanical behaviour of microcrystalline silicon films under longitudinal as well as transversal tensile (Figure 1) and compressive stress is studied. The effect of the nature of the substrate and its thickness on this behaviour is studied also. These studies led to determine the maximum strain that can hold microcrystalline silicon film. This strain limit is reached by bending the film at different curvature radii depending on the thickness of the substrate. Lower curvature radius is reached with thinner substrate. Lower than 1 mm radius, leading to fold in half the film, is reached without breaking it (Figure 2). This high flexibility together with demonstrated reliability led the use of a matrix of microcrystalline silicon based gauges in the determination of any form and in the characterization of human pulse (Figure 3).

Thin-film transistors are also fabricated on previous substrates at the same low temperature. Undoped microcrystalline silicon forms the active layer of these transistors. Phosphorus doped microcrystalline silicon is used as source and drain regions. The gate insulator is also deposited at low temperature. TFTs show very high flexibility. TFTs support lower than 1 mm curvature radius leading to compressive as well as tensile strain, without breaking (Figure 4). More than 200 times of such extreme bending are done without changing the TFT’s characteristics (Figure 5).

Figure 1
Controllably Aligned Ultra-Flexible and High-Performance Organic Single-Crystal Arrays Via Solvent Vapor Annealing for Large Area Soft Electronics
Authors: Kang Jingu , Kim Jaehyun , Jo Jeong-Wan , Kim Myung-Gil , Kim Jaekyun , Park Sung Kyu
Published: February 2020

Recently, semiconducting organic materials have been actively investigated for achieving high performance organic thin-film transistors and applying to diverse electronic applications. Particu-larly, in order to control the location and direction of organic single crystals with a densely packed molecular structure, several techniques such as inkjet printing and sheared deposition us-ing a self-assembled mono-layer pattern have been suggested. In this presentation, we used sol-vent vapor anneal (SVA) process of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) organic films, forming diverse patterns of their organic single crystals. Room-temperature photochemical patterning of polymer dielectric layer by using deep ultraviolet (DUV) enables the determined organization of C8-BTBBT single crystals with controlled-position and orientation. In SMSVA process, C8-BTBT small molecules become mobile on soluble polymer layer and re-assembled into micro rod-shaped single crystal only at pristine polymer dielectric region.

 Using the novel SVA, C8-BTBT single crystal arrays were easily produced on narrow trench of pristine polymer dielectric while their diverse patterns such as a multi-lines, zigzags and star shape were readily possible as well. Based on these arrays of C8-BTBT single crystals, we fabricated high performance and large current organic single crystal transistor on a 3-μm-thick flexible film in which the saturation mobility of devices exceeds ~ 3 cm2 V-1s-1 for one single crystal micro-rod. It was also found that the high performance of single crystal transistor remained functional following the aggressive bending test. We rolled up the device on optical fiber (bending radius:150 μm). After the bending test, the devices show reliable performance without significant degradation from its initial characteristics.
(Invited) High Performance of Nonvolatile Memory with Van Der Waals Heterostructures of WS2 and Multi-Layered Graphene
Authors: Kim Eun Kyu , Qiu Dongri
Published: February 2020

Two-dimensional (2D) semiconducting layered materials of transition metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) and tungsten disulphide (WS2) with typical energy band gap of 1-2 eV have emerged as novel materials and have presented various fascinating physical properties. Recently, worldwide researchers have made significant efforts on building flash memories with MoS2 channel based field-effect transistor. They have showed 28-40% charge loss after 10 years retention by using few-layered graphene, MoS2, metallic nanocrystal, hafnium oxide, and guanine as a charge trapping layer. However, limited works built their nonvolatile memories using entirely of assembled 2D crystals. Moreover, few-layered graphene with more than seven layers of graphene is attractable for use in floating-gates, because the high capacity of the charge storage as the density of state of few-layered graphene is five folds larger than that of graphene. WS2 has an indirect band gap of 1.3 eV (in bulk) and an electron affinity of 4.0-4.4 eV. Theoretical studies have predicted that the electron/hole effective mass of WS2 is smaller than that of other semiconducting 2D crystals. Along with high thermal stability and stable chemicals make it suitable for use as a channel of memory cells. To our knowledge, WS2 based memory is still undeveloped to date. Here, we report a novel concept of nonvolatile memories utilizing functional van der Waals heterostructure in which multi-layered graphene is encapsulated between SiO2 and hexagonal boron nitride. We observed that a large memory window (20 V) allows to reveal high on-/off-state ratio (>103). The devices with high charge storage capacity of few-layered graphene and high quality of WS2 manifest perfect retention of 13% charge loss after 10 years, which was recorded as 2 to 3 folds smaller than that of reported MoS2 memories. This study offers new device architecture for achieving future nanoelectronic building blocks by utilizing atomically thin van der Waals stacks.

Figure 1