(Invited) A Low-Power Neuron Circuit Using a Positive Feedback Device for Spiking Neural Networks
Authors: Woo Sung Yun , Oh Seongbin , Kang Won-Mook , Seo Young-Tak , Lee Soochang , Kim Jangsaeng , Lee Jong-Ho 
Published: December 2020

For more efficient computation, researches on neuromorphic systems suitable for neural networks have been conducted [1]. To replace conventional neuron circuits for integrate-and-fire (IF) function in neuromorphic systems, neuron devices with high density and low power consumption per spike have been studied [2, 3]. In the previous work, an n-type positive feedback (PF) device with steep switching characteristic was proposed for hardware-based neural networks [4]. In this paper, a p-type PF device with a charge storage layer is reported as neurons, which integrates signals using positive program bias (V
PGM). Fig. 1 shows a top view of a p-type PF device and an energy band diagram of the PF operation. Doping concentration and length of n-/p-channels are 1×1018 cm-3 and 1 μm, respectively. Fin width (W) and height (H) of PF device is 35 nm and 100 nm, respectively. Thickness of gate dielectric (SiO2/Si3N4/SiO2) for the charge storage layer is 2/4.2/9 nm. As a gate bias (V
G2) decreases, a hole-injection barrier decreases, and holes easily flow from anode to p-channel region. As more holes are injected to p-channel region, electron injection barrier decreases, and electrons easily flow from cathode to n-channel region. By positive feedback like this, an anode current (I
A) abruptly flows from anode to cathode as shown in the Fig. 1 (c). As a V
PGM pulse is applied to G1, a turn-on voltage (V
on) is shifted slightly toward the positive voltage. After 15 V
PGM pulses are applied, V
on shifts from -0.3 V to 0.03 V as indicated by the diamond symbols in Fig. 1 (c). The change of V
on by the number of pulses (V
PGM) mimics the IF operation of neurons. Fig. 2 shows the symbol of the PF device and the repeated measurement for IF operation of the PF device as a parameter of V
G1. IF and reset operations were measured by applying pulses of V
G1 and V
reset (-7 V) to G1. Reliable IF function with the repeated measurement is obtained in the PF device. As V
G1 increases from 5.8 V to 6.2 V, the firing rate of the PF device increases due to the increase in electrons trapped in the charge storage layer (Si3N4). Fig. 3 (a) shows a conventional neuron circuit for the IF function in SNNs [5]. When the membrane voltage (V
mem) exceeds the threshold of M2, M2 is turned on and the neuron is fired. However, even if the membrane voltage is less than the threshold voltage of M2, the subthreshold current continues to flow, resulting in a leakage path through M3 and M2, which takes up a large part of the standby power in neuron block. Hence, replacing M2 with a PF device with steep switching characteristics can effectively block this leakage path. Consequently, it can significantly reduce power consumption [4]. A 400–128–10 sized MLP network was simulated in the circuit level. A full network is composed of NOR flash synaptic array [6], current mirror, and IF block. The power consumed by each block is shown in Fig. 3 (b). MNIST data sets were presented over 8 time steps with each duration of 1 ms. IF block consumes 177.2 mW, which is about 28.3% of the total power consumption, and most of the power is consumed by the leakage or generation of output spikes. Networks that use only few spikes [7] have a higher rate of power consumption by the leakage than creating spikes. In addition, to accurately calculate the negative weight sum using the capacitor (C
mem), it is necessary to set the initial membrane voltage to a positive value, which further increases power consumption by the leakage. By replacing M2 with a PF device, it is possible to construct a novel neuron by significantly reducing unnecessary power consumption in the conventional neurons.

Reference

[1] S. Yu, Proc. IEEE 106, 2 (2018)

[2] J. Luo et al., IEDM Tech. Dig. 122 (2019)

[3] S. Dutta et al., Sci. Rep. 7 (2017)

[4] K. Choi et al., Front. Neurosci. 12, 704 (2018).

[5] W. Kang et al., Int. Jt. Conf. Neural. Netw. 1 (2019).

[6] C, Kim et al., IEEE Trans. Electron Devices 65, 5 (2018).

[7] S. Kheradpisheh et al., Int. J. Neural. Syst. (2020).

Figure 1