bluuebunny/crossref_metadata_2025 huggingface dataset:
Catalytic Activity of Hybrid Metal/Silicon and Metal/Silicon Dioxide Nanocomposites
Authors: Polisski Sergej , Goller Bernhard , Lapkin Alexei , Kovalev Dmitry
Published: October 2008

Here we demonstrate that H-terminated porous silicon (PSi) powders and layers can be utilized as highly efficient reductive templates for noble metal salts. The metal salt reduction results in a metal nanoparticle (NP) formation in the porous matrix of PSi. Gold NP formation has been monitored in-situ by measuring the plasmon resonance response. Pt NPs, formed in the pores of PSi, were investigated by transmission electron microscopy (TEM) and energy-dispersive X-ray (EDX) analysis. Furthermore, hybrid Pt/PSi nanocomposites exhibit a high catalytic activity for CO oxidation. Some of the samples were oxidized to obtain Pt/PSiOx nanocomposites for comparison of catalytic activity.
Gas Sensing Property of Porous SnO2 Layer Synthesized through Anodic Oxidation
Authors: Jeun Jeong Hoon , Ryu Hyun Sam , Hong Seong-Hyeon
Published: October 2008

SnO2 porous structure was fabricated by anodic oxidation. The Sn coated SiO2/Si wafer was used as an anode and it was anodized in 0.3 M oxalic acid aqueous solution using DC power supply. The phase of formed oxide was rutile and the morphology showed a nano porous structure. The porous SnO2 with nano-channel was obtained at 6V in 0.3 M oxalic acid and the pore diameter was approximately 20 nm. A post annealing was performed at 500 ° for 3 h to enhance the crystallinity. To evaluate the gas sensing properties, a comb like Pt pattern was deposited on the anodized and annealed specimen and its gas sensing properties were measured as a function of gas concentration and working temperature
Porous Silicon/Fe3O4-Nanoparticle Composite and its Magnetic Behaviour
Authors: Granitzer Petra , Rumpf Klemens , Roca Alejandro , Morales Puerto , Poelt Peter
Published: October 2008

Porous silicon (PS) matrices with oriented pores grown perpendicular to the surface are used as template for the incorporation of magnetite nanoparticles. The Fe3O4-particles used for infiltration into the PS-template are coated with oleic acid in a hexane solution and exhibit an average diameter of 9 nm {plus minus}1 nm. The narrow size-distribution and the superparamagnetic behaviour at room temperatre are interesting features of these nanoparticles. Magnetite nanoparticles play a key role in medical applications but also the magnetic properties of such a nanoparticle/PS system are of technical interest due to the transition between superparamagnetic and ferromagnetic behaviour. Temperature dependent magnetization measurements are used to gain information about the magnetic interaction of the particles.
Etching Deep Macropores in n-Type Silicon in Short Times
Authors: Ossei-Wusu Emmanuel , Cojocaru Ala , Carstensen Jürgen , Leisner Malte , Föll Helmut
Published: October 2008

Etching deep macropores into n-type Si was limited for more than 15 years to maximal depth around 500 μm at processing times > 10 hrs, severely impeding the commercialization of many applications. It will be shown that substantial progress with respect to depth and speed is possible without losing pore quality if newly designed electrolytes are used in conjunction with in-situ data acquisition and analysis. Some new phenomena are encountered in some regions of the now vastly increased parameter space that will be briefly discussed.
Model for Current Oscillations at the Si/Electrolyte Contact:Extension to Spatial Resolution
Authors: Grzanna Juergen , Notz T. , Lewerenz Hans J.
Published: October 2008

A morphological model is given for the anodic oxidation of n-type silicon in fluoride containing solution in a potentiostatic arrangement. An earlier introduced macroscopic version of the model is extended from temporal to spatio-temporal resolution using a cellular automate. The prediction of the macroscopic model that lattice mismatch between silicon and its oxide leads to stress and stress leads to two types of oxides in the case of photocurrent oscillation is approved by the cellular automate model. The oxide types differ in stability against the etching process. Both oxide types are arranged in clusters which alternate at the electrode surface. Each cluster is in the size of 80-100 nm.
OCP Oscillation of Silicon in Solution Containing Oxidizing Species
Authors: Ogata Y. H. , Itoh Takamasa , Chourou Mohamed Lassaad , Fukami Kazuhiro , Sakka Tetsuo
Published: October 2008

Oscillation behavior of p-type Si(100) was investigated in an aqueous solution containing HF and oxidizing agents at its open-circuit state. The presence of Cu2+ ions gives a regular and sustained oscillation of the open-circuit potential (OCP). Change in the solution pH does not affect the amplitude noticeably, but the period becomes long at low pH. The OCP oscillation appears also in a solution containing Ag+ while the condition is limited and the amplitude is small compared with the Cu2+ system. On the other hand, no oscillation is observed in a solution containing NO3-, the redox potential is high enough to oxidize the Si surface. These results indicate that the oscillation takes place at a surface spatially confined with deposits. A model for the OCP oscillation of Si is proposed based on local and inhomogeneous oxide formation at a Si surface in a confined space and its repair.
Enhanced Controllability of Periodic Silicon Nanostructures by Magnetic Field Anodization
Authors: Gelloz Bernard , Masunaga Masahiro , Shirasawa Takuya , Mentek Romain , Ohta Toshiyuki , Koshida Nobuyoshi
Published: October 2008

The presence of a magnetic field during anodization of Si in HF solution can drastically influence the resulting porous Si morphology. The effect of the strength of the magnetic field was investigated. The magnetic field enables the realization of non-percolating straight pores of diameters from 100 nm with n+-type Si to several micrometers for p-type Si, through depths as large as 100 μm, without any lithographic or pore initiation process. There is a clear enhancement of the pores aspect ratio when increasing the magnetic field strength, which enhances the collection of holes at the pore tips with respect to lateral pore walls. Thick, well-defined free-standing membranes can also been fabricated for applications such as bio-scaffold and filters.
Electrochemical Formation of Self-Positioned Nano-Sized Pores on Oxidized Porous Silicon Substrate
Authors: Ge Daohan , Jiao Jiwei , Bao Xiaoqing , Zhang Sheng , Zhou Ping , Wang Yuelin , Feng Songlin
Published: October 2008

This paper reports on recent improvements in the fabrication of self-positioned nano-sized pore array with a dimension of around 200 nm on the partly oxidized porous silicon (POPS) substrate. The fabrication process is based on photoelectrochemical etching, combined with steps of oxidation, CMP and KOH etching. Moreover, the dependency of a single pore diameter on the configuration of the partly oxidized micro-trenches with varied widths has been investigated. A simple model, based on the depletion effect, is proposed to explain the experimental phenomena.
Stabilization of Porous Silicon Free-Standing Coupled Optical Microcavities by Surface Chemical Modification
Authors: Gelloz Bernard , Murata Kouichiro , Ohta Toshiyuki , Ghulinyan Mher , Pavesi Lorenzo , Lockwood D. J. , Koshida Nobuyoshi
Published: October 2008

As-anodized porous Si photonic structures experience drifts of their optical properties upon prolonged exposure to air due to spontaneous oxidation of the metastabe Si-H bonds terminating the pores surface. This is a critical limitation in the case of optical coupled optical microcavities, where both long term usage and stable nanometer resolution are required. With a view to stabilizing these structures, the surface of porous Si was chemically modified by hydrosilylation. The resulting surfaces are protected by stable Si-C bonds and by a steric hinderance mechanism. The modified photonic structures are stable for many months.
Integration and Applications of Electrochemically-Etched Silicon Nanowires
Authors: Xu Wanli , Flake J. C.
Published: October 2008

Silicon nanowires (SiNW) are fabricated through electroless etching of single crystal silicon. The nanowires are separated from substrate, deposited onto electrodes and annealed. Nanowire silicidation methods and analysis of silicides including electrical characterization, SEM, TEM and sputter XPS, and XANES are considered.
Formation of Si Nanowire Arrays by Metal-Assisted Chemical Etching
Authors: Benoit-Moez Charlotte , Bastide Stéphane , Levy-Clement Claude
Published: October 2008

Formation of Si nanowire (SiNW) arrays using top-down methods based on metal-assisted chemical etching of Si is reported. Three different approaches were tested: i) a two-step process consisting in the electroless deposition of Ag nanoparticles followed by HF/H2O2 etching; ii) simultaneous electroless Ag deposition and etching in HF and highly concentrated AgNO3; iii) a multi-step process using an Au replica mask obtained by Au evaporation on Si samples covered with polystyrene spheres, followed by HF/H2O2 etching. The morphologies of the Si structures obtained in each case are discussed in terms of the influence of different parameters. The third approach led to well controlled etching. Depending on the polystyrene sphere size, Si pillars 1 µm or SiNWs 200 nm in diameter could be obtained.
GaAs Microarrays by Noble-Metal Assisted Chemical Etching
Authors: Yasukawa Yukiko , Asoh Hidetaka , Ono Sachiko
Published: October 2008

Microarrays of n-GaAs were fabricated for both (100) and (111) by colloidal crystal templating, ion sputtering and chemical etching using nanosized Au particles as the etching catalyst. Since self-organized polystyrene spheres were used as a mask, Au particles were selectively deposited at sites resulting in the formation of Au honeycomb pattern on GaAs. Microsized GaAs column arrays were achieved by chemical etching of GaAs, where the honeycomb-patterned Au metals were deposited. Although ordered column structures were obtained for both planes, different anisotropic etching patterns were observed by Au-assisted chemical etching between n-GaAs (100) and (111). The crystal-face orientation strongly affects the etching morphology and the rate of metal-assisted chemical etching.
High Catalytic Activity of Palladium for Metal-Enhanced Hydrofluoric Acid Etching of Silicon
Authors: Yae Shinji , Tashiro Masayuki , Hirano Tatsuya , Abe Makoto , Fukumuro Naoki , Matsuda Hitoshi
Published: October 2008

Metal-enhanced HF etching of Si is an electroless method to produce porous Si. Such etching generally uses not only metal-modified Si but also an oxidizing agent, such as hydrogen peroxide. Pd exhibits high activity for enhancing the HF etching of Si without an oxidizing agent, even under dissolved oxygen free and dark conditions. Electrolessly deposited Pd particles on n-Si enhance the HF etching of Si, but produce no porous layer. Patterned Pd films localize the etching under and the boundary of the Pd deposited areas, and thus Pd can produce a micro-etch pattern on Si with simple immersion in the HF solution. This etching reaction is explained by electron injection into the conduction band of Si due to Pd-enhanced anodic oxidization of Si with water.
Macropore Formation in Prepatterned p-type Silicon
Authors: Kim Jae Hyun , Kim K Phil , Seo Hong-Seok , Lyu Hong-Keun , Woo Sung-Ho , Lee Jung Ho
Published: October 2008

The formation of ordered macropores in a prepatterned p-type silicon wafer by electrochemical anodization in HF:H2O:DMSO (dimethyl sulfoxide) and HF:DMSO solutions was investigated. The pore wall thickness in the solutions was found to be reduced with increasing current density. The pore growth rate was compared using two kinds of etch pit; one is for 2 um lattice spacing, the other is for 5 um. The growth rate of the macropores for 2 um size revealed a saturation behavior, while that of 5 um corresponded to a linear increase in the same range of current density. The big difference in morphologies of macropores between HF:H2O:DMSO and HF:DMSO solutions was accounted for based on the chemical nature of DMSO.
Porous Multilayers as a Dielectric Host for Photons Manipulation
Authors: Ghulinyan Mher , Pavesi Lorenzo
Published: October 2008

Porous silicon multilayers are a suitable tool to modify the photon mode density in one dimension. In this way, new phenomena such as photon Bloch oscillations, Zener tunneling of light, slow light, photon Anderson localization, necklace light states and optical bistability may occur. A review of these phenomena and their actual demonstration is here reported.
Electrical Properties of Meso-Porous Silicon: From a Surface Effect to Coulomb Blockade and More
Authors: Boarino Luca , Borini Stefano , Amato Giampiero
Published: October 2008

Since the Volker Lehmann's paper "Resistivity of Porous Silicon: a surface effect" published in 1995, a great deal of effort has been produced in understanding the basic mechanisms ruling the electron transport in Si mesostructures and how these phenomena are affected by external environment. After more than 10 years, new experimental evidences and physical insights have been obtained, like gas sensitivity, chemisorptions phenomena, Coulomb blockade and glassy dynamics at room temperature, but reading that former paper, the feeling of an extraordinary comprehension and intuition of the physical phenomena occurring in this fascinating material is continuously accompanying the reader. A review of these major results in studying electronic transport in mesoporous silicon will be reported, starting from the still valid intuitions of Volker Lehmann in his paper.
Efficient Solar Cell Structure Prepared by Electrodeposition into Oscillation-Induced Nanoporous Silicon Oxide
Authors: Lewerenz Hans J. , Stempel Thomas
Published: October 2008

A silicon-based nanoemitter solar cell is described that operates in the photovoltaic mode of a photoelectrochemical solar cell (PECS). Low temperature scalable processing uses current oscillation-induced nanoporous oxide matrices as templates for noble metal nanocontacts prepared by electrodeposition. Light-to-electricity conversion efficiencies of h > 10% have been obtained if the nanopores in the passivating oxide layer are deepened into the silicon substrate by electro-etching in alkaline solution. In synchrotron radiation photoelectron spectroscopy (SRPES) investigations on model surfaces that were H-terminated, oxide formation during Pt deposition is observed while Pt is present in its elemental state. The influence of the oxidic film that is also present underneath the Pt nanoislands on the electronic properties of the cell is discussed and optimization routes for increased efficiencies are outlined.
Preferential <111>A Pore Propagation Mechanism in n-InP Anodized in KOH
Authors: Lynch R. , O'Dwyer Colm , Quill Nathan , Nakahara Shohei , Newcomb Simon B. , Buckley D. N.
Published: October 2008

This paper describes the formation of pores during the anodization of n-InP in aqueous KOH. The pores propagate preferentially along the <111>A crystallographic directions and form truncated tetrahedral domains. A model is presented that explains preferential <111>A pore propagation and the uniform diameters of pores. The model outlines how pores can deviate from the <111>A directions and from their characteristic diameters. It also details the effect of variation of carrier concentration on the dimensions of the porous structures.
Complete Removal of Irregular Top Layer for Sensor Applications of InP Porous Nanostructures
Authors: Sato Taketomo , Mizohata Akinori , Yoshizawa Naoki , Hashizume T.
Published: October 2008

The photo-electrochemical (PEC) process was developed to remove the irregular top layer of InP porous nanostructures for the application to amperometric chemical sensors. The PEC etching rate of the pore surface was associated with their structural properties, resulting in the complete removal of the irregular layer by monitoring and controlling the anodic photo-currents. The porous electrode prepared by PEC process gave higher sensitivity for detecting H2O2 due to the enlarged openings of all pores with complete removal of irregular top layer.
Growth of a Porous Layer on InP in Liquid Ammonia: A Specific Interfacial Behavior
Authors: Eb Alexandra , Gonçalves Anne Marie , Mathieu Charles , Etcheberry Arnaud
Published: October 2008

InP in liquid ammonia presents specific pore growth. The first stages of this process are studied with electrical, XPS and microscopy characterizations. We points out that an overlayer associated to typical phosphorus-nitrogen chemistry seem to acts as the precursor stage before the porosification starts.
Importance of Wafer Bonding for the Future Hyper-Miniaturized CMOS Devices
Authors: Okamoto Kazuya
Published: October 2008

Miniaturization technology based on Dennard's rule for CMOS devices has been progressing technically over time. Lithography has made amazing progress so far, achieving high resolution at 65nm-L/S or below using 193nm-UV light. However, there is a low probability that this scenario of producing ever-finer feature geometry will continue, because resolution capabilities will possibly reach a critical limit due to CMOS performance threshold and chip economy. Therefore, to assure continued performance improvements and to create added-value by miniaturization for the future devices, a new 3 dimensional (3D) monolithic integration should acquire increased importance. Especially, "precise" wafer-to-wafer (W2W) bonding using through-Si-via interconnect (TSV) would be an integral part of this technology. This paper describes characteristics of every W2W bonding process including the TSV formation method. Furthermore, key issues of the precise wafer bonding & inspection methodology to meet higher alignment accuracy will be discussed.
Copper Direct Bonding Characterization and its Interests for 3D Integration Circuits
Authors: Gueguen Pierric , Di Cioccio Léa , Gergaud Patrice , Rivoire Maurice , Scevola Daniel , Zussy Marc , Charvet Anne Marie , Bally Laurent , Lafond Dominique , Clavelier Laurent
Published: October 2008

3D technology will be the next step for the development of microelectronic devices. Vertical interconnection is one of the challenging issue. Metal bonding might be one of the possible technique to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure and ambient air is investigated. At room temperature, a 2.8 J/m2 bonding toughness is achieved. EELS spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions versus post bonding annealing are presented with TEM and XRD analyses. The ohmic behavior of the bonding is highlighted.
3D Stacking of Multiple Silicon Plates using Direct Wafer Bonding
Authors: Gunther Ramses , Ackermann Marcello , Partapsing Rakesh , Collon Maximilien , Wallace Kotska
Published: October 2008

In this paper we present a method to stack several tens of structured and curved silicon plates by direct wafer bonding into large geometries. We have developed a number of new processes and methods for the manufacturing and assembly of structured silicon plates. In this paper we will report on all of the process steps, like structuring of the wafers (grooving and dicing), surface protection, artificial wedging of the plates, metallic coating and detection and removal of sub-micrometer particles on ribbed surfaces. In addition we will describe methods to pre-bend plates, to align and to stack them. This also includes new optical and interferometric metrology systems that are used to perform inspection of the bonded surfaces. Furthermore, we report to have stacked 35 structured and curved silicon plates on top of each other. Such a stack is stiff enough to maintain its shape.
Silicon Wafer Bonding for Use in Fuel Cells
Authors: Petrovic Slobodan , McGinnis Bryan
Published: October 2008

Wafer bonding can be adapted from the silicon processing industry and applied to assembly of fuel cells, which traditionally suffer from low manufacturability readiness and lack of high-volume production methods. The requirements for the bond when used in fuel cells are different than for typical electronic products and new evaluation standards have to be developed. In response, a comprehensive methodology has been proposed for assessing suitability of wafer bonding techniques for use in silicon-based fuel cell. The first part of this protocol, which includes electrical measurements of the quality of the wafer bond using Electrochemical Impedance Spectroscopy, is presented here, while the complete testing methodology will be reported elsewhere. Five different bonding compounds were tested at room temperature and atmospheric relative humidity conditions. Subsequent testing steps will examine behavior of these bonds under typical fuel cell voltage, elevated temperature and pressure, high relative humidity, and presence of electrolyte.
Developments Trends in the Field of Wafer Bonding Technologies
Authors: Wiemer Maik , Haubold Marco , Jia Chenping , Wuensch Dirk , Froemel Joerg , Gessner Thomas
Published: October 2008

One well established technology for the fabrication of 3D devices in microelectronics and micro system technology is wafer bonding. After an overview about the existing bonding techniques the presentation will address aspects like bonding with plasma pretreatment to reduce the bond temperature below 200{degree sign}C, use of nanostructures for bonding, metal to metal bonding and integration of new materials to form special SOI substrates.
Microring Resonators Fabrication by BCB Adhesive Wafer Bonding
Authors: Dragoi Viorel , Alexe Marin , Hamacher Michael , Heidrich Helmut
Published: October 2008

Microring resonator devices are attractive for Wavelength Division Multiplexing (WDM) applications because of their inherent spectral characteristics. GaInAsP/InP microring resonator devices were fabricated using a vertical integration concept based on GaInAsP/InP-on-GaAs wafer-to-wafer bonding. Different materials and wafer bonding processes were tested. The successful fabrication process was using BCB wafer-to-wafer adhesive bonding.
Bump-less Wafer Level Bonding Experiment for Vertical Integration MEMS Device
Authors: Moriguchi Makoto , Shiozaki Masayoshi , Sasaki Sho , Oba Masatoshi
Published: October 2008

In the future, it is desired that high performance sensing module in small volume is realized. However, conventional MEMS (Micro Electro Mechanical Systems) packaging technology is becoming difficult to meet its desire (Especially Bulk MEMS). Small and package-less 3D sensing module, which consist of MEMS and IC chips bonded by SAB (Surface Activated Bonding) solves this problem (Fig. 1). But we have many technological opportunities in small and package-less 3D sensing module; Low damage bonding, electrical contact, and bonding alignment. This paper reports 'Bump-less wafer level bonding' which is needed for vertical integration MEMS device and the 3 wafer bonding experiment results of bonding strength, electrical contact, and alignment.
Suspended Si Microstructures with Rounded Concave and Sharp Convex Corners Using Wafer Bonding and Wet Anisotropic Etching
Authors: Pal Prem , Sato Kazuo , Shikida Mitsuhiro
Published: October 2008

In this paper, we report the fabrication method of suspended silicon microstructures with rounded concave and sharp convex corners of required thickness over controlled etch depth cavities. The fabrication process uses wafer bonding and wet anisotropic etching in pure and surfactant added TMAH. In order to reduce the undercutting at rounded concave and sharp convex corners, various types of non-ionic surfactants namely NC-200, Triton-X-100 and polyethylene glycol (PEG) with very small amount (0.1% by volume) were studied in 25 wt% TMAH solution. The non-ionic surfactants were preferred to preserve the CMOS compatibility of TMAH solution. The aforementioned surfactants were found to be very effective in terms of reducing the undercutting at both types of corners.
Permanent Bonding with Polymers
Authors: Farrens Shari , Sood Sumant , Ishida Hiroyuki
Published: October 2008

Many packaging applications for MEMS devices are using a variety of polymer materials. Polymer bonding has many advantages including a high tolerance to surface topography and particles, low cost, and shorter processing times. There are many varieties of polymers to choose from and engineered interfaces can be designed. The processing of the polymer must be reviewed from deposition to final testing to ensure that all functional requirements are met.
Optical Isolator with Si Guiding Layer Fabricated by UV-Activated Bonding
Authors: Yokoi Hideki , Sasaki Kotaro
Published: October 2008

An interferometric optical isolator, with a Si guiding layer, employing a nonreciprocal phase shift has been studied. The optical isolator is comprised of a magneto-optic waveguide with a magnetic garnet / Si / SiO2 structure, which is fabricated by wafer bonding technique. The nonreciprocal phase shift was calculated for magneto-optic waveguides with various layer structures. Wafer bonding between a garnet crystal and Si was also investigated.
Fabrication and Characterization of High Resistivity SOI Wafers for RF Applications
Authors: Lederer Dimitri C. , Roda Neve Cesar , Olbrechts Benoit , Raskin Jean-Pierre
Published: October 2008

This paper provides an overview of the issues associated with parasitic surface conduction (PSC) in oxidized high resistivity (HR) Si wafers, such as HR SOI, in which PSC is related to the presence of free carriers at the substrate surface. Most of these issues are suppressed when the substrate surface is passivated with a trap-rich layer of material, such as polysilicon. A technique to fabricate substrate-passivated HR SOI wafer is presented, where the wafers are obtained by bonding a polysilicon-passivated HR Si substrate with an oxidized donor substrate. Preliminary encouraging bonding test results are presented.
Plasma-Display-Panel Drivers as a Volume Application of Thick SOI Technology
Authors: Fujihira Tatsuhiko , Sumida Hitoshi , Kumada Keishirou
Published: October 2008

Thick SOI technology has achieved commercial success in plasma-display-panel (PDP) driver ICs. The present paper will give a review on the technology trend of PDP driver ICs and an outlook of the application status of thick SOI technology to PDP driver ICs. Thick SOI technology brings such merits as high device packing density, complete isolation and the integration of high-voltage and high-current devices to power and/or high-voltage ICs. PDP driver ICs need thick SOI, because it is possible to achieve the highest IC performances including cost by utilizing these merits.
Thick Bonded Silicon-On-Insulator Wafer with Polysilicon Interlayer for Gettering of Metal Impurities
Authors: Hintsala Jouko , Mäkinen Jari , Whiston Shay , Daly Paul , Nunan Kieran , Sawyer W.
Published: October 2008

A new technique for extrinsic gettering of transition-metal impurities in thick bonded SOI (BSOI) wafers is presented. Technique is based on adding a thin polycrystalline silicon layer between the active layer and buried oxide by means of direct wafer bonding. Gettering efficiencies of over 98 % of iron in active layer were demonstrated even after a high temperature heat treatment. Testing of wafers in CMOS processes showed a clear improvement of the gate oxide integrity, even approaching that of conventional bulk silicon wafers. Poly-Si interlayer showed no measurable effects on critical BSOI characteristics such as interfacial voids, bond strength, active layer thickness uniformity or sacrificial oxide etching. The residual stress was also very low. The results suggest that the thin poly-Si layer has minimal effect on fabrication of the MEMS elements.
Partial SOI Structure by Wafer Direct Bonding through Amorphous Layer
Authors: Himi Hiroaki , Fujino Seiji
Published: October 2008

A partial SOI structure suitable for power IC is taken up and as the fabrication method the wafer direct bonding using the intermediate poly-crystalline silicon layer is proposed. Through the amorphous layer formed on the bonding surface of the deposited and planarized poly-crystalline silicon by silicon ion implantation, the void-less interface has been achieved and an ideal partial SOI structure have become possible.
Method of Strengthening Safe Operating Area for SOI Lateral Insulated Gate Bipolar Transistor
Authors: Mizushima Tomonori , Lu David H.
Published: October 2008

A new SOI-LIGBT structure with multiple base depths is proposed and experimentally verified to address the imbalanced influence of the depleted-layer to the perimeter and the inner cells in device layout. The new devices are implemented by re-integrating the existing process steps. Compared with conventional structure with only single base depth, the new devices experimentally posses a 1.3 times stronger short-circuit safe operating area (SCSOA), an 18V higher forward-biased SOA, and a 15V higher off-state breakdown voltage. Adverse impact on current capability is barely observed.
III-V and III-Nitride Engineered Heterostructures: Wafer Bonding, Ion Slicing, and More
Authors: Moutanabbir Ousssama , Christiansen Silke , Senz Stephan , Scholz Roland , Petzold Matthias , Gösele Ullrich
Published: October 2008

Wafer bonding in combination with ion slicing emerges as a nonpareil strategy by which bulk quality thin layers can be transferred onto different host materials. In the first part of this paper a successful application of this process to transfer 4-inch InP layer onto Si wafer is demonstrated. The use of SiO2 interlayer makes the fabricated heterostructures compatible with high temperature processes. In the second section we address the applicability of this process for 2-inch freestanding GaN wafers which exhibit a strong post-implantation bowing making any bonding exceedingly difficult. We describe the origin of this bow enhancement and present a novel strategy to manipulate it. Based on our approach a successful bonding of 2-inch free-standing GaN into sapphire handle wafers is achieved. Finally, by using a variety of experimental techniques, we explore the atomic processes and structural transformations involved in H ion-induced GaN splitting. A plausible mechanistic picture is presented.
Cleave Engineered Layer Transfer using Porous Silicon
Authors: Joshi Monali , Hayashi Sumiko , Hu Sijiang , Goorsky M.
Published: October 2008

A Cleave-Engineered Layer Transfer (CELT) substrate was fabricated consisting of a thin InP template layer transferred, via wafer bonding and hydrogen exfoliation, onto a silicon handle wafer with a porous layer at its surface. The mechanically weak porous silicon layer enables transfer of subsequent epitaxial growth and device fabrication on the template layer by initiating cleavage through the porous layer. Structural and mechanical property changes in the porous silicon layer after various processing conditions were studied. Characterization included atomic force microscopy, high-resolution x-ray diffraction, scanning electron microscopy, and nanoindentation measurements. Atomic force microscopy and transmission electron microscopy show the template layer has high surface- and crystalline- quality for subsequent epitaxial deposition. Layer transfer capability was demonstrated on a similar structure by fracture through the porous layer.
Bonding of Elastically Strain-Relaxed GaAs/InGaAs/GaAs Heterostructures to GaAs(001)
Authors: Owen David , Lackner David , Pitts Oliver , Watkins Simon , Mooney Patricia
Published: October 2008

Bonding of elastically strain-relaxed GaAs/InGaAs/GaAs heterostructures has been achieved on GaAs(001) substrates by the method of in-place bonding. Pseudomorphic heterostructures were patterned and a sacrificial AlAs layer was removed by selective etching. As etching proceeds and the GaAs/InGaAs/GaAs structure is released from the substrate, elastic strain relaxation occurs and the strain-relaxed structures are weakly bonded in-place to the substrate. The bond between the strain-relaxed structure and the substrate was then strengthened by annealing under conditions similar to those used for whole wafer bonding of GaAs. The degree of strain relaxation of the InGaAs layer is determined by the relative thickness of the GaAs and InGaAs layers. The increase in the in-plane lattice parameter of these bonded GaAs/InGaAs/GaAs structures is 0.3-0.4%.
Chemical Mechanical Polishing of Exfoliated III-V Layers
Authors: Hayashi Sumiko , Joshi Monali , Goorsky M.
Published: October 2008

The chemical mechanical polishing of III-V materials including GaAs, InP, InAs, and GaSb is investigated with sodium hypochlorite and citric acid solutions. It is found that the surfaces can be polished to below 0.5 nm RMS surface roughness without the induction of crystalline damage using similar abrasive-free polishing solutions for all the materials with controlled polishing rates of 10 nm / min which is important for touch polishing of exfoliated III-V layers. The optimal composition of the slurry is adjusted for the particular material. A balance between reduced sub-surface mechanical damage and smooth surface morphology is obtained by adjusting the amount of citric acid. However, the damage-free planarization in these cases may be aided by an oxide formation as predicted by Pourbaix diagrams. Additionally, triple axis x-ray diffraction is found to be an extremely sensitive, non-destructive method for evaluating damage induced by the CMP process.
Strained Silicon on Wafer Level by Waferbonding: Materials Processing, Strain Measurements and Strain Relaxation
Authors: Reiche Manfred , Moutanabbir Ousssama , Himcinschi Cameliu , Christiansen Silke , Erfurth Winfried , Gösele Ullrich , Mantl Siegfried , Buca Dan , Zhao Q. T. , Loo Roger , Nguyen D. , Muster F. , Petzold Matthias
Published: October 2008

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing of thin silicon layers on SiGe buffers and their transfer to oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafers characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance.
Fabricating Strained Silicon Substrates Using Mechanical Deformation during Wafer Bonding
Authors: Turner Kevin T.
Published: October 2008

Mechanical straining during wafer bonding combined with thinning has recently been used to fabricate substrates with tensile and compressive uniaxial strained silicon layers. Mechanics analyses are presented here that allow for a better understanding of this fabrication process as well quantitative prediction of the strain in the final substrates. The analysis, results, and a comparison to reported experimental data are presented.
Strain Relaxation in Patterned Strained Silicon-on-Insulator by Raman Spectroscopy
Authors: Gu Diefeng , Baumgart H. , Zhu Mingyao , Celler George K.
Published: October 2008

Strained Silicon-on-Insulator (sSOI) wafers with various strained-Si layer thicknesses (15, 70 and 100 nm) were fabricated by the Smart Cut{trade mark, serif} technology. The sSOI layers were patterned into isolated sSOI device islands by electron beam lithography (EBL) followed by wet etching. The strain relaxation by film patterning and high temperature annealing is maximized in the absence of capping layers or any other precautions. The strain relaxation after patterning and annealing was measured by Raman Spectroscopy. No strain relaxation in un-patterned areas could be detected and the strain relaxation of the patterned sSOI device islands occurred mainly from the edges of the device islands. It was also noticed that strain relaxation increases as the sSi layer thickness increases. The majority of strain was maintained for 15 nm sSOI film thickness after patterning and annealing at 900 ºC.
Fundamentals of Wafer Bonding for SOI: From Physical Mechanisms Towards Advanced Modeling
Authors: Radu Ionut , Boussagol Alice , Barthelemy Alexandre , Vincent Sebastien
Published: October 2008

The wafer bonding has been established as a key process used for the fabrication of silicon-on-insulator (SOI) substrates. In the present paper an overview of the fundamental aspects involved in the wafer bonding process is presented. The mechanisms of the silicon and silicon oxide bonding are discussed with an emphasis on the phenomenological models developed in case of SOI bonding. Interactions between the mechanical adhesion and the dynamics of the interface chemistry and their impact on the bonding modeling are also discussed. One of the main challenges today is the validation of existing models and the comparison of physical measurements with the advanced modeling results.
Effect of Pre-bonding Thermal Treatment on the Bonding Interface Evolution in Direct Si-Si Hydrophilic Wafer Bonding
Authors: Ventosa Caroline , Rieutord François , Libralesso Laure , Fournel Frank , Morales Christophe , Moriceau H.
Published: October 2008

The effect of annealing prior to Silicon-Silicon direct bonding is investigated. It is shown that this thermal treatment densifies and increases the thickness of the native oxide, which becomes essentially water-tight. Hence, the evolution of the bonding interface upon post-bonding annealing is significantly altered.
Kinetics of Silanol Condensation for Low-Temperature Direct Bonding
Authors: Eichler Marko , Michel Benedikt , Thomas Michael , Klages Claus-Peter
Published: October 2008

This paper presents first results of fracture surface energies measurements performed in-situ during annealing of silicon wafers. The effect of wafer conditioning by atmospheric-pressure plasmas and subsequent chemical pretreatments was investigated. High surface energies are obtained at low annealing temperatures by plasma-treatment in oxygen and nitrogen mixtures without any post-treatment. The increase of surface energy during annealing of oxygen-plasma treated wafers is considerably accelerated by post-treatment with gaseous or aqueous ammonia. Aside from a catalytic effect of ammonia on siloxane formation, cationic bridging of bonding surfaces by ammonium must also be considered at low annealing temperatures.
Oxide-Free Silicon to Silicon Carbide Heterobond
Authors: Li Ling-Guang , Vallin Örjan , Lu Jun , Smith Ulf , Norström Hans , Olsson Jörgen
Published: October 2008

Thin crystalline device layers of Si were bonded to Si-faced SiC wafers, with either a chemical or a thermal oxide interface layer. The interface thermal oxide was successfully removed by oxygen out-diffusion for 2.5 h in an Ar atmosphere at 1250 oC. XTEM micrographs showed that an abrupt transition between Si and SiC with complete removal of the interlayer oxide had been obtained. Stress generated during the cool-down process after oxygen out-diffusion was shown to be compressive. IR imaging and an optical microscopy verified that no cracks occurred during cool-down.
Weakening of Hardness and Modulus of the Si Lattice by Hydrogen Implantation for Layer Transfer in Wafer Bonding Technology
Authors: Gu Diefeng , Baumgart H. , Bourdelle Konstantin , Celler George K. , Elmustafa Abdelmageed
Published: October 2008

We studied the effect of H implantation on the mechanical properties of Si (001). The hardness and modulus of H implanted Si samples were measured by nanoindentation technique before and after thermal annealing. A significant weakening of the hardness of the single crystalline Si lattice in the H implantation-induced damage zone following annealing was observed. The majority of extended defects, i.e. platelets and microcracks, developed during annealing were parallel to the Si surface. The relationship between the morphology of the damage zone and the drop in hardness and modulus is discussed.
MOS Capacitor Evaluation of Deep States at the Interfacial Grain Boundary in (110/100) Bonded Silicon
Authors: Yu Liya , Lu Jinggang , Wagener Magnus , Yu Xuegong , Rozgonyi George
Published: October 2008

Three different characterization structures of MOS capacitor: Homo orientation, Hybrid orientation and hybrid orientation with shallow grain boundary were applied to evaluate the deep states at (110/100) grain boundary. With multiple frequency C-V and G-V measurements from our unique HOMO and HOT structures, a complex equivalent circuit model of MOS capacitor on bonded wafer was proposed and fitted. With this non-destructive characterization approach, charge density at deep grain boundary became accessible. Moreover, the Continuum of interface trap density at grain boundary, ranged from 0.3 eV below mid-gap to 0.16 eV above mid-gap was completed by applying designed HOT MOS capacitor with shallow grain boundary. This accomplishment is leading us toward further studies on deep state of grain boundaries playing key roles in real device.
Acoustic Characterization of Bonded Wafers
Authors: Sood Sumant , Adams Tom , Thomas Ray
Published: October 2008

Wafer-to-wafer bonding methods provide hermetic packages for hundreds of devices in a single processing step. Once the wafers have been bonded, most defects are no longer visible to the naked eye but may be responsible for die failures. Detection of internal defects in bonded wafer pairs is vital to achieving anticipated yield and long-term device reliability of packaged MEMS devices. Acoustic micro imaging provides a nondestructive technique for detecting and analyzing these defects and is an essential component of process development and root cause analysis. In this paper, we discuss and analyze acoustic imaging results of wafer pairs bonded using various bonding techniques such as silicon direct, eutectic, glass-frit, and thermal compression bonding.
Electrical Properties of the Bonding Interface in a (110)/(100) Direct-Silicon-Bonded (DSB) Wafer
Authors: Lu Jinggang , Park Yongkook , Yu Xuegong , Rozgonyi George
Published: October 2008

In this article, the electrical activity of an interfacial grain boundary in a Direct-Silicon-Bonded wafer was examined by C-V and capacitance transient techniques using Al Schottky diodes. The samples consisted a 2.3 μm thick (110) Si layer on a p-type (100) Si substrate produced by hydrophilic wafer bonding, cleavage, and epi-thickening. Effects of Fe contamination and hydrogenation on the boundary's electrical properties were also examined. GB states below but close to the charge neutral level were studied. It was found that for the relatively clean interfacial bonding GB, the density of GB states (NT) is ~6x1012 eV-1cm-2, and the charge neutral level is at ~0.53 eV from the valance band. NT increased to over 2x1013 eV-1cm-2 after Fe contamination, which was reduced to ~1x1013 eV-1cm-2 after a hydrogenation treatment. The charge neutral level, which shifted towards the conduction band after Fe contamination, was reversed after hydrogenation. The electron emission rate from the GB donor states was found to be about two orders of magnitude larger than the corresponding hole emission rate.
Direct Bonding of Oxidized Cavity Wafers
Authors: Palokangas Martti O. , Dekker James , Henttinen Kimmo , Mäkinen Jari
Published: October 2008

SOI wafers with buried cavities can be used in MEMS fabrication to give more freedom in design and to simplify the process. Sometimes an etch stop layer is needed when DRIE is used to release the MEMS structures in order to prevent etching from continuing at the bottom of the cavity. Thermal oxidation of the cavity wafer as a method for forming an etch stop layer was studied. It was found that oxidation parameters such as temperature and thickness affect the formation of dislocations which in turn may cause voids in bonding. Higher oxidation temperature and thicker oxide were found to yield better bonding results. Patterns and geometry of etched features also play a role.
The Concealed Blister Test: An Implementable Test Method for a Non-Destructive Strength-Characterization of Full-Wafer-Bonds
Authors: Rabold Martin , Busch David , Ramachandran Senthil , Goldschmidtboeing Frank , Woias Peter
Published: October 2008

This article presents an on-wafer implementable test method for a non-destructive strength-characterization of full-wafer-bonds. The test is based on a modification of the common destructive blister test where, in addition, a "sacrificial bond" is implemented. During the test, a pressure ramp is applied onto the bond interface and an internal crack is generated at the "sacrificial bond" only. The crack can be detected and the corresponding pressure can be measured. An analytical model was set up and numerical simulations were carried out to enhance the model for small structures with large thickness-to-length ratios. The test handling was automated to be used within bulk fabrication. For the comparison with other test methods, the measurement uncertainty was determined. Finally, different samples were characterized and the result was compared to established methods.
Low Temperature Wafer Bonding
Authors: Fournel Frank , Moriceau H. , Ventosa Caroline , Libralesso Laure , Le Tiec Yannick , Signamarcheix Thomas , Rieutord François
Published: October 2008

Low temperature wafer bonding is requested in many applications. Most of them involve silicon or silicon dioxide bonding interfaces. Studying bonding process / mechanism in the low temperature range (<400oC) is therefore very important. But depending on the oxide thickness involved, bonding behaviors are different. In this paper, a quick overview presents the state of the art in silicon oxide or silicon bonding progress mainly focused on the bonding energy and defectivity with only low thermal treatment used after bonding. Specifically for thin oxide layer or silicon direct bonding, the defectivity evolution remains the most important issue. Different bonding mechanisms are proposed in order to understand this behavior. Such an understanding allows us to propose different processes which can minimize or even suppress the bonding defects.
Low Temperture Au-Au Thermal Compression Bonding of Thermally Mismatched Substrates
Authors: Farrens Shari , Sood Sumant
Published: October 2008

One of the limitations in using metal bonding materials for the integration of compound semiconductors and silicon has been controlling the thermal expansion difference. Metal diffusion bonding using copper or gold generally requires annealing temperatures around 400C which is not compatible with heterogeneous materials bonding with large CTE mismatch. However, several processing modifications can be exploited to increase the diffusion rates, reduce annealing temperatures and control stresses in metal diffusion bonded substrates.
Low Temperature Wafer Bonding: Plasma Assisted Silicon Direct Bonding vs. Silicon-Gold Eutectic Bonding
Authors: Rabold Martin , Kuster Holger , Woias Peter , Goldschmidtboeing Frank
Published: October 2008

This paper describes the development of two bonding techniques for structured silicon wafer pairs. The focus was set to low-temperature bonding to make the process compatible to a broad range of applications. First, we present a low temperature plasma-assisted hydrophilic bonding process that can be applied using standard clean room equipment. Unfortunately, direct bonding requires a smooth, undisturbed bonding surface with a roughness in the angstrom regime as a crucial prerequisite. Some complex MEMS process flows are unable to comply with that. Therefore, the second focus was set onto an eutectic silicon-gold wafer bonding process, that has a good tolerance against surface topographies due to the formation of a liquid phase at the bond interface. For surface characterization, contact angle and AFM measurements were carried out, the mechanical characterization of the bond was done by a blister and a tensile test method. Finally, a bonded micro fluidic device is presented.