bluuebunny/crossref_metadata_2025 huggingface dataset:
Ultrafast Nano-Crystalline and Highly-Dispersed-TiO2 (B) /CNF Composites for Negative Electrode of ‘Nanohybrid Capacitor’
Authors: Iwama Etsuro , Abe Masayuki , Furuhashi Takumi , Abe Yuta , Miyamoto Junichi , Naoi Wako , Naoi Katsuhiko
Published: February 2020

We have been applying our original in-situ material processing technology called ‘Ultra-Centrifuging (UC) Treatment’ to prepare a novel ultrafast nano-crystalline Li4Ti5O12 (nc-LTO) /carbon nano fiber (CNF) composite electrode for the generation-II capacitive energy storage device of ‘Nanohybrid Capacitor’ producing more than triple  energy density of a conventional electrochemical capacitor.[1] For the further improvement in the energy density of ‘Nanohybrid Capacitor’, LTO alternatives are needed. Among different candidates, TiO2 (B) possesses several advantages such as its 2-folds theoretical capacity (335 mAh g-1) of LTO (175 mAh g-1) and the comparable redox potential (1.6 V vs. Li/Li+). In addition, TiO2 (B) is an industrially attractive material because of its inexpensive raw materials and its environmentally benign synthesis using only aqueous solution (e.g., water-soluble complexes [2]) without any Li-sources.[2-4] However, TiO2 (B) has intrinsic problems; its low electronic conductivity and Li+ diffusivity due to the b-axis oriented growth of TiO2 (B) [3]. In this report, we successfully synthesized b-axis shortened and hyper-dispersed nc-TiO2 (B)/CNF composites, which has a potential to substitute nc-LTO/CNF as a negative electrode of ‘Nanohybrid capacitor’. Inhibition of b-axis growth and hyper dispersion of TiO2 (B) into the carbon matrix were simultaneously achieved by the UC treatment and the subsequent hydrothermal method [4]. The prepared nc-TiO2/CNF exhibited 236 mAh g-1 (active material) at high rate of 300 C, which even exceeds that of nc-LTO/CNF composites. A significant decrease of peak intensity corresponding to the C-site intercalation around 2 V vs. Li/Li+ indicates that the Li+ was directly accommodated into A1 and A2 site of TiO2 (B) owing to the limitation of b-axis growth. Furthermore, the combined analysis of the N2 adsorption experiment and electochemical characterization suggests that the "dispersibility" of nc-TiO2 (B) on CNF matrix correlates closely with its electrochemical performance.

References

[1] K. Naoi, et al., Energy & Environ. Sci., RSC, 5, (2012) 9363.

[2] a) M. Kobayashi,
et al., Chem. Mater., 19, (2007) 5373.

[3] A. R. Armstrong et al., Chem. Mater., 22, (2010), 6426.

[4] Y. Ren,
et al., Angewandte. Chem. Int. Ed, 51, (2012) 2164.
Cycle Stability of Manganese Dioxide Polymorph Supercapacitors at Elevated Temperature
Authors: Wu Nae-Lih , Pan Hsiao-An , Ghodbane Ouassim , Favier Frederic
Published: February 2020

Electrochemical supercapacitors are of great interest as complementary electrochemical storage devices in the applications that require high power pulses. Many compounds have been investigated as possible supercapacitor materials, and manganese dioxides are certainly among the most attractive candidates. This is mainly due to their low cost, environmental compatibility and appropriate electrochemical performances. The chemistry of MnO2 is abundant with a variety of structural types. In the field of supercapacitors, the structural complexities exhibited by the 1D, 2D or 3D arrangement of MnO2 materials result in various charge-storage performances [1]. We have previously revealed the crystallographic evolution of the MnO2 polymorph supercapacitors taking place during the course of electrochemical charge/discharge [2], pointing out different cell expansion/contraction behaviors pertaining to their crystal structures. In many potential applications, such as electric vehicle and stand-alone renewable energy storage, supercapacitor cells are likely to constantly operate under elevate temperatures. Unfortunately, the high-temperature cycling stabilities of many pseudocapacitve supercapacitors, including MnO2, have essentially not been looked into in the literature.

In this study, the high-temperature (50 oC) electrochemical performances, in particular cycling stability, of supercapacitos made of three different MnO2 polymorphs, including cryptomelane, birnessite and spinel, with aqueous K2SO4 electrolyte were investigated. The samples were subjected to different analyses, including electrochemistry cyclic voltammetry, synchrotron X-ray diffraction, and synchrotron X-ray absorption spectroscopy, in order to reveal the predominant fading mechanisms both at 25 oC and 50 oC. It is shown that for all three polymorphs, the capacitance fading rates at 50 oC are far greater than those at 25 oC. It is further evidenced that their capacitance fading mechanisms at high temperatures are strongly affected by their crystallographic structure and the volumetric variation behavior previously disclosed.

[1] O. Ghodbane, et al. ACS Appl. Mater. 1 (2009) 1130.

[2] O. Ghodbane, et al. J. Power Sources 206 (2012) 454
Double Templates Synthesis of Mesoporous Materials
Authors: Xue Tong , Lee Jong-Min
Published: February 2020

In recent years, synthesis and characterization of ordered nanomaterials with high specific surface area have received increasing interest because of their potential applications in catalysis, selective separation and electrochemical devices such as batteries, fuel cells and supercapacitors. With the development of self-assemble nanotechniques, template synthesis was paid much attention as a new kind of fabricated technology of ordered nanomaterials. The corresponding template can be looked as a nanoscopic reactor for the synthesis of nanoarrays of the desired materials such as metal, metal oxide, non-metal and so on by chemical or physical method. Therefore, structure of mesoporous ordered nanomaterials can be controlled easily and effectively by template synthesis. In the candidates of templates family, porous anodic aluminum oxide template as a hard template and the lyotropic liquid crystalline phase of surfactant as a soft template are most widely used to prepare ordered nanomaterials among the templates to fabricate nanostructure products due to the rich polymorphism and long-range periodicities of porous structures.
Large Amplitude Electrochemical Impedance Spectroscopy for Characterizing the Performance of Electrochemical Capacitors
Authors: Donne Scott W , Dupont Madeleine F
Published: February 2020

Electrochemical impedance spectroscopy (EIS) has been applied to the study of electrodeposited thin films of manganese dioxide as used in electrochemical capacitors. Conventionally EIS employs a relatively small AC excitation signal to provide valuable characterization on electrode features such as the series resistance, charge transfer and double layer charge storage processes, as well as mass transport. The small excitation signal is used so as to focus on the processes occurring within that potential domain allowing for considerable resolution across the full potential window. In this work we have compared the output from this conventional analysis with data from the application of a large amplitude AC excitation signal; i.e., an AC signal that spans the full potential window of the manganese dioxide electrode. Not only does this allow access to electrochemical data representative of the full range of domains within the manganese dioxide structure, it also facilitates performance analysis (determination of specific power and energy data) of the electrode in a much more efficient manner than conventional means.
Highly Luminescent Monolayers Prepared by Molecular Layer Deposition
Authors: Räupke André , Albrecht Fabian , Maibach Julia , Behrendt Andreas , Polywka Andreas , Heiderhoff Ralf , Helzel Jonathan , Rabe Torsten , Johannes Hans-Hermann , Kowalsky Wolfgang , Mankel Eric , Mayer Thomas , Görrn Patrick , Riedl Thomas
Published: February 2020

Molecular layer deposition (MLD) is a solvent-free technique to prepare organic molecular layers with a similar level of control and perfection as that known from inorganic films grown by atomic layer deposition (ALD). In both, MLD and ALD, the deposition process relies on the self-limiting chemical reaction of two precursors on the surface of the substrate. A plethora of MLD processes has been demonstrated.[1] Among them, hybrid materials made from typical metal-organic precursors and alcohols, so called metalcones, have received considerable attention.[2] However, there is only very limited work on MLD of molecular systems which provide functionalities like charge transport or luminescence.[3; 4]

In our work, a general avenue for the controlled preparation of conformal and highly luminescent monolayers of metal chelate complexes is presented, among them tris(8-hydroxyquinolinato)aluminium (Alq3) and bis(8-hydroxyquinoline)zinc (Znq2). Alq3 is an extremely important model compound for organic electronic applications - it has been the electron transporter and luminescent material in the first efficient hetero-structure organic light emitting diode (OLED). The controlled formation of Alq3 or Znq2 monolayers is achieved by functionalization of the substrate with amino groups which serve as initial docking sites for trimethyl aluminum (TMA) or diethyl zinc (DEZ) molecules which datively bind to the amine (see figure).[5] Subsequent exposure to 8-Hydroxyquinoline (8-HQ) results in the self-limiting formation of highly luminescent monolayers on arbitrary surfaces, e.g. curved 3D objects or highly porous silica aerogels. The growth mechanism is studied by in-situ quartz crystal microbalance and ex-situ by highly sensitive (time-resolved) optical absorption/emission spectroscopy and photo-electron spectroscopy. Applications of these thin conformal luminescent layers will be discussed.

[1] S.M. George, B. Yoon, R.A. Hall, A.I. Abdulagatov, Z.M. Gibbs, Y. Lee, D. Seghete, B.H. Lee, in, Atomic Layer Deposition of Nanostructured Materials, Wiley-VCH Verlag GmbH & Co. KGaA, 2011, pp. 83-107.

[2] B.H. Lee, B. Yoon, A.I. Abdulagatov, R.A. Hall, S.M. George, Advanced Functional Materials 23 (2013) 532-546.

[3] O. Nilsen, K.R. Haug, T. Finstad, H. Fjellvåg, Chemical Vapor Deposition 19 (2013) 174-179.

[4] O. Nilsen, K. Klepper, H. Nielsen, H. Fjellvaåg, ECS Transactions 16 (2008) 3-14.

[5] A. Räupke, et al., ACS Applied Materials & Interfaces 6 (2014) 1193-1199.
In-Situ Studies on 2D Materials
Authors: Wallace Robert M
Published: February 2020

The investigation of 2D materials such as graphene and transition metal dichalcogenides for beyond CMOS device concepts emphasizes the importance of surface and interfacial reactions. A fundamental understanding of such reactions in the context of materials integration for devices greatly benefits from in-situ characterization methods where processes such as surface cleaning, film deposition, and annealing can be simulated and subsequently correlated to device behavior. This invited talk will review our recent work on in-situ characterization of 2D materials in the context of device applications and the correlation of the physical and electrical characterization.

This research is supported in part by the STARNet Center for Low Energy Systems Technology, sponsored by the Semiconductor Research Corporation (SRC) and DARPA, the SWAN Center sponsored by the SRC Nanoelectronics Research Initiative and NIST, and by an IBM Faculty Award.
Electrical Properties of High Mobility Ultrathin Amorphous Indium Zinc Oxide Deposited by Atomic Layer Deposition
Authors: Cho Yeong-Ho , Lee Do-Joong , Cho Seong-Yong , Kim Hyun-Mi , Kim Ki-Bum
Published: February 2020

High mobility ultrathin (thinner than 10nm) amorphous Indium Zinc Oxide (a-IZO) films are deposited by Atomic Layer Deposition (ALD). Thickness is set as the main parameter, which is varied between 5nm ~ 50nm by changing the cycle numbers. It is easily predicted that the electrical conductivity shows serious degradation with decreasing thickness of the films because of the increase of the fraction of the surface. However, it is found that a-IZO shows less rapid decrease of the electrical conductivity than crystalline conducting oxides. Aluminum doped Zinc Oxide (AZO) is deposited by ALD to compare the various electrical properties such as mobility, carrier concentration, and resistivity with the a-IZO films. In addition, the resistivity data of Tin doped Indium Oxide (ITO) deposited by ALD is accepted from a literature for more appropriate comparison, because the resistivity of AZO film is one order of magnitude higher than those of IZO and ITO. The results say that with decreasing thickness, the resistivity of a-IZO decreases more slowly than those of crystalline AZO and ITO. As thickness varies from ~50nm to ~10nm, the resistivity of a-IZO goes up from 3.9 ˣ 10-4 Ω cm to 8.2 ˣ 10-4 Ω cm while that of AZO increases from 1.6 ˣ 10-3 Ω cm to 2.0 ˣ 10-2 Ω cm, and that of ITO increases from 3 ˣ 10-4 Ω cm to 9 ˣ 10-4 Ω cm. Moreover, for ~5nm, the resistivity of ITO is about an order of magnitude higher than that of a-IZO, so the conductivity of a-IZO overtakes that of ITO at ~10nm film thickness. This phenomenon is attributed to the electron mobility degradation due to the grain boundary scattering in polycrystalline oxides. As film thickness gets thinner to or below the dimension of grain size, grain size becomes smaller because of the constraint of the dimension in the direction of film normal. Therefore, as thickness varies from ~50nm to ~10nm, the electron mobility of AZO film changes from 11.2 cm2 / V s to 5.6 cm2 / V s while that of a-IZO changes from 52.1 cm2 / V s to 40.6 cm2 / V s. The models of the mobility from grain boundary scattering and surface scattering are explained well in this work, and the absence of grain boundary scattering in amorphous oxides explains the excellent electrical properties of a-IZO.
Absolute Value Determination of Vacancy Concentration in Silicon Crystals Using Low-Temperature Ultrasonic Measurements
Authors: Yamada-Kaneta Hiroshi , Okabe Kazuki , Akatsu Mitsuhiro , Baba Shotaro , Mitsumoto Keisuke , Nemoto Yuichi , Goto Terutaka , Saito Hiroyuki , Kashima Kazuhiko , Saito Yoshihiko
Published: February 2020

For the samples taken from the void region of the CZ silicon crystal having various thermal histories, we performed the low-temperature ultrasonic measurements for the relative magnitude S of the elastic softening, which is proportional to the concentration of the single vacancies [Vs], i.e. [Vs] =g
S. Here, g is the proportionality constant to be determined below. We also carried out void observation by means of the infrared light-scattering tomography, which gave us the information on the concentration and size of the voids (i.e., the size distribution of the voids), from which we calculated the concentration of the vacancies [Vc] consumed for the void formation. From the result of these two experiments, we have found that the formula [Vc]+
a
S = U holds for the samples belonging to the same value of the crystal-growth parameter v/G. Here, a is the obtained numerical value, and U is the obtained function of the crystal-growth parameter. When we reasonably assume that, in the void region, the sum [Vc]+[Vs] is the function of the crystal-growth parameter: [Vc]+[Vs]= W(v/G) , then we find U= W(v/G), which further leads us to the present conclusion, g = a. Using this obtained value of g, we can determine the absolute value of [Vs] from [Vs] =g
S. Some examples of determining the absolute values of [Vs] are demonstrated.

We will also represent briefly our completely new technique of measuring the vacancy concentration in the near surface region of the silicon wafers. In this technique, the elastic softening due to the near-surface vacancies is selectively observed by the surface acoustic wave, instead of the bulk sound wave used for the above-mentioned measurement.
Invited; Modeling of Oxygen Precipitation in Silicon
Authors: Dunham Scott T. , Trzynadlowski Bart C.
Published: February 2020

A model for the precipitation of oxygen and associated dislocation loops in Czochralski-grown silicon will be presented. Beginning with kinetic rate equations describing the growth and dissolution of oxide precipitates, a reduced model based on the moments of the precipitate size distribution is developed and validated against experimental data. Comparisons with the full, rate equation-based model show that the reduced version is comparably accurate while requiring significantly less computational power. The formation of dislocation loops due to silicon interstitial ejection during precipitate growth is modeled using a simple, moment-based approach.
Overcoming High Performance Semiconductor Packaging Challenges Using Plasma
Authors: Foote David
Published: February 2020

Moore’s Law has been the driving force of front end semiconductor technology development for over 40 years and is finally meeting its match. Technology demands, though, will not allow a slow down so the back end packaging technology needs to pick up the slack. Packaging technologies are now more like the front end chip technologies of 30 years past. Thirty years ago plasma processing was at best at the toddler stage in front end fabs while commonplace now. Thirty years hence plasma is at a similar stage in the back end packaging arena. Plasma processing enables the high performance packages required today.

Plasma is useful for both the manufacturing process of the packages as well as in the assembly of the package. High density interconnect assemblies are build on printed circuit assemblies that have had plasma processing to enhance adhesion between laminate layers as well as cleaning the through holes prior to plating.

Wafer level packaging is melding the front and back ends and plasma processing is enabling. The dimensional requirements are still such that high performance front end plasma processing techniques are not required but moving from the era of mils to microns does demand high performance from the plasma processing tool. Useful plasma processes for WLP include resist descum and strip, pre-bump cleaning and copper stud oxide reduction.

Optimized plasma processes enable three dimensional packaging technologies that are both useful and reliable. Flip chip packaging is becoming the norm at the leading edge and plasma enables better bondability and more reliable packages. Likewise plasma pre-treatment prior to wire bonding enables more robust and reliable bonds. Proper treatment levels enable robust bonds even on advanced packages of today with very thin metal stack for bonding. Plasma treatments are also useful for silicon stress reduction following wafer thinning and/or dicing.

Specific application examples will be presented showing the many uses and benefits of plasma processing for semiconductor packaging.
Effect of Cupric Methanesulfonate on through-Hole Filling by Copper Electroplating
Authors: Ye Ji-Xun , Dow Wei-Ping
Published: February 2020

Through-hole (TH) filling of a printed circuit board (PCB) by copper electroplating was performed using copper sulfate (CuSO4) in recent years. However, the process might cause crystallization issue of CuSO4 because of extremely high CuSO4 concentration (i.e., 220g/L). In the other words, CuSO4 concentration cannot be increase anymore, if someone wants to enhance the copper filling rate inside the TH by increasing plating current density.

The anions of cupric methanesulfonate ( Cu(CH3SO3)2 ) is CH3SO3
-, which is different from copper sulfate (CuSO4). The solubility of cupric methanesulfonate is much higher than CuSO4, so that we can increase the current density and decrease plating time for TH filling by means of increasing cupric methanesulfonate concentration.

In this work, we employed the butterfly filling formula[1] to perform the TH filling. The copper source was changed from CuSO4 to Cu(CH3SO3)2 in order to increase copper ion concentration. The result show that with the high concentration of copper ion, we can enhance the copper filling rate inside the TH by increasing plating current density. Moreover, the copper thickness deposited on the board surface is not increased and the filled TH is void-free when the plating current density is increased.

Keywords: Through-hole filling, Printed circuit board, Leveler, Cupric methanesulfonate

References

1. J. J. Yan, L. C. Chang, C. W. Lu, and W. P. Dow, “Effects of organic acids on through-hole filling by copper electroplating

”, Electrochim. Acta. 2013, 109, 1– 12.
Anodic Oxidation of SPS Resulting in PDS Formation and the Influence of PDS on Electrolytic Copper Via Filling Performance
Authors: Kimizuka Ryoichi , Toda Hisayuki , Eda Tetsuro , Takai Osamu
Published: February 2020

Electrolytic copper via filling based on three additive component copper sulfate bath chemistry has been and currently is widely used in electronic packaging. Progression in copper sulfate plating chemistry continues to promote device densification, which is vital to development of smart phones among other devices. Bath maintenance is an important aspect of ensuring filling performance, where in addition to additive concentration, additive decomposition product concentrations also require management. In order to further elucidate bath chemistry and possibly methods to improve performance, degradation of the disodium 3,3'-dithiobis(1-propanesulfonate) (SPS) additive, which is employed as brightener, during copper via filling by electrodeposition and the influence of a byproduct on plating were investigated. Oxidative decomposition of SPS and formation of disodium 1,3-propanedisulfonate (PDS) at an IrO2 coated Ti insoluble anode during electrolysis were confirmed by NMR analysis. Furthermore, formation of PDS by chemical oxidation of SPS was also observed, suggesting anodic oxidation as the mechanism for PDS formation in the plating bath during electrolysis. By addition to a fresh bath, PDS was then shown to compromise via filling performance, where increase in PDS concentration resulted in a proportional performance decrease. This study clarified the anodic oxidation of SPS to PDS under electrolytic filling conditions and that the PDS concentration correlated to the filling ability of the copper plating bath.
Stability Evaluation of Non-Agglomerated Pd Nanoparticle Catalysts for Electroless Deposition
Authors: Nakamura Noriaki , Taniuchi Junichi , Sone Takayuki , Sasaki Kotoe , Inoue Fumihiro , Shimizu Tomohiro , Shingubara Shoso
Published: February 2020

Conventional physical vapor depositions (PVD) of diffusion barrier and seed layers have been facing its limits of application for high aspect ratio of through Si via (TSV). Electroless plating (ELP) is an alternative candidate for TSV metallization because of their promising potential, e.g. conformal deposition property, cost reduction possible and low temperature.

In order to deposit ELP film on dielectric layer, catalyst process is the most important. In general, Sn-Pd process has been used for catalyst process of ELP. In addition, palladium nanoparticles (Pd-NPs) showed high density of adsorption, which assisted achievement of thin and conformal ELP formation in high aspect ratio TSV [1, 2].

To deposit electroless plating, high density of adsorption of Pd-NPs is required. Furthermore, in actual manufacturing process, long term stability that assumed repeated use is strongly desired.

In this study, we have developed the Pd-NPs to shorten the processing time in TSV and disperse in water for a long period. We found that the addition of compound A(COM-A ) or B enable to significantly improve the stability without losing the adsorption property of Pd-NPs.

Fig.1 shows the time transient of the diffusion coefficient of Pd-NPs with and without COM-A in solution which were stored at 25 °C. Diffusion coefficient of the particles were measured by dynamic light scattering (DLS).

In the Pd-NPs solution without COM-A, the diffusion coefficient of the particles gradually decreased. However, the diffusion coefficient of particles maintained a constant value in the Pd-NPs solution with COM-A.

According to the Stokes-Einstein equation, if the temperature and viscosity of a solution is constant, the decreasing of the diffusion coefficient indicates that the particles aggregate each other. Thus, the substantial catalyst particle number can be decreased for the case without COM-A.

Fig.2 shows SEM images of Pd-NPs adsorbed on blanket SiO2. The Pd-NPs solutions were stored 40 days at 25 °C before use. In the case of Pd-NPs solution with COM-A, there is no agglomeration of the particles on the sample. On the other hand, particles agglomeration were occurred in case without COM-A.

In addition, we also found that the addition of COM-A is possible to dispersed again agglomerated Pd-NPs. These results suggest that the Pd-NPs solution with COM-A is applicable to actual manufacturing process.

[1] F. Inoue, S. Shingubara, et al., ECS Transactions, 25 (38) 31-36 (2010)

[2] F. Inoue, S. Shingubara, et al., Electrochimica Acta
82 (2012) 372-277
Electrodeposition and Characterisation of Novel Ni-NbOx Composite Coatings as a Diffusion Barrier for Liquid Solder Interconnects - Part II: Diffusion Barrier Performance
Authors: Wang Jing , Wilcox Geoffrey D , Mortimer Roger J , Liu Changqing , Ashworth Mark A
Published: February 2020

Electronics products are increasingly required to operate at high temperatures in harsh environments, for instance in oil well, geophysical drilling and aerospace applications. Conventional solder interconnects, that have been extensively utilised in consumer electronics, are no longer adequate. This is primarily due to excessive intermetallic compounds (IMCs) that can form and continuously grow during high temperature operation. With the intention of reducing such excessive IMC growth, electrically conducting niobium sub-oxide containing Ni coating has been produced which acts as a barrier layer between the solder and substrate. This then promises the possibility of developing a new solder barrier material with electrical conductivity and chemical resistance as required.

The present study considers a novel electrochemical route to produce Ni-NbOx composite coatings of good uniformity, smoothness, compactness and purity. The electrolyte is derived from a Type IV eutectic solvent consisting of NbCl5 and propylene glycol (PG). The addition of a small amount of Ni ions (molar ratio: Ni : Nb=1 : 30) was found to enable the co-deposition of Nb species. The introduction of NaBH4 into the electrolyte has elevated the maximum deposit thickness (above 15 µm), although this led to a reduction in the co-deposited Nb content. The effects of cathodic current density, metal precursor and NaBH4 concentrations on the surface morphology, composition and thickness of the coatings were examined. Scanning transmission electron microscopy (STEM) revealed a nanocrystalline structure resembling that of a simple FCC structure of Ni, with a slightly fluctuating composition across the coating thickness and with Nb uniformly distributed (See Fig. 1). From X-ray photoelectron spectroscopy (XPS), a 0.7 eV shift to lower binding energy for the Nb (V) species signifies the partial chemical reduction of Nb2O5 due to possible Ni-Nb bonding. It is thus proposed that a Ni-NbOx deposit was formed by a two-step mechanism: the simultaneous electrochemical reduction of adherent Ni metal and inadherent niobium oxides on Cu, followed by nickelation of the NbOx. The composite coating’s electrical conductivity, solderability and diffusion barrier characteristics (the latter preventing excessive IMC growth between molten Sn-In solder and Cu substrate) were assessed and showed promising results. From diffusion studies, a Nb-enriched layer was observed at the solder/substrate interface after ageing at 200°C suggesting evident effectiveness of the diffusion barrier characteristics.

Figure 1 - STEM cross sectional image a) of a 95Ni-5Nb coating with corresponding Energy-dispersive X-ray spectroscopy (EDX) maps of b) Ni Kα & c) Nb Lα.
Invited: Heterointegration of Semiconductors: Challenges and Opportunities
Authors: Moutanabbir Oussama
Published: February 2020

Nowadays, semiconductor industry faces major challenges as the current materials and designs can hardly respond to the relentless course towards device miniaturization, higher performances, energy efficiency, cost-effectiveness, and multifunctionality, which have been the driving forces for the development of semiconductor technologies. New materials and integration processes are urgently needed to overcome these multi-faceted challenges. The heterointegration of dissimilar materials on the same platform has recently emerged as a powerful strategy to address some of these challenges. Particularly, tremendous efforts have been put to develop fabrication processes that allow the integration of III-V compound semiconductors on foreign substrates. For instance, III-V heterointegration on silicon substrates will enable the combination, within a single platform, III-V high-performance technologies with low cost and wafer size advantages besides its compatibility with standard semiconductor processing. In addition to electronic and optoelectronic applications, the realization of these hybrid substrates is also highly relevant for high-efficiency, low-cost photovoltaic cells, spintronics, bio-integrated technologies, to name a few. It is, however, noteworthy that this heterointegration needs to be achieved on the wafer level in order to be technologically and economically viable. In this presentation, we provide a description of important approaches to achieve this heterogeneous integration, with an emphasis on wafer bonding processes and thin layer splitting using the ion-cut process. A variety of bulk-quality heterostructures, frequently unattainable by direct epitaxial growth, can be produced provided that a list of technical criteria is fulfilled, thus offering an additional degree of freedom in the design and fabrication of heterogeneous, multifunctional, and flexible devices. Ion cutting is a generic process that can be employed to split and transfer fine monocrystalline layers from various crystals. Materials and engineering issues as well as our current understanding of the underlying physics involved in its application to cleaving thin layers from freestanding GaN, InP, and GaAs wafers will be presented and discussed.
Effects of Miscut Substrates on Electrical Conductivity Across InP and GaAs Wafer-Bonded Structures
Authors: McKay Jeffrey , Seal Mark , Yeung K. , Jackson M. , Goorsky M. S.
Published: February 2020

Direct wafer bonding of III-V materials is of great interest for the fabrication of next generation high efficiency solar cells. Traditional wafer bonding methods of III-V materials lead to highly unstable oxide interfaces and poor electrical properties. To resolve these issues, elevated annealing temperatures (>600 °C), long times, and large compressive forces are employed to break up this interfacial oxide layer, so that there is better contact between the III-V bonding interfaces. These harsh processing conditions ultimately limit the achievable efficiencies, due to dopant diffusion and residual thermal strains in processed devices. Sulfur surface treatment prior to bonding was found to reduce the inclusion unfavorable oxides at the interface, reducing the post-bonding thermal and compressive force requirements, and promoting the ability to bond large (100 mm diameter) wafers..

Various combinations of sulfur treated n-GaAs and n-InP directed bonded structures were measured to investigate the effects of offcut angles on the electrical conductivity. The impact of the relative offcut angle on the electrical properties is an new unexplored area which is of important issuece, as misorientated substrates are typically used for the growth of III-V epitaxial layers in the solar industry to avoid anti-phase boundaries. It is observed in both the GaAs and InP bonded structures, that out-of-plane relative surface orientations between the (001) planes that are greater than 4° exhibit non-ohmic behavior. A theoretical model that describes the electron tunneling across a grain boundary between semiconductor bicrystals is used to represent the bonded interface and estimate the barrier conduction height. Fitting the zero-bias conductance over a range of temperatures reveals an increase in barrier heights for samples with greater than 4° misoriented bonded pairs, correspondingly the interface resistance at room temperature increases. These results demonstrate that the out-of-plane relative surface misorientation is the critical parameter to be monitored in order to achieve superior electrical conductivity in direct-bonded multijunction solar applications. In addition, differences between GaAs-GaAs bonded structures and InP-InP bonded structures indicate that the barrier for GaAs-GaAs is significantly greater than for InP-InP. The impact of the miscut itself, however, is similar in both cases, showing that both the chemical nature and the structural interface properties play roles in trans-interface electrical conduction.
Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication
Authors: Flötgen Christoph , Razek Nasser , Dragoi Viorel , Wimplinger Markus
Published: February 2020

Compound semiconductor integration techniques draw ever more attention with increasing demands for high efficiency power electronics, photovoltaic or photonic devices. Aside from methods including epitaxial growth, one of these techniques is direct wafer bonding.

An interesting wafer bonding approach for the above-mentioned types of applications would be a process resulting in formation of covalent bonds at room temperature (“covalent bonding”) or at significantly low temperatures (e.g. <100°C). Hence, the common issues arising from bonding of materials with different thermal expansion coefficients could be avoided, in the first place.

The challenges in covalent bonding are mostly determined by the rigorous requirements for cleanliness with regards to particle and mobile ion contamination, as well as surface roughness and process uniformity.

If the bonding process must produce a conductive interface an intermediate process step needs to be added that reduces/removes the stable native oxides from the substrates surfaces, as they would form an insulating layer in the final bond interface and hence lead to decreased electric device performance. This implies that in addition to the requirements for covalent wafer bonding, an effective and complete oxide removal needs to be guaranteed, to achieve a successful conductive wafer bond. However, as lattice point defects (e.g. interstitials and dislocations) form traps for charge carriers which would affect device performance as well, a suitable oxide removal step would leave the underlying bulk material mostly unchanged.

The current work presents preliminary results of a novel technology designed to produce covalent / conductive wafer bonds. Results shown here were obtained in experiments using 200 mm wafers (prime Si and with 300 nm thermally grown oxide) supported by numerical modelling of sub-surface defects using SRIM [1]. The results obtained for Si are used as baseline for the new technology development (equipment and process) before applying it to compound semiconductor-based applications.

[1] J. F. Ziegler, M. D. Ziegler, and J. P. Biersack, Nucl. Instrum. Methods Phys. Res. B 268, 1818 (2010).
Electrical and Microstructural Characterization of Cu-Germanide Contacts Formed on p-Type Ge Substrate
Authors: Lim Yi-Rang , Lee Ye-Ji , Kang Min-Sung , Leem Chang-Hyun , Jyothi I. , Shim Kyu-Hwan , Choi Chel-Jong
Published: February 2020

We have investigated the electrical and microstructural properties of Cu-germanide formed on p-type Ge substrate as a function of rapid thermal annealing (RTA) temperature. As increasing RTA temperatures, Cu films reacted with Ge and formed Cu-germanides. The Cu3Ge phase appears to be the dominant phase along with Cu5Ge2 phase at annealing temperatures of 500 and 600 °C. The sheet resistance and specific contact resistivity were investigated as a function of germanide formation temperature. A minimum specific contact resistivity value of 6.19´10-6 Ωcm2 is obtained after annealing at 400 °C associated with the formation of stoichiometric Cu3Ge. The sheet resistance and specific contact resistivity increased after rapid thermal at temperatures >500 °C indicated the degradation of the contact properties and could be associated with the formation of copper rich Cu5Ge2phase and the loss of structural integrity with increasing annealing temperature.
(Invited) Electro-Thermal Characterization of SiGe HBT PA-Cells
Authors: Zimmer Thomas , Weiß Mario , De Matos M. , Maneux Cristell , Fregonese Sebastien
Published: February 2020

The European FP7 DOTSEVEN project is motivated by the increasing interest in utilizing the mm-wave frequency spectrum within the so-called THz gap (which ranges from 0.3 to 30 THz) for a wide variety of applications. In order to design and demonstrate working integrated mm- and sub-mm-wave circuits, the DOTSEVEN consortium aims the realization of SiGeC Heterojunction Bipolar Transistors (HBTs) operating at a maximum frequency up to 0.7 THz (i.e. 700 GHz) at room temperature. One associated main objective of the DOTSEVEN project is the evaluation, understanding, and modeling of the relevant physical effects occurring in such high-speed devices and circuits.

The higher the speed of advanced HBTs is the higher are their current densities and internal electric fields. This leads to increased self-heating and potential thermal instabilities. Their detailed impact on device characteristics and parameter extraction are investigated from a theoretical point of view with 3D thermal simulations, and from an experimental point of view with pulsed DC and AC measurements. Furthermore the impact of deep trenches on heat dissipation is analyzed as well as the thermal coupling with adjacent emitter fingers and pcells.
Effect of Graphene Passivation on Ge Pin Photodiode
Authors: Zagarzusem Khurelbaatar , Kim Joung-Hee , Kil Yeon-Ho , Kim Taek Sung , Choi Chel-Jong , Shim Kyu-Hwan
Published: February 2020

We characterized the electrical and optical properties of graphene layer deposited photodiode with n-Ge/i-Ge/p-Si hetero-junction structure which were grown on boron doped p-type Si (100) wafers with 5~15 Ω-cm resistivity using the rapid thermal chemical vapor deposition (RTCVD) method. Furthermore, a reference p-i-n hetero-junction photodiode also fabricated and its comparison results explained by corresponding band diagrams and Ge surface passivation.

Fig. 1(a) shows the cross-sectional SEM image of the n-Ge/i-Ge layer. The p-i-n structure consists of a ~ 0.3 µm thick heavily phosphorus doped n-Ge layer and ~ 2.5 µm thick intrinsic Ge layer grown on p-Si substrate. Crystalline homogeneity and the microscopic strain state of the n-Ge/i-Ge epilayer analyze was performed high resolution X-ray diffraction (HR-XRD). The (400) peak of the n-Ge/i-Ge layer was observed at 5522 arcsec separated with respect to Si peak, as shown in the Fig 1(b). The HR-XRD rocking curve shape demonstrates the superior quality n-Ge/i-Ge layer and absence of tensile strain components because of two peaks are clearly observed.

In order to investigate the number of layers and quality of the CVD grown graphene after deposit on hetero-structure, the room-temperature Raman spectra were obtained using a 487.55 nm Ar-ion laser in the range of 1.000 to 3.000 cm-1 as shown in the Fig 2. The laser power applied to the sample was about 1.011mW. Raman spectrum of the graphene film is found to consist of two sharp peaks: i.e., 2D-band peak at ~ 2698 cm-1 and G-band peak at ~ 1581 cm-1, suggest that the transferred graphene was a monolayer graphene.

The p-i-n photodiode with round mesa structure as shown in schematic form in Fig.3. Diameter of mesa were 250 µm and mesa were defined by standard photolithography and CF4 reactive ion etching of the n-Ge/i-Ge layer to p-Si substrate by using inductively coupled plasma (ICP) etching.

Fig. 4 shows the typical forward and reverse biased J–V curves under dark and photo illuminated graphene/n-Ge/i-Ge/p-Si and n-Ge/i-Ge/p-Si hetero-junction photodiodes. We obtained reduced dark J from proposed graphene/n-Ge/i-Ge/p-Si photo diode. Dark current density and photocurrent density values were 0.49 A/cm2 and 3.01 A/cm2, respectively at reverse 1 V. Also, these values obtained to be 1.43 A/cm2 and 3.819 A/cm2 from n-Ge/i-Ge/p-Si photodiode at same bias. Ideality factor n was found to be 1.3 in the low voltage range. This implies that the dark current is dominated by diffusion rather than recombination, which indicates the high quality of the material.

The spectral photo-responsivity of the two p-i-n photodiodes measured at reverse 2 V for wavelength in the range from 1520-1630 nm. Detailed comparison results and discussions will be present in the full manuscript.
(Invited) Thin Epitaxial Film of Ge and III-V Directly Bonded onto Si Substrate
Authors: Maeda Tatsuro , Mieda Eiko , Ishii Hiroyuki , Itatani Taro , Hattori H , Yasuda Tetsuji , Maeda Atsuhiko , Kurashima Yuichi , Takagi Hideki , Aoki T , Yamamoto T , Ichikawa Osamu , Osada T , Takada T , Hata Masahiko , Yugami J , Ogawa A , Kikuchi T , Kunii Y
Published: February 2020

Ge and III-V compound semiconductors are expected to be used for non-Si channel MOSFETs as one of the effective technical booster to reduce the power consumption of next generation VLSI because of its higher carrier mobility than that of Si. Various approaches to introduce those non-Si channel materials into Si platform have been proposed, among which the ELO(epitaxial lift off) technique may have a good potential for manufacturing such a composite wafer consist of non-lattice-matched crystalline materials.

High quality Ge and GaAs/InGaAs epitaxial thin film can be grown on lattice-matched/quasi-lattice-matched GaAs or InP single crystal substrate using CVD/MOCVD technology. The thin epitaxial film can be chemically lifted-off by selectively removing sacrificial epitaxial layer grown between the epitaxial film and the substrate, transferred and directly bonded onto Si substrate using thin oxide film made of Al2O3 and/or SiO2 as an adhesive layer, thus successively providing GOI and/or III-VOI(Ge and/or III-V compound semiconductors on insulator) composite wafer including the oxide film as an effective BOX(buried oxide) layer. The area size of transferred Ge/III-V film can be modified according to its application die size. The epitaxial layer quality after transferred onto Si substrate and initial device performance of Ge/III-V channel MOSFET formed on the Ge/III-V OI substrate will be introduced.
(Invited) Waveguide Germanium PIN Photodiodes for Optical Communication Applications
Authors: Vivien Laurent , Virot Léopold , Hartmann Jean-Michel , Fédéli jean-Marc , Marris-Morini Delphine , Cassan Eric , Baudot Charles , Boeuf Frédéric
Published: February 2020

Silicon photonics has generated in recent years a strong interest for a large range of applications from optical telecommunications to microelectronics. The main advantages of this technology are the reduction of photonic system costs and the increase of the number of functionalities on the same chip, notably by combining photonics and electronics. Numerous advances in silicon photonics have occurred, with the demonstration of high speed Si modulators, Ge photodetectors and hybrid laser on silicon [1].

The photodetector is one of the main building blocks for the implementation of fast silicon photonics integrated circuits. The required considerations for the design of such a device are the bandwidth, the power consumption and the responsivity. Germanium is now considered as the ideal candidate for fully integrated receivers on SOI substrates and based on CMOS-like processes. High speed and high responsivity Ge photodetectors have already reported on literature [2-4]. However, they suffer from relatively high dark currents as compared to their III-V homologues. The increase of bias voltage directly leads to higher bandwidth but also to a higher dark current mainly through tunneling, as a consequence of Ge low band-gap. Furthermore, Ge on Si suffers from crystal defects due to the lattice mismatch between Si and Ge.

In this paper, we report on lateral pin photodiodes with thick Ge layers as the active media. Germanium is then integrated at the end of the Si waveguide, using the butt-coupling configuration to totally absorb light after few microns propagation at wavelength ranging from 1.3µm to 1.55µm (fig.1). Reliable detection characteristics have been obtained, including a bandwidth over 50GHz under zero-bias (fig.1), an internal responsivity higher than 0.5A/W at a wavelength of 1.55 µm and a dark current of about 10nA under -1V. 40Gb/s open eye diagrams were also obtained under zero-bias, showing the possibility of fabricating Ge-based low power and ultra-fast receivers. Some recent demonstrations of multiple-wavelength circuits and 40Gbit/s optical link, fabricated on a 300-mm microelectronics pilot line will also be presented {4].

Fig. 1: Schematic view of lateral Ge photodetector integrated in Si waveguide. SEM view of Ge photodetector cross-section.Normalized optical response as a function of frequency for lateral pin Ge photodiode under zero-bias.

References:

[1] L. Vivien and L. Pavesi, Handbook of silicon photonics, CRC & Taylor Press (2013)

[2] L. Vivien et al., Opt. Express 20, 1096-1101 (2012).

[3] C.T. DeRose et al., Opt. Express 19(25), 24897-24904 (2011).

[4] S. Liao et al., Opt. Express 19(11), 10967-10972 (2011).

[5] D. Marris-Morini et al., Opt. Express 22, 6674-6679 (2014)
(Invited) Photonic Interconnection Made by a Ge/SiGe MQW Modulator Connected to a Ge/SiGe MQW Photodetector through a SiGe Waveguide
Authors: Frigerio Jacopo , Chaisakul Papichaya , Marris-Morini Delphine , Rouifed Mohamed-Said , Cecchi Stefano , Chrastina Daniel , Isella Giovanni , Vivien Laurent
Published: February 2020

In the last years Ge/SiGe multiple quantum wells (MQW) have received a great attention in the context of silicon photonics for the realization of efficient electro-absorption modulators based on the quantum confined stark effect. At present day, one of the main problems to be addressed toward the integration of Ge/SiGe MQW modulators is their coupling with passive optical components such as waveguides. In particular, the integration with silicon waveguides is very difficult due to the presence of a thick SiGe layer which act as a virtual substrate (VS) for the MQW stack. In this work we demonstrate that the VS can be used as a low loss optical waveguide by choosing a suitable compositional mismatch with respect to the MQW stack. A photonic interconnection made by a Ge/SiGe MQW modulator connected to a Ge/SiGe MQW photodetector through a SiGe waveguide has been fabricated and tested in order to demonstrate the great potential of this approach. The whole structure has been deposited on a silicon substrate in a single epitaxial step by low energy plasma enhanced chemical vapor deposition. The optical insertion loss of the device is less than 5 dB/cm. 5 and 10 µA are obtained in the photodetector with 1V and 3V voltage swing at the modulator. The photodetector bias is -1V and the dark current is 10 nA. Similar performance can be obtained in a wide spectral range from 1430 nm to 1450 nm. This demonstration confirms that Ge quantum well interconnects are feasible for low-voltage broadband optical links integrated on silicon chips. Our approach can be extended to any kind of Ge-based optoelectronic devices working within telecommunication wavelengths as long as a suitable Ge concentration is selected for the Ge-rich virtual substrate.