bluuebunny/crossref_metadata_2025 huggingface dataset:
Study on Bit Line TiCl4 TIN Process Optimization for Stack DRAM IDDS Standby Failure Improvement
Authors: Chen Liang , Li Zhi-Chao , Song Xing-Hua , Xu Lei , Lin Yi-Hui , Wei Hsueh-Hung , Lin Paul-Chang
Published: March 2009

Dynamic Random Access Memory (DRAM) plays an important role in semiconductor industry. For 0.13um stack DRAM (D13) process, Bit line (BL) is a critical loop and acts as a contact between active area (AA) and periphery area. Normally, BL consists of BL glue layer Ti/TiN and BL W. TiCl4 is applied for D13 BL glue layer Ti/TiN deposition. D13 suffers electrical drain-to-drain standby (IDDS) failure that means junction electrical leakage. Through further investigation, BL glue Ti/TiN have influence on AA Ti diffuse, and IDDS standby failure will be enhanced with deeper TiSix formation. In this study, we present the effect of TiCl4 glue TiN film's quality on D13 IDDS standby failure.
Second Generation Copper Dielectric Barrier (BLOk II): k Reduction and Interface Control To Improve TDDB and EM
Authors: Xia Li-Qun , Zubkov Vladimir , Ye Weifeng , Shek Mei-Yee , Cui David , Naik Mehul
Published: March 2009

Sub-45nm backend device integration requires material improvements for further RC reduction. One of the key candidates to achieve lower RC is the dielectric barrier. The dielectric constant of the copper barrier can be reduced to <4.0 by additional carbon doping. In addition, this new material can still maintain comparable copper barrier properties and etch selectivity to the current 45nm dielectric barrier baseline. To meet the challenges of the device shrink, advanced interface management is required to achieve good TDDB and EM. An Enhanced Nitride Interface (ENI) concept was adopted to maximize the interfacial mechanical and electrical strength without negative impacts on copper electrical performance.
Studies of Wafer Backside Micro-arcing Prevention In Encore Ta Process
Authors: Chen Andy , Bian Allen , Lin Paul-Chang , Xing Charles , Zhou Hua
Published: March 2009

In advance Cu BEOL process, Encore Ta/TaN deposition process is widely used for barrier layer deposition to achieve lower via resistance and better electro migration and stress migration performance. However, wafer micro arcing existed frequently due to complex chamber design and DC/RF/AC/ESC adoption in Encore Ta process. To solve the micro arcing issue is the one of key topics in Encore Ta process. In this study, the formation mechanism of micro arcing is analyzed. Gas plug is introduced into Encore Ta process to prevent micro arcing.
Pre-clean Study for Both Damascene SiN and N-Blok to Resolve Queue-time-dependent Dielectric Barrier VBD Degradation
Authors: Xu Jerry , Gao Rong , Wang Hongjie , Li Xianyuan , Lee Sang , Cui David , Naik Mehul , Xia Li-Qun , Xu Qiang , Zhang Ziying , Bei Emily
Published: March 2009

Recently, it was found that for 65 nm logic device the VBD for SiN will decrease dramatically (from about 60 V to below 30-40 V if the queue is longer than eight hours) when the queue time after Cu CMP (prior to damascene SiN deposition) is longer than two hours. The problem happened most at SiN and BD I interface (Metal layer 5 with the same design rule of line spacing of Metal layer 2). Such a problem makes the BEOL production extremely difficult. To overcome this major challenge for SiN, we have analyzed the various kinds of potential root causes and showed that the change of Cu oxidation post Cu CMP is the real root cause. We have developed a series of new pre-clean recipes and tested most of them at customer site with customer's device wafers together with CVD division at the 300 mm fab of Applied Materials in USA. In this paper, we will discuss the potential mechanisms of time dependant VBD degradation and the practical solution to this problem.
A Study on PVD Co Pre-clean Chamber RF Reflect Power Improvement
Authors: Gui Kun , Hu Pin-Sheng , Ouyang Dong , Peng Chi-Hsien , Yang Huang-Her , Lin Paul-Chang
Published: March 2009

For 0.18um and 0.13 um technology, Co/TiN deposition process is widely used to form CoSix to provide the needed lower contact resistance of the polysilicon gate. CoSix formation is sensitive to pre-existing wafer surface native oxides and ambient contamination. Pre-clean process before Co film deposition is required to remove residues before Co/TiN deposition. The corresponding chamber RF reflected power too high issue during this pre-clean has significant impact on the etch rate and particle performance. In this paper, three approaches to reduce Co pre-clean chamber RF reflect power are presented.
Robust HfxSi1-xO2 Gate Dielectric using Co-injection Atomic Layer Deposition
Authors: Bartholomew Larry , Bavin Andy , Lazerand Thierry , Rao Vivek
Published: March 2009

Using a novel Atomic Layer Deposition (ALD) process in which multiple chemical precursors are simultaneously injected to form a monolayer on the substrate and then oxidized, we demonstrate a robust hafnium silicate film that can be easily tuned to meet specific device requirements. A large process window is demonstrated via physical and electrical performance of the film. The film has been fully integrated into a CMOS structure and repeatable parametric results over a wide range of film compositions are shown.
Material Etch Rate Control in the Fluoride Containing Stripper for Post Etch and Ashing Residue Removal
Authors: Liu Bing , Peng Libbert , Peng Julia , Yu Joey , Wang Shumin
Published: March 2009

In this paper, we share a unique metal and dielectric inhibitor system and the corresponding methodologies in controlling the materials etch rate from the fluoride-containing stripper and the etch rate stability with the bath life time extension. In addition, the cleaning performance of the fluoride containing stripper with low materials etch rate is also introduced.
Influence of Polymeric Gas on Sidewall Profile and Defect Performance of Aluminum Metal Etch
Authors: Wang Xinpeng , Zhang Haiyang , Shen Manhua , Sun Wu , Chang Shih-Mou
Published: March 2009

As the semiconductor industry moves to 65nm node and beyond, Al metal etch has become more and more challenging for its insufficient amount of photo-resist (PR) to achieve the desired sidewall profile and keep the corrosion free performance simultaneously. In this paper, we focus on the selection of appropriate polymeric gas and identify the effect of various etch polymeric gases on Al metal sidewall profile and their corrosion defect performance. Three typical gases including N2, CHF3 and CH4 are selected in this paper. The observations of scanning electron micrographs indicate N2-based recipe is apt to form the severely tapering sidewall profile while CHF3-based recipe has loose polymer protection over the sidewall, thus leading to much worse corrosion defect performance. As expected, CH4-based recipe outperforms the two above polymeric gases. It not only shows the acceptable sidewall profile but also delivers the defect performance of free corrosion.
Etch Arts of Dual Damascus Structure and Their Impacts on WAT/VBD in 65nm Cu Interconnects
Authors: Sun Wu , Chang Shih-Mou , Zhang Haiyang , Yin Xiaoming , Fu Liya , Han Baodong , Wang Xinpeng , Wu Yongqin
Published: March 2009

In this paper, based on the via-first DD technology, we focus on the profile tuning of via and trench and the liner removal in order to optimize the trench profile. Via profile tuning include how to realize the via with the bowling profile, vertical profile and tapering profile. Trench profile tuning emphasizes the formation mechanism of bowling profile and top rounding profile. Footing profile and under-cutting profile of via bottom in liner open step is also addressed. The effect of different etching profiles on Rc, VBD (Breakdown Voltage) are examined. Results show that different via profiles have no impact on Rc, top-rounding trench-profile results in worse VBD, while under-cut & footing liner would deliver lower and higher Rc, respectively.
Study of Film Growth on Silicon in Advanced High Dose Implant Photoresist Strip
Authors: Diao Li , Xu Songlin
Published: March 2009

Downstream high dose implant photoresist strip (HDIS) plasma processes tend to cause an oxide growth on the exposed poly Si and a poly-Si loss, both need to be carefully controlled/minimized to avoid undesirable impacts to the corresponding IC device performance. Ellipsometry and FTIR spectrometry were used to characterize the ultrathin film growth and poly-Si loss introduced by the various chemistries used in HDIS, including O2, O2/FG, O2/H2, and N2/H2. Some discrepancies were observed between results obtained from Ellipsometry and those from FTIR for ultra thin films. Oxide growth was evident in O2 dominant chemistries, accompanied by a low level poly-Si loss. No oxide growth was observed in non-O2 chemistries. Hydrogen addition provided a better clean and a shorter processing time, but at the cost of increasing poly-Si loss and oxide growth.
3D DRAM in Server Application
Authors: Cai Biao , Patel Vipinchandra , Blackshear Edmund D.
Published: March 2009

Server system requirement drives the evolution of 3D DRAM technologies. The new generation provides form factor, electrical and power performance benefits. Meanwhile it brings in a more complicated design, new assembly technologies and new failure mechanisms. The optimum 3D DRAM technology is determined by complex tradeoff of benefits, cost, time to market and reliability. The characteristics of the optimum 3D DRAM technology for DDR2, DDR3 and future server memory system are analyzed in detail. TSV (Through Silicon Via) DRAM array stacking is expected to bring superior power performance which could be a significant market diver. The tradeoff of this future technology and process development trend is presented.
3D Integrated, Ultra-Thin Functional Microcontroller Device for Wireless, Flexible ECG Systems
Authors: Christiaens Wim , Torfs T. , Huwel W. , Van Hoof C. , Vanfleteren J.
Published: March 2009

This paper presents a technology for the 3D-integration of a TI-MSP430 low-power microcontroller inside conventional double sided flex substrates, for a wearable wireless ECG system. The devices are first thinned down to 25 µm and next integrated as UTCP (Ultra-Thin Chip Package) in between two polyimide layers, resulting in 50-60 µm thin package. These extremely thin, mechanically flexible packages serve as interposers for embedding into conventional multilayer flex substrate, replacing for example the integration of naked dies. Providing a contact fan-out, this approach enables the testing of the device before embedding (solving the KGD issue). It also eliminates the need for precise placement and the use of expensive ultra high density PCBs. Smaller SMD components have been mounted above and below the embedded chip, leading to high density integration. In addition, the embedded thin silicon chip becomes mechanically flexible itself, leading to an increased flexibility of the resulting system.
Challenges, Trends and Solutions for 3D Interconnects in Lithography and Wafer Level Bonding Techniques
Authors: Zoberbier Margarete , Hell Erwin , Cook Kathy , Hennemayer Marc , Neubert Barbara
Published: March 2009

Technology advances such as 3-D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what's currently possible for many production processes, including lithography processes and wafer bonding. There is still the need to coat, pattern and etch structures. This paper will explore some of the lithographic challenges associated with 3D interconnection technology. Wafer bonding techniques as used in the 3D Packaging will be described with all the challenges and available solutions and trends. Furthermore a new Maskalinger technology will be introduced which allows extreme alignment accuracy assisted by pattern recognition down to 0.25µm. An overall introduction on the challenges, trends and solutions for 3d interconnects in lithography and Wafer Level bonding techniques and the SUSS's equipment platform will be described accordingly to the needed processes. The processing issues encountered in those techniques will be discussed.
Throughput Enhanced Flip-Chip to Wafer Bonding: The Advanced Chip to Wafer Bonding
Authors: Sigl Alfred , Pargfrieder Stefan , Matthias Thorsten , Wimplinger Markus , Kettner Paul
Published: March 2009

System-in-Package (SiP) is a semiconductor packaging and integration approach to lower costs, increase performance and decrease form factor. Because of the shrinkage of the functional structures on the chips, metal joint technology has to be used, which allow smaller pad sizes for the interconnection of the chips but as drawback needs more time and force to form the connection. Therefore the throughput at standard flip chip bonding drops dramatically. The Advanced Chip to Wafer bonding process is a two step process for bonding chips on wafer. Chips are aligned and tacked temporarily to a wafer with high throughput and then all chips are bonded in parallel permanently to the wafer with application of force, temperature and under vacuum or process gases. This process flow enables higher throughput and is therefore well suited for bonding of SiPs of high integrated chips in production.
Development of Epoxy-Silicone Hybrid Polymer and Application for Semiconductor Assembly
Authors: Tomiyoshi Kazutoshi , Kanamaru Tatsuya , Fukui Kenji
Published: March 2009

Semiconductor package style is moving to 3D packaging and thickness become thinner. As a result request to assembly materials is to lower the internal stress for reducing mechanical damage to silicone die. Epoxy-Silicone hybrid technology has been developed for reducing stress of epoxy materials. It has been successfully applied to epoxy molding compound, underfill materials and B-stage die bonding materials as well.
UV Curable Adhesives for Cmos and Ccd Image Sensor Package
Authors: Kenmochi Taro
Published: March 2009

The packages of CMOS & CCD image sensor are widely used to digital still camera, digital video camera, D-SLR (single-lens reflex), surveillance, automotive and others. On those applications, the packages are composed of plastics or ceramics with using UV Sealant1-2). UV curable sealants have contributed to increase reliability and productivity of the assembly line of CCD or CMOS packages. UV sealants necessary have specific characteristics which are air-tight, visco-elasticity and others. Kyoritsu Chemical, we offer those technical data and explanations why those data are essential. We demonstrated necessity of required properties which affected the technical issues to produce packages and proposed causes and countermeasures. We have not only supplied UV curable sealants but have offered total solutions for the production of packages.
Current Evolution of Wafer Thinning and Dicing
Authors: Sullivan Scott M.
Published: March 2009

Over the past few years the backend assembly process has become increasingly complex in order to add more value to products. Two processes that are linked to the changes in assembly are wafer thinning and dicing. Ultra thin stacked die and the implementation of TSVs are driving improvements to the traditional stress relief and fixed abrasive grinding processes. Both CMP (Chemo-Mechanical Polishing) and MCP (Mechano-Chemical Polishing) are being used. Wafer dicing has a number of products and processes behind its evolution. Thin and stacked die with DAF (Die Attach Film) require modifications to existing blade dicing processes. Low-k and copper wafers are requiring the use of lasers to remove materials from the dicing streets. A new and alternative laser dicing process called Stealth Dicing is an enabling technology for a number of products.
Edge Protection of Temporarily Bonded Wafers during Backgrinding
Authors: Bai Dongshun , Zhong Xing-Fu , Puligadda Rama , Burggraf Jurgen , Burgstaller Daniel , Lypka Chris , Verzosa James
Published: March 2009

Edge chipping during backgrinding is one of the main challenges of processing temporarily bonded wafers. The edge chipping may propagate during subsequent process steps and eventually result in yield loss. We conducted a study to compare different methodologies for wafer edge protection during backgrinding, including using pre-thinned carrier wafers, large carrier wafers, edge-trimmed device wafers, and material edge modification. This paper will introduce the metrology developed to quantify edge chipping and compare the results from different protection methods.
Wafer Level SAW RF Filter Packaging With Through Wafer Via Interconnection
Authors: Kweon Youngdo , Park Seungwook , Kim Taehoon , Honh Jupyo , Yang Sijoong , Ha Job , Kim Taeho , Yi Sung
Published: March 2009

This study describes the wafer level 0.8x0.6 mm2 SAW filter (Surface Acoustic Wave Filter) with interconnection via and LiTaO3 (LT)-LiTaO3 (LT) wafer bonding structure. The via formation for interconnection is based on smaller package manufacture. The interconnection via is made by blind via and wafer thinning process. The blind via is formed by sand blasting process or laser drilling process. The eutectic bonding is applied to LT and LT bonding with Au-Sn for device protection and pads interconnection. These processes enable the wafer level saw filter. The result of electrical performance and laser process and sandblaster process for wafer level SAW filter package is discussed
High Volume, Low Cost Multi Die Packaging Using Conductive Polymer Interconnect
Authors: Robinson Marc , Leal Jeff
Published: March 2009

Wire bonding multiple die in a single package, PoP (Package on Package) and, more recently, TSV (thru silicon via) approaches are often considered for small, portable consumer electronic devices. Conductive polymer interconnect is a new approach that provides cost and size advantages for a wide variety of applications. Conductive filled polymer materials are well suited for chip to package and chip to chip interconnect. They are compatible with existing equipment and material sets used in a typical semiconductor assembly facility, and capital costs for adding this capability are relatively low. This method also offers size and cost advantages for single die packaging of image sensors and other die, where there is a requirement to connect to the front side of a die from the backside, without occluding the front surface. Wafer level packaging (WLP) methods and array processing greatly reduce costs, making the technology competitive with traditional wire bond techniques.
Consideration of Gold Thickness in ENIG UBM Application
Authors: Nozu Masahiro , Shibata Tishiaki , Yoshikawa Kazuki , Hashimoto S.
Published: March 2009

In the ENIG UBM formation technology on silicon wafer, even if the same gold thickness is measured by XRF, different solderability can be obtained from ENIG films prepared from different bath conditions. The deposit characteristics of immersion gold film are focused on, and the relation to the solderability is investigated. A uniform film having over 0.02um exhibits excellent solderability, but a film having a vertical growth deposition mechanism or excessive nickel corrosion does not. For the vertical growth deposition, the cause is considered to be the existence of a thin gold thickness area, and as for excessive nickel corrosion, a remaining oxide film and the generation of a P-rich layer can be considered to be the cause for solderability deterioration.
Dippable Paste: A Robust Assembly Material and Enabling Technology
Authors: Sy Hansen G. , Lathrop Richard
Published: March 2009

Despite the tackiness offered by ball attach fluxes, they have failed to prevent ball movement on Solder on Pad (SoP) finishes when the solder protrudes above the solder mask. Dippable solder paste provides the tackiness needed for these adverse situations as well as small solder particles that inhibit ball rolling due to mechanical or convective forces downstream. Also, other pad finishes like OSP has issues with oxidation with partial pad wetting as a common defect. The use of dippable paste has also demonstrated relief with these wetting related issues. The most current application of dippable pastes is in the assembly of stacked BGA's also known as Package on Package (PoP). Although water clean formulations are typical in BGA assembly, PoP assembly typically utilizes no clean formulations. Although tacky flux has been successful in many PoP applications, issues such as coplanarity and package tolerances that require increasing the sphere size during assembly have found benefit from dippable solder paste.
The Destructive Wire Bond Pull Test Methodology for the Ultra Low Loop Application on Thinner Die Package
Authors: Kwon O Dal , Chylak Bob , Yauw Oranna , Lee Kuan Fang
Published: March 2009

The destructive bond pull test is the most common methodology for quality control of the wire bond process optimization on assembly manufacturing. It was introduced in the 1960's and it is described in U.S military specifications. Today, some of the hottest wire bonding processes is System-In-Package (SIP), Package-On-Package (PoP) and 3D package. These processes require lower loop height on thinner die thicknesses. Ultra Low Loop (ULL, <75 mm height) on thinner die (<100mm) utilizes this process. But, the bond pull test specifications for wire pull hook position and minimum wire breaking force are not sufficient to apply for the ULL and thinner die applications necessary to meet today's criteria. This paper is presented in order to give a universal test method of the wire pull test specification and methodology for the ULL on thinner die application and optimization. It will extend the reliability and quality control of advanced packaging.
Cu2 Process Development For Cost Effective SOT Package
Authors: Soh Yuen Chun , Lim Tian Hing
Published: March 2009

Commodity discrete package SOT faces tremendous cost reduction pressure among integrated chip & packaging manufacturers. Low cost per piece is desired to create better gross margin. Cost analysis found that direct materials (leadframe, bonding wire, compound etc) contributed >50% package cost per piece. Therefore, one of the rock bottom ideas will be exploring on bare copper leadframe with copper wire bonding. Current SOT package material sets are NiFe42, silver plated leadframe bonded with gold wire. This could easily reduce leadframe & bonding wire cost by 50%. This paper will discuss details feasibility study & development of Cu2 (bare Cu leadframe + Cu wire) backend process on SOT. Material sets selection, technical challenges understanding, equipment setup, feasibility study & design of experiment, failure analysis etc are performed to assess process manufacturability. Meanwhile, thermo-mechanical & moisture related reliability assessment (HTS/TC/PCT etc) also will be performed prior to official qualification & customer build.
Enabling Technology in Thin Wafer Dicing
Authors: Van Borkulo Jeroen , Evertsen Rogier , Hendriks Rene
Published: March 2009

Driven by IC packaging and performance requirements, the die separation process is facing three main trends: Thinner wafers, stronger die and non-Silicon materials. Memory capacity increase, multichip functions and continuous package miniaturization require ultra thin wafer dicing. For IC performance increases, low-K material and other materials (top layers and even substrates) require different dicing methods for efficient and delamination free dicing processes. It is demonstrated that conventional blade dicing has reached the end of its capabilities and does not meet the separation requirements. Particular thin wafer development and the use of Die Attach Film (DAF) have added challenges and restrictions to the dicing technologies. Laser dicing processes have developed and have become the preferred dicing technology. This paper will discuss the various laser dicing technologies introduced for the different segments and will address the specific performances. Using a multibeam laser dicing process add significant advantages to the different solutions.
Growth and Electrical Characterization of Horizontally Aligned CNTs
Authors: Santini Claudia , Cott Daire J. , Romo Negreira Ainhoa , Riva Sanseverino Stefano , De Gendt Stefan , Vereecken Philippe M.
Published: March 2009

Nickel catalyst nanoparticles acting as nucleating seeds for carbon nanotube (CNT) growth were selectively deposited on the sidewalls of titanium nitride (TiN) electrodes by electrochemical deposition (ECD) from a Ni2+ electrolyte solution. Horizontal aligned CNTs were grown selectively from the sidewalls of these TiN electrodes forming a bridging CNT contact between the electrode gaps. Current-voltage measurements demonstrated this could be a promising technique towards nanoscale interconnections and nanoelectronic devices with resistance values for the bridging CNTs as low as 300Ω.
Fine Pitch Transfer and Join (T&J) From MCM to 3DI
Authors: Yu Roy R.
Published: March 2009

Over the last three decades computational performance propelled forward at a breath taking pace. This was enabled due to the introduction of CMOS technology, strict application of its scaling rules, and system innovation. The industry followed "Moore's Law" doubling transistor count every 18 month. In addition the design community drove innovations like on-chip caching, pipelined executions, and multi-core systems to deliver the required performance. All this time the processor chip could be considered to be flat which put increasing pressure on chip size to accommodate all its components. To continue the performance trend, however, it is conceivable to spread the components of the microprocessor chip over more than one active layer to maintain their close proximity. The device 3D integration (3DI) has the potential to achieve such goals to the next level. 3DI can be visualized as vertically stacked multi-chip-modules (MCM-D) with through-Si-via (TSV) integrated with all Si devices. The fine pitch transfer join (TJ) technology is well developed and suited for such integrations. This paper will review the evolution of the TJ technology in fine pitch device connection from it's early MCM applications to the more recent all-Si fine pitch 300 mm wafer-level connections.
Evaluation of InAs QWFET for Low Power Logic Applications
Authors: Chang Edward Yi , Kuo Chien I , Hsu Heng Tung , Miyamoto Yasuyuki , Chang Chia Ta , Wu Chien Ying
Published: March 2009

An eighty nanometer gate length InAs quantum well field effect transistors has been fabricated and the digital characteristics were evaluated. The devices show a drain-source current of 1015 mA/mm and a peak gm of 1920 mS/mm at VDS = 0.5 V. The fT and fmax are 340 GHz and 220 GHz at VDS = 0.4 V, respectively. A low delay time (CtotalV/ION) of 0.54 ps was also achieved. These excellent results indicate the InAs devices are the great potential option for the future low-power logic applications at post-Si CMOS technology.
Translucent Polymer Solar Cells
Authors: Ng Ging Meng , Vijila Chellappan , Goh Wei Peng , Zhu Fu Rong
Published: March 2009

The recent developments on the construction of translucent cathodes for the application of tandem or multi-junction organic solar cells are reviewed in this report. The translucent cathode plays a major role in determining the efficiency of translucent solar cells by controlling the intensity of incident light absorption at the photoactive layer of each cell. As a result, there are varieties of translucent cathodes based on conductive polymer, thin metallic layer, and transparent conducting oxides (TCO) have been developed by various research groups. A translucent cathode based on a combination of thin metallic (i.e. calcium and silver) and transparent conductive oxide layers (indium tin oxide (ITO)) is developed in our group and the advantages of this translucent cathode for organic solar cell application are presented. In addition, the experimental results obtained from polymeric solar cells, based on poly(3-hexylthiophene) (P3HT): 1-(3-methoxycarbonyl)-propyl-1-phenyl-(6,6)C61 (PCBM) blends, and ITO-based translucent cathode, are also presented.
PV Efficiency Improved Large-area Dye-sensitized Solar Cells
Authors: Yin Haiyou , Zhang Tianshu , Wang Xu , Liu Lifeng , Wang Yi , Liu Xiaoyan , Kang Jinfeng
Published: March 2009

Several techniques including current-collecting metal fingers and double-layer TiO2 electrode were applied to improve the conversion efficiency of large area dye-sensitized solar cells (DSSCs). Silver paste was used to fabricate the current-collecting metal fingers on the fluorine-doped tin oxide (FTO) glass substrate by screen-printing process. Then a single- or double-layer TiO2 electrode was fabricated by using screen-printing process. The double-layer TiO2 electrode consists of a transparent TiO2 layer and a light-scattering TiO2 layer. Results showed that applying the current-collecting metal fingers and double-layer TiO2 electrode could effectively improve the conversion efficiency. The conversion efficiency of 5.89% was achieved in a DSSC module with an area of 50mm×50mm by using the current-collecting metal finger cell of 45mm×3.5mm and double-layer TiO2 electrode under global air mass 1.5 condition.
Thin Film InP Epitaxy on Si (001) Using Selective Aspect Ratio Trapping
Authors: Li Jizhong , Bai Jie , Hydrick Jennifer M. , Fiorenza James G. , Major Cheryl , Carroll Mark , Shellenbarger Zane , Lochtefeld Anthony
Published: March 2009

High quality InP thin films have been demonstrated in SiO2 trenches on silicon via Aspect Ratio Trapping (ART), whereby defects arising from lattice mismatch (~8%) are trapped by laterally confining sidewalls. Double-buffer layers and two-step ART growth processes have been employed to trap vertical threading dislocations originating at InP/Si interface. InP film quality and optical properties have been analyzed using SEM, TEM and room temperature photoluminescence. Full trapping of dislocations has been demonstrated for trenches up to 400 nm in width without the additional formation of defects at the sidewalls above 500 nm initial growth. This approach shows great promise for the integration of III-V materials onto silicon.
Sub-micrometer Organic Field Effect Transistors
Authors: Shang Liwei , Liu Ming , Ji Zhouyu , Liu Ge , Liu Xinghua , Liu Jiang , Wang Hong
Published: March 2009

Pentacene organic field effect transistors with a series of sub-micrometer channel have been fabricated and characterized. Source and drain metal electrodes was made by electron-beam lithography and lift-off process. Image reversal photo resist was used to make integrated mask to pattern the organic semiconductor film to reduce the off-state current. And thiol treatment was applied on gold electrodes to modify their surface energy and improve the charge carrier injection. All the devices can behavior as typical p-type transistor, and have obvious saturation. Using electrode and dielectric surface treatment, device performances have significant improvement. All of the performances, including mobility, threshold voltage and on/off current ratio will change with the channel length decreasing because of the low quality interface between the OSC and dielectrics.
Agglomeration of Vacancies into Voids and Oxide Particles in Silicon Crystals
Authors: Voronkov Vladimir V.
Published: March 2009

The vacancies, incorporated into a growing crystal, agglomerate by two parallel paths - producing voids and oxide particles. The voids dominate if the vacancy concentration C0 is high while the oxide particles dominate at lower C0. The void and particle properties are simulated assuming that the particles are thin plates. The initial single-octahedral void shape can later change to double-octahedral, due to oxygen film adsorbed at the void facets. By a similar mechanism, platelet shape is developed in nitrogen-doped crystals.
Atomistic-to-Continuum Modeling of Defect-Related Phenomena in Silicon Crystals
Authors: Sinno Talid , Kapur Sumeet S.
Published: March 2009

Continuum process modeling of point defect and impurity aggregation during silicon crystal growth and wafer annealing has led to significant contributions toward understanding and improvement of industrial processes. Key inputs to these models are thermophysical properties of point defects and their clusters, which may be strong functions of temperature and cluster size. In this paper, a theoretical framework is presented for probing the high-thermodynamic properties of vacancy and self-interstitial clusters in crystalline silicon at elevated temperature. In particular, configurational and vibrational entropy are shown to be significant in both types of defect clusters. In both cases, configurational entropy leads to the existence of a wide distribution of possible cluster configurations that collectively lowers the free energy of formation relative to the energetic ground state configuration. Moreover, certain self-interstitial cluster sizes are additionally stabilized by configurations that possess anomalously high vibrational entropy.
Challenges in Wafering Processes for Semiconductor and Solar Wafers
Authors: Erk Henry
Published: March 2009

The transition from 50 to 32nm silicon technologies will place strict requirements on semiconductor wafer flatness and nanotopography. Site flatness and shape capability at the edge must improve, as well as the edge characteristics (finish and shape) and quality (damage free). As diameter increases from 300 to 450mm, thickness does not scale with wafer diameter leading to a relatively less rigid wafer. This adds additional burden to the task of capability improvement. To be competitive with alternative energy technologies solar wafer manufacture is focused on cost reduction and capability improvement to enable cell-processing optimization. The challenge is to cut thinner wafers with reduced depth of damage, lower TTV and with no micro-cracks. Slicing kerf reduction and abrasive / silicon recovery are options to further reduce cost.
Prediction of Melt-Crystal Interface Shape and Melt Convection in a Large-scale CZ-Si Growth System Using RANS and LES Methods in Global Simulation.
Authors: Liu Xin , Liu Lijun , Li Zaoyang , Wang Yuan , Kakimoto Koichi
Published: March 2009

Global simulations were performed for a large-scale CZ-Si growth system, in which three models were tested to predict the turbulent melt flow. The three turbulence models are the standard turbulence model using wall functions at solid boundaries, a modified two-layer turbulence model in RANS method and the standard Smagorinsky SGS model in LES method, respectively. The comparison of the simulation results obtained with these different models showed that each turbulence model has its own features in prediction of the melt convection and the melt-crystal interface shape in a large-scale CZ-Si growth system.
Advances in the Understanding of Oxide Precipitate Nucleation in Silicon
Authors: Kissinger Gudrun , Kot Dawid , Akhmetov Vladimir , Sattler Andreas , Mueller Timo , Von Ammon Wilfried
Published: March 2009

The influence of vacancy supersaturation installed by RTA pre-treatments in CZ silicon wafers on oxide precipitate nucleation was investigated in the temperature range 700-1000 {degree sign}C. Precipitation is enhanced at 800 {degree sign}C and increases with increasing vacancy concentration. Getter efficiency tests for Cu and Ni have shown that the threshold value of the normalized inner surface is shifting to higher values for increasing RTA temperature. This can be explained by a morphological change of the oxide precipitates with increasing vacancy concentration from plate-like to spherical shape.
Oxygen Precipitation in Heavily Phosphorus-doped Czochralski Silicon
Authors: Zeng Yuheng , Yang Deren , Ma Xiangyang , Zhang Xinpeng , Lin Lixia , Que Duanlin
Published: March 2009

Oxygen precipitation in heavily phosphorous (P)-doped Czochralski silicon (CZ-Si) subjected to the ramping or two-step anneals was investigated. It was revealed that the grown-in oxygen precipitates exerted significant effect on oxygen precipitation behaviors and then resulted in distinctive oxygen precipitation for the wafers form various positions of the ingot. Moreover, it was found that both the seed and tang-end wafers processed significantly intense nucleation at 650 oC without the influence of grown-in oxygen precipitates. It was considered that the heavily P-doping introduced phosphorus related precipitation at 650 oC. When the annealing temperature increased, the capability for nucleation of oxygen precipitation by heavily P-doping would be gradually weakened but the one by oxygen clustering became pronounced. In this case, it was understandable that the tang-end wafer processed higher density of oxygen precipitates than the seed-end wafer at around 750 oC, while a lower one at 1000 oC.
Simulation Analysis of Point Defects in Silicon Ingot during Unidirectional Solidification Process for Solar Cells
Authors: Chen Xuejiang , Nakano Satoshi , Liu Lijun , Kakimoto Koichi
Published: March 2009

A transient global model was used to obtain the solution of thermal field within the entire furnace of a unidirectional solidification process. The melt-solid interface shape was obtained with a dynamic interface tracking method. And then, based on the global solution of heat transfer, influence of growth rate Vg, temperature gradient G and ratio Vg/G on point defects were analyzed. Finally, several different melt-solid interface shapes were obtained by using different solidification times. Then, the effects of solidification times on ratio Vg/G and point defects were also studied.
Distributions of Light Elements and Their Precipitations Grown by Unidirectional Solidification Method in Multicrystalline Silicon for Solar Cells
Authors: Matsuo Hitoshi , Hisamatsu Sho , Kangawa Yoshihiro , Kakimoto Koichi
Published: March 2009

We investigated the relationship between the formation of small grains and distribution of precipitates such as Si3N4 and SiON in a multicrystalline silicon ingot grown by the unidirectional solidification method. Si3N4 precipitate was mainly observed inside the small grain region, while SiON was mainly precipitated outside there. We found that SiON started to precipitate prior to formation of Si3N4 precipitates. Therefore, precipitation of SiON prior to precipitation of Si3N4 plays a key role in the formation of small grains.
Numerical Simulation of Thermal Distribution during the Directional Solidification of Polycrystalline Silicon Ingot
Authors: Wu Dan , Sun Weizhong , Hao Qiuyan , Zhao Jianguo , Liu Caichi
Published: March 2009

Directional solidification is one of the key technologies of multi-crystalline silicon ingots in commercial photovoltaic market. During the directional solidification process, the changes of technologic parameters will influence the temperature gradient and the shape of the solid-liquid interface, which determine the qualities of polycrystalline ingots. In this paper, the relationship between the crucible lower rates with the temperature gradient and the shape of the solid-liquid interface were studied by numerical simulations. The results showed that when the crucible lower rate is less than 60mm/h , the temperature gradient is getting larger with the increase of crucible lower rate, and the shape of solid-liquid interface remains convex. But when the crucible lower rate is higher than 60mm/h, the shape of solid-liquid interface changes into concave.
Silicon Etching Technology Using Inductively Coupled Plasma Suitable for Fabrication of Silicon Nanowires and Ring Resonators
Authors: Zhou Jingtao , Shen Huajun , Zhang Huihui , Liu Xinyu
Published: March 2009

Silicon-on-insulator (SOI) is an attractive platform for single chip photonic integration. Silicon nanowires fabricated by SOI substrate are fundamental components such as ring resonators in the optoelectronics integrated circuits. High performance of these devices requires silicon nanowires have vertical and smooth sidewalls. In this paper, we report the fabrication of silicon nanowires with vertical and smooth sidewalls using SF6/C2H4/Ar based inductively-coupled-plasma (ICP) etching, Ring resonator with 200nm gap was fabricated. This technology is suitable for fabrication of planar photonic integrated components and circuits.
The Synthesization of Si Nanocrystals Embedded in HfO2 Matrix by Electron Beam co-Evaporation Technique
Authors: Li Weilong , Jia Rui , Chen Chen , Liu Ming , Li Hao F. , Zhu Chen X. , Long Shibing
Published: March 2009

Silicon nanocrystals synthesized by electron beam co-evaporation (EBCE) of Si and HfO2 mixture are studied. HfO2 and Si powder are uniformly mixed together in certain proportion. The mixed Si & HfO2 powder is evaporated by electron beam evaporation technique. Then the SRO thin films are annealed at different temperatures at 2 hours in N2 ambient to synthesize Silicon nanocrystals. For the sample annealed at 1050 ° at 2 hours, silicon nanocrystals with different size between 3 nm to 5 nm, the mean diameter of 4.0 nm, and the density of 3×1012 cm-2 are evidently observed by high resolution transmission electron microscopy (HRTEM). Then the Raman scattering and photoluminescence spectra arising from Silicon nanocrystals are further confirmed the above result. In addition, the samples annealed at 900 ° for 2 hours to 8 hours are carefully studied by Raman spectra. This way of preparing SRO thin films and Si NCs has unique advantage and is controllable and flexible
Inhibition of sympathetic N-type voltage-gated Ca2+ current underlies the reduction in norepinephrine release during colitis
Authors: Motagally Mohamed A. , Neshat Shadia , Lomax Alan E.
Published: March 2009

Inflammatory bowel diseases (IBD) are associated with altered neuronal regulation of the gastrointestinal (GI) tract and impairment of norepinephrine release from sympathetic varicosities. The sympathetic innervation of the GI tract modulates motility, blood flow, and secretion, and therefore defective norepinephrine release may contribute to symptom generation in IBD. Accordingly, our aim here was to utilize the mouse model of dextran sulfate sodium (DSS; 5% wt/vol) of IBD to determine how norepinephrine release is reduced during GI inflammation. We hypothesized that the inflammation-induced reduction in norepinephrine release was due to inhibition of voltage-gated Ca2+ current ( ICa) in prevertebral sympathetic neurons. We compared [3H]norepinephrine release in the colon and jejunum and ICa amplitude in superior mesenteric ganglion (SMG) neurons from control mice and mice with DSS-induced colitis. Changes to voltage-gated Ca2+ channels were investigated by fura 2-AM Ca2+ imaging, perforated patch-clamp electrophysiology, and real-time PCR. Depolarization-induced norepinephrine release from the inflamed colon and uninflamed jejunum was significantly impaired in mice treated with DSS, as was depolarization-induced Ca2+ influx in SMG neurons. Colitis reduced ICa in SMG neurons by inhibiting ω-conotoxin GVIA (300 nM)-sensitive N-type Ca2+ channels. The ω-conotoxin GVIA-sensitive component of norepinephrine release was significantly smaller in the colon during colitis. The inhibition of ICa was accompanied by a decrease in mRNA encoding the Ca2+ channel alpha subunit (CaV 2.2) and a rightward shift in the voltage dependence of activation of ICa. These findings suggest that DSS-induced colitis attenuates norepinephrine release in the colon and jejunum due to inhibition of N-type voltage-gated Ca2+ channels. This may contribute to functional alterations in both inflamed and uninflamed regions of the GI tract during inflammation.
Distinct contributions of CD4+T cell subsets in hepatic ischemia/reperfusion injury
Authors: Kuboki Satoshi , Sakai Nozomu , Tschöp Johannes , Edwards Michael J. , Lentsch Alex B. , Caldwell Charles C.
Published: March 2009

Helper T cells are known to mediate hepatic ischemia/reperfusion (I/R) injury. However, the precise mechanisms and subsets of CD4+T cells that contribute to this injury are still controversial. Therefore, we sought to determine the contributions of different CD4+T cell subsets during hepatic I/R injury. Wild-type, OT-II, or T cell receptor (TCR)-δ-deficient mice were subjected to 90 min of partial hepatic ischemia followed by 8 h of reperfusion. Additionally, wild-type mice were pretreated with anti-CD1d, -NK1.1, or -IL-2R-α antibodies before I/R injury. OT-II mice had diminished liver injury compared with wild-type mice, implicating that antigen-dependent activation of CD4+T cells through TCRs is involved in hepatic I/R injury. TCR-δ knockout mice had decreased hepatic neutrophil accumulation, suggesting that γδ T cells regulate neutrophil recruitment. We found that natural killer T (NKT) cells, but not NK cells, contribute to hepatic I/R injury via CD1d-dependent activation of their TCRs, as depletion of NKT cells by anti-CD1d antibody or depletion of both NKT cells and NK cells by anti-NK1.1 attenuated liver injury. Although regulatory T cells (Treg) are known to suppress T cell-dependent inflammation, depletion of Treg cells had little effect on hepatic I/R injury. The data suggest that antigen-dependent activation of CD4+T cells contributes to hepatic I/R injury. Among the subsets of CD4+T cells, it appears that γδ T cells contribute to neutrophil recruitment and that NKT cells directly injure the liver. In contrast, NK cells and Treg have little effects on hepatic I/R injury.
Role of the perforin/granzyme cell death pathway ind-Gal/LPS-induced inflammatory liver injury
Authors: Kuhla Angela , Eipel Christian , Abshagen Kerstin , Siebert Nikolai , Menger Michael D. , Vollmar Brigitte
Published: March 2009

Cytotoxic T lymphocytes and their granule components, such as perforin and granzyme, play an important role in the defense of hepatic infections caused by different pathogens. Moreover, it has been shown in vitro that hepatocytes can initiate cell death via a perforin-dependent mechanism. Although it is well known that hepatocellular apoptosis in d-galactosamine/lipopolysaccharide (d-Gal/LPS)-associated liver failure is mediated by TNF-α-dependent Fas/FasL cytotoxicity, there is no information on the role of perforin-mediated mechanisms in vivo. Therefore, we studied whether the cytolytic perforin/granzyme pathway contributes to the d-Gal/LPS-associated hepatotoxicity. Perforin knockout (Pko) mice showed significantly higher hepatic TNF-α and IL-6 mRNA expression as well as plasma TNF-α and IL-6 concentrations within the first hour upon d-Gal/LPS challenge compared with perforin wild-type (Pwt) mice. At 6 h upon d-Gal/LPS challenge, Pko mice further presented with higher transaminase release and onconecrotic tissue damage, whereas hepatocellular apoptosis and caspase-3 cleavage remained unaffected by the perforin deficiency. Pretreatment with a recombinant human TNF-α receptor fusion protein attenuated necrotic and apoptotic tissue damage and reduced plasma transaminase activities as well as cytokine release, thereby preventing acute liver failure in Pko mice as effectively as in Pwt mice. These data do not only confirm the significance of TNF-α as distal mediator of hepatic injury in this model but simultaneously reveal a contribution of a perforin-dependent immunoregulation, limiting the d-Gal/LPS-induced overwhelming cytokine release and onconecrotic tissue injury.