Layer Configurations for Al-Ge Eutectic Wafer Bonding
Authors: Visker Jakob , Peng Lan , Kang Shuo , Vereecke Bart , Haspeslagh Luc 
Published: December 2020

Introduction

Heterogeneous integration between CMOS and MEMS devices can be realized by using Al-Ge which are compatible materials in both fabrication environments. Al is widely used in the CMOS-industry and does not involve any contamination risk in contrast to other eutectic systems like Au-Si[1]. Si-Ge is also widely used to augment transistor switching speed [2]. The eutectic reaction for Al-Ge takes place around 420oC, which is CMOS-compatible[3], [4].

The limitation of the Al-Ge system is the need for removal of the surface oxides. It was previously reported that Ge can be deposited on top of Al using evaporation or sputtering without vacuum-break [4]. This prevents oxide formation on the Al layer. By contrast, GeO2 is easy to remove with a dilute-HF dip [5]. The current work investigates using a single layer or dual layers of Al and Ge for bonding. Depositing single layers is advantageous since it enables patterning by dry etch and avoids the need for a lift-off process. The layers are deposited in separate tools, so oxide formation is expected. The effect of the presence of the oxide layers will be investigated.

Method

Al and Ge layers are deposited on 200 mm wafers with 500 nm thermal oxide. Thicknesses are matched to eutectic composition. (300 nm Ge and 500 nm Al) The wafers are bonded and then analyzed using scanning acoustic microscopy (SAM) and cross-sectional scanning electron microscopy (X-SEM).

Results and discussion

The first group of wafers are prepared with a single layer of Al and Ge on either substrate while the second group has a double layer of either Al on top of Ge or Ge on top of Al. All wafers are joined by using forming gas pre-treatment at 390oC, 15 min of solid state inter-diffusion at 410oC followed by bonding for 30 min at 450oC with 25 kN of force. The bonding recipe is illustrated in figure 1. The wafers are analyzed using SAM and X-SEM. The SAM results are shown in figure 2.

In figure 2.a the result of the single layer configuration bond is visible. Micro-voids are visible in the center. The outer region has larger voids. The X-SEM image of the bonding interface confirms the presence of small voids, as shown in figure 3. The formation of the eutectic in the single layer configuration is only possible where the two wafers are in contact. Non-uniformity and roughness could be preventing full contact and result in voids.

The SAM result of the Al on top of Ge double layer configuration bond is shown in Figure 2.b, the outer region is mostly unbonded. The bonding interface is clearly visible on the X-SEM image, as shown in figure 4. There is no interface between the Al and the Ge layer visible. The native oxide on top of the Al layer could be preventing the two sides from mixing but the Ge oxide layer does not seem to hinder the eutectic formation.

The SAM image of the Ge on top of Al configuration bond is shown in figure 2.c. The wafer looks well bonded. X-SEM reveals a triple layer structure. (see figure 5) The bond interface is clearly visible and additionally two thinner interfaces are visible. These could be the remainder of the native Al-oxide.

Conclusion

Three configurations of Al-Ge eutectic bonds were investigated using SAM and X-SEM. The highest bond uniformity is obtained with Ge being the top layer prior to bonding. The presence of the oxide layers could be preventing the mixing of the eutectic across the bonding interface. In this regard especially the Al-oxide seems problematic.

[1] B. Pathangey, L. D. McCarthy, and D. C. Skilbred, “Effect of metal contaminants in pre-gate oxide cleans for sub-100-nm devices,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 4, pp. 631–638, Dec. 2005, doi: 10.1109/TDMR.2005.861161.

[2] M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, “Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 97, no. 1, p. 011101, Jan. 2005, doi: 10.1063/1.1819976.

[3] H. Takeuchi, A. Wung, X. Sun, R. T. Howe, and T.-J. King, “Thermal Budget Limits of Quarter-Micrometer Foundry” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2081–2086, Sep. 2005, doi: 10.1109/TED.2005.854287.

[4] A. Hilton and D. Temple, “Wafer-Level Vacuum Packaging of Smart Sensors,” Sensors, vol. 16, no. 11, p. 1819, Oct. 2016, doi: 10.3390/s16111819.

[5] B. Onsia et al., “The Influence of Wet Treatments on the Germanium Wafer Surface,” Solid State Phenom., vol. 103–104, pp. 27–30, Apr. 2005, doi: 10.4028/www.scientific.net/SSP.103-104.27.

Figure 1