(Invited) Optimal Target Functions for Epitaxy in New Channel Applications Such As Horizontal Gate-All-Around (h-GAA) Device Architectures Using Nano-Sheets or Nanowires
Authors: Bauer Matthias 
Published: February 2020

Continuation of Moore’s law, an observation of the economics and technological progress in semiconductor manufacturing, is becoming increasingly challenging due to many factors, since it is getting harder to advance the 3 technological P’s and the economic P: Performance/Watt, Precision, Perfection and Price/Transistor [JY Chen, Proc. of SPIE Vol. 8522 (2012) 852202]. Epitaxy allows precise control of the critical dimension(s) in new channel applications (h-GAA device architectures and epitaxially defined FinFETs), directly impacting Device Performance and Yield (DPY) and Cost of Ownership (CoO). "Target functions" include: (1) Uniformity and repeatability (perfection & precision) of thickness and composition, (2) abruptness of SL stack (precision & perfection), (3) crystalline perfection (absence of gas phase nucleation potentially causing defects), (4) Cost of Ownership (CoO) including precursor conversion (determining precursor consumption and waste) and throughput (TP) {wph=60min/(toverhead + tprocess)}, and (5) only applicable to self-aligned selective epitaxial growth (SEG) processes on structured topographies: (a) selectivity, (b) macro- and micro loading, (c) doping level & distribution (d) different shapes: faceting vs. conformality (perfection). Tight control of the critical dimension (epitaxial thickness) its distribution WiW (uniformity, perfection) and WtW (repeatability, precision) are essential for high volume manufacturing [WS Yoo, RTP’06, pp. 159-175].

Analyzing growth rate dependence on temperature (T) with an Arrhenius plot, two distinct growth regimes can be identified: (a) In the ‘low-T’, reaction rate (kinetic) limited regime growth rate is limited by the density of ‘free’ surface sites (1-σH/Cl) available for precursor absorption, thus by the rate of H2/HCl desorption from the surface. Precursor is offered in abundance, conversion rate is low, growth is slow and film uniformities are strongly correlated with thermal uniformity, making T-control (WiW & WtW) the single most important item. {Massive and slow hot wall systems operating in thermal equilibrium provide such T conditions, but challenges include (i) deposit build-up on hot quartz tubes, (ii) sub-optimal pre-clean strategy and difficult Q-time control may result in defective films and degraded particle performance.} (b) In the ‘high-T’, mass flow limited regime growth is fast and only limited by precursor supply and is quite in-sensitive to T variations/excursions (WiW & WtW). High precursor conversion accompanied with depletion of reactants, as they flow over hot surfaces, mandates wafer rotation and a ‘favorable’ flow pattern in order to achieve good WiW uniformities.

Precision & Perfection (impacting DP&Y): The interface abruptness of the as grown SiGe/Si super-lattice (SL) is mainly controlled by Ge surface segregation, rather than bulk inter-diffusion. Surface segregation, a thermally activated exchange reaction between surface and sub-surface atoms, is governed by (a) phonons (lattice vibrations => growth temperature), (b) ‘burying rate’ (time constant => growth rate) and (c) H/Cl surface coverage (acting as surfactants). Process flows minimizing channel material loss (thinning and tapering) require: (a) SL stacks with sharp ‘as-grown’ alloy transitions and sufficient material contrast [Δ
Ge], (b) well controlled thermal budget (T*t) and (c) a wet or dry etch chemistry (process) with high etch rate selectivity for sacrificial layer removal. Conversely, (i) imperfect alloy transitions, (ii) excessive thermal budget causing inter-diffusion (or even strain relaxation in metastable strained SiGe layers) and (iii) poor etch rate selectivity will cause deleterious channel thickness variations ultimately leading to increased device variability. Requirements for crystalline perfection of channel materials are far more stringent compared to S/D SEG. The tolerance for crystalline defects is virtually zero, requiring strict suppression of any gas phase nucleation or excessive reactor wall coating.

Cost of Ownership (CoO): Precursor conversion (and related precursor consumption = cost) speaks for itself. Reducing precursor flow and reducing deposition on hot parts, other than the wafer itself, yields cleaner processing (and likely fewer particles) and might allow reducing intensity and/or frequency of chamber cleaning time. Throughput (TP) is impacted by both, overhead and processing time, thus isothermal processing (or within a small T range for low-T chamber clean, wafer load, pre-epi surface treatment, epitaxial growth and unload) minimizes timefor T ramps and T stabilization. Thermal budget is reduced, thanks to low-T pre-epi surface preparation and reduced processing time (faster growth).

Strategies to meet all essential value criteria have been developed and experimentally demonstrated for a single wafer tool. Epitaxial process conditions have been studied over a quite wide range of process conditions. Repeatability (precision) of SiGe & Si thickness, [Ge] and its WiW distributions (perfection) as well as crystalline perfection have been demonstrated using Spectroscopic Ellipsometry and Light Scatterometry (SP3, <32nm defect size). Composition & thickness are controlled by HR-XRD. STEM is used to assess abruptness (perfection) of SiGe/Si SL interfaces and layer thicknesses (precision).