bluuebunny/crossref_metadata_2025 huggingface dataset:
Electrical Characterization of Lateral 4H-SiC MOSFETs in the Temperature Range of 25 to 600 °C for Harsh Environment Applications
Authors: Daves W. , Krauss A. , Häublein V. , Bauer A. J. , Frey L.
Published: October 2015

In this work, we investigated lateral 4H-SiC-based metal oxide field-effect transistors (MOSFET) for the use as transducers in harsh environments. Inversion channel (IC) as well as buried channel (BC) MOSFETs were fabricated by means of different epi-layer doping and ion implantation. Stacked SiO2/Si3N4 dielectrics and a sputtered Ti/TaSix/Pt contact metallization were used. The devices were characterized by means of current-voltage and capacitance-voltage testing up to 600 °C. The thermal stability of the transistor characteristics and the factors limiting the MOSFET mobility were analyzed and discussed. The effective barrier height for Fowler-Nordheim tunneling extrapolated at high fields (> 7 MV/cm) decreased of about 1 eV between 25 and 500 °C. At high temperatures, the Poole-Frenkel contribution to the leakage current became significant already in the mid-field range. The prolonged operation of MOSFETs at 500 °C indicated that sufficient MOS reliability can be achieved only by a minimization of the necessary gate bias. The lifetime was ~25 h when a stress field of 3.5 MV/cm was applied at 500 °C. When the stress field was reduced to 0.5 MV/cm, a lifetime > 300 h was found. A degradation of the drain current was observed during the prolonged operation independently of the biasing conditions. This was attributed to a degradation of the ohmic contacts.
High-Temperature, High-Power Performance of Ceramic Filter Capacitors
Authors: Bridger K. , Cooke A. , Kohlhafer D. , Strite R. , Schulze W. , Arrasmith S. , Weigner J. , Duva F.
Published: October 2015

Power conversion electronics in military vehicles and aircraft are currently experiencing high temperatures and future generations will see these temperatures rise even higher. The high temperatures arise not only from the environment but also from high power dissipation in the components themselves. Capacitors can occupy almost 50% of the real estate in some power converters and these capacitors are subjected to very high currents at high frequencies in dc-dc converters or 60-Hz 120 VAC in the output stage of an inverter. Dissipation resulting from the high power levels can lead to internal capacitor temperatures at least 50°C above their ambient and so for military hybrid electric vehicles (HEVs) capacitors are expected to reach at least 150°C and possibly 200°C, while future aircraft component temperatures are expected to exceed 250°C. A new family of high-temperature dielectrics based on sodium bismuth titanate has been developed by these authors and capacitors are now available from Novacap under the trade name “Type H” or “Type HA”. This paper examines the high-frequency, high-current and 60-Hz, 120-VAC performance of these capacitors including an estimate of internal heating. The primary operating temperature range studied is −40 to +150°C, although some higher temperature data are also presented.
Ceramic Capacitors and Stacks for High Temperature Applications
Authors: Gurav Abhijit , Xu Xilin , Magee Jim , Bultitude John , Ashburn Travis
Published: October 2015

There is a growing need for ceramic capacitors for applications at temperatures of 150°C or above, such as electronics for down-hole drilling, geothermal energy generation and power electronics. In traditional X8R ceramic capacitors (EIA specification, TCC or ΔC/C within ±15% between −55°C and +150°C compared that at 25°C), the dielectric material is designed for applications up to 150°C. However, at temperatures above 150°C, the X8R capacitors typically suffer from degradation of reliability performance and severe reduction in capacitance, especially under DC bias conditions. Recently, a Class-I C0G dielectric has been developed using Nickel electrodes for high temperature application up to 200°C and beyond. Due to its linear dielectric nature, this material exhibits highly stable capacitance as a function of temperature and voltage. Multi-layer ceramic capacitors (MLCC) made from this material can be qualified as X9G with robust reliability. This paper will report electrical properties and reliability test data on these Class-I C0G ceramic capacitors at high temperatures at 150–200°C and above along with a discussion of possible mechanisms behind the robust reliability of this high temperature dielectric.
Die Attach of Power Devices Using Silver Sintering – Bonding Process Optimisation and Characterization
Authors: Buttay Cyril , Masson Amandine , Li Jianfeng , Johnson Mark , Lazar Mihai , Raynaud Christophe , Morel Hervé
Published: October 2015

Silver sintering is becoming an attractive alternative to soldering, especially for high temperature applications. Indeed, the increase in operating temperature requires new soldering alloys with even higher melting points. Silver sintering, on the contrary, is a solution which only require moderate (<300°C) process temperature.

In this paper, we present the implementation of a die attach technique based on sintering of some silver paste, with a special focus on the practical considerations. A good quality bond can be achieved by paying attention to the assembly process.
Development of a Silicon Nitride High Temperature Power Module
Authors: Palmer Michael J. , Johnson R. Wayne , Motalab Mohammad , Suhling Jeffrey , Scofield James D.
Published: October 2015

Silicon nitride (Si3N4) offer potential advantages as a substrate for high temperature power packaging. Si3N4 has higher fracture strength than alumina and aluminum nitride. The coefficient of thermal expansion (CTE) of Si3N4 is ~3 ppm/°C and the thermal conductivity ranges from 30–50W/m-K. Active metal brazed Cu-Si3N4 substrates are commercially available for power modules. However, the large mismatch in CTE between Si3N4 and Cu results in ceramic fracture and delamination with the wide temperature thermal cycling ranges encountered in high temperature applications. In this work Cu-Carbon and Cu-Mo metal matrix composites have been investigated to reduce the CTE mismatch. The process details are presented along with finite element modeling of the proposed structure. Ultimately, the proposed structure was unsuccessful.
Factors influencing microstructural evolution in nanoparticle sintered Ag die attach
Authors: Paknejad S.A. , Mansourian A. , Noh Y. , Khtatba K. , Van Parijs L. , Mannan S.H.
Published: October 2015

The behaviour of sintered silver die attach at high temperature has been investigated. Assemblies were made by sintering a commercially available paste composed of Ag nanoparticles with zero applied pressure on the die. The morphology of the cross sectioned surface of assemblies remains stable even at temperatures of up to 400 °C. This behaviour remained consistent even inside vacuum or after acid cleaning of the free surface. In contrast, the same sintered Ag material in the interior of a joint or sintered under a glass cover slip showed rapid microstructural changes even at 300 °C. These samples were investigated using an optical microscope to analyse the changes in the microstructure after storage at 200 to 500 °C. The observations showed a 20% increase in silver grain size after only 5 h storage at 300 °C. However, in the case of a free surface, no changes were observed after 60h storage at 400 °C. These observations were combined with DSC experiments in order to suggest the cause of the difference in behaviour. The results suggest ways of stabilizing sintered silver materials so that they can be used in applications up to 400 °C without significant structural changes occurring in the material.
Semiconductor-to-metal attachment with silver-filled TPI bondlines
Authors: Fraivillig Jim , Koba Richard , Hutchings Kent
Published: October 2015

In the attachment of semiconductor chips and submounts to metal heat sinks, bondlines utilizing silver-filled thermoplastic polyimide adhesive (TPI) are very durable across a wide range of environmental conditions (thermal, physical, chemical, radiation). TPI bondlines can withstand an extreme CTE-mismatch between the laminated materials, and have excellent bonding with adhesive-layer thicknesses down to only a few microns. To provide electrical conductivity and enhance thermal conductivity, the TPI bondline can be compounded with a high concentration of silver particles, and retain durability and adhesion.

There are two general constructions of silver-filled TPI bondlines:Bondfoil – thin layers of silver-filled B-staged TPI coatings on either side of a metal carrier/substrate. The thickness of the (cured) TPI coatings would be 2–10 μm/side. TPI-priming (B- or C-staged; partially or fully cured) of a semiconductor surface may be required.TPI coating only – thin layers of silver-filled TPI polymer (1–3 μm/surface; B- or C-staged) on the interface surfaces to be bonded. A minimal amount of A-staged TPI (liquid: polymer in solvent) may be added to the bondline construction to optimize surface wetting during lamination.The ultimate in robustness and thinness, silver-filled TPI bondlines can provide:Continuous operation at 350°C, as well as temporary exposure to 450°C. Thermogravimetric analysis (TGA) of the TPI polymer shows that degradation does not start until well above 500°C. [See opposite.]Thermal shock durability -- the CTE-mismatched TPI bondline between silicon and aluminum can survive repeated thermal shocks with a ΔT of 300–400°C.Thermal impedance as low as 0.06 °C-cm2/W (0.01°C-in2/W) when using a silver-filled TPI bondfoil, and about 0.01 °C-cm2/W (0.002°C-in2/W) when using just silver-filled TPI coatings on the interface surfaces (no metal foil). In both constructions, the thermal impedance includes all interface resistances.Shear strength of 10 MPa to an aluminum surface and 1–2 MPa to silicon.

These features make TPI bondlines ideal for demanding, CTE-mismatched semiconductor packages. As opposed to cross-linked thermoset bondlines -- which are brittle, especially when highly filled -- thermoplastic polyimide bondlines remain ductile and resist cracking, even when highly stressed.
A high temperature nano/micro vapor phase conformal coating for electronics applications
Authors: Kumar Rakesh
Published: October 2015

Through characterization of dielectric and other properties at high temperatures, this work describes the development of a high temperature and UV stable nano/micro vapor phase deposited polymer coating for providing electrical insulation and protection of various electronics from chemical corrosion and other harsh environmental effects. Packaging, protection and reliability of various electronic devices and components, including PCBs, MEMS, optoelectronic devices, fuel cell components and nanoelectronic parts, are becoming more challenging due to the long-term performance requirements on devices. A recently commercialized high temperature polymer, Parylene HT®, offers solutions to many existing protective, packaging and reliability issues of electronic and medical applications, in part because of its excellent electrical and mechanical properties, chemical inertness and long-term thermal stability (high temperature exposure to over 350°C, short-term at 450 °C). Experimental results and commercial applications demonstrate the ability of Parylene HT coating to meet the growing requirements for higher dielectric capabilities, higher temperature integrity and mechanical processing, etc. of dynamic electronics applications. In addition, Parylene HT polymer coating truly conforms to parts due to its molecular level deposition characteristics. Its suitability and biocompatibility encourage researchers to explore Parylene HT's role in sensors and in active electronic devices for various industries.
Advances in Ceramic Capacitors for High Temperature Applications
Authors: Gurav Abhijit , Xu Xilin , Magee Jim , Phillips Reggie , Ashburn Travis
Published: October 2015

There is a growing need for capacitors for applications at temperatures of 150°C or above, such as electronics for down-hole drilling and exploration, geothermal energy generation and power electronics. Conventional X7R and X8R type ceramic capacitors are designed for applications up to 125°C and 150°C, respectively. At temperatures above 150°C, these types of capacitors typically suffer from degradation of reliability performance and severe reduction in capacitance, especially under DC bias conditions. Recently, a Class-I C0G dielectric has been developed using Nickel electrodes for high temperature application up to 200°C and beyond. Due to its linear dielectric nature, this material exhibits highly stable capacitance as a function of temperature and voltage. Multi-layer ceramic capacitors (MLCC) made from this material can be qualified as X9G with robust reliability. A Class-II modified-X7R dielectric composition with nickel internal electrodes showing robust reliability at 175°C has also recently been developed. This paper will report electrical properties and reliability test data on these Class-I C0G and Class-II ceramic capacitors at high temperatures of 150–200°C and above.
Investigation of Automotive Power Semiconductor Module Operates at Elevated Cooling Temperature
Authors: Wang Yangang , Wu Yibo , Dai Xiaoping , Jones Steve , Liu Guoyou
Published: October 2015

The degradation of performance and reliability of power semiconductor module with increment of temperature is an important issue to deal with in Hybrid and Electric Vehicles (HEV/EV) application. The high ambient and cooling temperatures are challenges to HEV/EV modules as the automotive industry is interested in cooling power electric system by sharing with engine's high temperature coolant. The elimination of low temperature cooling circuit has significant benefits to cost and volume/weight. However, the performance and reliability will be worsened to a large degree which may affect the feasibility of module application. In this work, an investigation is done to evaluate the electrical, thermal performance and reliability of a standard direct liquid cooled automotive IGBT module operates at 105°C coolant.
Simulation of a new hybrid Si/SiC power device for harsh environment applications
Authors: Gammon P.M. , Chan C.W. , Mawby P.A.
Published: October 2015

A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.
Optimized High Power GaN Transistors
Authors: Roberts J. , Mizan A. , Yushyna L.
Published: October 2015

GaN transistors intended for use at 600–900 V and that are capable of providing of 30–100 A are being introduced this year. These devices have a substantially better switching Figure-of-Merit (FOM) than silicon power switches. Rapid market acceptance is expected leading to compound annual growth rates of 85 %. However these devices present new packaging challenges. Their high speed combined with the very high current being switched demands that very low inductance packaging must be combined with highly controlled drive circuitry. While convention, and the usually vertical power device die structure, has largely determined power transistor package formats in the past, the lateral nature of the today GaN devices requires the use of new package types. The new packages have to operate at high temperatures while providing effective heat removal, low inductance, and low series resistance. Because GaN devices are lateral they require the package metal tracks to be integrated within the on-chip tracks to carry the current away from the thin on-chip metal tracks. The new GaN devices are available in two formats: one for use in embedded modular assemblies and the other for use mounted upon conventional circuit board systems. The package intended for discrete printed circuit board (PCB) assemblies has a top side cooling option that simplifies the thermal interface to the heat sink. The paper describes the die layout including the added copper tracks. The corresponding package elements that interface directly with the surface of the die play a vital role in terms of the current handling. They also provide the interface to the external busbars that allow the package to be mounted within, or on PCB. The assembly has been subject to extensive thermal analysis and the performance of a 30 A, 650 V transistor is described.
Performance and Reliability of SiC dies, Die attach and Substrates for High Temperature Power Applications up to 300°C
Authors: Hamilton Dean , Mills Liam , Riches Steve , Mawby Philip
Published: October 2015

The recent commercial availability of silicon carbide power semiconductor devices are theoretically capable of operating at temperatures well beyond the limits of silicon devices and have generated an interest in developing high temperature capable packaging solutions to match. In this work, the performance and reliability of a number of commercially available silicon carbide power MOSFET dies from multiple vendors was determined for die temperatures up to 350°C. Although these results have demonstrated a number of aging effects and very high on-state resistances at high temperatures, it appears that these devices can perform reliably even in air atmospheres for 100 hours or more at 350°C. In addition, commercially available DBC type ceramic-based substrates have been evaluated for their thermal cycling performance and candidate high temperature capable die attach materials including silver sinter paste and tin and gold-tin pre-form based transient liquid phase types have also been evaluated. These results have demonstrated that the active metal brazed substrates, both copper and aluminium variants, in conjunction with the silicon carbide dies and silver sinter die attach may serve as the basis for high temperature power modules, and may be operated reliably in thermal cycled applications and in air atmospheres up to 300°C. Due to large threshold voltage shift of the SiC MOSFETs at these temperatures, it may be necessary to implement a negative gate bias capability.

This work has been carried out under the Innovate UK supported project HITEC, led by Prodrive and also including The University of Warwick, GE Aviation Systems, Ricardo, TT Electronics Semelab, Diamond Hard Surfaces and GaN Systems.
A High Temperature, High Power Density Package for SiC and GaN Power Devices
Authors: Cole Z. , McGee B. , Stabach J. , O'Neal C. B. , Passmore B.
Published: October 2015

In this work, a compact 600 – 1700 V high current power package housing either silicon carbide (SiC) or gallium nitride (GaN) power die was designed and developed. Several notable configurations of the package include diode half-bridges, co-packed MOSFET-diode pairs, and cascode configured GaN devices. In order to avoid a significant redesign effort for each new application or improvement in device technology, a device-neutral design strategy enables the use of a variety of die types from any manufacturer depending on the end-use application's requirements. The basic SOT-227 is a widely used package type found in everything from electronic welders and power supplies to motor controls and inverters. This module is a variant of that style of package which also addresses some issues that a standard SOT-227 package has when used in higher voltage applications; it has increased creepage and clearance distances which meet IPC, UL, and IEC standards up to 1700 volts while retaining an isolated substrate. It also has low parasitic values in comparison to the SOT-227. One of the key elements of this design is the removal of the baseplate. This allows for far lower weight, volume, and cost as well as reduced manufacturing complexity. The wide bandgap power package is composed of high temperature capable materials, which allow for the high junction temperatures inherent in these high power density devices. This paves the way for the design of a small, low-profile package with low parasitic inductances and a small junction-to-case thermal resistance. This paper will discuss the mechanical design of the power package as well as the three-dimensional finite-element modeling and analysis of the thermal, electrical, and mechanical characteristics. In addition, the electrical characteristics as a function of temperature of the power module up to 225 °C will be presented.
Silver Thick Film Based Insulated Metal Substrates for High Temperature Power Applications
Authors: Riches S T , Whitmarsh J , Hamilton D
Published: October 2015

Thick film technology is normally applied to ceramic substrates such as Al2O3 and AlN, where conductor thicknesses for Au and Ag-Pd based thick film materials are <20μm for signal processing. For power devices applications, thicker deposits are required to increase the current carrying capacity and thick print Cu and Ag materials have been developed for ceramic substrates.

For power applications, this technology still requires attachment of the ceramic substrate to a heat sink, that may be made of aluminium or copper, which needs a thermal interface material. In printed circuit board technology, insulated metal substrates have been developed for power module assembly to eliminate the thermal interface material, where the copper conductor circuit is attached and isolated from the integral heatsink, through an organic based dielectric based on epoxy adhesive material. The organic based material limits the operating temperature of the substrate to around 175°C.

This paper covers the development of a thick film based approach to producing insulated metal substrates that can operate at higher temperatures than an organic based dielectric system. Thick film dielectric materials have been developed for direct deposition onto aluminium substrates with firing temperatures of around 500°C, combined with a silver based thick film material, which is used as the conductor to the power devices. SiC die attach to the silver based thick film material has been evaluated using a silver sinter die attach material which provides a mono-metallic die attach system. Samples have been temperature cycled from −40°C to +250°C for over 100 cycles without deterioration and the results are compared with Cu/Si3N4 substrates, which have shown issues with cracking and delamination for the equivalent thermal cycling regime.

This work has been carried out under the Innovate UK supported project HITEC, led by Prodrive and involving the University of Warwick, Ricardo, TT Electronics - Semelab, GE Aviation Systems – Newmarket, Diamond Hard Surfaces and GaN Systems.
Silicon Carbide Functional Primitives for Wireless Sensor Nodes
Authors: Horsfall A.B. , Chan H.K. , Vassilevski K.V. , Wood N.G. , Wright N.G.
Published: October 2015

While wireless sensor nodes based on conventional semiconductor technology have revolutionized our understanding of the world in which we live, they are limited to operating in benign environments. This limitation precludes their use in a wide range of industrial, automotive and geological applications, where the required operating temperatures can exceed 200°C. Silicon-on-insulator technology has enabled the development of high temperature electronics, however applications requiring higher temperature operation are becoming apparent. Battery technologies capable of sustaining the required power level in these extreme environments are also a significant challenge. In this work, we present the integration of analog functional primitive circuits capable of interrogating resistive and capacitive sensors to form a wireless sensor node based on silicon carbide technology. The electrical power is provided from the output of a novel self-starting boost converter connected to a thermoelectric generator. Data can be transmitted from the node via frequency modulation of a Colpitts oscillator, for remote post processing. The signal conditioning is realised using JFET based amplifier circuits, designed using a novel JFET compact model, which enables a greater level of confidence than existing models in the literature.
A Low Power Data Acquisition Solution for High Temperature Applications
Authors: Watson Jeff , Pachchigar Maithil
Published: October 2015

An increasing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. We have previously presented a new 600 kSPS SAR ADC that is rated at 210°C to meet these needs. However, the design of the supporting circuitry for a SAR ADC to achieve optimum performance is not trivial, especially over this wide temperature range. In this work we discuss the design of a complete data acquisition circuit building block that will take an analog sensor input, condition it, and digitize it to an SPI serial data stream. We will also discuss some of the practical aspects of fabricating the circuit to survive this harsh environment. This circuit reference design will be published and available off the shelf to designers of harsh environment systems.
Assessment of MEMS Vibration Energy Harvesting for High Temperature Sensing Applications
Authors: Riches S T , Doyle K , Tebbit N , Jia Y , Seshia A
Published: October 2015

Distributed electronics for improving the accuracy of sensing in harsh high temperature environments, such as aero-engine and down-well is a growing field, where reduced power input requirements in cabling and batteries is viewed a key enabler for accelerating the adoption of high temperature electronics. Although batteries are available that can operate up to 200°C, they offer limited life at high temperatures and are bulky, increasing the costs of deployment and maintenance. Cabling also adds weight and takes up space in limited access applications. Energy harvesting in-situ offers the opportunity to make a step change in the design of high temperature electronics modules and in expanding their possible range of applications; for example, in sensor systems for combustor and turbine monitoring in aero-engines.

This paper covers an assessment of MEMS vibration energy harvesting technology for high temperature sensing applications. MEMS devices based on the principle of parametric resonance, using AlN on Silicon have been designed and fabricated, along with sourcing of high temperature components for rectification, impedance matching and energy storage. The MEMS devices have been packaged into ceramic chip carriers and measured for energy output from a random vibration profile representative of an aerospace application. The measured output from the MEMS vibration energy harvester is capable of providing sufficient power to be of interest for autonomous sensing applications.

This paper reports on the performance of the MEMS vibration energy harvesting devices and their associated circuitry at room temperature and at temperatures of up to 150°C. The challenges remaining to develop robust energy harvesting devices that could be applied in aero-engine, down-well and other high temperature applications are described.

This work has been carried out under the Innovate UK supported project HI-VIBE, in a collaboration between GE Aviation Systems – Newmarket and the University of Cambridge.
Parametric Models of Ultrasonic Piezoelectric Transducers over a Wide Temperature Range
Authors: Morris Steven A. , Townsend Jeremy
Published: October 2015

Piezoelectric ultrasonic transducers are used extensively in well logging and logging-while-drilling applications for pulse-echo operation. We present a method of modeling the operation of ultrasonic thin-disk piezoelectric transducers over a wide range of temperatures. The model is based on using Redwood's version of Mason's model of thin-disk transducers. Laboratory measurements in the oven of non-backed transducers in air are used to extract the Mason model parameters as a function of temperature. Derived parameters are frequency-thickness constant, dielectric constant, and thickness mode coupling coefficient. A fourth parameter, bulk density, is measured independently and assumed constant over temperature. Temperature dependence of frequency thickness constant and coupling coefficient are modeled as linear temperature coefficients. Temperature dependence of the dielectric constant must be specified as a table because of the non-linear temperature dependence of that parameter.
High Temperature 256Kbit (32Kbit × 8) HTEEPROM Reliability Testing
Authors: Guimont Joe G. , Ohme Bruce W.
Published: October 2015

Results of reliability and qualification testing are presented for a commercial High Temperature EEPROM (HTEEPROM). This HTEEPROM is specified for operation at 225°C and is the highest temperature rated commercial non-volatile memory available to date.

Initial test results (at 250°C) and design details have been previously reported for a prototype 256Kbit (32Kbit × 8) HTEEPROM fabricated using a production high-temperature silicon-on-insulator (SOI) 0.8 micron CMOS process [1]. This paper presents reliability test results for a commercial version developed using knowledge gained from the previously reported HTEEPROM, and fabricated in the same technology. The reliability test results include data retention at 250°C, endurance (write cycling) > 100,000 cycles, parametric and functional test results for 1000 hours of dynamic life test at 250°C, 100 temperature cycles from −65°C to 200°C, ESD, Group D and residual-gas-analysis (RGA) testing. The HTEEPROM is packaged in a 56-pin ceramic pin-grid-array (PGA) package. It is configurable by a control input pin for either serial or parallel memory access. The design incorporates an on-chip timer to support periodic memory refresh to extend data retention indefinitely.
High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology
Authors: Grella K. , Dreiner S. , Vogt H. , Paschen U.
Published: October 2015

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.
Evaluation of Refractory Metals for Package Level Interconnection in a Harsh Environment
Authors: Made Riko I , Phua Eric Jian Rong , Tan Key Wen , Ong Wei Chuan , Huang Clare Guanqi , Ong Hock Guan , Nachiappan Vivek Chidambaram , Wong Chee Cheong , Zhong Chen , Gan Chee Lip
Published: October 2015

Operating in a high temperature and pressure environment is a serious challenge for microelectronics device packaging. This study evaluates the electrical and mechanical behavior of Al, Ag, Mo, Nb and W metallization on ceramic substrates aged under harsh conditions, with the latter three showing great potential as candidates for replacing Cu. In the experiments, metals of interest were deposited by physical vapor deposition on alumina substrates. Samples were aged at 400°C and in 100 MPa argon pressure to simulate the harsh environment condition. During initial aging, it was observed that there was varying degree of electrical resistance changes. It can be understood that metal grains may grow during the initial thermal aging, leading to reductions in electrical resistance of some metals. Such reductions were observed on Ag and W samples. In comparison, there were much smaller increase in the measured resistances of Al and Mo. Nb shows the most significant increase in resistance that practically renders it unsuitable as an interconnect. While Ag shows considerably weak metal-to-substrate adhesion, the other four metals show satisfactory post aging metal-to-substrates adhesion. From these results, considering the physical and electrical properties of the metal, Al, Mo and W could be good candidates for high temperature and pressure applications.
Effectiveness of Barrier Layer Metallisations in Long Term High Temperature Endurance Tests on Wire Bond Interconnections
Authors: Riches S T , Johnston C , Lui A
Published: October 2015

Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of >200°C, with device lifetimes of 5 years at 225°C being declared. One of the key areas governing the lifetime of the packaged electronic devices is the reliability of the wire bond interconnection between the device and the package or substrate connection. Extended temperature storage testing at 250°C of packaged SOI devices has highlighted end of life failure modes associated with wire bond connections.

SOI devices are normally supplied with an aluminium based bond pad metallisation, which are not suitable for direct connection of Au wire at operating temperatures of >125°C, due to the formation of Au-Al intermetallics. It is possible to post-process silicon wafers to deposit barrier and connection materials to create a mono-metallic Au-Au joint at the surface. For long term endurance at temperatures >200°C, the effectiveness of the barrier layer in preventing diffusion of the aluminium bond pad metallisation to interact with the Au is a critical factor.

This paper presents results of studies carried out on two post-process metallisation systems Au/TiW and Au/Pd/Ni deposited onto aluminium bond pads, which have been Au wire bonded and exposed to 250°C temperature storage for up to 13,000 hours. The results have shown that the barrier layers are not effective in preventing diffusion of the aluminium bond pad metallisation to create Au-Al based intermetallics. The results are compared with Al-1%Si wire bonding to the aluminium bond pad, where the 2nd wedge bond is attached to a Au/Ni plated metallisation, where the degradation appears to be less severe. Recommendations for designing stable wire bond interconnection systems for extended high temperature operation will be presented.
Evaluation of Pressure Free Nanoparticle Sintered Silver Die Attach on Silver and Gold Surfaces
Authors: Lewis G. , Dumas G. , Mannan S. H.
Published: October 2015

A commercially available silver nanoparticle based die attach material was used in a pressure free process to bond 2.5 mm square Ag plated Si die to Ag and Au plated substrates. The two substrate types were 5mm square Ni/Ag plated silicon substrate and a W/Ni/Au metallised cofired alumina package. The assemblies were stored at 300 °C for up to 500 h and the morphology of the sintered Ag and the shear strength was monitored as a function of time. Bondline thickness measurements were carried out after following the paste manufacturer's drying and sintering temperature profile. On Ag substrate it was found that die shear strength increased with storage time. The fracture surfaces of the sheared die and substrate as well as cross sections of untested die were examined using electron microscopy. It was found that the Ag grains grew in size and porosity decreased over time. There was also a clear difference in morphology between sintered Ag at the die edge and centre. During shearing the Ni layer was found to separate from the chip at the edges of the die after ageing. On Au substrate, it was found that die shear strength decreased with storage time. It was found that the Au diffused into the Ag, creating a low porosity Au-Ag layer. Ag also migrated towards the Au surface, leaving behind a layer of voids which contributed to weakening of the joint. Rapid Au diffusion was associated with the high density of grain boundaries arising from the sintering process.
Novel encapsulation materials for High Pressure-High Temperature (HPHT) applications
Authors: Phua Eric Jian Rong , Liu Ming , Made Riko I , Zhang Liying , Wong Chee Cheong , Chen Zhong , Rhee Min Woo , Hu Xiao , Gan Chee Lip
Published: October 2015

A modified thermoset polymer resin (PR) is evaluated as a form of alternative packaging material to traditional epoxy. It is understood that the thermoset cross-links to a higher degree at high temperature. Hence, its mechanical properties can be improved by changing treatment duration and temperature, rendering the material mechanically stronger for application temperatures beyond 300°C. Material strength was evaluated through a modified compressive testing setup which shows neat PR is comparable to epoxy. Concurrently, adhesion to silicon die and ceramic substrate were evaluated by means of bond shear using the DAGE-4000 shear tester both at room temperature and elevated temperature. Bond shear strength of PR is observed to be higher at room temperature as compared to elevated temperatures when bonded to Silicon (Si) and Alumina (Al2O3), a phenomenon which can be attributed to mismatches in coefficient of thermal expansions (CTE). For high pressure only applications, PR is a good alternative. Pre- and post-pressure loading analysis was carried out by forming an encapsulation analogous to that of a glob top on DIP packages. Observation shows no crack formation, indicating that the material is suitable for high pressure loading up to 207 MPa. For high pressure and high temperature applications (HPHT), pure PR is good up to 250°C at 25 kPsi (172 MPa).
1200 V SiC Schottky Rectifiers optimized for ≥ 250 °C operation with low junction capacitance
Authors: Singh Ranbir , Sundaresan Siddarth
Published: October 2015

Electrical Characteristics of Industry's first commercially available 1200 V rated SiC Schottky rectifiers, specially designed for operation at ≥ 250 °C are presented. These high-temperature SiC rectifiers fabricated in 1, 5, and 20 A current ratings feature reverse leakage currents of < 3 mA/cm2 at 1200 V up to temperatures as high as 300 °C. GeneSiC's 1200 V/20A High Temperature Schottky (designated SHT) rectifier offers a 10x reduction in leakage current and a 23% reduction in junction capacitance when compared to its nearest SiC Schottky rectifier competitor. In addition, these SHT rectifiers demonstrate superior surge-current ratings, and temperature-independent switching capability up to their rated junction temperatures.
Design Considerations of High-Current Density Capacitors Micromachined for Si Interposers
Authors: Beal A. N. , Tatarchuck J. , Stevens C. B. , Baginski T. A. , Hamilton M. C. , Dean R. N.
Published: October 2015

Many demanding power system requirements usher motivations for high-density, miniaturized capacitors capable of quickly sourcing large quantities of current. Various efforts achieved high capacitive density (∼500 nF/mm2) at D.C., but many applications promote an interest in transient and high-frequency (HF) characteristics. Thin capacitors (100–640 μm) were micromachined using several industry standard Si MEMS processes resulting in large surface area, high-density capacitive storage devices (7.34 nF/mm2). An evaluation of high-speed (1 GHz), energy storage devices and their respective fabrication technologies has been closely compared by considering each capacitor design's transient ring-down characteristics. Although their capacitive density remains ∼10 nF/mm2, large amounts of current (∼100 A/ns) were sourced while retaining desirable characteristics at high frequencies. These devices have been optimized as embedded passives and demonstrate compatibility with Si interposer technology.
New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA
Authors: Kwon Woon-Seong , Ramalingam Suresh , Wu Xin , Madden Liam , Huang C. Y. , Chang Hung-Hsien , Chiu Chi-Hsin , Chiu Steve , Chen Stephen
Published: October 2015

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.
Challenges of Scalable 2.5D IC Assembly
Authors: Wang Liang , Woychik Charles G. , Gao Guilian , Villavicencio Grant , McGrath Scott , Shen Hong , Arkalgud Sitaram
Published: October 2015

Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process, and integration choices. With these concerns as a backdrop, our article will discuss our approach to optimizing 2.5D assembly for HVM. This article starts with a review of our test vehicle and our overall choices of substrate, interposer, and die dimensions. Three different 2.5D assembly approaches that have been investigated for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. It is our finding that for achieving high yield and reliability, in the design stage of the system detailed considerations must be given to not only the electrical performance and signal integrity but also the thermal and mechanical behavior of the system in operation as well as the entire process history. This article reports our results from critical areas including temporary bonding, thermocompression bonding, mass reflow, thin wafer/die handling, flux, underfill, and molding. This article also presents our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In the last portion of this article, recommendations are made for an optimized assembly process flow.
Warpage Evaluation of High-Temperature Sandwich-Structured Power Module for SiC Power Semiconductor Devices
Authors: Anzai Takeshi , Murakami Yoshinori , Sato Shinji , Tanisawa Hidekazu , Hiyama Kohei , Takahashi Hiroki , Kato Fumiki , Sato Hiroshi
Published: October 2015

This article presents a sandwich-structured SiC power module that can be operated at 225°C. The proposed power module has two ceramic substrates that are made of different materials (Si3N4 and Al2O3). The SiC devices are sandwiched between these ceramic substrates. The module also has a baseplate soldered onto the ceramic substrate. Conventional power modules use baseplate materials with a large coefficient of thermal expansion (CTE), for example, Cu (17–18 ppm/°C and Al (23–24 ppm/°C). In the fabrication process, the soldering temperature reaches 450°C because Au-Ge eutectic solder is used. A problem was found in the fabrication process of the module because of the high soldering temperature and CTE mismatches of the components. Furthermore, for high-temperature operation, a thermal cycle of −40°C to 250°C will be needed to ensure reliability and it is important to decrease the warpage of the module during the thermal cycle. By using stainless steel (CTE: 10 ppm/°C) for the baseplate, the warp-age measured at room temperature was reduced to one-third that of a module using a Cu baseplate. Further, the warpage displacement from 50°C to 250°C was also reduced.
Bonded Ceramic-Metal Layers for Fabrication of Thermal Conduction Plates
Authors: Datta Madhav
Published: October 2015

The work described in this article is part of an effort to build reliable and efficient liquid cooling modules for high-power laser diodes. The cooling system is designed to mount at least 12 laser diodes to a common microheat exchanger, thus requiring a large-size thermal conduction plate. Fabrication of the thermal conduction plate involved void-free bonding of copper layers on both sides of an aluminum nitride (AlN) plate. In the current study, ceramic-metal bonding methods using moly-manganese metallization and active metal brazing were investigated. Bonded AlN/copper plates were characterized and evaluated by optical microscopy, scanning electron microscopy, and energy dispersive spectrometry. For detecting voids, cracks, and delamination, some of the plates were analyzed by scanning acoustic microscopy (C-SAM). Results indicated that >99% void-free bonded AlN/Cu plates can be fabricated by using properly selected metallization conditions and brazing temperature profiles. The active metal brazing approach was found to be a cost-effective method of fabricating reliable, void-free thermal conduction plates.