bluuebunny/crossref_metadata_2025 huggingface dataset:
Local Solid Phase Epitaxy of Few-Layer Graphene on Silicon Carbide
Authors: Escobedo-Cousin Enrique , Vassilevski Konstantin , Nikitina Irina P. , Wright Nicolas G. , O'Neill Anthony G. , Horsfall Alton B. , Goss Jonathan P.
Published: May 2012

Patterned Few Layers Graphene (FLG) films were grown by local solid phase epitaxy from nickel silicide supersaturated with carbon. The process was realised by annealing of thin Ni films deposited on the carbon-terminated surface of 6H-SiC semi-insulating wafer followed by wet processing to remove the resulting nickel silicide. Raman spectroscopy was used to investigate both the formation and subsequent removal of nickel silicide during processing. Characterisation of the resulting FLG films was carried out by Raman spectroscopy and Atomic Force Microscopy (AFM). The thickness of the final FLG film estimated from the Raman spectra varied from 1 to 3 monolayers for initial Ni layers varying from 3 to 20 nm thick. AFM observations revealed process-induced surface roughening in FLG films, however, electrical conductivity measurements by Transmission Line Model (TLM) structures confirmed that roughness does not compromise the film sheet resistance.
Study of Epitaxial Graphene on Non-Polar 6H-SiC Faces
Authors: Daas Biplob K. , Daniels Kevin M. , Shetu S. , Sudarshan Tangali S. , Chandrashekhar M.V.S.
Published: May 2012

We present epitaxial graphene (EG) growth on non-polar a-plane and m-plane 6H-SiC faces where material characterization is compared with that known for EG grown on polar faces. AFM surface morphology exhibits nanocrystalline graphite like features for non-polar faces, while polar silicon face shows step like features. This differing behavior is attributed to the lack of a hexagonal template on the non-polar faces. Non-polar faces also exhibit greater disorder and red shift of all Raman peaks (D, G and 2D) with increasing temperature. This is attributed to decreasing stress with increasing temperature. These variations provide evidence of different EG growth mechanisms on non-polar and polar faces, likely due to differences in surface free energy. We also present differences between a-plane ( ) EG and m-plane ( ) EG in terms of morphology, thickness and Raman characteristics.
Epitaxial Single-Layer Graphene on the SiC Substrate
Authors: Davydov Sergey Yu. , Lebedev Alexander A.
Published: May 2012

The analytical expression for the density-of-states (DOS) of single-layer graphene interacting with the SiC surface (epitaxial graphene) is obtained. The silicon carbide DOS is described within the scope of the Haldane-Anderson model. It is shown that due to the interaction with the substrate the gap of about 0.01-0.06 eV arises in the epitaxial graphene DOS. The estimation indicates that the electron charge of about (−10-3) e/atom transfers from the substrate to graphene.
Growth of a Thick 2H-SiC Layer in Si-Li Solution under a Continuous CH4 Flow
Authors: Imade Mamoru , Ishikawa Akito , Nakagawa Yusuke , Yoshimura Masashi , Kitaoka Yasuo , Sasaki Takatomo , Mori Yusuke
Published: May 2012

The growth of thick 2H-SiC layers in Si-Li solution under a continuous CH4 flow at atmospheric pressure was investigated. The thickness of the 2H-SiC layer increased linearly with the growth period, reaching as thick as 270-μm with a growth period of 7 hr. The Li concentration in the layers was as low as 1.0 × 1018 atoms/cm3, which was less than one-hundredth that observed in a previous study.
Studies of Li Intercalation into Epitaxial Graphene on SiC(0001)
Authors: Virojanadara Chariya , Watcharinyanon S. , Zakharov A. A. , Yakimova R. , Johansson Leif I.
Published: May 2012

Detailed studies of Li deposition on monolayer graphene grown on the Si-face SiC surface were performed using LEEM, µ- LEED, PES and ARPES. Li found to intercalate directly after the deposition at room temperature. However, excess Li was also observed on the surface and found to form a compound with carbon atoms. This compound is suggested to give rise to a new (√3x√3) R30° surface reconstruction. After annealing the (√3x√3) R30° reconstruction was vanished and only a (1x1) graphene diffraction pattern was visible. At the same time a sever change was observed on the graphene morphology, especially from the ex-situ grown graphene, i.e. extended area of cracks/wrinkles were observed. These wrinkles/cracks did not disappear even after heating at temperature of 500-1000°C when no Li signal was detected.
Plasma-Based Chemical Modification of Epitaxial Graphene
Authors: Walton Scott G. , Hernández Sandra C. , Baraket Mira , Wheeler Virginia D. , Nyakiti Luke O. , Myers-Ward Rachael L. , Eddy Charles R. , Gaskill D. Kurt
Published: May 2012

In this work, the treatment of epitaxial graphene on SiC using electron beam generated plasmas produced in mixtures of argon and oxygen is demonstrated. The treatment imparts oxygen functional groups on the surface with concentrations ranging up to about 12 at.%, depending on treatment parameters. Surface characterization of the functionalized graphene shows incorporation of oxygen to the lattice by disruption of ∏-bonds, and an altering of bulk electrical properties.
Evidence of Electrochemical Graphene Functionalization by Raman Spectroscopy
Authors: Daniels Kevin M. , Daas Biplob K. , Srivastava Nishtha , Williams Christopher , Feenstra Randall M. , Sudarshan Tangali S. , Chandrashekhar M.V.S.
Published: May 2012

Electrochemical functionalization of treated epitaxial graphene samples on Si-face 6H-SiC are presented in this work. Three semi-insulating 6H-SiC substrates cut from different boules with varying off cut angle (on axis, 0.5° and 1.0° degrees off axis in the [112‾0] direction) were diced into 10mm x 10mm samples and quality EG grown on top. A home-build electrochemical cell was used with current applied though a 10% H2SO4 solution, with a Pt wire and exposed graphene as the anode and cathode respectively. Functionalization was determined using Raman spectroscopy and measured by an increase in D/G ratio, increase in fluorescence background and introduction of C-H bond peak at ~2930 cm-1. Components of the Raman spectra before and after functionalization of all samples used were analyzed to show a substrate dependent effect on functionalization with values such as D/G ratio and normalized fluorescence slope varying between the substrates.
Molecular Gas Adsorption Induced Carrier Transport Studies of Epitaxial Graphene Using IR Reflection Spectroscopy
Authors: Daas Biplob K. , Nomani W. K. , Daniels Kevin M. , Sudarshan Tangali S. , Koley Goutam , Chandrashekhar M.V.S.
Published: May 2012

We investigate molecular adsorption doping by electron withdrawing NO2 and electron donating NH3 on epitaxial graphene. Amperometric measurements show conductance changes upon introduction of molecular adsorbents on epitaxial graphene. Conductance changes are a trade-off between carrier concentration and scattering, and manifest at direct current and optical frequencies. We therefore investigate changes in the infrared (IR) reflection spectra to correlate these two frequency domains, as reflectance changes are due to a change of EG surface conductance. We match theory with experimental IR data and extract changes in carrier concentration and scattering due to gas adsorption. Finally, we separate the intraband and interband scattering contributions to the electronic transport under gas adsorption. The results indicate that, under gas adsorption, the influence of interband scattering cannot be neglected, even at DC.
Gated Epitaxial Graphene Devices
Authors: Waldmann Daniel , Jobst Johannes , Speck Florian , Seyller Thomas , Krieger M. , Weber Heiko B.
Published: May 2012

A bottom gate scheme is presented to tune the charge density of epitaxial graphene via a gate voltage while leaving the surface open for further manipulation or investigation. Depending on the doping concentration of the buried gate layer, the temperature and illumination, the bottom gate structure can be operated in two regimes with distinct capacitances. A model is proposed, which quantitatively describes the gate operation. The model is verified by a control experiment with an illuminated gate structure using UV light. Using UV illumination the Schottky capacitor (SC) regime, which provides improved gate efficiency, can be used even at low temperatures.
T- and Y-Branched Three-Terminal Junction Graphene Devices
Authors: Pezoldt Jörg , Göckeritz Robert , Hähnlein Bernd , Händel Benjamin , Schwierz Frank
Published: May 2012

Heteroepitaxial graphene on semiinsulating silicon carbide was used to fabricate nanoelectronic devices. T- and Y-branched graphene three-terminal junction devices were realized. Room temperature electrical measurements demonstrate pronounced nonlinear electrical properties of the devices. Voltage rectification at room temperature was observed. Increasing branch width reduces the curvature of the voltage rectification response curve of the three-terminal junc¬tions.
Development of FETs and Resistive Devices Based on Epitaxially Grown Single Layer Graphene on SiC for Highly Sensitive Gas Detection
Authors: Pearce Ruth , Yakimova R. , Hultman L. , Eriksson Jens , Andersson Mike , Lloyd Spetz Anita
Published: May 2012

Epitaxially grown single layer graphene on silicon carbide (SiC) resistive sensors were characterised for NO2 response at room and elevated temperatures, with an n-p type transition observed with increasing NO2 concentrations for all sensors. The concentration of NO2 required to cause this transition varied with different graphene samples and is attributed to varying degrees of substrate induced Fermi-level pinning above the Dirac point. The work function of a single layer device demonstrated a steady increase in work function with increasing NO2 concentration indicating no change in reaction mechanism in the concentration range measured despite a change in sensor response direction. Epitaxially grown graphene device preparation is challenging due to poor adhesion of the graphene layer to the substrate. A field effect transistor (FET) device is presented which does not require wire bonding to contacts on graphene.
Growth Rate Prediction in SiC Solution Growth Using Silicon as Solvent
Authors: Lefebure Julien , Dedulle Jean Marc , Ouisse Thierry , Chaussende Didier
Published: May 2012

Besides the seeded sublimation process, which is the current industrial crystal growth process for silicon carbide (SiC), solution growth appears as a possible method for high quality bulk crystals. For a further development of the latter technique, a robust numerical model has been implemented with the aim to give quantitative outcomes in addition to qualitative information. Growth rates have been calculated for three different temperature ranges (1700, 1800 and 1900°C) in pure silicon. The computed values were found to be in good agreement with the experimental ones.
Temperature Dependent Chemical Sensitivity of Epitaxial Graphene
Authors: Nagareddy V. Kartheek , Gaskill D. Kurt , Tedesco J.L. , Myers-Ward Rachael L. , Eddy Charles R. , Goss Jonathan P. , Wright Nicolas G. , Horsfall Alton B.
Published: May 2012

We investigated the chemical sensing mechanism of epitaxial graphene grown on 6H-SiC (0001) to different polar solvents and their behavior at higher temperatures. We show that at 300 K the sensitivity of the graphene sensor increases exponentially with the dipole moment of a solvent and decreases significantly as the temperature increased to 425 K. Using electrical measurements, we also show that graphene can effectively discriminate between polar protic and polar aprotic solvents with the shift in device electrical resistance at 300 K.
Effect of Post-Oxidation Annealing in Wet O2 and N2O Ambient on Thermally Grown SiO2/4H-SiC Interface for P-Channel MOS Devices
Authors: Katakami Shuji , Arai Manabu , Takenaka Kensuke , Yonezawa Yoshiyuki , Ishimori Hitoshi , Okamoto Mitsuo , Kojima Kazutoshi , Fukuda Kenji
Published: May 2012

We investigated the effect of post-oxidation annealing in wet O2 and N2O ambient, following dry O2 oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO2/SiC interface, in each POA process. Notably, the N2O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O2-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.
Temperature Dependence of Inversion Layer Carrier Concentration and Hall Mobility in 4H-SiC MOSFETs
Authors: Dhar Sarit , Ahyi Ayayi Claude , Williams John R. , Ryu Sei Hyung , Agarwal Anant K.
Published: May 2012

Hall measurements on NO annealed 4H-SiC MOS gated Hall bars are reported in the temperature range 77 K- 423 K. The results indicate higher carrier concentration and lower trapping at increased temperatures, with a clear strong inversion regime at all temperatures. In stark contrast to Si, the Hall mobility increases with temperature for 77 K-373K, above which the mobility decreases slightly. The maximum experimental mobility was found to be ~50 cm2 V-1 s-1 which is only about 10% of the 4H-SiC bulk mobility indicating that while NO annealing drastically improves trapping, it does not improve the mobility significantly. Supporting modeling results strongly suggest the presence of a disordered SiC channel region.
Impact of Interface Defect Passivation on Conduction Band Offset at SiO2/4H-SiC Interface
Authors: Hosoi Takuji , Kirino Takashi , Chanthaphan Atthawut , Uenishi Yusuke , Ikeguchi Daisuke , Yoshigoe Akitaka , Teraoka Yuden , Mitani Shuhei , Nakano Yuki , Nakamura Takashi , Shimura Takayoshi , Watanabe Heiji
Published: May 2012

The change in energy band alignment of thermally grown SiO2/4H-SiC(0001) structures due to an interface defect passivation treatment was investigated by means of synchrotron radiation photoelectron spectroscopy (SR-PES) and electrical characterization. Although both negative fixed charge and interface state density in SiO2/SiC structures were effectively reduced by high-temparature hydrogen gas annealing (FGA), the conduction band offset (ΔEc) at the SiO2/SiC interface was found to be decreased by about 0.1 eV after FGA. In addition, a subsequent vacuum annealing to induce hydrogen desorption from the interface resulted in not only a slight degradation in interface property but also a partial recovery of ΔEc value. These results indicate that the hydrogen passivation of negatively charged defects near the thermally grown SiO2/SiC interface causes the reduction in conduction band offset. Therefore, the tradeoff between interface quality and conduction band offset for thermally grown SiO2/SiC MOS structure needs to be considered for developing SiC MOS devices.
Effect of Direct Nitridation of 4H-SiC Surface on MOS Interface States
Authors: Sakai Takashi , Hemmi Mitsunori , Murata Yusuke , Yamakami Tomohiko , Hayashibe Rinpei , Onuma Yoshiharu , Kamimura Kiichi
Published: May 2012

A nitride layer was formed on a SiC surface by direct nitridation in pure N2 or in NH3 diluted with N2. The SiO2 layer was deposited by the thermal decomposition of tetraethylorthosilicate (TEOS) on the nitride layer to form an MIS diode. The XPS analysis showed that the nitride layer was oxidized during the deposition process of SiO2. The direct nitridation was effective to reduce the interface state density between the insulating layer and 4H-SiC
Effect of POCl3 Annealing on Reliability of Thermal Oxides Grown on 4H-SiC
Authors: Morishita Ryuji , Yano Hiroshi , Okamoto Dai , Hatayama Tomoaki , Fuyuki Takashi
Published: May 2012

We have evaluated the reliability of POCl3-annealed oxides on 4H-SiC using time-zero dielectric breakdown (TZDB), constant current time-dependent dielectric breakdown (CC-TDDB), and high-frequency capacitance-voltage (C-V) measurements after electron injection. The POCl3 annealing does not deteriorate oxide breakdown field very much, still keeping an average value of larger than 9 MV/cm. However, the electron injection into POCl3-annealed oxide brings negative charges easily. From the C-V measurements, the POCl3-annealed capacitors were found to indicate a large positive flatband voltage shift after electron injection. Phosphorus atoms in the oxide may be related to the trapping site of injected electrons. The distribution and density of phosphorus in the oxide should be optimized to realize highly reliable 4H-SiC MOSFETs with high performance.
The Effects of Phosphorus at the SiO2/4H-SiC Interface
Authors: Sharma Yogesh K. , Ahyi Ayayi Claude , Issacs-Smith Tamara , Shen Xiao , Pantelides Sokrates T. , Zhu Xing Guang , Rozen John , Feldman Leonard C. , Williams John R. , Xu Yi , Garfunkel Eric
Published: May 2012

Phosphorous passivation of the SiO2/4H-SiC interface lowers the interface trap density and increases the field effect mobility for n-channel MOSFETs to twice the value of 30-40cm2/V-s obtained using standard NO nitridation. Passivation using P2O5 introduced with an SiP2O7 planar diffusion source (PDS) converts the oxide layer to phosphosilicate glass (PSG) which is a polar material. BTS (bias‐temperature‐stress) measurements with MOS capacitors and FETs show that the benefits of reduced interface trap density and increased mobility are offset by unstable flat band and threshold voltages. This instability can be removed by etching away the PSG oxide and depositing a replacement SiO2 layer. However, trap densities for etched MOS capacitors are "NO-like" (i.e., higher), which would lead one to expect a lower mobility if MOSFETs are fabricated with the PSG / etch / deposited oxide process.
Improvement in the SiO2/4H-SiC Interfacial Region by Thermal Treatments with Hydrogen Peroxide
Authors: Pitthan Eduardo , Corrêa Silma A. , Palmieri Rodrigo , Soares Gabriel Vieira , Boudinov Henri I. , Stedile Fernanda Chiarello
Published: May 2012

The effect of sequential thermal treatments with growth/removal steps of SiO2 films intercalated with hydrogen peroxide treatments on the SiO2/4H-SiC interfacial region thickness were investigated on both Si and C faces. In the Si face case, samples that were submitted to more H2O2 treatments presented thinner interfacial region thicknesses. In the C face case, on the other hand, no significant alteration in this region was observed.
Electron Trapping in 4H-SiC MOS Capacitors Fabricated by Sodium-Enhanced Oxidation
Authors: Basile Alberto F. , Ahyi A.C. , Feldman L.C. , Williams J.R. , Mooney P.M.
Published: May 2012

The electrical properties of the SiO2/SiC interface fabricated by sodium-enhanced oxidation (SEO) of n-type 4H-SiC were studied by temperature-dependent C-V and constant-capacitance deep level transient spectroscopy (CCDLTS). With the exception of near-interface traps in the SiC epi-layer, which are not present in the SEO samples, the trap species observed in SEO capacitors are the same as those observed in both standard-oxidized and NO-annealed MOS capacitors. Total electron trapping in accumulation is comparable in SEO and NO-annealed capacitors; however, the traps in SEO capacitors are located at the interface whereas tunneling into oxide traps is observed in NO-annealed samples. A series of bias-temperature stress tests show that electron trapping is essentially unchanged when mobile sodium ions are moved toward the interface. The improved mobility attained by this process compared to NO annealing may be due to the absence of near-interface SiC traps in SEO samples.
Impact of UV Irradiation on Thermally Grown 4H-SiC MOS Devices
Authors: Ikeguchi Daisuke , Kirino Takashi , Mitani Shuhei , Nakano Yuki , Nakamura Takashi , Hosoi Takuji , Shimura Takayoshi , Watanabe Heiji
Published: May 2012

The impact of ultraviolet (UV) light irradiation on thermally grown SiO2/4H-SiC structures was investigated by characterizing the 4H-SiC metal-oxide-semiconductor (MOS) capacitors fabricated with and without UV irradiation onto the oxide layers. The UV irradiation was found to significantly increase a hysteresis in capacitance-voltage (C-V) characteristics and cause a positive flatband voltage (VFB) shift, suggesting the generation of oxide charges and traps. Since the values of C-V hysteresis and VFB shift depend on the UV irradiation time, the electrical defects were considered to be induced during UV irradiation. In contrast, UV irradiation caused no marked change for the reference Si-MOS capacitors, indicating that the generation of UV-induced electrical defects was an intrinsic property of thermally grown SiO2/SiC structures. A detailed characterization of SiC-MOS capacitors with terraced SiO2 layers revealed that the UV-induced defects were located near the SiO2/SiC interface. The interfacial fixed charge density (QOX) was estimated to be 1.7×1012 cm-2 for the sample with UV irradiation, while that of the sample without UV irradiation was 1.0×1012 cm-2. Also, a slight increase was found in interface state density (Dit) due to UV irradiation. These results imply that the UV-induced defect generation correlates with residual carbon impurities at the SiO2/SiC interface.
Study of High Temperature Microwave Annealing on the Performance of 4H-SiC MOS Capacitors
Authors: Naik Harsh , Li Z. , Issa H. , Tian Y.L. , Chow T. Paul
Published: May 2012

The strong covalent bond of SiC imposes harsh post implantation annealing condition requirement for SiC MOS devices. As a consequence the effect of the annealing conditions on the channel region of the MOS devices becomes critical. High temperature microwave annealing has been shown to be an attractive alternative to conventional thermal annealing techniques. The effect of high temperature rapid microwave annealing on the performance of 4H-SiC MOS capacitors has been studied in this paper. Annealing temperatures ranging from 1600°C up to 2000°C for 30secs is used and the effect of annealing conditions is studied via C-V measurements on MOS capacitors.
Comparison of Oxide Quality for Monolithically Fabricated SiC CMOS Structures
Authors: Martin Lucy C. , Clark David T. , Ramsay Ewan P. , Murphy A.E. , Thompson Robin. F. , Smith Dave A. , Young R.A.R. , Cormack Jennifer D. , Wright Nicolas G. , Horsfall Alton B.
Published: May 2012

The recent development of silicon carbide complimentary metal-oxide-semiconductor (CMOS) is a key enabling step in the realisation of low power circuitry for high temperature applications, such as aerospace and well logging. This paper describes investigations into the properties of the gate dielectric as part of the development of the technology to realize monolithic fabrication of both n and p channel devices. A comparison of the oxide quality of the silicon carbide CMOS transistors is performed to examine the feasibility of this technology for high temperature circuitry.
A Reduction of Defects in the SiO2-SiC System Using the SiC Vacuum Field-Effect Transistor (VacFET)
Authors: Speer Kevin M. , Neudeck Philip G. , Mehregany Mehran
Published: May 2012

The SiC vacuum field-effect transistor (VacFET) was first reported in 2010 as a diagnostic tool for characterizing the fundamental properties of the inverted SiC semiconductor surface without confounding issues associated with thermal oxidation. In this paper, interface state densities are extracted from measurements of threshold voltage instability on a SiC VacFET and a SiC MOSFET. It is shown that removing the oxide can reduce the interface state density by more than 70%.
Two-Dimensional Roughness Growth at Surface and Interface of SiO2 Films during Thermal Oxidation of 4H-SiC(0001)
Authors: Hasunuma Ryu , Fukasawa Tatsuya , Kosugi Ryouji , Ishida Yuuki , Yamabe Kikuo
Published: May 2012

The surface and interface roughness of SiO2/4H-SiC(0001) was investigated in terms of Si emission from the interface and oxidation induced compressive stress. It was demonstrated that the SiO2 surface roughness growth was strongly related with oxidation mechanism, as well as SiO2 on Si substrate. A model for surface roughening was proposed with areal Si density and Young’s modulus to inclusively explain the surface roughness of SiO2 on various substrates.
Effects of Surface Morphological Defects and Crystallographic Defects on Reliability of Thermal Oxides on C-Face
Authors: Suzuki Takuma , Yamaguchi Hirotaka , Hatakeyama Tetsuo , Matsuhata Hirofumi , Senzaki Junji , Fukuda Kenji , Shinohe Takashi , Okumura Hajime
Published: May 2012

The causes of extrinsic failures in time-dependent dielectric breakdown characteristics of gate oxide on C-face of 4H-SiC are examined by comparing breakdown points of tested gate oxides with the images of X-ray topography and those of differential interference contrast microscopy. We have concluded as follows: (1) surface morphological defects that originate from threading screw dislocations degrade reliability of gate oxides. (2) These surface defects are not necessarily found on every wafer. (3) Crystallographic defects are not killer defects of MOSFET per se.
High Temperature Reliability of High-k/SiC MIS Hydrogen Sensors
Authors: Furnival Benjamin J.D. , Wright Nicholas G. , Horsfall Alton B.
Published: May 2012

In this work a Pt/HfO2/SiO2/SiC MIS capacitor is exposed in air at 400°C for 1000 hours, with its oxide capacitance, flatband voltage and density of interface traps being measured at various time intervals. After the structure has been shown to operate reliably for extensive periods of time at 400°C, the C-V characteristics of a device from the same fabrication batch are measured at 300°C in different concentrations of H2 and examined for sensitivity. The results demonstrate that gas sensitive MIS capacitors incorporating high-ĸ dielectrics, have the potential to operate at extreme temperatures for long periods of time. This makes them suitable for deployment in hostile conditions, where regular servicing may not be possible.
High Temperature Ion Implantation and Activation Annealing Technologies for Mass Production of SiC Power Devices
Authors: Tezuka Kazuo , Tsuyuki Tatsurou , Shimizu Saburou , Nakamata Shinichi , Tsuji Takashi , Iwamuro Noriyuki , Harada Shinsuke , Fukuda Kenji , Kimura Hiroshi
Published: May 2012

In this paper, we demonstrate the fabrication of SBD utilizing SiC process line specially designed for mass production of SiC power device. In SiC power device process, ion implantation and activation annealing are key technologies. Details of ion implantation system and activation annealing system designed for SiC power device production are shown. Further, device characteristics of SBD fabricated using this production line is also shown briefly.
The Formation Mechanism of Ni-Based Ohmic Contacts to 4H-n-SiC
Authors: Kuchuk Andrian V. , Gołaszewska Krystyna , Kladko Vasyl P. , Guziewicz M. , Wzorek Marek , Kamińska Eliana , Piotrowska Anna
Published: May 2012

In this work the electrical properties of Ni and Ni2Si contacts on n-type 4H-SiC were correlated to the strong structural changes at the contact/SiC interface upon annealing. We can conclude that only δ-Ni2Si grains play a main role in determining electrical transport properties of the Ni-based ohmic contacts to n-SiC. It is presumed that a recrystallization and texturization of δ-Ni2Si phase on (0001)SiC-surface during high temperature annealing (> 900°C) contributes to the change of barrier heights, as well as specific contact resistance of contacts.
Investigation of Ti3SiC2 MAX Phase Formation onto N-Type 4H-SiC
Authors: Drevin-Bazin Alexia , Barbot Jean François , Cabioc’h Thierry , Beaufort Marie France
Published: May 2012

In this study, investigations on MAX phase Ti3SiC2 formation to n-type 4H-SiC substrates and its ohmic-behaved are reported. Ti-Al layers were deposited onto SiC substrates at room temperature by magnetron sputtering in high vacuum system. Thermal annealing at 1000°C in Ar atmosphere were performed to allow interdiffusion processes. X-ray diffraction and High Resolution Transmission Electron Microscopy reveal that a Ti3SiC2 contact, in perfect epitaxy with 4H-SiC substrate, is so-obtained. In situ annealing experiment underlines the evolution of Ti-Al contact microstructure versus temperature. The evolution of contact system from Schottky to Ohmic behaved is observed by I-V measurements for annealing temperatures larger than 700°C.
GaZnO as a Transparent Electrode to Silicon Carbide
Authors: Lee Jung Ho , Kim Ji Hong , Do Kang Min , Moon Byung Moo , Joo Sung Jae , Bahng Wook , Kim Sang Cheol , Kim Nam Kyun , Koo Sang Mo
Published: May 2012

The characteristics of Ga-doped zinc oxide (GaZnO) thin films deposited at different substrate temperatures (TS~250 to 550oC) on 4H-SiC have been investigated. Structural and electrical properties of GaZnO thin film on n-type 4H-SiC (100)were investigated by using x-ray diffraction, atomic force microscopy (AFM), Hall effect measurement, and Auger electron spectroscopy (AES). Hall mobility is found to increase as the substrate temperature increase from 250 to 550 oC, whereas the lowest resistivity (~3.3 x 10-4 Ωcm) and highest carrier concentration (~1.33x1021cm-3) values are observed for the GaZnO films deposited at 400 oC. It has been found that the c-axis oriented crystalline quality as well as the relative amount of activated Ga3+ Introduction ions may affect the electrical properties of GaZnO films on SiC.
Common Metal Die Attachment for SiC Power Devices Operated in an Extended Junction Temperature Range
Authors: Tanimoto Satoshi , Matsui Kohei , Zushi Yusuke , Sato Shinji , Murakami Yoshinori , Takamori Masato , Iseki Takashi
Published: May 2012

A new high-temperature die attachment system that is cost effective has been strongly desired for SiC power applications in electric vehicles and consumer electronics. This paper presents preliminary results for SiC/Zn-Al/Cu-SiN die attachments using eutectic Zn-Al solder (m.p. = 356°C), focusing on preparation and die-shear reliability. Superior wettability and reproducibility were achieved in the soldering process. It was found that the attachments were viable at least for short-term application in a temperature range up to 300°C. Reliability test results revealed that they could withstand storage for 1500 hours at 200°C and thermal cycle stress of 1500 cycles between –40°C and 200°C.
Metal Work-function and Doping-Concentration Dependent Barrier Height of Ni-Contacts to 4H-SiC with Metal-Embedded Nano-Particles
Authors: Kang Min Seok , Lee Jung Ho , Hallén Anders , Zetterling Carl Mikael , Bahng Wook , Kim Nam Kyun , Koo Sang Mo
Published: May 2012

We investigated the effect of the metal work-function and doping concentration on the barrier height of Ni-contacts with embedded nano-particles (NPs) on 4H-SiC surfaces. Both n-type epitaxial layers with ND=1×1016 cm-3, and layers doped by phosphorous implantation to a doping concentration of ~1×1019 cm-3 are used. The barrier height is reduced with increasing doping concentration and the silver (Ag) nano-particles (R~18.5 nm) further enhances the local electric field of the electrical contacts to 4H-SiC in comparison to gold (Au) nano-particles (R~20.2 nm). In the case of ion-implanted samples, the barrier height of the fabricated SiC diode structures with embedded Ag-NPs was significantly reduced by ~0.09 eV and ~0.25 eV compared to the samples with Au-NPs and the sample without NPs, respectively.
Cutting Speed of Electric Discharge Machining for SiC Ingot
Authors: Yamada Hideki , Yamaguchi Satarou , Yamamoto Norimasa , Kato Tomohisa
Published: May 2012

A new method based on electric discharge machining (EDM) was developed for cutting a silicon carbide (SiC) ingot. The EDM method is a very useful technique to cut hard materials like SiC. By cutting with the EDM method, kerf loss and roughness of sample are generally smaller than those obtained by cutting with a diamond saw. Moreover, the warpage is smaller than that by the diamond saw cutting, and the cutting speed can be 10 times faster than that of the diamond saw at the present time. We used wires of 50 mm and 100 mm diameters in the experiments, and the experimental results of the cutting speed and the kerf losses are presented. The kerf loss of the 50 mm wire is less than 100 mm, and the cutting speed is about 0.8 mm/min for the thickness of a 6 mm SiC ingot. If we can maintain the cutting speed, the slicing time of a 2 inches diameter ingot would be about seven hours.
Cutting of SiC Wafer by Atmospheric-Pressure Plasma Etching with Wire Electrode
Authors: Sano Yasuhisa , Aida Kohei , Kato Takehiro , Yamamura Kazuya , Mimura Hidekazu , Matsuyama Satoshi , Yamauchi Kazuto
Published: May 2012

Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, it is so hard and chemically stable that there are few efficient conventional machining methods for it. We have developed plasma chemical vaporization machining (PCVM), an atmospheric-pressure plasma etching process, and investigated its application to the processing of SiC substrates. In this paper, the cutting characteristics of a SiC substrate by PCVM with a wire electrode are described. We found that increasing the rf power and reactive gas concentration increases the etch rate and that the etch width can be reduces by increasing the SF6 concentration. The maximum etch rate was 2.1 μm/min and the minimum etch width was 220 μm. It was also demonstrated that a SiC wafer prethinned to 100 μm can be successfully cut without breaking or cracking.
Growth and Light Properties of Fluorescent SiC for White LEDs
Authors: Syväjärvi Mikael , Yakimova Rositza , Iwaya Motoaki , Takeuchi Tetsuya , Akasaki Isamu , Kamiyama Satoshi
Published: May 2012

The LED technology started to developed many years ago with red light emitting diodes. To achieve the blue LED, novel growth technologies and process steps were explored, and made it possible to demonstrate efficient blue LED performance from nitrides. The efficiency was further developed and blue LEDs were commercially introduced in the 1990’s. The white LED became possible by the use of the blue LED and a phosphor that converts a part of the blue light to other colors in the visible range to combine into white light. However, even today there are limitations in the phosphor-based white LED technology, in particular for general lighting, and new solutions should be explored to speed the pace when white LEDs will be able to make substantial energy savings. In this paper we overview gallium nitride materials evolution and growth concepts for LEDs. We describe the fluorescent silicon carbide material prepared by a novel growth technology for a new type of white LED in general lighting with pure white light. This paper introduces an interesting research in fundamental growth and optical properties of light emitting silicon carbide.
Epitaxial Growth, Mechanical, Electrical Properties of SiC/Si and SiC/Poli-Si
Authors: Bosi Matteo , Attolini Giovanni , Watts Bernard Enrico , Roncaglia Alberto , Poggi Antonella , Mancarella Fulvio , Moscatelli Francesco , Belsito Luca , Ferri Matteo
Published: May 2012

We have investigated 3C-SiC layers grown on silicon and on poli-Si in order to realize test MEMS structures. The strain of the films were investigated by the fabrication of cantilevers, beams, springs and we successfully fabricated a Double-Ended-Tuning-Fork double clamped SiC resonator on the film, with perfectly aligned actuation electrode.
Impact of Surface Morphology above Threading Dislocations on Leakage Current in 4H-SiC Diodes
Authors: Hirokazu Fujiwara , Katsuno T. , Ishikawa Tsuyoshi , Naruoka H. , Konishi Masaki , Endo T. , Watanabe Y. , Tsuruta K. , Onda S. , Adachi A. , Nagao M. , Hamada Kimimori
Published: May 2012

The impact of threading dislocation density on the leakage current of reverse IV characteristics in 1.2 kV Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSDs), and PN junction diodes (PNDs) was investigated. The leakage current density and threading dislocation density have different positive correlations in each type of diode. For example, the correlation in SBDs is strong, but weak in PNDs. The threading dislocations were found to be in the same location as the current leakage points in the SBDs, but not in the PNDs. Nano-scale inverted cone pits were observed at the Schottky junction interface in SBDs, and it was found that leakage current increases in these diodes due to the concentration of electric fields at the peaks of the pits. These nano-scale pits were also observed directly above threading dislocations. In addition, this study succeeded in reducing the leakage current variation of 200 A-class JBSDs and SBDs by eliminating the nano-scale pits above the threading dislocations. As a result, a theoretical straight-line waveform was achieved.
Experimental Demonstration of 1200V SiC-SBDs with Lower Forward Voltage Drop at High Temperature
Authors: Tsuji Takashi , Kinoshita Akimasa , Iwamuro Noriyuki , Fukuda Kenji , Tezuka Kazuo , Tsuyuki Tatsuro , Kimura Hiroshi
Published: May 2012

The 1200V class silicon carbide Schottky barrier diodes were designed and fabricated. The drift layer resistance was reduced in order to realize low forward voltage drops. Since the low drift layer resistance led to the low breakdown voltage, the avalanche withstanding capability should be enhanced not to cause the destructive breakdown. By means of the optimized device design, we succeeded to realize the low forward voltage drop while maintaining the high avalanche withstanding capability. The forward voltage drops at 200A/cm2 were 1.35V at 25°C and 1.63V at 175°C, respectively. The avalanche withstanding capability was more than 3500mJ/cm2 at 25°C. By substituting SiC-SBDs for Si-pin diodes, the estimated total power loss of the module comprised by Si-IGBTs and the diodes was reduced by 35%. We could also confirm that no failures happened after long term reliability tests.
A Fully Electrically Isolated Package for High Temperature SiC Sensors
Authors: Brezeanu Gheorghe , Draghici Florin , Badila Marian , Rusu Ion , Bernea Florin , Godignon Philippe
Published: May 2012

A fully electrically isolated package for a SiC temperature sensor, able to work at high temperature, is presented in this paper. The adopted packaging solution was tested under thermal stress by varying the temperature between 300C and 400C (for 500 cycles) and between 50C and 400C (for other 500 cycles). The thermal stress had negligible effect on the capsules leakage currents (measured from the sensor terminals to the package metal casing) and did not degrade the glass which ensures the sealing of the capsule. The measurements and microphysical investigations showed a stable operation of the package up to temperatures of 400C.
Current Distribution in the Various Functional Areas of a 600V SiC MPS Diode in Forward Operation
Authors: Rupp Roland , Gerlach Rolf , Kabakow Andre
Published: May 2012

The forward current distribution in SiC 600V merged pn-Schottky (MPS) diodes is visualized with the help of emission microscopy at various current densities. It is shown how the light emission develops with increasing current densities and extends from the Schottky contact areas into the pn junction areas. Large p+-regions e.g. in the edge termination contribute first by minority carrier injection, whereas the smaller p+ hexagonal cells and the p+ grid follow subsequently.
Influence of Anode Layout on the Performance of SiC JBS Diodes
Authors: Radhakrishnan Rahul , Zhao Jian Hui
Published: May 2012

Various layouts of the anode of Junction Barrier Schottky (JBS) diodes are compared theoretically and it is found that the hexagonal honeycomb structure with 3-D symmetry offers the best figure of merit (FOM). Proportional relationships between the various layouts are reported, using which we extend a fully analytical 2-D model for reverse biased field shielding in a JBS diode to the superior 3-D layouts. The effect of reducing implanted feature size is also analyzed as a trade-off between FOM and breakdown voltage capability.
Hybrid Si-IGBT/SiC Rectifier Co-Packs and SiC JBS Rectifiers Offering Superior Surge Current Capability and Reduced Power Losses
Authors: Sundaresan Siddarth G. , Sturdevant Charles , Issa H. , Marripelly Madhuri , Lieser Eric , Singh R.
Published: May 2012

Novel device design and process innovations made at GeneSiC on SiC JBS rectifiers result in a significant increase in surge current capability with a 33% decrease in power dissipation at 10x rated current. On the 1200 V-class rectifiers, a clear signature of avalanche-limited breakdown with ultra-low leakage currents is observed at temperatures as high as 240 °C. Almost temperature independent Schottky barrier heights of 1.2 eV and ideality factors 2K2 (for 4H-SiC) is directly extracted from the forward I-V characteristics. When compared with an off-the-shelf all-Si IGBT power co-pack, GeneSiC’s GA100XCP12-227 co-pack offers 88% and 47% reduction at 125 °C in the IGBT and free-wheeling diode switching energy losses, respectively. This results in an overall switching loss reduction of about 28% as compared to its silicon counterpart.
Transient Electrical Characteristics of Electron Irradiated High Blocking Voltage 4H-SiC Pin Diode
Authors: Asano Katsunori , Tanaka Atsushi , Ogata Shuuji , Nakayama Koji , Miyanagi Yoichi
Published: May 2012

The transient electrical characteristics of the forward recovery and reverse recovery characteristics of lifetime-controlled high blocking voltage 4H-SiC pin diodes by electron irradiation are investigated. Even at a heavy electron dose of 1×1014 cm-2, the forward voltage overshoot of a 4H-SiC pin diode is lower than that of a 2 kV/100 A class Si fast diode. As for the reverse recovery characteristics, small reverse recovery current and fast reverse recovery time are obtained by electron irradiation. The reduction ratio of recovery loss can therefore exceed the increase ratio of steady-state loss by electron irradiation.
Positive Temperature Coefficient SiC PiN Diodes
Authors: Imhoff Eugene A. , Hobart Karl D. , Kub Francis J. , Ancona M.G. , Myers-Ward Rachael L. , Garces N.Y. , Wheeler Virginia D. , Nyakiti Luke O. , Eddy Charles R. , Gaskill D. Kurt
Published: May 2012

Integration of patterned ballast resistance into the anode of SiC PiNs is a solution to the dilemma of negative dVf /dT for such diodes. In fabricated 4H-SiC PiN diodes, we demonstrate a cross-over from negative to positive temperature coefficient for current densities as low as 80 A/cm2. Adjusting the percentage of the patterned anode area, the positive or neutral dVf /dT can be achieved over a wide current-density range without substantial penalty in the forward voltage drop. This characteristic is crucial for high-power SiC packages with ganged-parallel rectifier arrays.
Fully Ion Implanted Vertical p-i-n Diodes on High Purity Semi-Insulating 4H-SiC Wafers
Authors: Nipoti Roberta , Nath Anindya , Tian Yong Lai , Tamarri Fabrizio , Moscatelli Francesco , de Nicola Pietro , Rao Mulpuri V.
Published: May 2012

The fabrication of a fully ion-implanted and microwave annealed vertical p-i-n diode using high purity semi-insulating 4H-SiC substrate has been demonstrated for the first time. The thickness of the intrinsic region is the wafer thickness 350 µm. The anode and cathode of the diode have been doped with Al and P, respectively, to concentrations of few times 1020 cm-3 by ion implantation. The post implantation annealing has been performed by microwave heating the samples up to 2100°C. The device rectifying behavior indicates that a carrier modulation takes place in the bulk intrinsic region.
Electrical Characteristics of 4H-SiC Pin Diode with Carbon Implantation or Thermal Oxidation
Authors: Nakayama Koji , Tanaka Atsushi , Asano Katsunori , Miyazawa Tetsuya , Ito Masahiko , Tsuchida Hidekazu
Published: May 2012

The forward voltage drops of pin diodes with the carbon implantation process or thermal oxidation process using a drift layer of 120 μm thick are around 4.0 V and are lower than those with the standard process. The reverse recovery characteristics of diodes with the standard process or carbon implantation at room temperature show almost the same tendency. In the reverse recovery characteristics at 250 oC, pin diodes with carbon implantation process, however, have the longer reverse recovery time than those with the standard process. These characteristics indicate that a recombination path other than the bulk carrier lifetime, such as the interfaces or the surface recombination, becomes dominant in the reverse recovery characteristics at room temperature.
Physical Modelling of 4H-SiC PiN Diodes
Authors: Fisher Craig A. , Jennings Michael R. , Bryant Angus T. , Pérez-Tomás Amador , Gammon Peter Michael , Brosselard Pierre , Godignon Philippe , Mawby Philip  Andrew
Published: May 2012

With the recent technological advances in 4H-SiC PiN diode fabrication, simulation tools which enable the accurate and rapid prediction of losses of such devices in power electronics circuits will be increasingly sought-after. To this end, a physical electro-thermal model of the 4H-SiC PiN diode has been developed, which facilitates device optimization for power circuit applications. The performance of this model has been compared with both finite element simulations and experimental results; good matching for both switching and conduction characteristics has been observed.
Thermal Stress Response of Silicon Carbide pin Diodes Used as Photovoltaic Devices
Authors: Barker Simon , Vassilevski K.V. , Nikitina I.P. , Wright Nicolas G. , Horsfall A.B.
Published: May 2012

Recent progress in the field of silicon carbide sensor technology, such as wireless communications and sensors, has demonstrated the need for a resilient energy supply as an alternative to conventional batteries. Previous work has shown that silicon carbide is an effective energy harvester of UV light in high temperature and hostile environments. Until now however, there has been little work undertaken to assess the long-term effects of elevated temperature on such devices. Although it is understood that silicon carbide is unaffected by long-term temperature exposure below 400 °C, there has been little research into the overall device response and how changes in contact metallisation affect the photovoltaic behaviour.
Correlation of Surface Properties and Photocatalytic Activity of Nanocrystalline TiO2 on the Synthesis Route
Authors: Lazar Manoj A. , Tayade Rajesh J. , Bajaj H. C. , Jasra R. V.
Published: May 2012

Present work describes the synthesis of nanocrystalline TiO2 photocatalyst using sol-gel and solution combustion methods and their characterisation by powder X-ray Diffraction, Diffuse Reflectance Spectroscopy, surface area measurement, FT-IR, FT-Raman, Thermo Gravimetric Analysis, and Transmission Electron Microscopy. Their photocatalytic activity was evaluated by the degradation of two nitro aromatic pollutants, viz. para-nitroaniline (PNA) & meta-dinitrobenzoic acid (DNBA) commonly observed in nitroaromatic plants. Performance of the synthesized catalysts was compared with commercial Degussa P25 sample. The photocatalytic degradation and total mineralization were monitored using UV/VIS spectrophotometer and total organic carbon content analysis respectively. The materials properties such as crystallinity and surface hydroxyl group on the nanocrystalline TiO2 played crucial role for the total mineralization of the nitroaromatics.
Characterization of Multi-Walled Carbon Nanotubes/Natural Rubber Nanocomposite by Wet Mixing Method
Authors: Azira Abd Aziz , Hassim Dayang Habibah Abangismawi I. , Suriani Abu Bakar , Mahmood Mohamad Rusop
Published: May 2012

Multi-walled carbon nanotubes/natural rubber (MWCNTs/NR) nanocomposites is formed by incorporating nanotubes in a polymer solution and subsequently evaporating the solvent. Using this technique, nanotubes will be dispersed homogeneously in the NR matrix in an attempt to increase the mechanical properties of these nanocomposites. Mechanical test results show an increase in the tensile strength for up to 19 times in relation to pure NR. In addition to mechanical testing, the morphology of the MWNTs into NR was studied by Field Emission Scanning Electron Microscopy (FESEM) in order to understand the morphology of the resulting system. Slight shift noted from FTIR and Raman analyses from each different wt. % of MWCNTs with the NR due to the stress transfer that indicates reinforcement of the nanotubes.