bluuebunny/crossref_metadata_2025 huggingface dataset:
Tuning Photoresponse of Ultrathin ZnO Films Using Few Angstrom Al2O3 Overlayers
Authors: Wu Fei , Myung Yoon , Banerjee Parag
Published: February 2020

Ultra-thin ZnO films can be deposited with precise thickness control, good conformality and uniformity by atomic layer deposition (ALD). This strategy has been widely used in optical devices and solar cells.[i] However, ZnO with a thickness less than 10 nm – where surface effects dominate electronic transport properties, has been found to possess a high degree of electronic defects.[ii] These defects originate on the surface as unterminated, dangling bonds and degrade electronic and optoelectronic transport properties.[iii]

To understand the phenomena further, we report here temperature-based (80K-320K) conductance and photoresponse (Ion/Ioff) properties of 6.1 nm ZnO. Further, we track these parameters as a function of ALD Al2O3 ‘overlayers’ deposited on the same ZnO film. The temperature based Ion/Ioff is shown in Figure 1, left and the maximum Ion/Ioff is shown as a function of ALD Al2O3 overlayers in Figure 1, right. Based on these data, the Ion/Ioff ratio initially increases with the number of ALD Al2O3 layers and maximizes at 7 cycles of Al2O3 overlayer. It then decreases for additional ALD Al2O3 cycles. A maximum Ion/Ioff of 11.4x is obtained with 7 cycles of ALD Al2O3.

Activation energy (Ea) for conduction will be estimated using conductance vs. temperature curves.[iv] Accompanying data using XPS and photoluminescence will structurally probe the surface modification of the ZnO due to addition of the ALD Al2O3monolayers. These results lead to insights into the passivation mechanisms of ultrathin ZnO films with applications in a wide variety of electronic and optoelectronic devices.

Figure 1. Left - The Ion/Ioff vs. temperature (left) and, Right - The maximum Ion/Ioff plotted with number of ALD Al2O3 cycles. (*Ion/Ioffis defined by the light conductance over the dark conductance.)

[i] a) Lee, D.-J., Kim, H.-M., Kwon, J.-Y., Choi, H., Kim, S.-H., Kim, K.-B. Adv. Funct. Mater. 2011, 21, 448-455. b) Wang, J.-C., Weng, W.-T., Tsai, M.-Y., Lee, M.-K., Lee, M.-k., Horng, S.-F. Perng, T.-P., Kei, C.-C., Yu, C.-C. Meng, H.-F. J. Mater. Chem. 2010, 20, 862-866.

[ii] a) Cheun, H., Fuentes-Hernandez, C., Zhou, Y., Potscavage, W. J., Kim, S.-J., Shim, J., Dindar, A., Kippelen, B. J. Phys. Chem. C 2010, 114, 20713-20718. b) Na, J.-S., Scarel, G., Parsons, G. N. J. Phys. Chem. C 2010, 114, 383-388.

[iii] Cheun, H., Fuentes-Hernandez, C., Zhou, Y., Potscavage, W. J., Kim, S.-J., Shim, J., Dindar, A., Kippelen, B. J. Phys. Chem. C 2010, 114, 20713-20718.

[iv] Wu, F., Tian, L., Kanjolia, R., Singamaneni, S., Banerjee, P. ACS Appl. Mater. Interfaces, 2013, 5, 7693-7697.
Plasmonics and Metamaterials with Transparent Conducting Oxides
Authors: Abb Martina , Wang Yudong , Traviss D , Bruck R , de Groot C. H. , Chong Harold , Sepulveda Borja , Muskens Otto L.
Published: February 2020

With the maturation of the field of plasmonics, there is an increasing interest to develop new materials for plasmonics and field-enhanced spectroscopy. In particular, the combination with complementary functionalities, such as active control, is of importance. Metal oxides form an interesting materials platform with many applications in catalysis, chemical sensing, transparent conductors or heat reflective coatings.

Here, I will present our recent results on the use of highly conductive metal oxides such as indium-tin-oxide (ITO) and aluminium-doped ZnO (AZO) in active plasmonics and metamaterials [1-4]. We can define three windows of operation for these materials, corresponding to the regimes of dielectric [1,2], metallic [3], and epsilon-near zero [4] response. By combining metal oxides with plasmonic materials such as gold and silver, we explore new types of hybrid response with the potential of electrical and picosecond optical control of plasmon resonances [1]. This includes combination of lithographically defined plasmonic nanostructures with coatings obtained using atomic layer deposition (ALD) [2].

Further in the mid infrared spectral range, the plasmonic response of highly doped metal oxides can be used for spectroscopic characterization of molecular species using Surface Enhanced Infrared Absorption [3]. We have developed new methods for the fabrication of metal oxide antennas and have demonstrated their use as plasmonic devices for infrared molecular fingerprinting. Finally, an intermediate regime is explored where the ITO permittivity approaches zero and the optical response is governed by superluminal group velocity enabling new plasmonic modes with large nonlinearity [4].

[1] M. Abb, Y. Wang, P. Albella, C. H. de Groot, J. Aizpurua, O. L. Muskens, ACS Nano 6, 6462 (2012)

[2] M. Abb, B. Sepulveda, H. M. H. Chong, O. L. Muskens, J. Opt. 14, 114007 (2012)

[3] M. Abb, Y. Wang, N. Papasimakis, C. H. de Groot, O. L. Muskens, Nano Lett 14, 346 (2014)

[4] D. Traviss, R. Bruck, B. Mills, M. Abb, O. L. Muskens, Appl. Phys. Lett. 102, 121112 (2013)
Experiments and Modeling of Gas Heating in a Radio-Frequency Plasma Jet
Authors: Boswell Rod , Charles Christine , Greig Amelia , Dixon Sam
Published: February 2020

Small plasma sources have been developed for a variety of applications and are often known as plasma jets (e.g. biomedical applications using atmospheric pressure helium or argon plasmas), as micro-plasma sources or arrays [1] (e.g. surface processing using lower operating pressure plasmas), or as micro-thrusters (e.g. electric propulsion using hollow cathode thrusters or neutralizers). At the ANU we have designed a capacitively coupled radiofrequency (13.56 MHz) cylindrical plasma source which currently operates at pressures around a few Torr and at powers ranging from 1-100 Watts with or without a pressure gradient imposed along the 2 cm long cavity [2]. The plasma diameter ranges from 1 to 6 mm before expanding in a larger chamber. Neutral gas heating is measured for a variety of gases (argon, nitrogen, xenon) and cavity diameters using optical emission spectroscopy. The results are combined with electric probe measurements to develop a plasma heating model where the heating is assumed to come from ion-neutral collisions in the maximum of the discharge under the powered electrode. A peaked density on axis is well described by the plasma model [2]. Typically, gas temperatures around 1000K are measured for N2 and Ar in agreement with theoretical predictions from Fruchtman [3]. The results show that this type of source can be tailored to suit a variety of plasma applications: its effectiveness in dissociating species means that it can be used for remote plasma etching [1] or for surface passivation from atomic nitrogen using N2. It can also be developed as an electrothermal plasma micro-thruster for space propulsion[2]. All of these applications benefit from the neutral gas heating and from the ability of the source to be developed as an array of sources.

REFERENCES:

[1]S. Dixon, C. Charles, R. Boswell, W. Cox, J. Holland and R. Gottscho, “Interactions between arrayed hollow cathodes”, J. Phys. D: Appl. Phys. 46, 145204, 2013

[2]C. Charles and R.W. Boswell, “Measurement and modeling of a radiofrequency micro-thruster”, Plasma Sources Sci. Technol. 21, 022002, 2012

[3]A. Fruchtman, “Energizing and depletion of neutrals by a collisional plasma”, Plasma Sources Sci. Technol. 21, 022002, 2012
A Stable Cu Nanoparticles Used for Seed Layer Deposition of through Silicon Via
Authors: Tsai Yao-Lin , Dow Wei-Ping
Published: February 2020

In recent years, the evolution of two-dimensional (2D) chip packaging will soon reach its limitation. As a result, signiﬁcant attention is being paid to three-dimensional (3D) chip stacking. 3D chip stacking offers many beneﬁts to improve system performance, the most signiﬁcant of which is the ability to directly connect heterogeneous devices in the vertical direction. Thus, 3D chip stacking can reduce the size of packaging and increase system efficiency as well as saving capacitance, reducing power and increasing speed.

Through silicon via (TSV) is a key technology for 3D chip stacking, which serves as a bridge to connect multiple devices in z-direction. Comparing with the traditional through silicon via (TSV) metallization, it has to thin the wafer thickness by using chemical mechanical polishing (CMP) after the copper electroplating and go on the chip stacking process. Alternatively, wafer thinning can be processed first before making through holes. Following the wafer thinning and through hole drilling, the through silicon hole (TSH) can be fully filled with copper by direct electroplating without using a conducting template. The metallization of TSHs is a critical step in the manufacture process. Up to known, the traditional semiconductor industry uses sputtering process to deposit a barrier layer and a seed layer on a isolation layer (SiO2) inside the TSH. However, the sputter machine is very expensive. We introduce a wet process to replace the dry seed layer deposition process.

We made use of a flexible substrate to synthesize copper nanoparticles (CuNPs). The mean particle size of the CuNPs is below 10 nm and its size distribution is from 4 to 6 nm(Fig 1).Therefore, they perform a high activity in Cu electroless deposition. However, the CuNPs were unstable when they exposure to air, such that their activity decreased day by day. For this issue, we use a novel stabilizer to make the CuNPs survive for a long time(Fig 2) and still have good activity to catalyze copper eletroless deposition. Because silicon oxide is a non-conducting material, it has to be metalized by Cu electroless deposition and then by Cu electroplating. For the Cu electroless deposition process, we employed the CuNP as a catalyst for copper electroless deposition onto the sidewall of TSH in order to develop a wet TSH process. These processes ensure the complete electroless copper coverage inside the THS, which is coherent and conductive enough to allow TSH to be fully filling with Cu electroplating.
Electroless Plating for Seed Layer Deposition and Direct Metallization of Glass for Interposer Fabrication
Authors: Cordonier Christopher , Okabe Kyouhei , Honma Hideo
Published: February 2020

As a silicon substitute for interposer substrate, much attention has been turning to glass recently. Glass presents a number of advantages over traditionally used silicon such as low cost, small footprint, transparency, electrical insulation and potential for roll to roll or large area processing. However, it also bears shortcomings such as low thermal conductivity and difficulty in via formation. As economy is a major incentive for developing glass packaging technology, high cost fabrication techniques used for silicon, like sputtering, hinder the potential for application. To contribute to glass packaging development, a method for copper plating directly on glass substrate was proposed where an electroless copper seed layer is deposited then electro copper plating and via filling, followed by thermal diffusion to increase the adhesion (Scheme 1). A porous thin metal oxide film of a few ten nanometers fused to the substrate was used to support the catalyst for and anchor the seed layer to glass. The solution processed metal oxide films can be deposited by economic solution processing, can be applied to large area, do not impair substrate transparency, and maintain a smooth interface between copper and glass. Compared to alternative direct plating techniques that involve roughening the glass surface, impedance characteristics conducive to high frequency devices can also be expected. Two catalyst systems were investigated; adsorption of palladium onto the metal oxide film and inclusion of copper in the metal oxide, both of which sufficiently initiated autocatalytic reactions. Although seed layers showed high adhesion, adhesion significantly deteriorated after electroplating. As a solution to adhesion failure, thermal infusion of plated copper into the glass substrate was implemented resulting in 90° peel strengths of 0.3-0.4 kN/m for borosilicate glass and 0.5-0.6 kN/m for soda-lime glass. To allow thermal treatment under oxygen containing atmosphere, a high temperature resistant silica based oxidation prevention treatment was developed. With the anti-oxidation treatment, copper plating could be treated at up to 500°C in air without discoloration. Formation and mechanism of the passivation layer was analyzed by GD-OES and discussed. In circumstances where patterning is performed, this metallization method may prove compatible with subtractive and semi-additive methods, however the initially coated metal oxide anchor precursor films were found to be photodefinable. Based on photopatterning of the metal complex films that served as the metal oxide precursors, fully additive plating methods were also investigated. Photochemistry of the metal complexes and direct pattern plating will also be discussed.
Behavior of Cuprous Intermediate by RRDE
Authors: NIshimura Kouhei , Yokoi Masayuki , Kondo Kazuo , Hayashi Taro , Okamoto Naoki , Saito Takeyasu
Published: February 2020

1.
Introduction

The cuprous ion is crucial intermediate and the cuprous ion always produced during the process of the electrodeposition.

It is extremely difficult to detect the cuprous ion and accordingly few works exist which are related to the acceleration effect of cuprous ion.

Acceleration effect of trench via bottom electrode was presented in the San Francisco Meeting. Rotating ring disk electrode(RRDE) result will be presented. The cuprous ion detected at the ring of RRDE is 1000 times larger for the copper dissolution, if it is compared with cuprous ion for the electrodeposition[1]. Hence we formed cuprous ion at the disk of rotating disk electrodes and experimentally verify the relation between cuprous ion and acceleration.

2.Results

The ring electrode current of RRDE has been monitored in order to detect the free cuprous intermediate acceleration effect.

Figure 1 shows the ring current density by changing the ring potential. (a) is with no additive without dissolving the copper disk electrode. The ring current shows the lowest(a). With dissolving the copper disk electrode(forming cuprous), the ring current increases slightly(b). By adding 1ppm of SPS and 50ppm of Cl-, with dissolving copper, the ring current further increases(d). Further adding 40ppm of SPS and 50ppm of Cl-, with dissolving copper, the ring current shows the larger value[6]. These results indicate that Cl-and SPS are the accelerating additive and these additives forms accelerating intermediate with the cuprous.

We proposed a new cuprous intermediate model and this model is shown in Fig.2[9]. Cl- has been known to adsorb on the cathode(7). The Cl- forms electron bridge and reduces SPS to MPS(8). Cupric and MPS forms Cu+-MPS. The Cu+-MPS decomposes into SPS and cuprous and hence reduces to copper. The cuprous supplied by dissolving the copper disk electrode is accelerating the copper electrodeposition. The details will be presented at the meeting.

References

1.J.R.White, J.Electrochem.Soc.17,977(1987)

2.K.Kondo, T.Matsumoto and K.watanabe, J. Electrochem. Soc. 151,C250 (2004).

3.K.Kondo, T.Yonezawa,J.Electochem.Soc. 152(12), H173-H177 (2005).

4.Kazuo Kondo, Taichi Nakamura J.Appl.Electrochem.,39,1789(2009).

5.Kazuo Kondo, Hamazaki Kouta, ECS ELectrochem.Let., 3 (4) D3-D5(2014).

6.Yi-Hsin Chen and Dale Barkey, University of New Hampshire.

7.C.B . Elders and J.L. Stickney, J. Eleetroanaf. Chem., 284 403-412(1990).

8.Z.Nagy and J.P.Blaudeau, J.Electrochem.Soc. 142,L87(1995).

9.Nguyen T. M. Hai, J.Phys.Chem.C,116,6913(2012).
Glyoxylic Acid as Reducing Agent for Electroless Copper Deposition on Cobalt Liner
Authors: Inoue Fumihiro , Philipsen Harold , van der Veen Marleen , Van Huylenbroeck Stefaan , Armini Silvia , Struyf Herbert , Shingubara Shoso , Tanaka Tetsu
Published: February 2020

Cobalt has recently attracted interest as interconnect liner, because it can serve as nucleation layer for Cu deposition [1,2]. Nevertheless, in order to apply it in combination with a wet Cu deposition process, the dissolution of Co has to be taken into account since less-compatible with acidic and more negative redox potential than Cu.

Using an electroless deposition (ELD) of Cu chemistry with alkaline pH has the advantage of less-dissolution of Co and, therefore, a thinner Co liner can be used. This would be beneficial for small feature filling. Nevertheless, formaldehyde, which is conventional reducing agent of Cu, did not show catalytic effect on Co surface [3]. In this case, the nucleation mechanism on Co is a replacement reaction, during which some cobalt is consumed during ELD-Cu reaction that is in competition with ELD-Cu deposition reaction in the initial stage of the Cu film growth.

In this paper, we investigate minimization of Co consumption by analyzing each component of glyoxylic acid based ELD Cu.

Figure 1 shows polarization analysis of glyoxylic acid and formaldehyde on Co surface. In case of formaldehyde, there is no anodic oxidation. On the other hand, glyoxylic acid showed anodic oxidation on Co. It indicates that glyoxylic acid shows catalysis on Co.

Figure 2 shows linear sweep voltammetry of Cu complex solutions. When higher concentration of complexing than Cu ion was added, oxidation occured without reduction of Cu. In general, enough amount of complexing agent is added in the ELD solution to avoid generation of Cu hydroxide ions. However, the complexing agent also makes Co-complex. On the other hand, when the same amount of complexing agent was added (i.e. no ‘free’ complexing agent in the bath), there was no Co dissolution, which was deduced from electrochemical measurements.

Figure 3 shows the cross-sectional TEM images and TEM-EDX images of a 3 × 50 µm TSV after ELD-Cu on CVD-Co (45 nm)/ALD-TiN (12 nm). The Co thickness was 45 nm on top and 10 nm at the bottom. The ELD solution contained the identical concentrations of complexing agent and Cu ion. Glyoxylic acid was used as reducing agent. A continuous Cu seed was obtained in the TSV along the sidewall. Neither delamination nor voids were seen after ELD. Furthermore, the Co thickness in entire TSV did not changed. It is due to the optimization of complexing agent and reducing agent inside Cu bath.

The filling of the TSVs was performed by electrodeposition on the ELD-Cu seed. The continuous ELD-Cu seed layer promoted a bottom-up filling of the TSV afterwards.

References

[1] S. Armini et al., J. Electrochem. Soc., 158 (2) (2011) H160

[2] T. Nogami, et al., Proc. of IEEE IITC (2013) 11-1

[3] I. Ohno, et al., J. Electrochem. Soc.,132 (10) 2323 (1985)
Effect of Flow and Wafer Rotation on the Metallization of Copper Interconnects
Authors: Boehme Lindsay , Landau Uziel
Published: February 2020

The miniaturization of semiconductor devices poses challenges to interconnect metallization. Transport limitations within the features, which affect primarily the distribution of the additives, have been studied extensively in the past, experimentally and analytically1
-
3. However, the effect of transport external to the small features (vias or trenches), has not previously been addressed. Such transport limitations, that are directly related to the external flow and the wafer rotation, will affect the concentration of the species diffusing into the feature and thus may have profound effect on the feature fill process. We analyze here the effects of the external flow field and the boundary layer on the additives surface coverage and the via fill process.

Applying a computer based model, we analyze first the additives (suppressor, e.g., PEG, and anti-suppressor, e.g., SPS) distribution on a flat wafer. We determine the transient additives coverage on the surface and find, as expected, that the transport limited suppressor concentration increases with the rotation rate4. More significant is the analysis of the additives distribution on the sidewalls and the bottom of a via. We find that the transport and adsorption parameters applied in the model strongly affect the results. Applying commonly used parameters1
-
3 and considering the external transport limitations leads to a significantly lower suppressor concentration at the via rim and upper sidewalls (as shown in Fig. 1) than had been previously predicted2. This will consequently lead to inadequate fill. However, when applying transport and adsorption parameters that have been recently determined by co-injection studies4we note that the external flow has a significantly lower impact on the additives concentration within the via. Accordingly, the simulated process, accounting for the flow effects follows more closely predictions which neglected to consider the external boundary layer (Fig. 2). Experimental data reported in the literature indicates similar trends to those predicted by the current analysis.

References:

R. Akolkar and U. Landau, J. Electrochem. Soc., 151, C702 (2004).

R. Akolkar and U. Landau, J. Electrochem. Soc., 156, D351 (2009).

J. Adolf and U. Landau, J. Electrochem. Soc.,
158, D469 (2011).

L. Boehme and U. Landau, “Applying the Co-injection Test to Extract Difficult to Measure Process Parameters”, 226th ECS Meeting, October 5-10, 2014, Cancun, Mexico.
Electroless Deposition of Cu-Mn Alloy
Authors: Yu Lu , Akolkar Rohan
Published: February 2020

Interconnect scaling in semiconductor devices presents numerous challenges to the current dual-damascene process flow. One issue is the deteriorated Cu electromigration resistance, which shortens the device life. To address this problem, one approach is to dope the Cu interconnects with small amounts of manganese (Mn). The Mn segregates at the interface between Cu and the dielectric substrate and forms a barrier layer, thereby suppressing Cu diffusion. It was found that incorporation of ~2 at.% Mn increases the lifetime of Cu interconnects four-fold [1].

Currently, the state-of-the-art method for depositing Cu-Mn alloys is sputter deposition with Mn content generally above a few atomic percent [2,3]. Compared to sputter deposition, electroless deposition has numerous advantages such as simplicity, low cost and faster deposition rate. Therefore, it is of great interest to develop an electroless process for depositing Cu-Mn alloy.

In this study, we report electroless deposition of Cu-Mn. The Mn incorporated was found to be ‘mobile’, a prerequisite for its application in interconnect metallization. It was also observed that Mn was incorporated during electroless Cu-Mn deposition at potentials that are much more anodic to its standard reduction potential (-1.18 V vs. SHE). To further our understanding of the electroless Cu-Mn deposition, a combination of voltammetry and quartz crystal microbalance were used to unravel the Mn deposition mechanism.

References

[1] J. P. Gambino, “Improved Reliability of Copper Interconnects Using Alloying”, Proc.17th IEEE IPFA, 1-7 (2010).

[2] J. Koike and M. Wada, Applied Physics Letters, 87, 041911 (2005).

[3] J. Koike, M. Haneda, J. Iijima, Y. Otsuka, H. Sako and K. Neishi, Journal of Applied Physics, 102, 043527 (2007).
New Temporary Bonding Solution Based on a Vacuum Wafer Carrier
Authors: Rogers Tony , Santilli Rob
Published: February 2020

There are many applications that require wafers to be thinned to high thickness uniformity. In addition there are requirements for the thinned wafer to go through high temperature and vacuum based process steps. The present solution to these requirements involves the temporary bonding of the device wafer to a carrier wafer. This temporary bonding solution has been very difficult to solve, and until now it has been down to the crude technique of gluing the wafers together using an adhesive. This technology process has many flaws: complex procedures, low yields, and very expensive equipment to name but three. These drawbacks have been the main reason for holding back the implementation of volume production in the important application area of 3D IC’s.

This paper presents a novel solution and uses the vacuum chuck concept, instead of adhesives, for holding the device wafer in place. This transportable vacuum chuck is known as a vacuum wafer carrier.

The vacuum wafer carrier is used in conjunction with a wafer bonding / debonding tool and the principle of operation is as follows:

a) Load device wafer and carrier into vacuum chamber of the bonding / debonding tool

b) Pump chamber to bonding pressure (typically 10-3 mBar)

c) Bring device wafer into contact with carrier (this traps the vacuum in the cavities of the carrier)

d) Vent the vacuum chamber

The device wafer can then be put through the various required process steps (eg grinding , DRIE PECVD, electroplating). This makes it compatible with all 3D IC processing variants (via first, via middle, and via last). Once these processes are completed, the carrier is replaced in the vacuum chamber for the debonding step.

The carrier design ensures that the wafers are in rigid contact with the surface of the carrier during the grinding step, and the dimensions of the cavities are designed to ensure the deflection of the device wafer during grinding is minimised to produce thickness tolerances of <1µm. In addition the recessed cavities of the carrier can be designed to accommodate any surface topography, such as solder balls, on the contact surface of the device wafer.

The vacuum seal between the carrier and the device wafer has been optimised to include sufficient stiction to ensure that the device wafer remains adhered to the carrier even when the carrier is being transported in a vacuum environment. The debonding step has been designed to overcome this stiction and release the wafer. During the release step a receiving platen is positioned just below (typically ~0.5mm) the device wafer in the vacuum chamber and the thinned wafer can then be picked up from this platen by the robotic handler.

This new temporary bonding solution will enable fab lines to substitute the current adhesives based solutions and gain from cost reductions, simplified procedures, fewer processing steps, increased yields and lower manufacturing cost.
Large Area Plan-View Transmission Electron Microscopy Sample Preparation for Direct-Bonded Interfaces
Authors: Beekley Brett , Roberts C.R. , Salazar M. S. , Goorsky M. S.
Published: February 2020

Metal-metal bonding, and in particular Au-Au bonding, is frequently used for both MEMs structures and for integration of combining different device structures, including III-V and silicon integration.1 High bond strength, accompanied with good electrical conductivity and hermeticity are often achieved when grain growth occurs across the metal-metal bond interface. Usually, this type of grain growth requires elevated temperatures and longer annealing times and has been studied for Cu-Cu bonding, but not for Au-Au bonding. However, the conditions which most effectively initiate the grain growth across either of this bonded interface have not been clearly elucidated.

We established that the preferential growth of a particular grain across Au-Au bond interfaces is enabled through an epitaxial transformation. Au (111) grains on one side of the interface grew into the other side – albeit with nanovoids remaining at the original interface. The microstructure of the transformed side consisted initially of nanotwinned, columnar Au while the grains that extended across the interface were initially randomly oriented under thermocompression bonding conditions. High resolution transmission electron microscopy measurements addressed the orientation dependence of the growing grains. This indicates that microstructure control in metal-metal bond pairs can impact the resultant grain structure and hence other properties.
Low Activation Temperature Au/Ti Getter Films for Wafer-Level Vacuum Packaging
Authors: Wu Ming , Moulin Johan , Agnus Guillaume , Bosseboeuf Alain
Published: February 2020

Vacuum packaging is required for mechanical microresonators and microbolometers to obtain a high quality factor and a low heat loss respectively. Because the internal volume of wafer-level packages is small, integration of getter films in the cavity is needed to maintain a low internal pressure (<10-2 mbar) for a long period of time (several years or more) even if a highly hermetic wafer bonding process is used [1,2]. Many Non-Evaporable Getter (NEG) films based on sputtered highly reactive transition metal have been investigated for this purpose. In this work we investigate thermal diffusion of titanium through an ultrathin capping Au layer as an alternative way to produce a getter film activated at low temperature. Both films were evaporated to avoid rare gas contamination found in sputtered films which can outgas afterwards. [3]
The films have been annealed in N2 and Ti out-diffusion from Au/Ti thin films was studied as a function of the annealing temperature using four probe resistivity measurements, spectroscopic ellipsometry, XPS analysis, residual stress variations, SEM cross section observations and Energy Dispersive X-Ray Spectrometry (EDX) measurements. These measurements were completed by AFM and SEM surface analyses. All results are consistent and support the occurrence of significant Ti out-diffusion followed by oxidation, even at low temperature (<300°C). The electrical resistivity already increases by 10% after 1 hour annealing at 200°C. XPS measurements confirm the presence of a TiOx layer after annealing which contribution increases with the temperature and with a composition close to x » 1.8. SEM and AFM images of the as-deposited films surface show a smooth surface of gold, with RMS roughness below 1.5 nm. After annealing at 300°C, the titanium oxide is visible at the surface, in a shape of flakes and after annealing at 350°C, this layer covers completely the gold. Analysis of the sample cross-section shows that after annealing the gold layer is buried under the TiOx layer, that this layer is continuous and that its depth, corresponding to the TiOx thickness, increases with the annealing temperature (see fig., left-SE and right-BSE). Finally, TiOx films of several nm can be obtained by diffusion of the Ti through the Au at low temperature, showing that Au/Ti film can be used as a low temperature getter film for wafer-level vacuum packaging.
[1]. M. Deniel, A. Naumann, D. Sorger, S. Tenholte, J. Voigt, O. Mehner, The influence of vacuum on the design and characterization of MEMS, Vacuum, 2012, 86 pp. 536-546.
[2]. S. García-Blanco, P. Topart, Y. Desroches, J. Caron, F. Williamson, C. Alain and H. Jerominek, Low temperature hermetic wafer-level package for uncooled microbolometer FPAs, Proceedings of SPIE, 2008, 68840P-1.
[3]. L. Tenchine, X. Baillin, C. Faure, P. Nicolas, E. Martinez, NEG thin films for under controlled atmosphere MEMS packaging, Sensors and Actuators A, 2011, 172 pp. 233-239.
Monolithic Thin Wafer Stacking Using Low Temperture Direct Bonding
Authors: Burggraf Jürgen , Bravin Julian , Wiesbauer Harald , Dragoi Viorel
Published: February 2020

Due to the high process temperature required for fusion bonding (e.g. ~1000°C) this process was not attractive for 3D applications. In the recent years low temperature fusion bonding processes were developed for addressing such applications: in such process the maximum temperature ranges typically between 200°C – 400°C.

A low temperature thin wafer stacking process was developed. The low temperature fusion bonding process was used in combination with standard thin wafer manufacturing processes based on temporary bonding/debonding technology in order to demonstrate thin layer direct bonding with subsequent multi-layer stacking capability.

Temporary bonding is an enabling technology to manufacture and securely handle wafers with a thickness of < 20 µm. Thin wafer processing is enabled by temporary bonding the device wafer to a rigid carrier wafer using temporary bonding adhesives which allow subsequent thinning and backside processing of the device wafer. Two different processes for the thin wafer manufacturing and thin wafer stacking capability were evaluated. The process flow for thin wafer stacking is shown in Figure 1 and can be divided into four major tasks: thin wafer manufacturing, surface preparation, wafer bonding and carrier removal.

Experimental data of temporary bonded wafers with a wafer thickness of < 10 µm and a TTV ≤2 µm for 300 mm silicon wafers will be presented.

Low temperature oxide deposition followed by a Chemical Mechanical Polishing (CMP) process was evaluated on the thinned wafers to enable a direct bonding process and to first layer an extensive layer preparation process was performed to enable the stacking of the second layer [2].

The process is compatible with the high cleanliness levels required by CMOS technology and can be used for various application scenarios involving Through-Silicon Vias (TSV) technology.
Optimization of Low Temperature Cu-Cu Wafer Bonding Using Advanced Analytical Methods
Authors: Rebhan Bernhard , Wimplinger Markus , Hingerl Kurt
Published: February 2020

Metal thermo-compression wafer bonding is a promising candidate for three-dimensional integration of Integrated Circuits (3D ICs). 3D ICs are very interesting as they allow for higher performance due to shorter interconnect paths fabricated in a wafer-level integration approach, even for wafers processed in different technologies. For example, Complementary Metal Oxide Semiconductors (CMOS) and Micro- Electro- Mechanical Systems (MEMS) may be integrated this way. Due to its high electrical and thermal conductivity, low cost, and current availability in numerous IC fabrication facilities Cu is a very attractive bonding material for 3D integration. During the past decade processes were developed for Cu-Cu thermo-compression bonding using about 1 h at 400°C under high contact pressure. A substantial bonding temperature reduction is required in order to optimize post-bond wafer-to-wafer alignment accuracy, to minimize thermo-mechanical stresses, to prevent device degradation (as it is the case for Dynamic Random Access Memories - DRAMs), and to increase the throughput of the bonding process.

The aim of this work was to study the physical mechanisms of Cu-Cu bonding, develop a deep knowledge of the effects of these mechanisms, and then apply this knowledge to optimize the bonding process for low temperatures. This was achieved by preparing 150 mm silicon sample wafers by two alternative methods (Cu sputtering and electroplating) either with or without Chemical Mechanical Polishing (CMP), running a set of experiments covering combinations of wet chemical ex-situ and dry in-situ oxide reducing pre-treatments and then evaluating the results using analytical techniques, such as Atomic Force Microscopy (AFM), Electron Back- Scatter Diffraction (EBSD), Transmission Electron Microscopy (TEM), C-mode Scanning Acoustic Microscopy (C-SAM), several elemental analysis techniques and a qualitative version of the Maszara crack test. Here the used wet chemistry was diluted citric acid (1wt%) and the reducing gas was forming gas (96% Ar + 4% H2). Subsequent to the wafer bonding process, the post-bond annealing was performed in order to increase the bond strength while keeping the retention time in the wafer bonding system as short as possible.

It was determined that for successful low temperature Cu-Cu thermo-compression wafer bonding the following classes of variables have to be considered (i) the contact of the two Cu surfaces, even at atomic scale, (ii) the cleanliness of the Cu surfaces, (iii) the diffusion properties of the two Cu layers and (iv) process conditions. In this paper the measured experimental results are compared with current knowledge and theory. In addition, key variables for establishing a successful bonding process were discussed. Using the fundamental information learned in these experiments it was possible to perform Cu-Cu thermo-compression wafer bonding at and below 200°C (see Figure 1); even room temperature direct bonding is achievable.
A Novel Approach to Isolating the Edge of the Shallow Trench Isolation in SiGe HBTs for Improved Device Performance
Authors: Camillo-Castillo Renata A. , Liu Qizhi Z. , Jain Vibhor , Adkisson James W. , Khater Marwan H. , Gray Peter , Pekarik John Jack , Malladi R , Harame D. L.
Published: February 2020

Scaling silicon germanium heterojunction bipolar transistors (SiGe HBTs) to attain simultaneous increases in the figures of merit, fT
and fMAX
has necessitated a deep understanding of the inherent features of the process as it relates to the final device performance. The faceted nature of the base epitaxial growth on the periphery of the shallow trench isolation has been the focus of several investigations which have demonstrated the role it plays in the extrinsic collector-base capacitance. In this work, a novel approach to isolating the device periphery is presented in which a field polysilicon protect layer is used to isolate the edge of the active silicon region in the vicinity where the faceted growth typically occurs, for a 300/350 fT/fMAX
SiGe HBT NPN. Layout variations in the location of the field polysilicon layer relative to the edge of the active silicon region, results in marked changes in the intrinsic device, with increases in fT/fMAX
of 15/20GHz respectively. Technology computer-aided device techniques are utilized to understand the process and device changes driving the improvements in device performance observed and will be discussed.
SiGe HBTs in 90nm BiCMOS Technology Demonstrating fT/fMAX 285GHz/475GHz through Simultaneous Reduction of Base Resistance and Extrinsic Collector Capacitance
Authors: Liu Qizhi Z. , Adkisson James W. , Jain Vibhor , Camillo-Castillo Renata A. , Khater Marwan H. , Gray Peter B. , Pekarik John Jack , Zetterlund Bjorn , Divergilio Adam W. , Kerbaugh Michael L. , Harame D. L.
Published: February 2020

Development of SiGe HBTs in BiCMOS technology with both high fT and fMAX faces significant challenges. To increase fT, thinning the base and collector thickness is generally the first step to reduce the carrier transit times, but increases the base resistance and the collector-base capacitance, which impacts fMAX negatively. Increasing collector doping is also often employed to increase fT, but again increases collector-base capacitance, which drives fMAX down. To overcome these limits, a series of process and device structure innovations have been made in recent years. Millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. A novel approach to reduce the extrinsic collector-base capacitance is developed, concurrent to the reduction of base resistance, without affecting the manufacturability and integration with CMOS. The simultaneous reduction of both base resistance and collector capacitance enables high performance SiGe HBT devices in 90nm BiCMOS Technology with operating frequencies of 285/475GHz fT/fMAX.
Second Order Intermodulation Linearity of a 200 GHz SiGe HBT Technology
Authors: Li Zhen , Niu G. , Wei Xiaoyun
Published: February 2020

Intermodulation linearity is an important consideration for RF technologies. Third order intermodulation linearity is typically considered, as third order output is close to the fundamentals. Second order intermodulation outputs are far away from the fundamentals, and thus can be filtered [1]. However, the same second order nonlinearity also produces dc offset, which presents a significant problem for direct-conversion receivers [2]. While differential circuits can decrease second order nonlinearity, cancellation is not complete, and is worsened by transistor mismatch.

We present here characterization of the second order intermodulation linearity on 200 GHz peak fT SiGe HBTs. The second order input intercept point, IIP2, is characterized on IC-VCE plane for different breakdown voltages. The measurement system is set up and calibrated according to [3].

Fig. 1 (a) and (b) show the measured IIP2 and fT versus IC for VCE = 1.0, 1.3, 1.6, and 1.9 V on a standard breakdown voltage (SBV) HBT. For comparison, the third order input intercept point (IIP3) is shown in Fig. 1 (c). IIP2 increases with IC before fT roll-off, and then decreases. A higher VCE effectively delays IIP2, fT and IIP3 roll-off overall. The impact is more obvious for IIP2 and IIP3 than for fT. Observe that the IIP3 peak is reached at a much smaller IC, well before peak fT is reached. IIP2 peaks either reside inside the flat fT region or closely lag behind fT roll-off. At high IC, higher VCE shifts IIP2 to higher level, implying that a higher VCE can be used to effectively improve IIP2 at higher currents.

In Fig. 2 (a) and (b) , the current dependence of IIP2 and fT are compared for three HBTs of different breakdown voltage. IIP2 first increases with IC, peaks, and then decreases sharply before rising again. The IIP2 peak occurs approximately at the same current as the fT peak for all breakdown voltages. Before 1 mA, IIP2 is the same for all, indicating that the collector-base junction difference does not affect IIP2 so long as high injection does not occur. A higher VCE could be used with higher breakdown devices to extend the current range of high fT and IIP2, which is also confirmed by measurement.

References

[1] P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits, Kluwer, 1998

[2] B. Razavi, RF Microelectronics, Prentice-Hall, 2012

[3] G. Niu, et al., BCTM, pp. 1-4, 2006.
(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
Authors: Lu Darsen , Morin Pierre , Sahu Bhagawan , Hook Terence B , Hashemi Pouya , Scholze Andreas , Kim Bomsoo , Kerber Pranita , Khakifirooz Ali , Oldiges Philip , Rim Ken , Doris Bruce
Published: February 2020

We introduce SiGe MOSFET process integration and device impact from a simulation perspective. Germanium is know to have a higher channel hole mobility. Enhancement of hole velocity due to lattice mismatch strain in shilicon germanium epitaxial layers is significant. Processing challenges include the elimination of interface trap states at the dielectric interface, fast diffusion of n-type dopants, defects in stress relaxed buffer and critical thickness limitations. Uniaxial stress is beneficial for device performance. Transformation of biaxial stress to uniaxial is natural when etching silicon germanium into stripes. From a device perspective, silicon germanium is useful for shifting MOSFET device Vth.
Structural and Optical Properties of Ge1-XSnx Alloys Grown on GaAs (001) by R. F. Magnetron Sputtering
Authors: Pérez Ladrón de Guevara Héctor , Rodríguez A. G. , Navarro-Contreras H. , Vidal M. a.
Published: February 2020

Ge1-xSnx alloys were grown on GaAs (001) substrates in a conventional R. F. magnetron sputtering system with two independent plasmas not simultaneous focus to substrate. We determined the in-plane and in-growth lattice parameters for different Sn concentrations by high resolution X-ray diffraction (HRXRD). We observed that Ge1-xSnxlayers with low Sn concentrations have pseudomorphic characteristics. But this layers relax at Sn concentrations higher than the ones growth on Ge (001) substrates.

We also determined the band gap transitions and we found that the indirect-direct band gap crossover occurs as is predicted in Ge1-xSnx alloys growth on Ge (001). Raman spectroscopy confirms the presence and Sn concentrations of the Ge1-xSnx layers.
(Invited) Wrinkling Graphene with Bacteria and Functionalization of MoS2 for Electronic Applications
Authors: Briggs Donovan , Deng Shikai , Berry Vikas
Published: February 2020

The presentation with have two parts: (a) Wrinkle formation of 2D nanomaterials via bacteria and (b) MoS2 functionalization for electronic applications. (A) Wrinkle-formation via thin-sheet compression is a phenomenon readily exhibited by two-dimensional (2D) nanomaterials (like graphene). In graphene, these wrinkles can modify the band structure and local electronic states. Here, we show that bacterial cells can be employed as sacrificial scaffolds to induced controlled wrinkles on attached graphene. The wrinkles orient longitudinally on cylindrical bacterial cells and their attributes (wavelength and amplitude) can be controlled with high precision (in nanometer scale) and obey the modified Herringbone model. A circumferential Young’s modulus of 39 MPa suggests a wrinkle-wavelength of 27.3 nm, consistent with our measurements (33 nm in FESEM and 36.7 nm in AFM images). (B) Ultrathin two dimensional metal dichalogenides (MoS2, WS2, so forth) exhibit confinement of carriers, evolution of band structure, high on/off rectification, and high thermal absorption. However their incorporation into other systems requires controlled functionalization and/or interaction with other nanoscale entities. Here we enhance the stable sulfur/nobel metal functionalization via both diffusion limited aggregation and instantaneous reaction arresting (using microwaves). These gold nanoparticles are incorporated selectively on MoS2 crystallographic edges (with 60o displacement). The Raman, electrical and thermal studies indicate a remarkably capacitive interaction between gold and thin MoS2 sheet (CAu-MoS2 = 2.17 mF/cm2), a low Schottky barrier (14.52 meV), a vastly reduced carrier-transport thermal-barrier (253 to 44.18 meV after gold functionalization), and increased thermal conductivity (from 15 W/mK to 23 W/mK post gold deposition). This process provides a route to affiliate MoS2 with potential electronic application, such as electrodes attachment to hetero-structures of graphene and MoS2, where a gold film could be grown to act as an electron-tunneling gate-electrode connected to MoS2.
(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of III-V on Si: What About Defect Density?
Authors: Merckling Clement , Waldron Niamh , Jiang Sijia , Guo Weiming , Barla Kathy , Heyns Marc , Collaert Nadine , Thean Aaron , Vandervorst Wilfried
Published: February 2020

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor is a winning combination to further boost the performance of future CMOS devices.

Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy.

We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.

As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach on a common Si platform.