bluuebunny/crossref_metadata_2025 huggingface dataset:
Aura dalam Reproduksi Digital: Membaca Ulang Walter Benjamin
Authors: Hardiman Fransisco Budi
Published: December 2020

Walter Benjamin’s essay, The Work of Art in the Age of Mechanical Reproduction (1939), has revealed the fundamental changes of modern work of art affected by its mechanical reproduction. Camera, tape recorder, print machine have turned the work of art to be mass consumption, autonomous from tradition and ritual, and it has now a political function. According to Benjamin all of those new technologies have faded up the aura since the work of art lost its authenticity and its uniqueness. We are in the different era than Benjamin’s because nowadays digital reproduction by means of the internet ends the need of medium for the work of art, multiply and spread it very rapidly. The author comments on Benjamin’s analysis and applies it to discuss the ontological, epistemological, and axiological issues of the work of art in the age of digital reproduction. He argues that in the digital age the work of art will be still auratic if it reveals ‘the extraordinary’ in the experience of our humanity.

 

Key words: aura, hyperpolitization, work of art, medium, attention, digital reproduction
Testing-Based Failure Analysis: A Critical Component of the SIA Roadmap Vision
Authors: Maly W.
Published: December 2020

The feasibility of the vision of the Semiconductor Industry Association (SIA) Road Maps is rooted in a number of important assumptions. One of them is a requirement of up to 90% yields, which must be achieved for each of the subsequent SIA Road Map milestones. This article argues that such high yields cannot be achieved without a substantial increase in the efficiency of failure analysis. Consequently, it is indicated that testing-based failure analysis is the only alternative which must eventually take over the major responsibility for yield ramping. Finally, it is demonstrated that the increase in the cost of manufacturing due to the increase in failure analysis cost can be justified by extra revenue obtained via faster yield ramping. The article suggests that the testing and IC Design for Diagnosability-based rapid failure analysis are key elements for successful realization of the SIA Road Map objectives.
An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices
Authors: Yeoh E. H. , Mak W. M. , Lock H. C. , Sim S. K. , Ooi C. C. , Baker B. , Core D. , Maxwell K.
Published: December 2020

As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.
Application of Laser Scanning Microscope to Analyze Forward Voltage Snapback of Compound Semiconductors
Authors: Morris M. L. , Cook B. , DiSilvestro J.
Published: December 2020

A forward voltage (Vf) snapback phenomenon was observed during the analysis of silicon doped gallium-arsenide (GaAs) light emitting diodes (LEOs). In this paper emphasis is placed on both the techniques used during the analysis and the information obtained. Apart from the standard curve tracer characterizations, and utilization of two microsection techniques, significance is placed on the use of a laser scanning microscope (LSM). The LSM has four main analys is features: photoemission (FE) microscopy, optical beam induced current (OBIC), confocal microscopy and infrared laser scanning microscopy [1]. The analysis of the LEOs utilizes two of these features, PE microscopy and OBlC analysis. These techniques are used in a complementary fashion to analyze the forward voltage snapback. The analysis reveals two independent wafer processing related issues, a junction anomaly and an unintentional phantom junction at the substrate to epi interface. Both phenomena can result in the LED Vf snapback.
Moisture Detection Method in Ceramic Package by Slight Current Measurement
Authors: Hirai A. , Kikuchi T. , Namba H. , Sato J.
Published: December 2020

A method of measuring moisture in the ceramic Package (pKG) without the destruction of the samples was developed (We define KNH method: kinahi method). The moisture oondition in the cavity can be oonfirmed by the temperature dependence of the leakage current between adjaoont terminals (At least one of measured terminals is non-oonnect). This method is performed by measuring the leakage current between non-oonnect terminals at various temperatures. The temperature is raised from room temperature. In the caseof the standard sample which has no moisture in the cavity, the leakage current increases as the temperature is raised. However, a sample which has a large amount of moisture in the cavity has a leakage current that decreases with increasing temperature and increases after this cycle. When the temperature is raised, the leakage current decreases because of a decrease in oondensed moisture. After the temperature without oondensing, the leakage current increases as same as standard sample. When this KNH method is used for the product which has no non-oonnect terminals, the leakage current can be measured by using the signal terminals at 0.2V which is the voltage under Vt of protection diode. This KNH method is very useful for oonfirmation of the slight leakage current of fine ceramic PKG and for the amount of moisture in the cavity
Single Contact Electron Beam Induced Current Microscopy for Failure Analysis of Integrated Circuits
Authors: Phang J. C. H. , Kolachina S. , Chan D. S. H.
Published: December 2020

Single Contact Electron Beam Induced Current (SCEBIC) microscopy, a new junction imaging technique suitable for visualization of unconnected pn junctions in integrated circuits is presented. By using the substrate contact alone of a die, the SCEBIC approach eliminates the need to connect a junction to the imaging electronics as is done in the conventional Electron Beam Induced Current (EBIC) technique. The principles of SCEBIC are discussed and experimental data which validate the SCEBIC approach for imaging of pn junctions is presented. Examples of SCEBIC images are presented and applications of SCEBIC microscopy in IC failure analysis are discussed.
Electrical and Chemical Characterization of FIB-Deposited Insulators
Authors: Campbell A. N. , Tanner D. M. , Soden J. M. , Stewart D. K. , Doyle A. , Adams E. , Gibson M. , Abramo M.
Published: December 2020

The electrical and chemical properties of insulators produced by codeposition of siloxane compounds or TEOS with oxygen in a focused ion beam (FIB) system were investigated. Metal-insulator-metal capacitor structures were fabricated and tested. Specifically, leakage current and breakdown voltage were measured and used to calculate the effective resistance and breakdown field. Capacitance measurements were performed on a subset of the structures. It was found that the siloxanebased FIB-insulators had superior electrical properties to those based on TEOS. Microbeam Rutherford backscattering spectrometry analysis and Fourier transform infrared spectroscopy were used to characterize the films and to help understand the differences in electrical behavior as a function of gas chemistry and deposition conditions. Finally, a comparison is made between the results presented here, previous results for FIB-deposited insulators, and typical thermally-grown gate oxides and interlevel dielectric Si02 insulators.
IC Design Modification Using Laser Assisted Organometal Deposition
Authors: Bethke D.
Published: December 2020

This paper explains how laser assisted deposition used in combination with focused ion beam (FIB) milling reduces turnaround time for complex circuit modifications. It presents the results of three case studies, characterizing the process and the effect of various processing parameters. The first case involves the creation of a low resistance path between internal signal lines using only laser techniques; the second case demonstrates the use of laser deposition to route interconnects, millimeters in length, between two complex FIB modifications; and the third case is designed to reproduce a charge build-up problem. The paper also discusses the use of gold as a deposition material.
A Process Induced Failure Mechanism in the EEPROM Cell - Its Identification and Solution
Authors: Tsang Y. L. , Cavins C.
Published: December 2020

A 0.8 μm technology based Electrical Erasable, Programmable Read-Only Memory (EEPROM) cell having a high voltage select transistor and a floating gate transistor with a control gate on top as used in the Motorola Neuron product chip set was analyzed for program and erase failure. Silicon pitting in the select transistor channel was identified to be the failure mechanism. The silicon pitting was experimentally confirmed to be attributed to the penetration of the bottom oxide in the oxide-nitride-oxide (ONO) structure due to the nitride removal using reactive ion etching (RIE). A modified process flow with a thicker sacrificial oxide under the nitride eliminated the pitting failure mechanism and enhanced yield and reliability.
Detection of Gate Oxide Defects Using Electrochemical Wet Etching in KOH:H2O Solution
Authors: Ohtani N. , Katayama T. , Yamamoto H. , Koyama H.
Published: December 2020

A new technique to detect gate oxide defects has been developed. This method is based on electrochemical wet (ECW) etching of Si in KOH:H 20 electrolyte. Using this method, only leaky poly-Si gates caused by gate oxide defects can be clearly observed. When applying a certain voltage to a Si substrate in KOH:H20 after exposing the polySi gates, normal poly-Si gates can be etched, but poly-Si gates shorted to the Si substrate through gate oxide defects remain unetched because of the anodic oxide which covers the leaky gate. This method has proved to be very effective in obtaining information concerning gate oxide integrity without direct observation of gate oxides, which requires complicated deprocessing and a lot of time. This technique also reveals electrical characteristics of gate oxides which may be difficult to identify by conventional physical analysis.
Effectiveness of Emission Microscopy in the Failure Analysis of CMOS ASIC Devices
Authors: Parekh K. H. , Milburn R.
Published: December 2020

In the last several years emission microscopy has become an essential tool for failure analysis, specifically for VLSI devices. This paper describes various die related failure mechanisms in CMOS ASIC devices which were detected by emission microscopy. The failure analysis results discussed in this paper are primarily of the devices which were analyzed over the period of the last three years, 1994 - 1996. These devices were from a broad spectrum of final test failures, qualification and reliability test failures, special evaluation failures, testing and assembly failures at customer sites, and end user field failures. In addition to the failure mechanism statistic scanning electron micrographic illustrations of some of the failure mechanisms and associated damage are presented in this paper. The data presented in this paper clearly show the effectiveness of photon emission microscopy. The value of emission microscopy really lies in quick detection of failure locations on the die which failed functionally or due to excessive static IOD, functional IOD, or input/output leakage currents. It has certainly impacted tum around time of the analysis as significant reduction in analysis time has been achieved. In some cases same day turn around was possible.
BiCMOS Die Sort Yield Improvement from Isolation of a Localized Defect Mechanism and Precision TEM Cross Section
Authors: Douglass J. , Myers T. D. , Tsai F. , Ketcheson R. , Errett J.
Published: December 2020

This paper describes how the authors used a combination of focused ion beam (FIB) microprobing, transmission electron microscopy (TEM), and data and process analysis to determine that localized water residue was causing a 6% yield loss at die sort.
Failure Analysis of a Qualification Unit Injector for a Satellite Thruster
Authors: Lipschutz M. , Brannam R. , Nguyentat T.
Published: December 2020

This article details the results of a failure analysis performed on a Qualification Unit injector for a military satellite thrusters and explains that the failure was initially detected due to a shift in performance during qualification testing. Failure analysis involved non-destructive evaluation on the injector using micro-focus X-ray and scanning electron microscopy. Serial cross-sectional metallography was then performed, with each cross-section documented by optical microscopy and SEM. The failure analysis resulted in three main conclusions: (1) the root cause of the failure was attributed to multiple detonations in or around the damaged orifice; these detonations were likely caused by fuel and/or combustion products condensing in the orifice between pulses and then igniting during a subsequent pulse; (2) multiple damage mechanisms were identified in addition to the ZOT detonations; and (3) the material and platelet manufacturing process met all design parameters.
The Challenges of FIB Chip Repair and Debug Assistance in the 0.25μm Copper Interconnect Millennium
Authors: Herschbein S.B. , Fischer L.S. , Kane T.L. , Tenney M.P. , Shore A.D.
Published: December 2020

Copper will probably replace aluminum alloys as the interconnect metallurgy of choice for high performance semiconductor devices. This transition will challenge the suitability of established practices in focused ion beam (FIB) chip repair. A fundamental rethink in methodology, techniques, and process gases will be required to deal with the new metal films. This paper discusses the results of recent experiments in the areas of FIB exposure, cuts and connections to buried copper lines. While copper tends to mill faster than aluminum, etch rate variations due to grain structure tend to make reliable isolation cuts more difficult. The films also have been shown to suffer regrowth and surface reactions during long term storage following FIB exposure. Attempts at halogen gas assisted etch (GAE) mills result in undesirable removal characteristics, and in the case of bromine, the spontaneous destruction of all exposed copper in the immediate area. Resistance measurements and reliability of deposited tungsten connections to copper lines are also presented. In addition, the latest techniques developed for aluminum wiring isolation and device characterization are shown. These include 'cleanup' methods for achieving good circuit isolation without the extensive use of local oxide deposition, and the latest multilevel version of the FIB ‘wagon wheel’ for SRAM cell characterization. Also included is preliminary data from a custom built FIB chamber four manipulator prober module.
Non-Contact Probing of Integrated Circuits Using Electrostatic Force Sampling
Authors: Bridges G.E. , Thomson D.J. , Qi R.
Published: December 2020

We present a non-contact probing technique for measuring highfrequency voltage waveforms at the internal points of an operating integrated circuit. Internal circuit voltages are measured by sensing the local electrostatic force on a small micromachined probe that is held in close proximity to the circuit measurement point. The instrument currently has a 3GHz bandwidth and a capacitive loading on the test point of less than 1fF. The non-contact technique is capable of measuring signals on passivated interconnects
Mechanical/Plasma Decapsulation Method and Thermal Finite-Element Analysis Provide Explanation for SMB Zener Failures
Authors: Kime Kent , Reed Chuck , Di Silvestro Joe , Ruiz Ruth , Keeton Simon , Thome Gene P.
Published: December 2020

Failure analysis and finite-element analysis were used in conjunction to determine the cause of zener diode failures. A mechanical/plasma depot method was developed for the plastic-encapsulated SMB package and used to observe the presence of remelted extruded solder material on the die surface. That material provided a conductive path which manifested electrically as premature breakdown. Transient-thermal finite-element analysis was then used to show that a recent change of in-house surge test parameters could result in part temperatures during surge testing in excess of the solder melting temperature. These efforts lead to a respecification of the in-house surge test duration which resolved the problem.
Layout Overlay Techniques to Improve Failure Analysis
Authors: Burmer Christian , Görlich Siegfried , Pauthner Siegfried
Published: December 2020

New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.
A Method for Cross Sectioning Polyimide Passivated Semiconductors
Authors: Gatto Richard N.
Published: December 2020

This paper will present a practical and refreshingly simple polyimide cross sectioning alternative, along with some delineation recipes.
Waveform Acquisition from the Backside of Silicon Using Electro-Optic Probing
Authors: Bruce Mike , Dabney Greg , McBride Shawn , Mulig Jason , Bruce Victoria , Bachand Charles , Kasapi Steven , Block Jeffrey A.
Published: December 2020

A new tool (Schlumberger IDS 2000) has become available for acquiring waveforms from C4 (also known as flip chip) packaged IC’s. The waveform acquisition technique is based on electro-optic sampling through the backside of silicon. After explaining the physics of electro-optic sampling, the technique is demonstrated through the backside of Si on a simple diode test structure and a flip chip microprocessor. Also, many of the issues and challenges with this tool are discussed.
Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy
Authors: Lim Soon , Bi Jian Hua , Goh Lian Choo , Neo Soh Ping , Tatti Sudhindra
Published: December 2020

The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.
In-Situ Use of an Optical Microscope for FIB Microsurgery of Planarized Devices
Authors: Wolpert Patrick J. , Lee Raymond A.
Published: December 2020

The extensive use of planarization in many of today's leading process technologies significantly reduces the effectiveness of FIB circuit modification and debugging. Planarization has played a significant role in the development of denser chips with increasingly smaller geometries. Fully planarized devices offer little or no surface features on which the FIB operator relies for orientation and alignment. These conditions lead to increased debug cycle times and decreased success rates using the FIB. Recent FIB tool advancements in the field of C4 (controlled-collapse chip connection) flip-chip packaged device modification and debug have also made it easier to work on highly planarized conventional wire-bond technology. The integration of an optical microscope with an infrared camera into the work chamber allows the operator to view the circuitry under the surface layer. This paper will offer several techniques for overcoming the challenges that planarized devices present by using this in-situ optical microscope. When properly implemented, these techniques can significantly improve the success rate and throughput time of device modification on highly planarized parts.
Optimizing Contact Resistance at a Resistor/Conductor Interface via Thin Film Microanalysis and Process Design of Experiments
Authors: Linn J.H. , Thompson T.K. , Shlepr M.G.
Published: December 2020

Electrical data from chromium-silicon-carbon (CrSiC) thin film resistors (tfr) consistently showed highly variable contact resistance (Rc) to the aluminum (Al) interconnect. Transmission electron microscopy data from CrSiC/Al interfaces exhibiting high Rc showed a conformal, amorphous layer sandwiched between the tfr and Al. Auger data from the tfr/Al interface showed this ‘crud’ layer to contain increased C, S, and SiOx. Auger data from CrSiC films on test wafers exposed to the process steps before Al deposition showed additional growth of the ‘crud’ layer after each photoresist (PR) operation. In addition, Rc variability was reduced on product wafers from split lots when 2x the normal PR strip time was used compared to the normal strip time. A Designed Experiment (DOE) to examine improving the removal of this ‘crud’ layer was run on product lots utilizing two factors: the standard strip and a two-step strip. Electrical results for both Rc and die yield were significantly improved using the two-step process. The variability of the Rc was also reduced.
Failure Analysis of Plastic Packaged GaAs and AlGaAs/GaAs LEDs
Authors: Mead Patricia F. , Burch Melody , McCluskey Patrick , Johnson F. G.
Published: December 2020

Failure and degradation mechanisms of plastic packaged LEDs that have been subjected to high levels of moisture, current bias, and elevated temperature conditions have been investigated and analyzed. The investigation included electrical characterization and a variety of failure analysis techniques including photoluminescence (PL), electroluminescence (EL), cathodoluminescence (CL), and environmental scanning electron microscopy (ESEM). Our results highlight the usefulness of simple screening techniques to monitor the quality of newly manufactured LED packages. Our results also indicate that for AlGaAs structures, degradation of the light output and electrical performance involves a complex interaction between temperature, relative humidity at the LED surface and voltage bias.
Integrated Circuit Device Repair Using FIB System: Tips, Tricks, and Strategies
Authors: Hooghan K. N. , Wills K. S. , Rodriguez P.A. , O’Connell S.J.
Published: December 2020

Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.
Current-Signature-Based Analysis of Complex Test Fails
Authors: Gattiker Anne E. , Nigh Phil , Maly Wojciech
Published: December 2020

This article provides an analysis of a class of failures observed during the SEMATECH-sponsored Test Methods Experiment. The analysis focuses on use of test-based failure analysis and IDDQ signature analysis to gain insight into the physical mechanisms underlying such subtle failures. In doing so, the analysis highlights techniques for understanding failure mechanisms using only tester data. In the experiment, multiple test methods were applied to a 0.45 micrometer effective channel length ASIC. Specifically, ICs that change test behavior from before to after burn-in are studied to understand the physical nature of the mechanism underlying their failure. Examples of the insights provided by the test-based analysis include identifying cases where there are multiple or complex defects and distinguishing cases where the defect type is likely to be a short versus an open and determining if the defect is marginal. These insights can be helpful for successful failure analysis.
Residual Photoresist Identified as Cause for Frequency-Dependent Signal-to-Noise Failure After Autoclave Stress Testing
Authors: McVeigh Martin J.
Published: December 2020

A case history is presented for the failure analysis of a 0.5u CMOS A/D converter in which high fallout occurred after autoclave stressing. The observed failure mode of degraded signal-to-noise distortion (SINAD) ratio (measured in dB) was found to affect devices within a specific bandwidth centered around 5MHz. From a circuit designer’s viewpoint, an explanation for this unique failure mode did not readily present itself. Yet, using straightforward failure analysis techniques, involving laser ablation of photoresist and selective etching of passivation, the specific failing circuit block was isolated. Crosssectional analysis, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) found evidence of residual photoresist at topography related voids in the nitride passivation layer. The photoresist reacts with moisture in the autoclave, resulting in increased capacitance at minimum-spaced top layer metal lines. This failure mechanism correlates with the observed maximum SINAD degradation around 5MHz: at this frequency the signals along the affected metal lines are at their maximum voltage swing. This failure mechanism is potentially an issue for any similar high-speed, high-resolution designs.
Application of the Infrared Microscope (IREM1) for Flip-Chip (C4) Failure Analysis
Authors: Zaplatin A. N. , Low F. J. , Seidel Steve , Rao Valluri R. , Loh T. H.
Published: December 2020

Today’s process technology requires ever-increasing number of metal layers to meet the power and layout needs of modern products. These advances have rendered many of the conventional fault isolation (FI) methods from the front side of the die obsolete. The flip-chip package not only brings about the need to localize defects at die level through the Si substrate, but also introduces the need to isolate new defects at the package level. Recently, an infrared (IR) emission microscope which utilizes the cryogenically cooled HgCdTe (MCT) imaging array having spectral response of 0.8μm- 2.5μm, for near IR emission detection was developed. This system supersedes the conventional CCD based emission microscope with a spectral response of 0.4 μm-1.1μm. Since spectral detection extends into the thermal spectral region, it also offers an added advantage of detecting thermal spots on the die and flip-chip package where liquid crystal hot spot detection method is not possible. This article is an account of the use of the Mercury-Cadmium- Telluride based IR detector for “real life” failures. The article will demonstrate key features of the system as well as several FI examples. Both emission and thermal detection modes will be discussed. The authors will present several problems, including melted die bumps and package copper trace shorts, that could not be detected through conventional failure analysis (FA) methods, such as liquid crystal or front side emission microscopy. The MCT detectors increased sensitivity and backside navigation capabilities coupled with backside die preparation has proven itself an indispensable FA tool in the high volume manufacturing environment.
Failure Analysis of CDM-ESD Damage in a GaAs RFIC
Authors: Poe Amy , Brockett Steve , Rubalcava Tony
Published: December 2020

The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.
The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures
Authors: Morris Mark , Mohr James , Ortiz Esteban , Englebretson Steven
Published: December 2020

Determination of metal bridging failures on plastic encapsulated devices is difficult due to the metal etching effects that occur while removing many of the plastic mold compounds. Typically, the acids used to remove the encapsulation are corrosive to the metals that are found within the device. Thus, decapsulation can result in removal of the failure mechanism. Mechanical techniques are often not successful due to damage that results in destruction of the die and failure mechanism. This paper discusses a novel approach to these types of failures using a silicon etch and a backside evaluation. The desirable characteristics of the technique would be to remove the silicon and leave typical device metals unaffected. It would also be preferable that the device passivation and oxides not be etched so that the failure location is not disturbed. The use of Tetramethylammonium Hydroxide (TMAH), was found to fit these prerequisites. The technique was tested on clip attached Schottky diodes that exhibited resistive shorting. The use of the TMAH technique was successful at exposing thin solder bridges that extruded over the edge of the die resulting in failure.
Selective Au Etching in Au/Al Bonds in Current IC Technology
Authors: Vanzi M. , Serpe A. , Trogu E.F. , Deplano P. , Hartfield C. , Subido W.
Published: December 2020

A new Au etch, recently developed for selective Au etching on Ti/Pt/Au metallization of optoelectronic devices, has been tested on Au wires bonded on Al films. Contrary to theoretical expectations, Au wires are removed without Al damage, except for a very localized area around the bond interface. The role of the native Al oxide is discussed in preserving Al and allowing Au lift off.
Application of Scanning Acoustic Microscopy to Electric and Electronic Parts
Authors: Miyasaka C. , Tittmann B. R.
Published: December 2020

Ever since the invention of the scanning acoustic microscope (SAM), a key objective has been the enhancement of the resolution in an interior image. Thus, an acoustic lens that can form an interior image with a shear wave has been designed. The use of this lens gives benefits such as an increase of lateral resolution in the interior image, a reduction in background noise caused by surface roughness, and a reduction of spherical aberration. Significantly, with the current trend towards microminiaturization of microelectronic packages, acoustic microscopy with higher resolution and removal of surface roughness can play an important role in diagnostic examinations and failure analysis. In this paper, applications for the lens in microelectronic IC packages will be summarized.
Integrated Circuit SNR Improvement Using Dielectric Altering Compound, Laser Trim and FIB System
Authors: Dutt B.J. , Kroutch J.J. , Hooghan K.N. , Jenkins R.J. , Toth M.J.
Published: December 2020

Communication Signal Processors (CSP) did not have the Signal-to-noise ratio (SNR) performance expected. Significant differences were noticed between SNR values at wafer level and package testing. The analog section of the chip was suspected to be the culprit as the problem existed at the analog to digital conversion level. A Dielectric Altering Compound (DiAC) was chosen to simulate the packaged environment in decapsulated parts[1]. The DiAC was applied in and around the analog section, after application in other areas did not show the SNR degradation. The sampling capacitors in the A to D Converter section (ADC) were selectively coated with DiAC and laser trimmed to identify the offending circuit element. A signal trace running adjacent to the sampling caps, was isolated and suspected of coupling noise to the sampling caps. A FIB system was used to deposit a grounded metal shield that covered the suspect runner on a packaged part - subsequent testing showed no degradation. The above procedure was successful in isolating, verifying, and rectifying the SNR degradation. The SNR degradation was found on more than one code. The same procedure was used repeatedly on subsequent errant codes. Finally, a mask level fix on silicon achieved the desired SNR performance for all the codes.
Silicon Trenching Using Dry Etch Process for Backside FIB and Probing
Authors: Korchnoi Valentina , Fenigstein Amos , Barger Anastasia
Published: December 2020

The migration of microprocessor packaging from wire bond to flipchip technology in silicon "microsurgery" posed some challenges to on-chip circuit edit. The physical debug process through the backside silicon substrate was proposed as the common solution. The focus of this article is on step 2 of this process, namely the milling of large trenches over the edit area. Laser Chemical Etcher (LCE) was commonly used for this task. This article presents an alternative technique based on plasma dry etch process which consists of three steps: photolithography, plasma etching, and acoustic polishing. A detailed description of each step is provided, along with the details of experiments that were conducted for process optimization. The technique was successfully demonstrated in the preparation for backside FIB editing. However, the success rate of the proposed method is still lower than the LCE but this method can serve as a reliable backup process for the LCE.
3-D Defect Localization by Measurement and Modeling of the Dynamics of Heat Transport in Deep Sub-Micron Devices
Authors: Reverdy A. , de la Bardonnie M. , Kwakman L.F.Tz. , Lamy M. , Wyon C. , Doukkali A. , Murray H. , Perdu P.
Published: December 2020

Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.
Detection of a Counterfeit OTA Device and Certification of a Replacement Source
Authors: Hong Yong
Published: December 2020

The counterfeiting of semiconductor devices has become an important contributor as more components are used in the increasingly sophisticated audio and navigation systems while more suppliers are moving manufacturing plants off-shore. This paper presents a case study on how the authors were able to identify a counterfeit device and certify a replacement source. In this study, failed devices with Intersil CA3080 Operational Transductance Amplifier IC from factory testing and field returns in suspect lot codes were purchased from a second source, due to the unavailability of the obsolete device from the regular first source. The suspect lot codes that were not recognizable by the manufacturer were determined to be counterfeit devices. Many pieces of physical evidence suggested that the failed devices were not consistent with genuine devices directly purchased from the manufacturer.
Laser Logic State Imaging (LLSI)
Authors: Niu Baohua , Khoo Grace Mei Ee , Chen Yuan-Chuan Steven , Chapman Fernando , Bockelman Dan , Tong Tom
Published: December 2020

Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared photons emitted, and poor Signal to Noise Ratio (SNR) with low voltage and low leakage processes and products. Continuous-Wave Laser Scanning Microscope (CW-LSM) based Signal Imaging and Probing (CW-SIP) [5-9] technology is also widely used. It features inherently better spatial resolution than IREM, due to the use of monochromatic 1319nm or 1064nm laser light, and high SNR due to its weaker dependence on voltage and leakage, and, for signal imaging applications, the use of narrow band detection to reduce noise. However, CW-SIP can only detect modulating signals, so it couldn’t previously be applied to LSI. In this paper, we introduce an innovative approach that overcomes this limitation to enable Laser Logic State Imaging (LLSI). Actual fault isolation and design debug cases using this technology are presented to show its advantages in terms of resolution (>50% better), SNR (>2X better) and throughput time improvement, especially at low voltages (down to 500mV).
Pengaruh Pendekatan Pembelajaran STEM Project Based Learning terhadap Pemahaman Konsep Fisika Siswa
Authors: Sasmita Petri Reni , Hartoyo Zainal
Published: December 2020

Penelitian ini bertujuan untuk mengetahui pengaruh pendekatan STEM Project-Based Learning terhadap kemampuan pemahaman konsep fisika siswa. Metode penelitian yang digunakan adalah metode penelitian eksperimen awal dengan desain one-group pretest-posttest design. Teknik pengambilan sampling menggunakan metode sampling kelompok (cluster sampling). Pengumpulan data menggunakan tes awal (pretest) dan tes akhir (posttest) untuk mengukur kemampuan pemahaman konsep fisika siswa. Hasil perhitungan effect size menunjukkan bahwa pendekatan STEM Project-Based Learning berpengaruh besar terhadap kemampuan pemahaman konsep fisika siswa. Penelitian ini menunjukkan bahwa pendekatan STEM Project-Based Learning memiliki pengaruh terhadap kemampuan pemahaman konsep fisika siswa.
Normative and law regulation of land protection in the process of land reform
Authors:   Land Management Institute of the National Academy of Sciences of Ukraine, Barvinskyi A. , Kupriyanchyk I. ,   National University of Life and Environmental Sciences of Ukraine, Herasymenko O. ,   National University of Life and Environmental Sciences of Ukraine
Published: December 2020

The current state of the regulatory framework in the field of land protection is analyzed; such regulatory framework is designed to ensure the regulation of land protection measures in the agricultural sector of the economy. The declarative, fragmentary and unsystematic nature of most of the norms of national environmental legislation on land protection, along with the lack of adequate financial support, results in the low volume of actually implemented land protection measures. The latter, in turn, is the cause of a significant spread of degradation processes, deterioration of soil quality, reduced productivity of agricultural landscapes.It is proved that the only mechanism to ensure reliable protection of agricultural lands from harmful anthropogenic impact is land management, which provides improvement of land relations, planning and organization of rational use and protection of land at all levels from national to economic. The necessity of developing the National Program of Land Use and Protection as the main legislative act of strategic direction in this area is substantiated, making changes and additions to legislative acts on the content and structure of land protection measures, elaboration and approval at the legislative level of norms in land protection and soil fertility reproduction.
ANALYSIS OF THE HISTORICAL ALLEES OF UFA
Authors:   Bashkir State Agrarian University, Egorova L.I. , Karimova E.S. ,   Bashkir State Agrarian University
Published: December 2020

The article considers four alleys of the city of Ufa. The basic regulatory requirements are presented and the results of the analysis of the design structure of objects are presented. The sanitary and hygienic condition of the territory, the planning structure, etc. A balance of the areas of the territory was made on the basis of the constructed alignment drawings. The alleys considered are straight in regular and landscape styles. Plantings in Savushkino the alley – bunk, the rest single storey. Trees are free-growing, with a compact crown, durable and resistant to adverse conditions. The main breed is Linden, due to the fact that Ufa is included in its territorial growth. These alleys are popular among the population because of their historical significance and worthy spatial planning structure.
ENVIRONMENTAL PROTECTION
Authors:   Bashkir State Agrarian University, Magadieva A.A. , Murzabulatov B.S. ,   Bashkir State Agrarian University
Published: December 2020

The article discusses the key sources of environmental pollution and measures to preserve the environment and nature. By rational use of the Earth’s natural resources and responsible attitude to the environmental problem, this situation can be radically changed. One of the important problems of mankind today is environmental pollution. The environment is the habitat, the natural world that surrounds a person; includes natural and artificial environments. In many constituent entities of the Russian Federation, garbage reform has already begun to work. The goal of the garbage reform is the elimination of illegal landfills and the transition to separate waste collection, sorting and recycling so that they can be reused. Old landfills are subject to reclamation. Land reclamation as an integral part of environmental management in the development of environmental management projects in accordance with the requirements of regulatory documents is required. Thus, nature conservation is a set of measures and measures aimed at the rational use and reproduction of all natural resources of the Earth, as well as the conservation of the gene pool of flora and fauna, wealth of the subsoil, clean water and atmospheric air.
CADASTRAL WORKS IN CONNECTION WITH THE FORMATION OF THE LAND PLOT BY SECTION OF THE LAND PLOT OF THE MR KUSHNARENKOVSKY DISTRICT OF REPUBLIC OF BASHKORTOSTAN
Authors:   Bashkir State Agrarian University, Arslanov A.Z. , Minniakhmetov I.S. ,   Bashkir State Agrarian University
Published: December 2020

The article discusses the basic regulatory acts governing cadastral work. Using the example of the Kushnarenkovsky MR survey plan, the main stages of the formation of the survey plan were studied and presented: preparatory, cameral and field work. Cadastral registration - is the basis for the tax base for property tax, control over their use and protection of land and other real estate; real estate is assessed and a reasonable fee for its use is established, state registration of rights to real estate and transactions with it is ensured. The registry allows you to provide information in the civil circulation of land and other real estate. Cadastral registration and registration of rights allows you to protect the rights of citizens and legal entities to real estate.
SÖZLÜ TÜRK HALK MÜZİĞİ ESERLERİNDE ÖLÇÜ TESPİTİNE YÖNELİK BİR ANALİZ MODELİ
Authors: DÜZENLİ Emre , DOĞAN İsmet
Published: December 2020

Bu makalede, sözlü Türk halk müziği (THM) eserlerinin notasyonundaki en önemli unsurlardan biri olan “ölçü”nün tespitine yönelik bir analiz modeli önerilmiş ve bu model, örnek eserler üzerinde gerçekleştirilen analizlerle açıklanmıştır. Çalışma ile sözlü türkülerin ezgi, ritim ve söze dair özelliklerinin notaya daha doğru bir şekilde yansıtılması amaçlanmıştır. Tarama modelinin esas alındığı çalışmada, veriler kaynak taraması yoluyla elde edilmiş ve önerilen analiz modelinin uygulanması neticesinde bulgulara ulaşılmıştır. Bu açıdan bakıldığında çalışma, mevcut uygulamaları sorgulayan ve getirdiği önerilerle alana katkıda bulunmaya çalışan nitel bir araştırma özelliği göstermektedir. Çalışmanın örneklemi; Türkiye Radyo Televizyon Kurumu (TRT) THM repertuvarında bulunan ve özellikle Tunceli, Sivas, Malatya yörelerinde karakteristik olarak görülen, 8 ve 7 birimlik usûl yapılarının özel bir şekilde birleşmesinden oluşan türkülerden meydana gelmektedir. Söz konusu türkülerin, repertuvardaki sayıları çok olmasa da gerek nota deşifresinde gerekse tartımın doğru anlaşılarak icra edilmesinde çeşitli güçlükler çekilebilen türküler olması, bu örneklem tercihinin başlıca sebepleridir. Çalışmada ölçü kavramı, özellikle usûl ile bağlantılı olarak değerlendirilmiştir. Bu doğrultuda, analiz edilen eserlerin ölçüleri tespit edilirken usûl yapıları esas alınmış ve bir ölçü içerisinde bir usûl devrinin bulunması anlayışı benimsenmiştir. Usûl yapılarının tespitinde ise analiz bulguları ve yöresel icralarda vurulan usûllere dair bilgiler birlikte değerlendirilmiştir. Çalışma sonucunda; ölçünün söz, ritim ve form unsurları ile bağlantılı olarak tespit edilen usûle göre belirlenmesi gerektiği ve repertuvarda birbirinden farklı ölçülerle notaya alınmış olan örneklem eserlerinde ortak bir usûl yapısı olduğu sonucuna varılmıştır.