(Invited) Applications of Oxygen Inserted Epitaxy
Authors: Mears Robert J , Hytha Marek , Takeuchi Hideki 
Published: December 2024

Abstract

Silicon remains the semiconductor material of choice for most electronic applications of semiconductors and the silicon–silicon dioxide interface is one of the most studied interfaces. Over the past decade or more, epitaxial silicon-germanium (eSiGe) has found increasing applications in advanced logic, first for PMOS compressive source-drain (S/D) stressors, then as a channel material in high-k metal gate (HKMG) devices to help control the PMOS Vt, and more recently as a sacrificial layer to enable stacked nanosheets and even as a S/D liner to reduce phosphorus diffusion into the undoped nanosheets. Oxygen inserted (OI) silicon epitaxy was originally developed to complement and bridge the gap between silicon and silicon-germanium, and it has found applications ranging from improved figure of merit power devices to the most advanced nanosheet applications. In this paper we will provide an overview of OI silicon devices, their fundamental characterization and the electrical and physical benefits offered for a variety of semiconductor applications.

Introduction

Oxygen-inserted (OI) silicon had an unusual genesis for a semiconductor material, in that it was first explored using ab-initio quantum mechanical simulation. It was found that by carefully inserting a partial monolayer of oxygen during silicon epitaxy a stable layer could be manufactured where the individual oxygen atoms arranged themselves on a silicon-silicon bond, but that overall, the silicon retained its regular lattice, and the silicon-oxygen coordination was only one, as opposed to four in regular silicon dioxide. The idealized lattice configuration is shown in Fig. 1 (a). This configuration is technically thermodynamically metastable, but with a significant energetic barrier to formation of four-fold coordinated silicon dioxide, so that it can survive conventional semiconductor processing. Whereas a single oxygen atom is known to rapidly diffuse in silicon, there is a thermodynamic self-stabilization when the oxygen concentration has an aerial density of the order of 1E15cm-2, with an upper limit dependent both on the specific epitaxial recipe and the required defect density. If all available silicon bonds have attached oxygen, it is difficult to maintain high quality epitaxy. On the other hand, OI silicon has passed the most rigorous defect density requirements for advanced logic applications.

Dopant engineering - simulation

Oxygen is highly electronegative, and ab initio simulation shows that there is charge transfer in the silicon lattice in the near vicinity of the inserted oxygen as shown in Fig 1 (b). This leads to a change in the formation enthalpy for a single substitutional dopant atom or addition of a silicon point defect, vacancy or interstitial as shown in Fig 1 (c). The figure indicates that substitutional boron and phosphorus will have an energetic preference to be two or three silicon lattice atoms away from the inserted oxygen, whereas silicon point defects prefer to be coincident with the oxygen. As a result, the OI layers disrupt the diffusion of dopant-interstitial pairs, substantially reducing the dopant diffusion.

Dopant engineering – experimental data

OI silicon has been proven to create unique abrupt doping profiles for a variety of silicon and silicon germanium devices. In power devices, reducing the vertical and lateral diffusion below the OI silicon layer can be used to engineer significant improvement in critical figures of merit, such as the tradeoff between specific ON resistance (Rsp) and the breakdown voltage, and improved time constant (Ron∙ Coff) and reduced body current in RF power devices, while maintaining breakdown voltage. In advanced 3D applications, a 2nm thin liner of OI silicon has proven effective to create a diffusion barrier between highly doped epitaxial source/drain regions and undoped channels. By reducing dopant up-diffusion, thermally robust super-steep retrograde profiles can be created, which can be used to reduce local threshold voltage mismatch in both NMOS and PMOS devices by more than 50%. In gate-first HKMG planar CMOS applications, SiGe channel is used in the PMOS to facilitate Vt engineering. A thin OI silicon layer below the SiGe channel can be used to maintain a super-steep retrograde channel profile after HKMG formation and subsequent thermal processing.

Interface interactions

It has recently been discovered that OI silicon can also be used to engineer adjacent interfaces. For example, it has been shown by cryogenic measurements that OI silicon reduces surface roughness scattering of the silicon-dielectric interface. Also, OI silicon can reduce the interfacial dipole formed during HKMG processing, with benefits in reduced remote charge scattering and improved reliability.

These and other examples of engineered silicon and silicon-germanium devices will be discussed in detail.

Figure 1