bluuebunny/crossref_metadata_2025 huggingface dataset:
A New Approach to Outgassing Study of Plated Through‐hole Printed Boards
Authors: Feldin M. , Zevnik C. , Kovač I.
Published: February 2008

Outgassing of PTH PCBs at different stages of PCB production was studied with a modified IEC outgassing test, Draft June 1985, now included in IEC 326–2 Amendment No. 2, January 1988. Outgassing rate from single PTHs was quantitatively measured with a U‐tube manometer as a pressure of expanded steam escaped. Some technological parameters were taken into account and different comparisons were made: PCB production stage (drilling, copper and solder plating, reflowing) vs. outgassing rate, laminate thickness vs. outgassing rate. The contributions to outgassing of PTHs through PCB production, especially from copper and tin‐lead plating, are seen. On PCBs, drilled with different drills and soldered unpopulated on wave and drag soldering machines, outgassing faults were assessed. By multiple regression the relation between outgassing faults, hole wall roughness and plated copper thickness was calculated.
Environmental Considerations for Applying Photostructurable Liquid Soldermasks
Authors: Messner G.
Published: February 2008

Wherever solvents and solvent containing systems are employed, protection for people and the environment is a vital factor in the way that they are used. The paper addresses the following: Minimum contamination of the environment (air and water) by solvent emission; adherence to existing occupational safety laws: process technology and equipment that ensure high safety levels, and non polluting waste disposal.
A Complete Integrated Tooling System for Manufacture
Authors: Colquhoun W.
Published: February 2008

Wtih the increased use of multilayer boards incorporating yet smaller track and gap widths, careful thought must be given to the production of the manufacturing tooling to eliminate the faults which can be directly attributable to poor quality in the process. British Telecom have recently installed a Laser Photoplotter at their Research Laboratories which has the capacity to produce all phototools to the same degree of high accuracy demanded by today's fine line circuits. This paper points to the pitfalls of poor tooling production and shows how the prudent selection of a photoplotting contractor with the correct equipment and quality policy can reduce scrap levels and increase profitability.
Manufacturing Tolerances for High‐Speed PCBs
Authors: Ritz K.
Published: February 2008

A method is shown which allows evaluation of production tolerances for high speed PCBs (microstrip, stripline) in order to maintain the impedance Z within a specified range.
Analysis and Evaluation of TAB Bonds
Authors: Chung T.C. , Moore H.A.
Published: February 2008

Tape automated bonding (TAB) is one technology which is becoming widely adopted for interconnecting integrated circuits to a substrate or package. Both destructive and non‐destructive test methods for evaluation of TAB bonds are analysed and criticised. The key parameters and general guidelines of a destructive beampull test set‐up are identified and presented. The key features of four different non‐destructive test methods are described and discussed. It is found that no universal solution exists for non‐destructive evaluation of TAB bonds although some methods may be more useful than others under certain conditions and constraints. Data and experimental procedure are presented for correlation of scanning laser acoustic microscopy and beampull data.
Quo Vadis Printed (Circuit) Board?
Authors: Weinhold M.
Published: February 2008

Printed (circuit) boards have been used in the electronics industry for the past 25 years and more. The technology used to design and manufacture PCBs is well known and accepted. Recently, however, designers of electronic equipment have shown that the use of newer materials and systems, such as flexible and moulded circuits, hybrid circuits, or a combination of these, can significantly improve the cost/performance ratio for electronic interconnects. This paper examines some of the many possibilities open to electronics designers and how these new opportunities can improve the economics and performance of electronic equipment.
Inspection and Data Measurements for Solder Quality Process Control
Authors: Adams J.
Published: February 2008

Solder quality is a critical issue in circuit board production. However, the manufacturing process of today has few built‐in controls to ensure good solder quality. Instead, attention is only paid when a defect is found. The solution lies in the integration of inspection, test and process control. Now a new method, Scanned‐Beam Laminography, takes 3‐dimensional X‐ray slices of solder joints, enabling thorough inspection of each joint. Special software algorithms measure and report the solder joint conditions, creating a system which provides real‐time process control.
Methanol Depletion in Solvents
Authors: Johnson K. , Crawford T.J.
Published: February 2008

The Materials and Processes Research Laboratory of the Electronics Manufacturing Productivity Facility (EMPF) is undertaking a research project to examine the use of solvents in a vapour decreasing process. Fourteen solvents are included in this project. During the research, it was found that the concentration of the denaturant Methanol (MEOH) in the trichlorotrifluoroethane/ethanol (TCF/ethanol) mixture in the vapour degreaser boil sump was being depleted. The fresh material had a concentration of 0 · 35 percent MEOH by volume but the test data showed that this concentration dropped to levels between 0·19 and 0·11 percent MEOH. MEOH depletion in trichlorotrifluoroethane/methanol (TCE/methanol) azeotrope was also detected. The alcohol depletion that was discovered is a concern because when one component of an azeotrope breaks down, the entire azeotrope is affected and the constant boiling feature is no longer present. MEOH separation may also be a flammability hazard and may decrease the Threshold Limit Value (TLV) of the solvent because of MEOH toxicity. It was determined that the MEOH depletion was caused by the molecular sieve or desiccant adsorbing the alcohol. Recommendations are offered to minimise the flammability hazard associated with a MEOH‐adsorbing molecular sieve.
Residues on Soldered Printed Circuit Assemblies
Authors: Lea C.
Published: February 2008

Visible surface residues, commonly referred to as white residues, on soldered printed circuit assemblies are a very common but intermittent and unpredictable problem. Such residues, which are insoluble in normal solvents, are generally a rejectable condition. The chemistry of the deposition of white residues is complex; the deposits themselves are of a number of types and origins, and their incidence is associated with both materials and process parameters. This paper attempts to identify the different causes of the problem and suggest ways in which avoidance or removal is possible.
The Advantage of Joining Forces
Authors: Hinz G.
Published: February 2008

This article relates how a circuit board manufacturer joined forces with a user to develop a means of improving the packing density of SMD boards.
AT&S GmbH, Leoben‐Hinterberg, Austria
Authors: Cullen Lorna
Published: February 2008

When is an error not an error? A certain logistical error was made by this reporter, who, in the knowledge that AT&S have a facility at Engerwitzdorf close to Linz, duly caught a flight to Linz airport—only to discover that the next day's itinerary would begin with a 7.30 a.m. pick‐up for the 180 km journey to Hinterberg, where the actual PCB manufacturing plant is located! However, the touristic advantages made it unquestionably worth while. The day was hot and sunny, the sky cloudless. The journey from Linz, Austria's second largest city, along the Enns valley, passed through gently rolling landscape giving way to Alpine scenery at its most lush and verdant after the less settled weather of the early summer. Tree‐clad hills dotted with trim chalets, the soft brown coloured Alpine cattle grazing lazily, cool lakes and rivers with that greenness imparted by limestone, and in the villages en route every balcony a profusion of brightly coloured blooms.
Comparing Vision‐aided Stencil Printers
Authors: Lancaster T.
Published: February 2008

Surface Mount Technology relies on the use of screen or stencil printers for solder paste application. Many systems now incorporate complex vision systems to provide improved accuracy during printing. These systems advertise sub‐mil precision (x1|+3o<0·001 in.) but none provides a method to quantify this precision. With the advent of fine pitch pads [pad pitch ≤0·025 in.), accurate characterisation of the printing machine's capabilities is imperative for a successful manufacturing process. This paper will present a quantitative method with supporting experimental data, for analysing the printing capabilities of the stencilling machine.
Evaluation of the Corrosion and Reliability Aspects of Printed Circuit Boards Flow Soldered Using ‘No Clean’ Fluxes
Authors: Andrews G.J.
Published: February 2008

‘No clean’ fluxes (NCFs) have been in existence for a few years now. The initial claimed advantages of these fluxes were that post flow soldering cleaning would not be required, therefore a substantial cost‐reduction could be obtained in terms of no cleaning plant or cleaning solvent being necessary, and a consequent reduction in floor space requirements. Latterly, the restrictions to be placed on the manufacture of CFCs (the major flux cleaning solvent) via the Montreal Protocol have given these NCFs a much higher level of prominence. The advantages claimed for NCFs are very attractive; however, the fluxes represent a considerable technology shift from the conventional high solids rosin type fluxes which have been successfully used for many years. Probably the most important questions to be raised when considering their use are: ‘Will any remaining residue be corrosive and will the long‐term reliability of the printed circuit boards be affected?’ This paper sets out to address the following issues: (a) A definition of corrosion and long‐term reliability and what it means in practical terms, (b) an understanding of the basic formulation of NCFs and (c) evaluation and selection of test methods to establish confidence that corrosion and reduction in long‐term reliability, as described in (a), will not occur.
An Advanced Selective Metallisation Process for PTH Manufacture
Authors: Roubal J.
Published: February 2008

The Geislingen research laboratories of Dr Ing. Max Schlötter have developed Slotoposit, a new and advanced process for the manufacture of high quality PTH circuits, using conventional subtractive techniques. The aim of the research was to remove the hazardous formaldehyde present in most electroless copper systems, to improve hole wall adhesion and process the boards in one plating operation rather than the two (panel and pattern) employed in the traditional system. The following paper describes how a stable electroless nickel has been developed to achieve these ends and to increase productivity significantly by reducing the process steps and times.
The Effects of Ultrasonic Cleaning on Device Degradation
Authors: Richards B.P. , Burton P. , Footner P.K.
Published: February 2008

An investigation of the use of ultrasonic agitation for cleaning printed circuit boards using CFC‐based solvents has shown that, under the standard conditions required to produce clean assemblies, no damage will occur to the components studied. Damage can only be induced by use of anomalously longer times or higher power densities. In all cases in which damage has been induced, it is of a purely mechanical nature due to fatigue, and is located on the device bond‐wires and/or the package legs. Cleaning using CFC‐based solvents under standard ultrasonic conditions of power density and time etc. is readily achieved within 2 minutes, even with a minimum stand‐off height.
Rework and Repair of Printed Wiring Assemblies
Authors: Floeter E.J.
Published: February 2008

Advancements in printed wiring technology have led to an increased demand for technicians with the knowledge and manual skills necessary to perform modifications, rework or repairs to these assemblies. Five key requirements are necessary to control the process for repair. These elements include technical expertise, analytical assessment, structured procedures, proper tooling and performance inspection criteria. In this paper all five elements are analysed and selected guidelines are given for common rework and repair situations.
A Process for Multi‐level Copper‐polyimide High Density Interconnect Structures, Flex Circuits and TAB Tape
Authors: Volfson D. , Senturia S.D.
Published: February 2008

This paper describes a process for fabricating high density multilayer polyimide‐metal interconnect structures for packaging applications such as multichip carriers, flex circuits and multiconductor TAB tape. The process combines the advantages of a semi‐additive via process, such as the uniformity of the electroplated vias and the ability to produce vertical stacked‐up vias, with a processing sequence that does not require a temporary plating mask for vias or a planarisation/via‐top‐exposure step. The key idea behind the process is the fact that all of the circuitry in a multilayer interconnect is electrically connected to the upper conductor layer. This allows building the interconnect upside down on a temporary substrate using a continuous bottom level metallisation as an electrode for plating all level vias. This layer eventually becomes the upper conductor. After the processing is complete, the multilayer interconnect structure is either released from the temporary substrate, resulting in a multilevel multichip interconnect. After the multilevel structure is released, the continuous metal, which was on the bottom, is patterned with the upper conductor pattern, isolating the individual circuits. As an example, a process sequence for building a three‐metal‐layer substrate with 5 ?m by 30 ?m copper conductors, 50 ?m by 50 ?m square vias with 15 ?m interlayer polyimide is presented along with electrical test data. The process can be extended to producing mixed‐geometry multiconductor tape structures for TAB that result in tape frames with controlled conductor properties, and offer the potential for finer geometries for TAB fingers than are now available through conventional TAB tape processes.
The Pink Ring Condition in Multilayer PCBs
Authors: Graham S. , Hanson A. , Hattam M. , Jennison L. , Jordan M. , Klein G. , Lang I. , Lea C. , Moffat C. , Newlands M. , Streets P. , Tilbrook D. , Wallace D. , Wisnosky M. , Wylie I.
Published: February 2008

Pink ring is a ubiquitous problem arising during the manufacture of multilayer PCBs, being the manifestation of local delamination at the inner‐layer oxide interfaces around drilled holes and subsequent dissolution of the oxide during plating processes. Except in extreme cases, there is no evidence that the occurrence of pink ring identifies any in‐service reliability problem, but it is nevertheless a clear process indicator and is strictly monitored in statistical process control. The UK Printed Circuit Industry has carried out a collaborative research programme aimed at providing an understanding and a quantitative analysis of the pink ring condition. The research has advanced on two fronts: (i) an investigation into the micro‐mechanisms of the delamination and stress relief around drilled holes and subsequent rôles of the desmear and plating chemicals, and (ii) a statistical analysis of boards manufactured in a variety of ways, analysing the quantitative measurements of pink ring in terms of, for example, panel source, drill supplier, drill quality, drilling backing material, drilling chip rate, stack position, and panel entry/exit side.
Visual Inspection of Surface‐mounted Solder Joints
Authors: Lilley F. , Hobson C.A. , Koukash M.
Published: February 2008

Electronics manufacturing throughout the world now uses an increasing percentage of Surface Mount Technology (SMT). The compact and light‐weight surface‐mounted components offer a number of advantages to manufacturers. Unfortunately, however, these same beneficial characteristics make the quality of the product difficult to guarantee. As miniaturisation continues, the inspection problem becomes worse, and so advanced methods of inspection are required. Automatic inspection systems already exist, although an effective, inexpensive and reliable system has yet to be found. Recent work carried out within the Coherent and Electro‐Optics Research Group at Liverpool Polytechnic has looked at the feasibility of applying some of its established inspection methods to the problem of solder joint inspection. Extensive development must still take place; however, the methods employed have shown promise. The system uses structured light techniques to add height information to an image of the solder joint under inspection. In this way a 3‐D image of the joint may be built up, digitised and processed in a computer at high speed in order to determine its quality.
The Harmfulness of Blowholes in PTH Soldered Assemblies
Authors: Lea C.
Published: February 2008

One family of defects in soldered electronic assemblies that is almost invariably re‐worked is that due to outgassing, manifested as visible blowholes and solder blow‐out. It is known that re‐working can be very detrimental to the service life of an electronic assembly and should be avoided whenever possible. This paper describes work aimed to determine whether outgassing faults such as blowholes are harmful to service performance or whether more harm will be done by re‐working such faults. Standard test plated‐through‐hole (PTH) assemblies with controlled degrees of outgassing faults have been subjected to mechanical testing, thermal shock testing, mechanical fatigue, low cycle thermal fatigue and corrosion testing. Measurements in all these régimes have been carried out quantitatively with baseline controls. No evidence of significant loss of solder joint performance has been found, even for severe cases of solder loss. On the contrary, in cyclic fatigue testing, solder fillets with outgassing faults exhibit statistically significant performance enhancement. The conspicuous nature of blowholing and solder blow‐out undoubtedly over‐emphasises the problem during visual quality control inspection. Provided the copper barrel has been wet by the solder, outgassing faults should not be re‐worked. These faults should be used as process indicators and to draw attention to processes and the need for process control.
The Regulation of CFCs and Chlorinated Solvents in the 1990s
Authors: Lea C.
Published: February 2008

The worldwide production and the consumption of CFCs are now controlled through the Montreal Protocol. A meeting in London in June 1990 of the signatories of the Protocol will almost certainly tighten the controls on CFCs and introduce regulations to control other common chlorinated solvents. This paper gives the reasons why worldwide control of emissions of chlorinated substances is necessary, the events that led up to the present controls and the prognosis for future regulations. The properties and uses of the six key chlorinated solvents are discussed. Each industrial solvent‐using sector has a range of options available to implement cutbacks and eventual elimination of chlorinated solvents.
Press Cycle for Multilayer Bonding
Authors: Huschka M.
Published: February 2008

The actual press cycle is of utmost importance for the manufacture of multilayer printed circuit boards. It is necessary for both the engineers and the operators to understand its factors of influence in order to gain the highest production yields. This paper describes the differences between single‐stage and two‐stage press cycle, cold start and hot start, and also the difference between bonding of multilayers in a hydraulic press vs. in a vacuum autoclave. Detailed insight is given into what is actually happening during the press cycle and how it can be influenced. Special recommendations for bonding of no‐flow prepregs and of multilayers with buried via‐holes or metal cores are given in a separate chapter.
Alternatives to CFC‐113 for Cleaning Printed Circuits
Authors: Ellis B.N.
Published: February 2008

That the provisions of the Montreal Protocol (1987) are inadequate is a well‐known fact. The first revision of the Protocol will be approved by the Parties in June 1990, but the new provisions are still being discussed at the time of writing (December 1989). This paper discusses the various possibilities as to the available technologies which can replace current and future restricted cleaning solvents, as applied to the electronics assembly industry. It places particular emphasis on surface mount technology, as well as conventional assemblies.
A Thin Film Solder Mask for Assembling SMT Boards with Tented Via Holes
Authors: Pennock T.C.
Published: February 2008

New technologies bring new challenges to those who have to convert hand‐made prototype printed circuit boards into a robust, reliable, large volume manufacturing technique. The adoption by many electronic equipment producers of surface mount technology has demanded that production managers develop and understand new skills to increase yields and obtain the maximum reliability from the product. This paper describes in some detail the methods used, many of them empirical, to obtain the best performance. Of specific interest is the importance of selecting the optimum solder mask system to increase yields and provide reliability, and the reasons for selecting a high conformance thin film solder mask are discussed. Each process is examined step‐by‐step to highlight the pitfalls, suggestions are made as to how these can be overcome and the paper concludes with the author's view of how the new technology will evolve in the future—to present further challenges to the manufacturing processes.
Profile of the PCB Industry in Scotland
Authors: Francis Denise
Published: February 2008

What it may lack in numbers, Scotland has always made up for in the independence and enterprise of its inhabitants. While Scotland cannot claim much part in the earliest stages of printed circuit development, it should come as no surprise that the land which bore Alexander Graham Bell and John Logie Baird should have seized the opportunity of exploiting this other aspect of innovative technology, and that, for its mere 5 million inhabitants, it should boast a disproportionately large share of involvement in the printed circuit board industry. The total number of people involved in the PCB manufacturing industry (non‐captive market only) in England has been estimated at approximately 9,000—the numbers involved in Scotland total approximately 2,000, not far off 25% of the English figure. Wales and Ireland trail behind with about 300 and 400 respectively, while the Isle of Man, putting up a good show, numbers 16. Michael Hannon, of Michael Hannon Marketing (Ayr), comments, ‘Scottish PCB manufacturers have a disproportionate share of the UK rigid PCB home and export markets, as well as including in their number one of the largest flexible manufacturers in the UK. Out of the top five UK/Republic of Ireland PCB manufacturers’ production, the Scottish manufacturers represent about 55%. This is quite surprising when one considers that Scotland's population represents less than 10% of the total.’ Narrowing the focus from country to specific area, the Borders region is host to a number of PCB companies which together account for 55% of PCBs manufactured in Scotland, and 10% of the UK total.
Astro Technology Visit to Soltec
Authors: Cullen Lorna
Published: February 2008

On 1st February, undaunted by warnings of imminent gales, a party of almost 90 production managers and engineers embarked on charter flights from Manchester and Southampton to Eindhoven in the Netherlands. The group, which also included a few members of the electronics press, were the guests of Astro Technology who had planned an informative day trip to enable those present to learn more about the Dutch company, Soltec BV, and their latest soldering and board handling machine developments. The highlight of the day's programme was to be Soltec's approach to the ‘No‐clean’ soldering issue.
Soltec BV, Oosterhout, The Netherlands
Authors: Cullen Lorna
Published: February 2008

The earlier report on the Astro Technology visit to Soltec will have served as an introduction, and hopefully have whetted readers' appetites regarding learning still more about this interesting, internationally operating company of Dutch origin. Soltec has since 1983 been part of the Dover Corporation USA, a diversified conglomerate listed on the New York Stock Exchange and whose Technology Division comprises many companies offering equipment and products to the electronics industry (names like Universal, DEK, Cencorp, Corpane etc. springing readily to mind). The companies constituting the Dover Group are 100% owned by Dover, but management of the individual firms is carried out at local level by personnel appointed by each company.
Multichip Modules for Advanced Applications
Authors: Ginsberg G.L.
Published: February 2008

This paper discusses the increasing activity being directed towards microminiature multichip module packaging. It shows new substrate materials that are being investigated, including multilayer thin‐film ceramics and silicon wafers. Wire bonding, tape‐automated bonding (TAB), and flip device termination techniques are covered. Particular attention is given to the use of multichip modules for advanced data processing applications.
An Activity Number for Fluxes
Authors: Roché N.G. , MacKay C.A.
Published: February 2008

Current classification of fluxes is typically on the basis of a qualitative process with parameters like residue activity in a water extract or the ability to dissolve copper in a thin mirror film. The capability of quantitatively ranking fluxes by their total reaction capacity and reaction rate with copper oxide would provide valuable data for process design. Results are reported of experiments to establish a standard procedure to measure a flux activity number using a controlled reaction of a measured amount of flux reacted with an excess of a standard metal oxide.
Dr.‐lng. Max Schlötter GmbH & Co. KG, Geislingen, W. Germany
Authors: Cullen Lorna
Published: February 2008

When considering a technology as well established as electroplating, it seemed appropriate to visit this company with such a long history of involvement. It was 78 years ago that Dr.‐Ing. Max Schlötter formed an ‘electrochemical research laboratory’ in Leipzig, with the official opening date recorded as 12 September 1912. From this developed the Schlötter company, located in Geislingen in the province of Baden Württemberg since 1945, and recognised worldwide as a leading manufacturer of advanced processes and plant for the finishing industry.
Schoeller & Co. Elektronik GmbH, Wetter/Hessen, W. Germany
Authors: Cullen Lorna
Published: February 2008

A second summer visit to Germany in July took Circuit World to another large, well‐established company of high repute in the electronics industry—Schoeller & Co. Elektronik GmbH. The plant visited was the company's headquarters in Wetter, located some 100 kilometres north of Frankfurt and west of the university town of Marburg in Hessen. The factory is on the outskirts of Wetter, thus enjoying a peaceful rural setting. A second German production facility is situated at Grassau, near the Austrian border, while the company's third production plant is in Singapore and trades under the Degussa banner.
Industry News
Authors: Ellis B.N.
Published: February 2008

Nelco were pleased to announce the appointment of Mr George Grant to the position of Sales Manager from June 1st 1990. Mr Grant, who has considerable stature in the industry and brings a wealth of experience to Nelco from his previous 13 years with Gould Foil Division and more recently as Sales Director with GTS Flexible Materials, will report to Mr Charles Carter, President European Operations.
A New Adhesive System for Heat Sink Bonding
Authors: Hamilton S.
Published: February 2008

Current techniques for bonding thermal planes or heat sinks utilise materials and methods initially designed for other applications and so have several disadvantages. The new system described in this paper has been developed to give the optimum combination of bonding properties for this specific application.
Cyclic Voltammetric Studies on Synthetic Electroless Copper Plating Baths
Authors: Martyak N.M. , McDuffie B.
Published: February 2008

Cyclic voltammetric measurements were recorded on various synthetic electroless copper plating baths. The shapes of the current potential curves were observed as various components of the bath were added to an alkaline Cu‐EDTA solution. Peak potentials, Ep, were measured to identify the various species undergoing oxidation or reduction.
New Polymeric Multilayer Substrates and Packaging
Authors: Ohdaira H. , Yoshida K. , Sasaoka K.
Published: February 2008

This paper reports on the development of a simple manufacturing process for polymeric multilayer substrates utilising the thermoplasticity of thermoplastic resin. Features and defects noted in manufacturing trials of the substrates are also reported. The process involves a polymer‐based thick film conductive paste screen printed on a hole‐punched thermoplastic resin film and dried. The films are stacked to form multiple layers and are then compressed into one unit. As the extremely thin thermoplastic resin film layers are equivalent to a single layer, a feature of this substrate is its exceptional thinness. As thermoplastic resin is used as a base material, the soldering process and other connecting technologies which may be used in place of solder connection are also examined.
New Flexible Circuit Material Evaluation
Authors: Fossey D.J.
Published: February 2008

A project has been undertaken to evaluate new sources of flexible circuit materials for use by the author's company. The vast majority of flexible circuits are fabricated from polyimide film and acrylic adhesive circuit materials. One new polyimide film has been evaluated as an alternative dielectric film. Thirteen suppliers of flexible circuit materials have been identified. The paper discusses the results of the mechanical and electrical properties evaluation study of some of the new sources of flexible circuit materials.
Industry News
Authors: Galbraith Trevor
Published: February 2008

Robert Linsdell has been appointed Sales Manager by Dynachem, the Warrington‐based manufacturer of specialty chemicals for the printed circuit board industry.
Introducing the International Circuit Designers Association (ICDA)
Authors: Weinhold Michael
Published: February 2008

Ten years ago, long before surface mounting became an issue for mass production, the role of the printed circuit designer was mainly to design a conductive interconnect with through‐hole mounted connecting pins. At this time, manufacturing technology was very little influenced by the circuit designer, since all components were inserted into through‐holes and only a few basic rules were required for the soldering of the through‐hole mounted components.
Plasma Cleaning of Lands to Improve Bonding of Surface Mount Components to Printed Wiring Boards
Authors: Rust R.D. , Doane D.A. , Sawchyn I.
Published: February 2008

The bonding of surface mounted components to printed wiring boards (PWBs) is critical to the high yield assembly of components to the PWB. This process is one of the last steps performed in a complicated manufacturing and assembly sequence. Poor bondability at this late stage of assembly produces costly scrap. Aggressive wet‐chemical processes may succeed in cleaning the residues from the metal bonding lands, but in the process the polymeric materials that surround the land areas may be mechanically or visually damaged. Even when processing is carefully controlled during the final formation of land areas in the conformal coating, a thin residue, often invisible to the eye, can partially or fully cover the bonding land area. The residue may be extremely thin, but it inhibits bonding and is very resistant to conventional wet‐chemical cleaning methods. Plasma chemical etching is the one chemical process which can remove the residue from the metal lands and restore bondability without damaging other surfaces of the ready‐to‐assemble PWB. This paper reports examples of plasma removed residues from PWB surface mount bonding lands. The land areas are defined in photodefinable conformal coatings by conventional photolithographic techniques and have a non‐visible surface residue which inhibits the subsequent plating or soldering of the copper land. Auger analyses of the copper land surfaces prior to plasma processing show significant carbon peaks indicative of a polymeric residue. Auger analyses of the copper land surfaces following plasma processing show that the strong carbon peaks are gone.
Will Direct Plate Methods Replace Electroless Copper PTH Technology?
Authors: Thrasher H.
Published: February 2008

Industry pressure to find a more environmentally sound replacement for electroless copper technology is resulting in an increasing level of research and development by companies throughout the world. This paper addresses the issues in the Direct Plate versus Electroless Copper debate and discusses the technical challenges and the complex work required to develop and bring to market a viable new plated through‐hole process. The paper refers to Shipley's development of Crimson, a direct plate technology developed in laboratories in the US and England, which will eliminate electroless copper and all complexers from the PTH process.
Eliminating Solvents in the Cleaning of Circuit Assemblies: A Case History
Authors: Goldman I.B. , Aitken D.F. , Charest D.
Published: February 2008

This paper describes the work that was necessary to eliminate CFC (chlorofluorocarbon) cleaning solvents in the post‐soldering defluxing operation during assembly of printed wiring assemblies (PWA) in an off‐shore electronics manufacturing plant. The pressures—both external and internal—to utilise environmentally clean processes are becoming increasingly great in off‐shore manufacturing facilities, just as throughout the US. However, as will be shown in this paper, producers of electronic equipment must continue to ensure that a high level of product performance and reliability is not sacrificed when going to more environmentally favourable materials and processes. The study described here consisted of examining several water‐soluble flux materials, measuring ionic contamination levels of both Freon® TMS‐cleaned and water‐cleaned assemblies, and functional testing of the assembled devices at various levels of functional test severity. Materials, methods and actual physical data are presented in this paper.
LeaRonal (UK), Buxton, Derbyshire
Authors: Cullen Lorna
Published: February 2008

The winding, climbing roads of North Derbyshire still bore traces of the year's early snowfall, with mud‐splashed, hard‐packed drifts remaining by the roadside, when Circuit World visited LeaRonal on the outskirts of Buxton in December. At 1007 feet, Buxton is one of the highest towns in England. A spa and holiday resort, it is situated in the picturesque Peak District with its characteristic rocky crags, rugged moorlands and wooded dales. Britain's first national park—the Peak District National Park—covers some 540 square miles and it is at the edge of this leisure area that LeaRonal's High Peak Laboratories facility is located.
Effects of Rework on the Reliability of Pin Grid Array Interconnects
Authors: Lau J. , Leung S. , Subrahmanyan R. , Rice D. , Erasmus S. , Li C.Y.
Published: February 2008

In this study, the reliability of solder joints and plated‐through hole copper pads/barrels of pin grid array assemblies under rework condition has been determined by fatigue experiments. The cross‐sections of the re‐worked PGA assemblies (before and after fatigue tests) are also provided for a better understanding of the failure mechanisms of the composite structure. Furthermore, the load‐drop curves of the PGA interconnects for up to three reworks are provided for a better estimate of their fatigue life.
Adhesiveless Flexible Copper‐polyimide Thin Film Laminates
Authors: Fronz V.
Published: February 2008

For TAB tapes and flex circuitry, laminates with adhesives (3‐layer laminates) are commonly used. The drawbacks of adhesives are well known. Adhesiveless flexible copper‐polyimide laminates (2‐layer laminates) could avoid such disadvantages. Two‐layer thin film laminates may be produced using sputtering technology. Good adhesion strength between the copper and the polyimide film may be achieved by means of special plasma treatment. The advantages and disadvantages of 2‐layer flexible thin film laminates are discussed in this paper, along with their different production methods. The adhesion strength of 2‐layer laminates in comparison with 3‐layer laminates will be pointed out. Future uses of 2‐layer flexible thin film laminates will be considered, along with their benefits.
PWB Interconnect Strategy Using a Full Build Electroless Copper Plating System
Authors: Minten K. , Toth J.
Published: February 2008

Two current full build electroless copper deposits were investigated. This paper demonstrates that there are fundamental differences in the nature of their deposits. The consequences of these differences are highlighted for the PWB manufacturer.
The Effects of Ultrasonic Cleaning on Device Degradation—An Update
Authors: Richards B.P. , Burton P. , Footner P.K.
Published: February 2008

The effects of ultrasonic agitation on electronic components during PCB cleaning has long been the subject of controversy. This paper summarises the results of a series of studies into these effects for a range of components using CFC, aqueous and semi‐aqueous cleaning media. The variations with exposure time and power density under various ultrasonic stress conditions (loose, mounted on PCBs, or on purpose‐built test boards) are discussed. The results are encouraging and suggest that there is a large margin of safety when employing currently accepted regimes of operation and good quality components. However, the strong dependence of the damage accumulation on power density emphasises the need to specify and tightly control the power density used.
Advanced Multilayer Bonding Technology
Authors: Huschka M.
Published: February 2008

Continuously increasing requirements drive multilayer manufacturers to search for advanced manufacturing technologies and to evaluate new materials. This paper provides an insight into new multilayer bonding methods, improvements offered by laminators, and why to select high performance materials for special applications.
Correlation of Chemical Microstructure with Solderability of PCBs
Authors: Marshall J.L. , Miiller D.E. , Sees J. , Matteson S.E. , Weathers D. , Lichtenberg L.
Published: February 2008

A combination of analytical methods was used on printed circuit board coupons to conclude the following: (1) while steam ageing deteriorates solderability of tinned coupons, it does not increase the oxide thickness or tin‐lead ratio of the surface (top 50 Angstroms) of tinned coupons; (2) therefore, some other factor, probably oxidation of the copper or tin/copper intermetallic substrate, determines solderability of the coupons.
Interconnection Techniques for GaAs Packaging
Authors: Buck T.J.
Published: February 2008

In the never‐ending quest for speed, designers are now turning to digital GaAs integrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems associated with this transfer to GaAs logic. However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of existing multilayer printed circuit techniques using conventional dielectric materials and processing. This paper examines the design task in detail, and will present recent developments in shielded discrete wiring techniques as a possible solution for GaAs packaging.
Footprints of Fine Pitch SMDs
Authors: Klein Wassink R.J.
Published: February 2008

Most footprints of surface mounted components have been calculated on the basis of the sizes and tolerances of their electrodes, taking into account the various inaccuracies of the mounting processes to be applied. The introduction of components with very small connecting areas or leads (e.g., fine pitch IC packages) does not only imply smaller solder land dimensions, but also a different approach for the calculation of the footprint. This approach tackles the question of the required insulation spacing and lead/land overlap, and the ‘optimum’ solder land dimensions and the available mounting (i.e., placing and fixing) freedom are then obtained. The reduction of mounting freedom with decreasing pitch distances is quantitatively demonstrated. The ratio width of lead/size of pitch proves to be an important parameter in this respect. Requirements for mounting quality are linked with certain criteria for inspection of soldered joints (for example, regarding shift and rotation and vice versa), and some of these criteria are discussed in more detail.
Analytical and Experimental Studies of 208‐pin Fine Pitch (0·5 mm) Quad Flat Pack Solder‐joint Reliability
Authors: Lau J. , Dody G. , Chen W. , McShane M. , Rice D. , Erasmus S. , Adamjee W.
Published: February 2008

The reliability of 0·5 mm pitch, 208‐pin FQFP solder joints has been studied by experimental temperature cycling and 3‐D nonlinear finite element analysis. Temperature cycling results have been presented as a Weibull distribution. Thermal fatigue life of the solder joints has been estimated based on the calculated plastic strain and isothermal fatigue data on solders. A correlation between the experimental and analytical results has also been made.
Advanced Metal Core Substrates as a Solution for Multichip Module Backplanes
Authors: Buck T.J.
Published: February 2008

In future generations, electronic systems will rely extensively on advanced IC technology to achieve higher performance levels. However, with limits placed on the level of integration that can be obtained on a single IC, a need still exists for an interconnection hierarchy to provide the necessary density transform between system components. A recent addition to many high performance interconnection structures has been the Multichip Module. By eliminating the conventional IC package, MCMs have dramatically reduced the electrical length between devices, thereby minimising propagation delay, crosstalk, and attenuation. Although MCM techniques will offer many performance advantages, they also present many design challenges at subsequent levels of interconnection. This paper will focus on the requirements of MCM backplanes interconnecting several modules and, as a solution, will present recent work on advanced metal core substrates. MCM substrates provide a tremendous density advantage, however, the interconnection between modules is still a formidable task. Modules often have I/O densities of 300 to 500 leads per square inch and typically dissipate 10 to 50 watts per square inch. In addition, with sub‐nanosecond rise times, the distance between modules is often sufficient for signal paths to be treated as transmission lines. In an effort to meet these requirements, metal core circuits based on copper, copper Invar, and copper molybdenum have been fabricated using 0·0025 in. diameter embedded discrete wiring technology. Combined with a Kevlar surface layer suitable for wire bonding and blind laser drilled vias to access the internal wires, this technique offers many benefits. As many as 4 conductors can pass between holes on 0·050 in. centres in a single wiring layer only 0·018 in. thick. With the absence of interstitial vias, additional substrate area can be dedicated to create a sizeable thermal path, essential to conduct the heat from the MCM to an internal metal core. Together, these features have made this an attractive approach for interconnecting multichip modules.
Test Coupons as an Aid to Process Control of the PCB Manufacturing and Assembly Processes
Authors: McCormack B.M.
Published: February 2008

A high percentage of circuit boards manufactured in the electronics industry are of an irregular shape and are produced on a standard panel outline to facilitate assembly handling. The unused pieces of circuit board pass through the same processes as the useful parts and are normally discarded. This excess material could, among other things, be used to evaluate the quality of a bare board or an assembly. This paper will highlight the usefulness of designing test patterns on this excess material, namely test coupons, in terms of how these can be used to monitor all of the manufacturing and assembly process steps. It will also show how these coupons can be used to make the board easier to assemble and how they may actually lead to an improvement in the quality of the assembly and an increase in production yields. Suggestions will be made as to the types of test pattern that can be used, as well as how these patterns can be utilised as process control checkers. Since the test coupons are incorporated in the board design, a quality check of 100% of the boards that are being processed is possible. This would highlight any board‐to‐board variation if it were present. It would also allow for destructive testing to be carried out, without damaging any of the working product. The applications of these patterns are wide ranging. They can be used to check bare board quality—etch definition, layer registration, plating quality, solder mask definition etc. They can also be used to monitor the assembly processes for SMT and conventional PTH assembly types—cut and clinch quality, paste printing quality, onsertion accuracy, reflow/flow soldering quality and assembly cleanliness, among others. Many of these applications are examined in this paper.
A Possible Approach to Multilayer Manufacture to Enhance Soldeverability and Shelf Life
Authors: Mitter V.
Published: February 2008

As miniaturisation reaches new levels with the advent of surface mount technology, the mixed technology of surface mount and through‐hole brings into focus the need for soldermaskless printed circuit boards which can have considerable shelf life before assembly and which can satisfy the new requirements of NTL‐STD‐SOLD for optimum solderability. The ‘weak‐kneed’ hole due to the tin‐copper intermetallic encountered in hot air levelled boards needs to be eliminated. This paper describes a process based on cap layers for terminal and test pads, and a duplex alloy plating of tin, nickel and lead on the outer layers which has several advantages over the currently preferred solder mask over bare copper/selective solder coating process.