Thin Quad Die Package (QDP) Development
Authors: Bowers Shaun 
Published: January 2025

In the world of solid-state memory fabs, bits per mm2 rule. In the memory packaging market, mm2 of silicon per a

given package thickness is the

defining feature. Both the memory

architecture of the wafer and the

package technology take advantage of

3D structures to achieve best in class

bit density. In the case of the wafer

fab, 3D NAND and other technologies

are pushing the envelope to meet ever

increasing storage needs by stacking

memory cells on top of one another. In

the memory packaging market, the industry typically stacks individual

die on top of one another within the

package. The higher the number of the

die stacked equates to more memory cells in a given package. The current state of the art is 16 die in a 1.2 mm

package but there is a constant need to reduce package thickness. To meet

further reductions in memory package

thickness, new approaches are needed to allow a large silicon (Si) area in a small volumetric space.

The presentation will focus on the

development of a new packaging format that allows for extreme silicon area

density versus package volume. The

project demonstrates how to vertically

stack four wire-bonded die in a

package with an overall package

thickness of 200µ. The quad die package (QDP) development involved four fundamental building blocks to achieve the goal of 200µ total package thickness.

First, the silicon wafers must be

extremely thin, so it was determined

that an advanced wafer thinning

process mplementing stealth dicing before grind (SDBG) would provide the best chance to achieve the desired thickness. SDBG was used to thin the Si wafer to the required hickness of 25µ.

Second, a unique design and bonding

structure was utilized to allow overall package thickness to be less than 200µ. The design avoided the need for low loop bonding, which would take the wire outside of the dimensional envelope of 200µ in the z-direction. This approach allowed for use of a multi-layered laminate substrate as an interconnect to the outside of the

package.

Thirdly, a novel die attach method was

used on the new design format. This

method takes advantage of a release

technology similar to those used in panel and strip level manufacturing

and eliminated wasted space in the z-

direction.

Lastly, design simulation determined

how to manage package warpage for such a thin design and identified the

features needed to remain within

useable targets. The simulation results influenced the design of the package and substrate to maintain

warpage to levels of similarly sized

packages in high volume production.

The four facets of the development were confirmed using live silicon and were electrically, mechanically and

environmentally tested in component

level reliability testing. The results

indicate that this package provides a

leap forward in accommodating high

silicon density in a thin package. The

ability to deliver a 200µ package with

a four die stack will help meet the

demands for smaller/thinner mobile devices, provide freedom in designing groups of packages to meet the memory needs of the system and lead to other adaptations that can take advantage of

extremely tight z-height restrictions.