bluuebunny/crossref_metadata_2025 huggingface dataset:
(Invited) Reliability of SiGe HBTs in Long-Term Operation
Authors: Fischer Gerhard G.
Published: September 2014

The main reliability issue in SiGe HBTs is the cumulative degradation of the base current occurring during combined high collector voltage, high emitter current stress. This ageing is the result of the interplay between oxide interface trap creation and annihilation. Long-term stress tests show that the ageing rate varies significantly over time, reveals saturation behavior, and depends in a much more complex way on stress load as previously assumed. At high enough junction temperatures degradation can be reversed leading to efficient thermal recovery of the HBTs. With simple duty cycles switching between ageing and recovering states it could be demonstrated that pure DC stress represents an upper limit for degradation in SiGe HBTs.
(Invited) Anisotropoic Strain Evaluation in the Finite Si Area by Surface Plasmon Enhanced Raman Spectroscopy
Authors: Ogura Atsushi , Kosemura Daisuke
Published: September 2014

For the state-of-the-art large-scale integrated-circuits (LSI), Strain technology is indispensable for the transistor performance improvement. Raman spectroscopy has been performed to evaluate the strain induced in the devices owing to its advantages, i.e., non-destructive, easy-to-use, high-spatial resolution, and high throughput. We have been engaged in the development of extremely sensitive Raman system for the evaluation of strain at the Si surface using UV-laser excitation. In this paper, we report our achievements for the improvement of spatial resolution, evaluation of complicated strain state, and signal enhancement from localized area to evaluate the strain in the state-of-the-art LSI using Raman spectroscopy.
Surface Reaction in Thin Film Formation of Si1－xGex Alloys on Si(100) by Electron-Cyclotron-Resonance Ar Plasma Chemical Vapor Deposition without Substrate Heating
Authors: Ueno Naofumi , Sakuraba Masao , Sato Shigeo
Published: September 2014

Low-temperature epitaxial growth process of group IV semiconductors (e.g. Si, Si1−xGex and Ge) is important for quantum-effect nano heterostructures of group IV semiconductors especially with suppressed intermixing at heterointerfaces. Plasma CVD process is one of the candidates for low-temperature epitaxial growth of group IV semiconductors. The Ge fraction of Si1−xGex thin film is in good agreement with the GeH4 partial pressure ratio. Rate coefficient [(Si1−xGex deposition rate) × (Ge or Si fraction) / (partial pressure of GeH4 or SiH4 (PGeH4 or PSiH4))] tends to become larger by increasing PGeH4 or decreasing PSiH4. Change of rate coefficients depends not only on Ge fraction but also on deposition rate. Hydrogen incorporated in the Si0.50Ge0.50 film epitaxially grown on Si(100) is as small as the order of detection limit of our FTIR measurements (about 1020 cm-3) or below. Height of X-ray diffraction peak for the deposited Si0.50Ge0.50 film drastically increases by reducing GeH4 and SiH4 partial pressures i.e. deposition rate. Epitaxial growth of Si/Si1−xGex/Si(100) quantum heterostructure without strain relaxation can be also confirmed. From these results, our ECR Ar plasma CVD process is expected to be applicable to quantum heterostructures formation especially with suppressed intermixing.
Reduction of RIE Induced Ge Surface Roughness by SF6-CF4 Cyclic Etching Method
Authors: Ma Xuezhi , Zhang Rui , Zhao Yi
Published: September 2014

The SF6-CF4 cyclic RIE etching method is proposed in this work to effectively control the surface roughness and morphology of Ge Fins, aiming at the fabrication of superior Ge FinFETs for future CMOS applications. It is found that the surface roughness of Ge after RIE etching can be sufficiently suppressed by introducing SF6-O2 etching steps into CF4-O2 etching, with remaining a relatively large selectivity of vertical etching to horizontal etching of Ge. As a result, with a SF6-O2 proportion of 60%, an optimized RMS roughness of 0.9 nm has been revealed for Ge surfaces after etching with a selectivity of over 4 for vertical etching to horizontal etching of Ge.
Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current
Authors: Teherani James T. , Chern Winston , Antoniadis Dimitri A. , Hoyt Judy L.
Published: September 2014

Ultra-thin HfO2 MOS capacitors on strained-Ge (s-Ge) have been fabricated with an extracted effective oxide thickness (EOT) of 4.9 Å and leakage current less than 0.2 A/cm2. The CV measurements show no hysteresis and areal capacitance scaling for device sizes of 50×50 to 200×200 µm2. A high series resistance is observed, likely due to a 500 meV valence band offset between the s-Ge and relaxed Si0.55Ge0.45 virtual substrate. The capacitance results suggest an extremely-scaled, high quality dielectric on s-Ge suitable for deeply scaled CMOS.
(Invited) Application-Specific SiGe HBT Optimization
Authors: Magnée Peter H.C. , Dalen Rob van , Mertens Hans , Vanhoucke Tony
Published: September 2014

State of the art SiGe BiCMOS processes today show impressive high-frequency performance, with fT and fMAX exceeding 500GHz. However, there is also a vast application space that does not require these very high frequencies, but that can still benefit from the performance improvements made in HBT technology. By taking into account the specific application requirements, the transistor can be optimized e.g. for extremely low noise figures at moderate frequencies, or the high fT can be traded against a higher breakdown voltage, without degrading fMAX, for a better power capability. In this paper, the various aspects of tuning the technology parameters to fit the application requirements will be discussed.
SiGe HBTs in 90nm BiCMOS Technology Demonstrating fT/fMAX 285GHz/475GHz through Simultaneous Reduction of Base Resistance and Extrinsic Collector Capacitance
Authors: Liu Qizhi Z. , Adkisson James W. , Jain Vibhor , Camillo-Castillo Renata A. , Khater Marwan H. , Gray Peter B. , Pekarik John Jack , Zetterlund Bjorn , Divergilio Adam W. , Kerbaugh Michael L. , Harame D. L.
Published: September 2014

Development of SiGe HBTs in BiCMOS technology with both high f
T and f
MAX faces significant challenges. To increase f
T, thinning the base and collector thickness is generally the first step to reduce the carrier transit times, but this increases the base resistance and the collector-base capacitance, which impacts f
MAX negatively. Increasing collector doping is also often employed to increase f
T, but this increases collector-base capacitance, which drives f
MAX down. To overcome these limits, millisecond anneal techniques, low temperature silicide and low temperature contact processes are employed to reduce the base resistance. Concurrently a novel approach to reduce the extrinsic collector-base capacitance is developed, without affecting the manufacturability and integration with CMOS. The simultaneous reduction of both base resistance and collector capacitance enables high performance SiGe HBT devices in 90nm BiCMOS Technology with operating frequencies of 285/475GHz f
T/f
MAX.
(Invited) Electro-Thermal Characterization of SiGe HBT PA-Cells
Authors: Zimmer Thomas , Weiß Mario , De Matos M. , Maneux Cristell , Fregonese Sebastien
Published: September 2014

This paper investigates electrical performances of two different transistor array configurations operating as 60GHz power amplifier cells. Maximum RF power gain and a maximum PAE are determined using a load-pull measurement set-up. The electrical and thermal behavior between multi-finger transistor and multi-transistor array are compared. Drawbacks and advantages of each structure are discussed and the current preference of the usage of multi-emitter structures versus multi-transistor structures is questioned.
Second Order Intermodulation Linearity of a 200 GHz SiGe HBT Technology
Authors: Li Zhen , Niu G. , Wei Xiaoyun
Published: September 2014

We present here characterization of second order intermodulation linearity in a 200 GHz peak fT SiGe HBT technology. The impact of collector current, collector-emitter voltage, transistor size and breakdown voltage are investigated. Implications to circuit design are discussed.
A Study on the Sensitivity between Oxygen Radical and Negative Color PR in Exposure Process of CMOS Image Sensor
Authors: Hwang Sang Duk , Kim J N , Kim Y J , Choi J K
Published: September 2014

Color filter process for CMOS image sensor process is divided into micro-lens and color layer steps. And the structure of color layers is made by building up photo resist(PR). Then, color is distinguished by color pattern of image sensor after light induced transmits through the pattern built. So negative PR is generally used for the structural characteristic in color filter process. Negative PR needs high-dose which results in deactivation effect by oxygen radical. In this paper, the experiment was developed by reducing oxygen radical and the process in order to pattern by reduced dose was acquired
Low-Temperature Deposition of Thin Si, Ge, and SiGe Films Using Reducing Activity of Ballistic Hot Electrons
Authors: Koshida Nobuyoshi , Suda Ryutaro , Yagi Mamiko , Kojima Akira , Mentek Romain , Gelloz Bernard , Mori Nobuya , Shirakashi Junichi
Published: September 2014

It is shown that a wet process for thin Si and Ge films deposition based on the ballistic electron injection into solutions is available for SiGe. A nanocrystalline silicon (nc-Si) diode is composed of a thin Au (10 nm)/Ti (1 nm) film surface electrode, nc-Si layer (~1 µm), n+-Si substrate, and back contact. The electrochemical effect of ballistic hot electrons was confirmed by cyclic voltammetry analyses. Electrons are emitted from the nc-Si device on which a very small amount of SiCl4+GeCl4 solutions is dripped. After the emitter operation, thin SiGe films are deposited on the emitting surface with neither byproducts nor contaminations as in the case of thin Si and Ge films deposition. Based on the structural and compositional characterizations of deposited SiGe films, the specific features of this reduction-induced deposition mode are discussed in comparison with the conventional processes.
Fermi-Level Depinning of Ge Schottky Junction Using Se Treatment
Authors: Lim Yi-Rang , Lee Ye-Ji , Shim Ku-Hwan , Janardhanam V. , Choi Chel-Jong
Published: September 2014

Depinning of the Fermi-level at metal/Ge Schottky junctions was achieved by Se treatment at room temperature. Due to the strong Fermi-level pinning close to the valence band edge in Ge, Schottky and Ohmic behaviors were observed in conventional Al Schottky contact s to n- and p-type Ge, respectively. However, Al Schottky contacts to n- and p-type Ge with Se treatment became Ohmic and Schottky, respectively. The transmission electron microscopy (TEM) examination combined with X-ray photoemission spectroscopy (XPS) analysis showed that Se treatment at room temperature yielded the formation of a fairly uniform Se-Ge alloy film with partially ionic binding nature caused by the chemical reaction between Se and Ge. This led to the reduction of surface states of Ge surface along with the passivation of dangling bonds by the incorporation of Se atoms, which was responsible for Fermi-level depinning at Al/Ge junctions.
Fast and Accurate in-Line Monitor of Boron Implantation Energy and Dose by Spectroscopic Ellipsometry
Authors: Wen Tsai-Yu , Lu Tsuo-Wen , Wang Yu-Ren , Lin Chin-Fu , Wu J Y , Chang Shao-Ju , Chiu Sheng-Min , Huang Chien-Jen , Cheng Chao-Yu , Cheng Juli , Raphael Getin , Jiang Zhiming , Tan Zhengquan
Published: September 2014

Boron is a specified dopant applied at semiconductor manufacturing, which used for ultra-shallow junction (USJ) formation and stable SiGe stressed channel configuration at advanced generation. Aggressive device scaling over the last decade leads the precise implantation control much important and critical. In this paper, a non-destructive and fast technology for inline Boron implanted depth and dose concentration measurement was presented using Spectroscopic Ellipsometry (SE) methodology. Excellent correlation with SIMS reference result achieved. Further, the implanted processes quene time (Q-time) issue was also be considered for stable production monitor in foundry side. The metrology theory could extend to other doping species at medium and low energy application field.
Detection of Effect of Strain on the Valence Band Structure of SiGe by HXPES with High Spatial Resolution
Authors: Yamahori Shunta , Sasago Tomoya , Sakurai Takuya , Yonekura Eisuke , Sawano Kentarou , Ikenaga Eiji , Nohira Hiroshi
Published: September 2014

We have investigated the effect of the uniaxial strain on the binding energy of valence band top, Si 1s and Ge 2p core level by Hard X-ray Photoemission Spectroscopy (HXPES) with the high spatial resolution. By combining HXPES with the high spatial resolution using K-B mirrors and uniaxially strained SiGe samples fabricated by selective ion-implantation, we succeeded in observation of the effect of uniaxial strain on the valence band structure. We have found that the energy difference between Ge 2p and valence band top in the case of uniaxial strain is smaller than that in the case of biaxial strain.
Ge Condensation Using Rapid Thermal Oxidation for SGOI Substrate Preparation
Authors: Gourhant Olivier , Pribat Clement , Barge David , Mazzocchi Vincent , Andrieu François , Abbate Francesco , Juhel Marc , Gaumer Clement , Baylac Elise , Pofelski Alexandre , Bidaud Maud , Serventon Germain
Published: September 2014

Ge condensation using RTO is investigated to produce good quality SGOI channel. This study shows the significant role of the RTO temperature in Ge condensation. First, Ge diffusion requires a RTO temperature above 950°C to start homogenization of Ge in the channel. This is mandatory to minimize the risk of defects generation. Then, inconsistently to thermodynamics calculation, Ge-O bounds are formed during oxidation and a higher temperature oxidation leads to a lower Ge-O bounds formation. Therefore, Ge condensation using a 1100°C RTO is preferred. It is implemented in a SOI/SGOI co-integration to produce SGOI channel for PMOS transistor. Such channel exhibits a very smooth surface (RMS roughness below 0.15nm), a controlled Ge content (16%) and a high compressive strain (1%). Moreover, PMOS Vt modulation by the Ge concentration was performed with a sensitivity of 10mV/%. As a result, this study demonstrates that RTO is a solid alternative to furnace for Ge condensation.
(Invited) Monolithic Integration of InP Based Structures on Silicon for Optical Interconnects
Authors: Kataria Himanshu , Metaferia Wondwosen , Junesand Carl , Sun Yan-Ting , Loududoss Sebastian
Published: September 2014

Monolithic integration of InP based structures on Si for optical interconnects is presented. Different strategies are demonstrated to achieve requisite InP platform on Si. In the first strategy, defect free isolated areas of epitaxially and laterally overgrown InP are obtained on Si and the InGaAsP based quantum wells directly grown on these templates have shown high material quality with uniform interfaces. In the second strategy, selective area growth is exploited to achieve InP nano pyramids on Si which can be used for the growth of quantum dot structures. In the third and the final strategy, a method is presented to achieve direct interface between InP and Si using corrugated epitaxial lateral overgrowth.
Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding
Authors: Asadollahi Ali , Zabel Thomas , Roupillard Gabriel , Radamson Henry H , Hellström Per-Erik , Östling Mikael
Published: September 2014

We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.
(Invited) Challenges and Opportunities in the Design of Tunnel FETs: Materials, Device Architectures, and Defects
Authors: Esseni David , Pala Marco G. , Revelant Alberto , Palestri Pierpaolo , Selmi Luca , Li Mingda (Oscar) , Snider Gregory , Jena Debdeep , Xing Huili Grace
Published: September 2014

Tunnel FETs are perceived as promising emerging devices to improve the energy efﬁciency of CMOS integrated circuits. This paper presents results and discussions about some selected topics concerning the working principles and design options of Tunnel FETs, which we believe will play an important role in the development and optimization of these transistors in the near term future.
(Invited) Spin Transport in Germanium
Authors: Kawakami Roland Kenji
Published: September 2014

I will review the work leading to the first demonstration of spin transport in germanium. This includes the development of Fe/MgO/Ge(001) junctions by molecular beam epitaxy, characterization of Schottky barriers at this junction, and the fabrication of germanium lateral spin valves consisting of a Ge spin transport channel and Fe/MgO electrodes. We employ the nonlocal spin transport geometry to isolate pure spin currents (without net charge currents) that flow from the spin injector to the spin detector. Most importantly, we are able to provide the unambiguous proof of spin transport by observing the Hanle spin precession in the nonlocal geometry. We compare the results with three-terminal Hanle measurements and discuss a new future direction for spintronics research using a two-dimensional form of germanium known as germanane.
(Invited) Three-Dimensional Epitaxial Si1-XGex, Ge and SiC Crystals on Deeply Patterned Si Substrates
Authors: von Känel Hans , Isa Fabio , Falub Claudiu V. , Barthazy Eszter Judit , Müller Gubler Elisabeth , Chrastina Daniel , Isella Giovanni , Kreiliger Thomas , Taboada Alfonso Gonzalez , Meduna Mojmir , Kaufmann Rolf , Neels Antonia , Dommann Alex , Niedermann Philippe , Mancarella Fulvio , Mauceri Marco , Puglisi Marco , Crippa Danilo , La Via Francesco , Anzalone Ruggero , Piluso Nicolo , Bergamaschini Roberto , Marzegalli Anna , Miglio Leo
Published: September 2014

We show that geometric shielding of the reactive flux in chemical vapor deposition by tall neighboring structures obtained by deep substrate patterning, along with short surface diffusion lengths, can provide nearly space filling arrays of high-quality epitaxial crystals despite large mismatches of lattice parameters and thermal expansion coefficients. The density of extended defects is strongly reduced by the method, and wafer bowing and crack formation largely inhibited. The concept is shown to be valid for SiGe/Si heterostructures ranging from pure Si to pure Ge both on Si(001) and Si(111) substrates. Here, dislocations are efficiently eliminated from three-dimensional faceted crystals with high-aspect ratios on top of micron-sized Si pillars. The application to 3C-SiC/Si(001) ridges, characterized by a lattice mismatch of nearly 20%, provides significantly lower stacking fault densities compared with layers grown on planar substrates.
(Invited) Si Waveguide-Integrated High-Speed Ge Photodetector
Authors: Fujikata Junichi , Miura Makoto , Noguchi Masataka , Arakawa Yasuhiko
Published: September 2014

We present a Si waveguide (WG)-integrated high-speed Ge-PD (photodetector), which shows high speed of 50 GHz bandwidth with small footprint. First, we compare Si WG-integrated p-i-n and Schottky Ge PDs, which show very low dark current density with high efficiency. In addition, we study two types of p-i-n Ge-PDs, which are evanescently coupled and butt-joint coupled with the Si WGs. The optimized evanescently coupling type of a p-i-n Ge-PD shows good photoresponsivity of 0.8 to 1.0 A/W and low dark current density of 0.6 nA/μm2. It shows 50 GHz bandwidth at Vdc more than 3 V, and 30 GHz at 0 Vdc in case of 10 μm optical coupling length. Furthermore, we develop a butt-joint type p-i-n Ge-PD and achieve 46 GHz bandwidth and high-efficiency with only 5μm optical coupling length.
Post-Growth Laser Annealing for High-Performance Ge Photodiodes on Si
Authors: Kawamata Yuta , Nagatomo Sho , Fukuda Kotaro , Izawa Yusaku , Hoshino Satohiko , Ishikawa Yasuhiko
Published: September 2014

Near-infrared (NIR) laser light is used to irradiate Ge epitaxial layers on Si as a post-growth annealing process with a low thermal budget for high-performance photonic device applications. In contrast to ordinary furnace/lamp annealing, where both of Ge and Si are heated, NIR laser irradiation enables a preferential annealing of Ge layers due to the optical absorption selectively in Ge. Ge pin photodiodes on Si, fabricated applying a preferential annealing of Ge with an NIR laser (1.07 µm in wavelength), show a significant reduction of dark leakage current with keeping high photodetection efficiencies, resulting from the reduction of threading dislocation density in Ge. The results indicate that the NIR laser annealing is promising to incorporate the fabrication of Ge devices at the back end of line in the Si process.
Characterization of Ge1-x-ySixSny Ternary Alloys – Comparison of UHV-CVD and Gas Source MBE Growth
Authors: Claflin Bruce , Kiefer Arnold , Beeler Richard , Fang Z.-Q. , Grzybowski Gordon
Published: September 2014

Electrical, structural, and materials characteristics are reported for Ge1-x-ySixSny ternary alloys grown by UHV-CVD and gas source MBE. Composition and local bonding configuration are determined by XPS. Crystalline structural characteristics and relaxation of film strain were measured with X-ray diffraction. Temperature-dependent Hall-effect measurements show highly conductive layers although care must be exercised to account for parallel conduction through the substrate. Deep level transient spectroscopy shows two electron traps at low temperature in Ge1-x-ySixSny p-i-n diodes grown by UHV-CVD while samples grown by GS-MBE show only one, 10× weaker trap. The dark currents for both UHV-CVD and GS-MBE diodes exhibit an activation energy of Ea=0.40 eV at high temperature while the reverse bias leakage current in these films increases with increasing Sn content.
Virtual Substrate Technology for Ge1-XSnX Heteroepitaxy on Si Substrates
Authors: Kostecki Konrad , Oehme Michael , Koerner Roman , Widmann Daniel , Gollhofer Martin , Bechler Stefan , Mussler Gregor , Buca Dan , Kasper Erich , Schulze Joerg
Published: September 2014

Two new types of Ge1-XSnX virtual substrate (VS) with a Sn concentration of 2 % and 4 % were fabricated. The two types consist of a non-annealed directly on Si grown Ge1-XSnX VS and an annealed Ge1-XSnX VS on Ge VS. The complete layer structure is grown by means of ultra-low temperature molecular beam epitaxy (MBE) in order to suppress the Sn segregation. For an electrical and optical characterization, the VS technology is used to grow p-i-n photodetectors. The dark current characteristics show a higher dark current for Ge1-XSnX directly on Si, also the responsivity and the emission intensity are lower due to more dislocations.
Investigation on the Formation and Propagation of Defects in GeSn Thin Films
Authors: Mosleh Aboozar , Benamara Mourad , Ghetmiri Seyed Amir , Conley Benjamin R , Alher Murtadha Abdulmueen , Du Wei , Sun Greg , Soref Richard , Margetis Joe , Tolle John , Yu Shui-Qing , Naseem Hameed A
Published: September 2014

Defect formation and propagation in Ge1-xSnx/Ge thin films were investigated by using X-ray diffraction, transmission electron microscopy and scanning electron microscopy techniques. Samples with 0.9 to 7 % Sn mole fraction were deposited on a Si substrate with a Ge buffer layer using a chemical vapor deposition technique. The X-ray diffraction results show that the Ge1-xSnxfilms are 46-100 % compressively strained. Transmission electron microscopy images show that symmetrical and asymmetrical Lomer dislocations are formed at GeSn/Ge interface, which stops propagation of defects parallel to the growth direction. Average threading dislocation density (TDD) in the Ge buffer layer is measured to be 9.71×108 cm-2. Adding Sn to Ge made the Ge1-xSnx films to be more flexible, which traps 80 % of TDD propagating in Ge buffer layer. Reduction of TDD to 3×107cm-2 indicates achievement of higher quality of Ge1-xSnx film.
In Situ Studies of Germanium-Tin and Silicon-Germanium-Tin Thermal Stability
Authors: Fournier-Lupien Jean-Hughes , Chagnon Dany , Lévesque Pierre , AlMutairi AbdulAziz Awadh , Wirths Stephan , Pippel Eckhard , Mussler Gregor , Hartmann Jean-Michel , Mantl Siegfried , Buca Dan , Moutanabbir Oussama
Published: September 2014

Sn-containing group IV semiconductors provide a rich playground to independently engineer the band structure and lattice parameter with a potential impact of a variety of silicon-based electronic and optoelectronic devices. The introduction of these metastable alloys in device fabrication raises a number of concerns regarding the possible degradation of their composition and structural properties during different processing steps. With this perspective, in this work we present detailed in situ and ex situ investigations of the thermal behavior of both Sn-rich binary and ternary alloys. We used low energy electron microscopy and photoelectron emission electron microscopy to examine in real time the evolution of surface structure and composition during thermal annealing. These in situ studies are augmented using several ex situ characterization techniques. These investigations unraveled unprecedented details about the phase separation in these two systems. Particularly, in Ge0.84Si0.04Sn0.12 annealing above 410 °C leads to the formation of randomly distributed Sn-rich particles which grow as the annealing temperature increases. Additionally, the binary alloy Ge0.88Sn0.12 seems to be relatively more stable as compared to the ternary alloy with the same Sn content. The Sn-rich particles in the former system are not randomly distributed, but they are found to follow a well defined pattern on the surface along the <110> direction. The mechanisms and regimes involved in the phase separation are also briefly presented.
(Invited) The Thermoelectric Properties of Ge/SiGe Based Superlattices: from Materials to Energy Harvesting Modules
Authors: Samarelli Antonio , Ferre Llin Lourdes , Cecchi Stefano , Frigerio Jacopo , Etzelstorfer Tanja , Müller Gubler Elisabeth , Stangl Julian , Chrastina Daniel , Isella Giovanni , Paul Douglas
Published: September 2014

We report recent progresses in the characterization of the vertical electrical and thermal properties of multilayered silicon germanium (SiGe) materials for thermoelectric coolers and generators. Superlattice structures p- and n-type doped with different barriers and quantum well thicknesses were grown by Low Energy Plasma Enhanced Chemical Vapor Deposition. The electrical and thermal characterizations were performed using fully integrated metrology structures, microfabricated on the surface of the sample. Heaters, thermometers and electrical contacts were integrated onto the device to allow a simultaneous measurement of the electrical, thermal and Seebeck coefficient for the extraction of the figure of merit ZT. Enhancements in the Seebeck coefficient up to 450 µV/K and the reduction of the thermal conductivity down to 2.2 W/mK are mainly attributed to the low dimensionality of the system. Preliminary tests on microfabricated modules are performed on a non-optimized material and device dimensions as proof of concept for next generation devices.
Investigation of Growth Mechanism and Role of H2 in Very Low Temperature Si Epitaxy
Authors: Mosleh Aboozar , Ghetmiri Seyed Amir , Conley Benjamin R , Abu-Safe Husam Hamza , Benamara Mourad , Waqar Zafar , El-Ghazaly Samir , Yu Shui-Qing , Naseem Hameed A
Published: September 2014

High quality crystalline homoepitaxial silicon film has been deposited in single-step growth using ultra-high vacuum plasma-enhanced chemical vapor deposition at 250°C. An investigation on the effects of key growth parameters such as temperature, hydrogen dilution, and plasma power has led to achievement of balanced growth conditions. Material Characterization reveals that the defect-free growth is due to the dominant role hydrogen plays in enhancing surface diffusion over selective etching of the amorphous phase. Absence of crystal defects, such as dislocations or stacking faults, shows that single-step growth, results in extremely high quality growth at low temperatures.
Material Studies on Si:C Epitaxial Films Grown by CVD
Authors: Dhayalan Sathishkumar , Loo Roger , Rosseel Erik , Hikavyy Andriy Yakovitch , Shimura Yosuke , Nuytten Thomas , Richard Olivier , Bender Hugo , Douhard Bastien , Vandervorst Wilfried
Published: September 2014

We report the material properties of epitaxial Si:C in terms of layer defectivity and carbon substitutionality in view of its use as Source/Drain stressors for nMOSFET devices. Our discussion includes a comparison of disilane versus trisilane as Si precursor. The expected increase in defectivity with increasing carbon content is followed by an epitaxial breakdown (between 2.3% and 5% total C). The increase in defectivity is attributed to the formation of non-stoichiometric Si-C defect complexes. Raman spectroscopic studies revealed the presence of both random and ordered C distributions in the Si:C lattice. A correlation between these ordered distributions and defect structures is presented. The material properties are affected by both process conditions and the details of the process sequence. Typically, a single step deposition process results in a more ordered C structure while a cyclic deposition and etch (CDE) process results in a lower defectivity and an enhanced C substitutionality.
Progress in SiC MOSFET Reliability
Authors: Flicker Jack D. , Hughart David R. , Atcitty Stan , Kaplar Robert J. , Marinella Matthew
Published: September 2014

In this work, we have characterized a variety of SiC devices (first- and second-generation 1200 V SiC MOSFETs and 1200 V SiC JFETs) with regards to threshold voltage shifts and leakage currents at high temperatures under both static and dynamic gate bias stress conditions. It was found that, although the stability of SiC MOSFETs has increased dramatically from the first- to the second-generation due to an increase in the quality of the gate oxide layer, SiC JFET devices (which lack a gate oxide altogether) are much more stable with respect to ΔVT for both types of gate bias stresses at high temperatures. We have also characterized the interface trap density (DIT) in SiC MOSFETs based solely on changes in the sub-threshold slope of the devices’ I-V curves under elevated temperature and bias stress, and have produced ∆DIT profiles showing relative changes in interfacial defect concentration at energy levels referenced to the calculated surface potential at the threshold voltage. We have found that the defect density of second-generation SiC MOSFETs is almost an order of magnitude lower than similar first-generation devices from the same manufacturer, consistent with the decreased VT shifts seen in voltage/temperature stress experiments.
Characterization of Defects in SiC Substrates and Epilayers
Authors: Wang Huanhuan , Wu Fangzhen , Yang Yu , Guo Jianqiu , Raghothamachar B , Dudley Michael , Zhang Jie , Chung Gil , Thomas Berndt , Sanchez Edward K , Mueller Stephan , Hansen Darren , Loboda Mark
Published: September 2014

A review is presented of recent monochromatic and white beam synchrotron topography based studies of defects in SiC substrates and epilayers. The methodologies used in applying these techniques to gain understanding of the origins and evolution of the defect structures in PVT grown boules and CVD grown epilayers will be elucidated. In particular, criteria used in distinguishing grown-in defects from deformation induced defects will be discussed. Contrast observed from the various dislocations present in the crystals will be explained, and it will be shown how contrast simulation can be used to identify the detailed characteristics of the dislocations (for example, both Burgers vector sign and magnitude). Application of the various techniques to the complete analysis of the distribution, character and origins of grown-in c-axis screw dislocations (both hollow and closed-core), deformation induced basal plane dislocations, and grown-in threading edge dislocations will be discussed.
Novel Oxide Buffer for Scalable GaN-on-Silicon
Authors: Clark Andrew , Dargis Rytis , Arkun F. E. , Smith Robin S.
Published: September 2014

An alternative approach for growing GaN-on-Si using a hybrid epitaxial process, in which the rare-earth oxide buffer is first optimized with the template then used in a standard upstream MOCVD epitaxial process, is demonstrated. Using a rare earth oxide as the buffer layer the most obvious benefit is the spatial separation of the GaN from the silicon which removes one of the key breakdown paths. The oxide epitaxial process is robust and scalable to 200 mm diameter wafers. Combining oxides with different lattice spacings into ternary alloys enables the formation of graded and stacked layers starting from a lattice coincident material at the silicon surface to an upper surface that is now only 9% mismatched from GaN, as opposed to 17% for GaN on silicon. The suitability of the oxide within an MOCVD process has been demonstrated by the growth of bulk GaN using a standard sapphire like process.
Full Epitaxial Trench Type Buried Grid SiC JBS Diodes
Authors: Reshanov Sergey A. , Schöner Adolf , Kaplan Wlodek , Zhang Andy , Lim Jang-Kwon , Bakowski Mietek
Published: September 2014

The paper presents the advanced concept of fully epitaxial SiC junction barrier Schottky (JBS) diodes. It combines trench etching with embedded epitaxial re-growth and enables cost-efficient manufacturing. Fabricated devices are rated for 20A / 1200V and have leakage currents below 0.1µA at 1000V blocking voltage.
Flash-Lamp-Enhanced Atomic Layer Deposition of Thin Films
Authors: Henke Thomas , Knaut Martin , Hossbach Christoph , Geidel Marion , Rebohle Lars , Albert Matthias , Skorupa Wolfgang , Bartha Johann W.
Published: September 2014

Within this work flash lamp annealing (FLA) is utilized to thermally enhance the film growth in atomic layer deposition (ALD). First, the basic principles of flash-lamp-enhanced ALD (FEALD) are presented in detail, the technology is reviewed and classified. Thereafter, results of our studies on the FEALD of aluminum- and ruthenium-based thin films are presented. These depositions were realized by periodically flashing on a substrate during the precursor exposure. It is shown that the film growth is induced by the flash heating and that the processes exhibit typical ALD characteristics. The obtained relations between flash parameters and film growth parameters are discussed with the main focus on the impact of the FLA-caused temperature profile on the film growth. Besides, this work addresses technical challenges for the practical realization of this method and demonstrates the potential of this technology to extend the capabilities of thermal ALD.
Thin-film Deposition of Silicon Nitrides and Oxides from Trihydridosilanes
Authors: Arkles Barry , Pan Youlin , Kaloyeros Alain
Published: September 2014

Trihydridosilanes can provide a route for generating self-assembled monolayers on metal substrates. Under mild conditions, these precursors interact with a variety of clean, hydrogenated and fresh metal and metalloid surfaces, including titanium, silicon and gold. All classes of hydridosilanes have minimal interaction with anhydrous oxide surfaces. After initial deposition, SAMs formed from 2-chloroethyltrihydridosilanes may be converted to silicon nitride by pulsing with ammonia or silicon dioxide by pulsing water or oxygen. A proposed mechanism for the initial steps of deposition involves the dissociative adsorption of the silanes with the formation of hydrogen, followed by topmost atom layer insertion and concomitant surface reconstruction
Thinning the Active Layer of TFTs
Authors: Samb Mamadou Lamine , Dong HanPeng , Jacques Emmanuel , Sissoko Gregoire , Seidou Maiga Ahmadou , Mohammed-Brahim Tayeb
Published: September 2014

The effect of thinning the active layer of TFTs on their performance is studied. Experimentally, through the study of microcrystalline silicon TFTs, the beneficial effect of thinning the active layer is highlighted through the behavior of the subthreshold slope and of the off-current. Simulation results, using Silvaco tools, show that the beneficial effect is mainly due to the high increase of the lateral electrical field between source, channel and drain
Fabricating High-Performance Silicon Thin-Film Transistor by Meniscus Force Mediated Layer Transfer Technique
Authors: Sakaike Kohei , Akazawa Muneki , Nakagawa Akitoshi , Higashi Seiichiro
Published: September 2014

Single-crystalline Si (c-Si) thin-film-transistors (TFTs) were formed at a low temperature (150°C or less) on plastics by meniscus force mediated layer transfer technique. A c-Si layer supported by SiO2 columns on a starting Si-on-insulator (SOI) wafer and a counter polyethylene terephthalate (PET) substrate were placed in close face-to-face contact, and pure water was sandwiched in between the c-Si layer and the PET substrate. The samples formed in this manner were heated on a hot plate at 80°C, and the SOI layer is transferred to PET by the meniscus forces. By applying the proposed transferred technique, high performance c-Si TFT were successfully fabricated on the PET substrate, which showed a field-effect mobility as high as 343 cm2 V-1s-1.
Effect of Grain Growth Control by Atmospheric Micro-Thermal- Plasma-Jet Crystallization of Amorphous Silicon Strips on TFT Characteristics
Authors: Morisaki Seiji , Hayashi Shohei , Yamamoto Shogo , Nakatani Taichi , Higashi Seiichiro
Published: September 2014

High performance thin film transistors (TFTs) are fabricated on quarts substrate based on zone-melting-recrystallization (ZMR) of amorphous silicon (a-Si) strips induced by micro-thermal-plasma- jet (µ-TPJ) irradiation. The grain boundaries (GBs) in strip pattern were almost excluded and most of the strips consist of ∑3 coincidence site lattices (CSLs) or in some cases single grains. Strip pattern was quite effective even in the case of short channel TFTs. N- and p-channel TFTs with typical field effect mobility (µFE
) of 380 and 140 cm2/Vs, respectively, are successfully fabricated with significantly reduced characteristics variability. These high µFE
and low variation of threshold voltage (Vth
) by strip pattern showed significantly stable output characteristics regardless of the size of TFTs.
Drain Bias Effect on the Instability of Amorphous InGaZnO Thin-Film Transistors under Negative Gate Bias and Illumination Stress
Authors: Wang Dapeng , Hung Mai Phi , Jiang Jingxin , Toda Tatsuya , Furuta Mamoru
Published: September 2014

The effect of drain bias (V
DS) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO (a-IGZO) thin-film transistors was investigated using a double-sweeping gate voltage (V
GS) mode. The variation in the transfer characteristics was explored using current–voltage and capacitance–voltage characteristics. In the initial stage (<1000 s) of NBIS with V
DS of 40, 0, and −20 V (V
GS = −40 V and V
DS > V
GS), the transfer characteristics shifted negatively with an insignificant change in the subthreshold swing (SS) due to hole trapping at an IGZO/gate insulator interface. In the subsequent stage (>1000 s), on-current degradation was observed and was accelerated in the forward measurement as the NBIS duration increased. The enhanced and weakened degradations were respectively observed by applying V
DS of 40 and −20 V compared with grounded V
DS. The transfer curves in the reverse measurement shifted positively without on-current and SS degradations, which were well described by the stretched-exponential equation. Furthermore, it was confirmed that the NBIS degradations could be suppressed by applying a large negative V
DS bias of V
DS < V
GS (V
GS = −40 V and V
DS = −60 V) during NBIS.
The Role of Passivation Layer during Thermal Annealing for Oxide Semiconductor Thin Films
Authors: Hwang Chi-Sun , Park Sang-Hee Ko , Cho Sung-Heang , Ryu Min Ki , Oh Himchan , Lee Su Jae , Yang Jong-Heon , Byun Chunwon , Park Jonghyurk , Cho Kyung Ik , Chu Hye Yong
Published: September 2014

The change of the resistance of active films during thermal annealing was monitored under the split of passivation layers and active layers. ALD deposited Al2O3 layer and PECVD deposited SiO2 layer were applied for the passivation layer and sputter deposited Al-doped InZnSnO and InGaZnO were applied for the active layer. It is found that Al2O3 passivation layer supplies dopants to the active interface during high temperature annealing and the side wall of Al:IZTO pattern contains many defects, which become conductive during high temperature annealing through detailed measurement of resistance of patterned oxide semiconductor thin films with various sizes. It is suggested that PECVD deposited SiO2 layer with proper pre-treatment (possibly N2O plasma treatment) will be best candidate for the passivation layer in the oxide TFTs, especially in the case of oxide TFTs with high mobility.
(Invited) Contact Effects in Organic Thin Film Transistors with Different Device Structures
Authors: Mariucci Luigi , Rapisarda Matteo , Valletta Antonio , Calvi Sabrina , Benwadih Mohammed , Coppard Romain , Fortunato Guglielmo
Published: September 2014

In this work we discuss the contacts effects in organic transistors with different architectures (staggered and coplanar). By using electrical measurements, performed at different temperatures, and numerical simulations, we show that electrical characteristics of both types of devices can be reproduced considering an effective Schottky barrier and barrier lowering at the source contact. Furthermore, we show that in staggered devices, at low Vds, the current is injected along an extended source contact region, while at high Vds is mainly injected at the edge of the contact, as for coplanar devices. The different architecture also results in different voltage drop at the contact for different drain bias. These differences explain the different contact resistance observed for the two device architectures.
(Invited) Crystalline Oxide Semiconductor Using CAAC-IGZO and its Application
Authors: Yamazaki Shunpei
Published: September 2014

It is revealed that c-axis aligned crystal In-Ga-Zn oxide(CAAC-IGZO) and nanocrystalline IGZO films are suitable for practical use due to their high-density crystalline morphologies and stability under electron beam irradiation in transmission electron microscope observation. We attempted to reproduce an amorphous IGZO film with no ordering. However, we found nanocrystals in the film and this film has low density and is soft, so that it is an unstable material in which crystals grow when subjected to electron beam irradiation in TEM observation. We fabricated field-effect transistors using CAAC-IGZO and examined their switching characteristics. As a result of microfabrication scaling, cutoff frequencies of 2 GHz and 1.5 GHz were obtained when the channel lengths were 60 nm and 100 nm, respectively. This opens new possibilities for oxide semiconductor large-scale integration.
(Invited) Nano-Crystalline Oxide Semiconductor Materials for Display and Semiconductor Device Applications
Authors: Jeon Sanghun
Published: September 2014

Nano-crystalline oxide semiconductor devices offer an attractive alternative to the traditional display technology, enabling to realize high resolution, high motion speed and large area interactive display products with remote touch functionality and transparent electronics. Also it provides the novel device approaches over traditional down-scaling methods employed in ultra large scale integration. Here, we present various semiconductor and display device applications by using nano-crystalline oxide semiconductor materials.
(Invited) Growth of Czochralski Silicon Crystals with Ultralow Carbon Concentrations for High-Power Insulated-Gate Bipolar Transistor Devices
Authors: Nagai Yuta , Nakagawa Satoko , Higasa Mitsuo , Kashima Kazuhiko
Published: September 2014

The effects of the argon gas flow in a Czochralski (CZ) silicon growth furnace and the evaporation of carbon monoxide (CO) from the silicon melt on the carbon concentration in 8-inch CZ silicon crystals were studied by evaluating the carbon concentrations in the crystals using photoluminescence spectroscopy. Preventing silicon monoxide from flowing through the side of the heater and the graphite susceptor and preventing back-diffusion of CO from the top of the graphite susceptor effectively reduced carbon contamination during CZ silicon growth. In addition, CO was evaporated from the melt by increasing the gas flow rate above the melt surface. Owing to the effects of CO evaporation from the melt, 8-inch CZ silicon crystals were grown with a carbon concentration considerably lower than that in floating-zone silicon.
Highly Sensitive and Accurate Infrared Absorption Measurement of Carbon Concentration in Si Crystal
Authors: Inoue Naohisa , Watanabe Kaori , Seki Hirofumi , Uno Hiroyuki , Oyama Hidenori , Kawamura Yuichi
Published: September 2014

Infrared absorption (IR) measurement of carbon concentration ([C]) in silicon crystal around 1015 cm-3 was examined. Measurement of 605 cm-1 absorption was difficult due to the overlapping double phonon peak. Absorption of CiOi complexes at 862 cm-1 induced by electron irradiation was a good measure of [C] below 1015 cm-3. Also, electron irradiation was successfully utilized to reduce the substitutional carbon concentration in the reference sample by nearly one order of magnitude. Second harmonic vibrational mode at 1206 cm-1 was observed in samples with [C] down to 1016 cm-3. One mm thick samples and commercial wafers can be measured. Charged particle activation analysis was applied to samples with [C] around 1015 cm-3 and evaluated by IR.
(Invited) Modeling of Oxygen Precipitation in Silicon
Authors: Dunham Scott T. , Trzynadlowski Bart C.
Published: September 2014

A model for the precipitation of oxygen and associated dislocation loops in Czochralski-grown silicon is presented. Beginning with kinetic rate equations describing the growth and dissolution of oxide precipitates, a reduced model based on the moments of the precipitate size distribution is developed and validated against experimental data. Comparisons with the full, rate equation-based model show that the reduced version is comparably accurate while requiring significantly less computational power. The formation of dislocation loops due to silicon interstitial ejection during precipitate growth is modeled using a simple, moment-based approach.
Precipitation Behaviors of Rapid Thermal Annealing Treated Silicon Wafers under Various Thermal Cycles
Authors: Lee DongMyun , Kim TaeHyeong , Park SoonSung , Kim TaeHoon , Lee YongHyun , Park EunSik , Yeo Hwankug , Falster Robert
Published: September 2014

A “2-step Rapid Thermal Annealing (RTA)” treatment in NH3 and Ar gas is capable of producing a high density (6-8x109/cm3) of precipitates in a remarkably uniform profile in the 300mm silicon wafers, independently of thermal cycle, oxygen content and pre-thermal history. The profile sharply transitions from a shallow denuded zone to the fixed and uniform density in the bulk. Such a feature would guarantee a sufficient amount of gettering sinks to be retained in the extremely thinned wafers. The shape of the depth profile evolves in proportion to the thermal budget, following well the model of VO2 nucleation and growth reported previously.