bluuebunny/crossref_metadata_2025 huggingface dataset:
Nanomechanical Analysis of Polydimethylglutarimide Based Lift Off Resist Used for Temporary Bonding and Film Transfers
Authors: Mohammed Yousuf , Matsumae Takashi , Koehler Andrew D. , Suga Tadatomo , Baumgart Helmut , Hobart Karl D , Elmustafa A A
Published: September 2016

Six samples of polydimethylglutarimide based lift off resist (LOR) were prepared with combinations of two film thicknesses and three prebake temperatures. The LOR thicknesses are 500 nm and 1000 nm and the prebake temperatures are 80ºC, 105ºC, 150ºC. The nanomechanical properties were measured using nanoindentation to determine the modulus and hardness of the six samples. The experiment retained useful information regarding the effects of film thickness and prebake temperatures on the hardness and modulus of the LOR. It was found that the hardness increases as the film thickness decreases and hardness also increases as the prebake temperature increases.
Thin Layer Transfer Using Room Temperature Wafer-Level Bonding Process
Authors: Abadie Karine , Fournel Frank , Morales Christophe , Moriceau Hubert , Wimplinger Markus
Published: September 2016

This article deals with the transfer of a thin Si film (100nm) on top of a Si substrate using a room temperature covalent bonding. No annealing is performed post direct bonding. Before to detail this process, the equipment used for the bonding process is characterized in terms of particle and metal contamination. The etching occurring during one of the sub process of the surface preparation is also studied. Characterizations performed after layer transfer are presented. They include C-SAM inspections, SP2-HAZE measurements and TEM.
Decreased Surface Porosity and Roughness of InP for Epitaxially Grown Thin-Film Devices: A Path to Integration of High Performance Electronics
Authors: Gervasoni Michael , Machness Ariella , Goorsky Mark
Published: September 2016

Devices based on III-V semiconductors have generated widespread interest due to their superior performance over conventional semiconductors. However, III-Vs are inhibited from mass commercialization because of high costs. Thus, there is a motivation to develop affordable, high-quality thin film III-V devices, which has been realized through exfoliation techniques. In this work, a porous InP structure with optimal morphology was fabricated for exfoliation. A relationship between surface porosity and current density was determined for obtaining a desirable porous structure. Surface porosities as low as 0.02% were achieved, and it was found that reducing the porosity lowered the surface roughness. Thus, porous layers with surface roughness approaching polished InP were demonstrated. The porosities and surface roughness obtained are lower than previously reported and more ideal for growing a low-defect epitaxial film. By growing higher quality epitaxial films on a reusable seed wafer, high performance and cost effective III-V devices are made possible.
Wafer-Level Hermetic Seal Bonding at Low-Temperature with Sub-Micron Gold Particle Using Stencil Printing
Authors: Ishida Hiroyuki , Ogashiwa Toshinori
Published: September 2016

Wafer-level low-temperature hermetic seal bonding has been successfully demonstrated using sub-micron-size gold particles (0.3 μm mean diameter) with adopting a narrow-width rim structure to reduce the required total bonding force down to the range available on commercial wafer bonders. Conventional stencil printing combined with a newly developed suspended metal mask was employed as a cost-effective fabrication method to form sealing lines over the rim structure. Au-Au thermo-compression bonding using 10 μm-wide rim structure was performed at 200°C for 30 minutes with the bonding pressure of 200 MPa. An excellent hermeticity was achieved and the encapsulated pressure inside the sealed cavity was estimated to be around 100 Pa.
Aluminum-Germanium Eutectic Bonding for MEMS: Behaviour and Solidification of Liquid Al-Ge on Different Substrates
Authors: Lumineau Victor , Fournel Frank , Imbert Bruno , Hodaj Fiqiri
Published: September 2016

In this paper we study the formation and behaviour of liquid Al-Ge alloy, its solidification, the resulting microstructures and the appearance of voids in bonded structure for MEMS packaging. The underneath layer influences the wettability of liquid Al-Ge as well as its solidification which can lead to undesirable Al dendrites. Each underneath layer imposes a critical value for the cooling rate above which dendrites are likely to appear. Blanket and patterned Al/Ge deposited wafers are bonded together with process parameters optimized thanks to previous results. The interfaces present a dendritic-free eutectic structure. Micro-voids are observed at the interfaces between Al and Ge phases. The Kirkendall effect and thermal stresses are two possible reasons for voiding phenomenon.
Surface Protection for Semiconductor Direct Bonding
Authors: Knechtel Roy , Klingner Holger
Published: September 2016

Semiconductor direct wafer bonding is a widely used process for fabricating 3-dimensional structures, especially engineered substrates such as SOI wafers or cavity wafers with and without insulating layers at the bonding interface. The investigations described here concern cavity SOI wafers without insulating layers, as used for discrete and integrated pressure sensors. Semiconductor direct bonding is the initial bonding by mechanical contacting of high-quality surfaces activated by wet chemical and/or plasma treatments, followed by thermal annealing at temperatures and times related to the chosen activation. This ultimately results in a very strong mechanical bond, which can survive all of the subsequent process steps, such as those needed to process MEMS pressure sensors. The requirement for the direct bonding is that the wafers to be bonded have a very high quality; this means very low roughness, low waviness and no surface residues or contamination. In this paper, the focus is on roughness in relation to the bonding process and process integration.
High Efficiency Cleaning Processes for Direct Wafer Bonding
Authors: Dussault Donald , Rothballer Jan , Kurz Florian , Reichardt Make , Dragoi Viorel
Published: September 2016

Substrate cleaning is a very important process step in direct wafer bonding. Current work describes development, testing and verification of a single wafer megasonic cleaning method utilizing a transducer design that meets the extreme particle neutrality, Particle Removal Efficiency (PRE), and repeatability requirements of production scale wafer bonding and other applications requiring extremely low particle levels. The results were obtained using 300 mm diameter Si wafer which were processed as received, without any wet bench cleaning process. These experiments simulated real case production scenario in which the particle counts on incoming wafers are typically 0.1 LPD/cm2 and lower.
(Invited) Present and Future of LTPS Technology
Authors: Kaneko Toshiki , Nakamura Takashi , Kimura Hiroyuki
Published: September 2016

The Low temperature poly-silicon (LTPS) is suitable backplane technology for the high resolution TFT LCD displays to smartphone applications. We have applied the LTPS technology for the new targets, an 8 inch 2K4K TFT LCD display with 30Hz frame rate driving and a 17.3inch 8K4K TFT LCD with 120Hz frame rate driving. Both developed displays having the shrinkage of channel width together with the thinner insulator for storage capacitor, provides high display quality in terms of vertical crosstalk and flicker. Precise fabrication processes at 1.5 mm level enables the shrinkage and the reduction of off current.
(Invited) Microcrystalline Silicon Based TFTs and Resistors for Reliable Flexible Electronics
Authors: Kervran Yannick , Kandoussi Khalid , Dong Hanpeng , Janfaoui Sabri , Coulon Nathalie , Simon Claude , Jacques Emmanuel , Mohammed-Brahim Tayeb
Published: September 2016

Silicon based flexible electronics is shown here as the right way when considering the reproducibility of the process and the long-term reliability, the only way leading to commercially available products. Microcrystalline silicon films are deposited directly on plastic substrates (PEN and Polyimide) at low temperature. Films are highly crystallized. Crystalline volume is higher than 73% for 50nm thick film as calculated from Raman spectra. Resistances and TFTs based on such silicon film are bent at lower radius than 1 mm without breaking. More than 200 times of such extreme bending are done without changing the TFT’s characteristics
Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating
Authors: Hong Won-Eui , Ro Jae-Sang
Published: September 2016

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films was conducted by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. The phase-transformation phenomena during the JIC process were detected electrically and optically by the in-situ measurements of input voltage/current and normal reflectance at wavelength of 532 nm. We devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. JIC-processed poly-Si thin-film transistors were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.
(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization
Authors: Hara Akito , Ohsawa Hiroki
Published: September 2016

To integrate circuits on a glass substrate, high-performance and low-power-dissipation low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable. Fabrication of high-quality poly-Si film is one approach to enhance the on-current of LT poly-Si TFTs on a glass substrate. In this paper, we used continuous-wave laser lateral crystallization (CLC) to fabricate high-quality lateral large-grained poly-Si films on a glass substrate. To achieve low power dissipation, threshold voltage (Vth) control technology is one tentative approach. To control the Vth of LT poly-Si TFTs, we fabricated four-terminal (4T) self-aligned embedded metal double-gate (E-MeDG) LT poly-Si TFTs using high-quality CLC poly-Si films. The 4T self-aligned E-MeDG CLC LT poly-Si TFTs showed excellent Vth controllability. By exploiting the high controllability of the 4T TFTs, E/D inverter and extended gate pH sensor were fabricated and successful operation with high performance was confirmed.
Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization
Authors: Nguyen Thuy Thi , Hiraiwa Mitsuhisa , Hirata Tatsuaki , Kuroki Shin-Ichiro
Published: September 2016

Low-temperature poly-Si thin film transistors with high mobility and uniformity have been required for high resolution flat panel display (FPD) technology. In this work, we succeeded in controlling orientation of poly-Si film by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping and (100)-dominantly oriented poly-Si film was realized. Si crystal grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The adjacent Si crystal grains had almost identical orientation in the space with misorientation angle of under 15o. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. Moreover, device characteristics of the fabricated TFTs were investigated and mobility variation was evaluated.
Design of Bi-Directional Transmission Gate Driver in Amorphous Silicon Technology for TFT-LCD Application
Authors: Zheng Guang-Ting , Liu Po-Tsun , Wu Meng-Chyi , Lu i-Hsiang
Published: September 2016

A novel bi-directional transmission gate driver circuit integrated by amorphous silicon thin film transistors (a-Si:H TFTs) has been proposed. In the proposed design, the noise suppression structure of the gate driver utilized the AC drive inverter to reduce the degradation of the pull down TFTs. The clock frequency of AC signal is 30 Hz, which could reduce dynamic power consumption of the circuit. In addition, the synchronous controlled method in this research could reduce the amount of device in gate driver.The simulated result shows the good output performance of the gate driver and match the circuit design.
Cooling Rate Dependent High Substitutional Sn Concentration (>10%) in GeSn Crystals on Insulator by Pulsed Laser-Annealing
Authors: Moto Kenta , Matsumura Ryo , Sadoh Taizoh , Ikenoue Hiroshi , Miyao Masanobu
Published: September 2016

Crystallization of Ge1-xSnx (0.1≤x≤0.2) on quartz substrate by pulsed laser annealing was investigated. Substitutional Sn concentration increase with decreasing pulse number. As a result, GeSn crystals with very high substitutional Sn concentration (~12%) has been realized for the sample (initial Sn concentration: 15%) with a single shot. These results were attributed to the non-thermal equilibrium growth with higher cooling rate by decreasing pulse number. This technique is expected for application to high-speed thin-film-transistors and high-efficiency optical devices.
Inkjet-Printed Oxide TFTs with Solution-Processed Dual Semiconductors
Authors: Lee Seung-Hyun , Kwack Young-Jin , Lee Jun Seok , Choi Woon-Seop
Published: September 2016

To achieve the optimized electrical properties of an inkjet-printed double-active layer, the ZTO TFTs with various compositions of In2O3 solutions were examined. By controlling the annealing temperature and indium content, heterostructured In2O3/ZTO TFTs with improved mobility, threshold voltage and bias stability were obtained. The best electrical properties of the inkjet-printed double-active layer ZTO TFTs were obtained with 0.01 M of In2O3: a mobility of 8.6 cm2/ V s, a threshold voltage of 2.76 V, a subthreshold slope of 0.52 V/dec, and an on-to-off current ratio of 106. The electrical properties of the inkjet-printed double-active layer oxide TFTs were superior to those of the single-active layered TFTs.
Prospectively of Carbon-Doped Indium-Tungsten-Oxide Channel TFT for Bias Stress Instability
Authors: Kurishima Kazunori , Nabatame Toshihide , Kizu Takio , Mitoma Nobuhiko , Tsukagoshi Kazuhito , Sawada Tomomi , Ohi Akihiko , Yamamoto Ippei , Ohishi Tomoji , Chikyow Toyohiro , Ogura Atsushi
Published: September 2016

We studied characteristic of carbon-doped indium-tungsten-oxide (In1-xWxOC) thin film transistors (TFTs) with SiO2 gate insulator. The In1-xWxOC films, were fabricated by co-sputtering method with WC and In2O3 targets, had an amorphous structure and maintained W-C bond even after annealing at 300 °C. The saturation field-effect mobility, on/off current ratio and subthreshold swing values of the In0.96W0.04OC TFT were 5.6 cm2/Vs, 1.0 × 109 and 0.52 V/decade, respectively. To effect of doped carbon in In1-xWxOC channel on reliability of transistor properties, we compared the turn on voltage shift (ΔV
on) behavior between the In0.96W0.04OC and In0.98W0.02O TFTs under positive gate bias stress (PBS) and negative gate bias stress (NBS). The ΔV
on of the In0.96W0.04OC TFT was always smaller than that of In0.98W0.02O TFT under PBS. Moreover, it is clear that the ΔV
on (~ 0 V) of In0.96W0.04OC TFT was improved significantly compared to that (-0.5 V) of In0.98W0.02O TFT under the NBS of 5000 s. We concluded that the In1-xWxOC film is one of the promising candidates as InOx-based metal oxide semiconductor channel material.
Improvement of Stress Stability in Back Channel Etch-Type Thin Film Transistors with Post Process Annealing
Authors: Ochi Mototaka , Hino Aya , Goto Hiroshi , Hayashi Kazushi , Kugimiya Toshihiro
Published: September 2016

The chemical states and electronic structures near the back channel surfaces of amorphous In-Ga-Zn-O (a-IGZO) thin films were investigated by means of x-ray photoelectron spectroscopy (XPS) and photoinduced transient spectroscopy (PITS). The XPS analysis revealed that, due to source/drain (S/D) wet-etching, sub-gap states formed continuously near the valence band, which induced the degradation of the TFT characteristics. According to the PITS analysis, an increase in the hydrogen-related traps in a-IGZO thin films was clearly observed after the S/D wet-etching. The XPS spectra suggested that an increase in OH bonds at the back channel surface resulted in an improvement of stress stabilities such as negative bias, thermal and illumination stress environment.
(Invited) The Compact Models and Parameter Extraction for Thin Film Transistors
Authors: Shur Michael
Published: September 2016

The compact Thin Film Transistor (TFT) models should be suitable for the device characterization and parameter extraction and should account for the non-ideal effects including mobility dependence on the gate bias, self- heating, and effects of the series resistances and capacitances. The kink effects might become important in short channel devices. The unified and universal charge control models describe both the above and below threshold characteristics with one generalized charge control equation, have a good convergence and use a relatively small number of parameters. These models have been augmented with the contact models and AC transmission line models that account for the RC constants represented by the fractions of the channel resistances in series with the gate-to-channel distributive capacitances for reproducing the frequency dispersion. The non-linear properties of the TFT contacts have to be modeled. Such compact TFT models have been implemented in circuit simulators but they need further improvements with the emergence of new TFT materials systems.
(Invited) Stability under Gate Bias Stressing of Amorphous Oxide Thin Film Transistors
Authors: Niang Kham Man , Flewitt Andrew J.
Published: September 2016

Stability of amorphous zinc tin oxide thin film transistors (TFTs) is investigated under positive bias stressing (PBS) at temperatures between 65 and 105 °C. The time and temperature dependence of the threshold voltage shift is analyzed using a thermalization energy concept. A maximum energy barrier to defect migration of 0.76 eV and the attempt-to-escape frequency of 107 s–1 are extracted. These values are compared with those under PBS of amorphous indium gallium zinc oxide and hydrogenated amorphous silicon TFTs. The oxygen vacancy migration model that was proposed for amorphous oxide semiconductors is contrasted with the defect creation model that was proposed for amorphous silicon.
Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability
Authors: Mudgal Tarun , Edwards Nicholas , Ganesh Prashant , Bharadwaj Anish , Powell Eli , Pierce Michael S , Manley Robert G. , Hirschman Karl D
Published: September 2016

This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance. Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Device operation and response to applied bias-stress of all three gate electrode configurations will be compared, with reference to TCAD simulations that utilize common bulk and interface defect models. Electrical measurements and TCAD simulations are also used to develop a hypothesis on the origin of non-ideal behavior observed on scaled devices, which can be addressed by appropriate gate electrode option.
Thermoelectric Devices Fabricated Using Amorphous Indium Gallium Zinc Oxide
Authors: Fujimoto Yuta , Uenuma Mutsunori , Ishikawa Yasuaki , Uraoka Yukiharu
Published: September 2016

Thermoelectric property of amorphous InGaZnO (a-IGZO) thin film was optimized by adjusting the carrier concentration. The a-IGZO films were produced under various oxygen flow ratios. The Seebeck coefficient and the electrical conductivity were measured from 100 to 400 K. We found that the power factor (PF) at 300 K had a maximum value of 82 × 10−6 W/mK2, where the carrier density was 7.7 × 1019 cm−3. Moreover, the obtained data was analyzed by fitting the percolation model. Theoretical analysis revealed that the Fermi level was located approximately above the potential barrier when the PF became maximal.
A Current Supply with Single Organic Thin-Film Transistor for Charging Supercapacitors
Authors: Keshmiri Vahid , Larsen Christian , Edman Ludvig , Forchheimer Robert , Tu Deyu
Published: September 2016

We present a current supply, comprising a single organic thin-film transistor (OTFT), for the charging of supercapacitors. The current supply takes power from the electric grid (115 V AC, US standard), converts the AC voltage to a quasi-constant DC current (~0.1 mA) regardless of the impedance of the load, and charges the supercapacitor. Solution-processed OTFTs based on the popular polymeric semiconductor poly(3-hexylthiophene-2,5-diyl) have been developed to rectify the 115 V AC voltage. A diode-configured OTFT was used as a half-wave rectifier. The single OTFT current supply was demonstrated to charge a 220 mF supercapacitor to 1 V directly using 115 V AC voltage as the input. This work paves the road towards all-printable supercapacitor energy-storage systems with integrated chargers, which enable direct charging from a power outlet.
High-Performance Flexible Hybrid Photosensor Circuits Made by Low-Temperature Solution Processed Metal-Oxide and Organic TFTs
Authors: Kim Jaehyun , Kim Jaekyun , Kang Jingu , Kim Myung-Gil , Kim Yong-Hoon , Park Sung Kyu
Published: September 2016

Low-temperature solution-processed semiconductors including organic and oxide materials represent a promising platform enabling low-cost fabrication of flexible devices. We believe that heterogeneous integration of these materials in a synergetic way opens new routes toward multi-functional flexible system. Here, we demonstrated monolithically integrated oxide-organic semiconductor hybrid photo-sensor array on a flexible film in which the optical response of 2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene (diF-TESADT) organic material is transferred to InGaZnO thin film transistors for signal amplification.
Formation of ZnO Nanoparticles by Atomic Layer Deposition for the Nonvolatile Memory Thin-Film Transistor Applications
Authors: Seo Gi-Ho , Yun Da-Jeong , Lee Won-Ho , Kim So-Jung , Yoon Sung-Min
Published: September 2016

A low-temperature atomic-layer-deposition (ALD) process for the formation of ZnO nanoparticles (NPs) was demonstrated, in which the ALD temperature and cycles for diethylzinc precursor were controlled to be 160 oC and 20 cycles. The size and areal density of ZnO NPs were confirmed to be approximately 33 nm and 3×109 cm-2, respectively. Nonvolatile memory thin-film transistors were fabricated by employing the ZnO NPs as charge-trap centers for memory operations. The memory window was found to increase from 0.6 to 17.8 V with increasing the ALD cycles from 5 to 20. On- and off-program operations were also confirmed even with voltage pulses as short as 1 µs.
(Invited) Transparent Top Gate Oxide TFT with ITO/Ag/ITO Low Resistance Electrode for the Application to the High Speed Operation Fingerprint Sensor Array in the Touch Panel
Authors: Kim Yujin , Jeon Guk-Jin , Lee Myung Keun , Lee Seung Hee , Park Sang-Hee Ko
Published: September 2016

Oxide thin film transistor (TFT) and low-resistance electrode are necessary to manufacture transparent and high resolution fingerprint sensor for application to touch panel display. We adopted ITO/Ag/ITO triple layered stack as an electrode according to that inserting thin Ag layer between both sides of ITO layers definitely helps resistance decreases. Through simulation and optimization, we have chosen each thickness of three layers for optimal transmittance and sheet resistance, and developed dry etching conditions. Top gate structured IGZO TFT with triple layered S/D electrode showed outstanding electrical performance and is expected to be applied to transparent display panel.
(Invited) Physical Properties of Novel 2D Semimetal WTe2: From Microscopic Study to Devices
Authors: Pan Minghu , Yuan Hui
Published: September 2016

An increasing number of alternative two-dimensional (2D) materials are being explored in the “post-graphene age”, such as transition metal dichalcogenides (TMDs), silicene, and germanene. In this study, multiple measurements, including scanning tunneling microscopy (STM), electrical transport and Raman spectroscopy are performed on freshly cleaved surfaces of semimetallic tungsten ditelluride (WTe2) crystals. High sample quality with very low density of defects is confirmed by STM observation and four Fermi pockets can be revealed by Shubnikov–de Haas (SdH) oscillations based on transport measurement. Furthermore, we investigate Raman spectroscopy of thin-layer WTe2. Our results reveal that few-layer WTe2 could be an ideal candidate for future 2D electronic, optoelectronic devices.
(Invited) Nanowire Electrodes for Electrochemical Capacitors and Nanoparticles for Current Conduction
Authors: Nakanishi Hideyuki , Kikuta Ikuo , Kawabata Yuto , Matsumoto Ikuko , Naitoh Yasuaki , Segawa Hiroyo , Norisuye Tomohisa , Tran-Cong-Miyata Qui
Published: September 2016

Performance of supercapacitors is often influenced by their internal resistance since it causes unfavorable effects such as energy dissipation and delay of charge transport during charging/discharging. In the present study, we prepared monolithic metal nanowire array electrodes in aiming at suppressing the internal resistance of supercapacitors, and examined the influence of the defect structures present in the nanowire array electrodes. Performance of the supercapacitors was investigated by using galvanostatic charge/discharge measurement, cyclic voltammetry, and electrochemical impedance spectroscopy.
Electron Transport Behavior Analysis of Bis(terpyridine) Metal Complex Wires on Electrodes
Authors: Maeda Hiroaki , Sakamoto Ryota , Nishihara Hiroshi
Published: September 2016

Bis(terpyridine)iron(II) complex (Fe(tpy)2) wires terminated with redox active molecules were sequentially constructed on gold and hydrogen-terminated silicon electrodes. Potential-step chronoamperometry (PSCA) and electrochemical impedance spectroscopy (EIS) were performed to study the electron transfer of ferrocene-Fe(tpy)2 arrays on gold surfaces. The obtained Tafel plots and impedance spectra revealed greater first-order electron transfer rate constant than a ferrocene-terminated alkanethiol self-assembled monolayer and parameters contributing the smooth electron transport. On silicon electrodes, ferrocene-terminated Fe(tpy)2 wires showed slow electron transport between the ferrocene and the electrode while triarylamine-terminated Fe(tpy)2 wires displayed rapid electron transport. The difference of electron transport behaviors was discussed based on the band structure of silicon electrode and the HOMO level of terminal redox units.
(Invited) Gold Nanobridge Enhanced Fiber Optic Sensor
Authors: Floyd Adam , Scott Brian , Song Yunbin , Fraser Michael , Yu Zhihao , Wang Anbo , Pickrell Gary
Published: September 2016

We report a method for improving the transmission of a porous capillary tube waveguide gas sensor by applying a thin metallic coating to the inside surface. Using commercially available electroless gold plating solutions and a simple pressure setup, gold thin films were plated on the inner diameter surface of the capillary tube. Nano-porous gold coating was produced during the leaching process used to make the phase separated glass tube porous. Transmission spectra were characterized and determined that to the porous gold coating on the porous glass contributed to signal improvement. Detection of acetylene gas was accomplished but at higher concentrations than uncoated porous capillary tube waveguide. Detection limitations were attributed to lower transmitted power due to optical alignment difficulties.
Fluorescence Microscopy Characterization of Patterned Nano-Crystalline Quantum Dot Films
Authors: Sabeeh Ala , Price Jared , Ruzyllo Jerzy
Published: September 2016

This experiment is a continuation of the study concerned with the lift-off based patterning of nanocrystaline quantum dot (NQD) films. The NQD films patterned by lift-off process are analyzed by means of fluorescence microscopy to obtain information about film uniformity, pattern definition accuracy, and average fluorescence intensity. The lift-off process is implemented using wet (acetone immersion) and dry (oxygen plasma) photoresist removing ambient. Methods under investigation were found to perform similarly in terms of pattern resolution accuracy. However, in terms of the uniformity of fluorescence intensity distribution, acetone dissolution of photoresist was found to produce better results.
Controlling the Temporal Pulse Shape of the Passively Q-Switched Laser by Nonlinear Feedback Control
Authors: Thitsa Makhin , Rice Zechariah , Nve-Nsi Marcos , Xue Xiaojie
Published: September 2016

The design of a nonlinear controller that automatically adjusts the pump rate of the Q-switched laser to allow for customizing the temporal pulse shape of the laser output is proposed. The design is based on a method called feedback linearization, which is a well established technique in nonlinear dynamical system theory. It is demonstrated that such a nonlinear dynamical system can be transformed into a chain of two integrators by applying state feedback. Thus the desired output pulse shape is produced by applying its second derivative to the controller input. The design is verified by simulating the closed loop device in MATLAB Simulink.
(Invited) Current Topics in Electronic Devices Based on Wide Band-Gap Semiconductors for Power Applications and Energy Efficiency
Authors: Carlson Eric P , Kizilyalli Isik C. , Heidel Timothy D , Cunningham Daniel W
Published: September 2016

Wide-bandgap power semiconductor devices offer enormous energy efficiency gains in a wide range of potential applications. As silicon-based semiconductors are fast approaching their performance limits for high power requirements, gallium nitride (GaN), silicon carbide (SiC), and diamond, with their superior electrical properties are likely candidates to replace silicon in the near future. Along with higher blocking voltages wide-bandgap semiconductors offer breakthrough relative circuit performance enabling low losses, high switching frequencies, and high temperature operation. The progress of the development of high voltage, high current wide-bandgap power switching devices in the ARPA-E SWITCHES program is reviewed. The performance of various rectifiers and transistors, which have been demonstrated, is discussed. Material and processing challenges and reliability concerns for wide-bandgap power devices are also described. A glimpse into the future trends in device development and commercialization is offered.
(Invited) Wide Band-Gap on Its Hard Way up - The Trouble Starts Just Outside the Chip
Authors: Kaminski Nando
Published: September 2016

Semiconductor chips made from silicon carbide (SiC) or gallium nitride (GaN) are already approaching the theoretical limits given by the respective wide band-gap (WBG) materials. Unfortunately, their advantages over silicon devices cannot be fully exploited due to limitations imposed by the device packaging or the circuitry around the semiconductors. Stray inductances slowdown the switching speed and increase losses, packaging materials limit the maximum temperature and the maximum useful temperature swing, and passives limit the maximum switching frequency. All these issues have to be solved or at least minimized to make WBG attractive for a wider range of applications and, consequently, to profit from the economy of scale. Only this way, WBG-devices could step out of the high end niche and could really challenge silicon, which will remain to be a powerful competitor. And WBG-materials (theoretically) even better than SiC and GaN are at the horizon already.
(Invited) Novel Integrated Circuit Platforms Employing Monolithic Silicon CMOS + GaN Devices
Authors: Fitzgerald Eugene A , Lee K.E. , Zhang Li , Huang C.C. , Kadir A. , Bao Shuyu , Ren Z. , Wang C. , Wang Y. , Lee Kwang Hong , Liu Z.H. , Palacios Tomas , Tan Chuan Seng , Ng G.I. , Chua S.J.
Published: September 2016

We describe the research results produced from our focus on integrating GaN HEMTs and LEDs into silicon CMOS integrated circuits. Although current component markets are driving most GaN HEMT development, we have undertaken an innovation path in which the value of an integrated GaN device in a silicon design environment is the driver for materials and device development. Our integrated process flow employs standard foundry production of front and back end CMOS. Such constraints demand certain GaN epitaxial and material criterion that is different than those on non-integrated devices. We report on 200 mm GaN-on-Si 725 um thick engineered substrates formed through a combination of MOCVD and wafer bonding processes. We have developed wafer engineering techniques such as edge encapsulation and substrate replacement to address wafer fragility issues typically associated with GaN on SEMI-spec 725 um Si wafers. This also leads new wafer/device platforms such as GaN-OI and CMOS + GaN that will open new avenues in device performance and integration of III-N with Si CMOS.
(Invited) Silicon Carbide as a Robust Neural Interface
Authors: Frewin Christopher L. , Bernardin Evans E. , Deku Felix , Everly Richard , Hassan Jawad , Pancrazio Joseph J. , Saddow Stephen E.
Published: September 2016

The intracortical neural interface (INI) could be a key component of brain machine interfaces (BMI), devices which offer the possibility of restored physiological neurological functionality for patients suffering from severe trauma to the central or peripheral nervous system. Unfortunately the main components of the INI, microelectrodes, have not shown appropriate long-term reliability due to multiple biological, material, and mechanical issues. Silicon carbide (SiC) is a semiconductor that is completely chemically inert within the physiological environment and can be micromachined using the same methods as with Si microdevices. We are proposing that a SiC material system may provide the improved longevity and reliability for INI devices. The design, fabrication, and preliminary electrical and electrochemical testing of an all-SiC prototype microelectrode array based on 4H-SiC, with an amorphous silicon carbide (a-SiC) insulator, is described. The fabrication of the planar microelectrode was performed utilizing a series of conventional micromachining steps. Preliminary electrochemical data are presented which show that these prototype electrodes display suitable performance.
(Invited) Physics of GaN High Electron Mobility Transistors
Authors: Shur Michael
Published: September 2016

The nitride High Electron Mobility (HEMTs) have a great potential for high power and RF applications because of a high breakdown field, a very large density of the polarization induced two-dimensional electrons, high electron velocities and mobilities, excellent thermal properties, chemical inertness, and radiation hardness. GaN power transistors grown on silicon substrates are already being commercialized. However, the full potential of the nitride based HEMTs is still to be achieved and will require improvements in the device design that account for the both materials properties and device physics of wide band gap transistors. Such new features include the diamond substrates for a better heat removal, adding a low conducting passivation between the gate and drain, using the perforated channel with perforations extending beyond the gate, implementing the HEMT technology in the AlInN/GaN materials system for lattice matching design and employing lateral-vertical designs for a higher breakdown voltage.
(Invited) Manufacturing Microwave AlGaN/GaN High Electron Mobility Transistors (HEMTs) on Truly Bulk Semi-Insulating GaN Substrates
Authors: Piotrowska Anna Barbara , Kaminska Eliana Anetka , Wojtasiak Wojciech , Gwarek Wojciech , Kucharski Robert , Zajac Marcin , Prystawko Pawel , Kruszewski Piotr , Ekielski Marek , Kaczmarski Jakub , Kozubal Maciej , Trajnerowicz Artur , Taube Andrzej
Published: September 2016

The substrate of choice for high power microwave GaN-based devices is silicon carbide. However recently novel semi-insulating truly bulk GaN substrates with excellent crystalline and electrical parameters have been developed by Ammono S..A. These allow to elaborate AlGaN/GaN heterostructures with high electron mobility values and density of two-dimensional electron gas. Developed processing steps, especially planar isolation by ion implantation and formation of low resistivity regrown ohmic contacts enabled fabrication of high quality devices. An 1000 mA/mm on-state current density along with low 4.4 Ω/mm on-state resistance were achieved. For the devices with rectangular, 0.8 μm gate length the fMAG and fs were 31 GHz and 22 GHz. The maximum output power density was more than 4.15 W/mm in S-band.
(Invited) Improved Vertical GaN Diodes with Mg Ion Implanted Junction Termination Extension
Authors: Anderson Travis J , Koehler Andrew D. , Feigelson Boris , Hobart Karl D , Kub Francis J
Published: September 2016

Improved GaN Schottky barrier diodes (SBDs) and p-i-n diodes with edge termination formed by either a field plate or junction termination extension (JTE) achieved by ion implanted and symmetric multicycle rapid thermal annealing (SMRTA) are demonstrated. The devices with JTE exhibited substantially reduced leakage currents and improved turn-on characteristics. This is attributed to the elimination of the plasma process steps. The breakdown characteristics were studied by electroluminescence imaging, and is indicative of avalanche behavior. The realization of vertical GaN devices with low reverse leakage and ion implanted termination regions represents a key step for future power electronic devices.
Advances in AlGaN/GaN HEMT Surface Passivation
Authors: Koehler Andrew D. , Tadjer Marko J. , Anderson Travis J , Chojecki P. , Hobart Karl D , Kub Francis J
Published: September 2016

The high efficiency and power density of AlGaN/GaN high electron mobility transistors (HEMTs) can be limited by parasitic charge trapping at sites on the semiconductor surface. Trapped electrons at the surface deplete the two-dimensional electron gas (2DEG), resulting in effects known as current collapse, increased dynamic on-resistance, DC-RF dispersion, among others. A plasma-enhanced chemical vapor deposition (PECVD) SiN layer is conventionally implemented as surface passivation for GaN HEMTs, however the properties of this SiN layer and the impact of this layer on current collapse depend drastically on the deposition conditions of this film. Although passivation of GaN HEMTs has been studied extensively, the specific details behind the SiN passivation deposition are not commonly provided within literature. In this work, we investigate several passivation PECVD SiN passivation schemes and study their performance under dynamic switching conditions, under off-state stress, and implement electroluminescence imaging to identify electric field nonunifornities.
Non-Pressure Joining Method for Zn-Al Solder by Pre-Ultrasonic Bonding
Authors: Tanisawa Hidekazu , Takahashi Hiroki , Kato Fumiki , Koui Kenichi , Sato Shinji , Murakami Yoshinori , Sato Hiroshi
Published: September 2016

This paper reports joining technology for Zn-Al solder without pressure during reflow process. SiC power devices can operate at temperatures over 200 ºC. Taking the advantage of this benefit, the cooling system which occupies a large volume in an inverter can be downsized. However, high melting point solder is required, such as Zn-Al solder. This solder was needed to pressure during reflow process because Zn-Al solder preform has stiff natural oxide film on its surface. We propose a new process for breaking the oxide film and creating temporary joining by ultrasonic bonding. As the result, the solder can join other components without pressure during reflow.
Interfacial Transitional Layer in SiO2 Film Thermally Grown on SiC(000-1)
Authors: Nagai Ryu , Iitsuka Nozomu , Ozawa Kodai , Hasunuma Ryu , Yamabe Kikuo
Published: September 2016

The uniformity of SiO2 film thermally grown on 4H-SiC was characterized by atomic force microscopic observation of the emerged SiO2 surface after each step-etching using diluted HF solution. It was found that roughness of the emerged SiO2 surface drastically increases near the SiO2/SiC interface. This means that the film quality near the interface is not two-dimensionally uniform. We described the two-dimensionally non-uniform. On the other hand, the amount of roughness increase at the middle region was small, indicating the middle region is uniform film. These results indicate that the region is two-dimensionally uniform. These results indicate that the oxide film contains non-uniformly when just after being formed, and then the two-dimensional film uniformity is gradually improved during subsequent oxidation. Density profiles of SiO2 films were also characterized. The uniformity improvement was discussed in terms of impurity desorption and film density.
Deep Trap Levels Responsible for Current Collapse in AlGaN/GaN MISHFET
Authors: Seol Jeong-hoon , Kang Hee-Sung , Lee Gil-Ho , Lee Jung-Hee , Hahm Sung-Ho
Published: September 2016

We investigated the current collapse in AlGaN/GaN MISHFETs after negative gate bias by observing the spectral photo-responsive drain current. The photons of 2.25 eV were the most effective photon energy to excite the electrons trapped by the deep levels, and the energy was attributed to the current collapse induced by the negative gate bias. This trap deep energy might be related to the Ga vacancy in GaN bulk layer. The current collapse in AlGaN/GaN MISHFET was more significant for the wider gate-drain spacing.
(Invited) Study on the Role of Thermal Stress on Prismatic Slip of Dislocations in 4H-SiC Crystals Grown by PVT Method
Authors: Guo Jianqiu , Yang Yu , Goue Ouloide Yannick , Raghothamachar Balaji , Dudley Michael
Published: September 2016

Basal plane slip is most frequently observed deformation mechanism in 4H type silicon carbon (4H-SiC) single crystals grown by physical vapor transport (PVT) method. It has recently been reported, however, dislocations in such crystals can also glide in the prismatic slip systems. In our study, we have observed non-uniform distributions of three sets of prismatic dislocations in a commercial 4H-SiC substrate wafer. The non-uniformity is likely a result of the distribution of resolved shear stress on each prismatic slip system caused by the radial thermal gradients in the growing crystal boule. A radial thermal model during PVT growth has been developed to estimate the thermal stress across the entire area of the crystal boule. The model makes an excellent agreement with the actual observation, confirming that radial thermal gradients play a key role in activating prismatic slip in 4H-SiC during bulk growth.
(Invited) 4H-SiC Ion Implanted Bipolar Junctions: Relevance of the 1950°C Temperature for Post Implantation Annealing
Authors: Nipoti Roberta , Parisini Antonella , Sozzi Giovanna , Puzzanghera Maurizio , Parisini Andrea , Carnera Alberto
Published: September 2016

In case of Al+ implanted 4H-SiC, a post implantation annealing temperature of 1950°C has the beneficial effect of maximizing both the electrical activation of implanted Al and the reordering of the lattice damaged by the Al ions. However, the formation of extended defect in the implanted layers and that of carbon vacancies in the n-type epi-layers below the implanted layers may be hardly avoided. This study contains the results of structural and electrical investigation showing that: (i) on increasing the implanted Al concentration different type of extended defects form and grow; (ii) a strong anisotropic hole transport occurs when the Al implanted surface layer is confined by and contains stacking faults. This study contains also a study about the area and the perimeter current densities of Al+ implanted 4H-SiC p-i-n diodes showing that: (iii) the sole hypothesis of carrier lifetimes dominated by carbon-vacancy related traps and the presence of a negative fixed charge at the sample surface allow us a good but not perfect simulation of the measured area and perimeter current components.
(Invited) Progress in Buried Grid Technology for Improvements in on-Resistance of High Voltage SiC Devices
Authors: Schöner Adolf , Elahipanah Hossein , Thierry-Jebali Nicolas , Reshanov Sergey A. , Kaplan Wlodek , Zhang Andy , Lim Jang-Kwon , Bakowski Mietek
Published: September 2016

Buried grid technology is suggested to protect field sensitive device areas from high electric field in order to improve the high temperature and high voltage performance of SiC devices. More than three orders of magnitude lower leakage currents have been demonstrated at high temperature operation. The drawback is that the total resistance increases due to the introduction of the buried grid leading to higher voltage drop at rated current and higher conduction losses. In this paper, we discuss doping and barrier engineering methods in order to take full advantage of the superior shielding effect of the buried grid technology and at the same time minimize the effect on the current conduction. As example, the design considerations for a 1200V SiC buried grid JBS diode in terms of epi structure doping as well as buried grid properties is comprehensively investigated to optimize the on-state condition.
Characterization of Interface State Density of SiO2/SiC (000-1) Based on Oxygen Concentration at the Interface during Thermal Oxidation
Authors: Hasunuma Ryu , Hanasato Kohei , Yamabe Kikuo
Published: September 2016

The interface state density for SiO2/4H-SiC(000-1) was investigated and characterized with oxygen concentration at the interface during oxidation. The oxidation concentration was calculated by fitting the experimental oxidation data with the Deal-Grove model. It was found that the deep level (1.0 eV below the bottom of the conduction band of 4H-SiC) of the interface state was correlated to the concentration of oxygen at the interface. The interface state density decreases as the oxygen concentration increases, which corresponds to better interface property for thinner SiO2 film. It was concluded that oxygen molecules act as remover of C-related impurities from the SiO2 film. High temperature oxidation is effective to reduce interface state density, which is probably due to increase in the formation energy of CO giving rise to enhancement of out diffusion of the impurities.
Direct Observation of Energy Distribution of Interface States at SiO2/4H-SiC Interface
Authors: Yamashita Yoshiyuki , Hasunuma Ryu , Nagata Takahiro , Chikyow Toyohiro
Published: September 2016

The energy distribution of the interface states at the SiO2/4H-SiC(0001) interface was obtained using operando photoelectron spectroscopy. For the interface states, sharp and high density interface states were observed near the conduction band minimum and uniform interface states were present in the entire SiC band-gap. The uniform interface states observed in the whole gap were attributed to graphitic carbon clusters at the interface although the sharp interface states could not be assigned currently.