bluuebunny/crossref_metadata_2025 huggingface dataset:
A Novel Multilayered Ni–Zn-Ferrite/TaN Film for RF/Mobile Applications
Authors: Kaneko Kishou , Inoue Naoya , Furutake Naoya , Hayashi Yoshihiro
Published: April 2010

A novel multilayered Ni–Zn-ferrite/TaN (MFT) film is developed for RF/mobile complementary metal oxide semiconductor (CMOS) applications. The Ni–Zn ferrite (Ni0.5Zn0.5Fe2O4) film is deposited by low-temperature RF magnetron sputtering technique applicable for conventional low-k/Cu interconnects in advanced CMOS LSI. In the MFT film, a stacking unit of thin Ni–Zn-ferrite and thin TaN is laminated to enhance the ferrite (311)spinel orientation close to the magnetization easy axis of the ferrite. The saturated magnetization (M
s) increased 50% referred to the single-layer Ni–Zn-ferrite/TaN, and the coercivity (H
c) decreased one-fifth desirable for the high speed switching. By physical-based modeling, it is proved that the fraction of the (311)-orientation region in the total ferrite thickness is very important to improve the magnetic properties. In addition to the high resistivity (ρ=10 MΩ cm) to suppress eddy current loss, the MFT film is effective to confine and enhance the magnetic field in the on-chip inductor in GHz range, suitable for RF/mobile applications.
Stability of La2O3 Metal–Insulator–Metal Capacitors under Constant Voltage Stress
Authors: Wu Shu-Hua , Deng Chih-Kang , Hou Tuo-Hung , Chiou Bi-Shiou
Published: April 2010

In this study, we demonstrate the stability of high-κ La2O3 metal–insulator–metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance (α) decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of α. Additionally, high stability of 10-year lifetime is achieved for a 10-nm La2O3 MIM capacitor with an 11.4 fF/µm2 capacitance density.
Discrete-Dopant-Induced Power-Delay Characteristic Fluctuation in 16 nm Complementary Metal–Oxide–Semiconductor with High Dielectric Constant Material
Authors: Han Ming-Hung , Li Yiming , Hwang Chih-Hong
Published: April 2010

In this work, we carry out an experimental validated three-dimensional “atomistic” device-circuit coupled simulation to study the discrete-dopant-induced power and delay fluctuations in 16-nm-gate complementary metal–oxide–semiconductor (CMOS) circuits. The equivalent gate oxide thicknesses (EOTs) of planar CMOS range from 1.2 nm to 0.2 nm. SiO2 is used at gate oxide thicknesses of 1.2 and 0.8 nm, Al2O3 at an EOT of 0.4 nm, and HfO2 at an EOT of 0.2 nm. Under the same device threshold voltage, as EOT decreases from 1.2 to 0.2 nm, the fluctuations of threshold voltage and gate capacitance for CMOS transistors are reduced by 43 and 55%, respectively. For the state-of-art nanoscale circuits using high-dielectric constant (high-κ) materials, the delay time fluctuation is suppressed significantly from 0.1 to 0.03 ps. For the power characteristics, although the nominal powers of circuits using high-κ dielectrics are increased owing to the increased EOT, the fluctuations of dynamic power, short circuit power, and static power are reduced by 40, 70, and 30%, respectively.
Temperature Coefficient of Threshold Voltage in High-k Metal Gate Transistors with Various TiN and Capping Layer Thicknesses
Authors: Nishida Yukio , Eikyu Katsumi , Shimizu Akihiro , Yamashita Tomohiro , Oda Hidekazu , Inoue Yasuo , Shibahara Kentaro
Published: April 2010

The temperature coefficient of V
th (=d
V
th/d
T), which is commonly utilized for circuit design, was systematically obtained against various TiN and capping layer thicknesses in high-k/metal gate field-effect transistors (FETs). It is known that the magnitude of |d
V
th/d
T| for such FETs is larger than that of polycrystalline silicon (poly-Si) gate FETs. The origins of the d
V
th/d
T difference among high-k/metal gate FETs were attributed to differences in the temperature coefficient of flat band voltage (=d
V
FB/d
T) and the equivalent gate oxide thickness (EOT). Thicker TiN layers reduced d
V
FB/d
T, which enlarged the magnitude of |d
V
th/d
T|. The EOT increased as the TiN metal layer or Al2O3 capping layer increased in thickness. The large EOT led to an increase in |d
V
th/d
T|, since d
V
th/d
T is a function of the inverse of gate capacitance. In contrast, La2O3 capping hardly affected d
V
th/d
T. This is because La2O3 capping did not affect EOT differently from Al2O3 capping. The relationship between d
V
th/d
T and EOT implies that EOT scaling relieves the issue of large |d
V
th/d
T| for high-k/metal gate FETs.
DC Improvements and Low-Frequency 1/f Noise Characteristics of Complimentary Metal–Oxide–Semiconductor Transistors with a Single n+-Doped Polycrystalline Si/SiGe Gate Stack
Authors: Grados Hugo Ricardo Jiménez , Manera Leandro T. , Wada Ricardo , Diniz José Alexandre , Doi Ioshiaki , Tatsch Peter Jurgen , Figueroa Hugo Enrique , Swart Jacobus W.
Published: April 2010

Complimentary metal–oxide–semiconductor (CMOS) transistors with polycrystalline Si (poly-Si)/SiGe as the gate material are presented. The SiGe integration using a local CMOS process was developed. It uses a single n+-doped poly-Si0.7Ge0.3 gate instead of single n+- or double-doped poly-Si gate. After deposition, both the poly-Si and SiGe films used as gate layers were doped with phosphorus ions. The threshold, subthreshold, and low-frequency 1/ f noises of poly-Si/SiGe CMOS transistors are reported. Improvements in the performance of the poly-Si/SiGe CMOS transistor compared with the poly-Si gate CMOS transistor are presented, indicating that the presence of Ge in the gate material is beneficial, which agrees with results reported in the literature. The n-channel metal–oxide–semiconductor (n-MOS) transistor characteristics in the diode mode (V
GS=V
DS) are shown, followed by transconductance (G
m) results. Improvements in the current–voltage (I–V) characteristics are observed when poly-Si/SiGe CMOS transistors are compared with poly-Si gate CMOS transistors. Another key point is the low-frequency 1/ f noise characteristic, which makes the latter transistors promising devices for RF applications.
Analysis of Hundreds of Time Constant Ratios and Amplitudes of Random Telegraph Signal with Very Large Scale Array Test Pattern
Authors: Fujisawa Takafumi , Abe Kenichi , Watabe Shunichi , Miyamoto Naoto , Teramoto Akinobu , Sugawa Shigetoshi , Ohmi Tadahiro
Published: April 2010

Random telegraph signal (RTS) noise shows discrete and stochastic switching in two or more states at a drain current or threshold voltage. The capture and emission of carriers in individual traps near a silicon–gate insulator film interface induce RTS noise phenomena. RTS noise has become a crucial problem in analog devices and other devices. To suppress RTS noise, it is necessary to determine the energy level of traps. Time constant ratio has a strong relationship with the energy level of traps in gate insulator films. In this paper, we extract a large number of RTS data sets with large-scale array test patterns and evaluate the gate-bias voltage dependences of time constant ratio and amplitude. We demonstrate that the energy level of traps distributes uniformly at a drain current of at least 0.1–1.0 µA.
Experimental Investigation of Effect of Channel Doping Concentration on Random Telegraph Signal Noise
Authors: Abe Kenichi , Teramoto Akinobu , Watabe Shunichi , Fujisawa Takafumi , Sugawa Shigetoshi , Kamata Yutaka , Shibusawa Katsuhiko , Ohmi Tadahiro
Published: April 2010

Random telegraph signal (RTS) noise has become one of the most important problems in the continuous scaling down of field-effect transistors (FETs). In this study, we investigate experimentally the relationship between RTS amplitude and channel doping concentration (N
A), which is a key parameter related to threshold voltage adjustment and short-channel effects, in 393,216 n-type FETs by a high-speed measurement method. We demonstrate that N
A has a significant effect on RTS amplitude even at approximately the same interface and bulk trap densities of the gate insulator films, which are evaluated by the charge pumping method, by the quasi-static capacitance–voltage method, and on the basis of 1/f noise characteristics. An increase in RTS amplitude may arise from a more advanced channel nonuniformity as N
A increases.
Characteristics of Gate Current Random Telegraph Signal Noise in SiON/HfO2/TaN p-Type Metal–Oxide–Semiconductor Field-Effect Transistors under Negative Bias Temperature Instability Stress Condition
Authors: Zhang Liangliang , Liu Changze , Wang Runsheng , Huang Ru , Yu Tao , Zhuge Jing , Kirsch Paul , Tseng Hsing-Huang , Wang Yangyuan
Published: April 2010

Gate dielectric traps are becoming a major concern in the high-k/metal gate devices. In this paper, new experimental results and in-depth study on gate current random telegraph signal (I
g RTS) noise in SiON/HfO2/TaN gate stack p-type metal–oxide–semiconductor field-effect transistors (PMOSFETs) are reported. Single carrier trapping/detrapping in the high-k/metal gate stack under negative bias temperature instability (NBTI) stress is observed for the first time. The location of traps, the impacts of gate bias, temperature and substrate bias are discussed for understanding the RTS mechanism in high-k devices. Moreover, during long time stress, an abrupt change of amplitude of I
g fluctuation and the mean capture and emission time is also observed for the first time, due to new trap generated or activated by the NBTI degradation. The characteristics of the single carrier trapping/detrapping behavior under NBTI stress are very different from that on the normal bias condition, which give us more information about the traps in the high-k/metal gate stack.
Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width
Authors: Leonelli Daniele , Vandooren Anne , Rooyackers Rita , Verhulst Anne S. , Gendt Stefan De , Heyns Marc M. , Groeseneken Guido
Published: April 2010

This paper discusses the electrical characterization of complementary multiple-gate tunneling field effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard complementary metal oxide semiconductor (CMOS) processing, emphasizing the dependence of the tunneling current on the fin-width. A linear dependence of the tunneling current for narrow fins with the square root of the fin width is experimentally reported for the first time. The comparison between narrow fins and planar-like fins offers additional insights about the fin-width dependence. The output characteristic shows a perfect saturation, very attractive for analog circuits. The temperature dependence is measured indicating a weak dependence as expected for tunneling devices. Measured devices with a point slope of 46 mV/dec at low biases and an I
on/I
off ratio of 106 at a supply voltage of 1.2 V for 25 nm wide fins are reported as best performing devices with a MuGFET technology using a high-k dielectric and a metal gate inserted gate stack.
Quantitative Analysis of Hump Effects of Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Lee Woojun , Choi Woo Young
Published: April 2010

The hump effect of gate-all-around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs) has been analyzed quantitatively. The function H(V
G) is introduced to evaluate the hump magnitude of GAA MOSFETs by extracting threshold voltages of main and parasitic channels accurately. Based on simulation study, the effect of fin doping concentration, fin corner rounding and gate oxide thickness on the hump magnitude of GAA MOSFETs has been analyzed quantitatively, which presents the design guideline of GAA MOSFETs.
Investigation of Enhanced Impact Ionization in Uniaxially Strained Si n-Channel Metal Oxide Semiconductor Field Effect Transistor
Authors: Adachi Shinichiro , Asano Tanemasa
Published: April 2010

The impact ionization rate in uniaxially strained silicon is evaluated from viewpoints of the ionization threshold β and maximum electric field E
m for the first time. Strain and temperature dependences of β are investigated on the basis of the change in slope in a universal relation while E
m, which is also dependent on strain and temperature, is investigated on the basis of the change in saturation voltage V
DSAT. The impact ionization rate is a function of β and E
m such that we also evaluated strain and temperature dependence of multiplication factor M - 1 (= I
sub/I
D) to determine the major concern of change in impact ionization rate. The result shows that the change in E
m due to the change in potential drop along the channel is the major concern in a uniaxially strained silicon n-channel metal oxide semiconductor field effect transistor (nMOSFET).
Effect of Carrier Transit Delay on Complementary Metal–Oxide–Semiconductor Switching Performance
Authors: Hori Daisuke , Miyake Masataka , Sadachika Norio , Mattausch Hans-Juergen , Miura-Mattausch Mitiko , Iizuka Takahiro , Hoshida Teruhiko , Matsuzawa Kazuya , Sahara Yasuyuki , Tsukada Toshiro
Published: April 2010

The high-speed switching performance of a complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) inverters is analyzed. It is found that the propagation delay of an inverter can no lomger be described by a DC-current-based estimate, but that the charging/discharging current is essential for the propagation delay prediction under high-frequency operation.
Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack
Authors: Fukutome Hidenobu , Okubo Kazuya , Akiyama Sinichi , Idani Naoki , Ohta Hiroyuki , Kawamura Kazuo , Momiyama Yoichi , Satoh Shigeo
Published: April 2010

We demonstrated an ideal scaling of inversion gate dielectric thickness (T
inv) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved drive currents of 1.1/0.65 mA/µm at an off-leakage current of 50 nA/µm for the sub-30-nm n- and p-metal–oxide–semiconductor field effect transistors (MOSFETs). Because the decrease in gate length was larger than the T
inv scaling while maintaining a high drive current, the Ni-FUSI/SiON gate stack improved the intrinsic delay of the scaled inverter.
Experimental Evaluation of Coulomb-Scattering-Limited Inversion-Layer Mobility of n-type Metal–Oxide–Semiconductor Field-Effect Transistors on Si(100), (110), and (111)-Surfaces: Impact of Correlation between Conductivity Mass and Normal Mass
Authors: Nakabayashi Yukio , Ishihara Takamitsu , Numata Toshinori , Uchida Ken , Takagi Shinichi
Published: April 2010

The inversion-layer electron mobility limited by Coulomb scattering due to interface states (µit) and substrate impurities (µsub) are experimentally evaluated on Si n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) at the surfaces of Si(100), (110), and (111). The inversion-layer mobility is measured by the split C–V method and µit and µsub are extracted using Matthiessen's rule. µit exhibits almost the same behavior irrespective of the different surface orientations, while µsub has the surface orientation dependence. The very weak surface orientation dependence of µit are due to the correlation between the inversion layer thickness (Z
ave) determined by the normal mass (m

z
) and the weighed average value of conductivity mass (m
c_ave) under multi valley occupation. The surface orientation dependence of µsub is basically explained by the m
c_ave difference.
Accurate Extraction and Modeling of High-Temperature-Dependent Channel Mobility in Metal–Oxide–Semiconductor Field-Effect Transistors Using Measured S-Parameters
Authors: Ko Bonghyuk , Jung Daehyoun , Lee Seonghearn
Published: April 2010

An improved RF method based on the slope extraction of the total drain–source resistance and total gate charge versus mask gate length from measured S-parameters is presented to extract the effective channel mobility of bulk metal–oxide–semiconductor field-effect transistors (MOSFETs) from 27 to 250 °C. An improved temperature-dependent channel mobility equation is also used to eliminate the high-temperature modeling errors in the conventional equation. Much better agreement with measured electron mobility data from 27 to 250 °C is achieved by using the improved equation rather than the conventional one, verifying the accuracy of the improved equation.
Hall Factor in Ultrathin-Body Silicon-on-Insulator n-Type Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Kobayashi Shigeki , Saitoh Masumi , Nakabayshi Yukio , Ishihara Takamitsu , Numata Toshinori , Uchida Ken
Published: April 2010

Hall factor (γH) is investigated experimentally in the ultrathin-body (UTB) silicon-on-insulator (SOI) n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) with the SOI thicknesses (T
SOI) of less than 10 nm. It is demonstrated experimentally for the first time that when T
SOI is thicker than 4.2 nm, γH decreases slightly with a reduction of T
SOI, whereas when T
SOI is thinner than 4.2 nm, γH decreases drastically and becomes almost unity in T
SOI of 2.5 nm. The γH is calculated considering only phonon scattering. Then, calculated γH is compared with γH obtained experimentally. In addition, it is found that in phonon scattering γH is determined dominantly by the intravalley scatterings of the twofold valleys. The dominance of the intravalley scatterings of the twofold valleys in the γH determination is attributed to the energy levels of subbands whereby most of the scatterings are the intravalley scatterings of the twofold valleys.
Forward-Body-Bias-Enhanced Negative Bias Temperature Instability Recovery of p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: He Yandong , Du Gang , Yang Yunxiang , Zhang Ganggang , Zhang Xing , Wang Yangyuan
Published: April 2010

Experimental investigation on the negative bias temperature instability (NBTI) recovery of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with forward body bias (FBB) was conducted. Our results show that not only the positive gate bias but also the FBB will enhance the recovery of NBTI for pMOSFETs. A forward-body-bias-enhanced NBTI recovery mechanism was proposed with evidence of the NBTI recovery with FBB dependence and corresponding electron/hole density simulation results. Furthermore, the dynamic NBTI degradation was compared with and without FBB. The enhancement of NBTI recovery by FBB gives a comparable lifetime of zero body bias, which indicates that the forward body biasing technique can improve the drive capability without deteriorating NBTI performance.
The Layout Geometry and Power-Level Dependences of Degradation in Complementary Metal–Oxide–Semiconductor RF Power Cells from Hot-Carrier Stress with Load Pull System
Authors: Liu Chien-Hsuan , Su Yan-Kuin , Wang Ruey-Lue , To Chih-Ho , Juang Ying-Zong
Published: April 2010

A comparison of reliability for 0.18-µm complementary metal–oxide–semiconductor (CMOS) power cells with different layout geometry and output power level is proposed. The layout geometries of power cell are designed and optimized to alleviate hot-carrier effects for better performance and reliability. The degradation induced by the reflected power from load mismatch is demonstrated. The hot-carrier effect is aggravated by load mismatch in high power operation. The degree of degradation depends on input power levels. Two sets of power cells for output power of 10 and 50 mW are measured in this work. The results show that the drain current of the cell with compact layout was degraded much more critically after RF stress than one with dispersive layout pattern. Otherwise, both the degradation from DC and RF stress was higher in the cells with higher output power-level.
High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structure Based on Bulk Substrate
Authors: Tang Poren , Huang Ru , Wu Dake , Zhang Yilin , Wang Yangyuan
Published: April 2010

A novel quasi silicon-on-insulator (QSOI) capacitorless dynamic random access memory (DRAM) Cell with bulk substrate is proposed and investigated for the first time. The QSOI DRAM cell is based on the promising highly scalable QSOI device structure. The deep L-shape layer of proposed QSOI cell can provide isolation between adjacent cells along bit line, without increasing the cell area as the one transistor (1T) bulk capacitorless DRAM cell. The electrical performance of this structure is also studied and compared with 1T-bulk cell. Longer retention time and larger sensing margin can be achieved in the proposed QSOI cell, due to the suppressed leakage current. The results indicate that QSOI cell has great potentials for high density DRAM applications.
Source Side Injection Programmed P-Channel Self-Aligned-Nitride One-Time Programming Cell for 90 nm Logic Nonvolatile Memory Applications
Authors: Huang Chia-En , Chen Ying-Je , OuYang Hsun , Lin Chrong-Jung , King Ya-Chin
Published: April 2010

This study demonstrates a logic compatible p-channel self-aligned-nitride (SAN) cell for one-time programming (OTP) memory applications. The SAN storage structure is independent of the gate oxide thickness, allowing these cells to be performed in a pure advanced logic process beyond 90 nm. The study also exams the characteristics of the source-side injection hot electron (SSIHE) scheme using the simulation tools, and successfully verified the programming characteristics of the p-channel SAN cell with different program voltages. Moreover, this study shows the proposed SAN cell has a wide read current window, high reliability, and superior immunity to disturbance. Combined with a source-side injection scheme, this cell provides a promising solution for advanced logic nonvolatile memory (NVM) applications.
Direct Measurement of Back-Tunneling Current during Program/Erase Operation of Metal–Oxide–Nitride–Oxide–Semiconductor Memories and Its Dependence on Gate Work Function
Authors: Fujiki Jun , Fujii Shosuke , Yasuda Naoki , Muraoka Kouichi
Published: April 2010

In this study, we have established a novel scheme to extract the back-tunneling current from the transient characteristics of a metal–oxide–nitride–oxide–semiconductor (MONOS) memory capacitor during programming or erasing. Using a charge centroid extraction method, the separation of trapping current, leakage current and back-tunneling current was successfully accomplished. By studying the gate work function dependence of injected current, it was found that the leakage current due to electron injection from the Si substrate is the dominant component during deep programming and that the back-tunneling current due to electron injection from the gate electrode is the predominant component of injected current during deep erasing.
A Negative Word-Line Voltage Negatively-Incremental Erase Pulse Scheme with ΔVTH = 1/6ΔVERASE for Enterprise Solid-State Drive Application Ferroelectric-NAND Flash Memories
Authors: Hatanaka Teruyoshi , Yajima Ryoji , Takahashi Mitsue , Sakai Shigeki , Takeuchi Ken
Published: April 2010

A negative word-line voltage negatively-incremental erase pulse scheme is proposed for the enterprise solid-state drive (SSD) application ferroelectric (Fe)-NAND flash memories. The negative word-line voltage erase accelerates the erase pulse ramp-up from 1 ms of the conventional well erase to 2 µs and a 200 µs/page erase is realized. The erase characteristics with various erase pulse shape such as the fixed erase pulse, the variable time erase pulse, and the proposed negatively-incremental erase pulse for the Fe-NAND cells are investigated. With the proposed scheme, the erase voltage, V
ERASE decreases by ΔV
ERASE. The measured V
TH shift, ΔV
TH, is constant at 1/6ΔV
ERASE, which is different from that of the floating-gate NAND cells where ΔV
TH = ΔV
ERASE. The mechanism of the constant ΔV
TH is discussed with the major and the minor polarization–electric field curves. By combining the proposed negatively-incremental erase scheme with the bit-by-bit verify, a narrow erase V
TH distribution of 0.07 V is achieved with ΔV
ERASE of 0.4 V.
Charge Localization during Program and Retention in Nitrided Read Only Memory-Like Nonvolatile Memory Devices
Authors: Nowak Etienne , Vianello Elisa , Perniola Luca , Bocquet Marc , Molas Gabriel , Kies Rabah , Gely Marc , Ghibaudo Gerard , Salvo Barbara De , Reimbold Gilles , Boulanger Fabien
Published: April 2010

An alternative solution to standard Flash memories is represented by nitride-trap memories as silicon–oxide–nitride–oxide–silicon (SONOS) or nitrided read only memory (NROM) memories. However these structures are facing retention issues at high temperature and a quantitative analysis of the location of the charge during program and retention is required. This work investigates the location of charge of NROM Nonvolatile memory devices in order to evaluate the trapped charge distribution in program and retention conditions for Si3N4, Al2O3, and HfO2 trapping layers. During programming, the charge is initially injected on a 40–60-nm-length region in the trapping layer, then after reaching a trapped charge saturation level, it broadens. The charge saturation level is explained through electrostatic considerations and not by a limit of available number of traps. During retention, the lateral migration (inside the trapping layer) and vertical migration (charge loss) of the trapped charge are quantitatively evaluated. Thanks to a one-dimensional (1D) drift model, the characterization of lateral migration at room temperature is put in relation to the trap properties of Si3N4, Al2O3, and HfO2 layers.
Fabrication and Characterization of Ferroelectric Poly(vinylidene fluoride–tetrafluoroethylene) Gate Field-Effect Transistor Memories
Authors: Watanabe Tomohiro , Miyashita Hiroyuki , Kanashima Takeshi , Okuyama Masanori
Published: April 2010

Organic ferroelectric gate field-effect transistor (FET) memories have been fabricated using pentacene as the semiconductor and a poly(vinylidene fluoride–tetrafluoroethylene) [P(VDF–TeFE)] thin film as the ferroelectric gate. The P(VDF–TeFE) film is prepared by spin coating and annealing at 170 °C for 2.5 h, and pentacene is prepared by vacuum evaporation. The polarization–electric field (P–E) hysteresis of the P(VDF–TeFE) thin film is observed and enhanced by poling treatment. The obtained P
r of 4 µC/cm2 is sufficient for controlling pentacene surface potential. Good memory characteristics are obtained in the P(VDF–TeFE) gate FET. For such a FET, the ON/OFF ratio of drain current is 830, the carrier mobility is 0.11 cm2 V-1 s-1, and the memory retention is over 16 h.
Effect of Self-Heating on Time-Dependent Dielectric Breakdown in Ultrathin MgO Magnetic Tunnel Junctions for Spin Torque Transfer Switching Magnetic Random Access Memory
Authors: Hosotani Keiji , Nagamine Makoto , Ueda Tomomasa , Aikawa Hisanori , Ikegawa Sumio , Asao Yoshiaki , Yoda Hiroaki , Nitayama Akihiro
Published: April 2010

Spin torque transfer switching magnetic random access memory (Spin-MRAM) using MgO-magnetic tunnel junction (MTJ) is considered to be the most promising candidate for high-density, high-speed, and non-volatile RAM. Notwithstanding its excellent potential, the breakdown mechanism of MgO-MTJ has not been well understood although a thorough understanding is essential for commercialization of Spin-MRAM. In this paper, we demonstrate for the first time the modeling of dielectric breakdown phenomena of MgO-MTJ by time-dependent dielectric breakdown (TDDB) measurement concerning the effect of self-heating using simulation and conclude that E-model with the effect of self-heating at MgO-MTJ during current stress (power) removed gives the best fitting as a degradation model of MgO-MTJ ultrathin dielectrics.
A Complementary Metal–Oxide–Semiconductor Image Sensor with 2.0 e- Random Noise and 110 ke- Full Well Capacity and Noise Measurement of Pixel Transistors Using Column Source Follower Readout Circuits
Authors: Kohara Takahiro , Lee Woonghee , Mizobuchi Koichi , Sugawa Shigetoshi
Published: April 2010

A low noise complementary metal–oxide–semiconductor (CMOS) image sensor without degradation of saturation performance has been developed by using column amplifiers of the gains of about 1.0 in a lateral overflow integration capacitor technology. The 1/4-in., 4.5-µm pitch, 800H×600V pixels CMOS image sensor fabricated by a 0.18-µm 2-poly 3-metal CMOS technology including a buried pinned photo-diode structure has achieved fully linear response, 0.98 column readout gain, 104-µV/e- conversion gain, 2.0-e- total random noise, 110,000-e- full well capacity and 95-dB dynamic range in one exposure. Moreover, the random noise of the developed readout circuits has been reduced to 0.5-e- without degradation of saturation performance. As a result, the behaviors of pixel noises have been accurately measured. Operating condition dependency of the random noise generated by pixel transistors has been measured by using the developed readout circuits. In addition, considering the result of the measurements, we optimize pixel operating condition.
Three-Dimensional Binocular Range Sensor LSI with Enhanced Correlation Signal
Authors: Kawano Masatomo , Kawaguchi Norihito , Yoshida Takashi , Arima Yutaka
Published: April 2010

We developed a three-dimensional (3D) binocular range sensor LSI with an enhanced correlation signal. The developed LSI chip was produced using a process of 0.35 µm complementary metal oxide semiconductor (CMOS) 1-poly 3-metal and has a die size of 4.20×3.33 mm2. The chip uses a 3.0 V supply voltage and has a power consumption of 280 mW at a clock frequency of 10 MHz. Two image sensors and the circuits for binocular stereo vision are integrated into the sensor. The distance to an object is determined by calculating the correlation between the two photosensors' output differential signals and observing the position of strong correlated values. However, in the previously developed range sensor, the correlation was weak when there was a small differential signal and it was unable to simultaneously detect several objects. In the newly developed range sensor, a circuit that modulates the differential signal was integrated and the correlation process was enhanced. The object detection signals are ten times larger than those of the previous sensor. As a result, we were able to simultaneously detect the 3D position of several objects. All the necessary calculations for 3D detection take 32 µs per frame. However, the output time for one 3D frame is 26 ms. Thus, the frame rate is limited to 38 frames per second.
Three-Dimensional Binocular Range Sensor Large Scale Integration with a 410 µs/Frame Output Time High-Speed Data Output Method
Authors: Kawaguchi Norihito , Kawano Masatomo , Arima Yutaka
Published: April 2010

We developed a three-dimensional (3D) binocular range sensor LSI equipped with a high-speed data output circuit. The circuit outputs only the information of the position corresponding to the detected object. As a result, the output time was reduced and the frame rate improved. The chip was produced using a process of 0.35 µm complementary metal oxide semiconductor (CMOS) 1-poly 3-metal and has a die size of 4.20×3.33 mm2. The chip uses a 3.0 V supply voltage and has a power consumption of 405 mW at a clock frequency of 10 MHz. The correlation of the image sensor's output takes 32 µs/frame and the maximum output time is 410 µs/frame. Because the output time is shorter enough than typical exposure, the frame rate is practically not limited by the data output time.
A Current-Mode Multiple-Resolution Edge-Filtering Complementary Metal Oxide Semiconductor Image Sensor Employing Self-Similitude Processing in Non-Subtraction Configuration
Authors: Takahashi Norihiro , Shibata Tadashi
Published: April 2010

A non-subtraction configuration of the self-similitude image processing architecture has been developed for pixel-parallel multiple-resolution directional edge filtering. In contrast to the subtraction-separated configuration employed in our previous work, the subtraction operation has been entirely eliminated from the computation repertory of processing elements in the present configuration. As a result, the hardware organization of the multiple-resolution edge-filtering complementary metal oxide semiconductor (CMOS) image sensor has been greatly simplified, and a fully pixel-parallel self-similitude processing has been established without any complexity in interconnects. In addition, it has provided an opportunity to further apply the self-similitude architecture to other filtering operation like Gaussian filtering and Laplacian filtering. An analog edge-filtering chip implemented using current-mode computation capable of performing four-directional edge filtering at full, half, and quarter resolutions was designed and fabricated in a 0.18-µm five-metal CMOS technology. The concept has been verified by chip measurements, which show that the four-directional edge filtering at multiple resolutions is accomplished at 910 frames/s for 56×56-input images.
A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems
Authors: Ma Yitao , Shibata Tadashi
Published: April 2010

A binary-tree hierarchical multiple-chip processor architecture leveraging the K-means clustering algorithm has been developed for real-time learning of large amounts of sample data. To improve the computational speed, an embedded memory configuration has been used to store all sample data on the same chip for massively parallel processing. As a solution to the problem of the maximum sample data size limited by the chip area, a multiple-chip architecture has been developed, in which dedicated processor chips are connected in a binary-tree hierarchical structure. As a result, the system has been made extendible to any larger scale depending on the application needs. Furthermore, the pipeline calculation flow has been introduced to compensate for the interchip data communication delay. A proof-of-concept chip was designed using a 0.18 µm five-metal complementary metal–oxide–semiconductor (CMOS) technology. The chip operation was verified by NanoSim simulation, and pipeline calculation flow was demonstrated by test chip measurement.
Above-Complementary Metal–Oxide–Semiconductor Inductor for Rapid Prototyping of Mixed-Signal System on Chips
Authors: Omiya Yutaka , Kotani Koji , Ito Takashi
Published: April 2010

A new prototyping method for a radio frequency system on a chip (SoC) using above-complementary metal–oxide–semiconductor (CMOS) inductors is proposed. In this method, a spiral inductor is formed on a CMOS chip fabricated and diced by normal manufacturing processes. Since the fabrication of above-CMOS inductors is carried out in a chip-by-chip manner with simple processes, the flexible adjustment of inductance and the evaluation of chip performance can be carried out within a short turnaround time. Therefore, the rapid prototyping of mixed-signal SoCs can be realized. This technique can be understood as a realization of a “breadboard on a chip” since it is based on the experimental method on a cut-and-try basis. We have successfully fabricated above-CMOS inductors with different inductances on different CMOS chips of the same design. The adjustment of the oscillation frequency of a voltage-controlled oscillator and the impedance matching of a low-noise amplifier have also been demonstrated.
0.25-µm-Emitter InP Heterojunction Bipolar Transistors with a Thin Ledge Structure
Authors: Kashio Norihide , Kurishima Kenji , Fukai Yoshino K. , Ida Minoru , Yamahata Shoji
Published: April 2010

This paper describes 0.25-µm-emitter InP heterojunction bipolar transistors (HBTs) with a thin ledge structure. The HBTs consist of a degenerately-doped n+-InGaAs/15-nm-thick undoped InP emitter, a 25-nm-thick p+-In0.53Ga0.47As base, and a 75-nm-thick In0.53Ga0.47As collector. The emitter enables fabrication of a 15-nm-thick ledge structure simply by wet etching the n+-InGaAs emitter. The emitter mesa and base metal were scaled down to 0.25 and 0.3 µm, respectively. The fabricated HBT with a 0.25-µm emitter provides a current gain of 62 at a collector current density, J
c, of 10 mA/µm2. With the thin ledge structure, the current gain is virtually independent of emitter size and emitter–base spacing. The HBT also exhibits an f
t of 442 GHz and an f
max of 214 GHz at a J
c of 12 mA/µm2. The results of bias-temperature stress tests show that base and collector currents are stable up to 1042 h at a J
c of 5 mA/µm2.
Ultrafast Optical Response of InAlAs/InAs/InGaAs Pseudomorphic High Electron Mobility Transistors
Authors: Taguchi Hirohisa , Oishi Yasuyuki , Ando Takahisa , Uchimura Kazuya , Mochiduki Miho , Enomoto Mitsuhiro , Iida Tsutomu , Takanashi Yoshifumi
Published: April 2010

High-electron-mobility transistors with a pseudomorphically strained InAs channel (InAs-PHEMTs) have excellent electron transport properties and a high electron density, which are due to their large conduction band discontinuity. In this work, we show the dependence of optical response on drain-to-source voltage (V
DS) for InAs-PHEMTs and clarify the physical mechanism for the response time. The experimental results can be explained successfully using two different lifetimes, one dominated by the time required for a hole to transit from the channel to the source region under the channel field and the other dominated by Auger recombination. To numerically understand the optical response, we estimate minority carrier lifetime using the Auger recombination theory. The theoretical result agrees well with the experimental result.
Metalorganic Vapor Phase Epitaxy of GaAs with AlP Surface Passivation Layer for Improved Metal Oxide Semiconductor Characteristics
Authors: Terada Yuki , Shimogaki Yukihiro , Nakano Yoshiaki , Sugiyama Masakazu
Published: April 2010

Growth of an AlP epitaxial layer on the top of GaAs was proposed as a novel in situ passivation method. The AlP layer was almost converted to AlOx upon air exposure, forming a part of a gate dielectric. Removal of AlAs at the GaAs/AlP interface was mandatory for avoiding As-oxide formation upon air exposure, which necessitated complete As removal from the surface when switching growth from GaAs to AlP. H2S treatment allowed us to obtain low-As-content c(8×2) surface reconstruction for the first time with metalorganic vapor phase epitaxy (MOVPE). AlP on the c(8×2) GaAs surface has made it possible to obtain a smooth morphology and complete suppression of arsenic oxide. PL intensity increased by a factor of three with the AlP growth for 10 s at 500 °C, corresponding to a thickness of 0.5 nm. Accumulation capacitance obtained from capacitance–voltage (C–V) curves was the largest with that growth a condition of AlP, suggesting reduction in interface states.
High Voltage AlGaN/GaN High-Electron-Mobility Transistors Employing Surface Treatment by Deposition and Removal of Silicon Dioxide Layer
Authors: Choi Young-Hwan , Kim Sun-Jae , Kim Young-Shil , Kim Min-Ki , Seok Ogyun , Han Min-Koo
Published: April 2010

We have fabricated AlGaN/GaN high-electron-mobility transistors (HEMTs) employing the proposed surface treatment by the deposition and removal of a SiO2 layer. The proposed treatment was applied before the Schottky contact formation. The output DC characteristics of the conventional and proposed devices were almost identical. The same threshold voltage indicates that the deposited SiO2 layer on the proposed device was completely eliminated. The proposed device decreased its leakage current by more than three orders compared with the conventional device and achieved a high breakdown voltage of 1300 V. The improvement in the blocking characteristics of the proposed device is due to the suppression of buffer leakage current, which is induced by the elimination of native oxide and the effect of N2O plasma on the surface of the AlGaN/GaN heterostructure.
GaN Metal–Oxide–Semiconductor Field-Effect Transistor with Tetraethylorthosilicate SiO2 Gate Insulator on AlGaN/GaN Heterostructure
Authors: Ao Jin-Ping , Nakatani Katsutoshi , Ohmuro Keisuke , Sugimoto Masahiro , Hu Cheng-Yu , Sogawa Yuji , Ohno Yasuo
Published: April 2010

GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) with a tetraethylorthosilicate (TEOS) SiO2 insulator were developed and evaluated using an AlGaN/GaN HFET structure as the source and drain regions. Operation up to a gate voltage of 10 V was realized at a low gate leakage current. A new method of measuring the mobility of a MOSFET was developed to prevent the effect of hysteresis, in which a relay was used to switch between current measurement and capacitance measurement at the same gate voltage. The maximum field-effect mobility is approximately 45 cm2 V-1 s-1 at an interface state density of 1.02 ×1013 cm-2 eV-1.
Low-Resistivity V/Al/Mo/Au Ohmic Contacts on AlGaN/GaN Annealed at Low Temperatures
Authors: Yafune Norimasa , Nagamori Motoi , Chikaoka Hironari , Watanabe Fuminao , Sakuno Keiichi , Kuzuhara Masaaki
Published: April 2010

We investigated the electrical characteristics of V/Al/Mo/Au ohmic contacts on AlGaN/GaN heterostructure field effect transistors (HFETs). A minimum ohmic contact resistivity of 1.6×10-6 Ω cm2 was achieved after annealing at 550 °C by optimizing V thickness to 15 nm. Cross-sectional transmission electron microscope (TEM) images exhibited a large difference in the extent of metal reaction between V/Al/Mo/Au and Ti/Al/Mo/Au. In addition to their lower contact resistivities, the low-temperature annealed V/Al/Mo/Au ohmic contacts exhibited better characteristics, such as enhanced breakdown voltages by about 100 V and smooth surface morphology, than the Ti/Al/Mo/Au ohmic contact annealed at the optimum annealing temperature.
Metal–Insulator–Semiconductor Diode Characterization on n-GaN by Capacitance–Voltage Measurement at 150 °C
Authors: Hu Cheng-Yu , Nokubo Hiroyuki , Okada Masanari , Ao Jin-Ping , Ohno Yasuo
Published: April 2010

GaN metal–insulator–semiconductor (MIS) diodes (MISDs) were evaluated with capacitance–voltage (C–V) measurement at 150 °C and under UV light illumination. From C–V scan at 150 °C, a high density of SiO2/GaN interface traps was found to pin the semiconductor surface potential (ΦS) at 0.7–0.9 eV. At -20 V, transient capacitance measurement was performed at 150 °C under dark condition or after 5 min UV light illumination. From the transient measurements, ΦS of the steady status was measured to be 4.2 eV, which is much larger than the band gap of GaN, indicating that no thermal equilibrium was achieved at the steady status. The reason for the absence of thermal equilibrium was discussed. It was suggested that the leakage through the oxide is too large compared with the electron–hole generation rate in this wide-band-gap semiconductor. The insulative properties of conventional insulators should be reevaluated for wide-band-gap semiconductors.
Temperature Dependence of the Resistance of AlGaN/GaN Heterostructures and Their Applications as Temperature Sensors
Authors: Zahmani Abdeldjelil Habib , Nishijima Akira , Morimoto Yoshitaka , Wang Heng , Li Jing-Feng , Sandhu Adarsh
Published: April 2010

AlGaN/GaN heterostructures with a two-dimensional electron gas (2DEG) exhibit unique transport properties that could potentially be used for novel applications that are not related to conventional modulation-doped field effect transistor devices. Here, we describe the fabrication of high sensitivity temperature sensors exploiting temperature induced resistance changes of AlGaN/GaN-2DEG heterostructures. We observed a monotonous change in the resistance of the 2DEG from 3 to 1000 K. The temperature dependence of the resistance above 180 K fitted the Callender–Van Dusen equation. The sensitivity of the AlGaN/GaN temperature sensors was more than 2 times higher than conventional resistance temperature detectors near room temperature and 5 times higher at about 900 K. These new AlGaN/GaN temperature sensors may find niche applications in extreme environments, such as space exploration, as well as where high sensitivity is required over wide temperature ranges.
The Study of Stress Effects in GaN Epilayers on Very Thin Sapphire Substrates Using Chemical Mechanical Polishing Technique
Authors: Su Yan-Kuin , Kao Chien-Chih , Lin Chuing-Liang , Chen Jian-Jhong
Published: April 2010

The wafer bonding process and chemical mechanical polishing (CMP) technique are used to remove the sapphire substrate for fabricating the thin-GaN light emitting diodes (LEDs). The stress effects in GaN epilayers on very thin sapphire substrates are analyzed by Raman spectroscopy and photoluminescence (PL). By reducing the thickness of the sapphire substrate from 450 µm to the range between 1.1 and 20.3 µm, the compressive stress in GaN epilayers will be almost released. By analyzing the main scattering signal of E2 (high) mode, the sample with thinnest sapphire of 1.1 µm exhibits 248.3 MPa stress relaxation which is obtained from the Raman shift Δω of 1.54 cm-1. By analyzing the variation of the biaxial stress with sapphire thickness, the relationship between the Raman wavenumbers ω (in cm-1) and residual sapphire thicknesses d (in µm) can be expressed by ω=569.51-1.92×exp
(-d/5.81) (cm-1). Finally, an almost linear relationship between residual sapphire thickness and energy bandgap of GaN films was also observed during the CMP process.
Effect of Post-Thermal Annealing of Thin-Film Transistors with ZnO Channel Layer Fabricated by Atomic Layer Deposition
Authors: Kawamura Yumi , Horita Masahiro , Uraoka Yukiharu
Published: April 2010

We investigated zinc oxide (ZnO) thin films fabricated by atomic layer deposition (ALD) for their application in thin-film transistors (TFTs). The fabricated TFTs were annealed at various temperatures in various ambient gases. The characteristics of TFTs annealed in oxygen ambient at the temperature of up to 400 °C indicated improvements with no degradation of subthreshold swing or large shift in threshold voltage. From the annealing temperature dependences of transfer characteristics and X-ray diffraction patterns, we found that the improvements in electrical characteristics are attributed to the crystalline modification of ZnO films. The TFTs annealed at 400 °C in O2ambient indicate improved stability against the bias stress. Secondary ion mass spectrometry analysis revealed a marked decrease in the hydrogen concentration of the ZnO channel layer after the annealing at 400 °C.