bluuebunny/crossref_metadata_2025 huggingface dataset:
Impact of etch factor on characteristic impedance, crosstalk and board density
Authors: Renbi Abdelghani , Risseh Arash , Qvarnström Rikard , Delsing Jerker
Published: October 2015

Signal integrity becomes more important when the length of the Printed Wiring Board (PWB) traces surpasses where λ denotes the wavelength. For fast digital communication purpose and low energy consumption in CMOS technology, faster rise time of the clock which means higher harmonic frequency, has always been preferable. In this case, the importance of considering signal integrity gets a higher priority as issues such reections and crosstalk between adjacent traces cannot be omitted, especially in dense High Density Interconnect (HDI) boards. Several factors control the effect of reections and the crosstalk such as the shape and dimension of the traces, the isolator characteristics which is inserted between the trace and the ground plane, the nearness and the geometry of the nearby conductors. In other words, these factors control the characteristic impedance of the traces and the mutual inductances and capacitances between the adjacent traces. Although these factors have been taken into account during the design phase for good signal integrity, the manufacturing process, which differs from vendor to vendor, has a great impact on the above factors. PWB manufacturing process may result in many different variations, which involve the dielectric constant, the thickness of the insulator, the trace width and the copper foil thickness. In addition to these variations, the etching quality that falls mainly in three different categories of trapezoidal trace form. In this paper we present the effect of three different etching shapes on the characteristic impedance. Moreover, it is concluded that one could gain space which can be used for shrinking the electronics and/or saving the raw material when trading the characteristic impedance error for space. Similar method is followed to investigate the crosstalk reduction between two adjacent microstriplines when tolerating the error in the characteristic impedance. This procedure can only be applied when a 90° etch angle process is feasible.
Propagation Delay Analysis in 3D Stacked Memory using Novel MOS Depletion Layer Modeling Approach for Through Silicon Via
Authors: Kannan Kaushal , Harihara Sarma G. , Kannan Sukeshwar
Published: October 2015

This paper presents the physical level design analysis of 3D stacked memory ICs with Through Silicon Via (TSV) to compute the propagation delay. The difficulties in incorporating TSVs for 3D ICs are that TSV has additional complex parasitics, process based variations, and structure based reliability issues, thus warranting detailed modeling and analysis. TSVs are known to have a MOS structure which has been rigorously studied to evaluate the overall TSV performance and the effect of variable wafer doping profiles has been included in our analysis. Our proposed TSV model provides the IC designer with the yardstick for optimum TSV pitch. Furthermore, our model considers the TSVs to have a variable capacitor which enables frequency selective characteristics based on signal strength and operating frequency. Finally, we have incorporated our model towards optimization of memory array size in 3D stacked DRAMs while taking into account the key factors of TSV delay for a given process node and TSV pitch. This exhaustive analysis would help to choose optimum memory array size while stacking, without degradation in overall 3D Dynamic Random Access Memory (DRAM) performance, and can be effectively used as a primary guideline during memory stacking and layout for optimum bandwidth.
Meander Delay Compensation in High-Speed Digital Multilayer Packages
Authors: Frye Robert , Liu Kai
Published: October 2015

The routing of multi-trace digital signal buses in printed circuit boards often results in mismatches in the lengths of the lines. This results in mismatched propagation time, referred to as “timing skew” in a digital system. A common method that is used to compensate for this is to add meander sections of line to lengthen the signal path length. Many advanced circuit board design tools have the capability to perform this compensation automatically.

Advanced Ball Grid Array (BGA) packages are fabricated using fine-line multilayer laminate substrates or they are built up using multilayer wafer-scale processes. The design tools for these types of packages have evolved from printed circuit board tools and typically use the same methods and principles. It is very common in BGA packages for high-speed digital applications to use meander trace patterns to match the trace lengths of high speed bus interconnections either from the chip to the solder balls or between chips in a multi-chip package.

However, electromagnetic simulation of these packages shows that despite the use of these techniques to match the physical length of the traces, electrical lengths often vary by as much as a factor of two. Examples of such packages are presented and analyzed. The resulting timing skew is not a significant problem in most current applications, since the overall delay is small compared with the clock interval. But with emerging applications pushing well beyond 10Gb/s, timing skew in packages will be an important consideration.

The reasons for the ineffectiveness of meander delay compensation are discussed, and are demonstrated by some simple simulations.
Simulation and Experiment of Molded Underfill Voids
Authors: Chae MyoungSu , Ouyang Eric , Chung JaeHan , Yu DokOk , Gu SeonMo , Kim Gwang , Ahn Billy
Published: October 2015

The molded underfill (MUF) has become one of the trends in the IC packaging industry due to its simplification of assembly process steps and the saving of the cost. However, for the fine pitch flip chip bumping array, the void generation is one serious issue causing the short of the electrical connections and the cracking of the bumps. In this paper, the main focus is to predict the void generation and to compare with the experimental data. The early stage FEM numerical simulation not only can predict the risk of voids but also provide the best economic approach without the need to spend trial and error budget. A multiple segments substrate strip, with totally 64 packages populated on it, is used in the experiment. The manufacturing process parameters are programmed and recorded for comparison. The filling, packing, and curing of molding compound are carefully chosen in order to compare their effects. After the assembly process, each package is scanned with C-SAM inspection to check if the voids appear. For FEM numerical simulation, only one segment of the substrate strip, with totally 16 packages, is modeled to save computational resources and time. However, all the bumps, on each of the package, are modeled in order to check how the flow field is affected by the packages. In conclusion, we have obtained good match of experimental vs. simulation data. The prediction of voiding location is very close to each other.
Managing Voids in Underfill Process with 5-micron Gap Under Large Die
Authors: Liang Hanzhuang , Asymtek Nordson
Published: October 2015

Microelectronic packaging is continuously becoming smaller and denser, thus allowing for more functionalities and smaller devices including portable products. Flip-chip among other technologies continues to enable such trends. In fact denser arrays such as copper pillars or micro bumps of various metallurgies seem to be the technology of choice for the near future electronic interconnect. A technique is reviewed for successfully underfilling a 3cm2 Indium Phosphide flip-chip die mounted on a silicon substrate with 5 microns gap and large number of I/O (about 0.3 million indium bumps) connected in daisy chains. The method that resulted in a void-free underfill consisted of line dispensing along one side of the die such that the flow of the capillary fluid was normal to the direction of the daisy chains. For dot-dispense, substrate surface treatment and more careful design of dispense sequence helped to reduce voids. This study was compared to a manual dot-dispense technique that was unable to meet production throughput requirement, accuracy, repeatability and void-free. Achievement of void-free automated underfill into a 5-micron gap with complex features underneath a large flip chips will encourage today's microelectronic packaging industry to meet the challenges of smaller and denser components.
Pd-coated Cu Wire Bonding Reliability Requirement for Device Design, Process Optimization and Testing
Authors: Singh Inderjit , Low Shin , Song Syu Fu , Jung Chen Shih , San Lin Ming , Qin Ivy , Huynh Cuong , Clauberg Horst , Nguyen Son Truong , Chylak Bob , Xu Hui , Acoff Viola L.
Published: October 2015

One of the biggest technology drivers in the semiconductor industry today is the fast transition from Au wire bonding to Cu wire bonding. The fast adaptation of Cu and Pd-coated Cu (PCC) wire has focused the whole packaging industry to develop understanding, equipment and processes that can produce a more reliable and robust Cu wire bonding technology.

Although the fundamentals of wire bonding technology are very similar between Au and Cu wire bonding, there are a lot of new challenges in Cu wire bonding. Compared to Au wire bonding, Cu wire bonding needs different bond quality measures and metrology. Traditional ball diameter, ball height and shear measurements are not adequate to quantify a Cu wire bonding process. Some of the additional bond quality measures include pad material push out (pad splash), Al layer peel off (pad peel) and crack in the barrier and dielectric layer (pad crack).

Another area that is quite different between Au and Cu is the reliability test requirement. In Au wire bonding, because of the fast intermetallic compound (IMC) growth rate, the HTS test is normally the hardest to pass. Due to the corrosion of Cu wire, the HAST test is the most challenging in Cu wire bonding. Reliability requirements still need more knowledge. In this paper, we conduct reliability tests for devices with 3 sets of wire bonding parameters. The bonded samples have IMC coverage between 94% and 97%, well above the industry level of 80%. The reliability (HAST) test passed for all samples at 96 hours. However, there are some failures in the HAST test at 192 hr. There are many factors that can influence reliability outcome including wire bonding and non-wire bonding related factors. The failure analysis identified two potential causes in our case. In one failure case, an abnormally high Chlorine level and void in molding compound were detected next to the failed bond while no Chlorine and void were detected elsewhere. In the 2nd failure case, the bonded ball seems to be off centered and results in poor bonded ball to pad interface. These two factors will be more tightly controlled in future tests to verify the reliability outcome.

Intermetallic growth and phase transformation, aluminum oxide, and behavior of palladium in PdCu wire bonds are analyzed using transmission electron microscopy (TEM) of dual beam focused ion beam (FIB) thinned specimens. Results are compared to wire bonding measurement and reliability outcome.
Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks
Authors: Shelton Doug , (Charles) Wang C.Y.
Published: October 2015

Canon Litho Products support Vertical Lithography challenges required by TSV and advanced packaging applications that support “More-than-Moore” advancements. Vertical Lithography challenges include accurately performing backside, infrared alignment to distorted bonded-wafer grids and imaging through thick resist films.

This paper will provide examples illustrating severe wafer distortion that can be experienced after wafer thinning and the impact of overlay and imaging control. This paper will also introduce Canon stepper features that are designed to address Vertical Lithography challenges including the Canon Through-Silicon Alignment (TSA) System and advanced Projection Lens. Grid distortion characterization data and stepper compensation results are presented to illustrate Canon stepper technology performance under severe process conditions.
Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate
Authors: Orii Yasumitsu , Toriyama Kazushige , Kohara Sayuri , Noma Hirokazu , Okamoto Keishi , Uenishi Keisuke
Published: October 2015

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.
Control of Package Warpage by Package Substrate Design for Low Profile Package-on-Package Structure
Authors: Furusawa Takeshi , Kawamura Naomi , Furutani Toshiki , Kariya Takashi
Published: October 2015

In recent years, with increasing demand for high-density assembly in mobile electronics products, a package-on-package (PoP) structure has been standardized. The demand for lowering the PoP profile is getting stronger as consumers demand thinner mobile devices. To assemble a low profile PoP and mount it on a mother board, it is necessary to have a precise warpage control of PoP components, including its bottom package. It is expected that a flip-chip chip-scale-package (FCCSP) with thin mold cap will be used as the bottom package of the PoP in the next 2–3 years. In order to control the package warpage, it is necessary to optimize a large number of parameters related to the package substrate, silicon die and mold compound. Among them, equivalent coefficient of thermal expansion (CTE) of the package substrate is one of the most important factors.

In this paper, control of the package warpage was studied by focusing on the glass-cloth content ratio in the package substrate. Glass-cloth has the lowest CTE among the constituent materials of the substrate, so it contributes to reduce the equivalent CTE of the substrate. To maximize the glass-cloth content, a substrate with a thick core and thin build-up structure was prepared, and the package with thin mold cap was subsequently formed. Compared with a similar package with a conventional substrate structure, its warpage, measured experimentally, was about 20% smaller. Consequently, it was concluded that the glass-cloth content ratio is a key factor to control package warpage behavior in the PoP assembly process.
Low Temperature Hybrid Bonding of Organic/Inorganic Substrates at Atmospheric Pressure
Authors: Shigetou Akitsu
Published: October 2015

Homo- and heterogeneous bonding of Cu, SiO2, and polyimides, by using a single vapor-assisted surface activation method at 150 °C and atmospheric pressure, is highly feasible and will be of practical use in three-dimensional hetero-integration of thin, flat interconnection layers where the surfaces of electrodes and insulation layer appear on the same plane. Since it is necessary to achieve good bondability to diverse materials in a single process in order to obtain such a “bumpless” hybrid structure, we have to create a compatible bridging layer at low temperature. Bridging layers, based on Cu hydroxide hydrate and silanol and hydroxyl groups formed from SiO2 and a polyimide, respectively, were prepared by introducing water onto the activated surfaces at atmospheric pressure. The growth rate of the bridging layers was tunable via absolute humidity, and an exposure of 8 g/m3 was chosen based on the diffusion distance of Cu atoms. Heating at 150 °C, after exposure to humidity, caused tight adhesion between the mating surfaces for all combinations of starting materials with voidless amorphous interfacial (bridging) layers. Because of the well-controlled layer thickness, a low electrical resistivity of ∼ 4 × 10−8 Ω·m was obtained at the Cu-Cu interface. Furthermore, the preliminary study on the surface treatment using ultraviolet irradiation was carried out to Cu and transparent resin substrate to eliminate the vacuum process.
RF/Microwave Die Attach of Gallium Nitride Devices Achieving Less Than 1% Voiding in a Flux-Free Environment
Authors: Zappella Pierino I , Barnes Paul W , Muhs David , Wilson Bruce
Published: October 2015

High power devices operating at high temperatures are sources of excessive heat generation, whether the application is automotive, RF/Microwave, military, or commercial power components. Removal of this excessive heat is necessary not only for proper operation of the device, but also for longevity and reliable performance. The attachment interface between a high power device and a particular substrate, whether metal, sapphire, ceramic, or other exotic material, must be essentially void free. Voids consisting of air pockets are very poor thermal conductors and jeopardize the efficient heat transfer to the heat sink or substrate. Reducing or eliminating voids is paramount to a successful die attach and may be verified by either X-Ray or SAM (scanning acoustical microscopy). Our studies consisted of soldering a gallium nitride die to a copper tungsten thermal spreader using an Au80Sn20 solder preform. The equipment used was a dedicated vacuum/pressure reflow furnace which has the capabilities to reduce voids by using a pressure differential controlled process. Our findings will review the successful achievement of essentially void free die attach with a void level of less than 1% as verified by X-Ray and SAM scans. As a result of not using flux and achieving a void free solder interface, long term reliability is enhanced due to the absence of corrosive flux residue which would likely degrade the device over time.
A Numerical Study of Single Phase Dielectric Fluid Immersion Cooling of Multichip Modules
Authors: Knight Roy W. , Fincher Seth , Bhavnani Sushil H. , Harris Daniel K. , Johnson R. Wayne
Published: October 2015

Immersion, single phase free convection cooling of multichip modules on a printed circuit board in a pool of dielectric fluid was examined numerically, with experimental verification of baseline cases. A multi-chip module with multiple thermal test cells with temperature sensing capability was simulated. The commercially available computational fluid dynamics program from ANSYS, Fluent, was used with the electronics packaging front end, Icepak, employed to create the models and compact conduction modules. Simulations were first performed of an experimental test vehicle which had five 18 mm by 18 mm die, arranged in a cross pattern, equally spaced die, 25 mm between them. Two of the die were aligned vertically with the center die, two aligned horizontally with it. The board was suspended vertically in a large pool of dielectric fluid. Heat was dissipated in the die at a flux of up to 2 W/cm2, based on the die surface area. Simulation results were compared with experimentally measured die temperature values and excellent agreement was seen for the cases of one die heated and all five die uniformly heated with the board cooled by FC-72. A numerical parametric study was performed to examine the effect of die size and spacing on temperature rise. In addition to FC-72, immersion cooling in Novec 649 and HFE 7100 were modeled. Design guidelines are suggested for dielectric fluid immersion cooled multichip modules.
How to Deal with Resonances in Wirebonding
Authors: Sedlmair Josef , Nacke Uwe
Published: October 2015

Resonance effects can seriously impede or prevent wire bond formation. The two major kinds of resonance are discussed: sharp resonances on eigenfrequencies and passive, following resonances. Changing the ultrasonic frequency will remove the true resonance while the passive resonance is independent of the US frequency and can only be cured by the right fixation of the bonded parts.
Novel ESD Protection Scheme for Testing High Voltage LDMOS
Authors: Kannan Sukeshwar , Kim Bruce , Taenzler Friedrich , Antley Richard , Moushegian Ken
Published: October 2015

This paper presents a novel protection circuit for Electrostatic Discharge (ESD) for testing high-voltage devices using Silicon Controlled Rectifiers (SCRs). ESD related issues lead to test equipment damage, hence efficient protection techniques play a very critical role in testing high voltage devices. High-Voltage Laterally-Diffused MOSs (HV-LDMOSs) is extensively used for high voltage applications due to its advantages over other metal oxide semiconductor structures. In high voltage devices ESD protection is generally provided between the drain and source terminals. We have implemented SCRs as the ESD protection circuit for the drain connection in HV-LDMOSs. We have developed ESD stress models using conventional techniques such as human body, machine and charged device models for the high-voltage devices and implement SCRs as protection circuit in the high-voltage DIBs. Simulation has been completed to obtain the ESD stress data of the device. This ESD stress model data can be used to automate our testing process by incorporating the novel ESD protection scheme on a newly developed test software tool.
A Novel OPC Technique for 2D Critical Dimension Optimization of Sub-micron Patterns using an Experimental Methodology
Authors: Pak Murat , Yilmaz Zeliha , Ersoy Aylin
Published: October 2015

As the development of the ULSI technique with respect to the decrease in the feature sizes, critical dimension has become a vital parameter for the IC manufacturing. For sub-micron technologies, there has always been a significant mismatch between the layout and post lithography patterns. Since most of the conventional optimization techniques are model based, it is quite hard to obtain a good accuracy for a real-world solution. Moreover, these methods can not easily be integrated to any fabrication environment. This paper presents a layout correction technique which uses a look-up table of measured patterns with 0.3um and 0.4um critical dimensions. An interpolation method that takes the design grids into account has been used to obtain the optimum layout for sub-micron ULSI circuits. This paper not only focuses on an experimental and accurate critical dimension optimization, but also draws attention how to implement this methodology for any fabrication environment.
ULTRA THIN CHIPS STACKING ON TSV SILICON INTERPOSER USING BACK-TO-FACE TECHNOLOGY
Authors: Parès G. , Schnegg F. , Attard A. , Cruau D. , De Crecy F. , N'hari A. , Anciant R. , Klug G. , Luesebrink H. , Martinschitz K. , Karoui C. , Simon G.
Published: October 2015

Chip-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by on one hand the increase of the die surface and the number of I/Os and on the other hand by the reduction of the vertical dimensions.

In our integration, the chips are reported on a silicon interposer containing copper via-middle TSVs. Two different approaches have been considered to realize chip-to-wafer stacking with respectively 35 and 20 μm ultra-thin dies. The first one is the conventional flip chip (or Face-to-Face, F2F) integration based on Cu/SAC μ-pillar connections while the second is a less classical Back-to-Face (B2F) way based on the realization of a high topology RDL after bonding the chips face up on the silicon interposer using a polymer. This last architecture becomes more and more attractive with the reduction of the chip thickness to ultra-thin dimension and can offer substantial advantages in terms of design flexibility and technology cost.

Chip bonding is one of the first tasks to address: several bonding materials have been tested either on die side using die attach film (DAF) or on bottom interposer side using wafer level spin coated polymers. Then a novel brick consisting of high topology encapsulation and metallization has been fully developed to connect the dies to the bottom wafer enabled by the development of a specific lithography process.

Thermo-mechanical FEM simulation and first reliability assessment have been carried out and support the good mechanical behavior of this integration.

Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnections in terms of resistances and yield at front side level but also at back side level after TSV exposure.

Back to Face integration can be very attractive in terms of process complexity and cost for ultra-thin chips with limited I/Os counts.
Thermal Characterization and Simulation of a fcBGA-H device
Authors: Ouyang Eric , He Weikun , Jeong YongHyuk , Chae MyoungSu , Gu SeonMo , Kim Gwang , Ahn Billy
Published: October 2015

In this paper, the thermal performance data of theta jc (Rth-JC) and theta ja (Rth-JA) of a flip chip ball grid array device with heat spreader, fcBGA-H, is measured. For Rth-JC, various boundary conditions for the thermal resistance modeling are considered and discussed. A transient measurement method is used to obtain the temperature responses of the diodes, as a function of time. The structure functions of the diodes are measured, and based on the structure functions, the thermal resistances are calculated. With the structure functions, the impact of package configurations are better viewed and demonstrated, and a novice measurement technique is also proposed here to measure the thermal resistance of junction to die, Rth-JD. With this experimental setup, there is no need to use the thermal couples. The traditional drilling hole for thermal couple and thermal couple itself will change the package configuration and heat dissipation path, and, therefore, impact the accuracy of the measurements.
Design Optimization of Micro-channel Heat Exchanger embedded in LTCC
Authors: Aravelli Aparna , Rao Singiresu S. , Adluru Hari K.
Published: October 2015

Increase in the density of electronic packaging leads to the investigation of highly efficient thermal management systems. The challenge in these micro-systems is to maximize heat transfer per unit volume. In the author's previous work, experimental and computational analysis has been performed on LTCC substrates using embedded silver vias. This novel technique of embedding silver vias along with forced convection resulted in higher heat transfer rates. The present work further investigates into the optimization of this model. A Multi-objective optimization problem has been formulated for the heat transfer in the LTCC model. The Log Mean Temperature Difference (LMTD) method of heat exchangers has been used in the formulation. Optimization is done based on maximization of the total heat transferred and minimization of the coolant pumping power. Structural and thermal design variables are considered to meet the manufacturability and energy requirements. Demanded pressure loss and volume of the silver metal are used as constraints. The classical optimization technique Sequential Quadratic Programming (SQP) is used to solve the micro-heat exchanger problem. The optimal design is presented and sensitivity analysis results are discussed.
Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter
Authors: Dohle Rainer , Härter Stefan , Wirth Andreas , Goßler Jörg , Gorywoda Marek , Reinhardt Andreas , Franke Jörg
Published: October 2015

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed.

For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2].

For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side.

A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.
Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications
Authors: Schuler Jennifer D , Shih Chia-Hsin , Arvin Charles L , Kim KyungMoon , Perfecto Eric
Published: October 2015

Pb-free SnAg solder has become the industry standard for fabricating flip chip interconnects utilizing C4 (controlled collapse chip connection) technology. One area of interest for manufacturability of Pb-free solders is the ability to control and measure the %Ag composition and its variation from wafer to wafer, chip to chip, and C4 to C4.

There are various ways to measure solder composition. These are divided into two categories which are invasive and non-invasive referring to whether solder must be removed from the wafer in order to conduct the measurement.

There are a variety of invasive methods including Atomic Absorption (AA), Differential Scanning Calorimetry (DSC), Inductively Coupled Plasma (ICP) and Electron Probe Micro-Analyzer (EPMA) used with cross sections. Non-invasive methods are limited, making the development of the non-invasive X-Ray Fluorescence (XRF) method an important technique to determine both the thickness and composition of C4s on wafers without modifying the wafer.

There are many factors which can affect the accuracy of the XRF measurements. These include bump geometry, composition, UBM (under bump metallurgy) stack, bump spatial density, underlying chip wiring, tool vibration and tool parameters, such as collimator size, power levels, scan time, etc.

This paper will address the implementation issues in utilizing XRF for Pb-free solder SnAg systems. The paper will describe:(1) Experimental bumping variables,(2) XRF configuration, calibration, optimized measuring methodology and the importance of having known standards with the same dimensions of the bumps being measured(3) Measuring accuracy and correlation with ICP and DSC,(4) Ag distribution study in the die and wafer level
Additive Manufacturing of Fine Lines and Embedded Electronics for use in Chip Carriers and Microelectronic Systems
Authors: Lauer Scott , Little Whitten , Benci Pier , Schmitt Tim , Mazurowski John
Published: October 2015

Additive manufacturing is the application of layer manufacturing techniques to fabricate microelectronic products. These techniques differentiate themselves from incumbent technologies in that they only add material to build the device and are an alternative to subtractive technologies such as lithography that globally coat layers and then etch-away unrequired materials. In this paper we discuss an additive technology that performs material evaporation through shadow masks. This process has shown significant potential for the fabrication of chip packaging, microelectronic devices and circuitry; specifically, high density interposers, fine conductor lines and embedded components such as capacitors, resistors, and transistors. The process is compatible with a number of both rigid and flexible substrates and deposition materials. Examples of devices and lines that have been manufactured by this technique are shown and discussed. Preliminary test data shows line / space resolution that has reached 15 / 30 microns and better.
Development of Printed Power Packaging for a High Voltage SiC Module
Authors: KE Haotao , Hopkins Douglas C
Published: October 2015

Due to rapidly developing post silicon power devices, in particular SiC and GaN, three primary parameters in power packaging: temperature, voltage and current, are much more difficult to manage. The SiC devices are being developed for high voltage (>15kV). The GaN devices will have extremely low internal resistance, operate at extreme current densities (≫10A/mm2), and can account for <50% of the resistance in a power module. Both devices can operate at high temperatures (>300°C) and >10-times frequency compared to Si. The traditional power electronics packaging approaches need augmentation or replacement. Most technologies used in packaging of power electronic systems, or more generally Electronic Energy Systems, are ported from microelectronics. The recent development of printable 3D circuit techniques, e.g. jetting and dispensing, provide additional major approaches applicable to power packaging. Some printing techniques are already applied to solar cells and batteries. This paper explores the printable electronics technologies for application to power.
Thermomechanical Design for Fine Pitch 3D-IC Packages
Authors: Horibe Akihiro , Kohara Sayuri , Sueoka Kuniaki , Matsumoto Keiji , Orii Yasumitsu , Yamada Fumiaki
Published: October 2015

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.
Thinner and Miniaturization Embedded Device Package, MCeP, for PoP and Module Application
Authors: Tanaka Kouichi , Kurashima Nobuyuki , Iizuka Hajime , Ooi Kiyoshi , Machida Yoshihiro , Shiraki Satoshi , Koyama Tetsuya
Published: October 2015

Along with miniaturization and high functionality of electronics, many embedded device substrates and packages have been developed by various companies. We have been also developing embedded device package named MCeP, Molded Core embedded Package. This package consists of base substrate, upper substrate and molding resin. These substrates material is conventional organic base. Bare IC devices without re-routing are mounted on inner surface of base substrate. Upper substrate and base substrate are connected electrically by copper core solder balls. The space between upper and base substrate is encapsulated by molding resin.

MCeP is possible to be adopted for bottom package alternative of PoP. For thinner PoP application less than 1.0mm height, thinner MCeP less than 300um has been investigated. Base substrate has 3 conductive layers and thickness is 130um. Upper substrate has 2 conductive layers and thickness is 95um. Embedded layer thickness is 52.5um.

For original MCeP, IC device is mounted by flip chip bonding using Au bump and tin-silver solder interconnection. The space between IC device and base substrate is encapsulated by under-filling resin. It is necessary to keep under-filling resin flow area around IC device. Because of this resin flow area, package size should be enlarged. To miniaturize package size, solder bumped IC device and encapsulation by molding resin instead of under-filling resin were used, then resin flow area was eliminated.

MCeP is possible to use bottom package alternative for PoP and module application with IC device and passive components embedded.
2.5 / 3D PACKAGING TECHNOLOGY SOLUTION FOR HIGH FREQUENCY DEVICE.
Authors: Morikawa Yasuhiro , Murayama Takahide , Sakuishi Toshiyuki , Suu Koukou
Published: October 2015

“2.5D silicon interposers” and “Hetero 3D stacked” technology for high-performance LSI are gathering the most attention from now on. These technologies can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked each function devises. 2.5D and hetero-3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the TSV production cost is not still solved. In particular, the demand to a new plating bath technology to shorten Cu plating time is expected. On the other hand, TSV isolation liner materials with lower cost for high frequency devices will be necessary in the future. “Scallop-free” etching process has developed for TSV fabrication [1]. As a result, the smooth-sidewall had proved shorten PVD process time [2]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electro-chemical plating) in this paper. And then, a polyurea film using a vapor deposition polymerization technology (which is Ulvac's FPF/PV large panel technology) tried introduction as isolation liner for next-generation high frequency device. And, it performed the film formation to a TSV pattern.
Application of Low-k Liner for Stress and Capacitance Control in Cu-TSV
Authors: Tan C. S. , Zhang L. , Li H.Y. , Yoo W.
Published: October 2015

Through silicon via (TSV) is commonly fabricated by high aspect ratio deep silicon etching, lining with dielectric layer for electrical isolation and super-conformal filing with copper. It has been reported that Cu-TSV can exert thermo-mechanical stress on Si due to coefficient of thermal expansion (CTE) mismatch. This stress can result in undesired device mobility variation and structural reliability. In addition, TSV parasitic capacitance has the most predominant impact on the circuit operation. It is therefore imperative to reduce the TSV stress and capacitance. One solution is to use low-k dielectric as the liner since it has much lower elastic modulus and effective permittivity. In this work, low-k dielectric is successfully integrated in TSV as a liner. The implications on TSV stress, capacitance and leakage current are discussed. Due to its smaller elastic modulus (~7.2 GPa), the selected low-k carbon-doped oxide acts as a compliant layer to cushion the Cu-TSV stress on the Si compared with conventional oxide (75 GPa) by plasma enhanced chemical vapor deposition. This effectively reduces the near-surface compressive stress in Si by >25% compared with the conventional liner which is more rigid. Since the low-k liner has an effective dielectric constant of ~2.8, it is found that the integration of the low-k liner reduces the TSV capacitance by ~26% as compared with the conventional oxide liner. In summary, this work has provided evidence of the technical merits of a low-k material to mitigate the undesired Cu-TSV induced stress in the surrounding Si and the related parasitic capacitance.
Using Physics of Failure to Predict System Level Reliability for Avionic Electronics
Authors: Caswell Greg
Published: October 2015

Today's analyses of electronics reliability at the system level typically use a “black box approach”, with relatively poor understanding of the behaviors and performances of such “black boxes” and how they physically and electrically interact. Box level analyses tend to use simplistic empirical predictive models, and the effort is typically driven by cost and time constraints. The incorporation of more rigorous and more informative approaches and techniques needs to better understand and to take advantage of the advances in user interfaces and intelligent data capture, which will allow for a broader range of users and for similar resource allocation. Understanding the Physics of Failure (PoF) is imperative. It is a formalized and structured approach to Failure Analysis/Forensics Engineering that focuses on total learning and not only fixing a particular current problem. It can involve material science, physics and chemistry; also variation theory and probabilistic mechanics. The approach necessitates an up-front understanding of failure mechanisms and variation effects. In this paper we will present an explanation of various physical models that could be deployed through this method, namely, wire bond failures; thermo-mechanical fatigue; and vibration. We will provide insight into how this approach is being accepted by system assemblers, as it allows for failure oriented accelerated testing, for substitution or “what if” analyses in lieu of the traditional accelerated life testing. This paper will also provide insight into a process to develop viable test plans and a tool that facilitates the entire process so that minimal testing is performed, thus reducing costs and schedule impacts. Examples of this approach will be presented.
Solder Joint Reliability Study for Wafer Level Packages on Flexible and Rigid Boards
Authors: Gu Gary , Chadwick Jon , Jin Daniel
Published: October 2015

Applications of Wafer Level Packages (WLPs) have shown tremendous growth in the rapid developing smartphones and other portable electronic devices. The technology trends lead to smaller chip size, low cost, and more integrated functions, but also face higher reliability requirements due to the reduced number of solder bumps as well as smaller bump size and height. New assembly technologies such as flexible phone board and conformal coating also brought up new thermo-mechanical reliability challenges.

Based on 3D finite element modeling, the current studies focus on solder joint reliability of WLPs and compared between flex based and traditional rigid based WLP assemblies. Conformal coated and underfilled WLPs as well as some bump parameters are also studied. The parametric studies were carried out in ANSYS and all models were created by using APDL (ANSYS Parametric Design Language) scripts. Each simulation starts from stress free status set at solder reflow temperature and were subjected to thermal cyclic load between −40 and +125°C with ramp and dwell time. Creep strain was considered for solder alloys and kinematic plastic hardening was considered for other elastic-plastic materials. The solder fatigue life is estimated by using modified Coffin-Manson equation and was compared with available thermal cycling test data. The results show that underfill is still the most effective option and conformal coating can play an important role if the right material is selected. Bump parameters such as height, which have certain effects on the solder reliability on WLP-on-Rigid, have limited impact on WLP-on-Flex assembly.
Moisture Reliability Improvement of a High Performance Depletion Mode 0.15 um Gate PHEMT Process
Authors: Abrokwah Jon , Stanback John , Wang Jerry , Johnson Molly , Jiaa Chi L.
Published: October 2015

Moisture reliability of a 0.15-um gate PHEMT technology for mm-wave applications was investigated. The PHEMT technology is fabricated with a deep UV optical lithography, and typically exhibits transconductance of ~550 mS/mm and fT of ~90 GHz.

Moisture reliability, THBL or BHAST performed at 85% relative humidity, and 95 °C, or 130 °C and 85% RH, respectively, initially showed failures up to 70%, under various process splits. Extensive failure analysis pointed to a number of mechanisms contributing to failure, the key culprit being moisture ingress, enabled by poor quality of SiN, stresses, seams, and voids in the passivation dielectric around the gate topology. Moisture penetrated the SiN to GaAs surface through seams in the dielectric around the gate or regions of high local stress such as gate feeds and ends. A corrosion process ensued with the applied voltage bias on the device drain and gate during the THBL or BHAST environmental stress, leading to GaAs oxidation, metal migration and shorts.

By designing the gate topology appropriately, failures were reduced to the range of 0–3.4 %. Further, using a BCB overcoat, failures were completely eliminated.