bluuebunny/crossref_metadata_2025 huggingface dataset:
Panel selection on high courts
Authors: Alarie Benjamin , Green Andrew , Iacobucci Edward M
Published: October 2015

Outcomes of appeals to high courts will depend in part on the ideological preferences of the justices who decide the appeals. The institutional structure of a high court may affect how far these preferences influence outcomes. The US Supreme Court, for example, hears almost all appeals en banc, which means that there is no opportunity to ‘game’ the outcome by choosing which justices hear the appeal. High courts in other countries such as Canada, the United Kingdom, Australia, and Israel, on the other hand, hear appeals in panels of varying sizes and therefore provide potential opportunities for the choice of panel composition to influence outcomes. However, differing panel sizes also provide the opportunity to use judicial resources more efficiently, such as by tailoring panel size to the importance or difficulty of the particular appeal. In the article, we examine both these potential uses of varying panel sizes using data on how chief justices of the Supreme Court of Canada chose panels over the period from 1954 to 2013. We find some evidence of strategic panel composition but the practical impact of such gaming is negligible. In order to examine non-strategic motivations for why chief justices choose different sizes of panels, we develop a model for optimal choice of panel size. The model suggests that, in the presence of scarce judicial resources, panel sizes can be deliberately adjusted to improve allocative efficiency. Using data from the Supreme Court of Canada over the 1954–2013 period, we uncover evidence consistent with our model’s prescriptions for optimal panel sizes.
Tribunal administration and the duty to consult: A study of the National Energy Board
Authors: Graben Sari , Sinclair Abbey
Published: October 2015

In this study, the authors present evidence that the National Energy Board (NEB) does not evaluate whether the duty to consult has been met by applicants or the Crown for the purposes of regulatory approval. While NEB panels do draw conclusions about the sufficiency of consultation, they are not premised on the legal requirements established by the Supreme Court of Canada or subsequent case law. On the contrary, the authors discover that the NEB has approved nearly 100 per cent of the applications in which consultation remains an issue but it relies on three types of justifications for still recommending approval: (i) that it lacks the jurisdiction to consider the consultation at issue; (ii) that outstanding consultation can be addressed through ongoing consultation; and/or (iii) that there are no impacts on rights. Based on these findings, the authors argue that courts should attend to differences over legality and institutional rationality in guiding tribunal authority. In doing so, courts will be in a better position to identify the effect of these differences on tribunal findings, to understand how courts and governments already rely on these findings irrespective of their quality, and to compel transparency for their generation and use.
Pharmacological basis for the medicinal use of Viola odorata in diarrhea, bronchial asthma and hypertension
Authors: Janbaz Khalid Hussain , Khan Waseem Ullah , Saqib Fatima , Khalid Mamoona
Published: October 2015

Viola odorata is traditionally used in the management of gastrointestinal,  respiratory and vascular disorders. The present study was undertaken to validate its folkloric uses. The application of V. odorata to spontaneous contractions in isolated rabbit jejunum preparation exerted relaxant effect through decrease in magnitude and frequency of contractions. Moreover, it also caused relaxation of K+ (80 mM)-induced contractions and shifted the Ca2+ concentration response curves toward right in isolated jejunum similar to verapamil (standard Ca2+ channel blocker), confirming Ca2+ channel blocking activity. V. odorata also caused relaxation of carbachol (1 µM)- and K+ (80 mM)-induced contractions in isolated rabbit tracheal preparations comparable to verapamil, reflecting that observed relaxant effect may be the outcome of anti-muscarinic and/or Ca2+ channel blocking activities. It also exerted relaxant effect on phenylephrine (1 µM)- and K+ (80 mM)-induced contractions in isolated rabbit aortic preparations thus providing rationale for  its folkloric  uses to treat diarrhea, asthma and hypertension.
Le droit et le principe de précaution : leçons d'Australie
Authors: Giraud Catherine
Published: October 2015

Le principe de précaution est aujourd'hui consacré en droit international, quand bien même ses contours juridiques restent imprécis. L'application du principe en droit australien, inspirée des textes du droit international, révèle des enseignements intéressants sur le contenu juridique et la portée du principe de précaution, une application sujette toutefois aux règles d'incorporation particulières du droit international en Australie. Des textes australiens contemporains de la Conférence de Rio reprennent à leur compte le principe de précaution et font apparaître une définition consensuelle et commune tant en droit international qu'en droit interne. Surtout, les tribunaux apportent des éclaircissements sur la nature et le contenu du principe. Sont ainsi précisés, bien qu'il reste encore quelques zones d'ombre, les seuils de gravité, d'irréversibilité ou d'absence de certitude absolue au-delà desquels le principe de précaution s'applique et des mesures de prévention doivent être prises. La doctrine vient encore faire ses propositions, dont le droit français pourra aussi s'inspirer.
Les tribunaux administratifs face à l'application de la loi du 15 juillet 1994 relative aux oiseaux migrateurs : bilan jurisprudentiel contrasté
Authors: Viguier Jacques
Published: October 2015

Les arrêtés préfectoraux, qui reprennent les dates échelonnées de clôture de la chasse au gibier d'eau et aux oiseaux de passage fixées par la loi du 15 juillet 1994, sont attaqués devant les tribunaux administratifs. Les requérants invoquent une contradiction avec la directive de 1979, telle qu'elle a été interprétée par la décision de la C.J.C.E. du 19 janvier 1994. Les recours présentés devant les tribunaux administratifs visent soit directement l'arrêté préfectoral, soit la décision du préfet refusant de modifier cet arrêté. Lorsque l'illégalité de l'arrêté est retenue par le tribunal administratif, c'est généralement pour défaut de base légale ou contrariété avec la directive de 1979. Le degré de contrôle exercé sur l'arrêté varie suivant les tribunaux administratifs. Il en est de même pour la charge de la preuve qui doit être apportée, suivant les tribunaux, par le préfet ou par l'association requérante. Si l'illégalité est retenue, la sanction normale est l'annulation de l'arrêté, mais les tribunaux administratifs divergent sur l'attribution d'indemnités ou le recours au pouvoir d'injonction.
La convention alpine, la montagne et la souris
Authors: Servoin François
Published: October 2015

Le 6 décembre 1995, dans un climat ambigu, la France ratifiait in extremis la Convention alpine de manière à pouvoir figurer parmi les puissances fondatrices. La Convention ambitieuse continuait l'action menée de longue date par les écologistes allemands, reprise par le gouvernement allemand soucieux de leur appui.

Cette convention instaure des institutions et un cadre général permettant la rédaction de protocoles qui constituent autant de nouveaux accords internationaux. De fait, la Convention elle-même se réduit à un cadre peu innovant en droit français, son application est conditionnée par l'adoption ultérieure de protocoles dont le contenu croise largement les compétences communautaires dans le domaine de l'environnement.

La discussion en France provoqua des réactions vives de la part, principalement, des élus locaux, inquiets de n'avoir pas été associés à un projet, muet sur le développement économique des Alpes. Le débat sur la Convention qui ne vise qu'un seul massif de la montagne française a relancé le thème de l'avenir de la montagne et l'a réorienté sur la Charte européenne de la montagne en préparation au Conseil de l'Europe. En attendant que la discussion porte sur le projet Natura 2000.
Hexacoordinate Ru-based olefin metathesis catalysts with pH-responsive N-heterocyclic carbene (NHC) and N-donor ligands for ROMP reactions in non-aqueous, aqueous and emulsion conditions
Authors: Balof Shawna L , Nix K Owen , Olliff Matthew S , Roessler Sarah E , Saha Arpita , Müller Kevin B , Behrens Ulrich , Valente Edward J , Schanz Hans-Jörg
Published: October 2015

Three new ruthenium alkylidene complexes (PCy3)Cl2(H2ITap)Ru=CHSPh (9), (DMAP)2Cl2(H2ITap)Ru=CHPh (11) and (DMAP)2Cl2(H2ITap)Ru=CHSPh (12) have been synthesized bearing the pH-responsive H2ITap ligand (H2ITap = 1,3-bis(2’,6’-dimethyl-4’-dimethylaminophenyl)-4,5-dihydroimidazol-2-ylidene). Catalysts11and12are additionally ligated by two pH-responsive DMAP ligands. The crystal structure was solved for complex12by X-ray diffraction. In organic, neutral solution, the catalysts are capable of performing standard ring-opening metathesis polymerization (ROMP) and ring closing metathesis (RCM) reactions with standard substrates. The ROMP with complex11is accelerated in the presence of two equiv of H3PO4, but is reduced as soon as the acid amount increased. The metathesis of phenylthiomethylidene catalysts9and12is sluggish at room temperature, but their ROMP can be dramatically accelerated at 60 °C. Complexes11and12are soluble in aqueous acid. They display the ability to perform RCM of diallylmalonic acid (DAMA), however, their conversions are very low amounting only to few turnovers before decomposition. However, both catalysts exhibit outstanding performance in the ROMP of dicyclopentadiene (DCPD) and mixtures of DCPD with cyclooctene (COE) in acidic aqueous microemulsion. With loadings as low as 180 ppm, the catalysts afforded mostly quantitative conversions of these monomers while maintaining the size and shape of the droplets throughout the polymerization process. Furthermore, the coagulate content for all experiments stayed <2%. This represents an unprecedented efficiency in emulsion ROMP based on hydrophilic ruthenium alkylidene complexes.
WOOD PROCESSING BY-PRODUCTS TREATED WITH THE LIGNIN-BASED CONDITIONER AS MULCH FOR SOIL PROTECTION
Authors: SHULGA Galia , BETKERS Talrits , VITOLINA Sanita , NEIBERTE Brigita , VEROVKINS Anrijs , ANNE Olga , AMBRAZAITIENE Dalia , ZUKAUSKAITE Audrone
Published: October 2015

Wood processing by-products such as bark of different wood species and hydrolysis lignin were applied as soil mulch. The lignin-based soil conditioner (LSC) representing a lignin-based polyelectrolyte complex with the different composition (a lignin/polymer mass ratio) was obtained under laboratory conditions and was intended to protect sandy soil from erosion by simultaneous application of a soil conditioner as an adhesive, mulch and plant seeds by hydroseeding. The study revealed the pronounced dependence of the properties of the treated wood-originated mulch on the wood species as well as on the composition, the applied concentration and the application rate of LSC. A comparison of the obtained results showed that the treated hydrolysis lignin was characterised by higher compressive strength, higher water resistance and lower moisture losses from sandy soil for a given LSC composition and application rate than the bark-based mulch. The conditioner concentrations don't have negative impact on the germination of seeds plants of the coastal dune zone.
LED & HB-LED Packaging: Technology & Marketing Trends
Authors: Perkins Jeff
Published: October 2015

If LED lighting is to fulfill the promise it holds across all lighting segments, costs need to drop significantly and production volumes will need to double several times over in the coming years. To achieve both, cost improvements must happen at every level of manufacturing and manufacturing processes must evolve. When talking about LED device costs today, packaging holds the greatest cost saving opportunities. As with many semiconductor devices and for LED devices in particular, wafer level packaging will be a key cost saving move for the future. Much needs to be done and much is being done - this talk will take a look at the full spectrum of developments to bring LED into mainstream lighting applications.
System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages
Authors: Chiriac Victor
Published: October 2015

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated.

Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios.

Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.
Advances in 3D Memory and Logic Devices
Authors: Patti Robert
Published: October 2015

Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D DRAM will be presented along with the plans (and possibly some results) of further integration with other 3D host logic devices. Additionally, results from several other recent 3D integrations will be reviewed.
Contract Wafer Bumping of Compound Semiconductors
Authors: Strandjord Andrew , Teutsch Thorsten , Scheffler Axel , Otto Bernd , Li Jing
Published: October 2015

There are a number of qualified technologies for backend processing of traditional silicon based semiconductors. GaAs wafers have several unique properties that make these established technologies inadequate, including: the presence of air bridges, gold bond pads, and the bulk material properties of the GaAs.

In this paper, we describe a process flow and a set of materials which enable the pad resurfacing, UBM deposition, and solder bumping of GaAs wafers. The gold bond pads are resurfaced using a resist liftoff technology and TiCu sputtering. The combination of these allows for pad resurfacing while protecting the air bridges and GaAs. The UBM is deposited on these new TiCu pads by using a thin film layer to again protect the air bridges and GaAs, followed by electrolessly plating nickel and gold. The solder bumping is accomplished using a laser based sphere drop process which is fluxless. To complete the backend processing, the bumped GaAs wafers are then diced and sorted into waffle packs. Details will be discussed relative to the processing conditions, materials used, and yields.
Nano-Porous Gold Interconnect
Authors: Oppermann Hermann , Dietrich Lothar , Klein Matthias , Wunderle Bernhard , Reichl Herbert
Published: October 2015

Pure metal contacts offer some advantage as high thermal and electrical conductivity, ductile deformation behavior and reduction of mechanical peak stresses. They are used in flip chip assemblies as gold bumps, in die attach as sintered silver powder or as gold layer on very smooth surfaces for wafer bonding. Analyzing the demands in most suitable material properties we were looking for a compressible metal contact, which could compensate for all implanarities, with a highly reactive surface to reduce bonding temperature. It should be a noble metal, but with good adhesion to polymers.

We have developed a nanoporous metal layer processed by electroplating a silver-gold alloy with 20 to 30% gold. High plating rates could be achieved exceeding those of standard gold electrolytes. Subsequent de-alloying by etching off the silver provides a nano-porous gold layer as an open-porous sponge with 70 to 80% porosity. Pore and ligament size were measured from different samples between 20 to 100 nm. Aging experiments showed the coarsening of pore size.

We have successfully plated nano-sponge layer of 10 μm height on top of gold bumps on wafer level. But we don't see a limitation yet to further increase the thickness of gold nano-sponge. Chips were bonded by thermocompression resulting in a reduction of bump height without changing the bump diameter. At lower bond force and lower bond temperature the collapse of the porous structure occurred in the bond interface mainly, leaving the porosity in most of the bump volume unchanged.

This leads to a new interconnect structure of high porosity. For very high porosity stiffness should be reduced with the square of the volume ratio. We therefore expect improved reliability due to the reduction in stiffness.

Due to the compressible deformation behavior of the nano-sponge it could improve the yield during wafer-to-wafer bonding and stacking as the particle will be absorbed into the sponge. This allows bonding of wafers without the need of planarization the dielectric layer, e.g. due to steps over conductor lines. Therefore we will use the nano-sponge in stacking and 3D integration.

Beside compression bonding and sintering we use the nano-sponge also as a thermal interface for adhesives. Filler particles are pressed into the sponge structure leading to a larger contact area between particle and substrate surface, thereby the adhesive matrix can penetrate into the open porous film. The locking interface should also provide very high adhesion strength.
Electromigration Performance of WLPs with Standard and Polymer Core Balls
Authors: Nguyen L. , Nguyen H. , Prabhu A.
Published: October 2015

This talk will compare the electromigration performance of wafer level packages having standard SnAgCu solder with those having solder balls with polymer cores. Information on package construction, process, and board level reliability of packages having balls with polymer cores was presented earlier (2009 International Wafer Level Packaging Conference, San Jose, CA). In the new ball variation, the structure is made of a large solid polymer core, which is plated with a thin layer of copper and covered with a layer of SnAg. The polymer core within the solder ball ensures that the standoff height remains constant during board assembly, and acts as a stress absorption layer between the Si and the PCB during any thermal excursion and drop testing. Such characteristics allow extension of the wafer level package from small pin count (~30 I/O) to higher pin count (100+ I/O) without the need for redistribution layers.

For electromigration, bump resistances were monitored continuously at different current densities and temperatures for the two package types. Equivalent performance was obtained. Similar failure modes were observed in both cases, with pancake-like void formation growing outward from the pad corners due to current crowding. Equivalent performance was obtained, with both packages exhibiting MTTF of 1200 hrs at 150C, and 550 hrs at 165C. Application to a modified Black's equation to predict MTTF and account for current crowding, heating, and stress will also be discussed.
Enabling Wafer Level Processes for CIS Manufacturing
Authors: Pabo Eric F. , Oakes Garrett , Miller Ron , Lindner Paul , Kreindl Gerald , Matthias Thorsten , Dragoi V. , Wimplinger M.
Published: October 2015

CMOS (Complimentary Metal Oxide Semiconductor) Image Sensors have become ubiquitous, appearing in cars, cell phones, toys and many other devices used in every day life. The primary reason for this increasing presence of CIS (CMOS Image Sensors) is the continual improvement of the performance to cost ratio of these devices. The drivers behind this are the advancements of CMOS image sensor technology such as improved signal to noise ratio as well as advancements in wafer level processing technology related to 3D packaging. Numerous process developments related to both the electrical and optical aspects of 3D packaging of CIS that have enabled this climb up the performance vs. cost curve will be reviewed in this paper with particular attention to:(1) Lens molding – The ability to mold lenses, both spherical and aspherical at the wafer level as well as make full size master stamps from partial masters for lens molding. These lenses can be molded on both sides of a wafer and the lenses aligned to each other;(2) Aligned wafer bonding for optical interconnects consisting of lens stacks and CIS wafer, to allow the thinning of a CIS for BSI (back side illumination), and for electrical interconnects. Together these processes allow the heterogeneous integration of optical and electrical elements at the wafer level and advance the CIS up the performance vs. cost curve.
Advanced TSV Copper Electrodeposition for 3D Interconnect Applications
Authors: Beica Rozalia , Siblerud Paul , Erickson Dave
Published: October 2015

Robust and manufacturable processes are needed to enable a smoother and faster transfer of TSV technology from development to production.

There are several steps involved with TSV technology application. Either if it is done before or after thinning the wafer, as a via first, middle or via last approach, the main steps are: via etching, lining with insulator/barrier and copper seed, deep via fill and chemical mechanical planarization (CMP), chip dicing and stacking. Deep via fill is one of thee most critical steps in forming the TSV electrodes, and copper electrodeposition process has been identified to be the most appropriate and cost effective method of filling the vias.

Various critical factors with significant effect on the process performance were found: seed layer uniformity, via profile and size, stability and performance of the chemicals and equipment design. The amount and quality of the copper at the top of the vias and over the entire surface of the wafer is very important for the CMP processing. A more uniform deposition and lower overburden could significantly decrease the complexity and cost of the CMP step. The copper thickness profile between deposition and CMP can be cross-optimized to reduce dishing, increase throughput and reduce cost. This paper will focus on the deep via fill, the critical factors associated with this step and integration aspects of Cu TSV deposition step that need to be taken in consideration for successful application of this technology.

A significant amount of work has been performed to develop processes that can successfully fill features of various sizes in a cost effective way. Some of the chemistries available commercially today, although have very good super-fill characteristics, have the disadvantage of forming nodular and high-stress deposits which could have a negative impact on CMP processing. An innovative process with strong bottom-up capability that significantly reduces the overburden while increasing the speed of deposition has been developed at Semitool and the characteristics of this process and advantages over previous generation processes will be presented. The effect of copper stress and copper extrusion observed during annealing step as well as approaches taken to minimize this effect will be described.
Using Permanent and Temporary Polyimide Adhesives in 3D-TSV Processing To Avoid Thin Wafer Handling
Authors: Zussman Mel , Milasincic Chris , Rardin Anthony , Kirk Simon , Itabshi T.
Published: October 2015

This paper will examine the combined use of both permanent and temporary high-temperature polyimide adhesives used to avoid thin wafer handling. While 3D-TSV technology can improve functionality and performance, adoption of this technology has been delayed by cracking as well as unwanted wafer bowing. This presentation shows means by which a photo-lithographic polyimide adhesive is used in a temporary bonding scheme to eliminate intermediate-stage thinned wafer handling.
A Robust Wafer-Level Capping Approach for MEMS Devices
Authors: Seetharaman Krishnan , van Velzen Bart , van Zadelhoff Hans , Yuan Cadmus , Rietveld Frank , Tak Coen , van Beek Joost , Koning Jan-Jaap , Magnée Peter H. C. , van Wingerden Johannes , Beijerinck Herman C. W.
Published: October 2015

Micro-electromechanical systems (MEMS) devices are extremely sensitive to their environment, especially at wafer-level, until they are packaged in final form. The harsh back-end (BE) operations that the MEMS devices have to endure include dicing, pick-and-place, wire bonding and molding. During these processing steps, the MEMS device is exposed to particles and contaminants. Therefore, protection at an early stage is a fundamental requirement.

In this work, we describe a silicon nitride thin-film capping, which is processed using a sacrificial layer technique only with front-end technology. This approach is suitable for mass production of MEMS devices, owing to the fact that, it is more cost-effective when compared to other approaches such as wafer-to-wafer bonding and die-to-wafer bonding.

A Bulk Acoustic Wave (BAW) resonator, that finds application in the Radio Frequency (RF) front end, e.g., in cell phones, is taken as a MEMS vehicle for our work. It is an example of an extremely sensitive MEMS device, because the resonance frequency shifts significantly when additional mass is accidentally deposited on its surface. The thickness of the silicon nitride capping that is required to withstand all the BE steps, in particular transfer molding, is estimated using simple analytical calculations and finite element model (FEM) simulations. The pressure acting on the thin film capping and the thermal load during molding are included in the FEM model. Using this, the minimum thickness required for the capping is determined. We prove that, a BAW resonator capped with silicon nitride at wafer-level can be wafer-thinned, diced, wire bonded and molded without major degradation in its performance.
ZoneBOND™ Thin Wafer Support Process for Wafer Bonding Applications
Authors: McCutcheon Jeremy , Brown Robert , Dachsteiner JoElle
Published: October 2015

Wafer-to-wafer bonding is widely used to support both the production of integrated circuits and MEMS devices. Bonding may be accomplished in a variety of ways including anodic, thermal compression, and adhesive bonding. The bond may be either permanent or temporary. Permanent wafer bonding is used to combine two materials together that remain together for the life of the device, for example, in the production of Si/GaAs wafer heterostructures for integration of an optoelectronic device into silicon integrated circuit technology. Temporary bonding is used to support the device wafer during certain processing steps, and then removed once the device wafer is completed. Currently, there are several temporary bonding processes being developed in industry. The leading technology utilizes some form of polymeric material to temporarily fasten or bond a rigid backing material, usually silicon or glass, to the device wafer for processing. The main issues associated with these techniques are temperature stability of the adhesive, removal from the support wafer, and cleaning the adhesive from the device wafer. The ideal process would require bonding at an acceptable temperature (usually less than 200°C), surviving through higher temperature processes, followed by debonding at lower temperature or even room temperature. In this paper, an alternative solution is reported that utilizes current thermoplastic adhesives and silicon support wafers coupled with a patented technology, developed by Brewer Science, Inc. Support wafers are bonded to device wafers at acceptable temperatures, mechanical integrity is maintained through semiconductor or MEMs processing, and the completely processed device wafer is then safely debonded from the support wafer at room temperature.
3D TSV Interposer Technology with Cu/SnAg Microbump Interconnections
Authors: Yoon Seung Wook , Shariff Dzafir , Ku Jae Hun , Marimuthu Pandi Chelvam , Carson Flynn
Published: October 2015

Microelectronics packaging is driven by the continuous increase in demands for smaller, faster, and cheaper products with enhanced performances. Flip-chip technology and multichip packaging are developed to meet the market needs. In recent years, the concept of multichip packaging is evolved into system-in-a-package (SIP). Major advantages of SiP are that different types and generations of devices are assembled in a single package, providing high flexibility for systems designers. One way of integrating more devices into a smaller volume is 3-D packaging techniques by stacking the chips vertically. The 3-D packaging can be broadly classified as chip stacking and package stacking. In chip stacking technology, dice are stacked. This technology has advantages of increased die combination and flexibility.

These days there is more and more needs for 3D TSV interposers. Based on silicon or glass, 3D TSV interposers are next generation substrate technology which aims at replacing traditional PCB laminate or ceramic technologies for the sake of extreme miniaturization and performance. This intermediate TSV 3D technology is perceived as a bridging or linking platform between today¡¯s 2D and future genuine/ultimate 3D that will start beyond 2013.

This paper will highlight some of the recent advancements in 3D TSV interposer design, and fabrication and Cu/SnAg microbumping as well as what is being envisioned and developed to address future technology requirements in 3D TSV packaging. The advantage and applications of TSV silicon interposer technology will be presented with several examples. The process flow of TSV interposer fabrication, microbumping, assembly and packaging challenges, and performance characteristics will be also discussed.
Die-to-Wafer Bonding of Thin Dies using a 2-Step Approach; High Accuracy Placement, then Gang Bonding
Authors: Lecarpentier Gilbert , Agarwal Rahul , Zhang Wenqi , Limaye Paresh , Labie Riet , Phommahaxay A. , Soussan P.
Published: October 2015

25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 10μm and 40μm. A special test structure was designed on the landing die to electrically determine the alignment accuracy after bonding - both with respect to the X-Y alignment and the rotation. Stacks were then assembled by collective hybrid bonding process. The top die is aligned and placed on the landing wafer coverer by a patterned polymer acting as a temporary alignment holder, and then the populated wafer is moved to a wafer bonder where all the dies are collectively bonded. Electrical measurements on the alignment structures indicate that maximum misalignment of the TSV to the landing pad is in the range of 1.5–1.75 um and the maximum rotation of the die is 0.03 degrees.
Journey Toward Process Convergence in TSV Technology
Authors: Ramaswami Sesh , Dukovic John
Published: October 2015

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP).

Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products.

This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.
Electroplated Copper Pillar Feature Effects
Authors: Zhang Jim , Keigler Arthur , Liu Zhen , Hollman Richard
Published: October 2015

Economical manufacturing of electroplated copper pillars requires maximizing the deposition rate while achieving the coplanarity, flatness, and morphology required by the overall packaging process. Various aspects of the deposition are influenced by the resist pattern and the deposition rate. Experimental comparison of several different commercial copper chemistries is provided for copper pillars fabricated in 120 micron thick dry film resist with features sizes from 60 to 120 microns diameter. Feature height co-planarity and pillar top surface shape are analyzed versus feature size and pitch for a range of deposition rates.
Coreless Substrate Design, Assembly and Reliability for High Speed Applications
Authors: Aday Jon , Karim Nozad , Devita Mike , Lee Steven
Published: October 2015

There are 2 primary drivers for advanced substrate technologies to support the next generation of products. One driver is silicon designs which are shifting to 20–40 GBit applications. The band width of these products are requiring advanced materials, and designs which use much thinner cores making routing and manufacturing of these packages easier. The second driver is the move more advanced silicon nodes which also drives the importance for much better power delivery. Coreless substrates enable both of these applications by eliminating the core layer which enables much finner via pitchs to route signals and power/gnd planes. The thinness also reduces the bandwidth used up by the substrate which also enables better electrical performance. This paper will focus on the electrical drivers including simulation to support the structure, flip chip assembly of the package as well as the reliability data associated with the assembly.
Study of Thermo-Mechanical Reliability of TSV for 8-Layer Stacked Multi Chip Package
Authors: Choa Sung-Hoon , Choi Jin Young , Song Cha Gyu , Lee Haeng Soo
Published: October 2015

Through silicon via (TSV) technology is becoming a hot topic for three dimensional integration in IC packaging industry. However, TSV technology raises several reliability concerns particularly caused by thermally induced stress. In this study, the thermo-mechanical reliability of copper TSV technology for the multi chip packaging was investigated using finite element method. For the multi chip package design, the 8-layer stacked chip packaging with TSV structure has been constructed as our test vehicle. The numerical analysis of stress/strain distribution and thermal fatigue life prediction were performed in order to study the impact of several design parameters such as via diameter, via pitch, die thickness, bonding pad geometry. The effects of various underfill materials which have different Young¡¯s modulus and coefficients of thermal expansion (CTEs) were also investigated. The DOE (design of experiment) analysis was performed to find the optimal design conditions for 8-layer multi chip package. The most influential factors for the stress reduction are TSV diameter and the coefficient of thermal expansion of underfill material. The larger via diameter and lower CTE showed the smaller stress distribution. On the other hand, thermal fatigue life increases with via diameter, and becomes maximum at via diameter of 20 um, then decrease with increasing via diameter. The presence of underfill material significantly increased the thermal fatigue life of TSV structure. The bonding pad design is also important for TSV durability. The smaller bonding pad showed less stress and higher thermal fatigue life. The characteristics of warpage for 8-layer multi chip package were also investigated.
Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive
Authors: Huffman Alan , Reed Jason , Lueck Matthew , Gregory Christopher , Temple Dorota , Stapleton Russ
Published: October 2015

The study of copper-based bump structures for interconnects in 3D integration applications has been ongoing for several years. Typically, an array of Cu bumps is bonded to an array of Sn-capped Cu bumps or another Cu bump array using a thermocompression bonding process. These processes rely on high pressures and temperatures to facilitate bonding between the bump arrays. In order for this bonding to take place, some method of oxide removal is normally required for the Cu and/or Cu/Sn bump surfaces before bonding. A number of different methods have been investigated by a number of groups, including chemical cleaning, plasma cleaning, self-assembled monolayers, and no-flow underfill (NUF) materials. The use of NUFs is particularly intriguing, since these materials can be formulated with fluxing agents which could reduce surface oxides on Cu and Sn and can be deposited immediately prior to the thermocompression bonding process. In addition, the material provides a protective encapsulant to the interconnect array, protecting it from environmental damage and adding mechanical strength to the assembly.

We will present the results of a study to evaluate new fluxing NUF materials in thermocompression bonding processes on full area array test devices with 25 micron bump pitch. The test devices are fabricated with either Cu or Cu/Sn bumps to provide two different bonding options (Cu to Cu or Cu/Sn to Cu). We will compare the NUF bonding process and resulting bonded interfaces to assemblies fabricated using our standard bonding processes, which rely on both chemical and plasma pretreatment processes to prepare the bump arrays before bonding. Mechanical and electrical data will be used to compare the two bonding processes, as well as SEM cross-section analysis of the bonded interfaces.
Flexible On-Chip Inductors and Transformer
Authors: Wang James J.
Published: October 2015

Inductors directly on-chip was designed, processed and tested. Combining thick, electroplated gold used to produce LCD driver ICs plus gold wire bonding, toroidal inductors are formed directly on top of ICs. Both processes are production ready. One layouts inductor line segments on top of ICs and then complete loops using gold wire bonds at packaging. Two, 4, 8 or 16 toroids will fit inside thin QFN package. Cost to integrate 2 or more inductors is less than buying 0402 chip inductors and then soldering SMT components around ICs. Integrating inductors shrinks PCB board and allows IC design of filters, LC oscillator, EM noise suppression or ESD protection circuits.

On-chip 4nH to 2000nH inductors is practical today. Choosing the magnetic core material and selecting the number of loops/turns, designers can integrate different inductors on top of an existing IC. Custom, ultra-tiny magnetic cores are produced from same magnetic materials that are inside discrete inductors or transformers. 50nH to 500nH inductors with Q comparable to chip inductors are possible for MHz frequency ranges by selecting ferrite core. Using high permeability permalloy, one produces 200nH to 2000nH inductors or transformers directly on-chip.

Flexibility is another advantage of on-chip Gold InductorsTM. By adjusting loop heights during wire bonding, one can adjust inductance value +- 100%. By laying out both primary and secondary coils around magnetic core, designers can choose to integrate transformer or inductors. Low cost, production processes, control with IC design, plus flexibility, one can begin to design and produce on-chip filters and transformers; achieving smaller electronics.
Thermal Design of the High Brightness Thin LCDs
Authors: Chestakov D. , Cennini G. , Albani L. , Bonfiglio S.
Published: October 2015

Often, Medical Monitors have a special cabinet with closure to avoid liquids to hamper the monitor functionality and for cleaning requirements but limiting the airflow. The thermal management of the electronics and LCD panel should be designed with more accuracy and it is a limiting factor of the monitor specification. Introducing LED backlight in Medical Monitors not only allows a mercury free system (Green product) but provides the capability to match the white colour among similar Medical Monitors.

For thermal matters of the LCD backlights, one of the main differences between LEDs and CCFLs is that, the latter ones have an optimal operational temperature: CCFLs (and HCFLs as well) work better when they are hot. On the other hand, heating produces permanent damage to the electrodes, phosphor and gas mixture in the CCFL tube. This effectively reduces the lamp efficacy. For LEDs the situation is just the opposite: for higher efficacy, the light source temperature should be lower, which goes along with the increasing of the lifetime of the LEDs.

Moreover, red, red/orange and amber emitters are more sensitive to increases of junction temperature than other colors. Also, the wavelength of the emitter radiation shifts to higher wavelengths when the junction temperature rises. Red, Red/Orange and Amber emitters are the most sensitive to this effect.

Another difference is the construction of the light sources. The main heat transfer in CCFLs occurs via its glass tube, which is a light emitting surface as well. This makes difficult the realization of an efficient cooling without blocking the emitted light. Additionally, glass is famous for its low mechanical resistance against thermal stress. In case of LED, the heat transfer and light emitting surfaces are different. That makes easy the light and heat extracting designs.

In this paper, we report on the thermal design of a Medical Monitor based on LED backlight with brightness of 1000 cd/m2. The research has been carried out with the aim to define the optimum backlight architecture for an 18” size monochrome display. The design is based on an edge-lit configuration, with two or one row of high power LEDs, and a passive cooling by means of heat sinks or cooling plates
Thermal Dissipation-It's Not Rocket Science
Authors: Wall Franklin , Cassarino Sal
Published: October 2015

For many Engineers, designing an LED Luminaire seems like an insurmountable task, as typically Luminaires are fabricated from stamped sheet metal or cast custom shapes. Optics, Electrical Design Considerations & Thermal dissipation all come into play, and may require bringing in additional resources to enable a comprehensive design. For many, Thermal dissipation poses the most daunting task, as it greatly impact material & design considerations. This paper will use 3 case studies to highlight how, with a little clever design work, Thermal limitations can be overcome in a simpl fashion.
Status of the EMC3D Consortia to Cost Objectives
Authors: Siblerud Paul
Published: October 2015

TO COME
Lessons Learned from 3D-IC MPW Runs
Authors: Patti Robert
Published: October 2015

Tezzaron has worked for several years in the area of 3D integrated circuit development. During 2010, 3 different multiproject wafer runs targeting 2 to 5 layer 3DICs for several different customers were started. Tezzaron's perspective on the results of those runs, issues, and futures will be discussed.
High Throuput Fluidic PCBs for Medical Devices
Authors: Gassmann Stefan , Pagel Lienhard
Published: October 2015

Printed circuit boards (PCBs) perform normally wiring, holding and cooling tasks in electronic systems. But with the request for integration of more and more functionality in the devices the PCBs have to take over more and more tasks in a system and will become a functional device and not only the carrier for electronic devices.

One of these functions can be fluidics. The usage of PCBs for micro fluidic devices such as pumps and sensors was already reported. In this talk a new research area of the fluidic PCB group at the University of Rostock is presented: The usage of a fluidic PCB technology for the realization of medical fluidic devices with high throughput. The problems to overcome are the creation of high pressure proof channels with a low flow resistance and of course the biocompatibility.

In the talk a medical device developed in such a technology will be described. It is a support device for the minimal invasive surgery which has to regulate the pressure in the pneumoperitonaeum, a so called insufflator. For this device flow rates of up to 45l/min CO2 has to deliver and the channel must withstand a pressure of up to 3.5 Bar.

The focus in the talk will be the technological challenge of building pressure proof channels in the PCB. The requirements for the usage in medical devices will be explicitly described and the measurement results will be demonstrated. As a conclusion a comparison to a device build in a conventional technology device is given. The criterias are the functional parameters and the production and maintainance costs.