bluuebunny/crossref_metadata_2025 huggingface dataset:
(Invited) Advanced Heterogeneous Integration of InP HBT and CMOS/SiGeBiCMOS Technologies
Authors: Gutierrez-Aitken Augusto , Chang-Chien Patty , Oyama Bert , Scott Dennis , Hennig Kelly , Kaneshiro Eric , Chen John , Nam Peter , Ching Daniel , Thai Khanh , Poust Ben , Oki Aaron K , Kagiwada Reynold
Published: March 2013

Under the Compound Semiconductor Materials on Silicon (COSMOS) DARPA program, Northrop Grumman Aerospace Systems (NGAS) has developed an advanced heterogeneous integration technology to intimately integrate compound semiconductor (CS) devices and circuits on CMOS/SiGeBiCMOS wafers. The integration approach is based on a direct face-to-face bonding between pre-fabricated InP chiplets and Si wafers. The heterogeneous integration process is compatible with any semiconductor technology. This integration enables significant improvement in dynamic range and bandwidth of high performance mixed signal circuits. In this paper we describe the integration approach and present two demonstration circuits.
Wafer Level 3D Stacking Using Smart Cut and Metal-Metal Direct Bonding Technology
Authors: Di Cioccio Lea , Radu Ionut , Baudin Floriane , Mounier Angelique , Lacave Thomas , Delaye Vincent , Imbert Bruno , Chevalier Nicolas , Denis Mariolle , Gaudin Gweltaz , Mazen Frederic , Thieffry Stephane , Signamarcheix Thomas
Published: March 2013

While significant research effort on various planar approaches, the 3D vertical IC stacking is undoubtedly gaining increasing momentum as a leading contender in the challenge to meet performance, cost, and size demands through this decade and beyond. The Smart CutTM technology allowing the stack of very thin layers with direct bonding is one of the emerging technologies in this field. In this paper, the Smart CutTM technology using low temperature metal direct bonding (allowing direct vertical integration) is demonstrated.
Cu-Sn Transient Liquid Phase Wafer Bonding: Process Parameters Influence on Bonded Interface Quality
Authors: Floetgen Christoph , Corn Kevin , Pawlak Marta , van de Wiel Bart , Hayes Greg , Dragoi Viorel
Published: March 2013

Cu-Sn Transient Liquid Phase (TLP) wafer-level bonding is an interesting solution for wafer-to-wafer stacking technologies, due to its compatibility with 3D interconnections as well as vacuum sealing applications. The work presented here is analysing typical Cu-Sn TLP wafer bonding issues as occurrence of voids, bonded wafers pair bow and incomplete layer transformation with respect to process parameters as maximum bonding temperature, bonding time and contact (bonding) pressure.
Laser Transmission Bonding of Silicon with Titanium and Copper Layer for Wafer-Level Packaging
Authors: Wissinger Anselm , Schmitz Moritz , Olowinsky Alexander , Gillner Arnold , Poprawe Reinhart
Published: March 2013

For packaging of silicon components with high spatial selectivity and small heat affected zone (HAZ) laser transmission bonding (LTB) of silicon-silicon compounds using the intermediate layer system copper-titanium is investigated. The bonds are realized by using a cw-thulium fiber laser (wavelength 1940 nm). Several process parameters, like laser intensity, feed rate and contact pressure, are analyzed and optimized during the investigation. Also varying layer thicknesses for titanium and copper are compared in order to analyze their influence on the LTB process. Results are examined regarding the tensile strength measured by using tensile test. Occuring bond failures during the experiments are described and methods for avoiding these are discussed. Micrographs are analyzed in order to investigate the bond zone by SEM. Specimens bonded with corresponding standard bond process using the same layer system and bond geometry are used in order to compare the results.
(Invited) Mechanics of Wafer Bonding and Layer Transfer Processes
Authors: Turner Kevin T.
Published: March 2013

Mechanics plays a crucial role in semiconductor wafer bonding. For example, successful bonding requires elastic deformation of the wafers to achieve intimate contact between the surfaces, residual stresses can develop during bonding, and many layer transfer processes require managing crack propagation at interfaces. Furthermore, understanding adhesion that drives the bonding processes as well as characterizing the mechanical integrity of wafer bonds requires assessing mechanics of interfaces. This paper demonstrates how an understanding the mechanics of bonding processes can be leveraged to enhance process performance and identify new routes for bonded structure fabrication. Here, three mechanics-based topics are discussed: (1) role of wafer geometry in wafer bonding, (2) characterization adhesion energy during direct bond formation, and (3) mechanics of microtransfer printing processes for thin layer transfer.
Failure Mechanisms and Mechanical Characterization of Reactive Bonded Interfaces
Authors: Boettge Bianca , Schippel Fabian , Naumann Falk , Berthold Lutz , Lorenz Georg , Gerbach Ronny , Bagdahn Joerg , Petzold Matthias
Published: March 2013

This study presents results of microstructure diagnostics and mechanical strength investigations for reactive bonded components. For this purpose silicon (Si) test specimen were bonded by using commercially available 40 µm thick nickel/aluminum (Ni/Al) NanoFoils{copyright} with a 10 µm thick tin (Sn) solder layer on both sides. Scanning electron (SEM) and high resolution transmission electron microscopy (HRTEM) in combination with energy dispersive X-ray spectroscopy (EDXS) at the bond interface showed the formation of silver-copper-tin (Ag-Cu-Sn) and tin-silver (Sn-Ag) intermetallics within the Sn solder matrix. The hardness and modulus of the solder layer were characterized by Berkovich nanoindentation testing. Results from strength investigations using tensile and micro chevron testing revealed a strong bonding strength of the interface. SEM analyses of the fracture surfaces showed both, cohesive failure through the solder layer and adhesive failure between the silicon substrate and the gold-chrome coating layer.
Low Temperature Fusion Wafer Bonding Quality Investigation for Failure Mode Analysis
Authors: Dragoi Viorel , Czurratis Peter , Brand Sebastian , Beyersdorfer Jens , Patzig Christian , Krugers Jan-Paul , Schrank Franz , Siegert Joerg , Petzold Matthias
Published: March 2013

In this paper, a brief summary of potential defect formation and failure characteristics for low temperature plasma-assisted Si wafer bonding in correlation to different influencing factors is given. In terms of a failure catalogue classification, these defects are related to incoming material quality variation, wafer bonding equipment and bonding tools issues, or to the choice of inappropriate post-bonding process parameters. To attribute experimentally detected bond defects to its specific root cause requires applying appropriate failure analysis methods, such as e.g. atomic force microscopy, scanning acoustic microscopy, transmission electron microscopy and surface analysis but also strength testing. Practical failure analysis application examples together with new and upcoming methodical developments are presented briefly that support process and technology optimization for future wafer bonded 3D integrated electronic systems.
Investigation of Different Nano Scale Energetic Material Systems for Reactive Wafer Bonding
Authors: Braeuer J. , Besser J. , Tomoscheit E. , Klimm D. , Anbumani S. , Wiemer M. , Gessner T.
Published: March 2013

This paper introduces a method that uses a specific form of local heat generation, which is based on nano scale reactive multilayer systems. Such systems consist of several layers of minimum two different materials with nano scale thicknesses. These layers generate heat based on a self-propagating exothermic reaction during their intermixing. The resulting heat can be used as heat source for bonding processes at chip and wafer-level.
Quality Control of Bond Strength in Low-Temperature Bonded Wafers
Authors: Siegert Joerg , Cassidy Cathal , Schrank Franz , Gerbach Ronny , Boettge Bianca , Naumann Falk , Petzold Matthias
Published: March 2013

Low-temperature plasma activated wafer bonding is an important technology for the 3D integration of semiconductor devices, such as sensors and CMOS devices integrated on opposite sides on the same chip. In a volume production environment, monitoring the bond strength is essential to the overall product quality. In this publication, commonly used methods for bond strength measurement and their relative advantages and disadvantages for quality control are compared with a novel technique of sample preparation for tensile testing.
(Invited) Plasma Activation as a Pretreatment Tool for Low-Temperature Direct Wafer Bonding in Microsystems Technology
Authors: Eichler Marko , Hennecke Philipp , Nagel Krees , Gabriel Markus , Klages Claus-Peter
Published: March 2013

Dynamic measurements of interfacial fracture surface energies γ have been carried out during the annealing of pairs of silicon, fused silica and borosilicate glass wafers, resp. Pronounced maxima of the resulting γ(t) curves could be detected in several cases, especially for plasma activated wafer pairs. In the present article the different phases of the bonding process are discussed and an interpretation is given for the formation of the γ(t) maxima. Moreover, influences of plasma activation at atmospheric pressure and at low pressure on the increase in surface energy during annealing are compared. Based on AFM roughness measurements, power spectral densities were determined for two debonded wafer pairs and the influence of the bond strength is discussed here.
Investigations on Bond Strength Development of Plasma Activated Direct Wafer Bonding with Annealing
Authors: Plach Thomas , Hingerl Kurt , Stifter D. , Dragoi Viorel , Wimplinger Markus
Published: March 2013

In order to clarify the mechanism behind the bond strength enhancement at low temperatures by plasma activation the bond strength development with annealing temperature was systematically investigated. The study consisted of bonding experiments on the material system Si-SiO2 under varying process conditions. Combining experimental findings with established models we developed a better understanding of the bonding process which helps explaining the experimentally found behavior. Based on this improved understanding we can predict that plasma activated (PA) wafer bonding can be successfully employed for a larger group of materials than it is currently used.
Room Temperature Wafer Bonding by Surface Activated ALD- Al2O3
Authors: Li Yun , Wang Shengkai , Sun Bing , Chang Hudong , Zhao Wei , Zhang Xiong , Liu Honggang
Published: March 2013

Room-temperature Si/Al2O3 and Al2O3/Si wafer bonding has been achieved successfully using activating wafer surfaces by using O2 plasma and following N2 plasma generated by reactive ion etching (RIE) equipment. It is found that the plasma power has a strong influence on the voids formation between the two wafers. The effective bonded area, micro-structure and bond mechanism were investigated in this research. Scanning acoustic microscope (SAM) was utilized to observe the voids. A high quality interfacial layer has been observed by using scanning electron microscope (SEM). To test the bond strength, the wafer pairs are tested by a thinning and cutting process. The reactions on two activated surfaces are used to explain the surface activated bonding process, by taking the formation of Al-OxNy bonds into consideration. This wafer bonding method is theoretically suitable to bond any two wafers, because the technique is not sensitive to the substrate materials.
(Invited) Cost-Effective Layer Transfer by Controlled Spalling Technology
Authors: Bedell Stephen W. , Shahrjerdi Davood , Fogel Keith , Lauro Paul , Hekmatshoar Bahman , Li Ning , Ott John , Sadana Devendra K.
Published: March 2013

Although historically studied as a failure mode, substrate spalling can be transformed into a versatile layer transfer method by carefully controlling the thickness and intrinsic stress of a surface layer, and mechanically guiding the fracture path. This Controlled Spalling process requires no specialized equipment and can be applied to essentially any brittle substrate. We have successfully demonstrated i) device fabrication in Si, Ge, and III-V based materials, ii) removal of fully-processed CMOS circuits, iii) kerf-free ingot slicing, iv) 300 mm diameter layer transfer and v) a wide range of other materials such as GaN grown on sapphire.
Development of Porous InP for Subsequent Epitaxial Layer Transfer onto Flexible Substrates
Authors: Kou Xiaolu , Goorsky M. S.
Published: March 2013

In order to reduce substrate cost and produce integrated III-V semiconductor device structure, porous InP layer was formed on an InP substrate to be used a mechanically weak layer to assist lift-off of subsequent epitaxial grown layer which need to be transferred onto another substrate. This process follows the work done for ELTRAN (Epitaxial Layer TRANsfer) in the silicon material system(1). In this work, electrochemical etching was used to fabricate a dual porous layer and the sample was annealed to reconstruct porous structure and get ready for epitaxial deposition. The result of bonding and transferring process leaves a 2 μm InP layer on PDMS substrate, and it indicates promising application in flexible optoelectronics.
Optimization of H+ Implantation Parameters for Exfoliation of 4H-SiC Films
Authors: Amarasinghe Voshadhi P. , Wielunski Leszek , Barcz Adam , Feldman Leonard C. , Celler George K.
Published: March 2013

In this study we show that for 1 µm thick 4H-SiC exfoliated films, there is an optimum implantation dose of about 6E16 cm-2 at 180 keV. The layer transfer is more difficult for higher as well as lower doses. Material doping and small changes in crystalline orientation do not have much impact on the exfoliation. Optical transmittance, Raman, RBS with ion channeling, SIMS, and optical microscopy are used for sample characterization.
(Invited) Low-Temperature Bonding Technologies for Photonics Applications
Authors: Higurashi Eiji
Published: March 2013

This paper focuses on low temperature bonding technology and its applications in photonics devices in use in various fields. Fabrication of a wafer bonded two-layer germanium (Ge) structure for far-infrared detector application was demonstrated by surface activated bonding (SAB) method at room temperature. Very low-resistive Ge/Ge junctions were obtained by SAB method. The feasibility of low-temperature 3-D integration of optical semiconductor chips was also demonstrated by Au-Au SAB in ambient air. Using this technique, compact and thin micro encoders and laser Doppler velocimeters (2.8 mm × 2.8 mm × 1 mm thick) were developed.
Adhesive Wafer Bonding Applied for Fabrication of True-Chip-Size Packages for SAW Devices
Authors: Heuser Thorsten , Bauer Christian , Dragoi Viorel , Mittendorfer Gerald
Published: March 2013

Surface Acoustic Wave (SAW) filters are key components for mobile communication. In SAW devices mechanical waves propagate on the surface of a piezoelectric bulk material such as LiNbO3 or LiTaO3. SAW components require advanced cavity packaging solutions in order to enable the mechanical wave propagation on the substrate material. Size reduction of SAW filters allows further miniaturization of mobile phones and an extension of their functionality. The mobile communication industry, therefore, demands advanced cavity package technologies to be developed for SAW components. These packages have to offer high performance, high reliability, and low cost while maintaining a form factor as small as possible. To address these requirements EPCOS has developed a Die Sized SAW Package (DSSP), a true chip-size wafer level package for SAW filters. This paper discusses the manufacturing process of wafer-level-packages for SAW-devices with a special focus on the adhesive wafer bonding technology.
Monitoring Inner Pressure of MEMS Devices Sealed by Wafer Bonding
Authors: Knechtel Roy , Hering Siegfried , Dempwolf Sophia
Published: March 2013

Hermetic sealing is important regarding functionality and reliability for MEMS components. Typically this sealing is done on the wafer level using wafer bonding which simultaneously also provides mechanical protective caps. However, inner pressure and hermeticity testing and monitoring a still a critical issue; therefore, in this paper a test structure adapted to a MEMS foundry process for inertial sensors is introduced.
Chemical-Mechanical Polishing YAG For Wafer Bonding
Authors: Mc Kay Jeffrey , Moulet-Ventosa Caroline , Goorsky M. S.
Published: March 2013

The chemical mechanical polishing of yttrium aluminum garnet (YAG) using a commercial slurry (Ultra-Sol 500s) is investigated. Surfaces are polished to below 0.5 nm RMS surface roughness, with a controllable polishing rate of 0.3 nm / min. In addition, high resolution x-ray diffraction measurements show an improvement in crystal quality after polishing. After polishing, samples are further cleaned with citric acid and sodium hypochlorite solutions to remove any remaining slurry particles. Surfaces with < 0.5 nm RMS surface roughness are suitable for wafer bonding, and are treated with various surface preparation steps prior to bonding. Once bonded at room temperature, samples are heated at 1300{degree sign} C for 48 hours to further strengthen the bond.
Glass Direct Bonding for Optical Applications
Authors: Kalkowski Gerhard , Rothhardt Carolin , Jobst Paul-Johannes , Schürmann Mark , Eberhardt Ramona
Published: March 2013

The direct wafer bonding technology is applied to join glass substrates for optical devices in high power laser applications. Uncoated as well as coated fused silica substrates were bonded to each other by hydrophilic direct bonding and -for comparison- sodium silicate-solution bonding. Both technologies are expected to generate materials-adapted Si-O-Si bonds at uncoated interfaces. Optical transmission and reflection in the spectral range of 200 nm to 1200 nm were measured and reveal superior transmission for the direct bonding technology in the ultra-violet range. Even in the near infrared at 980 nm, better performance with direct bonding as compared to silicate-solution bonding is evidenced by laser induced damage threshold measurements. For all coated samples, a distinct reduction in bonding strength relative to uncoated ones is observed in 3-point bending tests.
(Invited) Twenty Five Years of Improvement of the Silicon Based TFT: From As-Deposited Polycrystalline Silicon to Nanostructured Silicon Deposited at Very Low Temperature
Authors: Mohammed-Brahim Tayeb , Bonnaud Olivier
Published: March 2013

25 years of effort made in Rennes 1 University to improve the performance of silicon based thin film transistors are reviewed. The review is focused mainly on the technological progress. It starts from the end of 80's at the time where the main work was devoted to understand the physical properties of polycrystalline silicon that was used as active layer of transistors for the first time. It finishes with microcrystalline silicon TFTs fabricated at low temperature compatible with the use of transparent plastic substrates, going through the different crystallized forms of silicon. These different crystallized forms obtained by different techniques allow silicon to be able to stay as the basic material of TFTs whatever the applications and the substrates
(Invited) Beyond the Current Horizontal of Silicon Thin Film Technology : Light-Soaking Free Nano-Crystal Embedded Polymorphous Silicon Thin Film by Neutral Beam Assisted CVD at Room Temperature
Authors: Hong MunPyo , Jang Jin Nyoung
Published: March 2013

Next generation display and photovoltaic devices are moved toward flexibility which needs low temperature process. However most of synthesis (or deposition) methods hardly avoid high temperature process, especially for crystalline structured thin films. A novel deposition process for nano-crystal embedded polymorphous silicon (nc-embedded pm-Si) thin films at room temperature has been developed by adopting the neutral beam assisted chemical vapor deposition (NBaCVD). Experimental results of the NBaCVD process show superior electrical properties and light soaking stability in nano-crystal silicon even the deposition temperature was below 80 {degree sign}C. The energetic neutral particles enhance doping efficiency (σ = 1.14 S/cm) and crystalline phase (up to 80%) in nc-embedded pm-Si thin films without additional substrate heating. The light soaking stability of nc-Si embedded pm-Si shows very strong tolerance.
Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors
Authors: Lin Cheng-I , Lin Horng-Chih , Huang Tiao-Yuan
Published: March 2013

In this work, we study the electrical characteristics of planar poly-Si junctionless (JL) thin-film transistors (TFTs) with 10 nm-thick channel and various gate width. The output current of JL devices is drastically larger than that of the control device with an undoped channel, owing to the abundant carriers contained in the channel of the JL devices which tends to reduce both channel and source/drain series resistances. Subthreshold swing of the JL devices is found to be larger than the control ones, owing to the existence of a depletion layer in the channel. Nonetheless, excellent on/off current ratio (>1E+07) is achieved, thanks to the use of the ultra-thin channel.
Characteristiscs of Nanocrystalline Silicon Films Deposited by Cat-CVD Below 100 ℃
Authors: Song Tae-Ho , Keum Ki-Su , Kang Sin Young , Park Jung-Hoon , Kim Jin-Hoon , Hong Wan-Shick
Published: March 2013

Nanocrystalline Silicon (nc-Si) films were deposited by catalytic chemical vapor deposition (Cat-CVD) at a low substrate temperature (100 {degree sign}C) for use as an active layer in bottom-gate thin-film transistors (TFTs). Hydrogen dilution technique was attempted to increase the crystalline volume fraction (Xc). The hydrogen dilution ratio, RH=[H2]/[SiH4], was varied from 2 to 74. Xc of the nc-Si films was estimated by Raman spectrum. The incubation-layer thickness was estimated by transmission electron spectroscopy (TEM). Incubation layer was limited up to 5.26 nm and crystallinity was 71 %.
Decreasing the Off-Current for Vertical TFT by Using an Insulating Layer between Source and Drain
Authors: Zhang Peng , Jacques Emmanuel , Rogel Regis , Bonnaud Olivier
Published: March 2013

A novel polysilicon vertical thin film transistor (VTFT) has been fabricated based on a low-temperature (T{less than or equal to}600{degree sign}C) process. This new structure eliminates the large overlapping area between source and drain, and thus reduced the off-current and increased the Ion/Ioff ratio. The technologically key point lies in the introduction of an insulating layer between source and drain, and the electrical properties of the fabricated VTFTs using different insulating layers are compared. These first results highlight that the SiO2 insulating layer shows great advantages over the Si3N4 insulating layer. The reduced off-current has revealed some potential applications for high density integration and high drive current.
Modes of Operation and Optimum Design for Application of Source-Gated Transistors
Authors: Sporea Radu Alexandru , Shannon John M. , Silva S. Ravi P.
Published: March 2013

We show that the source-gated transistor has two distinct modes of operation. In the low-field mode, the current from the reverse-biased source barrier is restricted by the depleted semiconductor at the drain end of the source. In the high-field mode, the current depends on field-dependent barrier lowering in the same region of the source. In practice, both these modes usually occur: the former at low VG, the latter at high VG. It is shown that this understanding enables us to design devices in which the current is insensitive to large changes in structure and geometry.
Deposition of Low Stress Amorphous Zinc Tin Oxide at Ambient Temperature Using a Remote Plasma Sputtering Process Suitable for Delicate Substrates
Authors: Pfaendler Sieglinde Marie Lousie , Ercolano Giorgio , MacManus-Driscoll Judith L. , Flewitt Andrew J.
Published: March 2013

ZnxSnyOz thin films (<100nm thickness), deposited by remote sputtering from a metal target using a confined argon plasma and oxygen gas jet near the sample, were investigated for their material properties. No visible deformation or curl was observed when deposited on plastic. Materials were confirmed to be amorphous and range between 5 and 10 at.% Sn concentration by x-ray diffraction, x-ray photoemission spectroscopy and energy-dispersive x-ray spectroscopy. Factors affecting the material composition over time are discussed. Depletion of the Sn as the target ages is suspected.
Simple Aqueous Solution Route for Fabrication High Performance Oxide TFT
Authors: Bae Byeong-Soo , Hwang Young Hwan , Seo Jin-Suk , Choi Gwang-Mun
Published: March 2013

Metal oxide semiconductor attracts considerable attentions for driving circuit of next generation displays and energy devices owing to their simultaneous transparency and high electrical performance. We report fluorine doped zinc tin oxide (ZTO:F) and indium zinc oxide (IZO) thin-film transistors (TFT) via aqueous route. The aqueous route enables the fabrication of oxide TFT at low temperature with reasonable cost. The ZTO:F TFT exhibits good electrical performance and stability over electrical stress due to the effective removal of oxygen vacancy and generation of carrier by F doping. The IZO TFTs also shows good performance in terms of mobility and operation accuracy. Finally, the optimized IZO TFT is fabricated on plastic substrate with 250 ℃ annealing and the device exhibits sufficient performance for operation of various displays and basic circuitries.
Fabricating Multiple Channeled Zinc Oxide Thin Film Transistor Via Sol-Gel Method
Authors: Chiou Guan-Yu , Liu Siou-Ting , Chen Sun-Zen , Chen Henry J. H.
Published: March 2013

We demonstrate here a sol-gel derived zinc oxide (ZnO) thin film transistor with a multi-channel architecture. As indicated in the experiment results, the number of film coating time and annealing temperature has greatly effects on film properties. The device with multi-channel architecture shows better performance than that without multi-channel one. The multi-channeled ZnO TFT shows high on-off ratio 8.5× 106 and high carrier mobility 77.61 cm²/V.s. The good device performance may attribute to the use of multichannel, the multiple coatings of ZnO, suitable annealing temperature, and adequate oxide gate.
Laser Patterned Junctionless In-Plane-Gate Oxide Thin-Film Transistors Arrays
Authors: Zhu Li Qiang , Wan Qing
Published: March 2013

A novel laser scribing process was successfully developed in fabricating junctionless low-voltage oxide-based thin-film transistors (TFTs) arrays without any mask and photolithography steps at room temperature. Such junctionless TFTs feature that the channel and the source/drain electrodes are of the same thin indium-tin-oxide films without any intentional source/drain junction deposition process. Effective field-effect modulation of the drain current has been realized. Such junctionless in-plane-gate TFTs exhibit a good electrical performance with a small threshold voltage (-0.7V), a small subthreshold swing (0.25V/decade), a high mobility (~12.6cm2/Vs), and a large on/off ratio (>106), respectively. The developed laser scribing technology is highly desirable in terms of the low-cost fabrication process.
Effects of Ultra-Violet Treatment on Electrical Characteristics of Solution-Processed Oxide Thin-Film Transistors
Authors: Lee Jeong-Soo , Song Seung-Min , Kang Dong-Won , Kim Yong-Hoon , Kwon Jang-Yeon , Han Min-Koo
Published: March 2013

We fabricated solution-processed IGZO and ZTO TFTs with annealing temperature of 350 {degree sign}C employing Ultra-Violet (UV) radiation treatment. The electrical characteristics of solution-processed oxide TFTs would be considerably improved by employing UV treatment on the active layer of oxide TFTs. UV treatment increased electron concentration of IGZO and ZTO active layer because electrons were generated with increasing O-H bonding by UV in oxide semiconductors. The threshold voltage decreased and the saturation mobility increased by UV treatment due to the increase of electron concentration at low annealing temperature of 350 {degree sign}C in solution-processed oxide TFTs. Saturation mobility of solution-processed IGZO TFTs increased from 0.31 cm2/V∙sec (without UV treatment) to 2.96 cm2/V∙sec (with 1 h UV treatment) and that of solution-processed ZTO TFTs increased from 0.01 cm2/V∙sec (without UV treatment) to 0.30 cm2/V∙sec (with 1 h UV treatment) with UV treatment.
(Invited) Top-Gate Effects in Dual-Gate Amorphous InGaZnO4 Thin-Film Transistors
Authors: Takechi Kazushige , Iwamatsu Shinnosuke , Yahagi Toru , Watanabe Yoshiyuki , Kobayashi Seiya , Tanabe Hiroshi
Published: March 2013

We discuss the dependence of bottom-gate transfer characteristics (Vbg-Id) on top-gate voltage (Vtg), which we call "top-gate effects", using a-IGZO TFTs having a dual-gate structure. We consider the top-gate effects to be a measure of how a-IGZO TFT characteristics are sensitive to charge generation on TFTs. We compare the top-gate effects in a-IGZO TFTs and conventional channel-etched a-Si:H TFTs. We found that the positive top-gate effect in a-IGZO TFTs varied depending on top-channel properties, while the negative top-gate effect had a similar impact on Vbg-Id characteristics irrespective of top-channel properties. We also found that a-IGZO TFTs had more significant top-gate effects than conventional a-Si:H TFTs.
(Invited) Channel Width and Channel Length Dependencies in Amorphous-Oxide-Semiconductor Thin-Film Transistors: From a Device Structure Perspective
Authors: Mativenga Mallory , Um Jae Kwang , Mruthyunjaya Ravi , Chang Jeff H. , Heiler Gregory N. , Tredwell Timothy J. , Jang J.
Published: March 2013

Owing to their unique device structures, amorphous oxide semiconductor (AOS)-based thin-film transistors (TFTs) often exhibit non-ideal dependencies on channel width (W) and channel length (L) variations. In particular, two abnormalities are common; 1) the TFT threshold-voltage (VTH) shifts to the negative gate voltage (VGS) direction as L decreases for fixed W; and 2) the TFT field-effect mobility (µFE) dramatically increases as W decreases for fixed L. This paper therefore seeks to explain the origin of these non-ideal behaviors and present device topologies that can be utilized to minimize them. The abnormal negative VTH shift (ΔVTH) is attributed to unintentional doping of the intrinsic channel region from n+ doped source/drain regions, whereas the large increase in µFE is due to spreading current, which effectively increases W. It is found that the former can be minimized by reducing the source/drain to active layer contact area, whereas the latter is solved by employing device topologies in which the source and drain electrodes extend over the active layer along the W direction. This paper furthers our knowledge and understanding of the physical topology of TFT designs and its impact to TFT performance.
Influence of Thermal Stress and Kinetic Bias Stress on the Electrical Performance of Mixed Oxide Thin Film Transistors
Authors: Vemuri Rajitha N. P. , Alford Terry L
Published: March 2013

This study discusses thermally activated defects in the channel layer of indium zinc oxide (IZO) thin film transistors (TFTs) under electrical and thermal stress resembling practical stress scenarios. Operating temperatures of 20, 50, and 80 {degree sign}C have been chosen to establish a relation between temperature and failure mechanism. With increasing stress period, acceptor- and donor-like traps contribute towards degrading drain current and subthreshold swing. Low temperature long hour anneal for 12, 24, 36, 48 and 60 hr at 150 {degree sign}C are performed on the TFTs post fabrication to cure the defects formed during fabrication. Structures treated for 48 hr demonstrate high stability under extended kinetic stresses, maintaining a high transistor Ion/Ioff ratio of ~ 108. A physically-based mathematical model discusses the reduction in the density of acceptor-like trap states by 50 % for TFTs treated for 12 hrs, and to insignificant numbers for TFTs treated for 48 hr.
Improvement of the Photo-Bias Stability of Zn-Sn-O Field effect Transistors by an Ozone Treatment
Authors: Yang Bong Seob , Oh Seungha , Kim Yoon Jang , Kim Hyeong Joon
Published: March 2013

This study examined the effect of O3 treatment on the instability of the ZTO FETs using a NBIS test. The untreated FETs suffered from a huge negative Vth shift, whereas the O3 treated device exhibited much superior stability with increasing O3 treatment time. The VO concentration in the film decreased gradually with increasing O3 treatment time. The Vth shift under NBIS conditions is due partly to the transition of VO to VO2+ by light excitation. Therefore, O3 treatment can enhance the in-diffusion of oxygen radicals and reduce the [VO] density, resulting improvement in photo-bias reliability. Simultaneously, the number of hydroxyl groups on the surface of increased with increasing O3 treatment time. This suggests another reason for the improved NBIS stability : the substitution of weakly bound O2- species at the surface with OH-. This suggests that the surface condition of ZTO films is an important factor determining the photo-bias stability.
Influence of Annealing Conditions on the Bias Temperature Stability of MgZnO Thin Film Transistors
Authors: Tsai Yi-Shiuan , Chen Jian-Zhang , Cheng I-Chun
Published: March 2013

We report the experimental results regarding the stability of back-channel cut bottom gate thin film transistors (TFTs) with Mg0.05Zn0.95O active layers. The TFTs are all fabricated at room temperature. Two different thermal annealing conditions are applied to the devices, 200 oC for 5 hours and 350 oC for half an hour. In both annealing conditions, the devices show similar electric characteristics initially. Nevertheless, 350 oC annealed TFTs show much better stability under gate bias stressing. When gate-bias stressing is applied to TFTs at 80 oC, the transfer curves exhibit much more significant humps at subthreshold regimes for 200 oC annealed TFTs compared to 350 oC annealed TFTs. It is highly suspected that the humps may be due to the two phase nature of as-sputtered MgZnO thin film. 350 oC annealing may transform the two phase mixture into single phase, leading to more stable TFTs.
Mixed Oxide Thin Film Transistors under Combinatory Optical Irradiation and Electrical Bias
Authors: Alford Terry L , Vemuri Rajitha N. P. , Mathews Winnie P.
Published: March 2013

This study reports the operational instability and failure causing defect mechanisms of indium gallium zinc oxides based thin film transistors (TFTs) under practical, combined bias and illumination stress conditions. The effect of the illumination stress with light source of different wavelengths (410 nm, 467 nm, 532 nm, and 632 nm) has been explained. Wavelengths shorter than green light (532 nm) demonstrate creation of ionized vacancies and subsequent generation of excess carriers that alter TFT functions. Recovery evaluations performed upon removal of combinatory stresses exhibits incomplete recovery due to incapacity in regenerating neutral oxygen vacancies. The Ion/Ioff values show an increase by an order of magnitude when compared to previous studies where the Ion/Ioff is reduced. This can be contributed to the reduced defect and vacancy densities due to the effective post anneal process.
The effect of Zn/Sn Ratio on the Electrical Performance of Amorphous ZrZnSnO (ZZTO) Thin Film Transistors by RF Sputtering
Authors: Chiu I-Chung , Cheng I-Chun , Chen Jian Zhang
Published: March 2013

Amorphous zirconium-zinc-tin-oxide (a-ZZTO) thin films and thin film transistors (TFTs) are investigated. The transmittance of the a-ZZTO is over 80% in the visible light wavelength region. The band gap, extracted from Tauc plot, is around 3.8 eV. The as-fabricated Zr0.03Zn0.32Sn0.65O TFT exhibits a threshold voltage of 2.8 V, field-effect mobility of 10.25 cm2/V-s, a sub-threshold swing of 800 mV/dec and an on/off ratio of 105. As the Zn/Sn ratio increases, the threshold voltage increases and the field-effect mobility decreases.
Composition Dependence of the Negative Bias Light Illumination Instability of Indium Zinc Oxide Transistors
Authors: Oh Seungha , Yang Bong Seob , Kim Yoon Jang , Kim Hyeong Joon
Published: March 2013

This study examined the effects of the indium fraction in indium zinc oxide (IZO) on the performance and stability of IZO thin film transistors (TFTs). The field-effect mobility and sub-threshold swing were much improved with increasing In fraction; 41.0 cm2/Vs and 0.2 V/decade, respectively, at 85 at% In, compared to 1.1 cm2/Vs and 2.4 V/decade of ZnO TFTs. In contrast, a local minimum negative bias illumination stress instability was observed near 73~77 at% In. This behavior was explained by a poly-crystalline to amorphous phase transition in IZO thin films.
The Interface Modification of Low-Voltage Pentacene-Based Organic Phototransistors
Authors: Liu Xiaohui , Dong Guifang , Duan Lian , Wang Liduo , Qiu Yong
Published: March 2013

Low-voltage organic phototransistors (OPTs) are promising for flexible optoelectronic applications such as photosensors and memories. In this paper, the effects of interface modification on the pentacene-based OPT are investigated. Commonly used polymer materials, polymethyl methacrylate, with different thicknesses are adopted on the high transparency and high permittivity tantalum pentaoxide (Ta2O5) gate dielectric layer. It is found that the thickness of the modifier layer can successfully tune the photosensitive characteristics of the low-voltage OPT. Through analysis of the energy level, the mechanism of the tuning is proposed that the polymeric layer acts as a tunneling layer for high-energy electrons and a blocking layer for low-energy electrons. Our study verifies that interface modification benefits not only the improvement of OPT performance but also the control of its applications in different fields.
(Invited) Materials, Processing, and Characterization for Printed Flexible Electronics
Authors: Wong William S. , Chow Melissa J. , Lújan Rene , Ng Tse Nga
Published: March 2013

An overview of the requirements for flexible image sensor arrays is given. Sensor devices based on amorphous silicon and polymeric bulk heterostructure is analyzed and compared. Organic and inorganic sensor performance under applied stress is compared and a charge-map testing and characterization technique for flexible arrays is described. Finally, the fabrication of a flexible organic sensor array is presented.
A Novel LTPS TFT Pixel Circuit for Compensating IR Drop of Large Area AMOLED Display
Authors: Lee Soo-Yeon , Kuk Seung-Hee , Song Seung-Min , Song Moon-Kyu , Han Min-Koo
Published: March 2013

We have proposed a new AMOLED pixel design compensating IR drop besides threshold voltage (Vth) variation of LTPS TFTs without any additional signal. The SPICE simulation results show that the proposed pixel, which consists of 7 PMOS TFTs and 1 capacitor, successfully compensates not only Vth variation but also IR drop. Vth of the driving TFTs are detected and data voltage can be memorized when PMOS only inverter has high input voltage.
Memory Thin Film Transistor with Monolayered Nanoparticles through Chemical and Biological Bindings
Authors: Lee Hyun Ho , Jung Hunsang , Kim Minkeun , Kim Yejin , Oh Sewook , Yoon Tae-Sik
Published: March 2013

To have an efficient monolayer of charging element in the memory OTFT, metallic or semiconductor nanoparticles (NPs) and surface of dielectric layers have been functionalized to accomplish specific binding mechanisms. In this study, using a strong chemical and biological binding system, polyaniline (PANI) NPs and Au NPs were monolayered between pentacene and organic dielectric layer in OTFT device. The PANI NPs were monolayered by epoxy-amine bonding and Au NPs were functionalized with streptavidin protein and the dielectric surface was modified by 3-amino-propyltriethoxysilane (APTES) and N-hydroxysuccinimide (NHS)-biotin. The memory OTFT can be applicable to develop a new conceptual device.
Ambipolar SnO Thin-Film Transistors and Inverters
Authors: Liang Lingyan , Cao Hongtao
Published: March 2013

Top-contact and bottom-gate thin-film transistors (TFTs) were fabricated employing polycrystalline SnO films as the channels. The influence of channel thickness, source/drain electrode materials with different work function and post-annealing of the devices on the electrical properties of the TFTs was systematically investigated. Ambipolar TFTs which possesses balanced electron and hole field-effect mobilities were achieved. Complementary metal oxide semiconductor (CMOS) - like inverters using the SnO dual operation transistors were also demonstrated with a gain up to 30. These results also demonstrate that, a simple route in realizing oxide-based ambipolar TFTs and CMOS-like inverters, provides a robust addition to the existing CMOS technology community.
(Invited) Advanced CMOS Scaling and FinFET Technology
Authors: Nowak Edward Joseph
Published: March 2013

Conventional scaling of planar CMOS devices has reached a practical electrostatic design limit at roughly 25nm gate lengths, corresponding to the 20nm node. The double-gate transistor has long been known to offer the potential to extend electrostatic scaling and in the last dozen years, workers around the world, in academia and industry, have applied a vertical fin-like embodiment of the double-gate FET, most popularly referred to as the 'FinFET,' to tackle the challenges of process, device, and product design, and accomplish the introduction of double-gate FETs into main-stream manufacturing. A view of these challenges and their solution leads to a projection that this FinFET structure will prove scalable to at least the atomic limit of CMOS scaling.
(Invited) FinFET and UTB--How to Make Very Short Channel MOSFETs
Authors: Hu Chenming
Published: March 2013

New materials with enhanced mobility are clearly going to be important to the IC industry. In addition, the leakage current in future short gate transistors must be suppressed somehow. FinFET was developed for this goal. Its fin shape or its 3D nature is not the reason for its ability to suppress the leakage current. A 2D planar short gate structure, Ultra-Thin-Body (UTB), was proposed and demonstrated at the same time as FinFET. Together they illustrate a new scaling principle. Future monolayer semiconductor transistors are naturally UTB and highly scalable.
Effect of Fin Doping Concentration on the Electrical Characteristics of Germanium-on-Insulator Multi-Gate Field-Effect Transistor
Authors: Liu Bin , Gong Xiao , Zhan Chunlei , Han Genquan , Daval Nicolas , Veytizou Christelle , Delprat Daniel , Nguyen Bich-Yen , Yeo Yee-Chia
Published: March 2013

We demonstrate the integration of high performance p-channel Germanium MuGFETs on GeOI substrate using a simple sub-400 º C process module. Ge fin doping effects on performance of Ge MuGFET are discussed for further device optimization on GeOI substrate. It is found that higher fin doping leads to better short channel control of Ge MuGFETs on GeOI but degrades the on-state current and transconductance. A record high on-state current for Ge MuGFETs is reported in this work.
Germanium Gate-All-Around pFETs on SOI
Authors: Chang Hung-Chih , Hsu S.-H , Chu C.-L , Chen Y.-T , Tu W.-H , Sung P.-J , Luo G.-Li , Yin Y. –C. Yin , Liu C. W.
Published: March 2013

The triangular Ge GAA pFET was fabricated and simulated. The hole concentration was obtained from spreading resistance profiling (SRP) and used in the simulation. Device with fin width (Wfin) of 52nm and Lg of 183nm has Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 μA/um at Vd= -1V. The Dit of 2×1012 cm-2eV-1 for EOT of 5.5 nm is confirmed by charge pumping measurement on planar devices and numerical simulation of triangular FinFET. The TCAD simulation shows the leakage current through SOI is only 10-7X of channel current when dislocated Ge on SOI is completely etched and the fin is floated on nothing.
Selective Growth of Strained Ge Channel on Relaxed SiGe Buffer in Shallow Trench Isolation for High Mobility Ge Planar and Fin p-FET
Authors: Vincent Benjamin , Witters Liesbeth , Richard Olivier , Hikavyy Andriy , Bender Hugo , Loo Roger , Caymax Matty , Thean Aaron
Published: March 2013

Strained Ge channels on SiGe strain relaxed buffer are grown selectively in active areas surrounded by Shallow Trench Isolations. Using advanced Reduced Pressure Chemical Vapor Deposition techniques, more than 2GPa stress was implemented for enhancing mobility in future Ge planar p-Field Effect Transistors (using a Si0.5Ge0.5 buffer layer) and in Ge p-FinFET(using a Si0.28Ge0.72 buffer layer) channels. The approach proposed can be co-integrated with Si or IIIV nFET channel processing.
(Invited) Advanced Transistor Architectures for Half-Terahertz SiGe HBTs
Authors: Heinemann Bernd , Fox Alexander , Rücker Holger
Published: March 2013

Different technological implementations of high-speed SiGe HBTs are compared which all represent a performance level of fmax close to 500 GHz. In addition to technologies with non-selective base epitaxy, a fully self-aligned emitter-base architecture with selective base epitaxy is considered. Fabrication details, DC and RF characteristics of these approaches are examined side by side in order to establish likenesses and differences of their high-frequency potential.
Improved Frequency Response in a SiGe npn Device through Improved Dopant Activation
Authors: Adkisson James , Khater Marwan , Gambino Jeff , Cheng Peng , Jain Vibhor , Camillo-Castillo Renata , Lavoie Christian , Sutton Akil , Gluschenkov Oleg , Liu Q.Z. , McDevitt Tom , Engelmann Sebastian , Pekarik Jack , Harame D. L.
Published: March 2013

We study the impact of improved dopant activation in a BiCMOS SiGe technology, using laser annealing to improve activation, and a low temperature contact module to avoid de-activation. We present the results of simple DC test structure measurements and high frequency bipolar transistor measurements. Improved activation significantly reduces sheet resistance, particularly for polysilicon layers. Likewise, reductions in the bipolar device resistance parasitics cause an improvement in maximum power gain frequency (fMAX).
Evaluation and Modeling of Relative Importance of RF Noise Sources in SiGe HBTs Using Various Noise Representations
Authors: Xu Ziyan , Niu G.
Published: March 2013

We evaluate the relative importance of different RF noise sources in SiGe HBTs through analytical expressions of noise correlation matrices for various representations. The relevant importances of terminal resistance thermal noise and correlated intrinsic terminal current noise are shown to vary with representation, and within the same representation, vary from element to element in the noise correlation matrix. An important analytical result is that the largest impact of base resistance on HBT noise figure is not the thermal noise it produces, but instead is its impact as an impedance element in affecting the propagation of intrinsic transistor terminal noise currents towards the extrinsic terminals. As a result, the importance of noise correlation in affecting transistor noise parameters is highly dependent on the base resistance, and for practical SiGe HBT technologies, correlated intrinsic terminal noise dominates over thermal noise in determining minimum noise figure.