bluuebunny/crossref_metadata_2025 huggingface dataset:
Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors
Authors: Yiyang Li , Fuller Elliot James , Asapu Shiva , Agarwal Sapan , Kurita Tomochika , Yang J. Joshua , Talin Albert Alec
Published: February 2020

Neuromorphic computers based on analog neural networks aim to substantially lower computing power by reducing the need to shuttle information between memory and logic units. Artificial synapses containing analog, non-volatile conductance states enable direct computation using memory elements; however, most non-volatile analog memories require high voltages and current densities, and have nonlinear and unpredictable weight updates. Here, we develop a redox transistor based on electrochemical ion insertion into LixTiO2 that not only enables linear weight updates at low current densities, but also has no baseline open-circuit voltage. The absence of an open-circuit voltage offset enables its pairing with a diffusive memristor acting as selector to create a Si-free synaptic memory cell with write voltages as low as 170 mV. We further show that the LixTiO2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade (at 80° C) when operating in an electrochemically driven phase transformation regime.
(Invited) Electron Beam Induced Current Microscopy of Interfacial Barrier Effects in Al2O3/TiOx Resistive Switches
Authors: Hoskins Brian Douglas
Published: February 2020

Resistive switching devices (ReRAM) represent a broad class of two-terminal continuously tunable resistors including memristors, phase change memory (PCM), valence change memory (VCM), and electrochemical metallization cells (ECM). Though these devices, especially PCM, are increasingly being commercialized by industry for use in next generation memories, they are also all actively studied for use as synaptic weights in next generation hardware-accelerated neuromorphic networks.

We have previously investigated Electron Beam Induced Current Microscopy as a means of reliably characterizing resistive switches. In that investigation, we observed surprising electronic effects, such as internal secondary electron emission, in addition to more traditional electron-hole pair separation, and we broke those up into constituent currents based on their origin through Monte-Carlo modeling of the electron beam-matter interaction.

Now, armed with a new understanding of the physics of EBIC imaging, we study the impact of manufacturing variations on resistive switches by continuously tuning the thickness of an Al2O3 interfacial barrier. Shifts in the apparent ratios of internal secondary electron emission from the top electrode to the bottom electrode and vice versa appear to indicate a continuous tuning of the apparent filament diameter as both a function of the injected current and the interfacial barrier thickness. This yields an apparent reduction in the current density, the primary effect of which is a reduction in the device damage from forming and a suppression of parasitic leakage currents imaged in devices without interfacial barriers.

Figure 1
Memristive Behavior in Core-Shell Nanowire Networks for Neuromorphic Architectures
Authors: Vasisth Shangradhanva Eswara , Palenzuela Jadie , Maruyama Hiraku , Nino Juan C.
Published: February 2020

Continuous enhancement of performance and processing powers of computing devices will soon reach a technological and physical limit and to overcome this, systems emulating the human brain are being developed. Presently, mathematical models known as artificial neural networks (ANNs) are designed to simulate the computational abilities of the brain. Due to large simulation times, the current digital ANNs cannot be efficiently scaled. By contrast, analog (as opposed to digital) neuromorphic devices with dedicated and adaptable synapses are expected to rival the scale and efficiency of the brain. Memristors are two-terminal electrical component where the resistance is a function of the amount and direction of current and therefore they can uniquely emulate biological synapse behavior. Here, we discuss memristive behavior of Ti/HFO2/Pt core shell nanowire systems and networks for neuromorphic architectures and discuss their potential application as ANNs. In prior studies, memristive architectures for neuromorphic computing are connected through a crossbar array of neurons. With a limit on the number of neurons and regular connectivity, the networks lack sparsity and randomness. As a result, they have high wiring cost and poor functional connectivity. To address such limitations, we have fabricated a random array of core-shell memristive wires to form the connectivity matrix for neuromorphic hardware. In the systems listed above, the conductive core (Pt or Ti) serves as the bottom electrode with a memristive shell (HfO2) that can be electroformed with a set of top electrodes (Ti or Pt) deposited on the surface. Prior to miniaturization, as proof of concept, the core-shell wire networks were fabricated using 20 μm tungsten fibers as conductive cores with tungsten oxide as memristive shells. After imprinting of top silver electrodes and electroforming, IV measurements revealed memristive behavior with switching between resistive states (i.e., LRS-HRS) at ±1 V. Subsequently, nanowire networks based on the Ti/HFO2/Pt system were fabricated using electron beam lithography (EBL). For example, in one embodiment, over 90 overlapping core (40 nm)-shell (5 nm) nanowires were written on a 200 μm × 200 μm write field. To complete the connectivity matrix, 64 nodes and individual vias connecting the resulting network to electrode pads were written and deposited. Network quantifying simulations revealed a small-world coefficient of 2.89, shortest path length of 3.61 and clustering coefficient of 0.057. After electroforming, the core-shell structures exhibited switching between LRS and HRS at ±7 V. In this presentation, the fabrication process and the memristive characteristics (endurance, resistance retention, pulse measurements, etc.) of the fabricated nanowire network structures will be discussed in detail.
(Invited) Trends in 3D Markets and Technology
Authors: Vardaman E. Jan
Published: February 2020

Driven by performance, 3D packaging with through silicon vias (TSVs) has become a reality for memory and advanced logic. New versions are emerging.

High Bandwidth Memory (HBM) is one of the most important 3D IC developments in the last 10 years. In the last decade, stacked DRAM with through silicon vias has transitioned from a handful of research programs to rapidly increasing volumes.

Tezzaron has been providing small quantities of 3D ICs for high-speed memory applications since 2005. Micron, Samsung, and SK Hynix began producing DRAM stacks with TSVs in late 2014 and early 2015. Micron began shipments of its Hybrid Memory Cube (HMC) in 2015. DRAMs and the logic controller were interconnected with TSVs. HMC was packaged in a BGA and tested before assembly on the board. The HMC has been used in Intel’s Knights Landing. The silicon-on-insulator (SOI) logic layer was fabricated by GLOBALFOUNDRIES (which purchased IBM’s fab) and the memory was fabricated by Micron. Micron used a thermo-compression bond (TCB) process with a non-conductive film (NCF) underfill for its die stacking in the HMC. Thermal issues were a challenge. Today Samsung and SKHynix are providing HBM stacks to the industry and Micron is expected to ship products next year.

In February 2018, Samsung announced that its first “three-layer” stacked CMOS image sensors (CIS) were in mass production and found in the Galaxy S9/S9+. This follows Sony’s adoption of three-layer CIS technology one year earlier in February 2017. A third silicon layer in the form of DRAM is added to the pixel array and signal processing layers to significantly improve data readout speeds. These devices are manufactured with 3D IC technologies using TSVs, but Samsung and Sony use different design approaches. Technically speaking, Samsung’s solution is a two-layer image sensor with a stacked DRAM. Sony uses a true three-layer bonded approach. In its three-layer CIS technology, Sony places the DRAM between the pixel array die and the image processor, with all three layers interconnected using TSVs. The pixel array, DRAM, and logic wafers are manufactured with 90nm, 30nm, and 40nm processes, respectively.

While logic and memory stacks have remained elusive, Intel and TSMC have introduced new packaging technology with active interposers that are considered 3D. Intel has introduced its Foveros 3D integration technology as a form of heterogeneous system integration. The technology uses a 3D face-to-face stacking process. In the process, logic die are bumped and mounted on an active interposer next to memory or die with other functions. The active interposer can contain active parts of the system, such as the platform controller hub (PCH) that manages I/O for the system. The active interposer is mounted on a package substrate with solder bumps. TSMC has introduced its SoIC with face-to-face stacking and wafer-on-wafer (WoW). These technologies are front-end packaging and use direct or fusion bonding. The SoIC is a wafer with logic, with our without TSVs.
(Invited) Characteristics, Types and Development Direction of the Copper Foils for Batteries
Authors: Kim Young tae , Jun Sang hyun , Lee An na , Kim Ho gun , Kim Seon hwa
Published: February 2020

Copper foil with low electrical resistivity was originally developed as an improved interconnect material for printed circuit boards. Since the development of lithium-ion batteries in the 1990s, copper foil has been used as anode current collectors in secondary batteries.

The control of copper electroplating conditions is a vital factor in the manufacturing of such copper foils. The manufacturing process comprises plating on a drum, surface treatment, and slitting. In particular, the core process of copper electroplating is the control of the additive recipe in copper electroplating. KCFT (Korea Copper Foil and FCCL Technologies) in South Korea is one of the leading companies in the world to develop these technologies.

Copper foil has the characteristics of double-sided shine. Since it is generally coated on both sides, the characteristics of both sides should be similar. For batteries, an anode is fabricated by coating an active material, such as natural or artificial graphite, on a copper foil. Batteries may be of the cylindrical, prismatic, or pouch types. The cylindrical-type battery is manufactured as a jelly roll, and the pouch-type battery is usually made by laminating. Depending on the properties of the copper foils, they can be classified as follows: general, high-strength, high-elongation, and high-strength and high-elongation types. The desired copper foil properties can be realized by controlling the grain size and its growth inhibition during heat treatment.

The direction of development for the copper foils for batteries is first to manufacture thin copper foil. The capacity or weight of the thin copper foils can be enhanced or reduced, respectively. Second, the stable handling of the battery manufacturing process should be realized.

Third, the copper foil productivity will be improved by adopting high-current-density plating or manufacturing longer and wider products. Finally, in order to improve the reliability of the batteries, copper foil swelling and breakage should be prevented by using high-strength materials and high-elongation materials for cylindrical-type batteries.

In conclusion, there is the need to develop of copper foil well based on the understanding of the role of additive and the understanding of the metal structures.
Electroless Copper Deposition Using Complexed Copper(II) Ion As Catalyst for Printed Circuit Board Fabrication
Authors: Dow Wei-Ping , Chuang Yu-Chien
Published: February 2020

Electroless (ELS) copper plating process has been commonly used for printed circuit board (PCB) metallization. The traditional ELS copper plating process uses tin/palladium colloid or complexed palladium ion as catalysts for ELS copper deposition. But the price of palladium catalyst is much higher than that of gold. Herein, we use complexed copper(II) ion to replace the palladium catalyst in order to greatly reduce the process cost but maintain the performance and the reliability of the complexed copper(II) ion as good as palladium. The synthesis process of the complexed copper ion is simple and its cost, which compared with palladium, is cheap. Especially, they have no oxidation issue because they are not metallic copper nanoparticles but copper(II) ions. Before ELS copper plating, the grafted copper(II) ion that is chemically adsorbed onto the substrate surface is reduced to copper atom, so they can catalyze ELS copper deposition. In this work, we optimize the experimental parameters such as operating temperature, reaction time, copper ion concentration and the pH of the plating solution.

After ELS plating process, the backlight test of through holes (THs) of a PCB and the morphology of the ELS copper deposited onto the sidewalls of the THs are evaluated by optical microscope (OM) and scanning electron microscope (SEM), respectively. The thermal reliability of the ELS copper deposition catalyzed by the grafted copper catalyst was examined after copper electroplating using thermal shock in a tin bath at 288℃ for ten seconds and repeated it for 5 times. Results show that it can pass the thermal shock test. Therefore, the application of complexed copper(II) ion as the catalyst of ELS copper plating is expected to replace the expensive palladium for PCB fabrication.
Conductivity Modification of Reduced Graphene Oxide (rGO)
Authors: Lee Yu-Guan , Dow Wei-Ping
Published: February 2020

In the traditional circuit board metallization process, the electroless plating process is the most common, but it contains precious metals (such as palladium catalyst), formaldehyde and chelating agents which can cause a serious environmental problem. However, the direct reduction process of graphene oxide (GO) does not include the toxic as mentioned above. In additionally, reduced GO (rGO) can be regarded as a direct plating process (i.e., without electroless deposition before copper electroplating) is simpler than electroless plating process and can replace the electroless plating process to achieve a green metallization process.

Although rGO is a good electric conductor, copper is difficult directionally deposited on it due to its p-electron characteristics, which transfers only in X-Y two-dimensions. Therefore, when rGO is electroplated in a copper electroplating solution, the deposited copper crawls initially from the cathodic terminal and then fully cover the rGO-coated substrate if the surface area of the substrate is large.

In this work, we propose an approach to enhance the conductivity of rGO in Z-direction, so that rGO will have three-dimensional conductivity to meet the industrial requirement.
(Invited) CdTe/Si-Roic Staced X-Ray Imaging Sensor
Authors: Aoki Toru , Takagi Katsuyuki , Takagi Toshiyuki , Kase Hiroki , Koike Akifumi
Published: February 2020

CdTe photon-counting X-ray image sensor with charge-counting readout IC was developed for high quality X-ray imaging. CdTe is one of the good material for X-ray imaging, because it has i) high sensitivity for X-rays by high atomic number (Average 50), ii) room temperature operation with low thermal noise by large band-gap (1.44eV) , and iii) direct conversion from X-ray photon to electron-hole pair (charge). CdTe also has electron mobility (1,100cm2/V/s) and large ut. It is very good properties for X-ray sensor, and it can be processed by using laser processes and some semiconductor post processes.

It is very difficult to make integrated circuit on CdTe wafer, however, we shold stack Si-readout IC and CdTe multi-pixel sensor chip. In this paper, we use sliver paste based bumping for this stack connection. We developed new readout IC, and report in this paper.

A direct charge conversion LSI (Si readout IC) for photon counting X-ray imaging sensor has been fabricated by TSMC 0.18um CMOS process. This LSI is designed to prove a behavior of the direct charge conversion architecture based on charge injection [1] for photon counting with energy information. The LSI has charge-to-digital convertors (QDC) used to read out a charge generated by an X-ray detector such as CdTe and digitize energy information of the source X-ray photon. The QDC realizes 15 energy windows within 200 keV and the LSI provides two 12-bit memories to output two images with differential energy information simultaneously. The LSI has 1600 QDCs and its pixel pitch is 80um. Analogue behaviors of the QDC, characteristics of energy discrimination and a capability to take X-ray/gamma-ray images have been tested. As the results, a desired gain and good linearity are equipped on the QDC, spectra of 241Am and 57Co can be discriminated, and differences between with and without a material have been shown as image. We demonstrate X-ray penetrate image and report in this paper.

References: [1] K. Takagi, et al., Sensors and Materials, Vol. 30, No. 7 (2018) 1611–1616

Fig.1. Direct charge conversion LSI with pixilated CdTe detector.

Figure 1
Low-Dielectric Constant Nanoporous Epoxy for Electronic Packaging
Authors: Jiang Jisu , Keller Landon , Kohl Paul A
Published: February 2020

Epoxide functionalized poly(propylene carbonate) was included in an epoxy resin formulation and thermally decomposed to create nano-porous epoxy films. The dielectric constant of the porous epoxy was lower than the epoxy formulation control. The introduction of 30% porosity in the epoxy lowered the dielectric constant from 3.78 to 2.76. A post-porosity chemical treatment further lowered the dielectric constant. Hexamethyldisilazane was used to terminate the pore walls with the hydrophobic silane layer and reduce both the dielectric constant and tangent loss of the porous epoxy. Two different styrene maleic anhydride crosslinking agents were used in the epoxy formulation, SMA2000 and SMA4000. The effect of the maleic anhydride concentration within SMA on the electrical, mechanical, and thermal properties of porous epoxy film was evaluated. Epoxy films crosslinked with SMA2000 resulted in films with a higher dielectric constant compared to films prepared with SMA4000 due to higher mole fraction of maleic anhydride within SMA2000. However, SMA2000 cross-linked films yielded films with better mechanical and thermal properties. SMA2000 cross-linked films with 30% porosity had a coefficient of thermal expansion of 35.2 ppm/K and glass transition temperature of 143 °C.
(Invited) Ion Implantation and Activation of n- and p-Type Dopants in GaN
Authors: Anderson Travis J. , Gallagher James C , Jacobs Alan G , Feigelson Boris , Hite Jennifer K. , Mastro Michael A , Foster Geoffrey M , Koehler Andrew D , Hobart Karl D.
Published: February 2020

GaN-based power switching devices are of significant interest for high efficiency power conversion circuits in medium voltage applications. However, there are still significant challenges preventing mass production and widespread adoption. Recently, GaN-based vertical and lateral power devices have attracted significant interest due to promising device results coupled with progress in native substrate, epitaxial growth, and processing technology developments. However, there are two significant limiting factors for vertical GaN power devices at present. The first issue is substrate and epitaxial layer uniformity and reliability, and the second is the lack of a planar selective-area doping process. While p-type epitaxial growth capability and the ability to stack layers are quite mature from the LED industry, power devices require planar selective-area doping, which is a routine step by ion implantation in the Si and SiC device industry. The ability to implant and activate dopants, particularly p-type dopants, in GaN still remains a challenge as implant activation typically requires annealing at temperatures ~ 2/3 of the melting point, which is a region where the GaN crystal is unstable and readily decomposes to Ga + N2 at atmospheric pressure. The NRL-developed symmetric multicycle rapid thermal annealing (SMTRA) technique has been the most successful, demonstrating electrical activation of up to ~10% of the implanted Mg dopant atoms using a combination of a temporary, thermally stable capping layer, annealing in a moderate nitrogen overpressure, and performing a well-optimized annealing temperature profile including multiple spike anneals. Advances in the SMRTA process development, including optimization of capping processes, implantation profile, and processing steps such as metallization and surface treatments will be reviewed here. In addition, the evaluation of components of the SMRTA process, such as the cap and overpressure anneal, have been applied to Si implantation for n-type doping and will be presented here. This is a critical step to reduce contact resistance in lateral GaN structures as well as form the source regions of vertical devices that is typically accomplished by selective area regrowth. The use of ion implantation and activation utilizes fewer process steps and avoids impurity incorporation at sidewalls compared to the selective area regrowth process, and has been shown to yield lower contact resistance as well. This presentation will review advances in both Mg and Si ion implantation and assess the viability of this process for practical device fabrication.
Advancements in High Indium Content Alinn Grown Via Metal Modulated Epitaxy and Application Towards Polar/Non-Polar Optical Devices
Authors: Engel Zachary , Clinton Evan A. , Matthews Christopher M. , Doolittle W. Alan
Published: February 2020

AlInN has been a topic of recent study due to its unique property among III-nitrides of lattice matching to GaN at a composition of 18% indium, making it a strong candidate for power electronic and optoelectronic applications. A widely unexplored area is the application of AlInN towards visible/Near-IR optical devices. AlInN has a tunable bandgap, spanning the infrared to ultraviolet range, of 0.7 to 6.1eV. At a composition of about 70% indium AlInN has a perfect bandgap, 1.7eV, for tandem solar cells with silicon and for various optical communications applications. Challenges exist with the growth of AlInN as a result of the large lattice parameter mismatch and differences in growth regimes between the two binary components. At the low temperatures required for the growth of AlInN the aluminum adatoms have a low mobility, often leading to lateral phase separation in the film. Metal Modulated Epitaxy (MME) offers a good solution to the growth issues of AlInN. This flux modulated technique allows for growth under metal rich conditions, increasing surface diffusion lengths of the Aluminum while limiting droplet formation and terminating in a dry surface suitable for devices.

For comparison ~100 nm thick high indium content AlInN samples were grown using nitrogen rich (0.8 III/V ratio) MBE and MME using a III/V ratio of 1.3 with a dose designed to prevent surface segregation (details supplied at the conference). Both films were grown cold at 375 degrees C to limit phase separation The MME sample showed improvement over the MBE sample in crystal quality and surface roughness, with the XRD (0002) reflection FWHM improving from 783 arcsec to 184 arcsec, the XRD (10-15) reflection FWHM improving from 2456 arcsec to 1421 arcsec, and the AFM surface roughness improving from 1.52nm rms to 0.882nm rms between the MBE and MME samples respectively. The carrier concentrations of both samples were found to be about 1E19 cm-3 via hall measurement implying that like InN, In-rich AlInN may suffer from excessive residual electron concentrations and/or surface fermi-level pinning. Optical measurements will be presented at the conference.

The same MME growth conditions were used to grow 100nm of indium rich AlInN directly on a (111) p-silicon substrate. Simple indium contacts were used to contact the Si and AlInN. Vertical conduction and rectification between the silicon and AlInN layers were observed in this large area (~0.25x0.25 cm2) device. Understanding of the limitations of and physics governing this promising vertical polar/non-polar heterojunction will be given at the conference. Additionally, results from various growth conditions will be detailed.

Figure 1
(Invited) Recent Advances in III-Nitride Devices Using Ultrawide Bandgap AlxGa1-Xn Active Layers
Authors: Khan Asif
Published: February 2020

III-Nitride devices with high-Al AlxGa1-xN (x>0.4) active layers have the potential of addressing several key application areas. For these high Al-compositions the direct bandgap leads to a cut-off wavelength<290 nm which makes the material ideal for solar blind detectors. Similarly, AlxGa1-xN (x>0.4) multiple quantum wells (MQWs) are used in the active region of the deep ultraviolet (DUV) light emitting diodes. More recently, to take advantage of the higher breakdown field for high voltage devices, several researchers including us have explored Heterojunction Field-Effect Transistors (HFETs) and metal-oxide-semiconductor (MOS) HFETs with high-Al AlxGa1-xN (x>0.4) channel layers.

Currently nearly all the (UWBG) AlGaN devices are fabricated on 3-5 µm thick MOCVD grown high quality AlN/sapphire templates. This choice is dictated by the deep UV optical transparency, the easy availability and the low-cost of sapphire. Increasing the AlN template thickness to larger than 5 µm leads to stress related cracking. The low thermal conductivity of sapphire and this AlN growth thickness limitation leads to device performance limitations especially for high power operation. To avoid this, recently using a pulsed MOCVD approach, we have for the first time succeeded in growing 16 µm thick, crack-free, low-defect AlN template layers on basal plane sapphire substrates. These were then used to deposit epitaxial structures for the AlGaN channel HFET/MOSHFETs. In this presentation we will present studies to establish the role that the high conductivity thick AlN buffers play in improving the devices’ electrical and thermal performance.

Recently we have also for the first time conducted optical waveguiding studies at UVC wavelengths. For these studies we fabricated monolithically integrated UVC LEDs, detectors and waveguides on an AlN/sapphire template platform. Optical attenuation coefficient as low as 4.8 cm-1 was measured for Al0.5Ga0.5N waveguide with an AlN clad layer. Details of our integrated device fabrication and optical losses measurements scheme will also be discussed.

Acknowledgement: This work was partially supported by Defense Advanced Research Projects Agency, Army Research Office and Office of Naval Research (Monitors: Dr. M. Gerhold. Dr. Paul Maki and Dr. Lynn Petersen).
(Invited) Heterogeneous Integration of III-V Semiconductors for Imaging and High-Speed Communication
Authors: Wood Michael G
Published: February 2020

Heterogenous integration of III-V compound semiconductors with Si circuitry is an enabling technology for applications including high-bandwidth communications [1], focal plane arrays [2] and concentrating solar cells [3, 4]. Typical integration schemes include low temperature flip-chip bonding using indium bump bonds along with epoxy underfill and may include the integration of micro-optics for collimation and focusing.

In this talk, I will discuss previous and ongoing compound semiconductor heterogenous integration efforts at Sandia National Laboratories and the challenges involved in forming high-yield devices. Specific programs to be discussed include the ARPA-E MOSAIC solar concentrator (Fig. 1), infrared focal plan arrays (Fig. 2), and the recently-awarded DARPA PIPES ultra-low-energy-per-bit photonic transceiver.

References

Ciftcioglu, et al, “3-D integrated heterogenous intra-chip free-space optical interconnect,” Opt. Express, vol. 20 2012.

W. Peters, et al., “Resonant ultrathin infrared detectors enabling high quantum efficiency,” IEEE RAPID, 2018.

Li, et al., “Wafer integrated micro-scale concentrating photovoltaics,” Prog. Photovoltaics, vol. 26, 2018.

H. Jared, et al., “Integration of wafer-level solar cells and micro-optic concentrators for micro-scale concentrating photovoltaics,” ASPE Annual Meeting, 2017.

Acknowledgment

This work was supported in part by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Figure 1
Dislocation Compensation in a Metamorphic Semiconductor Heterostructure Utilizing a Uniform or Graded Buffer Layer
Authors: Kujofsa Tedi , Islam Md Tanvirul , Ayers John E
Published: February 2020

Semiconductor device structures are often grown metamorphically on lattice-mismatched substrates using an intermediate buffer layer to accommodate the lattice mismatch and reduce the threading dislocation density. These structures have traditionally been designed empirically but this may not yield the optimum structure in terms of dislocation density reduction. Recently advancements in the understanding of dislocation dynamics have made it possible in principle to design the buffer layer and device structure so that all glissile threading dislocations in the buffer layer are diverted at the interface for the creation of misfit dislocations. In this paper we present a criterion for the complete removal of threading dislocations from the surface of a device structure on a buffer layer, and we discuss its practical application.
Electrochemical Energy Storage Properties of Hydrogen Titanates As a Function of Interlayer Structural Protonation
Authors: Fleischmann Simon , Augustyn Veronica
Published: February 2020

Electrochemical energy storage devices that offer a combined high energy and power are necessary to meet the demand for future mobile applications. Electrode materials that lead to pseudocapacitive charge storage are of particular interest as they enable Faradaic charge transfer at high rates. This behavior is observed when redox processes are not kinetically limited by the solid-state diffusion of reacting ionic species. Pseudocapacitance has mostly been introduced to transition metal oxides by nanostructuring, thereby increasing the electrode-electrolyte interface and reducing diffusion distances.1 Besides often costly synthesis procedures, the materials can show a low density and are hard to integrate in macroscopic electrode structures. A new approach to transition from battery-like to pseudocapacitive charge storage behavior is the use of layered metal oxides with interlayer molecules like structural water.2

Hydrogen titanates (HTO) can be obtained by a proton exchange reaction of sodium titanate in acidic solution. Monoclinic H2Ti3O7 consists of layers of edge-sharing TiO6 octahedra with hydrogen positioned in the interlayer. Upon heating, the interlayer deprotonates over three discrete steps with the intermediate phases H2Ti6O13 and H2Ti12O25, before forming TiO2(B) (Fig. 1).3 The intermediate phases exhibit reduced numbers of hydrogen atoms in the interlayer. This designates HTO as an ideal model system to study the influence of interlayer structural protonation on the electrochemical intercalation properties.

In this study, we synthesized HTO in different states of reduced interlayer structural protonation by thermal annealing and confirmed the compositions by matching the associated mass loss to the release of 0.5 and 0.75 H2O per H2Ti3O7, respectively. The materials were employed as hosts for proton intercalation in acidic electrolyte. Our results suggest a strong correlation between protonation state of the HTO interlayer and proton storage capacity, with fully protonated H2Ti3O7 offering the highest proton intercalation capacity. We will discuss the influence of interlayer proton mobility on the charge storage properties and correlate the crystal structure changes of the materials with the intercalation process.

Augustyn, V., Simon, P. & Dunn, B. Pseudocapacitive Oxide Materials for High-Rate Electrochemical Energy Storage. Energy Environ. Sci.
7, 1597–1614 (2014).

Mitchell, J. B., Lo, W. C., Genc, A., LeBeau, J. & Augustyn, V. Transition from battery to pseudocapacitor behavior via structural water in tungsten oxide. Chem. Mater.
29, 3928–3937 (2017).

Morgado, E. et al. Multistep structural transition of hydrogen trititanate nanotubes into TiO2-B nanotubes: A comparison study between nanostructured and bulk materials. Nanotechnology
18, 81–93 (2007).

Figure 1
Gravimetric and Volumetric Changes of Carbon Electrodes in Electrochemical Capacitors with Aqueous Electrolytes
Authors: Platek Anetta , Menzel Jakub , Bujewska Paulina , Frackowiak Elzbieta , Fic Krzysztof
Published: February 2020

Ionic fluxes at carbon electrode/electrolyte interface have been already well described for organic medium. This description allowed for comprehensive understanding of the phenomena occuring during electrochemical capacitor operation.

However, the processes on-going in aqueous electrolytes still need to be investigated, since several accompanying phenomena (eg. hydration, corrosion) might occur in this medium.

Our attention is primarily focused on the performance of carbon electrodes operating with pH-neutral aqueous electrolytes, allowing a relatively high capacitor voltage to be reached. Apart from typical capacitive storage, our interest is focused also on hybrid mechanisms, delivered by application of redox-active electrolytes, based on iodides or pseudohalides.

This paper will provide the insights into the ionic fluxes at the electrode/electrolyte interface, monitored by Quartz Crystal Electrochemical Microbalance, Scanning Electrochemical Microscope and Dilatometry techniques.

Preliminary results indicate that the situation at the interface is somehow different than one might expect. For instance, the changes for positive and negative electrode are significantly different, although from electrochemical point of view they appear to follow the conventional cation/anion adsorption manner. In the case of redox-active electriolytes, the situation is even more complicated.

This paper will provide the results from three different techniques - of different modus operandi but allowing for complementary observations and conclusions. Finally, the goal of this work is to understand and identify the phenomena at the interface, mostly in order to prevent the parasitic or detrimental processes and prolong the capacitor lifetime.
Effect of Time, Temperature and Potential on Pre-Conditioning of Supercapacitors
Authors: Roberts Alexander John
Published: February 2020

One unique property of supercapacitors relative to other energy storage devices is their exceptional lifetime, often reported in commercial devices as being over 1 million cycles. This cycle life is most often accompanied with a lifetime relating to a float at maximum voltage for a time of 1000 (or more) hours at a particular temperature, which gives a more practical indication of lifetime in terms of both time to assess and real life application. The end of life for such devices is taken as the point where the capacitance has decreased by 20% and/or the ESR has increased by 100%.

In the early stages of use for a supercapacitor, a significant drop in capacitance and an accompanying increase in ESR, along with an increased level of gas generation are observed, the result of which would be a reduced lifetime by the conditions defined above. In order to maximise the lifetime and performance of supercapacitors, this early stage is taken care of through a pre-conditioning or ‘burn in’ stage during manufacture.

The causes of the early stage issues mentioned are varied and include decomposition of carbon surface functional groups, solvent splitting (electrochemical decomposition, hydrogen and oxygen evolution reactions including decomposition of trace water) with gas evolution and current collector corrosion[1,2]. The typical burn-in procedure requires the cells to be held at a specific potential and temperature for an extended period of time, during which the capacitance fade, ESR increase and gas generation plateau, allowing the device to then exhibit excellent lifetime characteristics. Whilst the need for this step is clear, it is also costly and can be time consuming, requiring significant Capex and energy costs and also tying up significant inventory during the manufacturing process. Improvements and greater understanding of this process presents clear benefits to the manufacturing process and cost reductions.

In this work, the burn-in process has been investigated at various scales, from coin cells through to 100F pouch cells, with differences in the requirements as the cell size increases discussed. Coin cells and small format pouch cells (70x50mm) have been constructed with YP50-F (Kuraray, Japan) activated carbon electrodes and TEABF4 in acetonitrile electrolyte and have been conditioned at 25oC and floating at 2.7V for 72 hours to ensure a lifetime of over 1000 hours. The temperature and potential of the burn-in has then been varied to shorten the process time and also reduce the total electrical energy required to achieve the same lifetime of device in terms of capacitance and ESR. Furthermore, the effect of water content of the electrolyte on the performance and burn-in process has been investigated.

[1] S. Phadke, S. Amara and M. Anouti, Chem Phys Chem., 18, 2364, 2017

[2] M. He, K. Fic, E. Frackowaik, P. Novak and E. J. Berg, Energy Environ. Sci., 9, 623, 2016
(Invited) Nanoarray Electrodes for High-Rate Thin-Film Batteries
Authors: Fan Hong Jin
Published: February 2020

Nanoarray electrodes are particularly investigated for power source in microelectronics, which requires high rates, high areal capacity/capacitance and long cycle stability. When the battery electrode materials are designed into nanostructures (e.g., 1D array, 2D nanosheets), the pseudocapacitive effect may become dominating and can boost the power performance. In addition, choosing layered materials with single-phase solid-solution reaction with metal ions is also useful to enhancing the fast charging capability. Our group has been actively working on array-type nanomaterials that are grown directly on conductive substrates as the electrodes of metal-ion batteries. In this talk, I will present the following:

(1) demonstration of vanadium based intercalation-type cathode (e.g., V2O5, NVOPF) and tin based alloy-type anodes in Na-ion storage. Zn-ion batteries based on ZOV cathode and 3D Zn anode with high cyclic stability will also be discussed. These examples demonstrate effectiveness of nanostructure design to boost specific power (i.e., maintaining decent capacity at high discharge currents).

(2) hybrid capacitors (one battery-type electrode and the other capacitive-type electrode) that deliver high-power performance.

(3) Design of electrocatalytic bi-functional cathodes for metal-air batteries that have significantly capacity retentions and flexibility upon long cycles.

Keywords: Na-ion battery, Zn-ion battery, hybrid battery, pseudocapacitive effect, high power energy storage.

References:

Dongliang Chao, et al., Adv. Mater. DOI: 10.1002/adma.201804833.

Ming Song, et al. Funct. Mater. Invited Review, DOI: 10.1002/adfm.201802564.

Dongliang Chao, et al, Mater. (2018), DOI: 10.1002/adma.201803181.

Dongming Xu, et al., Energy Mater. DOI: doi.org/10.1002/aenm.201702769.

Huanwen Wang, et al, Non-Aqueous Hybrid Lithium and Sodium Ion Capacitors, Adv. Mater. 1702093 (2017)
Investigation of Li4Ti5O12 As a High Power Anode Material in Li-Ion Capacitor (LIC),
Authors: Akintola Taofeek , Shellikeri Annadanesh , Akintola Tawakalt , Bolufawi Omonayo , Zheng Jim P.
Published: February 2020

Li-ion capacitor (LIC) technology is an advanced energy storage device that helps bridge the massive gap between Li-ion batteries (LIBs) and electric double-layer capacitor (EDLC), by incorporating the inherent advantages of both devices. It uses a LIB material as an anode (e.g. hard carbon or graphite) and EDLC (e.g. activated carbon) as a cathode to improve the energy density, power density, and cycle life. However, there are some applications that need an extremely fast rate of charge and discharge (high rate performance) which the present LIB electrode material used in LIC cannot provide. This is due to various limitations of the LIB electrode material which are; structural damage of the material during high rate performance, the safety of the material, and the cyclability.

Lithium titanate oxide (Li4Ti5O12) is a material that can satisfy the requirements needed in high rate performance. This is because of its zero-strain insertion feature, very high safety, high efficiency, and excellent cyclability. However, it has an inherent problem of low electronic conductivity and poor ion diffusion. In order to address this issues, various approaches have been carried out by many researchers and it includes nano-structuring of the particle size to improve Li+ ion diffusion, surface coating with carbon, composting and many more.

In this work, investigation of Li4Ti5O12 as an anode material in LIC is done by using one synthesis method (sol-gel) to synthesize Li4Ti5O12 of different particle sizes. The effect of different particle sizes of the synthesized Li4Ti5O12 on its performance as an anode in LIC is studied in terms of energy density, power density, efficiency, and cycle life. Cathode to anode ratio effect in LIC performance is also carried out. Also, the study of different carbon coating thicknesses on the Li4Ti5O12 particles and how it affects its performance will also be carried out.
Synthesis of Polyaniline/Co(OH)2/Ni(OH)2 Nanocomposite Electrode Material for Supercapacitor Applications
Authors: Jadhav Vijaykumar
Published: February 2020

We attempt to demonstrate the experimentally supercapacitive performance of polyaniline (PANI) - cobalt hydroxide (Co(OH)2)-nickel hydroxide (Ni(OH)2) nanocomposites (NCs), prepared potentiostically via electrochemical deposition, compared to phase pure individual nanostructures. Amorphous PANI, Co(OH)2 – Ni(OH)2 and NCs are entirely different from one another from the surface appearance point of view, PANI exhibits nanofiber morphology, NCs exhibits nanofiber partially covered with Co(OH)2 - Ni(OH)2 materials and Co(OH)2 - Ni(OH)2 shows platelet morphology. The electrochemical properties of the PANI, Co(OH)2 - Ni(OH)2 and HNs electrodes have been investigated by cyclic voltammograms and galvanostatic charge-discharge. The specific capacitances of PANI, NCs and Co(OH)2 – Ni(OH)2 are found to be 0.59, 50, 46.4, 85.7, 74.1 and 312.5 F/g, respectively, at a sweep rate of 10 mV/s in 1.0 M NaOH electrolyte. The same nature of retention values in area of CV curves and power densities of PANI, NCs and Co(OH)2 – Ni(OH)2 with increased in scan rates are 25.8, 70.5, 75.5, 76.6, 57 and 42.4%, respectively and the same nature of retention in charge density, specific capacitance, and energy density values are 38.7, 33.8, 40.7, 42.6, 23.1 and 17.3% respectively for PANI, NCs and Co(OH)2 - Ni(OH)2 electrodes with increase in scan rate.
Low Temperature Synthesis of Iron Oxide and Nickel Phosphide Based Flexible Redox Electrodes for Supercapattery Application
Authors: Lee Ha Yeun , Surendran Subramani , Sim Uk
Published: February 2020

Energy storage systems play a vital role in rationalizing the imminent energy crisis and ecological discomfort. The modern tactic of resolving the lack of energy density dispute with the flexible supercapattery systems that could provide both high power and energy density in any form such as bending, stretching, twisting, and folding modes are trending in the field of energy storage devices. Here, we interpret a facile and efficient low-temperature approach to prepare iron oxide (Fe3O4) and nickel phosphide (Ni2P) as anode and cathode, respectively. The formation of well-defined, highly crystalline and single-phase pure Fe3O4 and Ni2P was identified through XRD and XPS analysis. The morphological feature portrays the uniform distribution of both the Fe3O4 and Ni2P nanoparticles. The electrochemical activity of the prepared Fe3O4 and Ni2P electrodes revealed improved storage capacity of 106 and 354 C g-1 at a current density of 3 and 1 A g-1, respectively. Successively, a lab scale flexible supercapattery device (Fe3O4 || Ni2P) was fabricated with an improved energy density (31.5 W kg-1) and superior power density (6400 Wh kg-1). Moreover, the fabricated device showed resilient strength and high cyclic stability by retaining 80 % of its initial capacity for about 20000 cycles. Therefore, a facile low-cost route is proposed to fabricate an efficient, flexible supercapattery system with improved storage property expressive kinetics, resilient strength and enhanced flexibility established itself as a potential material for supercapacitor application.
Enabling High-Rate Mn Oxide Pseudocapacitors Using Highly Dispersed Mn3O4 Nanocrystallites
Authors: WU NAE-Lih , Abdollahifar Mozaffar
Published: February 2020

Mn oxides are promising electrode materials for supercapacitors applications. They provide the advantages of high specific areal capacitance and densities, which are beneficial to achieving high device energy density. Nevertheless, they have so far demonstrated insufficient current rate performance, which is related to their poor electronic conductivities. Indeed, the establishment of a conductive network that is capable of efficiently connecting the nano-sized oxide particles within the electrode is essential to giving high current rate capability. In this work, we investigated the interplay between the Mn oxide particle properties and those of carbon conductive additives on the rate performance of the Mn oxide pseudocapacitor electrodes. The investigation adopts Mn3O4 as an example. Mn3O4 nano-crystallite powders having the same primary crystal size but varied agglomeration at the nano-meter scale were synthesized by a novel controlled solution oxidation process. The oxide powders were matched with carbon additives of different morphologies and dimensionalities for constructing electrodes having various electric networking configurations. The correlation between the rate performance of the oxide electrodes and the powder properties of both the oxide and the carbon additives is addressed. In particular, it is demonstrated that remarkable rate performance, along with superb cycle stability, is achieved with highly dispersed oxide nano-crystallites with zero-dimension carbon black additive. The results are important to the architecture design for oxide-based pseudocapacitors.

Figure 1