Thermal Budget Reduction in Triple Gate Oxide Process by Wet Etch Technique
Authors: Tai Hsin , Liao Hsin-Yi , Chen Hsin-An , Tou Pei-Ting , Liu Wei-Ting , Lu Ming-Chen , Ying Tzung-Hua 
Published: February 2020

As transistor geometry shrunk and System on Chip (SoC) requirement increased, chips with multiple operation voltages become regular criteria in IC design specification. It means multiple gate oxide thicknesses have to be integrated in semiconductor manufacturing front-end-of-line (FEOL) process. However, process thermal budget will be one of the concerns of transistor electrical performance shift resulted from diffusion of implantation species. In this study, thicker gate oxide (MV) was etched back by wet chemical as thinner gate oxide (I/O) to reduce gate oxide formation thermal budget. However, wet etching rate was degraded after clean and lithograph sequential processes. The oxidant, in wet clean chemical, oxidized silicon dioxide surface Si-H bonding into Si-OH which reacted with Hexamethyldisilazane (HMDS), commonly used as lithography adhesion material, and form an extremely thin Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on gate oxide surface. Fortunately, Trimethylsiloxy monolayer consists of Si-O bonding and Trimethylsilyl group (-Si(CH3)3) and can be easily removed by O2 plasma treatment.

To reduce thermal budget, induced from furnace process of gate oxide formation, in triple gate oxide process, I/O gate oxide was obtained by thicker MV gate oxide wet chemical etching back, showed as Figure 1.

However, when I/O gate oxide was removed at LV area, showed as Figure 1, step 6, wet etching rate was decreased. Reviewing similar process in I/O area wet etching back process, showed as Figure 1, step 4, the wet etching rate was normal.

To figure out why wet etching rate is different between step 4 and step 6 in Figure 1, both 1:200 dilute HF and gas type HF etching rate and etching rate variation percentage with as growth data were collected by blanket silicon dioxide (SiO2) wafer which quality is same as MV gate oxide and result is showed as Table I. Clean is Piranha and SC1, including SPM (sulfuric acid and hydrogen peroxide mixture, H2SO4+ H2O2) and APM (ammonia, hydrogen peroxide and deionized water mixture, NH3+ H2O2+ H2O) process steps.

In Table I, 1:200 dilute HF etching rates are normal after clean and after HMDS treatment, respectively. However, once combining clean and HMDS treatment, 1:200 dilute HF etching rate was decreased around 7.2%, but gas type HF etching rate didn’t show the same phenomena. Moreover, additional O2 plasma treatment was added in final step, 1:200 dilute HF etching rate became normal.

HMDS is commonly used adhesives between photo resist and coating surface. The mechanism is silylation reaction, showed as Figure 2. HMDS reacted with SiO2 surface hydroxyl group (-OH) and formed Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on SiO2 surface which changing surface property from hydrophilic into hydrophobic. Adhesion between Photo resist and SiO2 surface had been improvement due to the enhancement of van der Waals’ force.

Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation amount depends on hydroxyl group (-OH) amount on SiO2 surface. From Table II, after clean process, SiO2 surface hydroxyl group (-OH) increase due to the existence of hydrogen peroxide in clean chemical. The SiO2 surface become more hydrophilic, water contact angle decreased from 35.3° to 14.8°. After HMDS priming, SiO2 surface hydroxyl group (-OH) were substituted by Trimethylsiloxy group (-O-Si(CH3)3). The SiO2 surface become hydrophobic, water contact angle increased from 35.3° to 52.2°. After combining clean and HMDS processes, the water contact still increased from 52.2° to 59.1°. It means after clean process, some Si-H bondings oxidized by hydroperoxide into hydroxyl group (-OH), which will increase final Trimethylsiloxy monolayer (Si-O-Si(CH3)3) amount on SiO2 surface. After O2 plasma process, SiO2 surface was back to as growth condition by compatible water contact angle result.

Reviewing Table I data, 1:200 dilute HF etching rate dropped main root cause is the existence of Trimethylsiloxy monolayer (Si-O-Si(CH3)3). The densification of this monolayer might be not as good as from deposition process and results in gas type HF can easily penetrate to bottom oxide layer and no etching rate was impacted. Fortunately, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be removed by O2 plasma treatment.

To replace one of triple gate oxide growth under high temperature by thicker gate oxide wet etching back process. Post etched clean step and HMDS in following step will interfere with dilute HF etching behavior due to Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation. By adding additional O2 plasma treatment, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be easily and successfully removed and wet dilute HF SiO2 etching rate was back to normal. The thermal budget of triple gate oxide process can be successfully reduced by gate oxide wet etching back technique.

Figure 1