bluuebunny/crossref_metadata_2025 huggingface dataset:
Fatigue life analysis of Sn96.5Ag3.0Cu0.5 solder thermal interface material of a chip-heat sink assembly in microelectronic applications
Authors: Ekpu M. , Bhatti R. , Okereke M.I. , Otiaba K.C.
Published: October 2015

The reliability of microelectronic devices during operation has been a major challenge in recent years. Microelectronics devices will fail if one or more components do not function properly. Thermal interface materials are more likely to fail because of the role they play in heat management. Lead free solders such as SAC305 solder (Sn96.5Ag3.0Cu0.5) have become the thermal materials of interest because of their high thermal conductivity and government legislations on the ban of lead. Ansys finite element software was used for the design and analysis of the microelectronic device studied. The bond line thicknesses of the SAC305 solder thermal interface material were varied from 0.035 mm to 0.175 mm and a thermal load was applied using commercial thermal cycle profile of −40°C to 80°C. The results obtained showed that stresses and strains reduce as the lead free solder thickness increases. The number of cycles to failure and plastic work density increased as the SAC305 solder thickness is increased. This research showed that an increase in SAC305 solder thickness will improve thermal conduction and reliability. However, the solder thickness is limited to the gap between the chip-heat sink surfaces in contact.
Thermally and Electrically Enhanced Wirebond BGA
Authors: Carpenter Burton , Low Boon Yew , Higgins Leo M. , Neelakantan Sriram , Wenzel Robert , Boyne Daniel
Published: October 2015

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800).

An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance.

Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement.

This paper will present the package design, thermal and electrical simulation and measurement results.
Effects of Copper Pattern Density and Orientation on the Modulus of BGA Substrates
Authors: Carpenter Burton , Yeung Betty , Yuan Yuan
Published: October 2015

Substrate material properties directly impact package mechanical performance. Estimation of substrate mechanical properties based on each component layer provides maximum flexibility and better accuracy. The component materials of a BGA substrate are the fiberglass-reinforced epoxy layers, copper and soldermask. Even when the material properties (modulus and CTE) of each component are known, the behavior of the final substrate is not easily determined because factors such as copper density and pattern have significant effects. For example, the copper pattern may be oriented such that conductor traces run in one direction for a considerable length. The modulus in the direction parallel to the traces will be different from the modulus in the direction perpendicular to the traces. Package mechanical simulations typically do not mesh the details of the copper patterns, but rather average within each layer, thus neglecting the orientation effects. Therefore FEM (Finite Element Model) simulations may yield inaccurate stress and warpage results.

This study utilized a test vehicle (TV) to study the copper pattern density and orientation effect on substrate modulus. Each TV sample was a two-metal-layer copper-clad laminate designed with one of eight simple geometric patterns. One set of patterns had Cu traces running parallel in one direction, with varied metal densities of 0%, 25%, 50%, 75% and 100% respectively. Measurements were made both parallel and perpendicular to the trace orientation. Also studied were a pattern of holes (continuous metal plane with unconnected holes) and a dot pattern (unconnected circular metal pads).

Substrate flexural modulus measurements were made using two types of instruments: DMA and Instron. Data was collected from −65 to 260°C. FEM simulations which meshed the details of copper patterns were used to calculate the overall substrate modulus. These correlated better with the empirical data than simulations utilizing traditional layer averaging.

The copper pattern had significant effects; the substrate modulus was always much lower in the direction perpendicular to the traces than the modulus in the direction parallel to the traces. The amount varied depending on temperature, but could be as high as 35%. When measured parallel to the copper traces, the substrate modulus was observed to increase with copper pattern density as predicted by theoretical mixture rules. However, the substrate modulus in the direction perpendicular to the traces was not easily predicted theoretically. Therefore, more sophisticated averaging techniques and simulations are needed.
Method to Measure Effects of Surface Roughness on High-frequency Transmission Lines
Authors: Iwai Toshiki , Mizutani Daisuke , Tani Motoaki
Published: October 2015

In recent years, the transmission losses induced by surface roughness of conductors in printed circuit boards (PCB) have become important from the standpoint of signal integrity. To clarify this effect, current measurement methods use a microstrip line or a strip line in the PCB, which is fabricated for different values of surface roughness. However, since errors are induced in each sample because of the presence of dispersion in the manufacturing process, it is difficult to extract the effect of surface roughness from the measured data. In this paper, we propose a novel method to measure the effect by means of using capacitive coupling in which the dispersion errors can be eliminated. The results have been verified using electromagnetic simulation. This method was performed on three samples having differing values of surface roughness. It was concluded that the transmission characteristics are influenced by surface roughness at higher frequencies when the skin depth becomes comparable to the surface roughness.
RF Capacitor Material for Use in Printed Circuit Board
Authors: Hwang Jin-Hyun , Andresakis John , Feinberg Ethan , Carter Bob , Kageyama Yuji , Kuwako Fujio
Published: October 2015

A novel ceramic-functional-particle-filled polymer composite material has been developed for the use either in discrete elements on the printed circuit board or in being embedded within the packaging substrate for high frequency circuit applications. This material provides the desired properties such as low loss at high frequencies, about 0.002 or less up to 10GHz, and high dielectric strength, among other improved properties. The electrical properties were influenced significantly by the ceramic-functional-particle, i.e. type and particle size/distribution in the polymer matrix. Their contributions to the electric strength and temperature stability of capacitance which is an important material issue for practical device application will be discussed. In addition, capacitance tolerance for manufacturing embedded RF capacitor will be presented in terms of etching uniformity to minimize the variation of the capacitor electrode areas.
DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION
Authors: Parès G. , Attard A. , Dosseul F. , N'Hari A. , Boillon O. , Toffanin L. , Klug G. , Simon G.
Published: October 2015

3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market.

Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by, in one hand, the increase of the die surface and the number of I/Os and, on the other hand, the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 μm ultra-thin dies with low stand-off (< 15 μm) copper micro-bumps and tin-silver-copper solders (SAC).

Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips.

Copper μbump technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield.

Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stack configurations as well as new processes using damascene techniques.

Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes.

Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds.

Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique.

After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers.

Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between −40 and +125°C.
Long-term Electromigration Study of Lead-Free Flip-Chips with Solder Bumps with 50 μm or 60 μm Diameter Employing ENIG Surface Finish on Both Chip and Substrate Side
Authors: Gorywoda Marek , Dohle Rainer , Härter Stefan , Wirth Andreas , Goßler Jörg , Franke Jörg
Published: October 2015

Electromigration behaviour of Pb-free solder joints in flip-chip interconnects is usually studied in highly accelerated, short-term experiments using high current density and temperature. Failures typically occur in bumps which are in cathode contact at the chip side. There are only a few published studies in which Electroless Ni-P/Immersion Au (ENIG) surface finish was used as under-bump-metallization (UBM) structure, e.g. [5].

This paper deals with the long-term electromigration behaviour of Pb-free SAC305 flip-chip solder joints with a pitch of 100 μm and solder bump diameters of 50 μm or 60 μm, respectively. The ENIG surface finish was used on both the substrate and chip side. Test specimens were subjected to several levels of temperature and current density and tested up to 16,000 hours. The life time data is summarized using Weibull and lognormal distribution.

The microstructure changes of interconnects in failed samples were subsequently investigated by SEM and EDX. Interconnects had failed due to consumption of Nickel, voids caused by electromigration, and Kirkendall void formation in the Ni-P-layer. The damage was asymmetric in respect to the current flow direction through the solder bumps and was most pronounced at the cathode side. Unexpectedly, however, the most severe damage occurred at the substrate and not at the chip side. We could show that - allowing for a few guidelines - lead-free flip-chip solder joints with 50 μm or 60 μm diameter have a sufficient electromigration life time for most applications.
3D Integration of System-in-Package (SiP) Using Organic Interposer: Toward SiP-Interposer-SiP for High-End Electronics
Authors: Das Rabindra N. , Egitto Frank D. , Rosser Steven G. , Kopp Erich , Bonitz Barry , Rai Raj
Published: October 2015

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and embedded passives provides a high wireability package with excellent communication from top to bottom. In the present study, we also report a novel 3D “Package-Interposer-Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions incorporating various SiP configurations.
Improving WLCSP Reliability Through Solder Joint Geometry Optimization
Authors: Rogers Boyd , Scanlan Chris
Published: October 2015

The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die, an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.
Multi Beam Low-κ Grooving Evaluation of various removal principals
Authors: van der Stam Richard , van Borkulo Jeroen , Dijkstra Peter
Published: October 2015

Over the years the singulation of semiconductor wafers with a low-κ top structures has become a challenge in the production process of integrated circuits. With the traditional blade dicing process serious yield issues are encountered. These problems can be addressed by applying a laser grooving process before the blade dicing. However, these processes are slow or generate a significant heat impact on the wafer. In this article the special ALSI multi beam technology is presented which makes a high productivity grooving process possible with a very limited heat affected zone.
Z-Axis Interconnection: A Versatile Technology Solution for High Performance Electronics
Authors: Das Rabindra N. , Lauffer John M. , Egitto Frank D.
Published: October 2015

This paper presents a novel Z-axis interconnect approach for extending performance beyond the limits imposed by traditional approaches. Specifically, metal-to-metal z-axis electrical interconnection among substrates (subcomposites) of the same or varying size, or among flexible and rigid elements (rigid-flex), to form a single structure is described. The structure employs an electrically conductive medium to interconnect thin coreless substrates. The substrates are built in parallel, aligned, and laminated to form a variety of multilayer high density structures including rigid, rigid-rigid, rigid-flex, stacked packages, or RF substrates. The z-interconnect based structures offer many advantages over more conventional build-up technologies. For example, it enables designs having increased wiring density, leading to greatly reduced layer counts. When an increase in metal layer counts is required, z-interconnect avoids the cumulative yield loss of sequential (build up) processing. The parallel processing of cores and/or subcomposites leads to reduced fabrication cycle time. Avoidance of through hole drilling allows for reduction or elimination of via stubs that cause signal attenuation at high frequencies. In addition, multilayer rigid-flex packages for a variety of applications are being developed. For these applications, z-interconnect allows for placement of flex elements into any layer of the substrate, the opportunity for multiple flex layers within a rigid-flex substrate, the ability to connect multiple multilayer substrates of varying size, and the ability to connect between any two arbitrary metal layers within the rigid region without the use of plated through holes (PTHs). The process allows fabrication of z-interconnect conductive joints having diameters in the range of 55–500 microns. Via or component pitches down to 150 microns have been demonstrated. A number of RF structures have been designed and built with z-interconnect technology, affording the flexibility to place wide signals, narrow signals and grounds and clearances only where needed. Electrically, S-parameter measurements revealed low loss at multi-gigahertz frequencies and the insertion loss for narrow, short lines and wide, long lines are similar. The electrically conductive adhesive used to form z-interconnects shows good signal transmission to 25GHz. Z-interconnect technology provides unique solutions for next generation complex packaging products.
The Next Level of Accurate Server Power Monitoring and Capping
Authors: Steele Jerry
Published: October 2015

Accurate server power monitoring is essential in extracting the maximum financial benefit of server performance in the capped environment. Capping power errors leave money on the table.

A fully integrated solution has been developed double the measurement accuracy of server power monitoring. Some little known error sources will be discussed along with the methods for increasing measurement accuracy.

Furthermore, advanced data processing such as true running averaging along with a variety of settings for energy metering provide important parts of the processing for advanced power capping strategies.

Obtaining continuous, rapid power data is only handicapped by the popular I2C or PMBus used for these devices. Described is an alternate data path connection that bypasses normal bus limitations.
Advanced Thermal Simulation Model for Power MOSFETs
Authors: Ejury Jens
Published: October 2015

Modern Power MOSFETs are widely used for high efficiency SMPS applications. Also, they provide very low on-resistance which reduces conduction losses in Oring or eFuse applications. These applications as well as others have transition states in which they drive the MOSFET in linear mode operation during turn-on and turn-off events respectively. The high cell density in modern Power MOSFETs provokes uneven current distribution in linear mode operation which locally stresses certain cell areas more than others. To prevent destruction, the SOA of these MOSFETs has a thermal limit line boundary imposed. With existing L3 MOSFET models it is possible to simulate temperature rise and power loss of the entire MOSFET. However, the local heating effect is not represented in this model. Here, a wrapper is being introduced. It converts a standard L3-model into a model that incorporates a dynamic representation of the entire SOA diagram. The temperature rise follows the hottest cell so that simulations in linear mode become a valid way to predict the highest junction temperature. The limitations of this approach will be outlined.
A Highly Integrated GaAs-based Module for DC-DC Regulators
Authors: Miller Greg J.
Published: October 2015

There is a need and desire to push low voltage point-of-load voltage regulators (POL VRs) to higher switching frequencies. The main reason for this is to increase power density. Silicon MOSFET-based solutions are rapidly approaching their technology limits and are not capable of providing multi-MHz switching frequency for high current (>10A) applications. Gallium Arsenide (GaAs) field effect transistors (FETs) can switch much faster, enabling cost-effective, high-current, high switching frequency POL VRs. Recent advances in GaAs technologies have enabled the demonstration of 5MHz VRs and provide a path to even higher frequency (>50MHz) Power Supply in Package (PSiP) solutions.

The high-speed GaAs power FETs are the “engine” to enable efficient high switching frequency POL VRs, but certain key elements must be designed appropriately to realize the desired performance. The gate driver and power path impedances must be minimized. To do this, a high level of integration is required, thus packaging is a critical element. New embedded die packaging solutions enable this high level of integration, dramatically reducing key parasitic impedances that can otherwise throttle performance, while also facilitating very compact multi-chip modules.
Challenges of Adhesion Promotion for the Metallization of Glass Interposers
Authors: Bamberg Simon , Merschy Michael , Bernhard Tobias , Bruening Frank , Taylor Robin , Brandt Lutz , Liu Zhiming , Fu Hailuo , Hunegnaw Sara
Published: October 2015

Ultra-miniaturization and 3D integration of electronic systems require interposers with a very high density of off-chip interconnections. Silicon and glass interposers are being developed widely to meet these needs.

Through hole via formation or Through Package Via (TPV) in combination with the ability to handle of thin glass materials have already been demonstrated in combination with “polymer on glass” technologies at Georgia Tech Packaging Research Center and by industrial partners.

However there is an increasing industry demand to plate electroless copper directly onto smooth glass substrates which is extremely challenging.

This is being driven by the desire to be able to benefit from the ability to utilize existing infrastructure and therefore fully benefit from the cost advantages wet-chemical metallization can offer in the manufacturing of glass interposers.

It is therefore worthwhile to investigate replacing adhesion promoting techniques such as sputtered metal seed layers or laminated polymer films with a pure wet chemistry alternative.

In this study a modified sol gel processes were developed for the formation of metal oxide layers on the glass substrate. The impact of the sol composition on the resulting oxide's surface structure was examined.

Centrifugal adhesion measurement allowed quantification of the mechanical anchoring provided by metal oxide layers prepared from different sol gel compositions.

With regards to the interposer manufacturing process, the two possibilities of applying the sol gel coating prior to as well as after TPV formation are compared and their respective advantages are discussed.
A fully automated execution of complex DOE to characterize electroplating baths
Authors: Schroeder Norbert , Richter Fred , Stahl Juerg , Cziurlok Arnold
Published: October 2015

A new tool has been invented that enables a fast and efficient execution of design of experiments (DOE) for the characterization of electroplating chemistries. This new procedure uses a commercially available analysis system (tool). It is fully automated and systematically handles up to four different additives in conjunction with basic electrolytes to evaluate the impact of these on the electrochemical behavior of the plating bath.
Plating reliability and high frequency testing of DuPont™ GreenTape™ 9K7 LTCC
Authors: Beikmohamadi Allan , Graddy Patricia , Nair Deepukumar , Parisi Jim , Stewart Steve
Published: October 2015

Low Temperature Co-fired Ceramic (LTCC) with low dielectric loss is suitable for use on microwave and millimeter wave circuits. Thick film gold or silver conductors are used as metallization on LTCC substrates. Gold prices are increasing at a rapid rate, so efforts were made to lower the dependency on gold by substituting silver with Ni/Au surface finishes as the top conductor. The external thick film silver conductors were plated using a standard Electroless Nickel Immersion Gold (ENIG) process. The Ni/Au surface finishes provides substantial improvement to fretting corrosion, environmental protection, contact resistance, wire bond strengths, solder ability and solder joint reliability. The reliability testing of DuPont™ GreenTape™ 9K7 LTCC with Ni/Au surface finishes is being conducted. The reliability test methods & conditions were chosen from well-established industry standard test protocols. This paper reports the reliability and high frequency testing results on the ENIG plated GreenTape™ 9K7 LTCC system.
Low-Temperature Co-fired Ceramic (LTCC) Technology for Development of Sensors for Emerging Applications
Authors: Birol H. , Lopera S. , Farine G. , Maeder T. , Quintão W.B. , Gervasio J. , Gyoervary E. , Cesar L.O.S. , Buntaine J. , Ryser P.
Published: October 2015

LTCC technology continues to be an attractive option for fabrication of sensors, sensor packages and complex micro-systems. The objective of this work is to present LTCC sensors developed by CSEM Brasil with a focus on capacitive type wireless soil moisture sensor (SMS) for precision farming that is capable to measure soil moisture in real time and transmit the data to 80 m distance (line of sight). The sensor is constructed from 4 functional blocks: PCB (printed circuit board) base including the capacitive electrodes, LTCC block carrying the electronics and soldered on PCB, voltage regulator and wireless unit. Tests conducted with 28 prototypes reveal that the sensor response is over 1.00 V at full humidity and reproducible whilst the battery consumption is around 200 mW, permitting a battery life of 5 years at a measurement frequency of 1 sampling per minute.
Void formation and bond strength investigated for wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding
Authors: Vardøy Astrid-Sofie B. , van de Wiel H.J. , Martinsen Stian , Hayes Greg R. , Fischer Hartmut R. , Aasmundtveit Knut E. , Lapadatu Adriana , Taklo Maaike M. V.
Published: October 2015

A hermetic wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding was investigated to explore the sensitivity of selected process parameters with regard to voiding and possible reduction of strength. Little or no variation was observed in the void density as a result of modifying the plated Sn-thickness, the storage time between plating and bonding, the bonding tool pressure, or the thermal budget during bonding. All shear tested samples showed excellent shear strength, with an average of 110 - 164 MPa. Some statistically significant differences in shear strength were found between the varied process parameters. However, the differences were too small to be critical for the application. Analysis of fracture surfaces showed that shear strengths in the lower range corresponded to fracture between the adhesion layer (TiW) and the silicon cap, while shear strengths in the higher range corresponded to fracture in the Cu3Sn formed during the bonding. The results indicate that the bonding process is robust with regard to the studied process parameters.
Modular Microsystems with Embedded Components
Authors: Boehme Christian , Ostmann Andreas , Schneider-Ramelow Martin
Published: October 2015

Each system is designed to fulfill the desired purpose. It is defined by its inputs, outputs, structure, environment, boundary, and the including elements (subsystems). Due to the ongoing miniaturization and integration the complexity of subsystems increases continuously. This paper is intended to demonstrate the build-up of modular Microsystems. By using the embedding technology, each subsystem (module) is interchangeable and stackable. Therefore, the functionality of the entire system depends solely on the selected modules. Moreover, the enhancement, expansion or redesign can be accomplished by replacing existing or adding new modules. The communication between the individual modules is based on the standardized I2C bus. Additionally, a USB interface has been implemented to manage the data transmission between the embedded camera module and a computer. The whole system recognizes each module and performs accordingly. The user can access sensor values, watch the video stream, and change the parameters of each module via a Graphical User Interface (GUI) on his computer. To achieve the build-up of the modular Microsystems we only used packaged active and passive components. Depending on the complexity of each module a core of up to eight layers is build up. The components are then soldered onto both sides of the core. At this point the components are embedded using a laminating press. The afterwards even surface is then structured again, to enable the stacking of the modules. Each step of the entire assembly process is done via state of the art circuit board processing technologies, including laser drill and laser-direct imaging.
Size Matters – Embedding as an Enabler of Next-Generation SiPs
Authors: Renaud-Bezot Nick
Published: October 2015

Embedding is a relatively new packaging technology involving the use of (for example) laminates to encapsulate the active and/or passive component, as well as PCB and/or SMT processes for electrical connections. The embedded system can be used in that condition, or further processed to create a System-in-Package (or System-in-Board in case of larger assemblies). In that last case, the SiP (respectively SiB) is treated like any other substrate (respectively PCB).

In the search for higher integration, embedding is gaining traction as an alternative 3D-packaging solution, due to its multiple advantages: high integration, large production format, intrinsic matching to PCB in terms of pitch and CTE characteristics, mechanical stability and possibility to adapt substrate properties based on specific requirements (Dk, thermal conductivity…). The various players in the field are raking in new design-ins, and production volumes are rapidly increasing.

Those characteristics mean that embedded packages are directly competing with several other packaging architectures routinely used in smartphone applications:- Almost as small as WL-CSPs while being more robust and offering better thermal behavior,- Smaller than QFNs with similar thermal properties,- Thinner than PoPs while allowing easier 3D integration,- SiP architecture to decrease PCB-level cost-of-ownership.

Smartphone manufacturers are constantly demanding increased reliability and performance, while requesting from packages to enable higher functionalities in smaller form factors. This document compares multiple architectures meeting the tight height requirements from the smartphone industry, and proves that embedding is a valid enabler in the quest for higher integration. It also shows the latest developments in terms
Source-Sense Packages for HV MOSFETs
Authors: Lind Anders
Published: October 2015

In traditional 3-pin High-Voltage (HV) power MOSFET (MOSFET) packages, the hard-switching transition speed is limited by the package source-inductance because the MOSFET drain current and gate current both share a path through the same package source inductance. The details of this mechanism are discussed and the resulting additional switching power loss caused by it is both measured and simulated.

Proposed innovative “Source-Sense” packages split the two currents into separate paths by adding separate source-pin for Kelvin-type driver connection to gate-source on the chip, thus completely eliminating all switching loss incurred by the source inductance for improved efficiency and lower die temperature.

Leadless SMD packages employing this method are explored for further addressing complications caused by package source inductance, such as common-mode noise and requirement for filtering.

Advanced package concepts are discussed for future optimization and thermal management, and versatility of these advanced concepts as well as existing leadless SMD packages with “Source-Sense” is examined.
Managing Voids in Adhesives for Medical Devices
Authors: Ruales M. , Merced J. , Ramos R.
Published: October 2015

Void content within the adhesive layer dispensed over the connector module in neuromodulation devices is critical. Voids can affect the thermal transfer, bond strength, and stress decoupling of the adhesive, which can eventually lead to degraded device reliability. The effects of voids are investigated for a silicone based adhesive used in these medical devices. There are many challenges associated with the curing process that this adhesive undergoes which drive the need for unique and specific testing to determine optimal process settings. The parameters evaluated included curing time, temperature, thickness, and relative humidity. Reduction in void content was linked with mechanical properties including hardness and tensile strength. Achievement of void free medical adhesives will encourage today's microelectronic packaging industry to meet the challenges of smaller and denser medical devices.
Automatic Segmentation Method for Segmenting PBGA Package and PWB Regions during Warpage Measurement of Unpainted PWB Assembly
Authors: Kang Sungbum , Ume I. Charles
Published: October 2015

Among the various warpage measurement techniques, the digital fringe projection (DFP) technique is recent trend because of its noncontact, full-field, and high-resolution measurement capabilities for measuring the warpage of chip packages, printed wiring boards (PWBs), and PWB assemblies (PWBAs). When using the DFP technique, reflective painting is generally sprayed on a sample surface to ensure uniform surface reflectance and to obtain better image contrast for the measurement process. However, because painted samples may no longer be re-used, and the spray-painting process is not suitable inline, warpage measurement of unpainted chip packages, PWBs, and PWBAs using the DFP technique is required. One of the important tasks for measuring unpainted PWBAs is segmentation of the chip package and PWB regions in unpainted PWBA images so that separate warpage of the chip package(s) and the PWB can be determined. In this paper, an automatic image segmentation method that is used to segment plastic ball grid array (PBGA) package and PWB regions in unpainted PWBA images is presented. Because the patterns such as the copper patterns and traces, and inscriptions on a PWBA can cause measurement errors, the patterns and inscriptions are automatically masked out during the segmentation. The method is experimentally tested by segmenting the PBGA package and PWB regions in three different PWBA samples and measuring the warpage of the PBGA packages and the PWB in an unpainted PWBA.
The Characteristics of Cu/Sn/Cu and Ni/Sn/Ni Sandwich Solder Systems for Gold-free Wafer Bonding Technology
Authors: Chu Kunmo , Lee Sunghee , Moon Changyoul
Published: October 2015

Two sandwich-structured solder systems (Cu/Sn/Cu, Ni/Sn/Ni) are suggested for gold-free wafer bonding with a thermally stable joint. The influence of the thickness ratio of the metal layers on the microstructure and mechanical bonding strength of the solder joints was investigated by varying the thicknesses of the Cu or Ni side-layer.During the bonding process, the side-layer metal (Cu or Ni) reacts so rapidly with Sn that it is completely transformed into high melting point IMCs (Cu/Sn/Cu: Cu6Sn5, Cu3Sn or Ni/Sn/Ni: Ni3Sn4, Ni3Sn). Although the microstructures of sandwich joint samples are very similar to each other, the bond strength of the Cu-Sn samples is notably higher than that of Ni-Sn samples. It is inferred that both the irregular morphology and brittleness of the Ni-Sn IMCs could strongly affect the strength of Ni-Sn sample, resulting in a reduced bond strength compared to Cu-Sn.
Impact of Bath Stability on Electroplated Cu for Through-Silicon-Vias (TSV) in a Controlled Manufacturing Environment
Authors: Nguyen Anh , Fealey Kevin , Reilly Peter , Pattanaik Gyanaranjan , Gracias Alison , Wafula Fred , Flynn Michael , Enloe Jack
Published: October 2015

This study addresses the impact of bath stability on electroplated copper for through silicon via (TSV) in a controlled manufacturing environment. Microstructure, impurities and other properties of the copper produced were characterized using an array of techniques, including Electron Backscatter Diffraction Analysis (EBSD), Focused Ion Beam – Secondary Electron Microscope (FIB-SEM) and Time of Flight - Secondary Ion Mass Spectrometry (ToF-SIMS). Chemical analyses of the plating baths throughout their lives indicates that the process can be controlled. Overall, a manufacturing process was demonstrated that can create high quality TSV Cu fill interconnects for 3D IC over the life of the bath. The process has enabled further development work at State University of New York Polytechnic Institute (SUNY Poly) for downstream processes such as chemical mechanical planarization (CMP) and Cu-Cu bonding.
Compressive-Post Packaging of Double-Sided Die
Authors: Kim Woochan , Wu Jia-Woei , Alexander Bill , Chowdhury Sauvik , Hitchcock Collin , Lee Nga C. , Lu James J. Q. , Chow T. Paul , Ngo Khai D. T.
Published: October 2015

Double-sided module exhibits electrical and thermal characteristics that are superior to wire-bonded counterpart. Such structure, however, induces more than twice the thermo-mechanical stress in a single-layer structure. Compressive posts have been developed and integrated into the double-sided module to reduce the stress to a level acceptable by silicon dice. For a 14 mm x 21 mm module carrying 6.6 mm x 6.6 mm die, finite-element simulation suggested an optimal design having four posts located 1 mm from the die; the z-direction stress at the chip was reduced from 17 MPa to 0.6 MPa.
Analysis of crack length and crack position in the Solder Joints of High Power LEDs by Transient Thermal Measurements and Finite Element Simulations
Authors: Kandaswamy Shri Vishnu , Tetzlaff Ulrich , Derix Robert , Elger Gordon
Published: October 2015

In SMT devices, the CTE mismatch between the substrate and the component makes the solder joint region the most susceptible to crack. Due to temperature cycles experienced by the device during field life, the solder region often cracks leading to system failure. For high power devices that have to dissipate large thermal load through the solder joint, it was shown in earlier publication that transient thermal analysis is very sensitive to determine the solder joint reliability. For Transient Thermal Analysis the forward voltage (Vf) of the device is measured after switching the thermal load. By normalizing the transient Vf plots, an algorithm was introduced which eliminate the influence of k factor (a linear factor between Vf and T) and thermal load (Pth) for calculating the relative thermal resistance [1].

In this paper experimental studies are presented were the reliability of the solder joint of high power ceramic LED packages is investigated. The LEDs are soldered with two different lead free solders (SnAgCu 305 and Innolot FL-640) on Aluminum Insulated Metal Substrate (Al-IMS). Test batches were prepared and exposed to temperature cycles at −40°C / +125°C. Transient thermal measurements were performed directly after assembly and after specific cycle numbers. It is seen that as the temperature cycle number increases, the thermal signal corresponding to the solder region changes. After appropriate data processing the increase of the relative thermal resistance between the initial signal at ‘0’ cycles and ‘n’ cycles is calculated. Based on the increase of the relative thermal resistance a failure criterion is introduced and the cumulative failure probability is calculated. We observed a higher creep resistance for the test group soldered with Innolot FL-640 compared to the test group soldered with SAC 305.

Transient finite element analysis (FEA) is applied to simulate the experimental curves. The influence of crack length and crack position in the solder joint region of a high power ceramic LED used for automotive applications is analyzed and it is shown that the crack length and position has a significant impact on the relative increase in thermal resistance. Within the simulations the crack length and crack position is varied to match the peak-height difference and peak shift of the experimental curves by simulation. It is observed that the increase of relative thermal resistance strongly depends on the position of the crack. Therefore it is shown that the relative thermal resistance increase takes place not only within the solder joint but also within the dielectric layer of the Al-IMS. It is show that as the crack propagates from the exterior to the interior region of the solder joint, the effective area available for heat flow through the Al-IMS is significantly reduced and adds onto the increase of the thermal resistance within the solder joint.
Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package
Authors: Yamada Tomoyuki , Fukui Masahiro , Terada Kenji , Harazono Masaaki , Fujisaki Teruya , Iruvanti Sushumna , Carey Charles , Pan Yi , Reynolds Charlie , Sikka Kamal , Sundlof Brian , Toy Hilton , Wagner Rebecca
Published: October 2015

In organic packages, large die and large laminate body sizes are susceptible to CTE (coefficient of thermal expansion) mismatch driven warpage, stresses and strains, which can result in C4 white bumps, micro Ball Grid Array (BGA) interconnection issues, and package thermal reliability concerns. Low CTE carriers minimize these concerns and allow increased chip join yields and improved package reliability. Modeling and characterization of warpage, chip and micro BGA integrity and electrical characterization of a low CTE, Chip Scale Package (CSP) were described in an earlier paper.

In this paper we report the progress on the next phase - thermal and chip package interaction (CPI) evaluation of a single chip CSP designed for use with Multi-Chip Modules (MCM). Assembly, characterization, thermal performance and reliability stress results of these low CTE CSP Single Chip Modules (SCMs) are described. Measured warpage values are compared with thermo-mechanical modeling results. Demonstration of a dual CSP design and assembly with large dies is also presented.

The successful demonstration of the material set, bond and assembly processes, and reliability of a large die, high I/O CSP, followed by the demonstration of a dual CSP on a multi component carrier, are fore-runners to the development of multi-CSP MCMs.
Large Laminate and Die Coreless Substrate Packaging with Lid Ties
Authors: Blackshear Edmund , Quinlan Brian W , Fasano Benjamin , Lewison David J , Li Shidong , Gagnon Hugues C , Fortier Paul , Heath Richard , Roy Frederick , Nakajima Elaine Cyr Takashi , Miyazawa Yoichi , Shishido Itsuroh , Yamada Tomoyuki
Published: October 2015

Coreless flip chip laminate substrates have shown significant advantages over cored versions in terms of wireability due to the absence of large coarse pitch core vias and accompanying via lands. Resistance to widespread acceptance of coreless has been associated primarily with package manufacturability. Increased warpage tendencies for coreless both at room temperature and thermally have driven packaging techniques such as the use of stiffeners prior to chip join increasing packaging costs. A new low Coefficient of Thermal expansion (CTE) laminate dielectric material is being introduced for coreless substrates. A novel method for packaging using lid ties has been developed to enable this new substrate technology. Lid ties are dots of encapsulation material deposited in an array on the coreless laminate substrate outside the chip area prior to capping. Lid ties have been shown to enable excellent results for manufacturability, quality, and reliability of large die large laminate coreless semiconductor packages. use of lid ties has been introduced at acceptable costs. Assembly and reliability results will be shown. Design parameters related to lid tie patterns impacting reliability will be discussed. Affects of lid ties and lid tie design on test and burn in performance will be reviewed.
PoP Technology for the Automotive Industry
Authors: Williamson Jaimal , Wachtler Kurt , Chin David , Pierce Mike
Published: October 2015

Package-on-Package (PoP) technology has been in production for commercial and portable electronic applications for many years. The key challenge for PoP in automotive applications is meeting the aggressive defect level requirements. The need for PoP has historically been driven by mobile and tablet applications and an increased demand for more processor and memory performance within smaller spaces. With the maturity and excellent historical performance of PoP technology used with TI OMAPTM processor products, PoP can now be introduced as a reliable packaging technology in the automotive industry. This paper will describe the work involved in the enablement of commercial PoP technology into the automotive industry. The challenges and requirements regarding package design, warpage performance, surface mount (SMT) characterization, and board-level reliability (BLR) performance will all be explained.
Correlation between Thermo-mechanical Reliability and Superhydrophobic Nature of CNT Composite Coatings
Authors: Sohn Yoonchul , Kim Dongouk , Lee Sangeui , Song Jae Yong , Park Sunghoon , Kim Hajin , Ko Youngchul , Chu Kunmo , Han Intaek
Published: October 2015

One of the most important applications for superhydrophobic coatings is anti-frosting for safety and energy conservation. Safety concerns are especially critical in cold-climate regions where the daily temperature fluctuation is large. However, superhydrophobic coatings have not been studied in terms of their thermomechanical reliability. In this study, wetting characteristics and stress relaxation behavior were quantitatively investigated with multi-walled carbon nanotube (MWNT)–silicone composite films under thermal cycling condition. It is concluded that an open structure with numerous nanopores among the fillers, constituting air pockets described as the “Cassie structure,” is of great importance not only for developing a film's superhydrophobic nature but also for accommodation of thermal stress that evolved from different coefficients of thermal expansion between the coating and the substrate. The amount of stress relaxation for a 30 vol% MWNT–silicone composite film with open structure reaches ~80% of the value for its counterpart with a closed structure and no pores. A superhydrophobic MWNT–silicone composite film that can endure over 4000 thermal cycles (−30°C to room temperature) is fabricated by controlling the composition and microstructure of the composite. In addition, the importance of size and shape of nanofillers in delaying nucleation and growth of frost on superhydrophobic coatings is also discussed.