bluuebunny/crossref_metadata_2025 huggingface dataset:
Molecular Basis of NF-κB Signaling
Authors: Napetschnig Johanna , Wu Hao
Published: March 2013

NF-κB (nuclear factor kappa B) family transcription factors are master regulators of immune and inflammatory processes in response to both injury and infection. In the latent state, NF-κBs are sequestered in the cytosol by their inhibitor IκB (inhibitor of NF-κB) proteins. Upon stimulations of innate immune receptors such as Toll-like receptors and cytokine receptors such as those in the TNF (tumor necrosis factor) receptor superfamily, a series of membrane proximal events lead to the activation of the IKK (IκB kinase). Phosphorylation of IκBs results in their proteasomal degradation and the release of NF-κB for nuclear translocation and activation of gene transcription. Here, we review the plethora of structural studies in these NF-κB activation pathways, including the TRAF (TNF receptor–associated factor) proteins, IKK, NF-κB, ubiquitin ligases, and deubiquitinating enzymes. Although these structures only provide snapshots of isolated processes, an emerging picture is that these signaling cascades coalesce into large oligomeric signaling complexes, or signalosomes, for signal propagation.
(Invited) Innovative Wide Band Gap Power Devices Achievements in ITRI
Authors: Lee Chwan Ying , Chen Yung-Hsiang , Lee Lurng-Shehng , Hung Chien-Chung , Yen Cheng-Tyng , Lin Suh-Fang , Xuan Rong , Kuo Wei-Hung , Tsai Ming-Jinn
Published: March 2013

Wide band gap semiconductors, such as silicon carbide (SiC) and Gallium nitride (GaN), provide higher breakdown voltage, higher operation temperature, higher thermal conductivity and higher switching frequency than conventional silicon device, thus there are many research institutes and companies focus on wide band gap device development and explore the benefits of using those devices in power electronics application. In ITRI, there is a program to develop wide band gap device and we have established a wide band gap Power Electronics Consortium (WPEC) to link companies who is interested on this device and application and eventually form a supply chain in Taiwan. ITRI has achieved very good results on the wide band gap device design and process development, such as high uniformity and productivity of SiC SBD device with breakdown voltage > 1200V and current rating > 20A, two mask-level process of TMBS (trench MOS barrier schottky) device with breakdown voltage > 600V, SiC MOSFET with low interfacial defect density and breakdown voltage >1200V, and innovative normally-off GaN MIS-HEMT device with threshold voltage >2V.
PNP Transistor Design and Simulation in SiGe BiCMOS with Low Cost and High Performance
Authors: Liu Donghua , Shi Jing , Hu Jun , Duan Wenting , Ci Pengliang , Pan Jia , Chen Fan , Chen Xiongbin , Huang Jingfeng , Qian Wensheng , Xu Xiangming , Xiao Sheng'an , Chu Tungyuan
Published: March 2013

The study and design of a low cost and high performance vertical PNP transistor at BiCMOS process platform is presented. The effect of different device designs on baseline process has been compared in terms of their electrics characteristics simulation result. The performance of PNP has been improved further through process optimization with the aid of process simulation. The fabricated PNP transistor silicon data shows consistent performance with simulation. Finally the performance of PNP device has met the target including current gain above 38, breakdown voltage (BV
CEO) over 7 volts and cut-off frequency (f
T) 10GHz. Its performance addresses the requirement for high speed circuit design.
A Comprehensive Study of SiGe Source/ Drain Local Stress by Nano Beam Diffraction
Authors: Jin Lan , Tu Huojin , He Youfeng , He Yonggen , Wu Jingang
Published: March 2013

Compressive stress introduced by source/drain (S/D) SiGe is widely used in 45nm node and beyond advanced technology which boost the P-channel hole mobility. Quantitive measurement of localized stress in channel is limited by the scaling shrinking. Transmitted electron microscopy- Nano Beam Diffraction (TEM-NBD) is an effective method for the local stress distribution measurement in channel and well area derived from S/D Si1-xGex. In this paper, we study the channel strain from the following aspect, including i) active area (AA) width, ii) S/D recess shape, iii) S/D recess trench depth, and iv) Germanium (Ge), Boron (B) concentration of S/D Si1-xGex and Ge, B distribution profile. It is revealed that strain has strong relation with these factors. Pitch with narrow AA width shows lower strain than that of wider AA width. S/D recess shape affects the proximity which is critical for the stress derived from S/D SiGe transmit to channel location. Moreover, S/D recess trench depth determines the volume of filled SiGe then affect the strain to channel. Both of the Ge, B concentration of S/D SiGe and the distribution profile directly affects the lattice mismatch which results in the strain. In general, all these factors affect the volume of the filled SiGe and Ge concentration which eventually determine the strain of S/D to channel area.
A Novel Programming Method for Multilevel RRAM Based on Pulse Width Modulation
Authors: Chen Cheng , Cai Yimao , Yin Shihui , Huang Ru
Published: March 2013

A novel programming method for multilevel resistive random access memory (RRAM) is proposed and experimentally demonstrated to improve the stability of multilevel high resistance states (HRS). By substituting a relatively long reset pulse with a series of short pulses, this method effectively reduces the resistance variation resulted from Joule heating. The standard deviation of one HRS is greatly reduced. Though this method is demonstrated on our TiN/TaOX/Pt devices, further analysis indicates its possible validity in bipolar RRAM devices based on other transition metal oxides. Stable multilevel RRAM for applications in memory chips can be achieved through this method.
Optimization of HfO2 Growth Process by Atomic Layer Deposition (ALD) for High Performance Charge Trapping Flash Memory Application
Authors: Chen Guoxing , Huo Zongliang , Zhao Shengjie , Yang Xiaonan , Liu Ziyu , Zhang Manhong , Sun Zhong , Han Yulong , Zhang Dong , Wang Chenjie , Chu Yuqiong , Liu Su , Liu Ming
Published: March 2013

ALD process of HfO2 trapping layer with TEMAH and H2O as precursors is systematically investigated . By adjusting ALD process parameters of deposition temperature, purge gas cycle mode and purge time, HfO2 film quality is effectively improved for charge trapping memories(CTM) application. It is found that a large memory window of 4.4V can be obtained for devices with parameters of 150℃ deposition temperature, one TEMAH-one water cycle mode and 5s purge time. Enhancement of memory performance is attributed to the part transformation of chemisorption into physisorption when depositing the trapping layer. For further confirmation of the conclusion, both MHOS and MAHOS structures are employed. The findings provide a guide for future design of CTM.
(Invited) Revisiting the Impact on Sub-Threshold Regions in Uniaxially-Strained FETs
Authors: Na Myung-Hee , McStay Kevin , Nowak Edward Joseph
Published: March 2013

We report that uniaxial strain in silicon FETs results in a significant modification of subthreshold and near threshold characteristics. We show that modulation of the effective mobility in the region of VTH via uniaxial strain is very nearly proportional to that observed at high gate overdrive. Thus current-density-based VTH should be redefined when significant mobility enhancement is achieved. In this paper, we propose a simple correction to account for strain in the definition of current-density threshold voltage. In particular, this correction may be critical in analog designs where absolute Vth are important to overdrive circuits accurately without leakage penalty
A New High Speed Low Power Dissipation Three-Element Si-Based SRAM Cell
Authors: Tong Xiaodong , Wu Hao , Zhao Lichuan , Zhong Huicai
Published: March 2013

A novel SRAM cell expected to increase the SRAM integration density is proposed and demonstrated with a test structure in this work. It consists of three elements: a MOSFET, a load, and a bistable PNPN diode as the storage element. The PNPN diode and the load can be integrated in a vertically stacked structure, which can be scaled as small as the design rules allow, and the MOSFET has a small gate width, so the new SRAM cell offers the possibility for much higher integration density compared to the conventional 6-T SRAM cell. Moreover, the low holding current of the PNPN diode and the soft “punch-through” design provide the potential for low power consumption and high speed applications.
Impacting Factors and Improvement for Within-Shot IDSAT Uniformity
Authors: Tao Jiajia , Li Yong , Shi Weiming , Jin Da , Li Helen , Fan Zhong , Fan Forrest , Chang Tangfeng , Zhu Star , Ju Jianhua , Yu Shaofeng
Published: March 2013

This paper studies the root causes of the impacting factors for within-shot Idsat uniformity (IDU) improvement, and presents a model to characterize the impact factors. RTA process is one of main factors leading to high IDSAT non-uniformity within-shot because its initial temperature, ramp-up rate, peak temperature and ramp-down rate can affect the amount of thermal absorption and thermal distribution in the chip. Therefore the optimized RTA process can improve the thermal distribution in the chip, hence the IDU across the wafer. We also study the correlation of the transmission rate pattern density and the equivalent reflectivity to the device performance. Based on the model simulation results, we can modify the chip arrangement within the Multi-Project Wafer (MPW) shot in the way that can optimize the RTA process and improve both NMOS and PMOS the Idsat uniformity about ~20%. The use of this model can help to provide the guideline for the optimized arrangement of multiple chips within the shot to achieve better IDU performance
Substrate effect on CD Control for Ion Implantation Layer Lithography Beyond 45 nm Node
Authors: Hu Huayong , Ding Lihua , Pei Jinhua , Shen Manhua , Shi Xuelong , Wu Qiang , Liu Qingwei , Lin Yishih , Gu Yiming
Published: March 2013

Implant level photolithography processes are becoming more and more challenging due to decreasing CD and photoresist edge placement requirements. In addition to the traditional proximity effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of mechanisms to influence the edge placement of the developed implant layer. For many implant layers, the impact of underlying topography cannot be subdued, because, because it is not desirable to employ bottom anti-reflection coating (BARC) for various reasons. Therefore, the implant OPC models calibrated on bare silicon wafers must include additional compensation components to counter the various substrate complexities from real device/design scenarios. In this paper, we show our systematic study on substrate effect (AA/STI) on implant level lithography CD printing including real wafer data analysis and simulation with wafer 3D OPC. Besides, we also show some study of the poly effect on CD. Based on the results, we generate an empirical model to match the substrate effect, and also proposed an approach with additional substrate-aware OPC rule to correct such effect.
(Keynote) Advanced Lithography for Density Scaling
Authors: Rieger Michael L
Published: March 2013

Despite the widening gap between scaled feature sizes and optical exposure wavelengths, integrated circuit transistor density so far has kept pace with Moore’s Law. The absence of viable lens materials for smaller wavelengths precludes exposure wavelengths below 193nm for refractive optical tools. Reflective optical exposure tools using extreme ultraviolet (EUV) light have been under intense development over the past decade but, mainly due to light source power shortfalls, have not yet achieved performance levels needed for high volume production. Alternatives to optical pattern transfer are also under development, including electron beam direct write, and nano-imprint lithography (NIL) systems. Until EUV or an alternative technology meets high-volume production requirements, next-generation integrated circuit process nodes will rely upon 193nm immersion lithography tools augmented with novel optical and process technologies to achieve feature pitches below the single exposure resolution limit. Squeezing more information through the limited spatial bandwidth of 193nm systems imposes limitations on design layout freedoms. Designers can no longer draw arbitrary patterns even when minimum line and space dimension constraints are met. The types of layout restrictions demanded by alternative lithography approaches, and their impact on patterning resolution and noise trade-offs, are explored in the context of evolving IC end-use values, such as density, performance, and power efficiency.
(Invited) Development Status of EUV Resist toward Sub-20nmhp
Authors: Kimura Tooru
Published: March 2013

In this paper, we focus on resolution improvement for 1xnm half pitch. We report development of new short acid diffusion length PAG and under layer to achieve 1xnm half pitch resolution. The patterning of sub 20 nm half pitch LS was gathered from NXE: 3100 will be discussed. Patterning sub 26 nm half pitch contacts is feasible with new resist materials. The optimization of development process and application of rinse process was found to be effective to improve the RLS performance. Furthermore, we will also present the effect of underlayer materials on RLS performance.
Robust Trilayer Patterning Technique
Authors: Zhu Zhimin , Weigand Micheal , Krishnamurthy Vandana , Sullivan Daniel
Published: March 2013

This paper presents the results of efforts to achieve a very wide processing window lithography using a spin-on trilayer patterning stack. Materials design and processing are based on physical and chemical properties as well as optical field distribution and focus on molecular forces between resist and substrate. All of these factors closely affect line edge roughness/line width roughness (LER/LWR) and critical dimension (CD) processing window (PW). The technique aims to provide an extremely wide CD PW for producing lines and contact patterns in a single lithographic process. The wide depth of focus (DOF) performance allows the printing of difficult patterns having low image contrast, simplifying optical proximity correction (OPC) and source mask optimization (SMO) to make patterning more robust. Scanning electron microscope (SEM) cross sections of the lithography results are presented, and these results are compared to optical simulations.
(Invited) Important Challenges in Double Patterning Processes
Authors: Yaegashi Hidetami , Oyama Kenichi , Hara Arisa , Natori Sakurako , Yamauchi Shohei , Yamato Masatoshi
Published: March 2013

Double Pattering process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device[1], and it is expanding to employ in DRAM and logic device. If EUVL should not be ready on time, the industry will likely further extend DP to multiple patterning. Our proposed photo-resist core SADP has wide extendibility to Self-aligned Pitch-Tripling (SATP) and Pith-Quadrupling (SAQP) achieved 11nm hp as introduced in previous our study[2]. Sa-MP has been required to mitigate a process complexity and cost impact. Furthermore, Process variability, Pattern fidelity, CD metrology for sub 20nm pattern also has to be considered. Beside the invention of novel technical solutions, Double-patterning process is evolving steadily and its applicability is widened.
Identification and Characterization of a Subtle Bump Defect Formed Upon Organic Mandrel in a Self-Aligned Double Patterning Process
Authors: Yang Zusing , Hsu Fang Hao , Wei Kuo Liang , Lee Hong Ji , Lian Nan Tzu , Yang Tahone , Chen Kuang Chao , Lu Chih Yuan
Published: March 2013

Core bump defect is yield killer in terms of causing blocked etch during poly-Si hard mask etching in the spacer-type self-aligned double patterning (SADP) manufacture process flow. By clarifying the characteristics and formation mechanism of the core bump defect occurred on the top of the organic mandrel post room temperature oxide deposition, several strategies, e.g., electron beam illumination, high/low pressure baking and pulsed plasma etch, were explored. Afterward an effective suppression of the core bump adder was developed, resulting in the sorting yield ramping up by 10% at least.
Applying Uniform Design of Experiment in Tri-Layer-Based Trench Etch for EM Lifetime Performance Enhancement
Authors: Zhou Jun-Qing , Yang Siyuan Frank , Wang Xin-Peng , Hu Min-Da , Wang Dong-Jiang , Zhang Cheng-Long , Cao Yi-Bin , Gan Zheng-Hao , Zhang Hai-Yang
Published: March 2013

In this paper, we studied the improvement of EM lifetime distribution including both intrinsic lifetime extension and the reduction of earlier failure percentage by applying a uniform design of experiments (UDE) to organic under layer (OUL) step. UDE is an experimental approach that is capable of distributing experiments evenly within experimental space, especially when a large number of experimental levels are required. In our case, the experiments were carried out with a six variable design table of OUL step’s important parameters including pressure, power, gas flow rate and over-etch percentage. Factor level varies from four to six for each variable based on previous silicon wafer learning. The optimal OUL condition was identified among the EM performance of 18 UDE pi-runs by means of statistically scientific analysis. The predicted condition was validated and shows the current-best EM performance from the point of view of EM lifetime and the earlier failure percentage.
Etch Process Development for a New CMOS Image Sensor
Authors: Zhong Tao , Huang Ying , Hsu Chih-Hsun , Williams Scott , Schwarz Benjamin
Published: March 2013

A novel CIS, called the backside-illuminated (BSI) CIS, is more light-sensitive and less noisy than the traditional front-illuminated (FI) CIS. The key parameters in BSI etch are sidewall profile angle, micro-trenching, and silicon loss macro-loading. In this paper, theh Applied Centura® AdvantEdge™ Mesa™ etch chamber was used to develop a BSI CIS etch process. The target profile for sidewall angle can be achieved by tuning C4F8 flow. Tuning the pressure minimizes micro-trenching at the bottom of the BSI pad. For macro-loading of silicon loss, DC (Div. Cap) and MRAD (Motorized Radial Assembly Dial) tuning can achieve minimal silicon loss with good uniformity.
The Formation of Ultra Fine Cu Metal Line with Sub 5 Micron Using Photolithography and Semi Additive Process
Authors: Lee Youngjae , Harr Kyoungmoo , Lee Chang-Bae , Kim Jin-Gu , Kim Dahee , Kweon Youngdo
Published: March 2013

Recently changes in the semiconductor industry continue toward higher functionality that leads to higher input/output (I/O) counts, pushing packaging towards higher density architectures. With increasing these market demands of electric products, printed circuit board (PCB) are pushed to accommodate these requirements also. In other words, PCB industry is experiencing tremendous pressure to enhance the wiring density and reduce that feature size of PCBs, while retaining low cost. To keep up these trends, we developed substrate technology with ultra fine line/space and high aspect ratio using sputter, photolithography and semi additive process (SAP). Photolithography is the technology of reproducing images or patterns by using UV light. The designed patterns for constructing circuits are transferred onto a photosensitive thin or thick film by photolithographic method. This technology dominates the process capability of producing fine line structure. Wet etch is currently the most popular subtractive method used in PCB industry. It is known as low resolution technology due to the nature of isotropic etches or undercut. To minimize undercut, we introduced sputtering system to SAP method for seed layer deposition. SAP method is used for build up substrate manufacturing and uses electrolytic copper plating to fill in the patterned photo resist. In this study, we have successfully formed copper lines of sub 5um which have bellow 0.5um undercut by using SAP method and photolithography.
Characteristics of HfLaON/SiO2 Gate Stack Prepared Using Reactive Sputtering
Authors: Xu Gaobo , Xu Qiuxia , Zhou Huajie , Gao Jianfeng , Xiang Jinjuan , Liu Jinbiao , Xiong Wenjuan , Lu Yihong , Wang Guilei , Li Junfeng , Zhao Chao , Chen Dapeng
Published: March 2013

HfLaON is one of the most promising high-k dielectrics because of its higher crystallization temperature and ability to tune the work function of the metal gates from Si midgap to around 4eV, meeting the requirement of nMOSFETs. In this paper, HfLaON was prepared using reactive sputtering that alternates between Hf and HfLa targets in N2/Ar ambient, followed by a post-deposition anneal. Before deposition of HfLaON film, SiO2 interfacial layer was grown to improve the interface properties. HfLaON/SiO2 gate stack exhibited good physical and electrical characteristics, including good thermal stability, excellent interface properties, small equivalent oxide thickness and low gate-leakage current. Further studies found that the excellent characteristics of the gate stack have close relation to the grown method of SiO2 interfacial layer. In order to investigate their relationship, the different grown methods of SiO2 interfacial layer were adopted and compared in the fabrication of HfLaON/SiO2 gate stacks, such as oxidation in O3/H2O solution, rapid thermal anneal in N2 or N2/O2 mixed gas.
(Invited) Thin Film Challenges of Phase Change Random Access Memory
Authors: Ren Wanchun , Jing X. Z. , Xiang Y. H. , Xiao H. B. , Zhang B. C. , Liu B. , Song Z. T. , Rao F. , Xu J. , Wu G. P. , Feng S. L.
Published: March 2013

Phase change random access memory (PCRAM) has been regarded as a promising candidate of the next generation nonvolatile memory because of its high speed, low power, good endurance, good scalability and fabrication compatibility with standard complementary metal-oxide-semiconductor process. Thin film is the most critical module in the fabrication of high density and low power consumption PCRAM as the device continues to scale down to 45 nm and below. This article shall report some key challenges in thin film area. Examples of some thin film process developments, especially in nanoscale gap filling of phase change material, peeling issue and the new phase change material development, will be provided and the preliminary results will be analyzed.
An Overview of Recent Advances in Chemical Mechanical Polishing (CMP) of Sapphire Substrates
Authors: Zhang Yu-nong , Lin Bin , Li Z.C.
Published: March 2013

Nowadays, sapphire substrates are widely employed for GaN light emitting diodes (LEDs) due to their comparatively low cost, large diameter, high quality, optical transparency, and high temperature stability etc. However, in spite of its commercial importance and extended history, the machining of sapphire remains a challenge. In the manufacture of sapphire, chemical mechanical polishing (CMP) has been widely used to obtain a mirror surface on the sapphire substrate and minimize the subsurface damages. In this paper, published literature in the past decade on CMP of sapphire substrates is summarized. Recent investigations into material removal mechanism of CMP of sapphire substrates are introduced and advances in experimental studies are reviewed in terms of abrasives, sapphire crystal orientations, pad materials, and other process parameters (such as polishing pressure, pad rotational speed, and temperature etc.). Possible topics for future research are also discussed.
Study on Improving Dishing on STI Structure
Authors: Ding Yi , Yan Junhua , Wang CongGang , Zhu Yefang , Fang JingXun
Published: March 2013

Abstract: As a front-end technology, shallow trench isolation ( STI ) is widely used in submicron nodes of IC manufacturing because of its high space utilization rate on device layout. Chemical mechanical polishing (CMP) is used to achieve planarization by polishing off the oxide on top of pad nitride in a STI structure. When STI-CMP process is completed, oxide in the trench would likely form dish-shaped structure (dishing), which negatively affects the process stability and device performance. Such negative effect becomes more significant when IC technology advancing to nanometer nodes. Thus dishing improvement in STI-CMP for nanometer technology attracts more and more attention. In this paper, we studied influences of polishing amounts, CMP pressure and some other factors on post STI-CMP dishing performance in 45/40nm node. It was concluded that increasing in oxide polishing amount can reduce dishing; decreasing polishing pressure can enhance robustness of endpoint detection but has negligible effects on dishing reduction.
(Invited) Poly-Silicon Opening Polishing Slurry Development for Advanced HKMG Process
Authors: Tsai Ming-Shih , Huang Hung-Tsung , Yeh Ming Chi , Wu Kuo Chung
Published: March 2013

Tunable silicon nitride to silicon oxide selectivity plays the key role to meet the stringent requirement of poly silicon opening polishing in the advanced HKMG applications. Independent silicon oxide removal rates tuning by surface modified colloidal silica abrasives, specific additives and abrasive loading has been demonstrated, accompanied with high silicon nitride removal rates in acidic slurry pH and unique additive, large selectivity window can be obtained.
(Invited) Influence of Components in the Slurry Delivery Chain on Slurry Health and CMP Defects
Authors: Schoeb Reto , Litchy Mark R. , Grant Donald C.
Published: March 2013

The impact of many components and handling conditions on slurry health has been investigated extensively in previous studies. Numerous studies have shown that changes in the particle size distributions in CMP slurries can have a strong impact on scratch densities and surface roughness after CMP. This paper summarizes and quantitatively compares the impact of various components and conditions on slurry particle size distributions. The paper further summarizes oversize particle and micro scratch data from five different studies with 14 different slurry & substrate combinations. The goals of this paper are to identify the key elements that influence slurry health in the slurry delivery chain and establish a correlation between particle size distributions and micro scratch defect densities.
Development of Cu CMP Slurry with High Throughput and Low Dishing
Authors: Jing Jianfen , Wang Yuchun , Zhang Jian , Cai Xinyuan , Wang Xucheng , Xu Yanting , Shi Fengjun
Published: March 2013

To follow the Moore’s law, the advanced Cu slurry needs to continue the trend of cost reduction and performance improvement at the same time. With the technology node shrinking, there is a need to develop a Cu slurry with fast rate for high throughput and low dishing for minimal within die and within wafer variation, and stringent defect requirement such as residue, corrosion, and micro scratches. In this paper, we introduce a high performance Cu CMP slurry to overcome these performance challenges in Cu CMP process. The impact of slurry formulation on the slurry performance will be presented under different process conditions, including blanket removal rates/profiles, static etch rates, dishing, Cu residue clearance capability and corrosion status. Electrochemical study was also conducted to support the results and performance. With the optimized formulation and polishing process, the slurry achieves dishing under 300A at near 1 um Cu polishing rate. For multiple layers stacking, the slurry also has tunable dishing to provide a wide process integration window.
(Invited) Performance Analysis of a Novel Slurry Injection System for Oxide Chemical Mechanical Planarization
Authors: Borucki Leonard , Zhuang Yun , Sampurno Yasa , Philipossian Ara , Kreutzer-Schneeweiss Sascha
Published: March 2013

In this study, a novel slurry injection system (SIS) was installed on an Ebara F-REX200® polisher and its performance was analyzed for oxide chemical mechanical planarization process. The slurry injector contacts the pad with a light load and applies slurry in a thin layer at the device trailing edge using single or multiple injection points. Used slurry, rinse water and pad debris are then removed from the pad by the injector leading edge. Blanket 200-mm oxide wafers were polished using Cabot Microelectronics Corporation Semi-Sperse™ 25 slurry at different flow rates (100, 150 and 200 ml/min) on Dow IC1000™ k-groove and XY-perforated pads. The results show that at each flow rate, the oxide removal rate is enhanced sufficiently over the rate from the standard slurry applicator that the flow rate can be reduced by about 35% on the XY-perforated pad and 50% on the k-groove pad without sacrificing removal rate.
Impact of 40nm BEOL Film Stack on Cu Wire Bond Wire Pull Performance
Authors: Yang Zhigang , Chen Larry , Ni Baibing , Bao Wayne
Published: March 2013

Abstract: Cu wire bond has been widely adopted instead of Au as the choice of wire-bond material mainly for high electrical performance and lower cost. However, Cu wire-bond means greater bond stress than Au wire-bond to the under layer BEOL film stacks, particularly for low K or ultra low K dielectric materials used in advanced nodes for better BEOL RC delay performance. In this work, we used Cu wire pull failure rate as an index to study and optimize the BEOL film stack. In addition, we also studied the Cu wire-bond conditions on the wire-pull performance to find the optimized bond condition. Robust process condition with improved Cu wire-pull performance has been achieved that can meet the 40nm Cu wire-bond requirements. The improved BEOL film stacks and process has passed all the process and product qualifications and implemented as the baseline process for SMIC’s 40nm-node high volume production.
Dependence of Substrate Orientation on Blistering and Exfoliation Behaviors in Ion-Implanted Hydrogen in Germanium
Authors: Chien Chi Chen , Chao D. S. , Liang J. H. , Lin C. M.
Published: March 2013

This study investigated the effects of substrate orientation on the phenomena of surface blistering and exfoliation in hydrogen implanted germanium. Ge(100) and Ge(111) wafers were employed and implanted with 200 keV H2
+ ions to a fluence of 2.5×1016 ions/cm2. Following ion implantation, the specimens were annealed using furnace annealing methods. Characteristic analyses were conducted using optical microscopy (OM), secondary ion mass spectroscopy (SIMS), and cross-sectional transmission electron microscopy (XTEM). The results show that Ge(100) has a lower activation energy level for blister and crater formation than Ge(111) does. The average diameter of blisters and craters in Ge(100) is larger than that in Ge(111). Ge(100) also has a lower areal number density of blisters, but a higher one of craters. Furthermore, the micro-cracks in Ge(100) corresponds to a thicker exfoliated thickness as well as a more evident extension and growth than those in Ge(111).
Effect of the Interfacial SiO2 Layer on High-k Gate Stacks
Authors: Chen Yong , He Yonggen , Liu Hailong , Yu Guobin , Liu Jialei , Hong Zhongshan , Ni Jinhua , Wu Jingang
Published: March 2013

Interfacial oxide (IL) /high-k (HK) gate dielectric stack is widely used in 45nm logic technology and beyond nodes. Interfacial oxide, which is buffer layer between silicon substrate and HK dielectric, is a crucial factor to control Silicon/IL, IL/high-k interface charge and high-k film quality. In this work, atom layer deposition (ALD) Hf based HK film is deposited on two classes of IL by thermal oxidation (process A or B) and chemical oxidation (process C or D), respectively. XPS is used to characterize the film bonding energy, while non contact CV and spectroscopic ellipsometry (SE) are used to characterize the interface trap. The electric properties of the film stacks are characterized by C-V and I-V curves. The results reveal that interface trap of chemical oxide film has positive surface voltage and less dense SiOx, as compared with that of thermal oxide. With the same interfacial oxide thickness and HK deposition process, the chemical oxide/HK stack got 3.4A thick EOT, which is about two orders lower leakage than that of thermal oxide/HfO2. It can be explained by the fact that chemical oxide had plenty of O-H bonds, which is good for ALD Hf based HK film nucleation and growth and resulted in good film quality. However, due to the high Si/chemical oxide interfacial charge, the chemical oxide/HfO2 dielectric stack has a disadvantage of the larger C-V hysteresis.
Dicing Tape Evaluation for Wire-Bond and Bumped Flip Chip Wafer Applications
Authors: Pan Shannon , Li Kent , Dang Shannon , Chen Xing Long , Zhang Yalong , Liu Kevin , Kopp Bill , Haji-Rahim Mohsen , Warren Waite
Published: March 2013

Abstract This paper presents evaluation results of dicing tape selection for wire-bond and flip chip wafers in a volume production assembly environment. The goal of this project is to investigate a tape with low material cost, long shelf life and minimal dicing and die picking damages. Tape selection considerations, method and an evaluation plan were established, including inspection criteria for dicing and subsequent assembly steps.
(Invited) Solder Volume Effect on Interfacial Reaction between Sn-3.0Ag-0.5Cu Solder Balls and Cu Substrates - Experiment and Simulation
Authors: Huang Mingliang , Yang Fan , Zhao Ning , Liu Xiaoying
Published: March 2013

With the continuous miniaturization of electronic devices, solder joints are downsizing simultaneously. The downsizing of the solder balls may have a detrimental effect on the reliability of the solder joints. Because smaller solder joint has thicker intermetallic compound (IMC) layer which may degrade the mechanical properties of the solder joints. The solder volume effect on interfacial reaction was demonstrated in the present work. It was shown that, when the smaller solder ball was used, the Cu6Sn5 grains became larger and the interfacial intermetallic compound (IMC) layer became thicker, which were accompanied by less Cu consumption and higher Cu concentration in molten solder. A theoretical model was established to calculate the growth kinetics of the interfacial IMC and the consumption kinetics of the Cu pad during the liquid/solid reaction. The calculated results were compared with the experimental ones, and a good agreement was achieved.
Numerical Analysis on the Heat Transfer of Heatsink with Micro-Pin-Fins
Authors: Chiu Han-Chieh , Hsieh Ren-Horn , Jang Jer-Huan
Published: March 2013

This paper numerically studies the heat transfer in heat sinks with micro-pin-fins. Commercial software, ICEPAK, was used to explore the effect of micro-pin-fin array design on the flow rate and heat transfer characteristics of liquid cooling heat sink. The parameters include the diameter of pin fin, the gap between the pin fins, and the relative position between the pin fins. The diameters of the pin fin are 0.5mm, 0.6mm, and 0.7mm, respectively. The gap between the pin fins are 0.2mm, 0.25mm, 0.3mm, 0.4mm, and 0.5mm, respectively. Three types of fin array arrangements are set with different longitudinal spacing and transverse spacing. The driving force of the working fluid is the pressure head with 500, 1500, and 3000 Pa, respectively. Results show that the effective thermal resistance ranges from 0.27 to 0.55 with the power density of 300kW/m2.
Quantitative Index for Prediction of Properties of Process Early Detection Capability
Authors: Ma Jinyi Jenny , Kang Sheng Randy , Chen Zhenxiang JS , Chien Weiting Kary , Wang Xiaoqian Elaine , Ji Xinyuan Serena
Published: March 2013

Early detection of serious problems through the use of sensitive statistical methods could save a great deal of resources including financial investment and the scope of impacts with allowing early action to mitigate potential problems. Actually, there are many early detection approaches taken in process steps, such as inline/ offline SPC for each process detections, and failure isolation, failure/ defect/ material analysis to detect yield and reliability nonconformance. But till now, there is no index to indicate the whole foundry process’s early detection capability. In this paper, we firstly introduced the early detection calculation methods and define Early Detection Score (EDS) which covers the whole manufacturing process from AA (Active Area definition) to FT (Final Test) with three key screening stages: inline, WAT, and FT. With these three keys, we can assign the score accordingly based on the detection stage and timing. The earlier it is detected, the higher the score. Furthermore, we proposed five calculations, which can be applied for different purpose or improvements. In addition to the numerical calculation methods, we develop a total solution for the early detection system, which includes data collection, calculation template, scoring scheme, early detection capability target for each stage, and the routine (e.g., weekly/ monthly) review system.
Endpoint Detection Using Principle Component Analysis and Local Outlier Factor in the Double Layer Plasma Etching
Authors: Shin Sung-Hwan , Han Yi-Seul , Park Young-Kook , Hong Sang Jeen , Han Seung-Soo
Published: March 2013

Abstract.In plasma etch process, the optical emission spectroscope (OES) is widely used to detect plasma etch endpoint. The OES gathers the intensity of the wavelength from the radicals in the plasma chamber. In addition, the OES is very sensitive to the external elements or a particles, which means that there are diverse noise in OES data. Therefore, it is necessary to choose meaningful data, reduce noise, and reduce the quantity of data. In this paper, a new method to detect endpoint of double layer plasma etching is proposed. This algorithm uses data from OES and utilizing principle component analysis (PCA) and local outlier factor (LOF).
Preferred NV Field for Arbitrary Crossed-Gratings with Analytic Boundary
Authors: Deng Hao , Chen Shuqiang
Published: March 2013

The convergence problem of RCWA is still discussed up to now. Several methods are efficient to improve the convergence rate, such as the emprical method by Lanlane, and the normal vector (NV) method by Schuster et al.. It is a consuming-time method to set up NV fields. According to the method by Götz, the convergence problem of NV-RCWA is affected by the direction of NV field. In this paper, we simplify the work of setting up NV fields for arbitrary cross-gratings with analytic boundary based on Götz’s method. To implement the NV method, four types of NV fields are analyzed, and an optimized chose method of the preferred NV is discussed.
Vacuum Ultraviolet Spectrometric Ellipsometry Application to Optical Metrology of High-κ Dielectrics and Metal Gate Materials
Authors: Chen Yong , Wu Zhenyu , He Yonggen , Ye Junjie , Jiang Zhiming , Dong Hao
Published: March 2013

Nowadays an accurate measurement of the high-k dielectrics (HK) and metal gate (MG) material thickness and properties is becoming more and more important for beyond 40nm technology. Traditional optical broad band spectrometric ellipsometry (BBSE) (wavelength range 240~800 nm) thickness metrology is suffering from poor accuracy among initial layer (IL), HK layer and MG layers in multi-layer stacks and poor repeatability. By extending wavelength down to 150nm, KLA-Tencor Aleris 8500 Vacuum Ultraviolet SE (VUVSE) greatly improves measurement performance, and enables deduction of film energy bandgap and defect information from offline spectra analysis. In this work, the measurement performance on HKMG stacks with BBSE and advanced VUVSE were compared systematically. The better performance of VUVSE in metrology accuracy and repeatability was displayed. The results of measurement can be highly correlated with film production process conditions, including both in multi-layer stack thickness measurement and in HK material band gap and defects study.
Resistance Switching Properties of Titanium Oxide with Different Copper Electrode Structure
Authors: Shao Xinglong , Zhao Jinshi , Zhang Kailiang , Chen Ran , Zhou Liwei , Chen Changjun , Wang Jianyun
Published: March 2013

The reversible resistance switching (RS) effect of the Al/TiOx/Cu structure was investigated in this study. This RS is attributed to space-charge-limited conduction controlled by localized copper ions trap near the Cu electrode. Filament formation and dissolution in the Al/TiOx/Cu system were discussed to compare with the Cu/TiOx/Al decice. The linear relationship between the reset current and compliance current was discussed, it shown that the method to measurement play a important role. The electrical transport mechanism during the resistance switch periods are controlled by space charge limited current (SCLC) theory.
Synthesis of Zinc Oxide Nanowires by Cu-Additive Zinc Acetate Solution with Hydrothermal Method
Authors: Wang Yuzhu , Lai Yunfeng , Cheng Shuying
Published: March 2013

Zinc oxide (ZnO) nanowires were synthesized on bare silicon substrates and sputtered-ZnO seeded substrates by hydrothermal method in mixture solution of zinc acetate and cooper acetate. The nanowires are in random alignment on the bare substrate, while the vertically aligned nanowires with a c-axis (002) preferential orientation are available on the ZnO seeded substrate. The near band-edge UV emission peaks on the PL spectra could be seen, indicating a good crystal structure of ZnO. With the increase of cooper concentration, the intensity of UV peak decreases but that of green emission peak enhances, which means the defects inside nanowires could be increased by the cooper additive. For the Raman measurement, there is 437 cm-1 centered peak for each sample, indicating that nanowires are perfect hexagonal wurtzite structure. In the Raman spectra, the 581.4 cm-1 centered peak attributed to oxygen vacancies could also be seen for the sample with cooper additive.
Graphene-Based Inductors: Fabrication and Performance
Authors: Zhou Mengjie , Ren Liming , Wei Zijun , Zhao Hua-Bo , Hu Baodong , Jia Yuehui , Shi Zujin , Fu Yunyi , Huang Ru , Zhang Xing
Published: March 2013

Inductors are key passive components in analog circuits. The graphene is considered as the possible materials to develop the nanoscale inductors since the graphene has many advantages over Cu and Al. In this paper, we report the key fabrication processes and the performance of graphene-based inductors.
(Keynote) PowerMEMS Based on Semiconductor Technologies and Nano Materials
Authors: Wang Xiaohong , Shen Caiwei , Xing Hexin
Published: March 2013

This paper reviews our research on the micro direct methanol fuel cells (μDMFC) first, including the anode design for power-free fuel delivering, the cathode design with capillary-based water drawn out for an air-breathing μDMFC, as well as a novel assembly method using multi-layer bonding technique on the μDMFC. Second, our research on micro supercapacitors will be introduced. A high-aspect-ratio interdigital structure for 3D micro supercapacitor is achieved by combining SU-8 photoresist with self-supporting active materials. Then, in order to develop an effective and direct way for batch fabrication of micro energy storage devices, we demonstrate an idea of incorporating nano templating method developed in material science into photolithography, which is the most commonly used semiconductor technology. The method can directly prototype operational micro devices at wafer level, especially micro supercapacitors as demonstrated.
(Invited) Direct Electrochemical Detection of ssDNA with a Micro Three-Electrode System
Authors: Deng Tao , Zhao Chen Xu , Li Meng Wei , Liu Ze Wen
Published: March 2013

The intrinsic electrochemical activity of single strand deoxyribonucleic acid (ssDNA) is investigated with a micro three-electrode system (MTES) integrated inside an in situ electrochemical detection μPCR (EC-μPCR) chip. Based on the MTES, electrochemical cyclic voltammetry (CV) was performed with both normal ssDNA and special ssDNA(Guanine absence) solutions. Experimental results showed that the MTES can directly detect the electrochemical oxidation of the guanine in ssDNA. After a prepolarization step with a positive potential (+500 mV) applied to the MTES for 15 minutes, the electrochemical oxidation peak current of normal ssDNA can be increased about 40%. The detection limit of the MTES with CV method for normal ssDNA is down to 45 nM. The results reveal that label-free and real-time detection of PCR amplicons by directly monitoring the electrochemical oxidation of ssDNA is promising.
Unified Automated System Level Test Bench to Verify DDR2/3/4 and LPDDR2 Memory Controllers - Layered
Authors: Raghavendra Javagal Nagaraja
Published: March 2013

This paper aims at discussing in architecting a Generic Infrastructure for an Automated Layered Test Bench to verify DDR2, DDR3, DDR4 and LPDDR2 memory controller design independently in compliant with Open Verification Methodology (OVM) guidelines. This environment while satisfying the horizontal/vertical re-usability can be configured to verify each memory standard independently and across the projects with configurable user interfaces such as AXI, XILINX Custom interfaces (User Interface / Native Interface) in a plug-play fashion. This paper also aims at the effective usage of SV constructs and OVM built in features like Parameterized classes, OVM configuration mechanism, Macros, Reporting Mechanism which are used to build a Re-usable automated and layered system level test bench to be used across a set of technologies and projects.
Mice lacking the intestinal peptide transporter display reduced energy intake and a subtle maldigestion/malabsorption that protects them from diet-induced obesity
Authors: Kolodziejczak Dominika , Spanier Britta , Pais Ramona , Kraiczy Judith , Stelzl Tamara , Gedrich Kurt , Scherling Christian , Zietek Tamara , Daniel Hannelore
Published: March 2013

The intestinal transporter PEPT1 mediates the absorption of di- and tripeptides originating from breakdown of dietary proteins. Whereas mice lacking PEPT1 did not display any obvious changes in phenotype on a high-carbohydrate control diet (HCD), Pept1−/− mice fed a high-fat diet (HFD) showed a markedly reduced weight gain and reduced body fat stores. They were additionally protected from hyperglycemia and hyperinsulinemia. Energy balance studies revealed that Pept1−/− mice on HFD have a reduced caloric intake, no changes in energy expenditure, but increased energy content in feces. Cecal biomass in Pept1−/− mice was as well increased twofold on both diets, suggesting a limited capacity in digesting and/or absorbing the dietary constituents in the small intestine. GC-MS-based metabolite profiling of cecal contents revealed high levels and a broad spectrum of sugars in PEPT1-deficient mice on HCD, whereas animals fed HFD were characterized by high levels of free fatty acids and absence of sugars. In search of the origin of the impaired digestion/absorption, we observed that Pept1−/− mice lack the adaptation of the upper small intestinal mucosa to the trophic effects of the diet. Whereas wild-type mice on HFD adapt to diet with increased villus length and surface area, Pept1−/− mice failed to show this response. In search for the origin of this, we recorded markedly reduced systemic IL-6 levels in all Pept1−/− mice, suggesting that IL-6 could contribute to the lack of adaptation of the mucosal architecture to the diets.