Ultra-Low Temperature Epitaxy of Ge-Rich Nanosheets on SOI for Reconfigurable Transistor Applications
Authors: Prado-Navarrete Enrique , Wilflingseder Christoph , Salomon Andreas , Fromherz Thomas , Sistani Masiar , Fuchsberger Andreas , Wind Lukas , Nazzari Daniele , Weber Walter M. , Aberl Johannes , Brehm Moritz 
Published: December 2024

Implementing only tens of nanometer-thin Ge and Ge-rich SiGe nanosheets on SOI is expected to boost performance metrics of next-generation electronic devices, such as reconfigurable field effect transistors [1]. However, an inherent lattice mismatch between Ge and Si drastically limits the thickness of high-quality Ge layers on Si to a few monolayers, i.e., far too thin for practical nanosheet device applications. Thus, to date, many prototype Ge-rich nanoelectronics device concepts are based on nanowires' vapor-liquid-solid (VLS) growth. Since these nanowires grow on untypical (111) substrates and in a vertical manner, they need to be picked and placed onto Si(001) substrates: A serial process and, thus, barely scalable. Therefore, whenever two-dimensional nanosheets of a material are available, they provide distinct advantages with respect to the scalability of the device integration. Here, we show that pure Ge and SiGe alloyed nanowires can be formed top-down from nanosheets. We show that devices from nanowires based on Ge on SOI nanosheets have excellent quality and can outperform other material platforms, such as VLS nanowires or devices based on GeOI substrates, thereby enabling extended device functionalities [2].

For high Ge contents and typical Ge growth temperature above 500°C, the achievable thickness of pseudomorphic, defect-free (Si)Ge epilayers is just a couple of monolayers if grown directly on Si(001) substrates [3,4]. Above this thickness, the inherent strain between the layer and SOI substrate leads to harmful plastic or elastic relaxation under common growth conditions.

We depart from established (Si)Ge epitaxy temperatures of ≥500°C and employ molecular beam epitaxy (MBE) growth at ultra-low temperatures (ULT), ranging from 100°C to 350°C [5,6]. We show that the lowered surface kinetics leads to a pronounced layer supersaturation, allowing us to access layer thicknesses about an order of magnitude larger than previously reported values. Also, in contrast with previous results for ULT epitaxy [7], we do not observe layer amorphization even for growth at 100°C. Here, we highlight that pristine growth pressures deep in the ultra-high vacuum range (≤10-10 mbar) are crucial to keep the density of unwanted impurities in the (Si)Ge layers to a minimum and, thus, enable excellent electrical and optical properties of the grown heterostructures. These low growth pressures are particularly important in ULT growth since the low thermal budget impedes the efficient desorption of residual gas molecules from the substrate.

We further show the fabrication of nanosheet transistors based on fully strained, defect-free (Si)Ge epilayers grown directly on SOI substrates [2,8,9]. For these devices, properties like thickness, SiGe(Sn) content, barrier material, and doping can be conveniently tuned during the epitaxy process beyond past limitations. We demonstrate that these nanosheets are a highly scalable platform for emerging devices, such as reconfigurable transistors with excellent performance [2,8,9] and highly symmetric n- and p-type transistor characteristics. Notably, the ULT-grown nanolayers withstand high-temperature device fabrication steps such as SiO2 formation and Al-SiGe exchange [2,8,9].

References

[1] A. Heinzig et al., Nano Lett. 12, 119 (2012).

[2] A Fuchsberger et al., IEEE Journal of the Electron Devices Society 12, 83 (2024)

[3] H. Sunamura et al., Appl. Phys. Lett. 66, 3024 (1995).

[4] M. Brehm et al., Nanotechnology 28 (39), 392001 (2017).

[5] A. Salomon et al., physica status solidi (a) 219, 2200154 (2022).

[6] J. Aberl et al., https://arxiv.org/abs/2402.19227v1

[7] D. J. Eaglesham; M. Cerullo, Appl. Phys. Lett. 58, 2276 (1991).

[8] L. Wind et al., Small 18 (44), 2204178 (2022).

[9] A. Fuchsberger, et al., Advanced Electronic Materials, 2201259 (2023).