bluuebunny/crossref_metadata_2025 huggingface dataset:
Scalable high performance main memory system using phase-change memory technology
Authors: Qureshi Moinuddin K. , Srinivasan Vijayalakshmi , Rivers Jude A.
Published: June 2009

The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community.
Phase Change Memory (PCM)
devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints.

In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.
Stream chaining
Authors: Diaz Pedro , Cintra Marcelo
Published: June 2009

Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetchers operate by identifying patterns and correlations in the miss address stream. Separating streams according to the memory access instruction that generates the misses is an effective way of filtering out spurious addresses from predictable streams. On the other hand, by localizing streams based on the memory access instructions, such prefetchers both lose the complete time sequence information of misses and can only issue prefetches for a single memory access instruction at a time.

This paper proposes a novel class of prefetchers based on the idea of linking various localized streams into predictable chains of missing memory access instructions such that the prefetcher can issue prefetches along multiple streams. In this way the prefetcher is not limited to prefetching deeply for a single missing memory access instruction but can instead adaptively prefetch for other memory access instructions closer in time.

Experimental results show that the proposed prefetcher consistently achieves better performance than a state-of-the-art prefetcher -- 10% on average, being only outperformed in very few cases and then by only 2%, and outperforming that prefetcher by as much as 55% -- while consuming the same amount of memory bandwidth.
Memory mapped ECC
Authors: Yoon Doe Hyun , Erez Mattan
Published: June 2009

This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processor resources become constrained and error propensity increases. The continuing decrease in SRAM cell size and the growing capacity of caches increases the likelihood of errors in SRAM arrays. To address this, redundant information can be used to correct a value after an error occurs. Information redundancy is typically provided through error-correcting codes (ECC), which append bits to every SRAM row and increase the array's area and energy consumption. We make three observations regarding error protection and utilize them in our architecture: (1) much of the data in a cache is replicated throughout the hierarchy and is inherently redundant; (2) error-detection is necessary for every cache access and is cheaper than error correction, which is very infrequent; (3) redundant information for correction need not be stored in high-cost SRAM. Our unique architecture only dedicates SRAM for error detection while the ECC bits are stored within the memory hierarchy as data. We associate a physical memory address with each cache line for ECC storage and rely on locality to minimize the impact. The cache is dynamically and transparently partitioned between data and ECC with the fraction of ECC growing with the number of dirty cache lines. We show that this has little impact on both performance (1.3% average and < 4%) and memory traffic (3%) across a range of memory-intensive applications.
AnySP
Authors: Woh Mark , Seo Sangwon , Mahlke Scott , Mudge Trevor , Chakrabarti Chaitali , Flautner Krisztian
Published: June 2009

In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world-a device that we now all depend on in our daily lives. The current generation of devices employs a combination of general-purpose processors, digital signal processors, and hardwired accelerators to provide giga-operations-per-second performance on milliWatt power budgets. Such heterogeneous organizations are inefficient to build and maintain, as well as waste silicon area and power. Looking forward to the next generation of mobile computing, computation requirements will increase by one to three orders of magnitude due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent. Scaling of existing approaches will not suffice instead the inherent computational efficiency, programmability, and adaptability of the hardware must change. To overcome these challenges, this paper proposes an example architecture, referred to as AnySP, for the next generation mobile signal processing. AnySP uses a co-design approach where the next generation wireless signal processing and high-definition video algorithms are analyzed to create a domain specific programmable architecture. At the heart of AnySP is a configurable single-instruction multiple-data datapath that is capable of processing wide vectors or multiple narrow vectors simultaneously. In addition, deeper computation subgraphs can be pipelined across the single-instruction multiple-data lanes. These three operating modes provide high throughput across varying application types. Results show that AnySP is capable of sustaining 4G wireless processing and high-definition video throughput rates, and will approach the 1000 Mops/mW efficiency barrier when scaled to 45nm.
Rigel
Authors: Kelm John H. , Johnson Daniel R. , Johnson Matthew R. , Crago Neal C. , Tuohy William , Mahesri Aqeel , Lumetta Steven S. , Frank Matthew I. , Patel Sanjay J.
Published: June 2009

This paper considers Rigel, a programmable accelerator architecture for a broad class of data- and task-parallel computation. Rigel comprises 1000+ hierarchically-organized cores that use a fine-grained, dynamically scheduled single-program, multiple-data (SPMD) execution model. Rigel's low-level programming interface adopts a single global address space model where parallel work is expressed in a task-centric, bulk-synchronized manner using minimal hardware support. Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and/or restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications.

We perform a design analysis of Rigel to quantify the compute density and power efficiency of our initial design. We find that Rigel can achieve a density of over 8 single-precision GFLOPS/mm2in 45nm, which is comparable to high-end GPUs scaled to 45nm. We perform experimental analysis on several applications ported to the Rigel low-level programming interface. We examine scalability issues related to work distribution, synchronization, and load-balancing for 1000-core accelerators using software techniques and minimal specialized hardware support. We find that while it is important to support fast task distribution and barrier operations, these operations can be implemented without specialized hardware using flexible hardware primitives.
Multi-execution
Authors: Biswas Susmit , Franklin Diana , Savage Alan , Dixon Ryan , Sherwood Timothy , Chong Frederic T.
Published: June 2009

While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial demands on off-chip bandwidth and make the memory wall more significant than ever. This paper demonstrates that one profitable application of multicore processors is the execution of many similar instantiations of the same program. We identify that this model of execution is used in several practical scenarios and term it as "multi-execution." Often, each such instance utilizes very similar data. In conventional cache hierarchies, each instance would cache its own data independently. We propose the Mergeable cache architecture that detects data similarities and merges cache blocks, resulting in substantial savings in cache storage requirements. This leads to reductions in off-chip memory accesses and overall power usage, and increases in application performance. We present cycle-accurate simulation results of 8 benchmarks (6 from SPEC2000) to demonstrate that our technique provides a scalable solution and leads to significant speedups due to reductions in main memory accesses. For 8 cores running 8 similar executions of the same application and sharing an exclusive 4-MB, 8-way L2 cache, the Mergeable cache shows a speedup in execution by 2.5x on average (ranging from 0.93x to 6.92x), while posing an overhead of only 4.28% on cache area and 5.21% on power when it is used.
A case for bufferless routing in on-chip networks
Authors: Moscibroda Thomas , Mutlu Onur
Published: June 2009

Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip interconnection networks that eliminates the need for buffers for routing or flow control. We describe new algorithms for routing without using buffers in router input/output ports. We analyze the advantages and disadvantages of bufferless routing and discuss how router latency can be reduced by taking advantage of the fact that input/output buffers do not exist. Our evaluations show that routing without buffers significantly reduces the energy consumption of the on-chip cache/processor-to-cache network, while providing similar performance to that of existing buffered routing algorithms at low network utilization (i.e., on most real applications). We conclude that bufferless routing can be an attractive and energy-efficient design option for on-chip cache/processor-to-cache networks where network utilization is low.
Application-aware deadlock-free oblivious routing
Authors: Kinsy Michel A. , Cho Myong Hyon , Wen Tina , Suh Edward , van Dijk Marten , Devadas Srinivas
Published: June 2009

Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framework for application-aware routing that assures deadlock-freedom under one or more channels by forcing routes to conform to an acyclic channel dependence graph. Arbitrary minimal routes can be made deadlock-free through appropriate static channel allocation when two or more channels are available. Given bandwidth estimates for flows, we present a mixed integer-linear programming (MILP) approach and a heuristic approach for producing deadlock-free routes that minimize maximum channel load. The heuristic algorithm is calibrated using the MILP algorithm and evaluated on a number of benchmarks through detailed network simulation. Our framework can be used to produce application-aware routes that target the minimization of latency, number of flows through a link, bandwidth, or any combination thereof.
The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization
Authors: Dirik Cagdas , Jacob Bruce
Published: June 2009

As their prices decline, their storage capacities increase, and their endurance improves, NAND Flash Solid State Disks (SSD) provide an increasingly attractive alternative to Hard Disk Drives (HDD) for portable computing systems and PCs. This paper presents a study of NAND Flash SSD architectures and their management techniques, quantifying SSD performance under user-driven/PC applications in a multi-tasked environment; user activity represents typical PC workloads and includes browsing files and folders, emailing, text editing and document creation, surfing the web, listening to music and playing movies, editing large pictures, and running office applications.

We find the following: (a) the real limitation to NAND Flash memory performance is not its low per-device bandwidth but its internal core interface; (b) NAND Flash memory media transfer rates do not need to scale up to those of HDDs for good performance; (c) SSD organizations that exploit concurrency at both the system and device level (e.g. RAID-like organizations and Micron-style (superblocks) improve performance significantly; and (d) these system- and device-level concurrency mechanisms are, to a significant degree, orthogonal: that is, the performance increase due to one does not come at the expense of the other, as each exploits a different facet of concurrency exhibited within the PC workload.
End-to-end performance forecasting
Authors: Saidi Ali G. , Binkert Nathan L. , Reinhardt Steven K. , Mudge Trevor
Published: June 2009

Many important workloads today, such as web-hosted services, are limited not by processor core performance but by interactions among the cores, the memory system, I/O devices, and the complex software layers that tie these components together. Architects designing future systems for these workloads are challenged to identify performance bottlenecks because, as in any concurrent system, overheads in one component may be hidden due to overlap with other operations. These overlaps span the user/kernel and software/hardware boundaries, making traditional performance analysis techniques inadequate.

We present a methodology for identifying end-to-end critical paths across software and simulated hardware in complex networked systems. By modeling systems as collections of state machines interacting via queues, we can trace critical paths through multiplexed processing engines, identify when resources create bottlenecks (including abstract resources such as flow-control credits), and predict the benefit of eliminating bottlenecks by increasing hardware speeds or expanding available resources.

We implement our technique in a full-system simulator and analyze a TCP microbenchmark, a web server, the Linux TCP/IP stack, and an Ethernet controller. From a single run of the microbenchmark, our tool--within minutes--correctly identifies a series of bottlenecks, and predicts the performance of hypothetical systems in which these bottlenecks are successively eliminated, culminating in a total speedup of 3X.We then validate these predictions through hours of additional simulation, and find them to be accurate within 1--17%. We also analyze the web server, find it to be CPU-bound, and predict the performance of a system with an additional core within 6%.
Scaling the bandwidth wall
Authors: Rogers Brian M. , Krishna Anil , Bell Gordon B. , Vu Ken , Jiang Xiaowei , Solihin Yan
Published: June 2009

As transistor density continues to grow at an exponential rate in accordance to Moore's law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-chip cores proportionally. Unfortunately, off-chip memory bandwidth capacity is projected to grow slowly compared to the desired growth in the number of cores. This creates a situation in which each core will have a decreasing amount of off-chip bandwidth that it can use to load its data from off-chip memory. The situation in which off-chip bandwidth is becoming a performance and throughput bottleneck is referred to as the
bandwidth wall
problem.

In this study, we seek to answer two questions: (1) to what extent does the bandwidth wall problem restrict future multicore scaling, and (2) to what extent are various bandwidth conservation techniques able to mitigate this problem. To address them, we develop a simple but powerful analytical model to predict the number of on-chip cores that a CMP can support given a limited growth in memory traffic capacity. We find that the bandwidth wall can severely limit core scaling. When starting with a balanced 8-core CMP, in four technology generations the number of cores can only scale to 24, as opposed to 128 cores under proportional scaling, without increasing the memory traffic requirement. We find that various individual bandwidth conservation techniques we evaluate have a wide ranging impact on core scaling, and when combined together, these techniques have the potential to enable super-proportional core scaling for up to 4 technology generations.
A memory system design framework
Authors: Firoozshahian Amin , Solomatnikov Alex , Shacham Ofer , Asgar Zain , Richardson Stephen , Kozyrakis Christos , Horowitz Mark
Published: June 2009

As CPU cores become building blocks, we see a great expansion in the types of on-chip memory systems proposed for CMPs. Unfortunately, designing the cache and protocol controllers to support these memory systems is complex, and their concurrency and latency characteristics significantly affect the performance of any CMP. To address this problem, this paper presents a microarchitecture framework for cache and protocol controllers, which can aid in generating the RTL for new memory systems. The framework consists of three pipelined engines' request-tracking, state-manipulation, and data movement' which are programmed to implement a higher-level memory model. This approach simplifies the design and verification of CMP systems by decomposing the memory model into sequences of state and data manipulations. Moreover, implementing the framework itself produces a polymorphic memory system.

To validate the approach, we implemented a scalable, flexible CMP in silicon. The memory system was then programmed to support three disparate memory models' cache coherent shared memory, streams and transactional memory. Measured overheads of this approach seem promising. Our system generates controllers with performance overheads of less than 20% compared to an ideal controller with zero internal latency. Even the overhead of directly implementing a fully programmable controller was modest. While it did double the controller's area, the amortized effective area in the system grew by roughly 7%.
Achieving predictable performance through better memory controller placement in many-core CMPs
Authors: Abts Dennis , Enright Jerger Natalie D. , Kim John , Gibson Dan , Lipasti Mikko H.
Published: June 2009

In the near term, Moore's law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents the integration of a large number of memory controllers on-chip. With many cores, and few memory controllers, where to locate the memory controllers in the on-chip interconnection fabric becomes an important and as yet unexplored question. In this paper we show how the location of the memory controllers can reduce contention (hot spots) in the on-chip fabric and lower the variance in reference latency. This in turn provides predictable performance for memory-intensive applications regardless of the processing core on which a thread is scheduled. We explore the design space of on-chip fabrics to find optimal memory controller placement relative to different topologies (i.e. mesh and torus), routing algorithms, and workloads.
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
Authors: Madriles Carlos , López Pedro , Codina Josep M. , Gibert Enric , Latorre Fernando , Martinez Alejandro , Martinez Raúl , Gonzalez Antonio
Published: June 2009

Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism (TLP), and even a small part with limited TLP impose important constraints to the global performance, as explained by Amdahl's law.

In this paper we propose a novel approach for leveraging multiple cores to improve single-thread performance in a multi-core design. The proposed technique features a set of novel hardware mechanisms that support the execution of threads generated at compile time. These threads result from a fine-grain speculative decomposition of the original application and they are executed under a modified multi-core system that includes: (1) mechanisms to support multiple versions; (2) mechanisms to detect violations among threads; (3) mechanisms to reconstruct the original sequential order; and (4) mechanisms to checkpoint the architectural state and recovery to handle misspeculations.

The proposed scheme outperforms previous hardware-only schemes to implement the idea of combining cores for executing single-thread applications in a multi-core design by more than 10% on average on Spec2006 for all configurations. Moreover, single-thread performance is improved by 41% on average when the proposed scheme is used on a Tiny Core, and up to 2.6x for some selected applications.
Simultaneous speculative threading
Authors: Chaudhry Shailender , Cypher Robert , Ekman Magnus , Karlsson Martin , Landin Anders , Yip Sherman , Zeffer Håkan , Tremblay Marc
Published: June 2009

This paper presents Simultaneous Speculative Threading (SST), which is a technique for creating high-performance area- and power-efficient cores for chip multiprocessors. SST hardware dynamically extracts two threads of execution from a single sequential program (one consisting of a load miss and its dependents, and the other consisting of the instructions that are independent of the load miss) and executes them in parallel. SST uses an efficient checkpointing mechanism to eliminate the need for complex and power-inefficient structures such as register renaming logic, reorder buffers, memory disambiguation buffers, and large issue windows. Simulations of certain SST implementations show 18% better per-thread performance on commercial benchmarks than larger and higher-powered out-of-order cores. Sun Microsystems' ROCK processor, which is the first processor to use SST cores, has been implemented and is scheduled to be commercially available in 2009.
Guest column
Authors: Trevisan Luca
Published: June 2009

Additive combinatorics is the branch of combinatorics where the objects of study are subsets of the integers or of other abelian groups, and one is interested in properties and patterns that can be expressed in terms of linear equations. More generally, arithmetic combinatorics deals with properties and patterns that can be expressed via additions and multiplications.

In the past ten years, additive and arithmetic combinatorics have been extremely successful areas of mathematics, featuring a convergence of techniques from graph theory, analysis and ergodic theory. They have helped prove long-standing open questions in additive number theory, and they offer much promise of future progress.

Techniques from additive and arithmetic combinatorics have found several applications in computer science too, to property testing, pseudorandomness, PCP constructions, lower bounds, and extractor constructions. Typically, whenever a technique from additive or arithmetic combinatorics becomes understood by computer scientists, it finds some application.

Considering that there is still a lot of additive and arithmetic combinatorics that computer scientists do not understand (and, the field being very active, even more will be developed in the near future), there seems to be much potential for future connections and applications.
Optimized on-chip pipelining of memory-intensive computations on the cell BE
Authors: Kessler Christoph W. , Keller Jörg
Published: June 2009

Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and thus increase performance, by expressing our application as a task graph, by running dependent tasks concurrently and by pipelining results directly from task to task where possible, instead of buffering in off-chip memory. To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE. We present three approaches: an integer linear programming formulation that allows to compute Paretooptimal mappings for smaller task graphs, general heuristics, and a problem speci c approximation algorithm. We validate the mappings for dataparallel computations and sorting.
Automatic parallelization of simulation code for equation-based models with software pipelining and measurements on three platforms
Authors: Lundvall Håkan , Stavåker Kristian , Fritzson Peter , Kessler Christoph
Published: June 2009

In this work we report results from a new integrated method of automatically generating parallel code from Modelica models by combining parallelization at two levels of abstraction. Performing inline expansion of a Runge-Kutta solver combined with fine-grained automatic parallelization of the right-hand side of the resulting equation system opens up new possibilities for generating high performance code, which is becoming increasingly relevant when multi-core computers are becoming commonplace. An implementation, in the form of a backend module for the OpenModelica compiler, has been developed and used for measurements on two architectures: Intel Xeon and SGI Altix 3700 Bx2. This paper also contains some very recent results of a prototype implementation of this parallelization approach on the Cell BE processor architecture.
Ustilago maydis as a Pathogen
Authors: Brefort Thomas , Doehlemann Gunther , Mendoza-Mendoza Artemio , Reissmann Stefanie , Djamei Armin , Kahmann Regine
Published: June 2009

The Ustilago maydis–maize pathosystem has emerged as the current model for plant pathogenic basidiomycetes and as one of the few models for a true biotrophic interaction that persists throughout fungal development inside the host plant. This is based on the highly advanced genetic system for both the pathogen and its host, the ability to propagate U. maydis in axenic culture, and its unique capacity to induce prominent disease symptoms (tumors) on all aerial parts of maize within less than a week. The corn smut pathogen, though economically not threatening, will continue to serve as a model for related obligate biotrophic fungi such as the rusts, but also for closely related smut species that induce symptoms only in the flower organs of their hosts. In this review we describe the most prominent features of the U. maydis–maize pathosystem as well as genes and pathways most relevant to disease. We highlight recent developments that place this system at the forefront of understanding the function of secreted effectors in eukaryotic pathogens and describe the expected spin-offs for closely related species exploiting comparative genomics approaches.
Radiative Corrections for the LHC and Linear Collider Era
Authors: Laenen Eric , Wackeroth Doreen
Published: June 2009

We emphasize the importance of including radiative corrections when extracting physics from colliders such as the Tevatron Run II at Fermilab, the Large Hadron Collider (LHC) at CERN, and a future linear collider (LC). We review both well-tested methods and recent advances for calculating these corrections within the Standard Model of electroweak and strong interactions. We discuss the demands on theory and the prospects for matching or exceeding the anticipated experimental precision.
Specific attenuation of protein kinase phosphorylation in muscle with a high mitochondrial content
Authors: Ljubicic Vladimir , Hood David A.
Published: June 2009

Acute contractile activity increases the activation of protein kinases involved in signal transduction. We hypothesized that the contractile activity-induced kinase phosphorylation would occur to a lesser degree in muscle with elevated mitochondrial content. We compared red and white sections of tibialis anterior (TA) muscle with two- to threefold differences in mitochondrial volume, and we increased the mitochondrial content in the TA muscle by 40% with unilateral chronic stimulation-induced contractile activity (10 Hz, 7 days, 3 h/day). Both the chronically stimulated and the contralateral control muscles were then acutely stimulated in situ for 15 min (10 Hz). We investigated 1) the total protein content and 2) the phosphorylation of kinases important for mitochondrial biogenesis in skeletal muscle, including AMPKα and p44, p42, and p38 MAPKs, as well as Akt by immunoblotting. In response to chronic stimulation, a selective upregulation of kinase protein content was observed, suggesting unique transcriptional/translational processing for these enzymes. Inverse relationships were observed between mitochondrial volume and 1) kinase protein content and 2) basal levels of kinase phosphorylation. In general, the kinase phosphorylation response to acute exercise depended, in part, on the oxidative capacity of the fiber type, evidenced by a greater absolute level of acute contractile activity-induced kinase signaling in muscle with a lower mitochondrial volume. The attenuation of contraction-evoked kinase phosphorylation in muscle with high mitochondrial content suggests that these proteins may become less sensitive to upstream signaling and require greater stimulation for activation to propagate these adaptive cues downstream toward transcription or translation events.
Detection of EETs and HETE-generating cytochromeP-450 enzymes and the effects of their metabolites on myometrial and vascular function
Authors: Pearson Timothy , Warren Averil Y. , Barrett David A. , Khan Raheela N.
Published: June 2009

Cytochrome P-450 (CYP450) enzymes of the CYP2 and -4 family in humans metabolize arachidonic acid to generate bioactive epoxyeicosatrienenoic acids (EETs) and hydroxyeicosatetrenoic acids (HETEs). We report significantly higher levels of CYP 2J2 protein expression following the onset of labor ( n = 6, P < 0.05), implying increased EET-generating capacity within the uterus. Myometrial relaxation to 8,9-EET and 5,6-EET was observed, with the latter being inhibited by preincubation with 1 μM paxilline and is supported by whole cell recordings showing a modest effect of 5,6-EET on myometrial outward-current density ( n = 4, P < 0.05). Only 5,6-EET of the EETs tested affected vascular reactivity ( n = 6). Both 12- and 20-HETE ( n = 5–6) caused vasoconstriction of partially depolarized blood vessels, with glibenclamide ( n = 5) enhancing the effect of 12-HETE alone. Our findings signify a role for CYP2C9/19, -2J2, and -4A11/22 in late pregnancy, possibly related to the synthesis of lipid metabolites and downstream effects on vascular remodeling in the term pregnant uterus. The presence of CYP4A11/22 and their resultant procontractile metabolites could argue either a role in the control and initiation of labor and/or modification of the vascular delivery system to influence blood flow to the laboring uterus. The differential effects of the EETs and HETEs in the pregnant human uterus identify the CYP pathway as a novel modulator of myometrial and vascular physiology during late pregnancy.
Functional analyses reveal the greater potency of preadipocytes compared with adipocytes as endothelial cell activator under normoxia, hypoxia, and TNFα exposure
Authors: Mack Isabelle , BelAiba Rachida S. , Djordjevic Talija , Görlach Agnes , Hauner Hans , Bader Bernhard L.
Published: June 2009

Obesity is associated with a state of chronic low-grade inflammation. Immune cells accumulate in white adipose tissue (WAT). The vascular endothelium plays an interactive role in these infiltration and inflammatory processes. Mature and hypertrophic adipocytes are considered as the major adipogenic cell type secreting proinflammatory cytokines in WAT. In contrast, the proinflammatory capacity of preadipocytes and their role in endothelial cell activation have been neglected so far. To gain new insights into this molecular and cellular cross-talk, we examined the proinflammatory expression and secretion of normoxia, hypoxia, and TNFα-treated human preadipocytes and adipocytes (SGBS cells) and their impact on human microvascular endothelial cell (HMEC-1) function. In this study, stimulation of HMEC-1 with conditioned media (CM) from preadipocytes increased endothelial ICAM-1 expression and monocyte adhesion but not adipocyte-CM. After hypoxia and TNFα stimulation of SGBS cells, adipocyte-CM induced and preadipocyte-CM enhanced the monocyte adhesion. Concordantly, the expression of proinflammatory adipokines was considerably higher in preadipocytes than in adipocytes. SGBS-CM upregulated the phosphorylation of three MAPK pathways, STAT1/3, and c-Jun in HMEC-1, whereas the NF-κB pathway was not affected. Inhibitor experiments showed that monocyte/endothelial cell-cell adhesion and endothelial ICAM-1 expression was JNK and JAK-1/STAT1/3 pathway dependent and revealed IL-6 as a major mediator in CM increasing monocyte/endothelial cell-cell adhesion via the STAT1/3 pathway. Our study shows that preadipocytes rather than adipocytes operate as potent activators of endothelial cells. This can be enhanced in preadipocytes and induced in adipocytes by TNFα and hypoxia in a manner similar to what may occur in WAT in the etiology of obesity.
Early and Late Modulation of Saccade Deviations by Target Distractor Similarity
Authors: Mulckhuyse Manon , Van der Stigchel Stefan , Theeuwes Jan
Published: June 2009

In this study, we investigated the time course of oculomotor competition between bottom-up and top-down selection processes using saccade trajectory deviations as a dependent measure. We used a paradigm in which we manipulated saccade latency by offsetting the fixation point at different time points relative to target onset. In experiment 1, observers made a saccade to a filled colored circle while another irrelevant distractor circle was presented. The distractor was either similar (i.e., identical) or dissimilar to the target. Results showed that the strength of saccade deviation was modulated by target distractor similarity for short saccade latencies. To rule out the possibility that the similar distractor affected the saccade trajectory merely because it was identical to the target, the distractor in experiment 2 was a square shape of which only the color was similar or dissimilar to the target. The results showed that deviations for both short and long latencies were modulated by target distractor similarity. When saccade latencies were short, we found less saccade deviation away from a similar than from a dissimilar distractor. When saccade latencies were long, the opposite pattern was found: more saccade deviation away from a similar than from a dissimilar distractor. In contrast to previous findings, our study shows that task-relevant information can already influence the early processes of oculomotor control. We conclude that competition between saccadic goals is subject to two different processes with different time courses: one fast activating process signaling the saliency and task relevance of a location and one slower inhibitory process suppressing that location.
Common Fixed Point and Approximation Results for Noncommuting Maps on Locally Convex Spaces
Authors: Akbar F. , Khan A. R.
Published: June 2009

Common fixed point results for some new classes of nonlinear noncommuting maps on a locally convex space are proved. As applications, related invariant approximation results are obtained. Our work includes improvements and extension of several recent developments of the existing literature on common fixed points. We also provide illustrative examples to demonstrate the generality of our results over the known ones.
Convex Interval Games
Authors: Alparslan Gök S. Z. , Branzei R. , Tijs S.
Published: June 2009

Convex interval games are introduced and characterizations are given. Some economic situations leading to convex interval games are discussed. The Weber set and the Shapley value are defined for a suitable class of interval games and their relations with the interval core for convex interval games are established. The notion of population monotonic interval allocation scheme (pmias) in the interval setting is introduced and it is proved that each element of the Weber set of a convex interval game is extendable to such a pmias. A square operator is introduced which allows us to obtain interval solutions starting from the corresponding classical cooperative game theory solutions. It turns out that on the class of convex interval games the square Weber set coincides with the interval core.
Gene‐Based Multiclass Cancer Diagnosis with Class‐Selective Rejections
Authors: Jrad Nisrine , Grall-Maës Edith , Beauseroy Pierre
Published: June 2009

Supervised learning of microarray data is receiving much attention in recent years. Multiclass cancer diagnosis, based on selected gene profiles, are used as adjunct of clinical diagnosis. However, supervised diagnosis may hinder patient care, add expense or confound a result. To avoid this misleading, a multiclass cancer diagnosis with class‐selective rejection is proposed. It rejects some patients from one, some, or all classes in order to ensure a higher reliability while reducing time and expense costs. Moreover, this classifier takes into account asymmetric penalties dependant on each class and on each wrong or partially correct decision. It is based onν‐1‐SVM coupled with its regularization path and minimizes a general loss function defined in the class‐selective rejection scheme. The state of art multiclass algorithms can be considered as a particular case of the proposed algorithm where the number of decisions is given by the classes and the loss function is defined by the Bayesian risk. Two experiments are carried out in the Bayesian and the class selective rejection frameworks. Five genes selected datasets are used to assess the performance of the proposed method. Results are discussed and accuracies are compared with those computed by the Naive Bayes, Nearest Neighbor, Linear Perceptron, Multilayer Perceptron, and Support Vector Machines classifiers.
SyTroN: A Virtual Classroom for Collaborative and Distant E‐Learning System by Teleoperating Real Devices
Authors: Chellali R. , Dumas C. , Mollet Nicolas , Subileau G.
Published: June 2009

Distant E‐learning is a main issue nowadays, and it is strongly motivated by social and economical considerations. The increased people mobility and the reduction of educational costs push to develop ad hoc solutions enabling to access to knowledge regardless to geographical situation and economical capabilities. These parameters should not be limits for good training: learning material′s pertinence and efficiency have to remain the core of educational activities. In this paper we address the problem through SyTroN: a tele‐learning system. This system combines virtual reality and teleoperation techniques to offer an open platform with two main objectives. The first one is to propose intuitive virtual classrooms/desks, including a real teacher supervision and supporting collaborative and individual distant learning. The second goal is to place learners in real conditions with remote connections to real devices allowing distant experimentations. Both goals participate to increase learning impacts and to reduce costs, that is, sharing costly real devices from anywhere at any time. After 5 years of development, our work has been validated by an extensive use at a high engineering school. In situ tests and learning impact studies have been done. They show some advantages and some drawbacks of our global solution.
Developing Prognostic Systems of Cancer Patients by Ensemble Clustering
Authors: Chen Dechang , Xing Kai , Henson Donald , Sheng Li , Schwartz Arnold M. , Cheng Xiuzhen
Published: June 2009

Accurate prediction of survival rates of cancer patients is often key to stratify patients for prognosis and treatment. Survival prediction is often accomplished by the TNM system that involves only three factors: tumor extent, lymph node involvement, and metastasis. This prediction from the TNM has been limited, because other potential prognostic factors are not used in the system. Based on availability of large cancer datasets, it is possible to establish powerful prediction systems by using machine learning procedures and statistical methods. In this paper, we present an ensemble clustering‐based approach to develop prognostic systems of cancer patients. Our method starts with grouping combinations that are formed using levels of factors recorded in the data. The dissimilarity measure between combinations is obtained through a sequence of data
partitions produced by multiple use of PAM algorithm. This dissimilarity measure is then used with a hierarchical clustering method in order to find clusters of combinations. Prediction of survival is made simply by using the survival function derived from each cluster. Our approach admits multiple factors and provides a practical and useful tool in outcome prediction of cancer patients. A demonstration of use of the proposed method is given for lung cancer patients.
Mechanical Complication with Broviac Repair Kit in a 4-Year-Old Boy with MEN 2a
Authors: Sesia Sergio B. , Haecker Frank-Martin , Mayr Johannes
Published: June 2009

Background. Mechanical complications in the use of indwelling central venous catheters (CVCs) such as the Broviac catheter (BC) include kinking, occlusion, dislocation or leaking. We report on a mechanical complication after using a repair kit for the BC.Method. A 4-year old boy, suffering from multiple endocrine neoplasia type 2a (MEN 2a), intestinal aganglionosis (Hirschsprung's disease), and short bowel syndrome, required a BC for home parenteral nutrition.Result. Due to recurrent leakage of the BC, 5 subsequent repairs were necessary within seven months. During one repair a metallic tube belonging to the repair kit was found to have migrated proximally to the skin entrance level within the BC and requiring surgical removal.Conclusion. To our knowledge, this is the first report focusing on such a serious complication using a BC and its repair kit. The proximal migration of this metallic tube constitutes a distinct theoretical risk of endothoracic foreign body embolization.
Optimized Feature Extraction for Temperature‐Modulated Gas Sensors
Authors: Vergara Alexander , Martinelli Eugenio , Llobet Eduard , D′Amico Arnaldo , Di Natale Corrado
Published: June 2009

One of the most serious limitations to the practical utilization of solid‐state gas sensors is the drift of their signal. Even if drift is rooted in the chemical and physical processes occurring in the sensor, improved signal processing is generally considered as a methodology to increase sensors stability. Several studies evidenced the augmented stability of time variable signals elicited by the modulation of either the gas concentration or the operating temperature. Furthermore, when time‐variable signals are used, the extraction of features can be accomplished in shorter time with respect to the time necessary to calculate the usual features defined in steady‐state conditions. In this paper, we discuss the stability properties of distinct dynamic features using an array of metal oxide semiconductors gas sensors whose working temperature is modulated with optimized multisinusoidal signals. Experiments were aimed at measuring the dispersion of sensors features in repeated sequences of a limited number of experimental conditions. Results evidenced that the features extracted during the temperature modulation reduce the multidimensional data dispersion among repeated measurements. In particular, the Energy Signal Vector provided an almost constant classification rate along the time with respect to the temperature modulation.
Fuzzy Real Options in Brownfield Redevelopment Evaluation
Authors: Wang Qian , Hipel Keith W. , Kilgour D. Marc
Published: June 2009

Real options modeling, which extends the ability of option pricing models to evaluate real assets, can be used to evaluate risky projects because of its capacity to handle uncertainties. This research utilizes possibility theory to represent private risks of a project, which are not reflected in the market and hence are not fully evaluated by standard option pricing models. Using a transformation method, these private risks can be represented as fuzzy variables and then priced with a fuzzy real options model. This principle is demonstrated by valuing a brownfield redevelopment project using a prototype decision support system based on fuzzy real options. Because they generalize the original model and enable it to deal with additional uncertainties, fuzzy real options are entirely suitable for the evaluation of such projects.
Percutaneous Transhepatic Bile Duct Ablation with n-Butyl Cyanoacrylate in the Treatment of a Biliary Complication after Split Liver Transplantation
Authors: Lauterio Andrea , Slim Abdallah , Aseni Paolo , Giacomoni Alessandro , Di Sandro Stefano , Corso Rocco , Mangoni Iacopo , Mihaylov Plamen , Al Kofahi Mohammed , Pirotta Vincenzo , De Carlis Luciano
Published: June 2009

Biliary complications continue to be a major cause of morbidity after split-liver transplantation (SLT). In this report we describe an uncommon late biliary complication. One year after SLT the patient showed an intrahepatic bile dicy dilatation with severe cholangitis episodes. The segmentary bile duct of hepatic segment VI-VII draining in the left duct was unidentified and tied at the time of the in situ split-liver procedure. We perform a permanent obliteration of the dilated intrahepatic ducts by a percutaneous embolization using an n-butyl cyanoacrylate (NABC). The management of biliary complications after SLT requires a multidisciplinary approach. The use of NBCA in obliteration of a dilated bile duct seems to be a safe procedure with good results providing a less invasive option than hepatic resection and decreasing the morbidity associated with chronic external biliary drainage. Further studies are needed to determine whether this approach is effective and safe and whether it could reduce hospital stay and cost.
P2 Receptors in Neurological and Cardiovascular Disorders
Authors: Skaper Stephen D. , Debetto Patrizia , Giusti Pietro
Published: June 2009

P2X receptors are ATP-gated cation channels that mediate fast excitatory transmission in diverse regions of the brain and spinal cord. Several P2X receptor subtypes, including P2, have the unusual property of changing their ion selectivity during prolonged exposure to ATP, which results in a channel pore permeable to molecules as large as 900 daltons. The P2 receptor was originally described in cells of hematopoietic origin, and mediates the influx of and and and ions as well as the release of proinflammatory cytokines. P2 receptors may affect neuronal cell death through their ability to regulate the processing and release of interleukin-1, a key mediator in neurodegeneration, chronic inflammation, and chronic pain. Activation of P2, a key mediator in neurodegeneration, chronic inflammation, and chronic pain. Activation of P2 receptors provides an inflammatory stimulus, and P2 receptor-deficient mice have substantially attenuated inflammatory responses, including models of neuropathic and chronic inflammatory pain. Moreover, P2 receptor activity, by regulating the release of proinflammatory cytokines, may be involved in the pathophysiology of depression. Apoptotic cell death occurs in a number of vascular diseases, including atherosclerosis, restenosis, and hypertension, and may be linked to the release of ATP from endothelial cells, P2 receptor activation, proinflammatory cytokine production, and endothelial cell apoptosis. In this context, the P2 receptor may be viewed as a gateway of communication between the nervous, immune, and cardiovascular systems.