bluuebunny/crossref_metadata_2025 huggingface dataset:
Collapse Mechanisms for High Aspect Ratio Structures with Application to Clean Processing
Authors: Peter Daniel , Holsteyns Frank , Dalmer Michael , Kruwinus Hans , Lechner Alfred , Bensch Wolfgang
Published: September 2009

The fabrication of semiconductor devices includes the generation of high aspect ratio structures which are prone to lateral mechanical forces. Therefore, the mechanical stability of polysilicon line structures has been tested by an AFM technique for several line widths. Additionally, the damage has been evaluated and shows a uniform size distribution. These experimental results have been compared to numerical models, in which the influence of specific geometries and material present in the stack has been studied. A stress concentration region at the bottom of the line was observed and could be removed by corner rounding (fillet). Besides, the maximum stress is shifted away from the substrate. The experimental damage showed a stump at the bottom of the damage, thus confirming the numerical results.
Water and Bubble Motions Under Megasonic Wave in a Silicon Wafer Wet Cleaning Bath
Authors: Habuka Hitoshi , Okada Yuta , Fukumoto Ryohei , Yoshii Hirofumi , Kato Masayuki
Published: September 2009

The influences of a megasonic wave on water and bubble motions in a wet cleaning bath used for 300 mm-diameter silicon wafers were studied. The water motion in the entire bath was observed using a tracer of water-soluble blue-colored ink. The megasonic wave accelerated the water motion in the entire bath, although the water motion under no megasonic wave tended to be localized. The motion of small bubbles generated by the megasonic wave was also traced over the entire wafer surface. The bubble transport rate was shown to be increased by the megasonic wave and water flow.
Development of a Single-beam Megasonic System for Nano-particle Cleaning
Authors: Kim Hyunse , Lee Yanglae , Lim Euisu
Published: September 2009

A single-beam megasonic system for nano-particle cleaning which does not cause nano-scale pattern damage was designed. Considering ultrasonic wave propagation, a length of quartz waveguide was decided at a uniform acoustic wave region. The anti-resonance frequency of the piezoelectric actuator was measured to be 987 kHz, which agreed well with the fabricated quartz waveguide operating frequency of 983 kHz. The acoustic pressure of the single-beam megasonic system was measured, and the averaged value increased by 89% compared with a commercially available product (named an A-type). To compare uniformity, standard deviations of acoustic pressure values were calculated, and they were lower than A-type results by 20%. In addition, particle removal efficiency (PRE) tests were performed, and 91% of particles were removed after megasonic cleaning. These results explain our system's performance improvement in PRE and reduction in nano-pattern damage.
Impact of Acoustical Reflections on Megasonic Cleaning Performance
Authors: Brems Steven , Hauptmann Marc , Camerotto Elisabeth , Pacco Antoine , Halder Sandip , Zijlstra Aaldert , Doumen Geert , Bearda Twan , Mertens Paul
Published: September 2009

Electrical measurements have shown a direct impact of reflection of acoustic waves back into a transducer. Impedance measurements illustrate in specific cases the existence of multiple resonance peaks when reflected acoustic waves are present. Current and voltage measurements have confirmed this result. From these results, one can already conclude that acoustic reflections have a large impact on the operation of a transducer. Furthermore, it is shown that for megasonic cleaning tools with a face-to-face configuration of transducer and wafer, a precise control over the distance (control over the reflections) between the transducer and wafer is very important. Particle Removal Efficiency (PRE) measurements immediately show a major dependence on the position of the wafer. The PRE dependence is directly linked to the forward power consumed by the transducer, which is largely influenced by the position of the wafer or, in other words, by the reflection of acoustic waves.
Megasonic Metrology for Enhanced Process Development
Authors: Kumari Sangita , Keswani Manish , Beck Mark , Liebscher Eric , Liang Ted , Deymier Pierre , Raghavan Srini
Published: September 2009

Acoustic cavitation is known to be a primary source of both cleaning and damage of wafers during their megasonic processing. Understanding the response of process fluids to variables like acoustic power recipe and dissolved gases is an important first step in achieving damage-free megasonic cleaning of wafers. This paper reports the development of a portable, UV light tight, cavitation threshold (CT) cell to measure sonoluminescence (SL) signal arising from cavitation. The closed cell, integrated with a gas sensor and contactor, allows SL measurements under very controlled conditions. Using the CT cell the effect of the concentration of dissolved O2, CO2 and air on SL signal has been investigated. Results show that SL varies linearly with dissolved O2 concentration while CO2 is found to be incapable of supporting SL. This study also demonstrates a novel method for precise control of SL through addition of an O2 scavenger with fast O2 removal kinetics.
Cleaning and Damage Performance of Single Wafer Cleaning Tools using Physical Removal Forces
Authors: Pacco Antoine , Halder Sandip , Kenis Karine , Bearda Twan , Mertens Paul
Published: September 2009

The aim of this study was to evaluate the trade off between damage generation and particle removal of single wafer cleaning tools that apply a physical force. We looked at 30 nm silica removal and damage of ~ 20 nm wide amorphous-Si lines caused by aerosol spray cleaning or acoustic cleaning. A detailed calculation of local particle removal rates and local damage fluxes gives important information about cleaning (non-) uniformities. Average removal rates and average damage fluxes values were also obtained and give valuable about the cleaning versus damage trade-off.
Ruthenium Wet Etch on 200mm MEMS Wafers with Sodium Hypochlorite
Authors: Segaud Roselyne , Gabette Laurence , Louveau Olivier , Besson P.
Published: September 2009

Ruthenium is promoted as one of the most efficient metallization contact material in MEMS technology. In a good agreement with MEMS technology requirement, a cost friendly chemical mixture based on sodium hypochlorite is proposed hereafter to achieve a robust and reliable ruthenium wet etching process through a resist mask in a 200mm single wafer spray tool.
Cleaning-Free Deposition of Highly Crystallized Si Films on Plastic Film Substrates Using Pulsed-Plasma CVD under Near-Atmospheric Pressure
Authors: Matsumoto Mitsutaka , Ito Syun , Inayoshi Yohei , Murashige Shogo , Fukidome Hirokazu , Suemitsu Maki , Nakajima Setsuo , Uehara Tsuyoshi , Toyosihima Yasutake
Published: September 2009

By employing a pulsed-discharge, near-atmospheric-pressure plasma-enhanced chemical vapor deposition, equally qualified pair of poly-Si films are grown on polyethylene terephthalate (PET) substrates placed at both the grounded and the powered electrodes. This finding leads to a roll-to-roll-type deposition system of cleaning-free operation for film growth.
Etching of Sacrificial CVD Silicon Dioxides with Anhydrous HF Vapor
Authors: Ritala Heini , Kiihamäki Jyrki
Published: September 2009

Anhydrous HF vapor etching of sacrificial silicon dioxide thin films grown by plasma enhanced and low pressure chemical vapor deposition (PECVD and LPCVD) methods was studied. Film compositions as well as etch residue were analyzed. Effects of oxide deposition method, precursors, annealing and oxide composition on etch rate are discussed.
Quantitative Analysis of Transition Metals Penetrating the Silicon Substrate by Dopant Ion Implantation
Authors: Saga Koichiro , Ueno Keiji , Ohno Rikiichi
Published: September 2009

The behavior of metals penetrating the silicon substrate by the collision of dopant ion and surface metals are quantitatively demonstrated. We have found using silicon step etching followed by ICP-MS and SIMS that several percent of surface metals penetrate silicon and are present at a little shallower region than the depth of the highest dopant concentration after ion implantation. The depth of metals penetrating the silicon substrate during dopant ion implantation and subsequent annealing is found to depend on metal species. We have also found using recombination lifetime and Si photoluminescence measurements that carrier traps are generated in silicon by metal penetration even when implanted through SiO2.
Integration Challenges and Opportunities of Nanoelectronic Devices
Authors: Nishi Yoshio
Published: September 2009

It is critically important for us to carefully assess potential of individual new materials/devices and technologies with respect to integration capability, and also cost point of view. This talk will review progress made in high mobility channel for high performance devices, new nonvolatile memory and possible integration of optical interconnect toward 3 D integration and discuss which set of criteria would be necessary for the future screening of novel materials and devices.
Bio Inspired Architectures in the Nanoscale Integration Era
Authors: Shibata Tadashi
Published: September 2009

With the advent of the nanoscale integration era, we will be able to build super-high performance CPU chips with more than 1010 transistors on single chips. The number is equivalent to the total number of neurons in the neocortex of the human brain. However, is it really possible to build systems as intelligent as humans? Digital computers today have enormous computational powers and will have more in the future. However, they are not very smart in such tasks like naïve perception, intuitive understanding, and flexible decision making. Such functionalities are in great demand to establish seamless interfacing between the human society and the cyber world. In this paper we will discuss what we can learn from biology of its computing principles and how we can implement them in the VLSI hardware by best utilizing the sate-of-the-art ULSI integration technology.
A Roadmap for Nano-CMOS
Authors: Iwai Hiroshi
Published: September 2009

Logic CMOS technology roadmap for '22 nm and beyond' is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length.
Multi-gate Devices for High Performance, Ultra Low Power and Memory Applications
Authors: Balestra Francis
Published: September 2009

Multi-gate devices seem to be the best candidates for the ultimate integration of ICs on silicon. The comparison of the electrical properties on these innovative architectures with nanoscale single-gate and bulk transistors is shown. The impact of alternative channel materials, using strained Si, Ge or III-V layers on insulator, on the performance and physical mechanisms in multi-gate MOSFETs is addressed. The interest of multi-gate emerging and beyond-CMOS nanodevices for long term applications, based on nanowires or small slope switch structure for ultra power applications, is presented. The possible 3D integration of multi-channels and stacked nanowires is also investigated for the end of the roadmap. Finally, the flexibility of multi-gate SOI structures for boosting the scalability and performance of DRAM, SRAM and flash memories is outlined.
Very High Performance CMOS on Si(551) Surface using Radical Oxidation Silicon Flattening Technology and Accumulation-mode SOI Device Structure
Authors: Cheng Weitao , Teramoto Akinobu , Ohmi Tadahiro
Published: September 2009

In this study, we focus on the good surface flattening characteristics of Si(551) surface using the repeated radical oxidation technology. We demonstrate that the electrical characteristics of the MOSFETs on Si(551) have been obviously improved by introducing the Accumulation-mode device structure. Finally, a very high performance CMOS has been successfully realized on Si(551) surface by combining the radical oxidation silicon flattening technology and Accumulation-mode device structure.
Variability Headaches in Sub-32 nm CMOS
Authors: Asenov Asen
Published: September 2009

In this paper we study the statistical variability in future CMOS technology generations using 3D statistical simulations carried out with the Glasgow 'atomistic' device simulator. The results of the statistical simulations are validated in comparison with measurements of 45 nm technology generation LP MOSFETs. Predictive simulations about the increased magnitude of the statistical variability with scaling in bulk MOSFETs are presented and compared with results for fully depleted ultra thin body (UTB) SOI MOSFETs are presented. The major trends are analyzed and discussed.
Low-Power SiGe HBT and Circuit Technology for Future Quasi-Millimeter-Wave Wireless Communications
Authors: Washio Katsuyoshi , Shiramizu Nobuhiro , Miura Makoto , Nakamura Takahiro , Oda Katsuya , Masuda Toru
Published: September 2009

SiGe HBTs and their circuit technologies are suitable for future wireless communications. To achieve low 1/f-noise characteristics in RF applications, a SiGe HBT with a raised-emitter structure, fabricated by epitaxial growth of phosphorous-doped Si layers, was developed. Aimed at ultra-low power consumption in a wide range of microwave applications, a SiGe HBT fabricated by well-controlled SiGe/Si continuous epitaxial growth was developed. To improve the design process for Si-based RF-ICs, equivalent circuits for transmission lines under the slow-wave effect and for inductors under the peripheral ground effect were also demonstrated. Moreover, MMICs operating in the quasi-millimeter-wave region, namely, two 24-GHz LNAs, a 27-GHz VCO, and a 24-GHz mixer were developed. In regards to these MMICs, new circuit technologies, namely, inductive biasing, merged transformer matching, and pseudo-stacked configuration, were developed.
Advanced Charge Storage Memories: From Silicon Nanocrystals to Molecular Devices
Authors: De Salvo Barbara , Molas G. , Perniola L. , Jahan C. , Buckley J. , Jalaguier E. , Gely M.
Published: September 2009

In this paper, we will make a general overview of different technological approaches suitable for charge storage memories. Several solutions to extend the floating gate Flash memory technology to the 22nm nodes and beyond, are presented. In particular, new modules (discrete traps memories, and more specifically silicon nanocrystal memories), new materials (as high-k materials for the interpoly layer) and innovative architectures (as FinFlash memories) are discussed. Moreover, hybrid approaches which make use of organic molecules as storage sites will be also introduced. Finally, the main theoretical limits of ultra-scaled charge storage memories (i.e. reliability issues linked to few electron phenomena) will be analyzed, opening the path to the introduction of disruptive technologies based on new storage mechanisms (as Phase-Change Memories and Oxide resistive RAMs).
Novel Omega-Shaped-Gated TFT SONOS Memory
Authors: Liao Ta-Chuan , Chen Sheng-Kai , Kang Tsung-Kuei , Hsu Pang-Yu , Lin Chia-Min , Cheng Huang-Chung
Published: September 2009

A novel omega-shaped-gated polycrystalline-silicon thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had twin sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the Ω-Gate SONOS as compared to the conventional planar (CP) counterpart. Such an Ω-Gate-TFT SONOS memory using simple process is very suitable for future system-on-panel applications.
Overwhelming the 0.5 nm EOT Level for CMOS Gate Dielectric
Authors: Kakushima Kuniyuki , Ahmet Parhat , Iwai Hiroshi
Published: September 2009

MOSFET with EOT below 0.37 nm has been achieved with La2O3 gate dielectric by realizing direct contact on Si. A sufficient increase in drain current has been observed while scaling the EOT from 0.48 to 0.37 nm. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance. Moreover, the EOT increment by La- silicate formation after high temperature annealing can be well suppressed under control of oxygen by selecting a metal gate.
On the Low-frequency Noise Performance of Embedded Si:C nMOSFETs
Authors: Claeys C. , Simoen Eddy R. , Verheyen Peter , Loo Roger , Machkaoutsan V. , Bauer Matthias , Thomas Shawn
Published: September 2009

A study is made of the impact of embedded epitaxial Si:C source/drain regions on the DC and low-frequency (LF) noise characteristics of nMOSFETs with 1.4 nitrided oxide gate dielectric. It is shown that a ~10% improvement in ION is achieved for a C concentration of 1%, with not much further improvement going to 1.5%. At the same time, no change of the 1/f noise is observed, indicating that the gate stack integrity is preserved throughout the Selective Epitaxial Growth process.
SiGe SEG Growth for Buried Channels p-MOS Devices
Authors: Hikavyy Andriy , Loo Roger , Witters Liesbeth , Takeoka Shinji , Geypen Jef , Brijs Bert , Merckling Clement , Caymax Matty , Dekoster Johan
Published: September 2009

Different selective epitaxial growth processes to deposit buried SiGe channels with Ge contents in the range of 25-55% and with an ultra thin Si capping layer have been successfully developed and implemented in pMOS device flows. Relatively low deposition temperatures assure the absence of SiGe islands and enable high quality strained SiGe layers. The required low growth temperature governed the choice of precursors used. In this contribution we review in detail the developed SiGe processes together with the deposition of the ultra thin Si cap layer. Electrical data obtained on the devices with incorporated Si0.75Ge0.25 and Si0.55Ge0.45 buried channels are presented as well.
Silicon: Carbon Source/Drain Stressors: Integration of a Novel Nickel Aluminide-Silicide and Post-Solid-Phase-Epitaxy Anneal for Reduced Schottky-Barrier and Leakage
Authors: Koh Shao Ming , Zhou Wei-Jing , Lee Rinus T. P. , Sinha Mantavya , Ng Chee-Mang , Zhao Zhiyong , Maynard Helen , Variam Naushad , Erokhin Yuri , Samudra Ganesh , Yeo Yee-Chia
Published: September 2009

We report two distinct approaches to reduce leakage and parasitic resistance in Silicon:Carbon (Si:C) region. First, the effectiveness of a low-thermal budget post-Solid-Phase-Epitaxy (post-SPE) anneal in the suppression of leakages is examined. Second, we have developed a novel nickel-aluminide silicide (NiAlSi:C) with dopant-segregation (DS) technology to reduce the Schottky-Barrier height (SBH) for Si:C contacts. An optimum 18% substitutional incorporation of Al in the silicide matrix leads to a 10% reduction in the intrinsic SBH of NiSi:C. A low electron schottky barrier of 0.118 eV was attained with NiAlSi:C contacts on phosphorous-segregated regions. The results on Si:C establish a technique to achieve low leakage, low SBH for low contact resistance and low sheet resistance for Si:C S/D application.
Stress Characterization of Selective Epitaxial Si1-xGex Deposition for Embedded Source/Drain Before and After Millisecond Laser Anneal
Authors: Bargallo Gonzalez Mireia , Fernandez-Lanas Tatiana , Rosseel Erik , Hikavyy Andriy , Dekkers Harold , Eneman Geert , Verheyen Peter , Loo Roger , Simoen Eddy R. , Claeys C.
Published: September 2009

The purpose of this paper is to obtain a deep understanding of stress/bow behavior before and after millisecond laser anneal for epitaxially grown Si1­xGex layers. Stress measurements were performed by the laser reflectance method after different post-epi processing steps to further investigate the intrinsic film stress dependence on the ion implantation conditions (atom size, depth of the implant and dose) and the laser scan energy beam conditions (temperature, dwell time and power).
Atomically Controlled Plasma Processing for Epitaxial Growth of Group IV Semiconductor Nanostructures
Authors: Sakuraba Masao , Sugawara Katsutoshi , Murota Junichi
Published: September 2009

Plasma enhanced chemical vapor deposition (CVD) is useful to improve surface flatness and abruptness of doping profile and heterointerface by lowering epitaxial growth temperature for group IV semiconductors. By N and B atomic-layer formation and subsequent Si epitaxial growth on Si(100) without substrate heating, heavy atomic-layer doping has been demonstrated by using electron cyclotron resonance (ECR) plasma enhanced CVD. Most of the incorporated N or B atom amount of about 7x10^14 cm^-2 in the atomic-layer doped Si film is confined within an about 2 nm-thick region. Moreover, using a 84 % relaxed Ge buffer layer formed on Si(100) by ECR plasma enhanced CVD, it is found that the hole mobility is enhanced by introduction of strain to nanometer order thick Si film, and the mobility enhancement as high as about 3 is observed.
Low-frequency Noise Analysis of the Impact of an LaO Cap Layer in HfSiON/Ta2C Gate Stack nMOSFETs
Authors: Simoen Eddy R. , Akheyar Amal , Rohr Erika , Mercha Abdelkarim , Claeys C.
Published: September 2009

In this work, n-channel MOSFETs with a 0.5 nm LaO cap layer inserted between the 10 nm Ta2C metal gate and the HfSiON gate dielectric have been investigated, with emphasis on the low-frequency noise properties. It is shown that the capped devices show a roughly 0.3 V lowering of the threshold voltage and a significant increase in the maximum transconductance and the low-field mobility. At the same time, it is shown that the 1/f noise spectral density SI is not degraded by the introduction of the cap layer and even a lowering of the noise magnitude for thinner HfSiON layers has been observed. This points to a reduction of the effective gate oxide trap density which could result from the in-diffusion of La in the underlying gate stack.
Fast Detrapping Transients in High-K Dielectric Films
Authors: Rao Rosario , Irrera Fernanda
Published: September 2009

Charge trapping and detrapping are mechanisms which substantially modify dynamically the electric features of high-k dielectrics and cause instability of the MOS flat band voltage. The timescale on which such phenomena take place depends on the space and energy distribution of traps and in high-k dielectrics it may span on a very wide interval. On the other hand, conventional electrical measurements operating in stationary conditions take several seconds, thus affecting the measurement result and inhibiting from monitoring charge transients at shorter times. In this work, we present a detailed investigation of flat band transients due to charge detrapping in Al2O3 films designed for nonvolatile applications, on a timescale spanning from hundreds of microseconds to ten minutes. For this purpose, a technique based on the pulsed C-V measurement has been used. The flat band voltage instability due to charge detrapping has been studied systematically.
Charge Trapping Non Volatile Memory
Authors: Lorenzi Paolo , Rao Rosario , Ghidini Gabriella , Palma Fabrizio , Irrera Fernanda
Published: September 2009

The memory market is currently being evolving towards innovative device concepts which include the use of new materials and/or new structures. In this scenario, charge trapping represents one the most promising revolutionary concept in the frame of nonvolatile memory. Charge trapping-based devices feature quantum wells instead of metallic floating gate for the charge storage and include high-k dielectric films in the blocking layer. All those innovations allow for aggressive memory integration and a reduction of power consumption, preserving reliability at the same time. In this contribution, we present a systematic study of state-of-art TANOS-like Flash memory device in which the storage nodes are localized electronic states in Si3N4, whereas the blocking dielectric is Al2O3.
Advanced Contact Technology for MOSFETs: Integration of New Materials for Series Resistance Reduction
Authors: Yeo Yee-Chia , Lee Rinus T. P.
Published: September 2009

In this paper, new technology solutions for reducing contact resistance to enhance MOSFET drive current performance are discussed. We focus on several new approaches pioneered by our group for reducing electron and hole heights between the heavily-doped diffusion region and the silicide layer in n-FET and p-FET, respectively. Integration of these approaches in advanced device architectures would contribute to realization of high-performance CMOS devices.
Electrochemical processes for the production of copper interconnects on non-metallic barrier layers
Authors: Duquette David J.
Published: September 2009

This study reports the results of two process routes to eliminate the line-of-site limitations of depositing PVD copper seed layers for subsequent ECD copper deposition on nitride barrier layers. Direct deposition of adherent, low resistivity copper, directly on TaN, has been achieved using a serial electrolytic bath process. The technique uses anodic dissolution of air-formed tantalum oxides in a strong caustic bath, followed by wet transfer of wafer samples to a complexing plating bath for ECD. Highly adherent, unusually flat copper films can be produced. A second process route involves the conformal deposition of an ultra-thin plateable metallic adhesion layer on air exposed nitride surfaces, using ALD. Successful depositon of high conductivity adherent copper layers on blanket and patterned wafer surfaces has been demonstrated using Pd as a model adhesion layer.
Metal CMP Optimization Based on Chemically Formed Thin Film Analysis
Authors: Basim Gul B.
Published: September 2009

The conventional demands for development in semiconductor industry are changing as the Moore's Law is approaching to its limits. This paper demonstrates a theoretical optimization approach for the planarization of metal films by Chemical Mechanical Polishing (CMP) process. Optimal removal rate and a smooth surface finish post CMP can be achieved by the combined effect of the chemical and mechanical components of the process. Metal CMP necessitates a protective oxide film formation in the presence of surface active agents, corrosives, pH regulators etc' to achieve global planarization. Formation and mechanical properties of the chemically modified films determine the stresses develop in the film structure delineating the stability of the chemically altered films on the surface of the metal wafer. The balance between the stresses built in the film structure versus the mechanical actions provided during the process can be used to optimize the process variables and furthermore help define new planarization techniques for the next generation microelectronic device manufacturing which is expected to deal with atomic level structures.
Epitaxial Ge on Standard STI Patterned Si Wafers: High Quality Virtual Substrates for Ge pMOS and III/V nMOS
Authors: Loo Roger , Wang Gang , Souriau Laurent , Lin J.C. , Takeuchi Shotaro , Brammertz Guy , Caymax Matty
Published: September 2009

Further improving CMOS performance beyond the 22 nm generation likely requires the use of high mobility channel materials. Complementary integration of different materials on Si can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates on standard Si STI wafers. This reduces the fabrication cost of these virtual substrates as it omits the complicated isolation scheme in blanket Ge. The low topography enables integration of ultra thin high-K gate dielectrics. The fabrication schemes are compatible with uni-axial stress techniques. Both modules include an anneal at 850 {degree sign}C to reduce the threading dislocation density down to 4x108 cm-2 and 1x107 cm-2, respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter one will be illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.
Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration
Authors: Augendre Emmanuel , Sanchez Loïc , Benaissa Lamine , Signamarcheix Thomas , Hartmann Jean-Michel , Le Royer Cyrille , Vinet Maud , Van Den Daele William , Damlencourt Jean-François , Romanjek Krunoslav , Pouydebasque Arnaud , Batude Perrine , Tabone Claude , Mazen Frédéric , Tauzin Aurélie , Blanc Nicolas , Pellat Michel , Dechamp Jérôme , Zussy Marc , Scheiblin Pascal , Jaud Marie-Anne , Drazek Charlotte , Maurois Cécile , Piccin Matteo , Abbadie Alexandra , Lallement Fabrice , Daval Nicolas , Guiot Eric , Rigny Arnaud , Ghyselen Bruno , Bourdelle Konstantin , Boulanger Fabien , Cristoloveanu Sorin , Billon Thierry , Faynot Olivier , Deguet Chrystel , Clavelier Laurent
Published: September 2009

The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.
Pt/Ge Schottky-Barrier Reduction by Rapid Thermal Diffusion of P Dopants
Authors: Henkel Christoph , Abermann Stephan , Bethge Ole , Bertagnolli Emmerich
Published: September 2009

Low platinum-germanide-Schottky barrier diodes are fabricated via the incorporation of dopants by diffusion. A phosphorous spin-on-dopant resist is used for the formation of a highly doped surface layer in a rapid thermal annealing process, prior to the formation of platinum-germanide Schottky barrier diodes. For rapid diffusion processes above 580 {degree sign}C ohmic contact behavior is found while evidence is given for a lowered effective Schottky-barrier height.
Development of III-V MOSFET Process Modules Compatible with Silicon ULSI Manufacture
Authors: Thayne Iain , Li Xu , Jansen Wout , Ignatova Oleysa , Bentley Stephen , Zhou Haiping , Macintyre Douglas , Thoms Stephen , Hill Richard
Published: September 2009

To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) [1] to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. For ultimate CMOS exploitation, self-aligned III-V MOSFETs with sub-20 nm critical dimensions will have to be realized using silicon compatible process flows. This paper reviews the current status of III-V MOSFET research from the perspective of silicon ULSI process compatibility.
High Performance InGaAs MOSFETs with High Mobility using InP Barrier Layer
Authors: Zhao Han , Chen Yen-Ting , Yum Jung Hwan , Wang Yan Zhen , Xue Fei , Zhou Fei , Lee Jack
Published: September 2009

We have fabricated In0.7Ga0.3As and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) with and without InP barrier layer using atomic layer deposited (ALD) Al2O3 gate oxide directly on III-V substrates. InP is an excellent barrier and passivation layer to enhance current driving capability for these devices, especially for In0.7Ga0.3As MOSFETs due to good conduction band offsets. In0.7Ga0.3As MOSFETs with InP barrier layer show much higher transconductance and lower subthreshold swing than other MOSFETs in our study, and exhibit high drive current of 98 mA/mm (L=20 um), subthreshold swing of 106 mV/dec and maximum effective channel mobility of 4402 cm2/Vs, which is amongst the highest reported in the literature.
Quasiballistic Transport of Charge Carriers in Nanometer FETs in the Model of Heterogeneous Channel
Authors: Popov Vladimir P.
Published: September 2009

In most recent works dealing with the mobility in short channel transistors even an account of unwanted serial resistance near the source and drain were unable to explain why reducing effective mobility μeff defined from experimental I-V curves happens at the reduction in the channel length in decananometer range. Reduced mobility in nanometer transistors is a reliably established experimental fact, which contradicts to the basic Moore Law (1), requiring increased channel conductivity with the transition to each subsequent ULSI generation. Reasons for the reduced mobility in nanometer channels are analyzed in this report by the model of the heterogeneous channel proposed by us earlier and extended to the model of quasiballistic transport of charged carriers.
Emerging Non-Volatile Memories by Exploiting Redox Reactions on the Nanoscale
Authors: Waser Rainer
Published: September 2009

This review provides a survey of non-volatile, highly scalable memory devices which are based on redox phenomena controlling the resistance of nanoscale memory cells. The classification of the memory effects, the understanding of the underlying mechanisms, and a brief sketch of the integration efforts will be presented.
Tunnel Field-Effect Transistors for Future Low-Power Nano-Electronics
Authors: Verhulst Anne S. , Vandenberghe William G. , Leonelli Daniele , Rooyackers Rita , Vandooren Anne , De Gendt Stefan , Heyns Marc M. , Groeseneken Guido
Published: September 2009

Tunnel-FETs (TFETs) have the potential for a subthreshold swing below 60 mV/dec such that supply voltage scaling beyond the 1 V plateau of metal-oxide-semiconductor FETs (MOSFETs) is possible. The latter scaling is a necessary condition for a reduction of the power consumption per transistor. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon results in low on-currents. Therefore, the incorporation of heterostructures is proposed. In particular, a germanium-source silicon-channel n-TFET and, as complementary p-TFET, an indium(gallium)arsenide-source silicon-channel TFET reach on-currents comparable to MOSFETs. TFETs offer new opportunities, like the short-gate configuration, due to their different operating principle. At the same time, the latter implies that models need to be newly developed. The agreement of models with experimental data is still qualitative only.
3D Suspended Nanowires Integration for CMOS and Beyond
Authors: Ernst Thomas , Tachi Kiichi , Hubert Alexandre , Saracco Emeline , Dupré Cécilia , Bécu Stéphane , Vulliet Nathalie , Bernard Emilie , Cherns Peter , Maffini-Alvaro Virginie , Damlencourt Jean-François , Vizioz Christian , Colonna Jean-Philippe , Bonafos Caroline , Hartmann Jean-Michel
Published: September 2009

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations associated to such devices integration as well as their potential applications.
Physics of Nano-Interfaces and Nano-Structures for Future Si Nano-Devices
Authors: Shiraishi Kenji
Published: September 2009

Due to the aggressive scaling of semiconductor devices, present semiconductor devices contain various kinds of nano-scale interfaces and nano-structures. In this paper, we show two examples in which physics can really give guiding principles for future semiconductor technologies. First, we discuss physics for future Si nanowire FET. When one-dimensional ballistic conduction is achieved, the hole conductivity of a Si nanowire FET is basically determined by the number of hole quantum channels near the valence band maximum (VBM). However, as the density of bands increase, the spacing of each band becomes narrower, which will allow inter sub-band scattering and eventually reduces the conductivity. In the light of the above discussions, it may be concluded that there exists a trade-off between the quantum channel numbers and inter subband scattering and an optimum size exists for Si nanowire FET applications. Moreover, we also discuss our new interface physics which is crucial for controlling threshold voltages in high-k gate stacks.
Electrothermal Transport in Carbon Nanostructures
Authors: Yamada Toshishige , Saito Tsutomu , Fabris Drazen , Wilhite Patrick , Yang Cary Y.
Published: September 2009

An empirical model is developed that takes into account heat transport through the entire carbon nanofiber interconnect test structure and breakdown location. This electrothermal transport model elucidates observed current capacity behavior, and predicts variations in contact location with the support material. The resulting heat dissipation and current capacity are completely consistent with measurement data.
Systhesis and Devices of Graphene
Authors: Zhu Jing , Liu Wei , Wang Yanjie , Huang Bo-Chao , Xie Ya-Hong , Woo Jason
Published: September 2009

Graphene is of great interest of being a channel material in MOSFETs because of its ultra high mobility and large carrier densities. In this paper, several synthesis methods of graphene are introduced and Graphene channel FETs (Gra-FETs) are fabricated. Heavily doped n-type or p-type PolySi is adopted as source and drain to form Schottky tunneling junctions with graphene and successfully suppresses the ambipolar conduction which is caused by graphene's intrinsic properties. The total drain current is dominated by either electron or hole tunneling current and thus showing a unipolar relationship with VG. We demonstrated the Gra-FETs with Schottky tunneling source and drain and proved experimentally that these devices would have only one kind of carriers to conduct current and thus the ambipolar conduction is suppressed.
Novel Materials and Integration Schemes for CMOS-Based Circuits for Flexible Electronics
Authors: Quevedo Manuel , Gowrisanker S. , Allee D , Venugopal S , Krishna R , Kaftanoglu K , Alshareef H.N. , Gnade B. E.
Published: September 2009

The development of low temperature, thin film transistor processes that has enabled flexible displays also presents opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible, low metal content, sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, neutron/gamma-ray/x-ray detectors, etc. In this paper, we review the state-of-the-art in flexible electronics materials and devices and present recent results in our efforts to fully integrate complementary metal oxide semiconductors. We conclude with a discussion of the constraints of thin film transistors and the remaining challenges.
Influence of Phosphorus Concentrations in a-SiN:H Gate Layer on Electron Mobility in Thin Film Transistors
Authors: Kim Jun Woo , Sohn Young-Soo , Choi Sie-Young
Published: September 2009

Characteristics of a-Si:H TFTs with various phosphorus doping concentration in a-SiN:H layer has been investigated.
New Modes of Fast Fourier Impedance Spectroscopy Applied to Solar Materials Characterization and Semiconductor Pore Etching
Authors: Carstensen Juergen , Foell Helmut
Published: September 2009

Impedance spectroscopy (IS) essentially measures the current or voltage response of a complex system to small perturbations of the applied voltage or current, respectively. Multi-mode FFT IS as in-troduced here includes responses to (possibly local) perturbations of light coupled to photo-electrical semiconductor devices such as solar cells or (photo) electrochemical cells, and allows quick measurements by employing a FFT technique (1 s per spectrum) and thus in-situ data acquisition. In conjunction with device mod-els many parameters can be assessed simultaneously, quickly, and with high spatial and/or temporal resolution. Examples given in-clude electrochemical pore etching in Si where so far inaccessible parameters like the process valence or the pore depth are recorded in-situ, and simultaneous mapping of more than 8 solar cell pa-rameters such as life time, doping, surface recombination velocity, series resistance, or reflectivity.
Detection of Vacancy Distributions by Decoration with Hydrogen
Authors: Job Reinhart , Niedernostheide Franz-Josef , Schulze Hans-Joachim , Schulze Holger
Published: September 2009

A well-known method for the determination of vacancy distributions in silicon is based on the decoration of vacancies with in-diffused platinum and subsequent profiling of the Pt-distribution with DLTS analysis. The vacancy profile can then be correlated with the substitutional Pt profile. However, there are significant drawbacks of this method: The in-diffusion of platinum is a high-temperature step, which already can alter the vacancy profile; moreover, DLTS measurements with a suitable depth resolution are time-consuming and difficult. Therefore, it is proposed in this paper to decorate the vacancies with hydrogen by processes finally resulting in the formation of vacancy- and hydrogen-related donor and acceptor states. The determination of such doping profiles and by this the detection of vacancy distributions can be easily enabled by depth-resolved spreading resistance measurements with a very good spatial resolution. Hydrogen atoms for the decoration of vacancies can be incorporated by plasma exposure or ion implantation.
Probing the Behaviors of Point Defects in Silicon and Germanium Using Isotope Superlattices
Authors: Uematsu Masashi , Naganawa Miki , Shimizu Yasuo , Itoh Kohei M. , Sawano Kentarou , Shiraki Yasuhiro , Haller Eugene E.
Published: September 2009

In order to probe the fundamental behaviors of point defects in silicon and germanium, we studied the self-diffusion using isotope superlattices. In ion-implanted germanium, vacancies are in thermal equilibrium and transient enhanced diffusion is not present under the experimental conditions employed in this study. In contrast, silicon self-interstitials are supersaturated in ion-implanted silicon and the self-interstitial concentration is going down to the thermal equilibrium value toward the surface.
Comparison of Evaluation Criteria for Efficient Gettering of Cu and Ni in Silicon Wafers
Authors: Kot Dawid , Kissinger Gudrun , Sattler Andreas , Von Ammon Wilfried
Published: September 2009

The establishment of an evaluation criterion for efficient gettering of transition metals is a very important and difficult issue in the field of defect engineering on silicon wafers. In this work we present results of an investigation of the getter efficiency for Cu and Ni on Czochralski silicon wafers containing various concentrations of oxygen and vacancies. We compare the results with other works on criteria for efficient gettering and analyze their strengths and weaknesses.
Copper Decoration and Etching for Delineation of Crystal Defects in Thick SOI
Authors: Idrisi Hanan , Riedmüller Stefan , Zoller Jochen , Kolbesen B.
Published: September 2009

The standard method for the delineation of crystal defects in the thin silicon film of Silicon-On-Insulator (SOI) wafers is preferential etching with solutions like the dilute Secco etch. Copper decoration, prior to etching, improves defect delineation by magnifying even small defects. However, artefact formation may contribute to deceptively high defect densities. Results are presented of studies concerning the design and improvement of copper decoration of crystal defects using different preferential etching solutions. Defects with and without a halo were characterized. Differences in the defect densities were obtained after etching with varying etching solutions.
Characterization of Structural Defects in Silicon and SOI Wafers by Means of Laser Scattering Tomography
Authors: Monier Vanessa A. , Capello Luciana , Kononchuk Oleg , Pichaud Bernard
Published: September 2009

The ongoing quality improvement of Silicon-On-Insulator wafers motivates further developments of Laser Scattering Tomography (LST). LST coupled with advanced image processing and simulations enables to have highly reproducible quantitative information on small oxygen precipitates and extended defects, such as dislocations. The growth kinetics of individual defects is discussed. Theoretical predictions of dislocation light scattering dependence on polarization have been confirmed by the determination of dislocation Burgers vector and lines from LST measurements.
Considerable Improvement of Depth Resolution in Auger Sputter Depth Profiling of Polycrystalline Thin Films Using In-situ Sample Preparation Methods
Authors: Scheithauer Uwe
Published: September 2009

Today, one of the important applications of Auger electron spectroscopy in semiconductor material analysis is in-depth profiling of thin films. The sample is eroded by ion bombardment ('sputtering') and the residual surface is analyzed. The depth distributions of the elements are recorded as a function of sputter time. Especially, when sputtering polycristalline thin films, the depth resolution of sputter depth profiling is limited by the sputter yield differences attributed to grains having different crystalline orientations relative to the incoming ion beam. If depth profiling is performed on a single grain only, the depth resolution enhences. Here, two in-situ sample preparation methods are used to identify a single grain. It is found either at the sputter crater edge or using an in-situ low-angle cross section.
Semiconductor Thin Film Characterization with ac Surface Photo Voltage
Authors: Tsidilkovski Edward
Published: September 2009

Surface Photo Voltage (SPV) method is proven to be well-suited for accurate and non-destructive characterization of semiconductor thin films due to its high sensitivity to the near surface region. Presented data and analysis encompasses wide range of ac-SPV technique capabilities. A physical model describing measurement regimes is discussed. The results agree with the theory and correlate with the data obtained with alternative measurement techniques.
Comparison of Silicon Surface Preparation Methods for Measurement of Minority Carrier Lifetime using the Microwave Photo-conductive Decay (μ-PCD) coupled with Continuous Corona Charge (Charge-PCD)
Authors: Pavelka Tibor , Pap Aron , Kenesei Peter , Varga Mariann , Novinics F. , Tallian Miklos , Borionetti Gabriella , Guaglio Gianluca , Pfeffer Markus , Don Eric R.
Published: September 2009

Experimental results for a new method of measuring the minority carrier lifetime as a process control tool to determine trace metal contamination following wafering and/or epitaxial growth of silicon in a production environment are reported. In this new method the minority carrier lifetime by is measured by microwave photo-conductive decay (μ-PCD) while charging the surface silicon oxide with a corona charge. We have named the method Charge-PCD. Results are given comparing various qualities of the surface oxides prepared by low temperature methods coupled with various corona charging recipes in order to determine the optimum process and limitations of the new method.