bluuebunny/crossref_metadata_2025 huggingface dataset:
Energy-efficient computing for wildlife tracking
Authors: Juang Philo , Oki Hidekazu , Wang Yong , Martonosi Margaret , Peh Li Shiuan , Rubenstein Daniel
Published: July 2004

Over the past decade, mobile computing and wireless communication have become increasingly important drivers of many new computing applications. The field of wireless sensor networks particularly focuses on applications involving autonomous use of compute, sensing, and wireless communication devices for both scientific and commercial purposes. This paper examines the research decisions and design tradeoffs that arise when applying wireless peer-to-peer networking techniques in a mobile sensor network designed to support wildlife tracking for biology research.The ZebraNet system includes custom tracking collars (nodes) carried by animals under study across a large, wild area; the collars operate as a peer-to-peer network to deliver logged data back to researchers. The collars include global positioning system (GPS), Flash memory, wireless transceivers, and a small CPU; essentially each node is a small, wireless computing device. Since there is no cellular service or broadcast communication covering the region where animals are studied, ad hoc, peer-to-peer routing is needed. Although numerous ad hoc protocols exist, additional challenges arise because the researchers themselves are mobile and thus there is no fixed base station towards which to aim data. Overall, our goal is to use the least energy, storage, and other resources necessary to maintain a reliable system with a very high `data homing' success rate. We plan to deploy a 30-node ZebraNet system at the Mpala Research Centre in central Kenya. More broadly, we believe that the domain-centric protocols and energy tradeoffs presented here for ZebraNet will have general applicability in other wireless and sensor applications.
Enabling trusted software integrity
Authors: Kirovski Darko , Drinić Milenko , Potkonjak Miodrag
Published: July 2004

Preventing execution of unauthorized software on a given computer plays a pivotal role in system security. The key problem is that although a program at the beginning of its execution can be verified as authentic, while running, its execution flow can be redirected to externally injected malicious code using, for example, a buffer overflow exploit. Existing techniques address this problem by trying to detect the intrusion at run-time or by formally verifying that the software is not prone to a particular attack.We take a radically different approach to this problem. We aim at intrusion prevention as the core technology for enabling secure computing systems. Intrusion prevention systems force an adversary to solve a computationally hard task in order to create a binary that can be executed on a given machine. In this paper, we present an exemplary system--SPEF--a combination of architectural and compilation techniques that ensure software integrity at run-time. SPEF embeds encrypted, processor-specific constraints into each block of instructions at software installation time and then verifies their existence at run-time. Thus, the processor can execute only properly installed programs, which makes installation the only system gate that needs to be protected. We have designed a SPEF prototype based on the ARM instruction set and validated its impact on security and performance using the MediaBench suite of applications.
ECOSystem
Authors: Zeng Heng , Ellis Carla S. , Lebeck Alvin R. , Vahdat Amin
Published: July 2004

Energy consumption has recently been widely recognized as a major challenge of computer systems design. This paper explores how to support energy as a first-class operating system resource. Energy, because of its global system nature, presents challenges beyond those of conventional resource management. To meet these challenges we propose the Currentcy Model that unifies energy accounting over diverse hardware components and enables fair allocation of available energy among applications. Our particular goal is to extend battery lifetime by limiting the average discharge rate and to share this limited resource among competing task according to user preferences. To demonstrate how our framework supports explicit control over the battery resource we implemented ECOSystem, a modified Linux, that incorporates our currentcy model. Experimental results show that ECOSystem accurately accounts for the energy consumed by asynchronous device operation, can achieve a target battery lifetime, and proportionally shares the limited energy resource among competing tasks.
Cool-Mem
Authors: Ashok Raksit , Chheda Saurabh , Moritz Csaba Andras
Published: July 2004

This paper presents Cool-Mem, a family of memory system architectures that integrate conventional memory system mechanisms, energy-aware address translation, and compiler-enabled cache disambiguation techniques, to reduce energy consumption in general purpose architectures. It combines statically speculative cache access modes, a dynamic CAM based Tag-Cache used as backup for statically mispredicted accesses, various conventional multi-level associative cache organizations, embedded protection checking along all cache access mechanisms, as well as architectural organizations to reduce the power consumed by address translation in virtual memory. Because it is based on speculative static information, the approach removes the burden of provable correctness in compiler analysis passes that extract static information. This makes Cool-Mem applicable for large and complex applications, without having any limitations due to complexity issues in the compiler passes or the presence of precompiled static libraries. Based on extensive evaluation, for both SPEC2000 and Mediabench applications, 12% to 20% total energy savings are obtained in the processor, with performance ranging from 1.2% degradation to 8% improvement, for the applications studied.
Design and evaluation of compiler algorithms for pre-execution
Authors: Kim Dongkeun , Yeung Donald
Published: July 2004

Pre-execution is a promising latency tolerance technique that uses one or more helper threads running in spare hardware contexts ahead of the main computation to trigger long-latency memory operations early, hence absorbing their latency on behalf of the main computation. This paper investigates a source-to-source C compiler for extracting pre-execution thread code automatically, thus relieving the programmer or hardware from this onerous task. At the heart of our compiler are three algorithms. First,
program slicing
removes non-critical code for computing cache-missing memory references, reducing pre-execution overhead. Second,
prefetch conversion
replaces blocking memory references with non-blocking prefetch instructions to minimize pre-execution thread stalls. Finally,
threading scheme selection
chooses the best scheme for initiating pre-execution threads, speculatively parallelizing loops to generate thread-level parallelism when necessary for latency tolerance. We prototyped our algorithms using the Stanford University Intermediate Format (SUIF) framework and a publicly available program slicer, called
Unravel
[13], and we evaluated our compiler on a detailed architectural simulator of an SMT processor. Our results show compiler-based pre-execution improves the performance of 9 out of 13 applications, reducing execution time by 22.7%. Across all 13 applications, our technique delivers an average speedup of 17.0%. These performance gains are achieved fully automatically on conventional SMT hardware, with only minimal modifications to support pre-execution threads.
Compiler optimization of scalar value communication between speculative threads
Authors: Zhai Antonia , Colohan Christopher B. , Steffan J. Gregory , Mowry Todd C.
Published: July 2004

While there have been many recent proposals for hardware that supports
Thread-Level Speculation
(TLS), there has been relatively little work on compiler optimizations to fully exploit this potential for parallelizing programs optimistically. In this paper, we focus on one important limitation of program performance under TLS, which is stalls due to forwarding scalar values between threads that would otherwise cause frequent data dependences. We present and evaluate dataflow algorithms for three increasingly-aggressive instruction scheduling techniques that reduce the
critical forwarding path
introduced by the synchronization associated with this data forwarding. In addition, we contrast our compiler techniques with related hardware-only approaches. With our most aggressive compiler and hardware techniques, we improve performance under TLS by 6.2-28.5% for 6 of 14 applications, and by at least 2.7% for half of the other applications.
Enhancing software reliability with speculative threads
Authors: Oplinger Jeffrey , Lam Monica S.
Published: July 2004

This paper advocates the use of a monitor-and-recover programming paradigm to enhance the reliability of software, and proposes an architectural design that allows software and hardware to cooperate in making this paradigm more efficient and easier to program.We propose that programmers write monitoring functions assuming simple sequential execution semantics. Our architecture speeds up the computation by executing the monitoring functions speculatively in parallel with the main computation. For recovery, programmers can define fine-grain transactions whose side effects, including all register modifications and memory writes, can either be committed or aborted under program control. Transactions are implemented efficiently by treating them as speculative threads.Our experimental results suggest that monitored execution is more amenable to parallelization than regular program execution. Code monitoring is sped up by a factor of 1.5 by exploiting single-thread instruction-level parallelism, and by an additional factor of 1.6 using thread-level speculation. This results in an overall improvement of 2.5 times and a sustained 5.4 instructions-per-cycle performance. A monitored execution that used to be 2.5 times slower executes with a degradation of only 12% when compared to the performance on the baseline machine. We also show that the concept of fine-grain transactional programming is useful in catching buffer overrun errors through a number of real-life examples.
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Authors: Mukherjee Shubhendu S. , Silla Federico , Bannon Peter , Emer Joel , Lang Steve , Webb David
Published: July 2004

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ
arbiters
that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called
SPAA
(Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the
Rotary Rule,
which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.
Increasing web server throughput with network interface data caching
Authors: Kim Hyong-youb , Pai Vijay S. , Rixner Scott
Published: July 2004

This paper introduces network interface data caching, a new technique to reduce local interconnect traffic on networking servers by caching frequently-requested content on a programmable network interface. The operating system on the host CPU determines which data to store in the cache and for which packets it should use data from the cache. To facilitate data reuse across multiple packets and connections, the cache only stores application-level response content (such as HTTP data), with application-level and networking headers generated by the host CPU. Network interface data caching can reduce PCI traffic by up to 57% on a prototype implementation of a uniprocessor web server. This traffic reduction results in up to 31% performance improvement, leading to a peak server throughput of 1571 Mb/s.
Evolving RPC for active storage
Authors: Sivathanu Muthian , Arpaci-Dusseau Andrea C. , Arpaci-Dusseau Remzi H.
Published: July 2004

We introduce Scriptable RPC (SRPC), an RPC-based framework that enables distributed system services to take advantage of active components. Technology trends point to a world where each component in a system (whether disk, network interface, or memory) has substantial computational capabilities; however, traditional methods of building distributed services are not designed to take advantage of these new architectures, mandating wholesale change of the software base to exploit more powerful hardware. In contrast, SRPC provides a direct and simple migration path for traditional services into the active environment.We demonstrate the power and flexibility of the SRPC framework through a series of case studies, with a focus on active storage servers. Specifically, we find three advantages to our approach. First, SRPC improves the performance of distributed file servers, reducing latency by combining the execution of operations at the file server. Second, SRPC enables the ready addition of new functionality; for example, more powerful cache consistency models can be realized on top of a server that exports a simple NFS-like interface. Third, SRPC simplifies the construction of distributed services; operations that are difficult to coordinate across client and server can now be co-executed at the server, thus avoiding costly agreement and crash-recovery protocols.
A stateless, content-directed data prefetching mechanism
Authors: Cooksey Robert , Jourdan Stephan , Grunwald Dirk
Published: July 2004

Although central processor speeds continues to improve, improvements in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruction prefetch mechanisms have been proposed. Recently, several proposals have posited a
memory-side
prefetcher; typically, these prefetchers involve a distinct processor that executes a program slice that would effectively prefetch data needed by the primary program. Alternative designs embody large state tables that learn the miss reference behavior of the processor and attempt to prefetch likely misses.This paper proposes
Content-Directed Data Prefetching,
a data prefetching architecture that exploits the memory allocation used by operating systems and runtime systems to improve the performance of pointer-intensive applications constructed using modern language systems. This technique is modeled after conservative garbage collection, and prefetches "likely" virtual addresses observed in memory references. This prefetching mechanism uses the underlying data of the application, and provides an 11.3% speedup using
no additional processor state.
By adding less than ½% space overhead to the second level cache, performance can be further increased to 12.6% across a range of "real world" applications.
A stream compiler for communication-exposed architectures
Authors: Gordon Michael I. , Thies William , Karczmarek Michal , Lin Jasper , Meli Ali S. , Lamb Andrew A. , Leger Chris , Wong Jeremy , Hoffmann Henry , Maze David , Amarasinghe Saman
Published: July 2004

With the increasing miniaturization of transistors, wire delays are becoming a dominant factor in microprocessor performance. To address this issue, a number of emerging architectures contain replicated processing units with software-exposed communication between one unit and another (e.g., Raw, SmartMemories, TRIPS). However, for their use to be widespread, it will be necessary to develop compiler technology that enables a portable, high-level language to execute efficiently across a range of wire-exposed architectures.In this paper, we describe our compiler for StreamIt: a high-level, architecture-independent language for streaming applications. We focus on our backend for the Raw processor. Though StreamIt exposes the parallelism and communication patterns of stream programs, some analysis is needed to adapt a stream program to a software-exposed processor. We describe a partitioning algorithm that employs fission and fusion transformations to adjust the granularity of a stream graph, a layout algorithm that maps a stream graph to a given network topology, and a scheduling strategy that generates a fine-grained static communication pattern for each computational element.We have implemented a fully functional compiler that parallelizes StreamIt applications for Raw, including several load-balancing transformations. Using the cycle-accurate Raw simulator, we demonstrate that the StreamIt compiler can automatically map a high-level stream abstraction to Raw without losing performance. We consider this work to be a first step towards a portable programming model for communication-exposed architectures.
Just what is an op-code?
Authors: Brakefield James
Published: July 2004

The following computer architecture offers extensible machine language. That is it has an open-ended instruction set. It does this by using the same format for both op-codes and subroutine calls. Theoretically this means that the programmer can chose an instruction set for the application at hand. Ie., the machine language representation of a program can correspond to a high level textual representation or a program.The mechanism of instruction processing for this architecture is essentially a way of encompassing the major categories of interpreters : Direct threaded code, indirect threaded code, and P-code or compressed threaded code. The mechanism is closest in spirit to that of Forth and can be considered a hardware implementation of Forth.Due to the simplicity of instruction set representation, the design is not tied to any one word size. Thus, it is implementable on all the major word sizes (16, 24, 32, 36, 48, 60, or 64 bits).I hope this is perceived as an elegant design.
A Tree Structured Architecture for semantic gap reduction
Authors: Plotkin Arieh , Tabak Daniel
Published: July 2004

The article proposes a new Tree-Structured-Architecture (TSA). The TSA is object-oriented, implements the notions of capability-based-addressing and the single-level-store, and it is particularly designed to narrow the semantic gap. It encourages modular programming and directly supports the concepts of tasks and inter-task communication, making it particularly suitable for multiprocessing and multiprogramming implementation.The TSA is implemented on a multi-resource, distributed, matrix-structured, reconfigurable, fault-tolerant computing system, proposed in this article. The system implements some ideas of the dynamic and the flexible architecture. The system possesses a high degree of regularity by implementing large amounts of identical units. The hardware is modular, permitting the addition or removal of groups of units, without a change in the system's software.
Process exchange on the PR1ME family of computers
Authors: Feustel Edward A.
Published: July 2004

A high speed mechanism for process exchange is essential in a time sharing system based on the use of many processes. The automated process exchange mechanism on the Model P400 and the 50 Series of PR1ME machines is described. Typical timing for operations using the process exchange mechanism on the P750 is given. Its use in PRIMOS is explained and validated.
Computer design evaluation using programming language primitives
Authors: McKeeman W. M.
Published: July 2004

One aspect of the evaluation of computer design is the appropriateness of the instruction set for the primitives needed by high level programming languages. We present a set of primitives and a recipe for evaluation with respect to them.
The architecture of the picture system
Authors: Callan James F.
Published: July 2004

THE PICTURE SYSTEM is a self-contained, stand-alone line drawing system for presenting dynamically moving pictures of two- or three-dimensional objects. This highly interactive system can display smoothly changing true perspective views of 3-D objects in real time. Objects can be rotating, translating, and changing in scale. Individual sub-objects can assume independent or compound motion. Lines or parts of lines outside the chosen viewing window are clipped. All these transformations are performed digitally to avoid inaccuracy and range limitations.In order to perform these calculations fast enough to show smooth motion, support high-level interaction, and also sustain flicker-free pictures of 11000 line segments or more, a new graphics system architecture has been developed. This paper will present each of the hardware components of the system and discuss what each contributes to the production of pictures.THE PICTURE SYSTEM represents a significant new graphics system architecture in several respects. This paper will describe the system including data flow, the functions of each major component, and some of the advantages that accrue from the approaches taken.
A fast display-oriented processor
Authors: Staudhammer John , Eastman Jeffrey F. , England James N.
Published: July 2004

A detailed study of the basic operations of scan graphics processes led to the design of this general-purpose expandable processor. Full advantage is taken of evolving trends in ECL technology and large-scale integrated circuits. The design allocates hardwired instructions to critical display functions and provides general-purpose flexibility in externally microprogrammable asynchronous processors. The machine uses instruction set partitioning and is optimized to execute relatively short programs operating on large data bases. The processor is thus not limited to display generation but is rather well suited for other real-time tasks, particularly those operating with autonomous processors which can be added as external devices.
Computer display of colored three-dimensional objects
Authors: Eastman Jeffrey F. , Staudhammer John
Published: July 2004

A television-based computer display system is described which uses a minicomputer to calculate scan lines of the display image. A display resolution of 512 lines by 512 positions is achieved with each position definable with 15 bits of color information (over 32,000 colors). The scan conversion process incorporates hidden surface removal, calculation of intersections, surface shading and, optionally, perspective. Object description must be by polygonal planar surfaces; the surfaces can have a solid color and are considered opaque. Object complexity is limited only by main storage size.The design criteria which motivated the system architecture are discussed along with pertinent details on the particular implementation. The system described effectively mates minicomputer technology with that of the television industry to produce an economical, fast turnaround, color display system for 2-D and 3-D computer graphics. This system relies upon a special scan-line generator and upon a skillful hardware/software trade-off to achieve an economical and realistic color display device.Performance data and examples of display objects are given.
A microprogrammed processor for interactive computer graphics
Authors: Kerr Henry D.
Published: July 2004

This paper describes the architecture of the micro-programmed processor which is the heart of the Adage GP/400 interactive graphics system, and discusses some of the factors which influenced its design.
Functional memory techniques applied to the microprogrammed control of an associative processor
Authors: Armstrong C. V. W.
Published: July 2004

Consideration is given to the separation of the data and control structures of a microprogrammed processor. The use of functional memory techniques to provide a suitable medium for containing and processing the control structure and giving one possible solution to this separation problem is described. The design considered is that of an associative processor but the techniques involved are applicable to other types of processors. Some of the advantages of this approach are given, together with their implications in the light of advances in microprocessor technology and cellular logic.
HMO, a hardware microcode optimizer
Authors: Bondi James O. , Stigall Paul D.
Published: July 2004

This paper discusses an algorithm for optimizing the density and parallelism of microcoded routines in microprogrammable machines. Besides the algorithm itself, the algorithm's uses, adaptability to conventional machine characteristics, and architectural requirements are also discussed and analyzed. Even though the paper proposes a hardware implementation of the algorithm, the algorithm is viewed as an integral part of the entire microcode generation and usage process, from initial high-level input into a software microcode compiler down to machine-level execution of the resultant microcode on the host machine. It is believed that, by removing much of the traditionally time-consuming and machine-dependent microcode optimization from the software portion of this process, the algorithm can improve the overall process.
Picture systems, PS, and the design of a channel-to-channel computer interface
Authors: Isaacson Portia
Published: July 2004

This paper introduces a new simulation tool called picture systems. A picture system is (1) a set of pictures - one representing each state of a modeled computer system and (2) a transition graph which relates each picture to the set of pictures that may follow it. Picture systems can be used to model computer systems at any level of detail; however, this paper is concerned with modeling hardware/software systems at relatively high architectural levels. Picture systems, as a simulation tool, are useful to the computer architect. Perhaps more importantly, they provide an unexcelled means of communicating computer system mechanisms between people.The construction of picture systems from descriptions of the components of a computer system has been automated in PS. This paper describes a model of a channel-to-channel computer interface mechanism consisting of both hardware and software. Transition graph analysis by PS is briefly described. This powerful aid to computer system modeling eases the identification of problems such as deadlock, looping, and races.
Reference concepts in a tree structured address space
Authors: Löfgren Lennart
Published: July 2004

We start by summarizing our goals with an emphasis on our requirements on references. A dynamically varying space of virtual addresses is postulated. This space has the structure of a rooted tree. All references considered are essentially relative: to a target from a context. A few reference concepts are defined and explored, together with a unified operation of qualification and offsetting and one operation for forming references from new contexts.
A virtual memory for microprocessors
Authors: Anderson Judith A. , Lipovski G. J.
Published: July 2004

A virtual memory system for microprocessors is described. The system is designed to be extensible, to minimize software and execution overhead and to minimize operating system requirements. Specific application of the virtual memory system with the INTEL 8080 microprocessor is given, describing the necessary software constraints and operating system requirements.
Design study of an avionics navigation microcomputer
Authors: Kodres Uno R. , McCracken William L.
Published: July 2004

A microcomputer program to solve the complex task of airborne navigation was developed to demonstrate the practicality of replacing costly general-purpose digital computers with relatively inexpensive dedicated microcomputers on board naval aircraft. The microcomputer program showed that microcomputers have sufficient speed and accuracy to solve the navigation problem. In order to overcome the microcomputer's major deficiencies, speed and accuracy, special arithmetic subprograms based on table look-up were developed to trade inexpensive memory for more speed. An application of graph theory in the form of process graphs was made to facilitate the development and documentation of the navigation program.
An iteratively structured information processor
Authors: Kane Gerald R.
Published: July 2004

There exists a widely held belief that the full potential of LSI technology will be realized by arrays of logic circuits. A novel machine architecture is proposed that consists of a uniform array of identical cells with the property that the array executes a high-level programming language directly. Some of the more important features of such machines are their inherent abilities to sustain concurrent processes and to maintain efficient information storage. A detailed simulation of a language machine in its architectural style is presented.
The design and evaluation of the array machine
Authors: Sylvain Pierre , Vineberg Maniel
Published: July 2004

This paper describes work on a high-level language processor, the Array Machine System. The work described includes a description of the high-level language, a discussion of the two components of the system, the Net Compiler and the Array Machine, and recent measurements made on that system. The language described is based on postfix notation. The Net Compiler, which exists as a PL/l program, prepares the control code for the Array Machine. The Array Machine, which exists as a PL/l simulation program, executes the control code, using its primary processing element, an array of homogeneous building blocks. The measurements on the system feature a comparison to a third generation computer.
Reduction languages for reduction machines
Authors: Berkling K. J.
Published: July 2004

This paper describes a particular realization of a Lambda-Red language as a machine language. Parts of it resemble the Lambda Calculus or a transposed form of it. A constructor syntax is employed such that a linearized preorder representation of the syntax tree is the information structure on which the machine operates. Instances of reduction rules are recognized by combinations of constructors and atoms. Reduction rules with 1, 2 and 3 constructors and/or atoms have been described.A recursive control structure forms the essential part of the implementation. There is a one to one correspondence between constructor syntax and control structure rather than a simulation of recursive structure by von Neumann type instruction sequencing. Thus the system is easily expandable by new constructors and atoms. Execution, that is the application of reduction rules, is subsumed under editing. Emphasis has been on the following pragmatic concepts: locality of action, directness, and security. There are no error messages, errors appear as irreducible expressions. There is no "RUN" instruction, instead the number of reductions to be performed is specified. Whatever happens - it is restricted to subexpressions. The user has the security that all his actions are limited and predictable.The machine language resembles a higher level programming language, but it is "variable-free": expressions are named, not boxes which contain expressions. There seems to be a concept of late binding. However, this is not made a matter of principle, but a matter of degree. Between a general statement of a problem and the result are many intermediate representations - all in the same language - corresponding to various degrees of binding parameters. The user has complete freedom in the choice of variable names. There is a specially developped protection system which avoids confusion of variables.The efficiency of the system is limited by the rate characters can be processed which is essentially determined by the control store cycletime. Measurements will be performed as soon as a simulation of the system is available. Three other important subjects, namely arithmetic, the definition of constants, and source sink input-output will be reported later.
Advantages of structured hardware
Authors: Lawson Harold W. , Magnhagen Bengt
Published: July 2004

The proper structuring of the implementation levels in a digital computer system is an important attribute for all aspects of the product. That is to say, the design, development, testing, production and maintenance of the product are facilitated by a well-structured design of the software and hardware components. This paper discusses digital computer system structuring in general, followed by descriptions of the logical and physical architecture of the DATASAAB FCPU (Flexible Central Processing Unit). The implementation of a vector arithmetic instruction is presented to provide a more thorough insight into the operational aspects of the FCPU. Finally, the benefits derived from the structuring of this hardware product are presented.
Concepts of the MATHILDA system
Authors: Kornerup Peter
Published: July 2004

A dynamically microprogrammable processor called MATHILDA is described. MATHILDA has been designed to be used as a tool in emulator and processor design research. It has a very general microinstruction sequencing scheme, sophisticated masking and shifting capability, high speed local storage, a 64-bit wide main data path, a horizontally encoded microinstruction, and other facilities which make it reasonably well suited for this purpose. This paper presents a brief overview of the MATHILDA system, and some of the concepts in more detail.
Conjoined computer systems
Authors: Wann Donald F. , Ellis Robert A.
Published: July 2004

A new computer system organization and implementation is described and its application to problems in both clinical and research laboratory biomedical applications is outlined. This system, called a Conjoined Computer System to emphasize the idea of computer coordination, consists of a few storedprogram computers, each with a fixed assigned task, and inter-connected with combined data and control paths which may be easily changed. Such systems appear to be useful in situations where a) one or more major laboratory peripheral devices are included, b) operational speed is required which is greater than that which can be obtained from a single processor implementation, and c) the algorithms utilized can be partitioned into two or more machines such that only moderate intercomputer communication rates are needed. This architecture offers the possibility of simplifying the peripheral interfacing, reducing total computation time, allowing rapid system reconfiguration, enforcing the discipline required for structured programming, and, by means of a centralized program development console, increasing the efficiency of program development.
A distributed function computer for real-time control
Authors: Jensen E. Douglas
Published: July 2004

Due to advances in hardware technology, processors are no longer the limiting factor in system costs--the software and configuration portions are now dominant. Hardware can be effectively applied to these problems as well: low processor costs have revitalized multiprocessors and multicomputers; the executive functions entailed by such architectures can be facilitated with powerful yet flexible hardware mechanisms. This paper outlines the hardware aspects of an experimental distributed function computer intended to examine these issues in the context of real-time control systems.
Switched multiple instruction, multiple data stream processing
Authors: Radoy C. H. , Lipovski G. J.
Published: July 2004

A new architecture is proposed for the effective use of program memory in highly parallel applications. This architecture is particularly suited (but not limited) to being built with standard microprocessors. This architecture utilizes a combination of the state switching idea of the SIMD organization and the multiple data stream idea of MIMD organizations. Through scheduling, the program segments are broadcast at the times required to achieve efficient utilization of the parallel processing array. Relationships are developed to determine, for a given application, if this architecture is more cost effective than comparable SIMD and MIMD organizations.
STARLET
Authors: Giloi W. K. , Berg H.
Published: July 2004

It is a well-acknowledged fact that the adequate structuring of data is as important as the adequate structuring of a program. The classical von Neumann - machine deals on the hardware level only with scalars and, therefore, provides no hardware support of any sort for the manipulation of more complex data structures. Some more recently developed concepts - all variants of Iliffe's Basic Language Machine -- provide some hardware support for structuring data in the form of trees. Contrastingly, in the STARLET concept to be discussed in this paper, the basic data structure is that of ordered sets (as given by strings and arrays). In the paper, the basic notions of this novel concept are introduced and discussed, especially the internal information structure which differs considerably from that of the von Neumann-machine or other concepts. This very idiosyncratic information structure has far-reaching consequences with respect to the hardware structure of the machine. Finally, a number of resulting features will be discussed and an attempt will be made to compare the computing power of STARLET with that of avon Neumann-machine with equally fast hardware.
A machine-oriented resource management architecture
Authors: Goldstein Barry C. , Scrutchin Thomas W.
Published: July 2004

An architecture for resource management in a computer system is presented. The architecture is a subset of an APL-like higher level language machine architecture. The approach provides for a natural division of function between software and microcode/hardware. Any object in the system can be managed as a resource, and the fact that an object is managed can be transparent to the program using the object. Finally the resource management concepts are related to the current resource management problems of effective third-party control of resources, intelligent work scheduling, and deadlock resolutions.
The International Computers Ltd. ICL2900 computer architecture
Authors: Doran R. W.
Published: July 2004

The ICL2900 hardware architecture is compared with that of the B6700/B7700. The two systems are based on similar principles and are similar in overall design. However, although the ICL2900 postdates the B6700 by seven years, the machines have independent origins and differ in many important details.
A question of style
Authors: Lipovski G. Jack
Published: July 2004

Problems in the style of writing papers in Computer Architecture are delineated. A style of writing papers is proposed and some experiences with it are reported. This style may develop into a useful vehicle for reporting research in computer science.
Some thoughts on data flow architectures
Authors: Sharp John A.
Published: July 2004

Various possible approaches to the design of a data flow computer architecture are discussed. An attempt is made to identify some of the features that may be regarded as fundamental in data flow architectures. The logical structure of data flow programs is related to the physical structure of the machine.
A hardware implementation of capability-based addressing
Authors: Myers G. J. , Buckingham B. R. S.
Published: July 2004

The SWARD architecture, an experimental higher-level architecture, contains the naming and protection concept of capability-based addressing. After discussing the merits of capability-based addressing, its general representation in the SWARD architecture is discussed. The initial representation of capability-based addressing in the architecture led to a set of problems; these problems are described, as well as their solutions. Finally, the implementation of capabilities by the processor is discussed.
Architectural support for synchronous task communication
Authors: Burkowski F. J. , Cormack G. V. , Dueck G. D. P.
Published: July 2004

This paper describes the motivation for a set of intertask communication primitives, the hardware support of these primitives, the architecture used in the Sylvan project which studies these issues, and the experience gained from various experiments conducted in this area. We start by describing how these facilities have been implemented in a multiprocessor configuration that utilizes a shared backplane. This configuration represents a single node in the system. The latter part of the paper discusses a distributed multiple node system and the extension of the primitives that are used in this expanded environment.

This research is funded by a strategic grant from the Natural Sciences and Engineering Research Council of Canada (Grant No. G1581).
A software instruction counter
Authors: Mellor-Crummey J. M. , LeBlanc T. J.
Published: July 2004

Although several recent papers have proposed architectural support for program debugging and profiling, most processors do not yet provide even basic facilities, such as an instruction counter. As a result, system developers have been forced to invent software solutions. This paper describes our implementation of a software instruction counter for program debugging. We show that an instruction counter can be reasonably implemented in software, often with less than 10% execution overhead. Our experience suggests that a hardware instruction counter is not necessary for a practical implementation of watch-points and reverse execution, however it will make program instrumentation much easier for the system developer.
Efficient debugging primitives for multiprocessors
Authors: Aral Z. , Gerther I. , Schaffer G.
Published: July 2004

Existing kernel-level debugging primitives are inappropriate for instrumenting complex sequential or parallel programs. These functions incur a heavy overhead in their use of system calls and process switches. Context switches are used to alternately invoke the debugger and the target programs. System calls are used to communicate data between the target and debugger.

None of this is necessary in shared-memory multiprocessors. Multiple processors concurrently run both the debugger and the target. Shared-memory is used to implement efficient communication. The target's state is accessed by running both the target and the debugger in the same address space. Finally, instrumentation points, which have largely been implemented as traps to the system, are reimplemented as simple branches to routines of arbitrary complexity maintained by the debugger. Not only are primitives such as conditional breakpoints thus generalized, but their efficiency is improved by several orders of magnitude. In the process, much of the traditional system's kernel support for debugging is reimplemented at user-level.

This paper describes the implementation of debugging primitives in Parasight, a parallel programming environment. Parasight has been used to implement conditional breakpoints, an important primitive for both high-level and parallel debugging. Preliminary measurements indicate that Parasight breakpoints are 1000 times faster than the breakpoints in parallel “cdb”, a conventional UNIX debugger. Light-weight conditional breakpoints open up new opportunities for debugging and profiling both parallel and sequential programs.
Sheaved memory: architectural support for state saving and restoration in pages systems
Authors: Staknis M. E.
Published: July 2004

The concept of read-one/write-many paged memory is introduced and given the name
sheaved memory
. It is shown that sheaved memory is useful for efficiently maintaining checkpoints in main memory and for providing state saving and state restoration for software that includes recovery blocks or similar control structures. The organization of sheaved memory is described in detail, and a design is presented for a prototype sheaved-memory module that can be built easily from inexpensive, off-the-shelf components. The module can be incorporated within many available computers without altering the computers' hardware design. The concept of sheaved memory is simple and appealing, and its potential for use in a number of software contexts is foreseen.
Reference history, page size, and migration daemons in local/remote architectures
Authors: Holliday M. A.
Published: July 2004

We address the problem of paged main memory management in the local/remote architecture subclass of shared memory multiprocessors. We consider the case where the operating system has primary responsibility and uses page migration as its main tool. We identify some of the key issues with respect to architectural support (reference history maintenance, and page size), and operating system mechanism (duration between daemon passes, and number of migration daemons).

The experiments were conducted using software implemented page tables on 32-node BBN Butterfly Plus
™
. Several numeral programs with both synthetic and real data were used as the workload. The primary conclusion is that for the cases considered migration was at best marginally effective. On the other hand, practical migration mechanisms were robust and never significantly degraded performance. The specific results include: 1) Referenced bits with
aging
can closely approximate Usage fields, 2) larger page sizes are beneficial except when the page is large enough to include locality sets of two processes, and 3) multiple migration daemons can be useful.

Only small regions of the space of architectural, system, and workload parameters were explored. Further investigation of other parameter combinations is clearly warranted.
Translation lookaside buffer consistency: a software approach
Authors: Black D. L. , Rashid R. F. , Golub D. B. , Hill C. R.
Published: July 2004

We discuss the translation lookaside buffer (TLB) consistency problem for multiprocessors, and introduce the Mach shootdown algorithm for maintaining TLB consistency in software. This algorithm has been implemented on several multiprocessors, and is in regular production use. Performance evaluations establish the basic costs of the algorithm and show that it has minimal impact on application performance. As a result, TLB consistency does not pose an insurmountable obstacle to multiprocessors with several hundred processors. We also discuss hardware support options for TLB consistency ranging from a minor interrupt structure modification to complete hardware implementations. Features are identified in current hardware that compound the TLB consistency problem; removal or correction of these features can simplify and/or reduce the overhead of maintaining TLB consistency in software.
Failure correction techniques for large disk arrays
Authors: Gibson G. A. , Hellerstein L. , Karp R. M. , Patterson D. A.
Published: July 2004

The ever increasing need for I/O bandwidth will be met with ever larger arrays of disks. These arrays require redundancy to protect against data loss. This paper examines alternative choices for encodings, or codes, that reliably store information in disk arrays. Codes are selected to maximize mean time to data loss or minimize disks containing redundant data, but are all constrained to minimize performance penalties associated with updating information or recovering from catastrophic disk failures. We also codes that give highly reliable data storage with low redundant data overhead for arrays of 1000 information disks.