Evaluation of Hole Trapping Characteristics in MONOS-Type Memories Using the Constant Current Carrier Injection Method
Authors: Kato Kaihei , Ahmed Sheikh Rashel Al , Kobayashi Kiyoteru 
Published: February 2020

MONOS (Metal-oxide-nitride-oxide-semiconductor)-type nonvolatile memory (NVM) with a silicon nitride charge trapping layer has attracted considerable attention as the data storage for communication and multimedia applications.1-5In this type of memory, electrons and holes captured by traps in the silicon nitride layer cause shifts in the threshold voltage of memory transistors. Recently, the amount of charge stored in memory transistors is reduced because of shrinking the memory cell size. It is necessary to understand the charge trapping mechanism to ensure sufficient charge storage even in the small size transistors of NVMs. It is considered that three kinds of traps (namely, empty traps, traps which captured electrons and traps which captured holes) exist in the nitride layer. In the present study, we investigated the hole trapping characteristics in the empty traps and the traps which captured electrons in the nitride layer.

Memory capacitors with the blocking oxide-silicon nitride-tunnel oxide (17.2/30.4/2.4 nm) stacked films were fabricated on p-type (100) silicon substrates. A tunnel oxide film of 2.4 nm in thickness was formed by rapid thermal oxidation. A 30.4-nm-thick silicon nitride film was formed by LPCVD using of Si2Cl6 and NH3 gases at 600 °C. A 17.3-nm-thick blocking oxide film was grown at 400 °C by PECVD. Finally, an aluminum film was deposited to form the gate electrode. After the sample fabrication, all the memory capacitors were baked at 233 °C for a long period of time to emit electrons and holes trapped in the stacked films. The CV characteristics of the baked capacitors were measured to determine the flat-band voltage Vfb,0. To inject electrons from the silicon substrate into the nitride layer, the gate electrode was positively biased with visible light illumination. At the next step, negative voltages were applied to the gate electrode to inject holes from the silicon substrate into the nitride layer under a constant current density (Jg = -4.2 × 10-9 A/cm2). Two sets of experiments were performed on the samples. In the first experiment, the samples were subjected to hole injection following electron injection. (These samples called HI-EI.) In the second experiment, the samples were subjected to hole injection following the bake. (These sample called HI-BK.) The number of injected holes per unit area Finj was derived by combining Jg and hole injection time. After hole injection, the CV characteristics were again measured to obtain the flat-band voltage Vfb,h.

In Fig.1, Vfb,h as a function of Finj for the HI-EI samples (▲) is shown. Vfb,h increased with increasing Finj, and then was saturated. Fig.1 also shows Vfb,h as a function of Finjfor the HI-BK samples (△).

In Fig.2, we show the flat-band voltage shift ΔVfb,h as a function of Finj for the HI-EI samples (▲). Here, ΔVfb,h is defined as |Vfb,h-Vfb,0|. Fig. 2 also shows ΔVfb,h as a function of Finj for the HI-BK samples (△). At small Finj, ΔVfb,h for the HI-EI samples was almost equal to ΔVfb,h for the HI-BK samples. This suggests that the hole trapping speed of the HI-EI samples were identical to that of the HI-BK samples.

Next, at large Finj in Fig.1, Vfb,h for the HI-EI samples was almost equal to Vfb,hfor the HI-BK samples. The amount of net positive charge for the HI-EI samples was identical to that of the HI-BK samples.

On the other hand, in Fig. 2, ΔVfb,h for the HI-EI samples was greater than that for the HI-BK sample at larger Finj. In the HI-BK samples, the injected holes were captured by the empty traps (i). In the HI-EI samples, in addition to process (i), the injected holes were captured by the traps which were filled by electrons (ii), or electrons trapped in the nitride layer were emitted (iii). The presence of the process (ii) or (iii) would be responsible for the larger ΔVfb,h of the HI-EI samples.

Acknowledgements We would like to express gratitude to S. Tanaka, K. Hukuyama and K. Ozaki for their valuable discussions. This work was partly supported by JSPS KAKENHI Grant Number 26420280.

References [1]S. Minami et al., IEEE Trans. Electron Devices, 40, 2011 (1993). [2] T. Ishida et al., IEEE Trans. Electron Devices, 60, 863 (2013). [3] H. Puchner et al.,
IEEE Trans. Nucl. Sci.,
61, 2005 (2014). [4] G. H. Lee et al., Jpn. J. Appl. Phys.,
53, 014201 (2014). [5] H. Aochi, Ext. Abstr. 2015 Inter. Workshop on Dielectric Thin Films for Future Electron Devices: Science and Technology, Tokyo, 2015, p. 61.

Figure 1