bluuebunny/crossref_metadata_2025 huggingface dataset:
INITIAL PARAMETRIC REPRESENTATION OF BLOBS
Authors: FAUDOT DOMINIQUE , GARNIER LIONEL
Published: March 2009

Blobs, developed by J.F. Blinn in 1982, are the implicit surfaces obtained by composition of a real numerical function and a distance function. Since, many authors (C. Murakami, H. Nishimura, G. Wyvill…) defined their own function of density, from these implicit surfaces are interesting from several points of view. In particular, their fusion makes it possible to easily obtain an implicit equation of resulting surface. However, these surfaces do not admit a parametric equation yet. In this article, we will establish the parametric equation of two blobs in fusion, defined by the function of density of C. Murakami, by using an algebraic method. Then, we will develop another method, based on the differential equations.
Synthesis of porphyrin-carbohydrate conjugates using "click" chemistry and their preliminary evaluation in human HEp2 cells
Authors: Hao Erhong , Jensen Timothy J. , Vicente M. Graça H.
Published: March 2009

Using a Cu ( I )-catalyzed carbohydrate azide-alkynylphenylporphyrin cycloaddition (the so-called "click" chemistry), we have synthesized in high yields, a series of four new porphyrin-carbohydrate conjugates containing either one or four galactose or lactose moieties linked via triazole units to a meso-phenyl group of a TPP or tetrabenzoporphyrin (TBP) macrocycle. The time-dependent uptake and subcellular distribution of this series of porphyrin-carbohydrate conjugates were evaluated in human carcinoma HEp2 cells. While the three TPP conjugates accumulated to a similar extent within cells and localized mainly in the ER and endosomes, the TBP-galactose conju gate was the one most efficiently taken up by the HEp2 cells, accumulating approximately 5 times more than the TPP conjugates, and localized preferentially within the cell lysosomes.
Investigating different strategies towards the preparation of chiral and achiral bis-picket fence corroles
Authors: Bröring Martin , Funk Markus , Milsmann Carsten
Published: March 2009

Three different strategies have been designed and tested for the preparation of sterically hindered chiral and achiral bis-picket fence corroles. All attempts to prepare an A3 corrole, with six pivaloylamido pickets in the ortho-positions of the meso-aryl substituents, failed. Mass spectrometrical investigations of the reaction mixtures prove the very slow formation of tetrapyrrolic condensation products from strongly hindered benzaldehydes. For sterical reasons, however, these potential precursors seem to be forced into a stretched conformation incapable of oxidative macrocyclization. For A2B-type bis-picket fence corroles, the formation of trace amounts of four-fold pivaloylamido substituted species with a sterically innocent aryl group at the 10-position can be shown. A reverse order of steps, with the palladium-catalyzed amidations of o-bromophenyl groups at the 5- and 15-positions of the completed corrole macrocycle as the last step, has finally been found as the key to a successful and versatile synthesis of such chiral and achiral sterically encumbered corrole ligands.
Structures and properties of hemiquinone-substituted oxoporphyrinogens
Authors: Hill Jonathan P. , Ariga Katsuhiko , D'Souza Francis
Published: March 2009

The structure and physical properties of a series of N-substituted, hemiquinone-substituted oxoporphyrinogens is presented and discussed. Structures of the compounds are dictated by the nature of the substituent, with the substitution pattern being in turn dictated by regioselectivity of N-alkylation. X-ray crystallography and other aggregation properties of the compounds are discussed. Redox reactions are also strongly influenced by N-substitution and substituent identity. Also presented are properties related to guest binding and photophysical properties of oligochromophoric host-guest complexes, involving oxoporphyrinogen, N-substituted with porphyrins and appropriately substituted fullerene guest electron acceptors.
Synthesis, structures, and properties of BCOD-fused porphyrins and benzoporphyrins
Authors: Uoyama Hiroki , Takiue Takahiro , Tominaga Kazuyuki , Ono Noboru , Uno Hidemitsu
Published: March 2009

Bicyclo[2.2.2]octadiene (BCOD)-fused porphyrins with no other substituents were prepared by [2 + 2] and [3 + 1] porphyrin syntheses from ethanodihydroisoindole derivatives in fairly good yields. Thermal retro-Diels-Alder reactions of BCOD-fused porphyrins gave the corresponding benzoporphyrins with no substituent in quantitative yields. Their UV-vis spectra and crystal structures were carefully examined in terms of π-system expansion of the porphyrin ring current. In the cases of monobenzo- and adj-dibenzo-porphyrins, a single Soret band in their UV-vis spectra and no bond alteration in the benzene rings of their crystal structures were observed, while the split Soret bands and the obvious bond alteration in their benzene rings were recorded in the case of opp-dibenzoporphyrin.
EXPLORING THE FOLDING FREE ENERGY LANDSCAPE OF SMALL RNA MOLECULES BY SINGLE-PAIR FÖRSTER RESONANCE ENERGY TRANSFER
Authors: KOBITSKI ANDREI YU. , NIERTH ALEXANDER , HENGESBACH MARTIN , JÄSCHKE ANDRES , HELM MARK , NIENHAUS G. ULRICH
Published: March 2009

Proteins and RNA are biological macromolecules built from linear polymers. The process by which they fold into compact, well-defined, three-dimensional architectures to perform their functional tasks is still not well understood. It can be visualized by Brownian motion of an ensemble of molecules through a rugged energy landscape in search of an energy minimum corresponding to the native state. To explore the conformational energy landscape of small RNAs, single pair Förster resonance energy transfer (spFRET) experiments on solutions as well as on surface-immobilized samples have provided new insights. In this review, we focus on our recent work on two FRET-labeled small RNAs, the Diels-Alderase (DAse) ribozyme and the human mitochondrial tRNA Lys . For both RNAs, three different conformational states can be distinguished, and the associated mean FRET efficiencies provide clues about their structural properties. The systematic variation of their free energies with the concentration of Mg 2+ counterions was analyzed quantitatively by using a thermodynamic model that separates conformational changes from Mg 2+ binding. Furthermore, time-resolved spFRET studies on immobilized DAse reveal slow interconversions between intermediate and folded states on the time scale of ~ 100 ms. The quantitative data obtained from spFRET experiments may likely assist in the further development of theories and models addressing the folding dynamics and (counterion-dependent) energetics of RNA molecules.
CMOS Compatible RF MEMS Switches with Serpentine Springs
Authors: Evans Xiao L. , Gamble H.S. , Baine P.T. , Mitchell S.J.N. , Montgomery J. , Bain M.F. , Rainey P.V. , Bien D.C.S
Published: March 2009

This paper describes a serpentine flexure spring design and fabrication process development for radio frequency microelectromechanical (RF MEMS) capacitive switches with coplanar waveguide (CPW) lines. Sputtered tungsten is employed as the CPW line conductor instead of Au, a non-Si compatible material. The bridge membrane is fabricated from Al. The materials and fabrication process can be integrated with CMOS and SOI technology to reduce cost. Results show the MEMS switch has excellent performance with insertion loss 0.3dB, return loss -27dB at 30GHz and high isolation -30dB at 40GHz. The process developed promises to simplify the design and fabrication of RF MEMS on silicon.
Minimizing Device Variation Caused by RTA Temperature Variation Across the Shot Field
Authors: Ju Jianhua , Liu Eric , Dai Shugang , Zhou Allan , Shen Zhaoxu , Liu Jinhua , Wang Brisk , Deng Daniel , Tang Julie , Hung Albert , Ho Hokmin , Ning Jay
Published: March 2009

Spike Rapid Thermal Annealing (RTA) is commonly used method for source and drain dopant activation in 65nm CMOS technology. It is found that the Idsat variation is very sensitive to RTA temperature. To better control the Idsat uniformity across the shot, a systematic study on STI and poly pattern density distribution across the shot field and their effects on the RTA temperature was carried out. It was demonstrated that the STI and poly pattern density variation across the field will result in more than 10ºC RTA temperature variation. To minimize the effect, an optimization of RTA ramp rate and peak temperature was studied. Source/drain (S/D) extension and S/D implant optimization has also been done for the reduction of PMOS device Idsat temperature sensitivity
Electrical Characterization of W/Hfo2 MOSFETs with La2O3 Incorporation
Authors: Fujisawa Hiroki , Srivastava Asutosh , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Sugii Nobuyuki , Hattori Takeo , Sarkar Chandan K. , Iwai Hiroshi
Published: March 2009

Hf based oxides have been used to replace siO2 gate insulator for advanced CMOS technologies. Recently,La2O3 has attracted much attention as it can control the threshold voltage to negative direction. In this paper,the effect of La2O3 incorporation to HfO2 gated MOSFET on mobility and interfacial properties are investigated.A shift in threshold voltage to negative direction had been observed with La2O3 incorporation. Moreover,gm and subthreshold slope have been improved with La2O3.1/f noise measurement has revealed that HfO2 gated MOSFET with incorporating La2O3 layer reduce the noise level.
The Impact of Shallow Trench Isolation on the Channel Hot Electron Programming Behaviors of SONOS Cells
Authors: Li Zhiguo , Yang Fan , Wang Joshua , Lin Peter , Chang Jianguang , Wang Youngor , Yi Champion , Yan Feng
Published: March 2009

As scaling down of the flash memory cell size continues, the impact of shallow trench isolation(STI) on active area(AA) in cell array becomes much more severe. Two types of influence have been reported: i) boron segregation: boron atoms at AA corner around STI tend to diffuse out, which induces lower boron concentration at AA corners; ii) STI stress: a compressive stress, coming from STI. The former may cause lower threshold voltage of edge cells. The latter will reduce the electron mobility, leading to higher threshold voltage for n-channel cells. In this work, we have studied the impact of STI on the channel hot electron programming behaviors of SONOS cells on single cell and array level. It has been found that the programmability of cells adjacent to STI is different from that of center cells. Boron segregation will substantially decrease the program efficiency while the stress will increase the initial programming voltage. In this paper, the impact of STI on edge cells will be reported and compared with the simulation results.
Bistable Resistance Switching of Cu/Ti:ZrO2/Pt for Nonvolatile Memory Application
Authors: Liu Qi , Long Shibing , Wang Qin , Liu Ming , Zhang Sen , Chen Junning
Published: March 2009

Resistive switching characteristics of Ti doped ZrO2 films are investigated for nonvolatile memory applications. The devices are with a metal-insulator-metal structure adopting Ti doped ZrO2 films sandwiched between top Cu electrode and bottom Pt electrode. Both DC and pulse voltage can trigger the switching between high resistance state and low resistance state. The ratio between the high and low resistance can be on the order of 104 after more than 250 switching cycles. In voltage pulse mode, "write" and "erase" operation can be as fast as 5 ns and 100 ns, respectively. Furthermore, no data loss is found for more than 106 seconds. Finally, the switching mechanism is exploited and concluded to be related with the formation and rupture of conducting filamentary paths.
Bit Cost Scalable (BiCS) Flash Technology for Future Ultra High Density Storage Devices
Authors: Nitayama Akihiro , Aochi Hideaki
Published: March 2009

We've proposed Bit Cost Scalable (BiCS) technology which realizes a 3D multi-stacked memory array with a few critical lithography steps regardless of number of stacked layers to keep a drastically continuous reduction of bit cost. The cell array concept, fabrication process, and key features are presented.
Investigations on the Impact of the Parasitic Bottom Transistor in Gate-All-Around Silicon Nanowire SONOS Memory Cells Fabricated on Bulk Si Substrate
Authors: Ai Yujie , Huang Ru , Wang Yiqun , Zhuge Jing , Wu Dake , Wang Runsheng , Tang Poren , Zhang Lijie , Hao Zhihua , Wang Yangyuan
Published: March 2009

Gate-all-around (GAA) Si nanowire SONOS memory cells (SNWMs) have been fabricated on Si substrate using fully epi-free compatible CMOS technology. A parasitic bottom SONOS memory (PBM) was formed when the SNWM was fabricated on bulk Si substrate. The impact of the PBM on the performance of the SNWM is investigated in this paper. The PBM shows a slower program speed, a faster erase speed, and worse retention characteristics than the SNWM. Therefore, the PBM severely degrades the performance of the SNWM due to its slower program speed and worse retention characteristics, and should be carefully controlled for the SNWM based on bulk Si substrate.
Halo Implantation Optimization for 65nm Low Power PMOS Device Inverse Narrow Width Effect Improvement
Authors: Ye Haohua , Ju Jianhua , Shi Xuejie , Liu Bing-Wu , Ning Jay , Chen I. C.
Published: March 2009

Device with shallow trench isolation (STI) has inverse narrow width effect (INWE), that is the threshold voltage of narrow width transistors is lower than that of large width transistors. The conventional methods of improving INWE focus on STI module optimization, such as active area corner rounding, step height and divot control. In this paper, a new approach by implant optimization is proposed to improve INWE. For low power PMOS device, phosphorus halo implant is often used for its lower diode leakage characteristics. This paper reports optimized dual halo implant approach with both arsenic and phosphorus implants to improve INWE. This approach gives larger Gm*Rout and lower digital product chip stand-by current without reliability degradation.
Shallow Trench Isolation Stress Effect on NMOS Transistor Leakage, SRAM Standby Current and VCCMIN
Authors: Ju Jianhua , Liu Eric , Shen Zhaoxu , Zhou Allan , Liu Jinhua , Deng Daniel , Ren Cathy , Wei Susu , Ho Hokmin , Ning Jay
Published: March 2009

Three key process steps in shallow trench isolation (STI) technology: STI liner oxide, STI to AA step height, and annealing temperature. Their impacts on NMOS devices leakage, SRAM standby current and Vccmin have been studied. MOSFET transistors off state current (Ioff) and body current (IB) were measured at varied length of diffusion (LOD) for STI stress effect analysis. For low power NMOSFET transistors, IB is seen to be the main part of Ioff and has a strong correlation to the processes that modulates STI stress. The experiment results show that the STI stress level can be much reduced by decreasing STI oxide RTA temperature and liner ox thickness, hence leading to lower IB and SRAM standby current. It is also demonstrated that SRAM Vccmin can be improved ~10% by STI stress reduction.
A High Performance 80V Smart LDMOS Power Device Based on Thin SOI Technology
Authors: Sheu Gene N. , Hsu Yushan , Yang Shao-Ming
Published: March 2009

The high junction leakages, circuit latched issues, and high parasite capacitances happened in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 190 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.
Investigation of Power MOSFET with Strained SiGe Channel
Authors: Sun Shan , Zhou Wei , Yan Liren , Xu Jun , Yuan Jiann S , Shen Zheng
Published: March 2009

Two trench-gated power MOSFETs using strained SiGe channel are proposed to further reduce specific on-state resistance. The first is a multiple SiGe and Si layer structure for N-channel MOSFET. A 30nm Si0.85Ge0.15 layer and a 50nm Silicon layer are grown by RPCVD alternatively to achieve sufficient channel length which is longer than critical thickness before the trench etches. The second method is to form the strained SiGe layer along the trench sidewall for P-channel MOSFET. A single Si0.85Ge0.15 layer of 30nm thick is grown after the trench etches. It is expected that the channel mobility in the vertical direction will be increased by up to 40% and 60% for electrons and holes respectively compared to conventional silicon device with same structure and doping profile. The on-state resistance is predicted to be reduced by 12% and 20% for N-channel and P-channel MOSFET accordingly.
Simulation of Retention Characteristics for Metal Nanocrystal Nonvolatile Memory with a Modified Direct Tunneling Model
Authors: Li Yingtao , Liu Ming , Long Shibing , Wang Qin , Liu Qi , Zhang Sen , Wang Yan , Zuo Qingyun , Liu Su
Published: March 2009

By comparing the impacts of Coulomb blockade eﬀect and quantum conﬁnement eﬀect on the energy band shift of metal nanocrystal, it is obvious that not only quantum conﬁnement eﬀect but Coulomb blockade eﬀect could influence the energy band shift of metal nanocrystal. Taking into consideration these two eﬀects, a modified direct tunneling model and numerical calculations is proposed for describing the retention characteristics of metal nanocrystal nonvolatile memories completely. The simulation results which compare well with experimental data show that the retention characteristics are not only dependent on tunneling dielectric thickness, but significantly relational to the barrier height, dielectric constant, as well as the nanocrystal coverage ratio.
Metrology Requirements for the 32 nm Technology Node and Beyond
Authors: Allgair John , Bunday Benjamin , Cordes Aaron , Lipscomb Pete , Godwin Milt , Vartanian Victor , Bishop Michael , Arazi Doron , Kim Kye-Weon
Published: March 2009

Successful in-line metrology is imperative for a fab to achieve profitable production yields. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success and is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of mission-critical production processes. This article gives a high-level overview of the findings of the ISMI metrology program and details some of the major approaching manufacturing challenges.
Advanced 3D-AFM Metrology for Sidewall Spacers
Authors: Bao Tianming , Ukraintsev Vladimir , Dawson Dean
Published: March 2009

Gate spacer engineering has become one of the primary concerns in dimensional metrology for semiconductor manufacturing process control. In composite spacers, deposition and etch of each spacer determine where the transistor source/drain implants occur. The sidewall spacer thickness and profile, especially at the feature bottom, is critical to be characterized and controlled by applicable 3D metrology. This paper discusses recent advances in 3D atomic force microscopy (3D-AFM) that solve the specialized characterization needs for critical sidewall spacer geometry controls, including multiple spacer thickness and nitride spacer pulldown. 3D-AFM metrology measures with greater accuracy such typical gate spacer parameters as linewidth, height, pitch, sidewall profile, sidewall angle (SWA), line edge roughness (LER), and line width variation (LWV), and sidewall roughness (SWR).
Evolution of Wafer Inspection and Review Methodology
Authors: Chang Ellis , Park Allen
Published: March 2009

Since the introduction of KLA 2000 series systems in mid 1980, Semiconductor manufacturing has widely adopted automated wafer inspection to detect defects during manufacturing to mitigate excursion and to reduce overall defect density. While the earlier emphasis in yield management was to detect the smallest defect possible, current environment calls for changes in both inspection and post processing technique that lead to identification of yield relevant defects in an efficient manner. Industry calls for intelligent way of inspecting the most critical areas on a device with high sensitivity and post inspection technique that utilizes advance techniques to generate defect pareto that highlights most important issues in defect data. Such methods are needed to meet both technical and financial goals of semiconductor companies.
Use FPGA Configuration Memory For Backend Defect Capture
Authors: Qian Gang , Shi Jian Jun
Published: March 2009

In deep sub-micro era, with the increase of circuit complexity, more and more metal layers are used for inter-connection. Chance for killing defects coming from backend metal layers is significantly increased. Especially for lower metal layers with smaller features, defects on them may be difficult detected by conventional current-based isolation techniques. Therefore development of defect monitoring method becomes critical for wafer fabrication yield improvement. SRAM-based FPGA is already well known for front-end defect capture capability. With the dense and segmented data-line structure, it is also a good vehicle for lower metal layer defect detection. In this paper, we will go through the architecture of a 90nm FPGA and its configuration SRAM. By study the electrical data-line failure signature, we will discuss the corresponding isolation techniques. Finally we will show some defects captured by this methodology.
Si-O Bond-breakage Energetics Under Consideration of the Whole Crystal
Authors: Tyaginov Stanislav E. , Sverdlov Viktor , Gös Wolfgang , Schwaha Philipp , Heinzl Rene , Stimpfl Franz , Grasser Tibor
Published: March 2009

We extend the McPherson model for Si-O bond-breakage energetics, which considers only a single SiO4 tetrahedron, in a way to capture the effect of the whole crystal. No ledge in the direction assumed in the McPherson model was revealed. Instead, potential profiles feature a saddle point in a different direction. The activation energy for bond-breakage is found to be rather high (~ 6 eV). This suggests that the interaction with the electric field alone is not sufficient for bond rupture. The breakage rate calculated for a bond weakened by hole capture is comparable to that of the McPherson model. We conclude that only the common action of an electric field and other factors (structural disorder and/or energy delivered by particles, e.g. hot carriers) can result in bond-breakage.
Power-aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing
Authors: Yamato Yuta , Wen Xiaoqing , Miyase Kohei , Furukawa Hiroshi , Kajihara Seiji
Published: March 2009

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing without the need of any circuit modification. However, the effect achieved by previous X-filling methods for reducing launch switching activity may be far from optimal. In addition, some of them are not scalable. This paper proposes a new X-filling method based on the genetic algorithm (GA). Experimental results on benchmark circuits demonstrate the effectiveness and scalability of the new X-filling method for reducing launch switching activity.
Yield Learning Through Scan Diagnosis
Authors: Huang Yu , Cheng Wu-Tung
Published: March 2009

Increasing design complexities conspire to threaten long held assumptions about the predictability of design closure. Yield learning and ramp up become a very important issue in industry. High volume scan-based manufacturing diagnosis and data mining can be exploited as a capable contributor to identify systematic defects that have been the most important yield limiter. In this paper, this methodology will be illustrated by a few case studies.
A Low Power Architecture based on Unidirectional Cut
Authors: Chen Zhen , Xiang Dong
Published: March 2009

Test power of a circuit mainly consists of capture power and shift power. In this paper, a new scan architecture is proposed to reduce both of them. In the architecture, a new graph algorithm is proposed to partition the scan flip-flops into two parts and then the ones with common successors in each part are grouped as a chain. By partitioning the scan flip-flops into two parts, the process of capture is cut into two sequential steps. This technique can effectively reduce the capture power. Using the clock disabling scheme, we can make sure that, only one or a small portion of scan chains are active during the shifting phase. Therefore, the peak power and average power are reduced. This architecture can effectively reduce the test time too. Experimental result shows that average power and peak power reduction are very significant, compared with the ordinary full-scan architecture.
A Self-Repairable Microprocessor
Authors: Xie Yuanjiang , Fu Xiang , He Zijian , Zhao Yang , Hu Yu , Li Xiaowei
Published: March 2009

With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique.
Improved Cost of Test by Optimized Tester Utilization
Authors: Jeserer Günther
Published: March 2009

The semiconductor test industry agrees that cost of test (CoT) is one of the biggest challenges today and it will be crucial in future. Test cell efficiency needs to be increased. Enhanced tester capabilities allow shorter test times and higher parallelism. Handlers try to keep pace with higher parallelism but missmatch with speed. The urgent challenge is to optimize the tester utilization in order to benefit from higher parallelism as well as from shorter test times. The solution needs to improve the overall handler preformance. Increasing the number of contact sites will not be sufficient. In addition speed related parameters like soak capacity, index time and loading and sorting speed need to be considered.
Electromigration Improvement for Advanced Technology Nodes
Authors: Wu Hui-Jung , Wu Wen , Shaviv Roey , Sriram Mandy , Pradhan Anshu , Park Kie Jin , O'Loughlin Jennifer , Chattopadhyay Kaushik , Mountsier Tom , Dixit Girish
Published: March 2009

Electromigration (EM) reliability has become a growing concern for Cu interconnects in advanced technology nodes. The interface between the dielectric diffusion barrier (SiCN) and copper, metal barrier quality and metallization homogeneity are all critical to EM performance. Our EM enhancement investigation has focused on improving the SiCN/Cu interface, metal barrier quality and metallization homogeneity while mitigating the process integration risk and cost. Multiple processes developed at Novellus have demonstrated significant EM improvement without compromising stress migration or dielectric reliability. The results of these process developments and the mechanisms of EM improvement will be discussed in this paper.
Use of MIR-FTIR and k-value Measurements to Assess Potential Solutions to Reduce Damage During Porous Low-k Integration
Authors: Beynet Julien , De Roest David , Rochat Nevine , Kellens Kristof , Verdonck Patrick , Sprey Hessel
Published: March 2009

Multiple Internal Reflection (MIR) FTIR is used to assess the impact of potentially damaging BEOL integration process steps such as Chemical Mechanical Polishing (CMP) and NH3-based plasmas on a k=2.55 porous interlayer dielectric. The NH3 plasma is found to be very damaging, and a He plasma prior to the same NH3 plasma leads to a damage reduction. The impact of CMP is also confirmed and leads to an equivalent k-value degradation as a He + NH3 plasma. In order to reduce the integration damage, the addition of a low-k protective cap layer (k=3.3) is proposed. The required thickness to avoid impact from CMP and NH3-based plasmas is found to be 10 nm after CMP (Kstack=2.60 with 10 nm cap). As a result, those process steps are no longer a concern with this integration route.
Optimization of Nickel Salicide Strip Process Using Taguchi Method
Authors: Yu Shelby , Li Wenshen , Lin Chi Liang , Lu Yii-Chian
Published: March 2009

A one-step strip scheme of NiPt salicide has been developed to replace an existing two-step strip scheme for better throughput and defects. Taguchi method was utilized to fine-tune three key process factors including thickness of nickel, temperature and duration of the NiSi RTP-1. Optimization was obtained considering the complicated salicide formation such as crystalline structure, dopant type, and dimension of Si. Using signal-to-noise ratio analysis, ANOVA, and multi-objectives compromise, an optimal process was achieved with significant improvements in resistance shift, resistance uniformity, salicide surface roughness, and reverse linewidth effect.
Inverse Lithography Technology (ILT) Enabled Source Mask Optimization (SMO)
Authors: Pang Linyong , Xiao Guangming , Tolani Vikram , Hu Peter , Cecil Tom , Dam Thuc , Baik Ki-Ho , Gleason Bob
Published: March 2009

In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask. This approach has been successfully applied to explore and select lithography processes and design rules for advanced semiconductor technology nodes. In Luminescent's latest implimentation of ILT-enabled SMO, the same Level Set Method used in the mask optimization is used in the source optimization; in other words, the source map is represented by a level set function. During the optimization process, the level set function evolves to achieve a minimized cost function, where the cost function is defined as the difference between aerial image and ideal image (MEEF and DOF can also be used in the cost function) via a gradient flow, and the gradient flow is based on the cost function itself. This flow is interlaceded with the mask inversion flow so that a simultaneous mask & source co-optimization is achieved. In this paper a number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of ILT-enabled SMO.
OPC Accuracy and Development Time Improvement for Advanced Technology Nodes
Authors: Nikolsky Peter , Nooitgedagt Tjitte , Van Adrichem Paul , Meessen Jeroen , Kohler Carsten , Wisse Baukje , Hunsche Stefan
Published: March 2009

Double Dipole (DDL), Double Patterning (DP), Spacers and other advanced process technologies require an enormous amount of CD and tool data collection and development time for OPC modeling. In this paper we studied a way to reduce the overall OPC preparation time and increase the OPC accuracy by early and accurate collection of the OPC measurements, automatic CD-SEM recipe generation and CD data analysis and model calibration with Brion's Tachyon software. We reviewed the design of the OPC test chip, OPC exposures, data analysis and OPC modeling on the advanced and accurate Tachyon T2.0 OPC platform and ways to improve modeling cycle time. Another critical parameter of the OPC modeling is accuracy as one of the main parts of the CD error budget. We investigated approaches to OPC modeling accuracy and achieved RMS below 1nm for critical features by using module data of the respective ASML TWINSCAN XT:1900i scanner.
Hot-Spots Aware Inverse Lithography Technology
Authors: Yang Yiwei , Shi Zheng , Shen Shanhu , Xie Chunlei
Published: March 2009

This paper presents a new method of Inverse Lithography Technology (ILT) to accelerate its optimization process and convergence, which involves two steps in iteration: the first step is to find hot-spots in the layout in the optimization process and the second step is to optimize on the hot-spot areas. Information in optimization process such as gradient can be used in the first step to help finding the hot-spots. Optimized surroundings have been used as environment for local hot-spot fixing in the second step. In order to reduce ripple effects, specific penalty terms are used in the second step, thus the local fixing for hot-spots would minimally affect the surroundings through the procedure. This method focuses on the most un-optimized places and thus accelerates the optimization. Experiments show that this hot-spots aware ILT outperforms traditional ILT.
Novel Embedded Barrier Layer Materials for ArF Non-topcoat Immersion Applications
Authors: Wang Deyan , Wu Chunyi J. , Xu Cheng Bai , Barclay George , Trefonas Peter , Xu Min
Published: March 2009

With the decrease in pitch in the line/space patterning, micro-bridge defects have become the major defect in the immersion applications. As a result, reducing micro-bridge defect count is one of the key tasks for mass production of semiconductor devices using immersion lithography for both topcoat and non-topcoat processes. In this paper, we focus on the non-topcoat approach particularly the embedded barrier layer (EBL) technology1-4. The advanced EBL materials discussed in this paper have demonstrated to be able to reduce total defect including micro-bridge defect count to the same level as that of a topcoat process. It was found that the developer solubility of the EBL materials in both bright and dark fields and the contrast of the EBL materials play important roles for reducing overall defectivity.
Study on CMP Mechanism and Technology of Sapphire Substrate for Photo-conducting Device
Authors: Niu Xinhuan , Wu Tao , Zhao Xiaohong , Tan Baimei , Liu Y. L.
Published: March 2009

Sapphire(α-Al2O3) single crystals are widely used in many areas because of the special properties. As an important photoconducting device substrate material, stringent surface quality requirements are required. The use of CMP technique can produce high quality surface finishes at low cost and with fast material removal rates. In this paper, the polishing mechanism was studied. According to Arrhenius equation, temperature is the important factor of influencing chemical reaction rate. So the chosen temperature was 45°. SiO2 sol was chosen as abrasive, and the particle size is 40nm. For ensuring the stability of abrasive and chemical action of polishing slurry, the pH value was determined at 11.5~12. After polishing and cleaning the sapphire surface, the measured removal rate was above 11μm /h and the surface roughness was Ra 0.3nm. From the results, it was found that using such method, the optimal sapphire surface can be gotten.
Investigation of Defects in Post-CuCMP
Authors: Xiong Shiwei , Huang Simon , Yang Yifan , Tan Changxing , Wang Shan , Zhao Runtao , Xu Jerry
Published: March 2009

In this paper, two particular kinds of defects are investigated. The number of Queue-time defects is strongly impacted by environmental conditions. In the ambient environment, Q-time defects form easily and the number increases greatly with longer queue time. Q-time defect growth can be suppressed indefinitely by storing queued wafers under vacuum or in a nitrogen environment. SEM and EDX analyses show that Q-time defects mostly occur along the Cu line edge and are mainly very small Cu oxide particles. The formation mechanism of Q-time defects is discussed. Another commonly encountered defect - Cu metal missing - which is associated more commonly with previous processing steps, is also discussed.
Study On The Electro-Chemical Cleaning Technique with BDD Film Anode to Preparation of Electronic Devices
Authors: Gao Baohong , Zhu Yadong , Liu Yuling , Niu Xinhuan , Zhang Jianxin , Liu Xiaoyan , Li Li
Published: March 2009

Microelectronic devices are the core of the information products, and one of the key points of it is the cleaning techniques. The cleaning progresses and technology have great influence on the qualities, the price and the competition of the products. The boron-doped diamond (BDD) electrode has a very low capacitance and extreme electrochemical stability, and the BDD electrode was used as anode for ozone generation system through electrolysis of acidic solution. Therefore, the excellent oxidation property of BDD electrode was confirmed and the possibility of further various applications in the cleaning system instead of ozone was expected. This paper presents a new cleaning technology combined electrochemical cleaning, which using BDD film anode with special chemical agents, called electro-chemical cleaning method for short. The principle of the electrochemical progress and some experiment in point was also discussed in this paper.
Cu/Low-k Thickness Measurement for Advanced Cu CMP Process Development and Control
Authors: Li Yunlong , Heylen Nancy , Delande Tinne , Kellens Kristof , Ong Patrick , Leunissen Leonardus , Tarnowka Alexandre , Eliyahu Aviv
Published: March 2009

We investigated a wafer level Cu/low-k thickness measurement technique and compared it to the electrical and surface profiling techniques. With this optical technique, we can achieve a comprehensive within-die and within-wafer Cu/low-k thickness monitoring which allows for a more accurate Cu CMP process control in advance Cu/low-k damascene structures.
Cu/barrier CMP Protection Film Characterization Using Electrochemical Technique
Authors: Xu Sunny
Published: March 2009

As reported in a previous paper, electrochemical data not only can provide the information about Cu corrosion protection, but also can be correlated with slurry CMP performance. In this paper, further study on thermal stability of protection film and Cu planarization efficiency are carried out. Some surface related defect studies correlated with electrochemical data are also discussed.
Single Dispersion to Polish both Bulk Cu and Residual Cu along with Barrier Layers
Authors: Janjam Sathish Babu , Roy Deepankar , Babu S V.
Published: March 2009

Integration of Cu/Ta/low-k dielectric structures requires that chemical mechanical planarization (CMP) of Cu lines and barrier layers be performed at low down pressures (~2 psi) to avoid damages to the underlying fragile dielectrics. At the same time, to avoid loss of throughput, the chemical activity of the slurry must be increased. We report an approach to slurry engineering that can help to achieve these goals in CMP of Cu/Ta/TaN over low-k dielectrics. These slurries employ silica abrasives in a single dispersion of oxalic and tartaric acids, with the objective of removing both Cu lines and Ta/TaN barrier layers simply by varying the operating slurry pH. In this approach, bulk Cu can be removed at high rates and residual Cu can be removed at lower rates (to minimize dishing) by adjusting the pH and the H2O2 content of the slurries. Ta/TaN can also be removed at good polish rates.
Ultra-High Removal Rate Copper CMP Slurry Development for 3D Application
Authors: Hu Bin , Kim H. , Wen R. , Mahulikar Deepak
Published: March 2009

Chemical-mechanical planarization (CMP) has been widely accepted in IC manufacturing. With technology moves to 45 nm and beyond, the challenge of continuous reduction of interconnect features resulting in the increased Cu line resistivity. To mitigate this effect 3-D packaging where through-silicon vias (TSV) are filled with electroplated Cu can be used. A moderately high removal rate slurry, ER9200 was developed and the work was presented elsewhere (ICPT Taiwan Conference Nov. 2008). However certain 3D structures have very thick Cu overburden. For such structures ultra high removal rates of 4~5 µm/min may be needed. This process requires a high speed Cu CMP process to remove the thick overburden Cu layer. Presented herein is a Cu CMP slurry with ultra-high removal rate, yet good Planarization Efficiency and low defects. This new colloidal silica based developmental slurry achieves much higher removal rate, and is suitable for Cu 3D CMP application.
Effect of H2O2 Concentration and Slurry Dilution on Removal Rate and Surface Quality for a Cu Slurry
Authors: Lin Jie , Du Tianbao
Published: March 2009

The effects of H2O2 concentration and slurry dilution on Cu removal rate and surface quality were investigated for a colloidal silica-based slurry. At 1:6 dilution, the Cu removal rate increased with increasing H2O2 concentration, reaching a maximum at 0.90 wt% (H2O2 threshold concentration), and then decreasing and leveling off at higher H2O2 concentrations. A smooth Cu surface was obtained above the H2O2 threshold, but a rough Cu surface was produced below the H2O2 threshold. At higher dilutions of 1:8 and 1:10, similar effects of H2O2 concentration on Cu removal rates and surface qualities were observed, but the H2O2 threshold shifted down to 0.74 and 0.66 %, respectively. Electrochemical measurements explain the observation of a rough Cu surface below the H2O2 threshold, and a smooth Cu surface above the H2O2 threshold.
Controlled DI Water Gasification System for Advanced Semiconductor Cleaning Processes
Authors: Xia Annie , Niermeyer Karl , Conner Gregg , Mollica Russ
Published: March 2009

Driven by continually shrinking feature sizes and adoption of ever more fragile materials in IC manufacturing, it has become crucial to develop effective and low impact processes that are benign to features on wafers. Recently, there is increasing interest in using gasified DI water in photolithography, wet etch & clean, mask clean and CMP applications. In this paper, we describe the design and development of an automated in-line CO2 gasification system using Entegris all PFA hollow fiber membrane-based contactors. The paper addresses key system design features to enable a responsive and seamless process with minimum system downtime. Capacity and control data demonstrating the versatility and robustness of the system will also be presented.
A Matching Game for CMP Pads and Conditioners
Authors: Sun Fred F. , Hawkins Joe , Tsai Jimmie , Chiu George , Naman Ananth
Published: March 2009

The relationship between a pad and a conditioner may be the most critical among all "consumables" in a CMP process. The effect of a pad conditioner on pad can be both short-term (instant) and long-term (stability). This paper compares the instantaneous effect of different conditioners on removal rate of oxide, tungsten, and copper CMP. The impact of conditioners in removal profile in copper polishing and rate stability (long-term) in oxide polishing are also presented. The pad wear rate by conditioners of different aggressiveness on Epic® D100 vs. conventional hard pad is compared and the benefits and risks of adopting a more aggressive conditioning on Epic® D100 pad vs. a less aggressive conditioning on conventional pad is discussed.
Polycrystalline Diamond (PCD) Shaving Dresser: The Ultimate Diamond Disk (UDD) for CMP Pad Conditioning
Authors: Sung James C. , Chou Cheng-Shiang , Chen Ying-Tung , Chou Chih-Chung , Pai Yang-Liang , Hu Shao-Chung , Sung Michael
Published: March 2009

All conventional pad conditioners dress the CMP pad with discrete diamond grits of random orientation. With the advent of polycrystalline diamond (PCD) dressers, the pad conditioning can be performed with an unprecedented regularity. The result is a total elimination of "killer asperities" that may scratch the soft copper layer or porous dielectric layer. Moreover, the PCD dressers may be constructed to form a blade shaver so pad disruption during conditioning can be minimized. As a result, the original pad polymers can be preserved for polishing wafers. This ultimate diamond disk (UDD) has transformed stick slipping pad destruction to smooth shaving pad construction. UDD is particularly suitable for dressing CMP pads for polishing 22 nm interconnects, in particularly, with the anticipated debut of 450 mm pancake wafers scheduled for 2012.
Development of CMP Conditioner for Sub-50 nm Technology Nodes
Authors: Hwang Taewook , Vedantham Rama , Zhang Simon
Published: March 2009

Several key conditioner design parameters including diamond size, shape, and concentration were selected and optimized to tune wafer removal rate and pad cut rate for various types of CMP pads. Among various diamond types, two types of diamonds were selected for conditioner applications and numerous conditioners were manufactured to generate pad surface roughness on a regular polyurethane porous pad, hard porous pad, and hard solid pad. Furthermore pad cut rate stability curves and wafer removal rate were generated to correlate conditioner design with pad surface texture and wafer removal rate and defects. Experimental results revealed the effect of conditioner design on pad surface roughness was significant and wafer removal rate varied significantly depending on a specific set of conditioner and pad.
Poly-CMP Slurry for Flash Memories
Authors: Jing Jianfe , Chiu Bryan , Huang Travis , Hsu Arthur , Yang Chunxiao , Yu Chris
Published: March 2009

To prepare a floating gate or control gate, a poly-silicon (poly) layer will be deposited on the active area, which is between the STI trench structures, typically HDP oxide. Then through CMP technique, the overburdened poly will be removed, with no poly residue on the top of HDP surface and leaving a certain thickness of AA poly whose top surface is planar with HDP top surface. However, in the case that a poly layer and a silicon dioxide layer are being polished, the removal rate of poly-silicon will tend to be much higher than that of silicon dioxide, resulting in recess between the STI trench structures and a non-planar surface. To overcome this issue, we report here a novel poly CMP slurry that has the self-stopping capability and good planarization efficiency, with which the excellent surface planarity, poly dishing and poly residue clearance were obtained on 300 mm pattern wafer.
Solving Arcing Issues in CVD Processes
Authors: Yan Evan , Xu Jerry , Li Xianyuan , Chen James , Chen Yingjie , Zhao Dae Joo , Chan Lanchia , Ji Lily , Padhi Deenesh , Zhang Bob
Published: March 2009

As the semiconductor industry continues to scale feature sizes, higher deposition/etch rate and better gap-fill abilities are continuously required for chemical vapor deposition (CVD) and other processes. To achieve higher deposition rates, higher plasma power and density are required, which can lead to plasma arcing. Arcing is a severe issue common to CVD processing. Minor arcing can generate particles/defects. Severe arcing can completely destroy wafers and reactor components. In this paper, three typical arcing cases are examined using a 300mm CVD system. These include chamber body arcing using a high density plasma (HDP) phosphosilicate glass (PSG) chamber, electrostatic chuck (ESC) arcing using an HDP undoped silicate glass (USG) chamber, and wafer arcing with an advanced patterning film (APF) chamber. In each case, root causes were established and solutions to prevent arcing were demonstrated. Brief theories of arcing in CVD processes and arcing detection methods are also discussed.