bluuebunny/crossref_metadata_2025 huggingface dataset:
Characterization Complex Voltage Contrast Image Using Atomic Force Microscopy
Authors: Chen C.H. , Shen C.M. , Huang C.M. , Hsia Y.F.
Published: December 2020

The passive voltage contrast (PVC) in this experiment was widely used to detect open/short issues for most failure analyses. However, most of back-end particles were visible, but front-end particles were not. And sometimes only used PVC image, the failure mechanism was un-imaginable. As a result, we needed to collect some electrical data to explain complex PVC image, before physical failure analysis (PFA) was started. This paper shows how to use the scanning probe microscope (SPM) tool to make up PVC method and overcome the physical failure analysis challenge. From our experiment, the C-AFM could provide more information of the defect type and give faster feedback to production lines.
Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)
Authors: Qian Zhongling , Brillert Christof , Burmer Christian , Egger Peter
Published: December 2020

Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.
Correlation of Flash Memory Defects Detected With Passive and Active Localization Techniques
Authors: Quah A.C.T. , Phang J.C.H. , Li S. , Massoodi M. , Yuan C. , Koh L.S. , Chan K.H. , Chua C.M.
Published: December 2020

This article describes a series of experiments that were conducted on flash memory devices to correlate the defects that are detected by photon emission microscopy (PEM) and laser-induced techniques. Currently, there are two main categories of fault localization techniques for failure analysis, namely passive and active techniques. The article discusses defect localization by PEM and SOM. Three types of defects are described: Type 1 defects are those that can be accurately localized by both PEM and laser-induced techniques; Type 2 defects are defects which can only be detected with PEM and are not observable with laser-induced techniques; and Type 3 defects are those that are detectable with laser-induced techniques but cannot be detected by PEM. While PEM is able to capture the symptoms of existing leakage defects, laser-induced techniques can precisely localize temperature sensitive defects.
DuPont EKC265™ PERR as a Copper Metallization Etchant for the Physical Deprocessing of Failing 0.12 μm Technology Devices
Authors: Mulder Randal
Published: December 2020

DuPont EKC265 Post Etch Residue Remover has been available for many years as post reactive ion etch photo-resist etchant for semiconductor wafer processing. It has also proven useful for the physical analysis of failing semiconductor devices. This paper shows how EKC265 can be used as copper metallization wet etchant to aid in the physical deprocessing. It provides the EKC265 copper metallization etch results and physical deprocessing results using EKC265. An ancillary effect of wet etching copper metallization rather than removing by means of mechanical polishing is that only the thin layer of underlying barrier metal layer has to be removed by means of mechanical polishing. As the barrier metal is a metal-silicon nitride compound, the polishing rate to remove it is close to that of the surrounding oxide. Therefore, less total polishing time is required to remove the copper metallization layer when EKC is used.
Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis
Authors: Grilletto Carlo , Hsiung Steve , Komrowski Andrew , Soopikian John , Sullivan Daniel J.D. , Tan Kevan
Published: December 2020

This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.
SCM Application in Semiconductor Failure Analysis and Possible Solution for Well Inspection of Advanced Nanometer Process
Authors: Lin Coswin , Chao Chia-Hsing
Published: December 2020

Scanning capacitance microscopy (SCM) is a powerful technique that may readily be applied to semiconductor failure analysis yielding information on problems stemming from doping issues. This paper details the study of a current leakage failure and outlines the use of the SCM technique for shallow trench isolation applications. A two-step sample preparation technique involving firstly, Chemical Mechanical Polishing (CMP) followed by a wet etch, could improve the sample surface planarization allowing SCM inspection of the STI region.
Correction to 2003 Proceedings: ESD Failure Signature Differences in the Devices Core Logic and Protection Structures—A Case Study
Authors: Henry Leo G.
Published: December 2020

For certain programmable logic type devices, the electrical, morphological and failure location differences in the ESD signatures between ICC failures and I/O leakage failures have been identified. Based on these electrical, morphological and physical failure signature locations, this case study confirms that distinctions can be made between the signatures associated with the likely stress modes for pin combinations like I/O-to-Vss, I/O-to-Vcc, I/O-to-I/O, Vssto- Vcc and Vcc-to-Vss. This separation also facilitated the correct identification of core failures which are mostly due to the supply-to-supply pin combination stress, but in some cases are due to the pin-to-supply tests.
Quantitative Electrical Analysis of FIB Prepared Vias on BiCMOS and CMOS090 Designs
Authors: Domengès B. , Poirier P.
Published: December 2020

In this study, the resistance of FIB prepared vias was characterized by the Kelvin probe technique and their physical characteristics studied using cross-sectional analysis. Two domains of resistivity were isolated in relation to the ion beam current used for the deposition of the via metal (Pt). Also submicrometer vias were investigated on 4.2 µm deep metal lines of a BiCMOS aluminum based design and a CMOS 090 copper based one. It is shown that the controlling parameter is the shape and volume of the contact, and that the contact formation is favored by the amount of over-mill of the via into the metal line it will contact.
A Study of Low Leakage Failure Mechanism of X7R Multiple Layer Ceramic Capacitor (MLCC)
Authors: Wang Zhaofeng
Published: December 2020

This paper presents the result of a study of a particular failure mechanism of BaTiO3 MLCC (multiple layer ceramic capacitor). A unique technique of cross-section alternating with emission microscope analysis is developed to precisely locate the failure site for capacitors exhibiting low leakage current in μA range. Thermal Imaging Microscope, Photon Emission Microscope, SEM, STEM/EDS and TEM electron diffraction pattern are employed for the characterization of these low leakage failures. Evidence of high concentration impurities are detected in the dielectric layer of BaTiO3 grain boundaries as well as inside certain grains. TEM diffraction imaging at the failure site shows distinguishingly different diffraction patterns within the matrix of BaTiO3 crystal structure. The evidences point to a combination of impurities at grain boundaries and BaTiO3 crystal change induced by impurity as the failure mechanism.
Application of EDS Technique for OSP Film Thickness Measurement
Authors: Kongsubto Prong , Kongwudthiti Sirarat
Published: December 2020

Organic solderability preservatives (OSPs) pad is one of the pad finishing technologies where Cu pad is coated with a thin film of an organic material to protect Cu from oxidation during storage and many processes in IC manufacturing. Thickness of OSP film is a critical factor that we have to consider and control in order to achieve desirable joint strength. Until now, no non-destructive technique has been proposed to measure OSP thickness on substrate. This paper reports about the development of EDS technique for estimating OSP thickness, starting with determination of the EDS parameter followed by establishing the correlation between C/Cu ratio and OSP thickness and, finally, evaluating the accuracy of the EDS technique for OSP thickness measurement. EDS quantitative analysis was proved that it can be utilized for OSP thickness estimation.
A Fast Inspection of Well Implantation by Using Plane-View Stain Method
Authors: Lin Jian-Chang , Wu Wen-Sheng , Chen Kuo-Shiung , Yeh Jen-Hung , Hou Ying-Chin
Published: December 2020

In the field of failure analysis, electrical failures caused by improper implantation are often difficult to debug especially for fully processed products. Familiar implantation failure issues include improper implantation concentration, error doping types, incorrect doping ranges, and etc. Although some FA equipments, such as secondary ion mass spectrometry (SIMS), spreading resistance probe (SRP) and scanning capacitance microscope (SCM) [1] [2] [3], can do detail or quantitative analysis for these failure issues, most of these FA jobs are time-consuming and have a detection limitation at the size of failure area. This limitation may restrict the FA applications because the failure area is usually small at the fully processed products after fault isolation. In this paper, two examples with improper doping type and concentration will be analyzed by using a newly developed FA method. Instead of using traditional cross-section (X-S) stain method, we utilize a plane-view stain method to compare the doping type and doping concentration between normal and failed regions. With the aid of the plane-view stain method, we can have a quick check at the suspected failure area with improper front-end implantation before specific SCM analysis.
Voltage Noise and Jitter Measurement Using Time-Resolved Emission
Authors: Kasapi Steven , Woods Gary L.
Published: December 2020

In this paper, we demonstrate two applications of time-resolved emission (TRE): measurement of dynamic, local power-supply (Vdd) variations, and synchronous timing jitter induced by Vdd variations. The first technique measures the height of many peaks within a TRE waveform; differences in peak height are correlated with inter- pulse differences in Vdd. The second technique measures the timing of all of the peaks and extracts the inter-pulse timing variations. The measurement was automated and was performed on long (multiple-μs) acquisition windows containing hundreds of emission peaks. Our work advances the state of the art by using the peak heights and positions to extract this information, and by performing the measurements in an automated fashion.
The Techniques for Short Failure Isolation on Advanced Technology
Authors: Lin H. N. , Wang C. H. , Lin K. L. , Yang W. S. , Chen C. J.
Published: December 2020

Optical beam induced resistance change (OBIRCH) is one popular technique for isolating electrical shorts in process development test structures for 130nm and 110nm device technologies. However, OBIRCH inspection on 90nm technology is not always successful: since the OBIRCH signals of samples are very weak, or even comparable to noise. To overcome this, two alternative and complementary methods for isolating the failure have been developed. The first method is to calculate the coarse position of the defect directly from electrical resistance measurements. The second method is to enhance the OBIRCH signal using FIB circuit modification within the test structure. These methods can help locate defect at this structure by using electrical analysis only or enhancing the OBIRCH signal. The first method is an easy and quick method for short failure isolation, while the second can exactly locate the position of failure if the first method does not reveal a surface defect.
In Situ Electron Microscopy Study of Current-Induced Failure of Carbon Nanofibers
Authors: Suzuki Makoto , Ominami Yusuke , Ngo Quoc , Yang Cary Y. , Mcilwrath Kevin , Jarausch Konrad , Cassell Alan M. , Li Jun
Published: December 2020

We perform the in-situ scanning transmission electron microscopy (STEM) study of current capacity of carbon nanofibers (CNFs) suspended between two electrodes in vacuum. At an average current density of 4×106 A/cm2, CNFs show breakdown due to current stress. Current-induced failure results in many voids between graphitic layers in CNF, indicating that the structure of CNFs strongly affects their failure mechanism due to high current stress. These findings provide the insight of the failure mode of future carbon-based interconnects.
Effect of Die Chip-Outs and Reflow Temperature on the Mechanical Behavior of a 5-Die-Stacked Chip Scale Package
Authors: Evan Dennis , Balacano L. , De La Rama Lito P.
Published: December 2020

During package qualification, a 5-die-stacked chip scale package was being marginally triggered on high stand-by current collectively known as Power ICCS failure. Affected lots are subjected to 3x reflow at 240°C. Post reflow failures include blown_up, high standby current in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside is observed to propagate toward the active area on ISBLOQ failing units. Fracture analysis results show that the crack of the three failures all originated from die backside chip-out. Thermo-mechanical model of the package shows that, by design, Die 3 generates the highest stress concentration. Results show that if chip-outs are present on the area of the die with the highest stress concentration and the unit is subjected to reflow temperature of 240°C, die crack will propagate from the chip-out. This paper presents the unique failure mechanism observed on a 5-die-stacked chip scale package and the corrective actions applied to solve the issue.
A New Methodology for Electrical Debugging Short in Packages with the Modified Daisy-Chain Die
Authors: Hsiung Steve K. , Tan Kevan V. , Soopikian John
Published: December 2020

Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.
Masking Technique to Enable Multiple Site Defect Analysis on a Microchip
Authors: Hahn James
Published: December 2020

As feature sizes are shrinking beyond 130nm, fresh subsets of failures are coming to light. Multiple site defect analysis with adjacent block comparisons and multiple site comparative nanoprobing have become mandatory for these extraordinary and non-visible defects. There are instances where inspection or analysis will be required at multiple sites over a wide area on a sample. Traditional mechanical deprocessing techniques do not allow us to maintain planarity over a relatively large area, typically tens of microns. This article presents a 'masking technique' that addresses the issue of 'adjusting' the level at several local sites on a microchip. This technique can be utilized at all deprocessing levels of defect analysis and comparative circuit analysis and is time, tools, and labor efficient. Additionally, it enables multiple site nanoprobing, a preferred and essential tool for electrical validation of non-visible failures at technologies 90nm and beyond.
Failure Analysis Methodology for Li-Ion Incidents
Authors: Loud John , Hu Xiaoyun
Published: December 2020

The purpose of this article is to lay out a scientific methodology for investigating lithium ion (Li-ion) product failures. The discussion provides possible causes for an overheating Li-ion cell failure and covers processes involved in preventing Li-ion incidents. Performing a scientific root cause failure analysis involves systematically performing the failure analysis, which is explained in detail, to eliminate branches from the fault tree and arrive at the root cause of a given failure. Statistical analysis of Li-ion cells is provided, along with a recall determination of issues in Li-ion cells. The article also presents snapshots from actual Li-ion investigations selected from hundreds of investigations that have been performed by the authors at Exponent as far back as 1995.
Tool-Related ESD Surface Damage (ESDFOS) on Wafers in Cu-Technology
Authors: Jacob Peter , Hartfield Cheryl
Published: December 2020

In many cases it is difficult to distinguish mechanical damage from electrostatic surface impacts. In recent years, several investigations have resulted in publications on ESDFOS (Electrostatic Discharge From Outside to Surface). While the diagnostics of the phenomena have been worked out quite well for wafers with aluminum metallization, no formal studies on ESDFOS impact to copper-metallized wafers have been published. This paper investigates physical features of Cu-metallized wafers artificially exposed to ESDFOS impacts of variable severity, producing an understanding of damage features to more easily facilitate recognition of EDSFOS events.
Low keV FIB Applications for Circuit Edit
Authors: Rue Chad , Shepherd Randall , Hallstein Roy , Livengood Rick
Published: December 2020

Focused ion beam (FIB) tools are used to perform "circuit edit," (CE), in which existing integrated circuit devices are modified to create prototype devices that simulate potential mask changes. Although ion milling at low keV is common in TEM sample preparation, the technique has not become commonplace for CE applications. This is because most commercial FIB systems are optimized for either 30 or 50 keV. Recent work in the laboratories of FEI and Intel have attempted to apply low keV FIB processing to cutting small copper lines on advanced IC devices. The majority of this paper focuses on water-assisted, low keV copper etching. Secondary objectives of this work are to raise general awareness among FIB users of the potential benefits of low keV processing, to speculate on the physical mechanisms involved, and to discuss some of the technical difficulties associated with low keV FIB operation.
Novel Dielectric Etch Chemistry for the Next Generation of Circuit Edit: Delicate to Low-k Dielectrics and Silicon
Authors: Makarov Vladimir V. , Krasnobayev Leo , Misquitta Sabina F.
Published: December 2020

A novel solution is presented for dielectric and silicon etching when using FIB for circuit edit. In contrast to commonly used XeF2, the new solution has a significantly higher activation threshold that allows it to be used for etching new sensitive low-k dielectrics and even thin silicon without the risk of damaging these materials spontaneously. Examples of operations presented are: etching through ultra low-k dielectrics on a front side device, exposure of a conductor through shallow trench isolation (STI), and trimming active silicon when performing circuit edit on a back side device. The advantages in comparison to XeF2 applications are discussed.
Start up of a Dual Beam FIB for Automatic STEM Sample Preparation
Authors: Demarest James J. , DeSouza Zubin
Published: December 2020

This paper deals primarily with the difficulties and solutions to STEM sample preparation. The dual beam focused ion beam (DBFIB) whole wafer platforms often come with scripting features which allow the tool to operate with a high level of automation. The main focus of the paper is on the variety of challenges which are encountered in trying to implement automated STEM and TEM sample fabrication with minimal operator input and the engineering solutions implemented to overcome the challenges. The paper demonstrates that the challenges with making STEM and TEM samples in a highly automated fashion by DBFIB, while difficult, are not insurmountable. It has highlighted a mechanical issue with the ion aperture motor mechanism, which required extensive troubleshooting to fully diagnose and correct. A long standing software routine had to be modified to fully enable script automation by extending the beam dwell time of the automatic brightness contrast routine.
Laser-Thermal Imaging
Authors: Falk R. Aaron , Pham Tram
Published: December 2020

Laser induced emission and photocurrents with exponential power scaling were discovered using a near IR Raman laser scanning microscope. The potential for utilizing these highly non-linear effects for sub-diffraction limited imaging has been explored both theoretically and experimentally. A three-fold improvement over the linear diffraction limit was predicted and experimentally validated.
Mobile Diffractive Solid Immersion Lens Design for Backside Laser Based Fault Localization
Authors: Goh S.H. , Cho J.Y. , Lam Jeffrey , Phang J.C.H.
Published: December 2020

In this paper, a mobile Diffractive Solid Immersion Lens (mDSIL) design is proposed to enhance spatial resolution for backside laser fault isolation techniques. By allowing for multiple failure sites analysis using a single DSIL, this design improves conventional static DSIL directly fabricated on silicon substrate. The feasibility of mDSIL is demonstrated experimentally and the resolution performance is shown to be comparable to a static DSIL.
Fault Isolation of Sub-Surface Leakage Defects Using Electron Beam Induced Current Characterization in Next-Generation Flash Memory Technology Development
Authors: Nagatani Go , Yu Kenneth , Rosario Amalia Del , Sidorov Max , Stallcup Richard E. , Gray Joel-Anthony
Published: December 2020

This paper covers methods used to isolate single leaky junctions in a test structure designed for Flash memory technology development. It may be possible to isolate this failure through micro probing or a combination of electrical testing and physical structure modification by FIB, but at the expense of spending numerous days. The paper shows that a combination of emission microscopy (EMMI), electron beam induced current (EBIC) characterization and a SEM nano-probing can drastically simplify the fault isolation process. Results of nano-probing are also shown to prove the level of leakage detected in the faulty junction. A combination of EMMI and EBIC characterization was able to pinpoint the problematic junction from approximately 2500 junctions in the structure. Furthermore, the nano-probing IV characterization proved the identified junction to be indeed high in leakage current, providing further confidence for physical failure analysis.
A Novel Wet Etch In-situ Decapsulation of Devices on Boards
Authors: Gonzales Michael A. , Kiljan Joanna
Published: December 2020

This paper presents a novel technique for decapsulation of integrated circuits (ICs) mounted on printed circuit boards. This technique overcomes wet etch related sidewall blowouts that damage or alter the performance of the IC and board under test. It also allows well defined etch geometries and better endpoint detection. This is accomplished by protecting the region of interest (ROI) with a fast-curing, acid-resistant maskant that peels off easily. The technique was successfully utilized on a densely populated board, which exhibited temperature sensitive failure mechanism, as discussed in this paper.
Low Temperature Plasma Decapsulation of Copper-Wire-Bonded and Exposed Copper Metallization Devices
Authors: Staller Kristopher D.
Published: December 2020

One method of reducing costs in the packaging sector is to switch from gold bond wires to copper. Thicker copper wires (over 2 mils) can be safely decapsulated using a ratio mixture of fuming acids. Some surface etching of the copper will occur, but the wire will remain electrically viable. Microwave Plasma can provide a safer alternative for decapsulating packages with copper bondwires and exposed copper metallization. In this paper, experimental deprocessing of copper bond wire and copper metallization using laser ablation and downstream microwave plasma has found that 1 mil stressed wires can be safely exposed and examined, showing slip plane fractures in the corner wires. Topside copper metallization remains intact, even the thin protective nickel plating. Sensitive copper metal structures on top of the passivation (such as antennas) will remain electrically viable following decapsulation with plasma, but are often lost and defective following acid decapsulation.
Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis
Authors: Chen Kuo Hsiung , Wu Wen Sheng , Shu Yu Hsiang , Lin Jian Chan
Published: December 2020

IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.
Using Nano-Probing Technique to Clarify Nickel Silicide beyond Process Window Causing Device Failure
Authors: Lin Jian-Chang , Wu Wen-Sheng
Published: December 2020

A scanning electron microscopy (SEM) based nano-probing system is used in this study to clarify nickel silicide phase beyond process window. According to the nano-probing measurement result and the cross-sectional transmission electron microscopy (TEM) images, phenomena of junction leakage along with high resistance and a larger nickel silicide area are observed at failure site at the same time. The type of failure mechanism and in-line process issue caused multiple failure phenomena at failure site will be the major focuses in this paper. Nickel silicide phase transformation from NiSi to NiSi2 is highly suspected by the comparison of sheet resistance and silicon consumption. Consequently, nickel silicide beyond process window could be verified immediately.
Design Rule of Microchip Al Bond Pad and Optimization of Bonding Process in Wafer Fabrication
Authors: Younan Hua , Rao Nistala Ramesh , Boon Ang Ghim , Shuting Chen
Published: December 2020

Wire bonding continues to remain as the dominant chip interconnect technology in the far backend process, regardless of the shrinkage of microchip Al bond pad size and the increase in the number of I/O connections in the modern ICs. The reliability of IC devices is directly affected by the quality of adhesion between wire bond and microchip Al pad. Many factors, such as the wafer fab process residue and corrosion, creep-induced wire breakage and electrostatic damage, may result in poor adhesion. In this paper, we show a p-channel Field-Effect Transistor (pFET) failure caused by a mismatch in the bond pad size and the wire bond diameter as well as electrostatic damage during wire bonding. The failure analysis results, failure mechanism and the design rule of microchip Al bond pad in wafer fabrication are discussed. FA investigations were performed on the high gate leakage (nA to mA level) issue in the packaged pFET. It was found that two major factors contributed to the failure, namely mechanical and electrostatic damage. The mechanical damage was mainly due to incompatible Al pad size and bond wire diameter. More specifically, in the failed device, the bond wire diameter was larger than half size of the bond pad opening, contrary to the general design rules of wire bonding. The failure to adhere to the design rule resulted in the device failure. In addition, the electrostatic damage during wire bonding resulted in defects of poly Si/gate oxide and thus the high gate leakage. In this paper, the FA results, failure mechanism of the high gate leakage and the bond pad design rule will be discussed. Also, it will be demonstrated that to achieve good bonding quality and eliminate mechanical and ESD damage the diameter of the bond wire should be equal to or smaller than half of the bond pad opening.
Application to Non Destructive Physical Analysis Method Using X-ray CT Imaging
Authors: Mizoguchi Akira , Sugawara Minoru , Nakamura Masahide , Takeuchi Koichiro
Published: December 2020

We have been paying attention to the development of the nondestructive physical analysis (NDPA) technology. We think that NDPA is a technology which doesn't depend on the worker's capability or experience. There are many NDPA techniques, and analysis using X-ray imaging is one of the principal techniques. Due to the progress of the image analysis using computers in recent years, X-ray imaging have been evolving from two dimensional images to three dimensional imaging. We have been applying X-ray CT imaging to actual failure analysis and reliability evaluation since 2008. At ISTFA 2009, we reported on the effectiveness of X-ray Computed Tomography (CT) images in the failure analysis. [1] We confirmed that the X-ray CT image had various applications, for example, screening for counterfeit parts, the detection of the defect of the multi-layers printed wiring boards (multi-layers PWB), the structure confirmation of caulking contacts, and the detection of cracks or voids of the solder joint. This paper discusses the effectiveness of X-ray CT imaging in failure analysis and discusses the effectiveness of applying X-ray CT imaging to the propagation of cracks occurring at solder joints during temperature cycling test.
Case Studies of Counterfeit Part Detection in Assembled Products
Authors: Hartgerink Daniel P.
Published: December 2020

Counterfeit parts are marketed with the intent to deceive the customer. This intent to deceive defines a counterfeit part and separates it from faulty parts, which have defects that are unknown to the manufacturer or distributor. This paper presents three cases in which counterfeit electronic parts were assembled into hardware items and later found to be faulty in some manner. Laboratory techniques used to identify these parts as counterfeits are presented. Non-laboratory techniques that could have prevented the parts from entering service in these cases are also described. Techniques to combat counterfeit parts range from very simple observation of the parts and the paperwork to failure analysis carried out in a laboratory environment. In all of these cases, the potential existed to detect the counterfeit parts prior to assembly into hardware and prior to field deployment of the defective devices.
Differential and Lock-in Imaging of Dynamic Photon Emission and Applications in Failure Analysis
Authors: Qian Zhongling , Brillert Christof , Burmer Christian , Yokoyama Yoshiyuki
Published: December 2020

In this paper, the differential and lockin imaging techniques of Dynamic Photon Emission (DPE) were developed by using highly sensitive near-infrared InGaAs camera in time integrated mode. At first, the setup and method for differential imaging of DPE (DI-DPE) are introduced. The unique debug and pinpointing capability of fails of DI-PEM is discussed in combination with two case studies. Based on DI-DPE, the setup and method for Lockin imaging of DPE (LI-DPE) are then developed for such cases where the correlated DPE is enhanced in strong photon emission background. The correlation in LI-DPE can separate the emission spots from different power domains.
Methodology for Analysis of Schottky Diode Failures
Authors: Sood Bhanu P. , Pecht Michael , Miker John , Wanek Tom
Published: December 2020

Schottky diodes are semiconductor switching devices with low forward voltage drops and very fast switching speeds. This paper provides an overview of the common failure modes in Schottky diodes and corresponding failure mechanisms associated with each failure mode. Results of material level evaluation on diodes and packages as well as manufacturing and assembly processes are analyzed to identify a set of possible failure sites with associated failure modes, mechanisms, and causes. A case study is then presented to illustrate the application of a systematic FMMEA methodology to the analysis of a specific failure in a Schottky diode package.
Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique
Authors: Cao Lihong , Tran Loc , Donna Wallace
Published: December 2020

This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.
Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree
Authors: Huang Yu , Cheng Wu-Tung , Tai Ting-Pu , Lai Liyang , Guo Ruifeng , Kuo Feng-Ming , Chen Yuan-Shih
Published: December 2020

If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.
Al Bondpads, Halogens, and an ESCA-Based Search for the Invisible Cause of Poor Throughput at Wafer Probe
Authors: Niles David W. , Kee Ronald W.
Published: December 2020

The authors use electron spectroscopy for chemical analysis and Auger electron analysis to study the interaction of Cl and F with Al thin-films deposited as thin-films on Si wafers and as Al bondpads. The motivation behind the study is F contamination being the putative source of poor throughput at wafer probe. F species stemming from NH4F and XeF2 exposure behave quite differently from HF on the Al surface. Whereas HF tends to attack the Al metal and leave an extended oxygenated-fluorinated surface, NH4F and XeF2 promote the formation of a stable, non-deliquescent fluoride salt of aluminum. HCl is far less corrosive to Al than HF, leaving a thin chlorinated-oxygenated surface. Immersion of Al thin-films in tetra-methyl-ammonium hydroxide (TMAH) and NH4OH provided non-halogenated surfaces for comparison. With exposure to air, the surface coated with the fluorinated Al salt (NH4F) adsorbs oxygen from the air to form a segregated AlF3/Al2O3 bilayer that remains stable with a total thickness on the order of 5 nm to 10 nm. Furthermore, wafers treated with NH4F display stellar throughput performance at wafer test despite having surface F contamination. A mechanical rather than chemical model is proposed to explain the improved performance at wafer probe with the immersion of wafers in a bath containing fluoride salts before wafer probe.
Comprehensive Nano-Structural Approach of SSRM Nanocontact on Silicon through TEM-STEM Study
Authors: Domengès B. , Delaroque T. , Danilo K. , Colder A.
Published: December 2020

Scanning Spreading Resistance Microscopy electro-mechanical nanocontacts are nowadays well understood and numerous influent parameters have been identified (Bias, load, surface state of the sample, radius of curvature of the tip). Despite several simulation and modelization possibilities, calibration curves are required to ensure reliable electrical characterizations. In this paper, we bring, through nano-structural studies (Scanning Electron Microscopy, Transmission Electron Microscopy) of surface state of both SSRM tips and doped silicon surface a new understanding of tip-sample interaction during SSRM measurements. As a result of load, a nanometric residual amorphous silicon layer was observed which thickness depends on applied force and might be due to as well the plastic transformation (Si to β-tin phase) as plough-effect residues resulting from the tip indentation into the sample. It appears thus in a failure analysis process to find the best compromise between stable electrical SSRM response and sample/tip surface degradation.
Backside De-Processing of Integrated Circuits 40 nm and Below
Authors: Li Yuanjing , Scott Steven , Marks Howard Lee
Published: December 2020

This paper presents a novel backside de-processing technique for effective failure analysis of advanced multi-level interconnect metallization CMOS ICs with flip chip package.
Setup for Locating PV-Cell Defects through ISC Measurements
Authors: Shankar Santhosh , Bernhardt Andreas , Srinivasan Balaji , Enimidisetty Sravanthi , Versen Martin
Published: December 2020

Optical or light beam induced current (OBIC or LBIC) are well known techniques for the analysis of integrated circuits and the study of electrically active materials in material science. They are also natural methods for analysis of photovoltaic cells, as the photocurrent of a photovoltaic cell itself is measured. We present a new measurement setup including graphical user interface software which has been created in a student project by refurbishing a used CNC (Computer Numerical Control) milling machine. The technique is applied to the measurement of the short circuit current of a photovoltaic (PV) cell with dimensions of 154 × 154 mm2.
All-Contactless Measurement of Series Resistance Distributions on Solar Cells with Photoluminescence Imaging
Authors: Kasemann M. , Reindl L.M. , Michl B. , Warta W. , Schütt A. , Carstensen J.
Published: December 2020

Conventional series resistance imaging methods require electrical contacts for current injection or extraction in order to generate lateral current flow in the solar cell. This paper presents a new method to generate lateral current flow in the solar cell without any electrical contacts. This reduces the sample handling complexity for inline application and allows for measurements on unfinished solar cell precursors.
Failure Analysis Method of Using Laser Nano Electrostatic Field Probe Sensor (L-NEPS)
Authors: Ito Seigo , Sodeyama Hiroko , Takiguchi Kiyoaki , Matsumoto Toru
Published: December 2020

We propose in this paper to introduce the L-NEPS (Laser Nano Electro-static field Probe Sensor), which can detect the slight quasi-electrostatic field generated by optical excitation and thermal excitation occurred when laser beam irradiates on the surface and back of the Die of LSI under non-bias and non-contact conditions, as well as the method to locate the failure point with this device. This report explains the principle of quasi-electrostatic field sensing by L-NEPS and the detection mechanism, and also illustrates the effectiveness of this detection method on the basis of analysis data of two examples of LSI failures (ESD breakdown).
Hardness of Rinse Water and Swelling Behavior of Dry Film Photo-Resist
Authors: Kim Song-I , Heo JinWoo , Kim YunHee , Yu Yeonseop , Choi ChungSik , Yu JaeSu
Published: December 2020

We investigated the swelling behavior of dry film photoresist in rinse process after development by varying the hardness of water. We inspected the appearance of sidewalls and the foot of the resist. We also measured the depth of once swollen resist using a FIB (focused ion beam) and analyzed the chemistry of the resist after rinse using an XPS (X-ray photoelectron spectroscopy). We experimentally proved that divalent cations such as Ca2+ and Mg2+ in hard water could be exchanged with Na+ on the resist surface and quench swelling of the exposed resist in rinse. This study indicates that the use of hard water in rinse process may result in better line definition and resolution in PCB (printed circuit board).
Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing
Authors: Larré P. , Tupin H. , Charles C. , Newton R.H. , Reverdy A.
Published: December 2020

As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.
In FAB 300mm Wafer Level Atomic Force Probe Characterization
Authors: Kane Terence
Published: December 2020

A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front opening unified pod (FOUP) carrier and may be reintroduced into the manufacturing line without disruption for further inspection or processing. Whole wafer atomic force probe electrical characterization has been applied to 32nm, 28nm, 20nm and 14nm node technologies. In this paper we explore the cost benefits of performing non-destructive AFP measurements on whole wafers. We have found the methodology of employing a whole wafer AFP tool complements existing in-line manufacturing monitoring tools such as brightfield/dark field optical inspection, SEM in-line inspection and in-line E-beam voltage contrast inspection (EBI).
An Overview of Cu Wire Intermetallic Compound Formation and a Corrosion Failure Mechanism
Authors: Meng Dongmei , Buck Laura , Cargo James
Published: December 2020

Cu needs a higher level of ultrasound combined with bonding force to be bonded to the Al pad properly, not just because Cu is harder than Au, but it is also harder to initiate intermetallic compounds (IMC) formation during bonding. This increases the chances of damaging the metal/low k stack under the bondpad. This paper presents a fundamental study of IMC as well as one example of a failure mode of Cu/Al bonded devices, all based on detailed analysis using scanning electron microscopy, scanning transmission electron microscopy, energy dispersive spectrometers, and transmission electron microscopy. It presents a case study showing a corrosion mechanism of Cu/Al ballbond after 168hr UHAST stress. It is observed that all Cu9Al4 was consumed, while very little copper aluminide remained after 168 hours of UHAST stressing.
Study on ATPG Failure with Butterfly Pattern
Authors: Chen C.Q. , Ang G.B. , Zhao S.P. , Neo S.P. , Quah A. , Teo Angela , Liu B.H.
Published: December 2020

In this study, a 65nm product level low yield case has been investigated and its failure mechanism was identified. Root cause analysis was discussed and concluded. The product has been hit with ATPG failure with a unique wafer map signature - a butterfly pattern. Tools commonality and timeframe analysis show that the highly suspected process is the Metal1 Cu seed PVD step. To understand the failure mechanism and its root cause, product level FA was needed. However due to its functional failure property, the conventional EFA is not applicable in this case. Instead GDS study was performed to isolate the failure sites. Subsequently physical FA analysis was carried out at the identified sites to reveal its failure mechanism. Metal1 void was observed on the sidewall of the metal1. Meanwhile, a very interesting phenomenon was observed. If die was selected on the left part of the butterfly pattern, the void would be on the right side sidewall of the metal. If the die was selected on the right part, the void would be on the left side sidewall of the metal1. All of the voids were towards wafer center. After in-depth study of the PVD process, we suspect the pass die could also have void. These voids must be also towards wafer center. Subsequent PFA on good unit confirmed our suspect. The more detailed mechanism of the void formation was discussed and evidences supporting our analysis are to be presented in the paper. Nevertheless, the butterfly pattern is still a question in our mind. After in-depth analysis, we found the voids formation was associated with Metal1 orientation. Because of the horizontal orientation of Metal1, if the void happens it should locate in the end of the metal line in the butterfly area. While the majority of Via1/contact are stand on the line end, so the open Via1/contact failure will happen. For the die out of the butterfly area, the majority of the void locates in the sidewall of the metal line center. The majority Via1/contact are not stand in the center of the metal line center, of no Via1/contact open happen. But it is still has reliability concern. Much more detailed and in-depth mechanism is investigated in the paper. Moreover, improvement is also touched on. Systematic problem solving method is employed in this case. It is good reference for same kinds of failure analysis.
Fault Isolation Techniques and Studies on Low Resistance Gross Short Failures
Authors: Tan P.K. , Mai Z.H. , Lee W.Y. , Ma Y.Z. , He R. , Ng T.H. , Dawood M.K. , Low G.R. , Tan H. , Oh C.K. , Lam J.
Published: December 2020

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.