Failure Mechanism of Nano-Resistor Devices
Authors: Zhang Shumao , Kuo Yue 
Published: February 2020

Recently, a new type of nano-resistor device was reported by the authors’ group [1-7]. Nano-resistors are formed from the breakdown of an amorphous high-k thin film on a p-type Si wafer [4]. There are many applications of the nano-resistor device. For example, the broad-band light could be emitted from nano-resistors upon the pass of a large current [1-3]. Since the whole device is made of the IC-compatible materials and processes, it can be used as a solid-state incandescent light emitting device (SSI-LED) for the on-chip optical interconnect, microdisplays, etc. [8,9]. It also has antifuse- and diode-like characteristics that are suitable for IC and other electronics [5,6]. Without a passivation layer, the babo0resistor can be operated continuously for over 20,000 hrs in air [7]. In this paper, authors investigated the failure mechanism of the nano-resistor device using the high voltage stress condition. The surface morphology change was also studied.

The nano-resistor device was fabricated from a MOS capacitor made of the sputter deposited ZrHfO film on a p-type <100> Si (1015 cm-3). The detailed device fabrication process including the nano-resistors formation can be found in refs. 1-6. The post deposition annealing condition was 800°C, 3 min in N2 and the final annealing condition was 400°C, 5 min in forming gas. Although the device was normally operated at a gate voltage (Vg
) of -20V, in the accelerated failure test, it was stressed Vg
= -65 V.

Figure 1 shows the top-view graphs of the device after being stressed at Vg
= -65 V for 5 min. Fig. 1(a) is the photo of the device under the light emission condition. Compared with the nearly perfect round-shaped and uniformly distributed bright dots under the -20V stress condition, the high voltage stressed device is deteriorated. The shape of the lighted area is not round. A large number of bright dots are accumulated at the edge of the device. This is because the electric field, i.e., from the backside of the wafer to the individual device, on the edge is larger than that away from the edge. Since nano-resistors are formed from the breakdown of the dielectric film, it is natural that more nano-resistors are formed at the edge than near the center. Fig. 1(b) shows the same device without the V
g
stress. It shows that the damage of the device started from the edge. After a long period of high voltage stress, the complete device is damaged with the whole device showing as black.

Figure 2 shows the SEM micrograph of the failed region of the device (a) before and (b) after the stripping of the ITO electrode with an aqua regia solution for 5 min. In Fig. 2(a), the originally flat ITO gate becomes very rough and forms several irregular sharped bumps. This is due to the melt of the ITO layer under the high voltage stress condition. In Fig. 2(b), after the removal of the top ITO gate, the underlying Si surface is also very rough. This proves that Si was molten under the high voltage stress condition because the temperature of the nano-resistor is very high.

In summary, the failure of the nano-resistor device starts from the edge due to the local high density of the leakage path from the dielectric breakdown. More detailed discussion of the failure mechanism will be discussed.

[1] Y. Kuo et al, APL,
102, 031117 (2013).

[2] Y. Kuo et al, ESSL,
2, Q59 (2013).

[3] Y. Kuo et al, SSE, 89, 120 (2013).

[4] C.-C. Lin et al, APL, 106, 121107 (2015).

[5] Y. Kuo, ECST,
67, 183 (2015).

[6] Y. Kuo, ECST,
69, 23 (2015).

[7] Y. Kuo et al, 63rd AVS Abst. EM-FrM-7, 2016.

[8] Y. Kuo, Proc. ISSP 2015, 20-24, 2015.

[9] Y. Kuo, Proc. AMFPD ’15, 9-12, 2015.

Figure 1