bluuebunny/crossref_metadata_2025 huggingface dataset:
A Novel Si/Cu Slurry for TSV Applications
Authors: Lee Kanghua , Dai Guolong , Liu Vincent , Wu Kuochun
Published: March 2010

A novel TSV (Through Silicon Via) Silicon backside polishing slurry has been developed to offer the solution to integration flexibility of TSV applications. The requirements for back-side silicon substrate polishing are to deliver fast silicon removal rate for high throughput, tunable Cu/Si selectivity to achieve desired final topography. Owing to different oxidation properties between silicon substrate and copper metal, it is challenging to achieve both high copper and silicon removal rates with the conventional oxidize, like hydrogen peroxide which also suffers from short slurry pot life. In this study, we investigated a non-peroxide oxidizer, instead of hydrogen peroxide, which can effectively oxidize both silicon and copper metal and to give the relative higher Si and Cu removal rates higher than 0.8μm/min @ 3psi down force, and benefit longer pot life. The Si/Cu selectivity can be fine tuned from 1.6 to 1 as increasing oxidizer concentration from 0.3 to 0.8 wt.%
Study on Effects of Slurry Key Factors on Advanced Oxide CMP Performance
Authors: Song Peter , Yao Daisy , Lee Leo , Yuan Gu , Yu Chris , Xing Charles , Lin Paul-Chang , Sun Tao , Ma Zhiyong , Zhu Yefang , Zhang Chunlei
Published: March 2010

With the advancement of technology nodes, the demands on oxide CMP have become more stringent. Defectivity, rate, profile, selectivity to various films (in special applications), planarization efficiency, process window, as well as costs, are the main considerations in an advanced oxide CMP process. Polishing rate and profile tuning by slurry formulations are challenging in certain silica based slurry systems. In this paper, various designed, novel additives are explored to enhance oxide CMP performance. The effects of key factors including abrasive types, chemistry, and pH range on within wafer non-uniformity, especially on the wafer edge rate drop, have been studied. The results indicated that a controlled removal rate and desired wafer edge profile can be achieved through the optimum combination of functional chemistry compositions, abrasive type and properties, and pH. A number of possible mechanisms will also be discussed.
Influence of Abrasive on CMP Quality for NiP Substrate of Computer Hard-Disk
Authors: Tan Baimei , Niu Xinhuan , Bian Na , Chen Haitao , Liu Yuling
Published: March 2010

As the main unit of data storage of the computer, the hard-disk storage density is increasing continuously, which is influenced directly by surface quality, so the substrate surface must be smooth and no-defect. Currently, the chemical mechanical polishing (CMP) technology with nanometer abrasive is adopted as the precise disc polishing. In this paper, the chemical character of NiP substrate of computer disk was analyzed, the CMP mechanism was discussed. The CMP experiments were performed with alkali slurry. The action of abrasive on NiP film CMP was analyzed. It was indicated that the abrasive in slurry not only has the effect of grinding but also acts as micro-stirrer during CMP process. According to the experiments the effect of silica sol size and concentration in alkali slurry on removal rate and roughness of NiP substrate were analyzed and the higher removal rate was obtained. Low roughness was realized with small size and low hardness silica sol as abrasive.
Integrated Product and Process For Copper and Barrier CMP
Authors: Spiro Clifford L. , Wu Kuo C. , Yeh Mason , Dysard Jeffrey , Nam Chul W. , Sun Fred
Published: March 2010

Chemical mechanical planarization (CMP) of copper and barrier interconnects are significant value-adding steps in semiconductor manufacturing. There are a number of materials, designs, processes, and requirements to achieve a successful system. Variables that impact CMP include the selection of the polishing tool, pad, slurry, conditioner, ring, cleans and the elements of polishing processes including down-force, flow rate, time, temperature, friction, conditioning, and cross-contamination. Given the multiplicity of semiconductor design, materials, and processes, it is not surprising that CMP varies from fab to fab. We describe in this Paper, Cabot Microelectronics' approach to helping our customers develop an integrated system of slurry, pad, and auxiliary processes to achieve improved CMP process performance, yields, and costs.
The Black Pad with Graphite Impregnation for CMP
Authors: Sung James C. , Tsai Ming-Yi , Sung Michael
Published: March 2010

CMP has been practiced by polishing wafers with white polyurethane pads that contain pores. These pores may reduce the contact areas at the interface so the polishing rate is increased by enhanced pressure. Moreover, the pores also serve as the reservoir for storing excess slurry that can replenish the consumed abrasive particles at the polishing site from time to time. A new design of black pads has eliminated the need of built in pores. Instead, submicron graphite particles are impregnated in polyurethane matrix. The graphite particles can be plucked off at the polishing site so the contact pressure at the polishing site is increased as if pores are present. Furthermore, graphite particles are hydrophilic so slurry can be retained better than that in water repelling white pad. The wetting can also lubricate the polishing site and allow faster polishing of the wafer without damaging the local circuitry. This reports summarizes various features of the black pads including their CMP performance compared to conventional white pads.
Tribological and Kinetic Characterization of 300-mm Copper Chemical Mechanical Planarization Process
Authors: Han Zhenxing , Zhuang Yun , Sampurno Yasa , Meled Anand , Jiao Yubo , Wei Xiaomin , Cheng Jiang , Moinpour Mansour , Hooper Don , Philipossian Ara
Published: March 2010

The tribological and kinetic attributes of 300-mm copper chemical mechanical planarization process were characterized in this study. Coefficient of friction (COF) ranged from 0.39 to 0.59 for the Cabot Microelectronics Corporation D100 concentrically grooved pad, indicating that boundary lubrication was the dominant tribological mechanism. In comparison, COF decreased sharply from 0.55 to 0.03 for the Dow Electronic Materials IC1000 K-groove pad, indicating that the tribological mechanism transitioned from boundary lubrication to partial lubrication. For both pads, copper removal rate exhibited highly non-Prestonian behavior. A two-step modified Langmuir-Hinshelwood model was used to simulate copper removal rate, wafer surface reaction temperature, as well as chemical and mechanical rate constants. The simulated copper removal rates agreed very well with the experimental values. The simulated chemical rate constant to mechanical rate constant ratios indicated that the IC1000 pad generally produced a more mechanically controlled removal mechanism in this study.
Investigation of Mechanical Effects on Advanced Copper CMP
Authors: Jing Jianfen , Ma Zhiyong , Lin Paul-Chang , Li Pei , Xing Charles , Gu Yuan , Cai Xinyuan , Yang Xiaohua , Shiao Danny , Yu Chris
Published: March 2010

Chemical mechanical planarization (CMP) of copper is a critical step in advanced IC interconnects technology. The key performance metrics of a Cu CMP are the removal rate, removal rate profile, dishing and erosion, process window, and defectivity. Many researchers have studied the mechanisms of Cu CMP. The present investigations will mainly focus on the mechanical effects on advanced Cu CMP at low down forces. The two main mechanical factors, intrinsic properties of abrasives and polishing process conditions, were evaluated. It was found that the abrasive properties such as mean size, surface area, solid concentration and process conditions such as polishing down force and rotation speed have strong impacts on Cu CMP performance.
Effect of Pad Micro-Texture on Frictional Force, Removal Rate, and Wafer Topography during Copper CMP Process
Authors: Zhuang Yun , Liao Xiaoyan , Borucki Leonard J. , Theng Siannie , Wei Xiaomin , Ashizawa Toranosuke , Philipossian Ara
Published: March 2010

In this study, the effect of pad micro-texture on frictional force, removal rate, and wafer topography during copper CMP process was investigated. 200-mm blanket copper wafers and Sematech854 patterned wafers were polished and pad samples were taken after wafer polishing. Pad contact area and surface topography were analyzed using a laser confocal microscope. The Mitsubishi Materials Corporation (MMC) 100-grit TRD disc generated much larger flat near contact areas that corresponded to conditioning debris and fractured/collapsed pore walls. The conditioning debris and fractured/collapsed pore walls partly covered the adjacent pores, making the pad surface more lubricated and rendering a lower coefficient of friction and removal rate compared with the 3M A2810 disc. The mean summit curvature generated by the MMC disc was larger than the 3M disc during patterned wafer polishing, indicating sharper pad summits contributed to higher dishing for the MMC disc.
Effect of pH and Abrasive Concentration on Chemical Mechanical Polishing of Ge2Sb2Te5
Authors: Zhang Zefang , Liu Weili , Song Zhitang
Published: March 2010

This study explores the effect of pH and abrasive concentration on the chemical mechanical polishing of blank Ge2Sb2Te5 (GST) film using the colloidal silica-based slurry. High polishing rates were observed at low pH values and material removal rate (MRR) appears as a linear function of abrasive concentration. To better understand the effect of abrasive concentration on the material removal, MRR per abrasive particle was calculated and on-line coefficient of friction (COF) test was also conducted. Experimental results show that MRR per particle decreases along with abrasive concentration and COF increases linearly according to the abrasive concentration, which indicates that polishing efficiency per particles decreases linearly and MRR is strong related to COF respectively, during the CMP process.
Novel Post Cleaning Solutions for Next Generation Cu CMP Application
Authors: Ko Lennon , Chen Jesse , Liu Vincent , Wu Kuo Chun
Published: March 2010

An effective post CMP cleaning process has become a crucial technology to determine whether CMP technology can be successfully applied in semiconductor industry. As semiconductor fabrication technology advances and a variety of new applications emerge, there is an increase in demand on apply CMP and post-cleaning technology to new materials. It is challenging to develop a clean chemistry compatible with various applications. In this study, the cleaning solution design concept for advanced Cu CMP process is discussed and a novel alkali clean chemistry is proposed. The performance of the new clean chemistry was investigated and compared to industry benchmark products. Based on the data of inorganic particle removal, organic residue removal, Cu etching rate, roughness, Cu corrosion and defectivity on Cu/ULK wafers, the proposed clean chemistry showed promising performance in advanced applications.
Copper Seed Process Optimization for Pits Defect Improvement
Authors: Chen Terry , Kang Jian , Hu Adrian , Xu Joe , Gong Summer , Yi Wang
Published: March 2010

The defect performance becomes more and more important as the semiconductor industry scaling down. It impacts chip yield and impacts device reliability. This paper discusses one of the post CMP (chemical mechanical polishing) defect which observed in both 90nm and 65nm node. Although it appears after copper CMP, solutions can be achieved by controlling the copper seed deposition and electroplating condition. Copper seed deposition with resputter approach demonstrates its better overhang performance as well as better copper orientation for defect formation.
Application of Chemical Mechanical Polishing in the Infrared Focal Plane Arrays Manufacturing Process
Authors: Liu Xiaoyan , Liu Yuling , Zhao Zhiwen , Hu Yi , Gao Baohong , Wang Juan
Published: March 2010

Chemical mechanical polishing (CMP) is a powerful method for manufacturing the infrared focal plane arrays structure. In order to achieve planarizing surface and high polishing rate , the slurry prescription and polishing techniques for infrared focal plane arrays are studied, which is based on the low mechanical and high chemical polishing process, and the new point is put forward. The ingredient and prescription of slurry is found, in which the smaller size (ranging from 15 to 20 nm) silica sols is chosen as abrasive. The slurry with smaller abrasive and polishing technology effectively reduces the roughness and thickness of the damaged layer resulting from abrasion. After more research, the main ingredients, including oxidizer, complexing agent (organic-alkali hydroxide multi-amine) and surfactant are chosen preferentially.
High Doping HDP PSG Process Development
Authors: Cheng Xinhua , Sun Hongfu , Li Xianyuan , Zhao Ganming
Published: March 2010

In this study, we report a 9wt% PSG film for increasing the etch selectivity to poly gate by changing the sputtering gas from Argon to Helium to avoid the film haze and other issues. Due to the change of new sputtering gas, a new recipe has been developed to fine tune key film properties, including within wafer thickness non-uniformity (WIW NU%) and phosphor concentration uniform-ity in three dimensions. In order to get desired profile after etch process, it is very crucial to control the profile of initial layer and bulk PSG film phosphor doping concentration. Therefore, a new concept which is called "PH3 flow ramp up" has been developed and implemented. Other key concern of integration, i.e., how to control "flower pattern" shape is also discussed in this paper.
Study of Alternative Plasma Strip Techniques for Advanced Photoresist Removal
Authors: Luo Shijian , Escorcia Orlando , Waldfried Carlo , Roh Dongwan , Berry Ivan
Published: March 2010

This paper reports on the investigation and development of two alternative plasma strip processes to meet the photoresist (PR) removal requirements of future technology nodes. Experimental results show that new plasma strip approaches have comparable crust breakthrough and removal capabilities as O2/N2:H2 and fluorine-containing strip processes, but achieve significantly lower silicon oxidation, which is comparable to, or even lower than that of an N2:H2-only plasma process. Improved residue removal capability and very low metal (TiN and TaN) oxidation values have also been achieved. SIMS analyses of implanted silicon wafers processed with the new strip approaches have shown minimal dopant loss and profile changes. This work demonstrates that these novel plasma strip approaches are viable candidates for meeting the demanding wafer cleaning requirements of the 32nm technology node and beyond.
Modulation and Extraction of Schottky Barrier Height for Advanced Source/Drain Contact
Authors: Jiang Yu-Long , Li Bing-Zong
Published: March 2010

As the device geometry dramatically shrinks, the silicice/Si contact resistance on source/drain regions is dominating the parasitic resistance and degrading the device characteristics. To lower the contact resistance one of the effective methods is to lower the Schottky barrier height (SBH) of silicide/Si contact on source/drain regions. In this paper the influence of alloy addition on Ni silicidation and the corresponding SBH, such as Ni(Y), Ni(Yb) and Ni(Al) is investigated. Besides, as one of the rare earth (RE) silicides, YbSi2-x is a promising contact material in conventional n-channel metal-oxide-semiconductor field effect transistors (nMOSFET) and n-channel Schottky barrier source/drain FETs. In this paper the oxidation suppression and pinhole-free YbSi2-x film preparation will be reported. To extract the low SBH, a new method based on admittance measurement will also be introduced.
Study of Crater Defect Reduction in Cu Plating Process
Authors: Chen Liang , Wu Kan , He Peng , Bian Yi J. , Zhang Jiwei , Lin Paul-Chang , Chiu Wen-Pin , Xing Cheng
Published: March 2010

In copper metallization of BEOL, ECP (electro chemical plating) is used for copper deposition in via or trench for interconnection after PVD barrier & seed process. Crater defect has been the most dangerous killer defect of ECP process these years. There will be serious impact on wafer yield if craters found after electroplating and CMP (Chemical Mechanism Polishing) process. In this paper, we've done experiments on several aspects to prevent crater from happening, and the results are optimistic.
Wafer Sticking Reduction and MTBF Improvement in AlCu Sputtering Process
Authors: Wang Xuan , Li Xiu-jun , Li Xia , Wu Yong-qiang , Peng Chi-Hsien , Zhang Jiwei , Yang Huang-Her , Lin Paul-Chang , Chiu Wen-Pin , Xing Cheng
Published: March 2010

AlCu sputtering is widely used for IC BEOL interconnection. In manufacturing, wafer sticking is a major issue, which serious impacts the mean-time-between-fail (MTBF) of AlCu sputtering system. Also, during high power plasma sputtering, wafers can be easily stuck onto the chamber process kits, which leads to the yield loss or even wafer scrap. This paper studies the factors of wafer sticking and summarizes the methods including process and hardware optimization to improve MTBF by reducing the wafer sticking hit rate.
Investigation on Stress and Voids in Ultra-Thick Metal (UTM) Films with Electrochemical Plating Processes
Authors: Nie Jiaxiang , Yang Rui-Peng , Kang Yun , He Weiye , Liu Sheng , Kong Xiang-Tao
Published: March 2010

Ultra thick metal (UTM) is used in the IC manufacturing for special applications. For very thick ECP copper films, film stress is very high, which can induce large voids. Big voids in UTM films will results in serious reliability problems. In this work, patterned (trench thickness>3um) 300-mm Si wafers with silicon dioxide as a dielectric layer were used. A design of experiment (DOE) using two levels with 5 factors was conducted on patterned wafers. Delta bow and voids (cross-section by FIB) were analyzed by DOE method. Pareto plots showed that the current of electrochemical plating (ECP) was the main factor affecting delta bow value, and the anneal temperature post plating was the main factor for voids, as shown in cross-section images by FIB. The DOE results allowed process optimization to obtain UTM Cu films with small bow value and few voids, with no adverse electric performance impact.
Effect of Plating and Anneal Processes on Properties of Electroplated Copper Films
Authors: Liu Sheng , Yang Rui-Peng , Nie Jiaxiang , He Weiye , Kong Xiang-Tao , Kang Yun
Published: March 2010

Electroplated copper film has been used extensively in large scale integrated circuits as a conducting metal for interconnect. Therefore, the investigation on the correlations between film properties and process parameters is of great significance. This paper describes the effect of various plating parameters, including plating current, thickness of plated film, wafer rotation speed, and anneal process on the properties of electroplated copper films. The properties investigated are stress, sheet resistance, roughness, reflectance and grain size of electroplated copper conductive layers.
Cu-Cu Thermo-Compression Bonding for TSV Integration
Authors: Kim Bioh , Matthias Thorsten , Burgstaller Daniel , Zhu Swen , Kettner Paul , Jang Eun-Jung , Kim Jae-Won , Park Young-Bae
Published: March 2010

We developed total solutions for the optically aligned Cu-Cu direct bonding process. The quantitative analyses of the interfacial adhesion energy and seam voids of Cu-Cu bonds performed with varying process parameters showed that bonding temperature and post-bond annealing have the most significant influence on bond properties. By optimizing experimental parameters, we could achieve, even with a short bonding time, the sufficient interfacial adhesion energy ({greater than or equal to}5 J/m2) with no interfacial voids. Post-bond annealing performed at 250-300ºC drastically improves the interfacial adhesion energy. SmartView alignment enables the face-to-face Cu-Cu bonding of non-IR transparent wafers while maintaining less than 0.2µm (3σ) and 1.0µm (3σ) of the pre-bond and post-bond alignment accuracy, respectively. Temporary bonding and debonding based on a new spin-on adhesive has such benefits as temperature stability up to 250ºC, compatibility with bumped structures, short debonding time, low-temperature (<200ºC) slide-off release, easy cleanup with polar solvents, etc.
Flip Chip Assembly Using Carbon Nanotube Bumps and Anisotropic Conductive Adhesive Film
Authors: Zhang Xia , Wang Teng , Berggren Pär , Chen Si , Liu Johan
Published: March 2010

Carbon Nanotube (CNT) has been proposed as a promising candidate material to build next generation flip chip interconnects in electronics. In this paper, flip chip assembly using CNT bumps and ACF is performed. To realize CNT-based interconnects, post-growth processes including deposition of metallic layers on CNT bundles and low temperature transfer of CNT bundles have been developed to overcome the problems of the high growth temperature of CNT as well as the poor adhesion between CNT bumps and substrates. Moreover, ACF has been used to assemble the CNT bumps on another Si substrate. The electrical test is performed also to verify the good contact between CNT bumps and ACF.
Advancements in Packaging Technology Driven by Global Market Return
Authors: Todd Michael
Published: March 2010

Recently, the focus of attention in the IC packaging industry has been squarely on removing costs from the manufacturing supply chain. As the economic recovery accelerates, however, advances in innovative IC package design and manufacture are likely to lead the headlines. IC integration technologies, in particular, such as wafer-level packaging design, through silicon via (TSV) technology - especially in the area of IC/memory integration - and an explosion of new developments in the area of multi-die and die stacking technologies are poised to move the industry further and faster than in recent years. This paper will review how materials suppliers have invested significant resources to deliver market-ready materials aligned with this renewed emphasis on packaging technology development.
UV Curable Adhesives for Making Image Sensor Packages
Authors: Kenmochi Taro
Published: March 2010

CCD & CMOS image sensor market has been changed and separated market demands from high and low reliability of packages. This presentation offers 5 articles, as follows 1) Image Sensor Market Trends, 2) General Process of packages & UV curable sealant, 3) Big Challenge UV curable sealant from MSL/JEDEC Reflow, 4) Kyoritsu Chemical internal Reflow test, 5) New demands of image sensor market. These factors will contribute prevent delamination sealant after MSL/JEDEC Reflow, and making high reliability image sensor packages.
Porosity Analysis on the Performance of Heatsink with Microchannels
Authors: Jang Jer-Huan , Chiu Han-Chieh , Yeh Hung-Wei , Wu Ming-Shan
Published: March 2010

This paper investigates the heat transfer performance and characteristics of liquid cooling heatsink containing microchannels. The porosity analysis is utilized to study the thermal resistance of the heatsink with microchannels. Both numerical simulation and experimental work have been carried out. Results show that the effective thermal resistance of the heatsink was affected by both channel aspect ration and the pressure gradient. It is found that channel aspect ratio of 8 present the lowest effective thermal resistance at low pressure gradients. However, the lowest effective thermal resistance appears for channel aspect ratio of 11 under high pressure gradients. As an overall inspection, the value of the effevtive thermal resistance ranges from 0.32 to 0.65°C/W with various porosity at low pressure gradients, while it ranges from 0.18 to 0.37°C /W at high pressure gradients.
Improving Cost of Ownership for Underfill Applications
Authors: Ashley Dan
Published: March 2010

The application of underfill is often necessary for many active devices to ensure component lifetime matches product life and use model. There are many considerations required before an underfill application is ready for production. Often times the process is setup incorrect which ultimately results in reduced product yield and overall higher cost of ownership. To help ensure high yield and low cost of ownership, the process should be setup correct from the start.
First Multi Beam Full Cut Laser Dicing of Thin Low K Wafers
Authors: Borkulo Jeroen V. , Hendriks Rene
Published: March 2010

The traditional blade dicing technology has gone through an impressive evolution keeping up with quality, cost and miniaturization requirements that the semiconductor technology roadmaps introduced and specified. However, since wafer technologies have dropped below 90nm node and low k materials were introduced it became clear that blade dicing evolution came to an end and expensive hybrid solutions such as combined laser grooving processes and blade dicing technologies were required to achieve the desired product reliability. Similar situations have been seen with the ongoing trend to thinner wafer that are needed for miniaturization, 3D packaging and IC performance improvements. To achieve sufficient mechanical strength, complex dicing technologies and sequences have been introduced which do not respond to the requirements for current and near future technologies. The paper will discuss how a multi beam process will play a dominant role to achieve requirements from semiconductor industry.
Electrostatic Control and the Need of Feedback Control Ionization in Critical Environment of MEMS Manufacturing Process
Authors: Chakkaew Anusorn , Titiroongruang Wisut
Published: March 2010

This paper describes new electrostatic control countermeasures and solutions for critical electrostatic control environment that can be implemented in MEMS manufacturing, especially in MEMS's wafer handling that needs low electrostatic voltage. This includes ESD event measurement, machine grounding verification, and low ion imbalance ionization to support current and future needs of the MEMS. Proposed countermeasures are ESD event monitor with electrostatic voltage using a single antenna. Grounding measurement that designed to ignore high-frequency components and measure only the required parameter. These two will help front-end engineer to qualify tools and identify critical process and make the electrostatic issues manageable. Furthermore, the electrostatic field can also be minimized by sub-1 volt ionizer controller that discard initial imbalance, short-term and long-term drift. This brings the balance from 25 volt to sub-1 volt within few second to prevent charge built up in MEMS wafer handling process.
Solutions for Extending Capillary Life Correlated to Build-Up during Wire Bonding
Authors: Levinson Tomer , Billert Oleg
Published: March 2010

In recent years, many assembly houses have been actively seeking cost reduction techniques. Due to the contribution of consumables to the total cost of the wire bonding process, focus has turned to capillary life-span as a major factor in the qualification process. To answer the assembly industry's need for cost reductions, K&S Bonding Tools has designed a specialized extended-life capillary. This article discusses methods and techniques used during the study and development of this extended-life design. Techniques and measurement tools such as Build-up Measurements, Finite Element Analysis (FEA), Process Power Sensitivity Testing (PST), and Tool Life Simulations, were assessed in order to find a suitable capillary design that provides a strong, robust, and more durable wire bonding life performance.
Packaging of High-Temperature Power Semiconductor Modules
Authors: Ang Simon S. , Rowden Brian L. , Blada Juan C. , Mantooth H. A.
Published: March 2010

The requirements of higher operating temperatures for power semiconductor modules require substantial changes to conventional power module fabrication techniques. This paper discusses the selection of substrates, die attachment methods, assembly and package housing for high-temperature power module. A transient liquid phase die attachment method has been demonstrated using two binary alloy systems of Ag-Sn and Ag-In. High-temperature power modules have been fabricated to illustrate the feasibility of the proposed fabrication methods.
RF, Microwave, and Optoelectronic Packaging Die and Wire Bonding Case Studies
Authors: Evans Daniel D.
Published: March 2010

Although there is continued effort in the Semiconductor Packaging industry to reduce package size along with the never-ending pursuit of cost savings, there remain a significant number of applications requiring a wildly different set of capabilities for die and wire bonding. This paper will explore the die and wire bonding requirements of several device cases in RF, Microwave, High Brightness LED, and Optoelectronic package formats when compared to mainstream Semiconductor Packaging. The RF, Microwave, High Brightness LED, and Optoelectronic markets are characterized by lower volume and higher mix when compared to Semiconductor Packaging. This requires different levels of manual and automatic assembly process steps depending on product and manufacturing maturity. Suppliers can help customers through the various stages of manufacturing automation by providing manual, semi-automatic, and fully automatic islands and lines of equipment and process.
Challenges and Solutions of Extremely Thin SOI (ETSOI) for CMOS Scaling to 22nm Node and Beyond
Authors: Cheng Kangguo , Khakifirooz Ali , Kulkarni Pranita , Edge Lisa F. , Reznicek Alexander , Adam Thomas , He Hong , Seo Soon-cheon , Kanakasabapathy Sivananda , Schmitz Stefan , Holmes Steven , Johnson Richard , Zhu Yu , Demarest James , Sadana Devendra , Bu Huiming , Doris Bruce , Shahidi Ghavam
Published: March 2010

Fully depleted SOI (FDSOI) is a viable option for continued CMOS scaling. In this paper, we overview key challenges for designing and manufacturing extremely thin SOI (ETSOI) devices and provide solutions to each challenge. We demonstrate successful fabrication of ETSOI devices with physical gate length down to 25nm and SOI channel thickness down to 3.5nm. Our highly scaled ETSOI devices exhibit excellent electrostatics and respectable performances. We further discuss unique opportunities enabled by ETSOI for reducing CMOS process complexity and therefore reducing process cost, which in turn at least partially offsets the higher cost of SOI substrates. The unique advantages of ETSOI in conjunction with the presented solutions to challenges render ETSOI a strong candidate for scaling planar CMOS to 22-nm node and beyond.
Diamond Islands Wafer for Super LED Manufacture
Authors: Sung James C. , Kan Ming-Chi , Hu Shao-Chung , Yuan Joe C. , Sung Michael
Published: March 2010

Diamond's (111) face can grow epitaxial GaN with wurtzite structure. Better still, single crystal AlN can be deposited directly on such diamond surface. Boron doped diamond has the highest mobility of holes, and silicon doped AlN can boost electron mobility. The AlN on diamond is capable to emit ultraviolet (UV) light with high intensity. Such UV light can excite phosphors for the emission of different colors, including white light with balanced RGB distribution. There are many possibilities of making super LED with diamond. Unfortunately, diamond wafers are not available commercially. However, synthetic diamond crystals can be made cheaply by a noval seeding technology (DiaCan{trade mark, serif}). These diamond crystals are embedded in a ceramic matrix to form diamond islands wafer (DIW). DIW is the enabling substrate for making super LED in the near future.
Moisture and Oxygen Control in Wafer Microenvironments: Challenges and System Solutions
Authors: Wang Huaping , Liu Yingkai , Lee Poshin
Published: March 2010

With advancements in IC technology nodes, water and oxygen in air which used to be benign can become detrimental to some processes. In this paper, we first examine some current between-process wafer environment control challenges. We then present some solutions that can be implemented in wafer microenvironment products, such as FOUPs. These solutions encompass moisture barrier materials for FOUP construction and coatings for longer maintenance of low RH levels, moisture and oxygen getters for enhanced protection of established low moisture and oxygen environments, and flow distribution manifolds (snorkels) for open door purge and faster purge down. Experimental data concerning moisture and oxygen control performance are presented to demonstrate the effectiveness of these solutions.
Multivariate Statistical Process Control in Etching Process
Authors: Xie Kai
Published: March 2010

The purposes of multivariate statistical process control (MSPC) are to enhance process ability by quickly detecting process abnormalities and pinpointing the specific cause of the fault. This paper presents the implementing of MSPC system in etching process including principal component analysis (PCA), and fault contributions from square prediction error (SPE) statistic and Hotelling's T2 statistic. In addition, a combined index called PHI is introduced, which can incorporate information from the SPE and Hotelling's T2 to make fault monitoring more conveniently. The effectiveness of the system to process ability and the uniformity of product quality is demonstrated using etching process tool data.
Numerical Analysis of Oxygen and Carbon Transport in a Unidirectional Solidification Furnace
Authors: Gao B. , Kakimoto Koichi , Nakano S.
Published: March 2010

A global simulation of coupled oxygen and carbon transport in a unidirectional solidification furnace was carried out for accurate prediction of distributions of carbon and oxygen impurities in multicrystalline silicon material for solar cells. Both the gas flow and silicon melt flow were coupled each other. Five chemical reactions were taken into account during the transportation of the impurities.
Germanium Doping of Si Substrates for Improved Device Characteristics and Yield
Authors: Vanhellemont Jan , Chen Jiahe , Xu Wubing , Yang Deren , Rafi Joan Marc , Ohyama Hidenori , Simoen Eddy
Published: March 2010

During the last decade the 300 mm Si wafer has been optimized and one is already studying 450 mm crystals and wafers. The in­creasing silicon crystal diameter shows two important trends with respect to substrate characteristics: the interstitial oxygen concen­tration is decreasing while the size of grown in voids (COP's) in vacancy-rich crystals is increasing. The first effect is due the suppression of melt movements by the use of magnetic fields leading to a more limited transport of oxy­gen to the crystal. This and the decreasing thermal budget of ad­vanced device processing leads to reduced internal gettering capa­city. The increasing COP size is due to the combination of decreas­ing pulling rate and thermal gradient leading to a decreased void nucleation and increased thermal budget for void growth. The ef­fect of Ge doping in the range between 1E16 cm^-3 and 1E19 cm^-3 on both COP's and oxygen precipitation will be discussed.
Optimization on Junction Formation by Three-Stack Furnace POCl3 Diffusion and Analysis on Solar Cell Performance
Authors: Cheow Siu Leong , Salwa Abdul Ghani Nurul , Khairy M.Y. , Shahrul Anizan W. , Amin Nowshad , Sopian Kamaruzzaman , Zaidi Saleem H.
Published: March 2010

The emitter formation parameters for high-efficiency and low cost crystalline silicon solar cells on p-type Si (100) with resistivity in 10-20 ohm range have been investigated. All experimental works performed in 8-inch diameter quartz process tube using liquid source POCl3 as the doping source. Process temperatures in the range 850 - 1000 C with drive-in time in 15 - 30 minutes at O2 flow rate of 4800 sccm were investigated. The starting material wafers were <100> oriented, 100-mm diameter, Cz mono-crystalline silicon wafers with 350-μm thickness, 0 - 10 Ohm-cm of resistivity. This process produces an emitter with a sheet resistance in the range from 20 Ω/sq to 100 Ω/sq as measured with a four point probe (FPP). In order to reduce surface defects, we have also investigated thermal oxidation of heavily-doped wafers to ensure better surface passivation.
Fabrication of SB-MOSFETs on SOI Substrate Using Ni Silicide Containing Er Interlayer
Authors: Hosoda Wataru , Ozawa Kenji , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori Takeo , Iwai Hiroshi
Published: March 2010

SB-MOSFETs were fabricated on SOI substrates by applying novel Schottky barrier height modulation technique of Er interlayer insertion at the interface of Ni/Si prior to Ni silicidation process. It was found that Er interlayer insertion lowered Schottky barrier height for electrons while no significant increase of the resistivity in the Er interlayer inserted films compare to pure Ni silicide films in the annealing temperature range of 500-750 oC. Effects of Er insertion to the transistor characteristics of SOI SB-MOSFETs are also discussed.
Novel Mechanically Stacked Multi-Junction Solar Cells Applying Ultra-Thin III-V Cells and Wafer Based Germanium Cell
Authors: Zhao Lu , Flamand Giovanni , Mols Yves , Van der Heide Johan , Poortmans Jef
Published: March 2010

Compared with monolithically stacked multi-junction solar cells, the approach of mechanically stacking junctions allows more freedom on cell design and material choice. Since there is no requirement on current matching, mechanically stacked multi-junction solar cells are not sensitive to spectrum variations, thus have a high performance potential in terms of annual energy output. The trade-off of such an approach is its increased complexity in solar cell processing. At IMEC, we have developed a low temperature thin layer transfer process for the manufacturing of mechanical stack. First Gallium Arsenide-Germanium mechanically stacked dual-junction solar cells have been successfully demonstrated, with the GaAs top junction consisting of only active cell layer of about 4µm. Efficiencies of 23.2% for GaAs junction, 1.9% for Ge junction, have been achieved under AM1.5 global spectrum.
Copper Precipitates in Multicrystalline Silicon for Solar Cells
Authors: Li Xiaoqiang , Yang Deren , Yu Xuegong , Que Duanlin
Published: March 2010

In this paper, we have investigated the behaviors of Cu precipitation in multi-crystalline silicon by intentionally contaminating. It is found that, the Cu impurities are easily gettered at the structural defects, i.e. grain-boundaries and dislocations. However, in the defect-free region, the Cu impurities tend to form different kinds of precipitates, strongly dependent on the contamination level. The dot-like precipitates are often formed in the samples with low temperature contamination, and the star-like ones in the samples with high temperature contamination. The microwave photoconductivity decay measurements indicate that the Cu precipitates have strong recombination activity, significantly reducing the minority carrier lifetime.
Analysis of Elemental Impurities in Photovoltaic Silicon by Inductively Coupled Plasma Mass Spectrometry
Authors: Chen Jianmin , You Wilson , Du Jiabing , Pan H.-H.
Published: March 2010

A new, simple sample preparation method which results in minimal contamination has been developed for the ultratrace interference-free analysis of solar grade silicon wafers by Inductively Coupled Plasma-Mass Spectrometry (ICP-MS). Using Dynamic Reaction Cell (DRC) technology with patented dynamic bandpass tuning (DBT) and robust hot plasma conditions, the determination of many critical elements, including boron and phosphorus, without impact from interfering species is shown. For method validation, the mean results of a PV silicon wafer sample (purity > 6N) prepared with this new methodology and analyzed by ICP-MS were cross-checked with the data obtained from Glow Discharge Mass Spectrometry (GDMS). The comparative data of these two different technologies highlights the advantage of the ELAN DRC II ICP-MS for the fast determination of impurities in the PV silicon, over GDMS - which was found to be not as cost effective or time efficient.
Laser Annealing and Local Heating Effects during Raman Measurement of Hydrogenated Amorphous Silicon Films
Authors: Yang Ying-Jhe , Yang Yu-Heng , Peng Cheng-Yi , Liu CheeWee
Published: March 2010

Two possible side effects when evaluating the crystalline volume fraction of microcrystalline silicon films by Raman spectroscopy measurement have been investigated. Large laser power incident into the microcrystalline silicon film during measurement may cause some amorphous to crystalline phase transition. In addition, the local temperature rise during measurement also leads to some spectrum shift. Both effects results in incorrect or inaccurate evaluation of microcrystalline silicon film crystallinity. By changing the laser power during amorphous silicon film Raman measurement, it is found that the critical power density to induce crystallization of amorphous silicon is ~455kW/cm2. Furthermore, red-shift of the Raman peak due to local heating effect is observed.
Iron restriction improves type 2 diabetes mellitus in Otsuka Long-Evans Tokushima fatty rats
Authors: Minamiyama Yukiko , Takemura Shigekazu , Kodai Shintaro , Shinkawa Hiroji , Tsukioka Takuma , Ichikawa Hiroshi , Naito Yuji , Yoshikawa Toshikazu , Okada Shigeru
Published: March 2010

Accumulating evidence suggests that alcohol, hepatitis C virus infection, steatosis with obesity, and insulin resistance are accompanied by iron overload states. Phlebotomy and oral iron chelators are effective treatments for these conditions and for hemochromatosis. However, the mechanisms by which iron depletion improves clinical factors remain unclear. We examined the effect of iron depletion in a model of type 2 diabetes, Otsuka Long-Evans Tokushima Fatty (OLETF) rats. Age-matched Long-Evans Tokushima Otsuka (LETO) rats were used as controls for all experiments. Iron restriction was performed by eliminating iron in the diet from 15 wk of age or by phlebotomy. Phlebotomy was commenced at 29 wk of age by removing 4 and 3 ml of blood from the tail vein every week in OLETF and LETO rats, respectively. Rats were euthanized at 43 wk of age, and detailed analyses were performed. The plasma ferritin concentration was markedly higher in OLETF rats and decreased in iron-deficient (ID) diet and phlebotomy rats. Hemoglobin A1c (Hb A1c) was decreased significantly in OLETF rats fed the ID diet and in the phlebotomy group. Increased levels of triglycerides, glucose, free fatty acids, and total cholesterol were found in ID OLETF rats. Plasma, liver, and pancreas lipid peroxidation and hepatic superoxide production decreased in both groups. Pancreatic fibrosis and insulin levels improved in both groups of OLETF rats. Pancreatic levels of peroxisome proliferator-activated receptor-β/δ (PPARβ/δ) ligands and hypoxia-inducible factor (HIF)-1α were decreased significantly in OLETF rats. These factors were normalized in both rats fed ID and phlebotomy groups of OLETF rats. In conclusion, iron depletion improved diabetic complications by inhibition of oxidative stress and TGFβ signal pathways and the maintenance of pancreatic PPARβ/δ and HIF-1α pathways.
EGCG protects against oxidized LDL-induced endothelial dysfunction by inhibiting LOX-1-mediated signaling
Authors: Ou Hsiu-Chung , Song Tuzz-Ying , Yeh Yueh-Chiao , Huang Chih-Yang , Yang Shun-Fa , Chiu Tsan-Hung , Tsai Kun-Ling , Chen Kai-Ling , Wu Yun-Jhen , Tsai Chiou-Sheng , Chang Li-Yun , Kuo Wei-Wen , Lee Shin-Da
Published: March 2010

Lectin-like oxidized low-density lipoprotein receptor-1 (LOX-1), originally identified as the major receptor for oxidized low-density lipoprotein (oxLDL) in endothelial cells, plays a major role in the pathology of vascular diseases. Green tea consumption is associated with reduced cardiovascular mortality in some epidemiological studies. In the present study, we hypothesized that the most abundant polyphenolic compound in tea, epigallocatechin-3-gallate (EGCG), can downregulate parameters of endothelial dysfunction by modulating LOX-1-regulated cell signaling. In cultured human umbilical vein endothelial cells (HUVECs), exposure to oxLDL (130 μg/ml), which led to an increase in LOX-1 expression at the RNA and protein levels, was abrogated by addition of EGCG or DPI, a well-known inhibitor of flavoproteins, suggesting the involvement of NADPH oxidase. Furthermore, oxLDL rapidly activated the membrane translocation of Rac-1 and p47phoxand the subsequent induction of ROS generation, which was suppressed markedly by pretreatment with EGCG or anti-LOX-1 monoclonal antibody. OxLDL also increased p38 MAPK phosphorylation and decreased phosphorylation of the amino-terminal region of Akt, with maximal induction at about 30 min, and NF-κB phosphorylation within 1 h, resulting in redox-sensitive signaling. In addition, oxLDL diminished the expression of endothelial nitric oxide synthase (eNOS), enhanced the expression of endothelin-1 and adhesion molecules (ICAM, E-selectin, and monocyte chemoattractant protein-1), and increased the adherence of monocytic THP-1 cells to HUVECs. Pretreatment with EGCG, however, exerted significant cytoprotective effects in all events. These data suggest that EGCG inhibits the oxLDL-induced LOX-1-mediated signaling pathway, at least in part, by inhibiting NADPH oxidase and consequent ROS-enhanced LOX-1 expression, which contributes to further ROS generation and the subsequent activation of NF-κB via the p38 MAPK pathway. Results from this study may provide insight into a possible molecular mechanism by which EGCG suppresses oxLDL-mediated vascular endothelial dysfunction.
Alternative Transfers to the NEOs 99942 Apophis, 1994 WR12, and 2007 UW1 via Derived Trajectories from Periodic Orbits of Family G
Authors: de Melo C. F. , Macau E. E. N. , Winter O. C.
Published: March 2010

Swing‐by techniques are extensively used in interplanetary missions to minimize fuel consumption and to raise payloads of spacecrafts. The effectiveness of this type of maneuver has been proven since the beginning of space exploration. According to this premise, we have explored the existence of a natural and direct link between low Earth orbits and the lunar sphere of influence to get low‐energy transfer trajectories to the Near Earth Objects (NEOs) 99942 Apophis, 1994 WR12, and 2007 UW1 through swing‐bys with the Moon. The existence of this link is related to a family of retrograde periodic orbits around the Lagrangian equilibrium point L1 predicted for the circular, planar, restricted three‐body Earth‐Moon‐particle problem. The trajectories in this link are sensitive to small disturbances. This enables them to be conveniently diverted reducing so the cost of the swing‐by maneuver. These maneuvers allow a gain in energy sufficient for the trajectories to escape from the Earth‐Moon system and to stabilize in heliocentric orbits between the Earth and Venus or Earth and Mars. Therefore, the trajectories have sufficient reach to intercept the NEOs′ orbits.
The Determination of the Velocities after Impact for the Constrained Bar Problem
Authors: Fenili André , de Souza Luiz Carlos Gadelha , Schäfer Bernd
Published: March 2010

A simple mathematical model for a constrained robotic manipulator is investigated. Besides the fact that this model is relatively simple, all the features present in more complex problems are similar to the ones analyzed here. The fully plastic impact is considered in this paper. Expressions for the velocities of the colliding bodies after impact are developed. These expressions are important in the numerical integration of the governing equations of motion when one must exchange the set of unconstrained equations for the set of constrained equation. The theory presented in this work can be applied to problems in which robots have to follow some prescribed patterns or trajectories when in contact with the environment. It can also de applied to problems in which robotic manipulators must handle payloads.