bluuebunny/crossref_metadata_2025 huggingface dataset:
Micro-Scale Strength Evaluation for Bonding Interface of Cold Sprayed Coatings
Authors: Ichikawa Yuji , Tokoro Ryotaro , Ogawa Kazuhiro
Published: November 2016

A micro-scale interface strength evaluation technique is essential for evaluating cold-sprayed materials. A focused ion beam (FIB) micro strength test enables the micro-scale evaluation of the interface mechanical properties. However, this technique cannot be used to measure the strain in a specimen. This work discusses the possibility of strain measurement by combining this technique with image analysis in a newly designed test setup. Moreover, the micro stress-strain curve for cold-sprayed copper was obtained. This improved method enables us to measure stress with a precision of 5 MPa and strain with a precision of 0.015. It was determined that some local regions can deform plastically, which could not be determined with conventional micro-and macro-scale evaluation methods. These results proved that the coating is non-uniform, while also revealing various microstructure and mechanical properties.
Stress and Strain Analysis in an Fe-Ga Alloy Single Crystal
Authors: Ikeuchi Takehito , Tsubaki Shinki , Imafuku Muneyuki , Fujieda Shun , Onuki Yusuke , Suzuki Shigeru
Published: November 2016

We carried out in situ x-ray diffraction measurements of magnetostriction in an Fe-18at%Ga alloy single crystal under magnetic fields. The sample studied here was a Goss-oriented square plate (dimensions: 10 mm × 10 mm × 1 mm height) cutting from as-grown single crystal ingot produced by the Czochralski method. In-plain magnetic fields were applied with various directions in this study. The influence of magnetic field direction on the stress/strain states was precisely analyzed by using our original x-ray single crystal stress/strain measurement method. As a result, applied field angle dependence of tri-axial magnetostriction states was successfully obtained. Thereby, we found that the singular anisotropic mechanical properties of this material play an important role for its magnetostriction properties.
Preparation of Mg-TM-Y (TM=Transition Metal) Alloys with Long Period Stacking Ordered Phase and their Superior Mechanical Properties
Authors: Itoi Takaomi
Published: November 2016

Mg-Ni-Y alloy with composition ratio of 1 : 2 (Ni : Y) consisted of Mg, and 18R-type long period stacking ordered (LPSO) phases, whereas composition ratio of 1 : 1 (Ni : Y) consisted of Mg,14H-type LPSO and Mg2Ni phases, respectively. After hot-rolling at 693K, strong basal texture parallel to the plane sheet was formed in the LPSO, and Mg phases. Tensile test was performed along rolling direction (R.D) from room temperature (R.T) to 573K. The Mg98Ni1Y1, Mg96Ni2Y2, Mg94Ni3Y3, Mg97Ni1Y2 and Mg94Ni2Y4 rolled sheets exhibited 0.2% proof stress (σ0.2) of 232MPa, 255MPa, 358MPa, 337MPa and 393MPa, and elongation (δ) of 6%, 5%, 7%, 15% and 7% at R.T, respectively. The σ0.2 of the Mg-Ni-Y rolled sheet tend to increase with increasing of area fraction of the LPSO phase. After annealing at 773K for 0.6ks, the δ of Mg-Ni-Y rolled sheet tend to increase, while the σ0.2 decreased due to randomization of the Mg phase by re-crystallization. The Mg-Ni-Y rolled sheets exhibited high σ0.2 above 200MPa at 473K. Additionally, it was noted that σ0.2 of the Mg94Ni2Y4 rolled sheet exhibited 329MPa at 473K and 211MPa at 573K. Thus, the LPSO phase have high thermal stability and is attribute to strengthening of the Mg-Ni-Y alloy sheet at high temperature.
The Optimal Placement of Sensors by Minimizing the Maximum Probability of Non-Detection Using Genetic Algorithm
Authors: Jawali Veena , Parasivamurthy Prakash , Prakash Praveen
Published: November 2016

Optimally placing the sensors without compromising the performance is a challenge and its application is found in Structural Health Monitoring, Load Monitoring, Vibration Control and other areas. Every sensor has predefined region within which the source of disturbance is detected if it is present. This paper examines the use of fminimax concept on simple discretized plate using Genetic Algorithm to optimally place the sensors. This has been achieved by introducing maximum non detection probability in the objective function and the fitness of objective is minimized through genetic algorithm solver in MATLAB. The effectiveness of the present algorithm is then checked by comparing the solution with the solution obtained by implementing this concept on a continuous unit square plate using fminimax solver in MATLAB. The solution obtained in both the methods matched to that in the literatures. The study shows that the algorithm developed can be effectively adopted in discredited structures to optimally place the sensors.
Analysis of Thin Strip Shape and Profile in Cold Rolling: A Way to Improve Strip Profile and Mechanical Properties
Authors: Tibar H.B. , Jiang Zheng Yi
Published: November 2016

Optimisation of the physical and mechanical properties of cold rolled thin strips is achieved by controlling the rolling parameters. In this paper, the factors affecting the low carbon steel thin strip profile of asymmetrical cold rolling have been studied at a speed ratio of 1.3 without lubricant applied. The effect of rolling parameters on the resulting microstructure was also investigated. It was found that under dry condition, work roll shifting and work roll cross angle can improve the strip profile, and the improvement is more significant with an increase of work roll cross angle rather than that of work roll shifting. A slight change in microstructure was evident with increasing work roll shifting values. In addition, effects of rolling parameters on the strip profile and microstructure have also been discussed.
Determination of the Grain Coarsening Temperature in Nb Microalloyed Steels by Multiphase-Field Model
Authors: Kim Jeong Min , Hong Sok Yun , Jang Ji Hun , Lee Kyung Jong
Published: November 2016

The grain coarsening temperature in Nb microalloyed steels is investigated by multiphase-field model. In this study, the pinning force is treated as time-dependent using mean-field kinetics of precipitates including volume fraction and their size. The grain size is calculated with time under various temperature range. The grain coarsening temperature is determined by the ratio of the largest radius of grain vs. the average grain radius criteria (Rmax / Ravg > 2.94) in two-dimensional growth. Through this model, it is possible to simulate grain growth in microalloyed steels more precisely.
EBSD Analysis and Assessment of Porosity in Thermal Barrier Coatings Produced by Axial Suspension Plasma Spraying (ASPS)
Authors: Klement Uta , Ekberg Johanna , Ganvir Ashish
Published: November 2016

Axial suspension plasma spraying (ASPS) is a relatively new, innovative spraying technique which has produced thermal barrier coatings (TBCs) with attractive properties such as high durability and low thermal conductivity. Using a suspension, it is possible to spray with finer powder particles resulting in coatings that have a columnar microstructure and contain a wide range of pore sizes, both nm-and μm-sized pores. To optimize the thermal properties and to maintain them during service of the components, it will be important to design TBCs with optimal porosity. Hence, an important part in the assessment of ASPS coatings is therefore the characterization of the microstructure and how it is build up, and the determination of porosity. Both aspects are addressed by performing measurement on splats and ASPS-coating using electron backscatter diffraction (EBSD) technique and by measuring porosity by Mercury Intrusion Porosimetry (MIP).
Development and Challenges of Warpage for Fan-Out Wafer-Level Package Technology
Authors: Chan Mu-Hsuan , Wang Yu-Po , Chang Ivan , Chiang James , Pan George , Kao Nicholas , Wang David
Published: November 2016

Fan-out wafer-level-packaging (FO-WLP) technology has been widely investigated recently with its advantages of thin form factor structure, cost effectiveness and high performance for wide range applications. Reducing wafer warpage is one of the most challenging needs to be addressed for success on subsequent processes. Therefore, the majority of studies focus on the ratio of die and compound thickness, structure design. In order to optimize the warpage for success on subsequent processes, it is indispensable to consider whole wafer process including thermal loading and stress.

In this study, reducdution of wafer warpage at each process was proposed in terms of material selection, and process optimization through finite element analysis (FEA) and experiment. Wafer process dependent modeling results were validated by experimental measurement data. The mutual relationship and effects of material property, compound thickness, and corresponding thermal influences were both investigated and addressed. Key parameters were identified based on FEA modeling results: thickness ratio of die/compound andmolding compound materials. Therefore, the geometry design with balanced die/compound ratio is optimal for warpage improvement. The effect of process will be discussed and should be considered for future package warpage characterization. Such findings have been successfully used in process optimization to reduce wafer warapge after grinding process.
NSOP Reduction for QFN RF-IC Packages
Authors: Bora Mumtaz Y.
Published: November 2016

Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – Non- stick on Pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction [1].
Effect of Temperature/Humidity Treatment on Interfacial Reliability on Screen-Printed Ag / Polyimide for Advanced Embedded Packaging Technologies
Authors: Lee Kyu Hawn , Bae Byung-Hyun , Jeong Min-Su , Kim Jeong-Kyu , Park Young-Bae
Published: November 2016

The effect of temperature/humidity treatment conditions on the interfacial adhesion energy between a screen printed Ag film and a polyimide substrate was evaluated by using a 90° peel test. The measured peel strength values decrease from 254.7 N/m to 59.3 N/m after the temperature/humidity treatment at 85°CC/85% relative humidity for 500 h. X-ray photoelectron spectroscopy analysis of the peeled surfaces indicates that peeling occurs cohesively inside of the polyimide, which is closely related to both the decrease in the interfacial adhesion energy and the polyimide degradation due to weak boundary layer formation.
The reliability of Ag wedge bonding with various bonding pads for power devices
Authors: Wei Xing , Yu Zhou , Yan Ge , Iizuka Tomonori , Tatsumi Kohei
Published: November 2016

Recent years, with the development of intelligent vehicles, power devices would be widely used. But traditional Si power devices have problems under high temperature. Now, there is a tendency that using SiC instead of Si in power devices, as SiC has a higher band gap 3.25 eV comparing with 1.12 eV of Si. So that SiC power devices can withstand higher temperature and voltage. Also SiC power devices have the advantages of lower parasitic parameters, smaller device size and shorter response time. In this study, to investigate the reliability of Ag wedge bonding, Ag wires were bonded on Al pad and Au-Ni pad. And then we did shear test after high temperature storage life test (HTSL). Finally, we used energy dispersive X-ray spectroscopy (EDS) to do cross-section observation. The results show that, for Al pad, the shear strength has decreased after annealing at 300°C with mold packages, cracks and corrosion were observed. For Au-Ni pad, the shear strength has increased after annealing, and no cracks or corrosion formed. So Ag bonding wire is proposed as an alternative to Al bonding wire for selected metal pads in power devices.
Ultrasonic Bonding on Unstable Pin
Authors: Seppänen Henri
Published: November 2016

In power electronics modules, ultrasonic wire bonding is a common method to make electronic connections between the connector pins and the IGBTs. In these modules the connector pins are often residing on top of the plastic frame. Due to the pins being in positions which are hard to reach, clamping of these pins is either suboptimal or not used. This poor or absent clamping combined with the plastic frame's elasticity (softness) means that the pin has more freedom to move compared to the bonding on a metal substrate or IC. In our experiments we measured the pin and the plastic frame displacement with a laser Doppler vibrometer during the ultrasonic heavy wire (400 um in diameter Al wire) bonding process. We measured that the press fitted pin can move laterally along the ultrasonic excitation axis (2.0 ± 0.2) um whereas the frame under the pin moved (0.3 ± 0.1) um. This indicates that the pin slips over the frame while bonding. The slipping of the pin is also visible on the ultrasonic frequency waveforms of the transducer. While molded pins in general are thought to be more stable compared to the press fitted pins, similar behavior is seen in heavy wire bonding where high ultrasonic power is needed. We measured molded frame displacement (0.6 ± 0.2) um while bonding on the pin. In this paper we show how to use process traces and visual inspection to detect unstable pins and how to improve bondability on unstable pins by selecting process parameters that are optimized for the unstable pins rather than stable surfaces.
Isothermal DSC study of the curing kinetics of an epoxy/silica composite for microelectronics
Authors: Granado Lérys , Kempa Stefan , Bremmert Stefanie , Gregoriades Laurence J. , Brüning Frank , Anglaret Eric , Fréty Nicole
Published: November 2016

Curing kinetics of an industrially important printed-circuit board (PCB) base material (epoxy-phenol/glass fillers) were studied from isothermal differential scanning calorimetry (DSC) measurements between 150 and 190 °C. The extent of cure was calculated by integration of the exothermic peak and normalization by the total heat of reaction (obtained by non-isothermal DSC). The kinetic profiles show two regimes: one fast, and one slower. The completion was reached above 180 °C. The kinetic parameters have been elucidated using an isoconversional model-free kinetic method. The linearity of Arrhenius plots was satisfactory. The apparent activation energy of curing reaction has been found to increase with the degree of conversion. The elucidation of the kinetic parameters allows us to propose an accurate and predictive description of the curing kinetics of the composite until a degree of conversion of 50%. Finally, we discuss how these kinetic measurements and models can be completed and optimized.
Wedge Bonding Wire and Ribbon to Support RF and Optoelectronic Packaging
Authors: Evans Daniel D. , Qi. Wenjuan , Bauder Kevin
Published: November 2016

The proliferation of mobile devices, video on-demand mobile and home, and Internet of Things (IoT), continues to drive an exponential growth in data bandwidth. Meeting the data demand requires continuous improvements in bandwidth and capacity for RF base station modules and optoelectronic modules. RF and Optoelectronic modules have many similar wire bond packaging requirements, especially as optoelectronic data rates continue to increase from 10G through 400G.

This paper will provide a survey of RF and Optoelectronic Packages and their common wire and ribbon bond requirements. The paper will also survey the packaging challenges and solutions available to process engineers. Challenges include bonding on a variety of materials, signal pins, RF loop spans and shapes for wire and ribbon, program strategies to maintain constant loop span, referencing challenges, and simplified machine user interactions.

The paper will also discuss collaborations between manufacturer and equipment supplier with helpful tips leveraging each other's strengths to transition from concept to production.
Design and Process Considerations in Transitioning From Aluminum Wire to Aluminum Ribbon
Authors: Italiano C. , Oud Y. Mindin M.
Published: November 2016

Bonding of power devices is experiencing a rapid transition to aluminum ribbon for many reasons. Better electrical characteristics, improved heat dissipation, fewer bonds, and improved reliability are some of the most obvious advantages. The huge increase in battery powered motors that require more powerful devices in smaller packages also increases the need for ribbon bonding. Coining has developed SPM POWER BOND RIBBON™, a high purity corrosion resistant aluminum bonding ribbon, to meet this demand. New improved spooling is now available for ribbons as large as.080 X.010, and as small as.030 X.003 mil. This spooling method decreases or eliminates most of the traditional issues with despooling of bonding ribbons and is compatible with the most commonly used bonding machines. Several Bonder Manufacturers have introduced new equipment to handle the conversion to heavy aluminum ribbon. Design consideration must be given to items such as bond pad design, loop heights, bonding angles and more. A key point to consider is that fact that one bond of a given size Bonding Ribbon can replace several wire bonds. For example: one bond of.060 X.008 ribbon can replace 6 wires of.010 diameter. This is key to increasing throughput and reliability and ultimately reducing costs. This paper will address the basic design characteristics that need to be considered in order to take advantage of this emerging technology.
PERFORMANCE EVALUATION OF GOLD (Au) WIRE AND RIBBON INTERCONNECTS IN HIGH FREQUENCY CIRCUITS
Authors: Atalan Cenk , Eker Taylan
Published: November 2016

Gold (Au) wires and ribbons are widely being used in military and space applications of high frequency RF/microwave circuits. The purpose of this study is to examine the RF performance of different dimensions of Au wires & ribbons, which are typically bonded in cascade and parallel forms in the circuits operating microwave frequencies within 0–50 GHz. The second goal of this study is to establish a performance chart/handbook of Au wires, ribbons for high frequency circuit designers in order to show them which type of wire or ribbon as well as which type of interconnect form is suitable for their intended design.

First, the test circuit board is manufactured by using chip & wire, epoxy attach method. The substrate material of used RF circuit materials is chosen as Alumina to minimize losses and the material of wires, ribbons are chosen as %99.99 pure Gold (Au). Au plated copper traces are used as conductive layers for optimal reliability and conductivity in the test circuit board. Automated thermosonic ball bonders are used for Au round wire bonds to reduce process errors. Manual parallel gap resistance welders and manual thermosonic wedge bonders are used for Au ribbons and always pay great attention to form the same length by using high magnification microscopes. The experiment conducted with the help of 0.7 mil, 1 mil round wires and 3×0.5 mil, 3×1 mil, 5×0.5 mil, 7×1 mil and 10×1 mil ribbons. Single bonds, parallel double bonds as well as V-type bonds, stitch over ball bonds are performed onto the circuit pads as interconnect types and forms.

The RF tests (S11 return losses and S21 insertion loss) we performed showed that 0.7 mil and 1 mil round wires can be used in the frequency range of 0–20 GHz circuits. A better RF test result can be achieved if double parallel bonding method is used. For higher frequency range, 20 to 50 GHz, 3×0.5 mil, 3×1 mil, 7×1 mil and 10×1 mil ribbons should be used. On the other hand, the bare chip bonding pads and dimensions of transmission line conductive layer bond pads are limiting the usage of desired ribbon. Last but not least, a performance chart of RF wire/ribbon interconnects including a suggestion of bonding method with sustainable current load and shape is generated for design and application engineers who are dealing with high performance circuit efficiency.
Highly Selective Wet Silicon Etch Chemistry and Process for Advanced Semiconductor Packaging
Authors: Lu Yongqiang , Collins Sian , Mauer Laura B. , Taddei John , Clark John
Published: November 2016

A wet silicon etch chemistry and a process using the chemistry as a simple and cost-effective alternative to the polish/plasma etch silicon thinning process are presented in this paper. The new etch chemistry improves the Si etch rate over traditional etchants such as tetramethylammonium hydroxide (TMAH). The chemistry has very high silicon etch selectivity (ratio of Si etch rate to another film etch rate) over SiO2 and over copper films, with etch selectivity greater than 8000:1 and 2500:1 respectively. Chemical compatibility with typical packaging materials such as polybenzoxazole (PBO) and polyimide (PI) are also discussed. Additionally, real production TSV wafers have been successfully processed on an advanced single wafer etch tool using the chemistry. High uniformity and smooth surface finishing have been achieved.
Improvement of Coherency of the Panel Level Package by Integrated Dry Process
Authors: Endo Shinichi , Habu Tomoyuki , Aiba Akira , Suzuki Hiroko , Takezoe Noritaka , Horibe Hiroki , Arikawa Kazuki , Miura Masaki , Kikuiri Hajime , Yabu Shintaro
Published: November 2016

Lately, Semi Additive process has been considered to dry processing for the downsizing of the emiconductor packages. WET process is a process depending on the chemical reaction of the chemical solution. There are many problems with the formation of the minute redistribution layer. We repeated the study of the Photodesmear technology as a new technology of the dry process, reported result in IMAPS in 2013 and 2015.

We completed a panel level experiment tool equipped with a high power irradiation light source. We reported findings of the coherency improvement by integrated dry process which fused in a Photodesmear technology and a dry seed technology.

We confirmed the following effects in integrated dry process. Desmear of micro via was difficult at a panel level. We were able to keep flatness characteristics of the resin before the plating low. We were able to confirm strong coherence of the via filled plating. VUV light irradiation is effective for the residue that is left when removing the protective film before the pre-dry seed layer process.

Integrated dry process is a key technology to establish the next generation semi additive process.
Joint Healing Thermal Interface Material
Authors: Yang Jingting , Strader Jason , Orzolek Sean , Pruss Eugene , Fosnot Phillip , Galloway Jesse
Published: November 2016

Today, thermal interface materials (TIM) are widely used between a processor die and an integrated heat-spreader (IHS) to provide a good thermal conduction path for heat transfer from the electronic package. As the current trend towards larger “die size designs” progresses, the performance and reliability of the TIM will be a greater challenge for thermal engineers. In these larger die size designs, the TIM will experience increased movement as a result of the coefficient of thermal expansion (CTE) mismatch between the die and the printed circuit board. Traditionally, indium and dispensable thermoset materials are utilized in this application. However, delamination of the TIM from one of the mating surfaces is becoming more common as these materials are unable to compensate for the increased movement. In addition, the increasing cost of indium metal is causing indium-based TIMs to become cost prohibitive while dispensable materials require frozen shipment and storage, creating logistics complications and increased costs.

A recently concluded application study demonstrated that a joint-healing thermoplastic pad had better performance after thermal shock cycling, when compared to typically used TIMs. The joint-healing, thermoplastic pad maintained lower thermal resistance at the center and edges of the die. The soft thermoplastic nature of this material helps prevent delamination, or pump out, during cycling and is capable of joint-healing most delaminations that occur at operating temperatures. Data at various intervals ending at 1000 cycles will be presented.

The ability to ship and store this material at room temperature as well as pre-apply it to the IHS adds additional value by simplifying logistics and reducing cost.
Minimizing Voiding in Bottom Terminated Components by Optimizing the Solder Paste Flux
Authors: Briggs Ed
Published: November 2016

Perhaps the single biggest challenge in PCB assembly today is voiding under bottom terminated components (BTCs) such as QFNs (quad-flat-pack, no-leads), D-Paks, and LGAs (land grid arrays). Many bottom terminated components, such as QFNs, have a large thermal pad on the bottom side which provides excellent thermal and electrical grounding properties. However, effectively soldering these components to minimize thermal pad voiding can be a challenge. Many automotive electronics assemblers are increasing this challenge by requiring less than 10% voids to improve reliability.

The large deposit of printed solder paste required to solder the thermal pad typically induces flux entrapment and subsequent voiding during the reflow process. Large voids and/or a high number of voids cause decreased thermal conductivity and lower the mechanical strength of the resulting solder joints. The large solder paste deposit required may also cause the component to float and open up the electrical connections around the perimeter of the component. Another factor affecting voiding has been the transition to lead-free solder, which has been marked by the use of various SAC alloys. Most applications for surface mount assembly use SAC305 (96.5Sn/3.0Ag/0.5Cu) with a melting temperature range of 217–220°C. The higher temperatures required for lead-free soldering and the increased surface tension of the SAC alloy exacerbate the voiding issue.

This paper will focus on the techniques for optimizing the assembly process for QFN components, with a focus on minimizing voiding. Best practices for lead-free reflow profiling, stencil aperture design, solder paste volume control, and the importance of flux chemistry to minimize void formation will be discussed.
An Integrated Sensor for Detecting Moisture Ingress in Printed Circuit Board Assemblies
Authors: Dean Robert N. , Loden Nathan B. , Hartley Curtis J. , Craven Jeffery D.
Published: November 2016

Numerous applications exist where electronics must operate reliably in moist environments, and often for long periods of time. In these environments, the circuit board assemblies may experience moisture ingress, which can deleteriously affect the operation and life span of these systems. Detecting moisture ingress is therefore useful for improving system design, assembly techniques, packaging technologies and maintenance scheduling. Capacitive fringing field sensors are useful for measuring the moisture content of materials. Therefore, a capacitive fringing field sensor, implemented in printed circuit board technology with a CMOS relaxation oscillator interface circuit, is proposed for detecting moisture ingress into the printed circuit board assembly. A set of instrumented sensors was designed, fabricated and tested. The results demonstrated that when the test articles experienced prolonged exposure to moisture, the instrumented sensors experienced an 18.42% change in output value, indicating a satisfactory sensitivity to moisture ingress.
Evaluation of a Lead-Free Ultra Low Temperature Co-Fire Ceramic (ULTCC) Tape Designed for Lamination on Aluminum Substrates and a Compatible Co-Fireable Silver Conductor
Authors: Grabey Steven , Shahbazi Samson , Persons Ryan , Shahbazi Caitlin
Published: November 2016

Light-emitting diodes (LEDs) are the product of choice for many commercial and industrial lighting applications. Due to increasing power densities, alternative mounting solutions are being evaluated in order to achieve the lowest junction temperatures and lowest thermal resistances. Previous papers have explored the benefits of using a thick film system as opposed to a traditional Metal Core Printed Circuit Board (MCPCB). The advantage of being able to directly insulate a heat sink eliminates additional MCPCB layers and mechanical attachment that can decrease the thermal conductivity of the module and increase cost. Lower thermal resistance results in higher performing LED modules at a lower cost and a longer lifetime.

A process has been developed and evaluated where an ultra-low temperature co-fired ceramic (ULTCC) tape will be laminsated directly on to an aluminum heat sink in order to electrically isolate the substrate. The green tape will then have a silver conductor applied to it and fired in one step. Using a tape system as opposed to an ink system creates many advantages. The tape system allows for processing in cavities, which is beneficial for recessed lighting and three-dimensional substrates. The co-firing silver conductor reduces the number of firing steps, leading to less dimensional variation of the heat sink and lower processing costs. This paper will discuss the material solutions, processing requirements, and reliability data for a completely co-fired ULTCC system on aluminum.
Challenges in Assembly implementation of ultra-thin profile flipchip package-on-package
Authors: Eghan Abu , Choi Kyoo B
Published: November 2016

The assembly and structural challenges associated with a low profile bare die flipchip package-on-package (PoP) are reviewed. The PoP was designed to accommodate a JEDEC 256 ball FBGA memory. This dual channel 32-bit LPDDR3 memory package has a unique signal crossing ball arrangement between the Data bus of one channel and the Control/Address (CAS) bus of the other. The ball arrangement presents some crossing challenges for PoP implementation of controller ICs. For timing reasons, the memory controller blocks are traditionally placed together in a central area of the base chip, and signals are routed to line up with the fixed LPDDR3 landing sites. For the dual channel case the routing requires crossing one CAS signal group over the other's data lines. To address this crossing in this product, a copper redistribution layer (RDL) was deployed at the bump stage to bring the appropriate LPDDR3 signals from the controller block to line up with the memory balls. The thick copper RDL/Cu-Pillar arrangement left a 10–13um of dielectric layer over the base die. Because the 0.4mm pitch and clearance requirements of the selected memory package, a very low profile flipchip die standoff was required. The dielectric layers and copper density in RDL had significant impact on the handling of these thinned wafers and die through the assembly processes. Though newer package offerings - like Amkor's Thru Mold Via (TMV) technology or Invensas' Bond Via Array (BVA could have been deployed, a Cu-pillar based bare die flipchip (FCBGA) using a very thin die was selected for its simplicity and lower cost. All package related reliability tests have been completed with success. The process optimization and trade-off needed to achieve success through assembly are discussed in this paper
Novel glass substrates for minimizing thermal stress development during electronic device packaging process
Authors: Nomura Shuhei , Sawamura Shigeki , Hanawa Yu , Sakai Yusuke , Hayashi Kazutaka ,   Asahi Glass Co., Ltd.
Published: November 2016

Glass can be utilized for support or career substrate in large size packaging process since it has excellent mechanical and optical properties. However, the thermal stress caused by a mismatch of coefficient of thermal expansion (CTE) causes an unneglectable warpage during a thermal process.

In order to overcome this thermal stress issue, we have developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on a glass substrate whose CTE is perfectly matched with that of Si, and a series of glass substrates whose CTEs are controlled in sub-ppm order and within the range of 3.3 ~ 12.0 ppm/°C.

To evaluate the effect of glass CTE on the thermal stress management, the warpage behavior of Si wafer after glass wafer bonding were investigated by both numerical simulation and experiment. Both results indicate that a small CTE mismatch can cause an unneglectable wafer warpage during the thermal process. Thus sub-ppm order control of glass CTE is essential for minimizing thermal stress development in large size packaging process.

The glass substrate with Si matched CTE is suitable for the process where glass and Si are contact directly, e.g. Si back grinding process or through glass via (TGV) technology. The series of glass substrates whose CTEs are finely controlled in a high range are useful when the packaging process utilizes high amount of resins, such as Fan-Out wafer level packaging process.
Measuring Die Tilt Using Shadow Moiré Optical Measurements; New Techniques for Discontinuous and Semi-Reflective Surfaces
Authors: Hubble Neil
Published: November 2016

When dealing with production of Flip Chip Packages in semiconductor packaging, the angle between the die and package substrate is critical for maintaining product yield and reliability. Current outgoing quality checks for die tilt can be time consuming to measure heights via point to point measurement techniques. Existing die tilt measurement approaches can also have reproducibility issues from user to user.

Shadow moiré technology is a full field optical inspection technique commonly used for flatness characterization in the semiconductor industry, particularly at elevated temperatures. Two limitations to shadow moiré apply when discussing outgoing QC of die tilt: 1) shadow moiré requires a diffuse reflective surface for measurement; 2) shadow moiré is unable to measure sudden step heights.

This paper discusses applications techniques and real world examples to overcome or mitigate the limitations of shadow moiré technology and use this full field and high speed measurement technology to measure die tilt. Using shadow moiré for this measurement technology can reduce measurement and user time as well as improve consistency of measurements from user to user. As shadow moiré tools are often used for at temperature flatness measurements, this added application can reduce the number of different measurement tools needed in QA labs.
Achieving Low Voiding with Lead Free Solder Paste for Power Devices
Authors: Zappella Pierino I , Sedehi Saeed , Hizon Robert , Williams Adrienne D.
Published: November 2016

The objective of this research was: (1) to demonstrate a low void concentration of <5% using solder paste on different materials such as nickel to nickel, copper to copper, nickel to copper, silicon die to nickel and silicon die to copper; (2) to achieve a short cycle time for the solder paste reflow operation and (3) to highlight the advantages of solder paste vs. AuSn and other alloy preforms that require gold metallization.

For power device applications where low void concentration and reduced costs are important, we have demonstrated a solder paste solution that can offer a lower cost solution. The flux incorporated in solder paste is a major contributor in creating voids. Our approach was to utilize different pressures to reduce voids resulting in higher production yields.

Test coupons of pure nickel and copper were sized to simulate die and substrates. Silicon device die were also included. A lead free 95Sn5Ag alloy water soluble solder paste was selected for this evaluation. The paste application consisted of a manual screen print with templates of different thicknesses. Void detection concentrations were identified via our in-house X-ray system. The advantages of solder paste can be significant, but typically, we would expect an increase in voids resulted from the flux incorporated in the paste. Accordingly, in this paper, we evaluated a low voiding flux solder paste compatible with power device metal materials and suitable for use in a production environment.
Transient liquid phase sintering materials (TLPS) vs. conventional solders for high temperature MLCC interconnects.
Authors: McConnell John , Bultitude J. , Jones L. , Qazi J.
Published: November 2016

There is a growing need within the electronics industry for interconnect materials that can meet higher processing and operating temperatures. The solidus to liquidus range of current tin (Sn) based solders and other lead (Pb) solders are narrower than traditional SnPb solders as the industry is moving to higher temperatures. Transient Liquid Phase Sintering (TLPS) is a technology that offers low processing temperatures while having high temperature capabilities but has had limited exposure outside of the Semiconductor industry. Results of mechanical testing as well as product environmental data is presented herein as TLPS is used as a mechanical and electrical interconnect for Multi-Layer Ceramic Capacitors (MLCC).
Study of Void Formation Mechanism in Electroplated SnAg Solder Bump
Authors: Tatsumi Koji , Sakai Akio , Kawai Syunsuke , Katase Takuma , Miyazawa Takashi , Ishikawa Masayuki
Published: November 2016

SnAg electroplating method is widely used in the formation of LF solder bump for flip chip connection. While electroplating is able to form void free solder bump in a suitable operating condition, void may occur suddenly when used in mass production. This study aims at understanding the gas source in the void of electroplated SnAg solder bumps and determining the manufacturing process factors which affect the void formation.

There are various types of void formation mode. One mode is H2 gas generation on cathode surface during electroplating. Both the cross-sections of solder bumps, as well as an analysis data of the gas in the void taken by the TDS (Thermal Desorption Spectrometry) were evaluated. The cross-section of the solder bump which contains void due to the reflow process revealed the existence of several tens of nm to several μm size pits in the solder bump before reflow. TDS analysis indicates that the pits consisted of mainly H2O, H2 and the decomposition of organics. A possible void formation mechanism is the evaporation of H2 gas and the incorporated electrolyte solution in the bump by reflow. These pits in the solder were caused by various process parameters. One of the causes is due to the setting of the current density in the SnAg electroplating process being inappropriate. The current density should be adjusted corresponding to the electrolyte performance and bump design such as PR thickness, opening diameter and bump density. The computer simulation demonstrated that a thick PR limits the diffusion of the Sn2+ ions into via holes and having the current density too high causes a lack of Sn2+ ions on the cathode surface and causes H2 gas generation.

The other mode of void formation is Ag displacement of the under bump metallization (UBM) surface in dwell time in the SnAg electrolyte solution before the start of plating. The adjustment of each process parameter can eliminate the source of the void and achieve a high reliability of SnAg bump formation.
Effects of x-ray exposure on NOR and NAND flash memories during high-resolution 2D and 3D x-ray inspection
Authors: Sharma Anju , Sivakumar Preeth , Feigel Andrew , Bae In Tae , Lehman Lawrence P. , Gregor Joseph , Cash James , Kolly Joseph
Published: November 2016

In this paper, we present a detailed study on the effects of x-ray exposure on data corruption in commercially available NOR and NAND flash memory devices during x-ray inspection with a high-resolution Phoenix Nanomex system from GE. We investigated role of the x-ray tube voltage, tube current, device orientation, x-ray filters and photon energy. We explored the low exposure regime in detail when the first byte errors start occurring and also determined the absorbed dose for 100% byte errors. No data corruption was observed after the normal 2D x-ray inspection and CT scans of the NOR and NAND flash memory devices under study. However, increase in the tube voltage, tube current and/or the x-ray beam size resulted in byte errors which increased exponentially with the exposure time. The byte error rate was found to be much more sensitive to the tube voltage than the tube current. It was also affected by the device orientation with respect to the x-ray beam. The NAND flash memories were found to be more susceptible to data corruption from x-ray exposure than the NOR devices examined in this work. Some NOR devices were irradiated with the monochromatic x-rays from the CHESS synchrotron facility at Cornell University. Of all the photon energies used in this study, 12 keV x-ray irradiation resulted in the highest byte error rate. In this paper, we thus present a direct proof that it is the low-energy photon absorption that plays a major role in introducing bit errors in flash memories. Commonly available low-energy x-ray filters such as Cu and Al foils were found to be effective in preventing data corruption in such devices for long exposure time. Use of lower tube voltage, lower tube current, smaller x-ray spot size, short exposure time and low-energy x-ray filters, is recommended to prevent data corruption during 2D and 3D x-ray inspection of flash memory devices and other semiconductor devices in general.
The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components
Authors: Whitmore Mark , Schake Jeff
Published: November 2016

With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged.

For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components.

In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.
Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization
Authors: Chien Chun-Hsien , Chen Yu-Hua , Hsieh Yu-Chung , Lin Wei-Ti , Chen Chien-Chou , Hu Dyi-Chung , Tseng Tzvy-Jang , Shenoy Ravi
Published: November 2016

This paper aims to discuss the integration of 3D solenoid inductors fabricated by using a glass core substrate with through glass via (TGV) technology. Glass materials were chosen for the substrate core based on the natural properties of low insertion loss, adjustable CTE, low surface roughness and high insulation for RF application. The TGV formation and semi-additive conformal copper electroplating were the key processes of the glass core substrate manufacturing. The key benefits of these evaluations are a competitive cost structure for a 508mm × 508mm glass panel IC (integrated circuit) substrate HVM (high volume manufacture) line. The characterization results of TGV formation, the process flow of 3D solenoid inductor glass core substrate and real silicon device chips assembled on the top of glass core substrate were also investigated and discussed.
Silicon based cell sorting device: Fabrication, characterization and applications
Authors: Majeed Bivragh , Liu Chengxun , Sohn Erik , Van Acker Lut , De Wijs Koen , Sabuncuoglu Deniz , Lagae Liesbet
Published: November 2016

Cell sorting is an important diagnostic tool used in various aspect of medical prognosis. Numerous cell sorting techniques are currently available on market but they are quite bulky, expensive and at the same time requires very trained operators. In this paper we report on wafer level fabrication technique that will allows for a small form factor device targeting cell sorting. We give detailed overview for the fabrication of our miniaturized cell sorter that is formed with a CMOS compatible process. It used standard fabrication technique in combination with photo-patternable polymer, that has excellent properties for microfluidics applications. The ability to process on wafer level distinguish this from other processes, whose yields are limited to few test samples. The device fabrication includes: processing of micro-heaters, definition of polymer microfluidic channels and collective die-to-wafer bonding of glass substrate onto the polymer channels. We report on the initial characterization of the cell sorting targeting sorting rate and sorting yield. We have achieved sorting rate of 5,000 cells/s and yield of 70% is obtained in initial investigations.
Embedded RDL formation in Non-Photo Polymers using Excimer Laser Ablation
Authors: Hichri Habib , Lee Seongkuk , Arendt Markus , Malik Sanjay , Dimov Ognian , Sakamuri Raj , Sundaran Venky
Published: November 2016

The continuous trend towards miniaturization, increasing performance and mobility of electronic devices drives interconnect density and integration, not only at the chip level, but also at interposer and package level. Silicon interposers coming from wafer foundries using back end of line (BEOL) redistribution layer (RDL) processes have been introduced successfully. However, there is a continuing need for low cost interposers based on large organic or glass panels. While traditional organic flip-chip substrates using semi-additive processes (SAP) have not been able to scale to ultra-fine RDL pitches, photo-sensitive spin-on dielectrics and RDL processes used for wafer level packaging do not sufficiently address the cost reduction need, This paper presents the latest results from cost effective and innovative package RDL processes using excimer laser ablation, to meet the market's most stringent requirements.

To enable panel and wafer based interposers to reduce RDL cost and scale interconnect pitch to 40um and below, excimer laser ablation is introduced as a direct patterning process that uses proven industrialized excimer laser sources to emit high-energy pulses at short wavelengths to remove polymer materials with high precision and high throughput. The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet-processing. In addition, with excimer laser patterning technology the industry gains a much wider choice of dielectric materials (photo and non-photo) to help achieve further reductions in manufacturing costs as well as enhancements in interposer and package performance.

In this paper, we propose new process that uses excimer laser ablation to integrate via and RDL traces in one patterning process step, followed by seed layer deposition, plating and planarization steps. A new integration process flow is proposed, and its technical robustness and commercial advantages have been demonstrated. The capability of this excimer laser process to extend the current material portfolio to non-photo materials will be discussed, and its commercial benefits as compared to the current process of record (POR) will be highlighted.