(Invited) Thermal Transport in 2D Materials from First Principles: The Role of Interface and Substrate
Authors: Aksamija Zlatan 
Published: May 2020

The persistent down-scaling of nanostructures, such as electronic devices, sensors, NEMS, and nanocomposites, increases the surface-to-volume ratio and introduces atomic-scale disorder at boundaries and interfaces. To avoid these issues, the nanoelectronics community has turned to intrinsically two-dimensional (2D) materials platforms. 2D materials have tremendous potential for next-generation nanoelectronics beyond the 5 nm technology node due to their atomic flatness and absence of dangling bonds, which prevents scattering from interface roughness. However, heat dissipation and its removal from hot spots in the monolayer remains a critical concern to the design of 2D-based devices [1]. Thermal currents flowing in an atomic layer can either dissipate through source/drain contacts in a transistor configuration, or through a supporting substrate via van der Waals (vdW) coupling to it. When a 2D material is supported by a substrate, the interfacial area formed between it and the substrate is often far larger than the lateral source/drain contact area. Thus, the majority of waste heat is removed across the 2D-substrate interface and then via the substrate.

The thermal boundary conductance (TBC) between the 2D layer and substrate should be well characterized for reliable 2D device performance. Interfaces formed between 2D vdW materials and 3D substrates are fundamentally different than same-dimension 3D-3D and 2D-2D interfaces due to the presence of a vdW gap and the different dimensionalities of the phase spaces on either side of the interface. In this invited talk, I will review the progress in understanding lattice thermal transport, both in-plane and cross-plane, in 2D mono and few-layer materials from first principles. This work builds on vibrational properties of the 2D materials calculated from Density Functional Theory combined with Boltzmann transport equation for phonons. Then I will introduce our recent work aimed to tackle the question of selecting the best substrate for each 2D material from the point of view of heat dissipation and apply these results to 2D devices.

Several recent papers measured the TBC between various monolayers and mostly the silicon dioxide (SiO2) substrate, reporting a wide range of values due to inconsistent sample quality. Therefore, it is imperative to build predictive methods for quantifying the TBC between MLs and various substrates. Here, we use a combination of phonon dispersions from first-principles density functional perturbation theory simulations and our 2D-3D TBC model [2, 3]. We investigate the TBC between combinations of six atomic layers (h-BN, graphene, MoS2, MoSe2, WS2, and WSe2) and six substrates (SiO2, AlN, GaN, 6H-SiC, diamond, and Al2O3). We show that TBC is higher for softer substrates with smaller speed of sound, but of the 6 substrates we compared, amorphous SiO2 consistently produced higher TBC than crystalline substrates. Our work helps build a roadmap for quantifying the TBC between various 2D monolayers and their substrates and provides a framework for other 2D-3D interfaces to be studied.

Next, we employ our first-principles model to calculate the TBC of several beyond-graphene 2D materials, such as and blue and black phosphorene, on amorphous and crystalline substrates. A trend emerges that 2D materials with lower ZA branch frequencies have higher TBCs when placed on a-SiO2. Our results provide selection criteria for 2D materials that improve interfacial heat transport in 2D devices with amorphous and crystalline substrates.

To further probe the role of interfacial phonon transport, we develop a coupled electro-thermal model for FL-WSe2 stacks where we simultaneously solve for the current and Joule heating by treating the stack a resistor network. The resulting rise in temperature is obtained from a FL-TBC model [4] to shed light on self-heating and heat dissipation in such devices. We find that the temperature rise in the top layers is significantly larger than the bottom layers because the bottom layers have higher TBC and conduct heat more efficiently to the substrate [4,5]. The higher temperature of top layers, in turn, significantly reduces their mobility, which is strongly temperature-dependent as they are shielded by the bottom layers from substrate impurity scattering. We also uncover that, unlike monolayer FETs, a significant amount of heat is dissipated laterally through the contacts in FL devices at high VDS due to relatively large thermal healing lengths of the top layers.

References:

[1] Yalon, E., et al., Nano Letters 17, 3429–3433 (2017).

[2] Yasaei, P., et al., Advanced Materials Interfaces, 1700334 (2017).

[3] Correa, G. C., Foss, C. J., and Aksamija, Z. Nanotechnology 28, 135402 (2017).

[4] Behranginia et al., ACS Applied Materials & Interfaces 10, 24892-24898, 2018

[5] Yasaei et al., Advanced Materials 30, 1801629, 2018