Formation of ZnO Nanoparticles by Atomic Layer Deposition for the Nonvolatile Memory Thin-Film Transistor Applications
Authors: Seo Gi-Ho , Yun Da-Jeong , Lee Won-Ho , Kim So-Jung , Yoon Sung-Min 
Published: February 2020

Charge-trap-type memory device employing oxide-semiconductor charge-trap layers (CTL), such as ZnO and In-Ga-Zn-O (IGZO), have been intensively investigated for nonvolatile memory TFT applications [1]. Although encouraging device characteristics could be obtained for the proposed memory TFT, they can be expected to be far improved by using nano-particle (NP) mono-layers as alternative CTLs thanks to their isolated structures. So far, various methods such as spray pyrolysis and high-temperature-assisted self-assembly have been suggested to form discrete NP mono-layers [2]. However, low controllability in areal density of NPs and high process temperature limit device performance as well as process compatibility on flexible substrate.

In this work, we propose a low-temperature atomic-layer-deposition (ALD) process for the formation of ZnO NPs with an island-growth mechanism and fabricated the memory TFTs using the ZnO-NP CTLs. We also investigate the effects of ALD conditions for the ZnO NPs on the device performance of the fabricated ZnO-NP memory TFTs (NP-MTFT). The gate-stack structure of top-gate NP-MTFTs were designed as In-Sn-O (ITO) gate electrode (150 nm)/Al2O3 blocking oxide (50 nm)/ZnO NP CTL/Al2O3 tunneling layer (10 nm)/IGZO active channel layer (20 nm)/ITO source-drain electrode (100 nm). ALD cycles for the ZnO NPs were varied to 5, 20, 30, and 40 and the deposition temperature was modulated from 100 to 190oC to investigate the effects of ALD conditions on the island formation of ZnO NPs. Diethylzinc (DEZn) and H2O was used as Zn and O precursors, respectively. The size and areal density of the ZnO NPs prepared at 160oC with 20 ALD cycles were estimated to be approximately 33 nm and 3×109 cm-2, respectively. It was interesting to note the changes in arithmetic average of surface roughness (Ra) at various ALD temperatures when the ALD cycles increased from 5 to 20 cycles. The variations in Ra were summarized to be from 0.24 to 0.28 nm at 100oC, from 0.26 to 0.40 nm at 130oC, from 0.98 to 2.13 nm at 160oC, and from 0.21 to 0.22 nm at 190oC. Consequently, it was found that the island growth of ZnO NPs could not be available at 100 and 190oC. On the other hand, at 160oC, the ZnO NPs could be successfully formed with appropriate deposition rate with increasing the ALD cycles.

The NP-MTFTs employing these ZnO NP CTLs exhibited typical charge-trap nonvolatile memory device behaviors. The memory window (MW) width of the fabricated NP-MTFTs monotonously increased with increasing the ALD cycles from 0.6 to 14.6 V when VGS was swept in the forward and reverse directions in the range of ±20V at a drain bias (VDS) of 0.1 V. The MW (12.2 V) of the NP-MTFT drastically was increased for the 20-cycle device compared with that for the 5-cycle device. This result suggests that the areal density of ZnO NPs could be effectively modulated by controlling the ALD cycles of DEZ between 5 and 20 cycles. The on- and off-program characteristics of the NP-MTFTs were evaluated as a function of program voltage pulse width. The read-out operations were performed at VGS of -2 V and VDS of 0.1 V. The ratios of programmed IDS of on-states to that of off-states (Ion/Ioff) were obtained as more than 3×107 and did not experienced marked degradation when the program pulse width decreased from 1 s to 1 µs. These results suggest that the proposed NP-MTFT exhibited nonvolatile memory operations with wide memory window and high-speed program time. This is the first demonstration for the NP-MTFTs using the ALD-assisted ZnO-NP CTLs. Flexible memory device will be fabricated as future works and detailed device characteristics will be discussed at the presentation.

 

[1] S. J. Kim, W. H. Lee, C. W. Byun, C. S. Hwang, and S. M. Yoon, IEEE Electron. Dev. Lett. 36 (11) 1153, 2015.

[2] Z. Liu, C. H. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron. Dev. 49 (9), 1606, 2002.