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Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating
Authors: Hong Won-Eui , Ro Jae-Sang
Published: February 2020

Abstract

Large area crystallization of amorphous silicon (a-Si) thin-films on glass substrates is one of the key technologies for manufacturing flat displays on commercial scales. Low-temperature polycrystalline silicon (LTPS) is a crucial active-layer material for polycrystalline silicon thin-film-transistors (poly-Si TFTs) mounted on thermally susceptible glass substrates. LTPS-TFT backplanes are required for fabricating flat panel displays such as active-matrix liquid-crystal-displays and active-matrix organic-light-emitting diodes (AMOLEDs). The LTPS-TFT backplanes are strongly preferred over a-Si TFTs since several devices, AMOLEDs in particular, operate in a current-driven mode. The crystallization methods used for producing LTPS include solid phase crystallization, metal induced crystallization, and excimer laser crystallization (ELC). The ELC method is currently used for crystallizing the a-Si films in mass production lines.

Recently, we developed a novel and highly promising crystallization method named Joule-heating induced crystallization (JIC) by which an entire a-Si film could be crystallized on a glass backplane within tens of microseconds. However, arc instability was observed during the crystallization, which is attributed to the dielectric breakdown in the conductor/insulator/a-Si sandwich-structures at high temperatures during electrical pulsing for crystallization. We devised a method for crystallizing the a-Si films while preventing arc generation; in this method an a-Si active layer was pre-patterned into islands followed by the deposition of a gate oxide and gate electrode. An electric pulse was then applied to the gate electrode formed using a Mo layer. The Mo-layer was used as a Joule-heat source for the crystallization of the pre-patterned active islands of the a-Si films located below the Mo-layer. The JIC-processed poly-Si TFTs were fabricated successfully and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

In this report, we will discuss some critical issues concerning the arc generation, glass backplane deformation, and phase-transformation phenomena observed during the JIC process on the basis of theoretical investigations as well as in-situ and ex-situ experiments. Finally, we will discuss the procedure for fabricating stable JIC poly-Si TFTs and optimize the process flow and processing conditions such as the power density and pulsing time for fabricating the JIC poly-Si TFTS.

Figure 1
Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping
Authors: Hiraiwa Mitsuhisa , Nguyen Thuy Thi , Kuroki Shin-Ichiro
Published: February 2020

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved.

Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced.

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Ultra-Thin Flexible Electronics with the Enhancement Inverter Based-on Pentacene Thin Film Transistor
Authors: Lee Dong-Hoon , Cho Hyeong Jun , Kim Min Su , Oh JongSu , Park Eng-kyu , Wang Sihan , Kim Yong-Sang
Published: February 2020

Thin film technology is advancing the research on fully flexible system for new applications in various fields, such as electronics, sensors and energy harvesting. In particular, thin film transistor (TFT) based flexible circuits have been studied for diagnostic devices, solar-cells, and flexible display. Although many companies and research groups have presented semi-flexible devices; a fully flexible system has not shown the sufficient result in terms of mechanical and electrical performance. Recently, inorganic-organic hybrid type TFTs have been developed and it shows the useful performance. However, the devices show limited performance at extremely small bending radius (< 1mm). In order to overcome the limitations, many researchers have suggested various solutions such as new materials of high mechanical strength, neutral strain position fabrication and ultra-thin substrates. Among these solutions, ultra-thin substrate is promising in the field of smart-skin, implantable device and patch-type biosensor. Depending on the decreasing substrate thickness, the strain strength also decreases dramatically. In this study, we demonstrate a nm-level ultra-thin device based on pentacene TFT, using de-bonding-technology. For de-bonding, a double layer of PVA and PAA based water soluble release layer was spin coated on the glass substrate. Subsequently, we coated the buffer layer on the release layer. The Al as gate electrode was deposited on the buffer layer by thermal evaporation. PMMA was then spin-coated and baked at 100 °C for 30 min. The pentacene and gold layer was deposited using thermal evaporation. CYTOP material was used for the passivation of the device. Finally, the device was de-bonded in double deionized water followed by curing at 75 °C for 30 min. Based on this process, we fabricated the nm-level thick TFT and enhancement inverter. After de-bonding process, the nm-level ultra-thin device showed good performance compared with the initial device before de-bonding.
Investigation of High Current Tetracene-TFT Using Surface Nitrided SiO2 Gate Insulator Film
Authors: Nakao Hiroki , Hori Kabuto , Iwazaki Yoshitaka , Ueno Tomo
Published: February 2020

The use of surface nitrided SiO2 film as gate insulator of tetracene-TFT (Thin Film Transistor) has been proposed. Using Ar/N2 plasma, the nitridation has been carried out on the SiO2 surface to remove carrier trapping sites due to hydroxyl groups. As a result, transistor output characteristics have been drastically improved with extremely high current level using tetracene film as organic semiconductor material.

Recently, there has been widely interested in organic-TFT because of its flexibility, ability to have a lot of material designs, applicability to large area devices and so on. However, the surface of conventional gate insulator such as SiO2and other metal oxide films often contain charge trapping sites due to the existence of hydroxyl (-OH) groups and surface defects. The carriers of organic-TFT have to move at the surface layer in the organic film adjacent to the gate insulator. Therefore it is important to control the surface and/or interface of organic film and gate insulator to avoid the carrier scattering at the charge trapping sites.

Now, commonly used method to overcome this problem is deposition of SAM (Self-Assembled-Monolayer) film on the gate insulator. As a result, it is reported that electrical characteristics have been drastically improved. But it takes time about at least half a day to deposit the SAM film.

In this paper, we have attempted to improve the carrier mobility in the tetracene film as organic semiconductor material, with surface nitride SiO2 film as the gate insulator for a short processing time. Figure1 shows transistor output characteristics with the channel length (L) = 70[um] and channel width (W) = 2000[um], respectively. It is clearly shown the extremely high current have been achieved from the tetracene-TFT on surface nitrided SiO2. On the contrary, no modulation due to gate bias could be achieved on SiO2film without the nitridation.

Also, to clarify the difference, the property of tetracene/SiO2 interface of each sample, C-V measurement has been carried out. After the nitridation have been done on the SiO2 surface that had been etched with dil-HF to make hydroxyl groups, the width of C-V hysteresis is decreased. Therefore we can conclude the surface nitridation of SiO2 films with Ar/N2 plasma is effective method to remove charge trapping sites related to hydroxyl groups and improve transistor output characteristics.

Figure 1
(Invited) Highly Robust a-IGZO TFT for Foldable Displays
Authors: Lee Suhui , Billah Mohammad Masum , Mativenga Mallory , Jang Jin
Published: February 2020

The amorphous-oxide-semiconductor (AOS), particularly amorphous-indium-gallium-zinc-oxide (a-IGZO), has attracted considerable attention for applications in large-size, flexible AMOLED displays because it yields high device performance even when sputter deposited at temperatures that are compatible with plastic substrates. In particular, a-IGZO is now considered the most favorable material for designing integrated circuits used in display applications because of its mobility and processing compatibility with plastic substrates. To realize a flexible AMOLED display, the TFT backplane should be fabricated on a flexible substrate. One of challenge in making flexible AMOLED displays is the integration of driver circuits on the TFT backplane. The use of rigid external driver circuits limits the display flexibility because excessive bending may result in the detachment of/damage to the rigid external driver circuits. We have demonstrated foldable thin-film transistor (TFT) fabricated on a free-standing plastic substrate. With extreme bending machine, the repeated extreme bending stress was applied on the TFTs up to 10,000 times. If the bending stress applied along the strain perpendicularly on the channel current flow, conventional TFT characteristics degraded under extreme bending stress. In the a-IGZO TFTs with source and drain electrode splitted, no degradation could be found under the extreme bending stress. It is because in the reducing the area of metal electrode and active layer, occurring cracks by the extreme bending remarkably decreased after extreme bending up to 10,000 times. Therefore, the TFTs and TFT gate drivers perform well after repeated bendings. We will present the model to explain the experimental results.
Heterostructure Source-Gated Transistors: Challenges in Design and Fabrication
Authors: Sporea Radu Alexandru , Jayawardena K. D. G. Imalka , Constantinou Marios , Ritchie Munroe , Brewin Alistair , Wright William , Silva S. Ravi P.
Published: February 2020

Source-gated transistors (SGTs) [1, 2] use a potential barrier at the source to produce low-voltage saturation and flat saturated characteristics. This, in turn, results in excellent power efficiency and amplification performance [3-5].

Usually, SGTs are made with a Schottky source contact which acts as the current-control mechanism. These devices are easy to fabricate in a multitude of semiconductor systems, but may suffer, depending on design, from reduced dynamic range of the current above the threshold, and from significant temperature dependence of the on-current.

We propose an alternative method of making SGTs, using an ohmic source contact and a bulk barrier. We call devices realised following this principle bulk unipolar barrier source-gated transistors (BUSGTs). Several strategies for realising the bulk barrier exist, which depend on the material system and fabrication process considered [6].

Here, we realise the bulk barrier at the source with a tri-layer semiconductor heterostructure (Figure 1, top). The advantages of this architecture include improved dynamic range (Figure 1, bottom) and reduced temperature dependence of drain current, as well as the usual energy and gain characteristics of SGTs.

Measurement results on C70/C60/C70 n-type devices show: low hysteresis, indicating good quality interfaces; a large threshold shift due to the bulk barrier and residual charge in the heterostructure; and FET-like saturation, due to the interplay between semiconductor mobility and barrier height. A strong correlation is found between measurements and simulations using Silvaco Atlas.

We discuss the benefits of such structures, and also the fabrication and design challenges associated with this type of transistor (chemistry and materials, barrier realisation, interface properties, requirements on charge carrier mobility).

[1] S. D. Brotherton, Introduction to Thin Film Transistors: Physics and Technology of TFTs, Springer, 453–480, Cham (2013); [2] A. Valletta et al., J. Appl. Phys. 114 064501 (2013); [3] R. A. Sporea et al., Scientific Reports
4 4295 (2014); [4] R. A. Sporea, ULSI vs TFT V (2015); [5] R. A. Sporea et al., AA3.07, MRS Fall, Boston (2015); [6] J. M. Shannon, APL 35 (1) 63–65 (1979).

Figure 1 – Top: fabricated tri-layer fullerene heterostructure, showing the position of the bulk barrier at the source; bottom: transfer characteristic of the fabricated devices, illustrating high dynamic range above threshold, low hysteresis, and significant threshold shift as due to the bulk barrier.

Figure 1
Amplifier Circuit with Oxide TFT
Authors: Han Ye Lin , Kang In Hye , Jeon Young Eun , Lee Young Jin , Bae Byung Seong
Published: February 2020

Oxide TFT (thin film transistor) has higher electron mobility and less leakage current than amorphous silicon TFT. Among oxide TFTs such as ZnO, InZnO, InGaZnO and so on, the IGZO TFT has being studied by many researchers and being used in the display backplane. In this presentation, an amplifier circuit with oxide TFTs was developed for the higher voltage gain.

Most commonly used type of power amplifier is the Class A Amplifier. The Class A amplifier is the most common and simplest form of power amplifier, in which transistor is always biased on-state so that it conducts during one complete cycle of the input signal waveform producing minimum distortion and maximum amplitude to the output. The efficiency of this type of circuit is low and delivers small power outputs.

To get high amplification gain, we designed an amplifier circuit based on inverter and optimized the channel width of each TFTs. The circuit developed is a common source amplifier, which is a single transistor amplifier that the input terminal is the gate and the source, output terminal is the drain and the source. In that type of amplifier circuit, the ratio of the widths of load transistor and drive transistor should be optimized for the highest gain. The DC operating voltage for the input gate electrode is also important, and the conventional way to get the operation voltage is using resistor divider, in which we should design the resistor divider according to the characteristics of TFT. In this presentation, we proposed the auto setting operation voltage scheme instead of resistor divider, and obtained the voltage gain of 14.
The Oxide TFT with Solution Based Gate Insulator
Authors: Hong Min-Taek , Shin Seong Min , Lee Jong mo , Jacques Emmanuel , Mohammed-Brahim Tayeb , Bae Byung Seong
Published: February 2020

Low temperature poly-Silicon (LTPS) thin film transistor (TFT) and Oxide TFT are developed for the better performance of the active matrix display. Recently, oxide TFT has been investigated intensively due to simple process and higher mobility than amorphous silicon TFT.

Typical parameters of TFT are mobility, threshold voltage and On/Off ratio which are influenced by gate insulator. The widely used material for gate insulator is SiO2 which is rich in the earth and inexpensive. But vacuum equipments like the plasma enhanced chemical vapor deposition (PECVD) and the RF Magnetron sputter need large investment and maintenance cost than non-vacuum process.

Oxide TFT of top gate structure reduces the parasitic capacitance between source-drain and gate metal. The plasma damage during deposition of gate insulator on an oxide active layer cause the defects which deteriorate TFT characteristics. However, the gate insulator by solution process reduces the defects by plasma process.

SU-8 which is a negative photoresist (PR) has been being used widely in micro electro mechanical system (MEMS). It is constituted with octuple epoxy groups and includes photosensitize to react with UV light. The polymer network generated by cross-linking has mechanical and chemical stabilities and high electrical resistance. In this experiments, SU-8 was used for the gate insulator of the oxide TFT and investigated the effect of the SU-8 gate insulator on the oxide TFT.

In this paper, we investigated the characteristics of gate insulator of SU-8 as changing UV exposure time to SU-8. SU-8 was coated by spin coating with 2000 rpm on a p-type Si wafer. After soft-bake for 1.5 min at 95˚C, UV of 365 nm was exposed at an energy of 320mJ/s. Exposure times were varied as 30s, 60s, 120s, and 240s. After UV exposure, hard bake was done for 20 min at 115˚C. An Al layer was deposited on SU-8, and electrical properties of the SU-8 were measured after post-annealing.

Figure 1 shows the current densities of the SU-8 insulators for various exposure time from 30s to 240s. As shown in Fig. 1, the leakage currents decreased as the exposure time increased from 30s to 240s. For the gate insulator of the oxide TFT, the proper UV exposure is important.

Figure 1
Operational Amplifier Circuits with Oxide Thin Film Transistors
Authors: Kang In Hye , Hwang Jun Young , Hong Min-Taek , Lee Jong Mo , Bae Byung Seong
Published: February 2020

Amorphous silicon thin film transistors (TFTs) have been used widely due to good uniformity and low process cost. However, They are not suitable for a circuit due to the low carrier mobility. Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistor (a-IGZO TFT) exhibits higher mobility and lower leakage current than amorphous silicon TFT and it is common to use only n-type a-IGZO TFT due to a poor electrical property of p-type TFT. In this paper, we developed operational amplifier (op-amp) circuit using only the n-type a-IGZO TFTs.

Recently, medical device circuits for measuring bio-signals are being implemented on a wearable devices. Oxide TFTs are suitable for the integrated circuit for such applications. The analog signal processing such as amplification, and filtering of much noise are necessary for analog electrical signals introduced from bio-sensors.

The op-amp is most widely used amplifiers due to ideal linear performance characteristics. An op-amp is composed of two input voltages (+Vin, -Vin), two power supply voltages (+VDD, -VDD) and one output voltage (Vout). It amplifies the voltage difference between the two input voltages of the non-inverting and inverting inputs (+Vin, -Vin).

The op-amp with a-IGZO TFTs has lower gain than that of the op-amp by CMOS process and need increase of the gain by cascaded amplifier stages. We developed a single power supply (+VDD = +15V) OP amp with improved gain. The circuit is composed of three stages: the first is differential amplifier(T1~T8) of input stage, the second is common-source amplifier(T9~T17), and the third is output buffer(T18~T19) of the output stage.

The differential amplifier of the first stage amplified the differential voltage for given input signals (+Vin, -Vin). The output voltage was amplified at the common-source amplifier stage of the second stage. Common-source amplifiers were used for a large voltage gain. After optimization of the circuits, the input voltage of 0.05V was amplified to about 13V.
Improvement of Stress Stability in Back Channel Etch-Type Thin Film Transistors with Post Process Annealing
Authors: Ochi Mototaka , Hino Aya , Goto Hiroshi , Hayashi Kazushi , Kugimiya Toshihiro
Published: February 2020

Because of their superior performances to amorphous silicon (a-Si) semiconductors, amorphous oxide semiconductors have been attracting considerable attentions as backplanes for liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs). For mass production, the back channel etch (BCE)-type TFTs have considerable advantages owing to lesser process steps, lesser parasitic capacitances and shorter channel length than those of the etch stop layer (ESL)-type TFTs. However, the BCE-type TFTs often suffer from the unstable TFT operation against the transfer conditions and the various stress conditions due to the back channel damages to the oxide semiconductor [1-3]. Our study clearly demonstrates an addition of annealing process (post-annealing) that acts as recovery annealing is effective between SiNx deposition and SiOx deposition as passivation layer for the BCE-type TFTs application. The post-annealing effect to improve the stability of the BCE-type TFTs is investigated.

The Oxide TFTs were fabricated on glass substrates with gate electrodes and gate insulator. The IGZO (Indium Gallium Zinc Oxide) thin film was deposited on the substrate by DC magnetron sputtering. Next, source and drain electrodes were formed by wet-etching process using a H2O2-based etchant. The passivation layer composed of double layered SiNx/SiOx was formed by PECVD, and some samples were treated with the aforementioned post-annealing at 300 ℃ in air during the passivation layer formation. It is confirmed that the stability under the negative bias thermal illumination stress (NBTIS) of the BCE-type TFTs with the post-annealing was superior to that of the BCE-type TFT without the post-annealing. In order to clarify the variation of the chemical composition of the IGZO thin film surfaces due to the post-annealing, X-ray Photoelectron Spectroscopy (XPS) was examined as well as electronic state analysis such as photoinduced transient spectroscopy (PITS) [4,5].

[1] G. Wang, Z. Song, X. Xiao, and S. Zhang; AM-FPD 2015 Symposium Digest, pp.111.

[2] M. Nag, A. Bhoolokam, S. Steudel, A. Chasin, K. Myny, J. Maas, G. Groeseneken, and P. Heremans; Jpn. J. Appl. Phys, Vol. 53, No. 11, 111401 (2014).

[3] R. Zhan, C. Dong, P.-T. Liu, and an H.-P. D. Shieh; Microelectronics Reliability, 53, pp.1879 (2013).

[4] J. C. Balland, J. P. Zielinger, M. Tapiero, J. G. Gross, and C. Noguet; J. Phys. D: Appl. Physics, Vol. 19, No. 1 (1986).

[5] A. Hino, Y. Takanashi, H. Tao, S. Morita, M. Ochi, H. Goto, K. Hayashi, and T. Kugimiya; J. Vac. Sci. Technol. B 32 (2014) 031210.

Figure 1
Organic Electrochemical Transistors for Bio-Sensing Applications
Authors: Wang Naixiang , Yan Feng
Published: February 2020

Organic electrochemical transistors (OECT) have been demonstrated and extensively studied as an effective platform for the design of chemical and biological electronic sensing applications, based on their advantages on low-voltage operation, good biocompatibility and interaction with aqueous medium, facile chemical modification of semiconductors and electrodes, and applicability on varied substrates including flexible plastics.[1] However, conventional OECTs are normally fabricated in the scale of millimeter or larger, resulting in a slow response time for device operation.

To overcome this problem, here we develop a novel approach to miniaturize OECT by using only lithographic and magnetron sputtering technique. The channel of OECTs could be reduced to several to twenty microns therefore the speed of device response could be raised up to order of 10-5 s in aqueous medium.

Due to the improvement in transient response time of the micro OECT device, alternating current (AC) is possible to be introduced for device operation. Combined with lock-in amplifier, the small AC channel signal could be precisely extracted from an extremely noisy environment, which provides the possibility to enhance the sensing capability of the OECT devices in complex situations. A new detection method is then established based on AC signal driven micro OECT. The detection limit of dopamine, an important neuro transmitter within the central nervous system, is down to 10-8 M, which is comparable to previous OECT sensor in steady current mode[2]. Furthermore, the pre waiting time to stabilize the device under the newly established AC mode is much shorter (tens of seconds) than conventional device needs (more than 600 s), indicating that the AC signal driven micro OECT could be a promising candidate for rapid sensing and diagnosis applications.

In conclusion, we introduce a simple and easy-to-fabricate process for miniaturization of OECT devices to the cellular dimensions. The advantage of fast transient response makes the AC-driven micro OECT capable of in-situ cell activity monitoring and associated chemical sensing applications.

References:

[1] C. Z. Liao, M. Zhang, M. Y. Yao, T. Hua, L. Li, F. Yan, Adv. Mater.
2015, 27, 7493.

[2] C. Z. Liao, M. Zhang, L. Y. Niu, Z. J. Zheng, F. Yan, J. Mater. Chem. B
2014, 2, 191.
(Invited) Synthesis and Applications of Novel Two-Dimensional Nanomaterials
Authors: Zhang Hua
Published: February 2020

In this talk, I will summarize the recent research on synthesis, characterization and applications of two-dimensional nanomaterials in my group. I will introduce the synthesis and characterization of novel low-dimensional nanomaterials, such as graphene-based composites, and the epitaxial growth of metal and semiconductor nanostructures on solution-processable transition metal dichalcogenide (TMD) nanoshees at ambient conditions, single- or few-layer metal dichalcogenide nanosheets and hybrid nanomaterials, other 2D nanomaterials. Then I will demonstrate the applications of these novel nanomaterials in electronic devices.
(Invited) Nanowire Electrodes for Electrochemical Capacitors and Nanoparticles for Current Conduction
Authors: Nakanishi Hideyuki , Kikuta Ikuo , Kawabata Yuto , Matsumoto Ikuko , Naitoh Yasuaki , Segawa Hiroyo , Norisuye Tomohisa , Tran-Cong-Miyata Qui
Published: February 2020

Electrochemical capacitors (ECs) show the improved energy density, somewhat comparable to batteries, with excellent power density. Depending on the charge storage mechanism, ECs can be separated into two types: 1) supercapacitors, 2) pseudocapacitors. Supercapacitors store charges via the formation of the electric double layers at the interfaces of the electrode and electrolyte. In theory, the specific capacitance of supercapacitors can be linearly scaled with the surface area of the electrode. Hence, high-surface-area carbon nanotubes and graphenes are often used for the electrode of supercapacitors to increase the capacitance. The double layer capacitance is, however, intrinsically limited to a low value, typically in a range of 20 μF/cm2 to 50 μF/cm2. To this limitation, redox active substances have been incorporated with the porous electrodes to spuriously increase the capacitance based on their faradaic reaction (i.e. pseudocapacitance). This type of ECs is also known as pseudocapacitors. Thanks to the faradaic reaction, pseudocapacitors show higher energy density than that of supercapacitors. But instead, the power density of pseudocapacitors deteriorates plausibly due to the charge transfer resistance involved in the redox active substances. In developing pseudocapacitors, in most case, the energy density is increased at the expense of the power density. To improve the energy density without sacrificing the power density, a large number of metal oxides and conducting polymers have been recently examined on their morphology and electrochemical properties for the use of the electrode.

In the present study, we show that monolithic nanowire array electrodes mediate fast ion and electron transport, allowing for charge/discharge at fast rates. In a typical procedure, we prepare a gold nanowire array electrode by the electrodeposition of Au through the cylindrical pores of the in-house anodic aluminum oxide. The subsequent electropolymerization of pyrrole results in the coaxial nanowires in which polypyrrole is conformally coated with the preformed Au nanowires. Thus prepared coaxial nanowire electrodes are examined with galavanostatic charge/discharge measurement and cyclic voltammetry, showing ideal capacitive behaviors even at high charge/discharge rates. The performance of the coaxial nanowires is further examined with electrochemical impedance spectroscopy. The energy capacity and rate capability of the coaxial Ppy/AuNW based pseudocapacitors will be discussed.
(Invited) High-Performance Wearable Supercapacitor Textiles
Authors: Zheng Zijian
Published: February 2020

Wearable supercapacitor textiles are supercapacitors that made use of and/or shaped into textile fibers, yarns, and fabrics, which are inevitable energy storage devices for wearable electronic applications. To date, the major challenge in the development of wearable supercapacitors is how to improve the electrochemical properties of the device while acquiring high flexibility and durability under wearing conditions. Recently, our laboratory has developed several supercapacitor yarns and fabrics, which show record-high electrochemical performances of their kinds as well as excellent flexibility. These textile-based devices can be readily integrated into different textile forms by means of weaving, embroidery, and heat pressing for wearable applications.

Keywords: supercapacitor; wearable electronics; textiles; nanocarbon materials; polymer-assisted metal deposition

References：

[1] Q. Huang, L. Liu, D. Wang, J. Liu, Z. Huang, Z. J. Zheng*, J. Mater. Chem. A. 2016, DOI: 10.1039/c5ta09309k.

[2] L. Liu, Y. Yu, C. Yan, K. Li, Z. J. Zheng*, Nat. Commun. 2015, 6, 7260.

[3] Y. Yu, C. Yan, Z. J. Zheng*, Adv. Mater. 2014, 26, 5508-5516.
OLED Operating Active Matrix Pixel Device Using Two Dimensional Transition Metal Dichalcogenides Channel FET
Authors: Yu Sanghyuck , Kim Jin Sung , Ahn Jongtae , Lim June Yeong , Im Seongil
Published: February 2020

Two-dimensional transition metal dichalcogenides (TMDs) are fundamentally and technologically have been studied for their electronic and physical properties. The simplest Active Matrix pixel has two transistors and one capacitor, one is switch transistor and another is driver transistor. Here we fabricated p-WSe2 channel bottom gate field effect transistors (FETs) on the same glass to organize Active Matrix pixel. Linear mobilities of Switch transistor and Driver transistor were estimated to be ~30 and ~320 cm2/V s and saturation mobilities were estimated to be ~11.7 and 102.2 cm2/V s respectively. Maximum ON-current of driver transistor was measured to be ~387 uA and maximum ON/OFF ratio of switch transistor appeared to be 8x107 V. As a result, our Active Matrix pixel demonstrate organic light emitting diode (OLED) switching for green OLED and showing OLED gray scale properties.

Figure 1
Photodetection of CVD-Grown MoSe2 Monolayer Devices in Infrared Range
Authors: Chang Min-Wei , Lu Ming-Yen , Wang Hsiang-Chen
Published: February 2020

Recently, two-dimensional transition metal dichalcogenides (TMDs), such as MoS2, MoSe2, and WSe2, have bandgaps changing from indirect to direct for multi- to mono-layer. In this work, we successfully synthesized the highly-crystalline MoSe2 monolayers on 300nm SiO2/Si using chemical vapor deposition (CVD) method in atmosphere, the growth setup is illustrated in Fig. 1, an alumina boat containing Se powder located upstream of the furnace and another alumina boat with MoO3 powder located at the center of the heating zone, which is 20 cm away from the Se powder. Cleaned 300 nm SiO2/Si substrate were placed downstream near MoO3 powder. The heating zone was heated to 750oC at a rate of 20oC/min. After the temperature was reached, the heating zone was kept for 10 min then naturally cooled to room temperature. Atomic force microscopy (AFM) and Raman spectroscopy confirmed that the as-grown MoSe2 layers are ranging from single layer to multilayers by means of controllable parameters. Transmission electron microscopy (TEM) analysis showed the single-crystallinity of MoSe2 layers with the perfect hexagonal lattice. Moreover, MoSe2 monolayer has a direct bandgap of 1.5 eV, which is close to the optimal bandgap value of infrared photodetectors (IRPDs), the fast and ultrasensitive photodetection of MoSe2 monolayer devices was demonstrated. This technique is expected to have potential use in future ultracompact near-infrared photodetectors and optical memory devices.

Figure 1
(Invited) Contributions of Phase, Sulfur Vacancies, and Edges to the Hydrogen Evolution Reaction Catalytic Activity of Porous Molybdenum Disulfide Nanosheets
Authors: Ying Yin , Han Jiecai , Song Bo
Published: February 2020

Contributions of Phase, Sulfur Vacancies, and Edges to the Hydrogen Evolution Reaction Catalytic Activity of Porous Molybdenum Disulfide Nanosheets

 

Ying Yin,1 Jiecai Han,1 and Bo Song2,
*

1Centre for Composite Materials and Structures, Harbin Institute of Technology, Harbin 150080, China

2Academy of Fundamental and Interdisciplinary Sciences, Harbin Institute of Technology, Harbin 150080, China

Molybdenum disulfide (MoS2) is a promising non-precious catalyst for the hydrogen evolution reaction (HER) that has been extensively studied due to its excellent performance, but the lack of understanding on the factors that impact its catalytic activity hinders further design and enhancement of MoS2-based electrocatalysts. Here, by using novel porous MoS2 nanosheets synthesized through a liquid ammonia-assisted lithiation route, we systematically investigated the contributions of crystal structure (phase), edges, and sulfur vacancies (S-vacancies) to the catalytic activity towards HER from five representative MoS2 nanosheet samples, including 2H and 1T-phase, porous 2H and 1T-phase, and sulfur compensated porous 2H-phase. Superior HER catalytic activity was achieved in the porous 1T-phase MoS2 nanosheets that have even more edges and S-vacancies than conventional 1T-phase MoS2. A comparative study revealed that not only phase serves as the key role in determining the HER performance, as 1T-phase MoS2 always outperforms the corresponding 2H-phase MoS2 samples, but also both edges and S-vacancies also contribute significantly to the catalytic activity in porous MoS2 samples. Then, using combined defect characterization techniques of electron spin resonance (ESR) spectroscopy and positron annihilation lifetime spectroscopy (PALS) to quantify the S-vacancies, the contributions of each factor were individually elucidated. This study presents new insights and opens up new avenues for designing electrocatalysts based on MoS2 or other layered materials with enhanced HER performance.

*Corresponding Author: songbo@hit.edu.cn
Synthesis of Alternate Layered Structure of Ruthenate Nanosheet-Graphene Oxide for Electrochemical Applications
Authors: Mochizuki Dai , Ishimoto Keita , Ayato Yusuke , Sugimoto Wataru
Published: February 2020

As a power storage device with performances of rapid charge/discharge, long-life and high power density, electrochemical capacitor is receiving attention. As high power density materials, there are two types of materials: (1) carbon materials such as activated carbon, reduced graphene oxide (rGO), and carbon nanotube and (2) metal oxide materials such as RuO2 and MnO2. Studies have also been conducted to improve specific capacitance by supporting metal oxide on carbon materials.1 We focus on the combination of RuO2 nanosheet which has a high pseudocapacitance, with GO which has a high ion conductivity to enhance electrochemical performance.

As combining method of carbon material and ruthenium oxide, we focused on click chemistry. Click chemistry is a method to combine different materials by reacting them with surface functional groups.2 Click chemistry between two-dimensional nanosheets has been used to form alternate layers.3 Since the alternate layered structures are obtained in the form of powder, broader electrochemical applications are expected. Moreover, since the alternate layers are irregularly stacked, improved substance diffusion is expected compared to the regular stacking of nanosheets by Langmuir-Blodgett or Layer-by-Layer methods. In the present study, thiol-ene reaction is considered most useful among click reactions. This is because thiol-ene reaction makes use of a combination of alkene group and thiol group, and since GO has C=C bonds, the reaction with GO is possible by only modification of RuO2 nanosheet with thiol group.

We tried modification of layered ruthenium oxide with thiol group. As coupling agent, we used 3-mercaptopropyltrimethoxysilane. SEM-EDX observation results after silane coupling showed no substantial change in particle shape by silane coupling. The presence of S and Si after silane coupling was confirmed from the EDX results, indicating silane coupling was in progress. Following that we tried to exfoliate layered C3SH-RuO2 and synthesize C3SH-RuO2 nanosheet colloids. Figure shows the AFM image of substrate made by immersing silicon substrate in toluene. The AFM image showed a sheet-like morphology of approximately 1 nm thickness and 400 nm width, indicating the formation of the C3SH-RuO2 nanosheet.

Alternate layered structures were synthesized by thiol-ene reaction of C3SH-RuO2 nanosheet with GO in the addition of radical initiator. SEM-EDX observation of the product shows stacking of nanosheets. The compounding of ruthenium oxide and GO was confirmed by IR, suggesting the formation of the alternate layered structure after thiol-ene reaction.

Figure 1
Controlling the Temporal Pulse Shape of the Passively Q-Switched Laser by Nonlinear Feedback Control
Authors: Thitsa Makhin , Rice Zechariah , Nve-Nsi Marcos , Xue Xiaojie
Published: February 2020

Q-switched lasers are high intensity laser pulses with extremely short durations of a few nanoseconds. The application of such laser pulses is ubiquitous [1,2]. In many dermatological procedures, intense energy pulses of Q-switched lasers are used to evaporate pigmented cells with high precision while the ultra-short pulse duration prevents damaging the surrounding healthy tissues. These lasers are also used in many industrial applications that require precision cutting, ranging from laser ablation and micromachining to the high-speed drilling of holes. However, the necessary precision of desired pulse characteristics has become increasingly demanding. Ever shrinking dimensions of micromachining call for reliable pulses with predictable properties. Currently, the difficulty of producing identical pulses of prescribed intensity, shape, and duration limits the use of Q-switched lasers.

While the authors have previously worked on actively Q-switched lasers [3], this work focuses on passive Q-switching, where saturable absorber materials function as the internal switch in the laser cavity. In this paper theoretical tools from the field of nonlinear dynamical control systems [4] are applied to design a feedback controller circuit, which can produce a Q-switched pulse with customized characteristics by varying the pump rate, which can be influenced by the pump power. The pump power is considered as the input to the system and the photon number is the output of the system. The population inversion, the saturable absorber concentration and the photon number are considered as the states of the system. First it is demonstrated that by applying nonlinear state feedback, the Q-switched laser system can be transformed into a pair of two cascaded integrators. Therefore, the desired output can be customized by applying its second derivative as the input. Cr:YSO Q-switched Cr:LiSAF laser is used as an example to demonstrate our method. Both theoretical analysis of the method and the numerical simulation results are presented.

References:

1. E. Lim, S. Alam, D. Richardson, IEEE Photon. Tech. Lett.,
23(2011).

2. S. Kolpakov et. al, IEEE Journal of Quantum Electron. 20, (2014).

3. M. Thitsa and W. S. Gray, ECS Trans. 53(4) (2013).

4. A. Isidori, C. Moog, De Luca. IEEE Conf Dec Contr.
25 (1986).

Figure 1
(Invited) Reliability Study of RF Power Amplifiers with GaN-on-SiC HEMTs
Authors: Lang Jenny , Lim Jang-Kwon , Hellen Johan , Nilsson Torbjörn M.J. , Schodt Bo , Poder Ralf , Belov Ilja , Bakowski Mietek , Leisner Peter
Published: February 2020

In total 50 RF amplifier demonstrators consisting each of a PCB board containing one GaN-on-SiC, HEMT, CHZ015A-QEG, from UMS in SMD quad-flat no-leads package (QFN) were assembled for the study. Two types of solders, one of which is lead-free, (Sn63Pb36Ag2 and SAC305) and two types of TIM materials (NanoTIM and TgonTM805) for PCB attachment to liquid cold plate were tested for thermo-mechanical reliability. Out of the total number of the demonstrators 24 were subjected to thermal stress by 2300 thermal cycles (TC) between -20°C and 80°C and remaining 26 were subjected to the electrical stress by power cycling (PC) with drain current of 100 mA at drain voltage of 45 V and cycle time of 2 min. HF characterization of all the boards was done before subjecting them to the thermal and electrical stresses. All the devices were also subjected to static electrical characterization by measuring threshold voltage and output and voltage blocking characteristics. The static electrical and HF characterization was performed again after 2300 cycles of TC stress and after 1100, 4700 and 14500 cycles of PC stress. In addition failure analysis was performed on the TC and PC stressed demonstrators by using optical microscopy and 2D X-ray microscopy.

The results of electrical and HF characterization show clearly changes and degradation in device performance as a function of the number of the PC cycles and accumulated current stress time. No significant differences between the boards equipped with different solder or TIM materials are observed which means that the observed changes in performance are due to the degradation of the HEMT devices. A reduction in value of saturation current (VDS=10 V, VGS=0.8 V) of about 5, 12 and 16 % is observed after 1100, 4700 and 14500 cycles of PC stress, respectively. There is a clear tendency of the threshold voltage shift (measured at 10 mA) towards more negative values showed by devices from different groups. The shift is by -0.1 to -0.15 V from typical value of about -2.25 V. The leakage current is less well behaved. There are devices with no significant change in leakage current but also devices which show an increase in leakage current by a factor larger than 2, as a result of the PC stress. Results of HF measurements show a decrease in S11 and S21 parameters from -10.91±0.23 to -10.0±0.21 and from 16.04±0.24 to 15.51±0.28 after PC stress (measurement conditions VDS=45 V, IDS=100 mA, power level 5 dBm, 1.3 GHz).

The support of Sweden´s innovation agency, Vinnova, and Sweden Energy Authority is acknowledged.

Figure 1
(Invited) Improved Vertical GaN Diodes with Mg Ion Implanted Junction Termination Extension
Authors: Anderson Travis J , Koehler Andrew D. , Feigelson Boris , Hobart Karl D , Kub Francis J
Published: February 2020

GaN is an ideal material for power applications due to its high breakdown field, high switching speed, and low switching losses. The ability to implant and activate dopants, particularly p-type dopants, in GaN still remains a challenge. Dopant implantation and activation is crucial for many devices since it is the most straightforward method of selective lateral doping in GaN. Devices such as the current aperture vertical electron transistor (CAVET), Schottky diodes with guard ring termination or grayscale junction termination extension, and vertical p-i-n diodes will be enhanced and enabled by the ability to selectively dope GaN without the need for etching or regrowth. We have previously reported on the first implanted p-i-n diode fabricated on a bulk GaN substrate. Here, we present improved GaN Schottky barrier diodes (SBDs) and p-i-n diodes with edge termination formed by either a field plate or junction termination extension (JTE) achieved by ion implanted and symmetric multicycle rapid thermal annealing (SMRTA). The devices with JTE exhibited substantially reduced leakage currents and improved turn-on characteristics. This is attributed to the elimination of the plasma process steps associated with the deposition and patterning of the field oxide layer required in a field plate process. The breakdown characteristics were studied by electroluminescence imaging, and is indicative of avalanche behavior. The realization of vertical GaN devices with low reverse leakage and ion implanted termination regions represents a key step for future power electronic devices.