bluuebunny/crossref_metadata_2025 huggingface dataset:
Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers
Authors: Jahnes Christopher , Huenger Eric , Kisting Scott
Published: October 2015

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density.

The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 ï¬m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.
300mm Wafer-Level Image Sensor Packaging
Authors: Matthias Thorsten , Kim Bioh , Mittendorfer Gerald , Lindner Paul , Kriman Moshe , Grinman Andrey , Feldman Alex
Published: October 2015

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor.

Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack.

In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.
Thermal Analysis for a Novel 3D Heterogenous Integrated Platform MorPack
Authors: Chen Shih-Lun , Huang Chun-Ming , Wu Chien-Ming , Yang Chih-Chyau , Chue Jin-Ju , Chen Shih-Lun , Chen Chi-Shi , Wang Jiann-Jenn , Chiueh Tzi-Dar
Published: October 2015

This paper presents a thermal analysis result for a novel 3D heterogeneous integrated platform MorPack (morphing package). The MorPack platform is stacked by heterogeneous sub-modules composed of bare dies, a substrate, connection bridges, and solder balls. Since the MorPack platform owns the tiny, heterogeneous and integrable characteristics, the fabrication structure must be high-density and laminal. Thus, the cooling ability of forced convection is restricted due to limited space. It can be only cooled by increasing conduction and radiation capabilities.

In order to improve the cooling ability of MorPack platform, we created three indications to optimize the thermal solution. First, the vertical thermal conductivity can be improved by filling up whole MorPack with mold material. This skill efficiently cools down the 0.5-W consuming chip by 10°C more than non-filled-up structure. Second, the bare die chip with highest power consumption should be put on the lowest layer of this 3D structure because the bottom layer owns the best cooling ability. It achieves cooling a 0.5-W consuming chip by 12°C more than it is put on the top layer. Third, in order to lessen more volume of MorPack, the density of laminal structure was increased by reducing 50 % height of the platform. To realize it, we removed the connection bridges and cut out the substrate to make a room space for chip placement. With result shown, 50 % height and volume of MorPack can be minimized with only a few temperature rising.
Wafer Level Package for MEMS with TSVs and Hermetic Seal
Authors: Shiraishi Akinori , Higashi Mitsutoshi , Murayama Kei , Taguchi Yuichi , Mori Kenichi
Published: October 2015

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated.

In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined.

Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages.

Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.
Low Cost, High Reliability WLCSP for Higher Pin Counts
Authors: Curtis Tony , Sivaswamy Senthil , Yazzie Ronnie , Lawhead David , Tessier Theodore G.
Published: October 2015

The proliferation of Wafer Level Chip Scale Packages (WLCSPs) in portable handheld products has occurred due to the minimalist form factor, high reliability and low cost packaging that they afford. As the demand for WLCSPs has grown exponentially in recent years, the industry has also been coping concurrently with the technical challenges associated with increasing array sizes and more demanding end user reliability requirements. Since handsets are inherently prone to being dropped, they are particularly susceptible to this type of component failure though striking a proper balance of mechanical robustness and thermal cycling performance has remained an ongoing industry goal.

Similar to other packages, WLCSPs have transitioned over the past decade from lead-based solder alloys to Lead Free (LF) solders. LF solder connections are especially susceptible to brittle fracture and can result in variations in drop test performance from one bump structure to the next. This paper will provide an overview of process and material add-on strategies that have been shown to considerably improve mechanical robustness for bump structures or bumping applications that are inherently less robust than others. Such supplemental improvements can result in passing Board Level Reliability qualification requirements which may otherwise be elusive or have limited levels of reliability reproducibility.
A Novel Approach to 3D Chip Stacking
Authors: Vandermeulen Mark , Smith Andrew , Csermak Ron
Published: October 2015

Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures.

A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market.

This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.
Packaging Related Failure Modes of Microelectronic Components
Authors: Hertl Michael
Published: October 2015

Today's electronics development is governed by two trends: miniaturization of size and increase of power, which both contribute to significantly higher operation temperatures of the components and assemblies. Additionally, with the establishment of the RoHS standards, also the assembly process takes place at temperatures which are significantly higher than some few years ago. Therefore the package needs to protect the component against higher and higher temperatures during the entire component live time, from assembly through the entire operation cycle.

The packaging design engineer disposes of a large number of parameters to optimize each packaging for its individual application. Even in the “simple” case of just a small silicon die in a small package, the specific composition of the mould compound may make the difference between an “easy-to-solder” package and one with repetitive failure issues during soldering and/or product operation. It is immediately clear that the situation is even much more complicated in case of highly evolved MEMS components. Modern type cavity based sensor packages need to be designed for minimum component warpage during the entire product live time, a task which is particularly challenging for the 260 °C top temperature the component may face during assembly.

In the present paper we will apply our TDM (Topography and Deformation Measurement) system to monitor the warpage behavior of various components during temperature cycles which are either typical for the solder process, or for the components operation conditions. Simultaneously with heating or cooling the components, high resolution ( μm range) topographies will be obtained on the components packaging. These topography and deformation maps will be used to analyze potential packaging related failure modes. An example will be presented how to optimize a MEMS packaging process only by carefully adjusting the assembly conditions, without any variation of the packaging materials or design.
Aerosol Jet Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications
Authors: O'Reilly Michael , Renn Michael J. , Barnes Stephen
Published: October 2015

Optomec's Aerosol Jet print platform provides an evolutionary alternative to both wire bond and TSV technology, providing high density 3-dimensional interconnect capabilities which enable multi-functional integrated circuits to be stacked and vertically interconnected in high performance System-in-Package (SiP) solutions. The die stacks can include 8 or more die, with a total stack height of ~ 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Closely coupled pneumatic atomizers with multiplexed print nozzles are used to achieve production throughput of greater than 15,000 interconnects per hour. The Aerosol Jet deposits silver nanoparticle ink connections on staggered multi-chip die stacks. High aspect ratio interconnects with <30-micron line width and 6-micron line heights have been demonstrated at sub 60-micron pitches with resistivity <1x10−7 ohm*m. Pre-production yields exceeding 80% have been consistently realized. This paper will be further expanded to include pre-production qualification results, final production packaging, and further definition of the Aerosol Jet print platform integrated within a high throughput, manufacturing ready automation solution.
Fundamentals of a MEMS Rate Integrating Gyroscope that Exploits Wave Inertia
Authors: Gallacher Barry J.
Published: October 2015

Most micromachined vibratory gyroscopes may be classified as “rate” gyroscopes where it is angular rate that is measured. Measurement of angle from a
Towards a Parametrically Pumped Xylophone Bar Magnetometer
Authors: Grigg Harry T.D.
Published: October 2015

Xylophone Bar Magnetometers (“XBMs”) have considerable potential as a class of MEMS sensor, having desirable scale-invariance properties and being suited to fabrication via surface micromachining, as well as achieving high Q factors when carefully designed. Parametric amplification is a control technique which has attracted some attention in the sensor literature, being capable of augmenting resonator Q factors by two or more orders of magnitude. This work presents ongoing research aimed at developing a parametrically amplified XBM in a microscale integrated package.

The operating principles of an XBM and parametric amplification are briefly reviewed, and an analytical model is developed for a prototype device under parametric amplification and electrostatic actuation, based on the method of multiple scales and local nonlinear theory. The predicted behaviour and regions of instability are compared to numerical results obtained via FEA and numerical solution of the nonlinear differential equation. Control of the device is then considered, and the analytical results are used to propose a sense/control scheme.

The Q factor emerges from the analysis as the dominant design factor limiting the sensitivity of the device: on this basis, the prototype design is optimised for maximum Q, treating such sources of dissipation as gas damping, TMD, EMD, and support losses. It is shown that under certain reasonable assumptions, support loss dominates the Q factor. A novel expression for the support loss in an XBM is developed, which is shown to impose a tuning condition on the geometric design of the resonator. A lower-bound estimate for the device Q is thus obtained and compared with simulation and experimental results, leading to an estimated sensitivity on the order of nanoTesla – sufficient for inertial grade application.
TSV Resist and Residue Removal
Authors: Mauer Laura , Taddei John , Youssef Ramey , Pollard Kimberly , Rector Allison
Published: October 2015

3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are numerous technical papers and presentations on the etching and filling of these vias, however the process for cleaning is seldom mentioned. Historically, after reactive ion etching (RIE), cleaning is accomplished using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution-based post etch residue remover. However, in the case of TSV formation, deep reactive ion etching (DRIE) is used to create the vias. A byproduct of this etching process is the formation of a fluorinated passivation layer, often referred to as a fluoropolymer. The fluoropolymer is not easily removed using traditional post etch residue removers, thus creating the opportunity for new and improved formulations and processes for its removal. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using Dynastrip™ AP7880™-C, coupled with a megasonic final rinse provides clean results for high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.
Miniature MEMS Interface Circuits Using Nanoparticle Conductors and Embedded Components
Authors: Christensen C. Paul
Published: October 2015

MEMS devices are typically used in subsystems comprising the MEMS component and the infrastructure required to support it. This infrastructure – signal processing, communication interface, power supply, and system packaging – often determines the size and cost of the subsystem. This paper describes a new approach to fabrication of highly miniaturized electronic circuitry and packaging that is well-suited to interfacing and support of MEMS components.

The fabrication process utilizes nanoparticle silver conductors to connect miniature embedded surface-mount components. Interconnect conductors are produced by filling laser-ablated channels with nanoparticle silver pastes that cure at low temperatures. This laser-based approach allows production of very fine line interconnect structures (< 10 micron trace widths), which simplifies conductor routing and reduces layer count. Avoiding subtractive copper processes significantly reduces capital equipment and facilities costs and minimizes waste streams.

After interconnection, the component assembly is encapsulated in a thermally conductive epoxy to produce a robust, stackable electronic module. Techniques also have been developed for stacking and interconnection of these circuit modules to form 3D electronic systems of nearly arbitrary form factor. All fabrication processes are CAD/CAM controlled, providing fast adaptability to design change and a smooth transition to production in both small and large volumes.

The new fabrication technology has been applied to the challenge of miniaturization of wireless sensor nodes with the goal of constructing complete nodes of sugar-cube size (including an advanced battery). Node form factor can be easily adapted to specific applications.
Effects of Under-Fill Curing on Substrate Warpage
Authors: Hubbard Robert L.
Published: October 2015

The formulation of flip-chip under-fill adhesives has become more critical to avoid stress-induced cracking at the solder ball interfaces farthest from the center of the die (neutral point) and of the low-k dielectric layers on the die surface. Single die packages, multiple die packages, and thin core-less substrates have now become so warped as to make the ball attach and board attach processes difficult. Recommended under-fill supplier cure profiles are generally accepted without much modification.

This work compares the stress-induced substrate warpage developed in flip-chip assemblies using seven different under-fills from three different suppliers. Both low and high Tg materials from each supplier are included. Standard isothermal convection oven cures and variable frequency microwave (VFM) cures were compared with programmed multi-step cure profiles to determine the optimum conditions for lowest die stress and substrate warpage.

Due to the complex nature of modern under-fill mixtures and the significant differences in the heating mechanisms, the thermo-mechanical properties of the cured resins are not easily interpreted with respect to cause and effect, however some of the results are surprising. The differences in warpage between “full cure” and “cure to Tg” profiles for both heating methods are demonstrated and discussed with respect to potential adhesive network structures from model studies and actual thermal data. Recommendations are made for dispense temperatures, ramp rates, soak temperatures, and extended curing. These effects are important when assemblies face additional heat processing such as subsequent solder reflow.
Z-Axis Interconnection in Organic Packaging
Authors: Egitto Frank , Antesberger T. , Das R. , Markovich V. , Rosser S. , Schadt M. , Wilson W.
Published: October 2015

Greater I/O density at the die level, more demanding performance requirements, and the continued desire to package more function into smaller devices is driving the need for improved wiring density and a concomitant reduction in feature sizes for electronic packages. Traditionally, greater wiring densities have been achieved by reducing the dimensions of vias, lines, and spaces, while also increasing the number of wiring layers. However, each of these methods possesses inherent limitations in today's most challenging multi-chip module (MCM) and system-in-package (SiP) applications that also demand reduction in size, weight and power (SWaP). These applications are forcing new methods to be developed for achieving greater wiring densities while also meeting the cost for performance challenges that exist within this industry. One method of extending wiring density beyond the limits imposed by today's traditional approaches is the strategy of making metal-to-metal z-axis interconnection of subcomposites during lamination to form a composite structure. Conductive joints can be formed during lamination using an electrically conductive paste. As a result, one is able to fabricate structures with vertically-terminated vias of arbitrary depth. Replacement of conventional plated through holes with vertically-terminated vias opens up additional wiring channels on layers above and below the terminated vias, enables die shrink, and eliminates via stubs which cause reflective signal loss. In addition, parallel lamination of individually testable subcomposites offers opportunity for yield improvement, shorter cycle times, and ease of incorporating embedded features conducive to SiP applications. This technique has also been shown to be viable across a multitude of dielectric material sets (including Teflon, PPE, LCP and Epoxies) as well as various conductive joining materials allowing it to be utilized in various applications as well as giving designers the flexibility to mix materials within the same package to incorporate various functionality.
Laser Processing of 2-D and 3-D Structures for Tunable Embedded Capacitors
Authors: Das Rabindra N. , Antesberger Timothy E. , Marconi Francesco , Egitto Frank D. , Poliks Mark D. , Markovich Voya R.
Published: October 2015

Material formulation, structuring, and modification are key to increasing the unit volume complexity and density of next generation electronic packaging products. Laser processing is finding an increasing number of applications in the fabrication of these advanced microelectronic devices. This is due, in part, to the ability to achieve highly localized treatment of materials with a spatial resolution of tens of microns. In addition, the process is data-driven, that is, patterns can be generated without the need for masking materials. In the present investigation, a variety of structures have been generated in polymer nanocomposites, nanoparticle films, and sol-gel thin films using a computer-controlled laser system. Specifically, micromachining technology has been used to produce both variable-thickness and discrete capacitors from a single sheet (layer) of capacitor material, such that both types of structures can be integrated into the same layer. In addition, the laser micromachining technology has been extended to design and develop new vertical multilayer embedded capacitors for high speed applications. High speed packages require thick dielectrics. Calculations show that multilayer vertical capacitors can be better than thick capacitors formed from a single layer. In general, multilayer embedded capacitors are fabricated by repeated lamination of resin-coated copper, or pre-preg with a capacitor core. This is a time consuming, lengthy process. As an alternative, we have deposited a single, thick capacitance layer, and subsequent laser micromachining has been used to form multiple parallel channels of a controlled depth. Metal deposition in the channels results in a multilayer embedded capacitor structure. Lasers micromaching can also provide various complex patterns such as 3-D spiral channels within a dielectric or magnetically active nanocomposite, subsequently filled with conducting materials to form inductors. This technique can be used to prepare inductors and capacitors in the same layer of nanocomposite material. Hence, the technique can be used to generate multi-functional structures for tunable device applications.
RF System in Packages (SiP) using Integrated Passive Devices
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Kim Gwang , Ahn Billy
Published: October 2015

Passive components are indispensible parts used in System in Packages (SiP) for various functions, such as decoupling, biasing, resonating, filtering, matching, transforming, etc. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. As high integration and high performance have become a trend in the packaging solutions, integrated passive device (IPD) technology shows some unique features, which helps to achieve these goals, especially for RF packages. In the IPD process, low-loss substrate material is used, and therefore high-Q inductors can be built. In addition, thin-film IPD process has finer pitch feature and better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may yield very repeatable electrical performance, and provide packages of high integration.

Several cases of study will be presented and here are some highlights of them. In case one, a most straightforward SiP approach is presented using QFN package, where several dies (including IPD dies) are implemented side-by-side. This approach may give fast developing cycle times. But importantly, wire-bonding models have big impact on performance from RF packaging, and should be obtained accurately for designs. Another case of study is a stack-die package, where inter-die coupling/cross talk could be a big issue as far as electrical performance is concerned. Placement of some critical parts, such as coils in IPD and in VCO, should be investigated very carefully in design phases. This leads to a concept of ‘IC/IPD/package’ co-design. Finally, a hybrid SiP package solution, where an IPD die is embedded in a mold compound along side with a RF power amplifier die, is presented. This approach (so called ‘eWLB’ packaging), results in the shortest interconnection between dies to dies and dies to balls. With the benefit from both the IPD process and the eWLB process (where low-loss mold materials are used), this approach may lead to high electrical performance and small form-factor at the same time.
2.5D and 3D Packaging Enables Effective Multi-Chip Packaging
Authors: Marcoux Phil
Published: October 2015

3D and 2.5D packaging has been heralded as a set of the best package architectures to satisfy shrinking time to market windows while offering an effective way to combine the ever increasing set of circuits needed for today's popular products. There is significant confusion as to the design guidelines and the economics involved to create a 3D (stacked) or a 2.5D (stacked on interposer) package. The numbers vary widely depending on the sources and the designs utilized.

This paper will examine the relative cost, design, and performance trade-offs from actual production practice. Comparisons of designs using different via types, various substrate options and BEOL vs. FEOL RDL trace layers. It will show the economics of using 3D and 2.5D for a number of the more common applications in cell phones, tablets and other products.
Studies and Applications of Advanced Laser Scribing for High Brightness LEDs
Authors: Chyr Irving , Peng Cheng , Wang Ji , Halderman Jonathan
Published: October 2015

The optical and electrical properties of LEDs scribed using both traditional and advanced laser scribing were investigated. Variations in scribe line texture and depth were examined and monitored for both laser types using both optical and electron microscopy. Simulation was conducted and verified by the experimental results on laser scribing depth versus LED light output. The metrology techniques also correlated the sidewall roughness with light output of LED between traditional and advanced laser scribing. Improvements by the advanced laser scribing were demonstrated for different LED designs, such as DBR with metal mirrors. Our study showed that the advanced laser scribing is comparable to the sidewall etching process which is the current industrial standard. Our advanced laser scribing system can process different types of metal mirrors on top of DBR structures in a single tool solution. We also presented our latest results on the emerging new substrates of vertical LEDs on Si and other advanced non-sapphire substrates.
3D & System-in-Package Development with the Redistributed Chip Package (RCP)
Authors: Gong Zhiwei (Tony) , Hayes Scott , Chhabra Navjot , Duong Trung , Mitchell Doug , Wright Jason , Vincent Michael
Published: October 2015

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology.

Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.
Thin Film Packaging for Vacuum MEMS Encapsulation: A Study on Outgassing Phenomenon
Authors: Saint-Patrice D. , Pornin J. L. , Savornin B. , Rodriguez G. , Danthon S. , Charvet P. L. , Nicolas P. , Nicolas S. , Fanget S.
Published: October 2015

Most of the time, MEMS devices require hermetic encapsulation for protection against atmosphere, moisture, particles and standard back-end manufacturing technologies. In the last few years, Wafer Level Packaging (WLP) is moving toward developments on Thin Film Packaging (TFP) in order to save footprint, to reduce chip thickness and packaging costs. In the specific case of high-vacuum MEMS encapsulation (gyro, compass), long term pressure stability is required. As the final performances of these kinds of devices are strongly dependent on the working pressure, using TFP for MEMS encapsulation with controlled vacuum becomes more challenging due to very small cavity volumes. It is then necessary to understand the outgassing phenomenon that take place during TFP encapsulation in order to reduce it.

In this paper, our latest developments on thin film packaging technology are presented. Outgassing from materials used in TFP and MEMS devices become key parameters to decrease the pressure inside the package and to improve the reliability.

In a first part, pressure and Residual Gas Analysis (RGA) of typical TFP and typical MEMS materials are measured under different time / temperature baking processes. Measurements show that material outgassing mainly comes from H2 and maximum pick appears in the beginning of the thermal process. Thanks to these characterizations, an optimized outgassing baking process in term of time and thermal budget is presented. By minimizing the internal outgassing, materials deposited by PVD sputtering can now be implemented as sealing materials for low pressure MEMS devices.

In a second part, specific low temperature Al based materials which has been developed on equipment fully compatible with front-end fab is presented. Multi-layer materials like Ti / Al based materials are compared to our single Al based material to decrease the microstructure size and to improve the sealing performances. Scanning Electronic Microscopy (SEM) and Focused Ion Beam (FIB) cross section characterizations confirm that the grain sizes are highly impacted by sputtering process parameters and a compromise has to be done with MEMS outgassing.

Finally, the most suitable outgassing baking process for the inside cavity materials and various Al-based sealing materials and stacks are performed for a MEMS compass device on 200 mm wafers. Pressure inside the cavity less than 10 mbar is obtained and the TFP yield is presented on each process conditions.

These results are very promising and showed the capabilities of TFP for vacuum MEMS encapsulation applications despite very small volume cavity. Development of such technology is still under way in order to reach high vacuum level in the range of 10-1 to 10-3 mbar.
Reduced Temperature Metal Based Bonding Processes for Wafer Level Packaging and 3D Integration
Authors: Pabo Eric F. , Dragoi Viorel , Tang Tian , Matthias Thorsten
Published: October 2015

Metal based bonding processes are commonly selected because of the need for a conductive interface along with a high degree of hermeticity. Metal based bonding process can be based on solid diffusion which is commonly called thermo-compression or can be based on liquefying part or all of the metal in the bond interface. Thermo-compression bonding has the primary challenges of being slow because it is based on solid diffusion and has very poor step coverage. The most common liquid metal bonding processes are commonly called solder or eutectic bonding. The solder or eutectic bonding process allows some step coverage and the time required for the process is driven by the maximum temperature required, the residence time at this temperature and the maximum ramp rate. The process temperature and the required process time can be reduced by selecting an alloy with a low melting point; however this reduced melting point reduces the maximum post bond working temperature. TLP (Transient Liquid Phase) also known as SLID (Solid Liquid Inter Diffusion) bonding decouples the bonding temperature from the post bond maximum working temperature which allows the selection of alloys that reduce the bonding temperature while maintaining a high post bond maximum working temperature. For example a Cu-Sn TLP process can be performed at 280°C that will survive post bond temperature of up to 415°C. The fundamentals of TLP bonding will be reviewed and data will be presented for Cu-Sn TLP bonding
In-Coated Carbon Nanotubes for Flexible Interconnects
Authors: Xu Pingye , Hamilton Michael C.
Published: October 2015

This work explores a method to construct metal-coated carbon nanotube (CNT) structures, which are potential candidates for interconnects, transmission lines and contact structures. This simple method is suitable to many applications including flexible substrates.

In this work, electroplating is used to coat a carbon nanotube surface with Indium. CNT films are prepared using drop casting method on different substrates: Ni coated silicon wafer, copy paper and photo paper. The CNT dispersion used for this work is prepared using sonication and centrifugation with a surfactant. The resulting dispersion has 0.8 wt. % of multi-walled CNTs and 0.5 wt. % of sodium dodecyl sulfate (SDS) in DI water. This dispersion is modified to reduce resistivity by adding either silver nanoparticle powder or silver ink. Electroplating is done at room temperature with a current density of 0.02 A/cm2.

This work addresses two issues about electroplating on CNT: low electrical conductivity of CNT film and low CNT adhesion to substrate. A CNT film on a Ni surface displays poor adhesion; the film peels off easily during ultrasonication and electroplating. After thermal annealing or microwave treatment, adhesion between the CNT film and Ni is greatly enhanced such that no CNT film peel-off is observed during electroplating. A CNT film on paper has a high sheet resistance. As a result, Indium is only plated on the CNT film near the attached electrode. To reduce the film sheet resistance, the CNT solution is modified by adding silver nanoparticle powder or silver ink. Ethanol rinsing is also performed on the CNT film surface to wash away surfactant and further reduce sheet resistance.

On-going work involves ink-jet printing of CNT solutions onto flexible substrates. Indium, as an example metallization, will be plated on these ink-jet printing defined transmission lines and interconnects patterns. Performance of these structures will be presented.
Low Temperature Curing - Aqueous Base Developable Photoimageable Dielectric for WLP (Wafer Level Packaging)
Authors: Huenger Eric , Lachowski Joe , Prokopowicz Greg , Thibault Ray , Gallagher Michael , Kisting Scott , Mills Lynne , Kondoh Masaki
Published: October 2015

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.
Flexible Electronics Fabrication for Missile Wiring Interconnects
Authors: Whitley Michael R. , Hudson Tracy D.
Published: October 2015

The increased usage of unmanned aerial vehicles has driven the desire for smaller and lighter missile bodies. The wiring harnesses required to connect the missile subsystems constitute a significant portion of the missile weight and cost. We have been exploring the development of flexible electronics substrates manufactured using ink jet technology on polyimide films. This technology has an advantage over traditional flex circuit manufacturing because in addition to creating traditional wiring patterns the ink jet technology enables the creation of passive components such as resistors and capacitors. The Dimatix DMP-2831 ink jet system uses individually controllable piezoelectric driven MEMS nozzles to precisely deposit nanoparticle inks. These inks are then annealed to form wiring patterns. We will present the process for converting traditional printed circuit board data formats to inkjet printable data, the process for depositing the ink, annealing and testing.
Predicting the Reliability of Zero-Level TSVs
Authors: Caswell Greg , Hillman Craig
Published: October 2015

Through Silicon Vias (TSV) are the next generation technology for system in package devices and are similar to plated through holes in a PCB from a reliability behavior perspective. The promised advantages include thinner packages and a greater level of integration between active die. The process is still being optimized and costs must be reduced for widespread adoption. TSV is rarely justified by just miniaturization alone as it is more cost-effective to thin, stack and wire bond. Cost can be 2X–4X price of flip chip ($200/wafer is the goal) and 5X–10X the price of wire bonding. TSV will be justified by performance, specifically an increase in inter-die I/O, increase in bandwidth, and a corresponding decrease in interconnect length. This paper will present two different approaches to the generation of TSVs as the vias can be created at various stages of the process: By the wafer provider, IC manufacturer, or packaging house. The paper will also address the techniques for creating the TSVs e.g. etching and lasering with respect to their differences and results as well as provide insight into the various approaches for filling the vias. A comparison between solid fill, polymer fill and no fill concepts will be made. Finally, the paper will address the three primary failure mechanisms for TSVs, that of, cracking of the copper plating, cracking of the silicon/change in resistance of silicon and interfacial delamination of the via wall from the silicon. The paper will conclude with a focus on the challenges for this technology as the exact process and architecture (materials, design) for TSV has yet to be finalized which in turn can lead to large changes in stress states.
Temperature Cycling Induced Warpage of Packages with Embedded Copper Heatspreaders
Authors: Stahley Matthew , Osenbach John , Gogue Brenda , Heo Byong Il , Lee Byung Cheol , Meng Dongmei
Published: October 2015

Temperature cycling is an important reliability qualification test given the differences in thermal expansion coefficients for the materials in integrated circuit packages. In this work, leadfree Plastic-Ball-Grid-Array (PBGA) packages with embedded C1100 copper heatspreaders were exposed to standard qualification testing including MSL3 Moisture Preconditioning with leadfree reflows at 245C followed by Temperature Cycling (TC) with ranges of −55/+125C (TC-B) and 0/+125C (TC-K) per JEDEC JESD47. Electrical performance and package warpage were characterized on as-received, post-preconditioning, and post-TC devices.

After 200 cycles TC-B, gross electrical open failures were found on a large percentage of devices in some package lots. Physical failure analysis of the open failures revealed severe package warpage, as high as 20mils on a 31mm package. The severe warpage was accompanied by delamination and sheared wires. In contrast other package lots did not show failures nor severe warpage (<6mils) even after 1000 cycles of TC-B. The same package and BOM was qualified with 225C reflows for eutectic lead/tin solder with no warpage or failures after TC.

Detailed commonality studies revealed that the copper heatspreader lot used was the only definitive difference between “good” and “warped” package lots. It was found that for “warped” lots exposure to the leadfree reflow at 245C caused a significant reduction in the micro-hardness of the copper heatspreader, while there was minimal change in micro-hardness after exposure to leadfree reflow in the “good” lots.

The mechanism for this change is explained by the softening temperature of the C1100 copper heatspreader which is well within the range of leadfree reflows. Above this softening temperature, re-crystallization and grain growth occur, which result in susceptibility to permanent warpage induced by temperature cycling. Control of this warpage is critical to qualifying temperature cycling performance for heatspreader PBGA packages, and this can be achieved through micro-hardness screening of the heatspreaders.
Low Temperature Direct Aluminum Soldering Paste
Authors: Avery William F.
Published: October 2015

For economic and weight considerations using aluminum to make connections to copper has been important in electronic components and making these connections via soldering provides an excellent thermal and electrical pathway. Soldering aluminum to copper in many applications involves the use of low temperature solder bonding to prevent damage to heat sensitive parts such as sealed copper heat pipes and sensitive electronic components. Typically, aluminum soldering is accomplished by plating over the aluminum to make that surface solderable, which is an expensive extra step in this processing. The development of a low temperature direct aluminum soldering paste eliminates the costly plating operation needed to make certain aluminum alloys solderable.

The low temperature direct aluminum soldering paste, performing below 200 °C, provides for a soldering option that will work via induction, oven reflow, hot plate, or soldering iron techniques. The paste consists of a special flux medium and a proprietary low temperature lead-free solder alloy. Evaluation of the solderpaste was by several methods. Solderability testing compared the paste on a variety of aluminum alloys. Soldering joint cross-sectioning followed by scanning electron analysis proves the viability of the solder joints. Tensile strength testing of the solder joints measured the strength of the copper to aluminum and aluminum to aluminum solder joints.
Laser Processing and Integration for Si Interposers and 3D Packaging Applications
Authors: Knowles Matthew , Hooper Andy , Pettigrew Kip
Published: October 2015

Presented here are laser processes for drilling debris-free and recast-free vias in silicon that are then integrated into downstream process. The process strategy consists of an integrated laser via drill system combined with an isotropic etch. By careful selection of both the laser and etch process parameters it is possible to control the via depth, diameter, sidewall slope/taper, and to eliminate the damaged Si material in the laser heat affected zone. Because the etch process is selective to Si, this is a mask-free and cost-effective process. Two different processes are demonstrated. For Part 1 we demonstrate an integrated process flow for TSVs with diameters in the range of 250 um for <500 um thick Si wafers and a dry etch process. For Part 2 we demonstrate with a wet etch process