Design and Implementation of an Ethernet MAC IP Core for Embedded Applications
Authors: Naik Dessai Sanket Suresh 
Published: April 2019

<!--[if gte mso 9]><xml> <o:OfficeDocumentSettings> <o:RelyOnVML /> <o:AllowPNG /> </o:OfficeDocumentSettings> </xml><![endif]--> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications.<span style="mso-spacerun: yes;"> </span></span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt; mso-bidi-font-size: 10.0pt; color: black; mso-bidi-font-weight: bold; mso-no-proof: yes;"><span style="mso-spacerun: yes;"> </span>In this paper a</span><span style="font-size: 9.0pt;"> project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.</span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. </span></p> <!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables /> <w:SnapToGridInCell /> <w:WrapTextWithPunct /> <w:UseAsianBreakRules /> <w:UseFELayout /> </w:Compatibility> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style>

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