bluuebunny/crossref_metadata_2025 huggingface dataset:
Interview with Gabrielle Weinman at Team One
Authors: Lee Newton , Weinman Gabrielle
Published: August 2008

Gabrielle Weinman is the Creative Director of Interactive & Relationship Marketing for Team One in Los Angeles. She oversees all aspects of the creative work in both departments, integrating it with traditional advertising. Her biggest client is Lexus automobiles, and other clients have included Ritz Carlton Hotels, Flexjet, MTV, Air New Zealand, Infonet and Heal the Bay. Since technology constantly evolves and changes, her background in design, branding and traditional advertising gives her a distinct advantage. After working at Keith Bright & Associates and Hill Holiday, Gabrielle started as a Senior Art Director at Team One in 1992. In 1995, she agreed to spearhead the development of an interactive group at the strong protest of her headhunter who said she would never work in advertising again. Twelve years later, Gabrielle currently manages a staff of over 25 employees and a department that has won numerous awards including Cannes Cyber Lions, Clios and One Show pencils. In the video interview, you will hear Gabrielle's answers to the following questions:

1. What is the project that you are working on at the AFI Digital Content Lab?

2. What is the greatest innovation that you have brought to the project?

3. What is your experience working with the AFI Digital Content Lab?

4. What suggestions do you have that would make the Digital Content Lab more innovative, useful, and rewarding?

5. What do you think about the future of new media?

6. What are the major challenges in Interactive TV?

7. What are some of the Interactive TV projects that you are working on?

8. Do you find it difficult to design good user interface for Interactive TV?

9. How do you see the future of Interactive TV?

10. If you can do whatever you want, what would you do?
A goal-oriented development tool to automate the incorporation of intelligent agents into interactive digital media applications
Authors: Yu Han , Shen Zhiqi , Miao Chunyan
Published: August 2008

Recent developments in games and interactive storytelling applications have seen artificially intelligent computer controlled characters being included extensively. Non-human controlled characters are starting to play an increasingly significant role in enhancing the perceived intelligence of games. Although many of them employed certain cheating techniques (e.g. allocating more resources at the start to AI opponents to make them appear more aggressive), some limited learning did appear in several games (e.g. letting AI opponents remember where human users initiated attacked in previous game). In our
Virtual Singapura
research project, we incorporate software agents into our virtual world to provide more complex user interactions. With intelligent software agents being infused into interactive digital media applications, there is great potential in improving the overall user experience. However, during the process of our research, we discovered that the traditional way of adding a multi-agent system into a computer game requires a large amount of investment in time and resources and a high level of expertise in Agent Oriented Software Engineering (AOSE). Moreover, game AI is usually closely coupled with other parts of the game code which makes it hard to reuse or replace. This research proposes a multi-agent development and runtime framework which not only provides ease-of-use agent design and implementation tools but also can be easily plugged into various interactive digital media applications.
Style-learning with feature-based texture synthesis
Authors: Xie Xuexiang , Tian Feng , Seah Hock Soon
Published: August 2008

The objective of artistic style learning is to synthesize a new image from a source image with the style learnt from example images. Existing example-based texture synthesis (EBTS) techniques model style with low-level statistical properties. These methods work well with some artistic styles such as oil painting, but have difficulties in preserving image details and features for other styles, such as pencil hatching. In this article, an improved artistic style-learning algorithm with
feature-based texture synthesis
(FBTS) is introduced. Compared with existing EBTS methods, in our FBTS algorithm, image details and features are better defined with a feature field generated from the source image. Also, an improved L2 neighborhood distance metric which provides better measures of perceptual similarity is proposed. Results and comparisons are given to demonstrate the effectiveness of the FBTS algorithm with applications in the areas of stylized shading and artistic style transfer.
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
Authors: Park Chanik , Cheon Wonmoon , Kang Jeonguk , Roh Kangho , Cho Wonhee , Kim Jin-Soo
Published: August 2008

In this article, a novel FTL (flash translation layer) architecture is proposed for NAND flash-based applications such as MP3 players, DSCs (digital still cameras) and SSDs (solid-state drives). Although the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, efficient algorithms of an FTL have a significant impact on performance as well as the lifetime. After the dominant parameters that affect the performance and endurance are categorized, the design space of the FTL architecture is explored based on a diverse workload analysis. With the proposed FTL architectural framework, it is possible to decide which configuration of FTL mapping parameters yields the best performance, depending on the differing characteristics of various NAND flash-based applications.
Platform-based software design flow for heterogeneous MPSoC
Authors: Popovici Katalin , Guerin Xavier , Rousseau Frederic , Paolucci Pier Stanislao , Jerraya Ahmed Amine
Published: August 2008

Current multimedia applications demand complex heterogeneous multiprocessor architectures with specific communication infrastructure in order to achieve the required performances. Programming these architectures usually results in writing separate low-level code for the different processors (DSP, microcontroller), implying late global validation of the overall application with the hardware platform. We propose a platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources. We use a high-level environment to capture both application and architecture initial representations. An executable software stack is generated automatically for each processor from the initial model. The software generation and validation is performed gradually corresponding to different software abstraction levels. Specific software development platforms (abstract models of the architecture) are generated and used to allow debugging of the different software components with explicit hardware-software interaction. We applied this approach on a multimedia platform, involving a high performance DSP and a RISC processor, to explore communication architecture and generate an efficient executable code for a multimedia application. Based on automatic tools, the proposed flow increases productivity and preserves design quality.
Composing heterogeneous reactive systems
Authors: Benveniste Albert , Caillaud Benoît , Carloni Luca P. , Caspi Paul , Sangiovanni-Vincentelli Alberto L.
Published: August 2008

We present a compositional theory of heterogeneous reactive systems. The approach is based on the concept of tags marking the events of the signals of a system. Tags can be used for multiple purposes from indexing evolution in time (time stamping) to expressing relations among signals, like coordination (e.g., synchrony and asynchrony) and causal dependencies. The theory provides flexibility in system modeling because it can be used both as a unifying mathematical framework to relate heterogeneous models of computations and as a formal vehicle to implement complex systems by combining heterogeneous components. In particular, we introduce an algebra of tag structures to define heterogeneous parallel composition formally. Morphisms between tag structures are used to define relationships between heterogeneous models at different levels of abstraction. In particular, they can be used to represent design transformations from tightly synchronized specifications to loosely-synchronized implementations. The theory has an important application in the correct-by-construction deployment of synchronous design on distributed architectures.
Implementing fault-tolerance in real-time programs by automatic program transformations
Authors: Ayav Tolga , Fradet Pascal , Girault Alain
Published: August 2008

We present a formal approach to implement fault-tolerance in real-time embedded systems. The initial fault-intolerant system consists of a set of independent periodic tasks scheduled onto a set of fail-silent processors connected by a reliable communication network. We transform the tasks such that, assuming the availability of an additional spare processor, the system tolerates one failure at a time (transient or permanent). Failure detection is implemented using heartbeating, and failure masking using checkpointing and rollback. These techniques are described and implemented by automatic program transformations on the tasks' programs. The proposed formal approach to fault-tolerance by program transformations highlights the benefits of separation of concerns. It allows us to establish correctness properties and to compute optimal values of parameters to minimize fault-tolerance overhead. We also present an implementation of our method, to demonstrate its feasibility and its efficiency.
MTSS
Authors: Middha Bhuvan , Simpson Matthew , Barua Rajeev
Published: August 2008

Out-of-memory errors are a serious source of unreliability in most embedded systems. Applications run out of main memory because of the frequent difficulty of estimating the memory requirement before deployment, either because it depends on input data, or because certain language features prevent estimation. The typical lack of disks and virtual memory in embedded systems has a serious consequence when an out-of-memory error occurs. Without swap space, the system crashes if its memory footprint exceeds the available memory by even 1 byte. This work improves reliability for multitasking embedded systems by proposing MTSS, a multitask stack sharing technique. If a task attempts to overflow the bounds of its allocated stack space, MTSS grows its stack into the stack memory space allocated for other tasks. This technique can avoid the out-of-memory error if the extra space recovered is sufficient to complete execution. Experiments show that MTSS is able to recover an average of 54% of the stack space allocated to the overflowing task in the free space of other tasks. In addition, unlike conventional systems, MTSS detects memory overflows, allowing the possibility of remedial action or a graceful exit if the recovered space is not enough. Alternatively, MTSS can be used for decreasing the required physical memory of an embedded system by reducing the initial memory allocated to each of the tasks and recovering the deficit by sharing stack with other tasks. The overheads of MTSS are low: the runtime and energy overheads are 3.1% and 3.2%, on average. These are tolerable given that reliability is the most important concern in virtually all systems, ahead of other concerns, such as runtime and energy.
Remote specialization for efficient embedded operating systems
Authors: Bhatia Sapan , Consel Charles , Pu Calton
Published: August 2008

Prior to their deployment on an embedded system, operating systems are commonly tailored to reduce code size and improve runtime performance. Program specialization is a promising match for this process: it is predictable and modules, and it allows the reuse of previously implemented specializations. A specialization engine for embedded systems must overcome three main obstacles: (i) Reusing existing compilers for embedded systems, (ii) supporting specialization on a resource-limited system and (iii) coping with dynamic applications by supporting specialization on demand.

In this article, we describe a runtime specialization infrastructure that addresses these problems. Our solution proposes: (i) Specialization in two phases of which the former generates specialized C templates and the latter uses a dedicated compiler to generate efficient native code. (ii) A virtualization mechanism that facilitates specialization of code at a remote location. (iii) An API and supporting OS extensions that allow applications to produce, manage and dispose of specialized code.

We evaluate our work through two case studies: (i) The TCP/IP implementation of Linux and (ii) The TUX embedded web server. We report appreciable improvements in code size and performance. We also quantify the overhead of specialization and argue that a specialization server can scale to support a sizable workload.
An Analytic Framework for Modeling and Detecting Access Layer Misbehavior in Wireless Networks
Authors: Radosavac Svetlana , Moustakides George , Baras John S. , Koutsopoulos Iordanis
Published: August 2008

The widespread deployment of wireless networks and hot spots that employ the IEEE 802.11 technology has forced network designers to put emphasis on the importance of ensuring efficient and fair use of network resources. In this work we propose a novel framework for detection of intelligent adaptive adversaries in the IEEE 802.11 MAC by addressing the problem of detection of the worst-case scenario attacks. Utilizing the nature of this protocol we employ sequential detection methods for detecting greedy behavior and illustrate their performance for detection of least favorable attacks. By using robust statistics in our problem formulation, we attempt to utilize the precision given by parametric tests, while avoiding the specification of the adversarial distribution. This approach establishes the lowest performance bound of a given Intrusion Detection System (IDS) in terms of detection delay and is applicable in online detection systems where users who pay for their services want to obtain the information about the best and the worst case scenarios and performance bounds of the system. This framework is meaningful for studying misbehavior due to the fact that it does not focus on specific adversarial strategies and therefore is applicable to a wide class of adversarial strategies.
SDAP
Authors: Yang Yi , Wang Xinran , Zhu Sencun , Cao Guohong
Published: August 2008

Hop-by-hop data aggregation is a very important technique for reducing the communication overhead and energy expenditure of sensor nodes during the process of data collection in a sensor network. However, because individual sensor readings are lost in the per-hop aggregation process, compromised nodes in the network may forge false values as the aggregation results of other nodes, tricking the base station into accepting spurious aggregation results. Here a fundamental challenge is how can the base station obtain a good approximation of the fusion result when a fraction of sensor nodes are compromised?

To answer this challenge, we propose SDAP, a Secure Hop-by-hop Data Aggregation Protocol for sensor networks. SDAP is a general-purpose secure data aggregation protocol applicable to multiple aggregation functions. The design of SDAP is based on the principles of
divide-and-conquer
and
commit-and-attest
. First, SDAP uses a novel probabilistic grouping technique to dynamically partition the nodes in a tree topology into multiple logical groups (subtrees) of similar sizes. A commitment-based hop-by-hop aggregation is performed in each group to generate a group aggregate. The base station then identifies the suspicious groups based on the set of group aggregates. Finally, each group under suspect participates in an attestation process to prove the correctness of its group aggregate. The aggregate by the base station is calculated over all the group aggregates that are either normal or have passed the attestation procedure. Extensive analysis and simulations show that SDAP can achieve the level of efficiency close to an ordinary hop-by-hop aggregation protocol while providing high assurance on the trustworthiness of the aggregation result. Last, prototype implementation on top of TinyOS shows that our scheme is practical on current generation sensor nodes such as Mica2 motes.
Attack-Resistant Location Estimation in Wireless Sensor Networks
Authors: Liu Donggang , Ning Peng , Liu An , Wang Cliff , Du Wenliang Kevin
Published: August 2008

Many sensor network applications require sensors' locations to function correctly. Despite the recent advances, location discovery for sensor networks in
hostile environments
has been mostly overlooked. Most of the existing localization protocols for sensor networks are vulnerable in hostile environments. The security of location discovery can certainly be enhanced by authentication. However, the possible node compromises and the fact that location determination uses certain physical features (e.g., received signal strength) of radio signals make authentication not as effective as in traditional security applications. This article presents two methods to tolerate malicious attacks against range-based location discovery in sensor networks. The first method filters out malicious beacon signals on the basis of the “consistency” among multiple beacon signals, while the second method tolerates malicious beacon signals by adopting an iteratively refined voting scheme. Both methods can survive malicious attacks even if the attacks bypass authentication, provided that the benign beacon signals constitute the majority of the beacon signals. This article also presents the implementation and experimental evaluation (through both field experiments and simulation) of all the secure and resilient location estimation schemes that can be used on the current generation of sensor platforms (e.g., MICA series of motes), including the techniques proposed in this article, in a network of MICAz motes. The experimental results demonstrate the effectiveness of the proposed methods, and also give the secure and resilient location estimation scheme most suitable for the current generation of sensor networks.
Advances in information and knowledge management
Authors: Varde Aparna , Pei Jian
Published: August 2008

Several research areas today overlap between the tracks of databases, information retrieval and knowledge management, such as natural language processing, semantic web, digital libraries, visualization, information quality and data mining. Inter-disciplinary research across these tracks encourages advances in the development of databases, the extraction of information and the discovery of knowledge. This is precisely the focus of our article. We explain the research issues addressed in a Ph.D. workshop recently held at the ACM Conference on Information and Knowledge Management. This workshop had presentations on novel ideas addressing challenges in information and knowledge management. It covered a broad range of topics such as XML architectures, sensor data streams, personal information managers and text pre-processing. In this article, we provide an overview of the research problems and solutions discussed in the Ph.D. workshop. Our article thus describes the latest technological developments in information and knowledge management as seen by academia. This cutting edge technology also finds practical applications in the corporate world.
Report on the 9th International Workshop on Web Information and Data Management (WIDM 2007)
Authors: Fundulaki Irini , Polyzotis Neoklis
Published: August 2008

The 9th
ACM International Workshop on Web Information and Data Management (WIDM 2007
) was held in Lisbon, Portugal, in conjunction with the 16
th
International Conference on Information and Knowledge Management (CIKM), on November 9, 2007.
AIR 2006
Authors: Joho Hideo , Urban Jana , Villa Robert , Jose Joemon M. , van Rijsbergen C. J.
Published: August 2008

Adaptive Information Retrieval (IR) systems are designed to optimize retrieval effectiveness and user interaction in an underlying search environment. In this article, we report on a workshop held at Glasgow, UK, in October 2006. The workshop program consisted of three invited talks, four provocative presentations, and a panel discussion. In addition, 15 poster presentations enriched the workshop themes. Important pointers to further development of adaptive IR systems and their evaluation were suggested.
Information retrieval facility symposium in Vienna
Authors: Tait John
Published: August 2008

On November 8-9, 2007 the new Information Retrieval Facility (www.ir-facility.org) held its first annual Symposium in Vienna. The focus of the symposium was patent retrieval, and it was attended by 125 experts in Information Retrieval, Intellectual Property Management and related areas. Delegates came from Korea, Hong Kong, Singapore, Australia, Canada, the US and 10 European Countries. In terms of organisations, delegates came from Universities, Patent Offices (EPO, WIPO) and from commercial organisations ranging from majors like Shell and GlaxoSmithKline to one and two person consultancies.
The Fourth Asian Information Retrieval Symposium (AIRS 08)
Authors: Li Hang , Ma Wei-Ying , Nie Jian-Yun , Wong Kam-Fai
Published: August 2008

Asia Information Retrieval Symposium (AIRS) 2008 was held in Harbin Institute of Technology, China, in January 15--18, 2008. This was the fourth AIRS conference in the series established in 2004. The previous conferences have been held in Beijing (2004), Jeju (2005) and Singapore (2006). The AIRS conferences trace their roots to the successful Information Retrieval with Asian Languages (IRAL) workshops, which started in 1996.
Structuring and designing web information system for stroke care
Authors: Hassan Noor Hafizah , Md Nasir Mohd Hairul Nizam , Kurniawan Sri Hastuti
Published: August 2008

The rapid development of information technology is a powerful instrument for organizational problem-solving to help with establishing general information systems behavior. The choice of medium is important to insure the success of message delivery. The Internet plays an important role in providing information in a timely manner and in a way that can reach a large geographical area. Internet/web systems mean that business, government, or consumers can access the information (Walter and Scott, 2006). Nowadays, an important use of the Internet is to spread information with an emphasis on health. For more than thirty years, clinicians, health service researchers and others have been investigating the use of advanced telecommunications and information technologies to improve healthcare as mentioned by Hawkey et al. (2007). Health information includes stroke and cancer awareness to inform the public about how to detect and cope with situations related to these two diseases.
Throughput-delay tradeoff in small and sparse mobile ad hoc networks
Authors: Bhatia Swapnil , Bartoš Radim , Ma Kevin
Published: August 2008

This paper takes the first step in characterizing the throughput-delay tradeoff for small and sparse MANETs which have many practical applications. We find that as the MANET becomes sparser, throughput decreases and delay increases, as expected. If relaying is disabled then the throughput and delay depend on the size of the area of operation. While relaying does increase throughput, the single packet relaying strategy worsens the delay for small MANETs in the Grossglauser traffic model. Greedy relaying overcomes this worsening without trading throughput, but only for rapidly mixing mobility. Unlike in dense networks, local broadcasting does not provide any significant benefit. Packet repetition does decrease delay, but only at the expense of reduced throughput. Our results are useful in practical underwater MANETs which are typically small and sparse.
A synchronization-based multi-task communication mechanism for wireless sensor networks
Authors: Charfi Youssef , Wakamiya Naoki , Murata Masayuki
Published: August 2008

A lot of work has been done to design wireless sensor networks (WSNs) that are distributed, self-organized, and energy-efficient. Most of these WSNs are designed to carry out a single task such as data gathering or diffusion and are not flexible enough to perform multiple tasks while keeping their self-organized behavior. In this paper, we show how a fully dis-tributed and self-organized data gathering mechanism that rely on pulse-coupled oscillator models to achieve synchronization can be extended to offer periodic two-way communica-tion between the base station and the sensor nodes. We also demonstrate the ability of the proposed mechanism to perform multiple functions such as data gathering and retasking without any disturbance in the synchronization of the WSN.
Polymorphic On-Chip Networks
Authors: Kim Martha Mercaldi , Davis John D. , Oskin Mark , Austin Todd
Published: August 2008

As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range of traffic patterns. This indicates that there is an opportunity to gain performance by customizing the interconnect to a particular application or workload. We propose polymorphic on-chip networks to enable per-application network customization. This network can be configured prior to application runtime, to have the topology and buffering of arbitrary network designs. This paper proposes one such polymorphic network architecture. We demonstrate its modes of configurability, and evaluate the polymorphic network architecture design space, producing polymorphic fabrics that minimize the network area overhead. Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network designs.
TokenTM
Authors: Bobba Jayaram , Goyal Neelam , Hill Mark D. , Swift Michael M. , Wood David A.
Published: August 2008

Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance or concurrency. However, future programmers may wish to use large transactions more often in order to integrate with higher-level programming models (e.g., database transactions) or perform selected I/O operations. To prevent the "small transactions are common" assumption from becoming self-fulfilling, this paper contributes TokenTM—an unbounded HTM that uses the abstraction of tokens to precisely track conflicts on an unbounded number of memory blocks. TokenTM implements tokens with new mechanisms, including metastate fission/fusion and fast token release. TokenTM executes small transactions fast, executes concurrent large transactions with no penalty to nonconflicting transactions, and gracefully handles paging, context switching, and System-V-style shared memory.
Microcoded Architectures for Ion-Tap Quantum Computers
Authors: Kreger-Stickles Lucas , Oskin Mark
Published: August 2008

In this paper we present the first ever systematic design space exploration of microcoded software fault tolerant ion-trap quantum computers. This exploration reveals the critical importance of a well-tuned microcode for providing high performance and ensuring system reliability. In addition, we find that, despite recent advances in the reliability of quantum memory, the impact of errors due to stored quantum data is now, and will continue to be, a major source of systemic error. Finally, our exploration reveals a single design which out performs all others we considered in run time, fidelity and area. For completeness our design space exploration includes designs from prior work and we find a novel design that is 1/2 the size, 3 times as fast, and an order of magnitude more reliable.
Running a Quantum Circuit at the Speed of Data
Authors: Isailovic Nemanja , Whitney Mark , Patel Yatish , Kubiatowicz John
Published: August 2008

We analyze circuits for kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critical path. The result is a chip entirely dominated by ancilla generation circuits. To address this issue, we introduce optimized ancilla factories and analyze theirstructure and physical layout for ion trap technology. We introduce a new quantum computing architecture with highly concentrated data-only regions surrounded by shared ancilla factories. The results are a reduced dependence on costly teleportation, more efficient distribution of generated ancillae and more than five times speedup over previous proposals.
ReVIVaL
Authors: Liang Xiaoyao , Wei Gu-Yeon , Brooks David
Published: August 2008

Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip, and among microarchitectural blocks within one core. Hence, it will be difficult to only rely on traditional frequency binning to efficiently cover the large variations that are expected. Furthermore, multiple voltage/frequency domains introduce significant hardware overhead and alone cannot address the full extent of delay variations expected in future multi-core systems. In this paper, we present ReVIVaL, which combines two fine-grained post-fabrication tuning techniques---voltage interpolation(VI) and variable latency(VL). We show that the frequency variation between chips, between cores on one chip, and between functional units within cores can be reduced to a very small range. The effectiveness of these techniques are further verified through experiments on test chips fabricated in a 130nm CMOS process. Detailed architectural simulations of multi-core processors demonstrate significant performance and power advantages are possible by combining variable latency with voltage interpolation.
Counting Dependence Predictors
Authors: Roesner Franziska , Burger Doug , Keckler Stephen W.
Published: August 2008

Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To date, the most sophisticated dependence predictors, such as Store Sets, have been tightly coupled to the fetch and execution streams, requiring global knowledge of the in-flight stream of stores to synchronize loads with specific stores. This paper proposes a new dependence predictor design, called a Counting Dependence Predictor (CDP). The key feature of CDPs is that the prediction mechanism predicts some set of events for which a particular dynamic load should wait, which may include some number of matching stores. By waiting for local events only, this dependence predictor can work effectively in a distributed microarchitecture where centralized fetch and execution streams are infeasible or undesirable. We describe and evaluate a distributed Counting Dependence Predictor and protocol that achieves 92% of the performance of perfect memory disambiguation. It outperforms a load-wait table, similar to the Alpha 21264, by 11%. Idealized, centralized implementations of Store Sets and the Exclusive Collision Predictor, both of which would be difficult to implement in a distributed microarchitecture, achieve 97% and 94% of oracular performance, respectively.
Atom-Aid
Authors: Lucia Brandon , Devietti Joseph , Strauss Karin , Ceze Luis
Published: August 2008

Writing shared-memory parallel programs is error-prone. Among the concurrency errors that programmers often face are atomicity violations, which are especially challenging. They happen when programmers make incorrect assumptions about atomicity and fail to enclose memory accesses that should occur atomically inside the same critical section. If these accesses happen to be interleaved with conflicting accesses from different threads, the program might behave incorrectly. Recent architectural proposals arbitrarily group consecutive dynamic memory operations into atomic blocks to enforce memory ordering at a coarse grain. This provides what we call implicit atomicity, as the atomic blocks are not derived from explicit program annotations. In this paper, we make the fundamental observation that implicit atomicity probabilistically hides atomicity violations by reducing the number of interleaving opportunities between memory operations. We then propose Atom-Aid, which creates implicit atomic blocks intelligently instead of arbitrarily, dramatically reducing the probability that atomicity violations will manifest themselves. Atom-Aid is also able to report where atomicity violations might exist in the code, providing resilience and debuggability. We evaluate Atom-Aid using buggy code from applications including Apache, MySQL, and XMMS, showing that Atom-Aid virtually eliminates the manifestation of atomicity violations.
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
Authors: Lim Kevin , Ranganathan Parthasarathy , Chang Jichuan , Patel Chandrakant , Mudge Trevor , Reinhardt Steven
Published: August 2008

This paper seeks to understand and design next-generation servers for emerging "warehouse-computing" environments. We make two key contributions. First, we put together a detailed evaluation infrastructure including a new benchmark suite for warehouse-computing workloads, and detailed performance, cost, and power models, to quantitatively characterize bottlenecks. Second, we study a new solution that incorporates volume non-server-class components in novel packaging solutions, with memory sharing and flash-based disk caching. Our results show that this approach has promise, with a 2X improvement on average in performance-per-dollar for our benchmark suite.
Online Estimation of Architectural Vulnerability Factor for Soft Errors
Authors: Li Xiaodong , Adve Sarita V. , Bose Pradip , Rivers Jude A.
Published: August 2008

As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior research has shown that there is significant architecture-level masking, and many soft error solutions take advantage of this effect. Prior work has also shown thatthe degree of such masking can vary significantly across workloads and between individual workload phases, motivating dynamic adaptation of reliability solutions for optimal cost and benefit. For such adaptation, it is important to be able to accurately estimate the amount ofmasking or the architecture vulnerability factor (AVF) online, while the program is running. Unfortunately, existing solutions for estimating AVF are often based on offline simulators and hard to implement in real processors. This paper proposes a novel way of estimating AVF online, using simple modifications to the processor. The estimation method applies to both logic and storage structures on the processor. Compared to previous methodsfor estimating AVF, our method does not require any offline simulation or calibration for different workloads. We tested our method with a widely used simulator from industry, for four processor structures and for 100 to 200 intervals of each of eleven SPEC benchmarks. The results show that our method provides acceptably accurate AVF estimates at runtime. The absoluteerror rarely exceeds 0.08 across all application intervals for all structures, and the mean absolute error for a given application and structure combination is always within 0.05.
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime
Authors: Shin Jeonghee , Zyuban Victor , Bose Pradip , Pinkston Timothy M.
Published: August 2008

Microarchitectural redundancy has been proposed as a means of improving chip lifetime reliability. It is typically used in a reactive way, allowing chips to maintain operability in the presence of failures by detecting and isolating, correcting, and/or replacing components on a first-come, first-served basis only after they become faulty. In this paper, we explore an alternative, more preferred method of exploiting microarchitectural redundancy to enhance chip lifetime reliability. In our proposed approach, redundancy is used proactively to allow non-faulty microarchitecture components to be temporarily deactivated, on a rotating basis, to suspend and/or recover from certain wearout effects. This approach improves chip lifetime reliability by warding off the onset of wearout failures as opposed to reacting to them posteriorly. Applied to on-chip cache SRAM for combating NBTI-induced wearout failure, our proactive wearout recovery approach increases lifetime reliability (measured in mean-time-to-failure) of the cache by about a factor of seven relative to no use of microarchitectural redundancy and a factor of five relative to conventional reactive use of redundancy having similar area overhead.
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
Authors: Teodorescu Radu , Torrellas Josep
Published: August 2008

Within-die process variation causes individual cores in a ChipMultiprocessor (CMP) to differ substantially in both static powerconsumed and maximum frequency supported. In this environment,ignoring variation effects whenscheduling applications or when managing power withDynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This paper proposes variation-aware algorithms for applicationscheduling and power management. One such power managementalgorithm, called {\em LinOpt}, uses linear programmingto find the best voltage and frequency levels for each of thecores in the CMP --- maximizing throughput at a given power budget.In a 20-core CMP, the combination of variation-awareapplication scheduling and {\em LinOpt} increases the averagethroughput by 12--17\% and reduces the average $ED^2$ by 30--38\%--- all relative to using variation-awarescheduling together with a simple extension to Intel's Foxtonpower management algorithm.
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
Authors: Chen Shimin , Kozuch Michael , Strigkos Theodoros , Falsafi Babak , Gibbons Phillip B. , Mowry Todd C. , Ramachandran Vijaya , Ruwase Olatunji , Ryan Michael , Vlachos Evangelos
Published: August 2008

Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and security attacks and then limiting their damage (via containment and/or recovery). Unfortunately, their fine-grain nature implies very high monitoring overheads for software-only tools, which are typically based on dynamic binary instrumentation. Previous hardware proposals either focus on mechanisms that target specific bugs or address only the cost of binary instrumentation. In this paper, we propose a flexible hardware solution for accelerating a wide range of instruction-grain monitoring tools. By examining a number of diverse tools (for memory checking, security tracking, and data race detection), we identify three significant common sources of overheads and then propose three novel hardware techniques for addressing these overheads: Inheritance Tracking, Idempotent Filters, and Metadata-TLBs. Together, these constitute a general-purpose hardware acceleration framework. Experimental results show our framework reduces overheads by 2-3X over the previous state-of-the-art, while supporting the needed flexibility.
Atomic Vector Operations on Chip Multiprocessors
Authors: Kumar Sanjeev , Kim Daehyun , Smelyanskiy Mikhail , Chen Yen-Kuang , Chhugani Jatin , Hughes Christopher J. , Kim Changkyu , Lee Victor W. , Nguyen Anthony D.
Published: August 2008

The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested through vector/SIMD instructions as well as multithreading (through both multithreaded cores and chip multiprocessors). Vector parallelism can be more efficiently supported than multithreading, but is often harder for software to exploit. In particular, code with sparse data access patterns cannot easily utilize the vector/SIMD instructions of mainstream processors. Hardware to scatter and gather sparse data has previously been proposed to enable vector execution for these codes. However, on multithreaded architectures, a number of applications spend significant time on atomic operations (e.g., parallel reductions), which cannot be vectorized using previously proposed schemes. This paper proposes architectural support for atomic vector operations (referred to as GLSC) that addresses this limitation. GLSC extends scatter-gather hardware to support atomic memory operations. Our experiments show that the GLSC provides an average performance improvement on a set of important RMS kernels of 54% for 4-wide SIMD.
3D-Stacked Memory Architectures for Multi-core Processors
Authors: Loh Gabriel H.
Published: August 2008

Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examined the performance benefits of such an approach, but all of these works only consider commodity 2D DRAM organizations. In this work, we explore more aggressive 3D DRAM organizations that make better use of the additional die-to-die bandwidth provided by 3D stacking, as well as the additional transistor count. Our simulation results show that with a few simple changes to the 3D-DRAM organization, we can achieve a 1.75x speedup over previously proposed 3D-DRAM approaches on our memory-intensive multi-programmed workloads on a quad-core processor. The significant increase in memory system performance makes the L2 miss handling architecture (MHA) a new bottleneck, which we address by combining a novel data structure called the Vector Bloom Filter with dynamic MSHR capacity tuning. Our scalable L2 MHA yields an additional 17.8% performance improvement over our 3D-stacked memory architecture.
Feedback scheduling of real-time divisible loads in clusters
Authors: Luong Duc , Deogun Jitender , Goddard Steve
Published: August 2008

Quality of Service (QoS) provisioning for divisible loads in clusters can be enabled using real-time scheduling theory, but is based on an important assumption: that the scheduler knows the execution time of every task in the workload. Information from production clusters, however, shows that estimated execution times of tasks are often inaccurate. Most of the work on scheduling divisible loads on clusters is based on this information, and therefore maybe of limited use when applied in practice. In this paper, we present our ongoing work to develop an EDF (earliest deadline first) scheduling algorithm with a feedback mechanism that is able to solve this problem. The objective of the new algorithm is to provide QoS provisioning of divisible loads when estimated execution times of tasks are inaccurate.
A modular framework for iterative combinatorial auctions
Authors: Lahaie Séstien , Parkes David C.
Published: August 2008

We describe a modular elicitation framework for iterative combinatorial auctions. The framework includes proxy agents, each of which can adopt an individualized bidding language to represent partial value information of a bidder. The framework leverages algorithms from query learning to elicit value information via bids as the auction progresses. The approach reduces the multi-agent elicitation problem to isolated, single-agent learning problems, with competitive equilibrium prices used to facilitate auction clearing even without complete learning.
Can priced options solve the exposure problem in sequential auctions?
Authors: Mous Lonneke , Robu Valentin , La Poutré Han
Published: August 2008

The exposure problem appears whenever an agent with complementary valuations bids to acquire a bundle of items sold sequentially, in independent auctions. In this letter, we review a possible solution that can help solve this problem, which involves selling options for the items, instead of the items themselves. We provide a brief overview of the state of the art in this field and discuss, based on recent results presented in [Mous et. al. 2008], under which conditions using option mechanisms would be desirable for both buyers and sellers, by comparison to direct auctioning of the items. The paper concludes with a brief discussion of further research directions in this field.
Enabling internet singularity within the electronic commerce trust model
Authors: Mahmood Omer , Selvakennedy Selvadurai
Published: August 2008

Decentralization of publication is one of the great advantages of the Web's infrastructure. However, until now, Web failed to fully engage the user to contribute and add contents. This is the primary motivation for Web 2.0, which revolves around the notion that people can add contents for Collective Intelligence. Enterprises can also use Web 2.0 to reduce costs and increase profits through Social Network Analysis. Web 2.0 applications target to interconnect the users and contents so that the users can use contents to find participants and vice versa. Therefore, if the users are further assisted, to add contents to the web, link people with people, and link people with contents; then the distinction between the physical and electronic worlds will cease to exist. This web environment will enable the users to use web for Collective Intelligence and Social Network Analysis, defined here as 'Internet Singularity'. This paper proposes an application architecture based on decentralized information structure that links contents and people together. The architecture embraces FOAF, Atom, RDF, RDFS and OTER (Online Trust Evaluation RDF). OTER is constructed by using RDF Schema for linking and representing online trust evaluation information within Web 2.0. This architecture can be used as a model to develop Web 2.0 applications for any e-domain. However, it is believed that trust will be the main synthetic force in Web 2.0 as it is in the current physical environment. The proposed application architecture targets to assist the participants in committing online transactions while contributing towards Collective Intelligence.
GECCO-2007 highlights
Authors: Castellini Alexandre , Guthrie Charles , Yeten Burak , Yu Tina
Published: August 2008

The GECCO conference is the largest annual conference in the field of Genetic and Evolutionary Computation. Workshops on specific topics are organized every year. In July 2007, Chevron and Tina Yu from the University of Newfoundland organized the first workshop on Petroleum Applications. Speakers from industry and academia shared their recent work on a variety of subjects and a panel discussion addressed the gaps and opportunities for Oil and Gas companies.
GECCO-2008 new contest problem!
Authors: Armentrout Steven
Published: August 2008

In conjunction with the 2008 Genetic and Evolutionary Computation Conference (GECCO), Parabon Computation, the leading on-demand computation utility, announced today that it will sponsor a $1,000 prize competition in which contestants are challenged to evolve a program that can solve an arbitrarily scrambled Rubik's Cube. The competition is designed to demonstrate the combined capability of two complementary computing technologies provided by Parabon Computation. The Origin(tm) Evolutionary SDK (software development kit) uses computer-based evolutionary processes to derive (evolve) desired results and the Frontier Grid Platform harnesses the computational power of thousands of computers to deliver supercomputing as a service.