Enhanced Stability Under Positive Bias Temperature Stress in Oxide Thin Film Transistors with Double Gate Structure By Improving Bottom Channel Interface
Authors: Son Kyoung-Seok , Kim Myoeng-Ho , Lee Seung-Hun , Kim Youn-Goo , Kim Jaybum , Lee Sunhee 
Published: December 2024

Recently, oxide TFTs have been widely applied not only to TVs and monitors, but also to mobile products such as smartphones and smartwatches. In particular, since oxide TFTs exhibit ultra-low leakage current [1], it became an indispensable technology to reduce power consumption through low-frequency driving. On the other hand, as the resolution of display panels increase and high-speed driving of 120 Hz or more becomes the standard, the scan-on-time gradually shortens. Therefore, it is essential to increase the on-current of the oxide TFT to satisfy high-speed driving requirements in high-resolution displays. As a method of increasing the on-current, a double gate structure using both the top and bottom channels of the oxide semiconductor as shown in Figure 1 has been proposed. Although the on-current is improved, the double gate structure has a problem in that the Positive Bias Temperature Stability (PBTS) is significantly deteriorated compared to the TFT of the top single gate structure. We will discuss the causes of the reliability degradation of the double gate structure and how to improve it.

In this paper, self-aligned top gate (SA TG) device structures are considered as shown in Figure 1. After patterning the bottom metal layer (BML) to serve as a bottom gate, a buffer layer is deposited. IGZO film with conventional composition was deposited through sputtering and then gate insulator was deposited via PECVD. A self-aligned top gate structure is formed by patterning the gate electrode and then using the pattern to form an n+IGZO region. After depositing interlayer dielectric (ILD), source/drain electrodes are connected to n+ IGZO through contact holes.

Figure 2(a) and 2(b) show the change in transfer characteristics of top single and double gate IGZO TFTs as a function of PBTS duration, respectively. The devices were evaluated in air using a gate bias of Vgs = + 20 V, temperature of 70℃ for a total stress time of 8,000s. As shown in Figure 2, we can see that the Vth shift of the double gate TFT is much larger than that of the top single gate TFT. Since the double gate structure uses both the top and bottom channels of the oxide semiconductor, it is necessary to determine which side of the channel is the main cause of deterioration. Figures 2(c) and 2(d) show PBTS results when bias stress is applied only to the top gate and only to the BML using a 4-terminal TFT. Under the condition of applying a stress voltage to the top gate, excellent reliability characteristics were shown, similar to the results of the top single gate structure. However, under conditions where the stress voltage is applied only to the BML, significant shift of Vth is observed. The difference in deterioration of the top and bottom channels can be interpreted as a difference in the density of excess oxygen defects, which act as electron trap sites [2-3]. During the process of depositing the IGZO film through sputtering, many excess oxygen defects may occur at the bottom interface of the insulating film due to the ion bombardment. As the IGZO film is gradually deposited, the amount of defects accumulated at the bottom interface increases. Meanwhile, the excessive oxygen defect concentration at the top interface can be passivated by hydrogen introduced during gate insulator deposition via PECVD.

Figure 3 shows the PBTS results for the top single gate and double gate structures as a function of IGZO deposition power. As the sputtering power decreases, the amount of Vth shift for the top single gate remains nearly constant, while the amount of Vth shift for the double gate structure improves dramatically. It is presumed that the reduction in ion bombardment energy during IGZO deposition leads to decrease in excess oxygen defects accumulated at the interface between IGZO and the bottom insulating film.

In summary, reducing IGZO deposition power significantly improves PBTS reliability in double gate structures. This improvement is attributed to reduction of excess oxygen defects accumulated at the bottom channel interface, as inferred from the difference in PBTS results for the top single gate and double gate structures.

Reference

[1] K.Kato et al. Jpn.J. Appl. Phys. 51(2012) 021201

[2] S.Choi et al. IEEE Electron Device Lett., vol. 38, no. 5, pp. 580 (2017)

[3] D.H.Kim et al. J.SID, 25/2, p.98 (2017)

Figure 1