(Invited) CMOS Compatible High Performance IIIV Devices: Opportunities and Challenges
Authors: Sun Yanning , Shiu Kuen-Ting , Cheng Cheng-Wei , Majumdar Amlan , Bruce Robert , Yau Jeng-bang , Farmer Damon , Zhu Yu , Hopstaken Marinus , Frank Martin M. , Ando Takashi , Lee Ko-tao , Rozen John , Sadana Devendra K. , Narayanan Vijay , Mo Renee T. , Leobandung Effendi 
Published: February 2020

Introduction

Many IIIV materials such as InGaAs, InAs, InP, or GaAs are known for their superior transport properties and have been widely used in high speed RF devices. In last decade, there has been a renewed interested in these IIIV materials as a possible replacement of Si for CMOS application. With low electron effective mass, high electron mobility, and high ballistic velocity [1]. IIIV materials can provide better power performance tradeoff.

Self-aligned IIIV MOSFET

Most III-V devices focus on the MOS-HEMT structure [2]-[7], which is a good test vehicle for evaluating the upper limit of III-V FET performance as MOS-HEMT fabrication uses the least-damaging process conditions. MOS-HEMTs are, however, not CMOS compatible due to large overlap capacitance induced by thin high-k dielectric between the gate and RSD, which results in larger circuit delay. Furthermore, MOS-HEMTs are typically underlapped, which leads to high series resistance R
EXT, unless a d-doping layer is present, which degrades LG
scalability.

We have focused on self-aligned MOSFETs and processes that are not only manufacturable but also compatible with CMOS applications. We have  demonstrated high-performance self-aligned In0.53Ga0.47As MOSFETs with L
EFF down to 20 nm and peak G
MSAT over 2200 mS/mm at V
DD = 0.5 V. This devices are among the best In0.53Ga0.47As FETs in literature. [8-9]

IIIV on Si integration

IIIV material eventually needs to be integrated on Si substrate due to lack of pFET solution, as well as limited IIIV wafer size and cost-effective considerations. IIIV MOSFET has been demonstrated on Si substrates with direct epitaxy, wafer bonding, aspect-ratio-trapping (ART) [10], confined epitaxial lateral overgrowth (CELO) [11], etc. Each scheme has  its own challenges in terms of defect reduction and CMOS compatibility.

More than Moore

With high electron mobility, good optical properties, and variety of materials with different bandgap and properties, III-Vs are promising in many applications that “more than Moore”. Process and integration development such as gate stack, low resistance contacts, self-aligned process, scaling and especially the integration on Si substrate will tremendously benefit current III-V applications beyond Moore, as well as open up new opportunities.

Reference

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[6]   S. Datta et al., IEDM Tech. Dig., pp. 763-766, Dec. 2005.

[7]   S. Lee et al, VLSI Tech, Dig., pp 54-55, 2014

[8]   Y. Sun et al, IEDM Tech. Dig. Pp 48-51, 2013

[9]   Y. Sun et al,. IEDM Tech. Dig., pp. 582-585, 2014

[10]   N. Waldron et al. IEEE Electron Device Lett., vol. 35, pp1097-1099, 2014

[11]  L. Czornomaz et al., VLSI Tech. Dig., pp. T246-T247, Jun. 2015.