FDSOI Suitability for Asynchronous Circuits at Sub-VT
Authors: Amat Esteve , Christmann Jean-Frédéric , Billoint Olivier , Miro Ivan , Beigne Edith 
Published: February 2020

Ultra Thin Body and Box Fully Depleted Silicon-on-Insulator (UTBB FDSOI) devices are promising candidates to substitute planar CMOS technology for very large-scale integrated (VLSI) circuits, recently proved to implement complex systems [1]. Their main characteristic is the use of Buried-Oxide (BOX) by providing high channel isolation and excellent electrostatic control over the channel. Due to BOX use is feasible to combine n-/p-type backplane, by allowing different threshold voltages (VT) for the same gate stack, e.g. regular-VT (RVT) and low-VT (LVT) [2]. Their efficient use of a wide body-bias voltage (VBB) range allows a performance management [1, 2], in contrast to other device proposals [3] (i.e. FinFETs).

Due to the increasing interest on the Internet of Things, energy efficiency and sub-VT circuits are a hot topic for the research community. Minimum energy point (MEP, i.e. operating voltage where total consumed energy per operation is minimized) monitors their behavior. Sub-VT circuits’ target is medium speed applications (10-100MHz), e.g. wireless sensor networks, medical applications and mobile signal processing [1, 4]. Adders are representative of signal processing architectures, then, their implementation at sub-VT level become of high interest. Below 32nm reliability issues become relevant [4] (e.g. variability). Asynchronous circuits are considered a promising candidate to outperform these threats at sub-VTlevel [4, 5], mainly due to their delay insensitivity.

For this, we designed a dual-rail asynchronous 8 bits FA pipelined with four stages, and simulated by using 28nm FDSOI devices. We obtain the MEP regarding the highest consumption operation, from where we obtain both energy consumption and system delay. First, we compare it with its synchronous counterpart. Fig. 1 presents the delay-energy relation for both

a-/synchronous 8b FA at MEP, when VBB is shifted. While better VBB influence (i.e. larger delay reduction and lower energy increase) is observed for synchronous proposal, lower energy consumption is always shown for the asynchronous one, proving their higher feasibility at sub-VTlevel.

Hereafter, we only study the FDSOI suitability by simulating the asynchronous proposal. Then, we compare different technology options, e.g. FDSOI (LVT and RVT), 28nm Bulk CMOS and 20nm HP PTM FinFET [3]. Fig. 2 presents minor energy consumption for RVT FDSOI-based FA, although shows the largest delay, what highlight their suitability in circuits that are mainly in sleep mode. Nonetheless, Bulk CMOS depicts the worst overall performance, i.e. the highest energy consumption and large delay. Regarding LVT FDSOI and FinFET, we could determine that similar energy values are obtained for both, although FDSOI devices allow us to modify their performance thanks to VBB use. Moreover, note that FinFET models are predictive, in contrast of the “real” ones used for FDSOI. Besides, Fig. 3 depicts the delay-energy relation in function of the VBB, when the asynchronous-based FA uses different number of bits (4, 8 and 16). Larger VBB impact is observed when fewer bits are used, i.e. lower energy consumption and larger delay reduction. Afterwards, Fig. 4 depicts the VBB influence on asynchronous FA performance when environment temperature is modified. We observe wider energy range as temperature increases, contrary to the delay range trend. Moreover, we could manage the VBB to provide a temperature insensitive behavior of our system, i.e. almost constant delay (dashed line), when a proper VBB-shift is applied.

Regarding the process variation impact, after 10,000 Monte-Carlo simulations, Fig. 5 depicts that asynchronous FA with larger number of bits shows lower variability impact. Otherwise, when process variations are considered for synchronous-based FA a larger impact is observed, as they break the time constrains in contrast to its asynchronous counterparts. Then, Fig. 6 presents the large number of unexpected behavior attributed to the flip-flop’s time margin violation due to variability, i.e. the signal unfulfilled the setup and hold times. Then, more time margin should be provided to the clock, i.e. system performance lost as frequency reduces, what could be solved by modifying properly VBB[1].

Summarizing, we show the feasibility of asynchronous-based FA as sub-VT circuit (low energy consumption and high variability robustness). Besides, their implementation by FDSOI devices allows a proper management by only modifying VBBin function of the system requirements (performance, temperature and variability).

References

[1] R. Wilson et al., ISSCC, 2014.

[2] B. Pelloux-Prayer et al., IEEE FTFC, 2012.

[3] S. Sinha et al., DAC Proc., 2012.

[4] B. Marr et al., IEEE Trans. on VLSI Syst., 2012.

[5] T.T. Liu and J.M. Rabaey, ASYNC, 2012.

Figure 1