bluuebunny/crossref_metadata_2025 huggingface dataset:
Analysis and Identification of Off-Odor Compounds in Electronic Systems
Authors: Nailos Mary Ann , Stein Dan , Nielsen Lawrence T. , Iwasinska Anna
Published: December 2020

The detection and identification of substances that give rise to aromas and off-odors is often a difficult task. Perception of odors is very subjective and odor detection thresholds vary from person to person. The identification of trace levels of compounds responsible for perceived odors is difficult using conventional analytical tools. This paper will focus on a novel method for sampling and analyzing aromatic volatile compounds using an analytical system specifically designed for odor analysis.
Using a Unified Data Stream to Drive Failure Analysis for Product Improvement in the Personal Computer (PC) Environment
Authors: Horley Shirleen , Rascon Joseph
Published: December 2020

The longer defective units are in the manufacturing pipeline before they are detected, the more expensive it becomes. Economic pressures drive the requirement to capture failures and perform root cause analysis further upstream in the product manufacturing cycle. This places greater emphasis on the ability to identify failures and perform value add analysis to drive product improvements as early as possible. This paper describes the method used to develop a reliable Unified Data Stream (UDS) that feeds the failure analysis process which in turn provides actionable information to product development teams in the Personal Computer (PC) environment. This manuscript describes the development and implementation of the Unified Data Stream designed to replace ambiguity and uncertainty with a defect trend and symptom pareto that drives action upstream. Focus will be on the output of UDS enabling the prioritization of product defects that feed the failure analysis system. Additionally, this paper will touch on the application of the UDS system for different types of pc components. The future of UDS is without bounds as it can also be applied to a wide range of products.
Fundamental Considerations for CDM Failure in 90nm Products
Authors: Wakai Nobuyuki , Kobira Yuji , Egawa Hidemitsu , Tsutsumi Masayoshi
Published: December 2020

Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.
Surface Defect Analysis by Using a Novel Backside XTEM Sample Preparation Method
Authors: Luo Jian-Shing , Huang Lang-Yu , Gu Wen-Lon , Russell Jeremy D.
Published: December 2020

This paper demonstrates a novel method of XTEM sample preparation for site-specific surface defect analysis using backside polishing. Analysis of three different types of site-specific surface defects was demonstrated using a novel backside XTEM sample preparation method. The details of the backside XTEM sample preparation method and some examples are reported in this paper. Comparing to Auger electron spectrometry (AES) results on similar defects, more detailed and precise information is observed using TEM analysis with this method. It is therefore a complementary technique to traditional AES analysis on surface defects for contamination with atomic level concentration. From the results, the sample preparation method can produce a clean, pristine surface that is well characterized and could be reproduced, successfully.
Deformation Study of Low K Dielectric after E-beam Exposure
Authors: Chen Xianfeng , Gao Qiang , Li Ming , Niou Chorng , Kary Chien W.T.
Published: December 2020

In this paper, the deformation mechanism of low K dielectric film under electron beams (E-beams) is discussed, and the effect of film deformation on the development of a low K dielectric film etching recipe is investigated. To provide meaningful data for process development, numerical analysis was used in the failure analysis procedure. A correction factor is formulated to calculate the change in thickness of the low K dielectric film after E-beam exposure. In addition, scanning electron microscope (SEM) settings for imaging low K dielectric films are optimized to minimize deformation.
New Approach—Sample Preparation Techniques for Plastic Small Outline Package (Frontside and Backside)
Authors: Marquez Erwin , Nguyen Dat
Published: December 2020

As device packages become smaller, the job of failure analysts becomes more difficult. Other complex configurations such as Small Outline Packages (SOP) pose unique problems. The difficulty of removing the encapsulant while preserving the integrity of the die, bond pads, bond wires and lead frame interconnects on a small outline package pose a serious problem. A new sample preparation technique is offered in order to expose the front side and backside of the die. This technique dramatically reduced the risk of damage and ensures the functionality of the device after decapsulation.
Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display
Authors: Fredrickson R.
Published: December 2020

Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.
Functional IC Analysis Through Chip Backside with Nano Scale Resolution—E-Beam Probing in FIB Trenches to STI Level
Authors: Schlangen R. , Leihkauf R. , Kerst U. , Boit C. , Krüger B.
Published: December 2020

One method of dynamic probing in modern integrated circuits (ICs) is performed through the backside of the device. The established techniques are limited in lateral resolution because they use infrared (IR) light. This paper demonstrates how state of the art FIB circuit edit (CE) processes enable the application of E-Beam probing through chip backside on current and future IC technologies with low risk of device performance degradation.
Use of a Solid Immersion Lens for Thermal IR Imaging
Authors: Breitenstein O. , Altmann F. , Riediger T. , Karg D. , Gottschalk V.
Published: December 2020

A hemispherical silicon solid immersion lens (SIL) was used to improve the spatial resolution of front-side thermal IR imaging in lock-in mode. The bottom of the SIL was coneshaped to reduce the footprint of the SIL to the size of the imaged region. Caused by the lock-in operation mode, the detection limit improves by 2-3 orders of magnitude, and scattered light does not limit the image contrast. By using this SIL in combination with an IR camera working in the 3-5 μm wavelength range, a spatial resolution of 1.4 μm was obtained for thermal IR imaging. An automatic SIL positioning facility was constructed to place the SIL exactly in the center of the imaged region and to easily remove it after the detailed investigation.
Planar Deprocessing of Advanced VLSI Devices
Authors: Wills Kendall Scott
Published: December 2020

Modern day VLSI Semiconductor devices are manufactured using a chemical mechanical polish (CMP) process. The resultant layers are planar with respect to one another and should be easy to remove. All that needs to be done is to lap the layer until the region of interest is exposed. In practice this has been difficult. This article describes the combination of processes that are required to take full advantage of the strength of deprocessing techniques (lapping, plasma and gel controlled wet chemical deprocessing) to deliver a perfectly planar sample for inspection. A discussion on the thought process required to adequately select the proper chemicals for the gel controlled etch is given. Finally, a typical deprocessing flow is described. It is concluded that this combined solution enables planarity to be maintained across 100% of the device surface. There is less chance the failure site is damaged by the deprocessing.
Marginal Deviation of Thermal Budget Brings Shallow Junction Formation Failure Forth Study
Authors: Chuang Tsan-Cheng , Shen C.M. , Chou J.H.
Published: December 2020

Shallow junction formation in silicon chips is a hot topic in the semiconductor industry. Reduction of power consumption of integrated circuits and an increase of the device performance would drastically reduce the sizes of circuits and, therefore, would necessitate a similar reduction for the depth of the p-n junctions. This paper performed the flash lamp annealing process application, applied to the CMOS as alternative method to attain the goal of shallow junction in the case. A marginal thermal budget mismatch related failure mode was revealed and explained.
Metal Slice Defect Induced Package Level Reliability Failure
Authors: Zhang Mark , Liao Scott , Liang Sanan , Lou Ricky , Chen Rock , Niou Chorng , Kary Chien W.T.
Published: December 2020

In this paper, a case of package level reliability test failure was studied. A model of “Slice Defect”, which was identified as the root cause by failure analysis, is introduced. Experiment results are presented to approve that such model is in fact correct and the corrective actions are effective.
Effects of Backside Circuit Edit on Transistor Characteristics
Authors: Jain R.K. , Malik T. , Lundquist T.R. , Wang Q.S. , Schlangen R. , Kerst U. , Boit C.
Published: December 2020

Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.
Measuring Static Noise Margin of 65 nm Node SRAMs Using a 7-Point SEM Nanoprobing Technique
Authors: Stallcup Richard E. , Cross Zachary , James William , Ngo Phuc
Published: December 2020

Non-visual fails have become an ever present complication in the IC industry. Nano probing SRAM bit cells at the inverter level allows the cell to be tested and static noise margin (SNM) to be measured. This paper explains how nano probing of a 65nm technology 6 transistor bit cell was performed and SNM dependence on supply voltage was measured for both hold and read modes. Connection to the bit cell was made at the Metal 1 layer with 7 nano probes to collect the voltage transfer curves (VTCs) of the two inverters of the cell. In this experiment, each inverter was tested by varying Vdd voltage from 1.5, 1.2, 1.0, 0.8, 0.6, 0.4 and 0.2V while collecting the VTC. The two VTCs of the cell are plotted to produce the cell’s butterfly curve from which the SNM is found graphically for each setting of Vdd.
Comparison of Active and Passive Voltage Contrast for Failure Localization
Authors: Rosenkranz R. , Werner W.
Published: December 2020

In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.
Annular Illumination and Collection in Solid Immersion
Authors: Ippolito Stephen Bradley , Terada Hirotoshi
Published: December 2020

Tailoring the angular spectrum with annular illumination and collection can significantly improve integrated circuit analysis with an optical microscope, when combined with solid immersion. We present the development, testing, and optimization of a simple and compact apparatus to implement annular illumination and collection in a Hamamatsu iPHEMOS system. We demonstrated improved imaging of an IBM 45nm silicon-oninsulator circuit, with annular illumination and collection in confocal scanning optical microscopy and widefield microscopy with an InGaAs camera.
Backside IR Raman Temperature Measurements
Authors: Aaron Falk R. , Pham Tram , Albright Grant
Published: December 2020

Spatial resolution limitations of IR thermal microscopy also limit the temperature accuracy for small thermal sources. Use of Raman temperature measurements significantly improves spatial resolution and thereby temperature accuracy. Previous, visible-wavelength, Raman temperature measurements are limited to top side measurements in silicon. This paper describes the first ever IR Raman measurements in silicon and demonstrates its use for backside temperature measurements.
Methodologies for Quantifying FIB “Milling Acuity”
Authors: Rue Chad
Published: December 2020

FIB column performance can be difficult to evaluate, and the traditional metrics of imaging resolution and minimum spot size give little indication of how a FIB system will perform its intended daily tasks. A series of supplemental FIB performance tests is proposed to quantify “milling acuity” under real-world conditions. A quantitative measuring scheme for evaluating the quality of High Aspect Ratio (HAR) vias is proposed, and an example is shown in which the HAR measuring scheme can be used for process development.
Production Yield Enhancement through Failure Analysis Investigation
Authors: Medikonduri Rajesh
Published: December 2020

Production yield verification for a complex device, such as the flash memory, is a problem of primary importance due to high design density and current testing capabilities of such design. In this paper, the flow byte issue in the one time programmable block is investigated through physical failure analysis (PFA). The customer reported fail for this unit was flow byte error with flipped data loss in one of the bit. Various experiments were done on numerous units to identify the yield related issue and prevent shipment of such units to customers. The case study from this paper is beneficial to the FA community by showing the exact methodology in identifying the problem, its containment, and implementation of corrective actions on the ATE to prevent shipment of low yield units to customer. The yield was enhanced by implementing the containment and corrective actions on the ATE.
Case Study in Fault Isolation of a Metal Short for Yield Enhancement
Authors: Ipek Sarven , Grosjean David
Published: December 2020

The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.
Backside Infrared Imaging Using Improved Refraction-Assisted Illumination Methods
Authors: Yeoh Terence , LaLumondiere Stephen , Ives Neil , Leung Martin
Published: December 2020

Infrared backside imaging using refraction assisted illumination (RAIL) allows for imaging microelectronic devices at high contrast and resolution through 700 microns of silicon without the need for specialized optics or coatings. However, due to the angle of illumination, not all of the metal features are equally illuminated. In this paper we present improvements on this method through image composition of a series of RAIL images taken at various illumination directions. The resultant composited image provides more uniform illumination and better approximates the features seen in scanning laser confocal microscopy.
Counterfeit Parts Recognition and Detection for Failure Analysts
Authors: Whittington Katherine V.
Published: December 2020

The electronics supply chain is being increasingly infiltrated by non-authentic, counterfeit electronic parts, whose use poses a great risk to the integrity and quality of critical hardware. There is a wide range of counterfeit parts such as leads and body molds. The failure analyst has many tools that can be used to investigate counterfeit parts. The key is to follow an investigative path that makes sense for each scenario. External visual inspection is called for whenever the source of supply is questionable. Other methods include use of solvents, 3D measurement, X-ray fluorescence, C-mode scanning acoustic microscopy, thermal cycle testing, burn-in technique, and electrical testing. Awareness, vigilance, and effective investigations are the best defense against the threat of counterfeit parts.
Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology
Authors: Dickson K. , Lange G. , Erington K. , Ybarra J.
Published: December 2020

This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.
A Position-Sensitive, Single-Photon Detector with Enhanced NIR Response
Authors: Stellari Franco , Song Peilin , Weger Alan J. , Nakamura Tomonori , Kim Stanley , Roche Robert
Published: December 2020

In this paper, we evaluate a novel, position-sensitive, singlephoton detector with enhanced Near InfraRed (NIR) sensitivity [1-3] for taking 2D Time Resolved Emission (TRE), also known as Picosecond Imaging for Circuit Analysis (PICA), in future low voltage SOI technologies. In particular, we will investigate and quantify the sensitivity of two generations (Gen. I and Gen. II) of PICA cameras by Hamamatsu Photonics as a function of the power supply voltage on an IBM 45 nm SOI test chip. Additionally, we will compare the results to the performance obtained with an InGaAs Single Photon Avalanche Diode (SPAD) from DCG Systems [4]. Finally we will show a case study and an advanced analysis and localization technique that takes advantage of the 2D capability of the camera.
Transmission Electron Microscopy Characterization of FinFET – Understanding the 3D Structure by 2D Imaging Technique
Authors: Zhu Yu , Gonsalves Jemima
Published: December 2020

For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub-nanometer accuracy. Due to the projection effect of TEM technique, comprehensive understanding of the 3D structure from 2D images is needed for process development of FinFET. This paper will address sample preparations and TEM imaging techniques for FinFET device at sub-100nm pitch.
A Sample Preparation Technique to Localize Gate Oxide Defects in Memory Arrays Using Conducting Atomic Force Microscopy
Authors: Lakshmanan Lakshminarayanan , Herlinger Lowell , Miller Kathryn
Published: December 2020

Shrinking gate lengths have led to increased challenges in isolating defects using conventional physical failure analysis methods. Conducting atomic force microscopy (CAFM) has been proven to be a powerful tool to isolate gate oxide defects in silicon-on-insulator devices. Some sample preparation techniques of exposing polysilicon and gate oxide, which were critical to perform CAFM scan, are discussed in this paper.
New Method for Decapsulation of Copper Wire Devices Using LASER and Subambient Temperature Chemical Etch
Authors: Lefevre Matthew J. , Beauquis Frédéric , Obein Michael , Gounet Pascal , Barberan Sandrine
Published: December 2020

IC packages have been greatly improved over the past several years. With the adoption of Cu wires and new green EMC (Epoxy Molding Compound), the suppression of lead, the use of Cu pillars and the increased number of dies, the verification of the quality of the assembly and failure analysis becomes critical. Starting twelve years ago, LASER ablation was introduced as a means to facilitate the pre-decapsulation of packages aiming at a completion by wet chemistry (acids) or dry chemistry (plasma). The decapsulation process with acid at medium temperature (75°C) does not permit to keep the Cu wires intact. Our studies and work in the past several years has consisted in lowering the temperature of acid use in order to minimize the effect of acid attack on the Al pads and Cu wires. Currently the thinnest wires used are 0.6 mil in diameter (approximately 15 μm). In this article we will demonstrate that decapsulations at sub-ambient temperatures are now possible and give expected results. Moreover, openings at near ambient temperature reduce the component deformation and also the deformation of its constituents compared to decapsulations at medium or high temperature.
A Novel Low Cost Technique to Perform Concurrent Topside and Backside Analysis of a Bare Die
Authors: Kabadi Raj , Swe Win Thandar
Published: December 2020

A novel low cost technique to facilitate concurrent topside and backside imaging of a bare die for optical fault localization purposes is presented. The technique overcomes the restrictions posed by unavailability of a suitable package or limited choices that may be present at a small scale packaging lab. The difficulties imposed on backside preparation of commonly used ceramic packages are overcome by providing an alternative that is relatively less expensive and easier to implement. This is accomplished by mounting the bare die on a glass cover slip using a suitable adhesive and wire bonding the bond pads to a specially designed printed circuit board. This method is being successfully utilized on multiple failure analysis requests received in our lab.
Systematic EFA Approach in Locating Floating Nodes in Analog Mixed Signal Devices
Authors: Karki Sagar
Published: December 2020

With advancements in technology, it is nearly impossible to find the defects in integrated circuits without applying appropriate failure isolation techniques. Failure isolation is a critical step in identifying the physical defect on integrated circuits. This paper addresses the challenges imposed by floating node conditions on both analog and digital circuitry, and a case study for each circuit type is presented. Different approaches along with the challenges involved in isolating each case in a very timely manner are addressed. Finally, the usefulness of global isolation tools, such as PEM (Photon Emission Microscopy), FIB (Focused Ion Beam), and micro-probing, is also discussed.
Activity Analysis at Low Power Supply on 45nm Technology
Authors: Bascoul Guillaume , Perdu Philippe , Sanchez Kevin , Lewis Dean , Dudit Sylvain , Celi Guillaume
Published: December 2020

VLSI internal testing through silicon substrate has been widely studied and techniques like Time Resolved Emission has given impressive results. Nevertheless, Integrated Circuits (IC) are still evolving with more and more complex functions and various kinds of signals that could be split into two main categories: data and control. Controls activate specific block and according to the wide range of different blocks and device complexity, the first analysis task is to check block activity related to control line status. In this paper, we show how Time Resolved Imaging can precisely answer this challenge even in up-to-date technologies at low power supply.
Enhanced Comparison of Lock-In Thermography and Magnetic Microscopy for 3D Defect Localization of System in Packages
Authors: Schmidt Christian , Altmann Frank , Vallett David P.
Published: December 2020

Lock-in thermography and magnetic current imaging are emerging as the two image-based fault isolation methods most capable of meeting the challenges of short and open defect localization in thick, opaque assemblies. Such devices are rapidly becoming prevalent as 3D integration begins to ramp up production. This paper expands on previously published work with a qualitative comparison of the techniques on single chip and stacked die packages with known designed-in or FIB created defects.
DRAM Cell Fault Localization Using Passive Voltage Contrast
Authors: Liew San Lin , Wei Yu Pei , Chen Bi Jen , Chen Hua Sheng , Luo Jian Shing
Published: December 2020

This paper presents the memory cell level passive voltage contrast (PVC) involving diode, capacitor and transistor devices in a (dynamic random access) DRAM chip. More particularly, we show that the voltage contrast sensitivity can be improved significantly by the adjustment of scan location and scan location sequence. Both leaky and resistive fault localizations by PVC imaging are presented to illustrate our point.
Lock-in Phase Mapping of Modulated Reflectance in Dynamically Operating Mixed-Signal IC Devices
Authors: Qian Zhongling , Brillert Christof , Burmer Christian
Published: December 2020

The lock-in phase mapping technique with modulated reflectance is introduced for the first time. With its help, the modulated reflectance mechanisms using thermal laser in operating FETs, particularly in the pinch off region, are clarified. The free carrier absorption mechanism dominates at a high modulation frequency, while thermo-reflectance mechanisms at a low modulation frequency. In the pinch-off region, thermo-reflectance mechanism cannot be neglected due to extremely low free carrier concentration. The modulated reflectance signal was unexpectedly observed at passive poly/oxide/poly capacitance. The advantages of lockin phase mapping in dynamically operating mixed-signal IC devices are shown in several case studies.
From EBT to LVP, from 130nm to 28nm Node, Internal Timing Characterization Evolution
Authors: Parrassin Thierry , Larre Philippe , Dudit Sylvain , Vallet Michel , Reverdy Antoine
Published: December 2020

In semiconductor industries, development of new technologies and new products generally follows a phase of yield improvement where Failure Analysis expertise is used to locate and fix killer defects and for design debug. When process and design reach a certain level of maturity, a second phase of optimization, qualification and reliability is executed in which Failure Analysis expertise is used for internal timing characterization of integrated circuit and results are compared with design/process simulations. In order to reduce the cost of testing during manufacturing, circuits embed Built in Self Timing Characterizer (BISC) for timing measurements inside critical functional blocks. Thanks to advanced integration, the last CMOS technologies allow high performance in terms of speed. Arithmetic and Logical Units (ALU) are able to work at frequencies greater than few GHz and some memories’ access time is lower than hundreds picoseconds. In the CMOS 40nm analysis case study presented in this paper, a BISC measurement of memories’ access times gives different results than what was expected from simulation. Internal probing becomes mandatory to understand this critical timing issue. A complete comparison is done between the 3 contactless probing techniques available in our laboratory which are the E-Beam Testing (EBT), Time Resolved Emission (TRE) and the recent Laser Voltage Probing (LVP) to highlight strength and weakness of each probing techniques in front of this timing related defect. We demonstrate that the LVP is an inevitable technique to address the nanometer-scale technologies in terms of spatial resolution, low voltage measurements and timing performance.
Improved Parasitic Fault Modeling for Automatic Analog Fault Simulation
Authors: Borgmann Gerhard , Burmer Christian , Mézière Sébastien
Published: December 2020

Analog simulation combined with Time Resolved Light Emission (TRE) can be used to evaluate different fault possibilities and to isolate the most likely fault candidate. In this paper we will describe an improved fault model derived from parasitic layout extraction.
Focused Ion Beam Circuit Edit on Copper Redistribution Layer
Authors: Motta Lorenzo , Veneto Paolo , Antolik Mark , Di Donato Donato
Published: December 2020

Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.
Multi-Site Full Thickness Backside Focused Ion Beam (FIB) Editing for eDRAM Array Address Descramble Verification
Authors: Herschbein Steven B. , Scrudato Carmelo F. , Worth George K. , Hermann Edward S.
Published: December 2020

Focused Ion Beam (FIB) modification for chip repair, layout verification, and internal signal probing has become an integral part of the process for bringing advanced products to market. As devices become more complex, with more levels of dense, thick upper power planes and tighter lower point-to-point wiring and device geometries, primary FIB access through the backside of the chip has become the only viable approach. And the pervasive switch to flip-chip solder bump mounting of chips to modules and chip to chip stacked die has made the backside editing approach ever more sensible by placing the unobstructed backside of the die within easy reach. Sample preparation for backside edit, however, has become a growing problem. Mechanical thinning of the silicon to speed trenching time can be problematic on highly stressed chips as there is a high risk of silicon cracking. Plus there are situations in which die strength must be preserved to enable the transfer of an edited die to a new substrate. While single point full thickness silicon editing has been demonstrated, the need to make multiple trenches for repetitive edits can be extremely time consuming when using conventional FIB bulk removal recipes. A single logic error often gets repeated in each core of a multi-core chip, and may need to be fixed at each location. Verification of existing SRAM and the introduction of embedded DRAM (eDRAM) for large blocks of L3 cache on high end microprocessors meant that the FIB lab would be called upon to provide layout checking services on a number of designs. Clearly, a better method for rapid mass silicon removal needed to be developed to keep multi-point backside editing viable. Through an extensive set of experiments we were able to develop a process that can sustain a removal rate of 10 million cubic microns of silicon per minute, enabling full thickness trenches in as little as 25 minutes. As will be shown, this preparation technique was successfully used to ensure the bit map descramble accuracy of multiple eDRAM array blocks in several cores, and to help evaluate test coverage.
Image Reconstruction Techniques for High Numerical Aperture Integrated Circuit Imaging
Authors: Berkin Cilingiroglu T. , Hakan Koklu F. , Ramsay Euan , Lu Yang , Yurt Abdulkadir , Clem Karl W. , Konrad Janusz , Goldberg Bennett B. , Selim Unlu M.
Published: December 2020

As feature sizes in integrated circuits (ICs) become smaller, higher-resolution defect detection and failure analysis techniques are required. The introduction of solid immersion lenses (SIL) has been an enabling technology for highresolution backside IC imaging. High Numerical Aperture (NA) SIL imaging introduces properties of focused light which cannot be predicted by scalar beam optics. For example, spatial resolution can be manipulated in selected directions by modification of the polarization direction in linearly polarized light. In this work, we propose a unified framework combining multiple SIL microscopy images collected using polarizations at different directions in order to improve image reconstruction performance and ultimately resolution and defect localization. We show improvement in reconstruction quality by combining data taken using light with multiple polarizations. We demonstrate the effectiveness of our framework on experimental data.
Comparison of Beam-Based Failure Analysis Techniques for Microsystems-Enabled Photovoltaics
Authors: Yang Benjamin B. , Cruz-Campa Jose L. , Haase Gaddi S. , Cole Edward I. , Tangyunyong Paiboon , Okandan Murat , Nielson Gregory N.
Published: December 2020

Microsystems-enabled photovoltaics (MEPVs) are microfabricated arrays of thin and efficient solar cells. The scaling effects enabled by this technique results in great potential to meet increasing demands for light-weight photovoltaic solutions with high power density. This paper covers failure analysis techniques used to support the development of MEPVs with a focus on the laser beam-based methods of LIVA, TIVA, OBIC, and SEI. Each FA technique is useful in different situations, and the examples in this paper show the relative advantages of each method for the failure analysis of MEPVs.
Novel Defect Detection Using Laser-Based Imaging and TIVA with a Visible Laser
Authors: Miller Mary A. , Tangyunyong Paiboon , Cole Edward I. , Pimentel Alejandro , Udoni Darlene M.
Published: December 2020

This paper presents two different case studies that highlight the use of reflected light imaging in laser scanning microscopy. In the first case study, the exact location of defects in metal comb test structures were much easier to detect with reflected light imaging than with thermally-induced voltage alteration (TIVA). This case study also shows visible-wavelength TIVA defect localization using a 532-nm laser. A comparison between 532-nm TIVA and conventional 1320-nm TIVA is made to show the resolution improvement with the visible laser. In the second case study, the cause of a linear string of bit failures was localized easily with backside reflected light imaging. It is observed that the indicated sites matched the light-induced voltage alteration signals and the failing cells in the bit map. In both of the case studies, the reflected light images have proved very helpful in the localization and characterization of failing devices or test structures.
Advanced CMOS Device Fault Isolation Using Frequency Mapping on Passive Structures
Authors: Goh S.H. , Yeoh B.L. , You G.F. , Hung W.H. , Lam Jeffrey , Ruttkowski E. , Kamaludeen R. , Zhang Henry
Published: December 2020

Backside frequency mapping on modulating active in transistors is well established for defect localization on broken scan chains. Recent experiments have proven the existence of frequency signals from passive structures modulations. In this paper, we demonstrate the effectiveness of this technique on a 65 nm technology node device failure. A resistive leaky path leading to a functional failure which, otherwise cannot be isolated using dynamic emission microscopy, is localized in this work to guide follow on failure analysis.
Simple and Effective Technique of Backside Deprocessing of Thin Flip Chip Package
Authors: Lee Suk Ho , Park Chan Hee , Cha Seung Joon , Lee Eun Cheol , Hong Kyu Shik
Published: December 2020

This paper introduces a simple and effective technique of backside de-processing procedure. This technique reduces time and steps by simple wet etching. The front-side deprocessing requires many steps, such as wet and dry etching and parallel lapping, and also backside de-processing requires mechanical grinding to thin down the silicon thickness before wet etching. This paper introduces an effective way by skipping mechanical grinding and by etching at high temperature in case of thin flip chip. The backside silicon images are presented and compared after de-processing with TMAH and KOH which commonly have been used for bulk silicon etchant. The results show uniform backside images without any damage or residue. This backside de-processing technique was applied in two case studies to facilitate failure analysis.
A New Deprocess Flow of Failure Analysis for MEMS Motion Sensor
Authors: Huang Chun-An , Long Han-Yun , Chiang King-Ting , Chuang Li , Tsui Kevin
Published: December 2020

This paper demonstrates a new de-process flow for MEMS motion sensor failure analysis, using layer by layer deprocessing to locate defect points. Analysis tools used in this new process flow include IR optical microscopy, thermal system, SEM and a cutting system to de-process of MEMS motion sensor and successful observation defect points.
Top-Down Delayering with Planar Slicing Focus Ion Beam (TD-PS-XFIB)
Authors: Low G.R. , Tan P.K. , Ng T.H. , Yap H.H. , Feng H. , He R. , Tan H. , Dawood M.K. , Huang Y.M. , Wang D.D. , Zhao Y.Z. , Zhou Y. , Lam J. , Mai Z.H.
Published: December 2020

Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-SEM de-layering technique over mechanical de-layering is better control of the de-layering process. Combining the precise milling capability of the FIB with the real-time imaging capability of the SEM enables the operator to observe the de-layering as it progresses, minimizing the likelihood of removing either too much or too little material. Furthermore, real time SEM view during top-down XFIB de-layering is able to provide a better understanding of how the defects are formed and these findings could then be feedback to the production line for process improvement.
Improving Failure Analysis for Cell-Internal Defects through Cell-Aware Technology
Authors: Hapke F. , Keim M. , Herrmann T. , Heidel T. , Reese M. , Schloeffel J. , Rivers J. , Redemund W. , Over A. , Glowatz A. , Fast A. , Benware B. , Rajski J.
Published: December 2020

This paper describes a new approach for quickly ramping up the yield for new CMOS technologies by performing a cell-internal (CI) diagnosis based on the cell-aware (CA) methodology. We present results from carrying out this new method on a test chip of a 28-nm technology. After creating defect-oriented CA test patterns for this test chip, we tested various wafers with those CA patterns, selected fail data, conducted a normal electrical failure analysis, and used the new CI diagnosis method to guide the physical failure analysis (PFA) process to look specifically for hot-spot areas within standard library cells. This new approach can reduce the yield ramp-up time significantly.
Improved Lock-in Phase Mapping of Modulated Reflectance with SIL
Authors: Qian Zhongling , Brillert Christof , Burmer Christian
Published: December 2020

The application of lockin phase mapping of modulated reflectance with SIL is discussed in detail, particularly the socalled ghost mapping signal in STI neighboring to active regions. The different lockin phase between active regions and ghost regions showed clearly that both of them have different physical origins. The phase transition between active regions provides an enhancement of spatial resolution for defect localization in scan cell and sub blocks.c
A Comprehensive Investigation of the Galvanic Corrosion Induced Ag-Al Bond Degradation in Microelectronic Packaging Using Argon Ion Milling, SEM, Dual Beam FIB-SEM, STEM-EDS, and TOF-SIMS
Authors: Chen Yixin , Simon Emmanuel , Khoo Bing Sheng , Lee Esther , Chooi Meailing , Hao Meng , Shao Jingjing , Hua Younan , Li Xiaomin
Published: December 2020

In this study, a comprehensive investigation of the Ag-Al bond degradation mechanism in an electrically failed module using the argon ion milling, scanning electron microscopy (SEM), dual beam focused ion beam-SEM, scanning transmission electron microscopy energy dispersive x-ray spectroscopy, and time-of-flight secondary ion mass spectrometry is reported. It is found that the bond degradation is due to the galvanic corrosion in the Ag-Al bonding area. Specific attention is given to the information of microstructures, elements, and corrosive ions in the degraded bond. In this study, it is believed that the Ag-Al bond degradation is highly related to the packaging designs.
Feature Based Nondestructive Fault Isolation in Advanced IC Packages
Authors: Lee K.C. , Alton J. , Igarashi M. , Barbeau S.
Published: December 2020

Traditional time domain reflectometry (TDR) techniques employ time-based information to locate faults within packages with minimal references to internal structures. Here, we combine a novel and innovative technique, electro optical terahertz pulse reflectometry (EOTPR) [1], with full 3D device-under-test (DUT) modelling to quickly and nondestructively perform feature-based analysis. We demonstrate fault isolation to an accuracy of 10 ìm or better with respect to device features in an advanced integrated circuit (IC) package.
Identification of Subtle Defect by Means of High Kev SEM Passive Voltage Contrast
Authors: Xie Sujing , Chen Chaoying , Wang Nathan , Komrowski Andrew , Wu Qindi , Shah Saunil
Published: December 2020

This paper presents two cases utilizing high KeV Passive Voltage Contrast (PVC) for defect localization that is impossible with other techniques. The first case is thin layer resistor of CrSi. De-processing or polishing to expose the defective layer may damage it. High KeV PVC combined with FIB etch allows for a clear top view and x-section image. The second case involves a beam sensitive via chain. In order to avoid ion-beam-caused-damage, carbon paste was used to ground the sample. A high KeV electron beam was used to localize the defective via. This paper also discusses the way to avoid beam caused sample damage and how to apply it for further grounding and FIB cross sectioning to reveal the defect.
In-Line Defects Overlaying with Functional Failures and Characterization for Fast Defect Learning and Fast Yield Improvement
Authors: Song Zhigang , Patterson Oliver D. , Xu Qian
Published: December 2020

Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.
Application of Soft Defect Localization Technique for SRAM Soft Failure Debug
Authors: Je Moon Seung , Lian Yeoh Boon , Huat Goh Szu , Chithambaram Shaalini , Quah A.C.T , Lam Jeffrey
Published: December 2020

Dynamic Laser Stimulation (DLS) technique have met with great success over the past few years in helping failure analysis engineer to tackle different type of soft failures. DLS is widely applied to devices presenting an abnormal behavior for any electrical parameter, such as operating voltage and frequency. This paper showcase another successful implementation of DLS technique, combined with design analysis to reveal the root cause for SRAM soft failure.
Continuous-Wave 1064 nm Laser for Laser Voltage Imaging and Probing Applications
Authors: Ravikumar Venkat-Krishnan , Phoa Angeline , Sabbineni Prasad , Skvortsov Dmitry , Lundquist Ted
Published: December 2020

Laser-voltage probing (LVP) and imaging (LVI) using a continuous-wave (CW) 1320-1340nm laser have become mainstream techniques for electrical fault isolation. A 1064nm laser with a 20% shorter wavelength offers immediate resolution advantages compared to 1320nm at a cost of increased intrusion. This paper explores the potential of CW 1064nm laser and identifies opportunities in fault isolation
Development of DPA (Destructive Physical Analysis) Method for Cu Wire Device
Authors: Tateyama Hirohumi , Shimizu Wataru , Kubota Hidehisa , Murahara Daisuke , Hattori Tamiko , Ootani Naoki , Yasuda Yujiro , Yabe Kazuhiro
Published: December 2020

Destructive physical analysis (DPA) is one of the reliability evaluation methods, which observes defects and faults in a device, and it can classify the reliability level of the device. After a description of the current method for Au wires, this paper explains the DPA for a Cu wire device. The DPA for semiconductor devices is divided roughly into three steps: a non-destructive inspection, an assembly process inspection, and a wafer process inspection. Investigation of DPA for Cu wire device includes wire material identification, optimization of decapsulation for Cu wire device and wire pull strength test, and observation of package cross-section. From the result, novel sample preparation (embedding a sample in molding package and forming the package to be suitable for cross-sectional observation by ion polishing) enables the observation of the thin alloy layer at the wire/pad interface.