Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate
Authors: Takeda Yuki , Azuma Yuki , Zheng Ziye , Motohisa Junichi , Tomioka Katsuhiro 
Published: December 2024

Introduction

Miniaturization of field-effect transistors (FETs) have serious issues in enhanced leakage current, short-channel effect, and power consumption. In this regard, the vertical gate all-around (VGAA) structure using the III-V compound semiconductor nanowires (NWs) is expected as alternative transistor to solve the problems in leakage current and short channel effect. There is still challenge in decreasing power consumption of the FET because the reduction in subthreshold slope (SS) has physical limitation in thermionic carrier transport (SS = 60 mV/dec). Tunnel FETs (TFETs) can lower the SS less than the physical limitation in MOSFETs and are expected to be used as next-generation low-voltage switching devices. We have demonstrated vertical gate-all-around (VGAA) TFET using III-V/Si tunnel junction which was formed by the selective-area growth of III-V NWs on Si and achieved a steep SS characteristics and complementary operation [1]. These demonstrations should be expanded on silicon-on-insulator (SOI)(111) platforms toward circuit applications using the III-V/Si VGAA-TFETs. Here, selective-area growth of the InAs NWs on thin SOI(111) substrates and demonstrated InAs/Si VGAA-TFETs on SOI platforms.

Experimental procedure

First, a 35-nm-thick SiO2 film was formed on p-type SOI(111) by thermal oxidation. The SOI thickness was 600 nm. Periodical circular openings were formed using electron beam lithography and dry/wet etchings. Next, InAs NWs were grown by selective-area growth. Here, we used a pulse growth technique to orient NWs in the vertical <111>B direction on a nonpolar SOI substrate, making the substrate surface polar (111)B, and aligning vertical NWs [2]. Next, we fabricated VGAA-TFETs by using three-dimensional device process in previous reports [1]. First, Hf0.8Al0.2O were formed as gate oxides by atomic layer deposition (ALD). Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal. After that source metal (Ti/Au) was evaporated 20 nm/50 nm on the substrate by EB vapor deposition. Next, benzocyclobutene (BCB) was used as isolation layer between gate and drain metals. Then drain metal (Ti/Pd/Au) was evaporated 20 nm/20 nm/50nm on the top of the NWs. Finally, the VGAA-TFETs were annealed at 350 - 400°C in order in N2 for ohmic contacts in the source and drain regions. VGAA-TFETs were measured after annealing for each temperature.

Results

The growth results showed vertical InAs NWs were successfully integrated on the p-SOI(111) substrates. The grown InAs NWs have hexagonal pillar structures surrounded with {-110} vertical facets and (111) B planes. Each NWs were composed of axial Zn-pulse doped intrinsic/Si-doped n-type/Sn-pulse doped n+-type NW segments. The average height is inversely proportional to the square of the diameter. Therefore, as similar to the conventional selective growth of InAs NWs on Si(111), the surface diffusion process of In atoms was dominant for the NW growth on SOI(111) surface.

Transfer characteristics of the fabricated VGAA-TFET after annealed at 350°C indicated the tunnel current in the InAs/Si tunnel junction was electrically modulated by gate bias. The minimum SS was 37 mV/dec at VDS = 0.50 V, which was less than the theoretical limitation of conventional MOSFETs.

The on-state current was 21 nA/μm at drain and source (VDS) of 1.00 V. The off current was 6.5 fA/μm when VDS was 1.00 V. Also, the threshold voltage (VTH) was 0.55 V. Transconductance was 31 nS/μm at VDS = 0.50 V. The measured current and transconductance were normalized by the number of NWs and the gate outer perimeter.

We also investigated anneal temperature dependence of the device performance. The increasing in anneal temperature slightly lowered the minimum SS from 37 mV/dec to 23 mV/dec. And the on-state current was increased with increasing the anneal temperature. However, nonlinearity in the output IDS – VDS curve was enhanced with increasing the anneal temperature. This was assumed to be formed Schottky contact on the source metal. At the higher anneal temperature above 380°C, Ti/Au source metal possibly formed silicide (TiSi2) layer at the Ti/p-SOI interface. Thus, the contact resistance was decreased by the silicidation, and the on-state current was increased. However, Schottky contact of Au/Si was partially formed through the silicidation layer due to the very thin Ti interlayer. One of the possible approaches was to increase the Ti thickness or to use Al or Cu as single layer film. Further improvement of the device performance will be discussed.

[1] K.Tomioka et al., IEEE IEDM. Tech. Dig. (2020) 429-432

[2] K.Tomioka et al., Nano Lett. 8(2008) 3475-3480