bluuebunny/crossref_metadata_2025 huggingface dataset:
Effects of Liner Metal and CMP Slurry Oxidizer on Copper Galvanic Corrosion
Authors: Shima Shohei , Fukunaga Akira , Tsujimura Manabu
Published: September 2007

In-situ electrochemical measurements during polishing and in static were performed for copper and barrier metals in two kinds of copper slurries using a rotating disk electrode apparatus. Current density during polishing in the slurry using APS as oxidizer is larger than in H2O2 as oxidizer for all metals. This is due to the strong reactivity of APS on the exposed metal surface. Potential of Ru during polishing is larger than that of Cu. This means Ru is more noble than Cu and the possibility of Cu galvanic corrosion is high in APS slurry. In the case of Ta, Cu is more noble than Ta, so Cu is stable. In H2O2 slurry, Ru and Cu potential is almost same and current density is low, so Cu is stable. However, abrupt potential change of copper was detected by dipping exposed barrier metal window in all slurries. This indicates Cu could generate corrosion.
Acceleration Effect of CuCN in Ag Electrodeposition for Metal Interconnection
Authors: Cho Sung Ki , Lee Jong Kyun , Kim Soo-Kil , Kim Jae Jeong
Published: September 2007

The addition of CuCN accelerated the deposition rate in cyanide-based Ag electroplating. The catalytic effect came from the high-order complexation of Cu with the free CN- ions in electrolyte. It changed the equilibrium state of the electrolyte, presented as an increase in the amount of Ag(CN)2- compared to Ag(CN)32-. Because Ag(CN)2- could be reduced more easily, Ag electroplating was accelerated. FT-IR analysis showed the equilibrium change with the increase in Ag(CN)2- peak with CuCN addition. For superfilling, it is necessary to localize the complexation on Cu surface.
Selective Formation of Micropads for 3D Interconnect Applications
Authors: Mathew Varughese , Chatterjee Ritwik , Garcia Sam , Acosta Eddie , Jones Robert
Published: September 2007

Multi-strata bonding and inter-strata connectivity are the two key processes to enable 3D chip stacking. Die-to-wafer bonding can be achieved through thermo-compression bonding of micropads composed of Cu and Sn. This paper presents a method of formation and preliminary characterization of micropads consisting of a stack of Sn (top)/Cu/CoWB/Cu. CoWB, which serves as a diffusion barrier for Sn, is formed selectively on copper by electroless plating and Sn is deposited on Cu by immersion plating. The plating rate of Sn was found to strongly depend on temperature and the plating rate decreases with increasing Sn thickness. A plating condition was used which resulted in a Sn rich surface of the micropad which is desired for robust inter-strata bonding. Annealing of the film at 400 ºC resulted in complete conversion of the Cu and Sn film to Cu-Sn intermetallic compounds, which is required for using this metallurgy for bonding applications.
Critical Components of FinFet Integration: Examining the Density Trade-off and Process Integration for FinFET Implementation
Authors: Harris Rusty , Hussain M. , Smith Casey , Yang Ji-Woon , Barnett J. , Sassman Barry , Song S. , Lee B.H. , Tseng Hsing , Jammy Raj
Published: September 2007

While the scaling efforts continue into a device regime performance simply may not come without large scale off state leakage issues, significant device changes are being considered such as FinFETs. The concept of a double- or triple-channel device is not new, but the practical roadblock to implementing such a device has some familiar problems from an integration standpoint. Furthermore, new issues that the 3-dimensionality of FinFETs presents create integration challenges for series resistance and overall packing density. In this paper, we outline the critical issues and present practical solutions to these problems from a theoretical standpoint. It is shown that clear pathways do exist in spacer, silicide and epitaxial source/drain with unit process development. Finally, the implementation of necessary techniques such as spacer transfer and compatibility with high k/metal gate integration is examined.
Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond
Authors: Park Dae-Gyu , Chudzik Mike , Yin Haizhou
Published: September 2007

This paper provides a forum for reviewing and discussing new elements and challenges in the front end of line (FEOL) process integration for 32nm logic devices in the following areas: Metal/high-k (MHK) gate stack, mobility enhancement substrate technology and strain engineering.
Transport in Ultrathin SOI MOSFETs and Silicon Nanowire Transistors
Authors: Hiramoto Toshiro
Published: September 2007

Transport in ultra-thin-body (UTB) SOI MOSFETs and silicon nanowire MOSFETs is extensively studied by experiments and calculations. The transport properties in these devices are strongly affected by the quantum confinement effects. Mobility enhancement of both electron and hole is experimentally demonstrated in (110) UTB SOI MOSFETs. The characteristic variations of silicon nanowire transistors with nanowire width of less than 10 nm are also experimentally investigated.
Surface Energy Characterization of Partially Cured Benzocyclobutene for 3D Interconnect Applications
Authors: McMahon J. J. , Gutmann R. , Lu J.
Published: September 2007

Accommodation of nonplanarity is required in a monolithic wafer-level three-dimensional (3D) technology platform, in which two damascene patterned copper/benzocyclybutene (BCB) layers are bonded to form mechanical bonds between wafers and inter-wafer copper interconnects. The temperature dependence of the surface energy of partially-cured BCB, an important material parameter for determining accommodation of nonplanarities, is characterized using contact angle measurements and varies in the range of 39-50 mJ/m^2 between 35 C and 230 C. These changes are discussed with respect to the surface structure and mechanical properties of the BCB, and should not be a barrier to usage of partially-cured BCB as a bonding material.
MMICs Using SiGe BiCMOS for Ubiquitous Wireless Network
Authors: Masuda Toru , Shiramizu Nobuhiro , Nakamura Takahiro , Washio Katsuyoshi
Published: September 2007

Recent progress in circuit design techniques for SiGe BiCMOS MMICs in microwave and millimeter-wave region are presented. The effectiveness of low-power MMIC design techniques and slow-wave transmission line design technique were confirmed through the measurements using fabricated chips.
Advantages of Nano-Grating Si Substrates in CMOS-FET Characteristics
Authors: Zhu Xiaoli , Kuroki Shin-Ichiro , Kotani Koji , Ito Takashi
Published: September 2007

The drivability enhancement of CMOSFET of both n-type and p-type was achieved by using nano-grating silicon substrate without any complex fabrication process. The transconductances of both nMOSFET and pMOSFET on nano-grating substrates were increased thanks to the increase in effective channel width, leading to the area advantage of about 64% normalized by that of a conventional substrate. The channels were formed on horizontal (100) and vertical (110) surfaces of the nano-grating. Due to the existence of the current flowing in <110> direction on (110) surface, the effective carrier mobility in nano-grating nMOSFET was lower, while that in nano-grating pMOSFET was larger than the conventional one. So the difference of drivability enhancement between nMOSFET and pMOSFET became slighter, from which the area balance of CMOS circuit fabricated on the nano-grating substrates were improved.
Low-Temperature Epitaxial Growth of [Fe3Si/SiGe]n (n=1-2) Multi-Layered Structures for Spintronics Application
Authors: Sadoh Taizoh , Ueda Koji , Ando Yuichiro , Kumano Mamoru , Narumi Kazumasa , Maeda Yoshihito , Miyao Masanobu
Published: September 2007

Our recent progresses in epitaxial growth of Fe3Si on Ge substrates are reviewed. Single crystalline Fe3Si layers with atomically flat interfaces were achieved on Ge(111) substrates by optimizing growth conditions at low temperatures (60-200oC). Thermal stability of it was guaranteed up to 400oC. In addition, epitaxial growth of mixed layers composed of Fe3Si, FeGe, and FeSi on Ge substrates at 400oC is reported. Finally, epitaxial growth of Fe3Si/Ge/Fe3Si/Ge structures is discussed. These results will be a powerful tool to open up SiGe related spintronics.
Process Optimization by Means of Integrated Monitoring Tools in the Semiconductor Industry
Authors: Pfitzner Lothar H. , Nutsch Andreas , Roeder Georg , Schellenberger Martin
Published: September 2007

Semiconductor manufacturing still follows Moorés Law, stating a cost reduction of approximately 25 to 30 % per year, a value actu-ally achieved in the past 40 years. One of the key enablers for fur-ther continuation of Moore's Law will be a much tighter process control. This paper describes aspects of Advanced Process Control and especially of integrated metrology, the foundation of process optimization by means of integrated process monitoring tools. Shortest response time requires that measurement methods have to be engineered as near as possible to the process itself, thus reduc-ing the time between processes, measurement and corrective ac-tions. Such integrated metrology is realized as in-line metrology, in situ metrology or virtual metrology. This paper presents the devel-opment of sensors, their integration and results for control of resist processing in lithography, use of according sensors for the control and endpoint detection in CMP processes, and novel methods for geometrical metrology in CMP process monitoring.
Evaluation of Hybrid-Orientation (110)/(100) Direct Silicon Bonded Interfaces
Authors: Wagener Magnus C. , Seacrist Mike , Rozgonyi George
Published: September 2007

The interface state density of hybrid-orientation, direct silicon bonded wafers have been evaluated by current transport and capacitance techniques. Different measuring strategies are presented for (110)/(100) bonded interfaces positioned at various distances from the surface, ranging from 200nm to several microns. The Fermi-level is found to be pinned mid-gap by a high state density of roughly NSS = 1E13 states/cm2/eV at the interface. Methods by which the electrical uniformity of the bonding interface across the wafer surface can be determined have been demonstrated using photoconductive decay measurements and electron-beam induced current microscopy.
Deep Level Transient Spectroscopy Study of Dislocations and Related Defects in SiGe/Si Heterostructures
Authors: Lu Jinggang , Park Yongkook , Rozgonyi George
Published: September 2007

As-grown and annealed SiGe/Si heterostructures have been examined by Deep Level Transient Spectroscopy and C-V techniques. Detailed analyses of trap density obtained by the two techniques showed that the density of acceptor trap levels was 4E14 cm-3 in the as-grown SiGe layer. It was found that more than 1E14 cm-3 donors trap concentration were generated during 600degC, 10 min annealing, and annealing at 800degC to 1000degC removes most of the acceptor and donor trap levels. It is suggested that the acceptor levels in the as-grown sample is likely due to vacancy clusters generated by dislocation jog-dragging.
Characterization of Biaxial Strained-Silicon by Spectroscopic Ellipsometry
Authors: Gong Ying , Ng Chee , Wong Terence
Published: September 2007

Spectroscopic ellipsometry (SE) and synchrotron x-ray scattering have been applied to the non-destructive characterization of biaxial tensile strained silicon (ξ-Si). SE data from 250nm - 500nm were acquired from three epitaxial ξ-Si samples grown on silicon germanium (SiGe) virtual substrates by chemical vapor deposition (CVD). The SE data was fitted by a two-step procedure using a parametric dielectric function model for crystalline semiconductors and structural data obtained separately from X-ray scattering. By monitoring the shift of the E1 critical point in the fitted dielectric function spectrum, the tensile strain of ξ-Si can be determined from known elastic constants and deformation potentials of Si. Strain values obtained are generally in agreement with Raman measurements. The structural characteristic of the sample with the highest germanium concentration in the virtual substrate was further studied by reciprocal space mapping (RSM) and atomic force microscopy.
Verification of a Method to Detect Grown-in Oxide Precipitate Nuclei in Czochralski Silicon
Authors: Kissinger Gudrun , Sattler Andreas , Dabrowski Jarek , Von Ammon Wilfried
Published: September 2007

Ramped anneals with 1 K/min are suitable to characterize grown-in oxide precipitate nuclei. Fitting of experimental values to simulated values makes it possible to get information about the size of the nuclei. Theoretical simulations have shown that the nucleation of additional nuclei during the ramped anneals is negligibly small. It is confirmed again that grown-in nuclei just shrink during fast ramp anneals at 1000-1100 {degree sign}C for 15 min which are usually applied to dissolve grown-in oxide precipitate nuclei. It is assumed that the explanation for this observation can be found either in the fact that the nuclei are heterogeneous or in the different energy barriers resulting from the different phases involved in nucleation and dissolution of nuclei. While nucleation starts with the coherent agglomeration of VO2 complexes, dissolution starts from amorphous SiO2 leaving a core with a very high energy per oxygen atom which cannot be further dissolved.
Influence of the Synthetic Procedures on the Optoelectronic Properties of CdSe Nanodots
Authors: Farva Umme , Na Young Hee , Kim Young Wook , Kim Do Hoon , Nguyen Truong Nguyen Tam , Park Chinho
Published: September 2007

Synthetic procedure along with the annealing effects on the optical and structural properties of CdSe nanodots has been analyzed at the temperature of 350 oC. It was observed that annealing induced structural transition in nanocrystalline CdSe from cubic zinc blende to hexagonal wurtzite structure. The transition takes place at temperatures higher than those of CdSe bulk crystals (95 oC), underlying that the CdSe structure is determined not only by the temperature but also by the crystal size. The role of free surface energy in low-dimensional CdSe systems is elucidated. The thermal effect results in the increase of particle size from 4 nm to 5 nm in synthesized and annealed CdSe respectively.
Delineation of Crystalline Defects in Semiconductor Substrates and Thin Films by Chemical Etching Techniques
Authors: Kolbesen Bernd , Possner Daniel , Maehliss Jochen
Published: September 2007

Successful implementation of novel materials like SOI and sSOI into the mass production of advanced devices requires monitoring of their crystal quality and defect densities. Preferential etching techniques in combination with light optical microscopy are still the workhorse for a quick and simple evaluation of defect types and area densities.Classical etching recipes applied to SOI and sSOI substrates reveal certain limitations and the most common recipes are based on toxic Cr(VI). Therefore there is a need for alternative Cr-free recipes with adequate or superior performance for application to SOI and sSOI. We discuss some basic aspects of preferential etching and present two different types of novel Cr-free preferential etching chemistries which are suitable for the application on SOI. Organic peracid etches consist of hydrofluoric acid, an organic acid and hydrogen peroxide which reacts with the organic acid forming the corresponding organic peracid which then acts as the oxidizing agent. These etch solutions have very low removal rates (0.4 -1.5 nm/min at 25{degree sign}C), are very defect sensitive and are suitable for the application on SOI films as well as on CZ bulk material where they reveal vacancy agglomerates (D defects, COPs) with high sensitivity.
Doping Density Depth Profiling Analysis with High Resolution Elastic Recoil Detection
Authors: Bergmaier Andreas , Dollinger Guenther
Published: September 2007

The quantitative analysis of light elements in ultra thin films thinner than 10 nm is still a nontrivial task. This paper summarizes the prospects of high-resolution Elastic Recoil Detection (ERD) using a Q3D magnetic spectrograph. It is shown that sub-nanometer resolution can be achieved in ultra thin films and even monolayer resolution is possible close to the surface. ERD has the best quantification possibilities compared to any other method. Sensitivity is sufficient to analyze main elements and impurities as e.g. necessary for the characterization of microelectronic materials. In addition, high-resolution channeling ERD can be performed in order to obtain information on lattice location of light elements in crystalline ultra thin layers. The potential of high-resolution ERD is demonstrated by several applications where it is the most valuable tool for elemental profiling.
Advanced Metrologies for Wafer Contamination and Nanolayer Characterization Using XRF Methods
Authors: Beckhoff Burkhard , Fliegauf Rolf , Hönicke Philipp , Kolbe Michael , Müller Matthias , Pollakowski Beatrix , Weser Jan , Ulm Gerhard
Published: September 2007

X-ray fluorescence (XRF) analytical methods based on synchrotron radiation can effectively contribute to the characterization of both semiconductor surface contamination and nanolayered systems. Total-reflection XRF allows for contamination analysis, reference-free XRF for the determination of nanolayer thicknesses and composition, and grazing-incidence XRF for elemental depth profiling of nanolayered systems. Due to the tunability of synchrotron radiation, each of these XRF methods can be easily combined with NEXAFS investigation to determine the species of contamination as well as nanolayer constituents.
Hf-related Gate Oxide Thickness Mapping Using XRR/XRF
Authors: Ortega Richard , Baumann Scott , Hockett R. S. , Murakami H. , Ramakrishnan V.
Published: September 2007

For over 10 years the semiconductor industry has ardently pursued the research and development for a gate oxide that would replace silicon oxide nitride with a higher dielectric constant material in order to reduce gate leakage and continue Moore's Law scaling. The industry consensus has been Hf-related oxides such as hafnium oxide (HfO2), hafnium silicate (HfSiO), and nitrogen-doped hafnium silicate (HfSiON). One of the process goals for the thickness uniformity of these Hf-related gate oxides is +4% (3 sigma) of the Equivalent Oxide Thickness (EOT) which is the physical thickness divided by the dielectric constant of the new gate oxide scaled to the SiO2 dielectric constant. The work presented here is to show the capability of XRR/XRF for mapping the uniformity of the physical thickness of Hf-related gate oxides using the Technos S-MAT 2300.
Contactless Diagnostic Tools and Metallic Contamination in the Semiconductor Industry
Authors: Savin Hele , Yli-Koski Marko , Haarahiltunen Antti , Talvitie Heli , Sinkkonen Juha
Published: September 2007

Minority carrier recombination lifetime method is a widely used contactless tool to monitor metallic contamination in the semiconductor industry. We present here how the method can be used to measure and identify the three most common metallic contaminants in silicon: iron, copper, and nickel.
Aberration-corrected Scanning Transmission Electron Microscopy for Atomic-scale Characterization of Semiconductor Devices
Authors: Van Benthem Klaus , Pennycook Stephen J
Published: September 2007

Aberration correction in the scanning transmission electron microscope brings sub-Aångström electron probe sizes and single atom sensitivity which enable the characterization of semiconductor devices and their defects with unprecedented detail. Further benefits include simultaneous bright field and dark field image acquisition and a new three-dimensional imaging technique. Here, we will review some major results obtained by aberration corrected scanning transmission electron microscopy and highlight some future research directions.
ALD Capping Layers for Accelerator Superconducting Radio Frequency Cavities
Authors: Pellin Michael J. , Elam J. , Moore Jerry
Published: September 2007

Superconducting radio frequency (SCRF) materials are becoming increasingly important for a variety of applications. Applications range from cellular phone networks to high energy physics particle accelerators such as the International Linear Collider (ILC). Improvement of these devices requires coherent, high purity surface films of nanometer thickness. Here Atomic Layer Deposition (ALD) methods are described for producing well defined dielectric (Al2O3) films on Nb, the substrate of choice for SCRF applications.
Large Scaled ALD/PECVD Reactor for Flat Panel Display Application
Authors: Murata Kazutoshi , Washio Keisuke , Miyatake Naomasa , Mori Yasunari , Tachibana Hiroyuki , Uraoka Yukiharu , Fuyuki Takashi
Published: September 2007

High quality SiO2 gate insulators are one of the key technologies for improving performance of Low Temperature Poly Silicon TFTs. We have developed an ALD/PECVD reactor, which handles 370 mm×470 mm glass substrates. The reactor has a unique plasma source of the monopole antenna, which is the electromagnetic wave coupled type and operates at VHF range. A PE-ALD SiO2 film was deposited at 200{degree sign} with alternating exposures of aminosilane and radical oxygen generated by the plasma. Growth rate of the film and thickness variation were 0.1 nm cycle-1 and less than {plus minus}5 %, respectively. Conformal film growth was observed on patterned substrates. Uniform current-voltage performance was confirmed on the glass and its electrical field was higher than 8.0 MVcm-1 at a leakage current of 1×10-6 Acm-2. The film had an excellent Si / SiO2 interface trap density of lower than 1×1011 cm-2eV-1 after forming gas annealing.
Savannah ALD Systems: Enabling Quick Results
Authors: Monsma Douwe J. , Becker Jill
Published: September 2007

Cambridge NanoTech has sold more than 70 atomic layer deposition (ALD) systems in the last 3 years. These turn-key and affordable systems have enabled researchers both in personal and multi-user cleanroom environments to introduce ALD to a wide range of applications: chemical, electronic, nanotechnology, MEMS, optical, biological and many more. These fields can now take advantage of the unique conformal coating capabilities of ALD. Cambridge NanoTech is continuously enhancing the ALD experience and has recently introduced a new heated ALD precursor vapor trap. Conventional stainless steel wool and activated alumina traps were inadequate for ALD applications due to precursor backstreaming and particulation. The new honeycomb channel trap avoids backstreaming and particulation and allows operators to keep pumping line components and pumps clean.
A Silicon Nitride MIM Capacitor for Analog/Mixed-Signal Integrated Circuit using Manufacturable Atomic Layer Deposition Equipment
Authors: Ando Toshio , Ohta Yosuke , Ashihara Hiroshi , Imai Toshinori
Published: September 2007

MIM capacitors with ALD SiN as a dielectric are integrated in 0.18 um five-level Al-metrallization technology. Quadratic voltage coefficients of capacitance less than 60 ppm/V2 with capacitance density greater than 3 fF/um2 can be achieved using 400{degree sign}C deposition. TDDB lifetime of MIM capacitor with a capacitance of 4 nF is well above 10 years at 3.3 V.
ALD La-Based Oxides for Vt-Tuning in High-K/Metal Gate Stacks
Authors: Swerts Johan , Fedorenko Yanina , Maes Jan Willem , Tois Eva , Delabie Annelies , Ragnarsson Lars-Aåke , Yu HongYu , Nyns Laura , Adelmann Christoph , Van Elshocht Sven
Published: September 2007

Accurate thickness and composition control for ultra-thin films is demonstrated for the atomic layer deposition (ALD) of La2O3 and HfLaO. Growth studies indicate a linear growth without substrate inhibition for La2O3 and HfLaO ALD on HfSiO and hydroxylated SiO2, respectively. Layer closure studies on HfSiO show a fast La2O3 layer closure. Vt-tuning in a high thermal budget NMOS transistor flow is established (i) by inserting sub-nm La2O3 capping layers between the HfSiON gate oxide and the TaCx metal electrode and (ii) by replacing the HfSiON gate oxide film by HfLaO. Changing the La2O3 capping layer thickness from 0 till 1 nm, results in tunable Vt-shifts up to ~ 600mV while retaining low equivalent oxide thickness (EOT), high mobility, and low gate leakage current. Hf-rich HfLaO gate dielectric layers resulted in a Vt-shift of ~ 250 mV and EOT values down to 1.1 nm.
Effect of Nitridation for High-K Layers by ALCVDTM in Order to Decrease the Trapping in Non Volatile Memories
Authors: Grampeix Helen , Colonna Jean-Philippe , Molas Gabriel , Bocquet Marc , Martin François , Rochat Névine , Martinez Eugénie , Licitra Christophe , Veyron Thomas , Papon Anne-Marie , Gely Marc , Yckache Karim
Published: September 2007

In non-volatile memories, high-k materials such as Al2O3, HfO2, and hafnium aluminates are good candidates as interpoly layers. In order to decrease the parasitic trapping of the interpoly stack, the effect of post deposition nitridation (PDN) on different high-κ films was investigated. Several characterizations were performed on those films such as Angle Resolved X-ray Photo-electron Spectroscopy (AR-XPS), Auger Electron Spectroscopy (AES), Attenuated Total Reflection - Fourier Transform Infrared spectroscopy (ATR-FTIR) and Vacuum UltraViolet Spectroscopy Ellipsometry (VUV-SE). A correlation between the nitrogen incorporation and the crystallization was demonstrated. Al-rich films remain amorphous after PDN, with an incorporation of nitrogen in the film volume. Meanwhile, Hf-rich films crystallized after PDN, with nitrogen incorporated only at the high-κ / Si substrate interface. Also nitrogen increases the crystallization temperature onset, which leads to a reduction of charge trapping after high temperature spike anneals. Nitrided amorphous hafnium aluminate films are good candidates as interpoly layer.
Low Temperature Deposition of Ge Thin Films for Phase Change Memory
Authors: Chen Tianniu , Xu Chongying , Hunks William , Stender Matthias , Stauf Gregory T. , Chen Philip S. , Roeder Jeffery F.
Published: September 2007

The deposition of Ge-Sb-Te (GST) chalcogenide alloys in high aspect-ratio trench structures via CVD and ALD-like processes has attracted great attention for their application in next generation non-volatile Phase Change Random Access Memory (PRAM) devices. Several Ge (II) silylamido precursors were synthesized and characterized, and their behaviors in thermal CVD processes explored. Of these, a novel Ge precursor - bis (2,2,5,5-tetramethyl-2,5-disila-1-azacyclopentanide) germanium (II) was found to give a deposition rate of 1 Aå/min at 320 ºC by using NH3 as a co-reactant gas. Deposition rates below 0.1 Aå/min at these temperatures were obtained in the presence of H2 or an inert gas, which means this precursor exhibits the co-reactant limited deposition which is desirable for good step-coverage and uniform film growth in ALD. Data will be presented on deposition rates vs. temperature using this precursor and compared with two other bis(silylamido) germanium precursors. Preliminary results on the deposition of GeTe binary films will also be presented.
Characteristics of High Power Laser Shock Waves and Their Cleaning Performance
Authors: Kim Tae-Gon , Yoo Young-Sam , Son Il-Ryong , Jang Deoksuk , Kim Dongsik , Lee Jong-Myung , Choi Jae-Sung , Busnaina Ahmed A. , Park Jin-Goo
Published: September 2007

Plasma shock waves induced by focusing a Q-switched Nd:YAG laser at a maximum energy of 1.8 J in air were characterized by a laser beam deflection method and applied to the particle removal. The dimension of plasma plume and velocities of shock waves were measured as a function of laser energy and gap distance. The shock wave velocity decayed rapidly as the gap distance increased. The laser shock wave cleaned area followed the shape of shock waves, which was heart-shaped. The shorter gap distance, the higher particle removal efficiency (PRE) was observed. PRE of 98% was achieved by optimizing the laser energy, gap distance, and wafer scanning procedure.
Damage Clustering and Damage-Size Distributions After Megasonic Cleaning
Authors: De Marco Cinzia , Wostyn Kurt L. , Bearda Twan , Sano Ken-Ichi , Kenis Karine , Janssens Tom , Leunissen Leonardus H.A. , Eitoku Atsuro , Mertens P.
Published: September 2007

In this work the damage added on gate stack features after batch megasonic cleaning is identified and classified by SEM review. To understand if damaging is a random or a clustered process, damage clustering distributions are compared with a theoretical random distribution of damage sites. In the damaged areas, defect clusters are observed that we explain by the presence of so-called weak spots in the neighborhood of a damaging event. Only a limited influence of the megasonic cleaning settings was found on the damage-size distributions. This suggests that, for the cleaning conditions investigated in this work, the number of added defects varied with the amount of the damage events but the event strength remains the same.
Impact of Metallic Contamination on Si: Shortloop Issues
Authors: Borde Yannick , Maurel Adrien , Danel Adrien , Roche Agnes , Veillerot Marc
Published: September 2007

Advanced Integrated Circuit (IC) manufacturing faces both the development of many products and the introduction of a large number of new materials, which represent possible risk of contamination. Therefore, the estimation of the dangerousness of metallic elements must be estimated by relevant short loops. The process steps used in the short loop should represent the production reality or should be performed in the most detrimental conditions. This study shows the impact of different short loop parameters on the dangerousness of metallic elements and their behaviour toward Si and SiO2: type of contamination (depending on the deposition method), thermal budget, oxidizing and non oxidizing atmosphere of the intra-diffusion step, metrology technics. This paper shows that the usual short loops fulfil the conditions of a relevant test. Accordingly, estimation of the dangerousness of the metallic elements can be used to determine detrimental thresholds in manufacturing areas.
Plasma-Less Photoresist Stripping
Authors: Takahashi Hiroaki
Published: September 2007

In this paper, a novel technology for stripping implanted resists that uses wafer baking, followed by a combination of high temperature SPM (sulfuric acid / hydrogen peroxide mixture) and ultrasonics through H2SO4 will be proposed. We found that plasma-less stripping of highly dosed (1E16) resist is possible without damage in a short time, by making optimum reactive combinations of thermal decomposition and oxidation of resist (by baking and high temperature SPM), and then by removing residue using H2SO4 and ultrasonic waves.
Wet Resist Strip Capability vs. Implant Energy
Authors: Christenson Kurt K.
Published: September 2007

Implant doses greater than 5E14 atoms/cm2 can create an amorphous carbon like damage layer (crust) that is difficult to dissolve with wet chemistries. During the wet strip, the undamaged and lightly-damaged resist is dissolved quickly, undercutting and releasing most of the crust. The portions of crust that contact the silicon, however, cannot be undercut, and must be dissolved. The most extensive and difficult to dissolve regions of crust typically occur near the edge-bead-removal (EBR) region. This work uses the SRIM (Stopping Range of Ions in Matter) computer simulation to investigate the characteristics of the crust for a range of implant conditions including dose, energy and implant species. Techniques to prevent the formation of attached crust near the edge bead region are also discussed.
Single Wafer Tool Cleaning for Bi-layer Photoresist Rework - Stripper Development and Evaluation
Authors: Wu Aiping , Baryschpolec Eugene , Molnar Les , Henry Sally-Ann , Detterbeck Stefan , Brilz Ladislaus , Bartsch Christin , Sulzer Georg , Ott Andreas
Published: September 2007

A wet-cleaning solution for bi-layer photoresist rework using single-wafer tool process has been developed and proved to be successful. The chemical design of stripper related to cleaning mechanism was investigated. The cleaning performance of two types of strippers were evaluated and compared between beaker and single-wafer tool process. The results indicated that chemical design of stripper is the key to determine cleaning mechanism for bi-layer photoresist. It is demonstrated that removal of bi-layer photoresist through lift-off is not acceptable in single-wafer tool process; dissolution proved to be the key mechanism for successful removal of bi-layer photoresist in a single wafer tool. For single-wafer tool evaluation, the influence of process parameters such as wafer spin speed, process time, medium temperature and chemical dispense characteristics were evaluated and are discussed.
A Review of Microelectronic Manufacturing Applications Using DMSO-Based Chemistries
Authors: Kvakovszky George , McKim Artie , Moore John C.
Published: September 2007

Dimethyl Sulfoxide (DMSO) is a proven solvent used in microelectronic manufacturing. These processes include resist stripping applications in lithography. DMSO exhibits a unique high polarity as defined by a high dielectric constant which aids in its dissolution character for both polymers and inorganic salts. This polarity allows formulating with additives that aid in stripping polymers processed with inorganic species. DMSO is stable with limited hydrolysis when exposed to aggressive reagents. These qualities help to support challenging cleans applications where cured polymers are stripped from sensitive metal features such as gate-level high-dose implanted resist and in solder bumping. The safety classification of DMSO as non-regulated is in accordance with the US EPA and the European Union, a condition that is consistent with the needs of the ITRS challenge for next generation products used in the fab.
Advanced Surface Preparation Development on a 300 mm Single Wafer Spin-on Platform
Authors: Briend Guillaume , Besson P. , Salvetat Thierry , Pollet Olivier
Published: September 2007

Focus has been made on the so-called "Leti BKM-Clean" advanced surface preparation, developed on a 300 mm single wafer spin-on platform. Based on the "Dilute Dynamic Clean" (DDC) knowledge [1], dilute HF/HCl and O3/HCl chemistries have been investigated here in combined spin-on and immersion mode. Depending on the specific FEOL cleaning step requirements, the HF/HCl step can be tuned in order to precisely control the partial or total silicon surface de-oxidation as for pre-gate cleanings which require a controlled chemical oxide re-growth. In this last case, the Leti BKM-Clean presents good particle performance up to 65 nm particles size, good particle and metallic removal efficiency without any feature damage generation on high-K /TiN/poly-Si lines structures with an aspect ratio lower than 4.
Challenges in Sub-Micron Contact Hole Cleaning
Authors: Goh Felicia , Tjoa Tjin Tjin , Yeo Kwee Liang , Ismail Zainab
Published: September 2007

High aspect ratio (HAR) of contact holes in 65nm CMOS device technology impose significant challenges in post etch wet cleaning. IPA surface tension gradient (STG) drying of HAR holes was compromised at half pitch processing during post etch SC1 clean, resulting in polymeric residues. The source of the residues was determined to be polymers generated from nitride etch during contact RIE. SC1 reaction by-products of these polymers with IPA during drying resulted in the formation of CFx residues. Drying parameters played an important role in determining defectivity performance after SC1 post etch clean. Experiments have determined that a slow wafer lift up speed to provide higher STG would effectively remove soluble SC1 by-products that might be trapped within the contact holes. With the careful optimization of drying parameters, polymeric residues after post etch clean could be prevented.
The Impact of Drying Methods on Defect Generation in Deep Trench Processing
Authors: Goessens Claus , Martens Nick , Baele Joris , De Backer Eddy , De Pestel Freddy , Engle Mike
Published: September 2007

During failure analysis on high voltage I3T50 products, it was found that irregular Nsinker regions were present in the top region of the wafer. This Nsinker distortion, also called POCl3 deformation, was shown during failure analysis to be linked to certain binnings within the yield loss. A decoration technique has been developed to detect POCl3 deformations inline with KLA, and it is shown that drying marks in trenches in the Deep Trench Isolation (DTI) module are the root cause of POCl3 deformation. An improved drying technique has been put in place, thus preventing the defects observed.
Zero Defectivity Dual Gate Processing
Authors: Towner Janet M. , Naughton John J. , Lappan Raymond
Published: September 2007

A mixed-signal automotive device manufactured in a dual gate process historically had sporadic yields. Problems were associated with analog failures, including the temperature sense circuit, load dump trip levels, comparators and the 8MHz oscillator. These issues related to p-mos devices with common mode inputs <1.5V. The only anomaly observed at electrical test was in the threshold voltage matching of a particular size of transistor pairs. When 100% testing of these scribe line monitors was performed there were many random failures, with higher probability around the perimeter of the wafer. The magnitude of the offset was consistent with a 2nm difference in gate oxide thickness. Darkfield inspection following etchback of oxide from standard gate regions showed water spotting and damage to active areas. No defects were observed following the introduction of a 10sec oxygen plasma treatment prior to oxide etchback. This change coincided with improved yields and the elimination of the analog failures.
Interactions of Sapphire Surfaces with Standard Cleaning Solutions
Authors: Kirby Kevin W. , Shanmugasundaram Karthik , Bojan V , Ruzyllo J.
Published: September 2007

In this study, the effects of selected standard surface cleaning processes on sapphire surfaces were investigated. Wet chemistries commonly used in Si cleaning including HPM, APM and dilute HF were studied along with alumina etching H3PO4. The cleaned substrates were characterized by means of wetting angle measurements, AFM, and XPS analyses. The preliminary results presented in this report indicate that all chemistries studied were altering morphology of sapphire surface. The HPM and APM mixtures were found to smoothen the surface while the effect of acidic etchants, HF and H3PO4 was adverse and beneficial respectively. The XPS analysis indicated that within the range of elements monitored none of the above chemistries altered chemical composition of the sapphire surface in a meaningful manner.
Electrochemical Behavior of Copper in Post-Via-Etch Cleaning Solutions
Authors: Bilouk Sabrina , Pernel Carole , Nogueira Ricardo P. , Broussous Lucile , Haumesser Paul-Henri , Passemard Gerard
Published: September 2007

The actions of glycolic acid and BTA on copper have been investigated by electrochemical methods. Different concentrations in glycolic acid were investigated: 1%wt, 2%wt, 3%wt and 4%wt. Results show that the cleaning action of glycolic acid results from smooth corrosion of the metal. Copper dissolution increases with glycolic acid concentration due to the formation of a copper complex which precedes copper dissolution. In the presence of BTA, a corrosion inhibitor of copper, a [Cu(I)BTA] complex is formed on the surface which blocks copper dissolution. In a mixture of glycolic acid and BTA (1%wt/ 0.1%wt), an intermediary behavior is observed. A competitive action occurs between the film formation due to the interaction between BTA and copper and the superficial etching of the metal by glycolic acid which removes the inhibitor-copper film.
Incorporation of Cu Passivators in Post-CMP Cleaners
Authors: Peters Darryl W.
Published: September 2007

Simple first generation Cu post-CMP cleaners, such as oxalic acid solutions, promote corrosion of Cu due to removal of BTA and dissolution of cuperous oxide (Cu2O). The use of simple organic acid solutions imposed a short staging time before processing wafers to the next level due to corrosion of the exposed Cu. In some cases, a maximum holding time of less than one hour was needed to reduce device yield loss and reliability issues resulting from Cu corrsion. A way to significantly increase the post-clean wafer holding time was by incorporating a Cu passivator into the post-CMP cleaner. Four commonly used Cu passivators were evaluated in a commercially available, alkaline, post-CMP cleaner. Several unanticipated properties were observed when using 1,2,4-triazole, which will be discussed.
Particle Adhesion to Photomask Substrates
Authors: Jaiswal Ravi , Kilroy Caitlin , Kumar Gautam , Banerjee Souvik , Beaudoin Stephen
Published: September 2007

This manuscript describes a combined experimental and theoretical study of the adhesion of representative particles to mask materials. Particles as large as 10 microns were studied, and AFM cantilevers as small as 30 nm (radius of curvature of tip) were used to represent nanoscale particles. Adhesion forces were measured and modeled in air and in DI water. Based on the validated adhesion model, particle adhesion forces were predicted for spheroidal particles with varying degrees of roughness interacting with photomask substrates.
Removal of Gold Particles from Chromium Oxynitride Surface with Dilute Sulfuric Acid Solutions
Authors: Pandit Viraj S. , Keswani Manish , Raghavan Srini , Muralidharan Krishna , Deymier Pierre , Eshbach Florence , Sengupta Archita , Yun Henry
Published: September 2007

Removal of gold particles (100 nm) from chromium oxynitride surface (CrON) has been investigated using dilute sulfuric acid solutions. Two types of gold nano-particles, one with a negative surface charge and the other with a positive charge achieved by adsorption of poly diallyl-dimethyl ammonium chloride (PDAC), were used. Particle removal efficiency (PRE) increases with sulfuric acid concentration and bath temperature. In 1:10 H2SO4:DI solution, increasing the bath temperature from 25 to 100 {degree sign}C increases the PRE from 21 to 99 %. Introduction of megasonic energy at 0.43 W/cm2 in a 1:10 H2SO4:DI bath at 35 {degree sign}C increases the PRE to 88 %. PDAC coated gold particles are difficult to remove as compared to uncoated particles due to their electrostatic interaction with the surface leading to stronger adhesion.
The Approach for Direct Stacking of High-k Dielectrics on Si
Authors: Nagasato Yoshitaka , Iwazaki Yoshitaka , Hasumi Masahiko , Ueno Tomo , Kuroiwa Koichi
Published: September 2007

We present the approach for direct stacking of high-k dielectrics on Si. For the reduction of equivalent oxide thickness (EOT), the fabrication method of high-k/Si structure in which interfacial SiO2 layer scarcely formed was proposed. In this method, high-k films were fabricated by ultrahigh vacuum sputtering of metal thin films followed by post-oxidation. For the oxidation of metal films such as Hf, Zr or Al, using plasma oxidation methods at the low-temperature improves the electrical properties of high-k/Si. HfO2/Si structures fabricated by plasma oxidation in the Kr/O2 mixed ambient had the calculated k-value of 25.1 with the thickness of interfacial layer of 0.2nm. Furthermore, because the mutual diffusion at the interface was suppressed, interface quality was improved by low-temperature oxidation. In this study, using a suitable oxidation method and condition for each metal leads to the fabrication of an ideal stacking structure of high-k dielectrics on Si.
Oxygen Species in HfO2 Films: An in Situ X-Ray Photoelectron Spectroscopy Study
Authors: Driemeier Carlos , Wallace Robert , Baumvol Israel
Published: September 2007

The chemical bonding of O atoms in HfO2 films on Si was investigated by in situ x-ray photoelectron spectroscopy in the O1s spectral region. In addition to trivial O forming only O-Hf bonds, O1s signals corresponding to nontrivial secondary O (Osec) were also observed and angle-resolved photoelectron analysis was employed to quantitatively separate surface and bulk Osec contributions. Surface Osec was assigned to surface O-H groups generated either by room temperature water vapor exposure or by 600oC H2 annealing. Bulk Osec was assigned to O-O or O-H bonds located in HfO2 amorphous regions and grain boundaries. For some of the processing routes employed here, we observed additional, water-induced bulk Osec, which was attributed to dissociative water absorption in HfO2 amorphous regions and O-depleted grain boundaries.
Interface Reaction of High-k Gate Stack Structures Observed by High-Resolution RBS
Authors: Zhao Ming , Nakajima Kaoru , Suzuki Motofumi , Kimura Kenji , Uematsu Masashi , Torii Kazuyoshi , Kamiyama Satoshi , Nara Yasuo , Watanabe Heiji , Shiraishi Kenji , Chikyow Toyohiro , Yamada Keisaku
Published: September 2007

HfO2/SiO2/Si(001) structures were annealed in dry oxygen, and compositional depth profiles were measured by high-resolution Rutherford backscattering spectroscopy (HRBS). Growth of the interfacial SiO2 layer and simultaneous surface accumulation of Si were observed. The observed result indicates that silicon species are emitted from the SiO2/Si interface to release the stress induced by oxidation as was predicted by theoretical studies. The behavior of oxygen during the annealing was also observed using 18O as a tracer. The observed 18O profile suggests that oxygen molecules are decomposed into atomic oxygen in HfO2 and diffuse through the oxide layer via exchange mechanism. This is also supported by the observed activation energy of ~ 0.6 eV for the growth of the interfacial SiO2 layer.
Workfunction (WF) Simulations of Ta/HfO2, Ta2C/HfO2 and Ta2C/La2O3/HfO2 Capped High-k Stacks
Authors: Van der Heyden Nikolaas , Pourtois Geoffrey , De Gendt Stefan , Heyns Marc , Stesmans Andre
Published: September 2007

The electronic properties of tantalum based metal gates in contact with HfO2 are investigated through first-principles calculations. The (110) Ta surface has a p-type work function and is most likely to be formed at the interface with the dielectric. The influence of the transistor processing conditions is modeled by incorporating oxygen atoms in between the metal and the dielectric. Oxidizing the metal gate leads to an increase of the metal work function. To acquire either pMOS or nMOS work function values, the effective work function of the Ta (110)/HfO2 stack can be tuned by incorporating carbon or by inserting dielectric capping layers. The alloy of tantalum with carbon atoms reduces the metal work function which is also reported experimentally. Sandwiching a La2O3 capping layer between the gate and the dielectric leads to a work function reduction. These work function shifts are interpreted on the basis of the electronic density distribution at the interfacial region.
Improvement in Fermi-Level Pinning of p-MOS Metal Gate Electrodes on HfSiON by Employing Ru Gate Electrodes
Authors: Kadoshima Masaru , Sugita Yoshihiro , Shiraishi Kenji , Watanabe Heiji , Ohta Akio , Miyazaki Seiichi , Nakajima Kiyomi , Chikyow Toyohiro , Yamada Keisaku , Aminaka Toshio , Kurosawa Etsuo , Matsuki Takeo , Aoyama Takayuki , Nara Yasuo , Ohji Yuxuru
Published: September 2007

Methods of improving Fermi-level pinning of pure metal gate electrodes on Hf-based high-k dielectrics have been investigated. The pinning phenomenon is a crucial problem, resulting in an unintentional threshold voltage increase in p-MOSFETs when applying pure metal gate electrodes such as Ru and TiN in Hf-based high-k CMOS. After systematic investigation of the relation between oxygen vacancies in Hf-based high-k dielectrics and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. It is necessary to modulate the stable pinning energy position of Hf-based high-k dielectrics in p-MOSFETs in order to obtain thin EOTs in the gate-first process.