bluuebunny/crossref_metadata_2025 huggingface dataset:
Microstructural Analysis of Damaged Layer Introduced during Chemo-Mechanical Polishing
Authors: Sako Hideki , Yamashita Tamotsu , Tamura Kentaro , Sasaki Masayuki , Nagaya Masatake , Kido Takanori , Kawata Kenji , Kato Tomohisa , Kojima Kazutoshi , Tsukimoto Susumu , Matsuhata Hirofumi , Kitabatake Makoto
Published: February 2014

Damaged layers, which are introduced during chemo-mechanical polishing (CMP) underneath the 4°off-cut 4H-SiC wafer surface and cause surface defects formations after epitaxial films growth, are investigated by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). SEM observations show presence of small scratches on wafer surfaces after CMP process. The widths of such scratches are submicron meters, thus it is hard to detect them by optical microscopy. TEM observations show that high-density regions of dislocation loops exist below scratches and the widths of such dislocation loops are much wider than the morphological width. Details of the dislocation structure are also analyzed. It is shown that the high-density dislocation loops cause local surface roughening on the surface of the epitaxial film.
Nanomechanical Analysis of Triangular Defect in 4H-SiC Epilayer
Authors: Shin Yun Ji , Kim Soo In , Jung Hyeon Jin , Lee Chang Woo , Bahng Wook
Published: February 2014

We report an investigation of the formation of triangular defects (TDs) in 4H–SiC expitaxial layers using Kelvin probe force microscopy (KPFM) and a nano-indenter. The results provide valuable information on the crystallographic structure, including the polytype nature of the TDs and surface potential profile. The TDs were also characterized using micro-Raman spectroscopy and high-resolution transmission electron microscopy. We found that the TDs were composed of a thick 3C-SiC band, as well as stacking faults (SFs) in the 4H-SiC epilayer.
Analysis on Generation of Localized Step-Bunchings on 4H-SiC(0001)Si Face by Synchrotron X-Ray Topography
Authors: Sasaki Masayuki , Tamura Kentaro , Sako Hideki , Kitabatake Makoto , Kojima Kazutoshi , Matsuhata Hirohumi
Published: February 2014

Surface roughening regions running like scratches are often observed locally after epitaxy film grown on a very flat 4H-SiC wafer surfaces. We investigated generation mechanism of such roughening surface by using X-ray topography and confocal optical microscopy. We found that lattice defects were often introduced during CMP at local regions, and those local regions cannot be recognized by optical microscopy, since very flat surface can be observed. By H2 etching which is preprocess of epitaxy film growth, those lattice defects are almost etched off, but local rough surface consists of pits and step bunching regions appear like scratches, and those local pits and surface roughening regions grew up to step bunching during epitaxy film growth.
Non Destructive Inspection of Dislocations in SiC Wafer by Mirror Projection Electron Microscopy
Authors: Isshiki Toshiyuki , Hasegawa Masaki
Published: February 2014

A mirror electron microscopy (MPJ) was developed for defect inspection in silicon carbide (SiC) wafer as non destructive, high spatial resolution and high throughput method. Each of three type dislocations, threading screw dislocation (TSD), threading edge dislocation (TED) and basal plane dislocations (BPD) in 4H-SiC wafer were identified in MPJ image as a dark dot with different type of tailing. This new method provides high performance inspection of defects in SiC possible without specimen pre-treatment.
Deep-Level Transient Spectroscopy Characterization of Interface States in SiO2/4H-SiC Structures Close to the Conduction Band Edge
Authors: Hatakeyama Tetsuo , Sometani Mitsuru , Fukuda Kenji , Okumura Hajime , Kimoto Tsunenobu
Published: February 2014

Constant-capacitance deep-level transient spectroscopy was carried out to characterize in detail interface states close to the conduction band edge in SiO2/SiC structures. The measured results are summarized as follows: (1) The capture of electrons by the interface states proceeds logarithmically with time. (2) The emission of electrons accelerates slightly with increasing density of captured electrons. The oxide trap model explains the logarithmic change in capture with time but not the phenomenon of accelerated emissions. This prompted us to formulate a new model that replicates the logarithmic capture process with time. In this model, we postulated the electron density at the interface decreases exponentially as the trapped electron density increases owing to the interaction between the trapped electrons and the free electrons. In this case, the capture process is almost the same as with the oxide trap model except for the definition of parameters. Further, we do not need to take into account the delay of the emission process caused by tunneling. The phenomenon of accelerated emissions may be explained by interactions among captured electrons in this model.
Reciprocal Space Mapping Studies of the Initial Stage of the PVT Growth of 4H-SiC Crystals Parallel and Perpendicular to the c-Axis
Authors: Ohshige Chikashi , Takahashi Tatsuya , Ohtani Noboru , Katsuno Masakazu , Fujimoto Tatsuo , Sato Shinya , Tsuge Hiroshi , Yano Takayuki , Matsuhata Hirofumi , Kitabatake Makoto
Published: February 2014

Defect formation during the initial stage of physical vapor transport (PVT) growth in the [000-1] and [11-20] directions has been investigated by x-ray reciprocal space mapping (RSM) and defect-selective etching. RSM studies showed that, while the crystal grown in the [000-1] direction did not show a significant degradation of the crystalline quality during the initial stage of growth, the growth in the [11-20] direction resulted in misoriented subgrain structure near the grown crystal/seed interface. The cause of the domain formation is assumed to be the difference in nitrogen concentration between the seed and the grown crystal, and the results indicate that the growth in the [11-20] direction is greatly affected by the nitrogen doping difference.
Drain-Current Deep Level Transient Spectroscopy Investigation on Epitaxial Graphene/6H-SiC Field Effect Transistors
Authors: Roensch Sebastian , Hertel Stefan , Reshanov Sergey A. , Schöner Adolf , Krieger M. , Weber Heiko B.
Published: February 2014

The electrically active deep levels in a graphene / silicon carbide field effect transistor (FET) were investigated by drain-current deep level transient spectroscopy (ID-DLTS). An evaluation procedure for ID-DLTS is developed in order to obtain the activation energy, the capture cross section and the trap concentration. We observed three defect centers corresponding to the intrinsic defects E1/E2, Ei and Z1/Z2 in n-type 6H-SiC. The determined parameters have been verified by conventional capacitance DLTS.
High-Resolution Raman and Luminescence Spectroscopy of Isotope-Pure 28Si12C, Natural and 13C – Enriched 4H-SiC
Authors: Ivanov Ivan G. , Yazdanfar Milan , Lundqvist Bjorn , Chen J.T. , Hassan Jawad , Stenberg Pontus , Liljedahl Rickard , Son Nguyen Tien , Ager Joel W. , Kordina Olle , Janzén Erik
Published: February 2014

The optical properties of isotope-pure 28Si12C, natural SiC and enriched with 13C isotope samples of the 4H polytype are studied by means of Raman and photoluminescence spectroscopies. The phonon energies of the Raman active phonons at the Γ point and the phonons at the M point of the Brillouin zone are experimentally determined. The excitonic bandgaps of the samples are accurately derived using tunable laser excitation and the phonon energies obtained from the photoluminescence spectra. Qualitative comparison with previously reported results on isotope-manipulated Si is presented.
Carrier Density Dependence of Fano Type Interference in Raman Spectra of p-type 4H-SiC
Authors: Mitani Takeshi , Nakashima Shinichi , Tomobe Masaru , Ji Shi Yang , Kojima Kazutoshi , Okumura Hajime
Published: February 2014

We have investigated Raman spectra of p-type 4H-SiC crystals with hole concentration ranging from 3×1016 to 1×1021 cm-3. For folded transverse acoustic (FTA) doublet modes, Fano interference profiles were analyzed, and the frequency shift due to Fano interference was obtained as a function of hole concentration. We demonstrated that the shift of the FTA doublet modes is a quantitative measure for evaluating of hole concentration of p-type 4H-SiC. Spectral features of transverse optical (TO) and longitudinal optical phonon-plasmon coupled (LOPC) modes were also studied for various carrier concentrations. The results show that the full width at half maximum of the LOPC and relative intensity of TO and the LOPC can be used as other calibration measures for hole concentration.
Hall Factor Calculation for the Characterization of Transport Properties in N-Channel 4H-SiC MOSFETs
Authors: Uhnevionak Viktoryia , Burenkov Alex , Strenger Christian , Mortet Vincent , Bedel-Pereira Elena , Cristiano Fuccio , Bauer Anton J. , Pichler Peter
Published: February 2014

For the characterization of n-channel 4H-SiC MOSFETs, current-voltage and Hall-effect measurements were carried out at room temperature. To interpret the Hall-effect measurements, the Hall factor for the electron transport in the channel of SiC MOSFETs was evaluated, for the first time. The method of the Hall factor calculation is based on the interdependence with mobility components via the respective scattering relaxation times. The results of the calculation reveal a strong dependence of the Hall factor on the gate voltage. Depending on the gate voltage applied, the values of the Hall factor vary between 1.3 and 1.5. Sheet carrier density and drift mobility values derived from the Hall-effect measurements using our new gate-voltage-dependent Hall factor show very good agreement with simulations performed with Sentaurus Device of Synopsys.
High-Sensitivity High-Resolution Full-Wafer Imaging of the Properties of Large n-Type SiC Using the Relative Reflectance of Two Terahertz Waves
Authors: Hamano Akihide , Ohno Seigo , Minamide Hiroaki , Ito Hiromasa , Usuki Yoshiyuki
Published: February 2014

THz imaging was performed in 2 s intervals with 1 mm resolution on a 3 in., 0.42 mm thick, as-cut n-type Silicon Carbide wafer. Carrier density, relaxation time, mobility, and resistivity obtained from imaging results are 0.91 × 1018 cm-3, 4.36 × 10-14 s, 218 cm2V-1s-1, and 3.14 × 10-2 Ωcm, respectively. Compared with the standard values provided by the manufacturers, the results suggest that THz imaging has reliable precision and accuracy.
Characterization of LaxHfyO Gate Dielectrics in 4H-SiC MOS Capacitor
Authors: Xia Jing Hua , Martin David M. , Suvanam Sethu Saveda , Zetterling Carl Mikael , Östling Mikael
Published: February 2014

LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.
Si Emission into the Oxide Layer during Oxidation of Silicon Carbide
Authors: Hijikata Yasuto , Akasaka Yurie , Yagi Shuhei , Yaguchi Hiroyuki
Published: February 2014

To verify the Si emission phenomenon during oxidation of SiC, the behavior of Si atoms was investigated using HfO2/SiC structures. At low oxygen pressure, i.e. the oxidation condition predominant to active oxidation, Si emission into oxide layer and the growth of SiO2 on the oxide surface were clearly observed by TOF-SIMS. On the other hand, the growth of SiO2 on the surface was suppressed under an ordinary pressure. These results evidence the Si emission during oxidation that is proposed in the Si and C emission model.
Nano-Scale Native Oxide on 6H-SiC Surface and its Effect on the Ni/Native Oxide/SiC Interface Band Bending
Authors: Huang Wei , Liu Xi , Liu Xue Chao , Zhou Tian Yu , Zhuo Shi Yi , Zheng Yan Qing , Yang Jian Hua , Shi Er Wei
Published: February 2014

Native oxide layer with thickness of about 1 nm was found easy to form on 6H-SiC surface during transporting from cleaning process to vacuum chambers, which was examined by x-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM). The interface band bending was studied by synchrotron radiation photoelectron spectroscopy (SRPES). For the native-oxide/SiC surface, after Ni deposition, the binding energy of Si 2p red-shifted about 0.34 eV, which suggested the upward bending of the interface energy band. Therefore, the native oxide layer should be considered on the study of SiC devices because it may affect the electron transport properties significantly.
Systematic Analysis of the High- and Low-Field Channel Mobility in Lateral 4H-SiC MOSFETs
Authors: Strenger Christian , Uhnevionak Viktoryia , Mortet Vincent , Ortiz Guillermo , Erlbacher Tobias , Burenkov Alexander , Bauer Anton J. , Cristiano Fuccio , Bedel-Pereira Eléna , Pichler Peter , Ryssel Heiner , Frey Lothar
Published: February 2014

In this work, we investigate the impact of Al-implantation into n-MOSFET channel regions together with its p-doping concentration upon the mobility limiting scattering mechanisms in the channel. For this purpose, a study of the interface trap density, interface trapped charge density, field-effect mobility, and Hall mobility is carried out for normally-off n-MOSFETs with different doping profiles and concentrations in the channel region. The trend of the field-effect and the Hall mobility as well as the differences thereof will be discussed. Based on the determined mobilities in the range from 11.9 cm2/Vs to 92.4 cm2/Vs, it will be shown that for p-doping concentrations above 5·1016 cm-3 Coulomb scattering is the dominant scattering mechanism for both, low- and high-field mobility. In contrast, for p-doping concentrations below 5·1016, cm-3 further scattering mechanisms will be considered that may account for the observed mobility trend at high electric fields.
Rapid Thermal Oxidation of Si-Face N and P-Type On-Axis 4H-SiC
Authors: Florentin Matthieu , Montserrat Josep , Brosselard Pierre , Henry Anne , Godignon Philippe
Published: February 2014

This paper deals with the comparison of several MOS structures with different rapid thermal oxidation processes (RTO) carried out on Off and On-axis SiC material. A first set contains MOS capacitance structures on n-epitaxial layers, while a second set of MOS capacitance are built on p-implanted layers. Both sets include On and Off-Axis angle cuts. Furthermore, n-MOSFETs have been fabricated on On-axis p-implanted layers with the best oxidation process selected from the MOS capacitance study. The final objective is to show the performances of these On-axis p-implanted n-MOSFETs and to evidence the associated lower surface roughness at the SiO2/SiC interface.
Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures
Authors: Banzhaf Christian T. , Grieb Michael , Trautmann Achim , Bauer Anton J. , Frey Lothar
Published: February 2014

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.
4H-SiC MOS Capacitors and MOSFET Fabrication with Gate Oxidation at 1400°C
Authors: Naik Harsh , Chow T. Paul
Published: February 2014

This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.
Nitridation Effects of Gate Oxide on Channel Properties of SiC Trench MOSFETs
Authors: Ariyoshi Keiko , Harada Shinsuke , Senzaki Junji , Kojima Takahito , Kojima Kazutoshi , Tanaka Yasunori , Shinohe Takashi
Published: February 2014

We have studied gate oxide processes for SiC trench MOSFETs. It is demonstrated that nitridation of gate oxide is effective to suppress the variation of channel mobility depending on channel plane orientation and substrate off-angles. In addition, improved channel mobility has been obtained by the combined process of NH3 and N2O POA.
Analysis of C-Face 4H-SiC MOS Capacitors with ZrO2 Gate Dielectric
Authors: Chan Le Shan , Chang Yu Hao , Lee Kung Yen
Published: February 2014

ZrO2 films were deposited on C-face 4H-SiC substrates by using an RF sputter at a temperature of 200°C. Then, ZrO2 films were treated with RTA (rapid thermal annealing) process in Argon (Ar) ambient at 600°C, 700°C and 800°C for 4 minutes, respectively. The samples with RTA process show the lower leakage currents. As the measure temperature increases from room temperature (RT) to 150°C, the dielectric breakdown voltage reduces from 3 V to 1 V. The difference between quasi C-V characteristics and high frequency C-V characteristics at 1 MHz becomes larger with increasing RTA temperature. The C-V curves also shift to the left side as the measure temperature increases from RT to 150°C. It also shows the ledge on the C-V curves of samples with RTA at elevated measure temperature.
Comparative Study of the Current Transport Mechanisms in Ni2Si Ohmic Contacts on n- and p-Type Implanted 4H-SiC
Authors: Vivona Marilena , Greco Giuseppe , Di Franco Salvatore , Giannazzo Filippo , Roccaforte Fabrizio , Frazzetto Alessia M. , Rascunà Simone , Zanetti Edoardo , Guarnera Alfio , Saggio Mario
Published: February 2014

The knowledge of the temperature behavior of Ohmic contacts is an important issue to understand the device operation. This work reports an electrical characterization as a function of the temperature carried out on nickel silicide (Ni2Si) Ohmic contacts, used both for n-type and p-type implanted 4H-SiC layers. The temperature dependence of the specific contact resistance suggested that a thermionic field emission mechanism dominates the current transport for contacts on p-type material, whereas a current transport by tunneling is likely occurring in the contacts on n-type implanted SiC. Furthermore, from the temperature dependence of the electrical characteristics, the activation energies for Al and P dopants were determined, resulting of 145 meV and 35 meV, respectively. The thermal stability of the electrical parameters has been demonstrated upon a long-term (up to ~100 hours) cycling in the temperature range 200-400°C.
Ti/Al/Si Ohmic Contacts for both n-Type and p-Type 4H-SiC
Authors: Tamaso Hideto , Yamada Shunsuke , Kitabayashi Hiroyuki , Horii Taku
Published: February 2014

An ohmic contact process by using tri-layer materials for a source contact of a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The authors validate its extremely low contact resistance for both n-type and p-type SiC by a simple process. The characteristics of Ti/Al/Si ohmic contacts were measured by using the transfer length method (TLM). We examined the dependence of the contact resistance on the thickness of each layer of Ti/Al/Si. Then, it is found that Ti/Al/Si contacts with an appropriate thickness show excellent ohmic properties for both n-type and p-type SiC. N-type specific contact resistance (ρn) of 3.7 × 10-6 Ω cm2 and p-type specific contact resistance (ρp) of 1.7 × 10-4 Ω cm2 are obtained with Ti (20 nm) /Al (30 nm) /Si (30 nm).
Electrical Properties of Mg-Implanted 4H-SiC
Authors: Matsuura Hideharu , Morine Tatsuya , Nagamachi Shinji
Published: February 2014

Because Al and B (elements of III group) in SiC are deep-level acceptors and these acceptors cannot reduce the resistivity of p-type SiC very much, Mg (element of II group) that may emit two holes into the valence band is investigated. A p-type 4H-SiC layer is obtained by 1800 °C annealing of the Mg-implanted layer, not by 1600 and 1700 °C annealing. It is found that a Mg acceptor level in 4H-SiC is too deep to determine the reliable density and energy level of the Mg acceptor using the frequently-used occupation probability, i.e., the Fermi-Dirac distribution function. Using the distribution function including the influence of the excited states of the Mg acceptor, therefore, its density and energy level can be determined to be approximately 1×1019 cm-3 and 0.6 eV, respectively. Judging from the Mg implantation condition, the obtained values are considered to be reliable.
On the Ti3SiC2 Metallic Phase Formation for Robust p-Type 4H-SiC Ohmic Contacts
Authors: Jennings Michael R. , Fisher Craig A. , Walker David , Sanchez Ana , Pérez-Tomás Amador , Hamilton Dean P. , Gammon Peter Michael , Burrows Susan E. , Thomas Stephen M. , Sharma Yogesh K. , Li Fan , Mawby Philip  Andrew
Published: February 2014

This paper presents a detailed physical and electrical analysis of 4H-SiC ohmic contacts to p-type material, the main aim being to examine their ruggedness under high temperature conditions. XRD, FIB-TEM and SEM are techniques that have been utilized to examine the microstructure and interface properties respectively. A detailed physical study revealed the presence of a crystalline hexagonal Ti layer orientated in the same direction as the 4H-SiC epitaxial layer. This factor seems to be important in terms of electrical performance, having the lowest measured specific contact resistivity of 1x10-6 Ωcm2. We attribute this to the optimized formation of Ti3SiC2 at the metal/SiC interface. An initial high temperature study shows thermionic emission occurring across the metal/semiconductor junction.
Effect of Shallow n-Doping on Field Effect Mobility in p-Doped Channels of 4H-SiC MOS Field Effect Transistors
Authors: Noll Stefan , Rambach Martin , Grieb Michael , Scholten Dick , Bauer Anton J. , Frey Lothar
Published: February 2014

A high inversion channel mobility is a key parameter of normally off Silicon-Carbide MOS field effect power transistors. The mobility is limited by scattering centers at the interface between the semiconductor and the gate-oxide. In this work we investigate the mobility of lateral normally-off MOSFETs with different p-doping concentrations in the channel. Additionally the effect of a shallow counter n-doping at the interface on the mobility was determined and, finally, the properties of interface traps with the charge pumping method were examined. A lower p-doping in the cannel reduces the threshold voltage and increases the mobility simultaneously. A shallow counter n-doping shows a similar effect, but differences in the behavior of the charge pumping current can be observed, indicating that the nitrogen has a significant effect on the electrical properties of the interface, too.
Investigation of the Barrier Heights for Dissociative Adsorption of HF on SiC Surfaces in the Catalyst-Referred Etching Process
Authors: Bui Pho Van , Inagaki Kouji , Sano Yasuhisa , Yamauchi Kazuto , Morikawa Yoshitada
Published: February 2014

We have developed a novel abrasive-free planarization method, which we term catalyst-referred etching (CARE). In silicon carbide (SiC) CARE, Pt is used as a catalyst and HF solution is used as an etchant. CARE produces a crystallographically undamaged and smooth SiC surface. To understand the removal mechanism at the topmost surface of SiC in the CARE process, we performed first-principles reaction path simulations using the simulation tool for atom technology (STATE) program package. These calculations are based on the density functional theory within the generalized gradient approximation of Perdew et al. The barrier height of the dissociative adsorption of HF on a SiC surface was evaluated by the climbing image nudged elastic band method. We present simulation results for the initial stages of the etching process. The reaction barrier height for adsorption of the first HF is 1.2 eV.
Removal of Mechanical-Polishing-Induced Surface Damages on 4H-SiC Wafers by Using Chemical Etching with Molten KCl+KOH
Authors: Yao Yong Zhao , Ishikawa Yukari , Sugawara Yoshihiro , Sato Koji
Published: February 2014

High temperature (>1000 °C) chemical etching using molten KCl or molten KCl+KOH as the etchant has been carried out to remove the mechanical-polishing (MP) induced damage layer from 4H-SiC surface. Atomic force microscopy observations have shown that line-shaped surface scratches that have appeared on the as-MPed surface could be completely removed by KCl-only etching or by KCl+KOH etching (KCl:KOH=99:1 in weight) at ~1100 °C. Between the two recipes, KCl+KOH etching has shown a higher etch rate (6~7 times) and is able to remove ~9 μm and ~36 μm-thick damage layer from the Si (0001) and the C(000-1) surface, respectively. Besides, KCl+KOH etching seems to have formed a Si (0001) surface covered with atomic steps while KCl-only etched surface is featured with nanometer-scale pores.
Thinning of a Two-Inch Silicon Carbide Wafer by Plasma Chemical Vaporization Machining Using a Slit Electrode
Authors: Okada Yuu , Nishikawa Hiroaki , Sano Yasuhisa , Yamamura Kazuya , Yamauchi Kazuto
Published: February 2014

In recent years, silicon (Si) has been mainly used in power devices, but the limit of its performance is being reached. Therefore, silicon carbide (SiC) power devices have been attracting attention because they enable the fabrication of devices with low power consumption. To reduce the on-resistance in vertical power transistors, backside thinning is required after device processing. However, it is difficult to thin a SiC wafer with a high removal rate by conventional mechanical processing because its high hardness and brittleness cause cracking and chipping during thinning. Therefore, we have attempted to thin a SiC wafer using plasma chemical vaporization machining (PCVM), which is plasma etching using atmospheric-pressure plasma. In this study, we describe a machining property using a newly developed slit electrode that is composed of two parts and has a slit that allows for a new gas to pass.
Dicing of SiC Wafer by Atmospheric-Pressure Plasma Etching Process with Slit Mask for Plasma Confinement
Authors: Sano Yasuhisa , Nishikawa Hiroaki , Okada Yuu , Yamamura Kazuya , Matsuyama Satoshi , Yamauchi Kazuto
Published: February 2014

Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, because of the hardness and chemical stability of SiC, few conventional machining methods can handle this material efficiently. A plasma chemical vaporization machining (PCVM) technique is an atmospheric-pressure plasma etching process. We previously proposed a novel style of PCVM dicing using slit apertures for plasma confinement, which in principle can achieve both a high removal rate and small kerf loss, and demonstration experiments were performed using a silicon wafer as a sample. In this research, some basic experiments were performed using 4H-SiC wafer as a sample, and a maximum removal rate of approximately 10 μm/min and a narrowest groove width of 25 μm were achieved. We also found that argon can be used for plasma generation instead of expensive helium gas.
Effects of Machining Fluid on Electric Discharge Machining of SiC Ingot
Authors: Yamamoto Norimasa , Yamaguchi Satarou , Kato Tomohisa
Published: February 2014

Recently, ingots of silicon carbide have been adapted to be sliced by the wire-cut electrical discharge machining. Fast slicing, and the reduction in the loss are important for slicing of the wafer. In this paper, characteristic features of the electric discharge machining in the ion-exchange water and the fluorine-based fluid were compared for these improvement. The discharge was caused by a pulse voltage applied to a ingot of silicon carbide and the wire in machining fluid, and the slicing was proceeded. As a result, improvement of surface roughness and kerf loss was confirmed, for the first time. In addition, the improving methods for fast slicing were considered.
Top-Seeded Solution Growth of 3 Inch Diameter 4H-SiC Bulk Crystal Using Metal Solvents
Authors: Kusunoki Kazuhiko , Kamei Kazuhito , Okada Nobuhiro , Moriguchi Koji , Kaido Hiroshi , Daikoku Hironori , Kado Motohisa , Danno Katsunori , Sakamoto Hidemitsu , Bessho Takeshi , Ujihara Toru
Published: February 2014

We performed top-seeded solution growth of 4H-SiC for obtaining longer length crystal. Si-Cr and Si-Ti melts were used as solvents. Meniscus formation technique was applied to the present study. Special attention was paid to improve the process stability during long-term growth. One of major technological problems in the solution growth is that the precipitation of polycrystalline SiC which hiders the stable single crystal growth. Another problem is the fluctuation of supersaturation at the growth interface during the growth. Through the optimization of growth process conditions, we have successfully grown 4H-SiC single crystals up to 14 mm long with three-inch-diameter, and evaluated their crystalline quality.
Evaluation of Buried Grid JBS Diodes
Authors: Lim Jang Kwon , Peftitsis Dimosthenis , Sadik Diane Perle , Bakowski Mietek , Nee Hans Peter
Published: February 2014

The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm2 (1 A) and 0.024 cm2 (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured I-V characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60 % and 70 % of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Qc, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.
High Voltage SiC JBS Diodes with Multiple Zone Junction Termination Extension Using Single Etching Step
Authors: Deng Xiao Chuan , Rao Cheng Yuan , Wei Jin , Jiang Hua Ping , Chen Miao Miao , Wang Xiang Dong , Zhang Bo
Published: February 2014

A novel variation of lateral etching junction termination extension (VLE-JTE) for Silicon carbide (SiC) power junction barrier Schottky rectifier (JBS) using a single mask is proposed and investigated. Simulation results shows that the breakdown voltage of JBS terminated with VLE-JTE can achieve 6500V, reaching up to more than 95% of parallel-plane junction bulk breakdown. Moreover, it implements a single mask with window areas varying laterally away from the main junction instead of extra ion implantation or etching steps to achieve multiple-zone JTE, making it easier to be implemented in applications.
The Fabrication of 4H-SiC Floating Junction SBDs (FJ_SBDs)
Authors: Yuan Hao , Tang Xiao Yan , Zhang Yi Men , Zhang Yu Ming , Lv Hong Liang , Wang Yue Hu , Zhou Yu Fei , Song Qing Wen
Published: February 2014

Based on the theoretical analysis and the simulation results of the ion implantation process and the floating Junction structure, a 4H-SiC SBD with floating junction (FJ_SBD) is fabricated. Compared with the on-resistance 5.13 mΩ·cm2 of conventional SBD fabricated at the same time, the on-resistance of FJ_SBD with 3μm P+ buried box is only 6.29 mΩ·cm2. The breakdown voltage of the FJ_SBD reaches 950V which is much higher than the 430V of conventional SBD. According to the presented results, The BFOM of the FJ_SBD is 3 times higher than the value of the conventional SBD. It is proved that FJ-SBD has greater prospects for development.
Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC
Authors: Salemi Arash , Buono Benedetto , Hallén Anders , Hassan Jawad , Bergman Peder , Zetterling Carl Mikael , Östling Mikael
Published: February 2014

10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a VF of 3.3 V at 100 A/cm2 at 25°C, which was decreased to 3.0 V at 300°C.
High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode
Authors: Nakayama Koji , Ogata Shuji , Hayashi Toshihiko , Hemmi Tetsuro , Tanaka Atsushi , Izumi Toru , Asano Katsunori , Okamoto Dai , Tanaka Yasunori , Mizushima Tomonori , Yoshikawa Mitsuru , Fujisawa Hiroyuki , Takenaka Kensuke , Takei Manabu , Yonezawa Yoshiyuki , Fukuda Kenji , Okumura Hajime
Published: February 2014

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.
Development of SiC Super-Junction (SJ) Devices by Multi-Epitaxial Growth
Authors: Kosugi Ryoji , Sakuma Yuuki , Kojima Kazutoshi , Itoh Sachiko , Nagata Akiyo , Yatsuo Tsutomu , Tanaka Yasunori , Okumura Hajime
Published: February 2014

Super-junction (SJ) devices have been developed to improve the trade-off relationship between the blocking voltage (VBD) and specific on-resistance in unipolar power devices. This SJ structure effect is expected in SiC unipolar devices. Multi-epitaxial growth is a known fabrication method for SJ structures where epitaxial growth and ion implantation are repeated alternately until a certain drift-layer thickness is achieved. In this study, we fabricated two types of test elemental groups with an SJ structure to evaluate the breakdown voltage (VBD) and specific resistivity of the drift layer (Rdrift). Experimental results show that VBD exceeded the theoretical limit of the 4H-SiC by 300V, and Rdrift agreed well with the estimated value from the device simulation. The beneficial effects of the SJ structure in the SiC material on VBD and Rdrift were confirmed for the first time.
Evolution of Fast 4H-SiC CVD Growth and Defect Reduction Techniques
Authors: Tsuchida Hidekazu , Kamata Isaho , Ito Masahiko , Miyazawa Tetsuya , Hoshino Norihiro , Fujibayashi Hiroaki , Ito Hideki , Naitou Masami , Aoki Hirofumi , Nishikawa Koichi , Makino Emi , Tokuda Yuichiro , Kojima Jun
Published: February 2014

This paper introduces our recent challenges in fast 4H-SiC CVD growth and defect reduction. Enhanced growth rates in 4H-SiC epitaxial growth by high-speed wafer rotation and in a high-temperature gas source method promoting SiC bulk growth by increasing the gas flow velocity are demonstrated. Trials and results of deflecting threading dislocations by patterned C-face 4H-SiC epitaxial growth are also shown.
Variant of Excess Current in 4H-SiC pn Structures
Authors: Strel'chuk Anatoly M. , Kalinina Evgenia V. , Lebedev Alexander A. , Boricheva Irina K. , Pavshukov Vladimir V.
Published: February 2014

Excess currents and defects were investigated in the 4H-SiC p+nn+ structures created by implantation. It was found that the principal p+n junction is shunted by several or multiple Schottky barriers connected in parallel to the principal pn junction and formed by a contact of Al on the surface of p+-layer with n-layer perhaps with participation of carbon coated surfaces of the pits or other defects. Amount and area of Schottky barriers vary for different pn structures, in connection with which vary as the value of the excess current and character of the current-voltage dependence, and, apparently, that was observed in some cases, the instability of excess current.
Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination
Authors: Wada Keiji , Uchida Kosuke , Kimura Ren , Sakai Mitsuhiko , Hatsukawa Satoshi , Hiratsuka Kenji , Hirakata Noriyuki , Mikamura Yasuki
Published: February 2014

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.
4H-SiC Trench MOSFET with Bottom Oxide Protection
Authors: Kagawa Yasuhiro , Fujiwara Nobuo , Sugawara Katsutoshi , Tanaka Rina , Fukui Yutaka , Yamamoto Yasuki , Miura Naruhisa , Imaizumi Masayuki , Nakata Shuhei , Yamakawa Satoshi
Published: February 2014

Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.
14.6 mΩcm2 3.3 kV DIMOSFET on 4H-SiC (000-1)
Authors: Kono Hiroshi , Furukawa Masaru , Ariyoshi Keiko , Suzuki Takuma , Tanaka Yasunori , Shinohe Takashi
Published: February 2014

Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.
High Temperature Reliability of the SiC-MOSFET with Copper Metallization
Authors: Okabe Hiroaki , Yoshida Motoru , Tominaga Takaaki , Fujita Jun , Endo Kazuyo , Yokoyama Yoshinori , Nishikawa Kazuyasu , Toyoda Yoshihiko , Yamakawa Satoshi
Published: February 2014

We investigated the SiC-MOSFET with Cu metallization instead of conventional Al metallization to apply to high reliability power modules. As Cu has higher electrical and thermal conductivity, yield strength, and tolerance of its migration than those of Al, applying Cu to metallization and wire bonds will lead to longer lifetime for power modules. One of the major difficulties with Cu metallization is its high diffusivity into SiO2 and poly-Si which are used as gate oxide, interlayer oxide, and gate electrodes in SiC-MOSFETs, resulting in degradation of devices. We fabricated the SiC-MOSFET with Cu metallization and a diffusion barrier. We have successfully obtained good characteristics same as conventional Al metallization and demonstrated its high temperature reliability.
Improvement of Channel Mobility in 4H-SiC C-Face MOSFETs by H2 Rich Wet Re-Oxidation
Authors: Okamoto Mitsuo , Makifuchi Youichi , Araoka Tsuyoshi , Miyazato Masaki , Sugahara Yoshiyuki , Tsutsumi Takashi , Onishi Yasuhiko , Kimura Hiroshi , Harada Shinsuke , Fukuda Kenji , Otsuki Akihiro , Okumura Hajime
Published: February 2014

4H-SiC(000-1) C-face was oxidized in H2O and H2 mixture gas (H2 rich wet ambient) for the first time. H2 rich wet ambient was formed by the catalytic water vapor generator (WVG) system, where the catalytic action instantaneously enhances the reactivity between H2 and O2 to produce H2O. The dependence of SiC oxidation rate on the H2O partial pressure was investigated. We fabricated 4H-SiC C-face MOS capacitor and MOSFET by the H2 rich wet re-oxidation following the dry O2 oxidation. The density of interface traps was reduced and the channel mobility was improved in comparison with the conventional O2 rich wet oxidation.
Selection of SPICE Parameters and Equations for Effective Simulation of Circuits with 4H-SiC Power MOSFETs
Authors: Tanner Philip , Dimitrijev Sima , Moghadam Hamid Amini , Aminbeidokhti Amirhossein , Han Ji Sheng
Published: February 2014

Power MOSFETs based on 4H-SiC have recently been commercialized and so circuit designers require SPICE models for simulation purposes in a range of applications including switch-mode power supplies. We present a selection of SPICE LEVEL 3 parameters and equations that can be used for effective circuit simulation of these MOSFETs, taking into account their unique characteristics for both static and dynamic operation.
Touch-Less Java Based Hand Tracking System to Control an Artificial Arm
Authors: Baron Grzegorz , Czekalski Piotr , Malicki Daniel , Tokarz Krzysztof
Published: February 2014

Modern sensing technologies create new possibilities to control mobile robots without any dedicated manipulators. In this article authors present a novel method that enables driving of the Mindstorms NXT artificial arm with Microsoft Kinect, using gesture recognition and hand tracking. To imitate the movement of an artificial robotic arm, an algorithm of the human-computer interaction is employed using skeleton tracking and gesture control in 3D space. The solution is implemented using free, open source software, Java based.
Modeling the Electrical Behavior of Lithium-Ion Batteries for Electric Vehicles
Authors: Quantmeyer Florian , Liu-Henke Xiao Bo
Published: February 2014

The present paper describes the modeling of the energy-storage unit - a battery that consists of several lithium-ion cells. Identification by means of frequency measurements at different operating points and subsequent verification in the time domain serve to identify both the modeling structure and the system parameters. For the frequency measurement the Electrochemical Impedance Spectroscopy (EIS) is used. The iterative character of the selected procedure is exemplified. On the basis of dynamical testing cycles, the accuracy of the battery model is verified even in case of high frequencies.
Comparison of Electromagnetic Coil Launcher Model with Real-Device Characteristics
Authors: Kondratiuk Mirosław , Gosiewski Zdzisław
Published: February 2014

In this paper we describe a numerical model and a construction of an electromagnetic launcher (EML) consisting of ten copper coils located serially. The solenoids were mounted on the pipe-shaped slideway, inside which, the ferromagnetic core was moved driven by the coils magnetic force. The paper presents the model of an EML based on circuit approach involving lumped parameters which were obtained by means of a finite element methods (FEM). The numerical representation contained a mechanical part with introduced friction coefficients. In the article we proposed an algorithm which enabled us to fit the numerical model to the constructed device by selection of these friction parameters values. Thus, we were able to compare the signals from computer simulations and measurements which were taken during laboratory tests.
Introduction to the Conception of Combustion Process Onboard Monitoring System
Authors: Bieniek Andrzej
Published: February 2014

This paper presents a conception of a system designed for monitoring combustion process in a multi-cylinder combustion engine. The proposed system is based on the application of a pressure sensor installed in one of the engine’s cylinders. The analysis of the combustion process in the remaining cylinders is possible as a result of analyzing the course of the rotational speed by means of a sensor with a large resolution integrated with engine control phase sensor. This paper presents results of the initial testing of its operation and results of research into a system named CPMOS (Combustion Process Onboard Monitoring System) dedicated to a self-ignition engine of an off-highway vehicle. The use of an algorithm which applies a synthesis of a pressure sensor signal and rotational speed sensor offers the possibility of gaining a reconstructed course of pressure in all cylinders in the engine. The proposed measurement of pressure in a cylinder not involving fuel injection system can provide more detailed information regarding the course of the combustion process in the particular cylinders. The proposed concept of the CPMOS system leads to a decrease in the overall system cost as a result of the application of a single pressure sensor in a single cylinder. The future potential application of the monitoring of the combustion in each cylinder can enable the improvement of the operating parameters of the cylinders as a result of optimizing the control of the fuel injection system, EGR system and systems used for limiting exhaust gases used in the vehicle.