bluuebunny/crossref_metadata_2025 huggingface dataset:
Impact of PCB Manufacturing Process Variations on Trace Impedance
Authors: Renbi Abdelghani , Carlson Johan , Delsing Jerker
Published: October 2015

This paper demonstrates statistically the impact of PCB manufacturing variations on the characteristic impedance. Moreover, it shows that the characteristics of the PCBs vary across different suppliers. These differences cannot be tolerated in some applications where the characteristic impedance is restricted to be within a specific range. We sampled 3 × 20 PCBs, each batch of twenty is ordered from a different manufacturer. The sampling consist of measuring the phase shift between the reected and the incident signals when injecting a 180 MHz sinewave into a PCB trace. The trace is selected to be the same for all samples. All the PCBs are ordered to be identical and designed for 50 Ω devices. Our conclusion was drawn after running the T-tests to assess statistically the significance of the difference occurring between the PCBs. Based on the computed P-values all the three batches are different from each other in the mean of the measured phase shift with 95 % confidence. The difference between the measured and the expected characteristic impedance is found as 3 %, 10 % and 20 % for these three manufacturers. We also witnessed board-to-board variations even within the same batch and from the same supplier due to the process instability by looking at the probability density of having the same phase shift that is equal to the mean. Some samples shown 2.6 % to 3.5 % difference above the mean.
Zero-Power MEMS Sensor Actuated RFID System*
Authors: Zhang Yang , Chen Kerchia , Burke Sean , McLaughlin Scott , Li G. P. , Bachman Mark , Rieger Dennis , Ho Winston
Published: October 2015

We present an RFID system with embedded passive MEMS sensor switches to provide long-term, item-level monitoring and data logging. This patented temperature monitoring prototype for blood bag monitoring utilizes MEMS cantilever array both as passive multi-temperature sensors and as power triggers for data logging circuitry, all packaged in a flexible laminated PCB (2.5 × 2.5 × 0.2 cm). This system uses zero power to monitor temperature and uA level current to record temperature data beyond preset thresholds. The on-board data logger consists of a dual-communication, HIPAA compliant, 13.56 MHz RFID chip and customized antenna, an ultra-low power micro-controller, and supporting passives. Prototypes are estimated to have more than 60 days of continued temperature monitoring per use with a thin film battery.
Comparison Between Multilayer Ceramic and Organic Package Substrates Based Upon Signal and Power Integrity
Authors: Aguirre Jerry , Garland Paul , Vargas Marcos , Tallo Heather , Tallo Joseph
Published: October 2015

Comparisons between organic and ceramic packaging is a difficult task given the considerable number of differences in material properties and potential tradeoffs between cost, electrical performance, thermal performance, and environmental factors. This paper presents a power and signal integrity comparison between a select set of multilayer organic technologies (HDBU and CPCore) and multilayer ceramic technologies (HTCC and LTCC). The geometry and material property impact on electrical performance for the flip-chip first level interconnect are qualitatively discussed and compared. The broadband frequency performance for the ball grid array (BGA) second-level interconnect to a PWB is simulated and characterized to 40 GHz for a differential pair using full-wave simulation. The impedance of the power distribution network (PDN) for a ceramic package is characterized by measurement to correlate with full-wave simulation to then subsequently compare with an organic substrate PDN.
Optimization of a Flux-Less Metal Thermal Interface Material by Reflow in a Vacuum Furnace
Authors: Zappella Pierino I , Barnes Paul W , Muhs David , Wilson Bruce
Published: October 2015

This paper describes the work performed with a pure metal thermal interface material (TIM) for the sole purpose to improve the transfer of heat from the die to the metal cover case. A flux-less reflow process is employed in order to reflow the indium TIM material. This operation is performed in a vacuum furnace utilizing heat, vacuum, and pressure in a specific sequence in order to wet the metal lid and the backside of the flip chip die. The initial objective was to demonstrate minimal voiding of the TIM and subsequently limited flow out of molten solder from and along the sides of the die. A series of experiments were employed where acceptance criteria is evaluated by a) X-Ray, b) scanning acoustical microscopy (SAM), and c) cross-section. Acceptance criteria consists of 1) indium wetting of both lid to indium interface and indium to silicon interface die, 2) indium bond line (BLT) thickness, 3) lid tilt, and 4) lid shear strength. Acceptance is determined after a subsequent 4X ball grid array (BGA) reflow in a conventional belt reflow furnace with minimal voiding, no popcorn or blistering of the laminate substrate, and TIM thickness and solder flow out at sides of the die within the acceptable limits of the above mentioned criteria.
Simultaneous Characterization of Theta-JC and Theta-JB Using Through-Package 1-D Heat Flow
Authors: Kim Jichul , Kim Jae Choon , Choi Mina , Cho Eunseok , Baek Hyunggil , Song HoGeon , Kang Sayoon
Published: October 2015

A new technique is proposed for simultaneous, in-situ characterization of in-package thermal resistances (junction-to-case and junction-to-board) in a single test. A thin resistive heater is patterned on package top surface to establish one-dimensional heat conduction along the package vertical direction. Accompanying temperature rise at the heater is measured using a thermocouple and analyzed to estimate equivalent thermal R-C network model of the package. Due to the one-dimensionality of the probing thermal wave, the derived R-C network model represents physical package thermal structure, enabling simultaneous estimation of both thermal resistances (theta-JC and theta-JB). The proposed technique is validated by measuring theta-JC and JB of an overmolded flip-chip ball grid array package. The proposed method eliminates need for a separate test setup for the characterization of each thermal resistance, enhancing the accuracy and efficiency of the package thermal characterization. In addition, use of the external heater and sensing element, instead of on-chip heater and temperature sensor, enables in-situ thermal characterization of a real package mounted on the set board.
Surface Energy and Wettability Study of Flip Chip Packaging Materials
Authors: Wang Jinlin
Published: October 2015

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.
Direct Printing for Next Generation High Density Packaging
Authors: Chen Xudong , Church Kenneth
Published: October 2015

Next generation micro-packaging will feature a number of advances in high density techniques, including more components in a smaller volume. New techniques for metallization, passives, antennas, solders, and adhesives will be required. The key factor for these will be size constraints. Micro-dispensing can print a number of materials to include dielectrics, ruthenates, metallics, solder, and adhesives. Those with experience in micro-dispensing recognize the size limitation using a dispensing approach and understand that the hope of achieving smaller line widths, smaller pad sizes, and precise placement of the material is not feasible. nScrypt has demonstrated the ability to considerably shrink the line widths and dots from traditional micro-dispensing, thus enabling the next generation packaging and increasing the component count in the same or less volume. Micro-dispensing solder dots, precisely placing narrow adhesive lines and potentially directly printing resistors and antennas to replace standard pick and place and connectorized antennas will be demonstrated to reduce the size and volume for high micro-electronic circuits. In addition to the new and enabling reduced volume approach, nScrypt will also demonstrate how the speed of this approach will rival traditional high volume screen printing and other masking technologies, thus making this a viable manufacturing tool for micro-packaging.
Pure Copper Solder Paste with Sub-200 °C Processing Temperature
Authors: Zinn Alfred A. , Chiu Frances Y.
Published: October 2015

At the Advanced Technology Center of Lockheed Martin Corporation, we have developed a copper-based electrical interconnect material that can be processed around 200 °C. The material can be dispensed using Gauge 20–30 syringe tips and has shown electrical and thermal conductivity that progresses toward the bulk copper values. The approach is enabled by our controlled fabrication process of Cu nanoparticles, which takes advantage of rapidly increasing melting point depression as the particle size approaches the nanoscale. The readily scalable synthesis of Cu nanoparticles uses a low cost solution-phase chemical reduction approach. XRD, SEM and HRTEM confirm the formation of stable Cu nanoparticles as small as 10 nm and below and the effectiveness of the surfactant mixture to prevent oxidation. We have demonstrated assembly of fully functional LED test boards and built for the first time a fully functional small camera board using all Cu nanoparticle based pastes with a consistency very similar to standard SAC solder paste and a tap density approaching 6 g/ccm. Initial tensile testing gave values around 50% of eutectic SnPb solder. Once fully optimized, the pure copper electrical interface material is expected to produce joints with up to 10x electrical and thermal conductivity compared to the tin-based materials currently in use.
Photonic Curing Explanation and Application to Printing Copper Traces on Low Temperature Substrates
Authors: Schroder K. A. , Rawson Ian M. , Pope Dave S. , Farnsworth S.
Published: October 2015

Photonic curing is a transient thin-film thermal processing technique using flashlamps. It was developed by NovaCentrix® and incorporated in the PulseForge® toolset to address the need of the printed electronics industry to process high temperature materials on low temperature substrates such as paper and plastic on a moving web. Applications include photovoltaics, displays, solid state lighting, thin film batteries, RFID tags, and printed circuits. The ability to substitute inexpensive and flexible substrates for expensive, rigid substrates while achieving similar performance can dramatically reduce the cost of the final product and enable new products. In this paper, we discuss the technology and mechanisms of the process and illustrate a case study of forming copper traces on plastic and paper in a roll-to-roll environment. Here, a low cost copper oxide ink is printed on plastic or paper and chemically reacted using pulsed light from the PulseForge tool to form highly conductive copper traces. This process is performed in an ambient atmosphere.
Near-Zero Shift Attachment for Optoelectronic Components
Authors: Bourcier Roy J.
Published: October 2015

High performance laser-based optoelectronic devices commonly feature the use of free-space optical coupling between the laser diode and optical elements such as filters, secondary harmonic generators and optical fibers. A critical challenge in the assembly of such components is maintaining the required optical alignment precision during attachment of the optical subcomponents to a common platform. In the case of devices based on single mode waveguides, the post-attach shift must often be held to less than a few hundred nanometers to achieve the desired optical coupling efficiency. Historically, these tight tolerances have required the use of costly post-work operations such as laser hammering or re-bend to achieve performance objectives. Over the course of designing several such optoelectronic components, we have used and developed a variety of design concepts and assembly processes which have allowed us to achieve these demanding tolerances, often without the use of post-work. UV-curable structural adhesives and Nd:YAG laser spot welding have been used, individually and in combination, to perform the required sub-micron optomechanical attachments. Several approaches which have been successfully used will be described and their relative merits will be compared. In addition, key design and process elements which can impact post-attach shift will be discussed.
Thin Wafer Handling of 300mm Wafer for 3D IC Integration
Authors: Chang H. H. , Lau J. H. , Tsai W. L. , Chien C. H. , Tzeng P. J. , Zhan C. J. , Lee C. K. , Dai M. J. , Fu H. C. , Chiang C. W. , Kuo T. Y. , Chen Y. H. , Chen T. H. , Ku T. K. , Lo W. C. , Kao M. J.
Published: October 2015

In this study, thin wafer handling of 300mm wafer for 3D IC Integration is investigated. Emphasis is placed on the determination of the effect of a dicing tape on thin-wafer handling of wafers with Cu-Au pads, Cu-Ni-Au UBM, and TSV interposer with RDL. Also, thin-wafer handling critical issues such as the chip/interposer wafer, carrier wafer, temporary bonding, thinning, backside process, de-bonding, and assembly are presented and their potential solutions are discussed. Finally, state-of-the-art of materials and equipments for thin-wafer handling are examined.
Simulation of Huge Data Processing via Large Matrix Manipulation Using Hilbert Engine
Authors: Dang An , Delalic Joan , Nguyen Son , Gruenwald Bjorn , Lai Yuk , Chang Hoi Man
Published: October 2015

Modeling multi-physics structure is always accompanied by a huge complex data that need to be analyzed. For example, modeling of an explosion interacting with a solid object inherently consists of multiple phenomena including shock propagation, solid interaction, response of the solid, damage, debris movement, and thermal effects. Thus, the data processing speed always plays an important role. However, currently available computational software takes long time to reach the processing goals. The main goal of this presentation is to demonstrate faster processing using Hilbert Engine in huge matrix (billions of entries) manipulation in a single work-station. Indeed, Hilbert Engine is extremely efficient, fast and versatile in computation based on its abilities to bypass any operating system. Besides, it can operate as a stand-alone data analysis system or in a distributed, asynchronous processing network of cooperating system.
Very High Lead Count SMT Backplane Connector Rework Process: Recognizing the Challenges
Authors: Bielick Jim , Ferrill Mitchell G. , Kobeda Eddie , Lewis Theron
Published: October 2015

The ever growing demand for improved bandwidth, signal speeds, and performance in enterprise servers continues to drive increased circuit density and complex board designs. Single ended mode signaling is one design approach to address these challenges. A tightly integrated design team must carefully control the interfaces and trade-off complexity of chip and package designs to maintain power budgets at target performances. This single ended design approach has necessitated the use of very large (5040 contacts) surface mount connectors. These connectors are assembled to thick, densely wired, high copper content printed circuit boards which press the limits of conventional assembly and rework processes and tooling. Classical automated hot gas rework techniques, even with the best controls and practices in place, may not be capable of providing consistent, reliable connector rework. Extensive tooling modifications may also prove to be inadequate. Given these complex issues, in conjunction with shortening product development cycles, it is critical to define and investigate multiple rework approaches concurrently, so the probability of finding a manufacturable solution is greatly increased. This paper will discuss 1) the thermo-mechanical challenges encountered when trying to perform rework of this high lead count connector, 2) the tooling and process modifications attempted with respect to classical hot gas rework, and 3) the implemented solution which was full connector rework using a local vapor phase process. The local vapor phase process offers many advantages as the industry prepares for the transition to lead free when the RoHS server exemption expires. These advantages will also be discussed.
Single Probe for Bare Board Continuity and Isolation Testing
Authors: Renbi Abdelghani , Delsing Jerker
Published: October 2015

Bare board testing is vital before components loading. Defects after the PCB manufacturing process are possible such as opens, bridges, near-opens, near-bridges and characteristic impedance mismatches due to process variations and compounding raw material tolerances. Moreover, defects might cost about ten times more when detected in the next test phase, another motivation for unpopulated board test is loading expensive components on a set of defective boards might be economically catastrophic. Flying probe systems, which were developed in late 1980’s are commonly used and favorable to perform bare board isolation and continuity testing, especially when the volume is not big enough to justify bed of nails purchase. Flying probe system performance for a given bare board depends on the test algorithm, the mechanical speed and the number of probes. To reduce the cost on expensive test probes and probe maintenance and to accelerate the test time, this paper presents a new and cost efficient approach to test unpopulated and populated board with open sockets, using a single probe. Specifically, a coaxial probe injects one frequency signal into the PCB trace, the phase shift between the reected signal from the trace and the incident wave is detected and compared with the nominal value, which has been captured from a defect free board, which already underwent direct continuity and isolation testing. The conducted experiments have shown a good feasibility for practical use in the ATE (Automatic Test Equipment) for bare board and loaded board with open sockets. At the highest sensitivity of the phase shift detector, the prototyped tester is capable to distinguish between a defective and error free board with significant margins in case of defects such as opens, DC and RF bridges, exceeded and different width lines. The margin in the measurement between a defective and a correct board, which depends on the type of the defect is about 8 % to 65 %.
Improvement of Rated Power and VSWR Characteristics for Termination Resistor with Integrated Matching Network and Efficient Thermal Management
Authors: Rahman Akhlaq , Olinger Fred
Published: October 2015

Matching RF and Microwave signals to components within a circuit has become more challenging for circuit designer as operating frequency and power handling requirement increase. Termination resistors with excellent power handling capability with superior voltage standing wave ratio (VSWR) characteristics are needed for microwave circuit components in various wireless and telecommunication application. In this work, we extensively studied to improve the power handling capability and VSWR of termination resistor while maintaining the smaller size. We optimized the energy transmission within the component and significantly improved the efficiency of energy transfer between the transmission lines and the terminations. We discussed techniques of improving power handling capability and reduction of thermal fatigue to the component’s structure. By using innovative techniques of heat transfer we appreciably increased power handling capability while keeping the product size as minimum. We constructed matching network using integrated microstrip line at the beginning of the resistor material. We optimized impedance matching by varying length, width and pattern of transmission line as well as using defective ground structure (DGS) technique. We minimized the detrimental influence of component footprint and resistor material characteristics effect on signal reflection. Considering the necessary microwave parameters and required thermal performance, we designed and manufactured Pb free high power termination resistor. Several sizes of resistor are manufactured with rated power of 20 Watt, and 100 Watt which provides excellent VSWR characteristics for frequency up to 4 GHz. Resistors are manufactured for 50 ohm impedance; however, methods mentioned in the study are applicable to any impedance.
Mechanical Robustness of Solder Connections to Thick Film Gold
Authors: Marinis Thomas F. , Soucy Joseph W.
Published: October 2015

Thick film gold metallization is required for many high reliability circuits, especially those subjected to operation in high temperature or high humidity environments. Traditionally, wire bonded bare die are used on these circuits, but there is a trend to replace them with BGA packaged devices. State-of-the-art, chip scale packages increase circuit volume by less than 20 percent, while their use greatly simplifies testing and repair, as compared to wire bonded die.

The use of small, high density I/O pad arrays for attachment of BGA packages, necessitates very careful control of the solder reflow process to avoid excessive leaching of the gold into the solder. Also, unlike passive chip components and leaded devices, the solder filet associated with a solder ball attachment does not distribute mechanical loads over an extended area. Consequently, the stresses imposed on fine pitch, BGA pads are much higher than those imposed by other components. During aging, the gold metallization is converted to gold-tin intermetallic as inter-diffusion proceeds. This further reduces the mechanical integrity of the solder connection. This manifests itself in the observation that when BGA solder balls are subjected to accelerated aging followed by shear testing, the entire solder pad lifts off of the substrate, rather than failing in the solder joint.

What we have done is construct a diffusion based model to estimate the conversion of a thick film gold metallization pad to intermetallic and coupled this result with a finite element analysis to examine the effect of pad size and solder composition on the propensity of a pad to lift off the substrate, when subjected to mechanical or thermal induced loading. We are designing experiments to compare the predictions of our model to experimental results obtained from shearing solder balls, of different compositions and sizes, attached to substrates metalized with several different solderable, thick film gold materials.
Thermal and Mechanical Characterization of High Power GaN Packages
Authors: Willis Don , Gu Gary , Jin Daniel , Dry Rob
Published: October 2015

The typical package available for high power GaN application has the devices directly attached onto a metal flange, which could contribute significantly to the overall thermal resistance. This paper discusses an alternative approach to packaging both single and multiple devices through a heat spreader, which could potentially improve thermal performance and bring significant benefits to assembly in yields and cost. However, the heat spreader could also introduce significant CTE mis-match and potential concerns in reliability.

Nonlinear 3D finite element analysis (FEA) was conducted to characterize the thermal performance and evaluate mechanical/reliability concerns. Thermal modeling considered single and multiple die applications, and the results show13–15% thermal improvement with the copper heat spreader. Mechanical analysis focused on the thermal loads of the die attach and solder reflow processes. It reveals that the die attach process is more critical as shown in the higher stress due to higher thermal load, but stress/strain levels appear to be acceptable. Thus, this alternative approach could be a viable solution.
ASSESSMENT AND CHARACTERIZATION OF STRESS INDUCED BY VIA-FIRST TSV TECHNOLOGY
Authors: Parès G. , De Crecy F. , Moreau S. , Maurice C. , Borbely A , Mazuir J. , Chapelon L.L. , Sillon N.
Published: October 2015

Through Silicon Via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress build up in the silicon substrate that may induce warpage or expansion at the wafer level, strain and crystalline defects in the neighboring silicon of the TSV and finally can impact performances and reliability of the CMOS devices as well. Polysilicon, tungsten and copper are the three main conductors that are nowadays considered for the TSV fabrication. In a first part of this paper the different factors that contribute to the stress in these tree TSV types including the geometry, the materials and the process will be reviewed.

After bonding on a temporary carrier and thinning of the substrate to expose the via the stress built up during the fabrication of the TSV can be also revealed by the expansion of the silicon membrane.

Thermo-mechanical FEM simulations will be equally introduced and confronted to the experimental findings.

We also present some characterizations of silicon defects by chemical revelation around the TSV structures.

For characterization of the stress in TSV structures scale different techniques as EBSD, μRaman, XRD will be then presented.

Finally we conclude that with the optimization of some key processing steps, the stress induced in via-first technology may be acceptable for IC integration.
Topography and Deformation Measurement as a new Tool for Thermal Stress Assessment on Electronics Components
Authors: Hertl Michael
Published: October 2015

Requirements on electronics components are more and more demanding and extremely variable: the Automotive industry typically requires “zero defect” quality, which in practice means failure rates in the ppb range. Speed and energy critical applications are the drivers for the development of 3D die stacks and PoP designs, with the particularity that these components are facing at least 2 reflow solder cycles up to 260°C instead of only one. MEMS solutions typically include a cavity, with the specific demand for minimum component warpage during production in order not to damage the cavity.

Recently, Topography and Deformation Measurement (TDM) has been developed as a novel tool for the reliability analysis on package designs in the early development phase. It can be used to optimize the warpage behaviour of any new component under any kind of realistic thermal stress condition like for example reflow solder conditions, expected product life cycle thermal conditions, or accelerated aging test conditions.

The present paper will deal with four case studies: In the first, TDM is used to minimize the maximum warpage of a MEMS component’s package during reflow. In the second case study we will highlight the stress interaction between a component and a PCB, by analyzing the topography vs. temperature characteristics of the component before and after soldering it onto the PCB. In the third, the solderability of a small package which is strongly warped at room temperature will be studied. Finally, the In-Plane deformation behaviour of a PCB and a component will be compared in order to identify potential reliability issues due to CTE (coefficient of thermal expansion) mismatch between component and PCB.
3D-stacking of UTCPs as a module miniaturization technology
Authors: Priyabadini S. , Gielen A. , Dhaenens K. , Christiaens W. , Van Put S. , Kunkel G. , Petersen A.E. , Vanfleteren J.
Published: October 2015

3D-stacking of Ultra Thin Chip Packages (UTCP’s) – one of the emerging technologies in the field of high density integration - is presented here. This technology is developed to increase the functionality of the electronic devices and to raise the comfort zone by reducing the overall size and weight of the package. This has a bright future in the area of mobile communication, medical equipments like hearing aids, implants, patient monitoring. This paper describes an approach to produce miniaturized modular packages by using Ultrathin Chip Package Technology, stacking and through-hole (TH) interconnection technology. UTCP technology is a board level packaging concept, based on embedding of ultra-thin chips (∼20 μm) within two 20 μm thick spin-on polyimide layers resulting in a thin flexible chip package of thickness ∼50 μm. Stacking of the 4 layers of UTCPs by using 25 μm thick layers of adhesive films and vacuum lamination processes results in stacked UTCP modules of total thickness ∼300 μm. The connection to the different layers of the UTCPs is realized by drilling THs on the outer contact pads on the stacked packages, followed by metallization of these THs by Cu electroless deposition, electroplating and finally metal structuring. After processing and testing, the stacks can be easily mounted within functional demonstrators (e.g, Hearing Aid device, etc) replacing single silicon die of almost same size, but with 4 times output.
Z-axis Interconnections for Next Generation Packaging
Authors: Das Rabindra N. , Egitto Frank D. , Lauffer John M. , Antesberger Tim , Markovich Voya R.
Published: October 2015

In this paper, the use of electrically conducting adhesives (ECA) to form z-axis interconnections for next generation packaging is discussed. In particular, current efforts related to Z-axis interconnections for device level fabrication, integration, and electrical performance are highlighted. A few optimized ECAs were used for hole fill applications to fabricate Z-axis interconnections in laminates. Conductive joints were formed during composite lamination using the ECA. Around 5,000 to 200,000 through holes in the joining cores, formed by laser or mechanical drilling, and having diameters ranging from 50 μm to 750 μm, were filled with an optimized conducting adhesive. The adhesive-filled joining cores/layers were laminated with circuitized subcomposites to produce a composite structure. As a case study, a variety of z-axis interconnect constructions for a flip-chip plastic ball grid array package, rigid-flex, rigid-rigid, package-interposer-package (PIP), RF structures, and PWBs were fabricated and evaluated at both the subcomposite and composite levels to understand structural and electrical integrity. Electrically, S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES up to 15 Gbps over 750 mm. The present process allows fabrication of z-interconnect conductive joints having diameters in the range of 55 to 500 μm. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.
MEMS Packaging with 3D-MID Technology
Authors: Bachnak Nouhad
Published: October 2015

3D-MID (three dimensional molded interconnect devices) technology (which is already broadly used for 3D-MID mobile phone antennas) is also used for MEMS packaging and sensors applications. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part. The 3D electronic circuit is integrated into a 3D plastic casing or carrier, making it possible to achieve much more compact construction and much greater function density. More and more applications involving electrical and electro-optical circuits are made using 3D-MID technology. Typical 3D-MID applications are: Sensor packaging, LED packaging, security casings, RFIDs and Antennas. The main areas of application are in the automotive, medical, industrial technology and telecommunications sectors.
IC Bond Pad Structural Study by “Ripple Effect”
Authors: Martinez Jose , Salas Cesar , Salas Marco , Schofield Jason , Sheffield Steven , Wilkins Kyle , Hunter Stevan
Published: October 2015

IC bond pad structural reliability is studied for a variety of experimental pad designs in a 0.18um technology, having patterned metallization to simulate bond-over-active-circuitry (BOAC) situations in top-metal-minus-one and below. Underlying films deformation after wire bond is studied by optical microscopy after removal of the pad Al, with additional measurements by FIB. Pad designs in this study are rated for robustness to cracking according to an optical “ripple effect” deformation scale. “Ripple” is so named because it has a similar appearance to water ripples. It is due to non-uniform deformation in the underlying Al film(s) in the pad structure. Though the Al material is fully constrained within the SiO2 dielectric body, it is able to migrate plastically into local “hills and valleys” during bonding stress, with the top dielectric film bending in conformance. Cracks can then initiate in the undulating upper dielectric when its tensile strength is exceeded. “Ripple” in these pads is seen to vary depending upon the underlying metallization pattern and density as well as with wire bonding stress, for a fixed pad Al thickness. Traditional-style Al metallization pad structures with full metal plates are least robust, being the most prone to high “ripple” and cracks. Other pad structures more indicative of BOAC designs show varying degrees of improved robustness to cracking as shown by decreasing “ripple”. Results show that significant improvements in pad robustness to cracking are feasible in BOAC designs which include top-metal-minus-one routing in Al-metallization technologies, while providing increased process margin in wire bond, permitting efficient use of die area without extra processing or new issues.
A First Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive
Authors: Liu Mary , Yin Wusheng
Published: October 2015

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process.

After being used in the customer field for a few years, the implementation of SMT266 has been approved improving the process yield, eliminating voids and cracks in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT266 is high up to 6000 cycles, at least 4000 – 5000 cycles higher than other processes. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our paper.
Three-Dimensional Surface in LTCC for a MM-Wave Antenna
Authors: Uhlig Peter , Holzwarth Sybille , Sanadgol Bahram , Serwa Alexandra
Published: October 2015

Low loss LTCC (Low Temperature Cofired Ceramics) materials have already demonstrated their virtues for high density packaging of mm-wave modules and their capability to handle the inherent requirements of heat dissipation. A 60 GHz substrate integrated waveguide fed steerable antenna array is one example of the driving applications for new challenges in the LTCC process. This antenna is suitable for transmit and receive in the 60 GHz WPAN frequency band [1]. Integrating antenna array and mm-wave front-end in one module is a consequent way to avoid amplitude and phase uncertainties associated with connectors and cables. A compact module also helps to reduce losses in the signal path by providing short interconnects. This is important for mm-Wave systems, particularly for the receiver. The antenna design presented here requires a three-dimensional surface structure with features like small and precise cavities and grooves. Different methods to fabricate cavities in LTCC modules will be discussed and a new method which proved suitable for the demanding application will be presented in detail.
Why Wedge Bond?
Authors: Bubel Joe , Levine Lee
Published: October 2015

Wedge bonding has the potential to emerge as a driving technology for bonding fine-pitch devices. The deformation (width) of a full strength wedge bond is typically 33% smaller than the smallest diameter ball bond of the same wire diameter. As we move to finer pad pitches which necessitates smaller bond pads (as predicted by the ITRS Roadmap) the diameter of smaller diameter bonding wire presents a roadblock. Smaller diameter wire has significantly lower conductivity (current carrying capacity). Wedge bonding allows use of a larger wire diameter than ball bonding for the same pad size providing higher current for the package.

New looping capabilities, higher bonding speed (productivity) and quality assurance tools (Process Integrated Quality Control™) provide high-reliability interconnection solutions for advanced military, aerospace, medical and optoelectronic packages.
High Thermal-Transient Packaging for a SiC-Based Solid State Circuit Breaker
Authors: Baltis Theodore , Hopkins Douglas C , Pitaressi James M , Hazelmyer Donald R
Published: October 2015

Solid-State Circuit Breakers (SSCBs), or Contactors, are critical components in next generation electric aircraft, and must be small in size, fast in response, and have high reliability. Silicon Carbide (SiC) semiconductor switches provide a series of improvements over traditional silicon-based breakers in both electrical and thermal performances. The reported SSCB uses SiC MOSFETs mounted on cast-aluminum traces, cast onto an aluminum nitride (AlN) ceramic co-captured in an aluminum composite baseplate. The system is similar to an AlSiC and Direct-Bonded-Aluminum (DBA) approach.

This presentation details the transient thermal characterizations of an SSCB having the highest density in development. Previous work focused on a 30A SSCB that was constructed and tested to show a 300A, 500ns circuit breaking capability. The high density comes from allowing the SiC junctions to pulse to ∼350°C (in 5ms) from a 105°C ambient baseplate. The 30A/300A module was reported in IMAPS HiTEC’10 “Development of a SiC SSPC Module with Advanced High Temperature Packaging,” This paper builds on that paper adding the mechanical results and all new data on the larger, high energy density module with larger die. The objective of the presentation is to introduce (or update) the use of cast composite metal-ceramic structures for high thermal transient applications and document the mechanical stress/strain performance through simulations. The module is in development for military applications and has not been field-tested. This is also developed for Smart-Grid applications in local distribution systems.
Studies of Mesoscale Models Parameterized by Molecular Models for Interface Failure in Epoxy Molding Compounds
Authors: Iwamoto Nancy
Published: October 2015

Deeper understanding of material failure must include consideration of contributions from the molecular and atomistic scales from which a more complete root cause picture may be constructed. The current study, supported by an international consortium effort (NanoInterface) [1], reports efforts to bridge the gap between molecular models and macroscale models by use of a mesoscale discrete particle method. Both the initial stress-strain curve and the latter part of the stress strain curve has been developed for perfect (flat) interfaces as well as simulated rough interfaces, using a saw-tooth configuration.
Mix of analog and digital circuitry analysis in a noisy environment
Authors: Tournier Hugues , Hu Kaisheng , Deng Shuhui
Published: October 2015

High transient current from a digital circuitry, fast di/dt, within an analog circuitry co-existence is very demanding. Analysis of the diverse potential noise coupling path, and suggested solutions, is required to guarantee proper functionality and performances of both circuitries. Our noise analysis includes the die, package and PCB power supply and decoupling strategy. This analysis takes into consideration the efficiency of the power delivery Network, PDN, at a Macro and Micro environment.

The analysis is using 3D Simulations techniques based on causal model. With this novel technique, we investigate the potential noise induction through the ground path and isolation. For the conclusion, we suggest a method that improve the PI analysis over a mix signal IC..
Thermal Performance of an Adhesive Bonded Superconducting Multichip Module (MCM) on a Gifford-McMahon Cryocooler
Authors: John Ranjith , Dotsenko Vladimir , Gupta Deepnarayan , Malshe Ajay
Published: October 2015

We report the experimental study of the thermal resistance of a flip chip bonded superconducting multichip module (MCM) in a liquid cryogen free environment. A 5×5 mm2 indium-tin bumped superconducting chip was flip chip bonded on a 1×1 cm2 superconducting carrier chip. A non-conductive adhesive was used as an underfill to enhance the robustness of the package. We designed a test bed where the LSCE module was mounted onto the cold head of a Gifford McMahon (GM) cryocooler. The module was conductively cooled down to 4 K and the thermal resistance between the chip and the carrier chip was analyzed. The experimental results showed that for the power dissipation (2 – 5 mW), which is typical for low temperature superconducting electronic LSCE devices, the thermal resistance was 20.1 +/− 1.9 K/W. Thermal model of the current LSCE package was investigated using COMSOL multi-physics. Theoretical estimates showed that for the current package setup the expected thermal resistance of the bump path to be 6.2 K/W. The discrepancy between the model and experimental analysis has been explained due to the presence of voids and inadequate bump contact area. To our knowledge, this is the first such experimental investigation of the thermal performance of adhesive bonded LSCE package on a cryocooler. This experimental analysis is of paramount importance for future trends in single chip and multichip module packaging of LSCE devices.
Investigating Stress in Hybrid Electronic Packages Using White Light Surface Profilometry
Authors: Folgner Kelsey A. , Tang Ching-Yao , O’Brien Michael J. , Fuqua Peter D.
Published: October 2015

Hybrid electronic packages are often used in space applications because of their rigidity, hermeticity, and good thermal dissipation properties. These properties make them highly reliable in the harsh space environment. However, a recent space application of hybrid electronic packages failed during testing. The failure was traced to cracks in the high temperature co-fired alumina ceramic substrates that resulted in the loss of electrical continuity in some packages. To investigate stress states and crack growth in the packages, a novel technique for stress determination using optical surface profilometry was developed. The technique employs a scanning white light surface profilometer to obtain topographical contour maps of the hybrid electronic packages. Surface curvature reveals the stress state of a component, which can affect its functionality and reliability. By comparing the topography during thermal cycling and de-processing of a fully assembled package, hypotheses regarding the build-up of stress can be investigated.
Bulk and In-Circuit Dielectric Characterization of LTCC Tape Systems Through Millimeter Wave Frequency Range
Authors: Thrasher Bradley , Nair Deepukumar , Parisi James , Oliver Glenn , Smith Michael A.
Published: October 2015

Low Temperature Co-fired Ceramic (LTCC) material systems offer a highly versatile microwave and millimeter wave packaging platform. Extremely low microwave loss, excellent control of dielectric constant, uniform dielectric thickness, non-existent water absorption leading to very high hermeticity, ability to support multilayer structure leading to 3-dimensional packaging, ability to embed passive functions within the tape layers, availability of a wide range of metallizations, etc. are some of the key advantages of LTCC for microwave packaging. One of the important parameters which needs to be determined at the very early stages of circuit designs are the dielectric properties - dielectric constant and loss tangent, both of which are functions of frequency. These properties need to be known accurately over the entire frequency range of operation for the circuit. For LTCC based designs, the use of dielectric constant of bulk material can lead to deviations between the performance expected at the design stage and for the fabricated circuit. Such deviations are a significant concern for broadband circuits as well as for circuits with sharp resonant behavior such as filters. One of the significant sources of deviation between bulk LTCC and “in-circuit” dielectric constant is the nature of the thick film metallizations used in LTCC technology. Work described here is a comprehensive characterization of three DuPont™ GreenTape™ LTCC systems 951, 943, and 9K7 - in the frequency range 10 to 70 GHz. Both bulk and “in-circuit” dielectric properties with silver and gold metallizations are studied to quantify the deviations in dielectric properties. A Fabry-Perot open resonator technique is used for the bulk characterization while printed ring resonators are used for the in-circuit characterization. This comprehensive characterization will provide key design data for LTCC designers in the 10 – 70 GHz frequency range.
Sputter deposition of thin film MIM capacitors on LTCC substrates for RF bypass and filtering applications
Authors: Murray Jack , Huebner Wayne , O’Keefe Matthew J. , Wilder Kristina , Eatinger Ryan , Kuhn William , Krueger Daniel S. , Wolf J. Ambrose
Published: October 2015

Thin film capacitors for RF bypass and filtering applications were sputter deposited onto low temperature co-fired ceramic (LTCC) substrates. The capacitors were configured in a metal-insulator-metal (MIM) design featuring 200 nm thick Al electrodes and a 300 nm thick Al2O3 dielectric layer, with dimensions varied between ∼150×150 μm and ∼750×750 μm. DC current-voltage measurements (E ≤ 5 MV/cm) coupled with impedance analysis (≤15 MHz) was used to characterize the resulting devices. More than 90% of the devices functioned as capacitors with high DC resistance (>20 MΩ) and low loss (tan δ <0.1). A second set of capacitors were made under the same experimental conditions with device geometries optimized for high frequency (≥200 MHz) applications. These capacitors featured temperature coefficient of capacitance (TCC) values between 500 and 1000 ppm/°C as well as low loss and high self-resonant frequency performance (ESR <0.6 Ohms at self-resonance of 5.7 GHz for 82 pF). Capacitance and loss values were comparable between the capacitor structures of similar areas at the different frequency regimes.