(Invited) Resistive Memories (RRAM) Variability: Challenges and Solutions
Authors: Molas Gabriel , Sassine Gilbert , Nail Cecile , Alfaro Robayo Diego , Nodin Jean-François , Cagli Carlo , Coignus Jean , Blaise Philippe , Nowak Etienne 
Published: February 2020

Introduction

Resistive random access memory (RRAM) technologies have experienced an increasing interest as next generation non-volatile memory devices. Thanks to their promising characteristics, RRAM are believed to become a good choice for Storage Class Memory (SCM) [1-3]. Indeed, nowadays, due to popularity of cloud storage and mobile devices, it is urgent to develop lower energy consuming devices with high speed, high density and low cost. On the other hand, as they can be integrated in the BEOL of CMOS logic, they are strongly envisaged for future embedded memory generation [4-5].

RRAM working principle is based on the reversible formation and dissolution of a conductive filament in a resistive layer, resulting from oxygen vacancies generation and diffusion (OxRAM) or dissolution of an active electrode (CBRAM). As filament formation and dissolution is governed by stochastic mechanisms, RRAM features have to be described by statistic laws, and variability has to be carefully considered for RRAM reliability evaluation before industrialization could be envisaged.

In this work, we address Resistive RAM (RRAM) variability. To this aim, we investigate various classes of RRAM (Oxide RAM and Conductive Bridging RAM), integrated on kb 1T1R arrays. Impact of variability is evaluated and discussed for various RRAM features: window margin, switching speed, consumption, retention and endurance. Solutions are proposed in order to improve overall RRAM performances.

Results and discussion

First, we present a general overview of RRAM characteristics, and investigate how performances are correlated. In particular, we show that window margin, endurance and retention are linked. Using electrical characterization combined with atomistic calculations, we demonstrate that the tradeoff is associated to the ion migration energy barrier of the species constituting the conductive filament, and we propose guidelines to optimize RRAM material stack depending on the targeted application.

Then we deeply investigate variability, and we propose solutions to improve RRAM performances.

Window margin variability – We describe RRAM resistance distributions for high and low resistive states and quantify how resistance dispersion affects RRAM window margin, and impacts maximum memory array size. Optimized programming schemes are proposed to reduce resistance dispersion and enlarge window margin.

Consumption and speed – Variability has an impact on RRAM consumption and speed. Indeed, as RRAM switching time is dispersed, long programming pulses may be required to program all the array of a large memory matrix. In order to improve RRAM speed and consumption, Ramp Voltage Stress (RVS) is proposed to program the memory instead of Constant Voltage Stress (CVS) method. Voltage increase in RVS gradually increases programming strength, reducing impact of intrinsic RRAM switching time dispersion.

Retention variability – Filament dissolution in the resistive layer is follows a stochastic behavior, leading to dispersion of memory retention time. In order to improve RRAM retention, we propose to reduce the energy provided to the system during programming modes, reducing ion migration rate and improving RRAM stability during bake.

Endurance variability – We experimentally demonstrate that RRAM maximum number of cycles follows a log normal distribution law. Maximum endurance can be described using physics of dielectric breakdown. We investigate how SET and RESET programming conditions can affect RRAM endurance statistics. Then we propose optimized programming schemes to reduce electrical stress applied to the dielectrics, improving endurance, but maintaining sufficient RRAM window margin.

References

[1] E. Shiu, S. Lim, “Driving innovation in memory architecture of consumer hardware with digital photography and machine intelligence use cases”, proc. of IMW 2017, pp.1-6.

[2] C. Sun et al., “Latency Tails of Byte-Addressable Non-Volatile Memories in Systems”, proc. of IMW 2017, pp.11-14.

[3] C. Cagli et al., “Study of the energy consumption optimization on RRAM memory array for SCM applications”, proc. of IMW 2017, pp.76-79.

[4] J. R. Jameson et al., IEDM 2013 Tech. Dig., pp.30.1.1-30.1.4.

[5] Z. Wei et al., IEDM 2015 Tech. Dig., pp.177-180.