Nonvolatile Memory Characteristics of CdS Embedded Zr-Doped HfO2 High-k
Dielectric MOS Capacitors
Authors: Zhang Shumao , Kuo Yue 
Published: February 2020

The nanocrystals embedded high dielectric constant (high-k) stack is a potential gate dielectric structure to replace the conventional poly-Si floating gate structure in nonvolatile memories (NVMs) for advantages of the low leakage current and improved reliability [1]. Several kinds of materials, such as ITO, ZnO, RuO, and CdSe, have been embedded in high-k dielectrics to attain large memory functions and long charge retention times [2,3]. CdS is another favorable material as the embedded layer for its n-type semiconductor attribute and large electron affinity of 4.3 eV [4]. The Zr-doped HfO2 (ZrHfO) high-k film has excellent bulk and interface properties, e.g., higher crystallization temperature, larger effective k value, and fewer interface states [2]. In this paper, authors investigated the capacitance-voltage (C-V) characteristics of the CdS embedded ZrHfO MOS capacitors.

The ZrHfO/CdS/ZrHfO trilayer stack was deposited on the dilute HF cleaned p-type Si (100) wafer in one pumpdown with breaking the vacuum. The CdS layer was deposited from the CdS target in pure Ar at 5 mTorr and 60 W for 3 or 5 min between the sputter deposition of the tunnel and control ZrHfO layers. The post deposition annealing (PDA) was done at 900oC for 3 min under N2 atmosphere. The detailed device fabrication condition is the same as that described in Ref. 3. Previously, it was reported that the embedded CdSe layer was converted into discrete nanocrystals after the same PDA [2,3]. Therefore, CdS in this study may exist in the nanocrystalline form. However, further verification is required.    

Figure 1 shows the C-V hysteresis curves of the control and CdS embedded samples measured from -4 V to +4 V to -4 V at 1 MHz. Table 1 summarizes parameters calculated from Fig. 1, i.e., capacitance at the accumulation state (C), interface density of states (Dit
), equivalent oxide thickness (EOT), flat band voltage and shift (VFB
and
¢VFB
), and charge trapping densities (Q
ot). The C increases from 3.90×10-11 F for the control sample to 5.25×10-11 F for the CdS (3min) sample and 5.41×10-11 F for the CdS (5min) sample, which corresponds to the decrease of EOT. This is because the embedded CdS layer can reduce the diffusion of O2 to the ZrHfO/Si interface by the oxidization of CdS [5], which reduces the thickness of the interface layer and consequently increases the effective capacitance. On the other hand, since less O2 can reach the ZrHfO/Si interface, fewer Si dangling bonds are passivated and the higher interface density of states is detected. Then, the Dit
increases, i.e., 4.67×1010 cm-2∙eV-1 for the control sample vs 2.45×1011 cm-2∙eV-1 for the CdS (3min) sample and 4.77×1011 cm-2∙eV-1 for the CdS (5min) sample. The control sample shows a very small memory window of 0.049 V, which suggests the few charge trapping sites in the bulk ZrHfO and ZrHfO/Si interface layers. However, when the CdS layer is embedded, the C-V hysteresis window and Qot
increase dramatically, e.g., 0.404 V and 2.04×1012 cm-2 for CdS 3 min embedded sample and 0.498 V and 2.59×1012 cm-2 for CdS 5 min embedded sample.

Figure 2 shows the C-V curves of the CdS embedded samples measured from -2 V to +1 V at 1 MHz before or after being stressed at Vg
=-4 or +4 V for different times. Compared with the fresh sample, the C-V curves of both samples after being stressed at +4 V for 100 s have negligible small shifts, which indicates that the CdS embedded samples have very poor electron trapping capabilities. Nevertheless, after being stressed at -4 V, the C-V curve shifts towards the negative Vg
direction due to the trapping of holes. This shift increases with the increase of stress time, i.e., from 0.12 V after 0.01 s stress to 0.38 V after 100 s stress for the CdS-3min sample and from 0.13 V after 0.01 s stress to 0.61 V after 100 s stress for the CdS-5min sample. Furthermore, because the more CdS is embedded in the high-k stack, the more charge trapping sites are created and the larger C-V curve shift is observed.

[1] Y. Kuo, ECS Trans., 53, 121 (2013).

[2] Y. Kuo, ECS Trans., 35, 13 (2011).

[3] C.-C. Lin et al, JAP., 115, 084113 (2014).

[4] A. Kanevce et al, IEEE J. Photovoltaics., 1, 99 (2011).

[5] M. A. Islam et al, 38th IEEE PVSC, 000152 (2012).

Figure 1