bluuebunny/crossref_metadata_2025 huggingface dataset:
Failure Analysis of Stacked-Die Devices by Combining Non-Destructive Localization and Target Preparation Methods
Authors: Schmidt Christian , Simon Michél , Altmann Frank , Nowodzinski Antoine
Published: December 2020

The paper will present an approach for non-destructive localization of thermal active defects at multi chip devices combining the Lock-in Thermography and following local X-Ray inspection. In combination of both methods inner defects in inter chip connections of complex device built ups can be found in a non-destructive way before opening the device. The methods were demonstrated at defective flip chip devices with a high ohmic daisy chain with lots of chip to chip contacts. Subsequently, cross section analysis at located high ohmic contacts was performed in order to find the root cause of the failure.
Damage Induced Field Failures of Electrical Contacts
Authors: Munukutla Aravind , Rahn Randy , Lewis J.S.
Published: December 2020

Degradation of contact mating surfaces can produce a wide range of problems including intermittent failures and also full functional failures in all computer systems. This paper discusses the complexity involved with investigating the failure mechanism and root cause for intermittent memory failures on a product from end customers. Also discussed in detail is the approach of fault isolation followed by hypothesis development & physical analysis to arrive at root cause of failure. Fault isolation was achieved through register probing. Three major hypotheses were put forth namely plastic debris, misalignment and contact area issues. The physical analysis data collected through optical inspection, 2D x-ray, cross section and SEM analysis coupled with EDX to prove or disprove the hypotheses, revealed contact area corrosion in the form of nickel oxide. Contributors like gold plating thickness and plating porosity of the mating surfaces was verified to be not an issue in this case. Further analysis on the connector pins, memory modules and the contact area indicated damage to the connector pins leading to nickel exposure. The root cause for damage to the pins was analyzed to be a result of memory modules being inserted at an angle. Further studies are planned to look into design issues of connectors and memory modules to minimize damage to the contact area.
Two-Photon X-Variation Mapping Based on a Diode-Pumped Femtosecond Laser
Authors: Serrels K. A. , Reid D. T. , Lundquist T. R. , Vedagarbha P.
Published: December 2020

By inducing two-photon absorption within the device layer of a proprietary silicon test chip, the first nonlinear variant of X-variation mapping is reported by demonstrating frequency mapping of a ring oscillator circuit at 1.55µm.
Quantitative, Nanoscale Free-Carrier Concentration Mapping Using Terahertz Nearfield Nanoscopy
Authors: Wittborn J. , Weiland R. , Huber A. J. , Keilmann F. , Hillenbrand R.
Published: December 2020

We use ultra-resolving terahertz (THz) near-field microscopy based on THz scattering at atomic force microscope tips to analyze 65-nm technology node transistors. Nanoscale resolution is achieved by THz field confinement at the very tip apex to within 30 nm. Images of semiconductor transistors provide evidence of 40 nm (λ/3000) spatial resolution at 2.54 THz (wavelength λ = 118µm) and demonstrate the simultaneous THz recognition of materials and mobile carriers in a single nanodevice. The mobile carrier contrast can be clearly related to near-field excitation of THz-plasmons in the semiconductor regions. The extraordinary high sensitivity of our microscope provides THz near-field contrasts from less then 100 mobile electrons in the probed volume.
Quality Evaluation Techniques of Solar Cell Module
Authors: Murahara Daisuke , Shimizu Wataru , Kubota Hidehisa , Oda Tamiko , Yabe Kazuhiro
Published: December 2020

We have developed a process diagnostics system for photovoltaic energy modules based on standard methods and practices already developed for LSI and MEMS technologies. This paper provides a description of methods used to ensure the conformation of solar cell modules to the rigors of high-quality manufacturing necessary for reliable photovoltaic energy production when exposed to long-term environmental use. We have verified the possibility of inspecting each solar cell and the module assembly in detail for several photovoltaic technologies, specifically monocrystalline Si, polycrystalline Si, and CuInxGa1-xSe2 An objective set of criteria for the quality of each module can be provided by this method for use in module selection by consumers. Moreover, the quality of conformance and reliability data can be used as feedback to the manufacturer to minimize the number of defects created during manufacturing process and ameliorate their effects.
System Level FA on Transmission Line Issues
Authors: Konkol Nicholas
Published: December 2020

One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.
Failure Analysis Power Cycling Tool – FAPCT
Authors: Chua Yi Yun
Published: December 2020

One of the problems for failure analysis (FA) is to perform power cycling to stress the motherboard in order to duplicate the failure. The other problem is the timing is not synchronizing correctly. For this purpose, a user-friendly with extra feature program called Failure Analysis Power Cycling Tool (FAPCT) was developed to resolve problems associated with power cycling and enhance the AC cycling tools, which is more suitable for FA purpose. With this hardware and software, the FAE is provided one more option to duplicate intermittent or other issues that need to do power cycling to capture the failure. The hardware cost is only about 600 USD, which is consider at the lower cost hardware for a FA tools to do power cycling although there is some limitation compare to some hardware available in the market.
Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS
Authors: Pan Zixiao , Wei Wei , Li Fuhe
Published: December 2020

This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.
Innovative Methodologies of Circuit Edit on Wafer-Level Chip Scale Package (WLCSP) Devices
Authors: Liu Shih-Ting , Liu Tao-Chi , Chang Ming-Lun , Lin Jandel
Published: December 2020

Contrary to traditional packages, packaging and testing of wafer-level chip scale package (WLCSP) are done before wafer dicing. The package can’t be rebuilt on a single chip; therefore, the failure analysis and debug performed by Circuit Edit (CE) on ICs with WLCSP face challenges. In addition, there are route designs on the package level of WLCSP devices, which are unique compared with traditional packages. CE is required on both chip and package level of WLCSP devices. This package technology offers the smallest possible package size; consequently, it has seen wider use lately. Developing the approaches of FIB edits on a fully-packaged WLCSP device is indeed essential. Thus, methodologies for CE and debug on WLCSP devices will be explored in this study.
Application of Lock-in Thermography for Backside Failure Localization Using Solid Immersion Lenses
Authors: Schmidt Christian , Große Christian , Altmann Frank , Schulz Jürgen , Seibt Alexander
Published: December 2020

In this paper the application of solid immersion lenses (SIL) in combination with Lock-in Thermography will be demonstrated for backside defect localization. The paper will give an introduction into Lock-in Thermography technique and presents a new developed easy-to-use holding system to adapt SIL for high resolution thermal imaging. It will be shown that defect localization can be applied from the backside of the chip up to a silicon thickness of 250µm using the same SIL. The relationship between the bulk silicon thickness and the resulting optical parameters was investigated.
Fast Mixed Field Material Removal Using New Dielectric Etch Solution
Authors: Makarov Vladimir V. , Krasnobayev Leo , Hahn James
Published: December 2020

A new application of the Novel Dielectric Etch solution for FIB Circuit Edit is reported to allow smooth and fast removal of copper dummies/dielectric layers for exposure of the circuitry underneath. Experimental data on the selectivity of the removal of dummies as a function of the ion beam current density is provided. Examples of de-processing several layers to expose a line of interest as well as the exposure of fine copper lines beneath the copper dummies/dielectric layer are presented.
Resolving the Failure Analysis Challenges on Stacked Die Structure in Lead Frame Chip Scale Package
Authors: Mendaros Raymond G. , Salimbangon Jon Carlo P.
Published: December 2020

Access to critical die and package structures for failure analysis purposes is complicated in stacked die devices in small packages, such as thin plastic Lead Frame Chips Scale Packages also known as Quad Flat No Leads Packages. This paper discusses the failure analysis solutions developed to effectively access the areas of interest. It illustrates two different ways of analyzing the bottom die: a repackaging technique and a technique for accessing from the backside of the bottom die. One of the major concerns during the evaluations that had been addressed was the difficulty of removing the nonconductive die attach material in between the top and bottom die. This was resolved by a novel method of thermal decomposition of the material. Observations suggested that the die extraction process did not introduce surface oxidation or contamination that may have led to a bonding failure.
Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis
Authors: Schuermyer Chris , Benware Brady , Rhodes Graham , Appello Davide , Tancorre Vincenzo , Riewer Olivia
Published: December 2020

This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.
Practical Implementation of Soft Defect Localization (SDL) in Mixed Signal and Analog ICs
Authors: Barbian Eric , Crow Gretchen , Swe Win Thandar , Phillips Mark C.
Published: December 2020

Dynamic Laser Stimulation (DLS) techniques for Soft Defect Localization (SDL) have been well documented for logic devices [1][2]. More recent literature has broadened the traditional SDL pass/fail mapping by employing multiple device parameters including power analysis [3], spectrum response [4], and other analog variations [5]. A practical and efficient implementation of SDL without the use of synchronization or traditional Automatic Test Equipment (ATE) hardware is presented. A dynamic way of analyzing many parameters of mixed signal and analog ICs can be obtained through the use of a high waveform rate oscilloscope, feedback loop, or discrete comparator. Multiple case studies are shown to illustrate the methodology.
A Systematic Failure Analysis to Reveal the Mystery of Lower N-Well Resistance
Authors: Zhu David , Neo Soh Ping , Quah Alfred , Ang Ghim Boon , Zhu Lei , Huang Yanhua , Koo Hong Tak , Yau Moi Kian , Hninhnin Ma , Dayanand Nagalingam
Published: December 2020

In this paper, we will describe a low yield case which revealed itself as leakage failures near the wafer edge. A systematic problem solving approach was used based on the application of a variety of FA techniques such as electrical curve tracing, Spreading Resistance Probing (SRP), Secondary Ion Mass Spectrometry (SIMS), and Chemical Analysis coupled with extensive Fab investigations. These techniques transformed an invisible defect into a visible one, leading to a full resolution of the issue with good understanding of the failure mechanism and the root cause. We will show that the wafer edge leakage was the result of N-type contamination of the substrate due to Phosphorus outgassing from the V-ring during the high temperature Argon anneal process.
From the Store Shelf to Device-Level Atom Probe Analysis: An Exercise in Feasibility
Authors: Larson D. J. , Lawrence D. , Olson D. , Prosa T. J. , Ulfig R. M. , Reinhard D. A. , Clifton P. H. , Kelly T. F. , Lefebvre W.
Published: December 2020

There are many opportunities in semiconductor processing where atom probe tomography (APT) analysis of a finished product is desirable; competitive analysis and failure analysis are two good examples, and only recently have APT results been obtained from fully processed "off-the-shelf" transistor structures that are part of a finished product. This paper explores the feasibility of APT analysis for fully packaged integrated-circuit microelectronic devices by detailing the various options available in specimen preparation and the resulting analyses. The goal of this work is to take an off-the-shelf microelectronics product and perform APT analysis on various device-level components. This work demonstrates that a wealth of high quality information may be obtained from site-specific APT analysis of post-production microelectronic devices. The yield of useful results from such analyses has not yet been determined, but the small number of specimens analyses (four) yielded quality results in the first attempt.
Nano Probe Analysis of Device Characteristics Affected by Ring Type Crystalline Defect
Authors: Lee Jong Hak , Lee Yu Jun , Kim Jung Sam , Jeong Seo Kyung , Kim Min Su , Oh Seok Hoon , Jung Kyoung Wook , Son Soo Yong , Kim Chang Reol
Published: December 2020

In this work, crystalline defects (dislocations) occurred in the silicon substrate during annealing SOD (Spin On Dielectric) which is an easy choice for its superior STI gap-fill ability. The reversal of address data that share same SIO (Signal Input Out) line in a DQ arises from crystalline defects. The failure analysis of physical methods has difficulty finding minute defects within the active because it is scarcely detectable from the top view. Situation can be well understood by electrical analysis using the nano probe. Due to its ability to probing contact nodes around the fail area, a ring type crystalline defect which is hardly detected from the top view was effectively analyzed by 3D TEM with the assistance of nano probe. This work shows that hybrid analysis of electrical method by nano probe and physical method by 3D TEM is useful and effective in failure analysis in semiconductor.
Closer to the Theoretical Limit: Spherical Corrections to Aplanatic Solid Immersion Imaging with Adaptive Optics
Authors: Lu Y. , Ramsay E. , Stockbridge C.R. , Yurt A. , Köklü F. H. , Bifano T. G. , Ünlü M. S. , Goldberg B. B.
Published: December 2020

Aplanatic solid immersion lens (SIL) microscopy is required to achieve the highest possible resolution for next generation silicon IC backside inspection and failure analysis. However, aplanatic SILs are susceptible to spherical aberration introduced by substrate thickness mismatch. We have developed a wavefront precompensation technique using a MEMS deformable mirror and demonstrated an increase in substrate thickness tolerance in aplanatic SIL imaging. Good agreement between theory and experiment is achieved and spot intensity increases by at least a factor of two to three are demonstrated for thicknesses deviating several percent from ideal. This technique is also capable of fixing aberrations due to SIL fabrication, off-axis imaging and refractive index mismatch.
A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries
Authors: Zhihong Mai , Hau Ng Tsu , Khalid Dawood M. , Kee Tan Pik , Lam Jeffrey
Published: December 2020

IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.
Counterfeit IC’s Overview – From a Test Lab’s Perspective
Authors: Loaney Dave
Published: December 2020

Counterfeiting of electronic components continues to be an evolving issue that greatly impacts many companies around the globe. And with so many initiatives that have either been enacted or are in the works, there is a significant amount of confusion and even fear in our industry. The financial impact and potential loss of life related to counterfeit components has become so great that an enormous amount of attention is now being devoted to identifying and mitigating this risk by both private industry and governments agencies around the world. Many companies are reaching out to test labs for both the testing of their components and direction on how to address some of these issues. This paper addresses a few of the questions that our lab is getting from some of our customers regarding counterfeit IC’s and how we have answered those questions. The goal is to provide some additional insight to allow others to address this issue proactively and without fear.
Logic Yield Learning Vehicle Failure Analysis in Technology Development
Authors: Song Zhigang , Beaudoin Felix , Lucarini Stephen , Wu Stephen , Wang Yunyu , Arie Lior , Steiner Kobi
Published: December 2020

With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.
Image and Information Enhancement by Combining Brightfield and Darkfield Optical Images
Authors: Rosales Sonny Benson P. , Badillo Andrew C. , Oblefias Wilma R.
Published: December 2020

Image enhancement algorithm by combining brightfield and darkfield images is presented on this paper. The result combines the unique features of each illumination plus the power of differential interference contrast (DIC) even in the absence of DIC hardware and sophisticated software. The effectivity of the method is illustrated on actual samples with height variation.
Low Temperature Fault Isolation Using Soft Defect Localization
Authors: Staller Kristopher D.
Published: December 2020

Cold temperature failures are often difficult to resolve, especially those at extreme low levels (< -40°C). Momentary application of chill spray can confirm the failure mode, but is impractical during photoemission microscopy (PEM), laser scanning microscopy (LSM), and multiple point microprobing. This paper will examine relatively low-cost cold temperature systems that can hold samples at steady state extreme low temperatures and describe a case study where a cold temperature stage was combined with LSM soft defect localization (SDL) to rapidly identify the cause of a complex cold temperature failure mechanism.
Application of Scanning Probe Microscopy Techniques with Electrical Modules in Via Related Defects
Authors: Wang Xiang-Dong , David Theodore N. , Garteiz Gil , Sanders Paul
Published: December 2020

Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.
Open Failure Diagnosis Candidate Selection Based on Passive Voltage Contrast Potential and Processing Cost
Authors: Pan Yan , Khiam Oh Chong , Ohnmar Nyi , Zhang Chuan , Kannan Sekar , Chittora Atul , Huat Goh Szu , Yinzhe Ma , Nedeau Don , Keat Lim Seng , Lam Jeffrey
Published: December 2020

With a focus on open failure candidates, an extra effort in defining the ease of physical failure analysis (PFA) processing is taken in this paper by closely modeling the PFA processing flow and detailed estimation of the processing cost involved in every step is made. The paper begins with a discussion on the general PFA procedure to process open failure candidates in logic circuits. This is followed by a section that reviews common practice in PFA candidate selection, before proposing the comprehensive selection flow that aims to filter out the easiest candidate in terms of processing cost. This methodology is then evaluated by several case studies and is followed by a discussion on the potential future work. Case studies show that the cost model closely matches with real-world PFA turnaround time and the authors are working toward automating the full flow in software to further improve the efficiency.
Challenges of Small Defect Analysis in Large Analog Power FET Arrays
Authors: Cattey Eric
Published: December 2020

The proverbial needle in the haystack – locating a minute process defect or subtle ESD strike in a large sea of analog output power FETs can be just that. The premise of this paper is to discuss failure analysis techniques used to identify these elusive “needles”, specifically in large array power FET structures. Two case studies will be explored in detail – both of which are 250nm technology devices.
Thermal Laser Stimulation Technique for AlGaN/GaN HEMT Technologies Improvement
Authors: Carisetti Dominique , Sarazin Nicolas , Labat Nathalie , Malbert Nathalie , Curutchet Arnaud , Lambert Benoit , Brunel Laurent , Rousseau Karine , Latu Eddy Romain , Frank Thomas
Published: December 2020

To improve the long-term stability of AlGaN/GaN HEMTs, the reduction of gate and drain leakage currents and electrical anomalies at pinch-off is required. As electron transport in these devices is both coupled with traps or surface states interactions and with polarization effects, the identification and localization of the preeminent leakage path is still challenging. This paper demonstrates that thermal laser stimulation (TLS) analysis (OBIRCh, TIVA, XIVA) performed on the die surface are efficient to localize leakage paths in GaN based HEMTs. The first part details specific parameters, such as laser scan speed, scan direction, wavelength, and laser power applied for leakage gate current paths identification. It compares results obtained with Visible_NIR electroluminescence analysis with the ones obtained by the TLS techniques on GaN HEMT structures. The second part describes some failure analysis case studies of AlGaN/GaN HEMT with field plate structure which were successful, thanks to the OBIRCh technique.
Fault Localization of Metal Defects with Si-CCD Camera in Analog Device Functional Failure
Authors: Alves Stephane , Rousseille Philippe , Zirilli Thomas
Published: December 2020

This paper presents a case study on photon emission from metals and demonstrates the capability of Emission Microscopy Si-CCD camera to detect micro metal bridges on functional failures of Analog devices.
Arsenic Segregation Induced Gate Leakage by TEM Failure Analysis
Authors: Liu Binghai , Zhao Si Ping , Er Eddie , Chen Changqing , Ang Ghim Boon , Mo Zhiqiang
Published: December 2020

High gate to source/drain (S/D) leakage was observed at both failed pins and ET structures with random failure signatures. Detailed TEM failure analysis revealed an abnormal thin Nitrogen-rich nitride layer along the poly gate which extended to the S/D regions. Along the abnormal nitride layer, appreciable Arsenic (As) segregation occurred. The segregated As dopants at these interfaces may form a continuous conducting path, accounting for the gate to S/D leakage mechanism. The preferable As segregation at the Silicon nitride interface may be related to a vacancy-assisted As diffusion process.
Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM
Authors: Lifson Max L. , Chapman Carla M. , Pokrinchak D. Philip , Campbell Phyllis J. , Chrisman Greg S. , Boren Steven J. , Camillo-Castillo Renata A.
Published: December 2020

Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.
Automated Mapping of Very Large Areas of VLSI Circuit Using SIL
Authors: Lin Chung-Ching , Stellari Franco
Published: December 2020

In this paper, we present a novel system and method for the automated mapping of pattern and spontaneous photon emission from very large areas of VLSI circuit using Solid Immersion Lens (SIL). To the best of our knowledge, this is the first time that such a technique has been developed and demonstrated on a real chip. The system being presented includes an automation software Application Programming Interface (API) to control the microscope used to acquire the images, an acquisition software that allows to automatically navigate the chip, move (hop) the SIL to the desired location, focus the image after the SIL landing, register the acquired images, and stitch them together to create a high resolution mosaic. In this paper, we will present, for the first time, a real life example involving thousands of images acquired from a 90 nm bulk technology test chip that were used to create a mosaic of more than 25 x 25 images covering a total area of approximately 400 x 400 μm2.
Evaluation of TEM-Lamella Oxidation
Authors: Haber Thomas , Gspan Christian
Published: December 2020

This study investigated the origin of detrimental high ohmic behavior of contacts by means of analytical electron microscopy. The root cause for the high resistivity could be identified as delamination of the contact bottom in the nanometer range. Based on the results, we were able to establish a method to identify thin oxide layers using analytical methods without being able to spatially resolve them in a combined focused ion beam instrument and scanning electron microscope.
Effective and Efficient FEOL Defects Localization/Inspection by Selective Mechanical/Chemical Deprocessing
Authors: Peng Ng Hui , Angela Teo , Boon Ang Ghim , Hong Yip Kim , Chen Chang Qing , Quah Alfred , Seng Tam Yong , Lam Jeffrey , Mai Zhi Hong
Published: December 2020

With the rapid development of semiconductor manufacturing technologies, IC devices evolve to smaller feature sizes and higher densities, and thus the task of performing successful failure analysis (FA) is becoming increasingly difficult. Device miniaturization often requires high spatial resolution fault isolation and physical analysis [1]. To cater to the shrinking of devices, extensive process improvements have been conducted at the front-end-of-line (FEOL) structures. As a result, among the numerous types of defects leading to chip failure, FEOL defects are becoming more common for devices of advanced tech nodes [2]. Therefore, it becomes more complexity and difficulty on searching the physical defect. Sample preparation is a key activity in material and failure analysis. In order to image small structures or defects it is often necessary to remove excess material or layers hiding the feature of interest. Removing selected layers to isolate a structure is called delayering. It can be accomplished by chemical etching using liquid or plasma chemistry, or by mechanical means, by polishing off each unwanted layer.
Methods to Reconstruct SEM and Optical Probe Tips Using a FIB Tool
Authors: Lepuschenko Walter , Goulet David
Published: December 2020

Various electrical probing and nano probing solutions are offered for semiconductor or failure analysis labs. Using a focused ion beam (FIB) instrument, it is possible to make modifications to probe tips used in optical and SEM probe stations for improved ohmic contact and probe tip durability. The other added benefit is cost reduction by being able to reconstruct damaged tips. This paper shows various FIB techniques and compares reconstructed tip performance with new probe tips.
Al-Cu Alloy Films Characterization and Studies Using TOF-SIMS, XPS, AFM, EBSD and TEM
Authors: Shao J.J. , Shen Y.Q. , Shen Y. , Zhou Y.K. , Li K. , Chou S.Y. , Liu Y.F. , Hao M. , An W.W. , Hua Y.N. , Xing Z.X. , Li X.M.
Published: December 2020

Aluminum-copper alloys are popular for many applications that take advantage of the combination of properties in the alloys. This paper describes the use of multiple advanced failure analysis tools to analyze the physical and chemical properties of Al-Cu alloy thin films.
Foil Capacitor Characterization and Failure Analysis with Special Respect to Noise Filter Applications
Authors: Jacob Peter
Published: December 2020

An increasing number of foil capacitors (metallized thin film capacitors, MTFC) are used as filters in power converters. Thus, they are constantly connected between power lines (different phases) or between power lines and ground. However, after some years of operation, severe damage cases were observed, where filter capacitors became extremely hot and started a slow process of outgasing which sometimes is even ended by catastrophic burning. Failure analysis of surviving capacitors of the same kind in neighbor phases identified air inclusions as the cause, which led to internal corona discharge. Useful corona discharge measurements, based on a modification of the well-known partial-discharge (PD) tests, made it possible to assess capacitors on their potential risk of such failures. It turned out that many, even new foil capacitors, started internal corona discharge already underneath their official AC voltage specification.
Unique Approaches to Isolate Nanoscale Defect in Snake-Comb Test Structure
Authors: Xie Sujing , Wang Nathan , Chen Chaoying , Wu Qindi
Published: December 2020

Multiple techniques including electrical resistance measurement plus calculation, cross-sectional view of passive voltage contrast (XPVC) sequential searching, planar and cross-section STEM are successfully used to isolate a nanoscale defect, single metallic stringer in a snakecomb test structure. The defect could not be found by traditional failure analysis methods or procedures. The unique approach presented here, expands failure analysis capabilities to the detection of nanometer-scale defects and the identification of their root causes. With continuous shrinking feature sizes, the need of such techniques becomes more vital to failure analysis and root cause identification, and therefore yield enhancement in fabrication.
Magneto-Optical Frequency Mapping System for Very Low Resistance Short Circuit Failure Imaging
Authors: Nakamura Tomonori
Published: December 2020

Magnetic field imaging (MFI) has been an excellent tool for a low resistance failure localization in LSI devices. A Superconducting Quantum Interference Device (SQUID) and a Giant Magneto Resistive (GMR) sensor are well known in this field. A SQUID has extremely high magnetic sensitivity (500 nA, <40 pT/ √Hz)[1], but the spatial resolution is somewhat problematic due to the clearance that is needed for cooling and vacuuming mechanism. A GMR sensor has higher resolution but lower sensitivity (50 uA, <10 nT/√Hz)[1] and, they have less flexibility because the sensor/stage has to be scanned during operation. In this paper, we present a new current imaging method called Magneto-Optical (MO) Frequency Mapping (MOFM). The imaging is based on a laser beam scanning, which allows flexibility and ease of use. The MO signal intensity is inversely proportional to the distance between the sensor and the current path to be detected. Since it can be 10 um or less, i.e., one half of the MO crystal thickness, it practically makes the MOFM’s system sensitivity is 10 uA, it only 20 times lower than a SQUID method, even though the intrinsic sensitivity may be about 250 times or so lower. It can also achieve high special resolution as with the GMR sensor because of the short distance or clearance needed to sense the current. These characteristics are verified with a TEG sample and we present a case in which it is applied for the short circuit failure localization.
Analysis of Write Recovery Time Degradation Caused by Adjacent Storage Node Data in DRAM
Authors: Lee Kwangwon , Nam Incheol , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung
Published: December 2020

As microelectronic feature sizes are scaled down, the characteristics and distribution of DRAM data retention time and write recovery time are getting worse. This degradation is due to the increases in the leakage current and resistance of the cell node and the decrease of cell capacitance in DRAM devices. As the physical distance between storage nodes decreases, node potential is increasingly affected by small potential changes in adjacent storage nodes. In this paper, we will show that the one of the most dominant contributors to failure is the adjacent storage node level, and we will demonstrate how node level affects write time delay. The effect of the adjacent storage node level can be correlated with a change in threshold voltage, much like the MOSFET body effect. We define this phenomenon as the lateral body effect, and propose a model for adjacent potential effect using the Buried Cell Array Transistor (BCAT) structure in sub 20nm DRAM.
Implementation of a Visual System to Manage and Improve Failure Analysis Work Flow
Authors: Benz Jason M , Distelhurst Kevin A , Hunt Douglas B , Kontra Rick
Published: December 2020

Many articles and books have been written that discuss and study the techniques of lean thinking and methodologies. The applications of these methodologies have included such industries as manufacturing, health care, and information technology. Application to analytical laboratories has been rare or non-existent due to the inability to apply lean methodologies to a process with ‘unique’ analytical work flows as well as a lack of a direct connection to the manufacturing value stream. The following paper describes the work done in a semiconductor failure analysis laboratory to visualize work flow, design a forecasting model, and create a management system. The result of which has been sustained and improved quality, resource utilization, and delivery of actionable root cause failure analysis.
Symptom or Cause? A Case Study
Authors: Swaminathan Anuradha , Liao Joy , Marks Howard
Published: December 2020

Although there are many advanced technologies and techniques for silicon diagnostics, effective failure analysis to root cause is getting increasingly challenging, as very often the electrical failure analysis data would point to a symptom that is the result of the defect rather than the actual location of the defect. Therefore, a combination of multiple techniques is often employed so that sensitivity of "the cause of the problem" can be observed. This work compiles a successful analysis with the aid of continuous wave laser voltage probing and soft defect localization techniques and presents three cases that are voltage-sensitive fails. The first case is a 28 nm device which failed at-speed scan. The second case is a 28 nm device failing RAM register BIST with high Vmin and the third case is a scan shift failure in a less than 28nm device.
Non-Visible Defect Analysis by the Nanoprobing Methodology
Authors: Chen C.Q. , Ang G.B. , Ng P.T. , Quah A.C.T. , Ng H.P. , Teo A. , Lam J. , Mai Z.H.
Published: December 2020

This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.
LASER Combined with Plasma—Will It Be the Future’s Green and Safe IC Decapsulation Method
Authors: Poirier Patrick , Obein Michael
Published: December 2020

LASER techniques are widely used for pre-opening in combination with a final manual or automated wet chemistry decapsulation. Even if most of the ICs may be opened today, and if opening the recently introduced Ag wires packages have been solved with novel chemical recipes, the need for a greener and safer solution is still there. Plasma techniques combined with LASER can be a promising solution to these challenges. In this paper, after a presentation of the state of the art of the different techniques available in laboratories nowadays, the latest solution combining LASER and acid or plasma etching is presented. The paper compares the results obtained with these solutions on Cu an Ag wires devices with pros and cons for each solution. The results presented show the benefits, the constraints and the limitations of each technique regarding the different types of wires used in industry.
Failure Analysis of ILD Delamination—Uncovering Multiple Root Causes
Authors: Castignolles Marie , Zirilli Thomas , Cattey Eric , Lewenstein Justin , Schauer Steve , Liu Wei , Chen Jeff , Hammett Jake , Subramanian Sam
Published: December 2020

FA cannot consist of simply jumping to conclusions. The FA process is validated through correlation with the initial failure and through interpretation of the obtained results, subjective by definition. This paper illustrates the difficulty of analyzing complex failures caused by multiple factors, including wafer fabrication, assembly, and application conditions. Inter-Layer Dielectric (ILD) delamination was experienced on various ICs from the same 250nm technology. A complete set of techniques (C-SAM, laser and optical microscopy, SEM, FIB cross-sections, TEM, EFTEM, SIMS, Auger, delineation) was used as different pieces of the same puzzle to reveal the multiple factors contributing to the ILD delamination failures. Due to the subtle nature of some of the underlying causes, defining an accurate FA approach with appropriate sample preparation and accurate device traceability was critical to understanding this complex, multivariate issue.
Extending the Resolution of Emission Images beyond Diffraction Limits Using Deconvolution
Authors: Lan Fei , Stellari Franco , Shehata Andrea Bahgat , Song Peilin
Published: December 2020

In this work, we demonstrate the effectiveness of deconvolution algorithms in improving the spatial resolution of time-integrated emission images from integrated circuits. A mathematical model of the Point Spread Function (PSF) encompassing both the optical system and the imaging detector properties is used for the deconvolution process. Tuning of the PSF parameters is achieved through the minimization of dedicated cost functions that optimize image resolution while suppressing artifacts in the deconvoluted images. The optimized PSF is then used in both the Lucy-Richardson (L-R) and blind deconvolution algorithms. Results from 32 nm and 14 nm SOI devices show that the deconvolution process significantly improves spatial resolution of time-integrated emission images, pushing their resolution beyond the diffraction limit of Solid Immersion Lenses (SILs).
A Study on a Low Cost Thin Film Antireflection Coating Solution for Failure Analysis Applications
Authors: Awitan Fritz Christian , Garcia Camille Joyce , Doyle Dirk Andrew , Benedict Lawrence
Published: December 2020

An ARC solution that can be used to improve backside imaging for backside photoemission microscopy applications is presented in this paper. Zinc Oxide (ZnO) -based thin films used as ARCs are deposited at the backside of the failing units through a simple and low cost spray pyrolysis technique. An improvised set-up, composed of an atomizer and a hot plate, is used in the experiment. The paper provides evidence of acceptable process repeatability and demonstrates that the technique and the material have important applications in the field of failure analysis. Furthermore, it shows that the application of ARC resulted in better defect localization. The location of the defect is easily been determined upon doing frontside inspection - to - backside image comparison on the deposited unit. By using high kV ion beam passive voltage contrast (PVC) and angled cut focused ion beam (FIB) cross section, we are able to isolate further and show the nature of the defect at the failing block.
Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture
Authors: Schlangen Rudolf , Colburn Jon , Sarmiento Joe , Nelapatla Bala Tarun , Gupta Puneet
Published: December 2020

Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.
Analysis of Retention Time Degradation Caused by Electrostatic Potential Variation between Adjacent Bit-Line and Adjacent Contact Node in DRAM
Authors: Mok Jungil , Kang Byungki , Kim Daesun , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung
Published: December 2020

Systematic retention failure related on the adjacent electrostatic potential is studied with sub 20nm DRAM. Unlike traditional retention failures which are caused by gate induced drain leakage or junction leakage, this failure is influenced by the combination of adjacent signal line and adjacent contact node voltage. As the critical dimension between adjacent active and the adjacent signal line and contact node is scaled down, the effect of electric field caused by adjacent node on storage node is increased gradually. In this paper, we will show that the relationship between the combination electric field of adjacent nodes and the data retention characteristics and we will demonstrate the mechanism based on the electrical analysis and 3D TCAD simulation simultaneously.
Diamond Probe Applications for Nanoprobing
Authors: Pendyala Sweta , Dalton Andrew , Zumwalt Sean , Miller John
Published: December 2020

As technology continues to scale down, semiconductor devices and circuitry have become more complex. The layouts are more integrated and the devices do not isolate at contact level like they used to. Due to this, nanoprobing cannot always localize the defect to one gate finger and as a result the follow-on physical analysis gets more complicated and time consuming. In this paper, we will explore an approach to simplify a given circuit and localize the failing finger in that circuit by cutting metal lines using diamond nano-probes [1] on the FEI Hyperion Atomic Force Probe (AFP) Platform. We will also describe some of the other applications of diamond nano-probes in facilitating semiconductor failure analysis.
Failure Analysis Case Study of Inductively Coupled Cross-Chip Signals
Authors: Loveless Steven , You Zhihong , Chatterjee Tathagata , Subbannavar Badarish
Published: December 2020

This paper discusses a failure analysis case study in a highly integrated mixed signal device caused by inductive coupling of on-chip signals. The techniques utilized and the approach to root cause analysis are discussed in depth. The interactions between the device design and failure mechanism are identified in detail. Focus is placed on drawing conclusions from the sum of individual data points, and the discussion provides an analytical path by which similar failures can be isolated and specific device sensitivities can be identified.