bluuebunny/crossref_metadata_2025 huggingface dataset:
Supporting systolic and memory communication in iWarp
Authors: Borkar Shekhar , Cohn Robert , Cox George , Gross Thomas , Kung H. T. , Lam Monica , Levine Margie , Moore Brian , Moore Wire , Peterson Craig , Susman Jim , Sutton Jim , Urbanski John , Webb Jon
Published: July 2004

iWarp is a parallel architecture developed jointly by Carnegie Mellon University and Intel Corporation. The iWarp communication system supports two widely used interprocessor communication styles:
memory communication
and
systolic communication
. This paper describes the rationale, architecture, and implementation for the iWarp communication system.

The sending or receiving processor of a message can perform either memory or systolic communication. In memory communication, the entire message is buffered in the local memory of the processor before it is transmitted or after it is received. Therefore communication begins or terminates at the local memory. For conventional message passing methods, both sending and receiving processors use memory communication. In systolic communication, individual data items are transferred as they are produced, or are used as they are received, by the program running at the processor. Memory communication is flexible and well suited for general computing; whereas systolic communication is efficient and well suited for speed critical applications.

A major achievement of the iWarp effort is the derivation of a common design to satisfy the requirements of both systolic and memory communication styles. This is made possible by two important innovations in communication: (1) program access to communication and (2) logical channels. The former allows programs to access data as they are transmitted and to redirect portions of messages to different destinations efficiently. The latter increases the connectivity between the processors and guarantees communication bandwidth for classes of messages. These innovations have provided a focus for the iWarp architecture. The result is a communication system that provides a total bandwidth of 320 MBytes/sec and that is integrated on a single VLSI component with a 20 MFLOPS plus 20 MIPS long instruction word computation engine.
The K2 parallel processor
Authors: Annaratone Marco , Fillo Marco , Nakabayashi Kiyoshi , Viredaz Marc
Published: July 2004

K2 is a distributed-memory parallel processor designed to support a multi-user, multi-tasking, time-sharing operating system and an automatically parallelizing FORTRAN compiler. This paper presents the architecture and the hardware implementation of K2, and focuses on the architectural features required by the operating system and the compiler. A prototype machine with 24 processors is currently being developed.
Big science versus little science—do you have to build it? (panel session)
Authors: Ditzel David R. , Hennessy John L. , Rudin Bernie , Smith Alan Jay , Squires Stephen L. , Zalcstein Zeke
Published: July 2004

Research can be called
big science
if projects have numerous researchers, large funding, significant infrastructure, and plans to build complex tools or prototypes. Most experimental physicists practice big science, as do computer architects who build prototype software-hardware systems.

Conversely, research can be called
little science
when projects have few researchers, modest funding, little special infrastructure, and no plans to build complex tools or prototypes. Most mathematicians practice little science, as do computer architects who study aspects of a design and build confidence in their proposals with models or simulations.

A very simple model contrasting the two approaches is illustrated below, where money flows from governments (GOV) to academia (EDU) which produce ideas for industry (COM) to make better products for all (POP). A key difference is whether governments fund a few, large research projects or many, smaller ones.

The goal of this session is explore whether, when and why universities should do big or little science. Panelists may discuss why big science wastes money, exploits graduate students and makes research too short range. They may argue that little science produces results that are too deep and narrow, oblivious to global systems issues, not properly validated, and too out of touch with reality to ever be practical. Panelists may also find some advantages to both kinds of science.

Panelists include members from government, academia and industry, who are also members of the general population. To keep the discussion lively, nothing said necessarily represents the opinion of any government agency, university or corporation with whom panelists are affiliated.
Multiple instruction issue in the NonStop cyclone processor
Authors: Horst Robert W. , Harris Richard L. , Jardine Robert L.
Published: July 2004

This paper describes the architecture for issuing multiple instructions per clock in the NonStop Cyclone Processor. Pairs of instructions are fetched and decoded by a dual two-stage prefetch pipeline and passed to a dual six-stage pipeline for execution. Dynamic branch prediction is used to reduce branch penalties. A unique microcode routine for each pair is stored in the large duplexed control store. The microcode controls parallel data paths optimized for executing the most frequent instruction pairs. Other features of the architecture include cache support for unaligned double-precision accesses, a virtually-addressed main memory, and a novel precise exception mechanism.
The impact of synchronization and granularity on parallel systems
Authors: Chen Ding-Kai , Su Hong-Men , Yew Pen-Chung
Published: July 2004

In this paper, we study the impact of synchronization and granularity on the performance of parallel systems using an execution-driven simulation technique. We find that even though there can be a lot of parallelism at the fine grain level, synchronization and scheduling strategies determine the ultimate performance of the system. Loop-iteration level parallelism seems to be a more appropriate level when those factors are considered. We also study barrier synchronization and data synchronization at the loop iteration level and found both schemes are needed for a better performance.
Boosting beyond static scheduling in a superscalar processor
Authors: Smith Michael D. , Lam Monica S. , Horowitz Mark A.
Published: July 2004

This paper describes a superscalar processor that combines the best qualities of static and dynamic instruction scheduling to increase the performance of non-numerical applications. The architecture performs all instruction scheduling statically to take advantage of the compiler's ability to efficiently schedule operations across many basic blocks. Since the conditional branches in non-numerical code are highly data dependent, the architecture introduces the concept of
boosted
instructions, instructions that are committed conditionally upon the result of later branch instructions. Boosting effectively removes the dependencies caused by branches and makes the scheduling of side-effect instructions as simple as those that are side-effect free. For efficiency, boosting is supported in the hardware by
shadow structures
that temporarily hold the side effects of boosted instructions until the conditional branches that the boosted instructions depend upon are executed. When the branch condition is determined, the buffered side effects are either committed or squashed. The limited static scheduler in our evaluation system shows that a 1.6-times speedup over scalar code is achievable by boosting instructions above only a single conditional branch. This performance is similar to the performance of a pure dynamic scheduler.
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
Authors: Jouppi Norman P.
Published: July 2004

Projections of computer technology forecast processors with peak performance of 1,000 MIPS in the relatively near future. These processors could easily lose half or more of their performance in the memory hierarchy if the hierarchy design is based on conventional caching techniques. This paper presents hardware techniques to improve the performance of caches.

Miss caching
places a small fully-associative cache between a cache and its refill path. Misses in the cache that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache. Small miss caches of 2 to 5 entries are shown to be very effective in removing mapping conflict misses in first-level direct-mapped caches.

Victim caching
is an improvement to miss caching that loads the small fully-associative cache with the victim of a miss and not the requested line. Small victim caches of 1 to 5 entries are even more effective at removing conflict misses than miss caching.

Stream buffers
prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer and not in the cache. Stream buffers are useful in removing capacity and compulsory cache misses, as well as some instruction cache conflict misses. Stream buffers are more effective than previously investigated prefetch techniques at using the next slower level in the memory hierarchy when it is pipelined. An extension to the basic stream buffer, called
multi-way stream buffers
, is introduced. Multi-way stream buffers are useful for prefetching along multiple intertwined data reference streams.

Together, victim caches and stream buffers reduce the miss rate of the first level in the cache hierarchy by a factor of two to three on a set of six large benchmarks.
A simultaneous multithreading simulator
Authors: Torrant Marc , Shaaban Muhammad , Czernikowski Roy , Hsu Ken
Published: July 2004

The simultaneous multithreaded [1] architecture is an extension of the single-threaded architecture that helps hide the performance penalty created by long-latency instructions, branch mispredictions, and memory accesses. Simultaneous multithreaded architectures use a more flexible parallelism, which takes advantage of both instruction-level, and thread-level parallelism. Additionally, it tends to promote better utilization of available functional units. A model of a simultaneous multithreaded architecture was designed, simulated, and analyzed in order to evaluate design alternatives. The simulator was created by modifying a version of the Simple Scalar tool set, developed at the University of Wisconsin. The simulations provide documentation for an overall system performance improvement of a simultaneous multithreaded architecture. In early simulation results, performed with the same number of functional units, an improvement in the number of instructions per cycle (IPC) of between 43% and 58% was found using four threads versus a single thread.
Achieving the best performance on superscalar processors
Authors: Shahhoseini H. S. , Naderi M. , Nemati S.
Published: July 2004

In this paper the operation of a superscalar processor is studied. An analytical model is developed for computing the throughput and the speedup of the superscalar processors. The throughput is computed as a function of the reoccurrence period of the instructions in the program. It is shown that, when the number of the instructions is sufficiently large, the probability of referring to the different pipes and the number of pipes are more important than the length of the pipes.Also the results show that maximum throughput of a p-issues superscalar processor is equal to p instructions per cycle. This upper bound is reachable if and only if some conditions for reoccurrence period of the instructions in the program are fulfilled. At the end of the paper some remarks related to the structural designing and the number of pipes are offered.
Selective-set-invalidation (SSI) for soft-error-resilient cache architecture
Authors: Hwang Seung H. , Choi Gwan S.
Published: July 2004

This paper proposes a novel cache-memory design for soft-error silence, and verifies the design through a simulation that uses realistic system and software model. The SSI design is a combination of an n-bit error detector and a fast circuit that allows real-time-forced invalidation of corrupted data sets. The current design supports the write through caching policy and will be extended for the write back policy. To verify the effectiveness of the proposed design approach, mixed-mode simulations are conducted that insert soft-errors(bit-flips) into the cache-memory model. The simulation commences while running different class of programs (ALU-intensive and branch-intensive programs) designed to stress several key functions of the target system. System-level failure modes triggered by the soft errors are observed and all inserted errors are recovered by SSI scheme. The performance and layout-area overheads are also quantified. The worst-case performance/time overhead of the SSI scheme is approximately 9% while the lay-out-area overhead is less than 0.5%
Disbursed control computer architecture
Authors: Driker Benjamin
Published: July 2004

Disbursed Control Computer Architecture, comprising totally pipelined computer, a number of components interconnected in a pipeline:Control storage for control and input-output address maker, plurality of other control storage for corresponding plurality of data address makers, and another control storage for operators and operational registers.Any mentioned control storage contains, as a part of a program, a plurality of appropriate section of a control word. Control and input-output address maker issues control address to all mentioned control storage and receives its own section of control word.Plurality of data address makers receives plurality of corresponding sections of control word and issue corresponding plurality of data addresses to operands and results storage, which, in turn, is issuing and receiving data to and from operational registers and bus joint and to condition and status logic.Each clock cycle, new control address initiates new control word, sections of which contain all commands and addresses for enactment of next control and input-output address, by control and input-output address maker, and of next plurality of data addresses, by plurality of data address makers.Following in pipeline, new commands and data submitted to operators and operational registers direct performance of new primary (originated by the task) operations every clock cycle.Several clock cycles are allotted along pipeline to data address makers, allowing the most complex address preparations.Also comprising: interconnect of totally pipelined computer with other computers, operating via input-output devices with separate sending and receiving ports.
Performance evaluation of multimedia systems with MPEG-2 bitstreams
Authors: Khalid Humayun
Published: July 2004

MPEG-2 has become a compression standard for multimedia applications. Performance analysts, designers, and researchers have been using mpeg-2 bitstreams for evaluating the multimedia performance of their systems. There exist a significant difference in the characteristics and behavior of such bitstreams. The bitstream set, used for performance evaluation, that does not demonstrate such variations results in erroneous evaluations and projections. In this paper, we have proposed a methodology for improving the performance estimations/projections with mpeg-2 data. Our simulation results demonstrate variations in the mpeg-2 bitstreams and the consequence it can have when data from only one of the several classes is chosen for system measurement and evaluation
Tracing multimedia benchmarks with five degrees of validation
Authors: Khalid Humayun
Published: July 2004

In this paper we have extended our methodology, presented earlier in [1], for generating and validating representative traces. Our novel technique was applied to a relatively realistic and difficult multimedia benchmark suite called MediaMark. We have also introduced a new metric called the K-metric (
K
halid - metric) that was used for validation. The aim of our present research was to demonstrate that the proposed methodology can be successful even for complex and challenging benchmarks like multimedia benchmarks. Earlier our methodology was shown to be the most successful one as compared to the popular contemporary techniques for tracing relatively simple and primitive suite of applications contained within SPEC™95 benchmark suite [1]. Experimental results in this article demonstrate that our methodology works in the worst case scenarios.
Trace preconstruction
Authors: Jacobson Quinn , Smith James E.
Published: July 2004

Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due to capacity and compulsory misses. Trace preconstruction augments a trace cache by performing a function analogous to prefetching. The trace preconstruction mechanism observes the processor's instruction dispatch stream to detect opportunities for jumping ahead of the processor. After doing so, the preconstruction mechanism fetches static instructions from the predicted future region of the program, and constructs a set of traces in advance of when they are needed.

Trace preconstruction can significantly increase both the performance of the trace cache and the robustness of the trace cache to varying workloads. All but one of the SPECint95 benchmarks see a notable reduction in trace cache miss rates from preconstruction. The three benchmarks that have the largest working set (gee, go and vortex) see a 30% to 80% reduction in trace cache misses. We also consider the integration of preconstruction with another trace-specific mechanism (preprocessing) to produce a high performance frontend. When combined, preconstruction and trace preprocessing produce an average speedup of 14% for the SPECint95 benchmarks.
HLS
Authors: Oskin Mark , Chong Frederic T. , Farrens Matthew
Published: July 2004

As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and symbolic execution to evaluate design alternatives. This simulation methodology allows for quick and accurate contour maps to be generated of the performance space spanned by design parameters. We validate the accuracy of HLS through correlation with existing cycle-by-cycle simulation techniques and current generation hardware. We demonstrate the power of HLS by exploring design spaces defined by two parameters: code properties and value prediction. These examples motivate how HLS can be used to set design goals and individual component performance targets.

Additionally, these traces are not as susceptible to transient behavior because they are restricted to frequently executed code. Empirical results show that on average this mechanism can achieve better instruction fetch rates using only 12KB of hardware than a trace cache requiring 15KB of hardware, while producing long, persistent traces more suited to optimization.
Wattch
Authors: Brooks David , Tiwari Vivek , Martonosi Margaret
Published: July 2004

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.

This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.

We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
A fully associative software-managed cache design
Authors: Hallnor Erik G. , Reinhardt Steven K.
Published: July 2004

As DRAM access latencies approach a thousand instruction-execution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be appropriate. Two key features—full associativity and software management—have been used successfully in the virtual-memory domain to cope with disk access latencies. Future systems will need to employ similar techniques to deal with DRAM latencies. This paper presents a practical, fully associative, software-managed secondary cache system that provides performance competitive with or superior to traditional caches without OS or application involvement. We see this structure as the first step toward OS- and application-aware management of large on-chip caches.

This paper has two primary contributions: a practical design for a fully associative memory structure, the
indirect index cache
(IIC), and a novel replacement algorithm,
generational replacement
, that is specifically designed to work with the IIC. We analyze the behavior of an IIC with generational replacement as a drop-in, transparent substitute for a conventional secondary cache. We achieve miss rate reductions from 8% to 85% relative to a 4-way associative LRU organization, matching or beating a (practically infeasible) fully associative true LRU cache. Incorporating these miss rates into a rudimentary timing model indicates that the IIC/generational replacement cache could be competitive with a conventional cache at today's DRAM latencies, and will outperform a conventional cache as these CPU-relative latencies grow.
Recency-based TLB preloading
Authors: Saulsbury Ashley , Dahlgren Fredrik , Stenström Per
Published: July 2004

Caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. However, TLB misses have become a serious bottleneck as working sets are growing beyond the capacity of TLBs.

This work presents one of the first attempts to hide TLB miss latency by using preloading techniques. We present results for traditional next-page TLB miss preloading - an approach shown to cut some of the misses. However, a key contribution of this work is a novel TLB miss prediction algorithm based on the concept of “recency”, and we show that it can predict over 55% of the TLB misses for the five commercial applications considered.
Memory access scheduling
Authors: Rixner Scott , Dally William J. , Kapasi Ujval J. , Mattson Peter , Owens John D.
Published: July 2004

The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces
memory access scheduling,
a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.
Selective, accurate, and timely self-invalidation using last-touch prediction
Authors: Lai An-Chow , Falsafi Babak
Published: July 2004

Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper proposes
Last-Touch Predictors (LTPs)
that learn and predict the “last touch” to a memory block by one processor before the block is accessed and subsequently invalidated by another. By predicting a last-touch and (self-)invalidating the block in advance, an LTP hides the invalidation time, significantly reducing the coherence overhead. The key behind accurate last-touch prediction is
trace-based correlation,
associating a last-touch with the sequence of instructions (i.e., a trace) touching the block from a coherence miss until the block is invalidated. Correlating instructions enables an LTP to identify a last-touch to a memory block uniquely throughout an application's execution.

In this paper, we use results from running shared-memory applications on a simulated DSM to evaluate LTPs. The results indicate that: (1) our base case LTP design, maintaining trace signatures on a per-block basis, substantially improves prediction accuracy over previous self-invalidation schemes to an average of 79%; (2) our alternative LTP design, maintaining a global trace signature table, reduces storage overhead but only achieves an average accuracy of 58%; (3) last-touch prediction based on a single instruction only achieves an average accuracy of 41% due to instruction reuse within and across computation; and (4) LTP enables selective, accurate, and timely self-invalidation in DSM, speeding up program execution on average by 11%.
Lx
Authors: Faraboschi Paolo , Brown Geoffrey , Fisher Joseph A. , Desoli Giuseppe , Homewood Fred
Published: July 2004

Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software from the beginning to support both scalability (variable numbers of identical processing resources) and customizability (special purpose resources).

In this paper we consider the following issues. When is customization or scaling beneficial? How can one determine the right degree of customization or scaling for a particular application domain? What architectural compromises were made in the Lx project to contain the complexity inherent in a customizable and scalable processor family?

The experiments described in the paper show that specialization for an application domain is effective, yielding large gains in price/performance ratio. We also show how scaling machine resources scales performance, although not uniformly across all applications. Finally we show that customization on an application-by-application basis is today still very dangerous and much remains to be done for it to become a viable solution.
CHIMAERA
Authors: Ye Zhi Alex , Moshovos Andreas , Hauck Scott , Banerjee Prithviraj
Published: July 2004

Reconfigurable hardware has the potential for significant performance improvements by providing support for application-specific operations. We report our experience with Chimaera, a prototype system that integrates a small and fast reconfigurable functional unit (RFU) into the pipeline of an aggressive, dynamically-scheduled superscalar processor. Chimaera is capable of performing 9-input/1-output operations on integer data. We discuss the Chimaera C compiler that automatically maps computations for execution in the RFU. Chimaera is capable of: (1) collapsing a set of instructions into RFU operations, (2) converting control-flow into RFU operations, and (3) supporting a more powerful fine-grain data-parallel model than that supported by current multimedia extension instruction sets (for integer operations). Using a set of multimedia and communication applications we show that even with simple optimizations, the Chimaera C compiler is able to map 22% of all instructions to the RFU on the average. A variety of computations are mapped into RFU operations ranging from as simple as add/sub-shift pairs to operations of more than 10 instructions including several branches. Timing experiments demonstrate that for a 4-way out-of-order superscalar processor Chimaera results in average performance improvements of 21%, assuming a very aggressive core processor design (most pessimistic RFU latency model) and communication overheads from and to the RFU.
Piranha
Authors: Barroso Luiz André , Gharachorloo Kourosh , McNamara Robert , Nowatzyk Andreas , Qadeer Shaz , Sano Barton , Smith Scott , Stets Robert , Verghese Ben
Published: July 2004

The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers.

This paper describes the
Piranha
system, a research prototype being developed at Compaq that aggressively exploits chip multi-processing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.
Early load address resolution via register tracking
Authors: Bekerman Michael , Yoaz Adi , Gabbay Freddy , Jourdan Stephan , Kalaev Maxim , Ronen Ronny
Published: July 2004

Higher microprocessor frequencies accentuate the performance cost of memory accesses. This is especially noticeable in the Intel's IA32 architecture where lack of registers results in increased number of memory accesses. This paper presents novel, non-speculative technique that partially hides the increasing load-to-use latency, by allowing the early issue of load instructions. Early load address resolution relies on register tracking to safely compute the addresses of memory references in the front-end part of the processor pipeline. Register tracking enables decode-time computation of register values by tracking simple operations of the form reg±immediate. Register tracking may be performed in any pipeline stage following instruction decode and prior to execution.

Several tracking schemes are proposed in this paper:

Stack pointer tracking allows safe early resolution of stack references by keeping track of the value of the ESP register (the stack pointer). About 25% of all loads are stack loads and 95% of these loads may be resolved in the front-end.

Absolute address tracking allows the early resolution of constant-address loads.

Displacement-based tracking tackles all loads with addresses of the form reg±immediate by tracking the values of all general-purpose registers. This class corresponds to 82% of all loads, and about 65% of these loads can be safely resolved in the front-end pipeline.

The paper describes the tracking schemes, analyzes their performance potential in a deeply pipelined processor and discusses the integration of tracking with memory disambiguation.
Load-store optimization for software pipelining
Authors: Dai Min , Eisenbeis Christine , Touati Sid-Ahmed-Ali
Published: July 2004

Software pipelining can generate efficient schedules for loop by overlapping the execution of operations from different iterations in order to exploit maximum Instruction Level Parallelism (ILP). Code optimization can decrease total number of calculations and memory related operations. As a result, instruction schedules can use freed resources to construct shorter schedules. Particularly, when the data is not presented in cache, the performance will be significantly degraded by memory references. Therefore, elimination of redundant load-store operations is most important for improving overall performance. This paper introduces a method for integrating software pipelining and load-store elimination techniques. Moreover, we demonstrate that integrated algorithm is more effective than other methods.
Automatic memory layout transformations to optimize spatial locality in parameterized loop nests
Authors: Clauss Philippe , Meister Benoît
Published: July 2004

One of the most efficient ways to improve program performances onto nowadays computers is to optimize the way cache memories are used. In particular, many scientific applications contain loop nests that operate on large multi-dimensional arrays whose sizes are often parameterized. No special attention is paid to cache memory performance when such loops are written. In this work, we focus on spatial locality optimization such that all the data that are loaded as a block in the cache will be used successively by the program. Our method consists in providing a new array reference evaluation function to the compiler, such that the data layout corresponds exactly to the utilization order of these data. The computation of this function concerns the field of parameterized polyhedra and Ehrhart polynomials.
A compiler optimization paradigm for dynamic energy management
Authors: Tyagi Akhilesh , Lee Gyungho
Published: July 2004

We present a compiler and microarchitecture assisted framework for dynamic energy monitoring by a program. The programs will perform an ealloc (The operating system will support energy allocation through a program level utility ealloc similar to the dynamic memory allocation primitives such as malloc.) before entering every logical algorithm such as sorting, FIR filter, convolution. Based on the actual energy allocated by the OS (return parameter of ealloc), a program will enter one of its many variants each consuming different amount of energy through an eswitch. The compiler needs to monitor energy more frequently, probably as often as once every basic block. The existing instruction level energy models can be used. Assuming reasonably accurate instruction level energy models, the compiler can compute fairly accurate energy value for a basic block. However, the uncertainty of the control flow paths makes it close to impossible for the compiler to maintain the program level energy value. We introduce a new semantics for the branch instructions to get around this problem. A branch instruction in addition to branch condition and target offset also contains two more fields:
taken
basic block energy, and
not taken
basic block energy. The microarchitecture is assumed to maintain an energy counter (EC) which is program visible. The branch instruction also modifies the EC by adding to it the energy of the
taken
or
not taken
basic block based on branch condition. The EC thus provides an exact model of program energy consumed until that point. An instruction to clear EC (make it zero) will allow the compiler to use EC to track energy used between some two fixed points in the program. The compiler can now insert transformations that are conditional upon EC.
Internet Nuggets
Authors: Thorson Mark
Published: July 2004

This column consists of selected traffic from the
comp.arch
newsgroup, a forum for discussion of computer architecture on Internet--- an international computer network.
Firefly: a multiprocessor workstation
Authors: Thacker Charles P. , Stewart Lawrence C.
Published: July 2004

Firefly is a shared-memory multiprocessor workstation that contains from one to seven MicroVAX 78032 processors, each with a floating point unit and a sixteen kilobyte cache. The caches are coherent, so that all processors see a consistent view of main memory. A system may contain from four to sixteen megabytes of storage. Input-output is done via a standard DEC QBus. Input-output devices are an Ethernet controller, fixed disks, and a monochrome 1024 x 768 display with keyboard and mouse. Optional hardware includes a high resolution color display and a controller for high capacity disks. Figure 1 is a system block diagram.The Firefly runs a software system that emulates the Ultrix system call interface. It also supports medium- and coarse-grained multiprocessing through multiple threads of control in a single address space. Communications are implemented uniformly through the use of remote procedure calls.This paper describes the goals, architecture, implementation and performance analysis of the Firefly. It then presents some measurements of hardware performance, and discusses the degree to which SRC has been successful in producing software to take advantage of multiprocessing.
Parallel computers for graphics applications
Authors: Levinthal Adam , Hanrahan Pat , Paquette Mike , Lawson Jim
Published: July 2004

Specialized computer architectures can provide better price/performance for executing image processing and graphics applications than general purpose designs. Two processors are presented that use parallel SIMD data paths to support common graphics data structures as primitive operands in arithmetic expressions. A variant of the C language has been implemented to allow high level language coding of user applications on these processors. High level programming support is designed into the processor architecture that implements parallel object data typing and parallel conditional evaluation in hardware.
LIDE
Authors: Petit S. , Gil J. A. , Sahuquillo J. , Pont A.
Published: July 2004

Shared Virtual Memory (SVM) systems are organizations of Distributed Shared Memory systems (DSM). These systems offer a shared memory programming model that is more intuitive than the message passing paradigm. Other advantages include low hardware and maintenance costs. This paper introduces a new simulation environment for such architectures. The developed tool is an execution-driven simulator aimed at studying the behavior of memory consistency models, with the exception of those needing compiler modifications. Thus, we propose a cheap and flexible way to design efficient consistency approaches for SVM systems.
SAMP: a general purpose processor based on a self-timed VLIW structure
Authors: Nowak Lothar
Published: July 2004

A high-performance, general purpose processor has been designed, using various technology independent methods to improve performance. Its structure offers a large degree of parallelism and is adjusted to the application. A novel control unit, which asynchronously controls instruction execution by tokens, allows the evaluation of very complex expressions without any reference to clock cycles. The main memory communicates via 4 ports with the processor and avoids a bottleneck in accessing data. The processor performance is measured and compared with several commercial systems.
Direct execution lisp and cell memory
Authors: Chiang Y. P. , Manwaring M. L.
Published: July 2004

Lisp is the second oldest programming language in use today. It was treated as a special language for AI applications until the recent trend towards symbolic processing. The advantages of Lisp in processing symbols sometimes are outweighted by the inefficient implementations. This paper presents a direct execution approach in implementing Lisp. The concept of direct execution is explained. The Lisp execution environment is analyzed. The cell memory architecture is presented as the efficient solution for direct execution Lisp. This memory structure reduces the number of bits required for implementing garbage collection algorithm and the number of memory cycles for Lisp programs. Several examples are given to elaborate the direct execution concept and the advantages of cell memory. This direct execution Lisp machine has built-in functions such as interrupt and I/O which are major functions for real-time application.
Multiprocessor enhancements of the SimpleScalar tool set
Authors: Manjikian Naraig
Published: July 2004

This paper describes multiprocessor enhancements of the SimpleScalar tool set. The core simulation code has been modified to support multiprocessing, and a run-time library has been introduced for thread creation and synchronization. Measurements using the SPLASH-2 parallel benchmark suite [13] indicate that the multiprocessor enhancements introduce simulation overhead of 30%-50% relative to the original uniprocessor simulator. An idealized multiprocessor cache simulator has also been developed, and a dynamic visualization tool for cache coherence has also been developed. These multiprocessor enhancements are available at the WWW site for the SimpleScalar tool set.
Emerging opportunities for binary tools
Authors: Srivastava Amitabh
Published: July 2004

In recent years, binary instrumentation and optimization tools have been used effectively to understand and improve performance of significant programs. However, new opportunities are emerging in the distributed computing model of the Internet that has strong requirements for reliability and performance. These systems demand continuous operations in presence of open-ended design where some parts may be operated by third party services. Because we cannot reproduce the scale and complexity of this environment on our desktops or in our labs, our traditional testing-based approaches to correctness and performance optimization will prove insufficient; these tasks must extend beyond the traditional idea of product development.In the past, compilation has been about turning source code into executables, balancing compilation speed against code optimization. Binary tools "hacked" their way into the compilation process by intercepting and transforming executables; binary modification stage was not designed to be part of the compilation process. In the new environment, the definition of compilation must broaden: compilation will start very early---perhaps when we write the specification of a program---and continues very late---perhaps through all the program's various executions on the client machines.This dynamic and heterogeneous environment provides great challenges and opportunities to expand the role of binary tools. This talk discusses the new opportunities and requirements for binary tools. It also describes Vulcan, a second generation technology that is designed to address some of these challenges. Vulcan has both static and dynamic code modification capabilities. It can provide system level analysis with heterogenoeus programs. Vulcan works in the Win32 environment and can process x86, IA64, and MSII binaries. Vulcan can process large commercial applications and has been used to improve performance and reliability of Microsoft products in a production environment.
A dynamic binary translation approach to architectural simulation
Authors: Cain Harold W. , Lepak Kevin M. , Lipasti Mikko H.
Published: July 2004

We present the design of a PowerPC-based simulation infrastructure for architectural research. Our infrastructure uses an execution-driven out-of-order processor timing simulator from the SimpleScalar tool set. While porting SimpleScalar to the PowerPC architecture, we would like to remain compatible with other versions of SimpleScalar. We accomplish this by performing dynamic binary translation of the PowerPC instruction set architecture to the SimpleScalar instruction set architecture, and by mapping the PowerPC architectural state onto the SimpleScalar register set. Using this infrastructure, we execute unmodified PowerPC binaries on an out-of-order processor timing simulator which implements the SimpleScalar architecture. We describe and investigate trade-offs in the translation of some complex PowerPC instructions and advocate adoption of
speculative decode
to optimize instruction translations for the common case. We find that simple decode predictors can reach better than 90% accuracy for guiding speculative decode.
JiTI
Authors: Ronsse Michiel , De Bosschere Koen
Published: July 2004

In this paper, we describe JiTI, a novel technique for instrumenting program binaries. The technique correctly deals with programs that contain traditionally hard to instrument features such as data in code, code in data, and self-modifying code. The technique does not require reverse engineering, program understanding tools or heuristics about the compiler or linker used. The basic is that a running process is cloned in memory, and that the cloned process is completely instrumented (code + data). By using the code of the instrumented process (clone) on the data of the original process, we can guarantee a correct instrumentation of the full code while keeping the process data untouched. JiTI has been completely implemented for SPARC processors and is used in a data race detector.
Optimization and precise exceptions in dynamic compilation
Authors: Gschwind Michael , Altman Erik
Published: July 2004

Maintaining precise exceptions is an important aspect of achieving full compatibility with a legacy architecture. While asynchronous exceptions can be deferred to an appropriate boundary in the code, synchronous exceptions must be taken when they occur. This introduces uncertainty into liveness analysis since processor state that is otherwise dead may be exposed when an exception handler is invoked. Previous systems either had to sacrifice full compatibility to achieve more freedom to perform optimization, use less aggressive optimization or rely on hardware support.In this work, we demonstrate how aggressive optimization can be used in conjunction with dynamic compilation without the need for specialized hardware. The approach is based on maintaining enough state to recompute the processor state when an unpredicted event such as a synchronous exception may make otherwise dead processor state visible. The transformations necessary to preserve precise exception capability can be performed in linear time.