bluuebunny/crossref_metadata_2025 huggingface dataset:
Preparation of Bismuth Telluride Compound Semiconductors Through Thin Film Reactions
Authors: Liao Chien-Neng , She D. H. , Liao B. J. , Kuo S. W.
Published: November 2006

Thermal management of integrated circuits (IC) chips has become a critical issue because of poor heat dissipation induced performance degradation and reliability concerns. Lately, thin-film type thermoelectric micro-cooler is being considered as a potential solution to the chip cooling problem. Hence, high quality thin film thermoelectrics becomes essential in making such micro cooling devices. In this study the preparation and characterization of the bismuth telluride compound semiconductor in thin film forms were conducted. The Bi-Te thin films were prepared using sequential sputter deposition followed by thermally induced Bi/Te interfacial reactions. The best Bi-Te thermoelectric thin film obtained has the Seebeck coefficient of -202 uV/K, the resistivity of 2.3x10-3 ohm-cm, and the thermal conductivity of 0.71 W/m-K after the Bi/Te bilayer samples were annealed at 200 C for 24 hours. The effects of process parameters and annealing conditions on thermoelectric properties of the Bi-Te composite thin films are also discussed.
Fabrication processing of ZnO-Based LEDs
Authors: Chen Jau-Jiun , Li Yuanjie , Jang Soohwan , Anderson Travis , Fan Ren , Kim Hyun-Sik , Gila Brent , Norton David , Pearton Stephen , Rawal S. , Osinsky A. , Dong J. W. , Chu S. N. G.
Published: November 2006

To create efficient ZnO-based LEDs, it is important to develop practical etching process and optimize Ohmic contacts on ZnO. Wet etch rates at 25{degree sign}C for Zn0.95Cd0.05O grown on sapphire substrates by rf plasma-assisted molecular beam epitaxy were in the range 30-90 nm min-1 using HCl/H2O and H3PO4/H2O (2x10- 3-3.5x10-3 M) solutions. A comparison of Ti/Al/Pt/Au and Ti/Au Ohmic contacts on n-type Zn0.95Cd0.05O layers grown on ZnO buffer layers with GaN/sapphire templates shows a minimum contact resistivity of 2.3x10-4 Ω-cm2 obtained at 500{degree sign}C for Ti/Al/Pt/Au and 1.6x10-4 Ω-cm2 was obtained at 450{degree sign} C for Ti/Au. Ti/Au Ohmic contacts on heavily Al-doped (n~1019 cm-3) n-ZnO produce a low specific contact resistivity of 2.4x10-7 Ω- cm2 in the as-deposited condition and extremely low minimum values of 6x10-8 Ω-cm2 after annealing at 300{degree sign}C.
Work Function Characterization of TaSiN and TaCN Electrodes Using CV, IV, IPE and SKPM
Authors: Xiong Hao , Nguyen Nhan , Kopanski Joshep , Suehl John , Vogel Eric
Published: November 2006

Work function of TaSiN (TaCN) films on HfO2 or SiO2 gate dielectrics is investigated for the first time using a combination of Capacitance-Voltage, Fowler- Nordheim tunneling, internal Photoemission, and scanning Kelevin probe microscopy methods, which consistently show ~0.2 eV work function difference between these two metals. These results indicate that Fermi-level pinning on HfO2 is not an issue for these metal systems. SKPM gives qualitative results. Beveled structure and complicated modeling are needed for the potential quantitative application of SKPM in metal/high-k systems. The capacitive-voltage and internal photoemission measurements were performed on the same test structures. Work function values extracted from these two methods agree well.
Influence of Process Parameters on Leakage Current of Metal-Organic based HfSiOx Dielectrics
Authors: Avellan Alejandro , Patz Matthias , Erben Elke , Ivanov Alexey , Kudelka Stephan
Published: November 2006

The influence of the deposition parameters pressure and temperature on the energetic trap depth within the hafnium silicate (HfSiOx) dielectric is investigated. Since the leakage current in this material is dominated by trap-assisted and Poole-Frenkel tunneling, the trap distribution plays a key role in defining the leakage. It is found that the deposition parameters change the trap depth by more than 0.3eV. The impurity content correlates with this observation. By choosing the proper process parameters, the leakage current can easily be tuned to fulfill the requirements for Deep Trench DRAM capacitor application.
Experimental Study of the Impact of SO Phonon Scattering in High-K Gate Dielectric MOSFETs
Authors: De Souza Maria M. , Atarah Samuel , Peterson J. , Bersuker Gennadi , Brown G. , Young C.
Published: November 2006

The phonon limited carrier mobility in MOSFETs is found to be accurately described by an exponential relationship over a wide range of temperature and electric field. It is shown that low temperature mobility is more sensitive to SO phonon scattering in comparison to high temperature mobility. Hence the impact of SO phonon scattering is not readily discernable using the conventional power law which shows significant deviation at low temperatures from experiment. A combination of poly-Si/Hf Silicate results in complete recovery of mobility at 150K whereas TiN/HfO2 remains degraded by 35%. A metal gate enhanced the HfO2 mobility by about 50%.
Interface States in Hf-Based Stacks and their Impact on the Reliability of these Alternative Oxides
Authors: Garros Xavier , Reimbold Gilles , Martin Francois , Louveau Olivier
Published: November 2006

This paper investigates interface states in Hf-based devices with metal gate. By electrical measurements we first show that the interface defects of HfO2 stacks are very similar to those of conventional SiO2 oxides. To passivate these defects forming gas anneals FGA under N2/H2 can be performed at high temperature T>500{degree sign}C in Hf-based oxide. We also propose for the first time the use of an atomic H0 plasma performed at low temperature T~300{degree sign}C to passivate these interface defects. Finally we investigate the impact of the interface states on the reliability of High-K dielectrics. The interface state generation in HfO2 oxides annealed by FGA is similar to the one induced by NBTI stress in SiO2. On the other hand, in H0 annealed samples, degradation is enhanced due to plasma charging in the oxide. But some of the interface degradations induced by PID can be cured by standard thermal treatments.
Analysis of Electronic Structure of High-K Films using STEM-EELS
Authors: Ikarashi Nobuyuki , Manabe Kenzo , Takahashi Kensuke , Saitoh Motofumi
Published: November 2006

Electron energy-loss spectroscopy in a scanning transmission electron microscope (STEM-EELS) and ab initio electronic structure calculations were used to analyze how the chemical composition of a HfxSi1-xO2 film affects the electronic structure near the bandgap. We first show that the bandgap of Hf-rich HfxSi1-xO2 (x ≥ 0.5) is identical to that of HfO2 because the energy gap between O 2p and Hf 5d states determines their bandgaps, and because Si-derived states barely affect the energy gap between O 2p and Hf 5d states in HfxSi1-xO2. Second, we show that incorporation of N into a HfxSi1-xO2 film changes the valence band structure and reduces the bandgap. Finally, we show that these results can explain the previously reported chemical composition dependency of the dielectric constant of HfxSi1-xO2 and the N concentration dependency of the dielectric constant of N-incorporated HfxSi1-xO2.
Structural and Chemical Investigation of Annealed Al2O3 Films for Interpoly Dielectric Application in Flash Memories
Authors: Alessandri Mauro , Piagge Rossella , Caniatti Massimo , Del Vitto Annalisa , Wiemer Claudia , Pavia Giuseppe , Alberici Stefano , Bellandi Enrico , Nale Angeloclaudio
Published: November 2006

One of the candidates for the Oxyde-Nitride-Oxyde replacement in next generations Flash Non Volatile Memories is aluminum oxide deposited by Atomic Layer Deposition, which guarantees excellent film conformality, a feasible dielectric constant and low leakage current (1). Al2O3 films are grown in an ALD reactor at 300{degree sign}C using Trimethylaluminium and H2O as precursors. The impact of NH3 and O2 post deposition treatments on Al2O3 thermal stability up to N2 Rapid Thermal Process (RTP) at 1030{degree sign}C has been investigated. After RTP, while the O2 treatment prevents N incorporation and does not induce any crystallographic modification of the Al2O3 layer, the NH3 treatment causes an increase of the N content in the film and induces a reduction of the preferential orientation of the crystallized Al2O3 grains. Actually, the crystallization on set temperature is shifted to higher temperatures when Al2O3 is exposed to NH3 treatment before RTP.
Threshold Voltage Instability and Low Frequency Noise in Hafnium-Based Gate Dielectrics
Authors: Crupi Felice
Published: November 2006

This paper focus on two of the main reliability problems observed in Hafnium-based gate dielectrics: threshold voltage instability and low frequency noise. Both issues are ascribed to the Hf-Si bonds generated at the HfO2/polysilicon interface. These defects act as charge capture centers whose trapping probability decreases with the inverse of the number of injected charges. In the case of HfO2/polysilicon gate stack the drain low frequency noise increases of two orders of magnitude and the gate low frequency noise increases of three orders of magnitude with respect to SiO2/polysilicon gate stack. By using HfSiON as gate dielectrics or metal as gate electrode both reliability problems are strongly reduced.
Improvement in NBTI of Metal Gate pMOSFETs with Sub-1nm EOT HfSiON Gate Dielectric by Ar/N2/H2(D2) Plasma Nitridation
Authors: Inumiya Seiji , Aoyama Takayuki , Nara Yasuo
Published: November 2006

In order to improve the NBTI of pMOSFETs with ultra-thin HfSiON gate dielectrics, a novel plasma nitridation process has been developed. Inclusion of hydrogen in the plasma nitridation ambient brings about an increased NBTI lifetime of about half an order of magnitude. The improvement is due to the suppression of bulk hole traps, presumably originating from the Hf-N bond. Hydrogen in the plasma ambient is thought to prevent the formation of additional Hf-N bonds during post- nitridation annealing.
Reliability and Stability Issues for Lanthanum Silicate as a High-K Dielectric
Authors: Lichtenwalner Dan , Jur Jesse S. , Kingon Angus I. , Novak Steven , Misra Veena
Published: November 2006

Lanthanum silicate gate dielectric MIS devices have been studied in relation to material stability and device reliability. Uncapped dielectric films 2 nm thick exposed to air for 7 months show very little increase in hydroxide formation (~2%, determined by XPS) if experiencing an initial high temperature anneal (1000{degree sign}C, 10 sec). Likewise, after an initial 1000{degree sign}C anneal, MIS device characteristics show no appreciable change over this time period. Negative bias temperature instability measurements on MIS devices at 100{degree sign}C and -2.5 V reveal process-temperature-dependent midgap voltage shifts, with negative shifts (>50 mV) observed for <=900{degree sign}C processing indicating predominantly hole trapping, and small (10 mV) positive shifts for samples experiencing a 1000{degree sign}C process temperature, well within accepted device reliability limits. These results indicate that lanthanum silicate will not introduce significant device lifetime issues when optimally processed.
Electronic Structure Of Defects In Dielectrics With Electronic Correlation
Authors: Fiorentini Vincenzo , Filippetti Alessio , Lopez Giorgia
Published: November 2006

A consistent and accurate calculation of the electronic levels of defects in insulators is still difficult despite all advances in ab initio techniques. Here we report applications of a density-functional-based self-interaction corrected method to defect in oxides exhibiting different degrees of electronic correlation. that Fundamental gaps agreeing well with experiment can be obtained even where conventional techniques give metallic behavior. We analyze the electronic and charging levels of a selection of defects in oxides of technological interest (O vacancy in HfO2, and LaAlO3, Mn in CuO, and O interstitial in YBa2Cu3O6). The calculated properties exhibit an improved consistency, sometimes qualitative, over previous treatments.
Electronic Structure of Bulk and Defected CaCu3Ti4O12
Authors: Alippi Paola , Fiorentini Vincenzo , Filippetti Alessio
Published: November 2006

The calcium copper titanate CaCu3Ti4O12 is a distorted perovskite exhibiting a giant dielectric constant with non-ferroelectric temperature behavior. Recent investigations tend to attribute the origin of the anomalous behavior of CaCu3Ti4O12 dielectric properties to the presence of heterogeneous microstructure and grain boundary layers, excluding that the giant dielectric constant is present in perfectly stoichiometric, defect-free crystals. The intrinsic origin is also ruled out by the normal dielectric behavior obtained in ab initio Density Functional Theory (DFT) calculations. In this work, we present ab initio calculations performed to estimate the energies associated with the creation of defects in the CaCu3Ti4O12 lattice, including oxygen and copper vacancies, and investigate their electronic properties. Furthermore, with a view at ascertaining whether correlation effects may modify the electronic structure and dielectricity of CaCu3Ti4O12, we present an application to CaCu3Ti4O12 of a DFT-based pseudo-selfinteraction-correction (pSIC) method already applied successfully to Mott insulators.
On the Issue of Work Function Tuning of Nickel Silicide Gates
Authors: Biswas Nivedita , Lee Bongmook , Misra Veena
Published: November 2006

The mechanism of work function tuning in NixSiy gates was investigated critically. Furthermore, the role of the underlying dielectric (SiO2 and high-k materials) was also evaluated and it was found that the work function tuning mechanism strongly depends upon the concentration of SiO2 in the dielectric. Ternary alloy silicides NixTa1-xSi and NixPt1-xSi were investigated as possible gates for NMOS and PMOS application repectively. Phi m of 4.27eV and 5.1eV was achieved for the cases of Ta rich and Pt rich silicides on SiO2. However , the window of Phi m range reduced as hafnium was added to the dielectric such that for the case of HfO2 dielectric, the range reduced to 200meV. We attribute this to Fermi level pinning due to increase in Hf+Si bonds. Critical investigation of the role of dielectric-metal gate interface was carried out. Results of varying the Ni and Si composition on SiO2, HfO2 and HfSiOx dielectrics and resulting variation of EOT and Phi m are compared. We report dielectric surface related possible phase modulation of NixSiy gates. To understand the co-relation of EOT variation with work function of the metal gate, top interface of HfSiOx was modulated and the results of such modulation affected increase in the Phi m tuning.
Wide Controllability of Flatband Voltage in La2O3 Gate Stack Structures - Remarkable Advantages of La2O3 over HfO2 -
Authors: Ohmori Kenji , Ahmet Parhat , Shiraishi Kenji , Yamabe Kikuo , Watanabe Heiji , Akasaka Yasushi , Umezawa Naoto , Nakajima Kiyomi , Yoshitake Michiko , Nakayama Takashi , Chang Kao-Shuo , Kakushima Kuniyuki , Nara Yasuo , Green Martin L. , Iwai H. , Yamada Keisaku , Chikyow Toyohiro
Published: November 2006

We have achieved a remarkably wide range (~1.2 V) of differences in flatband voltage (Vfb) by using a combination of metal alloy (Pt-W)/La2O3 gate stacks. The controllable range is about 3 times greater than that of Hf-based gate stacks. The wide range of Vfb can be maintained even after annealing in forming gas and oxidizing gas ambients. We consider that this is attributed to charge transfer at the Pt- La2O3 interfaces inducing increase in the effective work functions, especially at high Pt composition ratios. We believe that La2O3 is one of the most promising high-k dielectric materials for future CMOS devices in 32nm-node and beyond.
Materials and Processes for High k Gate Stacks: Results from the FEP Transition Center
Authors: Osburn Carl , Campbell Steve , Demkov Alex , Eisenbraun Eric , Garfunkel Eric , Gustafsson Torgny , Kingon Angus I. , Lee Jack , Lichtenwalner Dan , Lucovsky Gerry , Ma T.P. , Maria Jon-Paul , Misra Veena , Nemanich Robert , Parsons Greg , Schlom Darrell , Stemmer Susanne , Wallace Robert M. , Whitten Jerry
Published: November 2006

A wide variety of materials and processes for high k dielectrics and metal gate electrodes have been studied as replacements for poly-Si/SiO2 or SiON in advanced CMOS devices. Care must be taken with the interfacial layer to control not only the nitrogen content but its spatial location. Nanocrystallization of the high k dielectric and the corresponding formation of charge and trapping levels associated with defects in the dielectric present one of the current challenges. Control of the workfunction of the gate electrode is shown to depend on many variables, including oxygen content and the material used for the capping layer on the metal gate. The hafnium oxide family of materials, along with metal alloy gates, is seen to provide the best solution for equivalent oxide thicknesses (EOT's) < 0.7 nm, but higher k dielectrics and thinner interfacial layers are needed below 0.7 nm.
Towards the Fabrication of Ultra-Thin SOI on Si (001) using Epitaxial Oxide and Epitaxial Semiconductor Growth Processes
Authors: Lichtenwalner Dan , Hydrick Jennifer M. , Vankova Viera , Maria Jon-Paul , Misra Veena , Kingon Angus I.
Published: November 2006

Silicon on insulator (SOI) substrates will be required to reduce capacitive coupling and other parasitic effects as device scaling continues. ITRS projections point to a future need for SOI buried oxide layers as thin as 10 nm, and Si channel thickness potentially as low as 5 nm for fully- depleted ultra-thin-body devices. For such thin layers, conventional SOI fabrication processes become increasingly difficult. Progress towards fabricating ultra-thin SOI on Si (001) through an all-growth approach is presented. All steps are performed sequentially in situ, with no wet chemical processing. Starting with a Si wafer as large as 8 , our approach is to: 1) deposit a thin commensurate epitaxial oxide layer such as Ca1-xSrxTiO3; 2) oxidize to grow an interface SiO2 layer ('floating' the epitaxial oxide) for stress relief and lowering of the dielectric constant; and 3) deposit epitaxial Si or Si1-xGex to complete the fabrication process.
Factors Influencing Characteristics of Hafnium Based High-K Dielectrics
Authors: Triyoso Dina H.
Published: November 2006

In this paper, factors influencing characteristics of thin hafnium based dielectrics are investigated. Impact of deposition techniques on film characteristics is studied by comparing HfO2 films deposited by atomic layer deposition (ALD) and metal organic chemical vapor deposition (MOCVD). Impact of precursor choice on HfO2 material and electrical properties is revealed by comparing a hafnium tetrachloride (HfCl4)-water process and a tetrakis[ethylmethylaminohafnium] (TEMAHf)-ozone process. In addition to deposition technique and precursor choice, thin hafnium-based film properties are also impacted by materials in contact with the dielectric. Significant differences in physical and electrical properties were observed when HfO2 is annealed at a high temperature with and without a metal (TiN) capping layer. Finally, the role of additives or impurities on characteristics of hafnium-based films was studied by modulating the amount of ZrO2 content in HfO2 from 0.2% to 98%. Improvements on the properties of HfO2 with ZrO2 addition are discussed.
Ultra-Thin (EOT ~ 0.31nm) and Low Leakage Dielectrics of La-Aluminate Deposited Directly on Si Substrate
Authors: Suzuki Masamichi , Tomita Mitsuhiro , Yamaguchi Takeshi , Fukushima Noburu , Koyama Masato , Nishiyama Akira
Published: November 2006

Ultra-thin (0.31 nm) LaAlO3 gate dielectrics directly deposited on Si substrate were realized. We found that LaAlO3 deposition at substrate temperature of 700{degree sign}C led to low defect density of the film at the as-deposited state. The electron mobility of LaAlO3 n-MISFET was improved by forming gas annealing, meaning that the defects at the direct interface could be passivated with hydrogen.
La2O3 Gate Dielectric Thin Film with Sc2O3 Buffer Layer for High Temperature Annealing
Authors: Shiino Yasuhiro , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Sugii Nobuyuki , Hattori Takeo , Iwai H.
Published: November 2006

Leakage current characteristics of high temperature annealed La2O3 film with Sc2O3 buffer layer was reported. Large amount of leakage current suppression was obtained by inserting Sc2O3 when annealed at high temperature ,without degrading the Equivalent Oxide Thickness (EOT). La2O3/Sc2O3 gate stack would be one of the solution for La2O3-based gate insulator for high temperature annealing.
Enhanced Dielectric Constant of HfO2 and Al2O3 Thin-Films with Silver Nanoparticles
Authors: Ravindran Ramasamy , Othman Maslina , Yun Minseong , Biswas Nivedita , Mehta Narendra , Guha Suchi , Gangopadhyay Keshab , Gangopadhyay Shubhra
Published: November 2006

Through an electron beam evaporation process, silver nanoparticles (Ag-nps) were introduced into dielectric thin-films. Silver incorporation into the oxide films resulted in a distribution of insulating Ag-nps at a density of ~10^12 particles/cm^2. For these samples, an enhancement of about two fold in dielectric constant was observed in both Al2O3 and HfO2. We attribute the dielectric constant enhancement to the polarizability of metallic nanoparticles. The dipole moment of the Ag-nps increased the stack dielectric constant in a frequency dependent manner. Because of the inherent relaxation frequency of the Ag-np dipoles and space-charge polarization, the dielectric constant was more strongly enhanced at lower frequencies (down to 100 Hz) relative to higher frequencies (up to 1 MHz). Gate leakage currents remained comparable between the control and nanocomposite samples. The Ag-nps also produced a memory effect. Potential applications of these Ag-np based films in CMOS devices are discussed.
High Pulling Rate Defect-Free Crystals with Axially Asymmetric Characteristics Due to Controlled Melt Convection
Authors: Cho Hyon-Jong , Lee Bo-Young , Lee Sang-Hoon , Lee Jeong Yong
Published: November 2006

We reviewed experimental results of the variation of growth parameters bringing forth the axially asymmetric formation of vacancy-interstitial boundary and the increase of the critical growth rate V*, transition from interstitial to vacancy, of Czochralski-grown silicon crystals. Such results show that controlled melt convection for defect-free crystals can make the critical growth rate V* much higher like EMCZ. Some parameters can control interstitial oxygen concentration in the crystal effectively as well. From the cone-shaped shouldering test, asymmetric formation of {111} crystal facets was obtained at very low crucible rotation, which confirms asymmetric distributions of the melt temperature. Based on the results of two dimensional (2D) and three dimensional (3D) simulations, it is shown that the very low crucible rotation rate decreases radial temperature gradient and increases axial temperature gradient in the silicon melt.
Rotationless Floating Zone Crystal Growth
Authors: Luedge Anke , Riemann Helge , Hallmann-Seiffert Birgit , Muiznieks Andris , Schulze Friedrich Wilhelm
Published: November 2006

A silicon single crystal can grow without rotation by the FZ method. The effects when stopping the rotation are investigated for large crystals. A special crystal was grown the first part of which was rotated and the second was not. The results were rather surprising. Once the crystal was stopped, the growth was very stable. This can be explained by the absence of periodic thermal disturbances when the rotating crystal passes the main slit of the induction coil. First calculations have been made for explaining the changes in the melt convection after the rotation stopped. Using a specially formed inductor, the non-rotating crystal gets approximately square-shaped. First results are shown. Especially in the situation of silicon shortage, such crystals have a high potential of cost savings for the solar industry. The typical FZ quality of the square single crystal will enable highest efficiencies for solar cells.
Oxygen Precipitation in Lightly and Heavily Doped Czochralski Silicon
Authors: Sueoka Koji
Published: November 2006

Oxygen precipitation in Czochralski (CZ) silicon has been studied for nearly half a century due to its important impact on material and device properties. This paper summarizes the recent understandings of oxygen precipitation in lightly and heavily doped CZ-Si mainly reported by the research groups including the present author. Systematic experiments of annealing condition and dopant effect, and detail analyses of TEM observations and other methods contributed to understand the precipitation mechanism. Further, the theoretical analyses were carried out to explain some experimental results.
Oxygen Precipitation of Nitrogen-Doped Czochralski Silicon Subjected to Multi-Step Thermal Process
Authors: Yang Deren , Ma Qiang , Ma Xiangyang , Duan Duanlin
Published: November 2006

The effect of nitrogen on oxygen precipitation in nitrogen- doped Czochralski (NCZ) silicon subjected to the simulated CMOS process was investigated. It was found that nitrogen could enhance oxygen precipitation in silicon during the multi- step thermal process. And the denuded zone in NCZ silicon was formed near the surface, through it was not as wide as that in conventional Czochralski (CZ) silicon. It was also found that the loss rates of oxygen concentration in the NCZ silicon pre- annealed by rapid thermal process (RTP) were higher than those in the CZ silicon. In addition, during the multi-step process the oxygen concentrations in the CZ silicon and NCZ silicon after the multi-step pre-annealing, which could create denuded zone, changed slightly.
First-Principle Study on the Identification of Nitrogen-Oxygen Defect Domplexes in Silicon
Authors: Fujita Naomi , Jones Robert , Oberg Sven , Briddon Patrick
Published: November 2006

Local density functional theory is used to investigate the interaction of nitrogen with oxygen in Cz-Si. The binding energy of O with N2 and the positions of four local vibrational modes of the N2O center are in good agreement with experiment. The N2O2 defect is the most common nitrogen-oxygen defect after N2O and we suggest that the experimentally observed lines at 1018 and 810 cm−1 are due to this defect. The concentrations of these defects are greater than those of oxygen dimers at temperatures around 650{degree sign}C. Furthermore these defects could be nuclei for oxygen precipitates in nitrogen doped Cz-Si. Neither NO nor NO2 play any significant role.
Ab-Initio Calculations of the Energetics and Kinetics of Defects and Impurities in Silicon
Authors: Windl Wolfgang
Published: November 2006

In this paper, we discuss concepts and examples of ab-initio calcu-lations to understand the energetics and kinetics of defects and im-purities in silicon. We focus on how to determine equilibrium dis-tributions and diffusion and reaction constants, where modern methods such as the nudged elastic band method in combination with density-functional theory allow a systematic and reliable search for the minimum-energy migration paths and barriers. Since calculations especially for Si self-diffusion give sometimes contro-versial results when compared to experiments, we also discuss their validity and possible improved theoretical approaches in or-der to enhance the predictive power of ab-initio calculations.
Lateral Incorporation of the Intrinsic Point Defects in Czochralski Silicon Crystals
Authors: Kulkarni Milind S.
Published: November 2006

Silicon crystals grown by the Czochralski process typically contain many structural imperfections termed microdefects. The formation of all microdefects requires an abundance of one of the intrinsic point defect species of silicon, vacancies and self-interstitials. The evolution of the distribution of microdefects in a growing Czochralski crystal is influenced by its temperature field and the boundary conditions defined by its surfaces. This paper addresses the effects of the lateral surface on the defect dynamics in a crystal growing without an abundance of any intrinsic point defect species, away from the lateral surface. It is shown that, under such conditions, the lateral surface of the crystal induces a moderate vacancy supersaturation in its vicinity, leading to the formation of oxygen clusters and small voids. The vacancy incorporation from the lateral surface of a growing Czochralski crystal is driven by the interplay among the Frenkel reaction, the diffusion of the intrinsic point defects, and their convection.
Simulation of Slip during High-Temperature Annealing of Silicon Wafers in Vertical Furnaces
Authors: Gupta Puneet , Kulkarni Milind S.
Published: November 2006

The argon-annealing of silicon wafers involves high temperature treatment of wafers in a quartz furnace while being supported on a silicon carbide wafer-support structure (boat). The transient power input to the furnace during an annealing cycle that is directed into the quartz furnace leads to spatio- temporal thermal gradients within each wafer as well as from one wafer to another. The thermal stresses thus generated in conjunction with the gravitational stresses and a reduction in the Critical Resolved Shear Stress (CRSS) with increasing temperature can lead to slip formation in the wafers. In this study, a coupled thermal and structural finite element based approach is utilized to model and simulate the Resolved Shear Stress (RSS) in silicon wafers during annealing. Within the constraints and assumptions of the coupled FE model, good comparison of simulation results with experimental data is observed. The method is further utilized to design a new wafer- boat.
Nitrogen-Doped Silicon: Mechanical, Transport and Electrical Properties
Authors: Murphy John D. , Alpass Charles R. , Giannattasio Armando , Senkader Semih , Emiroglu Deniz , Evans-Freeman Jan H. , Falster R. J. , Wilshaw Peter R.
Published: November 2006

A novel dislocation locking technique is used to study the behaviour of nitrogen in float-zone silicon (FZ-Si). Specimens containing well-defined arrays of dislocation half-loops are subjected to isothermal anneals of controlled duration, during which nitrogen diffuses to the dislocations. The stress required to bring about dislocation motion is then measured. From measuring this unlocking stress as a function of annealing time and temperature it is possible to deduce information on nitrogen transport and nitrogen-dislocation interactions. In this paper, the results obtained by using the dislocation locking technique are reviewed. Furthermore, deep-level transient spectroscopy (DLTS) and high-resolution DLTS (HR- DLTS) are applied to nitrogen-doped silicon. A deep-level with an emission enthalpy of approximately 0.50eV and a concentration of order 1011cm-3 was found in n-type nitrogen- doped FZ-Si and n-type nitrogen-doped neutron transmutation doped FZ-Si. No additional deep-levels with a concentration of greater than 6 x 1010cm-3 were found in either material. No deep-levels were found in p-type nitrogen-doped Czochralski silicon (Cz-Si), for which the detection limit was approximately 1012cm-3.
Analysis of the Segregation Phenomena of Copper in P/P+ Epitaxial Silicon Wefers
Authors: Nakamura Kozo , Iga Hisao , Tomioka Junsuke
Published: November 2006

We investigated the segregation gettering of copper in P/P+ epitaxial wafers and determined the segregation coefficient of copper in the P+ layer at room temperature by evaluating the copper concentration using SIMS. The segregation coefficient of copper at the P+ layer with a boron concentration less than 1018 atoms/cm3 was confirmed to be three-orders-of-magnitude lower than that expected by the theoretical model proposed. In this paper we discuss two possible explanations for these results. 1) The segregation coefficient of copper, that is, the dependence of the equilibrium concentration of copper on the boron concentration is overestimated in the theoretical model proposed. 2) Certain barriers work to prevent copper from diffusing and segregating near the surface of the wafers.
Reducing Iron in Single Crystal Silicon Grown Using CZ Process
Authors: Sreedharamurthy Hariprasad
Published: November 2006

The metal iron, that is present in graphite hot zone components used in CZ silicon process, contaminates the crystal. To eliminate and reduce contamination, graphite components were coated with two protective layers including a first protective layer of silicon carbide and a second protective layer of silicon. The effectiveness of these coatings to prevent iron contamination was tested. At test temperature of 1100{degree sign}C and 900{degree sign}C, the Fe concentrations in the monitor wafer that was exposed to graphite sample with layers of silicon and silicon carbide coating was ten times lower. Several hot zone structural components were coated using this method and were used to grow single crystal silicon. The wafers from these crystals were tested for iron concentrations using standard SPV method and are found to be much lower when compared to wafers from crystals grown using only silicon carbide coated graphite components.
Performance-Limiting Oxygen-Related Defects in Silicon Solar Cells
Authors: Schmidt Jan , Bothe Karsten
Published: November 2006

The energy conversion efficiency of solar cells fabricated from oxygen-containing crystalline silicon wafers with boron as p-type dopant is ultimately limited by boron-oxygen-related recombination centers which form under illumination or forward-bias-induced electron injection into the p-type base of the cell. This paper reviews the recent progress in understanding the physics of this degradation effect. It is shown that two different types of boron-oxygen centers are simultaneously formed at very different formation rates. Electronic defect properties, formation mechanisms and the impact on device properties are discussed.
Proof of Interstitial Cobalt Defects in Silicon Float Zone Crystals Doped during Crystal Growth
Authors: Lemke Heinz , Irmscher Klaus
Published: November 2006

In Si crystals, which were doped with cobalt during floating- zone growth, mainly substitutional Co defects with a concentration of about 7 x 1012 cm-3 can be detected by deep- level transient spectroscopy. But a second fundamental defect with a lower concentration around 7 x 1011 cm-3 shows features, which are typical for an interstitial defect with a remarkable mobility even at room temperature. It has a donor level at EV + 0.31 eV as well as an acceptor level at EC - 0.4 eV and is attributed to interstitial Co. In p-type samples pairing of interstitial Co with boron acceptors is observed. The capture coefficient of this pairing reaction is thermally activated with a characteristic energy of 0.9 eV. A binding energy of the Co-B pairs of about 0.6 eV is obtained. In the upper half of the gap an acceptor level was observed at EC - 0.08 eV.
Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors
Authors: Galeti Milene , Martino João Antonio A. , Simoen Eddy R. , Claeys C. L.
Published: November 2006

This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 mm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions. In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2mm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range.
SOI Material Readiness for 45nm and Sub-45nm Device Options
Authors: Maleville Christophe
Published: November 2006

IC scaling has accelerated. The official 3 year ITRS cycle between technology nodes is in reality 2 years. The 65nm technology node is moving into production and the next 45nm node is being defined. The industry has clearly moved into the nano scale integration era. What stands out in this race towards smaller dimensions is the central role that materials have occupied. Among the material innovations, engineered substrates with SOI as its more eminent example stand out. The advances being made by the industry in SOI manufacturing have matched the quality of prime Si epi bulk wafers. The further development of SOI towards atomic level quality control, the SOI engineering focusing on mobility enhancement, RF, smart power, automotive, optoelectronic or MEMS applications address both the miniaturization as well as the diversification requirements of the electronics industry. In summary, it will be discussed how substrate engineering is a key contributor that will help the IC industry keep on the higher density-more performance-less power scaling path.
Fabrication of Directly Bonded Si Substrates with Hybrid Crystal Orientation for Advanced Bulk CMOS Technology
Authors: Bourdelle Konstantin , Rayssac Olivier , Lambert Audrey , Fournel Frank , Hebras Xavier , Allibert Frédéric , Figuet Christophe , Boussagol Alice , Berne Cécile , Tsyganenko Kira , Letertre Fabrice , Mazuré Carlos
Published: November 2006

Introduction of hybrid orientation substrates has led to the development of CMOS technologies in which NMOS transistors are fabricated on (100) Si and PMOS on (110) Si. This maximizes the crystal orientation dependent mobilities of electrons and holes. The Smart Cut technology has been successfully applied to fabricate hybrid orientation substrates with a buried oxide between the top Si layer and the bulk substrate having two different crystal orientations. This paper describes the application of the Smart Cut method for the fabrication of the directly (i.e. with no oxide in between) bonded 300 mm Si engineered substrates. The technological challenges, process flow and the results of the wafer characterization are presented and discussed.
From Smart-Cut to Soft-Cut: Mechanisms of Hydrogen Plasma Supported Layer Exfoliation in Silicon
Authors: Job Reinhart , Düngen Wolfgang , Ma Yue , Horstmann John T.
Published: November 2006

Comparative investigations of silicon layer exfoliation within the Smart-Cut process and its progression at lower H+ implantation doses and subsequent H-plasma exposure (Soft-Cut) were done by µ-Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM) on (100)-oriented Cz Si wafers. Blister formation and evolution at various process temperatures were analyzed to clarify the mechanisms of layer exfoliation for both approaches. On base of the Raman analyses and supporting SEM and AFM measurements of samples prepared under various process temperatures, we identified the V2H6 defect complexes as the precursor of blisters for the Smart-Cut scenario. Under Soft-Cut conditions (100)-oriented platelets created during H-plasma exposure can be identified as the prevailing precursors of blisters.
Effect of Intrinsic Gettering on Semiconductor Device Performance in SOI Substrates
Authors: Nevin Andy , Hoelke Alex
Published: November 2006

This work investigates the effect of varying structural characteristics of fusion-bonded thick SOI on the quality of oxides grown when fabricating transistors using normal CMOS processing methods. The influences of the SOI device material, handle material and bonding procedure were examined using material supplied by various SOI vendors. In addition, the incorporation of gettering sites into the SOI near the interface with the buried oxide, was studied using implanted layers. We found a strong influence of both the vendor and the position of the bonding interface on the quality of the surface thermal oxides, with handle-oxidised material giving superior gate oxides to device-oxidised SOI. A large improvement in oxide quality was shown by the introduction of the implanted ions, which was strongly dependent on the species, germanium giving the largest effect. This enabled the growth of high quality gate and tunnel oxides for electronic device fabrication.
Carrier Transport and Stress Engineering in Ultrathin-body SOI MOSFETs
Authors: Uchida Ken
Published: November 2006

This paper presents a comprehensive study on carrier transport in ultrathin-body (UTB) SOI MOSFETs. Phonon, roughness, and Coulomb scatterings in UTB MOSFETs are discussed. The single-gate and double-gate operations of UTB MOSFETs are compared. In addition, stress engineering in UTB MOSFETs is experimentally investigated using bending apparatus.
Modeling of SiGe Devices Using a Self-Consistent Full-Band Device Simulator Which Properly Takes into Account Quantum-Mechanical Size Quantization and Mobility Enhancement
Authors: Vasileska Dragica , Krishnan Santhosh , Fischetti Massimo
Published: November 2006

We examine performance enhancement of p-channel SiGe devices using our recently developed particle-based device simulator that takes into account self-consistently the bandstructure and the quantum mechanical space-quantization and mobility enhancement (due to the smaller 2D density of states function) effects. We find surface roughness to be the dominant factor for the bad performance of p-channel SiGe devices when compared to conventional bulk p-MOSFETs at high bias conditions. At low and moderate bias conditions, when surface-roughness does not dominate the carrier transport, we observe performance enhancement in the operation of p-channel SiGe MOSFETs versus their conventional counter-parts.
Noise and Mobility Characteristics of Bulk and Fully Depleted SOI pMOSFETs using Si and SiGe channels
Authors: Östling Mikael , Haållstedt Julius , von Haartman Martin , Hellström Per-Erik , Radamson Henry
Published: November 2006

State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 µm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced 1/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.
Performance of Ge-on-Si p-i-n Photodetectors for Standard Receiver Modules
Authors: Dosunmu Olufemi I. , Morse Mike , Chetrit Yoel , Sarid Gadi
Published: November 2006

Ge-on-Si p-i-n photodetectors of sizes that are compatible with commercially-available receivers have been fabricated and tested. A dark current density of 28.7 mA/cm2 at - 2V bias has been measured at room temperature; when heated to 85ºC, the measured dark current increases by a factor of nine. A responsivity of 0.59 A/W at 850 nm has been measured from these Ge detectors, which matches or exceeds values obtained from commercially available GaAs devices. We have measured bandwidths approaching 9 GHz at -2V bias from 50 µm diameter Ge detectors, and have observed eye diagrams comparable to those obtained from GaAs-based receivers at 4.25 Gb/s.
Performance Assessment of Ge-on-SOI-photodetector / Si-CMOS Receivers for High-Speed Optical Communications
Authors: Koester Steve , Schares Laurent , Schow Clint L. , Schaub Jeremy D. , Dehlinger Gabriel , Doany Fuad E. , John Richard A. , Chu Jack O.
Published: November 2006

This paper provides an assessment of the performance capabilities of infrared detectors and receivers using Ge-on- silicon-on-insulator (Ge-on-SOI) photodiodes and CMOS ICs. An overview of our recent results on these detectors is given, and an estimate of their performance capabilities based upon an optimized layer structure design is described. We also provide an overview of high-performance receivers that utilize Ge-on- SOI photodiodes paired with Si CMOS amplifier ICs, and describe the materials and integration challenges needed to be overcome in order to develop a full monolithically-integrated technology.
The Process and Optoelectronic Characterization of Ge-on-Insulator
Authors: Liu Cheewee , Yu C.-Y. , Liao M. H. , Huang C.-F. , Lee C.-J. , Lee C.-Y. , Lin Chuhsuan
Published: November 2006

The Ge-on-insulator metal-oxide-semiconductor detector was fabricated by the wafer bonding and smart-cut. The surface roughness after smart-cut is reduced to be ~7 nm at 150ºC, due to the suppression of hydrogen outdiffusion. The large work function metal (Pt) is used for the gate electrode on the n- type Ge on insulator to reduce the dark current. Due to the small bandgap of Ge, the 850 nm, 1.3 μm and 1.55 μm infrared can be detected. The increasing photo response of the detector using the Ge-on-insulator with decreasing bonding temperature also indicates that the defects caused by hydrogen implantation are passivated more effectively by hydrogen at lower temperature. In order to increase the responsivity of 1.3 μm infrared, n-Ge thickness of 1.3 μm is used, and the responsivity reaches 231 mA/W. The external mechanical strain can further enhance the photo current without degradation of dark current.
Interlayer-Assisted Stability of Germanosilicide for Heavily-Doped n+-Si0.83Ge0.17 Grown by Reduced Pressure Chemical Vapor Deposition
Authors: Shim Kyu-Hwan , Choi A.R. , Choi S.S. , Yang H.D , Kim Sang-Hyeob , Lee S.H. , Lee N.E.
Published: November 2006

Ni-based germanosilicide process of heavily doped n+- Si0.83Ge0.17 has been investigated to understand the influence of temperature and doping concentration on the evolution of sheet resistance and micro-structures. After annealing Ni film on various Si0.83Ge0.17 epi layers for silicide reaction, the evolution of sheet resistance and surface roughness was analyzed using x-ray diffraction, four pint probe, atomic force microscope, and transmission electron microscope. Especially, bi-layer metal structures were employed to resolve inappropriate degradation associated with heavy doping of phosphorous in Si0.83Ge0.17, from which crucial improvements in structural and electrical properties could be confirmed. Pt interlayer played an important role for uniform germanosilicide at the interface of metal and semiconductor, and resulted in low sheet resistance and relevant thermal stability.
Vacancy - Assisted Redistribution of Ge in SiGe/Si Multilayer Structures Irradiated with High Energy Ions
Authors: Antonova Irina V. , Back-Misiuk Jadwiga , Romanowski P , Skuratov Vladimir , Zaumseil Peter , Sustersic N , Kolodzey James
Published: November 2006

Interaction between defects, introduced in multilayer SiGe/Si heterostructures by high energy ions, and strained SiGe layers is studied by means of high resolution X-ray diffraction, transmission and scanning electron microscopy, and electrical measurements. It has been found that implantation and subsequent annealing lead to decreased thickness of SiGe layer with increased Ge content in Ge - containing layer. Formation of precipitates in SiGe layers is strongly depended on the strain, the Ge content in SiGe layer, and the regime of ion implantation.
Isolated Carbon Confinement Methodology for Ultrathin Boron Profiles with Enhanced Conductivity in Sub-50 NM Strained Layers of Silicon Germanium
Authors: Enicks Darwin , Oleszek Gerald
Published: November 2006

This work reports on observations of enhanced carbon confinement of boron in strained silicon germanium. By locating carbon outside of the boron doped region during the pseudomorphic growth, less carbon is required to mitigate boron diffusion during subsequent thermal anneals, the film resistivity is reduced, and the film is more strained than the conventional method of placing carbon throughout. SIMS (secondary ion mass spectrometry) is utilized to verify O, C, B, and Ge concentrations in SiGeC layers following low temp growth by LPCVD (low pressure chemical vapor deposition) and a subsequent thermal annealing. Four-point probe is utilized for 49-point sheet resistance measurements and X-ray diffraction is used to confirm the effect of carbon placement on the SiGe lattice parameter.