bluuebunny/crossref_metadata_2025 huggingface dataset:
Compression Molding for Thin PoP Top Packages
Authors: Adimula Ravikumar , Brand Jason , Yim Myung Jin , Zhang James , Strode Richard , Yoo Chan
Published: October 2015

The package on package (PoP) has become the preferred method for vertical stacking of logic processors and memory in mobile applications. The industry is constantly working toward reducing the total stack height, and current road maps point toward a total stack Z-height of 1mm. One approach to reduce the package height is to reduce the mold cap thickness as well as reduce the mold cap clearance (the distance between the top silicon die to the mold top). In this study, we used the compression molding for manufacturing top PoP packages with 200μm, 250μm, 300μm, and 350μm mold cap and with sub-100μm mold cap clearance. As part of the mold material selection, two different form factors, granular and powder form, of the mold compound were used for the compression mold process. The key objective for this study is to investigate compression mold process and to study its effect on the package integrity.

The major challenge for PoP stack up is the package warpage at reflow temperatures. All the PoP packages must meet certain critical warpage criterion to meet board mount yield requirements. Warpage of the packages was measured by the shadow moiré method, and the warpage results for the packages molded by the transfer mold were compared against that of the compression molded packages. Results indicate that there is considerable difference in warpage behavior betwee n the pellet and powder form of the same mold compound. However, the granular form of the same mold compound resulted in similar warpage behavior of the pellet form mold compound. Further analysis was done to compare the filler distribution in the mold for transfer versus the compression mold process. Results indicate much uniform filler distribution in compression mold furthering evidence that the warpage for the unit level package will be uniform across the strip. Warpage results were analyzed using finite element methods, and the results are extrapolated to different package XY dimensions. The data obtained from these experiments show that the compression mold method can be potentially implemented for thin PoP top packages in the future.
TSV Modeling Considering Signal Integrity Issues
Authors: Ndip Ivan , Curran Brian , Löbbicke Kai , Guttowski Stephan , Reichl Herbert , Lang Klaus-Dieter
Published: October 2015

Since a TSV has a metal-insulator-semiconductor structure, it supports three fundamental modes namely, skin-effect, slow-wave and dielectric quasi-TEM mode. In this contribution, we predict the frequency range of these modes, considering TSVs for interposer applications as an example. Furthermore, the impact of Si-resistivity on signal integrity is quantified and coaxial TSV configurations are proposed to minimize this impact.
Low temperature wafer level packaging technology of bulk-micromachined MEMS device
Authors: Park Heung Woo , Han Seung Hun , Lee Hyun Kee , Lee Yeong Gyu , Kim Seoung Ho , Moon Bok Gun , Yun Taek Hee , Jang Min Seok , Yang Si Joong , Park Sang Hun , Lee Sung Jun , Jeung Won Kyu , Lee Jung Won
Published: October 2015

New low temperature, low cost, small size packaging technology of novel bulk-micromachined MEMS sensor for mobile applications was developed. The sensor was fabricated with the bulk-micromachining process of SOI substrates and composed with a proof mass, membrane and electrodes for capacitance sensing. The sensor device was capped with very thin (130um-thickness) top and bottom silicon cap wafers which have a 80um-depth cavity. Top and bottom cap wafers were bonded with the sensor wafer with a low temperature curing polymer adhesive lower than 200°C. It is needed that the low temperature packaging technology and the passivation of top and bottom sides of the sensor for keeping the sensor performances and preventing stiction of the proof-mass during the molding processes. After bonding the three substrates, the top cap silicon was dry etched to expose bonding pads for the signal interconnection. The ASIC chip was polished to 75um-thickness, diced and bonded on a half-etched 200um-thick lead-frame with a DAF. The diced wafer-level-capped sensor was stacked on the ASIC, wire bonding was accomplished between the sensor and the ASIC, and the ASIC and the lead-frame and finally transfer molding process was done. The developed package is 24-leads QFN and the dimension is 4.0mm×4.0mm×1.1/1.2mm.
MEMS Device Sealing in a High Vacuum Atmosphere Achieving Long Term Reliable Vacuum Levels
Authors: Barnes Paul W.
Published: October 2015

Microeletromechanical Systems (MEMS) require encapsulation of delicate microelements in a controlled atmosphere or vacuum environment. In order to achieve proper device operation and protection from harsh environments, these packages must be hermetically sealed and the internal atmosphere must be maintained to prevent degradation of the device over it's lifetime. Controlled atmospheres and vacuum levels can change over time due to improper consideration of material and their outgassing characteristics. Packaging of MEMS has been and continues to be a major challenge unless all of the materials comprising of a sealed package are evaluated at the initial design phase. This paper will address the issues related to a ceramic package with a gold metallization seal ring, the importance of using low outgassing sensor attach materials, incorporating a getter material to be sealed in the package cavity, and the proper handling of the hermetic lid. In order to achieve the best and highest entrapped vacuum in the package, materials must be prepared before processing. This will involve proper vacuum baking and activating the getter film prior to sealing the MEMS device. By controlling the vacuum levels with aggressive bake outs, fully activating the getter, addressing all material out gassing rates, and optimizing the high vacuum sealing process profile a MEMS device with a controlled vacuum level can be obtained.
Development of a Low Voiding Solder Attach Process for Photovoltaic Cell Assemblies
Authors: Hardy Ian
Published: October 2015

The level of competition for a share of the burgeoning solar cell market naturally drives companies towards low-cost, high-volume subcontractors. But the stringent operating requirements in a concentrated photovoltaic (CPV) application are more consistent with the process capabilities of lower volume manufacturers. Specifications for attach of PV cells as large as 1 cm2 require the high thermal conductivity of a solder connection with minimal voiding in order to prevent current-crowding effects and thermal hotspots. These design aspects are most easily achieved through the use of lower volume, more labor-intensive batch processes such as vacuum reflow, often using expensive alloys such as 80Au20Sn.

Crane Electronics in Redmond, WA, has developed an in-line solder reflow process for PV cell attach that uses standard, inexpensive solder alloys to address large die, low-voiding applications. This paper discusses the initial design and subsequent incremental improvement of that process, with supporting x-ray and yield data.
A First Individual Solder Joint Encapsulant Adhesive
Authors: Liu Mary , Yin Wusheng
Published: October 2015

In order to meet the demand of fine pitch and 3D package, and eliminate complex underfilling process, a first solder joint encapsulant has been invented. Solder joint encapsulant adhesive is to encapsulate each individual solder joint using polymer to enhance solder joint, and leave empty space in-between solder joints to avoid thermal stress applied onto solder joints. Now two kinds of solder joint encapsulants are SMT256 and SMT266, which have been used in the customer field. Using solder joint encapsulants – SMT256 and SMT266, the pull strength of solder joint has been increased by about five times, resulting in significant increase in the reliability. In this paper more details have been investigated.
“Cleaning”- The Dirty Word in Packaging Assembly
Authors: Brooks Rich
Published: October 2015

A majority of the package assembly facilities are using only DI water to remove flux residue from under flip-chip devices, prior to an underfill process. As the new technologies are being implemented, not only has DI water reached its limitations, but some cleaning chemistries are not able to perform adequately to remove ALL of the flux residues. Complete cleaning and removal of the flux residues under low profile components are critical to maintain the reliability of the integrated circuit. Therefore, the cleaning process must be carefully examined and optimized to obtain maximum performance for removing the flux residues. The total cleaning process can be broken down into two subsets:Static Cleaning rate & Dynamic Cleaning rate

The Static Cleaning rate is ability of the cleaning chemistry to remove or dissolve the residue in the absence of temperature and pressure. The Dynamic Cleaning rate involves the kinetic forces and energy to remove the residue. This includes the Thermal energy and Impingement energy required to remove the flux residue. The sum of these two cleaning rates (Static and Dynamic cleaning rates) equal the Total Process Cleaning rate (see formula below). This paper will review cleaning problems brought about with the implementation of the latest technologies and explain how the cleaning process can be optimized to guarantee the reliability of the assemblies.
Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)
Authors: Chien Heng-Chieh , Lau John H. , Chao Yu-Lin , Tain Ra-Min , Dai Ming-Ji , Wu Sheng-Tsai , Lo Wei-Chung , Kao Ming-Jer
Published: October 2015

Thermal performance of 3D IC integration is investigated in this study. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, the thermal behavior of a TSV cell is examined. Furthermore, 3D heat transfer simulations are adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.
Modifiable Silicones for Harsh Environments
Authors: Velderrain Michelle , Lindberg Matthew
Published: October 2015

Silicones have been used for decades in aerospace and other harsh environments where temperature extremes are common. As the level of sophistication increases for electronic devices to serve these industries where failure is not an option, the material supplier has to also be able to meet these needs. Silicones are polymeric materials composed primarily of repeating silicon and oxygen bonds, known as siloxanes, which can be optimized for various chemical and physical properties by incorporating different organic groups onto the silicon atom. Employing advanced processing techniques to the siloxane system can also greatly reduce mobile siloxane molecules to reduce contamination that can cause electronic failures during assembly or operation. Siloxane based polymeric systems are also unique polymers compared to standard organic based materials in that they have a large free volume that imparts a low modulus which absorbs stresses during thermal cycling as well as not degrading at continuous operating temperatures up to 250 C. They are also slightly polar which allows the incorporation of fillers to impart a variety of unique properties. Filler technology is also a rapidly growing enterprise where fillers with various particle sizes and shapes can be added to silicones to impart key properties such as maintaining electric conductivity at elevated temperatures. This paper will explain fundamentals of silicone chemistry and processing related to getting the optimal performance in harsh environments. A case study comparing two different electrically conductive fillers and how they can influence the electrical conductivity at elevated temperatures will be presented.
How Silver Powder Metallurgy Affects the Physical Properties of Low Temperature Firing Silver Conductor
Authors: Shahbazi Samson , Challingsworth Mark
Published: October 2015

With the implementation of RoHS (the Restriction of Hazardous Substance) Directive banning the use of Lead, Cadmium, Mercury and Hexavalent Chromium, hybrid microelectronic manufacturers are globally embracing the lead free movement. These manufacturers must not only understand the implications of their material choice but must be aware of the interaction between lead free solder alloys and their RoHS compliant thick film materials.

It is commonly known that lead free solder alloys process at much higher reflow temperatures than lead containing solder which can directly impact the fired film leach resistance and the loss of adhesion. There are also other concerns; lead free solders alloys generally require a different organic flux system to promote wetting and reflow, but this change may cause a fired film conductor to leach more easily than the flux used in the lead containing solders. The use of lead free solders such as SAC305, SAC405 or 95/5 on a low firing (550–570 °C) pure silver conductor has the tendency of leaching the fired film more readily than conductors containing small amounts of palladium or platinum. Many of these situations provide new challenges for the hybrid circuit manufacturer. There is little information available regarding the effects of the lead free solders on low firing silver thick film conductors.

This paper discusses the results of a newly developed Pb and Cd free silver thick film conductor paste with a modified silver powder metallurgy to improve the leach resistance, solder acceptance and adhesion using lead free solder. In addition, the pure silver conductor was fired on top of a low temperature dielectric paste. This conductor was evaluated by comparing lead free solder alloys to traditional tin-lead-silver solder alloys. This study included evaluations based on SEM photos, solderability, leach resistance, and initial and long term adhesions. Results are published describing the difference in behavior between the different solder alloys in conjunction with the different silver powder metallurgy.
Superhydrophobic Coatings on Electronic Components
Authors: Jones Andrew , Sikka Vinod
Published: October 2015

Superhydrophobic coatings provide exceptional protection to electrical circuits, switches, and other electrical devices which operate in wet environments, such as food processing plants or outdoor applications. Among various electrical device applications, electric motors and electrical switches have been successfully tested in the field at two food processors for nearly 20 months with exceptionally good results. Coated microelectronic circuit board has been in operation without any incidence for over 1 year.
Evaluation of Test Protocol for Eutectic Die Attach Using High Power LEDs
Authors: Hartnett Amanda , Homer Seth , Beck Donald , Evans Daniel
Published: October 2015

High-power semiconductor devices, such as high-brightness Light Emitting Diodes (LEDs), must be mounted using a robust adhesive material to handle the temperature fluctuations generated by the chip and the mechanical stresses due to the coefficient of thermal expansion (CTE) mismatches between the die material and substrate it is mounted to. The selected material must also comply with current legislation restricting manufactured products containing numerous materials including some that were historically popular in HB LED applications due to environmental concerns. Eutectic gold-tin (AuSn) materials meet these requirements, and process recommendations for their implementation will be presented in this paper.

Utilizing a Palomar Technologies die bonder, AuSn solder preforms and paste will be placed/dispensed and reflowed using a Pulsed Heat System (PHS). Evaluation methods comparing these means of eutectic die attach to a pre-plated AuSn die will be discussed. Technical generalizations will be detailed to explain the derivation of test methods as well as hypotheses of results.
Rated Power Enhancement of Termination Resistor by Employing Innovative Thermal Management Techniques
Authors: Rahman Akhlaq , Olinger Fred , Howieson Michael
Published: October 2015

Wireless telecommunication, broadcast and radar industries rely on high power transmission of the radio waves to reach subscribers or measure the environment. As the wireless revolution extends, component requirement in higher frequency, elevated operating power, smaller in size, and improved performance demands on resistive devices grow even more stringent. In this work, we extensively studied to improve the power handling capability of termination resistor while maintaining the smaller size. We optimized the energy transmission within the component and significantly improved the efficiency of energy transfer between the transmission lines and the terminations. We explored several innovative techniques to optimize thermal management. We applied new packaging techniques and developed termination resistors with optimum thermal management. We discussed several methods of improving power handling capability and reduction of thermal fatigue to the component’s structure by improving component packaging technology. Applying the packaging technology methods we significantly reduced the chance of solder cracking due to thermal fatigue. Employing novel techniques of heat transfer we appreciably increased power handling capability while keeping the product size as minimum. We constructed matching network using integrated microstrip line at the beginning of the resistor material. Considering required thermal performance, we designed and manufactured Pb free high power termination resistor. Several sizes of resistor are manufactured with rated power of 20 W and 100 W. Thermal profiles of the termination resistors illustrates the high power handling capability of the fabricated termination resistors.
Meter for the measurement heat of combustion
Authors: Magonski Zbigniew
Published: October 2015

This paper presents a proposal of a thermal instrument intended for the evaluation of heat energy of fluid fuels. Two thermal devices the flowmeter and the combustor are the basic components of the instrument. The meter maintains a constant temperature in the vicinity of the combustion zone. The amount of heat energy in the fuel is calculated as the ratio of the electric power change expressed in Watts to the change of fuel supply delivered to the combustor within a time period of 1sek. The method enables a direct evaluation of fuel energy expressed in Jules per unit of mass or volume. For some applications, the meter may be a good alternative for a bulky bomb calorimeter.
“IC Packaging Trends Causing Concerns in Complete Flux Removal”
Authors: Brooks Rich
Published: October 2015

The complete cleaning and removal of flux / soil residues under low profile components (especially flip-chip devices) are becoming more critical, especially as the conductor spacing’s decreases and the power increases. The reliability of the circuit can be greatly affected when residues are not completely removed.

Flip chip bump pitch and die size push packaging trends resulting in tighter and smaller spaces underneath the devices. A majority of flip-chip assemblers are using water soluble fluxes and they typically use only DI water to remove the flux residues. Because of the tighter spaces and increased I/Os, the complete removal of these water soluble flux residues are becoming more difficult. Due to the ionic nature of water soluble flux residues all residue must be removed to prevent a pathway for electrochemical migration and acceptable bonding of the underfill material.

To insure that all of the flux residues are being removed from under the package, cleaning chemistries must be used. Cleaning chemistries provide the polarity and hydrogen bonding forces needed to remove oxidized flux while lowering surface tension to improve penetration under the die. The cleaning agent design must also be matched with the cleaning equipment.

To completely remove flux residue under the IC packages, the cleaning equipment’s dynamic energy must also be studied, along with the cleaning chemistry. Additionally, both the cleaning chemistry and equipment must be matched up with the flux residue that is being removed. This paper will evaluate various cleaning chemistries and cleaning equipment that provide the best cleaning performance for very low package stand-offs and tighter pitch devices, as well as the different flux residues and process parameters.
Electro-migration Behavior in Micro-joints of Sn-57Bi solder and Cu Post Bumps
Authors: Murayama Kei , Sakai Taiji , Imaizumi Nobuaki , Higashi Mitsutoshi
Published: October 2015

The bonding technique for high density Flip Chip(F.C.) packages requires a low temperature and a low stress process to achieve high reliability of the micro joining. Sn-Bi solder has been noted as a low temperature bonding material.

Electromigration behavior of Sn-57wt%Bi flip chip interconnection with Cu post bumps was investigated. The flip chip bumps used for this experiments consisted of Cu post formed with plating and Sn-57wt%Bi solder. Two types of under bump metal(UBM) of organic substrate were studied, that is, electroless Ni(6μm)/Au(0.5μm) on Cu pad and Cu pad. Electron flow to induce the electro-migration was from organic substrate side (Cu pad) to chip side (Cu post) with current density of 40000A/cm2 at 125 degree C. At both types of the UBM, Bi migrated and accumulated to the anode side (Cu post) and Sn migrated to the cathode side (substrate pad). Each interconnect resistance has increased to about 25% and 46% within 100 hours, respectively. However, after more than 3000 hours, they were stabilized.

With Ni/Au UBM pad, Cu3Sn/Cu6Sn5 intermetallic compounds (IMCs) were formed at the Cu bump side. And under the Bi layer Cu6Sn5/Ni-Sn compounds were formed. But we didn’t observe the failure like cracks or voids at the Ni layer.

With Cu pad, only Cu3Sn IMC at the Cu bump side and under the Bi layer Cu6Sn5/Cu3Sn compounds were formed after 4000 hours. Although the voids were observed at Cu3Sn/Cu interface, good electrical connection was obtained.
TEMPORARY PROTECTIVE PACKAGING FOR OPTICAL MEMS
Authors: Bogaerts L. , Phommahaxay A. , Gerets C. , Jaenen P. , Van Hoof R. , Severi S. , Van De Peer M. , De Coster J. , Beernaert R. , Rudra S. , La Manna A. , Soussan P. , Witvrouw A.
Published: October 2015

The fragility of MEM devices is one of the main concerns in case of standard packaging. Steps such as wafer dicing, die handling, assembly and wire bonding can seriously damage the device functionality if the MEM devices are not properly protected during the assembly processes. In this paper we report for the first time on bonding and removal of protective temporary caps used to ease the packaging of MEMS for optical applications. The package, based on a heat decomposable and photo-patternable polymer sealing ring, is gross leak tight, fulfills the MIL spec for shear testing and respects the thermal budget of Al-coated SiGe micro-mirrors. After release of the micro-mirrors at wafer level, a temporary cap with patterned Unity 2203P is bonded to the device wafer, enabling dicing, followed by assembly of the die to a PCB. This can be done by wire bonding and the cap will finally be removed by applying heat. The protective caps are assembled using a die to wafer approach on a flip-chip bonder. The caps are removed by thermal decomposition of the Unity film, leaving little residues in the patterned area. Debonding is done on the flip-chip tool, allowing a slow separation of the cap and MEMS wafer during heating. Several dies with released micro-mirrors were covered with temporary caps by using the optimized process. After dicing and debonding the mirrors were found to be unharmed. Optical and electrical measurements demonstrate the applicability of the process.
Wafer Level Integration of MMIC and Microwave IPD with Metal/BCB Multilayer Interconnection Based on Low Resistance Silicon
Authors: Tang Jiajie , Luo Le
Published: October 2015

A new high-density wafer-level integration of a GaAs based monolithic microwave integrated circuit (MMIC) chip and a microwave integrated passive device (IPD) is presented. This integration technology, an important and IC-compatible option for system-in-package (SiP), utilizes bulk Si fabrication and film deposition based multichip module (MCM-D) process. MMIC is entirely embedded into the silicon wafer while IPDs are integrated on the dielectric layers simultaneously with the metal/BCB multilayer interconnection. Key fabrication processes and crucial technologies are described in detail. Normal silicon wafer is selected as substrate because of its mature processing technology, low cost, good thermal dissipation as well as its thermal expansion matching with GaAs. To obtain excellent microwave performances and good planarization, thick photosensitive BCB of 25um/layer is adopted as dielectric and thus the use of tapered via that is hollow inside or filled by BCB is a cost-effective way to accomplish inter-layer connection instead of Au bump bonding or column used in dry-etch BCB process. Further promotions on microwave performances are achieved by the shielding effect through ground layer coverage on silicon surface and the application of microstrip lines. Several experiment results such as dc inter-layer connection resistance and thermal resistance measurements are complemented to investigate the characteristic of the whole package. The Microwave properties of the integration sample are measured by transmission performance test from 15GHz to 30GHz. The measurement results are analyzed and discussed comparing with the theoretical or simulation results.
Applications of 3D X-Ray Microscopy for Advanced Package Development
Authors: Fahey K. , Estrada R. , Mirkarimi L. , Katkar R. , Buckminster D. , Huynh M.
Published: October 2015

This paper describes the utilization of non-destructive imaging using 3D x-ray microscopy for package development and failure analysis. Four case studies are discussed to explain our methodology and its impact on our advanced packaging development effort. Identifying and locating failures embedded deep inside the package, such as a solder fatigue failure within a flip chip package, without the need for physical cross-sectioning is of substantial benefit because it preserves the package for further analysis. Also of utility is the ability to reveal the structural details of the package while producing superior quality 2D and volumetric images. The technique could be used not only for analysis of defects and failures, but also to characterize geometries and morphologies during the process and package development stage.
Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-bumps for 28nm Technology
Authors: Banijamali Bahareh , Chaware Raghunandan , Ramalingam Suresh , Kim Myongseob
Published: October 2015

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting significant industry attention.

High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Different design/material related factors are evaluated during this study in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.
Analysis and Control of Interface Reactions in Microelectronic Systems
Authors: Perepezko J.H. , Imhoff S.D. , Sakidja R.
Published: October 2015

Multilayer, multicomponent architectures are ubiquitous in microelectronic systems over size scales ranging from microns to nanometers. During device fabrication and use reactions at component interfaces often occur and lead to both beneficial and deleterious product phases. The analysis of the reactions is an essential component in developing strategies for reaction control. An effective approach for the analysis of interface reactions is presented based upon the interpretation of the interface microstructure evolution in terms of the operative multicomponent diffusion pathway where the influence of initially steep concentration gradients is included in the examination of reaction phase sequencing. From the established diffusion pathway a novel kinetic biasing approach can be devised as a robust means to engineer thermodynamic and mechanical compatibility including the development of an in-situ diffusion barrier. The degree of kinetic control can be augmented further by means of tailoring the diffusion pathways to establish the preferred interfacial reaction sequences. Furthermore, the extent of the interfacial control can be utilized to limit the formation of undesired interfacial reactions. The analysis and control concepts are illustrated with an example from high temperature SiC applications.
Design and Process Implementation for Embedding Components
Authors: Solberg Vern
Published: October 2015

Although the printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces, companies attempting to improve product functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process. Some components are easy candidates for integrating into the substrate while other may involve more complex processes and will be difficult to rationalize. Although many of the discrete passive and active devices may remain mounted on the outer surfaces of the multilayer board, embedding passive components and one or more silicon based semiconductor elements within the inner layers of the subsrate will enable greater utilization of the circuit board structure. Benefits can include improved performance. For example, by embedding the uncased semiconductor element on an inner layer of the circuit vertically in-line with a related semiconductor package mounted on the outer surface, the conductor interface can be minimized. The close coupling of semiconductor elements will significantly reduces resistance, inductance and contributes to increasing signal speed.

This paper includes design guidelines, material selection and the use of micro-via build-up termination methodology for embedding and interconnecting miniature passive components; resistor, capacitor, inductor, discrete transistor elements and thinned semiconductor elements. Detailed process information and examples will be included to enable the product designer and manufacturing specialist to have a clear understanding of the principles for embedding and interconnecting components in an organic multilayer circuit board structure
ToF-SIMS Analysis of Fiberglass Cloths for PCB Manufacturing
Authors: Boday Dylan , Haag Michael , Kuczynski Joe , Schmidt Markus , Wahl Michael , Windeln Johannes
Published: October 2015

Woven fiberglass cloths are by far the most common reinforcement material used in PCBs. The glass yarns are coated with silane-based coupling agents designed to improve the bond between the glass filaments and the resin matrix. Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) was utilized in order to garner a better understanding of the observed poor glass surface wetting and weak adhesion of the resin to the yarn. These are the major root causes for a number of PCB failure mechanisms such as delamination cracks, IR (insulation resistance) and CAF (conductive anodic filament) growth. ToF-SIMS revealed that the silane surface is far from being ideal. The results are used to derive recommendations for the glass cloth suppliers in order to improve the efficiency of their silanation process.
Interference of Sb(III) in the Determination of Hexavalent Chromium in Thermoplastic Matrices
Authors: Lau Sophia S. , Kuczynski Joe P.
Published: October 2015

Due to the adverse health effects of hexavalent chromium, Cr(VI), pigments and other materials containing Cr(VI) were largely banned for use in electrotechnical products under the EU RoHS Directive [1]. While there are several effective methods to determine the presence of total chromium in electrotechnical plastic matrices, a validated compliance test method that is capable of discerning Cr(VI) from the non-regulated forms of Cr(III) is not yet available. One of the challenges in developing a standardized compliance test for Cr(VI) is the low recovery of Cr(VI) compounds from polymer matrices This study identified antimony trioxide (ATO), a common synergist added to enhance the ignition resistance of brominated flame retardants (BFRs), as a source of matrix interference in the quantitative determination of hexavalent chromium extracted from polymer matrices. ATO reduces hexavalent chromium to trivalent chromium prior to complexation of Cr(VI) with diphenylcarbazide (DPC) leading to false negatives. EDTA was found to be an efficient reagent for Sb(III) complexation, thereby suppressing the reduction of Cr(VI) and enabling quantitative Cr(VI) determination in the presence of ATO.
Location of the Critical Solder Joint of a PBGA under Temperature Cycling Load for SAC and SnPb Solder. Results of Experiments vs. FE-Simulations on System and Board Level.
Authors: Schafet Natalja , Schrempp Bruno , Spraul Manfred , Becker Ulrich , Güttler Herbert
Published: October 2015

PBGAs with SnPb and SnAgCu (SAC) solder joints were stressed with temperature cycles on board- and system-level. A significant influence of the different solder materials on the location of the most damaged PBGA solder balls was observed in the experiment. The reason for this experimental finding was investigated and explained by FE–simulation. The simulations of the PBGAs were done on package-, board- and system-level (PCB within a metal housing). For the system level simulation a 2-step sub-model technique described in [1] was used. Through such an approach the transient PCB deformation and the transient temperature field within the ECU-housing can be incorporated into a creep simulation of the PBGA solder joints. The creep results for both SnPb and SnAgCu solder joints from the board- and system-level simulation were compared. The calculated damage factor due to the ECU-housing influence is different for PBGA with SnPb and SAC solder joints. The simulation results were validated step by step with measurements and experiments: warpage of the non-soldered PBGA, mechanical strain and temperature on the mounted PCB, crack length evaluation of all PBGA solder joints.
Overview on Thermal and Mechanical Challenges of High Power RF Electronic Packaging
Authors: Yuan Cadmus , Kregting René , van Driel Willem , Gielen Sander , Xiao An , (Kouchi) Zhang G. Q.
Published: October 2015

High Power RF electronics is one of the essential parts for wireless communication, including the personal communication, broadcasting, microwave radar, etc. Moreover, high efficient high power electronics has entered the ISM market, such as the power generator of microwave oven.

Power electronics requires a close co-development of digital-analog mixed circuit design, high power IC manufacturing technologies, and high power packaging design/process, in order to guarantee their performance and lifetime. In this paper, we overviewed our works on the packaging/assembly development of high power packages, including three parts: (1) Thermal simulation and die bond defect control (2) Mechanical integrity model for soft package heatsink implementation (3) Al wire multiphysics modeling and reliability of plastic power package.
High temperature Au-based solder reliability in electronic packages for harsh environments
Authors: Sousa M.F. , Riches S. , Johnston C. , Grant P.S.
Published: October 2015

The operation of electronic packages in high temperature environments is a significant challenge for the microelectronics industry, and poses a challenge to the traditional temperature limit of 125°C for high electronic systems, such as those used in down-hole, well-logging and aero-engine applications. The present work aims to develop understanding of how and why attach materials for Si dies degrade/fail under harsh environments by investigating high temperature Au based solders. Au-2wt%Si eutectic melts at < 400°C and offers high temperature stability but high temperature processing and complex manufacturing steps are the major drawbacks. Changes in the die attach material were investigated by isothermal ageing at 350°C, thermal shock and thermal cycling treatments. Die attach reliability investigated by thermal shock and thermal cycling showed that the bonded area degraded. Nevertheless, most of the samples tested had high bonded area ranging from 92.5 to 97.5%. The failure behaviour of the die attach materials included cracking of die and/or attach material, delamination and voiding. Scanning acoustic microscopy images provided a rapid assessment of delamination and other defects and their location within the package. Microstructural analysis and die shear testing were also carried out, along with the high temperature endurance of a SOI test chip for signal conditioning and processing applications at 250°C. All functions evaluated have shown stable performance at 250°C for up to 9000 hours.
Fully Additive Chip Packaging: Science or Fiction?
Authors: Oosterhuis Gerrit , van der Zon Ben , Maalderink Hessel , Dunias Par
Published: October 2015

The current trend in IC packaging towards an ever increasing degree of integration, combined with a high level of production flexibility calls for novel approaches in manufacturing. To address these challenges in a flexible manufacturing setting, TNO investigated to what extend mask-less additive manufacturing (3D printing) can be applied to packaging of semiconductor components and systems.

The micro-stereolithography (μSLA) process has been applied to two different cases to assess its feasibility in creating integrated chip packages and interconnects. First, 2D interconnects based on conductive inks have been integrated into thin layers, manufactured using μSLA. In principle, this process allows building a 3D interconnect circuit on a layer-by-layer basis. A second approach is to build a fully functional, densely integrated system based on a 3D interconnect structure in μSLA resin (insulator) followed by global metallization and a trimming step. This approach allows creating almost free form interconnects integrated with functional properties in the package.

These process examples allow manufacturing of small series with complex, integrated packages. Therefore, to asses the industrial relevance, the cost-of-ownership of manufacturing with the μSLA process on 200 mm wafers is estimated as a comparison to wafer-level molding. It will be shown that, especially in cases where complex geometries, integrated functionality or small series are required, mask-less additive manufacturing enables novel manufacturing solutions at reasonable cost.
NanoBond® Assembly – A Rapid, Room Temperature Soldering Process
Authors: Matteau Jacques
Published: October 2015

Indium Corporation of America has commercialized a new technology that will revolutionize how manufacturers join components using solder materials. (See Figure 1) The joining process is based on the use of reactive multilayer foils as local heat sources. The foils are a new class of nano-engineered materials, in which self-propagating exothermic reactions can be ignited at room temperature through an ignition process. By inserting a multilayer foil between two solder layers and two components, heat generated by the reaction in the foil melts the solder and consequently bonds are completed at room temperature in air, argon or vacuum in approximately one second. The resulting metallic joints exhibit thermal conductivities two orders of magnitude higher, and thermal resistivity’s an order of magnitude lower, than current commercial TIMs.

The use of reactive foils as a local heat source eliminates the need for torches, furnaces, or lasers, speeds the soldering processes, and dramatically reduces the total heat that is needed. Thus, temperature-sensitive or small components can be joined without thermal damage or excessive heating. In addition, mismatches in thermal contraction on cooling can be avoided because components see very small increases in temperature. This is particularly beneficial for joining metals to ceramics. The fabrication and characterization of the reactive foils is described, and the value proposition for NanoBonding is presented. This presentation also shows the applicability of this platform technology to many areas of packaging including Thermal Interface Materials, microelectronics, optoelectronics, and Light Emitting Diodes (LEDs)
Localized Temperature Stability in A Multilayer LTCC Package
Authors: Dai Steve
Published: October 2015

Low temperature cofired ceramic (LTCC) is a multilayer 3D packaging, interconnection, and integration technology. One of the advantages of LTCC is the ability it affords to integrate passive components via the cofiring processes. For LTCC modules with embedded resonator functions targeting high frequency applications, the temperature coefficient of resonant frequency (τf) is a critical parameter. The base dielectrics of commercial LTCC systems have a τf in the range −50 ∼ −80 ppm/°C. This study explores a method to achieve zero or near zero τf embedded resonators by incorporating τf compensating materials locally into a multilayer LTCC structure. Chemical interactions and physical compatibility between the τf modifiers and the host LTCC dielectrics are investigated. A stripline (SL) ring resonator with near zero τf is demonstrated in a non-zero τf commercial LTCC.
MEMS Integrated Packaging for RF Circuit Testing and Self Calibration
Authors: Kannan Sukeshwar , Kim Bruce , Evana Naga Sai , Gupta Anurag , Noh Seok-Ho
Published: October 2015

This paper presents MEMS enhanced integrated packaging which provides testing and self-calibration to identify process-related defects and out of specification circuits, thereby enabling the package to calibrate itself in case of faults and defects to designed performance levels. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. Hardware testing is performed and the results are compared with the look-up table to verify whether the device is fault-free. In faulty circuit conditions, calibration is performed using a tuning circuit which consists of MEMS switches. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.
Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) wafer for 3D IC Integration
Authors: Lau J. H. , Tzeng P-J , Lee C-K , Zhan C-J , Dai M-J , Li Li , Ko C-T , Chen S-W , Fu H. , Lee Y. , Hsiao Z. , Huang J. , Tsai W. , Chang P. , Chung S. , Hsu Y. , Chen S-C , Chen Y-H , Chen T-H , Lo W-C , Ku T-K , Kao M-J , Xue J. , Brillhart M.
Published: October 2015

In this study, the wafer bumping and characterization of fine-pitch lead-free solder microbumps on 300mm wafer for 3D IC integration are investigated. Emphasis is placed on the Cu-plating solutions (conformal and bottom-up). Also, the amount of Cu and solder (Sn) volumes is examined. Furthermore, characterizations such as shearing test and aging of the microbumps are provided and cross sections/SEM images of the microbumps before and after test are discussed. Finally, the process windows of applying the conventional electroplating wafer bumping method of the ordinary solder bumps to the microbumps are also presented.
A Study of Solder Joint Failure Criteria
Authors: Pan Jianbiao , Silk Julie
Published: October 2015

One of the challenges in an experimental study of solder joint reliability is to determine when cracks occur in a solder joint or when a solder joint fails. Cracks in a real solder joint are difficult to identify using an X-Ray system. Cross-sectioning and scanning electron microscopy (SEM) is a destructive method. A common non-destructive test method is to monitor resistance increase in a solder joint or a daisy-chain. However, no scientific research has been done in establishing the relationship between the crack area of an interconnection and the change in resistance of the interconnection. This paper proposes a method of defining failure criteria as the resistance increase in a solder joint exceeding a threshold. The threshold is determined by k times the range over the natural variation in resistance measured by a measurement system. The natural variation by random cause is judged using X-bar and R charts. The principles of defining failure criteria are to be able to detect failure of solder joints as early as possible with minimum false detection due of measurement system error/variation. An experimental study confirmed that a full crack of an interconnection occurs when the increase of resistance in the interconnection is 10 times the natural variation of resistance change. The results of this study could be used to narrow the definition of failure in consensus standards IPC 9701A, JESD22-B111, and IPC/JEDEC-9702.