bluuebunny/crossref_metadata_2025 huggingface dataset:
Evaluation of Glass Frits for Development of Lead-Free Thick Film Resistor
Authors: Chen Xudong , Jones W. Kinzy
Published: October 2015

Glass frit is a major component of thick film resistor (TFR) for the production of hybrid circuits. More than thirty commercial lead-free glass frits with different compositions have been evaluated for developing a lead-free thick film resistor that is compatible with typical industry thick film processing and has comparable electrical properties as the lead bearing counterpart. Two glass compositions were selected out of 33 candidates for preparation of RuO2 based TFR inks, which were screen printed on alumina substrates and fired at 850°C. The preliminary results of these resistors showed that the sheet resistance spanned from 400 ohms per square (Ω/□) to 0.4 mega-ohms per square (MΩ/□) with 5–15% RuO2 and the hot temperature coefficient of resistance (HTCR) fell in a range of ±350ppm/°C.
Automated Precision Assembly for High-Volume HB LEDs
Authors: Beck Donald J. , Sylvester Jessica
Published: October 2015

Since the introduction of automated die and wire bonders in the 1980s, equipment manufacturers and process engineers have been challenged to balance speed with repeatability. Today, die bonders can perform epoxy die attach at a rate of 1.5 to 4 thousand die per hour [6]; and wire bonders can interconnect complex packages at speeds of more than 10 wires per second [7]. The advantage of automation is speed and consistency—however, there is one major concern with operating at these speeds: if something in the assembly process is wrong, everything will be wrong. Having tightly regulated assembly processes helps avoid the risk of building a large batch of rejected product.

This paper presents a methodology and process flow supporting High Bright Light Emitting Diode (HB LED) automated assembly, supported by equipment certification, product inspection and SPC data collection methods. The methods presented in this paper have been formulated through extensive work in the high-reliability microelectronics industry and commercial production lines over the last three decades. To ensure time-to-market success in high-volume production, specific methods to achieve throughput and quality are required. This paper will cover the strategies and methods necessary to achieve the ultimate goal of an automated precision HB LED assembly—to blend the requirements of high-reliability and high-throughput to support high-volume commercial production.
GaN based RF Modules - Demands & Needs for Packaging
Authors: Oppermann M. , Widmer K. , Reber R. , Sledzik H. , Schuh P. , Schmid U. , Bunz B. , Chartier S. , Drüeke K. , Bedenbecker M.
Published: October 2015

GaN/SiC based powerbars and MMICs are the youngest semiconductor devices which have arrived in the field of Radio Frequency modules and applications, e.g. radar, communication links and high power transmitters and amplifiers. Nearly 5 years ago, the first GaN devices were used in the fields of telecommunication equipment, mainly in base-station amplifiers and today GaN devices are more and more part of modern radar applications, like T/R (Transmit/Receive) modules in AESA (Active Electronically Scanned Array) antennas.

The main advantages of GaN/SiC semiconductor devices in comparison to GaAs-devices are the higher bandwidth, higher robustness level and the higher operation voltage. Another big issue of GaN is the higher power density, with in minimum 4 times higher values compared to GaAs. Therefore the assembly of GaN MMICs and powerbars on heatsinks and module-baseplates is a big challenge for soldering technology. An absolute minimum of voids between backside of the GaN/SiC devices and the heatsink is necessary to guarantee an optimised heat transfer during operation.

Different package materials and technologies are on the market and big international package suppliers deal with new material combinations, like sandwich structures of Cu and Mo. Materials like Al-diamond are used for heatsink materials and with special tests and measurements the results of heat transfer studies will be shown.

In this paper examples of power amplifiers, operating in the frequency range of 2–6 GHz and 6–18GHz, and a typical X-Band Frontend will be shown and the RF results will be discussed.
Impact of Process Tolerances on the Performance of Bond Wire Antennas at RF/Microwave Frequencies
Authors: Ndip Ivan , Öz Abdurrahman , Tschoban Christian , Schmitz Stefan , Schneider-Ramelow Martin , Guttowski Stephan , Reichl Herbert , Lang Klaus-Dieter
Published: October 2015

Due to the multitude of advantages bond wire antennas have over conventional planar antennas (especially on-chip planar antennas), they have received much research attention within the last four years. The focus of the contributions made so far has been on exploiting different configurations of single-element and array bond wire antennas for short-range applications at RF/microwave frequencies. However, the effects of process tolerances of bond wires on the radiation characteristics of bond wire antennas have not been studied in published literature. Therefore in this paper, we investigate the impact of up to 20% fluctuations in the parameters of bond wires on the performance of 42 GHz and 60 GHz bond wire antennas. Our results reveal that the length and radius of bond wires are the most and least sensitive parameters, respectively. Furthermore, the severity of the impact of process tolerances depends on the impedance bandwidth of the original antenna, before considering the tolerances. For example, a 10% change in the length of a bond wire causes the resonance frequency of a 42 GHz antenna to be shifted out of the specified 3GHz bandwidth (40.5 GHz–43.5 GHz) required for point-to-point communication. However, although a 10% change in length of a bond wire yields a 2.5 GHz shift in the resonance frequency of a 60 GHz bond wire antenna, it doesn’t completely detune the antenna because of the original 6 GHz bandwidth available, prior to the fluctuation. Therefore, to prevent the impact of process tolerances from severely degrading the performance bond wire antennas, these antennas should be designed to have larger bandwidths than specified. For experimental verification, a bond wire antenna was designed, fabricated and measured. Very good correlation was obtained between measurement and simulation.
Evaluation of electromigration in flip-chip solder joints
Authors: Lee Hyun-Kyu , Chu Yong-Chul , Chun Myung-Ho , Jeon Sang-Ho , Kwak Jung-Ug , Lee Seung-Jin , Bae Sung-Mun
Published: October 2015

The flip-chip solder joint has become one of the most important technologies of high-density packaging in the microelectronics industry. But, electromigration has become a critical reliability issue in flip-chip technology. Because the dimensions of solder joints are expected to decrease and current density is expected to increase.

This study is about electromigration of flip-chip solder joints, we evaluated many kinds of solder balls such as SnAgCu, SnCu and so on in flip chip package. The lifetime against electromigration was defined the fail from the value of resistance with electric current reaches 1.5 times of that of initial resistance with electric current for.

In solder bumps with electric current, since the atoms composed of the solder bump and UBM move in the direction of electron flows, the IMC was accumulated on the anode side. Meanwhile, the IMC disappeared in the cathode side, and the voids were formed. In the solder bumps without electric current, the IMC gradually grew on both sides.

SnAgCu had better lifetime than SnCu, and different time-to-failure caused by different crystallographic orientation of Sn. And various dopants in SnCu had a different EM lifetime each other.
Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications
Authors: O’Reilly Michael J. , Leal Jeff , Pangrle Suzette K. , Vartanian Kenneth
Published: October 2015

Aerosol Jet deposition systems provide an evolutionary alternative to both wire bond and TSV technology. As part of the Vertical Interconnect Pillar (ViP™) process, the Aerosol Jet system prints high density three-dimensional (3D) interconnects enabling multi-function integrated circuits to be stacked and vertically interconnected in high performance System-in-Packages (SiP). The stacks can include two or more die, with a total height of ∼ 2 millimeters. The non-contact printing system has a working distance of several millimeters above the substrate allowing 3D interconnects to be printed with no Z-height adjustments. The Aerosol Jet printhead is configured with multiple nozzles and a closely coupled atomizer to achieve production throughput of greater than 19,000 interconnects per hour. The Aerosol Jet printer deposits silver fine particle ink to form connections on staggered die stacks. High aspect ratio interconnects, less than 30-microns wide and greater than 6-microns tall, are printed at sub 60-micron pitch. After isothermal sintering at 150° C to 200° C for 30 minutes, highly conductive interconnects near bulk resistivity are produced. Pre-production yields exceeding 80% have been realized. This paper will provide further details on the 3D printed interconnect process, current and planned production throughput levels, and process yield and device reliability status.
Embedded Capacitors on Silicon Interposers Enable Higher Frequency Applications
Authors: Savastiouk Sergey , Hewlett James , Marcoux Phil
Published: October 2015

Silicon interposers are being used in 3d stacked assembly applications for an increasing variety of reasons, such as, reduced costs. The inclusion of an interposer opens up the option of fabricating capacitors closer to the devices they need to protect. This paper will present the results of tests and developments ALLVIA has completed on planar and trench capacitors on interposers. Test results up to 6 GHz will be detailed along with reliability results.
High resolution analyzes of resistance behavior in eWLB metal contacts
Authors: Klengel (Bennemann) S. , Krause M. , Berthold L. , Petzold M. , Förster J. , Pressel K. , Meyer T.
Published: October 2015

The embedded Wafer Level Ball Grid Array (eWLB) technology is a new packaging solution that allows a minimum package size for any number of interconnects at a given pitch and the possibility of further system integration in x-, y- and z-direction. The eWLB is a fan-out wafer level package solution realized by a thin film redistribution layer above the semiconductor chip and using standard thin-film processes. The eWLB technology is driven by smaller form factor and better electrical performance with respect to high frequency applications. For optimum electrical performance, it is important to measure and control the contact resistance at interfaces caused by intermediate layers of the electrical re-routing. This paper presents a case study for high resolution analyzes at the eWLB metallization system Al/TiW/Cu with different intermetallic resistance behavior. First, we investigate different eWLB metallization systems after different process step variations. We observe chemically high resistance intermediate layers using Time-of-Flight Mass Spectrometry (ToF-SIMS). These results show that the intermediate layer consists of carbon, oxygen, fluorine, chlorine and sulfur. Second, we applied Focused Ion Beam (FIB) preparation and Transmission Electron Microscopy (TEM) as well as High Resolution Transmission Electron Microscopy (HRTEM) experiments to investigate the metallization interface Al/TiW/Cu. We resolve a porous 2–10 nm thin layer. We show that control of different humidity concentration out of the mold compound and different pre-clean etch rates at warped wafer parts are crucial for optimum contact resistance. The results demonstrate that high resolution analyzes and combinations of different analytical methods (e.g. HRTEM and ToF-SIMS) are very important for optimum process developments in modern package technology.
Suppression of Kirkendall voiding in Sn-3.5Ag/Cu solder joints by pre-annealing process
Authors: Kim S. H. , Yu Jin
Published: October 2015

In this study, electroplated Cu films were pre-annealed at T (T = 673, 773, 873 K) for varying times. Sn-3.5Ag solder reflowed over the Cu films and subsequently aged at 150°C for 240 hrs. Effects of pre-annealing on the microstructure of Cu films, as well as contents of organic impurities incorporated in the Cu films were investigated. After solder reflow, the formation of Kirkendall voids at Cu3Sn/Cu interface was observed from SEM micrographs. Results show that the pre-annealing process significantly suppressed Kirkendall void formation in the Sn-3.5Ag/Cu solder joints. A line fraction of voids at the Cu3Sn/Cu interface was definitely suppressed in the case of 500°C and 600°C pre-annealed samples compared to as-deposited Cu sample. SIMS analyses revealed that pre-annealing reduced the level of impurities in the Cu films, especially S and C. The mechanism of suppressing Kirkendall voids at the Cu3Sn/Cu interface was presented by schematic diagram, and it could be seen that pre-annealing method has a potential to enhance solder joint reliability.
Manufacturability & Reliability Challenges with Leadless Near Chip Scale (LNCSP) Packages in Pb-Free Processes
Authors: Tulkoff Cheryl , Caswell Greg
Published: October 2015

Leadless, near chip scale packages (LNCSP) like the quad flat pack no lead (QFN) are the fastest growing package types in the electronics industry today. Early LNCSPs were fairly straightforward components with small overall dimensions, a single outer row of leads and small lead counts. However, there is currently a proliferation of advanced LNCSP package styles that have started to approach BGA packages in terms of both size and number of connections. Some of the newer packages have 3 or more rows, pitches as fine as .35mm, lead counts exceeding 200, and dimensions exceeding 12 mm × 12 mm.

While the advantages of these packages are well documented, concerns arise with both reliability and manufacturability in Pb-free environments. So, acceptance of these packages in long-life, severe-environment, high-reliability applications is somewhat limited. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies like LNCSP. Since robust manufacturing and qualifications standards always lag behind implementation, users must carefully select and validate these components for suitability in their use environments and customer applications.

Soldering, flexure, and cleanliness issues have driven many failures seen in production and in the field. All of these areas must be addressed early in the selection and validation processes. In this paper, we will review and discuss LNCSP related reliability concerns and challenges, and propose Physics-of- Failure (PoF) based approaches to allow the successful introduction and failure analysis of LNCSP components in electronics products.
Fabrication of an electrostatically actuated impingement cooling device
Authors: Majeed B. , Jones B. , Oprins H. , Vandevelde B. , Tezcan D. S. , Fiorini P.
Published: October 2015

This paper reports on the fabrication and characterization of an electrostatically actuated liquid droplet, impingement cooling device. The continuous increase of IC power density and the widespread use of 3D integration call for advanced cooling techniques. These are necessary to keep the device temperature low and to improve the reliability. Here we propose a 3D cooling device in which droplets are electrostatically actuated through vertical channels and impinge on an IC surface. The channels are formed by stacking thinned perforated silicon dice. By means of DRIE, vias with diameters ranging from 100 μm to 300 μm are etched into a low resistivity 200 mm silicon wafer. Further processing involves passivation with oxide, contact opening, bonding to a carrier wafer and grinding. Finally, stacking of the dies is achieved by debonding individual dies from the carrier wafer and bonding the first die to a silicon base. A second die is then aligned and bonded on top of the first one, and this operation is repeated a third and fourth time so as to create a “tower of Hanoi” structure. The preliminary results on the electro wetting properties of this device are reported.
Piezoelectric Nanogenerators for Mechanical Energy Harvesting
Authors: Wang Xudong
Published: October 2015

Piezoelectric ZnO nanowires (NWs) have recently been demonstrated as a promising concept to harvest micro- and nano-scale mechanical energy from the surroundings. It is named nanogenerator. The operation principle relies on the bending of NWs by an external disturbance which creates piezoelectric potential along the deformed surfaces. The piezoelectric potential was predicted to be hundreds of milivolts per NW and the optimal power output per NW could reach a few nanowatts when it is under resonant oscillation. The first nanogenerator prototype was fabricated with vertically aligned ZnO NW arrays that were placed beneath a zigzag-shaped metal electrode with a small gap. In this design, all the NWs can be actuated simultaneously and continuously by ultrasonic waves, leading to the production of a continuous DC current. A textile fiber based nanogenerator has been developed for harvesting low-frequency vibration/friction energies. A piezoelectric thin film based nanogenerator was demonstrated to convert low-speed wind energy into electricity through the stimulated oscillation. These devices have the potential to fundamentally improve the mechanical energy harvesting capability with advanced nanostructure building blocks and compact designs, which might eventually lead to an effective power source for self-powered electronic systems with higher energy density, higher efficiency, longer life time, as well as lower cost.
Development of Laser Direct Ablation Process on Solder Resist in Printed Circuit Boards
Authors: Lee Changbo , Hong Daejo , Kim Suil , Choi Cheolho , Ryu ChangSup
Published: October 2015

In recent, the laser direct ablation process (LDA) for opening solder resist (SR) is getting the spotlight because this process favors small size opening and process shortening. However, it is concomitant with a desmear process which causes SR whitening defect. The SR whitening, in general, is known to be caused by the diffused reflection of the SR surface reformed and coarsened by the chemical reaction between the permanganate and SR polymer components. The process comprising the surface treatment on the SR prior to conducting LDA is proposed to resolve the problem. Therefore, the whitening defect-free products can be obtained even after the wet chemical desmear or plasma desmear. As an application, selective surface finish products, which are treated by gold surface finish and organic surface finish at different areas in the same substrate, can be fabricated using the LDA process.
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)
Authors: Lau J. H. , Zhan C-J , Tzeng P-J , Lee C-K , Dai M-J , Chien H-C , Chao Y-L , Li W. , Wu S-T , Hung J-F , Tain R-M , Lin C-H , Hsin Y-C , Chen C-C , Chen S-C , Wu C-Y , Chen J-C , Chien C-H , Chiang C-W , Chang H-H , Tsai W-L , Cheng R-S , Huang S-Y , Lin Y-M , Chang T-C , Ko C-D , Chen T-H , Sheu S-S , Wu S-H , Chen Y-H , Lo W-C , Ku T-K , Kao M-J , Hu D-Q
Published: October 2015

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.
Epoxy Flux – A Low Cost High Reliability Approach for PoP Assembly
Authors: Lee Ning-Cheng
Published: October 2015

Package on package (PoP) is a packaging that rapidly prevails in mobile devices of the electronic industry, due to its flexibility in combining memory and processor into one component with a reasonably low profile. However, similar to BGA, the solder joints of assembled PoP are prone to cracking upon dropping onto the floor, thus needing reinforcement by underfilling. The underfilling process needs an underfill material plus additional dispensing equipment, dispensing and flowing steps, and subsequent time-consuming curing. Furthermore, underfilled PoP suffers solder extrusion upon rework, particularly when reworking at the opposite side of the board right underneath the PoP. Epoxy flux is a new material developed to address the issues described above. It is a liquid epoxy with fluxing power, and it is compatible with solder paste. Applied by a dipping process, epoxy flux can be used at the mounting of bottom package and top package. First, the bottom package is dipped in a film of epoxy flux, and then placed onto the footprint pad on a PCB with or without solder paste. Then, the top package is dipped in epoxy flux and placed on top of the bottom package. The PCB with a stacked PoP is subsequently reflowed in the oven together with other surface mount components placed on printed solder paste. Epoxy flux combines soldering and reinforcement into one single process. With a controlled pick up flux volume, a venting channel is formed, allowing outgassing at reflow. The low stress characteristics of epoxy flux prevents the formation of solder extrusion. Overall, epoxy flux provides a low cost and high reliability solution for PoP assembly.
Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly
Authors: Whitmore Mark , Ashmore Clive
Published: October 2015

As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged.

A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s.

Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures having area ratios as low as 0.4. Such a breakthrough will allow the printing of ultra fine pitch components and additionally will assist with heterogeneous assembly concerns, to satisfy up and coming mixed technology demands.
Robustness and Versatility of Thin Films on Low Temperature Cofired Ceramic (LTCC)
Authors: Wolf J. A. , Peterson K. A. , Vianco P. T. , Johnson M. H. , Goldammer S.
Published: October 2015

Thin film multilayers have previously been introduced on multilayer low temperature cofired ceramic (LTCC). The ruggedness of a multipurpose Ti-Cu-Pt-Au stack has continued to benefit fabrication and reliability in state-of-the-art modules. Space optimization is described, preserving miniaturization of critical spaces and component pads. Additional soldering details are also presented, including trends with solder-stop materials. Feature compensation becomes a simple step in the normal manufacturing flow which enables exact targeting of desired feature sizes. In addition, fine details of the manufacturing process, including ion milling, will be discussed. We will discuss full long-term aging results and structural details that reinforce the reliability and function. Different thin film materials for specific applications can be exploited for additional capabilities such as filters and other integral components. Cross sections verify the results shown. This successful integration of thin films on LTCC points to higher frequencies which require finer lines and spaces. Advancements of these applications become possible due to the associated progression of smaller skin depth and thinner metallic material.

This work prepared by The Kansas City Plant for the United States Department of Energy under Contract No. DENA0000622. The Kansas City Plant is operated by Honeywell Federal Manufacturing & Technologies, LLC.
Ageing characteristics of Cu Wire Bonds on Palladium Surface Finishes
Authors: Oezkoek Mustafa , Clauberg Horst , Roberts Hugh
Published: October 2015

During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is already being used in mass production. Evaluations with even finer wire are underway.

Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate.

On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as:- Thick expensive Au layers of 0.1 to 0.4μm- Electrically connected pads (bussing for the plating) which requires added space on the substrate.- Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire

Furthermore electrolytic Ni/Au was not chosen for Cu wire bonding as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages.

This paper is offering the results of a two company joint work regarding alternative copper wire bondable surface finishes.

The result of the project is separated in 2 papers/publications. The first publication [1] presents the investigations with Cu wire bond pull forces and process windows of 23 different surface finish variations. The main aim was to identify alternative surface finishes for copper wire bonding. Within this study the surface finishes ENEP (Electroless Nickel/Electroless Palladium) and “Direct Electroless pure Pd on copper” (pure EP finish) was identified as copper wire bondable finishes with the pure Cu wire.

The second part of the evaluation summarizes an in-depth study of copper wire bonding tests after thermal aging with ENEP and the pure EP surface finish using the pure copper wire. The results of this investigation does include results with pull forces after thermal aging and an IMC Investigation with FIB Pictures of the copper wire/surface finish connection in order to evaluate the reliability of such an interconnection.
Which Frequency is Best for Wirebonding?
Authors: Sedlmair Josef , Farassat Farhad , Schlicht Franz
Published: October 2015

In industrial practice, frequencies from 40 kHz up to 160 kHz are currently employed for wire-bonding while for experimental purposes, lower and higher frequencies from around 25 kHz up to 300 kHz are discussed. Typically, heavy aluminium wire or ribbon is preferably bonded at lower frequencies between 40 and 80 kHz, while thin aluminium or gold wires are wedge- or ball-bonded at frequencies between 100 and 140 kHz.

We present a discussion of the pros and cons of different ultrasonic frequencies by looking at the mechanics during the bonding process. Higher frequencies allow shorter bonding times and permit bonding on more sensitive surfaces, but suffer from a narrower parameter window. This is mainly due to the smaller vibration amplitudes at the tool tip which can be employed for higher frequencies. The major benefit for many applications is that higher bond quality is possible even at lower wire deformation which additionally creates a healthier bond heel. Lower frequencies, on the other hand, seem to have advantages for rougher surfaces where some planarizing and smoothing is required before bonding can begin to take place, while running a higher risk of damaging the bond after forming it.

Resonance effects can seriously damage bond formation, and ways are discussed on how to deal with this problem.
Mechanical Stress Impact of Assembly Processes onto a Stress-sensitive Testchip
Authors: Theuss H. , Elian K. , Fink M. , Fries M. , Kalz F.-P. , Schwabe B. , Vaupel M. , Jaroschek C. , Schubert A. , Hummel H. , Steffens O.
Published: October 2015

A semiconductor die typically undergoes a variety of assembly processes, each of them influencing the mechanical stress environment of the chip. We report on a stress-sensitive testchip and its application to measure and characterize the respective stress distributions across the die. Particularly in the field of MEMS and sensor devices, even low stresses might deteriorate the electrical performance of a device significantly, while higher stress levels may even cause cracks and irreversible damage. This is why the present methodology has a high potential to develop into a useful tool in the field of sensor package development. After a brief introduction to the sensing principle, we investigate the stress distribution in various sample assemblies – all of them targeting pressure sensors. Typical low stress packages use silicone based soft elastic encapsulations. Changing to a harder material with a young’s modulus comparable to standard mold compounds, we demonstrate an increase of the average stress level by more than one order of magnitude.
The Reliability Impact of Reballing COTS Pb-Free BGAs to Sn/Pb for Military Applications
Authors: Caswell Greg , Arnold Joelle
Published: October 2015

The electronics assembly market has experienced a material shift from lead (Pb) based solders to Pb-free solders. This is a result of the widespread adoption of Reduction of Hazardous Substances (RoHS) legislation and practices in commercial industry. As a result, it is becoming increasingly difficult to procure commercial off-the-shelf (COTS) components with tin-lead (SnPb) solder balls or finish.

There are essentially three responses to the scarcity of acceptable SnPb parts: custom order, post process or adapt. Custom ordering parts with SnPb finishes negates the benefits of COTS based acquisition; however, has a reduced reliability risk because the material and processes are known. Reprocessing parts once in house saves money because the parts are COTS, but expends money and resources by performing post processing on them.

Also, the additional touch labor and handling increases the risk of damaging the part. Finally, adapting to Pb-free finishes is the preferred long term approach because it preserves the cost benefits of using COTS parts and does not require post processing. It is the riskiest approach due to the lack of historical data in the DoD environment.

This paper presents results regarding reballing 208 I/O Ball Grid Array (BGA) parts from tin-silver-copper (SAC305) solder to SnPb eutectic solder. It is important to understand the reliability risks associated with the reballing procedure, particularly as it relates to thermal cycling, shock and vibration environments. Three major efforts will be presented to answer these concerns.

First, a survey of reballing vendors was performed to better understand the processes and variables associated with that industry. The results of that survey were used to down-select to five vendors that were used for the physical testing portion of the effort. Finally, physical testing consisting of thermal cycling, shock, and vibration was performed. The physical testing was performed on parts from the five different reballing vendors as well as native SnPb parts and native SAC305 parts. The results of these activities will be presented.
Materials Selection and Processing Techniques for Small Spacecraft Solar Cell Arrays
Authors: Torabi N. Meetra , Lumpp Janet K. , Lumpp James E.
Published: October 2015

Body mounted germanium substrate solar cell arrays form the faces of many small satellite designs to provide the primary power source on orbit. High efficiency solar cells are made affordable for University scale satellite programs as triangular devices trimmed from wafer scale solar cells. The smaller cells allow the array designs to pack tightly around antenna mounts and payload instruments, giving the board design more flexibility. We are investigating the reliability of solar cells attached to FR-4 and carbon core laminate printed circuit boards. FR-4 circuit boards have significantly higher thermal expansion coefficients and lower thermal conductivities than germanium. This thermal expansion coefficient mismatch between the FR-4 board and the components used cause major concern for the power system when considering a failure of the solar cells, such as a series of cracked cells or faulty solder joints. These failures are most likely to happen with a longer orbital lifetime and longer exposure to the harsh environment the satellite will experience while in orbit. Carbon core laminates provide an advanced alternative because the core thickness can be selected to more closely match the device substrate, or at least provide a wider thermal expansion coefficient range to match the components on the board. We are also comparing various methods of attaching the solar cells to the printed circuit boards, using solder paste alone and in parallel with a silicone adhesive, considering the application of these adhesives by comparing the solder joints under x-ray when applied by screen printing versus stencil printing, and looking closely at the cleaning processes for array assembly. Storage, vacuum exposure, thermal cycling, functional and vibration testing will be used to compare the survivability and performance of the solar arrays.
Optoelectronic Substrate With High-Aspect-Ratio Optical Through-Hole for Chip-to-Chip Interconnects
Authors: Suzuki Atsushi , Takagi Yutaka , Horio Toshikazu , Kojima Toshifumi , Takada Toshikatsu , Iio Satoshi , Okuyama Masahiko
Published: October 2015

We report high-aspect-ratio optical through-holes fabricated in optoelectronic substrates for chip-to-chip optical interconnections. They are used for transmitting optical signals vertically through the optoelectronic substrate. They consist of cladding layer and cores that are 50 μm in diameter. Their lengths are 1.2 mm equal to the thickness of the substrate. This small diameter enables the optical through-holes to achieve low-loss optical coupling with a polymer optical waveguide. This thickness of the optoelectronic substrate accommodates embedded capacitor integration under CPUs. The capacitor will improve power supply to the CPU and co-planarity for both package level and board level assembly.

We have evaluated the optical characteristics of the high-aspect-ratio optical through holes. We have measured optical loss and crosstalk. Optical coupling dependencies of alignment offset for the optical through-holes are also evaluated to clear the effects of misalignment. The optical loss of core-cladding optical through-hole was 1.3 dB that was 2.9 dB better than that of only one kind of transparent resin and 3.8 dB better than that of a vacant drilled hole. The narrowest 1-dB coupling tolerance was +/− 12 μm from the transmitter optical through-hole to the optical waveguide. Total optical loss was estimated to be 6.8 dB from a vertical-cavity surface-emitting laser through 100-mm polymer waveguide with two 45°-ended mirrors to a photodiode.
An Innovative High Thermal Conductive Solderable Adhesive
Authors: Liu Mary , Yin Wusheng
Published: October 2015

With increasing LED development and production, thermal issues are becoming more and more important for LED devices, particularly true for high power LED and also for other high power devices. In order to dissipate the heat from the device efficiently, Au80Sn20 alloy is being used in the industry now. However there are a few drawbacks for Au80Sn20 process: (1) higher soldering temperature, usually higher than 320 °C; (2) low process yield; (3) too expensive.

In order to overcome the shortcomings of Au80Sn20 process, YINCAE Advanced Materials, LLC has invented a new solderable adhesive – TM 230. Solderable adhesives are epoxy based silver adhesives. During the die attach reflow process, the solder material on silver can solder silver together, and die with pad together. After soldering, epoxy can encapsulate the soldered interface, so that the thermal conductivity can be as high as 58 W/mk. In comparison to Au80Sn20 reflow process, the solderable adhesive has the following advantages: (1) low process temperature – reflow peak temperature of 230 °C; (2) high process yield – mass reflow process instead of thermal compression bonding process; (3) low cost ownership. In this paper we are going to present the die attach process of solderable adhesive and the reliability test. After 1000 h lighting of LED, it has been found that there is almost no decay in the light intensity by using solderable adhesive – TM 230.
3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain
Authors: Gu S.Q. , King D.W. , Ramachandran V. , Henderson B. , Ray U. , Nowak M.
Published: October 2015

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices.

In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.
A Novel Wafer-Level Double Side Packaging and Its Microwave Performance
Authors: Chen Xiao , Tang Jiajie , Xu Gaowei , Luo Le
Published: October 2015

In this paper, a wafer-level System-in-Packaging structure using through silicon via (TSV) for integration on both sides of the silicon wafer is presented. It is composed of BCB/ metal multilayers, high-resistivity silicon substrate with TSV. To reduce the transmission loss in microwave frequency, not only the high-resistivity silicon is used, but also a special TSV structure with 6 grounded shielding vias around the core via are adopted. Microstrip line (MSL) is used to transmit high-frequency signal on package plane together with the low permittivity intermediate dielectric polymer, BCB. Descriptions on the interconnection structure and the fabrication process are included. The microwave measurement result of the MSL connected by TSVs is measured up to 35GHz. The results of both the simulation and the measurement are presented.
High-Reliability Component Attachment Process for <5μm Placement Accuracy
Authors: Beck Donald J. , Bok Zeger , Martinez Daniel
Published: October 2015

As complex microelectronic packaging designs and components mature, improved placement accuracy becomes increasingly more important. High-accuracy placement has been an ongoing theme in the commercial assembly arena for several years. For example, some phononic designs require better than 2μm precision placement for optimum performance.

Military and aerospace companies routinely evaluate higher precision technologies, although this has been traditionally accomplished using semi-automatic bonder equipment. A manual or semi-automatic process is adequate and often perceived as essential for prototyping; however, semi-automatic processes are not practical for higher volume production. Aside from the slower speed of semi-automatic equipment, application performance relies on how well the technician can target the die since these systems mainly require manual alignment.

This paper presents a process solution for automating <5μm component attach specific to organizations requiring high-reliability device packaging. The methods presented in this paper have been proven through real-world experiences related to the high-reliability microelectronics industry.
Effects of the Impurities on the Embrittlement Phenomena of Electroplated Nickel Films
Authors: Sohn Yoonchul , Bae Minjong , Song Inyong , Lee Sangeui , Kim Dongouk , Chu Kunmo , Kim Dongun , Park Sunghoon , Kim Hajin , Han Intaek
Published: October 2015

Electroplated nickel has been known to have brittle fracture problem and the phenomena originated from the fact that the nickel films contained small amounts of impurities such as hydrogen, sulfur and phosphorus which enabled plating process and improved mechanical properties (hardness) through grain refinement effect. In this study, correlation between the impurities and brittle fractures of electroplated nickel films were systematically investigated at temperature range of 673–973K. Experimental results showed that the fracture toughnesses were closely related with the microstructures of the nickel films and their impurity content. The measured KC values were ranged between 2.0 and 4.5, which were one order of magnitude lower than those of pure nickel. Activation energy for the grain growth of the nickel films was determined as 234KJ/mole.
Pb-free PBGA Design Points to Improve Handling Robustness
Authors: de Sousa Isabel , Roggeman Brian , Chacon Oswaldo , Spencer Niki , Ueno Mamoru
Published: October 2015

Pb-Free BGA solder joints are more brittle and more susceptible to interfacial fails than the leaded versions. These brittle failures typically occur if the modules are subjected to high strain rates through module handling impacts or PCB flexural stress. The high speed ball shear technique is a useful method to submit solder joints to high strain rates in a controlled manner to emulate the levels of strain the BGAs may see in handling. This measurement technique was used to evaluate different laminate design and process variables on organic laminate substrates to create a more robust Pb-Free solder joint.

Experiments were conducted to evaluate the effects and interactions of laminate, module assembly process, SAC alloy composition, and thermal treatments. Modulations of shear speed and shear angle made it possible to observe transitions from ductile to brittle solder fractures. The high speed ball shear method was successful to differentiate subtle effects resulting from different design points and process variables. The copper composition in the PbFree solder alloy, thermal history, and geometric factors such as solder volume, solder resist opening and solder resist thickness all had measurable impacts on the shear strength and transition point of ductile to brittle failure.

Some BGA configurations have also been tested in reliability, namely in thermal cycling, and were shown to meet application requirements. Optimal design points can therefore be applied to enhance handling robustness without compromising on reliability.
Material Analysis of Lead Free Solder Deposited by Electrochemical Deposition
Authors: Ritzdorf Tom , Lee Sam , Drucker Ian
Published: October 2015

Lead-free solders have essentially replaced lead-tin solders for new microelectronic applications. At the same time, many products are continuing to go through miniaturization, so the behavior of the solder material is changing as a function of the connection size. As lead-tin solder has been replaced by lead-free alloys, electrodeposited SnAg has become the standard solder alloy used on wafers. Tin-based solders exhibit a complex material structure in the deposit, as recrystallization occurs in the deposit, and as intermetallic compounds form. Understanding the complex nature of these materials is becoming increasingly important to the performance of our electronic products. We have characterized ECD SnAg solder alloy deposits in terms of composition, grain size, phase, microstructure, and texture using EBSD analysis. We will discuss the effects of modifying the process parameters on the microstructure which could implications on the performance of the solder bump as a chip-level interconnect. We have seen that the metals deposit as β-tin with finely dispersed intermetallic grains. We have also seen evidence of recrystallization of the deposit subsequent to deposition, although the recrystallization behaviour is significantly different than the well-characterized copper recrystallization. Finally, the metal at the interface below the solder reacts with Sn to form intermetallic compounds, the compositions of which are dependent on the materials present. The effects of the process parameters on the deposit properties are becoming increasingly important to understand in order to control the properties of the interconnection, and how it changes over its lifetime. We have characterized the incorporation of trace organic materials in the deposit as a function of plating parameters. The deposition of SnAg from an MSA-based plating bath is very different from the deposition of copper from a copper sulfate plating bath. We have noticed that the incorporation of organic additive materials, as well as the grain size, increases as the deposition rate is increased in the deposition of SnAg.