bluuebunny/crossref_metadata_2025 huggingface dataset:
(Invited) Fabrication of Pure-GaB Ge-on-Si Photodiodes for Well-Controlled 100-pA-Level Dark Currents
Authors: Sammak Amir , Aminian Mahdi , Qi Lin , de Boer Wiebe B. , Charbon Edoardo , Nanver Lis K.
Published: September 2014

The selective epitaxial growth of Ge-on-Si followed by in-situ deposition of a nm-thin Ga/B layer stack (PureGaB) has previously been shown to be a robust CMOS-compatible process for fabrication of Ge-on-Si photodiodes. In this paper, strategies to improve the control and reproducibility of PureGaB Ge-on-Si photodiode fabrication by reducing the local loading effects during the depositions are presented. As compared to the earlier PureGaB devices, the elimination of parasitic Ge and concomitant in-situ As-doping from oxide regions surrounding the deposition windows leads to a well-controlled process flow that improves photodiode electrical and optical characteristics. For micrometer-sized diodes, ideality factors of less than 1.1 and dark current densities in the range of 15 µA/cm2 at room temperature are now achieved. Moreover, improvements in the flatness of the Ge-island surface facilitated a process flow for contacting the diode perimeter while leaving a large oxide-covered PureGaB-only light-entrance window on the central photosensitive region. The optical characteristics of the photodiodes at the low temperature of 180 K display dark current densities of less than 150 pA/cm2 and increased sensitivity towards infrared wavelengths.
Silicon-Germanium-Silica Monolithic Photonic Integration Platform for High-Performance Optical Data Communication Systems
Authors: Yamada Koji , Tsuchizawa Tai , Nishi Hidetaka , Kou Rai , Hiraki Tatsurou , Takeda Kotarou , Fukuda Hiroshi , Okazaki Kota , Ishikawa Yasuhiko , Wada Kazumi , Yamamoto Tsuyoshi
Published: September 2014

For practical data communications applications highly-integrated silicon-based photonic devices, we have developed a silicon-germanium-silica monolithic photonic integration platform, on which high-performance silica-based passive devices and compact, high-speed silicon-based dynamic/active devices can be monolithically integrated. In the Si-Ge-silica monolithic integration, it is important to deposit index-controllable silica at a low temperature, so as not to damage the Si- and Ge-based active/dynamic devices. Using this platform, various kind of photonic devices have been integrated on a small silicon ship. On this photonic platform, moreover, high-speed electronic circuits can also be integrated.
(Invited) Photonic Interconnection Made by a Ge/SiGe MQW Modulator Connected to a Ge/SiGe MQW Photodetector through a SiGe Waveguide
Authors: Frigerio Jacopo , Chaisakul Papichaya , Marris-Morini Delphine , Rouifed Mohamed-Said , Cecchi Stefano , Chrastina Daniel , Isella Giovanni , Vivien Laurent
Published: September 2014

In this work we demonstrate a photonic interconnect made by Ge/SiGe multiple quantum well modulator and photodetector connected through a SiGe waveguide. The whole structure was grown on a silicon substrate in a single epitaxial step. We show that the Ge-rich Si1–xGex virtual substrate can act as a passive, high-quality optical waveguide on which low-temperature, epitaxial growth of Ge quantum well devices can be realized. Our approach can be extended to any Ge based optoelectronic device working within the telecommunications wavelengths and it is very promising for the realization of silicon based optical interconnections.
Low Temperature Geometrically Confined Growth of Pseudo Single Crystalline GeSn on Amorphous Layers for Advanced Optoelectronics
Authors: Li Haofeng , Brouillet Jeremy , Salas Alan , Chaffin Ian , Wang Xiaoxin , Liu Jifeng
Published: September 2014

Highly textured Ge0.91Sn0.09 is obtained on both amorphous SiO2/Si and glass substrates at low temperatures <475 oC, which shows grain sizes up to tens of microns. Strikingly, the nucleation center spacing ranges from 0.1 to 1 mm, orders of magnitude larger than common solid state crystallization. This observation indicates an exceedingly high grain growth rate vs. a low nucleation rate. Therefore, we can control nucleation sites and fabricate geometrically confined pseudo single crystalline GeSn grain using patterning techniques, including surface Sn dots/patches, local laser annealing, and nanotaper patterns. Another remarkable result is that ~9 at.% Sn is incorporated substitutionally into Ge, far exceeding the equilibrium solubility limit of ~1 at.%. The high Sn composition, together with ~0.24% thermally induced tensile strain in the film, shifts the GeSn direct band gap to ~0.5 eV (2500nm) and converts it into a direct band gap semiconductor with significantly enhanced optoelectronic properties.
(Invited) High Ge Content SiGe Thin Films: Growth, Properties and Integration
Authors: Hikavyy Andriy Yakovitch , Rosseel Erik , Dhayalan Sathish Kumar , Witters Liesbeth , Mertens Hans , Bender Hugo , Favia Paola , Loo Roger
Published: September 2014

SiGe with practically whole Ge range (0-100%) becomes a common feature in many different device architectures explored nowadays. Both strained and relaxed layers are being considered in order to strain the active channel, reduce contact resistance or simply avoid certain technological obstacles. Modern pMOS transistors already utilize SiGe with Ge concentrations up to 50%. Use of such highly strained layers demands not only carefully optimized epitaxial processes but also sets stringed requirements to the whole device production flow. This paper deals with epitaxial deposition of SiGe with high Ge content, its properties and application in Source/Drain and channel of p-type fin-FETs.
Optical and Electronic Propreties of GeSn and GeSiSn Heterostructures and Nanowires
Authors: Attiaoui Anis , Moutanabbir Oussama
Published: September 2014

The first part of this work reports on detailed studies of the influence of both strain and composition on the band structure of GeSiSn ternary alloys. First, we developed a simple yet rigorous semi-empirical second nearest neighbors tight binding sp3s* method that incorporates the effect of substitutional disorder. We have found that the composition of α-Sn at the direct to indirect crossover of the ternary alloy decreases from 11% in a fully relaxed alloy to 7% in tensile strained alloy (for a strain value of 0.71%). In the latter case, we have considered a thin GeSiSn layer is epitaxialy grown on a thin Ge substrate. The last section of this work addresses the behavior of GeSn/Ge core-shell nanowires. Herein, we have solved the effective mass Hamiltonian in cylindrical coordinates using a finite difference technique for the core-shell nanowires where the core and the shell are made of different alloys. We have found that above a critical doping concentration of 5×1016 cm-3 and below a core radius of 20 nm, the electron density is localized in the Ge shell for the Ge0.9Sn0.1/Ge core-shell nanowire system.
Characterization of Electron Emission from High Density Self-Aligned Si-Based Quantum Dots by Conducting-Probe Atomic Force Microscopy
Authors: Takeuchi Daichi , Makihara Katsunori , Ohta Akio , Ikeda Mitsuhisa , Miyazaki Seiichi
Published: September 2014

Self-aligned Si-quantum dots (QDs) with an areal density as high as ~1011 cm-2 were formed on ~1.0 nm thick SiO2/n-Si(100). For spatially-resolved characterization of electron emission from the aligned dots in a diode structure through Au top electrodes, current images were taken using atomic force microscopy in a non-contact mode while maintaining a distance of ~200 nm from the sample surface by using an Au-coated Si cantilever with DC negative bias application to an Al back contact with respect to the grounded Au top electrode at room temperature in atmosphere. In DC bias application of over -5.0 V, non-uniform current image contrast, which is attributable to local electron emission, emerged and enhanced with increasing applied bias. From the band diagram of the self-aligned dots structures at applied biases over -7 V, which is drawn by considering the dot size and oxide thickness evaluated using high resolution transmission electron microscopy observations, the quantized levels of the dots higher than the vacuum level of the top electrode and the tip are thought to be occupied by electrons, which can be interpreted in terms in which the tunneling rate between the lower to upper dots is enhanced as the electrons acquire high kinetic energies. Therefore, the observed electron emission implies quasi-ballistic transport through the aligned-dots structure.
Selective Epitaxial Si:P Film for nMOSFET Application: High Phosphorous Concentration and High Tensile Strain
Authors: Li Xuebin , Dube Abhishek , Ye Zhiyuan , Sharma Shashank , Kim Yihwan , Chu Schubert
Published: September 2014

An in-situ heavily phosphorous doped selective epitaxial Si:P process was developed to reduce the source/drain contact resistance in the scaled-down 2D and 3D nMOSFET devices. The phosphorous concentration in as-deposited Si:P epitaxial films is >1×1021 at/cc. Most of phosphorous atoms contribute to the in-film tensile strain that is comparable to Si:CP epitaxial film (with >1 at% Csub) for nMOSFETs. High-resolution XRD data and cross sectional TEM images demonstrated high quality epitaxial Si:P film grown on differently orientated substrates and planar/fin structures. Furthermore, phosphorous atoms in Si:P films can be highly activated, resulting in a low resistivity of ~0.3 mOhm-cm, by the milli-second anneal treatment without the loss of phosphorous concentration and tensile strain.
Evaluation of the Si0.8Ge0.2-on-Si Epitaxial Quality by Inline Surface Light Scattering: A Case Study on the Impact of Interfacial Oxygen
Authors: Wostyn Kurt , Kenis Karine , Rondas Dirk , Loo Roger , Hikavyy Andriy Yakovitch , Dhayalan Sathish , Douhard Bastien , Mertens Paul W. , Holsteyns Frank , De Gendt Stefan , Simpson Gavin , Bast Gerhard , Swaminathan Karthik
Published: September 2014

Inline light scattering measurements are frequently used to determine wafer quality and cleanliness. In this paper we will show how this technique can be extended to determine the crystalline quality after hetero-epitaxy. Misfits on the surface of the epitaxial layer cause increased surface light scattering. The Si0.8Ge0.2-on-Si epitaxial quality has been evaluated by surface light scattering. A correlation is observed with the controlled variation of the interfacial oxygen between the Si substrate and epitaxial Si0.8Ge0.2.
Status of Large Diameter SiC Single Crystals
Authors: Ruland Gary , Wu Ping , Xu Xueping , Rengarajan Varatharajan , Zwieback Ilya , Gupta Avi , Ramm Mark
Published: September 2014

Large SiC single crystals, semi-insulating and n-type, up to 150mm in diameter are grown by II-VI Incorporated. In addition to the recent product launch of 150mm substrates, significant improvements have been made in crystal quality. The values of FWHM of x-ray rocking curves are typically 15-30 arc-seconds for 4H SI wafers and 11-25 arc-seconds for 4H n+ wafers. We have achieved 150 mm wafers free of stacking faults and micro pipes with total dislocation density of 2x103 cm-2, TSD density of ~3x102 cm-2, and BPD density of 2x102 cm-2. For semi-insulating wafers we have achieved resistivities in excess of 1E11Ω-cm.
An Ultra Compact GaN 3x3 Matrix Converter
Authors: Nagai Shuichi , Yamada Yasuhiro , Kawai Yasufumi , Negoro Noboru , Handa Hiroyuki , Hiraiwa M , Ueno H , Kudoh Yuji , Mizutani Kenji , Ishida Masahiro , Ueda Tetsuzo , Otsuka Nobuyuki , Ueda Daisuke
Published: September 2014

In this paper, we describe compact isolated gated drivers with Drive-by-Microwave (DBM) technology, which can provide isolated gate signal and power all together by a microwave wireless power transmission. The fabricated GaN gate driver successfully drives a GaN power switching device without an isolated voltage source. Furthermore, an ultra-compact GaN 3x3 matrix converter with DBM technology is presented, which is composed of a GaN-GIT (Gate Injection Transistor) bi-directional power switches integration chip, electro-magnetic resonant coupling based isolated dividing couplers in printed circuit board to reduce the complicated gate lines, and an one-chip and low consumption GaN/Si DBM driver chip for 9 bi-directional power switch control. The proposed GaN 3x3 matrix converter for 5.0kW is overwhelmingly compact such as 25mm x 18mm because of GaN power device integration and the DBM technology. Furthermore the power consumption for all divers is very low as 2.0W due to the isolated microwave power source sharing.
Stacking Fault Formation during Homo-Epitaxy of 4H-SiC
Authors: Wang Huanhuan , Wu Fangzhen , Yang Yu , Guo Jianqiu , Raghothamachar B , Dudley Michael , Zhang Jie , Chung G , Thomas Berndt , Sanchez Edward K , Mueller Stephan , Hansen Darren , Loboda Mark
Published: September 2014

Synchrotron topographic and optical microscopic studies are presented of stacking faults formed during homo-epitaxy of 4H-SiC. Grazing incidence synchrotron white beam x-ray topographs reveal V and Y shaped features which transmission topographs reveal to be ¼[0001] Frank-type stacking faults. Geometric analysis of the size and shape of these faults indicates that they are fully contained within the epilayer and appear to be nucleated at the substrate/epilayer interface. Detailed analysis shows that the positions of the V shape stacking faults match with the positions of c-axis threading dislocations with Burgers vectors of c or c+a in the substrate and thus appear to result from the deflection of these dislocations during epilayer growth. Similarly, the Y shaped defects match well with the substrate surface intersections of c-axis threading dislocations with Burgers vectors of c or c+a in the substrate which were deflected onto the basal plane during substrate growth. A model for their formation mechanism is presented.
Thermodynamics and Kinetics of SiC CVD Epitaxy
Authors: Yanguas-Gil Angel , Shenai Krishna
Published: September 2014

One of the challenges in modeling epitaxial growth is to establish a connection between the experimental conditions and microstructure and epitaxial quality of the films. At the core of this problem is the need to have accurate models of the heterogeneous chemistry during epitaxy that can bridge reactor scale with atomic scale simulations and take into account the impact of film microstructure. In this work we focus on the heterogeneous chemistry models for SiC epitaxy by CVD. First, we carry out a sensitivity analysis of existing models in the literature, and we identify their limitations as well as the main reaction pathways that can be found at different experimental conditions. We then cast these models in the context of the step-flow growth. This allow us to rationalize the expected dependence of the different sticking probability values on the miscut angle and, more generally, on the surface terrace to step site ratio. Finally we show how these models can be used to bridge reactor-scale and atomistic simulations by providing sticking probabilities that depend on the surface morphology and the atomistic details of gas-surface interaction.
An Industrial 650V GaN DHEMT Cascode Technology
Authors: Tack Marnix , Moens Peter , Liu Charlie , Bauwens Filip
Published: September 2014

This paper reports on an industrial 650V GaN DHEMT cascode technology. 650V rated DHEMT power transistors are fabricated on GaN-on-Si wafers in a standard CMOS production line. The MISHEMT transistors use in-situ MOCVD grown SiN as surface passivation and gate dielectric. Detailed characterization is done on static and dynamic behavior demonstrating good performing power transistors. DHEMT transistors are mounted in a cascode configuration to realize a normally-off power switch. The basic functionality of this cascode switch is demonstrated through implementation in a 300W 100kHz PFC system. Additional in-depth study is performed through virtual prototyping and testing, revealing challenges such as cascode mid node voltage dynamics.
On the Power-Handling Capability of Wide Bandgap (WBG) Semiconductor Power Switching Devices
Authors: Shenai Krishna
Published: September 2014

Power switching devices made from wide bandgap (WBG) semiconductors such as Silicon Carbide (SiC) and Gallium Nitride (GaN) have the potential to make transformative impact on electricity infrastructure. However, limited availability, high cost, unproven application-level field-reliability, inaccurate and incomplete datasheets from the manufacturers, and most importantly - lack of trust and true collaboration among the WBG supply chain industries - are severely hindering the large-scale commercialization of WBG power conversion technology. Although SiC power diodes and power MOSFETs are commercially available for voltage ratings up to 1,700 volts from a couple of manufacturers, a careful review of the published literature and commercial product datasheets suggests that performance and reliability of these devices may be severely compromised compared to silicon power devices. For example, limited reported data available for dv/dt, avalanche, and safe-operating area (SOA) parameters of SiC power diodes and MOSFETs are inferior to silicon power devices with identical ratings. This paper presents a simple physics-based analysis of power-handling capability of WBG power devices, and explains the possible causes of limited performance and reliability of SiC power devices.
GaN/Si(111) Device Defects and Degradation Mechanisms
Authors: Christou Aristos , Shahin David
Published: September 2014

The origin of the leakage current has been explained in the present investigation by impurity states near the Si interface. However, the present investigation has discovered that commercial grade GaN/Si(111) has surfaces that include smooth areas with features; there are usually anti-phase domains with electron channeling patterns which are not sharp, and with threading dislocation densities in the 108 cm-2 range. The ultimate performance goal for GaN/Si high voltage switches is to approach the electrical performance characteristics of homoepitaxial GaN/GaN switches. A necessary condition is the elimination of APBs and the reduction of threading dislocations and oval defects.
PECVD and Thermal Gate Oxides on 3C vs. 4H SiC – Impact on Leakage, Traps and Energy Offsets
Authors: Gutt Tomasz , Przewlocki Henryk Maria , Piskorski Krzysztof , Mikhaylov Aleksey , Bakowski Mietek
Published: September 2014

Energy-band model offsets, trap density distributions and gate leakage characteristics of MOS capacitors with PECVD and thermal gate oxides on 3C- and 4H-SiC were compared. The difference in trap energy distributions between the polytypes demonstrated in this experiment confirms that the 3C-SiC polytype is less vulnerable to near-interface traps (NIT) which are found in high density in the 4H-SiC. It was also shown that the nitridation of SiO2 on SiC improves the leakage properties of the gate oxides. Finally, the energy band model of the SiC MOS devices was described quantitatively which could be considered in further development of the devices and processes.
Improvement of GaN Deep Etched Surface State by Fluorination Dedicated to Power Devices
Authors: Gosset Nicolas , Ladroue Julien , Tillocher Thomas , Lefaucheux Philippe , Boufnichel Mohamed , Dussart Rémi
Published: September 2014

In this paper, the etched surface states of GaN using two different etching techniques are reported. In Cl2/Ar ICP based plasma, two types of defect were identified: cavities and columns. A strong decrease of the cavity diameter and density on etched surface was observed with the addition of CHF3 in the chemistry. SF6 addition instead of CHF3 leads to an etched surface free of defects with low GaN etch rate similar to that obtained with IBE technique. XPS and AFM measurements revealed the importance of fluorine species which leads to the formation of a GaxFy passivation layer on the GaN etched surface.
Study of Ti-Rich and Al-Rich Contact Metallization for AlGaN/GaN HEMT Power Devices
Authors: Bertrand Dimitri , Fayolle Murielle , Torres Alphonse , Blanquet Elisabeth , Volpi Fabien
Published: September 2014

Ohmic contacts on AlGaN/GaN HEMT are sensitive to metals and annealing temperature. In this paper, we have studied a Ti/Al metallization on nitrogen-rich substrate (SiNx and AlGaN). Al-rich metallization (meaning Al in excess regarding TiAl3 stoichiometry) is shown to be not suitable for contact metallization because a detrimental porous AlN layer is formed during the 900°C annealing step. In the case of Ti-rich metallization, it is demonstrated that a nitridation appears at the interface between TiAl3 and substrate (in both SiNx and AlGaN substrates). This nitrogen pumping from the substrate appears from 600°C and is amplified at 900°C. In conclusion, it is shown that nitrogen pumping is impacted by Ti/Al ratio and by annealing temperature. Nitrogen pumping is known to be a key parameter for the formation of low resistivity ohmic contact in AlGaN/GaN HEMT. This explains why Ti/Al ratio and annealing temperature must be properly optimized.
Characterization of GaN Switches for Solar Invertors
Authors: Gachovska Tanya , Radimov Nikolay , Gerolami Chris , Orr Ray , Hudgins Jerry L , Shenai Krishna
Published: September 2014

To improve the efficiency of a solar cell application, two areas of focus are necessary. The first is to improve the quality of the solar panels; and the second is to increase the inverter efficiency, which can be accomplished by using high frequency switches with low on-state and switching losses. GaN has a significantly bigger bandgap compared to Si material, resulting in higher breakdown voltage. Also, the channel lengths of GaN MOSFETs are smaller and, therefore, have smaller gate-to-source and drain-to-source capacitance. In this work, different GaN switches are characterized through their steady state and switching characteristics. Also, the use of GaN switches in some Solantro Semiconductor Corp. applications and a comparison of the total power losses of Si and SiC switches are also presented.
ALD Applied to Conformal Rare-Earth Coating of ZnO Nanoparticles for Low Temperature Thermal Imaging Applications
Authors: Rauwel Erwan , Galeckas Augustinas , Rauwel Protima , Hansen Per-Anders , Wragg David , Nilsen Ola , Fjellvåg Helmer
Published: September 2014

We report on properties of nanocomposites composed of oxide nanoparticles (ZnO, CaHfO3 and SrHfO3) embedded in oxide rare earth (Eu2O3, Nd2O3) matrices deposited using atomic layer deposition. The embedment of nanoparticles in different oxide matrices allowed us for highlighting the role of surface defects via monitoring of the luminescence properties. We provide a comparative analysis of the photoluminescence (PL) of the bulk material, thin films, oxide nanoparticles and nanocomposites, and discuss the possible nature of the luminescent sites on the surfaces of the nanoparticles. The ZnO nanocomposites show distinguishable PL properties from those of the free-standing nanoparticles in terms of overall quantum efficiency and referring to intensity ratios of characteristic blue and green emission bands associated with radiative transitions that involve excitons and intrinsic defects, respectively. In contrast to the observed PL enhancement in the case of ZnO nanocomposites, the embedment of hafnia perovskites into oxide matrix is found to suppress the luminescence efficiency
Multiscale Simulations of ALD in Cross Flow Reactors
Authors: Yanguas-Gil Angel , Libera Joseph A. , Elam J. W.
Published: September 2014

We have developed a multiscale simulation code that allows us to study the impact of surface chemistry on the coating of large area substrates with high surface area/high aspect-ratio features. Our code, based on open-source libraries, takes advantage of the ALD surface chemistry to achieve an extremely efficient two-way coupling between reactor and feature length scales, and it can provide simulated quartz crystal microbalance and mass spectrometry data at any point of the reactor. By combining experimental surface characterization with simple analysis of growth profiles in a tubular cross flow reactor, we are able to extract a minimal set of reactions to effectively model the surface chemistry, including the presence of spurious CVD, to evaluate the impact of surface chemistry on the coating of large, high surface area substrates.
Molecular Layer Deposition of Nanoscale Organic Films for Nanoelectronics Applications
Authors: Bergsman David , Zhou Han , Bent Stacey F.
Published: September 2014

The development of new processes for depositing thin organic films has seen a renewed interest due to an increased demand for nanoelectronic devices. Tools for producing these devices, such as advanced lithographic patterning, often require ultrathin films with a high degree of compositional homogeneity. Molecular layer deposition (MLD) is a promising method for creating films with these qualities. By using an alternating sequence of self-saturating reactions, MLD can produce conformal films with a high degree of control over the composition and thickness. In a series of studies by our group, photoresist films were grown using MLD by incorporated acid-labile groups into a MLD-grown polyurea chain. The inclusion of photo acid generators was demonstrated both as a soaked-in additive as well as a polymer-bound reactive group. These films show potential as good photoresist materials, with some designs exhibiting sensitivities of 30 µC/cm2 with 100 kV electron beam exposure, and a line resolution of sub-100 nm.
Higher-K Formation in Atomic Layer Deposited Hf1-XAlxOy
Authors: Tapily Kandabara , Consiglio Steve , Clark Robert , Vasic Relja , Wajda Cory , Jordan-Sweet Jean , Leusink Gert , Diebold A.C
Published: September 2014

We have successfully deposited ALD Hf1-xAlxOy with Al/(Al+Hf)% ranging from 0 to 25% using a sequential precursor pulse method. The crystal phase was confirmed to be a mixed phase of tetragonal with monoclinic using a combination of synchrotron measurement techniques consisting of grazing incidence X-ray diffraction, and grazing incidence extended X-ray absorption fine structure. We observed an enhancement in electrical properties near the crystallization temperature of the Hf1-xAlxOy films. In addition, the leakage current was also reduced by a factor of 10 while maintaining a flat-band voltage that is comparable to post deposition annealed (PDA) HfO2 films processed under identical conditions. An EOT reduction of ~2Å EOT with lower gate leakage was obtained for devices with post deposition anneal near the crystallization temperature of the Hf1-xAlxOy films.
Engineering the III-V Gate Stack Properties by Optimization of the ALD Process
Authors: Sioncke Sonja , Nyns Laura , Ivanov Tsvetan , Lin D , Franco Jacopo , Vais Abhitosh , Ameen Mahmoud , Delabie Annelies , Xie Qi , Maes Jan Willem , Tang Fu , Givens Michael , Van Elshocht S. , Holsteyns Frank , Barla Kathy , Collaert Nadine , Thean Aaron , De Gendt Stefan , Heyns Marc
Published: September 2014

The passivation of the III-V/high-k interface is of key importance in order to bring these materials into the 7 nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons and therefore the mobility will drop and the SS (Subthreshold Slope) will degrade. Additional defects present in the oxide near the III-V interface will generate device instabilities: the targeted amount of oxide traps should be below <1.5E10 /cm2 at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5 nm). However, the oxide trap behavior seems to change only slightly with the ALD process and further improvement of the ALD process is required when introducing the III-V materials into the 7 nm technology node.
Manganese Precursor Selection and the Thermal Atomic Layer Deposition of Copper/Manganese Alloy Films
Authors: Kalutarage Lakmal C. , Clendenning Scott B. , Winter Charles H.
Published: September 2014

This paper describes the thermal ALD growth of Cu/Mn alloy films using the precursors Cu(OCHMeCH2NMe2)2, Mn2(tBuNCHC(tBu)(Me)O)4, and BH3(NHMe2) at 160 °C. Deposition rates of about 0.09 Å/cycle were observed on a variety of substrates. Cu:Mn ratios of about 70:30 were obtained by controlling the number of Cu and Mn cycles. X-ray photoelectron spectroscopy supports the presence of metallic Cu and Mn within the Cu/Mn alloys. Similar precursors and chemistry were used to deposit 35-50 nm thick Cu/Mn/Cu film stacks on Ru, Pd, and Pt substrates. Depth profiling of stacks that were overcoated with an SiO2 layer showed that the Mn atoms diffuse to the SiO2/Cu interface in samples grown on Pd and Pt, both in as-deposited films and those that were annealed at 350 °C. With Ru substrates, the Mn atoms collected slightly at the SiO2/Cu interface, but primarily remained distributed throughout the film in as-deposited and annealed samples.
Promoted Platinum Catalytic Activity and Thermal Stability with Nano-Scale Cobalt Oxide Coating via Atomic Layer Deposition
Authors: Cao Kun , Huang Bin , Zhang Yihang , Liu Xiao , Shan Bin , Chen Rong
Published: September 2014

Ultra-thin cobalt oxide has been deposited on the Pt nanoparticles to enhance the metal nanoparticles thermal stability. The thickness of protective Co3O4 coating layer can be accurately controlled around 1nm via atomic layer deposition. The Pt catalytic activity towards CO oxidation has been investigated in a micro flow reactor. In contrast to alumina oxide coating, the cobalt oxide coated Pt nanoparticles has demonstrated lower conversion temperature than bare Pt nanoparticles. Moreover the coated Pt nanoparticles show good sintering resistance up to 700°C in atmosphere condition.
Nanomechanical Properties of Tungsten Trioxide (WO3) Grown by Atomic Layer Deposition
Authors: Mamun M A , Zhang Kai , Baumgart Helmut , Elmustafa A A
Published: September 2014

Tungsten oxide WO3 films were deposited on p-type Si (100) substrates using atomic layer deposition (ALD) technology with 200 and 600 ALD deposition cycles and annealed at different temperatures. The thicker 600 ALD cycle WO3 samples were annealed at 150, 250, and 300 °C, whereas the thinner 200 ALD cycle sample was annealed at 250 °C. We tested these films for structural and nanomechanical properties and for surface morphology using nanoindentation. The structural and surface properties were explored using X-ray diffraction, scanning electron microscopy and atomic force microscopy. We discuss the influence of the deposition technique on the structure and properties of the WO3 films citing the characteristic features of the ALD technique that was used in the synthesis of the films that are presented in this study. The results depict no significant difference in the hardness among the different films and annealing temperatures. The SEM images exhibit radial cracks in all the samples tested for a 1 µm deep indents.
Heteroleptic Precursors for Atomic Layer Deposition
Authors: Niinistö Jaakko , Blanquart Timothee , Seppälä Sanni , Ritala Mikko , Leskelä Markku
Published: September 2014

As the atomic layer deposition (ALD) method is based on sequential, self-limiting surface reactions the precursor chemistry is the key to a successful processing of conformal high quality thin films. ALD precursor chemistry has traditionally been based on homoleptic compounds such as, but not limited to, metal halides, alkylamides and alkoxides. However, these precursors sometimes have drawbacks such as possible halide contamination and low thermal stabilities. Consequently, heteroleptic precursors have been investigated as alternatives to the existing homoleptic counterparts, leading to the development of several advantageous processes. Here, examples of heteroleptic precursors for ALD processes of transition metals and their oxides are given. Special focus is given to oxides of the rare earths and groups 4 and 5. Trends in the properties of heteroleptic precursors are discussed. Several examples of our recent results are shown, including introduction of novel processes based on amidinate-cyclopentadienyl complexes for ALD of rare earth oxides.
Selective-Area Atomic Layer Deposition of Copper Nanostructures for Direct Electro-Optical Solar Energy Conversion
Authors: Willis Brian G. , Qi Jie , Jiang Xiaoqiang , Chen James , Weisel Gary J. , Zimmerman Darin T.
Published: September 2014

We investigate selective-area atomic layer deposition (ALD) of copper onto nanofabricated palladium structures for plasmonic applications in electro-optic conversion devices. We examine arrays of nanofabricated tip shaped electrodes for the formation of geometrically asymmetric tunnel junctions. We find ALD growth to be sensitive to sample pretreatment, and demonstrate that UV-ozone treatment is effective for initiating growth. We show that nucleation density and grain evolution are important properties of growth because ALD deposited topological features are on the same scale as the nanostructures. We predict electric-field intensities within the gap region between electrodes to scale exponentially with ALD growth. We establish the basis for ALD tuning of plasmonic nanostructures.
Plasmonics and Metamaterials with Transparent Conducting Oxides
Authors: Abb Martina , Wang Yudong , Traviss D , Bruck R , de Groot C. H. , Chong Harold , Sepulveda Borja , Muskens Otto L.
Published: September 2014

Metal oxides are materials of great interest for a wide range ofapplications in electrochemistry, catalysis, sensing, and electronics.We show that highly doped transparent conducting oxides can becombined with plasmonics to enhance functionality, or can be usedas novel plasmonic materials exhibiting resonances in the midinfrared.
(Invited) A Bottom-up SiNW AMOSFET Fabrication Approach Giving SOI Level Performance
Authors: Nam Wook Jun , Pan Suxing , Garg Pranav , Fonash Stephen J
Published: September 2014

A new fabrication approach for AMOSFETs (junctionless transistors) is demonstrated using a-Si:H and XeF2 as a sacrificial material and an etchant, respectively. The new approach, which provides advantages of our previous encapsulated and extruded Grow-in-Place approaches, can offer; (1) precise control of position and dimension of grown silicon nanowires (SiNWs) and (2) excellent material properties of grown SiNWs. The resulting AMOSFETs provide on/off current ratios of 106 and a subthreshold slope of ~ 90 mV/dec.
Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization
Authors: Yamano Masayuki , Kuroki Shin-Ichiro , Hirata Tatsuaki , Sato Tadashi , Kotani Koji , Kikkawa Takamaro
Published: September 2014

Highly biaxially oriented linearly arranged poly-Si thin films were formed by double-line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and an energetically stable Σ3 grain boundary was dominantly observed. Silicon grains were elongated along the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were formed. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low-temperatures (≦550゜C) by a metal gate self-aligned process and a TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. Also, electron field effect mobility variation of below 10% was obtained at the same crystallization region. Leakage current mechanism was also investigated by temperature dependence of the TFT characteristics.
(Invited) Self-Aligned Bottom-Gate InGaZnO Thin-Film Transistor with Source and Drain Regions Formed by Selective Deposition of Fluorinated SiNx Passivation
Authors: Furuta Mamoru , Jiang Jingxin , Tatsuoka Gengo , Wang Dapeng
Published: September 2014

A novel doping method of fluorine in IGZO for making thermally stable source and drain (S/D) regions of self-aligned oxide TFTs is presented. Thermally stable IGZO homo-junction could be achieved by the selective deposition of fluorinated silicon nitride (SiNx:F) on top of the IGZO. Electrical properties of self-aligned IGZO TFT drastically improved owing to the reduction of parasitic and offset resistances in S/D regions, and the field effect mobility of 10.6 cm2×V-1×s-1 was achieved. The proposed method is an essential for making self-aligned oxide TFTs with thermally stable S/D regions.
Improvement of Electrical Properties and Bias Stability of InGaZnO Thin-Film Transistors by Fluorinated Silicon Nitride Passivation
Authors: Jiang Jingxin , Tatsuya Toda , Tatsuoka Gengo , Wang Dapeng , Furuta Mamoru
Published: September 2014

The electrical properties of InGaZnO (IGZO) thin-film transistors (TFTs) with SiOX and fluorinated silicon nitride (SiNX:F) passivation were investigated. The IGZO TFTs with SiNX:F passivation showed excellent performance and positive bias temperature stress (PBTS) stability as compared with those with SiOX passivation after annealing in N2 ambient at 350 °C for 3 hours. Long time annealing could promote fluorine (F) diffusion through an etch stopper layer to an IGZO film. The diffused F could passivate the electron traps, which were the main factor to improve the performance and bias stability of oxide TFTs. The SiNX:F passivation layer will supply F to IGZO channel layer through post-fabrication annealing, which is a novel method for making high performance and stability TFT used in next generation display.
Effects of the Bombardment of Negative Oxygen Ions on Gate Bias Stability of InGaZnO Thin Film Transistors
Authors: Kim Doohyun , Yoon Soobok , Hong MunPyo
Published: September 2014

During the sputtering process, the bombardment effect of negative oxygen ions (NOIs) on the bias stability of amorphous indium gallium zinc oxide based thin film transistors (a-IGZO TFTs) was investigated. To control the bombardment energy of NOIs, a-IGZO active layer was prepared by using a superimposed rf/dc magnetron sputter. The electrical characteristics of a-IGZO TFTs under a negative bias illumination stress (NBIS) shows the different trend with that in the dark. We propose that the heavy defects such as neutral oxygen vacancy defects (Vo) as bulk defects are closely related with the bombardment energy of the negative oxygen ions.
Interpretation of Defect States in Sputtered IGZO Devices Using I-V and C-V Analysis
Authors: Mudgal Tarun , Walsh Nathaniel , Edwards Nicholas , Manley Robert G. , Hirschman Karl D
Published: September 2014

Capacitance-voltage (C-V) analysis is a valuable tool in separating the influence of material and interface defects from other factors that influence transistor operation. Thin-film transistors and interdigitated capacitors fabricated using sputtered IGZO have been studied to enhance the interpretation of defect states. Interdigitated capacitors are representative of the TFT channel region, and large-area designs provide a high capacitance swing from depletion to accumulation. Alumina was applied for back channel passivation, with annealing performed at 400 °C in oxidizing ambient conditions. Both I-V and C-V results were used with TCAD device simulation to develop a refined material and device model.
Flash Lamp Annealing Effect on Stability of Oxide TFT
Authors: Moon Seung Jae , Yu Kyeong Min , Jeong So Hyun , Kim Ju Yeon , Kim Byung Kuk , Kim Hyoung June , Yun Eui Jung , Bae Byung Seong
Published: September 2014

Flash-lamp annealing (FLA) of a millisecond time scale has been shown to be a promising tool in the preparation of high-quality semiconducting materials. The flash lamp anneal pulse width is so small that thermal stress becomes small. We used flash-lamp annealing to improve the quality of oxide material for the thin film transistor (TFT) application. We investigated the flash lamp annealing effect to improve the stability of Oxide TFT. We have investigated Xenon (Xe) FLA effect on the stability of each IGZO single layer and Oxide TFT as varying the power of the lamp. And also, we investigated the effect of the shot numbers of the flash lamp. We measured the light illumination effect on the transfer curves. FLA improved the stability of the IGZO TFT without substrate damage. Crystallization by FLA occurred under 8kW 5shots at Room temperature (RT). The light illumination stability was better for higher energy of FLA under the non-crystallized condition, which was 8kW 5shots at RT.
(Invited) Gate Insulator for High Mobility Oxide TFT
Authors: Park Sang-Hee Ko , Kim Hee-Ok , Cho Sung-Heang , Ryu Min Ki , Yang Jong-Heon , Ko Jong-Beom , Hwang Chi-Sun
Published: September 2014

We adopted SiO2 film by means of plasma enhanced atomic layer deposition (PEALD) as the first gate insulator of top gate IGZO TFT. TFT post-annealed at 300oC shows mobility, Vth, and S.S of 39.9 cm2/V.s, -1V, and 0.32 V/dec., respectively. We investigated the effect of H in the gate insulator during the annealing with the comparison of bottom gate coplanar TFT with ALD grown alumina film as the gate insulator.
(Keynote) Epitaxy-Based Strain-Engineering Methods for Advanced Devices
Authors: Grützmacher Detlev , Wirths Stephan , Rieger Torsten , Buca Dan , Stoica Toma , Lepsa Mihail Ion , Zhao Qing-Tai , Mantl Siegfried
Published: September 2014

Progress in epitaxial methodology as well as in nanotechnology opened new routes to custom design novel device structures harboring highly mismatched layers as well as materials far beyond the solubility limit. In this paper we discuss III/V nanostructures as well as SiGeSn alloys grown on Si(100). Taking GaAs/InAs core shell nanowires as an example, the possibility to control the crystal structure enables to fabricate advanced radial/axial heterostructures by phase selective epitaxy. Controlling (GaIn)As/(GaIn)Sb core shell nanowires offer broken and staggered bandgap alignments for the design of advanced tunnel FETs. Finally (Si)GeSn alloys of extraordinary structural quality with Sn concentration up to 14% were deposited by reactive gas source epitaxy. PL and absorption data give evidence for a fundamental direct band gap in these materials. The potential of these materials for ultra-low power electronic devices as well as for optoelectronics is demonstrated.
(Invited) The Impact of a (Si)Ge Heterojunction on the Analog Performance of Vertical Tunnel FETs
Authors: Agopian Paula Ghedini Der , Martino J. A. , Vandooren Anne , Rooyackers Rita , Simoen Eddy , Thean Aaron , Claeys Cor
Published: September 2014

This work studies the impact of the germanium content in the source on analog parameters of vertical nanowire Tunnel-FETs (NW-TFETs) operating in a temperature range from room temperature to 150ºC. Although, the higher the germanium amount in the source the higher the on-state current, with respect to the analog applications the NW-TFETs performance depends mainly on the predominant conduction mechanism. At room temperature, TFETs for which BTBT is the predominant transport mechanism, present better analog performance, while at high temperature the device that is more trap-assisted-tunneling dependent presents the best performance due to its higher immunity to the drain electric field.
(Invited) Ge-on-Insulator MOSFETs for High-Performance and 3D-LSI Applications
Authors: Tezuka Tsutomu , Ikeda Keiji , Kamata Yoshiki , Kamimuta Yuuichi , Usuda Koji , Moriyama Yoshihiko , Ono Mizuki , Koike Masahiro , Oda Minoru , Irisawa Toshifumi , Mieda Eiko , Maeda Tatsuro , Jevasuwan Wipakorn , Kurashima Yuichi , Takagi Hideki , Furuse Kiyoe , Kurosawa Etsuo
Published: September 2014

Ge-on-insulator (GeOI) MOSFET structures are advantageous to suppress off-state current levels while keeping the high-performance originated from the high electron and hole mobility. On the other hand, the low thermal budget of the fabrication processes could provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs. In this paper, electrical properties and processes of strained Ge nanowire pMOSFETs and strained GeOI nMOSFETs for high performance applications are presented. Ultra-high hole mobility of over 1900 cm2/Vs and 4-times enhancement of the nMOSFET drive current are demonstrated for the p- and nMOSFETs, respectively. Poly-Ge trigate p- and nFETs on buried oxide (SiO2) layers are also presented for 3D-LSIs. Reasonable operation of sub-100 nm devices and improvement of the current drivability are demonstrated.
(Invited) Solid Phase Epitaxy of GeSn Alloys on Silicon and Integration in MOSFET Devices
Authors: Lieten Ruben R. , Maeda Tatsuro , Seo Jin Won , Jevasuwan Wipakorn , Hattori Hiroyuki , Uchida Noriyuki , Miura Shu , Tanaka Masatoshi , Fleischmann Claudia , Vantomme Andre , Johnson Brett C. , Locquet Jean-Pierre
Published: September 2014

We investigate the crystallization of amorphous Ge alloy layers on silicon substrates for optical and electronic applications. Amorphous GeSn layers are obtained by limiting the adatom surface mobility during deposition. Subsequent annealing transforms the amorphous layer into single-crystalline GeSn by solid phase epitaxy. Structural investigation shows excellent structural quality for layers with up to 6.1% Sn. The surface and interface are smooth thanks to the low thermal budget. The GeSn layers show a significant increase in optical absorption with respect to Ge. We demonstrate tensile-strained GeSn p-type pMOSFET devices on Si(111) substrates using solid phase epitaxy of amorphous GeSn layer, with 4.5% Sn and +0.33% tensile strain. Structural investigation showed the presence of twin defects in the GeSn layers after crystallization. In this work we present a method to effectively suppress the formation of twin defects. Furthermore we demonstrate the crystallization of multiple amorphous layers in a 1 step anneal.
(Invited) Alternative High n-Type Doping Techniques in Germanium
Authors: Capellini Giovanni , Klesse Wolfgang M. , Mattoni Giordano , Simmons Michelle Y. , Scappucci Giordano
Published: September 2014

In this paper we review the state of the art of high n-type doping techniques in germanium alternative to ion implantation.We discuss a novel technique for achieving ultra-high doping based on adsorption and thermal incorporation of P atoms from PH3 or P2 molecules into a Ge surface and subsequent encapsulation by Ge homoepitaxial growth. This process results in the formation of spatially-confined P δ-layers with planar electrically active densities as high as 1×1014 cm-2. Owing to the high morphological quality of the crystal matrix, it is possible to stack an arbitrary number of δ-layers and tailor the thickness of spacer layers in between to build an electrically active donor density in excess of 1020 cm-3 in a bottom-up process.
Deep-Level Defects in High-Dose Proton Implanted and High-Temperature Annealed Silicon
Authors: Jelinek Moriz , Laven Johannes , Rommel Mathias , Schustereder Werner , Schulze Hans-Joachim , Frey Lothar , Job Reinhart
Published: September 2014

We review the principal mechanisms of deep-level defect formation after proton irradiation and subsequent annealing of float zone grown crystalline silicon. Various reaction paths commonly related to vacancy-complexes, interstitial oxygen and hydrogen are discussed. In the experimental part DLTS results of proton-irradiated pn-diode structures are presented. It appears that some detected defects show a thermal stability differing from that reported in literature. Furthermore the metastability of two defects at 300 meV and 418 meV below the conduction band is examined. This behavior commonly designated to a negative-U defect is for the first time reported in a sample annealed at 350° C.