bluuebunny/crossref_metadata_2025 huggingface dataset:
Component-based synthesis of table consolidation and transformation tasks from examples
Authors: Feng Yu , Martins Ruben , Van Geffen Jacob , Dillig Isil , Chaudhuri Swarat
Published: September 2017

This paper presents a novel component-based synthesis algorithm that marries the power of type-directed search with lightweight SMT-based deduction and partial evaluation. Given a set of components together with their over-approximate first-order specifications, our method first generates a program sketch over a subset of the components and checks its feasibility using an SMT solver. Since a program sketch typically represents many concrete programs, the use of SMT-based deduction greatly increases the scalability of the algorithm. Once a feasible program sketch is found, our algorithm completes the sketch in a bottom-up fashion, using partial evaluation to further increase the power of deduction for rejecting partially-filled program sketches. We apply the proposed synthesis methodology for automating a large class of data preparation tasks that commonly arise in data science. We have evaluated our synthesis algorithm on dozens of data wrangling and consolidation tasks obtained from on-line forums, and we show that our approach can automatically solve a large class of problems encountered by R users.
Synthesizing memory models from framework sketches and Litmus tests
Authors: Bornholt James , Torlak Emina
Published: September 2017

A memory consistency model specifies which writes to shared memory a given read may see. Ambiguities or errors in these specifications can lead to bugs in both compilers and applications. Yet architectures usually define their memory models with prose and litmus tests—small concurrent programs that demonstrate allowed and forbidden outcomes. Recent work has formalized the memory models of common architectures through substantial manual effort, but as new architectures emerge, there is a growing need for tools to aid these efforts.

This paper presents MemSynth, a synthesis-aided system for reasoning about axiomatic specifications of memory models. MemSynth takes as input a set of litmus tests and a framework sketch that defines a class of memory models. The sketch comprises a set of axioms with missing expressions (or holes). Given these inputs, MemSynth synthesizes a completion of the axioms—i.e., a memory model—that gives the desired outcome on all tests. The MemSynth engine employs a novel embedding of bounded relational logic in a solver-aided programming language, which enables it to tackle complex synthesis queries intractable to existing relational solvers. This design also enables it to solve new kinds of queries, such as checking if a set of litmus tests unambiguously defines a memory model within a framework sketch.

We show that MemSynth can synthesize specifications for x86 in under two seconds, and for PowerPC in 12 seconds from 768 litmus tests. Our ambiguity check identifies missing tests from both the Intel x86 documentation and the validation suite of a previous PowerPC formalization. We also used MemSynth to reproduce, debug, and automatically repair a paper on comparing memory models in just two days.
Network configuration synthesis with abstract topologies
Authors: Beckett Ryan , Mahajan Ratul , Millstein Todd , Padhye Jitendra , Walker David
Published: September 2017

We develop Propane/AT, a system to synthesize provably-correct BGP (border gateway protocol) configurations for large, evolving networks from high-level specifications of topology, routing policy, and fault-tolerance requirements. Propane/AT is based on new abstractions for capturing parameterized network topologies and their evolution, and algorithms to analyze the impact of topology and routing policy on fault tolerance. Our algorithms operate entirely on abstract topologies. We prove that the properties established by our analyses hold for every concrete instantiation of the given abstract topology. Propane/AT also guarantees that only incremental changes to existing device configurations are required when the network evolves to add or remove devices and links. Our experiments with real-world topologies and policies show that our abstractions and algorithms are effective, and that, for large networks, Propane/AT synthesizes configurations two orders of magnitude faster than systems that operate on concrete topologies.
Alive-Infer: data-driven precondition inference for peephole optimizations in LLVM
Authors: Menendez David , Nagarakatte Santosh
Published: September 2017

Peephole optimizations are a common source of compiler bugs. Compiler developers typically transform an incorrect peephole optimization into a valid one by strengthening the precondition. This process is challenging and tedious. This paper proposes Alive-Infer, a data-driven approach that infers preconditions for peephole optimizations expressed in Alive. Alive-Infer generates positive and negative examples for an optimization, enumerates predicates on-demand, and learns a set of predicates that separate the positive and negative examples. Alive-Infer repeats this process until it finds a precondition that ensures the validity of the optimization. Alive-Infer reports both a weakest precondition and a set of succinct partial preconditions to the developer. Our prototype generates preconditions that are weaker than LLVM’s preconditions for 73 optimizations in the Alive suite. We also demonstrate the applicability of this technique to generalize 54 optimization patterns generated by Souper, an LLVM IR–based superoptimizer.
Compositional recurrence analysis revisited
Authors: Kincaid Zachary , Breck Jason , Boroujeni Ashkan Forouhi , Reps Thomas
Published: September 2017

Compositional recurrence analysis (CRA) is a static-analysis method based on a combination of symbolic analysis and abstract interpretation. This paper addresses the problem of creating a context-sensitive interprocedural version of CRA that handles recursive procedures. The problem is non-trivial because there is an "impedance mismatch" between CRA, which relies on analysis techniques based on
regular languages
(i.e., Tarjan's path-expression method), and the
context-free-language underpinnings
of context-sensitive analysis.

We show how to address this impedance mismatch by augmenting the CRA abstract domain with additional operations. We call the resulting algorithm Interprocedural CRA (ICRA). Our experiments with ICRA show that it has broad overall strength compared with several state-of-the-art software model checkers.
Compiling without continuations
Authors: Maurer Luke , Downen Paul , Ariola Zena M. , Peyton Jones Simon
Published: September 2017

Many fields of study in compilers give rise to the concept of a join point—a place where different execution paths come together. Join points are often treated as functions or continuations, but we believe it is time to study them in their own right. We show that adding join points to a direct-style functional intermediate language is a simple but powerful change that allows new optimizations to be performed, including a significant improvement to list fusion. Finally, we report on recent work on adding join points to the intermediate language of the Glasgow Haskell Compiler.
Similarity of binaries through re-optimization
Authors: David Yaniv , Partush Nimrod , Yahav Eran
Published: September 2017

We present a scalable approach for establishing similarity between stripped binaries (with no debug information). The main challenge in binary similarity, is to establish similarity even when the code has been compiled using different compilers, with different optimization levels, or targeting different architectures. Overcoming this challenge, while avoiding false positives, is invaluable to the process of reverse engineering and the process of locating vulnerable code.

We present a technique that is scalable and precise, as it alleviates the need for heavyweight semantic comparison by performing
out-of-context re-optimization
of procedure fragments. It works by decomposing binary procedures to comparable fragments and transforming them to a
canonical, normalized form
using the compiler optimizer, which enables finding equivalent fragments through simple syntactic comparison. We use a statistical framework built by analyzing samples collected "in the wild" to generate a global context that quantifies the significance of each pair of fragments, and uses it to lift pairwise fragment equivalence to whole procedure similarity.

We have implemented our technique in a tool called GitZ and performed an extensive evaluation. We show that GitZ is able to perform millions of comparisons efficiently, and find similarity with high accuracy.
One Process to Reap Them All
Authors: Hussein Ahmed , Payer Mathias , Hosking Antony L. , Vick Chris
Published: September 2017

Ubiquitous mobile platforms such as Android rely on managed language run-time environments, also known as language virtual machines (VMs), to run a diverse range of user applications (apps). Each app runs in its own private VM instance, and each VM makes its own private local decisions in managing its use of processor and memory resources. Moreover, the operating system and the hardware do not communicate their low-level decisions regarding power management with the high-level app environment. This lack of coordination across layers and across apps restricts more effective global use of resources on the device.

We address this problem by devising and implementing a global memory manager service for Android that optimizes memory usage, run-time performance, and power consumption globally across all apps running on the device. The service focuses on the impact of garbage collection (GC) along these dimensions, since GC poses a significant overhead within managed run-time environments. Our prototype collects system-wide statistics from all running VMs, makes centralized decisions about memory management across apps and across software layers, and also collects garbage centrally. Furthermore, the global memory manager coordinates with the power manager to tune collector scheduling. In our evaluation, we illustrate the impact of such a central memory management service in reducing total energy consumption (up to 18%) and increasing throughput (up to 12%), and improving memory utilization and adaptability to user activities.
Improving Virtualized Storage Performance with Sky
Authors: Arulraj Leo , Arpaci-Dusseau Andrea C. , Arpaci-Dusseau Remzi H.
Published: September 2017

We introduce Sky, an extension to the VMM that gathers insights and information by intercepting system calls made by guest applications. We show how Sky gains three specific insights -- guest file-size information, metadata-data distinction, and file-content hints -- and uses said information to enhance virtualized-storage performance. By caching small files and metadata with higher priority, Sky reduces the runtime by 2.3 to 8.8 times for certain workloads. Sky also achieves 4.5 to 18.7 times reduction in the runtime of an open-source block-layer deduplication system by exploiting hints about file contents. Sky works underneath both Linux and FreeBSD guests, as well as under a range of file systems, thus enabling portable and general VMM-level optimization underneath a wide range of storage stacks.
Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching
Authors: Yang Chun , Liu Xianhua , Cheng Xu
Published: September 2017

Storage consolidation in a virtualized environment introduces numerous duplications in virtual disks and imposes considerable pressure on disk I/O and caching. In this paper, we present a content look-aside buffer (CLB) approach for simultaneously providing redundancy-free virtual disk I/O and caching. CLB attaches persistent fingerprints to virtual disk blocks, which enables detection of I/O redundancy before disk access. At run time, CLB exploits content pages already present in the guest disk caches to service the redundant reads through page sharing, thus eliminating both redundant I/O requests and redundant disk cache copies. For write requests, CLB uses a group invalidating writeback protocol for updating fingerprints to support crash consistency while minimizing disk write overhead. By implementing and evaluating a CLB prototype on KVM hypervisor, we demonstrate that CLB delivers considerably improved I/O performance with realistic workloads. Our CLB prototype improves the throughput of sequential and random read on duplicate data by 4.1x and 26.2x, respectively. For typical read-intensive workloads, such as booting VM and launching application, CLB's I/O deduplication and cache deduplication eliminates 94.9%--98.5% of read requests and saves 50%--100% cache memory in each VM, respectively. Compared with the QEMU's raw virtual disk format, CLB improves the per-disk VM density by 8x--16x. For mixed read-write workloads, the cost of on-line fingerprint updating offsets the read benefit; nevertheless, CLB substantially improves overall performance.
Security Analysis of Encrypted Virtual Machines
Authors: Hetzelt Felicitas , Buhren Robert
Published: September 2017

Cloud computing has become indispensable in today's computer landscape. The flexibility it offers for customers as well as for providers has become a crucial factor for large parts of the computer industry. Virtualization is the key technology that allows for sharing of hardware resources among different customers. The controlling software component, called hypervisor, provides a virtualized view of the computer resources and ensures separation of different guest virtual machines. However, this important cornerstone of cloud computing is not necessarily trustworthy or bug-free. To mitigate this threat AMD introduced Secure Encrypted Virtualization, short SEV, which transparently encrypts a virtual machines memory.

In this paper we analyse to what extend the proposed features can resist a malicious hypervisor and discuss the tradeoffs imposed by additional protection mechanisms. To do so, we developed a model of SEV's security capabilities based on the available documentation as actual silicon implementations are not yet on the market.

We found that the first proposed version of SEV is not up to the task owing to three design shortcomings. First the virtual machine control block is not encrypted and handled directly by the hypervisor, allowing it to bypass VM memory encryption by executing conveniently chosen gadgets. Secondly, the general purpose registers are not encrypted upon vmexit, leaking potentially sensitive data. Finally, the control over the nested pagetables allows a malicious hypervisor to closely monitor the execution state of a VM and attack it with memory replay attacks.
Parallel Automata Processor
Authors: Subramaniyan Arun , Das Reetuparna
Published: September 2017

Finite State Machines (FSM) are widely used computation models for many application domains. These embarrassingly sequential applications with irregular memory access patterns perform poorly on conventional von-Neumann architectures. The Micron Automata Processor (AP) is an in-situ memory-based computational architecture that accelerates non-deterministic finite automata (NFA) processing in hardware. However, each FSM on the AP is processed sequentially, limiting potential speedups.

In this paper, we explore the FSM parallelization problem in the context of the AP. Extending classical parallelization techniques to NFAs executing on AP is non-trivial because of high state-transition tracking overheads and exponential computation complexity. We present the associated challenges and propose solutions that leverage both the unique properties of the NFAs (connected components, input symbol ranges, convergence, common parent states) and unique features in the AP (support for simultaneous transitions, low-overhead flow switching, state vector cache) to realize parallel NFA execution on the AP.

We evaluate our techniques against several important benchmarks including NFAs used for network intrusion detection, malware detection, text processing, protein motif searching, DNA sequencing, and data analytics. Our proposed parallelization scheme demonstrates significant speedup (25.5x on average) compared to sequential execution on AP. Prior work has already shown that sequential execution on AP is at least an order of magnitude better than GPUs, multi-core processors and Xeon Phi accelerator.
Redundant Memory Array Architecture for Efficient Selective Protection
Authors: Zheng Ruohuang , Huang Michael C.
Published: September 2017

Memory hardware errors may result from transient particle-induced faults as well as device defects due to aging. These errors are an important threat to computer system reliability as VLSI technologies continue to scale. Managing memory hardware errors is a critical component in developing an overall system dependability strategy. Memory error detection and correction are supported in a range of available hardware mechanisms. However, memory protections (particularly the more advanced ones) come at substantial costs in performance and energy usage. Moreover, the protection mechanisms are often a fixed, system-wide choice and can not easily adapt to different protection demand of different applications or memory regions.

In this paper, we present a new RAIM (redundant array of independent memory) design that compared to the state-of-the-art implementation can easily provide high protection capability and the ability to selectively protect a subset of the memory. A straightforward implementation of the design can incur a substantial memory traffic overhead. We propose a few practical optimizations to mitigate this overhead. With these optimizations the proposed RAIM design offers significant advantages over existing RAIM design at lower or comparable costs.
Scalpel
Authors: Yu Jiecao , Lukefahr Andrew , Palframan David , Dasika Ganesh , Das Reetuparna , Mahlke Scott
Published: September 2017

As the size of Deep Neural Networks (DNNs) continues to grow to increase accuracy and solve more complex problems, their energy footprint also scales. Weight pruning reduces DNN model size and the computation by removing redundant weights. However, we implemented weight pruning for several popular networks on a variety of hardware platforms and observed surprising results. For many networks, the network sparsity caused by weight pruning will actually hurt the overall performance despite large reductions in the model size and required multiply-accumulate operations. Also, encoding the sparse format of pruned networks incurs additional storage space overhead. To overcome these challenges, we propose Scalpel that customizes DNN pruning to the underlying hardware by matching the pruned network structure to the data-parallel hardware organization. Scalpel consists of two techniques: SIMD-aware weight pruning and node pruning. For low-parallelism hardware (e.g., microcontroller), SIMD-aware weight pruning maintains weights in aligned fixed-size groups to fully utilize the SIMD units. For high-parallelism hardware (e.g., GPU), node pruning removes redundant nodes, not redundant weights, thereby reducing computation without sacrificing the dense matrix format. For hardware with moderate parallelism (e.g., desktop CPU), SIMD-aware weight pruning and node pruning are synergistically applied together. Across the microcontroller, CPU and GPU, Scalpel achieves mean speedups of 3.54x, 2.61x, and 1.25x while reducing the model sizes by 88%, 82%, and 53%. In comparison, traditional weight pruning achieves mean speedups of 1.90x, 1.06x, 0.41x across the three platforms.
PowerChief
Authors: Yang Hailong , Chen Quan , Riaz Moeiz , Luan Zhongzhi , Tang Lingjia , Mars Jason
Published: September 2017

Modern user facing applications consist of multiple processing stages with a number of service instances in each stage. The latency profile of these multi-stage applications is intrinsically variable, making it challenging to provide satisfactory responsiveness. Given a limited power budget, improving the end-to-end latency requires intelligently boosting the bottleneck service across stages using multiple boosting techniques. However, prior work fail to acknowledge the multi-stage nature of user-facing applications and perform poorly in improving responsiveness on power constrained CMP, as they are unable to accurately identify bottleneck service and apply the boosting techniques adaptively.

In this paper, we present PowerChief, a runtime framework that 1) provides joint design of service and query to monitor the latency statistics across service stages and accurately identifies the bottleneck service during runtime; 2) adaptively chooses the boosting technique to accelerate the bottleneck service with improved responsiveness; 3) dynamically reallocates the constrained power budget across service stages to accommodate the chosen boosting technique. Evaluated with real world multi-stage applications, PowerChief improves the average latency by 20.3x and 32.4x (99% tail latency by 13.3x and 19.4x) for Sirius and Natural Language Processing applications respectively compared to stage-agnostic power allocation. In addition, for the given QoS target, PowerChief reduces the power consumption of Sirius and Web Search applications by 23% and 33% respectively over prior work.
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware
Authors: Li Zhaoshi , Liu Leibo , Deng Yangdong , Yin Shouyi , Wang Yao , Wei Shaojun
Published: September 2017

CPU-FPGA heterogeneous platforms offer a promising solution for high-performance and energy-efficient computing systems by providing specialized accelerators with post-silicon reconfigurability. To unleash the power of FPGA, however, the programmability gap has to be filled so that applications specified in high-level programming languages can be efficiently mapped and scheduled on FPGA. The above problem is even more challenging for irregular applications, in which the execution dependency can only be determined at run time. Thus over-serialized accelerators are generated from existing works that rely on compile time analysis to schedule the computation.

In this work, we propose a comprehensive software-hardware co-design framework, which captures parallelism in irregular applications and aggressively schedules pipelined execution on reconfigurable platform. Based on an inherently parallel abstraction packaging parallelism for runtime schedule, our framework significantly differs from existing works that tend to schedule executions at compile time. An irregular application is formulated as a set of tasks with their dependencies specified as rules describing the conditions under which a subset of tasks can be executed concurrently. Then datapaths on FPGA will be generated by transforming applications in the formulation into task pipelines orchestrated by evaluating rules at runtime, which could exploit fine-grained pipeline parallelism as handcrafted accelerators do.

An evaluation shows that this framework is able to produce datapath with its quality close to handcrafted designs. Experiments show that generated accelerators are dramatically more efficient than those created by current high-level synthesis tools. Meanwhile, accelerators generated for a set of irregular applications attain 0.5x~1.9x performance compared to equivalent software implementations we selected on a server-grade 10-core processor, with the memory subsystem remaining as the bottleneck.
ShortCut
Authors: Choi Jiho , Shull Thomas , Garzaran Maria J. , Torrellas Josep
Published: September 2017

The same flexibility that makes dynamic scripting languages appealing to programmers is also the primary cause of their low performance. To access objects of potentially different types, the compiler creates a dispatcher with a series of if statements, each performing a comparison to a type and a jump to a handler. This induces major overhead in instructions executed and branches mispredicted.

This paper proposes architectural support to significantly improve the efficiency of accesses to objects. The idea is to modify the instruction that calls the dispatcher so that, under most conditions, it skips most of the branches and instructions needed to reach the correct handler, and sometimes even the execution of the handler itself. Our novel architecture, called ShortCut, performs two levels of optimization. Its Plain design transforms the call to the dispatcher into a call to the correct handler --- bypassing the whole dispatcher execution. Its Aggressive design transforms the call to the dispatcher into a simple load or store --- bypassing the execution of both dispatcher and handler. We implement the ShortCut software in the state-of-the-art Google V8 JIT compiler, and the ShortCut hardware in a simulator. We evaluate ShortCut with the Octane and SunSpider JavaScript application suites. Plain ShortCut reduces the average execution time of the applications by 30% running under the baseline compiler, and by 11% running under the maximum level of compiler optimization. Aggressive ShortCut performs only slightly better.
Clank
Authors: Hicks Matthew
Published: September 2017

The processors that drive embedded systems are getting smaller; meanwhile, the batteries used to provide power to those systems have stagnated. If we are to realize the dream of ubiquitous computing promised by the Internet of Things, processors must shed large, heavy, expensive, and high maintenance batteries and, instead, harvest energy from their environment. One challenge with this transition is that harvested energy is insufficient for continuous operation. Unfortunately, existing programs fail miserably when executed intermittently.

This paper presents Clank: lightweight architectural support for correct and efficient execution of long-running applications on harvested energy---without programmer intervention or extreme hardware modifications. Clank is a set of hardware buffers and memory-access monitors that dynamically maintain idempotency. Essentially, Clank dynamically decomposes program execution into a stream of restartable sub-executions connected via lightweight checkpoints.

To validate Clank's ability to correctly stretch program execution across frequent, random power cycles, and to explore the associated hardware and software overheads, we implement Clank in Verilog, formally verify it, and then add it to an ARM Cortex M0+ processor which we use to run a set of 23 embedded systems benchmarks. Experiments show run-time overheads as low as 2.5%, with run-time overheads of 6% for a version of Clank that adds 1.7% hardware. Clank minimizes checkpoints so much that re-execution time becomes the dominate contributor to run-time overhead.
DICE
Authors: Young Vinson , Nair Prashant J. , Qureshi Moinuddin K.
Published: September 2017

This paper investigates compression for DRAM caches. As the capacity of DRAM cache is typically large, prior techniques on cache compression, which solely focus on improving cache capacity, provide only a marginal benefit. We show that more performance benefit can be obtained if the compression of the DRAM cache is tailored to provide higher bandwidth. If a DRAM cache can provide two compressed lines in a single access, and both lines are useful, the effective bandwidth of the DRAM cache would double. Unfortunately, it is not straight-forward to compress DRAM caches for bandwidth. The typically used Traditional Set Indexing (TSI) maps consecutive lines to consecutive sets, so the multiple compressed lines obtained from the set are from spatially distant locations and unlikely to be used within a short period of each other. We can change the indexing of the cache to place consecutive lines in the same set to improve bandwidth; however, when the data is incompressible, such spatial indexing reduces effective capacity and causes significant slowdown.

Ideally, we would like to have spatial indexing when the data is compressible and TSI otherwise. To this end, we propose Dynamic-Indexing Cache comprEssion (DICE), a dynamic design that can adapt between spatial indexing and TSI, depending on the compressibility of the data. We also propose low-cost Cache Index Predictors (CIP) that can accurately predict the cache indexing scheme on access in order to avoid probing both indices for retrieving a given cache line. Our studies with a 1GB DRAM cache, on a wide range of workloads (including SPEC and Graph), show that DICE improves performance by 19.0% and reduces energy-delay-product by 36% on average. DICE is within 3% of a design that has double the capacity and double the bandwidth. DICE incurs a storage overhead of less than 1KB and does not rely on any OS support.
Bespoke Processors for Applications with Ultra-low Area and Power Constraints
Authors: Cherupalli Hari , Duwe Henry , Ye Weidong , Kumar Rakesh , Sartori John
Published: September 2017

A large number of emerging applications such as implantables, wearables, printed electronics, and IoT have ultra-low area and power constraints. These applications rely on ultra-low-power general purpose microcontrollers and microprocessors, making them the most abundant type of processor produced and used today. While general purpose processors have several advantages, such as amortized development cost across many applications, they are significantly over-provisioned for many area- and power-constrained systems, which tend to run only one or a small number of applications over their lifetime. In this paper, we make a case for bespoke processor design, an automated approach that tailors a general purpose processor IP to a target application by removing all gates from the design that can never be used by the application. Since removed gates are never used by an application, bespoke processors can achieve significantly lower area and power than their general purpose counterparts without any performance degradation. Also, gate removal can expose additional timing slack that can be exploited to increase area and power savings or performance of a bespoke design. Bespoke processor design reduces area and power by 62% and 50%, on average, while exploiting exposed timing slack improves average power savings to 65%.
Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent
Authors: De Sa Christopher , Feldman Matthew , Ré Christopher , Olukotun Kunle
Published: September 2017

Stochastic gradient descent (SGD) is one of the most popular numerical algorithms used in machine learning and other domains. Since this is likely to continue for the foreseeable future, it is important to study techniques that can make it run fast on parallel hardware. In this paper, we provide the first analysis of a technique called Buck-wild! that uses both asynchronous execution and low-precision computation. We introduce the DMGC model, the first conceptualization of the parameter space that exists when implementing low-precision SGD, and show that it provides a way to both classify these algorithms and model their performance. We leverage this insight to propose and analyze techniques to improve the speed of low-precision SGD. First, we propose software optimizations that can increase throughput on existing CPUs by up to 11X. Second, we propose architectural changes, including a new cache technique we call an obstinate cache, that increase throughput beyond the limits of current-generation hardware. We also implement and analyze low-precision SGD on the FPGA, which is a promising alternative to the CPU for future SGD systems.
A Programmable Hardware Accelerator for Simulating Dynamical Systems
Authors: Kung Jaeha , Long Yun , Kim Duckhwan , Mukhopadhyay Saibal
Published: September 2017

The fast and energy-efficient simulation of dynamical systems defined by coupled ordinary/partial differential equations has emerged as an important problem. The accelerated simulation of coupled ODE/PDE is critical for analysis of physical systems as well as computing with dynamical systems. This paper presents a fast and programmable accelerator for simulating dynamical systems. The computing model of the proposed platform is based on multilayer cellular nonlinear network (CeNN) augmented with nonlinear function evaluation engines. The platform can be programmed to accelerate wide classes of ODEs/PDEs by modulating the connectivity within the multilayer CeNN engine. An innovative hardware architecture including data reuse, memory hierarchy, and near-memory processing is designed to accelerate the augmented multilayer CeNN. A dataflow model is presented which is supported by optimized memory hierarchy for efficient function evaluation. The proposed solver is designed and synthesized in 15nm technology for the hardware analysis. The performance is evaluated and compared to GPU nodes when solving wide classes of differential equations and the power consumption is analyzed to show orders of magnitude improvement in energy efficiency.
Effect of increases in cardiac contractility on cerebral blood flow in humans
Authors: Ogoh Shigehiko , Moralez Gilbert , Washio Takuro , Sarma Satyam , Hieda Michinari , Romero Steven A. , Cramer Matthew N. , Shibasaki Manabu , Crandall Craig G.
Published: September 2017

The effect of acute increases in cardiac contractility on cerebral blood flow (CBF) remains unknown. We hypothesized that the external carotid artery (ECA) downstream vasculature modifies the direct influence of acute increases in heart rate and cardiac function on CBF regulation. Twelve healthy subjects received two infusions of dobutamine [first a low dose (5 μg·kg−1·min−1) and then a high dose (15 μg·kg−1·min−1)] for 12 min each. Cardiac output, blood flow through the internal carotid artery (ICA) and ECA, and echocardiographic measurements were performed during dobutamine infusions. Despite increases in cardiac contractility, cardiac output, and arterial pressure with dobutamine, ICA blood flow and conductance slightly decreased from resting baseline during both low- and high-dose infusions. In contrast, ECA blood flow and conductance increased appreciably during both low- and high-dose infusions. Greater ECA vascular conductance and corresponding increases in blood flow may protect overperfusion of intracranial cerebral arteries during enhanced cardiac contractility and associated increases in cardiac output and perfusion pressure. Importantly, these findings suggest that the acute increase of blood perfusion attributable to dobutamine administration does not cause cerebral overperfusion or an associated risk of cerebral vascular damage.

NEW & NOTEWORTHY A dobutamine-induced increase in cardiac contractility did not increase internal carotid artery blood flow despite an increase in cardiac output and arterial blood pressure. In contrast, external carotid artery blood flow and conductance increased. This external cerebral blood flow response may assist with protecting from overperfusion of intracranial blood flow.
Small RNA-seq during acute maximal exercise reveal RNAs involved in vascular inflammation and cardiometabolic health: brief report
Authors: Shah Ravi , Yeri Ashish , Das Avash , Courtright-Lim Amanda , Ziegler Olivia , Gervino Ernest , Ocel Jeffrey , Quintero- Pinzon Pablo , Wooster Luke , Bailey Cole Shields , Tanriverdi Kahraman , Beaulieu Lea M. , Freedman Jane E. , Ghiran Ionita , Lewis Gregory D. , Van Keuren-Jensen Kendall , Das Saumya
Published: September 2017

Exercise improves cardiometabolic and vascular function, although the mechanisms remain unclear. Our objective was to demonstrate the diversity of circulating extracellular RNA (ex-RNA) release during acute exercise in humans and its relevance to exercise-mediated benefits on vascular inflammation. We performed plasma small RNA sequencing in 26 individuals undergoing symptom-limited maximal treadmill exercise, with replication of our top candidate miRNA in a separate cohort of 59 individuals undergoing bicycle ergometry. We found changes in miRNAs and other ex-RNAs with exercise (e.g., Y RNAs and tRNAs) implicated in cardiovascular disease. In two independent cohorts of acute maximal exercise, we identified miR-181b-5p as a key ex-RNA increased in plasma after exercise, with validation in a separate cohort. In a mouse model of acute exercise, we found significant increases in miR-181b-5p expression in skeletal muscle after acute exercise in young (but not older) mice. Previous work revealed a strong role for miR-181b-5p in vascular inflammation in obesity, insulin resistance, sepsis, and cardiovascular disease. We conclude that circulating ex-RNAs were altered in plasma after acute exercise target pathways involved in inflammation, including miR-181b-5p. Further investigation into the role of known (e.g., miRNA) and novel (e.g., Y RNAs) RNAs is warranted to uncover new mechanisms of vascular inflammation on exercise-mediated benefits on health.

NEW & NOTEWORTHY How exercise provides benefits to cardiometabolic health remains unclear. We performed RNA sequencing in plasma during exercise to identify the landscape of small noncoding circulating transcriptional changes. Our results suggest a link between inflammation and exercise, providing rich data on circulating noncoding RNAs for future studies by the scientific community.
PPARγ and retinol binding protein 7 form a regulatory hub promoting antioxidant properties of the endothelium
Authors: Woll Addison W. , Quelle Frederick W. , Sigmund Curt D.
Published: September 2017

Peroxisome proliferator-activated receptors (PPARs) are a family of conserved ligand-activated nuclear receptor transcription factors heterogeneously expressed in mammalian tissues. PPARγ is recognized as a master regulator of adipogenesis, fatty acid metabolism, and glucose homeostasis, but genetic evidence also supports the concept that PPARγ regulates the cardiovascular system, particularly vascular function and blood pressure. There is now compelling evidence that the beneficial blood pressure-lowering effects of PPARγ activation are due to its activity in vascular smooth muscle and endothelium, through its modulation of nitric oxide-dependent vasomotor function. Endothelial PPARγ regulates the production and bioavailability of nitric oxide, while PPARγ in the smooth muscle regulates the vasomotor response to nitric oxide. We recently identified retinol binding protein 7 (RBP7) as a PPARγ target gene that is specifically and selectively expressed in the endothelium. In this review, we will discuss the evidence that RBP7 is required to mediate the antioxidant effects of PPARγ and mediate PPARγ target gene selectivity in the endothelium.
Downregulation of SAFB Sustains the NF-κB Pathway by Targeting TAK1 during the Progression of Colorectal Cancer
Authors: Jiao Hong-Li , Ye Ya-Ping , Yang Run-Wei , Sun Hui-Ying , Wang Shu-Yang , Wang Yong-Xia , Xiao Zhi-Yuan , He Liu-Qing , Cai Juan-Juan , Wei Wen-Ting , Chen Yan-Ru , Gu Chun-Cai , Cai Yue-Long , Hu Yun-Teng , Lai Qiu-Hua , Qiu Jun-Feng , Liang Li , Cao Guang-Wen , Liao Wen-Ting , Ding Yan-Qing
Published: September 2017

Purpose: To investigate the role and the underlying mechanism of scaffold attachment factor B (SAFB) in the progression of colorectal cancer (CRC).

Experimental Design: SAFB expression was analyzed in the Cancer Outlier Profile Analysis of Oncomine and in 175 paraffin-embedded archived CRC tissues. Gene Ontology analyses were performed to explore the mechanism of SAFB in CRC progression. Western blot, RT-PCR, luciferase assay, and chromatin immunoprecipitation (ChIP) were used to detect the regulation of transforming growth factor-β–activated kinase 1 (TAK1) and NF-κB signaling by SAFB. The role of SAFB in invasion, metastasis, and angiogenesis was investigated using in vitro and in vivo assays. The relationship between SAFB and TAK1 was analyzed in CRC tissues.

Results: SAFB was downregulated in CRC tissues, and low expression of SAFB was significantly associated with an aggressive phenotype and poorer survival of CRC patients. The downregulation of SAFB activated NF-κB signaling by targeting the TAK1 promoter. Ectopic expression of SAFB inhibited the development of aggressive features and metastasis of CRC cells both in vitro and in vivo. The overexpression of TAK1 could rescue the aggressive features in SAFB-overexpressed cells. Furthermore, the expression of SAFB in CRC tissues was negatively correlated with the expression of TAK1- and NF-κB–related genes.

Conclusions: Our results show that SAFB regulated the activity of NF-κB signaling in CRC by targeting TAK1. This novel mechanism provides a comprehensive understanding of both SAFB and the NF-κB signaling pathway in the progression of CRC and indicates that the SAFB–TAK1–NF-κB axis is a potential target for early therapeutic intervention in CRC progression. Clin Cancer Res; 23(22); 7108–18. ©2017 AACR.
Sarcomatoid Renal Cell Carcinoma: The Apple Doesn't Fall Far from the Tree
Authors: Bergerot Paulo , Agarwal Neeraj , Pal Sumanta K. , Jones Jeremy
Published: September 2017

The most comprehensive sequencing effort of sarcomatoid renal cell carcinoma (sRCC) to date reinforces the notion that the sarcomatoid component is closely related to the epithelial component of the cancer. This work also challenges the notion that sRCC evolves from low-grade RCC and identifies potential mediators of sarcomatoid differentiation. Clin Cancer Res; 23(21); 6381–3. ©2017 AACR.

See related article by Wang et al., p. 6686
Alternative Polyadenylation of PRELID1 Regulates Mitochondrial ROS Signaling and Cancer Outcomes
Authors: Gillen Austin E. , Brechbuhl Heather M. , Yamamoto Tomomi M. , Kline Enos , Pillai Manoj M. , Hesselberth Jay R. , Kabos Peter
Published: September 2017

Disruption of posttranscriptional gene regulation is a critical step in oncogenesis that can be difficult to observe using traditional molecular techniques. To overcome this limitation, a modified polyadenylation site sequencing (PAS-seq) protocol was used to generate a genome-wide map of alternative polyadenylation (APA) events in human primary breast tumor specimens and matched normal tissue. This approach identified an APA event in the PRELID1 mRNA that enhances its steady-state level and translational efficiency, and is a strong breast cancer subtype-dependent predictor of patient clinical outcomes. Furthermore, it has been demonstrated that PRELID1 regulates stress response and mitochondrial reactive oxygen species (ROS) production in a cell type–specific manner. Modulation of PRELID1 expression, including its posttranscriptional control, appears to be a common stress response across different cancer types. These data reveal that PRELID1 mRNA processing is an important regulator of cell type–specific responses to stress used by multiple cancers and is associated with patient outcomes.

Implications: This study suggests that the regulation of PRELID1 expression, by APA and other mechanisms, plays a role in mitochondrial ROS signaling and represents a novel prognostic factor and therapeutic target in cancer. Mol Cancer Res; 15(12); 1741–51. ©2017 AACR.
Definitive Chemoradiotherapy for Anal Carcinoma: Long-Term Results Based on Consistent Time-to-Event Endpoints
Authors: De Felice Francesca , Martinetti Maria Teresa , Orelli Simone , Bulzonetti Nadia , Musio Daniela , Tombolini Vincenzo
Published: September 2017

Aim: To report the long-term results after definitive chemoradiotherapy (CRT) for anal carcinoma, using consistent time-to-event endpoints. Methods and Materials: Anal carcinoma patient charts were reviewed. All patients received definitive CRT. Overall survival (OS), local failure-free survival (LFFS), locoregional failure-free survival (LRFFS), distant metastasis-free survival (DMFS), and anal dysfunction-free survival (ADFS) were estimated. Results: In total, 65 patients were included. CRT was well tolerated, with only 24.6% grade ≥3 acute toxicity. Overall, the 5-year OS, LFFS, LRFFS, and DMFS were 75.3, 60.2, 74.2, and 66.2%, respectively. Early complete clinical response and tumor stage at diagnosis were the strongest predictors of OS (p = 0.04) and local failure (p = 0.03), respectively. Conclusions: In the treatment of anal cancers, excellent ADFS and OS, and valid LFFS, LRFFS, and DMFS can be achieved with definitive CRT. Adequacy of time-to-event endpoints is paramount.
Hemothorax following Uncomplicated Endoscopic Variceal Sclerotherapy and Ligation for Esophageal Varices
Authors: Ochiai Tomoko , Nakade Yukiomi , Kitano Rena , Kato Shunsuke , Sakamoto Kazumasa , Inoue Tadahisa , Kobayashi Yuji , Ishii Norimitsu , Ohashi Tomohiko , Sumida Yoshio , Ito Kiyoaki , Nakao Haruhisa , Furuta Chihiro , Yano Motoki , Yoneda Masashi
Published: September 2017

Endoscopic variceal sclerotherapy and ligation are standard treatment modalities used for the management of esophageal varices. Reportedly, sclerotherapy and ligation are associated with complications such as hematuria, pulmonary thrombus formation, pleural effusion, renal dysfunction, and esophageal stenosis. However, hemothorax following sclerotherapy and ligation has not yet been reported. We treated a patient who presented with liver cirrhosis and polycythemia vera and later developed hemothorax following the above-mentioned procedures. An 86-year-old man diagnosed with liver cirrhosis due to chronic hepatitis type B and alcohol abuse underwent variceal sclerotherapy using ethanolamine oleate to treat his esophageal varices. Oozing from the esophageal varices continued even after the sclerotherapy procedure; therefore, we performed endoscopic variceal ligation. The patient developed left-sided hemothorax within 24 h after treatment of his varices, and an emergency thoracotomy was performed. A pulmonary ligament of the left lung was bulging and ripping because of mediastinal hematoma, and oozing was noted. Cessation of bleeding was noted after the laceration of the left pulmonary ligament had been sutured. Ours is the first case of hemothorax reported in a patient following an uncomplicated procedure of sclerotherapy and ligation.
Flora da Serra do Cipó, Minas Gerais: Asteraceae – Eupatorieae
Authors: Contro Fernanda Lechado , Nakajima Jimi Naoki
Published: September 2017

O estudo da tribo Eupatorieae é parte de um projeto mais amplo denominado “Flora da Serra do Cipó, Minas Gerais, Brasil”. Nesta área, a tribo está representada pelos seguintes gêneros e seus respectivos números de espécies: Acritopappus (1), Ageratum (3), Ayapana (1), Campuloclinium (1), Chromolaena (20), Disynaphia (1), Grazielia (1), Heterocondylus (2), Koanophyllon (1), Mikania (28), Praxelis (4), Pseudobrickellia (3), Stevia (3), Stomatanthes (1), Symphyopappus (6), Trichogonia (4) and Vittetia (1). Neste estudo apresentamos chaves de identificação para gêneros e espécies, descrições dos gêneros e espécies, comentários sobre taxonomia, distribuição geográfica, habitat e ilustrações das espécies.
Flora da Serra do Cipó, Minas Gerais: Cleomaceae
Authors: Akemi-Borges Isabela , Pirani José Rubens
Published: September 2017

O estudo da família Cleomaceae é parte do levantamento da Flora da Serra do Cipó, Minas Gerais, Brasil. Esta família está representada naquela área pelos gêneros Cleome, Dactylaena e Tarenaya, todos com apenas uma espécie. São apresentadas chave para gêneros, descrições e ilustrações das espécies, além de comentários sobre sua distribuição geográfica, fenologia e variabilidade.