bluuebunny/crossref_metadata_2025 huggingface dataset:
Droplet-on-demand Inkjet-filled Through-silicon Vias (TSVs) as a Pathway to Cost-efficient Chip Stacking
Authors: Sadie Jacob , Quack Niels , Wu Ming C. , Subramanian Vivek
Published: October 2015

Using metal nanoparticle-based inks and droplet-on-demand inkjet printing, we have demonstrated the ability to fully fill, bump, and bond through-silicon vias (TSVs). Standard thermo-compression flip-chip bonding is used to provide both robust mechanical as well as electrical contact while processing below conventional back-end-of-line (BEOL) thermal budgets. This novel process enables both the filling and bumping of TSVs in a single process step, making this process unique among conventional TSV process flows and providing a cost-effective alternative for three-dimensional integration and chip stacking at both the die-level and wafer-scale.
Packaging of 1.3 Tb/s Full Duplex Optical Interconnect
Authors: Benjamin Shuki , Hasharoni Kobi , Stepanov Stanislav , Katz Gideon , Geron Amir , Mesh Michael
Published: October 2015

The electro-optical packaging process of an optical interconnect device is described. The device has an aggregate full duplex bandwidth of 1.3 Tb/s.

The optical interconnect is assembled from a standard printed-circuit-board (PCB), an optical module chip (icPhotonics™ module) and a large format fiber-bundle.

The icPhotonics™ module is assembled from an organic substrate, an Application-Specific-Integrated-Circuit (ASIC) die, vertical-cavity surface-emitting laser (VCSEL) matrix, Photo-diode (PD) matrix and 2 micro-lens-arrays (MLA's). The data is transmitted to and from a specially designed fiber-bundle through a second set of MLA's. Each optical device consists of a 12 × 14 matrix array, where each link transmits and receives in 8 Gb/s – totaling to a 1.344 Tb/s full duplex in each optical interconnect module and a bandwidth density of 64Gb/s/mm2

The icPhotonics™ module packaging is performed using five different flip-chip and reflow or glue steps – thus maximizing module density. The optical fiber-bundle assembly is performed after the PCB is populated, and completes a full optical-interconnect.

Reliability studies had been performed successfully for the entire assembly.

The optical-interconnect PCB's are routinely fabricated in a small series production scale and used as a crucial building block in Compass-EOS core-router system, creating a full mesh optical link between different line-cards and racks
Preparation of a Wafer-level Micro Polymer Lens Array With Improved Performance Using a Low Cost Glass Mold
Authors: Ma Mengying , Qin Shunjin , Shang Jintang , Zhang Chunwei , Zhang Li , Chen Dong , Lai Chiming
Published: October 2015

In our work, polymer-based micro lens arrays with spacers were innovativly fabricated by low cost wafer-level glass-silicon molds. The upper glass mold was prepared by a well-controlled hot forming process (HFP) combined with a chemical foaming process (CFP). The under silicon mold was formed by an etching process. Before dispensing UV-curable glue between the two concave molds, the contact surface should be coated with an anti-stick layer. After UV curing and de-molding, the micro lens arrays were successfully fabricated. The lenses were inspected by an atomic force microscope(AFM), a white light interferometer and a beam analyzer. The results demonstrate the excellent quality of surface roughness and optical characteristics. This study indicates the potential of this novel molding process for industrial production.
A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology
Authors: Hechfellner Rudi , Kruger Michiel , Heemstra Tewe , Caswell Greg , Blattau Nathan , More Vikrant
Published: October 2015

Light Emitting Diodes (LEDs) are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solidstate-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance.

The LUXEON Rebel has been accepted as an industry leading LED product, widely used in Mean-Time-Between-Failure (MTBF) sensitive applications. Customers use various mounting platforms, such as FR4 Printed Circuit Board (PCB), FR4 PCB with thermal via's, Aluminum & Copper Metal Core printed Circuit Boards (MCPCB), Super MCPCB, etc. As in other LEDs, when mounting to a platform where a large Coefficient of Thermal Expansion (CTE) exists between the LED & the PCB, Solder fatigue could become an issue that may affect system level lifetime.

In this paper we have examined extreme cases and how a solder joint can impact system level reliability. We have modeled the conditions and formed a means to predict system level reliability. We have compared the prediction modeling with empirical tests for validation of the models.

It is vital to understand system level reliability factors to build lighting solutions that match the application and customer expectations. It is impractical to test LEDs and other components for 50k hours ~5 years since the device evolution is much faster than that – on average one LED generation every 12–18 month. Hence we need models and prediction methods …..
Multi-layer PC boards Fabricated using Aerosol-jet Printing
Authors: Bolger John , Lantz Leon , Lewis Rich , Trudeau Rick , Hines Daniel
Published: October 2015

Additive manufacturing methods hold several advantages over standard semiconductor fabrication techniques such as the reduction of hazardous waste, the reduction of fabrication steps and the elimination of mask sets. For prototyping, low volume manufacturing and custom parts, additive manufacturing has the potential to dramatically reduce both the time and cost of fabrication. As a demonstration of the capabilities of additive manufacturing, a ‘2-layer’ power supply circuit board was fabricated using aerosol-jet printing. Silver nanoparticle ink was used to print the conducting layers and polyimide was used to print the dielectric layer. Each layer was printed separately and sintered/cured for at least 90 minutes up to a temperature of 255 °C. For an initial proof of concept, a power supply circuit was selected, providing three different voltage outputs. In order to supply the necessary current while minimizing topology, the metal traces were designed to be as wide as possible while staying within a 16 × 20 mm footprint. Additionally, an “inverse via” scheme was utilized in which the dielectric layer was printed only where layer-to-layer isolation was needed. This minimized the amount of material used and eliminated the need to include standard vias into the design. Once printed, a 2-layer circuit board was populated by using standard pick-and-place techniques and a conductive adhesive to attach components in place. Built up boards were tested for functionality at room temperature, thermally cycled from 10 to 80 °C for 63 cycles and subjected to high temperature operational life testing at 70 °C for 96 hours. Design criteria, fabrication methods and test results will be presented in detail.
High Speed Signal Transmission using Through-Si Vias and Coplanar Waveguides in a 3D IC Test Structure
Authors: Xu Min , Geer Robert , Kabos Pavel , Wallis Thomas
Published: October 2015

High frequency signal transmission through silicon substrates is critical for 3D heterogeneous integration. This paper presented fabrication, testing, and simulation of high-frequency interconnects based on through-silicon vias (TSVs) and coplanar waveguides (CPWs) for stacked 3D integrated circuits (3D ICs). Our simulation results showed that adding ground TSVs can improve signal transmission by 6× at 50GHz. We further investigated signal/ground TSV (1SXG) configurations for high-bandwidth signal transmission links. Scattering parameter measurements of fabricated 1SXG TSV structures for frequencies from 100MHz to 50GHz show low insertion loss (S21 less than −1dB up to 50GHz) and return loss (S11 lower than −15dB). These results indicate that these vertical interconnects exhibit good performance for high speed signal transmission. To understand the RF signal transmission in 3D interconnects, we used full wave electromagnetic simulation to investigate the electromagnetic field distribution associated with the ground TSV placement. We observed that the ground TSVs induced substantial overall field confinement, consistent with the experimental observation of improved signal transmission. Simulations also provided design guidance with respect to the substrate conductivity's impact on EM confinement and signal transmission.
Warpage Characterization and Improvements for IC Packages with Coreless Substrate
Authors: Baloglu Bora , Lin Wei , Stratton Ken , Jimarez Miguel , Brady Danny
Published: October 2015

Coreless package substrates are preferred for their superior electrical performance and thin profile compare to conventional substrates with core. However, one of the major concerns with coreless substrate packages is warpage control. It is difficult to meet industry standards for co-planarity because of the high CTE of the coreless substrates and the missing stiff core material in the stack up of the coreless structure. Finite element analysis (FEA) is utilized to investigate the use of coreless substrate in different package configurations. In this study, known stiffening structures such as a stiffener ring, lid and molding options are investigated to characterize the advantages and disadvantages of using each of these structures to control the warpage in an IC package with coreless substrate. Available shadow moiré data is used for initial correlation of the finite element model and further design changes were carried out to stiffen the structure in the final packaged configuration. It is important to understand and make design considerations accordingly to improve assembly yield. Suggestions made depend on the FEA findings which would guide the selection of the stiffening structure for a package with coreless substrate.
A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION
Authors: Liu Mary , Yin Wusheng
Published: October 2015

Silicon dioxide is normally used as filler in underfill. The thermal conductivity of underfill is less than 1 w/mk, which is not able to meet the current flip chip application requirements such as 3D stacked multi-chips packaging. No matter which direction the heat will be dissipated through PCB or chip, the heat has to pass through the underfill in 3D stacked chips. Therefore the increase of thermal conductivity of underfill can significantly enhance the reliability of electronic devices, particularly in 3D package devices. YINCAE Advanced Materials, LLC has developed a novel high thermal conductive underfill for flip chip applications. Diamond powder is selected as filler in our product system due to its excellent thermal stability and high thermal conductivity. Three different diamond powders have been used as filler in underfill, the thermal conductivity has been increased many times (up to 6w/mk), which can greatly reduce the thermal stress for solder joint. The flowability, pressure cooking test and other properties of underfill have been characterized and investigated. All details will be discussed in this paper.
Solder Joint Encapsulant Adhesive – LGA High Reliability And Low Cost Assembly Solution
Authors: Liu Mary , Yin Wusheng
Published: October 2015

More and more Land Grid Array (LGA) components are being used in electronic devices such as smartphones, tablets and computers. In order to enhance LGA mechanical strength and reliability, capillary flow underfill is used to improve reliability. However, due to the small gap, it is difficult for capillary underfill to flow into the LGA at SMT level. Due to cost considerations, there are usually no pre-heating underfill or cleaning flux residue processes at the SMT assembly line. YINCAE solder joint encapsulant SMT 256 has been successfully used with solder paste for LGA assembly. Solder joint encapsulant is used in in-line LGA soldering process with enhanced reliability. It eliminates the underfilling process and provides excellent reworkability. The shear strength of solder joint is stronger than that of underfilled components. The thermal cycling performance using solder joint encapsulant is much better than that using underfill. Bottom IC of POP has been studied for further understanding of LGA assembly process parameters. All details such as assembly process, drop test and thermal cycling test will be discussed in the full paper.
Automated Wirepull Testing – Parallelogram of Forces-Real Time Application
Authors: Garcia Richard C. , Sedlmair (F&K Delvotec) Josef
Published: October 2015

In hybrid electronics, it is a standard practice to perform 100% wire bond pull testing to ensure robust wire bonding of the components. The principle behind Mil-STD-883 method 2023.5 compliant wire bond pull testing is to position the hook underneath the wire and either pull until the wire breaks or, alternatively, pull to a predefined force. With high density layouts, small component geometry or staggered wire bonds, it has been a challenge for manufacturing operations to maintain consistency in “manually” placing the wirepull hook on wires with varying height, looping profiles and wire distances. The influence of loop height and wire distance is a significant factor in determining the true wire pull strength. A low wire loop will result in lower measured pull strength, while a higher loop will result in higher pull strength. Therefore, if we can accurately quantify the loop height and profile then we can place the wirepull hook in the optimum position for pulling. In this study we will demonstrate how the “parallelogram of forces” can affect wirepull measurements. With the advent of the current generation of automated wirebond pull testers, we can accurately determine the appropriate correction factor(s) for varying loop heights in order to position the wirepull hook at the precise location necessary for accurate and meaningful results. In addition, with real time yield monitoring, the new pull testers are capable of locating and identifying missing wires that can often be attributed to the high density of today's circuit designs.
Decision Making Model for the Emerging Nanotechnologies
Authors: Dixon Audré , Verma Kewal K.
Published: October 2015

The difficulty in decision making for the emerging technologies is due to the evolving nature of the new technology, new materials, limited or unavailability of the historic and current data, private and protected nature of the data, product knowledge to monitor and control potential toxic exposure, and other untested or unavailable data on the environment and health effects. The demand for lighter material in healthcare for prosthetics, the automotive and aerospace industries search for Nano-materials. The pharmaceutical industries are challenged with the increase of systematic diseases to provide soluble drug delivery targeting affected tissue, organs, or cells. Investors are seeking opportunities to find the hidden niche in the nanotechnology markets. The ultimatum to meet these industry demands, provide opportunities to investors, newly created nanotechnology industries, and industries looking to expand in other markets. In such complex and ambiguous environment, with limited understanding or predictability for the known and unknown effects of the emerging technology on environment and health, development of the framework for a decision-making model would be an imperative. Successful and appropriate decision making model may come from the leadership insight and governance, stakeholder alliances, sharing of the unknowns, problems, solutions, and advancements. The work presented in the paper is based on the qualitative modified Delphi study by Dr. Audré Dixon for her doctoral degree in Doctor of Health Administration at the University of Phoenix Online.
A STUDY ON PREVALENT FACTORS BEHIND EFFICIENCY DETERIORATION OF A TYPICAL LOW POWER SOLAR PANEL
Authors: Ganescu V. , Pascu A.
Published: October 2015

Efficiencies for a number of different low power (10W MAX) consumer grade PV solar panels were studied in this research. Outdoor behavior was contrasted with lab environment simulations. The authors focused on four parameters: extreme temperatures of operation, duration of operation per “on” cycle, number of “on – off” cycles and overall period of “on” operation for a 365 days interval. Standard environmental operating conditions were taken into account for the lab environment, where constant solar noon was simulated for 70% of the equivalent daylight exposure time. No CPV or lenses were used. Additionally, a comparison surrounding the estimated life expectancy and efficiency decrease pattern of the panels was targeted and presented in this study.
Scaling Challenges of Semiconductor Packaging in the Era of Big Data
Authors: Orii Yasumitsu , Horibe Akihiro , Toriyama Kazushige , Matsumoto Keiji , Noma Hirokazu , Kohara Sayuri , Aoki Toyohiro , Sueoka Kuniaki , Mori Hiroyuki
Published: October 2015

In advent of multimedia, social media and Internet of Things, our world is exploding with enormous amount of data, so-called Big Data. The use of Big Data provides us with opportunities to bring solutions and innovations to variety of industries such as healthcare, energy, banking and automotive. On the other hand, the computing requirement to analyze this large volume of data is becoming higher than ever. The exascale computing is required in the Era of Big Data. In order to achieve this demand, further technology innovations for package scaling such as 3D-IC with TSV (through silicon via) are needed. The fine pitch die-to-die interconnection is a key element in increasing the total bandwidth in 3D integration. The important technologies in 3D integration include micro-bumping, thermally enhanced underfill materials and advanced interposers. Material selection for reliable fine-pitch interconnection has become a critical challenge in 3D chip stacking. Underfill material in die-to-die device is also a critical element in reducing total packaging stress and in enhancing vertical thermal conductivity. Low CTE high-density organic substrate is an emerging technology for 2.5D structure.
High Thermal Conductive Inter Chip Fill for 3D-IC through Pre-applied Joining Process
Authors: Kawase Y. , Ikemoto M. , Yamazaki M. , Sugiyama M. , Kiritani H. , Mizutani F. , Matsumoto K. , Horibe A. , Mori H. , Orii Y.
Published: October 2015

Three dimensional (3D) IC has been proposed for high performance and low power in recent years. Due to the narrow gap between stacked chips and fine pitch of bumps, new inter chip fill (ICF) which can be used for pre-applied ICF process is required. The heat generation of 3D-IC is higher than 2D, so that a high thermal conductive inter chip fill (HT-ICF) is simultaneously required to dissipate the heat from 3D-IC and for the purpose of pre-applied ICF and HT-ICF, highly active flux agent and thermal conductive materials such as filler and matrix have been called for at the same time.

In this study, some kind of materials were prepared, synthesized and optimized for the HT-ICF, and we evaluated its characteristic and confirmed applicability to pre-applied joining for 3D-IC.
Low temperature Si-Si, SiO2-SiO2 covalent bonding structures with thin siloxane layer
Authors: Lee Jeongyub , Chu Kunmo , Park Yongyoung , Yang Wooyoung , Xianyu Wenxu , Moon Changyoul
Published: October 2015

We present new Si to Si, SiO2 to SiO2 bonding technologies for low temperature applications (<200°C). Direct bonding process between Si (or SiO2) substrates makes high bonding strength without contamination problems. However, high temperature over 1000°C is needed for the reliable Si to Si and SiO2 to SiO2 direct bonding processes. To reduce the bonding temperature, thin siloxane layer and low-powered oxygen plasma treatment was used in this study. We used dimethyl siloxane layer having siloxane chains (-Si-O-)n and methyl ends. Siloxane layer is able to be bonded strongly with Si-based substrates at low temperature (<200°C) when oxygen plasma is treated on it. Polymerized siloxane layer such as PDMS has much higher coefficient of thermal expansion (CTE) of 300ppm/K than Si of 2.6ppm/K. When the bonded structure is cooled or heated, the interfaces is possibly distorted and cracked by the high residual stress between siloxane layer and Si substrate. To solve these problems, we developed new fabrications of reducing the siloxane layer thickness to 3∼4nm, that is the monomer layer levels. Extremely thin thickness of siloxane layer prevented the problems of the CTE differences. The Si to Si bonding structure with siloxane layer showed strong adhesion properties in this study. The bonded body kept reliable bonding force when it was heated to high temperature (∼900°C). The feasible wafer-level bonding process was demonstrated. We investigated the siloxane layer thickness by TEM images. The bonding strength was confirmed by dicing test by 1mm and measured over 20MPa. We also expended this new development to SiO2 to SiO2 bonding structures. Low temperature bonding between non-Si substrates such as GaN was possible with thin siloxane layer when amorphous Si thin film was deposited on these substrates.
Interactions between Variable Frequency Microwave Underfill Processing and High Performance Packaging Materials
Authors: Diop Mamadou Diobet , Paquet Marie-Claude , Drouin Dominique , Danovitch David
Published: October 2015

Variable frequency microwave (VFM) has been recently proposed as an alternative underfill curing method that provides flip chip package warpage improvement as well as potential underfill cure time reductions. The current paper outlines how such advantages in VFM processing of underfill can be compromised when applied to high performance organic packages. VFM recipes for three underfill materials were developed by performing several VFM curing runs followed by curing rate measurements using the differential scanning calorimetry method. The VFM curing rate was seen to strongly dependent upon the underfill chemistry. By testing flip chip parts that comprised large and high-end substrates, we showed that the underfill material has negligible impact on VFM warpage with the major cause attributed to the coefficient of thermal expansion mismatch between the die and the substrate. Comparison between the convection and the VFM methods indicated two warpage tendencies that depended upon the VFM curing temperature. First, when both curing methods used comparably high temperatures, warpage increases up to about + 20% were found with VFM. This unexpected result was explained by the high-density Cu loading of the substrate which systematically carried heat generated by VFM energy from the die/underfill system to the substrate. Since this high-end substrate consists of sequential dielectric/Cu layers with asymmetric distribution of Cu, additional stresses due to local CTE mismatches between the Cu and the dielectric layers were induced within the substrate processed with VFM. Second, warpage reductions down to about − 22% were obtained at the VFM curing temperature of 110°C with a curing time similar to that of convection cure. This suggests that the negative effect of the local CTE mismatches were no longer at play at the lower VFM temperatures and that the significantly lower final cure temperatures produced lower total shrinkage of the die and the substrate. Finally, due to lower elastic moduli, the cured VFM parts showed better mechanical reliability with no fails up to 1500 cycles.
Heat Sink Induced Thermo-Mechanical Joint Strain in QFN Devices
Authors: McVicker Gerard , Khanna Vijay , Sri-Jayantha Sri M.
Published: October 2015

A Blade Server System (BSS) utilizes Voltage Regulator Modules (VRM), in the form of Quad Flat No-Lead (QFN) devices, to provide power distribution to various components on the system board. Depending on the power requirements of the circuit, these VRM's can be mounted as single devices or banked together. In addition, the power density of the VRM can be high enough to warrant heat dissipation through the use of a heat sink. Typically, during field conditions (FC) the BSS are powered on and off up to four times per day, with their ambient temperature cycling between 25°C and 80°C. This cyclical temperature gradient drives inelastic strain in the solder joints due to the coefficient of thermal expansion (CTE) mismatch between the QFN and the circuit card. In addition, the heat sink, coupled to the QFN and the circuit card, can induce additional inelastic solder joint strain, resulting in early solder joint fatigue failure. To understand the effect of the heat sink mounting, a FEM (Finite Element Model) of four QFN's mounted to a BSS circuit card was developed. The model was exercised to calculate the maximum strain energy in a critical joint, due to the cyclical straining, and the results were compared for a QFN with and without a heat sink. It was determined that the presence of the heat sink did contribute to higher strain energy and therefore could lead to earlier joint failure. While the presence of the heat sink is required, careful design of the mounting should be employed to provide lateral slip, essentially decoupling the heat sink from the QFN joint strain. Details of the modeling and results, along with DIC (Digital Image Correlation) measurements of heat sink lateral slip, are presented.
A Photo-Desmear Method for Via Residue Removal Using a VUV Light Source
Authors: Habu Tomoyuki , Yabu Shintaro , Hirose Kenichi , Horibe Hiroki , Fujinami Toru , Kitano Naoki , Ozawa Eiji , Bhattacharjee Sanchali , Andideh Ebrahim , Sobieski Daniel
Published: October 2015

The desmear process of removing via residue after laser drill in substrate manufacturing is a critical step for reliability and electrical performance. Cost effective and environmentally clean desmear processes are industry-wide objectives, as the current wet desmear process results in significant chemical waste and regular bath replacement.

Here, we evaluated an effective photo desmear method targeting a low total cost of ownership and negligible environmental impact. This method achieves residue and silica free via bottoms with the use of 172nm vacuum ultraviolet light (VUV) photo-chemical ashing followed by water clean. Studies of organic molecular photochemical decomposition by short wavelength UV light are widely reported and have been applied for purposes such as surface cleaning and improving wettability and are naturally extendable to via residue removal. Scanning electron microscope (SEM) and energy dispersed X-ray spectroscopy (EDX) reveal that the application of VUV desmear results in residue free microvia without negatively affecting via shape or the dielectric surface. In addition, the surface remains highly wettable, which aids downstream copper plating. The high reaction rate, absence of wet chemistry, and creation of surfaces amenable for subsequent copper plating make this dry desmear process a strong candidate for future applications in substrate manufacturing.
Characterization of CVD Diamond for Thermal Management Applications
Authors: Balmer R.S. , Bolliger B. , Dodson J.M. , Twitchen D.J.
Published: October 2015

Data is presented on state-of-the-art microwave plasma assisted chemical vapour deposited (CVD) diamond films with thicknesses between 0.1 and 0.8 mm. Infrared transmission measurements are compared with through-thickness and in-plane thermal conductivities measured using thermal flash and heated bar techniques, respectively. A simple model is presented and discussed on the correlation between thermal conductivity and the integrated absorption in the infrared region of the spectrum between 2760 and 3030 cm−1. This correlation opens the possibility to a cost effective, repeatable measurement methodology accurate enough for quality control and new recipe development.
Organic Chip Scale Package (CSP) Development for Flip Chip Applications
Authors: Yamada Tomoyuki , Fukui Masahiro , Terada Kenji , Harazono Masaaki , Fujisaki Teruya , Reynolds Charles , Audet Jean , Pan Yi , Moore Scott , Iruvanti Sushumna , Liu Hsichang , Zhang Hongqing , Sundlof Brian
Published: October 2015

This paper describes a Chip Scale Package (CSP) development project and evaluation of the corresponding organic laminate material. Chip scale packaging can combine the strengths of various packaging technologies, such as the large size and performance advantages of a bare die assembly and the reliability of encapsulated devices. Optimizing the laminate carrier material for low CTE reduces the dimensional mis-match between chip and laminate during Bond and Assembly (BA) and mitigates Chip-Package Interactions (CPI) related fails. Utilizing a low CTE material significantly reduces the strain in the solder joints during the reflow process. Modeling laminate CSP groundrules with the organic material parameters provides stress and strain predictions and highlights parameter ranges for successful BA process capability. Predicted global and chip-site warp data from thermo-mechanical modeling are compared to the measured warpage data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated. Electrical and mechanical tests carried out on the low CTE laminate material and subsequently on the related CSP are described. Recommendations for future CSP development and testing are presented.
Si Vapor Chamber Integrated with Through Silicon Via for 3D Packaging
Authors: Taniguchi Jun , Shioga Takeshi , Mizuno Yoshihiro
Published: October 2015

We demonstrate an etched silicon vapor chamber integrated with a through-silicon via (TSV) for 3D packaging. The Si vapor chamber chip enables low mismatch in the thermal expansion coefficient of a Si-LSI chip and provides a new heat dissipation path for 3D-LSI inter layer cooling. For the first prototype of the vapor chamber, an outside 33-mm × 33-mm chip consisting of a 25-mm × 25-mm area for the vapor chamber, a wick structure 30-μm high, and a vapor passage 100-μm high is developed. In-situ observation of the behavior of the working fluid through the cover glass and heat transfer enhancement is successfully demonstrated. The improvement rate of thermal resistance is 7.1% compared to a test chip without working fluid. Next, the fluid flow of a second vapor chamber prototype consisting of the first prototype integrated with a TSV structure using a Si pillar of 150-μm diameter is investigated. Thermal resistance and droplet observation conducted to evaluate the influence of the TSV. The operation of the vapor chamber is confirmed when a Si pillar is arranged to a coarse pitch of more than 500 μm. A droplet is generated and the vapor passage is partially obstructed. However, the droplet eventually degenerated and the performance of the vapor chamber is maintained. When the Si pillar is arranged to a fine pitch of 200 μm, the entire vapor passage is blocked during the liquid charging process, and no improvement is observed in the thermal resistance of the chip.
Package design and development of a low cost high temperature (250°C), high current (50+A), low inductance discrete power package for advanced Silicon Carbide (SiC) and Gallium Nitride (GaN) devices
Authors: McPherson B. , Passmore B. , Killeen P. , Martin D. , Barkley A. , McNutt T.
Published: October 2015

The demands for high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of post silicon materials, including Silicon Carbide (SiC) and Gallium Nitride (GaN), are numerous, including: high temperature operation, high voltage blocking capability, extremely fast switching, and superior energy efficiency. These advantages, however, are severely limited by conventional power packages, particularly at temperatures higher than 175°C and >100 kHz switching speeds.

In this discussion, APEI, Inc. presents the design of a newly developed discrete package specifically intended for high performance, high current (>50A), rapid switching, and extended temperature (>250°C) wide band gap devices which are now readily available on the commercial market at voltages exceeding 1200V. Finite element analysis (FEA) results will be presented to illustrate the modeling process, design tradeoffs, and critical decisions fundamental to a high performance package design. A low profile design focuses on reducing parasitic impedances which hinder high speed switching. A notable increase in the switching speed and frequency reduces the size and volume of associated filtering components in a power converter. Operating at elevated temperatures reduces the requirements of the heat removal system, ultimately allowing for a substantial increase in the power density.

Highlights of these packages include the flexibility to house a variety of device sizes and types, co-packaged antiparallel diodes, a terminal layout designed to allow rapid system configuration (for paralleling or creating half- and full-bridge topologies), and a novel wire bondless backside cooled construction for lateral GaN HEMT devices. Specific focus was placed on minimizing the cost of the materials and fabrication processes of the package components. The design of the package is discussed in detail. High temperature testing of a SiC assembly and electrical test results of a high frequency GaN based boost converter will be presented to demonstrate system level performance advantages.
Thermal Characteristic and Performance of the Glass Interposer with TGVs (Through-Glass Via)
Authors: Chien Heng-Chieh , Chien Chun-Hsien , Dai Ming-Ji , Tain Ra-Min , Lo Wei-Chung , Lu Yung-Jean Rachel
Published: October 2015

In this study, we used simulation technique to analyze the thermal characteristics of solo TGV (through-glass via) structure and solo TSV (through-silicon via) structure. The analysis showed, no matter in in-plane direction or in cross-plane direction, the thermal conductivity of a TGV structure is much lower than that of a TSV structure. Also, using simulation, we chose a typical 2.5D IC SiP (system in package) to compare the thermal performances between the SiP with TGV interposer and TSV interposer by using simulation. The specific via structures of 30μm in diameter and 60μm in pitch were adopted in the case studies. The results show the thermal performance of the 3D IC system with TSV is slightly better than that of the system with TGV, but both performances are nearly equal. The evaluations demonstrate the ultra-low thermal conductivity does not damage the thermal performance of a 3D IC SiP with TGV interposer; and proves the feasibility of the glass interposer for electronics applications.
Advanced warpage characterization for FOWLP
Authors: Teixeira Jorge , Ribeiro Mário , Pinho Nélson
Published: October 2015

Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2].

In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3].

Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.
The Effectiveness of Screening Techniques for Revealing Cracks in High Volumetric Efficiency MLCCs
Authors: Teverovsky Alexander
Published: October 2015

Multilayer ceramic capacitors (MLCCs) constitute the majority of components used in electronic assemblies and most of their failures are related to cracks. It is often assumed that dissipation factor (DF), insulation resistance (IR), and breakdown voltage (VBR) are characteristics that are sensitive to the presence of mechanical defects, and screening of capacitors by measurements of these characteristics, and by dielectric withstanding voltage (DWV) testing assures high quality products. This work analyzes the effectiveness of these screening techniques for revealing cracks in high-volumetric efficiency, low-voltage ceramic capacitors. Various types of class II dielectric capacitors with rated voltages from 6.3 V to 100 V, and capacitances from 0.1 μF to 100 μF from different manufactures were used in this study. Fractures in the parts were introduced mechanically and by thermal shock stress. It has been shown that cracking results in relatively minor variations of capacitance and DF. Absorption currents prevail over leakage currents during standard IR measurements at room temperatures, and at high temperatures the intrinsic leakage currents exceed substantially leakage currents caused by cracking thus masking the presence of defects. Analysis of distributions of breakdown voltages in normal capacitors and capacitors with cracks showed that the majority of defective capacitors can pass the DWV testing. New, more effective methods of electrical testing and possible improvement of the existing techniques are discussed.
Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application
Authors: Tran Tu Anh , Mathew Varughese , Koh Wen Shi , Yow K. Y. , Au Y. K.
Published: October 2015

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With the hardness of nickel and palladium being more than 10 to 15 times the hardness of aluminum, OPM-plated SGPC's were much more difficult to dice than conventional SGPC's with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Specifically, dicing was observed to be not centered on SPGC pads on the pizza mask. Off-centered dicing produced drastic change in Ni loading at the center of the blade and on the edges of the blade. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.
Immersion Tin for QFN Packages to create a 3-D solder joint for reliability enhancement
Authors: Özkök Mustafa , Mertens Hubertus , Bender Jerome
Published: October 2015

The QFN (Quad-Flat No-leads) package is one of several package technologies that connect ICs to the surfaces of PCBs without through-holes. The side edges of the standard QFN Package are not covered by solder, which results in the fact that the package is soldered only planar in 2 dimensions from the QFN bottom side onto the PCB as shown on fig. 1 a).

The QFN where the side edge is covered by immersion tin will keep the side edged of a QFN solderable as shown in fig. 1 b). This allows the package to be soldered in 3 dimensions onto the PCB providing a stronger solder joint and a better reliability. The suggested paper describes a new process to cover the side edges of the package with immersion tin after the QFN package singulation step. The exposed lead frame edges are covered by immersion tin. No exposed copper is visible and delivers a 3 dimensional solder joint with better reliability and protection for the soldered package.
Thick film pastes for nitride ceramics for high power applications
Authors: Wenzel Marco , Schmidt Richard , Partsch Uwe , Eberstein Markus
Published: October 2015

Aluminum and silicon nitride ceramics show high potent as substrate materials for thick film- / hybrid applications in the field of power electronics and microwave technology. A main advantage of AlN is its very high thermal conductivity. Si3N4 has also a thermal conductivity comparable to AlN but higher thermal shock resistance and fracture toughness. Nevertheless, the use of Si3N4 in power electronic packages or heater applications is not achieved due to the lack of suitable connection technology such as thick film pastes. The main challenge for the respective pastes is the adhesion on the substrate. The low thermal expansion (CTE) of about 2.8 ppm/K of Si3N4 and material interactions with the thick film components must be considered in the paste development. Therefore, new glasses and glass-ceramic composites are required.

Reason development was performed towards AgPd based thick film heater pastes for Si3N4. The pastes consists of AgPd in a 1:1 ratio, an inorganic filler and a glass phase adapted to the CTE of Si3N4. By variation of the content of inorganic filler and glass content three pastes with a sheet resistivity of 0.1 ohm/sq, 0.8 ohm/sq, and 7.9 ohm/sq and temperature coefficient of the resistance (TCR) between −100 and 100 ppm/K were developed. The performance of heater films prepared from these pastes under electric pulse load was studied. An electrical power of up to 85 W can be applied without a significant change of the resistivity (ΔR/R) of 0.1%. As reference comparable investigations on AlN were performed with adapted pastes. The film structures were analyzed in FESEM studies.
A current-controlled pcb integrated mems tilt mirror
Authors: Dean Robert N. , Stevens Colin B. , Tatarchuk John J.
Published: October 2015

MEMS tilt mirrors are used in many applications. They usually consist of a reflective tiltable surface that is actuated electrostatically, piezoelectrically or thermally. By integrating a miniature rare earth magnetic onto a micromachined Si tiltable platform, a DC current controlled tilt mirror chip can be realized. This approach was used with a NdFeB rare earth magnet integrated onto a micromachined Si platform attached to a surrounding frame with torsional springs. The device was then mounted on a printed circuit board in close proximity to a current carrying trace for evaluation. The resulting MEMS tilt mirror achieved a tilt range exceeding ±10° using a DC control current ranging from +5A to −5A, with an R2 value of 0.9969.
Integrated Current Sensing Technology for Synchronous Buck Converters
Authors: Reutzel Evan , Chen Rengang , Ragona Scott , Jauregui David
Published: October 2015

A lossless current sensing technique is proposed, which takes advantage of the on-resistance of the sync FET used in the buck converter to sense the current flowing through the device and to reconstruct an emulated version of the inductor current. The current sensing circuit is integrated into the MOSFET driver and co-packaged with a set of FETs in a stacked die arrangement with common lead-frame shared between driver and sync FET to enable accuracy equivalent to or better than DCR sensing. In addition to steady-state operation, modern multiphase controllers are required to drive the buck converter in other operating modes including: Diode Emulation Mode (DEM), body-braking, tri-state (phase off). These additional modes are also correctly emulated by the current sense logic.
Detailed Analysis of How Power Stage and Power Clip Products Achieve Optimized Power Density
Authors: Black Arthur
Published: October 2015

The power stage and power clip packages are designed to increase the power density, in a synchronous rectifier (SR) buck application, while using a significantly smaller PCB land pattern area than a conventional discrete pair of MOSFETs. This paper presents a detailed analysis of how these new Fairchild dual-die designs achieve this performance.
Backside Exposure of Small-Sized TSVs Using Si/Cu Grinding, CMP, Cap Layer Deposition, and Alkaline Etching
Authors: Watanabe Naoya , Aoyagi Masahiro , Katagawa Daisuke , Bandoh Tsubasa , Yamamoto Eiichi
Published: October 2015

For backside exposure of through-silicon vias (TSVs), we developed a new process using Si/Cu grinding, chemical mechanical polishing (CMP), cap layer deposition, and alkaline etching of Si. In this process, Si/Cu grinding without Cu burning or smearing was performed by using a novel grinding wheel (vitrified-bond type), with in situ cleaning of the grinding wheel by a high-pressure micro jet. CMP was then performed to remove grinding scratches generated by Si/Cu grinding. Next, slight Cu contamination in the Si region between TSVs was decreased by cap layer deposition and alkaline etching of Si. The cap layer was Ni-B film formed by electroless plating. We also applied the developed process to backside exposure of 4-μm-diameter TSVs. As a result, TSVs were exposed uniformly without grinding scratches and Cu contamination in Si region between TSVs was suppressed to < 2.7×1010 atoms/cm2.