bluuebunny/crossref_metadata_2025 huggingface dataset:
Wafer level packaging for high-brightness LED lighting with optimized thermal dissipation and optical performance
Authors: Wang Liang , Guevara Gabe , Co Rey , Zhang Ron , Alatorre Roseann
Published: October 2015

High-brightness LED lighting has gained high attention in the industry and its market share for general lighting has been rapidly expanding upon the continued progress on improving internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A lion share of cost of an LED module is incurred during the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure remains the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimized light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimal contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moire patterning and Topography and Deformation Measurement to understand the warpage profile and varying temperatures along both heat up and cool down paths, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, current-spreading layer, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for high-throughput and low-cost manufacturing, to achieve both superior thermal management and optimized power efficiency.
Development of 2.5D and 3D IC Fabrication and Assembly Technologies
Authors: Gao Guilian , Sheng Hong , Lee Sangil , Lee Bong-Sub , McGrath Scott , Wang Liang , Woychik Charles , Uzoh Cyprian , Villavicencio Grant , Alatorre Roseann , Arkalgud Sitaram
Published: October 2015

2.5D/3D IC assembly is where the traditional foundry and assembly house model breaks down. The greatly reduced feature sizes of microbumps in combination with very large, thin interposers and ICs present many challenges for assembly. With densely integrated packages and stacked thin dies, warpage at various steps of assembly process can lead to die crack, weak or open interconnection, and delamination. Microbump die with copper pillar and solder cap lacks the flexibility of conventional BGA solder balls in warpage compensation. Low temperature dielectric materials for interposer backside passivation lack chemical, thermal stability and mechanical strength compared to similar materials cured at higher temperatures. Ultra- low stand-off between dies creates new challenge for flux residue removal and underfill processing, adhesion and reliability.

In this paper, we present learning and results from building two Invensas 2.5D interposer test vehicles with rectangular (19mmx27mm) and square (24mmx24 mm) silicon interposers. Since the industry is still debating where the MEOL processes will take place, these two test vehicles use both assembly centric and fab centric flows. We conducted comprehensive material and process compatibility studies to meet our goal of process capability and product reliability. We explored three different interposer fabrication/ assembly flows that includes copper-to-copper bonding as well as solder capped copper pillar microbumps for microbump die to interposer connection. We optimized the interposer fabrication process to improve interposer quality and warpage. We instituted 100% bump inspection and tight control on microbump die quality and co-planarity to improve assembly yield. We developed robust soldering and cleaning processes to achieve high soldering process yield. We evaluated several methods of flux clean and developed a procedure to achieve optimal flux residue removal without causing mechanical damage to solder joints. We explored vacuum and pressure curing process for underfill and adopted advance underfill cure technology to eliminate voids in underfill. The impact of these factors on assembly yield and reliability will be presented.
Advanced High Density Trench Capacitor Substrate Technology for 3D heterogeneous stacks with outstanding performances.
Authors: Bunel Catherine , Murray Franck
Published: October 2015

3D technology using TSV interconnect is an option that is enabling various heterogeneous integrations , bringing more functionalities by stacking different types of devices , performance enhancement and miniaturization .This paper will cover IPDiA's latest product developments in the medical and power management domains .Several examples with high density trench capacitor substrate technology connected in a 3D heterogeneous stack using TSV with active dies such as microcontroller , crystal, or sensor will be illustrated. This technology is getting more and more mature and a few players are now able to bring such products to the market but the industry is still struggling with challenges .Some of them such as wafer bonding , wafer testing and packaging will be depicted in this paper .
Silicon Wafer Integrated Fan-out Technology
Authors: Zwenger Curtis , Huemoeller Ron , Kim JinHan , Kim DongJean , Do WonChul , Seo SeongMin
Published: October 2015

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm.

Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed.

A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT package technology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single & multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer level packaging technique. This can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enables the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.
Low Cost Chip Last Fanout Package using Coreless Substrate
Authors: Chen Scott , Wang Simon , Lee Coltrane , Hunt John
Published: October 2015

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices.

Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP).

The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers.

We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm.

All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.
Multi3D Manufacturing: 3D Printing of Geometrically-Complex Aerospace Structures with Embedded Electronics
Authors: MacDonaldd Eric , Espalin David , Culp Slade , Wicker Ryan
Published: October 2015

Recent efforts have concentrated on 3D printing for use not only in creating conceptual models but functional end-use products as well and the expiration of many of the additive manufacturing process patents of the 1980s has led to lower cost systems in general. The freedom of 3D printing along with the change in economics is leading to the democratization of manufacturing, where products will soon be fabricated locally and with requirements specified individually by the end user. However, currently 3D printing is limited to single material fabrication and consequently can only create mechanical structures. For additively manufactured end-use products to be relevant, additional features will need to be incorporated into the complex structures in terms of electronic, electromechanical, electromagnetic and thermal composition. Recent research has been reported of embedding electronic components and electrical interconnect into 3D printed structures either by interrupting the process or by inserting the additional content after the structure has been built. However, only until recently with an investment from the presidential initiative on manufacturing ï¿½ America Makes ï¿½ has there been a focused research effort on technology that produces multi-functionality with enhanced 3D printing, where additional manufacturing technologies are leveraged. This presentation will describe the development and status of the Multi3D Manufacturing System underway at the University of Texas at El Paso.
3D MICROSENSOR IMAGING ARRAYS NETWORKS
Authors: Fries David , Barton Geran
Published: October 2015

2D microsensor arrays can permit spatial distribution measurements of the sensed parameter and enable high resolution sensing visualizations. Measuring constituents in a flowing media, such as air or liquid could benefit from such flow through or flow across imaging systems. These flow imagers can have applications in mobile robotics and non-visible imagery, and alternate mechanical systems of perception, process control and environmental observations.

In order to create rigid-conformal, large area imaging systems we have in the past merged flexible PCB substrates with rigid constructions from 3D printing. This approach merges the 2D flexible electronics world of printed circuits with the 3D printed packaging world.

Extending this 2D flow imaging concept into the third dimension permits 3D flow imaging networks, architectures and designs and can create a new class of sensing systems.

Using 3D printing, 3D printed filaments, nets and microsensor cages, can be combined into integrated designs to generate distributed 3D imaging networks and camera systems for a variety of sensory applications.
Development of TSV Reveal Process Using Very Fine Si/Cu Grinding and Metal Contamination Removal
Authors: Watanabe Naoya , Aoyagi Masahiro , Katagawa Daisuke , Bandoh Tsubasa , Mitsui Takahiko , Yamamoto Eiichi
Published: October 2015

Three-dimensional integrated circuits (3D-ICs) using through silicon via (TSV) have been developed as an emerging technology that can lead to significant progress (1–4). Among various TSV processes, the via-middle process has potential for wide spread use because formation of small-sized TSVs is relatively easy in the via-middle process. However, TSV reveal process must be performed for electrical contact in the via-middle process. This TSV reveal process is important because it can influence the metal contamination and stacking yield of 3D-ICs. Conventionally, TSV reveal is performed by Si grinding and Si dry etching (5). A disadvantage of that method is the resultant TSV depth deviation, which can cause bonding failure during wafer/chip stacking. In (6), TSV leveling was performed by introducing a chemical mechanical polishing (CMP) step after deposition of the backside insulator. However, the revealed TSVs break during CMP step if they exceed a certain height.

To overcome these problems, we developed a novel TSV reveal process comprising direct Si/Cu grinding and metal contamination removal (7,8). First, simultaneous grinding of Cu and Si was performed using a novel vitrified grinding wheel. In situ cleaning with a high-pressure micro jet and the inelastic porous structure of the grinding wheel suppressed the adhesion of Cu contaminants to the Si, and TSVs were leveled and exposed. Next, an electroless Ni-B film was deposited on the Cu surface of the TSVs. The Si was etched with an alkaline solution, whereas the Cu was protected by the Ni-B film. An insulator was deposited, and then the insulator on the top surface of the TSV was removed. We achieved the backside reveal of TSVs without TSV depth deviation and suppressed Cu contamination to less than 1e11 atoms/cm2. However, after direct Si/Cu grinding with an 8000 grit grinding wheel, the average surface roughness of Si was 5–10 nm, which is larger than that after chemical mechanical polishing (CMP).

In this paper, we developed vitrified grinding wheels with very high grit numbers (#30,000 and #45,000) and present an improved version of our TSV reveal process. The average surface roughness of Si after Si/Cu grinding was approximately 3 nm for the 30,000 grit grinding wheel and 1 nm for the 45,000 grit grinding wheel. This value is equivalent to that after CMP. The improved process produced a uniform reveal of 4-um-diameter TSVs without TSV depth deviation and Cu contamination. The Cu contaminant concentration on Si region between TSVs was small (<3e10 atoms/cm2). This process will reduce the cost of the TSV reveal process and considerably improve the TSV yield.
Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications
Authors: Xu Pingye , Hamilton Michael C.
Published: October 2015

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly.

Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate.

In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging.

The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.
System in Package Design Case Study
Authors: Meyer James
Published: October 2015

In today's world, electronics need to be as small as possible. This is especially true for a wide range of electronics from UAV controllers, cellphones, to implantable medical devices. One approach to achieving small system size is the System in Package (SIP). This approach incorporates a complete system (processor, memory, etc) into one small package. On the SIP, packaged parts are replaced by dies directly mounted to the substrate via flip-chip or wire-bond technology. SIP allows the designer flexibility to create a small system with only functionality that is required. A designer can pick and choose what parts are needed for a design and is not limited to the functionality of a single signal chip.

Since the first level part packaging is eliminated, the overall board size decreased leading to an overall reduction in area and weight. Not only is there a reduction in size of each packaged part, but routing area is also reduced. The line widths and spacings can be reduced along with via size.

The system used in the case study is a typical system with a FPGA, flash memory, DDR3 memory, ADC, DAC, voltage monitors, power supply monitor and control. The design is a complete system capable of processing analog sensor data, recording the data in external memory and controlling analog outputs. Such a system can be used for data collection, vehicle control, data processing, etc.

In terms of signal integrity, the SIP offers many advantages over a traditional PWB. Given the small nature of overall package generally means shorter routes. A shorter route has the advantage of a reduced propagation delay. Also, a shorter trace will have a lower insertion loss and improved return loss. Many parts require data busses signals to match in length. This is very important for DDR3 memory. A mismatch in trace length will cause skew between the data signals and the data strobe. On a smaller board, there is an overall improvement for matching signal traces.

Power distribution is another area of improvement for the SIP. A smaller board size means the board resonances will be shifted higher in frequency, alleviating possible power rail noise issues. Overall, the power planes are less lossy. Also, decoupling capacitors will be placed closer to the active components reducing the inductive path from the active device and the capacitor. This will allow decoupling for parts switching at fast rates. Given the shorter distances between transceivers within the system, the drive strength can be reduced. Decreased drive strength will reduce the amount of power dissipated by the transceiver.

This presentation details a case study for a system in package design. A comparison will be made between the system laid out on a traditional printed wiring board (PWB) and the same system laid out on a substrate (SIP). Comparisons of the area, weight, route-ability and signal integrity will be made.
A PCB Technology Electrical Conductivity Sensor for the Measurement of Saltwater Contamination
Authors: Dean Robert N. , Werner Frank , Adams Mark
Published: October 2015

Saltwater intrusion is when sea water moves into freshwater aquifers and contaminates them. It can be a serious problem for coastal communities and inland ecosystems. A number of factors, both natural and manmade, contribute to this contamination. Natural factors include events such as storm surges from hurricanes that push seawater into inland freshwater bodies. However, manmade factors contribute far more to saltwater intrusion than natural factors. The biggest human factor is the overuse of freshwater aquifers in coastal areas. Saltwater has a higher density than freshwater, and hence a higher static pressure. So when a freshwater aquifer is partially drained by over usage, the higher pressure saltwater will percolate through the bedrock into the aquifer under the freshwater. Contamination of the freshwater body then occurs through dispersion and diffusion. Manmade canals and channels for shipping, drainage and irrigation can also provide a pathway for seawater to move into coastal bodies of freshwater. Oil and gas production and mining can also contribute to saltwater contamination of freshwater. Saltwater contamination can render freshwater aquifers non-potable, kill freshwater fish and other inhabitants, kill freshwater plants and deleteriously affect inland freshwater ecosystems in coastal areas.

Dissolved salt ions in water are excellent charge carries, resulting in a large difference in the electrical conductivity between freshwater and saltwater. Therefore the measurement of the electrical conductivity of a water sample can be used to gauge the level of possible saltwater contamination. Commercial printed circuit board (PCB) technology affords the realization of a low-cost sensor probe for measuring the electrical conductivity of aqueous samples. This sensor makes use of the materials and processes inherent in commercial PCB manufacturing, including the FR4 substrate, patterned Cu cladding and soldermask. The non-conductive E-glass FR4 substrate is used as the rigid backbone of the sensor probe. The patterned Cu cladding is used for electrodes and signal traces. The polymeric soldermask is used as a thin insulating and moisture barrier layer. With these materials, the sensor consists of two planar exposed metal pads on the surface that are used to measure electrical conductivity. Additionally, the PCB probe is directly compatible with the integration of any desired integrated electronic components and/or other sensors. Furthermore, the turnaround time for a new PCB sensor design can be as little as 24 hours at modest cost, making this technology economically superior to traditional sensor technologies, such as silicon based MEMS, where it can take months to realize a new design and be very expensive.

A prototype PCB electrical conductivity sensor probe has been designed, fabricated and evaluated with mixtures of freshwater and seawater, demonstrating its usefulness.
The discrete vacuum packaging of IR-microbolometers
Authors: Mauri Luca
Published: October 2015

Packaging of Micro Electro Mechanical Systems (MEMS) requires technical challenges to be solved and overcome when stringent vacuum and hermetic sealing is required.

This is typical for a wide class of devices, such as inertial sensors, MEMS atomic clocks, IR micro-bolometers, where such conditions need to be achieved to provide the performance stability during the lifetime of the devices. The most challenging vacuum requirements are related to micro-bolometers, since good vacuum level is needed for thermal insulation. Typical target pressure is ≈ 10-3 – 10-4 mbar.

Vacuum hermetic packaging can be successfully achieved by dedicated getter film integration, key technology for vacuum requirements, in combination with a specific sealing process and choice of vacuum compatible materials.

The discrete packaging of the device requires the attachment of the sensing element into a ceramic package, like LCC. Typically, adhesives are used as die attach material. From the vacuum point of view, adhesives are not ideal candidates and therefore the compatibility with stringent vacuum requirements is not always guaranteed. Preliminary outgassing tests on these components are recommended to select appropriate materials.

Thermal treatment of components is another key point for vacuum sealing, since specific degassing treatments before and during sealing can effectively reduce the amount of gas inside the volume of the device.

The getter film integration is mandatory in such kind of devices because of the stringent vacuum requirements. SAES' proprietary technology is fully compliant with micro-bolometer manufacturing and the optimization of the getter activation step, during the bonding process, enables the functionality of the device along its lifetime.

Moreover, capabilities of performing residual gas analyses and leak rate measurements of sealed devices are fundamental for quality control of vacuum sealing as well as for analyses and prediction of device lifetime.
Material and Process Developments for Robust and High Reliability Glass Wafers for 2.5D Packaging
Authors: Keusseyan Roupen , Mobley Tim
Published: October 2015

Borosilicate glass based wafer technologies are being developed for next generation high speed electronic, telecom and biotech systems; that integrate heterogeneous devices in a single package for improved electrical performance. The primary key to success is to have a well understood via through the glass that can be used as a core to build wafer level packages from. The present paper will discuss developments in through hole formation technology and via metallization materials and processes.

Through hole formation in borosilicate glass with corresponding wall morphology and chemistry play important roles in building robust vias through the glass. These hole characteristics and their dependence on performance, defects at the wafer level and key developments that have been achieved to overcome them will be discussed in detail.
Magnetic Current Imaging of a TSV short in a 3D IC
Authors: Gaudestad Jan , Orozco Antonio
Published: October 2015

In this paper we show Magnetic Field Imaging (MFI) is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a Dual Beam-Plasma FIB (DB-PFIB) system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects.

Magnetic Current Imaging (MCI) is a sub technique of MFI which has been used by the semiconductor industry for more than a decade to find electrical shorts and leakage paths and which has the capability to “look through” all materials typically used in the semiconductor industry, allowing global imaging without the need for physical de-processing [1, 2, 3]. MCI utilizes two types of sensors: a Superconducting Quantum Interference Device (SQUID) sensor for low current and large working distances and a Giant Magneto Resistance (GMR) sensor for sub micron resolution current imaging at wafer/die level [3].

The sample investigated in this work is a triple-layer stack, in which 2 layers of 50 μm thick test chip (Chip 1 and Chip 2 in Figure 1) were assembled on a 200 μm thick bottom chip (Chip 0 in Figure 1). The test chips were manufactured by imec's standard 65 nm CMOS Back End of Line (BEOL) process, 5×50 μm via-middle TSV technology [4], and fine pitch micro bumping process [6]. Further details of the test vehicle and assembly process can be found elsewhere [5].

The sample had a short between daisy chain a1 and a2, which were supposed to be electrically separated. The probe tests that was used for this experiment is shown in Table 1.

The signal was injected into the respective daisy chains by probing V+ to V− on the bottom chip. To send a signal between daisy chain a1 and a2 one could probe V− to V− and V+ to V+. The MCI scans were done using the GMR sensor only. The sample was attached to a vacuum chuck and raster scanned.

From Fig. 2 one can see that the current enters the top layer (Chip 2) at TSV 18 and goes back down again to Chip 1 at TSV 28.

Since the sample clearly has multiple shorts, the short located at TSV pair 23 was chosen for PFA using the PFIB. A short is found between the 2 BEOL layers of Chip 1, causing the current to leak into Chip 2 (Fig. 3).
Multi Beam Full Cut Dicing of Thin Si IC Wafers
Authors: van Borkulo Jeroen , van der Stam Richard , Knippels Guido
Published: October 2015

The ongoing trend to thinner wafers which are needed for continuous miniaturization, 3D packaging and IC performance, inevitably means that sole blade dicing evolution is coming to an end. Over the last years several technologies to handle the separation process of thin Si wafer dicing have been evaluated (DBG, Stealth, Plasma, etc). Although they are capable for certain applications to meet the process specifications, they achieve this at expense of flexibility, productivity and process costs. ALSI, the inventor of multi beam dicing for semiconductor materials, has developed a technology using a multi beam laser concept which allows to dice through thin Si IC wafers while achieving a die strength equal or higher than achieved with blade dicing. In this single step process a multi beam laser configuration allows to remove the (ultra) low-K and metal top structures, dice through the Si substrate and recover the die strength (>450MPa for a 70um Si wafer). This technology allows the semiconductor industry to continue with the development of advanced node wafer technology utilizing (ultra) low-K and thick metal structures while having a separation technology that can cope with all these process steps.

The presentation will address how the multi beam laser dicing process is an enabling technology and the first process in the world that can meet the die strength criteria without the need of additional process steps which increase the cost and reduce the flexibility and yield of the process. Multi beam laser dicing allows semiconductor manufacturers to execute their technology roadmap in a cost efficient manner.

This presentation will address in depth, the challenges and issue's that semiconductor manufacturers are facing with respect to the dicing of thin (ultra) low-K IC wafers. We will present the die strength and quality that has been achieved using the multi beam dicing technology and compare this to other separation technologies.

We will disclose how a multi beam process will play a dominant role in achieving an extremely small Heat Affected Zone combined with a significantly higher productivity. It will be demonstrated how a unique combination and optimization of multiple beams, pulse duration, and low pulse energy, can meet the challenging requirements set by the industry. In addition dicing results and achieved productivities will be presented.
Optical Cavity Interrogation for MEMS Accelerometers
Authors: Kranz Michael , Hudson Tracy , Grantham Brian , Whitley Michael
Published: October 2015

MEMS accelerometers utilizing electrostatic, piezoelectric, and magnetic proof mass displacement readout approaches have achieved success in both commercial- and defense-related applications. However, there is a desire for improved acceleration resolution suitable for navigation-grade applications. Optical readout of mechanical displacements has demonstrated high levels of resolution in macro-scale applications including precision movement and placement systems. In addition, optical techniques are common in high performance inertial sensors such as fiber optic gyros and ring laser gyros. Incorporating optical readout approaches into MEMS acceleration devices may yield sufficient resolution to achieve navigation-grade performance. Therefore, the U.S. Army AMRDEC is developing MEMS accelerometers based on optical cavity resonance readout. In the device, an optical cavity is formed between a MEMS proof mass and a reference reflector. A tunable laser excites the cavity on the edge of its resonance peak. Small displacements of the cavity from its rest position are detected by frequency shifts of the resonance, leading to high-resolution proof mass displacement detection and therefore high acceleration resolutions. This paper will present modeling associated with the design concept, as well predictions of device geometries and performance with the goal of achieving less than 1 micro-g bias instability and a velocity random walk of better than 0.2 micro-g/rt.Hz.
Multiscale, Ceramic Microsystems for Heat and Mass Transfer
Authors: Lewinsohn C. , Wilson M. , Fellows J. , Anderson H.
Published: October 2015

Structures with several dimensional length-scales can be integrated with ceramic microsystems by using ceramic processing methods that produce components with novel functions. For example, structures optimized for heat transfer can be incorporated with structures designed for gas separation to produce microreactors in low cost, compact packages. Examples of incorporating multiple forming methods with, and without, one-step densification approaches will be described. This presentation will describe several examples of components incorporating multiscale structures. Typical applications are power electronic heat management, microreactors for chemical processing, and industrial heat exchangers. Features of design optimization methods that are unique to ceramic microsystems will be described. The objective of the presentation is to demonstrate the potential for ceramic microsystems in a broad range of applications and describe the benefits and challenges associated with their design, fabrication, and operation.
Ceramic modules for micro solid-oxide fuel cells
Authors: Maeder Thomas , Jiang Bo , Yan Yan , Ryser Peter , Muralt Paul
Published: October 2015

Micro solid-oxide fuel cells (μ -SOFCs) based on microfabrication processes are a promising alternative to batteries for supplying portable electronics, as very high energy densities may be achieved. However, a complete μ -SOFC module is a quite intricate structure, comprising 1) a gas-processing unit (GPU) to process a convenient energy source such as lighter gas into a more usable form, 2) the energy-generating cells proper, and 3) a post-combustor. The mechanical integration of these elements and their fluidic and electrical interconnection into a single module is a very challenging task for micro-scale integration. Therefore, a modular low-temperature co-fired ceramic (LTCC) package is proposed, allowing individual testing and subsequent full integration of the different cell elements. The package functions as a hotplate, a mechanical support for the hot zone and as an electrical / fluidic interconnect, applying a slender-bridge design to minimise thermal conduction losses and stresses, thus allowing convenient low-temperature electrical connections and fluidic ports. For applications requiring a better thermal expansion match to silicon and borosilicate glass, a silicon / borosilicate glass-sealed variant was also developed. Preliminary thermal characterisation of these packages is shown, and concepts for integrating the GPU and post-combustor into the LTCC structure are presented.
Ceramic Interface and Multilayer Technology for Micro Fuel Cells
Authors: Ziesche Steffen , Michaelis Uwe Partsch A.
Published: October 2015

Planar fuel cells typically consist of several functional layers stacked on top of each other. We have extended the concepts of multilayer ceramics and thick film technology to provide novel approaches for the design of extremely compact and cost efficient micro fuel cells, either for the high temperature operation (SOFC) or for near ambient operation (PEMFC).

Solid oxide fuel cells (SOFCs) operate at temperatures as high as 850°C. Several ceramic technologies were developed to facilitate mechanical integrity and good electrical contact to the cell at these high operating temperatures and upon rapid thermal cycling.

Ceramic interconnector plates can be manufactured by adapting the multilayer / thick film / via approach known from LTCC to HTCC multilayers such as zirconia. The result is a 3D shaped SOFC interconnector plate with an unparalleled thermomechancial stability and rigidity for special applications like military.

Extending that HTCC functionalisation approach further led us to the manufacturing of other multilayer ceramic based micro-reactors, namely micro-reformers for hydrogen production on a pocket size scale. We have combined several high throughput 3D shaping technologies with novel catalyst coating approaches to yield micro-reactors that are cost efficient to manufacture and that expose a high inner catalytically active surface at a low pressure drop. We have also applied thick film technologies to incorporate additional functions such as sensors or heaters right into the multilayer.

The contribution is concluded with a summary of the crucial shaping and coating technologies and an outlook on how these can be applied to future compact SOFC and PEMFC fuel cells.
Ink-jet Printing of TiO2 Suspensions
Authors: Trefalt Gregor , Kosec Marija , Kuščer Danjela , Stavber Gaj , Malič Barbara
Published: October 2015

A general approach to prepare aqueous suspensions of inorganic particles suitable for ink-jet printing was developed. Titanium dioxide was used as the model material. Stable colloidal suspensions of TiO2 particles in water were prepared by adjusting the pH. The milling conditions were optimized in order to effectively mill the starting micron-sized powder. After 280 min of milling, the particle size was decreased to dmean = 170 nm. The fluid properties of the suspensions, i.e. viscosity and surface tension, were optimized by increasing the solid load of TiO2 powder and by addition of the surfactant triton X-100. Additionally, glycerol was added to the suspensions to control the drying behavior. The patterns of TiO2 were successfully printed on glass substrates.
Inkjet Printed MgO-Thickfilm-Layer with Embedded BST Pillars
Authors: Diel Waldemar , Wassmer Marcel , Krueger Klaus
Published: October 2015

Barium strontium titanate (BST) and magnesium oxide (MgO) are common materials for electronic applications. Because of its low permittivity MgO can be used for passivation layers. In contrast to that the high-k BST allows for building up structures with high capacitances. Bandgap and antenna applications are feasible based on periodic BST/MgO structures, which are e.g. woodpile shaped. Furthermore BST can be used for filter or phase shifter applications due to the dielectric constant of BST that can be modified by the applied electrical field. To keep the applied voltage in a low range very fine structures are required. There are reports about the attempt to realize these very fine structures by screen printing or thin film deposition of BST and MgO. In this paper inkjet printing will be presented as an alternative method for the realization of such fine structured thick films.

BST particles with a diameter of 0.5 micron are deposited by inkjet printing with the additional advantage of creating two dimensional patterns in one layer. The resulting BST structures are embedded in MgO layers, which are inkjet printed as well.

The corresponding, own developed inks are based on an organic non-polar solvent. The particles are dispersed in the solvent by triple-roll-mill process and stabilized sterically. A solvent is found which is compatible to both kinds of particles as well as to the used substrates. Hence, the ink formulation differs only in the solid phase.

The printed structures are processed in two steps. First the MgO layer with the included holes is printed, the BST columns are deposited afterwards. The realization of fine MgO and BST structures is demonstrated. Printing of large areas with holes or channels as well as printing of columns with a high aspect ratio is investigated.

Numerous designs can be realized using inkjet printing. Any common passive devices as well as periodical structures with small dimensions and high aspect ratio are feasible.
Process Evaluation of DuPont™ GreenTape™ 9k7 LTCC
Authors: Dai Steve , Casias Adrian
Published: October 2015

GreenTape™ 9K7 low temperature cofired ceramic (LTCC) is a low loss glass ceramic dielectric tape for high frequency applications. The low loss is mainly achieved via glass-derived and glass-reacted crystallizations that occur during the sintering stage. This paper reports on the impact of one critical process parameter, the ramp rate from the binder burnout to the sintering temperature (530 – 850°C), which affects the shrinkage behavior, dielectric properties and strip line (SL) resonator characteristics of 9K7. At slow ramp rates crystallization occurs before densification, increasing glass viscosity, and thus inhibiting 9k7 from reaching full density. The sintering of 9k7 can be optimized using ramp rates that allow densification prior to crystallization.
Microelectronics Packaging Application using post-LTCC technology
Authors: IMANAKA Yoshihiko , AMADA Hideyuki , KUMASAKA Fumiaki
Published: October 2015

The rapid evolution in electronic equipment has created a demand for advanced devices that are flexible, thin, and light in weight. This demand is driving the development of flexible and stretchable electronic devices as a core technology. To produce wearable computers, we need to fabricate functional membranes that contain passive devices such as capacitors and resistors on resin sheets at low temperatures. These sheets can then serve as mounting boards for various electronic devices.

By improving the technique for room-temperature aerosol deposition (ASD) of a ceramic material (post-LTCC technology), we have established a technology for forming a dielectric inorganic film with an excellent degree of crystallinity and favorable electric properties for use in the production of flexible and stretchable electronic devices on a polyimide sheet. In the barium titanate film produced by the deposition on a polyimide sheet, a closely packed film with a high degree of sealing was formed by means of structure control to establish large-particle anchors, measuring about 100 nm in diameter, at the interface between the ceramic film and the polyimide sheet. The maximum dielectric constant of a film of barium titanate formed on the polyimide sheet by using the improved aerosol-deposition was 350 .By using this method to form a three-dimensional capillary structure inside a film, we produced a capacitor film with an apparent dielectric constant of 40,000 at room temperature. We also demonstrate cathode films for quick-charging lithium ion batteries. To achieve rapid charging, it is necessary to improve the speed of the chemical reaction between the cathode material and the electrolyte. Our process, however, does not require any unnecessary additive, such as a binder, unlike conventional tape casting method, and forms a film consisting of nano-particles of a high crystallinity, and is therefore effective for rapid charging.
Advanced Ceramic Structures and Materials for High-Reliability Millimeter-Wave Applications
Authors: Labadie Iris
Published: October 2015

Semiconductor device speeds and circuit operating frequencies have increased substantially over the past decade. Although millimeter-wave technology has been around for over 100 years, it is only within the past 5–10 years that increased demand for millimeter-wave commercial products and services has driven the development of new electronic package designs, low-loss materials, and the transformation of passive components to integrated and smaller geometries. High-reliability applications have employed millimeter-waves for several decades, but typically utilized heavy materials and distributed architectures. The transition of high-reliability millimeter-wave applications to new materials such as low-temperature co-fired ceramics requires innovative package designs to achieve comparable or better electrical performance in a much smaller form factor. Ceramic packaging technology continues to meet or exceed the performance requirements of high-reliability millimeter-wave applications with a broadened portfolio of material sets and innovative internal circuit components such as filter banks, antennas, and waveguides. Today's ceramic package design techniques and materials for applications within current and future high-reliability millimeter-wave markets will be discussed.
History and Future Prospect of Electro-ceramics in Japan and Asia
Authors: Takagi Hiroshi
Published: October 2015

On the background of a long history of Japanese ceramics, various electro-ceramic materials have been studied and many kinds of electronic components using them have been developed in Japan. The first invention of electro-ceramics in Japan should be a ferrite at Tokyo Institute of Technology in 1930, and the mass production of ferrite started in 1937. Then, Japanese electro-ceramic industry has led the world on electro-ceramic materials and components until now, especially in the fields of BaTiO3, PZT, PTC thermistor, ZnO varistor and insulating ceramics. In recent years, new electro-ceramic materials, their processes and new devices using them have been still studied actively in Japan. Currently, R&D activities in Asia outside of Japan, and electro-ceramic industries in those areas have been grown steadily.