bluuebunny/crossref_metadata_2025 huggingface dataset:
Post Decapsulation Internal Visual Inspection
Authors: Jordan Erik
Published: December 2020

One of the biggest problems in the integrated circuit industry as of late has been counterfeiting. Because the counterfeiting process is still quite crude in its nature, visual inspection has become a cornerstone process. This paper discusses the significance of the documentation post decapsulation during internal visual inspection. In order to properly inspect for counterfeit components, it is critical to understand that one inspection method alone will not provide enough information to detect all counterfeits. Proper counterfeit detection involves detailed inspection of multiple aspects of a component in order to gather as much information as possible, so that each component can be successfully labeled counterfeit or authentic. A collaboration of multiple inspection processes, comparison of data amongst sample testing batch, comparison to "known good/golden sample" when possible, and documentation of findings results in the highest confidence level of authenticity of counterfeit labeling of components.
Alternative Lapping Method to Reduce Edge Rounding Effect
Authors: Ong Hock Guan , Gan Chee Lip
Published: December 2020

Polishing is a simple and direct method to prepare samples for failure analysis and characterization. However, polishing commonly gives rise to the issue of rounding at the sample's corners and edges. This is believed to have arisen from the uneven distribution of polishing slurry between the edges and sample surface during polishing. Thus, we propose a new lapping method to reduce the rounding effect. From our experiments, negligible rounding effect was observed on a 9 mm by 7 mm die after a depth of ~ 2 μm of material was removed using our proposed alternative lapping method.
Stress Reduction during Silicon Thinning Using Thermal Relaxation and 3D Curvature Correction Techniques
Authors: Colvin Jim , Patel Heenal , Hazeldine Timothy
Published: December 2020

Backside sample preparation is required by many post silicon validation techniques like FIB (Focused Ion Beam) circuit editing and optical probing using Photon Emission or Laser Stimulus methods [1]. In spite of many conventional methods of silicon thinning and polishing, some challenges remain as new packages are introduced. With large die packages the issue of cracking during backside thinning is arising due to package curvature stress. 3D profile methods will be shown in conjunction with thermal relaxation to alleviate silicon center to edge variance allowing sample prep of large areas with thicknesses below 10μm. Thinning and polishing methods will be shown to be interactive with the device heated; demonstrating both thermal stress reduction coupled with curvature reduction.
Fast and Precise 3D Tomography of TSV by Using Xe Plasma FIB
Authors: Hrnčíř Tomáš , Hladík Lukáš
Published: December 2020

3D tomography of TSVs was performed by combining Xe plasma FIB milling and lift-out techniques. This approach allows analyzing the structure of TSVs in detail using a method faster than the usual 3D tomography by Ga FIB and more precise than X-ray tomography. Both well-filled TSVs and TSVs with voids were analyzed and the results were compared. The analysis procedure was optimized in order to reduce the analysis time and to increase the throughput. The lift-out of the analyzed block of material was performed to obtain 90° angle between TSV and the ion beam axes, which is critical to reduce the curtaining effect and which allowed to increase FIB beam current significantly, reducing the analysis time.
Defect Isolation Tools Accelerate the Failure Analysis Process
Authors: Winterstrom Adam , Meehan Kevin , Sanchez Ralph , Ackerman Rich
Published: December 2020

This paper presents case studies that highlight the use of novel scan technologies and techniques to quickly test, diagnose, localize, and isolate the root cause of the defects, demonstrating that the solution meets the rapid and constant changing demands of industry. Cases include a device that has seemingly passed the functional test, but not the scan test with emission; a device with emission requiring resolution to its location; and a device having a timing issue that does not have emission. All case studies concluded with successful completion of finding the root cause of the defect. The diagnosis time for each of the three devices was within a period of one to three days per device. The confirmation stage of the defect is the longest lead time of the diagnostic process.
Implications of Helium and Neon Ion Beam Chemistry for Advanced Circuit Editing
Authors: Wu H. , Ferranti D. , Stern L.A. , Xia D. , Phaneuf M.W.
Published: December 2020

Gallium focused ion beams (Ga-FIB) have been used historically in the semiconductor industry for failure analysis, as well as circuit edit. However, in spite of the best of these efforts, as integrated circuit dimensions continue to shrink, Ga-FIB induced processes are being driven to their physical limits. The main purpose of this paper is to report the helium and neon ion beams' induced chemistry, including metal deposition, dielectric deposition, and chemically enhanced etching. Two simple examples are shown as proofs of concept demonstrating gas field ion source (GFIS) development for circuit edit applications. The paper summarizes the general utility of helium and neon ion beams for metal deposition, dielectric deposition, and sputtering and etching processes, and discusses some of the technical challenges associated with current GFIS technology. Using GFIS ion beams, it has been observed that the top and buried metal lines can be cut precisely and then reconnected.
Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe
Authors: Lee Jong Hak , Kim Jong Eun , Park Chang Su , Kim Nam Il , Moon Jang Won , Kim Jong Chae , Son Soo Yong , Yoo Kyung Dong , Hong Sung Joo
Published: December 2020

In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.
A New Approach for Screening Retention Time Failure Bits in DRAM Device
Authors: Sung Bonggu , Kim Daejung , Park Yongjik , Choi Joo-Sun
Published: December 2020

In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.
Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping
Authors: Pan Yan , Chittora Atul , Sekar Kannan , Huat Goh Szu , Feng You Guo , Viswanatha Avinash , Lam Jeffrey
Published: December 2020

The root cause deconvolution (RCD) provides an easy-to-understand defect Pareto, together with targeted physical failure analysis candidates. Unfortunately, even the RCD analysis also has some assumptions and limitations, and its result cannot always be interpreted literally. This calls for a variety of conventional yield analysis techniques to be adopted in parallel to improve the confidence in the RCD results. This paper briefly introduces the RCD analysis and explains how it distinguishes itself from other conventional volume diagnosis analysis techniques. Its typical inputs and outputs are discussed as well. Next, the paper focuses on two case studies where the authors leverage RCD for logic yield improvement together with other conventional analysis techniques. It then proposes a comprehensive analysis system that is backed up by accumulating RCD results over time and across different design IPs.
Defect Localization Enhancement Using Light Induced CI-AFP
Authors: Dayanand N. , Quah A.C.T. , Chen C.Q. , Neo S.P. , Ang G.B. , Gunawardana M. , Mai Z.H. , Lam J.C.
Published: December 2020

This paper describes the effectiveness of using light induced Current Imaging – Atomic Force Microscopy (CIAFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and nongated diode, as a result enhanced localization of gate to source/drain short.
Novel NIR Camera with Extended Sensitivity and Low Noise for Photon Emission Microscopy of VLSI Circuits
Authors: Shehata Andrea Bahgat , Stellari Franco , Weger Alan , Song Peilin , Deslandes Herve , Lundquist Ted , Ramsay Euan
Published: December 2020

This work presents a new photon emission microscopy camera prototype for the acquisition of intrinsic light emitted from VLSI circuits during their normal operation. This novel camera was designed to be sensitive to longer wavelengths in order to maximize the signal intensities from modern VLSI chips which are characterized by a red shift in the intrinsic emission spectrum. In this paper, we will characterize the performance of the camera using 32 nm and 22 nm SOI chips. The novel camera is able to collect emission images with the circuit under test operating at a supply voltage down to 0.5 V, exceeding the performance of a state-of-the-art InGaAs camera.
Comparative Study on Decapsulation for Copper and Silver Wire-Bonded Devices
Authors: Kerisit François , Domenges Bernadette , Obein Michael
Published: December 2020

The introduction of silver as bonding material led to new failure analysis issues. This study compares the efficiency of wet and dry chemistries for decapsulation on Cu and Ag-based alloy wires. It is shown that dry chemistry allows better control and selectivity on the EMC/ Cu and Ag-based bond wires.
Introduction of Spectral Mapping through Transmission Grating, Derivative Technique of Photon Emission
Authors: Parrassin Thierry , Dudit Sylvain , Vallet Michel , Reverdy Antoine , Deslandes Hervé
Published: December 2020

By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.
Efficient Nondestructive 3D Defect Localization by Lock-in Thermography Utilizing Multi-Harmonics Analysis
Authors: Naumann Falk , Altmann Frank , Grosse Christian , Herold Rolf
Published: December 2020

Lock-in Thermography in combination with spectral phase shift analysis provides a capability for non-destructive 3D localization of resistive defects in packaged and multi stacked die devices. In this paper a novel post processing approach will be presented allowing a significant reduction of measurement time by factor >5 in comparison to the standard measurement routine. The feasibility of the approach is demonstrated on a specific test specimen made from ideal homogenous and opaque material and furthermore on a packaged hall sensor device. Within the case studies the results of multiple single LIT measurements were compared with the new multi harmonics data analysis approach.
Automated Defect Analysis in Solar Cells Using EBIC
Authors: Moldovan Grigore , Lotharukpong Shark , Wilshaw Peter
Published: December 2020

Electron Beam Induced Current (EBIC) characterization is unique in its ability to provide quantitative high-resolution imaging of electrical defects in solar cells. In particular, EBIC makes it possible to image electrical activity of single dislocations in a Dual-Beam Focused Ion Beam (FIB) Scanning Electron Microscope (SEM), to cut and lift out a micro-specimen containing a particular dislocation, and then transfer it for further structural or chemical analysis. As typical solar cell material presents a complex array of defects, it is important to observe statistical variations within a sample and select key sites for analysis. This paper describes a method for automated defect identification and characterization, and shows an application to multi-crystalline silicon (mc-Si) solar cell wafers selected from different heights along the manufactured ingot. Information presented here includes the experimental setup for data acquisition, as well as the basic algorithms used for identification and extraction of dislocation contrast.
Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices
Authors: Dawood M.K. , Chen C. , Tan P.K. , James S. , Limin P.S. , Tan H. , Yap H.H. , Low G.R. , Lam J. , Mai Z.H.
Published: December 2020

In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.
Understanding the Cu Void Formation by TEM Failure Analysis
Authors: Liu Binghai , Zhu Jie , Chen Changqing , Er Eddie , Zhao Siping , Lam Jeffrey , Elizabeth Sebastian , Ye Chen
Published: December 2020

In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.
Site-Specific, Wide Field-of-View Cross-Sectional Sample Preparation, Imaging and Analysis in a Plasma Ion Source Helios DualBeam™ Microscope
Authors: Alvis Roger , Kelley Ron
Published: December 2020

A Plasma-source focused ion beam (Helios PFIB) DualBeam™ microscope with sub-nanometer 1kV SEM resolution was used to investigate the structure of a state-of-the-art organic light-emitting diode (OLED) display. The capability of the Helios PFIB to produce and manipulate millimeter-scale samples for wide field-of-view crosssectional SEM analyses was demonstrated by lifting out a 570μm long by 40μm wide x 10μm deep and mounting it on a copper half-grid. An angled face was cut into the chunk and high-resolution back-scattered SEM tiles across the entire exposed face were automatically acquired within a modular automated processing system (MAPS).
Automatic Emission Spots Identification in Static and Dynamic Imaging by Research of Local Maxima
Authors: Boscaro A. , Chef S. , Jacquir S. , Sanchez K. , Perdu P. , Binczak S.
Published: December 2020

For VLSI, internal electrical measurements are key steps to solve design debug issues and to perform failure analysis. Due to multiple metal layers, active areas of the chip are only accessible from the backside of the die. The ability of optical contactless techniques to operate through the silicon substrate and the few sample preparation required have widely contributed to promote them as unavoidable tools of the defect localization workflow. Timing issue or unusual consumption can be detected by static and dynamic photon emission analysis. The identification of the emission spots is an essential step of the process. Due to scaling, more and more emission nodes are located within the acquisition area so that large variations of emission intensity can exist. Because of various limitations, former thresholding techniques cannot ensure an exhaustive localization. In this paper, an automated process is reported to locate spots in these complex areas. We will underline the challenge and define application boundaries of this technique.
Static Fault Isolation on the Functional Failure Analysis
Authors: Chen C.Q. , Mai Z.H. , Ang G.B. , Liu B.H. , Ng P.T. , Yip K.H. , Khalid D. , Lam J.
Published: December 2020

As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.
Test Circuit Conditioning for Soft Defect Localization
Authors: Staller Kristopher D. , Goodrich Corey
Published: December 2020

Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.
Ultra-Low Voltage Time-Resolved Emission Measurements from 32 nm SOI CMOS Integrated Circuits
Authors: Shehata Andrea Bahgat , Stellari Franco , Weger Alan , Song Peilin , Anant Vikas , Sunter Kristen , Berggren Karl K. , Lundquist Ted , Ramsay Euan
Published: December 2020

This work presents a comparison of two generations of Superconducting nanowire Single-Photon Detector (SnSPD) prototypes used for Time-Resolved Emission (TRE) measurements from VLSI chips. The performance of the systems is compared in order to understand the figures of merit that a single-photon detector should have to enable the acquisition of time resolved emission waveforms for ultra-low voltage applications. We will show that measurements down to a new World record low 0.4 V supply voltage were made possible by a careful optimization of the detector front-end electronics. We also characterized the emission from devices with different threshold voltages in order to understand how the emission contributions depend on this parameter and how this affects the resulting waveform SNR.
Debugging Phase-Locked Loop Failures in Integrated Circuit Products
Authors: Goh S.H. , Lau Wendy , Yeoh B.L. , Ho H.W. , You G.F. , Hao Hu , Koh Y.E. , Lam Jeffrey
Published: December 2020

A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.
Investigation of Protection Layer Materials for Ex-Situ Lift-Out TEM Sample Preparation with FIB for 14 nm FinFET
Authors: Feng H. , Low G.R. , Tan P.K. , Zhao Y.Z. , Yap H.H. , Dawood M.K. , Zhou Y. , Du A.Y. , Chen C.Q. , Tan H. , Huang Y.M. , Wang D.D. , Lam J. , Mai Z.H.
Published: December 2020

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).
Application of Passive Voltage Contrast (PVC) to Dual Beam Focused Ion Beam (FIB) Based Sample Preparation for the Scanning/Transmission Electron Microscope (S/TEM)
Authors: Senowitz Corey , Nguyen Hieu , Vollrath Ruby , Yuan Caiwen , Rassolzadeh Fati , Graupera Theresa , Lyons Don , DiBattista Michael
Published: December 2020

The modern scanning transmission electron microscope (S/TEM) has become a key technology and is heavily utilized in advanced failure analysis (FA) labs. It is well equipped to analyze semiconductor device failures, even for the latest process technology nodes (20nm or less). However, the typical sample preparation process flow utilizes a dual beam focused ion beam (FIB) microscope for sample preparation, with the final sample end-pointing monitored using the scanning electron microscope (SEM) column. At the latest technology nodes, defect sizes can be on the order of the resolution limit for the SEM column. Passive voltage contrast (PVC) is an established FA technique for integrated circuit (IC) FA which can compensate for this resolution deficiency in some cases. In this paper, PVC is applied to end-pointing cross-sectional S/TEM samples on the structure or defect of interest to address the SEM resolution limitation.
Advanced Failure Analysis on Silicon Pipeline Defects and Dislocations in Mixed-Mode Devices
Authors: Weber Y. , Goxe J. , Alves S. , Zirilli T. , Castignolles M. , Subramanian S. , Tsang Y. , Harber K.
Published: December 2020

The presence of crystalline defects, including dislocations and pipeline defect, is detrimental to both the processing and the intrinsic quality of semiconductor devices. The electrical parametric or functional failures generated by those defects require accurate identification and proper classification in a continuous improvement mindset. Depending on the failure analyst choice of the investigation technique, the distinction between a dislocation and a pipeline defect can be difficult. In this paper, based on case studies of mixed-mode devices, the various electrical and physical FA investigation techniques are explored and compared. From an electrical investigation standpoint, fault localization techniques will be reviewed (Thermal Laser Stimulation and Photon Emission Microscopy) as well as the direct electrical measurements means (external measurement and nanoprobing AFP). From a physical analysis standpoint, the use of various methods after deprocessing will be considered: top down delineation etch, Atomic Force Microscopy (AFM), Scanning Microwave Microscopy (SMM), and Transmission Electron Microscopy (TEM). The position of the defect as well as its physical signature observed through the various methods will determine its proper classification and will determine the appropriate corrective actions. The paper will be concluded with a discussion on the physical differences between a dislocation and a pipeline defect, as well as insights into the wafer fab manufacturing process.
Laser Logic State Imaging Using Transient Voltage Collapse Circuits
Authors: Baek Gwanghyeon , Keane John , von Haartman Martin
Published: December 2020

A laser based logic state imaging (LLSI) by activating transient voltage collapse (TVC) circuits of SRAM blocks is demonstrated. In order to induce a voltage modulation on a power rail, significant numbers of TVC units are activated. The image quality of LLSI strongly depends on a number of activated TVC circuits. From this experiment, it is concluded that an additional circuit or experimental setup is not necessary for LLSI.
Near Field EMC Scanning Method Based on an E-Field Collapse
Authors: Dunnihoo Jeff , Tamminen Pasi , Viheriäkoski Toni
Published: December 2020

In this study we present a novel method to use a field collapse method together with fully automated near field scanning equipment to construct E- and H-field information of a system during transient ESD events. This inexpensive method provides an alternative way for system designers to validate and analyze the EMC/ESD capability of electronic systems without TLP pulsers, ESD simulators, or precision inductive current probes.
Time Domain Reflectometry—Case Studies in Electrical Failure Isolation
Authors: Wheeler Jason , Fasolino Stephen
Published: December 2020

Time Domain Reflectometry (TDR) is an analysis technique for characterizing a transmission environment (PCB traces, cable assemblies, etc.) and identifying the physical location of defects or impedance discontinuities which can quickly narrow the focus of an investigation. This paper introduces the capability and presents several case studies spanning different applications where TDR was useful as a non-destructive analysis technique.
Isolating Electrically Open Laminate Defects Using Space Domain Reflectometry with a Superconducting Quantum Interference Device
Authors: Distelhurst Kevin A.
Published: December 2020

An electrically open defect on a laminate may not always be found timely or successfully due to the lack of fault isolation techniques for this type of defect. This is partly due to needing high frequency techniques to isolate the location of the open. Magnetic field imaging (MFI) using a Superconducting Quantum Interference Device (SQUID) is a technique that maps, in this case, an RF signal through a trace, up until the open defect boundary. Several obstacles are introduced when using an RF signal, one of which is the shielding of the signal from the external world. Despite this obstacle, analysis of an open in an arbitrary location along a laminate under a copper plane is proven successful using this technique.
A Study of How Different FIB Beam Current Intensities Locate Possible Defects
Authors: Shu Wen Cheng , Shu Yu Hsiang
Published: December 2020

Voltage contrast (VC) is a useful technique and used widely in failure analysis of integrated circuit (ICs). This paper will demonstrate different FIB current intensities in a specific VC case and, by means of the technique, locate possible defect sites quickly. With the help of conductive atomic force microscopy (C-AFM), we can get an electrical verification at the same time. We discuss the relationship of VC and C-AFM as well as what the root cause of failure is in this case.
Selective Etching of Heavily-Boron-Doped Si Substrate Using Lightly-Boron-Doped Si Epi as an Etch Stop Layer
Authors: Korchnoy Valentina
Published: December 2020

A sample preparation technique for flip chips (FC) deprocessing from the back side proposed. The technique uses HNA chemistry (consisting of a mixture of acids: hydrofluoric, nitric and acetic) to wet-etch the heavily-boron-doped Si bulk substrate selectively to the lightly-boron-doped Si epi. The procedure can be used as a FC device sample preparation technique for back-side optical probing and FIB editing.
Environmental Control Scanning Nonlinear Dielectric Microscopy Measurements of p-n Structures, epi-Si Wafers, and SiC Crystal Defects
Authors: Yu Jing-jiang , Yamaoka T. , Hasumura S. , Hirose R. , Ando K. , Mizuguchi K.
Published: December 2020

Scanning nonlinear dielectric microscopy (SNDM) has improved significantly, achieving low-concentrated observations. Therefore, it is of great interest to observe how adsorbed water and other measurement environments influence SNDM measurements so that the material's dielectric properties can be detected. This study investigates how specific measurement environments, namely air, dry nitrogen, and vacuum environments, influence the SNDM and C-V curve measurements of semiconductor samples. The p-n structure created by ion implantation was measured by applied-DC-voltage SNDM, and in these environments, the corresponding C-V curves were obtained. As with the p-n structure sample, an abnormal result was obtained when a positive DC voltage was applied to an epi-Si sample in air. A low concentration level was clearly measured in vacuum. From these results, it can be concluded that measurement in a high vacuum is an effective way to obtain highly precise carrier distributions.
Tester Assisted Multiple Emission Microscopy
Authors: Hollerith Christian , Borgmann Gerhard , Schaller Wolfgang , Burmer Christian , Brillert Christof
Published: December 2020

Multiple emission microscopy can be used to obtain a comprehensive overview of device emission during IDDQ-test. In this new approach an emission microscopy image is taken for each pattern of the IDDQ-test. Then the extensive amount of images is analyzed for correlation with IDDQ current levels. As a result, for each increased current level concurrent spots can be identified and further analyzed.
Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges
Authors: Ismail Hashim , Keow Ang Chung , Siong Kenny Gan Chye
Published: December 2020

An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.
Body Effect Measurement in DRAM Cell Transistor Using Memory Test System
Authors: Jung Ilwoo , Choi Byoungdeok , Sung Bonggu , Kim Daejung , Kim Ilgweon , Kim Hyoungsub , Jin Gyoyoung
Published: December 2020

Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.
Sample Chemical Staining and Latest Generation SEM Imaging—Characterizing Process Robustness in Semiconductor Manufacturing
Authors: Meyer Andreas , Langer Eckhard
Published: December 2020

Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.
Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness
Authors: Chivas Robert , Silverman Scott , DiBattista Michael , Kindereit Ulrike
Published: December 2020

Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.
Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset
Authors: Goxe Julien , Vanhuffel Béatrice , Castignolles Marie , Zirilli Thomas
Published: December 2020

Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.
Failure Analysis of Automotive Ultrasonic Parking Sensors
Authors: Flores Miguel Angel Neri , Villafañe Alberto Martinez , Carreño Caleb
Published: December 2020

Automotive ultrasonic parking sensors were analyzed using X- ray computed tomography (XCT or microtomography), in order to determine if there were internal failures generated on the soldering process between copper wires and piezoelectric ceramic on these sensors. This paper reports the use of X-ray radiography and computer image processing for the study of internal defects. By using X-ray tomography technique, pores, cracks, holes, solder balling, insufficient solder, lead related defects, device related defects, and solder bridging may be identified (1-2). When coupled with a real time radiographic detector and image processor, X-ray technology allows instantaneous radiographic imaging and semi-automatic or totally automatic inspection. Analysis was conducted on six produced test samples showing that the application of XCT as a method of quality control of specimens produced by electronic packaging offers a wide range of possibilities to detect defects within materials. There were determined that five sensors contain internal defects on the soldered joints, between the copper wire, and the piezo electric ceramic covered with silver paint, as shown on the computed tomography. Accuracy of XCT method strongly depends on the size of the samples analyzed, but the possibility of obtaining information in 3D nondestructively shows considerable advantages of XCT method over traditional metallographic cross-sectional analysis.
Studies and Application of Auger Monitoring System for Quality Control and Assurance of Al Bondpads
Authors: Younan Hua
Published: December 2020

In wafer fabrication (Fab), Fluorine (F) based gases are used for Al bondpad opening process. Thus, even on a regular Al bondpad, there exists a low level of F contamination. However, the F level has to be controlled at a lower level. If the F level is higher than the control/spec limits, it could cause F-induced corrosion and Al-F defects, resulting in pad discoloration and NSOP problems. In our previous studies [1-5], the theories, characteristics, chemical and physical failure mechanisms and the root causes of the F-induced corrosion and Al-F defects on Al bondpads have been studied. In this paper, we further study F-induced corrosion and propose to establish an Auger monitoring system so as to monitor the F contamination level on Al bondpads in wafer fabrication. Auger monitoring frequency, sample preparation, wafer life, Auger analysis points, control/spec limits and OOC/OOS quality control procedures are also discussed.
A New Methodology to Protect PCBs from Nondestructive Reverse Engineering
Authors: Guo Zimu , Shakya Bicky , Shen Haoting , Bhunia Swarup , Asadizanjani Navid , Tehranipoor Mark , Forte Domenic
Published: December 2020

Reverse engineering of electronic hardware has been performed for decades for two broad purposes: (1) honest and legal means for failure analysis and trust verification; and (2) dishonest and illegal means of cloning, counterfeiting, and development of attacks on hardware to gain competitive edge in a market. Destructive methods have been typically considered most effective to reverse engineer Printed Circuit Boards (PCBs) – a platform used in nearly all electronic systems to mechanically support and electrically connect all hardware components. However, the advent of advanced characterization and imaging tools such as X-ray tomography has shifted the reverse engineering of electronics toward non-destructive methods. These methods considerably lower the associated time and cost to reverse engineer a complex multi-layer PCB. In this paper, we introduce a new anti–reverse engineering method to protect PCBs from non-destructive reverse engineering. We add high-Z materials inside PCBs and develop advanced layout algorithms, which create inevitable imaging artifacts during tomography, thereby making it practically infeasible for an adversary to extract correct design information with X-ray tomography.
Device Dielectric Quality Analysis and Fault Isolation at the Contact Level by Scanning Microwave Impedance Microscopy
Authors: Hu Wei-Shan , Lee Jeng-Han , Kao Ming-Hong , Yang Hui-Wen , De Wolf Peter , Amster Oskar
Published: December 2020

Dielectric film quality is one of the most important factors that will greatly impact device performance and reliability. Device level electrical analysis techniques for dielectric quality monitoring are highly needed. In this paper we present results using a new electrical AFM mode, scanning Microwave Impedance Microscopy (sMIM), for characterization of device oxide quality and for fault isolation. Devices with poor oxide quality show sMIM nano C-V and dC/dV hysteresis behavior during forward and reverse bias sweep. The sMIM capacitance sensitivity is below 1 aF allowing one to capture C-V spectra from the MOS structure formed by the gate and gate oxide with excellent signal/noise ratio and observe subtle variations between different sites.
Failure Analysis Work Flow for Dislocation Identification and Characterization by Electron Channeling Contrast Imaging Using SEM and FIB
Authors: Zhou Yongkai , Han Luyang
Published: December 2020

A failure analysis work flow is presented demonstrating dislocation visualization, site isolation, TEM lamella preparation and defect characterization. A novel beam control technique allows visualizing dislocations with significantly improved spatial resolution in SEM using Electron Channeling Contrast Imaging. Site-specific TEM preparation on dislocations is therefore possible. The prepared thin lamella can be inspected in the SEM using STEM to study dislocations. This is a cost effective work flow without using TEM.
Advanced X-Ray Inspection Techniques for Counterfeit IC Detection
Authors: LaVoy Rosanne M. , Babian Fred , Reid Andrew
Published: December 2020

It is known by both the commercial and government suppliers, one of the best ways to guarantee the security and reliability of IC's is to image the IC directly using an x-ray microscope. These images can be inspected for many signs of counterfeit electronics. Unfortunately, previous generations of x-ray imaging systems have not kept up with the increasingly sophisticated counterfeiting techniques. Traditional 2D X-ray inspection techniques are becoming inadequate for imaging and verifying features due to the limited resolution of these systems for thick samples and because 2D images contain too many overlapping features to easily discern, making identification very difficult. This paper discusses the development of advanced sample preparation techniques for counterfeit IC detection. It presents information on the limitations of X-ray imaging and 3D tomographic reconstruction, and on the models for resolution configuration improvement.
Acoustic and Photoacoustic Inspection of Through-Silicon Vias in the GHz-Frequency Band
Authors: Brand Sebastian , Kögel Michael , Altmann Frank , DeWolf Ingrid , Khaled Ahmad , Moore Michael J. , Strohm Eric M. , Kolios Michael C. , Strohm Eric M.
Published: December 2020

Through Silicon Via (TSV) is the most promising technology for vertical interconnection in novel three-dimensional chip architectures. Reliability and quality assessment necessary for process development and manufacturing require appropriate non-destructive testing techniques to detect cracks and delamination defects with sufficient penetration and imaging capabilities. The current paper presents the application of two acoustically based methods operating in the GHz-frequency band for the assessment of the integrity of TSV structures.
Optical Investigations of Temperature Effects in 14/16 nm FinFETs
Authors: Vogt Ivo , Boit Christian , Nakamura Tomonori , Motamedi Babak
Published: December 2020

This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.
Conductive-AFM for Failure Analysis of Parametric Test Structures in Advanced Technology Development
Authors: Zhang Chuan , Chen Esther P.Y.
Published: December 2020

A variety of parametric test structures were designed with the purpose of characterizing parameters tied to failure modes for specific structures, and the electrical test of the parametric test structures are typically conducted earlier inline, which could be months ahead of the functional test. Due to the unique advantages, conductive-atomic force microscopy (CAFM) was introduced to parametric test structure failure analysis during advanced technology development, and has been proven to be a powerful solution to many challenging failure analysis (FA) problems. This paper uses several case studies to illustrate how CAFM can be used to successfully localize defects in challenging parametric test structures that would otherwise be invisible with conventional FA techniques.
Exploring the Physical Limits of Gallium-Based Focused Ion Beam Chip Circuit Editing
Authors: Herschbein Steven B. , Scrudato Carmelo F. , Hermann Edward S. , Wagner Raymond L.
Published: December 2020

This paper describes a circuit editing procedure in which the authors used a gallium column Focused Ion Beam (FIB) tool to divide a merged 32nm multi-finger planar transistor into two separate operating components. Rather than rely on live imaging or the various endpoint detection techniques commonly used during an active mill, the authors opted for a ‘blind’ dose-driven technique. The paper explains how the authors made multiple attempts on practice material in order to determine the exact beam placement location and the depth of cut required to perform the operation with a minimum of lateral damage. The loss of a pair of poly gate fingers in the middle of the multi-gate structure seemed to have minimal impact on the final electrical parameters and the separate data paths worked per design specifications.