(Invited) How to Integrate MEMS on Foundry-Fabricated CMOS Backplanes
Authors: Schulze Matthias , Hohle Christoph , Friedrichs Martin 
Published: February 2020

A large variety of new applications for Internet of Things (IoT), Industrie 4.0 and other consumer products are pushing volume and manufacturing of microelectromechanical systems (MEMS) into a new phase. Due to massive use of these sensors and actuators in mobile and industrial applications smaller systems combined with low power consumption and higher versatility are required.

MEMS are transducers that sense or control physical, chemical or optical quantities creating devices for applications in the area of 3D-motion tracking, pressure sensing, light shaping or detection of irradiation. The combination of MEMS with an application specific integrated circuit (ASIC) based on CMOS technology enables the entire system to interact with outside world. These ASICs are providing required features such as analog-to-digital conversion, amplification, filtering, information processing and storage as well as communication to the outside world.

There are different solutions available to combine MEMS with customized CMOS circuits. One choice known as system-in-package (SiP) is the manufacturing of MEMS and CMOS on separate wafers and its subsequent integration in a multi-chip module using interposer/ rewiring technologies. Key advatanges of this technique are high flexibility, high modularity and a complete decoupled manufacturing of CMOS and MEMS. This enables a rapid development and leads to low development costs. And, there is no impact of different sizes between CMOS and MEMS chip.

In order to enhance the integration density, to drive system feature size down, to suppress potential parasitic capacitances and to reduce power consumption an integrated manufacturing on the same substrate is a must and known as system-on-chip (SoC) solution. On one hand this approach can be still realized by a multi-wafer processing and a final integration using bonding technologies. This technology is often named as heterogeneous integration. Key advantage of multi-wafer technology is the possibility to use high-performance MEMS materials such as monocrystalline silicon as actuation/sensing material and its integration on CMOS wafers. Disadvantages are the required alignment accuracies when using a metallic bond or limitation for integration densities when using via-last approach.

A more consistent way is a complete monolithic integration of MEMS on CMOS substrates. Especially when large transducer arrays are required (e.g. bolometers, micro-mirror arrays, CMUT arrays) a monolithic integration of MEMS on CMOS is the best solution. All advantages are now on hand – high integration densities, low parasitic capacitances and an effective usage of CMOS area. Fraunhofer IPMS applies surface and bulk micromachining technologies for the integration of MEMS on customized CMOS backplanes. To reduce development costs and time-to-market IPMS combines standard CMOS processes offered from CMOS foundries with a subsequent integration of MEMS part in our MEMS fab. Due to the application specific design of the CMOS backplane this concept allows a perfect match between ASIC and MEMS functionalities.

In a typical project flow CMOS and MEMS will be manufactured and tested in parallel to shorten development time. After ASIC design is finished it will be tested using Multi- Project- Wafer run (MPW) in a CMOS foundry. Using these MPW runs a complete characterization of CMOS functionality can be realized in an early project state at low costs. Parallel to CMOS testing an entire process development of MEMS part can be done on passive devices in our MEMS fab. If CMOS and MEMS characterization is completed the MEMS part will be monolithically integrated on these customized CMOS backplanes. But there are still some challenges for the integration of MEMS on foundry fabricated CMOS backplanes, e.g.:

Modifications of last CMOS/ interconnect/ ILD layers to realize an appropriate interface to MEMS

Clarification of PCM (process control monitoring) test environment, depth of test structures and possible arising contamination issues

In-chip surface topology after interconnect processing to define necessary actions to achieve required planarity for further processing

Tuning mix-and-match lithography to achieve high overlay accuracies

(Picture 1: Reached overlay accuracy between last 0,18µm CMOS and first MEMS layer of about 30- 40nm after correction step using i-line stepper)

Required chip design features when using sacrificial layer technology

IPMS offers a wide range of surface and bulk micromachining technologies which are particularly suitable for the fabrication of sensors and actuators on pre-fabricated CMOS wafers using monolithic integration. Especially surface micromachining using inorganic sacrificial layer technology allows the realization of rather complex MEMS structures on CMOS backplanes. Based on examples such as spatial light modulators (SLM) and capacitive micromachined ultrasonic transducers (CMUT) we will present solutions for the integration of surface micromachined MEMS on customized CMOS substrates.

Figure 1