Temperature Effect on Performance of Enhancement Mode Al0.4Ga0.6n-Channel Moshfets with Hybrid Oxide
Authors: Mollah Shahab , Gaevski Mikhail , Hussain Kamal , Mamun Abdullah , Chandrashekhar Mvs , Simin Grigory , Khan Asif 
Published: July 2021

The metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) based on AlxGa1-xN materials with the high aluminum composition is a promising choice for high-power, high-temperature harsh environment applications. In the present work the temperature stability of MOSHFETS with high-k ZrO2, Al2O3 gate dielectrics has been studied. Our data show these high-k dielectrics introduce negative fixed charges (Qox) as high as 1-3×1013 cm-2 depleting 2DEG density of 2×1013 cm-2 causing a positive shift of threshold voltage (VTH) compared to that for HFET which is an important feature for realizing enhanced (E-) mode MOSHFET. ZrO2 possesses higher Qox resulting in stronger positive VTH shift in devices, while devices with Al2O3 demonstrate lower gate leakage. To take advantages of both oxides, UWBG Al0.4Ga0.6N channel E-mode MOSHFET has been fabricated. E-mode device was realized using the hybrid oxide (ZrO2/Al2O3) combined with gate recess. To separate effects of dielectric charges and damage from recess process on device performance depletion (D-) mode and E-mode devices were fabricated on the same wafer simultaneously. D-mode devices were protected during gate recess step to avoid additional damage. Thermally induced VTH instability of these MOSHFETs were studied and potential mechanism for this VTH instability is discussed.

Experimental: Figure 1(a) shows the pseudomorphic device structure that was grown using metalorganic chemical vapor deposition on AlN/sapphire templates. A graded composition (AlxGa1-xN, x=1-0.4) back barrier reduces internal stress and improves gate control in the devices.[i]
, [ii] The top 200 Å thick graded n-AlxGa1-xN (x from 0.6 to 0.3) layer assists with the formation of ohmic contacts resistance as low as 1.7 Ω-mm. The n-doping of this layer compensates the positive charges resulting from the reverse composition grading.[iii] The 2DEG sheet resistance was ~1900 ohm/□. Device processing details published elsewhere.[iv] The fixed gate-length LG ≈ 2.0 μm, source to drain spacing, LSD=6 μm, were used for regular devices with 15 μm channel width, while for precise C(V,T,f) measurements we use a test structure with gate area 200x80 μm2 .

Results and discussion: The combination of gate recessing and hybrid oxide resulted in threshold-voltage (VTH) shift of +12.2 V from D to E-mode device (Figure 1(b)). The gate leakage current in both D and E-mode MOSHFETs is ~103 smaller than that of MOSHFETs using singe Al2O3 or ZrO2 layer (Figure 2(a)) which allows us to apply gate voltage as high as +12 V. The peak DC currents for D and E-mode devices were found to be 1.1 A/mm and 0.48 A/mm respectively while in the pulse mode it was 1.3 A/mm and 0.53 A/mm. ON/OFF ratio as high as 3×108 was achieved which is higher than ~2 orders of magnitude than that for Al2O3 or ZrO2. We then performed temperature dependent threshold and gate leakage study of our fabricated MOSHFETs. Figure 2(b) shows the temperature dependent gate leakage characteristics of MOSHFETs of this study. It has been found that, in the D-mode MOSHFET, the VTH experiences positive VTH shift of + 1.7 V from RT to 150 °C; for the E-mode MOSHFET the shift is negative: -2.9 V (Figure 3(a)). The VTH shift for similar device having Schottky gate (no dielectric) (HFET) is significantly smaller, +0.2 V. This shows that the VTH shift is mainly due to the charges in dielectric or at dielectric-barrier interface. In the E-mode devices, the effective channel mobility and VTH was additionally affected by radiative defects introduced during gate-recess step. The mobility (µ) in D-mode devices decreases with temperature while it increases for the E-mode devices. We estimated temperature dependent interface state density (DIT(T)) and Qox (T) using frequency- dependent C-V measurements as shown in Figure 3(b). Our analysis show that in D-mode device, Qox(T) dominates over interface charges. These are fixed negative charges which deplete the channel giving a total VTH shift of +1.7 V from RT to 150°C. The extracted SS value for D and E-mode devices were 99 mV/decade and 134 mV/decade, indicating an increased density of interface traps (DIT) at the recessed interface in the E-mode device. Larger DIT value in E-mode devices caused by a radiation damage from the barrier recessing process and becomes comparable with Qox. Thus the temperature effect on Qox is compensated by DIT changes, increasing SS and making the VTH(T) more negative.

[i]) G. Simin et al., Jpn. J. Appl. Phys., 40, L1142 (2001).

[ii]) C. Ren et al., J. Semicond. 36, 014008-1 (2015).

[iii]) S. Bajaj et al., Appl. Phys. Lett. 109, 133508-1 (2016).

[iv]) S. Mollah et al., Appl. Phys. Lett. 117, 232105 (2020).

Figure 1