bluuebunny/crossref_metadata_2025 huggingface dataset:
Electrical Characterization of Fibre-Reinforced Plastics by Atmospheric Plasma Technology
Authors: Rene Schramm , Thomas Reitberger , Joerg Franke
Published: October 2015

In previous investigations the additive metallization of conductor paths on thermoplastic substrate materials using printing technologies (Inkjet, Aerosol-Jet) was analyzed. Major disadvantages of printing technologies are the double-stage process chain divided in printing and sintering and the low current-carrying capacity of the printed structures. Accordingly, printed conductor paths are mainly used for sensor and control currents.

The plasmadust technology, based on a cold active atmospheric plasma beam, offers the possibility for additive metallization of copper circuit paths on a sandwich material. The process consists of a nano and micro scale metal powder (particle size 0.1 μm to 20 μm), which is melted in the plasma nozzle by a highly energetic nitrogen gas. Based on the kinetic and thermal energy of the nitrogen-metal-compound the circuit paths are generated in a thermo-mechanical interconnection on the substrate surface. The plasmadust technology is characterized by a one-stage process chain, a very high coating speed (up to 50 m/min) and a high current-carrying capacity of the generated conductor structures. Hence, it is possible to transfer high currents, e. g. for illumination applications. Additionally three-dimensional substrates (3D MID) can be processed by handling with an industrial robot.

In the investigations copper circuit paths on sandwich materials generated with the plasmadust technology were characterized. In this research work the adhesion of the layers and the current-carrying capacity of the copper structures were analyzed. Secondly the specimen were tested in selected reliability studies, a temperature-humidity (85 °C/85 % r.H.) and a temperature-cycling-test (−40 °C/+125 °C). With the first one the influence of moisture absorption of the sandwich material (up to 7 %) to the adhesion of the copper circuit paths is analyzed. With the second one the compound of the substrate and the additive metallization is qualified during thermo-mechanical stress. In conclusion the additive metallization of circuit paths on sandwich materials using plasmadust technology is qualified to mass production as well as different passivation possibilities of the generated structures will be presented.
SNaP: A Process for Achieving Adhesion between Electroless Copper and Dielectrics with Minimal Surface Roughening
Authors: Hsieh Meng , Libman Ellina , Brandt Lutz
Published: October 2015

The continuing demands of the electronics industry for faster and/or smaller products have been driving the necessity for the size reduction of all subsystems and components. This continuing trend in miniaturization leads to challenges in circuitry as adhesion of the conductor to the dielectric substrates has historically been achieved by the roughening of the substrate. This adhesion technique limits the line width because a highly roughened surface which will have strong adhesion to the copper may lead to poor line definition and compromise electrical performance and signal transfer. Alternatively, a less roughened surface with precise line definition may have poor adhesion of the copper to the substrate leading to reliability issues. It is evident that an alternative method for creating adhesion of copper to dielectric substrates is necessary. SNaP, a nanoparticle-based chemical adhesion process, will be introduced as a method to impart adhesion of electroless-deposited copper onto dielectric substrates with minimal roughening. The wide range of dielectric substrates to which this process can be applied will also be demonstrated.
Reliability of Multi-Layer Wiring Board Embedded with Two Dies in Stacked Configuration
Authors: Munakata Koji , Ueta Nobuki , Okamoto Masahiro , Onodera Kumi , Itoi Kazu , Okude Satoshi , Nakao Osamu , Tessier Theodore (Ted) G.
Published: October 2015

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides.

This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process.

We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally.

This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.
SHORT LOOP ELECTRICAL AND RELIABILITY LEARNING FOR THROUGH SILICON VIA (TSV)MID-WAFER FRONT-SIDE PROCESSES
Authors: Vartanian Victor , Hummler Klaus , Olson Steve , Barbera Tyler , Yu Kai-Hung , Hu Shan , Fujita Akira , Wafula Fred , Pattanaik Gyanaranjan , Gracias Alison , Smith Larry , Enloe Jack , Leusink Gert , Matthews Kenneth , Maekawa Kaoru , Sapp Brian
Published: October 2015

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.
A Case Study of the Reliability of Copper Bond Wires In Plastic Encapsulated Integrated Circuits
Authors: Turner Ken
Published: October 2015

Sixteen plastic encapsulated integrated circuits were initially received as part of a root-cause failure investigation, twelve of which contained copper bond wires and the other four containing gold bond wires. It was reported that eight of the integrated circuits had failed in the field with intermittent or complete malfunction of the components. Electrical testing confirmed the reported failure and found temperature sensitive, intermittent open circuits on various pins coinciding with the sample history.

C-Mode scanning acoustic microscopy (CSAM) was performed on the devices, with each sample exhibiting varying degrees of delamination between the lead-frame and the plastic encapsulant. The backside of the package was polished into the underside of the lead-frame to preclude the introduction of any contamination due to chemical decapsulation. This allowed the mechanical removal of the leads from the package and inspection of the stitch bonds. Scanning electron microscope (SEM) inspection revealed that the copper stitch bonds had corroded to some extent (ranging from mild corrosion to complete consumption of the stitch bond) in each of the examined bonds, whereas the gold stitch bonds were unaffected. Overall inspection of the leads identified chlorine contamination along the delaminated interface.
Substrate-integrated divider networks in LTCC with optimized tolerance / isolation properties for Ka-Band satellite systems
Authors: Klein Tobias , Uhlig Peter , Günner Carsten , Kulke Reinhard
Published: October 2015

Low Temperature Cofired Ceramics (LTCC) technology is increasingly used for creating high-rel solutions, especially in class S products deployed in space. Current research, executed by the german and european space agencies, focuses inter alia on new, compact beam forming networks for Ka-band multiple feed per beam antennas. These networks consist of a high number of dividers and must provide a high isolation between neighbouring cells to ensure compliance with frequency plan regulations. While the LTCC process brings a number of advantages, its thick film printing process and the tolerances of available resistive paste systems introduce difficulties in implementing typical Wilkinson divider networks. This paper presents a novel concept to implement tolerance-optimized dividers, taking special focus on the properties of the LTCC process.
Direct Write Electronics – Thick Films on LTCC
Authors: Eastman Tim , Cook Adam
Published: October 2015

For low volume, high value microelectronic applications reducing cost and time to initial production parts in Low Temperature Cofired Ceramics (LTCC) play a big part in customer satisfaction. Using Direct Write Electronics (DWE) for conductor printing and other structures has the potential to reduce time to production through elimination of intermediate tooling and to reduce waste by applying expensive materials only where they are needed. Additional benefits may be realized by using DWE: wire bonds may be replaced by dispensed conductors; individual layers and parts may be uniquely labeled at the time of printing to improve traceability of product throughout the line and reducing manufacturing errors. This paper investigates using engineered fluid dispensing to print interior and exterior conductors on a demonstration Multi-Chip Module (MCM). Industry standard materials and processes are used to form individual layers of unfired LTCC tape, as well as the forming and filling of interlayer connecting vias with conductive thick film paste. Conductor patterns on each layer are created by dispensing modified Au conductor paste with a commercial three-axis machine with a fine-tipped dispensing pump. Standard processes for collation, lamination, and sintering were followed by aerosol jet printing of Ag ink with a commercial print head mounted on a custom, 6-axis positioning gantry to form wire bond replacements, part identification and individualized markings. Resultant parts are tested for electrical functionality and cross sections are compared to in-progress build photos and line measurements to study the effect of the new printing method vs. structures produced with standard conductor printing processes.
Package-on-Package Design and Assembly Process Development for Size Reduction
Authors: Ahmad Syed Sajid , Reich Mike , Haring Fred , Berge Layne , Mattson Kevin , Bauer-Reich Cherish , Gilbertson Bob , Strommen Greg
Published: October 2015

A package-on-package configuration was designed and assembled to replicate an off-the-shelf RF device to reduce its footprint, height and thus volume. The footprint was reduced by 60% and the height was reduced by 32% resulting in 73% reduction in volume. An efficient assembly process was developed using information form electrical, thermal and mechanical simulations.
New Method for Mitigating Weave-induced Differential Skew in PWBs
Authors: Fukumori Taiga , Akahoshi Tomoyuki , Mizutani Daisuke , Tani Motoaki
Published: October 2015

Weave induced skew in printed wiring boards (PWB) in high-performance computers has become a significant problem as data rates have increased. We present a new method to reduce weave induced skew. Using three-dimensional electromagnetic simulation, we have discovered that skew can be reduced by adjusting the line width to a specific value, and that the specific values are approximately the same for both stripline and microstripline. We have ascertained the effect in actual PWB manufacturing and measurement. As a result, we have verified by measurement that skew can be reduced to less than one-third. Investigation of a wider range of line width / weave pitches by simulation suggests that skew can be reduced to less than one-tenth of a usual structure.
Epoxy Underfill Challenges for Copper (Cu) Pillar Solder Bump Packages
Authors: Schmaltz Brian , Abe Yukinari , Kohara Kazuyuki
Published: October 2015

From Eutectic, to Lead Free, to Copper Pillar (Cu) Bumping Technologies. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder ball reflow process is being pushed by advancements in copper pillar capped bumps, which in turn allows for high density lead free IO counts at sub 40um bump pitches. Even so, low CTE epoxy materials are still needed in order to dissipate stress concentrations seen during thermal cycling. What challenges await this next technological revision? This presentation will centralize around the latest advancements in epoxy materials for Advanced Packaging Technology; Capillary Underfill (CUF) for narrow pitch Lead Free Copper (Cu) Pillar Solder Bump packages.
One Step Chip Attach Materials (OSCA) for Conventional Mass Reflow Processing
Authors: Duffy Daniel J. , Xin Lin , Liu Jean , Tolla Bruno
Published: October 2015

One step chip attach (OSCA) materials are dispensable polymeric materials for flip chip assembly, which are designed to flux metallic interconnections and subsequently turn into an underfill upon curing. OSCA materials enable a drastic simplification of the assembly process by combining the reflow (fluxing/soldering), defluxing and capillary underfilling steps used in traditional processing into a single step. One key challenge for the design of OSCA materials is timing the cure kinetics with fluxing activity and solder reflow during processing. A second key challenge is to factor a process-friendly rheological design into the formulation. The OSCA material rheology must allow for high filler loading levels, seamless integration with standard dispensing equipment, flow control during and after dispense (avoid keep out zones), flow during die placement (elimination of voids), after placement (fillet formation) and during reflow. The final key requirements for a functional device are defect-free interconnections combined with optimal thermo-mechanical and water resistant properties of the final underfill to guarantee the long-term reliability of the assembly in various environmental conditions. This paper presents the properties of materials designed by Kester for use in mass reflow processing (OSCA-R). The rheological design principles behind a seamless integration into customer-friendly processes will be presented In addition results illustrating the timing of cure kinetics with fluxing and soldering events during processing will be discussed. Preliminary device reliability results will also be presented for several types of test vehicles including; Si-Si and Si-FR4.
Advancement in Thermosonic Bonding Wire
Authors: Murali S. , Deok Tark Yong , Senthilkumar B. , Xi Zhang
Published: October 2015

Coated copper (Cu) and alloyed silver (Ag) wires are the new developments in bonding wire sector and this paper discusses on its bonding performances. Palladium (Pd) coated Cu wire replaces rapidly with Au wire. A thin gold (Au) coating over Pd coated Cu wire revealed wider 2nd bond process window and superior 2nd bond bondability, termed as Au Flash Pd Coated Cu Wire (AFPC). The free air ball (FAB) formation, looping, 1st bond and reliability performance of the AFPC wire satisfies the basic requirements. The benefits of doped/alloyed Cu wire are also presented. Good reflectance properties of Ag wire replaces with Au wire in LED sector. Moreover, soft nature of Ag wire and its FAB near to Au, turn the focus to Ag as a potential bonding wire. Detailed examination on alloying additions, Ag electro migration, reliability, bondability, FAB formation, etc., are currently examined and discussed. During bonding, purging with forming gas is a common practice irrespective of the wires used (bare/alloyed/coated Cu or Ag wires).
Fine Pitch Cu Wire Bonding Capability – Process Optimization and Reliability Study
Authors: Qin Ivy , Xu Hui , Huynh Cuong , Chylak Bob , Abe Hidenori , Kang Dongchul , Endo Yoshinori , Osaka Masahiko , Nakamura Shinya
Published: October 2015

Wire bonding has been around for over 70 years and it is still growing. The most recent advances in wire bonding are the wide proliferation of fine pitch Cu wire bonded applications and the development of fine pitch Cu capability extending to the newest technology nodes. Around 2008, fine pitch Cu wire bonding started to take off driven by the skyrocketing Au price. Since then, Cu wire bonding capability has improved dramatically so that today's advanced technology devices such as 28nm and 20nm nodes are being bonded with Cu wire including Pd coated and AuPd coated Cu wire. It turns out that not only is Cu wire cheaper, but it is more suitable for high I/O counts, and fine pitch advanced node applications due to its better electrical and mechanical properties.

This paper examines the most advanced Cu wire bonding capability using a Cu optimized process called ProCuTM process. 40um pitch and 35um pitch capability are demonstrated using this new ProCu process. Process responses such as process bonding windows, intermetallic coverage (IMC), and free air ball size control are studied in detail. The ProCu process achieved fine pitch capability for 40um as a robust production process and it also shows that 35um pitch with 13um (0.5mil) wire is a possibility using the latest technology.

The JEDEC Reliability test has been a challenge for Cu wire bonding especially for fine pitch applications. As part of this paper, we also examined reliability aspects of fine pitch Cu wire bonding. TEM analysis was used to understand the major factors that affect Cu wire bonding reliability.
Gold Wirebond on Discolored Bond Pads
Authors: Andrews Derek , Hill Levi , Masood Hassan , Pidikiti Durgasamanth , Khalid Qutaiba , Hunter Stevan
Published: October 2015

An integrated circuit wafer lot having some wafers with discolored bond pads and other wafers with normal bond pads was identified, and wafers with discolored pads were scrapped. The reason for scrap is the expectation of poor bondability or unreliable wirebonds on discolored pads. The cause of discoloration was unknown. We took the opportunity to run a bonding experiment and analysis as a student project, comparing a good wafer with one having the discolored bond pads. Unprobed die from each wafer were wirebonded for mechanical integrity analysis of the bonds. Bonding recipe designed experiments included different ultrasonic generator (USG) current settings within the bonding process window, two bonding forces, and two temperatures, all thermosonic binding 25um gold (Au) wire on AlCu pad metal of 0.7um thickness. 2% non-stick-on pads (NSOP) was found at a higher ultrasonic power settings on the discolored pads, indicating that the discolored pads can indeed be problematic in wirebonding. Analysis of wire pull test and bond shear test results indicate slightly less performance of bonds on the discolored pads. Chemical and physical analysis of the discolored pads reveals the nature of the unknown cause and leads to a hypothesis about what went wrong during the wafer processing.
SIP with TSV for Class 1 Medical Devices
Authors: Link Doug
Published: October 2015

The demand for greater performance of hearing instruments in smaller form factors continues to drive the need for miniaturization of microelectronic packages. Reported here is how TSV technology was used to shrink the size of a conventional DSP-based system in package (SIP) used in the smallest In-The-Ear (ITE) hearing instruments. The conventional SIP is a heterogeneous multichip module containing a wire bonded EEPROM die mounted atop a DSP flip chip die along with 10 passive components built upon a high density alumina substrate. The wire bonds of the conventional SIP, along with the extra space they require, are eliminated and replaced by TSV structures fabricated in the DSP IC wafer using the via last method. A redistribution layer on the back side of the DSP IC enables direct attachment and electrical interconnection of the memory IC to the DSP IC. The result is a 23% smaller SIP with functionality demonstrated in hearing aid prototypes. This is believed to be the first demonstration of TSV in a heterogeneous hearing aid multichip module. This paper describes the design approach, materials, basic process steps, results, and challenges encountered in creating this novel TSV-SIP.
Challenges and Solutions in Preparation for High Resolution Failure Analysis of Power Electronics
Authors: Klengel Robert , Klengel Sandy , Böttge Bianca
Published: October 2015

The high-resolution failure analysis of power electronic devices is very challenging, as relatively large features have to be accessed and analyzed with nanometer resolution. Recently new tools have been introduced for fast and efficient sample preparation of stacked devices and complex packages. One of them is the focused ion beam (FIB) technique using a high energy Xenon Plasma-FIB. This paper outlines preparation issues needed to find the physics of failure of large and complex devices as used in power electronics. Different methods like high throughput Plasma FIB preparation to combined Laser-FIB preparation are compared. Additionally an innovative mechanical preparation technique developed for interface defect preparation of power electronic materials will be introduced. Within the paper selected case studies regarding reliability investigations and failure analysis are presented for example on silver sinter layers and bond wire contacts done by high resolution Transmission Electron Microscopy (TEM). In addition, an assessment of the analysis throughput increase, of new extended application ranges and current limitations will be given.
Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages during the Assembly Process
Authors: Macurova K. , Bermejo R. , Pletz M. , Schöngrundner R. , Antretter T. , Krivec T. , Morianz M. , Brizoux M. , Lecavelier A.
Published: October 2015

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional numerical finite element model is capable to use geometric and material properties which are not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an X-ray diffraction method (Rocking-Curve-Technique) showing a good agreement of the calculated and measured curvature radius values.
Low Cost Glass Interposer Development
Authors: Chen Yu-Hua , Hsu Shaun , Ray Urmi , Shenoy Ravi , Lai Kwan-Yu , Shorey Aric B. , Lu Rachel , Thomas Windsor P. , Hu Dyi-Chung
Published: October 2015

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage becomes critical. Traditional organic substrates may face several challenges for high density I/Os with very fine line interconnections. Glass is one of the candidates that can be used in substrate industry. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating ability.

In this paper, we successfully demonstrate early manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel of thickness of 200μm in 508mm μ 508mm panel size format and under the IC substrate manufacturing environment. Fabrication and electrical results of a test vehicle are documented. The test vehicle includes daisy chains that are connected with 100μm diameter through glass via (TGV) in a 200μm thick glass. The laser via in via technology was adopted for double side electrical connection. The copper line width/space of 8/8μm was demonstrated. The total thickness of 4 layers test vehicle is about 390μm. The warpage of glass in comparison with an organic substrate (BT) with 200μm core thickness is 3X better. Further work is needed to develop, fine tune and assess the detailed manufacturability and reliability concerns.

Based on this work, it is clear that the potential of glass in IC packaging and integration is tremendous in diverse applications for substrate warpage enhancement.
Thermal Modeling of Large Embedded GaN Transistors
Authors: Roberts J. , Klowak G. , Renaud-Bezot N. , Yushyna L.
Published: October 2015

This paper highlights the recent thermal characterization and simulation work carried out on large area embedded GaN power transistors. Two types of embedded formats are characterized and compared. A package that has a bottom side thermal pad requires thermal vias is compared, at the system level, with a package that has a top side thermal pad that can be more directly interfaced to a heat sink. In both cases a thermal interface material (TIM) is used to provide electrical insulation. GaN power transistors have Ron·Qg Figure of Merit results that are more than 10 times better than SJ MOSFETS. However Ron increases substantially as the GaN channel temperature increases. Control of the channel temperature plays a major role in achieving the promised performance improvement expected from GaN devices. It is also vitally important that the heat removal strategies do not compromise the dynamic performance of these exceptional transistors.
Thermal Management Solutions for Network File Server Used in Avionics Applications
Authors: Grosu Vicentiu , Lindgren Chris , Vejsz Tamas , Chen Ya-Chi , Bhunia Avijit
Published: October 2015

In the modern era of commercial aviation there is an increasing need for establishing on-aircraft networks that interconnect legacy avionics systems for the purpose of data collection, health monitoring, and software management. At the heart of these networks are flightworthy file servers that perform similar functions to servers used in ground-based IT infrastructures. However, the size, weight, and power constraints for airborne servers are significantly more challenging than the constraints placed on groundbased equipment. As a result, the critical goals in the development of aircraft network systems are reducing the size and weight, maximizing the performance and reliability, and reducing cost. One of the main challenges includes dissipating high power in small packages within a confined space. This makes thermal management a critical component of the overall LRU (Line-Replaceable Unit) design. In addition, passive cooling systems are often required in place of internal fans in order to improve long-term reliability of the system. This presents another set of challenges, such as optimizing the airflow provided by the aircraft in the electronics compartment. This paper will present some of the critical elements of thermal management such as heat sinking, component placement, thermal interface materials, thermal vias, thermal links, heat spreader, packaging approaches and cooling strategies. The design and optimization of this system are based on analytical solutions, conjugated heat transfer and experimental results. Thermal management solutions must enable reliable operation under various environmental conditions: ground operation, flight operation, high operating temperature and loss of cooling air. Each environmental condition has different parameters for coolant airflow rate, effect of the surroundings, and ambient and coolant air temperature. Cooling airflow analyses were performed using CFD (Computational Fluid Dynamics). We have identified multiple approaches to remove heat from the critical components through optimization of the components and subsystems. These same approaches also serve to increase the system's performance and reliability.
New Liquid Crystal Polymer Substrate For High Frequency Applications
Authors: Zimmerman Michael , Smith Keith , Scavuzzo William , Dunbar Meredith , Nair Deepukumar , Carney Thomas , Wessel Richard , Thrasher Brad , Oliver Glenn , Parisi Jim
Published: October 2015

Novel LCP films have been developed by iQLP, LLC in a Joint Development effort with Dupont, for commercialization in the Printed Circuit Board (PCB) industry, for high frequency applications. The films will be commercialized as Copper Clad Laminate (CCL), and thermoplastic bond ply. Prototype PCB's have been built to evaluate integrity during processing, and tested for mechanical reliability. The films/laminates were well suited for PCB manufacture, and the resulting board's surpassed reliability testing requirements. Of particular note, is the low Z axis coefficient of expansion of the LCP which allows for multilayer reliability and the large difference in melting temperature between the bond and circuit layer which allows for ease of manufacture. In addition RF test vehicles were established that demonstrated that the material supports very low loss signal transmission in Millimeter wave frequencies in the range 40 to 110 GHz, making this material system one of the best circuit laminates available for Millimeter wave applications today.
High Temperature Reliability of Copper Wire - Bonded Packages Encapsulated with Mold Compounds Containing Sulfur compounds
Authors: Mathew Varughese , Chopin Sheila
Published: October 2015

Copper wire-bonded (CuWB) packaging is more susceptible to corrosion than traditional inert gold wires. CuWB reliability greatly depends on the compatibility of Cu wire with the surrounding encapsulating mold compound as this matrix can provide a corrosive environment leading to reliability issues. Many mold compounds contain specific components which are sulfur-based compounds. Since the reliability testing of an encapsulated packaged device involves thermal treatments such as high temperature storage life (HTSL) test, there is a concern that corrosive sulfur compounds can be produced at high temperatures, e.g. 150 °C and 175 °C, endangering CuWB reliability. This paper describes methods of detection of sulfur compounds produced from mold compounds, if any, at high temperatures such as 175 °C and CuWB die package reliability with mold compounds containing sulfur compounds. Dynamic Headspace Concentration-Gas Chromatography–Mass Spectroscopy (DHC-GC-MS) analysis technique was used to test liberation of gaseous and volatile sulfur compounds from mold compounds at temperatures 25 °C, 150 °C, 175 °C, and 200 °C. No gaseous sulfur compounds were detected by chromatographic methods within the time period of the experiments. In order to determine sulfur containing anionic species present in the mold compound matrix, such as sulfide, sulfite, sulfate and thiosulfate, ionic compounds were extracted to water and analyzed by Ion Chromatography. Upon analysis, the only sulfur bearing anion found in the samples was sulfate. Thermally treated mold compounds for 2000 hours at 150 °C and 1000 hours at 175 °C were also extracted and analyzed to determine possible decomposition of sulfur compounds due to the thermal aging process. Corrosion due to sulfur compounds and reliability of CuWB (bare Cu-25 μm wire diameter) were evaluated by HTSL for 2000 hours at temperatures of 150 °C and 175 °C with devices packaged with mold compounds containing sulfur compounds. CuWB ball bond – Al interface and Cu stitch bond integrity were evaluated by FIB (Focused Ion Beam) - SEM (Scanning Electron Microscope) with EDX (energy dispersive X-ray spectrometer) analysis and wire pull and ball shear testing of CuWB ball bonds. No reliability issues due to sulfur compounds were found with mold compounds containing sulfates up to about 45 ppm.
Packaging Induced Die Stress Characterization Using van der Pauw Sensors Between −180°C and 80°C
Authors: Goteti Uday S. , Akkara Francy J. , Jaeger Richard C. , Hamilton Michael C. , Suhling Jeffrey C.
Published: October 2015

Packaging-induced die-stresses due to temperature effects on various materials of the package are characterized using piezoresistive van der Pauw stress sensors over a temperature range of −180° C to 80° C. Piezo-resistive coefficients extracted previously are then used to obtain a mapping between change in resistance and corresponding stress at all tested temperatures. The obtained values of stress are compared with finite element simulation results.
Characterization of Thermally Induced Stress in IC Packages Using PiFETs Over a Temperature Range of −180°C to 80°C
Authors: Akkara Francy J. , Goteti Uday S. , Jaeger Richard C. , Hamilton Michael C. , Palmer Michael J. , Suhling Jeffrey C.
Published: October 2015

In certain applications, IC packages may be exposed to extreme temperatures and knowledge of thermally induced stress aids the prediction of performance degradation or failure of the IC. In the devices that are used in extreme conditions, the stress is caused mainly by the mismatch in expansion of various materials triggered by the different coefficients of thermal expansion. This work performed in this study is conducted using NMOS current mirror circuits that are cycled through a wide temperature range of −180°C to 80°C. These circuits are highly sensitive to stress and provide well-localized measurements of shear stress. The sensors are fabricated in such a way that the effects of certain stress components are isolated. These sensors are also temperature compensated so that only the effect of mechanical stress components is observed and changes in device performance due to temperature changes are minimal. Current readings obtained from the sensors are used to extract the shear stress component. Finite element simulations, using expected materials performance parameter information were also performed for similar packages and these results are compared to the measured results.
High-Temperature-Resistant Interconnection Using Nickel Nanoparticles
Authors: Tanaka Yasunori , Hashimoto Suguru , Iizuka Tomonori , Tatsumi Kohei , Matsubara Norie , Ishikawa Shinji , Tanaka Masamoto
Published: October 2015

The bonding characteristics of nickel nanoparticles as a new alternative bonding material for high-temperature soldering was considered and a high bonding strength was achieved at a bonding temperature of 300°C. It was also revealed in a bonding experiment using a silicon dummy chip with a deposited aluminum layer that direct bonding to an aluminum electrode was possible. On the other hand, a stress-relaxation structure using a metal film was presented as a new structure for resolving the problem of deteriorating bonding reliability due to thermal stress arising from differences in the coefficient of thermal expansion between the chip and the substrate. A silicon carbide device was assembled using the new bonding method and an operating test was performed to verify normal operation in a high-temperature environment of approximately 300°C.
A Small Feature-Sized Organic interposer for 2.1D Packaging Solutions
Authors: Romero Christian , Lee Jeongho , Oh Kyungseob , Harr Kyoungmoo , Kweon Youngdo
Published: October 2015

The continuing advancement of semiconductor devices steadily increase the number of global interconnects and higher I/O counts thus driving more the importance of smaller feature size interconnects. One of the most difficult technical challenge for interconnects involves new material development, however, it is believed that mitigation of the impact of size scaling such as its aspect ratio (thickness/width) and spacing could fill the gap for high dense packaging requirement brought by Moore's Law. The next generation substrate design rules require a process capability with less than 50um pitch to accommodate leading-edge mobile applications such as Wide I/O memory-Logic packaging integration.

In this paper, we describe an organic interposer that is capable of providing high density interface between chips with large I/O counts therefore could be an attractive low-cost 2.1D packaging solution. Our concept can demonstrate ultra fine line interconnects with width/space below 5um with microvias having pitch below 50um which can be effective solution for high density routing. This feature enables the ICs to be attached directly to the substrate therefore eliminating the need for a silicon interposer needed in conventional 2.5D package architecture.

Microvia formation using photo-imageable material is another key feature of our organic interposer offering favorable cost efficiency for designs requiring very large numbers of microvias. The buildup layers could be vertically connected by microvias with min. 10um diameter using this process. Aside from the simplicity in supply chain, the high density organic interposer has the potential to meet both power and bandwidth requirement therefore can be considered an incremental move from conventional system-in-package providing flexibility in performance and yield capacity that allows integration of advanced logic and memory devices.

We will present our various feasibility results of electrical/mechanical performance obtained from our fabricated test vehicles.
Magnetic Field Imaging for Non-Destructive 3D Package Fault Isolation
Authors: Gaudestad Jan , Vallett David
Published: October 2015

While microelectronic packages are becoming more and more advanced, the need for non-destructive Electrical Fault Isolation (EFI) becomes ever more critical for the entire product life-cycle ranging from the chip development yield enhancements to failures on product returns. In the beginning of product development, short failures are often the main issue while opens and cracks become the reliability problems after the product reaches the marketplace. In this paper we present Magnetic Field Imaging (MFI) as the one technique that can find all static defects: shorts, leakages and opens in a true non-destructive way.
SEM-based X-ray tomography of sub-micrometer defects in 3D integration
Authors: Laloum D. , Ribière C. , Gottardi M. , Mourier T. , Lorut F. , Bleuet P.
Published: October 2015

3D integration is a promising technology to overcome miniaturization challenges and chips densification. It consists in increasing the number of components by realizing vertical pileups of interconnected chips. Solder balls, through silicon vias (TSVs) and copper pillars are widely used for that purpose. It is essential to characterize these metallic structures in order to validate the fabrication process and to ensure an optimal connection between the different chips. Here, X-ray tomography is proposed as a non-destructive technique to investigate metallic interconnections. In particular, the potential of an innovative computerized tomography (CT) system, the X-ray tomography hosted in a scanning electron microscope (SEM), is presented. Since sample preparation is an important step of the X-ray characterization process, the use of a Plasma Focused Ion Beam (P-FIB) to extract large chunks out of the bulk silicon is reported. We expose an original work towards systematic studies: in order to validate a new copper filling chemistry, five samples containing TSVs at various filling rates have been scanned and the 3D results are shown. Chunks containing completely filled TSVs have then been scanned and their resulting 3D reconstructions demonstrate that the instrument is able to detect 500 nm diameter voids. The advantages and limitations of this characterization method are finally pointed out.
Comparison of Aluminum Electrolytic Capacitor Lifetimes Using Accelerated Life Testing
Authors: Gulbrandsen Stephani , Arnold Joelle , Caswell Greg , Cartmill Ken
Published: October 2015

This research compared the lifetime of similar aluminum electrolytic capacitors from different manufacturers using an accelerated life test, which consisted of critical weight loss testing and rate of weight loss testing. In critical weight loss testing, capacitors are perforated to speed up electrolyte evaporation and the equivalent series resistance (ESR) and weight are measured periodically to determine their relationship. In rate of weight loss testing, capacitors are subjected to final operating conditions (i.e. voltage and ripple current are applied) and the weight is periodically measured over the course of 500 hours. After test completion the relationship between ESR and weight loss is used to calculate the critical weight loss that occurs at datasheet-defined failure, which is typically a 200% increase in ESR. The rate of weight loss is extrapolated to the critical weight to estimate a time to failure that can be compared to other capacitors tested using the same accelerated approach. In this research, testing compared 450 V, 68 μF capacitors from Manufacturer A and Manufacturer B, and results indicated Manufacturer A had a significantly longer lifetime. Therefore, capacitors from Manufacturer A are more reliable than capacitors from Manufacturer B.
High Value Thin Wafer Support Technology for 3DIC
Authors: Pettit Jared , Law Alman , Brewer Alex , Moore John
Published: October 2015

As the 3DIC market matures, more is understood about the technical and cost challenges [1]. At the 2013 Semicon-West gathering, a panel of global experts identified these technical challenges to represent some of the most significant barriers to the industry's efforts to maintain progress with Moore's Law [2]. Searching and achieving high value manufacturing of 3DIC devices requires wrestling with several technologies and processes, all which may assert a different value for the manufacturer [3]. Current technologies for thin wafer support use a wide range of adhesives applied to the device wafer, bonded to a carrier, backside processed, and de-bonded by an array of methods. Daetec has been investigating temporary bonding for nearly 15yrs, is producing a range of products for semiconductor (e.g. WaferBondTM (Brewer-Science, Inc.)) [4], and for the display market using a low-cost tunable adhesion-force material that is peeled by simple means [5]. Daetec has developed a new technology, DaeBond 3DTM, allowing de-bonding to occur in a batch process while thinned wafers are affixed to film frames. This new approach provides a shift in conventional practice. Our paper presents several temporary bonding options with DaeBond 3DTM in an effort to define value-added approaches for thin wafer handling.
Hermetic Electrical Feedthroughs Based on the Diffusion of Platinum into Silicon
Authors: Rudmann Linda , Ordonez Juan S. , Zappe Hans , Stieglitz Thomas
Published: October 2015

Within this paper a novel approach for the development of hermetic electrical feedthroughs is introduced. So far, every vertical feedthrough induces at the feedthroughs' interfaces possible paths for water to leak across the hermetic barrier into the hermetic package. The presented approach is based on the diffusion of platinum into silicon, locally changing the electrical behavior of the substrate due to the induced impurities. This method avoids destroying the bulk material, in this case silicon, preserving the hermetic barrier environment. Different n-type silicon substrates were investigated for their usability through various diffusion experiments under two gas atmospheres: Argon/hydrogen and pure nitrogen. A significant change in silicon behavior could be shown for one of the used substrates. The current flowing through the bulk could be decreased by a factor of around 12 for an argon/hydrogen atmosphere and by around 10 for pure nitrogen. The current directly correlates with a local increase of the substrates' resistance, demonstrating the possibility of adapting the electrical properties of a substrate to create insulating areas within a conductive substrate.
DBC Switch Module for Management of Temperature and Noise in 220-W/in3 Power Assembly
Authors: Kim Woochan , Shin Jongwon , Ngo Khai D. T.
Published: October 2015

Achieving high power density is a challenge in the presence of stringent specifications on temperature rise and switching noise. Integration of the DBC module with PCB mother board was found to be the right approach to achieve 220-W/in3 power density, 2-kW output power, and 48.9°C junction-temperature rise. The reduced layout inductance (2.89-nH) at the source and the negative coupling between source and drain layout inductances suppressed turn-off noise. The prototyped dc-dc boost converter switched between 400 kHz to 1 MHz without self-turn-on problems and efficiency was 98.4 % by employing DBC switch module.