(Digital Presentation) Instability of α-Si:H TFTs under Simultaneous Ultraviolet Light Illumination and Different Bias Stresses
Authors: Liu Han-Wen , Hung Tzu-Cheng , Huang Bo-Xiang 
Published: November 2022

Hydrogenated amorphous silicon thin-film transistors (α-Si:H TFTs ) are widely applied in liquid crystal displays (LCD). They can be used as not only the switching devices in the panel but also the scan driving circuit in the active-matrix liquid crystal displays (AMLCD), as well as large-area optical imaging sensor arrays. The α-Si:H could be deposited on the glass or plastic substrates at the low temperature, good uniformity in the large area, and the process is relatively mature, so it is still a competitive material. This study would investigate the deterioration of the α-Si:H TFTs under various bias stressing conditions with and without UV light.

For the DC bias stress on the gate terminal, the electron trapping within the gate dielectric under positive bias would cause the threshold voltage (Vth) to shift to the positive direction, but the hole trapping under negative bias would cause the Vth to shift to the negative one. Furthermore, under the DC bias stress, the UV light illuminates the TFTs simultaneously, and the active layer of TFTs would generate additional electrons and holes, which would increase the trapping probability of charges and the amount of degradation and recovery. Both effects of the electron capture in the dielectric and defects creation in the channel would cause the Vth to shift to the positive direction, so the degradation of TFTs under positive bias stress is relatively serious. The increment of the subthreshold swing of TFTs under negative bias stress would be much larger than those under positive one, and the captured holes are easily released in the reverse sweeping mode, leading to the decrease of the drain current. Therefore, the amount of degradation and recovery of the TFTs under negative bias stress is relatively small in the reverse sweeping mode, because the energy barrier of holes is smaller than that of electrons in the interface of α-Si:H/SiNx.

For the experiments of AC bias stress on the gate terminal with UV light illuminating simultaneously, the frequency of AC signal is fixed at 10 KHz. It could be found that the leakage current in the cut-off region under negative bias (-35 ~ 0 V) stress would increase with the stress time lasting, which shows that the holes are trapped within the gate dielectric closer to the active layer at the high frequency. These shallow positive trapped charges would attract the electrons to accumulate in the channel region, which causes the drain current to increase gradually. However, under bipolar bias (-17.5 ~ +17.5 V) stress, the charge trapping would first dominate the Vth degradation of TFTs, and then the defect states creation would gradually dominate the change of the Vth as the stress time increasing, which causes the Vth first to shift to the negative direction and then to positive one.

For another experiments of AC bias stress on the gate terminal without UV light illumination, the frequencies of AC signals are fixed at 10 Hz and 10 KHz with different ranges of biasing voltages. It could be found that the Vth degradation of TFTs at different frequencies under the higher positive bias cycle (0 ~ +35 and -10 ~ +25 V) is not obviously different, mainly because the speed of electron’s accumulation and disappearance in the channel region could keep up with the switching speed of AC signals. However, it could be found that during the higher negative bias cycle(-35 ~ 0 and -25 ~ +10 V), the amount of change in the Vth at low frequency is relatively larger than that at high frequency, which is due to the RC delay effect of the n+α-Si:H layer on the holes under negative bias stress. To investigate the recovery behavior of TFTs, including the direction and amount of the Vth change in the resting time, we could know the dominating mechanism that leads to the TFT’s degradation. And the probably balanced AC bias stress condition is about -10 ~ +25 V. As the magnitude of negative biasing voltage increases, the holes capture within the gate dielectric would increase, and the drain current in the cut-off region also increases.

Finally, the β parameter, in the formula of ΔVth= Atβ, is obtained by fitting the trends of ΔVth v.s. stress times. The value of β parameter would exhibits the influence of different mechanisms on the degradation of TFTs stressed by different bias conditions and with/without UV light illumination over the stressing time. And these results are consistent with above experimental data.