bluuebunny/crossref_metadata_2025 huggingface dataset:
Improvement of Boron Doping in SiGe Raised Sources and Drains for FD-SOI Technology by Carbon Incorporation
Authors: Labrot Maxime , Cheynis Fabien , Barge David , Juhel Marc , Müller Pierre
Published: September 2016

Selective epitaxial growth (SEG) of highly boron-doped SiGe (SiGe:B) is a key step to realize Raised Source and Drain (RSD) for applications in SiGe-based microelectronic devices. This paper is devoted to the optimization of boron dopant profiles in SiGe RSD. For this purpose Fully-Depleted Silicon-On-Insulator (FD-SOI) blanket and patterned wafers are considered. We show that, in both situations, a weak carbon incorporation increases the dopant level and flattens the boron profile in the RSD. Finally experimental conditions for optimal RSD fabrication are reported.
Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations
Authors: Hashemi Pouya , Balakrishnan Karthik , Ando Takashi , Bruley John , Ott John A. , Engelmann Sebastian , Chan Kevin , Lee Kam-Leung , Park Dae-Gyu , Mo Renee T. , Leobandung Effendi
Published: September 2016

High Ge content SiGe FETs have recently drawn significant attention as a candidate for p-MOSFETs due to their enhanced transport and reliability properties and compatibility with bulk or SOI substrates. In addition, compared to strained pure germanium, they can offer reduced off-state tunneling leakage due to their relatively larger bandgap. Utilization of high Ge content SiGe in a FinFET architecture by direct epitaxial growth is quite challenging due to epitaxial critical thickness constraints, resulting in high levels of defectivity which may be detrimental to the device functionality and performance. In this paper, we review our recent progress on high Ge content SiGe FinFETs with Ge content over 60%. In particular, gate stack, passivation and equivalent oxide thickness scaling are major factors in achieving high quality devices based on high Ge content SiGe. We present our results based on a Si-cap-free FinFET surface passivation to achieve excellent sub-threshold swings for both gate first and replacement high-K and metal gate integration flows. In addition, various device aspects such as transport and mobility, S/D and junction, off-state drain leakage current and short channel performance are discussed.
Integration of Low Temperature SiGe:B Raised Sources and Drains in p-Type FDSOI Field Effect Transistors
Authors: Lu Cao-Minh Vincent , Fenouillet-Beranger Claire , Hartmann Jean-Michel , Rodriguez Philippe , Benevent Véronique , Samson Marie-Pierre , Previtali Bernard , Tabone Claude , Cassé Mikael , Allain Fabienne , Romano Giovanni , Brunet Laurent , Batude Perrine , Skotnicki Thomas , Vinet Maud
Published: September 2016

In order to enable 3D sequential CoolCubeTM integration, low temperature epitaxy of raised sources and drains below 500°C is required. However, bad surface preparation and degradation of the epitaxial layer quality are then issues that need to be addressed. In this work, we first study different combinations of thermal, wet and dry surface preparation in order to find an optimum sequence. Then, we present for the first time the integration of SiGe:B raised sources and drains grown at 500°C in p-type FDSOI MOSFETs.
Comparative Analysis of Growth Rate Enhancement and Ge Redistribution during Silicon-Germanium Oxidation by Rapid Thermal Oxidation
Authors: Rozé Fabien , Gourhant Olivier , Blanquet Elisabeth , Bertin François , Juhel Marc , Abbate Francesco , Pribat Clement , Duru Romain
Published: September 2016

SiGe-On-Insulator layers are promising materials for high mobility pMOSFET channels and can be fabricated by the condensation technique. This technique is based on SiGe oxidation and a sound understanding of it is thus needed in order to fabricate optimized SGOI structures. The present study is a read-across of oxidation kinetics and Ge redistribution during dry Rapid Thermal Oxidation (RTO) of SiGe layers with different compositions and different oxidation temperatures. The evolution of the Ge concentration below the oxidation front is found to follow different regimes depending on the oxidation temperature. We examine them in light of a competition between oxidation rate and diffusion rate. It is also shown that RTO of SiGe is faster than Si and that the oxidation rate depends not only on the initial Ge concentration, but also on the oxidation temperature. A correlation between the Ge concentration below the oxidation front and oxidation kinetics is evidenced.
(Invited) SiGe Applications in Automotive Radars
Authors: Liebl Wolfgang , Boeck Josef , Aufinger Klaus , Manger Dirk , Hartner Walter , Heinemann Bernd , Lachner Rudolf
Published: September 2016

An overview of the SiGe technologies used at Infineon Technologies for radar applications will be given. The production of bare-die chips started in 2009 using the bipolar technology B7HF200. Since 2012 packaged MMICs in an embedded wafer level ball grid array (eWLB) are available. Process challenges and solutions for radar chips in an eWLB package are presented. Examples of commercial SiGe radar chips in production are shown. Furthermore Infineon’s next generation BiCMOS technology B11HFC with fT of 250 GHz and fmax of 370 GHz is described. In addition, significant improvements of the cut-off frequencies can be achieved by replacing the currently used double-poly self-aligned configuration by a more advanced SiGe HBT architecture like IHP’s transistor module with selective base link epitaxy. The capability of this transistor cell for future BiCMOS generations was demonstrated by integrating it into Infineon’s 130 nm CMOS process. A transistor performance with fmax of 500 GHz was achieved.
On the Challenges of SiGe HBTs in Advanced BiCMOS Technology Toward Half THz fMAX
Authors: Liu Qizhi , Jain Vibhor , Camillo-Castillo Renata A , Pekarik John J , Adkisson James W. , Joseph Alvin , Harame David L.
Published: September 2016

Advanced BiCMOS technology employing SiGe HBTs is a cost-effective candidate for a wide range of exciting applications including automotive radar and 5G wireless communications. In this paper, results from two experimental studies are presented in an advanced 90nm SiGe BiCMOS technology in production. One experiment reduces the collector-base capacitance, while the other reduces base resistance. Both experiments achieved 300GHz fT and met or exceeded the 360GHz fMAX goal of the technology. Furthermore, results from a series of experiments are also reviewed in this paper, showing paths toward SiGe HBTs of half THz fMAX and fT around 300 GHz, based on the same 90nm SiGe BiCMOS technology.
An Analytical Model of Avalanche Multiplication Factor for Wide Temperature Range Compact Modeling of Silicon-Germanium Heterojunction Bipolar Transistors
Authors: Zhang Huaiyuan , Niu G.
Published: September 2016

This paper presents a new semi-empirical avalanche multiplication factor (M-1) model for wide temperature range compact modeling of SiGe HBTs. Current dependence of M-1 is also accounted for and shown to be important for accurate modeling of output characteristics at medium to high current levels of practical interest. The proposed model is implemented into an experimental version of Mextram and demonstrated to be effective from 93 K to 393 K.
Power-Dependent Transient Gain Study on Direct Gap GeSn Crystallized on Amorphous Layers
Authors: Wang Xiaoxin , Li Haofeng , Liu Jifeng
Published: September 2016

In this study we investigate the power-dependent femtosecond transient gain of direct-gap Ge0.91Sn0.09 thin films crystallized on amorphous SiO2 layers. At carrier injection density Δn<1×1017 cm-3, there is no optical bleaching. When Δn increases to ~8×1018 cm-3, the Ge0.91Sn0.09 film becomes transparent at λ~2000 nm. At higher injection of Δn~2×1019 cm-3, net transient gain is observed at λ=1900-2150 nm, with a peak gain of 6300 cm-1 at λ=2000 nm. Further increasing Δn to ~1×1020 cm-3, the peak of transient gain red-shifted to 2100 nm due to the bandgap renormalization, and the peak gain further increases to ~8000 cm-1. The transient gain coefficient of Ge0.91Sn0.09 is similar to III-V direct bandgap semiconductors at similar injection levels. The gain lifetime was measured to be ~0.1 ns at λ=2100 nm and Δn~6×1018 cm-3. These results confirm that direct-gap GeSn crystalized on amorphous SiO2 is a good optical gain medium towards 3D photonic integration.
(Invited) GeSn Short-Wave Infrared Photodetectors
Authors: Cheng Buwen , Liu Zhi , Zheng Jun , Su Shaojian , Zhang Dongliang , Wu Wenzhou , Xue Chunlai , Wang Qiming
Published: September 2016

Ge photodetector is very success in the Si-based photonics. Butdue to the limitation of the bandgap, Ge photodetector can’t beoperated at light wavelength longer than 1600nm. Theincorporation of Sn into Ge adjusts the band structures, andeffectively shrinks the bandgap relative to pure Ge. This makesGeSn photodetector a promising device for short-wave infraredlight detection (about 2000nm wavelength). In this paper, growthof GeSn alloys on Si and Ge substrates by MBE and sputtering willbe introduced. GeSn PIN photodetectors were fabricated by CMOScompatible process. The performance of the GeSn PDs, such asdark current, response spectra and quantum efficiency will bepresented and discussed.
Mid-Infrared Sensing Using Heavily Doped Germanium Plasmonics on Silicon Substrates
Authors: Baldassarre Leonetta , Sakat Emilie , Frigerio Jacopo , Frigerio J. B. J. , Samarelli Antonio , Giliberti Valeria , Pellegrini Giovanni , Gallacher Kevin , Fischer Marco , Brida Daniele , Isella Giovanni , Biagioni Paolo , Paul Douglas J , Ortolani Michele
Published: September 2016

Heavily-doped semiconductor films are very promising for applications in mid-infrared plasmonic devices because the real part of their dielectric function is negative and broadly tunable in this wavelength range. In this work, we investigate, n-type doped Ge epilayers grown on Si substrates. We design and realize Ge nano-antennas on Si substrates demonstrating the presence of localized plasmon resonances, and exploit them for molecular sensing in the mid-infrared.
In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain
Authors: Qi Yi , Peng Jianwei , Lo Hsien-Ching , Holt Judson Robert , Willemann Michael , Gaire Churamani , Evans Sarah , Flanagan Patrick , Yu Hong , Hu Owen , Kennett Michael
Published: September 2016

In-situ Boron doped embedded SiGe epitaxy has been widely used for CMOS source/drain in advanced technology nodes, from its introduction in planar devices to its more recent application in FinFETs. Compared to planar technology, FinFETs have the benefit of an improved short channel effect, which enables significantly higher in-situ doping level for lower contact resistance. This work explores the source/drain expitaxy design differences between planar and FinFET transistors, and how the in-situ doped epitaxy process can be optimized to address the call for a higher doping level in the FinFET source/drain. Specifically, we observe a competing relationship between germanium and boron incorporation -- increasing Ge incorporation generally lowers boron doping, and increasing boron incorporation generally lowers Ge. Moreover, our work shows that the limit of boron doping can be boosted by increasing Ge percentage, and furthermore a Si-Ge-B phase diagram is proposed based on this experimental data. Defective epitaxy is observed outside of the soluble region of the phase diagram, featuring Boron-rich incoherent phase or Boron segregation. Finally, we present device data that show the performance benefit when Ge% and boron is optimized according to the phase diagram, characterized by lower Ron and higher drive current.
Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs
Authors: Wang Guilei , Luo Jun , Qin Changliang , Cui Hushan , Liu Jinbiao , Jia Kunpeng , Li Junjie , Yang Tao , Li Junfeng , Yin Huaxiang , Zhao Chao , Ye Tianchun , Yang Ping , Jayakumar Ganesh , Radamson Henry H
Published: September 2016

In this study, the process integration of SiGe selective epitaxy on source/drain and SiGe/Ge bilayers selectively epitaxy on replacement Si channel regions for 14 nm node FinFETs has been presented. The epi-quality, layer profile and strain amount of the selectively grown SiGe and Ge layers were also investigated by means of various characterization tools. A series of prebaking experiments were performed for different temperatures in order to in-situ clean the Si fins prior to the SiGe S/D epitaxy. It was also found that a SiGe layer with graded Ge content was deposited as the strain relaxed buffer (SRB) layer in the channel trench prior to the Ge layer filling in the small trenches to make the void defect free.
(Invited) Group IV Epitaxy Applications for Enabling Advanced Device Scaling
Authors: Colombeau Benjamin P , Bauer Matthias , Wood Bingxi Sun , Chung Hua , Hebb Jeffrey , Huang Yi-Chiau , Tao Xianzhi , Chopra Saurabh , Dube Abhishek , Chudzik Michael , Chu Schubert
Published: September 2016

In this paper, we first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, channel mobility, sub-fin isolation, and sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.
Thermal Rounding Kinetics and Demonstration of Steep and Flat Facets Succession in Selective Si-Based Epitaxy
Authors: Paredes-Saez Victorien , Dutartre Didier , Bremond Georges
Published: September 2016

In the first part of this work, a quantitative study of rounding kinetics in Si1-xGex (SiGe) epitaxies on patterned wafers is shown. A perfect screening of different patterns’ morphological evolution during annealing is performed by AFM. This allows the kinetics to be quantified by measuring the displaced volume of matter during the annealing. Two energies are extracted: 7.1eV between 650°C and 675°C and 1.2eV between 675°C and 700°C. The second part deals with the behavior of Si-based caps deposited on a non-flat surface. Different caps (Si vs SiGe) of different thicknesses were used. Both caps do not behave in the same way since SiGe caps are more efficient to flatten the rounded surface and obtain a “standard” morphology as if it was deposited on a perfectly flat surface. This is not the case for Si which makes a succession of terraces when deposited on such a surface.
(Invited) In-Situ Doped Epitaxial Growth of Highly Dopant-Activated n
+-Ge Layers for Reduction of Parasitic Resistance of Ge-nMISFETs
Authors: Moriyama Yoshihiko , Kamimuta Yuuichi , Ikeda Keiji , Sakai Akira , Tezuka Tsutomu
Published: September 2016

An n
+-Ge layer with a carrier density of 7 x 1019 cm-3 (physical dopant concentration = 1 x 1020 cm-3) was successfully grown by choosing an appropriate growth condition with a conventional low-pressure CVD technique. We found that a high activation rate of the n-type dopants can be realized at some limited growth pressure range. Ti contacts on the P-doped n
+-Ge epi-layers exhibited ohmic properties in contrast to those on P ion-implanted Ge layers of almost the same dopant concentration. Low sheet resistance of 33 Ω/sq and low specific contact resistivity of 1.2 x 10−6 Ωcm2 were obtained for the 65-nm-thick epi-Ge layers as a result of the high activation rate. By applying the n
+-Ge layers to Source/Drain region of GeOI-nMISFETs (Lch=60nm) to reduce the parasitic resistances, a high drive current of 300 mA/mm was obtained at Vd=1V, Vg-Vth=1.5V.
Very Low Temperature Epitaxy of Heavily In-situ Phosphorous Doped Ge Layers and High Sn Content GeSn Layers
Authors: Aubin Joris , Hartmann Jean-Michel , Barnes Jean-Paul , Pin Jean-Baptiste , Bauer Matthias
Published: September 2016

We have studied at temperatures 350 °C and less, the 100 Torr epitaxy of heavily in-situ phosphorous doped Ge and high Sn content (> 6 %) GeSn alloys in a 200 mm industrial Reduced Pressure - Chemical Vapor Deposition tool. A dedicated low temperature Ge precursor, digermane (Ge2H6), was used here in order to promote Sn or P incorporation. We have first of all quantified the impact of the phosphine (PH3) flow on the structural and electrical properties of Ge:P layers. We have then investigated the epitaxy of high Sn content GeSn binaries with tin tetrachloride (SnCl4).
(Invited) Integration of III/V Hetero-Structures By Selective Area Growth on Si for Nano- and Optoelectronics
Authors: Kunert Bernardette , Guo Weiming , Mols Yves , Langer Robert , Barla Kathy
Published: September 2016

Selective area growth by metal organic vapor phase epitaxy of III/V nano ridges on patterned (001) Si substrates was investigated applying different growth conditions. The deposition of mismatched III/V materials in narrow oxide trenches leads to an efficient defect trapping at the trench side walls whereas the growth out of the trenches allows for a clear ridge formation with increased III/V volume. The ridge evolution depends strongly on the chosen growth parameters as well as mask pattern. InGaAs/GaAs and InGaP/GaAs hetero-structures were integrated on box shaped GaAs nano ridges in order to realize first laser device structures for optoelectronics on 300 mm Si substrate.
(Invited) Enabling Hetero-Integration of III-V and Ge-Based Transistors on Silicon with Ultra-Thin Buffers Formed by Interfacial Misfit Technique
Authors: Gong Xiao , Yadav Sachin , Goh Kian Hui , Tan Kian Hua , Kumar Annie , Low Kian Lu , Jia Bowen , Yoon Soon-Fatt , Liang Gengchiau , Yeo Yee-Chia
Published: September 2016

In this paper, we discuss the application of the interfacial misfit (IMF) technique to enable the heterogeneous integration of III-V and Ge-based transistors on Si substrates. Ge pFETs and InAs nFETs were co-integrated on a Si substrate using common contact formation, digital etch, and gate stack formation modules. In addition, vertically stacked nanowire (NW) GaSb pFETs and InAs nFETs on Si substrates were also realized.
(Invited) SiGe and III-V Materials and Devices: New HEMT and LED Elements in 0.18-Micron CMOS Process and Design
Authors: Fitzgerald Eugene A , Lee K.E. , Yoon Soon-Fatt , Chua S.J. , Tan Chuan Seng , Ng G.I. , Zhou X. , Gong Xiao , Chang J.S. , Peh L.S. , Boon C.C. , Antoniadis D.a. , Yadav Sachin , Nguyen X.S. , Kohen D.a. , Kumar Annie , Zhang Li , Lee Kwang Hong , Liu Z.H. , Chain S.B. , Ge T , Choi P.
Published: September 2016

We have established new methodologies, materials, processing, devices, and circuits for integrating III-V devices monolithically into CMOS circuits. Certain constraints were applied on this research from the start in order to converge on viable commercial strategies as the research moves closer to a path for new innovation in the semiconductor industry. Integration technology has been established for incorporating HEMTs and LEDs into CMOS integrated circuits, and both nitride-based and arsenic-phosphide-based materials are currently supported. Device models are inserted into standard foundry design libraries, allowing silicon technology efficiencies such as exploring various circuit designs before final physical silicon and fabrication-test feedback loops using test chip designs.
Challenges and Opportunities of Near and Mid-Infrared Photonics Based on SiGe and Ge
Authors: Takenaka Mitsuru , Kim Younghyun , Han Jae-Hoon , Kang Jian , Takagi Shinichi
Published: September 2016

Silicon-germanium (SiGe) and germanium (Ge) have been investigated as high-mobility channel materials for high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The intense development of heterogeneous integration of SiGe and Ge on Si has given us opportunities to extend functionalities of photonic integrated circuits based on Si photonics technologies. We have investigated strain engineering by SiGe for enhancing modulation efficiency in Si optical modulators. By using the light hole effective mass in strained SiGe, we have demonstrated the enhanced plasma dispersion effect in SiGe. In addition to low-dark-current Ge photodetectors with GeO2 passivation, we have proposed Ge CMOS photonics for mid-infrared integrated photonics platform. We have successfully demonstrated Ge passive waveguide devices as well as carrier-injection variable optical attenuator operated at a 2-µm wavelength on Ge-on-Insulator wafer.
Modeling and Simulation of Negative Capacitance Gate on Ge FETs
Authors: Liao Yu-Hung , Fan Sheng-Ting , Liu C. W.
Published: September 2016

In this work, a polysilicon-ferroelectric gate capacitor is proposed to be stacked on the Ge-MOSFET to simultaneously maintain the stability and the potential amplification in the sub-threshold region of a Negative Capacitance Field Effect Transistor. Hence, the non-hysteresis ID-VG characteristics with sub-60mV/dec subthreshold slope can be designed. A simple capacitance model including the effects of gate-to-source/drain overlap, interface trap states at oxide/Ge, and polysilicon/FE/metal is presented to analyze the subthreshold behavior. The optimized SS is further improved when the direct S/D overlap with floating metal of Ge-MOSFET increases. The polysilicon doping concentration causes the trade-off between subthreshold swing and hysteresis-free maximum voltage. The impact of the interface traps at the FE/poly interface on the device performance and the optimization approach are also discussed.
(Invited) The Use of Silicon-Germanium Superlattices in Thermoelectric Devices and Microfabricated Generators
Authors: Ferre Llin Lourdes , Mirando Francesco , Samarelli Antonio , Odia Ameze , Cecchi Stefano , Etzelstorfer Tanja , Müller Gubler Elisabeth , Chrastina Daniel , Isella Giovanni , Stangl Julian , Weaver John M R , Dobson Phil , Paul Douglas J
Published: September 2016

Low dimensional structures such as superlattices have the potential to improve the thermoelectric properties of materials by engineering the scattering of phonons to reduce the thermal conductivity and therefore improve the thermeoelectric performance. Here we demonstrate the reduction in thermal conductivity in Ge/SiGe superlattices using multiple barrier engineering to scatter acoustic phonons at the key wavelengths for thermal transport. The approach allows ZT to be increased in wide quantum well superlattices through the reduction of heterointerfaces which scatter both electrons and phonons.
(Invited) Graphene for Biosensor Applications
Authors: Matsumoto Kazuhiko
Published: September 2016

As graphene has the two-dimensional electron gas with ultra high mobility on its surface, it is the optimal material for sensor application with high-sensitivity. In this study, we have succeeded in selective detection of the bird and human influenza virus using the sugar chain modified graphene FET for the first time.
(Invited) Germanium Enrichment for Planar-, Fin- and Nanowire-Channel MOSFETs Made on SOI
Authors: Augendre Emmanuel , Loubet Nicolas , Morin Pierre Francois , Liu Qing , Schmitt Joël , L'Herron Benoît , Nguyen Phuong , Barraud Sylvain , Hutin Louis , Maitrejean Sylvain , De Salvo Barbara , Coquand Rémi , Reboh Shay , Venigalla Rajasekhar , Doris Bruce , Yamashita Tenko , Faynot Olivier , Vinet Maud
Published: September 2016

This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid excessive Ge pile-up on tensile-strained planar Si films due to lower Ge diffusion. Patterning SiGe Fins in thick blanket SiGe layers faces the crystal quality limits set by plastic relaxation beyond critical thickness. As an alternative, Ge enrichment of pre-existing Si Fins requires conformal SiGe growth and can produce strained SiGe Fins up to 50% without significant relaxation, independently from Fin height. Enrichment requirements for NWFETs are identical to those of planar devices. As a result, NWFETs benefit from both SiGe mechanical stability and uniaxial compressive strain performance enhancement.
(Invited) Graphene Synthesis and Processing on Ge Substrates
Authors: Lukosius Mindaugas , Lippert Gunther , Dabrowski J , Kitzmann Julia , Lisker Marco , Kulse P , Krüger Andreas , Fursenko Oksana , Costina Ioan , Trusch Andreas , Yamamoto Yuji , Wolff Andre , Mai Andreas , Schroeder Thomas , Lupina Grzegorz
Published: September 2016

We review some of the recent results obtained on the graphene synthesis on Ge(100)/Si(100) substrates by molecular beam epitaxy and wafer scale chemical vapor deposition. We outline some of the identified challenges in synthesis and present first experimental results on patterning and in-line metrology of graphene in a 200 mm wafer pilot line.
In-Plane Biaxial Strain Evaluation Induced in Ge1-X
Sn
x
Films Using Oil-Immersion Raman Spectroscopy
Authors: Takeuchi Kazuma , Suda Kohei , Suzuki Ryota , Yokogawa Ryo , Sawamoto Naomi , Usuda Koji , Ogura Atsushi
Published: September 2016

We performed evaluation of anisotropic strain relaxation in the patterned Ge1-x
Sn
x
mesa by Raman spectroscopy. For strain evaluation, several coefficients, e.g., strain shift coefficient b and phonon deformation potentials (PDPs: p and q), are indispensable. In this study, using thin Ge1-x
Sn
x
films which were epitaxially grown on Ge substrate by MOCVD, the b coefficient and PDPs were derived. From results of Raman spectroscopy and XRD, the b coefficient was -399.3±5.6 cm-1. And, the p and q show only small variation in the Sn concentration range less than 3.2%. These derived coefficients were used to evaluate the biaxial strain in the patterned Ge1-x
Sn
x
mesa by oil-immersion Raman spectroscopy. As a result, we confirmed uniaxial strain relaxation in the Ge1-x
Sn
x
stripe pattern.
Epitaxial Growth of Ge Strain Relaxed Buffer on Si with Low Threading Dislocation Density
Authors: Abedin Ahmad , Asadollahi Ali , Garidis Konstantinos , Hellström Per-Erik , Ostling Mikael
Published: September 2016

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with enhancement carrier mobility. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.
(Invited) Finely Controlled Heterointerfaces between Ge(111) and Metallic Alloys or Insulators for Next Generation Ge-Based Devices
Authors: Hamaya Kohei , Yamada Shinya , Kasahara Kenji , Kanashima Takeshi
Published: September 2016

Heteroepitaxial growth of bcc metallic alloys or a high-k insulator on Ge(111) has been explored for next generation Ge-based devices. First, we introduce a finely controlled crystal growth technique of bcc-type ferromagnetic alloys on Ge(111). Next, we show that the Fermi level pinning is significantly suppressed at the high-quality bcc-alloys/Ge heterointerfaces. Using these kinds of structures, we can achieve spin injection and detection in n-Ge. Finally, we present a new approach to gate-stack structures for Ge-MOSFET. Even a crystalline high-k insulator can be grown epitaxially on Ge(111) and a high-quality heterointerface can be achieved. Also, reasonable electrical characteristics are obtained. These finely controlled heterointerfaces will open a way for developing new technologies in next generation Ge-based devices with low power consumption.
(Invited) Silicene: Silicon at the Two Dimensional Limit and Its Applications to Nanoelectronics
Authors: Molle Alessandro , Grazianetti Carlo , Cinquanta Eugenio
Published: September 2016

In the realm of two dimensional materials for nanoelectronics, silicene, a honeycomb lattice of silicon atoms, has recently attracted an enormous interest for the semiconductor technology roadmap because of its intrinsic affinity with the silicon technology standards. The synthesis and the processing of silicene are non-trivial because of a number of physical constraints and technical bottlenecks that are here briefly mentioned. Attention is paid to outline technical strategies to easily handle silicene single layer and integrate it into functional devices.
(Invited) The Structure-Dependent Properties of InAs Nanowires and Their Devices
Authors: Fu Mengqi , Shi Tuanwei , Li Xing , Chen Qing
Published: September 2016

InAs nanowires (NWs) have attracted broad research interests due to their high electron mobility, easily forming ohmic contacts, high g-factor and small bandgap. These excellent properties make InAs NWs suitable for a rich variety of applications, such as high-speed electronic devices, quantum devices and optoelectronic devices. Here, we summarize and analyze our recent results on structure–dependent properties of InAs NWs. The structural properties referred in our works include the diameter, the crystal structure and the axis orientation. Both the electrical properties of InAs NWs and the contact properties between InAs NWs and metals are systematically studied.
In-Line Critical Dimension and Sidewall Roughness Metrology Study for Compound Nanostructure Process Control by in-Line 3D Atomic Force Microscope
Authors: Kim Tae-Gon , Ryu Heon-Yul , Jo Ah-jin , Cho Sang-Joon , Park Sang-il , Vandeweyer Tom
Published: September 2016

Metrology solution for critical dimension and sidewall roughness of compound structure in nondestructive manner is an important for better device performance and improving yield. Due to high complexity in SiGe and III-V film stacks with embedded defects a new metrology solution needs to be evaluated. In-line 3D atomic force microscopy was performed to provide a suitable metrology for compound semiconductor process. The technique could measure accurately the height and CD of Fin structures, which has the space with of 25 nm and the height of 60 nm. The uniformity of recess height could be measured, which could be interpreted by loading effect of etch process. Sidewall roughness of InGaAs/InP Fin with various CDs were also measured in success and the technique can differentiate the sidewall roughness changes below 0.1 nm, which were treated at different chemistries and processes. In-line 3D AFM could provide a suitable metrology solution not only for the development of compound semiconductor device, but also its process monitoring.
Evaluation of Dielectric Function of Thermally-grown SiO2 and GeO2 from Energy Loss Signals for XPS Core-line Photoelectrons
Authors: Yamamoto Taishi , Ohta Akio , Ikeda Mitsuhisa , Makihara Katsunori , Miyazaki Seiichi
Published: September 2016

An evaluation methodology of the dielectric functions of insulating films from x-ray photoelectron spectroscopy (XPS) analysis have been studied for accurately determining the energy band structure for materials of interest. Evaluation of dielectric functions of thermally-grown SiO2 and GeO2 have been demonstrated from the combination of measured energy loss signals and the results of Kramers-Kronig transformation of the energy loss signals. In addition, obtained dielectric functions of SiO2 and GeO2 were converted into optical constants and absorption coefficient, and the Eg of SiO2 and GeO2 were determined from a Tauc plot of absorption coefficient.
Development of Interatomic Potential of Group IV Alloy Semiconductors for Lattice Dynamics Simulation
Authors: Tomita Motohiro , Ogura Atsushi , Watanabe Takanobu
Published: September 2016

We have newly developed the interatomic potential of Si, Ge or Ge, Sn mixed systems to reproduce the lattice constant, phonon frequency, and phonon dispersion relations in the bulk pure group IV crystal and group IV alloys by molecular dynamics (MD) simulation. The phonon dispersion relation is derived from the dynamical structure factor which is calculated by the space-time Fourier transform of atomic trajectories in MD simulation. The newly designed potential parameter set reproduces the experimental data of lattice constant and phonon frequency in Si, Ge, Sn, and SiGe. Furthermore, the Sn concentration dependence of the phonon frequency, which are not yet clarified, is calculated with three type assumptions of lattice constant in GeSn alloy. This work enables us to predict the elastic and phonon related properties of bulk group IV alloys.
(Invited) Surface Activated Wafer Bonding; Principle and Current Status
Authors: Takagi Hideki , Kurashima Yuichi , Suga Tadatomo
Published: September 2016

The surface activated bonding (SAB) is a method which achieves strong bonding at room temperature. It is assumed that at the bonding interface prepared by SAB atoms bind to each other by the same interatomic bonds with those in bulk materials, such as covalent bond, metallic bond, etc. SAB well matches the wafer direct bonding, because intimate contact at the bonding interface is spontaneously achieved by the attractive force between very smooth wafer surfaces. In SAB, the surfaces of bonded materials are sputter-etched, in other word “cleaned”, before bonding. Various materials, such as semiconductor wafers, single crystal oxide wafers, metal films on wafers, etc. has been successfully bonded. Recently, other surface treatments have been proposed to apply SAB to wide variety of materials. SAB has been used to fabricate integrated substrates for RF-filters for more than 10 years, and has been already applied in MEMS packaging in industry. Other applications, such as power semiconductors, solar cells, etc. are now extensively developed.
Conductive Semiconductor Interfaces Fabricated by Room Temperature Covalent Wafer Bonding
Authors: Flötgen Christoph , Razek Nasser , Dragoi Viorel , Wimplinger Markus
Published: September 2016

Low temperature direct bonding in the range of maximum 400°C opened an entirely new applications field as it allowed for the direct bonding of wafers with metallization (e.g CMOS) while maintaining a high alignment accuracy as well as bonding of thermally mismatched materials. Despite the clear benefits of the low temperature direct bonding process, the requirements of some categories of applications in terms of allowing for room temperature covalent bonding or oxide-free, electrically conductive interfaces fabrication cannot be fulfilled. A new technology was developed to address these types of applications: EVG®580 Combond®. This paper reports on fabrication of oxide-free, electrically conductive Si-Si and Si-GaAs bonded interfaces based on the newly developed technology. Experimental results on bonding quality and electrical performance of the bonded interfaces are presented.
Cu-Cu Die to Die Surface Activated Bonding in Atmospheric Environment Using Ar and Ar/N2 Plasma
Authors: Chua Shen Lin , Tan Chuan Seng
Published: September 2016

Surface activated bonding (SAB) method is an attractive option for Cu-Cu bonding as the force application duration is considerably shorter as compared to thermocompression bonding. Die to die SAB allows 3D heterogeneous integration to be done with lesser energy consumption compared to thermocompression. In this report, blanket and patterned Cu-Cu die to die SAB are demonstrated. Two different types of plasma were used for the surface activation of Cu. Both Ar and Ar/N2 plasma activation were performed on the Cu surfaces enabling direct bonding at room temperature, ambient air, and atmospheric pressure without any wet chemical process.
Control of Direct Bonding Behavior by Interlayers
Authors: Eichler Marko , Dillmann Helena , Nagel Krees , Klages Claus-Peter
Published: September 2016

Atmospheric pressure plasma treatments were used to control free surface energy of different areas on silicon wafers before bonding. Surface energy measurements in situ during annealing for this different areas are presented for SF6 etching as well as acetylene, glycidyl methacrylate, tetramethylsilane and C4F8 and coatings. The bonding energy can be permanently reduced by appropriate coatings or surface roughness. The results revel important aspects for the choice of precursors and parameters to obtain high contrast between the treated and untreated areas.
Determination of Band Structure at GaAs/4H-SiC Heterojunctions
Authors: Liang Jianbo , Shimizu Sae , Arai Manabu , Shigekawa Naoteru
Published: September 2016

The effects of thermal annealing process on the interface in p+-GaAs/n-SiC heterojunctions fabricated by using surface-activated bonding (SAB) were investigated. It was found by measuring their current-voltage (I-V) characteristics that the reverse-bias current and the ideality factor were extracted to be 7.57 ´ 10-7 A/cm2 and 1.33, respectively, for the junctions annealed at 400 °C. The flat-band voltage obtained from capacitance-voltage (C-V) measurements was found to be 1.29 eV, which is almost consistent with the turn-on voltage extracted from I-V characteristics. These results suggest that the SAB-based GaAs/SiC heterojunctions are applicable for fabricating high-frequency power devices.
Surface Preparation and Eutectic Wafer Bonding
Authors: Heller Martin , Zoberbier Margarete , Fujita Toma , Eichler Marko
Published: September 2016

Bond surface preparation is an integral part of all eutectic wafer bond processes currently used in high volume production. It is not unusual to have a requirement conflict between the bond surfaces and the device itself, especially in case of MEMS inertial sensors. A typical example of the issue at hand is the need of an anti-stiction coating material for the device and the interference of the material with the eutectic bond process. This paper reports on the novel usage of localized plasma in conjunction with an improved permanent wafer bonder to reconcile the conflicting needs in case of eutectic Aluminum-Germanium wafer bonding.
Glass Frit Wafer Bonding - Sealed Cavity Pressure in Relation to Bonding Process Parameters
Authors: Knechtel Roy , Dempwolf Sophia , Klingner Holger
Published: September 2016

Glass frit wafer bonding remains a very attractive process for industrial applications. The main benefit is that the glass frit is an active bonding layer, which planarizes surface roughness and topography up to the direct sealing of metal lines at the bonding interface. This allows very simple process integration. The bonding yield and bonding strength are high, while the bonding interface is reliable regarding mechanical degradation and hermeticity. The processing costs for screen printing, thermal conditioning (firing) of the printed glass paste to a solid glass are moderate, but no extra costs arise from any specially-required preparations of the electrical connecting metallization (no passivation or planarization is needed). In this publication detailed investigations and optimizations of bond process parameters regarding stable and low inner pressure of cavities sealed by glass fit bonding, considering the mechanical bonding strength and bonding behavior, are described.
Low Temperature Thermo Compression Bonding with Printed Intermediate Bonding Layers
Authors: Wiemer Maik , Roscher Frank , Seifert Tobias , Vogel Klaus , Ogashiwa Toshinori , Gessner Thomas
Published: September 2016

The paper describes capabilities of additive material transfer technologies Aerosol Jet Printing (AJP), Stencil Printing (STP) and Screen Printing (SP) based on nano particle inks with the purpose of intermediate bond layer manufacturing for Chip-to-Chip, Chip-to-Wafer and wafer level bonding. For realization of these applications, the deposition process and the related material morphology, the bonding with nano particle based intermediate bonding layer (IBL) as well as the characterization methods are described. AJP was used to deposit silver (Ag) as IBL to bond copper (Cu) and gold (Au) metallized wafers. Stencil printed Au nano particle IBL layers were used to bond Au metallized wafers. The interface between nano particles and substrate were investigated. For bonding result evaluation, bonding frames and occurring bonding interfaces were analyzed using scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDX) and focused ion beam (FIB). Mechanical properties were qualified using compression shear tests and tensile tests.
High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing
Authors: Kurz Florian , Plach Thomas , Süss Jürgen , Wagenleitner Thomas , Zinner Dominik , Rebhan Bernhard , Dragoi Viorel
Published: September 2016

The development of low temperature direct wafer bonding processes paved the way for new categories of applications based on semiconductor devices. Precise optical alignment of wafers prior wafer bonding plays a key role in manufacturing of current and future applications based on wafers stacking. In order to address the continuous feature size shrinking and increasing integration levels the need for high alignment accuracy imposed significant hardware and process improvements. The future microelectronics applications are foreseen to require wafer-to-wafer alignment accuracy as low as ±100 nm and better. This work reviews the main contributors to the misalignment budget and presents experimental alignment results for alignment accuracy in the range of 50 – 100 nm.
Bonding of SiO2 and SiO2 at Room Temperature Using Si Ultrathin Film
Authors: Utsumi Jun , Ide Kensuke , Ichiyanagi Yuko
Published: September 2016

The bonding of metal electrode and insulator hybrid interfaces is very important in three-dimensional integration technology. Surface activated bonding (SAB) is expected to be suitable method for three-dimensional integration technology, as the bonding method is carried out at room or low temperatures. Though metal materials such as Cu or Al is easy to directly bond by the SAB method, insulator materials such as SiO2 or SiN are difficult to directly bond. We have already reported on the bonding technique at room temperature using only Si ultrathin films for insulator materials, and we have shown that high bonding strength is achieved. In this report, we investigated the relationship between the SiO2/SiO2 bonding strength and the thickness of Si ultrathin film. We confirmed that the surface energy was about 1 J/m2 for the Si film’s thickness of more than about 3nm.
Heterostructure Source-Gated Transistors: Challenges in Design and Fabrication
Authors: Sporea Radu Alexandru , Jayawardena K. D. G. Imalka , Constantinou Marios , Ritchie Munroe , Brewin Alistair , Wright William , Silva S. Ravi P.
Published: September 2016

Source-gated transistors (SGTs) are usually made with a Schottky source contact which acts as the current-control mechanism. We propose an alternative method, using an ohmic source contact and a bulk barrier. Here, we realize the bulk barrier at the source with a tri-layer C70/C60/C70 heterostructure, which should lead to improved dynamic range and reduced temperature dependence of drain current, as well as the usual energy and gain characteristics of SGTs. Measurements correlate well with Silvaco Atlas simulations and show: low hysteresis, indicating good quality interfaces; a large threshold shift due to the bulk barrier and residual charge in the heterostructure; and FET-like saturation, due to the interplay between semiconductor mobility and barrier height. We discuss the benefits of such structures, and also the fabrication and design challenges associated with this type of transistor (chemistry and materials, barrier realization, interface properties, and requirements on charge carrier mobility).
(Invited) A New Materials Concept for High Performance Organic Thin Film Transistors
Authors: Iino Hiroaki , Kunii Masafumi , Hanna Jun-ichi
Published: September 2016

We have established a new materials concept for organic field effect transistors (OFETs) solution-processed, i.e., utilization of highly ordered smectic liquid crystals, which exhibit self-organization and solid-like nature, in order to solve the problems such as film uniformity and thermal durability in small molecule OFET materials. 2-Phenyl-7-decyl-benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) exhibiting SmE phase was designed and synthesized to apply OFETs. Bottom-gate and bottom-contact OFETs fabricated with its polycrystalline thin films exhibited high mobility of over 10cm2/Vs with its small variation from device to device and high thermal durability up to 200oC . In addition, we succeeded in operating the OFETs at a few volt with a low-dielectric gate insulator material of SiO2.
Controllably Aligned Ultra-Flexible and High-Performance Organic Single-Crystal Arrays Via Solvent Vapor Annealing for Large Area Soft Electronics
Authors: Kang Jingu , Kim Jaehyun , Jo Jeong-Wan , Kim Myung-Gil , Kim Jaekyun , Park Sung Kyu
Published: September 2016

We used deep ultraviolet (DUV) irradiation onto polymeric sacrificial layer of PMMA for micro-rod single crystallization of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) with the controlled location and orientation in the subsequent process of solvent vapor annealing (SVA) process. We fabricated ultra-flexible organic single crystal transistors, showing mechanical flexibility with bending radius of 150μm on optical fiber. After the bending test, the devices show reliable performance without significant degradation from its initial characteristics.
Investigation of High Current Tetracene-TFT Using Surface Nitrided SiO2 Gate Insulator Film
Authors: Nakao Hiroki , Hori Kabuto , Iwazaki Yoshitaka , Ueno Tomo
Published: September 2016

The use of surface nitrided SiO2 film as gate insulator of tetracene-TFT (Thin Film Transistor) has been proposed. Using Ar/N2 mixture gas plasma, the nitridation has been carried out on the SiO2 surface to remove charge-trapping sites due to hydroxyl groups. As a result, transistor output characteristics have been drastically improved with extremely high current level using tetracene film as organic semiconductor material. Also, to clarify the difference of the property of tetracene/SiO2 interface of each sample, C-V measurement has been carried out. After the nitridation have been done on the SiO2 surface that had been etched with dil-HF to make hydroxyl groups, the width of C-V hysteresis is decreased. Therefore we can conclude the surface nitridation of SiO2 films with Ar/N2 plasma are effective method to remove charge-trapping sites related to hydroxyl groups and improve transistor output characteristics.
Low-Temperature Formation of Sn-Doped Ge on Insulating Substrates by Metal-Induced Crystallization
Authors: Sakai Takatsugu , Matsumura Ryo , Sadoh Taizoh , Miyao Masanobu
Published: September 2016

Low-temperature formation of Sn-doped Ge on insulator is desired to realize next generation flexible electronics. To achieve this, metal-induced crystallization (MIC) of a-GeSn layers on insulating substrates is investigated using Au as a catalyst metal. For a-GeSn with initial Sn concentration of 5%, Sn-doped Ge is laterally grown around Au patterns at low temperatures (≤250°C). The Sn concentration (0.5-2.0%) in the grown layers can be controlled by the annealing temperature in the range of 150-250°C.