bluuebunny/crossref_metadata_2025 huggingface dataset:
Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates
Authors: Nguyen Phuong , Barraud Sylvain , Cassé Mikael , Pelloux-Prayer Johan , Tabone Claude , Hartmann Jean-Michel , Arvet Christian , Bernier Nicolas , Hutin Louis , Ecarnot Ludovic , Maleville Christophe , Nguyen Bich-Yen , Mazure Carlos , Faynot Oliver , Vinet Maud
Published: September 2016

We present for the first time the successful fabrication of Ω-gate P-type FETs with epitaxial compressively-strained SiGe (Ge=30%) on tensily-strained SOI substrates. The recess down to the strained-Si etch-stop layer in the source/drain (S/D) areas (after spacer etching) followed by a selective epitaxy of in-situ boron-doped Si0.7Ge0.3 raised S/Ds allowed us to offset the performance loss due to tensile strain in short gate length Si0.7Ge0.3/sSi NW devices. The hole mobility improvement resulting from the compressive strain and VTH shift between Si0.7Ge0.3/sSi and Si channel transistors led to an ION current improvement of +100% at LG=15nm compared to SOI, providing a promising path for performant CMOS integration.
300 mm SiGe-On-Insulator Substrates with High Ge Content (70%) Fabricated Using the Smart Cut™ Technology
Authors: Widiez Julie , Veytizou Christelle , Hartmann Jean-Michel , Loup Virginie , Besson Pascal , Baumel Nicolas , Figuet Christophe , Huyet Isabelle , Mazen Frédéric , Schwarzenbach Walter , Tempesta Catherine , Ecarnot Ludovic
Published: September 2016

We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 µm thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the Si0.3Ge0.7 layers. We obtained in the end 57 nm thick, flat Si0.3Ge0.7 layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).
(Invited) SiGe BiCMOS for Optoelectronics
Authors: Knoll Dieter , Lischke Stefan , Awny Ahmed , Zimmermann Lars
Published: September 2016

Silicon-based electronic-photonic integrated circuit (ePIC) technology enables a high degree of integration of optoelectronic subsystems for optical communications. In this paper we give an overview about IHP’s work in ePIC technology development under use of different SiGe BiCMOS baseline processes. Focus is on "Photonic BiCMOS", a new monolithic ePIC technology which combines high-performance BiCMOS technology with high-speed photonic devices for electronic-photonic submodules for next generation communication networks. Main features of this technology are described, including an overview of offered photonic and electronic devices. Examples of demonstrator circuits fabricated in the new technology are also presented. Another approach of merging photonics with electronics is hybrid assembly. In a second part of the paper we will demonstrate the potential of SiGe BiCMOS as the ‘electronics supplier’ for this approach.
A Multimode SiGe BiCMOS 5–6 GHz Front-End IC that Enables 802.11ac Wave 2 and 802.11ax Wireless LAN Front-End Designs
Authors: Huang Chun-Wen Paul , Christainsen Kenny , Allum Justin , Lam Lui , Chen Andrew , Doherty Mark , McPartlin Mike , Vaillancourt Bill
Published: September 2016

A multimode 4.9–5.9 GHz front-end IC (FEIC) is presented, which is based on SiGe BiCMOS and realized in an 2 x 2 x 0.5 mm3 package. With a 5 V supply, the Tx chain features 31 dB gain and meets -40 dB DEVM for 1024 QAM 802.11ax tests up to 19 dBm Pout and -35 dB DEVM for 256 QAM 802.11ac tests up to 20 dBm Pout. The linearity is perfectly linearly scaled with the supply voltage and insensitive to modulation bandwidths and duty cycle. The low linearity mode with DPD can achieve the similar linear power with 40 mA current reduction. The Rx chain features <2.5 dB NF and 15 dB gain with 7 dBm IIP3 and 8 dB bypass attenuation with 25 dBm IIP3. All the unique features simplify the front-end circuit designs of complex 802.11ac and emerging future complex radios standards.
(Invited) Toward GeSn Lasers: Light Amplification and Stimulated Emission in GeSn Waveguides at Room Temperature
Authors: Mathews Jay , Li Zairui , Zhao Yun , Gallagher James , Agha Imad , Menendez Jose , Kouvetakis John
Published: September 2016

Waveguides were fabricated from n-type doped GeSn layers with Sn content in the range 4.4-7.0 % Sn grown on Ge-buffered Si substrates. The waveguides were optically pumped a 976nm continuous wave laser, and their power output was measured as a function of pump power. The output power dependence indicates light amplification through stimulated emission, and that GeSn acts as a gain medium. Under the experimental conditions, the cavity gain did not exceed the lasing threshold, but amplified spontaneous emission was still observed. This demonstration of optical gain at room temperature is an important first step to achieving room temperature lasing in GeSn.
Low Threshold Light Emission from Reverse-Rib n+ Ge Cavity Made by P Diffusion
Authors: Yako M. , Park ChanHyuck , Ahn Donghwan , Ishikawa Yasuhiko , Wada Kazumi
Published: September 2016

Ge laser is expected as a solution for a key issue in electronic-photonic integrations, CMOS compatible on-chip light source. Two important issues remain in Ge laser technologies; the large threshold current (Ith) and the multiple growth of Ge epi-structures to co-integrate Ge devices such as photodetectors, whose pn junction profiles are much different from the Ge lasers. The reported Ith values are larger than those for III-V lasers by two orders of magnitude, and an in-situ heavily n-type doping in Ge prevents to form various pn structures unless the multiple growth with different doping profiles are performed. To solve these issues, the present paper proposes a "reverse-rib" Ge epi-structure in combination with an ex-situ P diffusion for heavily n-type doping, instead of in-situ doping. P-diffused n+-Ge reverse-rib structures first verify a clear threshold behavior of light emission at a low power of optical pumping.
(Invited) SiOxNy Back-End Integration Technologies for Heterogeneously Integrated Si Platform
Authors: Nishi Hidetaka , Tsuchizawa Tai , Kakitsuka Takaaki , Hasebe Koichi , Takeda Koji , Hiraki Tatsuro , Fujii Takuro , Yamamoto Tsuyoshi , Matsuo Shinji
Published: September 2016

Photonic integrated circuits on Si have been attracting much attention and are being intensively investigated. On a Si photonic chip, in addition to the monolithic Si and Ge photonic devices, InP-based active devices can be integrated heterogeneously by utilizing direct-bonding technology. To connect these functional devices, we have proposed back-end photonic wiring using silicon oxynitride (SiO
x
N
y
) -based waveguides. In this paper, we report recent progress in our back-end photonics integration technology. First, back-end SiO
x
waveguide integration with InP-based membrane active devices will be presented. Then, our technology for the low-loss SiO
x
N
y
deposition at low temperature will be presented, which is applied to a SiN waveguide for compact arrayed-waveguide-grating (AWG) filter and Ge integration. These technologies have attributes for future highly integrated photonic circuits on Si.
(Invited) Development of SiGeSn Technique Towards Mid-Infrared Devices in Silicon Photonics
Authors: Du Wei , Al-Kabi S. , Ghetmiri Seyed , Tran Huong , Pham Thach , Alharthi Bader , Mosleh Aboozar , Margetis Joe , Tolle John , Naseem Hameed A , Mortazavi Mansour , Sun Greg , Soref Richard , Li B , Yu Shui-Qing
Published: September 2016

SiGeSn techniques are of great interest in the area of Si photonics mainly due to the compatibility with current Si complementary metal-oxide semiconductor (CMOS) process and the tunable bandgap allowing the optoelectronic devices operation features broad wavelength coverage in near- and mid-infrared ranges. Moreover, the independent engineering of bandgap energy and lattice constant enables the design of SiGeSn-based device to be more flexible. In this work, the following aspects regarding the SiGeSn techniques are investigated: 1) low-defect material growth technique via Chemical Vapor Deposition (CVD) system; 2) advanced material and optical characterizations of SiGeSn alloys; 3) demonstration of SiGeSn-based photoconductors.
Mid-Infrared Intersubband Absorption from p-Ge Quantum Wells Grown on Si Substrates
Authors: Gallacher Kevin , Ballabio Andrea , Millar Ross , Frigerio Jacopo , Bashir Aneeqa , MacLaren Ian , Isella Giovanni , Ortolani Michele , Paul Douglas J
Published: September 2016

Mid-infrared intersubband absorption from p-Ge quantum wells with Si0.5Ge0.5 barriers grown on a relaxed Si0.2Ge0.8 buffer on a Si substrate is demonstrated from 6 to 9 μm wavelength at room temperature and can be tuned by adjusting the quantum well thickness. Fourier transform infra-red transmission demonstrate clear absorption peaks corresponding to intersubband transitions among confined hole states. The work indicates an approach that will allow quantum well intersubband photodetectors to be realized on Si substrates in the important atmospheric transmission window of 8-13 μm where many chemical and biological molecules have unique molecular absorption lines for spectroscopic identification.
Si-Based Ge and GeSn Material Epitaxy and Thermal Stability Characterization
Authors: Xue Chunlai , Zhang Xu , Cong Hui , Cheng Buwen , Wang Qiming
Published: September 2016

Ge 、GeSn and GeSn/Ge MQW have been grown on Si, Ge/Si and Ge. The crystallinity and growth quality of the Ge and GeSn films were investigated through material characterization methods including x-ray diffraction, scanning electron microscopy, energy-dispersive x-ray spectroscopy, and transmission electron microscopy. The effect of rapid thermal annealing on the conversion of metastable elastically strained GeSn layers into a plastically relaxed state is also examined.
A Benchmark of Germane and Digermane for the Low Temperature Growth of Intrinsic and Heavily in-situ Boron-Doped SiGe
Authors: Hartmann Jean-Michel , Aubin Joris , Barnes Jean-Paul
Published: September 2016

We have benchmarked germane and digermane for the low temperature growth of SiGe and SiGe:B (with disilane as the Si gaseous precursor). At 500°C, 20 Torr, the SiGe growth rate increased linearly with the Ge flow. It was 8 to 10 times higher with Ge2H6 than with GeH4, however. Ge atoms were otherwise 4 times more likely to incorporate in SiGe films with Ge2H6 than with GeH4. The use of GeH4 led to an exponential increase of the 20 Torr SiGe growth rate with temperature (42 kcal. mol.-1 activation energy), together with a slight linear decrease of x. The situation was different with Ge2H6. As T increased, we had a slight exponential increase of the SiGe growth rate (Ea = 15 kcal. mol.-1) and a huge linear decrease of the Ge content. Adding HCl to Si2H6 + Ge2H6 otherwise led at 500 °C, 20 Torr to a significant decrease of the growth rate, together with a significant Ge concentration increase. Finally, we have investigated the 500°C, 20 Torr growth of SiGe:B layers (with a Si2H6 + Ge2H6 + B2H6 chemistry). A marked increase of the SiGe:B growth rate with the B2H6 flow was observed, together with a less than linear decrease of the Ge concentration. The lowest resistivity, e.g. 4.3x10-4 Ω.cm, was obtained for F(B2H6)/F(H2) = 2.5x10-6. For higher B2H6 flows, we had a resistivity re-increase, which was likely due to the crystalline quality degradation then the transformation into poly-SiGe:B evidenced in X-Ray Diffraction.
(Invited) Industrial Applications of Si-Based Epitaxy in Nanoelectronics
Authors: Dutartre Didier
Published: September 2016

Si, SiGe, SiC and Ge heteroepitaxial depositions (epi) on silicon wafers are of great interest as they allow dramatic performance improvements or even new devices fabrication. In this lecture, the various epi techniques will be briefly benchmarked for industrial usage and the characteristics of RTCVD, the most adopted technique, will be detailed. Then, based on the wide variety of epi processes integrated in very different technologies (Imagers, Photonics, Bipolars and CMOS) at STMicroelectronics (Crolles), important epi applications will be presented. This will also allow the main challenges/difficulties of epi to be listed; and some of them, namely the temperature control on product wafers in RTCVD, the thermal budget limitations coming from materials or technologies, and the “small size effects” in epi will detailed. As a conclusion, we will try to summary the recent and future trends in epi process.
Abrupt SiGe and Si Profile Fabrication by Introducing C Delta Layer
Authors: Yamamoto Yuji , Hesse Anne , Zaumseil Peter , Murota Junichi , Tillack Bernd
Published: September 2016

High quality and steep Si / Si0.5Ge0.5 / Si profile is fabricated by　introducing a C delta layer at the interface using reduced pressure chemical vapor deposition system. The Si0.5Ge0.5 and Si layers are deposited by H2-SiH4-GeH4 at 500oC and H2-Si2H6 at 500oC to 575oC, respectively. By introducing a C delta layer at the surface, roughening of the Si0.5Ge0.5 surface is maintained at 575oC due to suppressed surface migration of Si and Ge as well as defect injection into the Si0.5Ge0.5 layer resulting in high crystallinity Si cap layer growth. Adsorbed CH3 species at the surface are preventing the epitaxial Si cap layer growth at 500oC, but it is possible to deposit high quality epitaxial Si at higher temperature because of hydrogen-desorption from adsorbed CH3. Interdiffusion of Si and Ge at the interface is observed at 525oC in the case of sample without C delta layers, but the interdiffusion is suppressed even at 575oC by introducing C delta layers.
(Invited) Selective Epitaxial Growth of High-P Si:P for Source/Drain Formation in Advanced Si nFETs
Authors: Rosseel Erik , Dhayalan Sathish Kumar , Hikavyy Andriy Yakovitch , Loo Roger , Profijt Harald Benjamin , Kohen David , Kubicek Stefan , Chiarella Thomas , Yu Hao , Horiguchi Naoto , Mocuta Dan , Barla Kathy , Thean Aaron , Bartlett Gregory , Margetis Joe , Bhargava Nupur , Tolle John
Published: September 2016

As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers for the Source/Drain formation in Si bulk FinFETs. We report on the macroscopic and microscopic properties of the Si:P layers and discuss the details of the microstructure and the manifestation of Phosphorus-Vacancy complexes at high Phosphorus concentrations. We analyze how a post-epi thermal budget like spike or laser annealing modifies the microstructure and leads to an enhanced P activation and diffusion. We also zoom in on some of the integration aspects of the Si:P layers and discuss the benefit of the high-P concentration for the contact resistivity and the final device performance.
Atmospheric Pressure Selective Epitaxial Growth of Heavily in-situ Phosphorous-Doped Si(:C) Raised Sources and Drains
Authors: Hartmann Jean-Michel , Aubin Joris , Barraud Sylvain , Samson Marie-Pierre
Published: September 2016

We have developed an innovative atmospheric pressure process for the selective co-flow deposition of Si(C):P Raised Sources and Drains (RSDs) at 700 °C – 800 °C. A Si:P growth rate that increased as the PH3 mass-flow increased, together a P+ ions concentration that reached at most 7x1019 cm-3, were associated with Si:P layers grown with SiH2Cl2, HCl and a PH3 1% in H2 bottle (with no dependence whatsoever on growth temperature). Wanting to probe even higher phosphine flows, we have switched over to PH3 5% in H2 bottles and studied at 700°C the growth kinetics and n-type doping of Si. The Si:P growth rate increased, stabilized then decreased (which is most likely due to surface poisoning) as the PH3 mass-flow increased. This was associated with a sharp increase then a stabilization at nearly 1020 cm-3 of the P+ ion concentration. The resulting Si:P layers were single crystalline and slightly rough. Full selectivity versus SiO2 (isolation) and SiN sidewall spacers was achieved on patterned wafers with this heavily chlorinated chemistry. Finally, we have evaluated the feasibility of adding SiCH6 to the gaseous mixture to obtain SiC:P layers. The substitutional C concentration was rather small (at most 0.55%). Meanwhile, the resistivity was at first stable then increased, while the SiC:P growth rate monotonously decreased as the SiCH6 mass-flow went up.
Growth and Etch Forms of Germanium Microcrystals on a Silicon Oxide Substrate
Authors: Huang Yi-Chiau , Cai Man-Ping , Zhou Hongwen , Chung Hua
Published: September 2016

We have studied how the forms of germanium microcrystals evolve during thermal growth and etch processes in a reactive gas ambient. Microcrystals of germanium formed by chemical vapor deposition on thermally grown silicon oxide were examined before and after further processing to determine how particular crystal faces developed or receded and how other surface features evolved. The observed behavior is interpreted in terms of orientation-dependent kinetics and surface free energy.
(Invited) Low Resistance Contacts to Nanoscale Semiconductor Devices
Authors: Saraswat Krishna C. , Shine Gautam
Published: September 2016

Low Resistance Contacts to Nanoscale Semiconductor Devices Krishna C. Saraswat and Gautam Shine Department of Electrical Engineering, Stanford University, Stanford, CA, 94305 As device scaling continues, parasitic resistance largely dominated by contact resistance, is beginning to limit the device performance. Specific contact resistivity, ρc, of a metal-semiconductor (M/S) contact is dependent on the Schottky barrier height, ΦB, and the electrically active dopant density N at that interface. In M/S contacts the metal Fermi level is pinned at the charge neutrality level, ECNL due to metal induced gap states (MIGS), resulting in fixed electron and hole Schottky barrier heights. High ΦB and low N results in high ρc, eclipsing the promise of intrinsic performance of scaled devices. To obtain low ρc it is essential to reduce ΦB and increase N. In this paper we review the problem caused by Fermi level pinning and various methods to overcome this problem and thus obtain low contact resistance. These methods include heavy doping to reduce barrier thickness, Fermi level depinning with interfacial layers, dipole formation at the interface, and heterostructures for barrier lowering.
The Effect of H-Implantation Energy on the Annealing Kinetics of Germanium Surface Blistering
Authors: Yang Fan , Zhang Xuan Xiong , Shen Yuming , Ou Yi , Jiao Jiwei , Meng Hua
Published: September 2016

The impact of implantation energy on hydrogen-induced blistering in germanium is investigated. The results demonstrated that the kinetic plots were shifted with the variation of H-implanted energy but also the plots with a break point, which is usually existed in Arrhenius straight-line plot for H-implanted Ge with a low energy or low dose, is changed into an unitary straight-line with increasing H implantation energy. The characterizations of the cross-section transmission electron microscopy (XTEM) indicate that <001> H-platelets parallel to germanium surface play a main role in the subsequent exfoliation. According to the observation of optical microscopy and the analysis of the statistical critical dimension (i.e. broken blisters), we propose that a mode can reasonably explain the critical dimension modification with H-implantation energy even though the same dimension <001> H-platelets is viewed.
Investigation of Disilane-Based SiGe-HBT Layers for Low External Base Resistances
Authors: Mai Andreas , Costina Ioan , Lenke Thomas , Yamamoto Yuji
Published: September 2016

In this work we study different SiGe epitaxial processes for the base realization of a heterojunction bipolar transistor. In particular we investigate the poly SiGe layer of external base contact region. Silane (SiH4) and disilane (Si2H6) based precursors were used for a chemical vapour deposition (CVD) process of the Si/SiGe/Si layer stack. Sheet resistances of the poly SiGe layer as well as the boron doping and germanium distribution before and after different rapid thermal annealing steps were analyzed. We show that for equal doping profiles in the single crystalline region and minor differences in the thickness of the poly SiGe region the use of a disilane based precursor is beneficial for a reduced external base resistance. Sheet resistance measurements a decrease by more than 60% with respect to the standard silane based SiGe layer.
(Invited) Anisotropic Strain Introduction into Si/Ge Hetero Structures
Authors: Sawano Kentarou , Konoshima Shiori , Yamanaka Junji , Arimoto Keisuke , Nakagawa Kiyokazu
Published: September 2016

We show that anisotropic strain can be induced into Si/Ge hetero structures by growing them on selectively ion-implanted substrates. It is found that strain relaxation of SiGe buffer layers takes place through generation of misfit dislocations along one direction, perpendicular to the selectively ion-implanted stripe patterns. As a result, the SiGe buffer layers accommodate anisotropic (uniaxial) strain states, which are highly stable and controllable since the relaxation is based on the plastic deformation by the dislocations. On the strain controlled SiGe buffers, uniaxially strained Si/Ge channels can be grown and are highly applicable to high-mobility complementary metal oxide semiconductor (CMOS) channels.
Hole Effective Mass of Strained Ge1-X
Sn
x
Alloys P-Channel Quantum-Well MOSFETs on (001), (110), and (111) Ge Substrates
Authors: Lan Huang-Siang , Liu C. W.
Published: September 2016

The dependence of effective mass on Sn content, pseudomorphic strain, cap layer thickness, and substrate orientation is theoretically studied for Ge-cap/Ge1-x
Sn
x
/Ge substrate p-channel MOSFETs through six-band k·p method. The Luttinger-like and deformation potential parameters were obtained from the fit of Ge1-x
Sn
x
band structures by the empirical pseudopotential method. The valence band alignment is theoretically determined by the empirical pseudopotential method and the model-solid theory. The high Sn content and thin Ge-cap layer both result the small effective mass at zone center along channel direction of the first subband.
Investigation of the Low Temperature / High Temperature Approach to Produce Si0.5Ge0.5 and Pure Ge Strain Relaxed Buffers
Authors: Hartmann Jean-Michel , Aubin Joris , Bogumilowicz Yann , Delaye Vincent , Papon Anne-Marie
Published: September 2016

We have checked whether or not the Low Temperature / High Temperature approach used for pure Ge growth on Si yielded high quality Si0.5Ge0.5 Strain-Relaxed Buffers (SRBs) that could serve afterwards as templates for thick Ge layers. We had, as soon as the Si0.48Ge0.52 layers grown at 550°C plastically relaxed, a surface roughening which was not recovered by the 850°C growth of Si0.5Ge0.5 (rms roughness: 5 nm). Thickening it with Ge at 750°C and using a Thermal Cycling yielded a slight surface roughness decrease, however (down to 4 nm). The HT Si0.5Ge0.5 and pure Ge layers were slightly tensile strained. This was due to thermal expansion coefficient differences between Si and SiGe (Ge) coming into play during the cooling-down to room temperature. We had otherwise used the Ayers’ theory in order to transform the full widths at half maximum of SiGe and Ge X-Ray Diffraction omega scans into Threading Dislocations Densities. We would then have, for 60° misfit dislocations in our stacks, the following values: 3.5x108 cm-2 in annealed 1.7 µm thick Si0.5Ge0.5 SRBs and 1.6x108 cm-2 in the 1.3 µm thick Ge layers on top. Those values were definitely higher than those in 1.4 µm thick, cyclically annealed pure Ge layers grown directly on Si and in the top part of ~ 6 µm thick Si0.5Ge0.5 linearly graded virtual substrates.
Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges
Authors: Dube Abhishek , Huang Yi-Chiau , Cherian Benjamin , Nafisi Kourosh , Chung Hua , Chu Schubert
Published: September 2016

Silicon Germanium (SiGe) strain relaxed buffers (SRB) are fully relaxed epitaxial layers that serve as templates for subsequent growth of tensile or compressively strained layers that can serve as N and P channels for continued scaling of Si CMOS technology. In the work reported here, we have studied thick graded SRB layers from a holistic perspective which includes SRB growth targeting defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates.
Engineering Large In-Plane Tensile Strains in Ge Microdisks, Microrings and Racetrack Optical Cavities
Authors: Millar Ross , Gallacher Kevin , Frigerio Jacopo , Ballabio Andrea , Bashir Aneeqa , MacLaren Ian , Isella Giovanni , Paul Douglas J
Published: September 2016

Highly strained Ge micro-cavities are demonstrated, with biaxial equivalent tensile strains > 2 % at the top surface, demonstrating photoluminescence up to the detector cut-off of 2.5 µm wavelength. Ge on Si micro-disk, rings, and racetrack structures are investigated, which have been undercut by wet etching techniques. The anisotropy of the wet etch in the Si leads to the realization of novel, partially suspended structures. The strain distributions in the different cavity structures are discussed and compared with regard to the in-plane uniformity, peak strain level, and effect of the strain distribution on the Ge band-structure.
Physics of Metal/Ge Interfaces; Interface Defects and Fermi-Level Depinning
Authors: Nakayama Takashi , Sasaki Shogo , Asayama Yoshihiro
Published: September 2016

Defect distribution and Fermi-level depinning at metal/Ge interfaces are studied based on the first-principles calculations. It is shown that metal induced gap states (MIGS) hybridize with defect electronic states and work to increase interface disorders. In addition, we show that Fermi-level pinning (FLP) is caused not only by MIGS but also by disorder induced gap states (DIGS), while the GeO2 and α-Sn interface layers block the MIGS penetration into Ge layers and break the FLP. The effects of dopant segregation and germanide/silicide metal electrodes on FL depinning are also discussed.
Impact of N2O/NH3/N2 Gas Mixture on the Interface Quality of Germanium MOS Capacitors
Authors: Dushaq Ghada , Rasras Mahmoud , Nayfeh Ammar
Published: September 2016

In this paper, nitration of germanium surface using a mixture of N2O, NH3 and N2 is performed using RF-PECVD reactor. The electrical characteristics of Al/HfO2/GeON/p-Ge capacitors are investigated. Results show that the hysteresis of metal–oxide–semiconductor (MOS) capacitors with nitration-based passivation step is reduced to ~150 mV, compared with ~400mV of the untreated sample. The suppression of hysteresis is attributed to the reduction of electron traps and enhancement of dielectric/Ge interface quality. The improved interface quality of plasma-based nitration of Ge surface is a promising technique for high performance Ge MOSFET fabrication.
Role of High-k Interlayer in ZrO2/High-k/ZrO2 Insulating Multilayer on Electrical Properties for DRAM Capacitor
Authors: Onaya Takashi , Nabatame Toshihide , Sawada Tomomi , Kurishima Kazunori , Sawamoto Naomi , Ohi Akihiko , Chikyow Toyohiro , Ogura Atsushi
Published: September 2016

We studied characteristic of Metal-Insulator-Metal capacitors with ZrO2/high-k/ZrO2 (Z/high-k/Z)-nanolaminate dielectric layers and TiN electrodes. Amorphous Al2O3, (Ta/Nb)Ox (TN) and (Ta/Nb)Ox-Al2O3 (TNA) as high-k interlayer were prepared by atomic layer deposition and post-deposition annealing. The dielectric constant (k) of ZrO2 thin film exhibited about 28 because of tetragonal, orthorhombic and cubic phases. The k value of Z/high-k/Z-nanolaminate dielectric layer is high in order of ZTNZ > ZTNAZ > ZAZ due to the dependence of each k value of Al2O3 (~ 9) and TN (~29). The ZTNAZ layer exhibited lowest leakage current density of 10-8 ~ 10-7 A/cm2 at 0.6 V compared to those of ZAZ and ZTNZ in CET ~ 1.1 nm. We found that the leakage current property of Z/high-k/Z layer is influenced by not only amorphous structure but also band gap width (conduction band offset of ZrO2) of high-k interlayer. We conclude that the TNA material is one of the candidate material as high-k interlayer for future DRAM.
The Improvement of GeO2 Film Characteristics on Ge Substrates Using Ultrathin Hf Metal Deposition Followed by Annealing
Authors: Ueno Tomo , Niida Jun-pei , Yamaguchi Marina , Iwazaki Yoshitaka
Published: September 2016

The relationship between the electrical characteristics and the water absorbency of GeO2, GeO2 with Al-PMA, and GeO2 with Hf-PMA, on Ge substrates has been investigated. For as grown GeO2 films using high oxidation temperature of Ge substrates, the electrical characteristics of GeO2/Ge interface degrade owing to water absorption into the GeO2 film. It is clarified the degradation caused by water absorption into GeO2/Ge system can be suppressed using lower oxidation temperature. In addition, the interfacial deterioration due to absorbed water into GeO2 which is fabricated by high temperature oxidation can be also suppressed using Post Metallization Annealing (PMA) using Al or Hf. After PMA, the hysteresis width is decreased and the amount of water in GeO2 film is also reduced. Moreover, the GeO2 does not dissolve in water after PMA. From these results, it is confirmed that the PMA is a method to enhance water resistance of GeO2 film.
(Invited) The Effect of Germanium/Silicon Interface on Germanium Photonics
Authors: Kim Daeik , Bao Shuyu , Tan Chuan Seng , Nam Ju Hyung , Saraswat K. C. , Nam Donguk
Published: September 2016

Germanium has been an important material in the field of group IV photonics and photonic-integrated circuits because of its superior optical properties over silicon such as high responsivity up to 1550 nm (C-band). Although the material quality of germanium plays an important role in improving the performance of germanium-based photonic devices, it has been a technical challenge to obtain a high-quality germanium layer on silicon due to large lattice mismatch between silicon and germanium. In this paper, we discuss the effect of germanium/silicon interface on germanium-based optical devices. We present a couple of approaches to obtain a high-quality germanium layer on a silicon platform. By using various characterization techniques including transmission electron microscopy, time-resolved photoluminescence and steady-state photoluminescence, we show that the minority carrier lifetime and light emitting efficiency can be significantly improved in our engineered germanium-on-silicon platforms.
Effect of Ge Core Size on Photoluminescence from Si Quantum Dots with Ge Core
Authors: Yamada Kentaro , Kondo Keigo , Makihara Katsunori , Ikeda Mitsuhisa , Ohta Akio , Miyazaki Seiichi
Published: September 2016

Si quantum dots (Si-QDs) with Ge core were self-assembled on thermally grown SiO2 from alternate thermal decomposition of pure SiH4 and GeH4 diluted with H2. When the sample was excited by a 979 nm line of semiconductor laser at room temperature, photoluminescence (PL) spectra peaked at 0.6-0.75 eV were observed. It is interesting noted that, with decreasing the Ge core size, the PL signals were shifted towered the higher energy side reflecting quantum size effect. We also found that surface passivation of selectively-grown Ge on pre-grown Si-QDs by the formation of Si clad, namely formation of core/shell structures, can enhance the light emission from the Ge core.
(Invited) Strain Engineered Crack-Free GaN on Si for Integrated Vertical High Power GaN Devices with Si CMOS
Authors: Dayeh Shadi , Tanaka Atsunori , Choi Woojin , Chen Renjie
Published: September 2016

The ability to grow thin GaN layers on Si substrates has led to the development of lateral high power and high-speed devices such as GaN HEMTs. These devices have already demonstrated promising performance and have been adopted for mass market. But lateral devices require large drain/gate separation to sustain high voltage impairing cost effectiveness. This highlights the need for growth of thick GaN layers to enable vertical high power device architectures and to achieve high performance and attain high breakdown voltages in small chip area. This paper presents a successful growth of over 10μm thick crack-free GaN on Si by engineering the strain induced by thermal mismatch between GaN and Si. We discuss the origin of cracking and introduce a surface strain-relief mechanism in 0.5mm diameter GaN dots to overcome thermal mismatches. The first demonstration of vertical thick GaN Schottky diodes on Si will be presented. To fully exploit these results of GaN power devices on Si, side-by-side integration of GaN and CMOS circuitry elements is necessary. We have assessed and validated the compatibility of the GaN-CMOS process. These advances can pave the way for commercialization of next generation compact and efficient power systems that are composed of monolithically integrated GaN and Si technologies.
(Invited) Realizing 2D Materials Via MOCVD
Authors: Briggs Natalie , Subramanian Shruti , Lin Yu-Chuan , Eichfeld Sarah , Jariwala Bhakti , Bhimanapati Ganesh , Zhang Kehao , Robinson Joshua A
Published: September 2016

This manuscript presents a brief review of previous works related to synthesis of 2D materials via metal-organic chemical vapor deposition. Additionally, synthesis of heterostructures based on tungsten diselenide and epitaxial graphene are discussed.
Surface Activation and Planarization with Gas Cluster Ion Beam for Wafer Bonding
Authors: Toyoda Noriaki , Sasaki Tomoya , Yamada Isao , Suga Tadatomo
Published: September 2016

In this paper, preliminary irradiation effects of glancing incidence gas cluster ion beam (GCIB) for surface activated bonding are reported. Unique irradiation effects of GCIB, such as low-damage irradiation and surface smoothing effects, might be beneficial for surface activated bonding. From XPS analysis, Ar-GCIB irradiation at 70o removed native oxide on Si(100) substrate efficiently. On the contrary, mixing of native oxide by normal incidence GCIB occurred, which caused residual oxide layer formation. The surface roughness at oblique incidence showed lowest value (Ra ~ 0.5 nm) without ripple formations. In addition, Cu-Cu bonding were demonstrated as preliminary results of wafer bonding with GCIB.
Ultra-Thick Metal Ohmic Contact Fabrication Using Surface Activated Bonding
Authors: Liang Jianbo , Furuna Katuya , Matsubara Moeko , Dhamrin Marwan , Nishio Yositaka , Shigekawa Naoteru
Published: September 2016

We successfully bonded aluminum foils to Si substrates to fabricate p-Si/Al, n-Si/Al, p+-Si/Al, and n+-Si/Al junctions by surface activated bonding (SAB). The effects of the annealing temperature process on the electrical properties of the junctions were investigated by measuring their current voltage (I-V) characteristics. It was found that the leakage current of the reverse bias of n-Si/Al junctions was improved and the I-V characteristics of p-Si/Al revealed excellent linearity properties after the junctions annealing at 400°C. The interface resistance of p+-Si/Al, and n+- Si/Al junctions decreased with increasing annealing temperature and decreased to 0.021 and 0.032 Ω·cm2 after the junction annealing at 300 and 400°C, respectively. These results demonstrated that thick metal Ohmic contact in devices could be realized by SAB.
(Invited) Analysis of Defect Levels at GaAs/GaAs Surface-Activated Bonding Interface for Multi-Junction Solar Cells
Authors: Sugiyama Masakazu , Yamashita Daiji , Watanabe Kentaroh , Fujino Masahisa , Suga Tadatomo , Nakano Yoshiaki
Published: September 2016

Quantitative evaluation of crystal defects introduced by fast atom beam (FAB) treatment was developed for surface-activated wafer bonding. The surface of n-GaAs was treated with the FAB using Ne, Ar and Kr, and Au Schottky electrodes were formed on the surfaces. Capacitance of a Schottky diode as a function of both probe frequency and DC bias allowed us to characterize both energy depth of the defects and their density profile along the physical depth from the GaAs surface. The results indicated that atoms with the smaller diameter generate high-density defects to the deeper region from the surface. When the defect density exceeding the doping level of GaAs spreads to wider than 5 nm, significant Schottky characteristics appeared in the interfacial current-voltage characteristics, as suggested by simulations. Such a tendency was semi-quantitatively in good agreement with the measured current-voltage characteristics.
The Roles of Band Bending, Surface Misorientation, and Passivation on Electrical Transport Across III-V Bonded Structures
Authors: Yee Matthew , Liao Michael , Seal Mark , Goorsky Mark S.
Published: September 2016

With results from bonding of several different materials combinations, surface orientations, and passivation treatments, as well as an assessment of barrier heights reported in the literature for transport in polycrystalline III-V materials as well as for other III-V bonded materials combinations, a general model has emerged. Lattice mismatch does not play a major role in limiting conductivity across an interface; however, misalignment (through twist or tilt) produces interfaces with increased resistance. Passivation techniques are most important for these systems which possess significant interface band-bending. The electrical characteristics of a grain boundary, whether in polcrystalline material or at a bonded interface, are determined by the presence of defect states and interfacial charge which create band bending and Fermi level pinning. The barrier heights and widths from zero bias conductance vs bias measurements over a wide range of temperatures and for different materials can be matched to band structure simulations of bonded semiconductor heterojunctions with resultant I-V curves showing good agreement between experiment and theory. Based on this study, which combines experimental results and transport modelling, it is expected that narrow bandgap III-V semiconductors should show lower barrier heights; but more importantly, modelling indicates that high doping at mismatched interfaces helps to significantly reduce the interface barrier height.
(Invited) High Output Power Deep Ultraviolet Light-Emitting Diodes with Hemispherical Lenses Fabricated Using Room Temperature Bonding
Authors: Ichikawa Masatsugu , Endo Shinya , Sagawa Harunobu , Fujioka Akira , Kosugi Takao , Mukai Takashi , Uomoto Miyuki , Shimatsu Takehito
Published: September 2016

We reviewed the structural and optical properties of high output power 255 and 280 nm light-emitting diodes (LEDs) bonded with hemispherical lenses made of inorganic materials. [This is described as a full paper (and not a review). Is this your intended meaning?][This is my intended] The optimal LED structure with a lens to improve the output power for deep ultraviolet LEDs was designed using Monte Carlo simulation. The LED chips were bonded to sapphire lenses at room temperature using either atomic diffusion bonding or surface activated bonding. The bonding of the lenses to the LEDs is experimentally shown to improve the light extraction efficiency, and the light output power of the LEDs with lenses was significantly higher than that of conventional structure LEDs. The output power of a 255 nm LED with a lens was 2.8 times larger than that without a lens, with a maximum external quantum efficiency of 4.56%, and that of the 280 nm LED with a lens was larger by a factor of 2.3.
Necessary Thickness of Au Capping Layers for Room Temperature Bonding of Wafers in Air Using Thin Metal Films with Au Capping Layers
Authors: Uomoto Miyuki , Shimatsu Takehito
Published: September 2016

This study elucidated room temperature bonding of wafers in air using Ag, Al, and Cu films with thin Au capping layers. To avoid oxidation of 20-nm-thick of Ag and Cu films, a 2-nm-thick Au layer was found to be effective. Bonding was achieved in air over the entire area without a loading pressure. However, the necessary thickness of the Au capping layer for 20-nm-thick Al films was 6 nm or more, which is three times thicker than those for Ag and Cu films. The necessary Au layer thickness increased as the thicknesses of Al and Ag layers increased. Moreover, a loading pressure was necessary for bonding using thick films. These results were attributed to increased the surface roughness. However, the necessary Au capping layer thickness for bonding was 1/10 or less of the thickness of Al or Ag layers in the present thickness range of 20–500 nm.
(Invited) Diverse Accessible Heterogeneous Integration (DAHI) Foundry at Northrop Grumman Aerospace Systems (NGAS)
Authors: Gutierrez-Aitken Augusto , Scott Dennis , Sato Ken , Poust Ben , Nakamura Eric , Thai Khanh , Chan Wes , Kaneshiro Eric , Monier Cedric , Smorchkova Ioulia , Lin Nancy , Ferizovic Dino , Zeng Xiang , Oki Aaron , Kagiwada Reynold
Published: September 2016

The performance, size, weight and power requirements for future systems are increasingly demanding. These can be met by intimate integration of lower power and higher performance scaled CMOS and compound semiconductor technologies into smaller areas and volumes. The more adaptable and more intimate is this integration between two or more technologies, the more flexibility is given to the designer for the selection of the technology for a specific function, or even better, for an optimum combination of different transistor technologies in the same function or cell in the design. Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing integration processes, design kits and thermal simulation tools to integrate submicron CMOS, InP HBT, GaN HEMT and high-Q passive technologies for advanced DoD systems. We have demonstrated integration of NGAS’ InP HBT and GaN HEMT technologies on 65nm and 45nm CMOS wafers.
Suppressed Self-Heating in Multi-Finger InP-Based DHBTs with Au Subcollector Fabricated on SiC Substrate by Surface-Activated Bonding
Authors: Shiratori Yuta , Hoshi Takuya , Kashio Norihide , Kurishima Kenji , Higurashi Eiji , Matsuzaki Hideaki
Published: September 2016

InP-based multi-finger double-heterojunction bipolar transistors (DHBTs) with an Au subcollector were fabricated on a highly-thermal-conductive SiC substrate by surface-activated bonding (SAB). The fabricated DHBTs have good electrical properties without any degradation due to the wafer-bonding process. They also show 68% reduction of thermal resistance (R
th) compared with a conventional DHBT on an InP substrate. Reduced R
th enables us to increase current density while maintaining the junction temperature of DHBTs, which boosts their operating speed and enhances their integration density. Therefore, multi-finger DHBTs on a SiC substrate fabricated by SAB is very useful for reducing IC chip size and increasing the operation speed.
Combined Surface Activated Bonding Technique for Hydrophilic SiO2-SiO2 and Cu-Cu Bonding
Authors: He Ran , Fujino Masahisa , Yamauchi Akira , Suga Tadatomo
Published: September 2016

Wafer bonding with high quality (such as high strength, void-less interface, and low-resistance vertical electrical interconnects) obtained at low temperatures is highly desired for 3D integration of microsystems. This paper reports a combined surface activated bonding (SAB) technique for improvement of the bonding quality of SiO2-SiO2 pairs bonded at 200°C. The present bonding technique employs a combination of surface irradiation using a Si-containing Ar beam and prebonding attach-detach procedure prior to bonding in vacuum, followed by postbonding annealing in ambient pressure. The bonding method has also been found effective for SiO2-SiNx and Cu-Cu bonding at 200°C. Results of bonding strength measurements, transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS) observations are reported and discussed to understand the present technique. The feasibility of this bonding technique for Cu/SiO2 and Cu/SiO2/SiNx hybrid bonding is also discussed.
Impact of Water Edge Absorption on Silicon Oxide Direct Bonding Energy
Authors: Fournel Frank , Tedjini Marwan , Larrey Vincent , Rieutord François , Morales Christophe , Bridoux Claudine , Moriceau Hubert
Published: September 2016

Direct bonding energy is one of the key parameter for wafer direct bonding. Since few years the impact of the water stress corrosion on the measurement has been pointed out. It has been also proven that water can diffuse into the direct bonding interface from the sample edges. This study is then based on the impact of the edge water diffusion on the direct bonding energy. A positive and a negative impact will be shown depending if the diffusion occurs before or after the bonding annealing. A mechanism will be proposed to explain these results and will mainly be based on water stress corrosion influence.
Adhesion Energy and Bonding Wave Velocity Measurements
Authors: Larrey Vincent , Mauguen Gaelle , Fournel Frank , Radisson Damien , Rieutord François , Morales Christophe , Bridoux Claudine , Moriceau Hubert
Published: September 2016

Adhesion energy and bonding wave velocity are key parameters that should be controlled in an industrial direct bonding process because it reports what exactly occurs at the time of the bonding. While dynamics of the bonding front has been analytically studied and modelled [1-4], the literature gives not much information about its characterization. This study is then focused on adhesion energy (Ea) and bonding wave velocity (Vo) measurement. After considerations about immediate and stabilized adhesion energy, we will show the dependence between Ea and Vo and we will confirm Rieutord’s model [1] for hydrophilic direct bonding. Roughness dependence, plasma pre-treatment, hydrophobic direct bonding and re-bonding will also be discussed.
A Study of Void Formation in Fluorine Containing Plasma Activated Wafer Bonding
Authors: Wang Chenxi , Liu Yannan , Suga Tadatomo
Published: September 2016

A quantitative evaluation of void formation in the fluorine containing plasma activated wafer bonding is demonstrated. Results shows adding a small amount of carbon tetrafluoride (CF4) into oxygen plasma could effectively mitigate void formation in subsequent annealing process. Moreover, long plasma treatments (e.g. >60 s) may produce more porous surfaces and introduce undetected microdefects. Therefore, a short fluorine containing plasma treatment (e.g. ~10 s) is able to remove organic contaminants with fewer defects and the bonding interfaces are nearly void-free during heating from 200 to 800ºC. A void formation model is proposed to gain insight the mechanism of the fluorine containing plasma activated bonding.
Modified Surface Activated Bonding Using Si Intermediate Layer for Bonding and Debonding of Glass Substrates
Authors: Takeuchi Kai , Fujino Masahisa , Suga Tadatomo
Published: September 2016

This study reports the bonding and debonding technology based on the Surface Activated Bonding method for the handling of the thin glass substrates. The glass substrates are bonded by The Si intermediate layer oh under 10 nm thick. From the XPS analysis, the OH groups are formed in the bonding interface and the Si layer’s surface is oxidized by the reaction with the OH groups and water at high temperature. Additionally the Si intermediate layer remains on the deposited glass surface. AFM observation also shows the smooth debonded surfaces. From these results, the debonding at the bonding interface is confirmed.