bluuebunny/crossref_metadata_2025 huggingface dataset:
28nm Overlay Control Improvement By Wafer Quality Enhancement and Mask Registration Control
Authors: Zu Yanlei , Liu Chang , Zhang Shi-Jian , Wu Qiang
Published: March 2014

It is known that critical dimension (CD), overlay, and defect are the three most crucial factors for Semi-conductor manufacture. Overlay control is especially important for Gate layer. In this paper we will focus on how to control overlay performance. Simulation will be carried out to optimize under-layer films to optimize the alignment signal strength, or the ASML’s unit: wafer quality (WQ). A solid alignment can ensure a good overlay control. Mask registration can also affect overlay performance markedly which is a new learning at 28nm tech node. A simple error distribution from metrology measurement angel will be made to discuss the effect of mask registration to overlay performance. KLA SOV (sources of variation) tool will be used to trace the error sources and analyze how much they each contribute to the total overlay error. Finally, a specification on mask registration error is built based on this analysis. Through these improvements, ITRS referred overlay specification is achieved on ASML immersion scanner. We believe that with high order function turned on, even better overlay performance will be achieved which could meet the manufacturing tolerances for the 28nm technology node.
OPC Model Calibration Accuracy Improvement by Using Mask 3D Model
Authors: Zhang Yingchun , Wang Liang , Cheng Renqiang , Liu Qingwei , Shi Xuelong
Published: March 2014

Low k1 and high NA lithography of critical layers require advanced resolution enhancement techniques for masks on large designs such as scattering bars, complicated mask edge placement and segmentation, etc. When mask feature sizes are comparable to or less than the exposure wavelength, the thin mask model (Kirchhoff) has been proven inadequate. It has been well known that mask 3D effects lead to image contrast loss, feature-dependent best focus, dependence of diffraction efficiency on illumination, etc. Mask transmission obtained with a rigorous solver of Maxwell Equations could catch these effects but running time is too slow and impractical for large chips OPC. HHA (Hybrid Hopkins Abbe) and DDM (Domain Decomposition Method) offer a fast and sufficiently accurate mask 3D OPC model solution. In this paper, we set up mask 3D model using HHA and DDM method for 28nm clear-field critical layers. We compare 3D model experimental results with thin mask 2D Kirchhoff model. The results shows mask 3D OPC model calibration get better model fitting error than 2D OPC model, also the improvement of model calibration results on model verification structures and on real design structures was realized by the use of 3D HHA and DDM models. The comparison result also shows process window data calibration accuracy increased by the mask 3D model.
Defect Investigation of the Develop Process on 28nm Contact Mask
Authors: Shi Irene , Tian Eric , Ren Catherine
Published: March 2014

For 28nm node devices, Photomask feature size has decreased in accordance and been requested strict CD uniformity performance. Considering fan develop mode without distinct develop loading effect would benefit a lot for CD uniformity, it was chosen as baseline process at first. However, one certain defect type occurred on 28nm CT hole mask, and was hard to repair since its deference from normal pattern was limited but its impact would be so sensitive on wafer due to CT mask critical characteristics in high mask error factor (MEF), lower image contrast, or exposure latitude (EL), and reduced common depth of focus (DOF). With defect investigation, we studied puddle develop mode connected with exposure PRC function to achieve acceptable CD uniformity and take advantage of defect free.
Study on Abnormal Intra-Field CD Uniformity in Exposure Scan Direction
Authors: Deng Guogui , Hao Jingan , Cai Bo-Xiu , Xing Bin , Yao Xin , Zhang Qiang , Li Gaorong , Lin Yi-Shih , Wu Qiang , Shi Xuelong
Published: March 2014

Critical dimension uniformity (CDU) of hole layer is becoming more and more crucial alongside with the technology node being driven into 28 nm and beyond, since the critical dimension (CD) variation of 2-dimensional (2D) hole pattern is inherently larger than that of 1D pattern (line/space). As the process window becomes more marginal with the more advanced technology node, EFESE tilt (focus drilling method) is a simple but useful way to enhance depth of focus (DOF) (1-4). Despite the compromises in image contrast and exposure latitude (EL), it’s still worth the trade-off; especially in BEOL photo process where incoming wafer topography eats significantly into focus control window. We report an abnormal up to 6 nm ADI CD trend-down in Y-direction (exposure scan direction) in the strictly repeated via-hole patterns within an about 9 mm x 6 mm chip in base line (BL) photo condition wafer (short as BL wafer). No CD trend-down or trend up in X-direction. This hole layer BL photo condition uses EFESE tilt to improve DOF. This CD trend-down phenomenon is investigated and a model of “effective EFESE tilt” is proposed and verified. Based on the model, we made a further step into the impact of applying EFESE tilt on not only intra- but also inter-field CDU. Through all this analysis, we give an insight of the safety zone for applying EFESE tilt for future reference.
90nm Contact Hole Study with KrF Process
Authors: Wang Lei , Guo Xiaobo , Xu Gang
Published: March 2014

Production feasibility under groundrules smaller than 0.09 um while maintain the cost advantages in KrF exposure tools systems becomes more and more important to all companies including 300mm/200mm FABs. The k1 factor for sub 0.09um with current popular KrF exposure tools will be comprable to 0.028 um at 1.3 NA with 193 nm immersion tools. For line/space patterns, some good results had been achieved. But for contact hole patterns, the patterning is much more challenging. It is the biggest obstacle to transfer all layers patterning from ArF to KrF tools on sub-90nm technology node. In order to improve cotanct holes resoltuion and process window, lots of methods had been proposed in advanced technology. But their manufacturing costs are not satisfied when they are used in 90nm nodes with pure KrF process. In this paper, we will discuss the contact hole patterning with focus tilting technology on 0.82NA KrF scanners. The process window, OPC performance and its issues are discussed. Combine with the line/space pattern results, all layers design rule with KrF process had been pushed to the same level of gerneric ArF process at 90nm nodes.
Studies of the Water-Spot like Defect in 28nm Metal Layer
Authors: Xing Bin , Hao Jingan , Deng Guogui , Zhao Jian , Wu Qiang
Published: March 2014

When the semiconductor technology enters the 28 nm and below, defectivity becomes increasingly difficult to detect and remove. In this paper, we studied one kind of water-spot like defect which was first suspected to originate from the immersion lithography process. After immersion lithography, a step-by-step defect tracing had been performed among several reactive ion etch (RIE) steps and after chemical mechanical planarization (CMP). We found that the relatively long delay time between the wet process after hard mask (HM) etch and organic dielectric layer (ODL) coating process could be one possible origin for this water-spot like defect. Our analysis also showed that the defect can be caused by the bubbles generated during the ODL coating process, whose round shape resembles very much the relatively speaking more familiar water spot defect. Based on the above analysis, we have optimized our coating process to reduce the defect density and our results will be presented
Backside Lithography in 3D Device
Authors: Wang Lei , Hu Rongxing , Guo Xiaobo
Published: March 2014

The requirements for some special devices such as MEMS, image sensors and power devices are increased rapidly. Their structures and fabrication methods are different to normal CMOS devices. At the same time, the wafer thicknesses for these special devices are largely reduced to achieve better energy loss and cooling performance. In order to formulate the complex 3D structures on ultra-thin silicon wafers, pattern technologies with good alignment between front side and backside are needed. How to handle the ultra-thin wafer is also a big challenge. In this paper, we will demostrate how to transfer the layout design to both wafer frontside and backside with a good alignment on ultra-thin wafers. A kind of RC-IGBT device formulation is used as an example. Two approaches are proposed. One is aligned by intrared light and the other one is aligned by visible light. A method to handle ultra-thin wafers is also discussed.
Sub-Resolution Assist Features Challenge and Solution in 28nm Active Area Lithography
Authors: Shen Manhua , Zu Yan-Lei , Shu Qiang , Wu Qiang , Liu Juan
Published: March 2014

Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in immersion lithography. The selection of SRAF’s size and placement are vital. 28nm node requires stringent CD control for active area (AA) layer. Since both AA line CD and space CD control are important, not only scattering bar (SB) but also reverse scattering bar (RSB) is used to improve AA litho process window. SB is used to improve line pattern process window, meanwhile RSB is implemented to improve space pattern process window as space CD shrinks as small as possible to meet design rule requirement. The main challenges of SRAFs are the proper SRAF size, right SRAFs placement, and avoiding SRAFs printing issue. SRAF size needs to balance process window and SRAF printing issue. Further more, mask making feasibility is also considered. 28nm AA lithography SRAFs rule simulation study with FDTD is used to optimize the AA litho process. 28nm AA test vehicle with SB and RSB size split and location split is designed to determine the integrated SRAFs solution. After implement thorough considered SRAFs rule, 28nm AA litho through pitch line and through pitch space process window can meet manufacturing specification.
(Invited) The Novel Spin-on Hard Mask and Ultra Thin UL Material for EUVL
Authors: Sakamoto Rikimaru , Yaguchi Hiroaki , Shigaki Syuhei , Sassa Suguru , Fujitani Noriaki , Endo Takafumi , Onishi Ryuji , Ho Bang Ching
Published: March 2014

For below Hp22nm generation, Hard-mask strategy is one of the key issues to achieve the good balance for Lithography and Etching performance. The thickness of resist should be thicker enough to obtain the etching margin for the substrate etching. However, the thickness of photo resist (PR) needs to be thinner to obtain the good pattern collapse margin and resolution. In order to solve this tread-off, the spin-on hard mask (HM) technology can be applied. On the other hand, the ultra thin organic Underlayer (UL) being combined with the CVD-HM film stack is also one of the processes for EUV lithography. In order to avoid the film loss of resist during UL open, the thickness of UL must be thinner and the etch rate need to be faster. We studied the effect of UL design and thickness for the EUV lithography performance. For EUV lithography, the electron generation effect from UL is one of the key factors to improve the patterning performance of resist. In this paper, we studied the suitable functional group for the Silicon containing HM(Si-HM) for multilayer process and Org.-UL, which has high potential to generate 2nd electron and enhance the resist performance, and discuss the material design and performance.
(Invited) Optical Lithography Extension Technique with Multiple-Patterning Process
Authors: Yaegashi Hidetami , Oyama Kenichi , Hara Arisa , Natori Sakurako , Yamauchi Shohei , Yamato Masatoshi
Published: March 2014

The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP)[1], we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER,we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.
Comparing the Advantage and Disadvantage Between OMOG and PSM Masks for 20nm Node
Authors: Yue Liwan , Hao Jingan , Wu Qiang , Zhou Junqing , Xing Bin , Li Gaorong
Published: March 2014

As 193 nm immersion lithography moves toward sub 20 nm half pitch, a new type of mask known as opaque MoSi on glass (OMOG) has been introduced to overcome the shortcomings of the well-established phase shift mask (PSM). The OMOG gives smaller Mask Enhanced Error Factor (MEEF), better Mask CDU and registration but it also suffers some problems such as poor Line Width Roughness (LWR), lower image contrast. In this paper, we gave a series of experiments to compare the OMOG mask with PSM mask. We checked the thru pitch FEM result for both types of mask. And we have tried some methods to improve contrast and process window. The results showed very promising. The disadvantages for OMOG mask would cause some serious problems. PSM mask can give better LWR and 2D pattern profile but is also suffered higher MEEF and CD control issue.
Investigation of a Promising Chemical for BEOL Ultra Low K Cleaning of 28nm Node and Beyond
Authors: Hu Chunzhou , Yuan Zhugen , Liu Huanxin , He Yonggen , Song Xinghua , Chen LinLin , Wu Jingang
Published: March 2014

In this paper, novel cleaning chemical for BEOL dual damascene cleaning was evaluated. The cleaning performance mainly focus on electrical property of Cu interconnect and physical impact on dual damascene structure such as Cu erosion and TiN pullback profile. It’s found Cu erosion is well controlled by Cu inhibitor in the chemical, while TiN pullback amount can be controlled by H2O2 ratio, process time. The DIW rinse hard removability of the Cu-inhibitor and its impact on device reliability also discussed in this paper. This drawback can be fixed by low temperature anneal to decompose the Cu and inhibitor complex.
Aluminum Gap Fill Challenge and Evolution for Metal Gate
Authors: Wu Guilong , Luo Liechao , He Weiye , Zhang Lei , Kang Jian , Zhao Ganming
Published: March 2014

High-κ metal gates have become the new paradigm in volume production of high-performance logic devices since the 45nm node. At the same time, aluminum is used for gap fill in the metal gate trench. As the technology node shrinks from 32/28nm to less than 20nm, the gate CD (critical dimension) has become smaller and aluminum gap fill has become the big process integration challenge. This paper addresses the aluminum gap fill challenge and extendibility solutions.
Siconi Process Applications Study for 28nm Technology Node and Beyond
Authors: Tong Hao , Zhang Bin , Deng Hao , Yan Yan , Guo Shi Bi , Zhao Jie , Pan Zhou Jun , Chen Zheng Ling , Xiao Li Hong , Tan Jin Jin , Xiang Yang Hui , Zhang Beichao
Published: March 2014

This work presents some Siconi process applications in 28nm technology node and beyond fabrication steps, such as STI/ILD gap-fill trench profile modification, fin or AA oxide recess (adjustment of fin or AA height) and dummy gate ox removal in 20nm planar structure. Morphological results indicate that Siconi process can reduce trench gap-fill challenge in STI/ILD process, and it can achieve perfectly filled trenches, better AA or Fin/STI oxide height control. Morphological and electrical results also indicate that Siconi clean for dummy oxide removal can reduce CESL/HARP loss, which benefits in MG height control and HKMG material residue elimination after metal gate CMP, without EOT penalty.
Novel RF PVD Ti Technology for HAR Structure Applications
Authors: Zhang Lei , Kang Jian , Luo Liechao , Wu Guilong , He Weiye
Published: March 2014

Titanium (Ti) liners have been widely used in ULSI technology to improve contact/via resistance. As devices scale down to 32nm and below, Ti extends its application as a wetting layer for planar metal gate and 3D tri-gate structures. To meet the accompanying challenges, a novel RF/DC PVD chamber was developed, operating with capacitively coupled plasma (CCP) and a DC source to create high metal-ion flux with low energy. The new technology reduces overhang and increases bottom coverage. This paper presents the chamber’s tuning knobs that fulfill different process requirements for contact and metal-gate, thereby widening the process window for effective gap fill.
Synthesis and Characterization of Nano-Structure Tungsten-Doped Vanadium Oxide
Authors: Cai Wenbo , Zhang Kailiang , Miao Yinping , Wang Fang , Han Yemei , Liu Kai , Sun Kuo , Cheng Wenke
Published: March 2014

Nano-structure tungsten-doped vanadium oxide film is prepared by deposition on the Si (400) substrate using DC magnetron sputtering. Tungsten has been doped to improve the crystal structure and electrical properties of vanadium oxide films. The doping level was controlled by adjusting the sputtering time. The influence of tungsten layer thickness on the structure and properties of the doped films were investigated. To further improve the structure and properties, annealing was employed to form a nano-structure film. The morphology and crystalline structure of prepared films were characterized by AFM and XRD, respectively. Influence of the tungsten dopant on the transmittance was investigated.
Extending Dry Pump Reliability on High-k ALD Furnaces
Authors: Boger Maiku , Nishimura Katsumi , Ito Kazuki
Published: March 2014

High-k dielectric films deposited using ALD are prevalent in the industry today. At the introduction into high volume manufacturing, pump reliability became a key concern. Investigation of the exchanged pumps and analysis of the problem allowed for better understanding of the likely failure mechanisms. Changing the pump mechanism from that used in the original pumps resulted in extending the service interval four to six times that originally experienced. More than temperature changes or purge adjustments, fundamental changes to the pump structure enabled positive results.
Flowable CVD Process Application for Gap Fill at Advanced Technology
Authors: Yan Yan , Zhang Bin , Deng Hao , Chen Liang , Xiao Lihong , Zhang BeiChao , Chen Yingjie
Published: March 2014

In this work, we report the application of flowable chemical vapor deposition (FCVD) technology in sub-20nm devices and flash devices. FCVD displays a strong ability in filling the gap of not only high aspect ratio straight vertical trench, but also re-entrant narrow profile as well as small horizontal trench. Through optimizing the annealing conditions, the as-obtained FCVD film can fully satisfy both the STI and ILD requirements which have different thermal budget. The FCVD oxide film also shows a better WET resistance than HARP film does.
Surface Smoothing Effect of an Amorphous Thin Film Deposited by Chemical Vapor Deposition or Atomic Layer Deposition
Authors: Lau Wai Shing , Zhang Jian , Wan Xia , Wong Hei , Luo Jack K , Xu Yang
Published: March 2014

Previously, one of the authors pointed out that the deposition of an amorphous thin film by chemical vapor deposition (CVD) or atomic layer deposition (ALD) or plasma-enhanced ALD on a substrate with nano-sized roughness probably has a surface smoothing effect. In this paper, experimental data based on atomic force microscopy (AFM) will be provided to support this claim.
Effect of Embedded Graphene on Al/VOx/Cu Resistive Switching Performance
Authors: Lu Hechao , Sun Kuo , Zhang Kailiang , Wang Fang , Miao Yinping , Wang Baolin
Published: March 2014

In this report, we investigated effect of embedded graphene based on VOx-RRAM. Two structures of Al/VOx/Cu, Al/graphene/VOx/Cu (G-VOx) in the same sample were fabricated to compare the effect. Then a slice of graphene was transfered to the surface of VOx/Cu. Al electrode was deposited on VOx and graphene in the same sample to form the two structures. The graphene was grown on the Cu foil by plasma enhanced chemical vapor deposition (PECVD). Surface morphology of the graphene was observed using scanning electron microscope (SEM) and Atomic Force Microscopy (AFM). Raman spectroscopy revealed the single crystals graphene to be uniform monolayers with a low D-band intensity. It shows that method can obtain high quality graphene. Finally, we found that the uniformity of G-VOx RRAM device was improved with embedded graphene compared with VOx RRAM device.
Electrical and Optical Characterization of Boron-doped Microcrystalline SiH Films Prepared by ECR-CVD for Solar Cell
Authors: Hsieh Yu Lin , Li Tomi T. , Hu Li Cheng , Chu Yen Ho , Lee Chien Chien , Chang Jenq Yang , Chen I Chen , Lee Ju Yi , Wang Shih Hung
Published: March 2014

In this study, boron doped p-type hydrogenated silicon films were prepared by Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) at lower temperature (＜200℃) for solar cell. In order to analyze the optical and electrical property of the film, the film’s absorption coefficient and imaginary part of the pseudo-dielectric function 〈ε2〉 as well as resistivity and dopant concentration were obtained by spectroscopic ellipsometry (SE) and Hall measurement respectively. The Optical Emission Spectroscopy (OES) is used as a diagnostic tool for analyzing the plasma spectra, and we try to find out the correlation between plasma spectra and film properties. Based on the above results, we can build up the database from plasma spectra corresponding to film properties, and the processing time required for optimization of process can be reduced significantly. In addition, it was found that the applications of these results can be used for the phase transition in the boron doped hydrogenated silicon film from amorphous to microcrystalline structure.
New CMP Pad Conditioners with Increased Number of Diamond Tips for Longer Dressing Life
Authors: Yang Zongqing , Sung Michael
Published: March 2014

With the relentless progression of Moore's Law toward sub-virus sized (e.g. 28 nm) node of interconnected circuitry (IC), and also the planned debut of 450 mm wafers for 2015, CMP reaches a bottleneck that the polishing of the delicate IC wafers must be achieved by effective deglazing of pad with the extended life of dressers (diamond disks). The conventional diamond disks are made by bonding individual diamond grits by either brazing or electroplating. Brazing can allow higher protrusion of diamond tips that facilitate the deglazing process, but the tips leveling cannot be controlled due to the melting of the braze powder at high temperature (e.g. 1000 C). On the other hand, electroplating may improve the leveling of diamond tips, but the protrusion is limited (e.g. 50 microns) so the deglazing of metal layers cannot be achieved efficiently. Moreover, all pad conditioners today used an array of diamond grid that was invented by Dr. James Sung back in 1997. Due to the alignment of the diamond tips, the pad dressing may not be uniform so the wafer polishing could not be uniform. Worse still, deep penetrating diamond tips may be chipped and cause scratches on expensive IC wafers. Here we introduce the world's first diamond disks that are brazed with amorphous alloy without using powder and binder. Amorphous alloy can allow uniform melting across the diamond disk surface and also avoid the presence of residue carbon from charring of binder. Additionally, we use concentric rings of diamond placement that avoids stress concentration on certain diamond tips. Due to the improved process design, we have demonstrated a significant increase of working diamond tips from conventional number of a few hundreds to over one thousand. This can be seen by indenting diamond disks on colored films spread on a flat platform. Our diamond disks have been tested on CMP process with high removal rate of IC wafers and we expect that the life time may be at least twice of conventional diamond disks. This can allow the dressing of large pad such as that for polishing future 450 mm IC wafers.
Statistical Analysis Methodology for STI CES333 Unstable Process Window
Authors: Gao Fang , Xu Ying , Zhao Runtao Tao , Zhao Ganming
Published: March 2014

STI CMP is a widely used and basic process in current VLSI FEOL manufacturing of both logic and memory chips. Highly selective slurry CES333 is standard for the STI CMP soft-landing process stopping on the barrier layer. However, it has been reported and also observed in mass production that the removal rate of CES333 has a tendency to vary from wafer to wafer, especially at the wafer edge. This is an issue in mass production of smaller technology nodes. More stable performance is, however, difficult to achieve owing to the character of the slurry. A creative method of analyzing a vast database was employed to devise a solution and meet CMP requirements.
(Invited) CMP Challenges toward DRAM Device below 20nm Technology
Authors: Oh Kee Joon , Lim Ji Min , Kim Dong Woo , Kim Hyung Hwan , Park Sung Ki
Published: March 2014

Below 30nm DRAM device technology, we currently have been facing so many challenges such as chip size reduction, particle size reduction, cost reduction and process step reduction. As chip size gets smaller and smaller, manufacturing processes would be very difficult due to particles and affecting defects. Relating to these, some aspects of the chemical mechanical polishing (CMP) processes we are currently challenging were studied case by case. We approached three kinds of techniques toward below 20nm technology. Scratch reduction techniques were reviewed and extreme edge control method by new head tool was introduced and finally nano-colloidal slurry was successfully evaluated for next devices. We would like to emphasize that most important thing is to cooperate with world-wide suppliers and work hand in hand with our chip makers to overcome challenges below 20nm technology.
Solution to W Plug Patc Recess Issue for W CMP Process
Authors: Deng Wu Feng , Chen Feng , Zhao Feng , Wang Dong , Hu Tony , Liu Hao , Cao Junzhu , Liu Hongtao
Published: March 2014

W CMP process plays an important role to form the contact W plug. We had faced a severe issue of W plug recess during W CMP process. In this paper, a solution to above issue will be reported. Firstly, the characteristic and mechanism of W plug recess in W CMP process will be elaborated. Secondly, an improved method to solve the issue will be described. The selection of buffing slurry plays a critical role to find the solution. Next, the impact of W plug recess on the electric performance in the whole integration scheme will be analyzed. In addition, the optimization process with the improved method for other post CMP performance, such as uniformity, oxide loss, W plug protrusion and defectivity etc. will be reported as well. In a summary, a corrosion free W CMP process has been achieved with the improvement in oxide buffing step of W CMP process. The contact resistant performance has been improved and the wafer yield has been significantly increased.
Slurry Delivery Loop Optimization for Micro Scratch Reduction in Cu CMP
Authors: Tan Changxing , Xu Ying , Zhao Runtao
Published: March 2014

The effect of the slurry delivery loop on micro scratch defects in Cu CMP was investigated. Three different kinds of slurry delivery loops were designed. Test results showed that the third slurry delivery loop was the best and reduced micro scratch defects by more than 90%, compared with the first one.
(Invited) Approach to High Efficient CMP for Power Device Substrates
Authors: Kurokawa Syuhei , Doi Toshiro , Wang Chengwu W. , Sano Yasuhisa , Aida Hideo , Oyama Koki , Takahashi Kunimitsu
Published: March 2014

Power devices play an important role in energy saving and material substrates for power devices such as sapphire, silicon carbide (SiC), gallium nitride (GaN), and diamond are attracting extensive concern. However, because of the high hardness and stable chemical properties of power device substrates, processing is very difficult. Approach to the high-efficiency and high-quality CMP of SiC wafer and a diamond substrate is presented. The experimental results show that MnO2 slurry with strong oxidizer has a great impact on improving the SiC-CMP removal rate. Moreover, a diamond substrate, which is regarded as an ultimate power device substrate, must be also polished efficiently. In our project of efficient diamond planarization process, the surface of a diamond substrate is irradiated by femtosecond (fs) laser to enhance the polishing efficiency. The cross-section image by TEM observation shows that the formation of amorphous site was successfully induced.
Effects of Polishing Parameters on the Evolution of Wafer Patterns during Cu CMP
Authors: Wu Lixiao , Yan Changfeng
Published: March 2014

Chemical mechanical polishing (CMP) has been widely used in IC industry. To specify the proper selectivity ratio for Cu CMP is a very important and difficult task. In this paper, the effects of selectivity ratio on the evolution of different wafer patterns during Cu CMP are discussed. The wafer patterns contain square-wave features with different pitches and different pattern densities. Based on the linear system model, the evolutions of the wafer patterns under different polishing parameters are simulated and are compared with experimental data.
Ultrathin Interfacial Layer (UTIL) Formation and Its Application in HKMG for Advance CMOS Technology
Authors: Yu Guobin , He Yonggen , Liu Hailong , He You Feng , Ni Jinghua , Wu Jingang
Published: March 2014

This paper investigates two kinds of ultra thin interfacial layer (UTIL) include SiO2 and SiON, their formation and application in HKMG for advanced CMOS technology. Compare to SiO2 UTIL, SiON UTIL demonstrates good NMOS EOT uniformity, low gate leakage current, but high defect density. Beside offline characterization, these two kinds of interfacial layer were also investigated their application in semiconductor device wafer for electronic test. It is found that the ultrathin SiON as interfacial layer exhibits a lower Tinv and better leakage performance under same physical thickness as compared to SiO2. However, PMOS device mobility suffers some degradation, which is contributed to N diffusion into the interface between UTIL and substrate, as verified by N SIMS profile. Different N atom concentration and thickness of UTIL SiON and their impact on device performance were also discussed in this paper. In general, UTIL SiON film is a promising candidate interfacial layer for HKMG advanced CMOS technology to meet EOT scaling requirement.
Raw Material Incoming Quality Abnormal Early Detection
Authors: ShangGuan Ao. Yu , Shui Xiao. Feng , Xie Li. Bai , Yu Yan. Ju , Chang Kai. Yuan
Published: March 2014

Raw material quality control is one of the most important subjects for foundry manufacturing process due to advanced technology in sub nano-meter. Therefore, how to effectively detect abnormality in early stage of raw material incoming or even at supplier sites becomes an increasingly challenging topic. Comparing with traditional management concept based on judgment inspections to just confirm if raw material meets customer’s specification requirement, this paper will focus on raw material incoming quality abnormality early detection via method of enhanced management about both supplier manufacturing process abnormality handling method and customer side raw material incoming performance warning limit setting to reduce foundry manufacturing risk.
Stacking Faults and Stress Memorization Technique Study for n-Type MOSFET Performance Improvement in All Last High-k Metal Gate Process Development
Authors: Li Yong , Sun Hao , Ju Jianhua
Published: March 2014

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement; it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed.
Dummy Poly Removal Impact Factors and Improvement in Hkmg Last Process
Authors: Zeng Yi Zhi , Zhao Jie , Gao Han Jie , Awuti Kurban , Song Woei Ji , Yu Shao Feng , Zhang Qin , Lin YiHui , Liu Jialei , Liu HX
Published: March 2014

For 20/16nm HK-last and MG-last process, Dummy poly is removed by Wet process. This paper studies the factors impacting the dummy poly removal process, and presents some models to explain the impacting factors. Implant process is one of main factors influencing dummy poly removal capability because the differences of implant ions and doping amount into dummy poly induce difference of poly removal rate by wet process. We also study poly surface single clean, multiple clean and thermal process. Based on the model, we plan N-type doping poly and P-type doping poly with different ion doping amounts on blank wafer and 20nm structure wafers to evaluate dummy poly removal. We find dummy poly removal rate is different between N-type doping poly and P-type doping poly, and receive different dummy poly removal trend by ion amount on N-type doping poly and P-type doping poly. The model can help to improve dummy poly removal process control.
Horizontal Growth and Electrical-Crosstalk Simulation of CNT Interconnection
Authors: Liu Yuhang , Zhang Kailiang , Wang Fang , Han Yemei , Li Jiawei , Tian Bo
Published: March 2014

The impact of time on the horizontal growth of carbon nanotubes with Fe catalyst is investigated at 600℃ for fabricating interconnects. The carbon nanotubes prepared using Fe catalyst was found to have small diameters, long lengths and high density. Resistivity of the horizontal carbon nanotube interconnect structures were found to be 2.79 Ω•cm. We also studied crosstalk using different lengths of multi-walled carbon nanotubes. Through the analysis of the basic parameters of carbon nanotubes, we establish a distribution model and a three-line structure of parallel multi-walled carbon nanotubes interconnects to analyze the impact of crosstalk between the interconnect line. Simulation was used to study the crosstalk behavior which was found to increase with respect to the length of the multi-walled carbon nanotubes and the crosstalk voltage decreased with the increase in radius. However, the thickness of the oxide layer or medium had little effect on the carbon nanotube interconnects.
(Invited) Flipchip with Au Die Bumps Interconnected to Au Plated Substrate Used for Mobile Processors
Authors: Zhang T L , Zhang W H , Zhou F , Yan X L , Hong S P , Ji L L , Lu H L , Shen H J , Wu S H
Published: March 2014

Recently, TCNCP (Thermal Compression with Non-Conductive Paste) flipchip technology has received much attention because of the demands of flipchip with high bump density for mobile devices and 2.5D/3D applications. TCNCP technology is a relatively new technology that is applied for flipchip with very fine bump pitch. One of the advantages of TCNCP process is that it could ensure IC flatness during local reflow process as IC is under pressure during TCNCP process. Here TCNCP technology is used with Au stud bump for mobile processor. Au stud bumping process is done with sawn IC with standard wire bonder. The Au stud bumps are usually connected to trace on the substrate (Bump on Trace) as there is no space for bump landing pads. Pressure and heat are applied simutaneoursly during thermal compression bonding (TCB) process at temperature of less than 230︒C. The formed Au to Au joint is mechanical contact without interrmetallic formation. Reliability results show that although without intermetallics, the package structure can pass TCT 1000 cycles, HTS 1000 hours and uHAST 192hrs without failures.
The Removal of Compound Residue in Semiconductor Assembly
Authors: Liu Peng , Wu Ping , He Qingchun
Published: March 2014

In the semiconductor assembly, the step cut is always used for the Singulation Saw process of non-lead packages. Due to the compound’s property, there is a compound residue left after the Singulation Saw. The residue is an insulating compound trace and easy to drop on the PCB to cause an electrical open in the customer SMT line. According to the study result, the new saw blade with V shape edge is introduced, which can break through the compound directly and eliminate the opportunity of residue arising in Saw Singulation process.
Influence of Coupling Agent on the Performance of Epoxy Molding Compound
Authors: Liu Hongjie , Tan Wei , Li Lanxia , Qiu Chi , Cheng Xingming , Han Jianglong
Published: March 2014

Coupling agent, which acts as the bridge of epoxy resin and silica filler as well as the adhesion promoter of the Epoxy Molding Compound (EMC) and metal leadfream, is one of the most important ingredients in EMC manufacture. Here, the influences of the incorperation mannner of coupling agent agent, different types and content of coupling agent on the performance of EMC have been screened. Dynamic Mechanical Analyzer (DMA) modulus, impact strength, water absorption and adhesion test on copper, silver and PPF have been introduced to characterize the performance of EMC. Test results showed that for the incorperation manners, 85% coupling agent hydrolysate directly added in the high speed mixing process show hgiher adhesion strength on the silver, when coupling agent is used to pretreat silica, all the pretreated batches show a little lower DMA modulus than that non treated one. For different coupling agent types, normal epoxy group silane show higher adhesion on copper as well as other silanes, special silane A show higher adhesion on silver while special silane B show higher adeshion on PPF, meanwhile composite silane C show lower water absorption. For the content of the coupling agent, when the perportion of the siliane is more than 1%, the impact strength significantly decreased.
PVD Copper Seed Queue Time Extension for 200mm TSV Application
Authors: Li Ming , Chen Xiaojun , Chang Shaohui , Liu Xuanjie , Zhang Haifang , Chen Zheng
Published: March 2014

This work studied queue time between PVD and ECD in a 200mm TSV application. The proposed new PVD condition successfully extended queue time from the original 2-4 hours to at least two weeks. The original PVD condition was found to produce a Cu seed orientation of primarily (200) Cu. This produced a very rough post-plating surface when post-PVD queue time exceeded four hours. The orientation (200) appears to affect gap-fill capability when queue time exceeded four hours. With the new PVD condition, Cu seed orientation was optimized to be primarily (111) Cu, which created a shiny and clear post-plating surface. As a result, the vias could be filled well as long as two weeks after PVD. Copper seed recrystallization and post-plating morphology were found to be sensitive to nitrogen content in the barrier and to the bias power during Cu seed formation.
(Invited) Study on Two Types of Embedded Components in Substrate Technology
Authors: Gunawan Ferlee , Luo Bin , Cai Jian , Kong Lingwen , Ding Kunpeng
Published: March 2014

Nowadays, the Integrated Circuit of electronic products have been getting smaller in size, higher density with more I/Os, more functions, and better electrical performance. In last decade, one of novel packaging technology known as embedded in substrate technology has been researched to keep up with all of these requirements. Recently, there are a lot of technologies have been developed to embed the electronic components into PCB substrate. Base on interconnection method, there are two types of these technologies: embedded in substrate technology with via technique and embedded in substrate technology with via-less technique. These two kinds of technology have a lot of differences which are very unique with each other, such as different manufacturing process, different requirement for alignment precision, different type of component’s I/O’s Pad, which can be alternatively selected depend on the capability of the PCB/substrate manufacturer to satisfy and accomplish the customer’s requirements.
(Invited) Software Development for Evaluation on Bond Pad Layout
Authors: Zhirong Zheng , Kevin Cui
Published: March 2014

The article shows the development method of whole net list of bond pad in integrated circuit design by using the Autolisp & DCL program languages in AutoCAD environment. We can evaluate whether the net list can match the actual bond pad layout for assembly by a kind of new software development based on AutoCAD. The software's arithmetic, operation procedure and development flow are displayed steo by step. The application of software is discussed. The result of such evaluation is validated by a case study.
(Invited) Electromigration Reliability of Lead-Free Solder Interconnects
Authors: Huang M.L.
Published: March 2014

Line-type Cu/Sn/Ni and Cu/Sn/Ni-P interconnects as well as real Ni/Sn3.0Ag0.5Cu/Cu and Ni/Sn3.0Ag0.5Cu/Ni-P flip chip solder joints were comparatively studied to reveal the electromigration reliability of solder joints. The experimental results of the line-type solder interconnects showed that Cu could diffuse to the opposite anode Ni interface and change the interfacial IMC type while Ni could not change IMC type at the opposite anode Cu interface under a current density of 1×104A/cm2 at 150 oC. In real flip chip solder joints, the EM life of Cu (OSP) solder joints was significantly longer than that of Ni-P (ENEPIG) solder joints. A higher Cu content in the solder bumps effectively improved the electromigration resistance of solder joints. This work provides a suggestion for optimizing the structure of flip chip solder joints.
Cleaning PCBs in Electronics: Understanding Today’s Needs
Authors: Duchi Patrick , Laügt Anne-Marie
Published: March 2014

Because of the phase out of CFC’s and HCFC’s, standard solder pastes and fluxes evolved from RA and RMA fluxes, to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product released being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices. Cleaning performance is affected by three main criteria. The first involves the Hansen Parameters which is a characterization of a contaminant to be dissolved and which can be simplified by the solvency power of a product also known as the Kauri Butanol Index. The second is surface tension, expressed in mN/m. The third point, which are physical parameters like temperature, mechanical activities, and the duration of the process to reach medical specifications like ROHS, REACH, ISO etc.
The Technical Problems of Discrete Embedded Technology
Authors: Yao Tengfei , Luo Bin , Gunawan Ferlee , Ding Kunpeng , Peng Qinwei , Kong Lingwen
Published: March 2014

Discrete embedded technology is one of miniaturization technologies, it can save places for 3D structure, which is suitable and supporting for higher density of electrical components in PCB/substrate, and improve the electrical performance by shorten the distance of interconnection between components and reduce parasitic impedance. However there are still some problems need to be solved, for example: the type of embedded components; the design rules; the process technology; the electrical test method and etc. Some key technical problems and solutions have been given in this article for reference.
Wafer Edge Process Integration and Defect Inspection with the Immersion Lithography Process
Authors: Ni Qiliang , Chen Hunglin , Wang Kai , Long Yin , Fang Rongwei
Published: March 2014

The study aims at the wafer edge engineering with defect reduction and the corresponding inline inspection methodology. The BARC (bottom anti-reflective coating) step of the immersion lithography in the front-end-of-the-line (FEOL) process was found that would lead to metal film peeling defects at the very later process in middle-end-of-the-line (MEOL). In this work, the wafer-edge inspection tool was used to scan the BARC profile in the wafer edge, including the front-side, apex and the back-side edges and which presents an effective inline routine monitor for EBR (edge bead removal) control of the BARC. The silicon residues were found after the etch process and caused by the bad edge BARC profile at wafer edge. The intrinsic stress of the Ti/N metal film would lead to the delamination and peel off from the wafer-edge silicon residue with poor adhesion. After cycles of experiments, an innovative bevel etching step with oxygen-based gas was added to tailoring the wafer edge profile after active area (AA) lithography, and the peeling defect dramatically trended down to zero.
Methodology and Application of the Detection of Invisible Defect by Voltage Contrast Inspection
Authors: Fan Rongwei , Chen Hunglin , Long Yin , Ni Qiliang , Wang Kai , Gu Xiaofang
Published: March 2014

The study aimed at the detection of non-visual defects of poly gate CT leakage at dense logic area by voltage-contrast (VC) inspection. At the same time, some new steps after N-type plus (NP) source drain (S/D) implantation of front-end-of-the-line (FEOL) was proposed and compared to detect poly gate CT leakage at the dense logic area. The cause of t`he poly gate CT leakage was the extreme tiny poly footing which was too small to be detected by the optical system. The PG leakage was obviously impacted by poly etch process and the step height between active area (AA) and shallow trench isolation (STI). The poly gate CT leakage defects were solved by inline controlling to reduce the step height between AA and STI and optimizing poly etch process. Furthermore, the application extended the VC inspection from just middle-end-of-the-line to FEOL of semiconductor technology.
Optical Critical Dimension Measurement for AEI Structures at Sub 65 Nm Node
Authors: Huang Yi , Cai Bo-Xiu , Lin Yi-Shih , Zhan Yan-Kun , Wang Xin , Dang Jiang-Tao , Li Hai-Tao , Gao Hai-Jun , Zhang Zhen-Sheng , Shi Yaoming , Xu Yiping
Published: March 2014

In this work, Optical Critical Dimension (OCD) spectroscopy was used to monitor the critical dimension for After-Etch Inspection (AEI) structures at sub 65 nm node, such as Poly Gate, Shallow Trench Isolation, Offset Spacer, and Oxide-Nitride Spacer. The dynamic repeatability of the measurement was obtained through a 10-cycle measurement process with loading and unloading wafers. The long-term stability was examined with more than 3 day’s measurements. The good correlation results between the OCD spectroscopic tool and reference tools, such as, CD Scanning Electron Microscope and Transmission Electron Microscopy, were obtained. The results demonstrated that the OCD spectroscopic tool has advantages of high precision and high stability for 65 nm node and beyond.