High Density Integrated Stack Capacitor (ISC) for Advanced Package Solutions
Authors: Min Max , Jang Kevin J. , Hong Sugmin , Chung JaeYup , Jeong Yoojeong , Park Sunwoo , Kim Jihyung , Lee Juyong 
Published: January 2025

Surface mount device (SMD) type capacitors such as MLCC (multi-layer ceramic capacitor) are normally closely placed to LSI chips to reduce switching noise. However the impedance profile of the conventional discrete decoupling capacitor is narrow due to the equivalent series inductance (ESL) of the capacitor itself. So the decoupling capacitor is no longer effective in higher frequencies over the self-series-resonant-frequency. Furthermore conventional ceramic capacitor cannot be attached closely to BGA type packages without sacrificing impedance profile due to its large dimension. In order to improve the impedance profile of the power distribution network, many papers have been published in respect to high performance capacitor, both in discrete and embedded capacitor of silicon-substrate package.

This paper reports on implementation of high density silicon capacitor targeting both high performance discrete component and embedded capacitor in silicon-substrate package (2.5D interposer) which requires integrating with through-silicon-via (TSV) process. Unlike any reported capacitors, this high density 3D capacitor (ISC: integrated stack capacitor) is formed between metal interconnects, rather than in silicon substrate, with very low profile. The fabrication process and aspect of silicon capacitor is reported in this paper. The capacitor is fabricated by utilizing existing silicon technology so that yield is high and uses relatively low mask count.

There are three major methods to achieve high capacitance densities that are required: increased effective surface area, higher dielectric constant, and optimized dielectric thickness which is always a trade-off between reliability and total capacitance. Regarding high capacitor surface area, it was already shown that this could be done by etching structures with high aspect ratio into silicon and depositing the dielectric film on this enlarged surface area, in some cases with aspect ratio greater than 20:1 with depth of 170um. Etching into silicon with such a high aspect ratio could result in mechanical stability problem. The approach presented here is based on fabricating vertical capacitor between metal stacks that are able to etch hole-diameter smaller than 120nm with height of 1.6um in SiO2 dielectric. Due to its formation of capacitor between metal stacks with such a low profile, mechanical stability problem can be substantially reduced in large die, which is required for 2.5D interposer. Also due to its formation between metal interconnect, series resistances for both cathode and anode can be substantially reduced. Furthermore unlike any previous reports, this capacitor can be potentially stacked multiple times without compromising process complexity, to increase capacitor density multiple times. It is demonstrated in silicon that single stack can reach 250nF/mm2 (at BVDSS= 6V). 3D simulation shows that impedance of power delivery network of mobile application processor can be lowered by 70% at 500MHz, with reduction of VDD (0.8V) drop as much as > 20% in operation.