Study of Electrostatics and Transport Properties of Multigate Graded Nanowire Channel MOSFETs
Authors: Khosru Quazi D. M. , Khan Saeed Uz Zaman , Datta Kanak 
Published: February 2020

In this work, we have studied the electrostatics and ballistic transport characteristics of a multigate MOSFET structure with axially composition graded InGaAs channel. Wave-function penetration and other quantum mechanical effects were considered, along with the effects of strain on the graded heterojunction. Schrödinger and Poisson’s equations were solved numerically using FEM method. Furthermore, we have studied effects of doping and depth variation of the graded layers on the threshold voltage and gate leakage current of the device.

            With exceptional transport properties, III-V MOSFETs are replacing conventional Si MOSFET for deep sub-micron applications [1]. Multigate non-planar architectures based on III-V materials have drawn attention over the past few years because of their ability to provide better electrostatic control and short channel performances. The novel concept of graded nanowire channel MOSFET assumes improved performance over conventional Nanowire MOSFET. In this paper we justify the improved electrostatic and transport performances of an In-composition graded Nanowire channel device, compared to regular Nanowire Gate-All-Around MOSFET. The device structure under consideration has an inner rectangular channel of In0.53Ga0.47As with a width of 20 nm, surrounded by a 5 nm thin layer of In0.75Ga0.25As. 10 nm thick Al2O3 warps around the In0.75Ga0.25As layer and serves as the dielectric insulator for the device (Figure 1).

To study the properties of the device, a numerical simulator is developed which solves Schrödinger and Poisson’s equations self-consistently using COMSOL multiphysics [2] and MATLAB in a coupled manner. Assuming fully depleted channel and zero inversion carriers initially, the simulator first solves the Poisson’s equation for a 2-D vertical cross section of the device. The solution of the Poisson’s equation is used to update the energy band diagram, which is then used to solve the 2-D Schrödinger’s equation and calculate the inversion charge for the 2-D cross section. New inversion charge changes the solution of the initial Poisson’s equation. This process continues until convergence is achieved and we get Eigen energy, wave function, inversion charge distribution and potential profile of the channel. Later, the solution from vertical cross-section is used to approximate the wave functions and Eigen energies of a lateral cross-section across the channel. Landauer-Büttiker formalism with step-like transmission co-efficient then estimates the ballistic current-voltage characteristics. Effects of strain on the band structure of In0.53Ga0.47As- In0.75Ga0.25As are estimated using Luttinger parameters [3]. Finally, direct gate leakage current is calculated using modified Tsu-Esaki model [4].

Dit improves at Al2O3-InGaAs interface with higher In-composition [5], justifying the placement of the In0.75Ga0.25As layer near oxide interface. On the other hand, Figure 2 shows improved gate leakage profile with lower In-composition, thus supporting the idea of In0.53Ga0.47As core. Figure 3 displays that; increased relative thickness of the core layer increases the threshold voltage. Similarly, Figure 4 confirms that higher core doping can lead to significant threshold shift.

In summary, this work presents an III-V multigate device structure which exploits the better interface property of oxide-In0.75Ga0.25As and lower gate leakage profile of In0.53Ga0.47As core channel. Further investigation of the structure revealed, threshold voltage of the device is strongly dependent on the relative doping and thickness of the core.

References:

[1] Del Alamo, Jesús A., Nature 479.7373 (2011): 317-323.

[2] Official Website: https://www.comsol.com/comsol-multiphysics

[3] Piprek, Joachim. Semiconductor optoelectronic devices: introduction to physics and simulation. Academic Press, 2003.

[4] Schuegraf, K. F. et al., Proc. Symposium on VLSI Technology, (1992): 18-19.

[5] Sharmin, Saima et al., IEEE Nanotech . Materials and Devices Conf., (2012).

Figure 1