bluuebunny/crossref_metadata_2025 huggingface dataset:
Bulbar dysfunction and aspiration pneumonia due to a brainstem haemangioblastoma: an unusual complication of von Hippel-Lindau disease
Authors: Panayi Christos , Antoun Nagui , Sandford Richard
Published: October 2016

A 44-year-old woman with a history of von Hippel-Lindau (VHL) disease, a rare inherited neoplasia syndrome, presented acutely to hospital with a productive cough, symptoms of respiratory tract infection and odynophagia (painful swallowing). A chest X-ray confirmed right-sided pneumonia. Investigation of the persistent odynophagia using barium swallow revealed aspiration of the contrast into the lungs and suggested a neurological cause for her chest infection. Clinical assessment and speech and language therapy confirmed a pseudobulbar palsy. Subsequent neuroimaging identified a cystic haemangioblastoma, located at the cervicomedullary junction of the brainstem, as the cause of the pseudobulbar palsy. Urgent neurosurgical excision produced symptomatic relief and with continuing medical therapy, and clinical resolution of her pneumonia. In patients with VHL disease and other inherited cancer syndromes, a high index of suspicion should be maintained for new tumours presenting with common medical symptoms and signs.
Hepatitis B virus infection in Chinese patients with hepatitis C virus infection: prevalence, clinical characteristics, viral interactions and host genotypes: a nationwide cross-sectional study
Authors: Yan Li-Bo , Rao Hui-Ying , Ma Yuan-Ji , Bai Lang , Chen En-Qiang , Du Ling-Yao , Yang Rui-Feng , Wei Lai , Tang Hong
Published: October 2016

Objectives

Little is known about hepatitis B virus (HBV) infection in patients with hepatitis C virus (HCV) infection in China. This study aimed to evaluate the prevalence, clinical characteristics, viral interactions and host genotypes of HBV/HCV dual infection compared with HCV monoinfection.

Study design

A cross-sectional study.

Setting

China.

Participants and methods

997 patients with HCV from 28 university-affiliated hospitals in China were enrolled in this research. Patients were divided into two subgroups.

Results

The prevalence of HBV infection in patients with HCV was 4.11% (41/997). The age-specific prevalence of HBsAg was 0.70%, 3.97% and 5.85% in groups aged 18–30, 30–50 and >50 years old (p=0.057), respectively. Patients with HBV/HCV dual infection and patients with HCV monoinfection had similar HCV viral loads (5.80±0.89 vs 5.83±1.00 log10 IU/mL, p=0.904). The dominant HCV genotype was 1b in both groups (53.65% vs 56.90%, p=0.493). The protective C allele in IL-28B (rs12979860) was also the dominant allele type in both patient groups (85.36% vs 83.99%, p=0.814). Patients with HBV/HCV dual infection had a higher ratio of liver cirrhosis and hepatic decompensation than patients with HCV monoinfection (39.02% vs 17.69%, p=0.001; 31.70% vs 12.13%, p=0.001).

Conclusions

The HBV burden was moderate in HCV-infected patients in China. Liver cirrhosis was more common in patients with HBV/HCV dual infection, suggesting the need for closer monitoring of dual-infected individuals.

Trial registration number

NCT01293279; Post-results.
Intra-aneurysmal hemodynamics: evaluation of pCONus and pCANvas bifurcation aneurysm devices using DSA optical flow imaging
Authors: Pérez Marta Aguilar , Henkes Hans , Bouillot Pierre , Brina Olivier , Slater Lee-Anne , Pereira Vitor Mendes
Published: October 2016

Background

Implantation of self-expanding stents from the parent artery into the sac of a bifurcation aneurysm is regularly used to facilitate endovascular coil occlusion with the so-called waffle cone technique (WCT). Self-expanding aneurysm bridging stents like Solitaire AB, can be used; however, bifurcation devices like pCONus and pCANvas are especially designed for WCT. These devices provide additional support for coil implantation owing to intraluminal nylon fibers (pCONus) or membranes (pCANvas) covering the intracranial aneurysm neck.

Objective

Assessment of the intra-aneurysmal hemodynamic impact of these three devices: a regular intracranial stent (Solitaire AB) and two bifurcation devices (pCONus and pCANvas).

Material and methods

An in vitro experiment was set up using a silicone model of a basilar tip aneurysm filled with blood mimicking fluid under a pulsatile circulation. Solitaire AB, pCONus, and pCANvas were successively implanted in the model for hemodynamic evaluation. High frame rate DSA series were acquired under various conditions. Intra-aneurysmal flow changes, including mean aneurysm flow amplitude ratio (R), were subsequently assessed by the optical flow method, measuring the detector velocity field before and after device implantations.

Results

pCONus and Solitaire minimally reduced the intra-aneurysmal flow (R=0.96, p=0.17 and R=0.91, p=0.01, respectively), whereas pCANvas strongly diminished the intra-aneurysmal flow (R=0.41, p=5×10−12).

Conclusions

Waffle cone deployment of stents and technique-specific devices had no undesirable effect on the intra-aneurysmal flow. In particular, no increased flow was redirected into the aneurysm sac. The intraluminal membrane of the pCANvas strongly reduced the intra-aneurysmal flow, potentially preventing recanalization problems.
Cattle practice: ready to adapt to a changing world?
Authors: Huxley Jon
Published: October 2016

How well placed is UK cattle practice to meet future challenges? This question was addressed at a recent meeting of the Nottingham Dairy Health Innovation Forum. Forum member, Jon Huxley, reports on the outcome
Third‐year student diary
Authors: Perrett Rosie
Published: October 2016

After a ‘brilliant’ summer, Rosie Perrett is back at Liverpool vet school, starting her third year. The students are embarking on a year of clinical application.
Characterizing the mechanical behaviour of the Tournemire argillite
Authors: Su Xueqing , Nguyen Son , Haghighat Ehsan , Pietruszczak Stanislaw , Labrie Denis , Barnichon Jean-Dominique , Abdi Hadj
Published: October 2016

A laboratory programme of uniaxial, triaxial, cyclic and Brazilian tests was conducted to investigate the anisotropic mechanical behaviour of the Tournemire argillite, with different axial loading orientations with respect to the bedding planes (i.e. loading orientation angle, θ=0°, 30°, 45°, 60° and 90°). The experimental results show that both strength and deformation of the argillite are direction-dependent. Failure occurs in a brittle manner with a sudden collapse of the material strength. The failure mode exhibits localization along distinct failure planes and also depends on the loading orientation. This paper summarizes the experimental results and describes constitutive relationships that were developed in order to simulate the stress–strain behaviour of the Tournemire argillite. A microstructure tensor approach is adopted in order to take into account the anisotropic behaviour of the argillite. The identification procedure for material function and parameters is outlined, and the model is applied to simulate the set of triaxial tests performed at different levels of confining pressure and orientation of the bedding planes. It is demonstrated that the model adequately reproduces the anisotropy, the pre-peak stress–strain response and the onset of material collapse in those tests.
A 3D regional crustal model of the NE Atlantic based on seismic and gravity data
Authors: Haase C. , Ebbing J. , Funck T.
Published: October 2016

We present a 3D regional crustal model for the North Atlantic, which is based on the integration of seismic constraints and gravity data. The model addresses the crustal thickness geometry, and includes information on sedimentary thickness, the presence of high-velocity zones in the lower crust, and information on the crustal density distribution in the continental and oceanic domains. Using an iterative forward- and inverse-modelling approach, we adhere to the seismic constraints within their uncertainty, but manage to enhance the crustal geometry in areas where seismic data are sparse or absent. A number of basins are resolved with more detail. Recently released seismic reflection data beneath the NE Greenland Shelf allowed for a major improvement of the crustal thickness estimates. Estimated Moho depths beneath the basins there vary between 15 and 25 km, which is compatible with the conjugate Norwegian margin. A major lower-crustal seismic velocity anomaly in the vicinity of the Greenland–Iceland–Faroe Ridge complex is supported by density modelling. We discuss the validity and uncertainties of our model assumptions and discuss the correlation with the main structural elements of the North Atlantic.
A review of the NE Atlantic conjugate margins based on seismic refraction data
Authors: Funck Thomas , Erlendsson Ögmundur , Geissler Wolfram H. , Gradmann Sofie , Kimbell Geoffrey S. , McDermott Kenneth , Petersen Uni K.
Published: October 2016

The NE Atlantic region evolved through several rift episodes, leading to break-up in the Eocene that was associated with voluminous magmatism along the conjugate margins of East Greenland and NW Europe. Existing seismic refraction data provide good constraints on the overall tectonic development of the margins, despite data gaps at the NE Greenland shear margin and the southern Jan Mayen microcontinent. The maximum thickness of the initial oceanic crust is 40 km at the Greenland–Iceland–Faroe Ridge, but decreases with increasing distance to the Iceland plume. High-velocity lower crust interpreted as magmatic underplating or sill intrusions is observed along most margins but disappears north of the East Greenland Ridge and the Lofoten margin, with the exception of the Vestbakken Volcanic Province at the SW Barents Sea margin. South of the narrow Lofoten margin, the European side is characterized by wide margins. The opposite trend is seen in Greenland, with a wide margin in the NE and narrow margins elsewhere. The thin crust beneath the basins is generally underlain by rocks with velocities of >7 km s
−1
interpreted as serpentinized mantle in the Porcupine and southern Rockall basins; while off Norway, alternative interpretations such as eclogite bodies and underplating are also discussed.
Noncommutative Valiant's Classes
Authors: Arvind V. , Joglekar P. S. , Raja S.
Published: October 2016

In this article, we explore the noncommutative analogues, VP
nc
and VNP

nc

, of Valiant’s algebraic complexity classes and show some striking connections to classical formal language theory. Our main results are the following:

— We show that Dyck polynomials (defined from the Dyck languages of formal language theory) are complete for the class VP

nc

under ≤

abp

reductions. To the best of our knowledge, these are the first natural polynomial families shown to be VP

nc

-complete. Likewise, it turns out that PAL (palindrome polynomials defined from palindromes) are complete for the class VSKEW

nc

(defined by polynomial-size skew circuits) under ≤

abp

reductions. The proof of these results is by suitably adapting the classical Chomsky-Schützenberger theorem showing that Dyck languages are the hardest CFLs.

— Assuming that VP

nc

≠ VNP

nc

, we exhibit a strictly infinite hierarchy of p-families, with respect to the projection reducibility, between the complexity classes VP

nc

and VNP

nc

(analogous to Ladner’s theorem [Ladner 1975]).

— Additionally, inside VP

nc

, we show that there is a strict hierarchy of p-families (based on the nesting depth of Dyck polynomials) with respect to the ≤

abp

reducibility (defined explicitly in this article).
Parallel SystemC Simulation for ESL Design
Authors: Weinstock Jan Henrik , Murillo Luis Gabriel , Leupers Rainer , Ascheid Gerd
Published: October 2016

Virtual platforms have become essential tools for the design of embedded systems. Developers rely on them for design space exploration and software debugging. However, with rising HW/SW complexity and the need to simulate more and more processors simultaneously, the performance of virtual platforms degrades rapidly. Parallel simulation techniques can help to counter this by leveraging multicore PCs, which are widely available today. This work presents a novel parallel simulation approach that is targeted toward acceleration of virtual platforms from the ESL domain. By trading some timing accuracy, multiprocessor virtual platforms can be accelerated by up to 3.4× on regular quad-core workstations.
Morpheus
Authors: Tseng Hung-Wei , Zhao Qianchen , Zhou Yuxiao , Gahagan Mark , Swanson Steven
Published: October 2016

In high performance computing systems, object deserialization can become a surprisingly important bottleneck---in our test, a set of general-purpose, highly parallelized applications spends 64% of total execution time deserializing data into objects.

This paper presents the Morpheus model, which allows applications to move such computations to a storage device. We use this model to deserialize data into application objects inside storage devices, rather than in the host CPU. Using the Morpheus model for object deserialization avoids unnecessary system overheads, frees up scarce CPU and main memory resources for compute-intensive workloads, saves I/O bandwidth, and reduces power consumption. In heterogeneous, co-processor-equipped systems, Morpheus allows application objects to be sent directly from a storage device to a co-processor (e.g., a GPU) by peer-to-peer transfer, further improving application performance as well as reducing the CPU and main memory utilizations.

This paper implements Morpheus-SSD, an SSD supporting the Morpheus model. Morpheus-SSD improves the performance of object deserialization by 1.66×, reduces power consumption by 7%, uses 42% less energy, and speeds up the total execution time by 1.32×. By using NVMe-P2P that realizes peer-to-peer communication between Morpheus-SSD and a GPU, Morpheus-SSD can speed up the total execution time by 1.39× in a heterogeneous computing platform.
Strober
Authors: Kim Donggyu , Izraelevitz Adam , Celio Christopher , Kim Hokeun , Zimmer Brian , Lee Yunsup , Bachrach Jonathan , Asanović Krste
Published: October 2016

This paper presents a sample-based energy simulation methodology that enables fast and accurate estimations of performance and average power for arbitrary RTL designs. Our approach uses an FPGA to simultaneously simulate the performance of an RTL design and to collect samples containing exact RTL state snapshots. Each snapshot is then replayed in gate-level simulation, resulting in a workload-specific average power estimate with confidence intervals. For arbitrary RTL and workloads, our methodology guarantees a minimum of four-orders-of-magnitude speedup over commercial CAD gate-level simulation tools and gives average energy estimates guaranteed to be within 5% of the true average energy with 99% confidence. We believe our open-source sample-based energy simulation tool Strober can not only rapidly provide ground truth for more abstract power models, but can enable productive design-space exploration early in the RTL design process.
Biscuit
Authors: Gu Boncheol , Yoon Andre S. , Bae Duck-Ho , Jo Insoon , Lee Jinyoung , Yoon Jonghyun , Kang Jeong-Uk , Kwon Moonsang , Yoon Chanho , Cho Sangyeun , Jeong Jaeheon , Chang Duckhyun
Published: October 2016

Data-intensive queries are common in business intelligence, data warehousing and analytics applications. Typically, processing a query involves full inspection of large in-storage data sets by CPUs. An intuitive way to speed up such queries is to reduce the volume of data transferred over the storage network to a host system. This can be achieved by filtering out extraneous data within the storage, motivating a form of near-data processing. This work presents Biscuit, a novel near-data processing framework designed for modern solid-state drives. It allows programmers to write a data-intensive application to run on the host system and the storage system in a distributed, yet seamless manner. In order to offer a high-level programming model, Biscuit builds on the concept of data flow. Data processing tasks communicate through typed and data-ordered ports. Biscuit does not distinguish tasks that run on the host system and the storage system. As the result, Biscuit has desirable traits like generality and expressiveness, while promoting code reuse and naturally exposing concurrency. We implement Biscuit on a host system that runs the Linux OS and a high-performance solid-state drive. We demonstrate the effectiveness of our approach and implementation with experimental results. When data filtering is done by hardware in the solid-state drive, the average speed-up obtained for the top five queries of TPC-H is over 15×.
Energy efficient architecture for graph analytics accelerators
Authors: Ozdal Muhammet Mustafa , Yesil Serif , Kim Taemin , Ayupov Andrey , Greth John , Burns Steven , Ozturk Ozcan
Published: October 2016

Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area.
EIE
Authors: Han Song , Liu Xingyu , Mao Huizi , Pu Jing , Pedram Ardavan , Horowitz Mark A. , Dally William J.
Published: October 2016

State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resources and power budgets. While custom hardware helps the computation, fetching weights from DRAM is two orders of magnitude more expensive than ALU operations, and dominates the required power.

Previously proposed 'Deep Compression' makes it possible to fit large DNNs (AlexNet and VGGNet) fully in on-chip SRAM. This compression is achieved by pruning the redundant connections and having multiple connections share the same weight. We propose an energy efficient inference engine (EIE) that performs inference on this compressed network model and accelerates the resulting sparse matrix-vector multiplication with weight sharing. Going from DRAM to SRAM gives EIE 120× energy saving; Exploiting sparsity saves 10×; Weight sharing gives 8×; Skipping zero activations from ReLU saves another 3×. Evaluated on nine DNN benchmarks, EIE is 189× and 13× faster when compared to CPU and GPU implementations of the same DNN without compression. EIE has a processing power of 102 GOPS working directly on a compressed network, corresponding to 3 TOPS on an uncompressed network, and processes FC layers of AlexNet at 1.88×10
4
frames/sec with a power dissipation of only 600mW. It is 24,000× and 3,400× more energy efficient than a CPU and GPU respectively. Compared with DaDianNao, EIE has 2.9×, 19× and 3× better throughput, energy efficiency and area efficiency.
RedEye
Authors: LiKamWa Robert , Hou Yunhui , Gao Julian , Polansky Mia , Zhong Lin
Published: October 2016

Continuous mobile vision is limited by the inability to efficiently capture image frames and process vision features. This is largely due to the energy burden of analog readout circuitry, data traffic, and intensive computation. To promote efficiency, we shift early vision processing into the analog domain. This results in RedEye, an analog convolutional image sensor that performs layers of a convolutional neural network in the analog domain before quantization. We design RedEye to mitigate analog design complexity, using a modular column-parallel design to promote physical design reuse and algorithmic cyclic reuse. RedEye uses programmable mechanisms to admit noise for tunable energy reduction. Compared to conventional systems, RedEye reports an 85% reduction in sensor energy, 73% reduction in cloudlet-based system energy, and a 45% reduction in computation-based system energy.
Minerva
Authors: Reagen Brandon , Whatmough Paul , Adolf Robert , Rama Saketh , Lee Hyunkwang , Lee Sae Kyu , Hernández-Lobato José Miguel , Wei Gu-Yeon , Brooks David
Published: October 2016

The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous datatype optimization reduces power by 1.5×; aggressive, inline predication and pruning of small activity values further reduces power by 2.0×; and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7× through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1× power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.
Opportunistic competition overhead reduction for expediting critical section in NoC based CMPs
Authors: Yao Yuan , Lu Zhonghai
Published: October 2016

With the degree of parallelism increasing, performance of multi-threaded shared variable applications is not only limited by serialized critical section execution, but also by the serialized competition overhead for threads to get access to critical section. As the number of concurrent threads grows, such competition overhead may exceed the time spent in critical section itself, and become the dominating factor limiting the performance of parallel applications.

In modern operating systems, queue spinlock, which comprises a low-overhead spinning phase and a high-overhead sleeping phase, is often used to lock critical sections. In the paper, we show that this advanced locking solution may create very high competition overhead for multithreaded applications executing in NoC-based CMPs. Then we propose a software-hardware cooperative mechanism that can opportunistically maximize the chance that a thread wins the critical section access in the low-overhead spinning phase, thereby reducing the competition overhead. At the OS primitives level, we monitor the remaining times of retry (RTR) in a thread's spinning phase, which reflects in how long the thread must enter into the high-overhead sleep mode. At the hardware level, we integrate the RTR information into the packets of locking requests, and let the NoC prioritize locking request packets according to the RTR information. The principle is that the smaller RTR a locking request packet carries, the higher priority it gets and thus quicker delivery.

We evaluate our opportunistic competition overhead reduction technique with cycle-accurate full-system simulations in GEM5 using PARSEC (11 programs) and SPEC OMP2012 (14 programs) benchmarks. Compared to the original queue spinlock implementation, experimental results show that our method can effectively increase the opportunity of threads entering the critical section in low-overhead spinning phase, reducing the competition overhead averagely by 39.9% (maximally by 61.8%) and accelerating the execution of the Region-of-Interest averagely by 14.4% (maximally by 24.5%) across all 25 benchmark programs.
Short-circuit dispatch
Authors: Kim Channoh , Kim Sungmin , Cho Hyeon Gyu , Kim Dooyoung , Kim Jaehyeok , Oh Young H. , Jang Hakbeom , Lee Jae W.
Published: October 2016

Interpreters are widely used to implement high-level language virtual machines (VMs), especially on resource-constrained embedded platforms. Many scripting languages employ interpreter-based VMs for their advantages over native code compilers, such as portability, smaller resource footprint, and compact codes. For efficient interpretation a script (program) is first compiled into an intermediate representation, or
bytecodes
. The canonical interpreter then runs an infinite loop that fetches, decodes, and executes one bytecode at a time. This bytecode dispatch loop is a well-known source of inefficiency, typically featuring a large jump table with a hard-to-predict indirect jump. Most existing techniques to optimize this loop focus on reducing the misprediction rate of this indirect jump in both hardware and software. However, these techniques are much less effective on embedded processors with shallow pipelines and low IPCs.

Instead, we tackle another source of inefficiency more prominent on embedded platforms--redundant computation in the dispatch loop. To this end, we propose Short-Circuit Dispatch (SCD), a low-cost architectural extension that enables fast, hardware-based bytecode dispatch with fewer instructions. The key idea of SCD is to overlay the software-created bytecode jump table on a branch target buffer (BTB). Once a bytecode is fetched, the BTB is looked up using the bytecode, instead of PC, as key. If it hits, the interpreter directly jumps to the target address retrieved from the BTB; otherwise, it goes through the original dispatch path. This effectively eliminates redundant computation in the dispatcher code for decode, bound check, and target address calculation, thus significantly reducing total instruction count. Our simulation results demonstrate that SCD achieves geomean speedups of 19.9% and 14.1% for two production-grade script interpreters for Lua and JavaScript, respectively. Moreover, our fully synthesizable RTL design based on a RISC-V embedded processor shows that SCD improves the EDP of the Lua interpreter by 24.2%, while increasing the chip area by only 0.72% at a 40nm technology node.
Future vector microprocessor extensions for data aggregations
Authors: Hayes Timothy , Palomar Oscar , Unsal Osman , Cristal Adrian , Valero Mateo
Published: October 2016

As the rate of annual data generation grows exponentially, there is a demand to aggregate and summarise vast amounts of information quickly. In the past, frequency scaling was relied upon to push application throughput. Today, Dennard scaling has ceased and further performance must come from exploiting parallelism. Single instruction-multiple data (SIMD) instruction sets offer a highly efficient and scalable way of exploiting data-level parallelism (DLP). While microprocessors originally offered very simple SIMD support targeted at multimedia applications, these extensions have been growing both in width and functionality. Observing this trend, we use a simulation framework to model future SIMD support and then propose and evaluate five different ways of vectorising data aggregation. We find that although data aggregation is abundant in DLP, it is often too irregular to be expressed efficiently using typical SIMD instructions. Based on this observation, we propose a set of novel algorithms and SIMD instructions to better capture this irregular DLP. Furthermore, we discover that the best algorithm is highly dependent on the characteristics of the input. Our proposed solution can dynamically choose the optimal algorithm in the majority of cases and achieves speedups between 2.7 × and 7.6 × over a scalar baseline.
Peak efficiency aware scheduling for highly energy proportional servers
Authors: Wong Daniel
Published: October 2016

Energy proportionality of data center severs have improved drastically over the past decade to the point where near ideal energy proportional servers are now common. These highly energy proportional servers exhibit the unique property where peak efficiency no longer coincides with peak utilization. In this paper, we explore the implications of this property on data center scheduling. We identified that current state of the art data center schedulers does not efficiently leverage these properties, leading to inefficient scheduling decisions. We propose Peak Efficiency Aware Scheduling (PEAS) which can achieve better-than-ideal energy proportionality at the data center level. We demonstrate that PEAS can reduce average power by 25.5% with 3.0% improvement to TCO compared to state-of-the-art scheduling policies.
DRAF
Authors: Gao Mingyu , Delimitrou Christina , Niu Dimin , Malladi Krishna T. , Zheng Hongzhong , Brennan Bob , Kozyrakis Christos
Published: October 2016

FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devices in environments with tight cost and power constraints. This is the case for datacenter servers, where a modestly-sized FPGA cannot accommodate the large number of diverse accelerators that datacenter applications need.

This paper introduces DRAF, an architecture for bit-level reconfigurable logic that uses DRAM subarrays to implement dense lookup tables. DRAF overlaps DRAM operations like bitline precharge and charge restoration with routing within the reconfigurable routing fabric to minimize the impact of DRAM latency. It also supports multiple configuration contexts that can be used to quickly switch between different accelerators with minimal latency. Overall, DRAF trades off some of the performance of FPGAs for significant gains in area and power. DRAF improves area density by 10x over FPGAs and power consumption by more than 3x, enabling DRAF to satisfy demanding applications within strict power and cost constraints. While accelerators mapped to DRAF are 2-3x slower than those in FPGAs, they still deliver a 13x speedup and an 11x reduction in power consumption over a Xeon core for a wide range of datacenter tasks, including analytics and interactive services like speech recognition.
MITTS
Authors: Zhou Yanqi , Wentzlaff David
Published: October 2016

Memory bandwidth severely limits the scalability and performance of multicore and manycore systems. Application performance can be very sensitive to both the delivered memory bandwidth and latency. In multicore systems, a memory channel is usually shared by multiple cores. Having the ability to precisely provision, schedule, and isolate memory bandwidth and latency on a per-core basis is particularly important when different memory guarantees are needed on a per-customer, per-application, or per-core basis. Infrastructure as a Service (IaaS) Cloud systems, and even general purpose multicores optimized for application throughput or fairness all benefit from the ability to control and schedule memory access on a fine-grain basis. In this paper, we propose MITTS (Memory Inter-arrival Time Traffic Shaping), a simple, distributed hardware mechanism which limits memory traffic at the source (Core or LLC). MITTS shapes memory traffic based on memory request inter-arrival time, enabling fine-grain bandwidth allocation. In an IaaS system, MITTS enables Cloud customers to express their memory distribution needs and pay commensurately. For instance, MITTS enables charging customers that have bursty memory traffic more than customers with uniform memory traffic for the same aggregate bandwidth. Beyond IaaS systems, MITTS can also be used to optimize for throughput or fairness in a general purpose multi-program workload. MITTS uses an online genetic algorithm to configure hardware bins, which can adapt for program phases and variable input sets. We have implemented MITTS in Verilog and have taped-out the design in a 25-core 32nm processor and find that MITTS requires less than 0.9% of core area. We evaluate across SPECint, PARSEC, Apache, and bhm Mail Server workloads, and find that MITTS achieves an average 1.18× performance gain compared to the best static bandwidth allocation, a 2.69× average performance/cost advantage in an IaaS setting, and up to 1.17× better throughput and 1.52× better fairness when compared to conventional memory bandwidth provisioning techniques.
Evaluation of an analog accelerator for linear algebra
Authors: Huang Yipeng , Guo Ning , Seok Mingoo , Tsividis Yannis , Sethumadhavan Simha
Published: October 2016

Due to the end of supply voltage scaling and the increasing percentage of dark silicon in modern integrated circuits, researchers are looking for new scalable ways to get useful computation from existing silicon technology. In this paper we present a reconfigurable analog accelerator for solving systems of linear equations. Commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty in programming are all compensated for using methods we discuss. Based on a prototyped analog accelerator chip we compare the performance and energy consumption of the analog solver against an efficient digital algorithm running on a CPU, and find that the analog accelerator approach may be an order of magnitude faster and provide one third energy savings, depending on the accelerator design. Due to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint. Finally, we conclude that problem classes outside of systems of linear equations may hold more promise for analog acceleration.
Virtual thread
Authors: Yoon Myung Kuk , Kim Keunsoo , Lee Sangpil , Ro Won Woo , Annavaram Murali
Published: October 2016

Modern GPUs require tens of thousands of concurrent threads to fully utilize the massive amount of processing resources. However, thread concurrency in GPUs can be diminished either due to shortage of thread scheduling structures (scheduling limit), such as available program counters and single instruction multiple thread stacks, or due to shortage of on-chip memory (capacity limit), such as register file and shared memory. Our evaluations show that in practice concurrency in many general purpose applications running on GPUs is curtailed by the scheduling limit rather than the capacity limit. Maximizing the utilization of on-chip memory resources without unduly increasing the scheduling complexity is a key goal of this paper.

This paper proposes a Virtual Thread (VT) architecture which assigns Cooperative Thread Arrays (CTAs) up to the capacity limit, while ignoring the scheduling limit. However, to reduce the logic complexity of managing more threads concurrently, we propose to place CTAs into active and inactive states, such that the number of active CTAs still respects the scheduling limit. When all the warps in an active CTA hit a long latency stall, the active CTA is context switched out and the next ready CTA takes its place. We exploit the fact that both active and inactive CTAs still fit within the capacity limit which obviates the need to save and restore large amounts of CTA state. Thus VT significantly reduces performance penalties of CTA swapping. By swapping between active and inactive states, VT can exploit higher degree of thread level parallelism without increasing logic complexity. Our simulation results show that VT improves performance by 23.9% on average.
Boosting access parallelism to PCM-based main memory
Authors: Arjomand Mohammad , Kandemir Mahmut T. , Sivasubramaniam Anand , Das Chita R.
Published: October 2016

Despite its promise as a DRAM main memory replacement, Phase Change Memory (PCM) has high write latencies which can be a serious detriment to its widespread adoption. Apart from slowing down a write request, the consequent high latency can also keep other chips of the same rank, that are not involved in this write, idle for long times. There are several practical considerations that make it difficult to allow subsequent reads and/or writes to be served concurrently from the same chips during the long latency write. This paper proposes and evaluates several novel mechanisms -- re-constructing data from error correction bits instead of waiting for chips currently busy to serve a read, rotating word mappings across chips of a PCM rank, and rotating the mapping of error detection/correction bits across these chips -- to overlap several reads with an ongoing write (RoW) and even a write with an ongoing write (WoW). The paper also presents the necessary micro-architectural enhancements nee-ded to implement these mechanisms, without significantly changing the current interfaces. The resulting PCM access parallelism (PCMap) system incorporating these enhancements, boosts the intra-rank-level parallelism during such writes from a very low baseline value of 2.4 to an average and maximum values of 4.5 and 7.4, respectively (out of a maximum of 8.0), across a wide spectrum of both multiprogrammed and multithreaded workloads. This boost in parallelism results in an average IPC improvement of 15.6% and 16.7% for the multi-progra-mmed and multi-threaded workloads, respectively.
Agile paging
Authors: Gandhi Jayneel , Hill Mark D. , Swift Michael M.
Published: October 2016

Virtualization provides benefits for many workloads, but the overheads of virtualizing memory are not universally low. The cost comes from managing two levels of address translation---one in the guest virtual machine (VM) and the other in the host virtual machine monitor (VMM)---with either nested or shadow paging. Nested paging directly performs a two-level page walk that makes TLB misses slower than unvirtualized native, but enables fast page tables changes. Alternatively, shadow paging restores native TLB miss speeds, but requires costly VMM intervention on page table updates.

This paper proposes
agile paging
that combines both techniques and exceeds the best of both. A virtualized page walk starts with shadow paging and optionally switches in the same page walk to nested paging where frequent page table updates would cause costly VMM interventions. Agile paging enables most TLB misses to be handled as fast as native while most page table changes avoid VMM intervention. It requires modest changes to hardware (e.g., demark when to switch) and VMM policies (e.g., predict good switching opportunities).

We emulate the proposed hardware and prototype the software in Linux with KVM on x86-64. Agile paging performs more than 12% better than the best of the two techniques and comes within 4% of native execution for all workloads.
Type 1 diabetes modulates cyclooxygenase- and nitric oxide-dependent mechanisms governing sweating but not cutaneous vasodilation during exercise in the heat
Authors: Fujii Naoto , Dervis Sheila , Sigal Ronald J. , Kenny Glen P.
Published: October 2016

Both cyclooxygenase (COX) and nitric oxide synthase (NOS) contribute to sweating, whereas NOS alone contributes to cutaneous vasodilation during exercise in the heat. Here, we evaluated if Type 1 diabetes mellitus (T1DM) modulates these responses. Adults with ( n = 11, 25 ± 5 yr) and without ( n = 12, 24 ± 4 yr) T1DM performed two bouts of 30-min cycling at a fixed rate of heat production of 400 W in the heat (35°C); each followed by a 20- and 40-min recovery period, respectively. Sweat rate and cutaneous vascular conductance (CVC) were measured at four intradermal microdialysis sites treated with either 1) lactated Ringer (vehicle control site), 2) 10 mM ketorolac (nonselective COX inhibitor), 3) 10 mM NG-nitro-l-arginine methyl ester (nonselective NOS inhibitor), or 4) a combination of both inhibitors. In nondiabetic adults, separate and combined inhibition of COX and NOS reduced exercise sweat rate ( P ≤ 0.05), and the magnitude of reductions were similar across sites. In individuals with T1DM, inhibition of COX resulted in an increase in sweat rate of 0.10 ± 0.09 and 0.09 ± 0.08 mg·min−1·cm−2for the first and second exercise bouts, respectively, relative to vehicle control site ( P ≤ 0.05), whereas NOS inhibition had no effect on sweating. In both groups, NOS inhibition reduced CVC during exercise ( P ≤ 0.05), although the magnitude of reduction did not differ between the nondiabetic and T1DM groups ( exercise 1: −28 ± 10 vs. −23 ± 8% max, P = 0.51; exercise 2: −31 ± 12 vs. −24 ± 10% max, P = 0.38). We show that in individuals with T1DM performing moderate intensity exercise in the heat, NOS-dependent sweating but not cutaneous vasodilation is attenuated, whereas COX inhibition increases sweating.
Lexicon-Based Sentiment Analysis of Teachers’ Evaluation
Authors: Rajput Quratulain , Haider Sajjad , Ghani Sayeed
Published: October 2016

The end of the course evaluation has become an integral part of education management in almost every academic institution. The existing automated evaluation method primarily employs the Likert scale based quantitative scores provided by students about the delivery of the course and the knowledge of the instructor. The feedback is subsequently used to improve the quality of the teaching and often for the annual appraisal process. In addition to the Likert scale questions, the evaluation form typically contains open-ended questions where students can write general comments/feedback that might not be covered by the fixed questions. The textual feedback, however, is usually provided to teachers and administration and due to its nonquantitative nature is frequently not processed to gain more insight. This paper aims to address this aspect by applying several text analytics methods on students’ feedback. The paper not only presents a sentiment analysis based metric, which is shown to be highly correlated with the aggregated Likert scale scores, but also provides new insight into a teacher’s performance with the help of tag clouds, sentiment score, and other frequency-based filters.
A Novel Framework for Interactive Visualization and Analysis of Hyperspectral Image Data
Authors: Jordan Johannes , Angelopoulou Elli , Maier Andreas
Published: October 2016

Multispectral and hyperspectral images are well established in various fields of application like remote sensing, astronomy, and microscopic spectroscopy. In recent years, the availability of new sensor designs, more powerful processors, and high-capacity storage further opened this imaging modality to a wider array of applications like medical diagnosis, agriculture, and cultural heritage. This necessitates new tools that allow general analysis of the image data and are intuitive to users who are new to hyperspectral imaging. We introduce a novel framework that bundles new interactive visualization techniques with powerful algorithms and is accessible through an efficient and intuitive graphical user interface. We visualize the spectral distribution of an image via parallel coordinates with a strong link to traditional visualization techniques, enabling new paradigms in hyperspectral image analysis that focus on interactive raw data exploration. We combine novel methods for supervised segmentation, global clustering, and nonlinear false-color coding to assist in the visual inspection. Our framework coined Gerbil is open source and highly modular, building on established methods and being easily extensible for application-specific needs. It satisfies the need for a general, consistent software framework that tightly integrates analysis algorithms with an intuitive, modern interface to the raw image data and algorithmic results. Gerbil finds its worldwide use in academia and industry alike with several thousand downloads originating from 45 countries.
Dietary Energy Density, Renal Function, and Progression of Chronic Kidney Disease
Authors: Rouhani Mohammad Hossein , Najafabadi Mojgan Mortazavi , Esmaillzadeh Ahmad , Feizi Awat , Azadbakht Leila
Published: October 2016

Background. There is evidence of the association between dietary energy density and chronic diseases. However, no report exists regarding the relation between DED and chronic kidney disease (CKD).Objective. To examine the association between dietary energy density (DED), renal function, and progression of chronic kidney disease (CKD).Design. Cross-sectional.Setting. Three nephrology clinics.Subjects. Two hundred twenty-one subjects with diagnosed CKD.Main Outcome Measure. Dietary intake of patients was assessed by a validated food frequency questionnaire. DED (in kcal/g) was calculated with the use of energy content and weight of solid foods and energy yielding beverages. Renal function was measured by blood urea nitrogen (BUN), serum creatinine (Cr), and estimated glomerular filtration rate (eGFR).Results. Patients in the first tertile of DED consumed more amounts of carbohydrate, dietary fiber, potassium, phosphorus, zinc, magnesium, calcium, folate, vitamin C, and vitamin B2. After adjusting for confounders, we could not find any significant trend for BUN and Cr across tertiles of DED. In multivariate model, an increased risk of being in the higher stage of CKD was found among those in the last tertile of DED (OR: 3.15; 95% CI: 1.30, 7.63;P=0.01).Conclusion. We observed that lower DED was associated with better nutrient intake and lower risk of CKD progression.
Percutaneous Transluminal Angioplasty in Patients with Peripheral Arterial Disease Does Not Affect Circulating Monocyte Subpopulations
Authors: Maga Pawel , Mikolajczyk Tomasz P. , Partyka Lukasz , Krzanowski Marek , Malinowski Krzysztof P. , Nizankowski Rafal
Published: October 2016

Monocytes are mononuclear cells characterized by distinct morphology and expression of CD14 and CD16 surface receptors. Classical, quiescent monocytes are positive for CD14 (lipopolysaccharide receptor) but do not express Fc gamma receptor III (CD16). Intermediate monocytes coexpress CD16 and CD14. Nonclassical monocytes with low expression of CD14 represent mature macrophage-like monocytes. Monocyte behavior in peripheral arterial disease (PAD) and during vessel wall directed treatment is not well defined. This observation study aimed at monitoring of acute changes in monocyte subpopulations during percutaneous transluminal angioplasty (PTA) in PAD patients. Patients with Rutherford 3 and 4 PAD with no signs of inflammatory process underwent PTA of iliac, femoral, or popliteal segments. Flow cytometry for CD14, CD16, HLA-DR, CD11b, CD11c, and CD45RA antigens allowed characterization of monocyte subpopulations in blood sampled before and after PTA (direct angioplasty catheter sampling). Patients were clinically followed up for 12 months. All 61 enrolled patients completed 12-month follow-up. Target vessel failure occurred in 12 patients. While absolute counts of monocyte were significantly lower after PTA, only subtle monocyte activation after PTA (CD45RA andβ-integrins) occurred. None of the monocyte parameters correlated with long-term adverse clinical outcome. Changes in absolute monocyte counts and subtle changes towards an activation phenotype after PTA may reflect local cell adhesion phenomenon in patients with Rutherford 3 or 4 peripheral arterial disease.