bluuebunny/crossref_metadata_2025 huggingface dataset:
Sestrin and the Consequences of Aging
Authors: Ray L. Bryan
Published: March 2010

Sestrin proteins protect fruit flies from the tissue degeneration and disruption of metabolic homeostasis that accompany aging.
Stress-Activated Cap'n'collar Transcription Factors in Aging and Human Disease
Authors: Sykiotis Gerasimos P. , Bohmann Dirk
Published: March 2010

The oxidative stress response is an attractive target for treating human diseases and extending the healthy life span.
Differentiation of Clonal Complex 59 Community-Associated Methicillin-Resistant
Staphylococcus aureus
in Western Australia
Authors: Coombs Geoffrey W. , Monecke Stefan , Ehricht Ralf , Slickers Peter , Pearson Julie C. , Tan Hui-Leen , Christiansen Keryn J. , O'Brien Frances G.
Published: March 2010

Clonal complex 59 (CC59) community-associated methicillin-resistant
Staphylococcus aureus
(CA-MRSA) strains were characterized using pulsed-field gel electrophoresis,
spa
typing, multilocus sequence typing, diagnostic DNA microarrays, and PCRs targeting staphylococcal cassette chromosome
mec
(SCC
mec
) elements and Panton-Valentine leukocidin (PVL). Six distinct groups within CC59 were characterized. At least seven different variants of SCC
mec
elements were identified (IVa [2B], IVb [2B], IVd [2B], IV variant [2B], IVa [2B&5], V variant [5C2], and V [5C2&5]). (The structural type is indicated by a Roman numeral, with a lowercase letter indicating the subtype, and the
ccr
complex and the
mec
complex are indicated by an Arabic numeral and an uppercase letter, respectively. Where there is an extra
ccr
element, this is indicated by “&” and an Arabic numeral designating the
ccr
type.) The first group is similar to the American sequence type 59 (ST59) MRSA-IV CA-MRSA strain USA1000. The second group includes a PVL-negative ST87 strain with an SCC
mec
element of subtype IVb (2B). The third group comprises PVL-variable ST59 MRSA-IV strains harboring multiple SCC
mec
IV subtypes. PVL-negative ST59 MRSA strains with multiple or composite SCC
mec
elements (IVa [2B&5]) form the fourth group. Group 5 corresponds to the internationally known “Taiwan clone,” a PVL-positive strain with a variant SCC
mec
element (V [5C2&5]). This strain proved to be the most common CC59 MRSA strain isolated in Western Australia. Finally, group 6 encompasses the ST59 MRSA-V variant (5C2). The differentiation of CC59 into groups and strains indicates a rapid evolution and spread of SCC
mec
elements. Observed differences between groups of strains as well as intrastrain variability within a group facilitate the tracing of their spread.
Cyclotide Interactions with the Nematode External Surface
Authors: Colgrave Michelle L. , Huang Yen-Hua , Craik David J. , Kotze Andrew C.
Published: March 2010

Cyclotides are a large family of cyclic cystine knot-containing plant peptides that have anthelminthic activities againstHaemonchus contortusandTrichostrongylus colubriformis, two important gastrointestinal nematodes of sheep. In this study, we investigated the interaction of the prototypic cyclotide kalata B1 with the external surface ofH. contortuslarvae and adult worms. We show that cyclotides do not need to be ingested by the worms to exert their toxic effects but that an interaction with the external surface alone is toxic. Evidence for this was the toxicity toward adult worms in the presence of a chemically induced pharyngeal ligature and toxicity of cyclotides toward nonfeeding larval life stages. Uptake of tritiated inulin in ligated adult worms was increased in the presence of cyclotide, suggesting that cyclotides increase the permeability of the external membranes of adult nematodes. Polyethylene glycols of various sizes showed protective effects on the nonfeeding larval life stage, as well as in hemolytic activity assays, suggesting that discrete pores are formed in the membrane surfaces by cyclotides and that these can be blocked by polyethylene glycols of appropriate size. This increased permeability is consistent with recently reported effects of cyclotides on membranes in which kalata B1 was demonstrated to form pores and cause leakage of vesicle/cellular contents. Our data, together with known size constraints on the movement of permeants across nematode cuticle layers, suggest that one action of the cyclotides involves an interaction with the lipid-rich epicuticle layer at the surface of the worm.
Antiviral Activity of a Small-Molecule Inhibitor of Filovirus Infection
Authors: Warren Travis K. , Warfield Kelly L. , Wells Jay , Enterlein Sven , Smith Mark , Ruthel Gordon , Yunus Abdul S. , Kinch Michael S. , Goldblatt Michael , Aman M. Javad , Bavari Sina
Published: March 2010

There exists an urgent need to develop licensed drugs and vaccines for the treatment or prevention of filovirus infections. FGI-103 is a low-molecular-weight compound that was discovered through an
in
vitro
screening assay utilizing a variant of
Zaire
ebolavirus
(ZEBOV) that expresses green fluorescent protein.
In
vitro
analyses demonstrated that FGI-103 also exhibits antiviral activity against wild-type ZEBOV and
Sudan
ebolavirus
, as well as
M
arburgvirus
(MARV) strains Ci67 and Ravn.
In
vivo
administration of FGI-103 as a single intraperitoneal dose of 10 mg/kg delivered 24 h after infection is sufficient to completely protect mice against a lethal challenge with a mouse-adapted strain of either ZEBOV or MARV-Ravn. In a murine model of ZEBOV infection, delivery of FGI-103 reduces viremia and the viral burden in kidney, liver, and spleen tissues and is associated with subdued and delayed proinflammatory cytokine responses and tissue pathology. Taken together, these results identify a promising antiviral therapeutic candidate for the treatment of filovirus infections.
Synergistic Effects between Conventional Antibiotics and 2-Aminoimidazole-Derived Antibiofilm Agents
Authors: Rogers Steven A. , Huigens Robert W. , Cavanagh John , Melander Christian
Published: March 2010

2-Aminoimidazoles are an emerging class of small molecules that possess the ability to inhibit and disperse biofilms across bacterial order, class, and phylum. Herein, we report the synergistic effect between a 2-aminoimidazole/triazole conjugate and antibiotics toward dispersing preestablished biofilms, culminating with a 3-orders-of-magnitude increase of biofilm dispersion toward
Staphylococcus aureus
biofilms. Furthermore, we document that the 2-aminoimidazole/triazole conjugate will also resensitize multidrug-resistant strains of bacteria to the effects of conventional antibiotics, including methicillin-resistant
Staphylococcus aureus
(MRSA) and multidrug-resistant
Acinetobacter baumannii.
Many Chromosomal Genes Modulate MarA-Mediated Multidrug Resistance in
Escherichia coli
Authors: Ruiz Cristian , Levy Stuart B.
Published: March 2010

Multidrug resistance (MDR) in clinical isolates of
Escherichia coli
can be associated with overexpression of
marA
, a transcription factor that upregulates multidrug efflux and downregulates membrane permeability. Using random transposome mutagenesis, we found that many chromosomal genes and environmental stimuli affected MarA-mediated antibiotic resistance. Seven genes affected resistance mediated by MarA in an antibiotic-specific way; these were mostly genes encoding unrelated enzymes, transporters, and unknown proteins. Other genes affected MarA-mediated resistance to all antibiotics tested. These genes were
acrA
,
acrB
, and
tolC
(which encode the major MarA-regulated multidrug efflux pump AcrAB-TolC),
crp
,
cyaA
,
hns
, and
pcnB
(four genes involved in global regulation of gene expression), and the unknown gene
damX
. The last five genes affected MarA-mediated MDR by altering
marA
expression or MarA function specifically on
acrA
. These findings demonstrate that MarA-mediated MDR is regulated at multiple levels by different genes and stimuli, which makes it both complex and fine-tuned and interconnects it with global cell regulation and metabolism. Such a regulation could contribute to the adaptation and spread of MDR strains and may be targeted to treat antibiotic-resistant
E. coli
and related pathogens.
A comparison of flower-visiting insects to rare Symphyotrichum sericeum and common Solidago nemoralis (Asteraceae)
Authors: Robson Diana Bizecki
Published: March 2010

Flower-visiting insect activity to the rare Symphyotrichum sericeum (Vent.) G.L. Nesom and the common Solidago nemoralis Ait. var. longipetiolata (Mack. & Bush) Pal. & Steyerm. was examined to detect compositional and temporal similarities. A hand pollination experiment was conducted to determine whether pollen was limiting seed set. Of the 31 insect taxa that visited these plants, Bombus bifarius Cresson was the most common visitor to both species. More insect visitors of the Halictidae and Bombyliidae were received by S. sericeum than S. nemoralis, which received more visitors of the Syrphidae and Tachinidae. The insect visitation rate was not significantly different between the two plant species. Solidago nemoralis was visited by fewer insect taxa per day than S. sericeum, but the constancy of its visitors was higher. The insect visitor composition changed over time, with B. bifarius ignoring S. sericeum plants initially, then visiting them more frequently as the number of receptive S. nemoralis capitula declined. Hand pollination increased seed set in the earliest flowering capitula of S. sericeum, but not for those flowering during the peak. This research shows that the quantity of insect visits to the rare plant is comparable with that of the common plant but that pollination quality may be lower, particularly for early blooming capitula.
FABRICATION AND OPTICAL PROPERTIES OF METAL-COATED NON-CLOSE-PACKED COLLOIDAL CRYSTALS
Authors: MUSTONEN ANNA , LIPSANEN HARRI
Published: March 2010

We present a study of optical transmission through metal-coated non-close-packed colloidal crystals. The arrays combine semi-shell particles and circular holes simultaneously. We show that the optical response of the structures can be tuned by altering the size of the semi-shell particles and holes. The non-close-packed colloidal crystals were fabricated using modified nanosphere lithography and reactive ion etching.
MORPHOLOGICALLY CONTROLLED ELECTRODEPOSITION OF ZnO AND Cu2O BY THE COLLOIDAL CRYSTAL TEMPLATE METHOD
Authors: FU MING , ZHAO AILUN , ZHOU JI , HE DAWEI , WANG YONGSHENG
Published: March 2010

This paper presents a versatile method for fabricating 3D macroporous materials using colloidal crystals as the templates. ZnO and Cu2O were deposited by the electrochemical method via the colloidal crystal template. Not only were 3D inverse opal structures and 2D nanobowls fabricated, but nanoparticles with a controlled shape were also prepared. Morphological controls via colloidal crystal templating are discussed.
ULTRAVIOLET AND BLUE UPCONVERSION EMISSIONS OF NaYF4:La3+(Er3+, Tb3+) NANOCRYSTALS UNDER 532 NM LASER EXCITATION
Authors: LIANG HUIJUAN , WU LI , CHEN GUANYING , LIU YUAN , LI LONG , ZHANG ZHIGUO
Published: March 2010

The upconversion (UC) fluorescences from 300 nm to 500 nm of NaYF4:La3+(Er3+, Tb3+) nanocrystals under 532 nm laser excitation were investigated at room temperature. These UC luminescences have potential applications in UC lasers.
STATISTICAL COMPARISON OF METHODS TO ESTIMATE THE ERROR PROBABILITY IN SHORT-READ ILLUMINA SEQUENCING
Authors: ABNIZOVA IRINA , SKELLY TOM , NAUMENKO FEDOR , WHITEFORD NAVA , BROWN CLIVE , COX TONY
Published: March 2010

As was the case in the beginning of the sequencing era, the new generation of short-read sequencing technologies still requires both accuracy of data processing methods and reliable measures of that accuracy.

Inspired by the classic of the genre, the Phred method, we generalized those findings in the area of base quality value calibration. We introduce a simple, straightforward statistically established way to measure the performance of a calibrator, and to find an optimal way to assess its reliability. We illustrate the method by assessing the performance of several calibrators/predictors for Illumina, Genome Analyser 2 (GA2) data. The choice of the best predictor is based on optimization of validity, discriminative ability and discrimination power for several candidate predictors. We applied the method on data from one experimental run for genome of the phage ϕX, and found the best predictor out of ten candidates to be 'Purity', a statistics derived from corrected cluster intensities.

The source code for the comparison of the predictors is available from the authors by request.
Stealthy malware detection and monitoring through VMM-based “out-of-the-box” semantic view reconstruction
Authors: Jiang Xuxian , Wang Xinyuan , Xu Dongyan
Published: March 2010

An alarming trend in recent malware incidents is that they are armed with stealthy techniques to detect, evade, and subvert malware detection facilities of the victim. On the defensive side, a fundamental limitation of traditional host-based antimalware systems is that they run inside the very hosts they are protecting (“in-the-box”), making them vulnerable to counter detection and subversion by malware. To address this limitation, recent solutions based on virtual machine (VM) technologies advocate placing the malware detection facilities outside of the protected VM (“out-of-the-box”). However, they gain tamper resistance at the cost of losing the internal semantic view of the host, which is enjoyed by “in-the-box” approaches. This poses a technical challenge known as the semantic gap.

In this article, we present the design, implementation, and evaluation of
VMwatcher
—an “out-of-the-box” approach that overcomes the semantic gap challenge. A new technique called guest view casting is developed to reconstruct internal semantic views (e.g., files, processes, and kernel modules) of a VM nonintrusively from the outside. More specifically, the new technique casts semantic definitions of guest OS data structures and functions on virtual machine monitor (VMM)-level VM states, so that the semantic view can be reconstructed. Furthermore, we extend guest view casting to reconstruct details of system call events (e.g., the process that makes the system call as well as the system call number, parameters, and return value) in the VM, enriching the semantic view. With the semantic gap effectively narrowed, we identify three unique malware detection and monitoring capabilities: (i) view comparison-based malware detection and its demonstration in rootkit detection; (ii) “out-of-the-box” deployment of off-the-shelf anti malware software with improved detection accuracy and tamper-resistance; and (iii) nonintrusive system call monitoring for malware and intrusion behavior observation. We have implemented a proof-of-concept VMwatcher prototype on a number of VMM platforms. Our evaluation experiments with real-world malware, including elusive kernel-level rootkits, demonstrate VMwatcher's practicality and effectiveness.
Forming-Less Unipolar TaOx-Based RRAM with Large CC-Independence Range for High Density Memory Applications
Authors: Zhang Lijie , Zhu Minghao , Huang Ru , Gao Dejin , Kuang Yongbian , Shi Congyin , Wang Yangyuan
Published: March 2010

In this paper, a unipolar resistive change memory (RRAM) based on TaOx has been successfully fabricated. The fabricated unipolar RRAM exhibits lower switching voltages without any forming process, fast switching speed, good retention performance even under high temperature baking and stable cycling behavior. Multi-level of data storage can also be achieved by voltage control during the reset process. In addition, the current compliance (CC) effect on the behavior of the device has also been investigated. Based on the measurements, the switching voltages/currents and the low resistance state (LRS) of the device have little dependence on CC, which can effectively simplify RRAM circuit design. Resistive switching polarity dependence on the bi-layer structure has also been analyzed with comparative experiments.
Review on Methods for Trench MOSFET Gate Oxide Reliability and Switching Speed Improvement
Authors: Ng Hong Seng
Published: March 2010

In high density vertical trenched power double-diffused metal oxide semiconductor (DMOS), the trench width (CD) continually shrinks as driven by market for low cost and longer battery lifetime. Subsequently, this imposes technical challenges to keep high breakdown voltage without affecting other performances such as gate charge and on-state resistance. This paper discusses some of the technical challenges faced and suggested solutions. The various methods to improve the trench oxide uniformity and trench corner profile are also presented through experimental data. Different methods to thicken the trench bottom oxide to reduce gate-to-drain capacitance (Cgd) and eliminate the oxide weak points are introduced. This paper also reviews advanced industrial developments to increase the device switching speed as well as breakdown voltage.
Junction Technology for 2D and 3D Devices: Self Regulation Plasma Doping SRPD
Authors: Mizuno Bunji
Published: March 2010

For near future 2D and 3D devices, Self-Regulation Plasma Doping (SRPD) with B2H6/Helium gas plasma has been developed to provide precisely controllable ultra-shallow junctions for planar FETs and conformal junctions for fins at the same time. Manufacturing level of process controllability (<1% on dose) and advantage on the dvices of SRPD have been achieved with FinFETs and planar pMOSFETs.
Fabrication and Characterization of Polycrystalline SiC Comb Resonators
Authors: Ning Jin , Zhao Yongmei , Sun Guosheng , Han G.W. , Si C.W. , Yang F.H.
Published: March 2010

A polycrystalline 3C silicon carbide comb microelectromechanical(MEMS) resonator has been designed and demonstrated. An optical measure method was used to characteristic them under different pressure. The resonance frequency of the SiC resonator is about 512.5kHz. When the measure pressure decreased from atmosphere to 11Pa, the quality factor of the resonator increased from 682.92 to 3416.67.
Comparison of High Voltage (200-300 Volts) Lateral Power MOSFETs for Power Integrated Circuits
Authors: Sheu Gene , Lin Yin-Huang , Tseng Wen-Chin , Yang Shao-Ming , Chen Chao-Nan , Guo Yu-Feng
Published: March 2010

A variety of lateral high-voltage devices has been investigated in the range of 200V to 300V applications in power ICs, including reduced surface electric field (RESURF), laterally double diffused MOS (LDMOS) transistor, lateral variation doping (LVD), vertical linear doping (VD) and linear thickness (LT) devices. These devices are described and compared on the basis of on-state, off-state breakdown voltages, on-state resistance (Rdson), safe operation area (SOA) and Baliga's Figure-Of-Merits (BFOM). It is observed that for devices operating lesser than 300V, the VD LDMOS exhibits superior performance, where as higher voltage devices (≧300 V), the LT device proves to be superior. Applications arround 200 V, the VD device exhibits only a marginal improvement over the LT LDMOS device.
Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETs
Authors: Zhu Congyi , Fu Jun , Wang Yudong , Liu Zhihong , Wu Zhengli , Xu Ping , Cui Jie , Jiang Zhi , Zhao Yue , Zhang Zhaojian
Published: March 2010

In this article the impact of geometrical parameters of the dummy gate on capacitance characteristics for RF-LDMOS transistors is analyzed and studied by using a 2-D numerical TCAD process and device simulator. Firstly, the device structure and fabrication process are described. Then measured and simulated capacitance characteristics of the fabricated RF-LDMOS transistors are compared, confirming the effectiveness of the TCAD simulations. On the basis of this, further extensive simulations on the device capacitance characteristics for varying thickness of the oxide layer under and beside the dummy gate (tfox) and length of the dummy gate over n-drift region (Lf) are carried out. Based on these simulation results, the effects of the dummy gate on various capacitance components are analyzed and discussed, indicating that feedback capacitances can be effectively reduced by the introduction of the dummy gate to the device, nevertheless, at the expense of increased output and input capacitances. For this reason, the key geometry parameters of the dummy gate have to be traded off in order to optimize device design.
Analysis and Optimization of High-Voltage Devices in a BCD Process
Authors: Fu Chunxiao , Xu Fan , Cheng Yuhua
Published: March 2010

Abstract: This paper presents two-dimensional process and device(15V) simulation results and optimization of power device in a 0.35um Bipolar/CMOS/DMOS(BCD) process. Detailed device simulations and structure designs have been done. Test structures with specific considerations have been developed. With both simulation and experimental results, the optimized devices show excellent performance, which have been demonstrated with characterization results from devices on wafers from process qualification lots.
Combining 2D and 3D Device Simulations for Optimizing LDMOS Design
Authors: Lin Chin-Che , Sheu Gene , Yang Shao-Ming , Guo Yu-Feng
Published: March 2010

Lateral DMOS power devices can achieve high breakdown voltage by optimizing the two dimensional (2-D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3-D) device parameters in order to support a given breakdown voltage. In this paper, We report the effect of 3-D parameters such as the curvatures of the drain and source regions, doping density of LDMOS device with SOI (Silicon-On-Insulator) substrates based on numerical simulations and analytical solutions using cylindrical coordinates with device simulator "MEDICI" and Synopsys 3D simulator Sentaurus 2009.06-SP2 version. We stress the necessary 3D simulation for power device with racetrack, interdigitated layouts etc.
A Voltage-Type Sense Amplifier for Low-Power Nonvolatile Memories
Authors: Li Ming , Yang Li-Wu , Kang Jin-Feng
Published: March 2010

A voltage-type sense amplifier for low-power nonvolatile memories is presented against traditional current-type ones. Such a sense amplifier employs a capacitor to minimize the current for reading operations, and a negative feedback loop to increase reading reliability. A testing chip has been implemented based on 0.18μm EEPROM technology, and measurement results show that the overall current of the proposed sense amplifier is less than 1μA under low power supplies.
Outlier Detection to Assure Good Quality for Metrology Bias Acceptance Test
Authors: Yang Siyuan F. , Chien Wei-Ting K.
Published: March 2010

The quality of measurement system in semiconductor manufacturing industry has been inevitably important to assure good quality of IC products being manufactured. Metrology tool's bias acceptance test is a regular test to decide whether a tool needs re-calibration. The current practice in manufacturing industries follows the renowned "Measurement Systems Analysis (MSA) Reference Manual" by Chrysler, Ford, and General Motors. However, most practitioners ignore outlier detection on the repeated measurement data, largely due to the fact that the MSA Reference Manual does not cover the outlier detection for bias acceptance test although ISO 5725 requires the outlier detection and replacement with correct values. This article discusses the impact of the outliers if existed on the bias acceptance test and the statistical methods of outlier detection. If the outliers are not detected and replaced with correct values, the bias acceptance test could fail to reject a metrology tool with unacceptable bias. This article introduces the statistical definition of the outlier, basics of statistical criteria for outliers and possible causes for the existence of outliers. Additional methods to detect outliers besides those recommended by ISO 5725 are introduced to assure good quality for metrology bias acceptance tests.
Wafer-Area-Saving Test Structures and Measurement Method for the Characterization of Interconnect Resistance and Capacitance in Nanometer Technologies
Authors: Qin Xiaojing , Jiang Lele , Cheng Yuhua
Published: March 2010

Interconnect parasitic parameters are the dominant source for delay and noise in modern integrated circuits. Aggressive technology scaling has led to much higher resistance and larger coupling capacitance on interconnect. To predict the impact of interconnect to the circuit performance by accurately extracting electrical parameters of interconnect for circuit simulation, a novel test structure and an effective measurement method, which consumes less wafer area and hence results in lower production cost, are proposed in this paper. The method could be easily implemented for device characterization for DFM (design-for-manufacturing) applications.
Development of a MEMS/IC Design Environment for RFIC Applications
Authors: Xin Sun , Fu Zhengzhong , Cheng Yuhua
Published: March 2010

The development of MEMS/IC design environment based on SMIC 0.13um CMOS process was reported. This effort includes the development of PDK (Process Design Kit) by integrating MEMS inductor devices. The MEMS inductors can be used to design high performance RF circuit with standard CMOS devices. A low noise amplifier (LNA) circuit was designed with the PDK. The results showed that the MEMS inductors can improve the performance of the LNA circuit and the PDK can be used for Radio Frequency Integrated Circuits (RFIC) design. This work has laid a foundation for our future development of a design environment for MEMS/IC applications.
Address RF Multi-Site Test Efficiency Challenge
Authors: Ge Liang
Published: March 2010

To economically test RF device in high volume, one important approach is to make multi-site test. But some features of RF test challenges the multi-site efficiency. These challenges include the data uploading, data processing and the idle waiting behavior in semi-parallel test. In this paper, we will introduce the ATE architecture and solution which take advantage of latest CPU, DSP and HSIO technology to handle above-mentioned challenges. Thus, the good architecture achieves high efficiency multi-site RF test, lower the cost of test.
High Precision Defect Inspection & Binning
Authors: Chang Ellis , Park Allen
Published: March 2010

Wafer inspection and defect classification have been traditionally done in Fab solely using wafer level data. For processes as 45 nm and beyond, device performance has become very sensitive to process variations that include litho conditions and process-induced pattern fidelity. For example a slight mismatch in process chamber can have a drastic impact to yield. Also evaluation of OPC treatment on wafer is becoming more difficult when subtle pattern failures can be hidden in high volume of defect data. Certain defect type such as incomplete contact hole cannot be detected before etch and the occurrences can be intermittent, making it virtually impossible to detect them using random sampling [1]. In addition, Foundry Fabs need to meet the challenge of fast device characterization and quick ramp. Design-Aware inspection delivers new capability that allows Fabs to characterize device and process with higher dimension that were not possible before using the traditional approaches.
A Mathematics Model to Estimate ATE Performance Impacts on EVM Testing of RF 2G and 3G Devices
Authors: Chen Zai Man , Zhang Zhenyu , Phong Pham
Published: March 2010

Error vector magnitude (EVM) is a measure of the transceiver's modulation accuracy representing any deviation from the ideal bit location. It can fully indicate system level performance of the device. If the device meets the EVM margin specifications then it is assured that the function in the final application. That's why nowadays more and more fabless are using EVM testing in mass production to screen their RF product to achieve lower field return. While in mass production, the EVM result is the combination of both device EVM performance and test system's performance. Even if the device has a good EVM, the noisy ATE system will make the final measurement result poor so as to "kill" the good parts. This paper will provide a mathematical model to estimate how much impact will happen on the device test with ATE's specification so as to help designer to select the RIGHT ATE to test their RF products.
Reverse-Bias Electroluminescence Observation for Reliability Investigations of the InGaN LED
Authors: Chen Hsiang , Lu Tien-Chang
Published: March 2010

The reverse-bias operation of the InGaN LED device can shed a light on device reliability problems. Our goal is to use noninvasive optical characterization techniques including surface temperature measurements, 2D XRF(X-ray fluorescent) element analysis, and 2D electroluminescence measurements to visualize the leakage current distribution and examine the origin of the reverse-bias leakage current. The origin of the reverse-bias emission is attributed to imperfect metal contact caused by process variation. Hot electron induced emission due to the leakage current should be the mechanism of the reverse-bias emission from the surface defect and the imperfect contact. The light emission was proved to be relevant to reliability problems in terms of the leakage current.
Breakdown Statistics of Gate Dielectric Stacks
Authors: Suñé Jordi , Tous Santi , Wu Ernest Y.
Published: March 2010

Gate dielectrics of present interest are formed by at least two layers of different materials: an interfacial layer of SiO2-based material and a high dielectric constant (HK) layer. Accurate modeling of the BreakDown (BD) cumulative failure distribution is at the basis of any reliability assessment methodology. In dielectric stacks, this is a non-Weibull distribution which has been recently understood in the framework of the percolation theory. Here, we present a cell-based analytical percolation theory for multiple-layer insulator stacks. The model is validated by comparison with kinetic Monte Carlo simulations of percolation and with large statistical sample size BD experiments on hafnium-based HK/SiO2 stacks. Finally, this analytic model is also applied to single layer dielectrics showing progressive BD.
The Impact of Different Stress Condition Combinations on Parameters Estimations in Electromigration Tests
Authors: Ma Jinyi J. , Wang Xiaotao J. , Gong Excimer B. , Chang Venson
Published: March 2010

Electromigration (EM) is one of the major indices to evaluate the reliability performance in IC devices. From the point of view of permutation and combination, there are many combination types for temperature and current density that used to determine the model parameters (Ea and n) in EM. Fourteen types among these combinations are chosen for this study and confidence intervals for model parameters are used as theoretical criteria. The study shows the most popular stress combination type is not the best one both from theory and experiment. Also, it is found that the tight confidence interval is a trade off for either the equipment capacity or the test cycle time in choosing the stress condition combination. Further, we recommend the appropriate stress combination types to be implemented in the experiment in order to save capacity and/or shorten test cycle time with still acceptable confidence interval.
Different Interface Role in CuOx Based RRAM
Authors: Wu J.G , Zhou Peng , Lin Y.Y , Huang R. , Song S. , Zou Q. , Wu H. , Chi Min-hwa
Published: March 2010

For the embedded application of resistive switching memory using CuOx films, the differences in interfacial chemical interaction may affect filament formation and rupture processes near the electrode and hence alter the resistive switching behaviors. Al/CuxO/Cu and TaN/CuxO/Cu devices were fabricated and investigated for the memory switching characteristics, data retention and mechanism, respectively. The results show better stability, preferable endurance, and larger resistance ratio for Al electrode. An interface AlOx layer is detected by transmission electron microscopy and Auger electron spectroscopy. This layer can strongly affect the movement of oxygen vacancies. TaON was observed for TaN/CuxO/Cu device at the anode interface by X-ray photoelectron spectroscopy and transmission electron microscopy, which is believed to play a key role in the resistance transition. The physics behind this phenomenon of reactive top-electrode is revealed. The interface filament/charges trapping dominated model is proposed to clarify the electrical characteristics of the top-electrode/oxide reactions
STI Liner Evolution as the CMOS Scaling Down
Authors: Zhao Zhibiao , Tang Ji Yue , Fang Zhijun , Zhao Ganming
Published: March 2010

As the planar CMOS transistor devices scaling down, a lot of original process have to be optimized, developed or changed to meet the evolutional requirement, and the new process elements were continuously implemented into the manufacture. The STI-liner is one of the processes from the STI module, which comes after the trench etch and before the trench gap-fill, to provide an excellent interface and good adhesion between the silicon and the oxide. While the device scaling down, some device issues, such as, the incident of dislocations which impacted on the device leakage current, the dopant segregation which result in the threshold voltage variation and impact the inverse narrow width effect (INWE) and the gate oxide integrity (GOI), etc, are associated with the STI module and can be improved by the STI-liner process. The STI liner process is evolved from the furnace oxidation, the dry RTO, the nitrided oxide liner to the ISSG.
Improvement of Characteristic Ramped Voltage Breakdown in Multi-Level Cu/SiOC Low k Integration
Authors: Chen Yuwen , Zou Johnston , Chen Steven , Bei E. , Wang Jimmy
Published: March 2010

As the interconnect RC delay becomes a dominant factor in determining the overall circuit performance, the advantages of Cu and low k materials become more re-markable. The introduction of new materials is driving significant research of the impact of these materials on the reliability. Active investigation is focus on the im-pact of back end of line (BEOL) processing on Cu/low k reliability. Until now, the investigation mainly focuses on the EM and SM, etc. In this paper, inter layer di-electric (ILD) characteristic ramped voltage breakdown (VBD) of multiplayer Cu/SiOC interconnect was investigated. It was found the breakdown performance is highly process-related. Some process/integration changes have significant influence on VBD performance, such as some specific treatment to Cu surface, application of capping layer, and modified deposition process of etch stop layer (ESL), etc.
Mechanism Analysis of Plasma Charging Damage on Gate Oxide for HDP FSG Process
Authors: Li Xi , Wang Peng , Bu Jiao , Liu Yuwei , Cao Gang , Shi Yanling , Liu Chunling , Li Fei , Sun Lingling
Published: March 2010

For its stability and relatively lower K value, FSG (fluorine silica glass) is widely used in 0.18μm and below VLSI process. In this paper, the plasma charging damage on 30Aå gate oxide from the high-density-plasma deposition (HDP) of FSG is investigated. Positive and negative nondestructive JTDDB stress is applied to fresh transistors to simulate the plasma charging current. According to the results comparison, positive plasma stress at the end of the HDP-CVD FSG deposition is found to be the major cause of damage. The damage is located near the Gate/SiO2 interface. By increasing the FSG thickness, the damage is effectively suppressed.
Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC Product
Authors: Zhang Guan-Qun , Gu Athics , Lin Yi-Hui , Sun Peng , Zhang Jiwei , Chiu Wen-Pin , Lin Paul-Chang , Xing Cheng
Published: March 2010

In advanced BEOL process, metal defect reduction plays an important role for Cp yield improvement. "Crown defect" is one of the killer defects. It develops in Litho process, forms after Aluminum etching, and finally turns out to be ring-type Al2O3 residue. Aluminum grain size is strongly related with crown defect performance. Especially for thick Aluminum film (>3μm), which is widely applied on high voltage power management IC product, it is a big challenge to control grain size and keep a relatively uniform film surface. In this paper, a study of the relationship between Aluminum grain size and crown defect is presented. Also, a novel approach to control the grain size is shown to reduce the crown defect for Cp yield improvement.
GOI Improvement in 65nm Sacrificial Oxide Free Process Integration
Authors: Deng Daniel Y. , Ren H.-R. , Fan Q. , Ho H.-M. , Xu Q. , Zhang Z.-Y. , Zheng K. , Wu Y.-J. , Gan Z.-H. , Ning X.-J.
Published: March 2010

GOI (Gate Oxide Integrity) improvement in 65nm SAC OX (Sacrificial Oxide) free process integration was studied in this paper. After studying the effects of various processes in STI (Shallow Trench Isolation) module with SAC OX free scheme on GOI, it was found that the dominant process that could degrade GOI was the STI HDP (High Density Plasma) gap fill process. STI HDP gap fill process could cause Si damage on AA corners, also named as AA clipping, which will result in irregular corners and hence a thinner gate oxide formation at imperfect AA corners. This was observed by a TEM (transmission electron microscopy) study. In SAC OX free scheme, the exposed AA Si corners that were damaged during the HDP process did not get consumed and repaired while they would have gotten in the scheme with SAC OX and hence degraded GOI. By optimizing the STI gap fill processes and hardware configuration, the AA clipping can be greatly reduced and GOI can be improved to the required level.
Physical and Electrical Characteristics of the High-K Er2O3 Polyoxide Deposited on Polycrystalline Silicon
Authors: Kao Chyuan Haur , Chen Hsiang , Chiu Jing-Siang
Published: March 2010

In this study, the high-k Er2O3 gate dielectrics were deposited on polycrystalline silicon were fabricated for the first time. The as-deposited samples treated at different annealing temperatures were examined by applying different material and electrical analysis. All the electricalanalysis and structural investigation concluded that annealing temperature at 800°C was the optimal condition that formed the well-crystallized Ta2O5 film. The high-k Er2O3 dielectric will be promising for future generation of electronic device applications.
Simultaneous Double Side Grinding of Silicon Wafers: A Further Investigation into Grinding Marks Pattern
Authors: Li Zhichao , Lin Bin , Sun Wangping , Zhang Xiaohong
Published: March 2010

Simultaneous double side grinding (SDSG) is one of the state-of-art processes to flatten silicon wafers. A critical issue in SDSG is the grinding marks pattern. In this paper, a mathematical model is developed to study the grinding marks pattern in SDSG of silicon wafers. The model is used to simulate the grinding marks pattern and predict the number of wafer rotations needed to generate the grinding marks pattern. One practical application of the model is also discussed.
A New Survey of Routing Algorithms in Ad hoc Networks
Authors: Hosseini Nazhad Ghazani Seyed Hossein , Jabari Lotf Jalil , Alguliev Rasim
Published: March 2010

In this paper, we compared the reactive and proactive protocols, and discussed that which type of protocols are suitable for which type of networks. The results are interesting. We choose newly protocols for discussed.
Mask and Wafer Topography Effects in Optical and EUV-Lithography
Authors: Erdmann Andreas , Shao Feng , Evanschitzky Peter , Fühner Tim
Published: March 2010

The detailed understanding and accurate modeling of light diffraction from (sub-) wavelength size features on lithographic masks and wafers becomes indispensable for the development and optimization of advanced lithographic processes. This is demonstrated by two examples: optical proximity correction (OPC) for optical/EUV masks and wafer topography induced linewidth variations in double patterning.
Regularization in Inverse Lithography: Enhancing Manufacturability and Robustness to Process Variations
Authors: Lam Edmund
Published: March 2010

Inverse lithography, as a mask design tool, has the capability of producing unintuitive patterns with topologies much different from those obtained from either rule-based or model-based optical proximity correction (OPC). These mask patterns may have the advantage of producing circuit patterns that are otherwise very difficult to achieve; on the other hand, the mask may be too complicated that renders it impossible to manufacture, or that the cost of producing it would be astronomical. There is also good likelihood that the resulting circuit patterns may be severely affected when there are process variations, such as in focus or dose. In this work, we discuss how various regularization techniques may be employed to tackle these two problems: simplifying the mask pattern in an inverse lithography process, and incorporating robustness explicitly in the design algorithm.
From Computational Lithography to Computational Inspection: Inverse Lithography Technology (ILT) and Inverse Inspection Technology (IIT)
Authors: Pang Linyong , Peng Danping , Hu Peter , Chen Dongxue , Cecil Tom , He Lin , Xiao Guangming , Tolani Vikram , Dam Thuc , Baik KiHo , Gleason Bob
Published: March 2010

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.
ArF Scanning Exposure Tool Using High NA Projection Lens
Authors: Cheng Jianrui
Published: March 2010

A prototype of ArF scanning exposure tool using a projection lens has been developed by SMEE. As the first lithography tool, the maximum numerical aperture is 0.75 and the maximum coherence factor of illumination system is 0.88 for the maximum numerical aperture. The illuminator provides continuously variable conventional and off-axis illumination mode to improve the resolution. The design concepts of synchronous scanning are researched. The configurations and actual data of the system will be shown and discussed.
Atomic Scale Overlay Control
Authors: Smith Nigel P. , Dasari Prasad , Li Jie
Published: March 2010

We report scatterometry overlay measurements data from a set of twelve test wafers, using four different target designs. The TMU of these measurements is under 0.4nm, within the process control requirements for the 22nm node. Comparing the measurement differences between targets and with image-based overlay data indicates the presence of systematic and random measurement errors that exceed the TMU estimate.
Study on Circle Defect Induced by TARC (Top Anti-Reflective Coating) Bubbles
Authors: Wang Eric , An Petros , Shu Andy , Lv David , Chen Zhongkui , Gao Joe , Lin Alien , Seo JK
Published: March 2010

Although TARC is widely used in semiconductor photolithography processes, the understandings of TARC related defects are still far from completeness. In this paper, the root causes and corrective actions of TARC related circle defect were studied. The results showed that the circle defect was induced by TARC bubbles and could be significantly decreased or totaly removed by using several different treatments. Among these treatments, the optimization of TARC coating process by adjusting the spin speed at the final dry step displayed more attractive results. In addition, the TARC thickness, profile, uniformity as well as the related wafer CD (critical dimension) uniformity by applying the new TARC coating recipe were carefully checked and did not show any deterioration.
CMP Process Technology in TSV Application
Authors: Wang Yuchun , Gage Max , Xia Sherry , Tu Wen-Chiang , Karuppiah Lakshmanan
Published: March 2010

Through-silicon via (TSV), an emerging technology for 3D IC manufacturing, involves fabrication of vertical vias through the wafers. The two methods commonly used involve "via-first" and "via-last" process flows. While the via-last approach appears to be relatively simple with minimum impact to circuit layout, the via-first scheme may ultimately offer more benefits by enabling a higher density of I/O's. This paper describes the rapid progress made in the process integration of CMP for TSV, to offer unique advantages especially in the via-first approach where planarity is critical. In addition, with backside polishing after wafer thinning, the CMP process ensures a smooth surface finish for bonding and provide extra process knobs to correct the non-uniformity in via depths caused by preceding via etch and silicon grinding processes.
Application and Advantage of CMP in Silicon Wafer Reclaim
Authors: Tan Changxing , Xiong Shiwei , Zhao Runtao , Xu Ying , Wang Xucheng , Zhang Weifeng , Wang Shan
Published: March 2010

In this paper, a silicon CMP process has been developed inside semiconductor fabrication to reclaim bare silicon wafers for cost and time reductions. Firstly, the high level defect after CMP was encountered and mainly particle; after related polishing and cleaning processes were optimized, the defect count was much reduced but still higher than the specification; finally, the defect count was dramatically decreased and met the specification by adding a surfactant (TMAH) in polishing. The effect of surfactant on defect reduction is also discussed in this paper.
Novel Approach for W Loss Defect Prevention on WCMP Re-Clean Process
Authors: Zhang Jian , Wang Zhe , Wen Jing , Wu Duan-Yi , Lin Paul-Chang , Xing Charles
Published: March 2010

With the device dimension rapidly shrinking, Tungsten Chemical Mechanical Polishing (WCMP) becomes one of the critical manufacturing processes for multi-layer interconnection of ULSI (ultra large scale integrated) circuits. The effectiveness of Post-CMP cleaning is one of critical step for particles removal and product Cp yield improvement. WCMP re-clean process is a general way to further reduce particles on high-defect-density impacted wafers in IC manufacturing. However, W loss defect could be generated frequently due to the extra re-clean process introduced in post WCMP step for sub-0.13um devices. In this paper, the mechanism of W loss defect after re-clean process is studied. Also one novel approach is proposed to prevent W loss and improve product CP yield.