(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs
Authors: Pizzanelli Riccardo , Prates Rhaycen , Pavanello Marcelo Antonio , de Souza Michelly 
Published: September 2023

Nanowire transistors constitute an alternative for the continuous downscaling of MOSFETs. These devices present a trigate architecture featuring the fin width (WFIN) and height (HFIN) with similar dimensions, in the order of tenths of nanometers [1], which improves the gate control on the channel charges, reducing short-channel effects (SCE) and improves electrical properties in both digital and analog applications [1].

Junctionless nanowire transistors (JL) are easier to fabricate than inversion-mode MOSFETs [2]. They also are less vulnerable to the occurrence of SCE, which is one of the main concerns when downscaling the MOS transistor [3, 4]. Unlike inversion mode (IM) transistors, the junctionless device is made with a heavily doped silicon layer with the same doping type from source to drain [2, 5]. To lower the series resistance, the source and drain receive an additional doping step to increase their concentration.

Although JL transistors are a good alternative for the continuous downscaling of MOS transistors, they still have their basic operation like any other transistor MOSFET. Therefore, it is not completely immune from SCE, such as Drain-Induced Barrier Lowering (DIBL) effect.

In this work, a comparison between the DIBL effect in junctionless and inversion-mode nanowire transistors is performed. Experimental results at room and high temperatures are presented for devices with different channel widths.

The JL and IM nanowire transistors used in this work were fabricated at CEA-Leti, as described in reference [6]. Devices with 10 parallel channels and channel length (L) of 40 nm and 100 nm were measured, fin width (WFIN) of 12 nm, 17 nm, 22 nm, and 42 nm. Two different values of drain voltage (VD) were applied for all devices, VD1 = 40 mV and VD2 = 800 mV. Finally, the DIBL has been calculated as DIBL=|VT2 – VT1| /(VD2 – VD1). The threshold voltage in both VD has been extracted as described in ref. [7].

The analysis for DIBL as a function of fin width is shown in Figure 1(A). For devices with L=100nm, no SCE has been observed and all devices present Subthreshold Slope (SS) close to the theoretical limit. Also, for WFIN up to 22 nm, DIBL is the same both for IM and JL nanowires. When downscaling the length to 40 nm, despite of DIBL increase for all devices, no degradation on SS is seen for JL, whereas IM devices exhibit SS>82mV/dec. Considering reasonable characteristics, i.e., DIBL=100mV/V and S=80 mV/dec [8], except from WFIN=42nm, all JL devices meet these requirements, whereas no IM nanowire with L=40 nm could be used. Even if maximum allowable DIBL were increased to 120mV/V, only the narrowest IM with L=40nm would be acceptable.

Aiming to verify the influence of the temperature on the DIBL, Figure 1(B) shows the variation of DIBL in relation to room temperature for IM and JL nanowires with L=100nm and WFIN=12nm, which have similar DIBL at 300K. One can see that DIBL variation with temperature in the IM device is larger than in JL. While the IM transistor presented a DIBL variation of 0.15(mV/V)/K, for the JL one, it is 0.11(mV/V)/K. These results indicate that apart from the good immunity to SCE, JL nanowires are less susceptible to DIBL variation with temperature.

Acknowledgements

The authors thank financial support from CAPES, CNPq and FAPESP.

References

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Figure 1