bluuebunny/crossref_metadata_2025 huggingface dataset:
Properties of SiO2/4H-SiC Interfaces with an Oxide Deposited by a High-Temperature Process
Authors: Vivona Marilena , Fiorenza Patrick , Iucolano Ferdinando , Severino Andrea , Lorenti Simona , Roccaforte Fabrizio
Published: May 2017

This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.
Improved 4H-SiC N-MOSFET Interface Passivation by Combining N2O Oxidation with Boron Diffusion
Authors: Cabello Maria , Soler Victor , Mestres Narcis , Montserrat Josep , Rebollo José , Millán José , Godignon Philippe
Published: May 2017

A new oxide configuration for the development of high mobility 4H-SiC lateral MOSFETs is proposed in this work. The oxide is composed by a rapid thermal oxidation (RTO) in N2O environment, a Boron diffusion into the SiO2 and a PECVD TEOS deposited oxide, in order to improve the interface quality. The obtained MOSFETs show very high peak field effect mobilities ranging from 80 up to more than 170 cm2V-1s-1 in MOSFETs with higher channel length than the tested transistors. The physical (SIMS) and electrical analysis of the oxide and SiC surface reveals that the Boron has not diffused into the SiC. This is most probably due to the high concentration of Nitrogen at the interface generated during the N2O oxidation.
Enhanced Low-Temperature Oxidation of 4H-SiC Using SrTi1-xMgxO3-δ
Authors: Li Li , Ikeda Akihiro , Asano Tanemasa
Published: May 2017

SrTi1-xMgxO3-δ, an oxidation catalyst, is employed to produce active oxygen species in an oxidation furnace and to enhance oxidation of 4H-SiC at low temperatures. The linear rate constant of the oxidation model at the 4H-SiC (0001)-Si surface at 800~900 °C is enhanced by two orders of magnitude in comparison to the conventional dry oxidation. The catalytic oxidation is, therefore, able to for a gate oxide at temperatures as low as 800°C. Interface state density in the energy range of 0.2~0.5 eV from the conduction band edge of the 4H-SiC oxidized with catalyst at 800°C is almost same as the one oxidized using the conventional dry oxidation at 1100 °C.
Demonstrating the Instability of SiC Ohmic Contacts and Drain Terminal Metallization Schemes Aged at 300 °C
Authors: Hamilton Dean P. , Hindmarsh Steven A. , Li Fan , Jennings Michael R. , Russell Stephen , McMahon Richard A. , Mawby Philip  Andrew
Published: May 2017

The long-term thermal stability of the drain contacts of three different commercially available SiC MOSFET devices has been determined at a storage temperature of 300 °C. Existing literature suggests that, at this temperature, the nickel silicides associated with ohmic contact creation should be stable, but this was found not to be the case. Our TEM and EDX work revealed silicide phase transformations, further silicide growth and severe thermally-driven degradation of the drain contact metallization stack on top of the silicide layers. We attribute this instability and growth of the silicides to the high storage temperature and large supply of nickel atoms available from the metal stack. The nickel atoms diffuse and decompose the original silicides to enable the formation of a new low temperature Ni32Si12 phase, and slowly decompose the SiC substrate to form additional nickel silicide.
Evaluation and Reduction of Epitaxial Wafer Defects Resulting from Carbon-Inclusion Defects in 4H-SiC Substrate
Authors: Guo Ling , Kamei Koji , Momose Kenji , Osawa Hiroshi
Published: May 2017

In this study, we investigated the epitaxial surface defects resulting from the carbon-inclusion defects in 4H-SiC substrate. Most carbon-inclusion defects developed into one of three types of epitaxial surface defects under normal epitaxial growth conditions. Among them, we found a regular hexagonal pit by high-resolution microscopy, which we regarded as a large-pit defect, and which had an adverse impact on the reverse electrical characteristics of Schottky barrier diodes. Conversion of a carbon-inclusion defect to a large-pit defect or a triangular defect could be reduced by reducing the C/Si ratio.
Effect of Annealing on the Characteristics of Ti/Al Ohmic Contacts to p-Type 4H-SiC
Authors: Tang Yi Dan , Shen Hua Jun , Zhang Xu Fang , Guo Fei , Bai Yun , Peng Zhao Yang , Liu Xin Yu
Published: May 2017

Ti/Al contacts deposited on p-type epilayer doped with Al at 2×1019 cm-3 are reported. The current-voltage curves of Ti/Al contacts annealed at different temperatures from 800 to 1000 °C were measured, which provided the specific contact resistances (SCRs) of 6.59×10-5 Ω/cm2 and 7.81×10-5Ω/cm2 after annealing at 900°C for 5min and 950°C for 2min, respectively. The microstructures of Ti/Al contact on P-type 4H–SiC were investigated by X-ray diffraction (XRD). The results of XRD show that the phases of Ti3SiC2 was formed at the metal/SiC interface after annealing, which could be effective to ohmic contacts on P-type 4H-SiC. The quantitative phase analysis were also discussed, which show that the phase composition of Ti3SiC2is key factor for low resistance to P-type 4H–SiC. Moreover, simulations proved that the gradual Ti3SiC2ISL reduces or eliminates the effective barrier height at the metal/Ti3SiC2/p-type and may also contribute to low contact resistivity.
An Electrical and Physical Study of Crystal Damage in High-Dose Al- and N-Implanted 4H-SiC
Authors: Fisher Craig A. , Esteve Romain , Doering Stefan , Roesner Michael , de Biasio Martin , Kraft Martin , Schustereder Werner , Rupp Roland
Published: May 2017

In this paper, an investigation into the crystal structure of Al-and N-implanted 4H-SiC is presented, encompassing a range of physical and electrical analysis techniques, with the aim of better understanding the material properties after high-dose implantation and activation annealing. Scanning spreading resistance microscopy showed that the use of high temperature implantation yields more uniform resistivity profiles in the implanted layer; this correlates with KOH defect decoration and TEM observations, which show that the crystal damage is much more severe in room temperature implanted samples, regardless of anneal temperature. Finally, stress determination by means of μRaman spectroscopy showed that the high temperature implantation results in lower tensile stress in the implanted layers with respect to the room temperature implantation samples.
4.5 kV SiC Junction Barrier Schottky Diodes with Low Leakage Current and High Forward Current Density
Authors: Schoeck Johannes , Buettner Jonas , Rommel Mathias , Erlbacher Tobias , Bauer Anton J.
Published: May 2017

High-voltage 4H-SiC Junction Barrier Schottky diodes with a reverse breakdown voltage of over 4.5 kV and a turn-on voltage below 1 V have been fabricated. They achieved a forward current of 5 A at a forward voltage drop of 1.8 V and 20 A at 4.2 V. A low reverse leakage current of 0.3 μA at 1.2 kV and 37 μA at 3.3 kV was measured. The chip size was 7.3 mm x 7.3 mm, the active area 0.25 cm2 and the diode was able to handle a repetitive pulse current density of over 300 A/cm2 without degradation. Floating field rings in combination with a field-stop ring were used as edge termination to reach 73 % of the theoretical breakdown voltage. The epitaxial layer was 32 μm thick, with a nitrogen doping concentration of 1 x 1015 cm-3. The JBS diodes have been manufactured in a 100 mm SiC prototyping line, using well established processing technology, to achieve cost-efficient devices.
Simulation of 4H-SiC Trench Junction Barrier Schottky Diodes with High-k Dielectrics
Authors: Yang Shuai , Song Qing Wen , Tang Xiao Yan , Zhang Yi Meng , Zhang Yu Ming , Zhang Yi Men , Yuan Hao , Sun Qiu Jie
Published: May 2017

In this paper, a novel 4H-SiC trench JBS (TkJBS) with high-k semi-insulating polycrystalline silicon (SIPOS) is proposed. By adopting a new high-k dielectrics-trench structure, the peak electric field at the corner of P+ region (COP) in Silicon Carbide (SiC) can be weakened significantly, and the device breakdown voltage can be enhanced significantly. SiC TkJBS has a 60.7% higher breakdown voltage (BV) and a 110.6% higher Baliga’s figure of merit (BFOM) than the conventional SiC JBSs, and the surface electric field (Esf) of the SiC TkJBS is 0.73 MV/cm lower than it at breakdown voltages, resulting in a much lower tunneling current (Ir). The reverse recovery characteristics of SiC TkJBS are also slightly better than those of the SiC JBS. It is indicated that SiC TkJBS is a promising candidate for next-generation high power diodes.
6.5 kV 4H-SiC PiN Diodes without Bipolar Degradation
Authors: Bu Yuan , Yoshimoto Hiroyuki , Konishi Kumiko , Shima Akio , Shimamoto Yasuhiro
Published: May 2017

We designed, fabricated and evaluated 6.5 kV SiC PiN diodes. In order to suppress process-induced basal plane dislocation (BPD) in SiC PiN diodes, we improved the fabrication processes. The Ir-Vr measurements showed that the breakdown voltage was over 9 kV at room temperature (25 °C). The leakage currents (Ileak) at 6.5 kV are as low as 5.9×10-6 mA/cm2 (25 °C) and 9.7×10-5 mA/cm2 (150 °C). The maximum recovery loss among our switching test results was 6.7 mJ at 150 °C, 60 A. Moreover, the diodes fabricated on BPD-free area are very stable during applying 20 A current for 8~1000 h. Photoluminescence (PL) observation and KOH etching indicated that no BPD generated during improved fabrication processes.
Al+ Ion Implanted 4H-SiC Vertical p+-i-n Diodes: Processing Dependence of Leakage Currents and OCVD Carrier Lifetimes
Authors: Nipoti Roberta , Puzzanghera Maurizio , Sozzi Giovanna
Published: May 2017

The reverse and forward currents of Al+ ion implanted 4H-SiC p+-i-n diodes have been compared for identically processed devices except for the implanted Al concentration in the emitter, 6×1019 cm-3 against 2×1020 cm-3, and the post implantation annealing treatment, 1600°C/30 min and 1650°C/25 min against 1950°C/5min. The diodes’ ambipolar carrier lifetime, as obtained by open circuit voltage decay measurements, has been compared too. The devices with lower annealing temperature show lower leakage currents and higher ambipolar carrier lifetime; they also show lower current in ohmic conduction.
An Investigation into the Impact of Surface Passivation Techniques Using Metal-Semiconductor Interfaces
Authors: Bonyadi Yeganeh , Gammon Peter Michael , Sharma Yogesh K. , Baker G.W.C. , Mawby Philip  Andrew
Published: May 2017

Schottky barrier diodes (SBD) were fabricated on SiC surfaces that had been treated with different surface passivation techniques, so that metal-semiconductor analysis could be used to evaluate the quality of this surface. In this paper, we discuss the results of this study that used Current-Voltage (I-V), Capacitance-Voltage (C-V) and Current-Voltage-Temperature (I-V-T) analysis to look at the impact of untreated oxidation, Nitrous oxide (N2O) and Phosphorus Silicate Glass (PSG) treatments prior to oxide removal, and the formation of Mo, Ni and Ti diodes. While the results of this study did not reveal any consistent patterns between the different treatments, a Mo diode formed on a surface after PSG treatment, displays exceptionally low leakage (4.44×10-5 A/cm2 at 19°C; 7.26×10-4 A/cm2 at 300°C) given a low barrier height (1.27 eV). Moreover, the barrier heights extracted from C-V analysis before contact annealing show a variation across all the diodes, suggesting that the interface is greatly suffering from Fermi-Level pinning, the result of significant interface traps.
Degradation of 600-V 4H-SiC Schottky Diodes under Irradiation with 0.9 MeV Electrons
Authors: Lebedev Alexander A. , Davydovskaya Klavdia S. , Kozlovski Vitalii V. , Korolkov Oleg , Sleptsuk Natalja , Toompuu Jana
Published: May 2017

In this paper investigation of degradation 4H SiC Schottky diodes parameters after irradiation by electrons with an energy of 0.9 MeV was doine. It was determined the carrier removal rate (Vd), which amounted to 0.07 - 0.09 cm-1. It is shown that the investigated Schottky diodes retained rectifying current-voltage characteristics of up to doses ~ 1017 cm-2. It is concluded that the radiation resistance of SiC Schottky diodes is much greater than the radiation resistance of Si p-i-n diodes with the same breakdown voltages
Design Optimization of a High Temperature 1.2 kV 4H-SiC Buried Grid JBS Rectifier
Authors: Elahipanah Hossein , Thierry-Jebali Nicolas , Reshanov Sergey A. , Kaplan Wlodek , Zhang A. , Lim Jang Kwon , Bakowski Mietek , Östling Mikael , Schöner Adolf
Published: May 2017

1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 225ºC is analyzed and measured on wafer level. At 100 A/cm2 a forward voltage drop of 2 V at 25ºC and 3 V at 225ºC is achieved. At reverse voltage of 1 kV, a leakage current density below 0.1 µA/cm2 and below 0.1 mA/cm2 is measured at 25 and 225ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.
On the Influence of Active Area Design on the Performance of SiC JBS Diodes
Authors: Mihaila Andrei , Minamisawa Renato Amaral , Knoll Lars , Sundaramoorthy Vinoth Kumar , Bianda Enea , Bartolf Holger , Alfieri Giovanni , Rahimo Munaf
Published: May 2017

This paper presents an investigation regarding the influence of the active area design on the static and dynamic performance of SiC JBS diodes. The analysis has been performed on fabricated JBS diodes, rated for 1.7kV applications. For the active area layout, both stripe and hexagonal cell patterns have been used for the implanted p+ regions.
0.97 mΩcm2/820 V 4H-SiC Super Junction V-Groove Trench MOSFET
Authors: Masuda Takeyoshi , Kosugi Ryoji , Hiyoshi Toru
Published: May 2017

We have fabricated Super Junction (SJ) V-groove trench MOSFETs (VMOSFETs), demonstrated a low specific on-resistance (RonA) of 0.97 mΩcm2 and a blocking voltage (VB) of 820 V. In the first trial, SJ structure in 4H-SiC have proved to be a good combination with MOS interface on (0-33-8) faces which keep high channel mobility in high doping concentration. We designed a protection structure called “upper p-pillar region” and demonstrated that VB lowering appeared according to its width.
1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage
Authors: Harada Shinsuke , Kobayashi Yusuke , Kinoshita A. , Ohse N. , Kojima Takahito , Iwaya M. , Shiomi Hiromu , Kitai Hidenori , Kyogoku Shinya , Ariyoshi Keiko , Onishi Yasuhiko , Kimura Hiroshi
Published: May 2017

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.
Switching Performance of V-Groove Trench Gate SiC MOSFETs with Grounded Buried p+ Regions
Authors: Saitoh Yu , Masuda Takeyoshi , Tamaso Hideto , Notsu Hiroshi , Michikoshi Hisato , Hiratsuka Kenji , Harada Shinsuke , Mikamura Yasuki
Published: May 2017

We developed V-groove trench gate SiC MOSFETs with grounded buried p+ regions. An effective reduction can be seen in the feedback capacitance (Crss) of static characteristics, and a fast switching performance was achieved. The grounded buried p+ regions were found to be an effective structure for reducing a switching loss.
Carrier Lifetime Control of 4H-SiC Epitaxial Layers by Boron Doping
Authors: Miyazawa Tetsuya , Tawara Takeshi , Tsuchida Hidekazu
Published: May 2017

An epitaxial growth technique for 4H-SiC with B doping was developed to control the carrier lifetimes of the epilayers. A linear relationship was observed between the B doping concentration and the flow rate of tri-ethyl-boron, which was used as the B doping source. A room temperature photoluminescence spectrum of a N-and B-doped epilayer showed a broad B-related peak at 2.37 eV instead of a band-edge luminescence, which indicates that the carrier recombination path was changed by the B doping. The minority carrier lifetime decreased (< 30 ns at 250°C) with increasing B doping concentration. The thermal stability of the short carrier lifetime was compared with a conventional carrier lifetime reduction method, namely an electron irradiation technique. After thermal annealing at 1700°C, the carrier lifetime of the electron irradiated epilayer recovered while that of the B-doped epilayer remained, indicating that the carrier lifetime controlled by the B doping technique was more stable against the thermal processes.
Design and Fabrication of 1400V 4H-SiC Accumulation Mode MOSFETs (ACCUFETs)
Authors: Sung Woong Je , Baliga B. Jayant
Published: May 2017

This paper presents design, fabrication, and electrical performance of 8A, 1400V 4H-SiC ACCUFETs. It is intended to provide detail discussions on channel design, edge termination technique, and electrical characteristics of high current, 1.2kV rated 4H-SiC ACCUFETs.
Next Generation Planar 1700 V, 20 mΩ 4H-SiC DMOSFETs with Low Specific On-Resistance and High Switching Speed
Authors: Zhang Q.J. , Wang G. , Jonas Charlotte , Capell Craig , Pickle Steve , Butler P. , Lichtenwalner Daniel J. , van Brunt Edward , Ryu Sei Hyung , Richmond Jim , Hull Brett , Casady Jeff , Allen Scott , Palmour John W. , Zhang Qing Chun
Published: May 2017

Due to their fast switching speed, knee-free forward characteristics, and a robust, low reverse recovery body diode, SiC MOSFETs are ideal candidates to replace silicon IGBTs in many high-power medium-voltage applications. 1700 V SiC MOSFETs have already been released to production at Wolfspeed based on its 2nd Gen technology. In this paper, we present our latest results in high voltage 4H-SiC MOSFET development. A low specific on-resistance of 4.7 mΩ⋅cm2 has been achieved on 1700 V, 20 mΩ 4H-SiC DMOSFETs at 250°C based on a 3rd generation planar MOSFET platform, which is less than half of the resistance of the previous generation devices. A detailed analysis has been carried out with respect to the static and dynamic characteristics, third quadrant conduction, and body diode reverse recovery charge, etc.
Short-Circuit Robustness Testing of SiC MOSFETs
Authors: Green Ronald , Urciuoli Damian P. , Lelis Aivars J.
Published: May 2017

This paper presents electrical results for two different commercial devices and one prototype 1.2 kV SiC power MOSFET device subject to short-circuit (SC) stress. Two failure modes were observed among the devices tested, with one mode of failure resulting in catastrophic device destruction and the other resulting in permanent damage of the insulating gate dielectric manifested as a leakage current of 400 mA. Short-circuit pulses of increasing time duration caused a reduction in the gate-to-source voltage toward the falling edge of the pulse. This phenomenon is a precursor to failure of SiC MOSFETs under SC stress, but this reduction in VGS is not known to occur in silicon-based devices. The measured short-circuit withstand times for commercial devices from group A and B MOSFETs were 8 us and 12 us, respectively. MOSFET-C devices had a withstand time of 7 us. A larger chip size improves robustness even for large values of peak short-circuit current.
Negative Bias Temperature Instability on Subthreshold Swing of SiC MOSFET
Authors: Yen Cheng Tyng , Hung Hsiang Ting , Hung Chien Chung , Lee Lurng Shehng , Lee Chwan Ying , Huang Yao Feng , Hsu Fu Jen , Chen Tzong Liang
Published: May 2017

The NBTI characteristics of SiC MOSFET were studied by the subthreshold swing. The subthreshold swing was found to be very sensitive to the starting bias of transfer curve. The increase of subthreshold swing for MOSFET with poor oxide reached 400% when the starting bias was-15V. The increase of subthreshold swing was caused by enhanced hole trapping which could be explained by the mechanism of positively charged interface states assisted hole trapping. The increase of subthreshold swing for MOSFET with improved gate oxide was reduced to about 40% when the starting bias was-20V and the value approached saturation for starting biases more negative than-10V, which can also be explained by the proposed mechanism. The increase of subthreshold swing for MOSFET with improved oxide was not sensitive to the temperature. The increase of subthreshold swing at 175°C was only 5%~7% higher than that at room temperature.
Analysis Self-Healing of Gate Leakage Current due to Oxide Traps to Improve Reliability of Gate Electrode
Authors: Sato Shintaroh , Shimizu Haruka , Shima Akio , Shimamoto Yasuhiro
Published: May 2017

To achieve robust SiC-MOSFET, reliability of the gate insulator was investigated in terms of gate electrode edge treatment. Analytical calculation showed that r should be larger than the thickness of gate insulator to relax the electric field concentration. We obtained the rounded gate edge by dry oxidation at 1000°C, while oxidation at 800°C had it sharpened. Former samples exhibited low leakage current with Time-Zero-Dielectric-Breakdown (TZDB) measurement. Ig consisted of Fowler-Nordheim (FN) tunneling current for Vg > 0, and it includes excess components for Vg < 0. We confirmed that they occurred at the gate edge and that they coursed positively charged trap centers in oxide near poly-Si/SiO2 interface which caused local barrier lowering. Electron injection removed them by tunneling/recombination process, which followed tunneling-front model.
Comparative Evaluation of Commercial 1200 V SiC Power MOSFETs Using Diagnostic I-V Characterization at Cryogenic Temperatures
Authors: Chowdhury Sauvik , Hitchcock Collin W. , Chow T. Paul
Published: May 2017

We present a comparative study of the electrical characteristics of different 1200V commercial SiC power MOSFETs at cryogenic temperatures down to 77 K. As compared to conventional silicon power MOSFETs, SiC MOSFETs show very different operating characteristics at low temperatures which is due to unique material and design parameters used in SiC MOSFETs. Of particular interest is a non-linear mixed triode/pentode-like I-V characteristic exhibited by all SiC MOSFETs at 77 K, which is demonstrated to be due to short channel effects in the constituent JFET.
Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET
Authors: Okamoto Mitsuo , Sometani Mitsuru , Harada Shinsuke , Yano Hiroshi , Okumura Hajime
Published: May 2017

The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.
Collector Conductivity Modulation in 1200-V 4H-SiC BJTs (Modeling)
Authors: Ivanov Pavel A. , Yuferev Valentin S. , Levinshtein Mikhail E. , Zhang Qing Chun , Palmour John W.
Published: May 2017

The resistance of the BJT collector layer can be sharply reduced by the effective injection of minority carriers (holes) from base to collector. As a result, the voltage drop across the BJT becomes substantially lower. The conditions under which this process can occur are the short rise time and the high amplitude of the base pulse.
Simulation Study of Switching-Dependent Device Parameters of High Voltage 4H-SiC GTOs
Authors: Ogunniyi Aderinto , Schrock James , Hinojosa Miguel , O’Brien Heather , Lelis Aivars J. , Bayne Stephen , Ryu Sei Hyung
Published: May 2017

The silicon carbide (SiC) “Super” gate turn-off thyristor (SGTO) is a viable device for high voltage and fast dI/dt switching applications. These devices are well suited for various pulsed power applications requiring high peak currents in the kilo-amp regime. The turn-on transition speed is determine by the spreading velocity, which depends on applied gate current, applied anode current density, minority carrier lifetime, and both the gate base-width and the drift region of the thyristor. The impact of device parameters on switching performance is discussed in this work.
Capacitances in 4H-SiC TSI-VJFETs
Authors: Kayambaki Maria , Vamvoukakis Konstantinos , Stavrinidis Antonis , Konstantinidis George , Kornilios Nikolaos , Zekentes Konstantinos
Published: May 2017

Internal device capacitances in 4H-SiC based devices play an important role in determining their performances. In the present work, an analysis of the capacitance measurements in 4H-SiC trenched and single-implanted (TSI) gate vertical JFET TSI-VJFETs has been undertaken. Physical parameters such as threshold voltage and the related to its value effective channel length as well as channel layer and drift layer doping profiles have been extracted. The measured internal capacitances have been modeled by various models based on device physics.
Comparison of Thermal Stress during Short-Circuit in Different Types of 1.2 kV SiC Transistors Based on Experiments and Simulations
Authors: Sadik Diane Perle , Lim Jang Kwon , Colmenares Juan , Bakowski Mietek , Nee Hans Peter
Published: May 2017

The temperature evolution during a short-circuit in the die of three different Silicon Carbide1200-V power devices is presented. A transient thermal simulation was performed based on the reconstructedstructure of commercially available devices. The location of the hottest point in the device iscompared. Finally, the analysis supports the necessity to turn off short-circuit events rapidly in orderto protect the device after a fault.
Design and Simulation of 4H-SiC MESFET Ultraviolet Photodetector with Gain
Authors: Bai Yun , Li Chengzhan , Shen Hua Jun , Yang Cheng Yue , Tang Yi Dan , Liu Xin Yu
Published: May 2017

The 4H-SiC ultraviolet detector of the MESFET structure with gain is proposed and simulated in this paper. The Schottky gate of MESFET is transparent or semi-transparent to allow more of the incident UV light to be absorbed in the device. The effect of the doping and thickness of the channel layer on the photocurrent of the 4H-SiC MESFET UV detector is simulated and the effect mechanism is analyzed. The simulation results show that the 4H-SiC MESFET exhibits photocurrent below 380 nm. And only when the channel of the 4H-SiC MESFET is in the open state there will be a gain in the detector. Shorter gate length is beneficial to improve the responsivity and the gain of the 4H-SiC MESFET UV detector. When the gate length is set to 10 μm with the channel thickness of 0.3 μm and channel doping of 1×1017 cm-3, the peak responsivity and the gain are calculated to be 12.9 A/W and 55.6 respectively.
Implementation of 4H-SiC Pin-Diodes as Nearly Linear Temperature Sensors up to 800 K towards SiC Multi-Sensor Integration
Authors: Matthus C.D. , Erlbacher Tobias , Schöfer Bernhard , Bauer Anton J. , Frey Lothar
Published: May 2017

The usability of 4H-SiC pin-diodes as nearly linear temperature sensors up to 800 K is demonstrated. Two sensor concepts were evaluated including the constant current forward bias (CCFB) concept and the integrated proportional to absolute temperature (PTAT) concept. The maximum sensitivity was 4.5 mV/K for the CCFB and an applied current density of 118 nA/cm2. Additionally, this device can be used for UV detection, too, demonstrating the feasibility of 4H-SiC multi-sensor integration.
4H-SiC PIN Diode as High Temperature Multifunction Sensor
Authors: Hou Shuo Ben , Hellström Per Erik , Zetterling Carl Mikael , Östling Mikael
Published: May 2017

An in-house fabricated 4H-SiC PIN diode that has both optical sensing and temperature sensing functions from room temperature (RT) to 550 °C is presented. The two sensing functions can be simply converted from one to the other by switching the bias voltage on the diode. The optical responsivity of the diode at 365 nm is 31.8 mA/W at 550 °C. The temperature sensitivity of the diode is 2.7 mV/°C at the forward current of 1 μA.
Chemical Stability of Si-SiC Nanostructures under Physiological Conditions
Authors: Bange Romain , Bano Edwige , Rapenne Laetitia , Labau Sébastien , Pelissier Bernard , Legallais Maxime , Salem Bassem , Stambouli V.
Published: May 2017

The fast and direct detection of small quantities of biological and chemical species is of key importance for numerous biomedical applications. Extensive research has been conducted on nanoelectronic devices that can perform such detection with high sensitivity using silicon nanowires and nanostructures. However, it was recently demonstrated that Si material suffers a lack of long-term stability in physiological environments at nanometer scale [1,2], and is hence not suited for in situ sensing of biological molecules. The results presented here are two important steps toward the realization of core-shell Si-SiC NWFETs for the detection of biomolecules in liquid media. First, we show that SiC NWs exhibit higher chemical stability than Si NWs under physiological conditions. Second, we present the successful carburation of a thin film of Si resulting in a 3.6 nm thin SiC layer.
Monolithically Integrated Solid-State-Circuit-Breaker for High Power Applications
Authors: Huerner Andreas , Erlbacher Tobias , Bauer Anton J. , Frey Lothar
Published: May 2017

In this study, the basic device features of a novel monolithically integrated solid-state-circuit-breaker (MI-SSCB) are demonstrated and analyzed using numerical simulations. Thereby, the MI-SSCB is built according to the concept of the dual thyristor. But, in comparison to similar technical solutions reported in literature, due to the advanced device structure proposed in this study a monolithically integration could be achieved for the first time.
4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics
Authors: Kuroki Shin Ichiro , Kurose Tatsuya , Nagatsuma Hirofumi , Ishikawa Seiji , Maeda Tomonori , Sezaki Hiroshi , Kikkawa Takamaro , Makino Takahiro , Ohshima Takeshi , Östling Mikael , Zetterling Carl Mikael
Published: May 2017

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.
V and Ti Doping in 4H-SiC Epitaxy for Reduction of Carrier Lifetimes
Authors: Miyazawa Tetsuya , Tawara Takeshi , Tsuchida Hidekazu
Published: May 2017

Epitaxial growth of 4H-SiC with intentional V or Ti doping was performed to obtain short minority carrier lifetimes, using VCl4 or TiCl4 as the doping sources. The doping efficiencies and quality of the epilayers were compared for H2+SiH4+C3H8 and H2+SiH4+C3H8+HCl gas systems. The addition of V or Ti in highly N-doped epilayer demonstrated very short minority carrier lifetimes of 20-30 ns at 250°C.
650V SiC Cascode: A Breakthrough for Wide-Bandgap Switches
Authors: Alexandrov Peter , Bhalla Anup , Li Zhong Da , Li Xue Qing , Bendel John , Dodge Jonathan
Published: May 2017

We present a SiC Trench JFET technology that achieves a record setting specific on-resistance (RDSA) of 0.75mohm.cm2. These SiC devices are combined with optimized low voltage MOSFETs to form co-packaged cascode transistors, which provide unprecedented performance benefits, with a clear path to direct cost parity with silicon superjunction devices. These devices are shown to be useful for all circuit topologies..
A Built-In High Temperature Half-Bridge Power Module with Low Stray Inductance and Low Thermal Resistance for In-Wheel Motor Application
Authors: Suzuki Tatsuhiro , Yamashita Mari , Mori Tetsuya , Araki Sawa , Tanimoto Satoshi , Iizuka Shota , Niitsuma Yuuta , Akatsu Kan
Published: May 2017

In order to integrate a five-phase inverter system into the limited space of an in-wheel motor, a high temperature low stray　inductance SiC half-bridge power module with a volume of about 5 ml was designed, fabricated and tested. The stray inductance in the module was calculated by an electromagnetic simulator and confirmed by measurements to be 4.4 nH. Double-pulse switching tests were conducted at temperatures up to 200°C. Thermal resistance, including that of the substrate, was calculated to be 0.153 °C/W. Fast switching capability was accomplished with an external gate resistance of 1 Ω.
High Frequency Power Supply with 3.3 kV SiC-MOSFETs for Accelerator Application
Authors: Okamura Katsuya , Takayama Ken
Published: May 2017

Pulse switching characteristics of newly developed 3.3 kV SiC-MOSFET were investigated and they were provided for a prototype switching power supply (SPS). With supply voltage of 2.5 kV and the load resistor of 100 Ω, rise time Tr and fall time Tf were 76 ns and 88 ns respectively. The SPS exhibited a successful 2.5 kV-20 A-1 MHz burst mode operation.
Switching SiC Devices Faster and More Efficient Using a DBC Mounted Terminal Decoupling Si-RC Element
Authors: Matlok Stefan , Erlbacher Tobias , Krach Florian , Eckardt Bernd
Published: May 2017

Large power modules include several parallel mounted chips per switch to raise active area and current. By the electro-mechanical connection interface, the resulting large parasitic inductance is a huge problem especially for very fast switching SiC devices. This challenge is handled by many approaches, but these recent developments require additional development effort along all aspects of the power module, e.g. smart DBC layout, low inductive top side metallization, special terminal designs or additional pins. In this paper we demonstrate an approach to enable excellent switching performance with con-ventional power module technologies: By using a recently developed monolithic silicon RC (Si-RC) element to decouple the bus bar, this problem can be solved in a very efficient way. The Si-RC element is assembled directly adjacent to the power switches on the DBC. This allows a significant reduction of the SiC chip area by minimizing the power losses caused by the switching transients from the parasitic DC-link and module inductances.
Switching Analysis for All-SiC Module
Authors: Sato Shinji , Tanisawa Hidekazu , Koui Kenichi , Takahashi Hiroki , Murakami Yoshinori , Kato Fumiki , Watanabe Kinuyo , Sato Hiroshi
Published: May 2017

In this paper, we propose a method to accurately calculate the turn-off switching loss. For that purpose, a simple analytical model is proposed in which the parasitic capacitances and stray inductances are integrated within the power module. Experiment confirmed that the turn-off loss analyzed by this model is correct.
SiC Power Devices in Impedance Source Converters
Authors: Rabkowski Jacek
Published: May 2017

This paper discusses issues related to application of SiC power devices to new family of power converters. Impedance source converters show unique feature, buck boost characteristics due to specific impedance network. Passive elements of this network may be seriously reduced with the switching frequency increase, possible with fast-switching SiC transistors. On the other hand, switching conditions of the power devices are more severe than in traditional voltage-source or current-source converters. These issues are discussed on the base of the 6kVA/100kHz quasi-Z-source inverter example.
Hydrogen Etching Influence on 4H-SiC Homo-Epitaxial Layer for High Power Device
Authors: Anzalone Ruggero , Piluso Nicolo , Salanitri Marco , Lorenti Simona , Arena Giuseppe , Coffa Salvo
Published: May 2017

The surface preparation of 4H-SiC substrate plays a crucial role for the epitaxial growth. In the present work, the Hydrogen etching influence on 4H-SiC surface of substrate before the growth process was studied. The epi-layer was grown .with a commercial low-pressure, hot-wall Chemical Vapor Deposition (CVD) reactor by Tokyo Electron Limited. The etching time of the surface was increased until three time (x3) respect with the normal value usually adopted for the growth. Photoluminescence and optical inspection analyses show a clear relationship between the etching time and the defectivity. Atomic Force Microscope (AFM) measurements also show an increase of step bunching with the etching time.
Prediction of High-Density and High-Mobility Two-Dimensional Electron Gas at AlxGa1-xN/4H-SiC Interface
Authors: Shen Zhan Wei , Zhang Feng , Dimitrijev Sima , Han Ji Sheng , Tian Li Xin , Yan Guo Guo , Wen Zheng Xin , Zhao Wan Shun , Wang Lei , Liu Xing Fang , Sun Guo Sheng , Zeng Yi Ping
Published: May 2017

This work presents theoretical demonstration of two-dimensional electron gas (2DEG) at the interface between Al0.2Ga0.8N and 4H-SiC, based on the self-consistent solution of Schrödinger–Poisson equations. High sheet carrier density of 1.1×1013 cm-2 was obtained in the Al0.2Ga0.8N/4H-SiC heterostructure, which is comparable to the electron concentration in Al0.2Ga0.8N/GaN heterostructure. The current–voltage characteristics of a high-electron-mobility transistor (HEMT), based on the Al0.2Ga0.8N/4H-SiC heterostructure, show a saturated drain current of 1.5 A/mm at the gate voltage of 2 V and the transconductance of 194 mS/mm at -3.95 V. In spite of interface-roughness scattering and phonon scattering, the 2DEG at the AlxGa1-xN/4H-SiC interface exhibits high electron mobility values of 3365 cm2/ (V·s) at 77K and 1120 cm2/ (V·s) at 300K. These results indicate that AlxGa1-xN/4H-SiC heterostructure can significantly improve the mobility of SiC based power switching devices.
High Temperature Grown Graphene on SiC Studied by Raman and FTIR Spectroscopy
Authors: Auge Manuel , Hähnlein Bernd , Eckstein Marco , Woltersdorf Georg , Pezoldt Jörg
Published: May 2017

Epitaxial graphene on semiinsulating silicon carbide was grown using a high temperature method at atmospheric pressure in argon atmosphere. The temperature dependence of the layer quality was analysed using Raman and infrared spectroscopy. It is demonstrated that infrared spectroscopy can be used as a versatile tool to access the layer count and the quality of the epitaxial grown graphene on silicon carbide. The results obtained by infrared spectroscopy correlate with the Raman measurements.
The Effect of Interfacial Charge on the Development of Wafer Bonded Silicon-on-Silicon-Carbide Power Devices
Authors: Gammon Peter Michael , Li Fan , Chan Chun W. , Sanchez Ana M. , Hindmarsh Steven A. , Gity Farzan , Trajkovic Tanya , Kilchytska Valeria , Pathirana Vasantha , Camuso Gianluca , Ben Ali Khaled , Flandre Denis , Mawby Philip  Andrew , Gardner Julian W.
Published: May 2017

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.
Influence of Growth Temperature on Site Competition Effects during Chemical Vapor Deposition of 4H-SiC Layers
Authors: Zielinski Marcin , Chassagne Thierry , Arvinte Roxana , Michon Adrien , Portail Marc , Contreras Sylvie , Juillaguet Sandrine , Peyre Hervé
Published: May 2017

After presenting an exhaustive experimental study of aluminum incorporation in epitaxial 4H-SiC and 3CSiC films grown by chemical vapor deposition (CVD), we focalize once more on what is called site competition effects. We observed that the influence of C/Si ratio on dopant (Al, N) incorporation in SiC was qualitatively different depending on whether the growth experiments were performed in “low temperature” (LT) or “high temperature” (HT) regime. Partial explanation of observed phenomena basing on thermal evolution of carbon coverage of SiC surface is proposed.
Silicon Deposition on 3C-SiC Seeds of Different Orientations
Authors: Yeghoyan Taguhi , Alassaad Kassem , Soulière Véronique , Ferro Gabriel
Published: May 2017

Silicon deposition on 3C-SiC seeds was studied as a function of seed orientations and thicknesses. The 3C-SiC seeds were grown on silicon substrates of (100), (110), (111) and (211) orientations by standard two-step CVD (low temperature carbonization followed by high temperature epitaxy). Then, the Si layers were grown onto these SiC seeds at various temperatures. Almost all the conditions gave polycrystalline deposit. At high deposition temperature (1350°C) the Si deposit was composed of separated hillocks and was never fully covering the 3C-SiC seeds. Lower deposition temperatures (≤ 1100°C) allowed obtaining silicon full coverage but not full epitaxy. Focusing on (100) orientation, it was shown that (100) Si deposit could be obtained but only on the as carbonized 3C-SiC sample, i.e. with the thinner SiC layer.
CXCR3.1 and CXCR3.2 Differentially Contribute to Macrophage Polarization in Teleost Fish
Authors: Lu Xin-Jiang , Chen Qiang , Rong Ye-Jing , Chen Feng , Chen Jiong
Published: May 2017

The study of multiple copies of chemokine receptor genes in various teleosts has long appealed to investigators seeking to understand the evolution of the immune system. The CXCR CXCR3 gene has two isoforms, CXCR3.1 and CXCR3.2, which are both expressed in macrophages. The distinct roles of teleost CXCR3s have not been identified previously. In this article, we found that CXCR3.1 and CXCR3.2 differentially contributed to macrophage polarization in the teleosts: ayu (Plecoglossus altivelis), grass carp (Ctenopharyngodon idella), and spotted green pufferfish (Tetraodon nigroviridis). In ayu macrophages, the P. altivelis CXCR3.1 (PaCXCR3.1) gene was constitutively expressed, whereas the P. altivelis CXCR3.2 (PaCXCR3.2) gene was induced postinfection with Escherichia coli. Upon E. coli infection, PaCXCR3.1+ and PaCXCR3.2+ macrophages showed an M1 and an M2 phenotype, respectively. CXCL9–11-like proteins mediated M1 and M2 polarization by interacting with the PaCXCR3.1 and PaCXCR3.2 proteins on macrophages, respectively. The transcription factors P. altivelis STAT1 and P. altivelis STAT3 were activated in PaCXCR3.1+ and PaCXCR3.2+ macrophages, respectively. Furthermore, the prognosis of septic ayu adoptively transferred with PaCXCR3.2+ macrophages was improved. Our data reveal a previously unknown mechanism for macrophage polarization, suggesting that redundant genes may regulate crucial functions in the teleost immune system.
Dental Implant Expectations among Partially and Completely Edentulous Patients
Authors: Mekkawy Maha A , Almutairi Huda A
Published: May 2017

Purpose

To assess edentulous patient awareness, expectations, and source of information about dental implants (DIs).

Materials and methods

Edentulous patients’ knowledge and awareness in using DIs, as an option in replacing missing teeth, either in implant-supported fixed prosthesis or implantsupported overdenture, were evaluated through a standardized self-explanatory questionnaire distributed in three places: King Saud Hospital, AL Harkan Private Dental Clinics (in Unaizah), and College of Dentistry, Qassim University. The questionnaires were either handed to the patients during their regular dental visits or asked by the dentist. A total of 178 subjects were included in this survey.

Results

About 93.3% of participants were aware of DIs, with statistically significant difference between the study groups (p = 0. 012). The participants’ friends and relatives were the main source of information (49.40%), followed by dentists (33.70%). Approximately 41.60% were moderately informed about DIs. Over one-third of patients expected an implant to require more care than natural teeth (39.80%). About 65.3, 73.6, and 80% of single missing, partially, and completely edentulous patients respectively, preferred to have their teeth replaced with DIs. Improvement in function was the predominant reason for completely edentulous patients (57.9%) to consider DIs, while 37.6 and 41.4% of single missing and partially edentulous patients were considered DIs to avoid adjacent teeth damaging. Fear of surgical risks was the major factor in preventing patients from choosing DIs (13.5%), followed by high cost (9.6%) and unknown side effects (6.2%).

Conclusion

There was a high awareness about DIs among removable denture patients; however, this awareness was associated with a low level of accurate information.

Recommendations

There is a need to provide more accurate information about DIs to the patients by the dentists.

How to cite this article

Mekkawy MA, Almutairi HA. Dental Implant Expectations among Partially and Completely Edentulous Patients. J Contemp Dent 2017;7(1):28-34.
Segurança alimentar e a governança econômica global
Authors: Denny Danielle Mendes Thame , Castro Douglas , Witt Gabrille , Valverde José , Machado Alexandre Ricardo
Published: May 2017

O presente artigo tem o objetivo de fazer uma análise da segurança alimentar sob a ótica do Direito Econômico Internacional. Primeiro discorre sobre as causas da insegurança alimentar, em seguida faz um histórico global e brasileiro, fazendo na sequência um análise do desperdício, contextualizando a questão no Direito Econômico Ambiental Internacional e na defesa dos Direitos Humanos, para, por fim, tratar da problemática sob a perspectiva da governança global. A conclusão principal do trabalho é que a insegurança alimentar vem sendo causada pela má distribuição e não por falta propriamente de alimentos e que as ferramentas de governança global para coordenar interesses antagônicos na busca do objetivo comum da erradicação da fome têm muito a melhorar. A metodologia escolhida foi a análise qualitativa com pesquisa documental, legislativa e bibliográfica.