bluuebunny/crossref_metadata_2025 huggingface dataset:
Instrumental Discrepancy and Relation of Stress Condition between ESD Association and JEDEC Standards on ESD CDM Test
Authors: Satirakul Yuparwadee , Butngam Tanawat , Phunyapinuant Surapol
Published: December 2020

Instrumental difference including characteristic aspects between ESDA and JEDEC standards on CDM test have been investigated and discussed. ESDA test systems provides higher discharge current, lower rise time and lower full width at half maximum at the same stress level, which is due to the higher inductance in the discharge path. We have succeeded in finding out the linear relation of the stress condition between these 2 standards. Furthermore, the current monotonically increases with the stress level for all capacitances and depends on the package size as expected. The relationship between current and package area is proportional because a larger package affords a higher capacitance. The current tends to saturate with a package size over 250 mm2 in both standards. The electrical failure yield of each standard system can be predicted by a stress condition of the other. The stress condition in JEDEC standard is undoubtedly a subset of the ESDA standard.
Picosecond Single-Photon and Femtosecond Two-Photon Pulsed Laser Stimulation for IC Characterization and Failure Analysis
Authors: Pouget V. , Faraud E. , Shao K. , Jonathas S. , Horain D. , Haller G. , Goubier V. , Picart B. , Forli L. , Lewis D.
Published: December 2020

This paper presents the use of pulsed laser stimulation with picosecond and femtosecond laser pulses. We first discuss the resolution improvement that can be expected when using ultrashort laser pulses. Two case studies are then presented to illustrate the possibilities of the pulsed laser photoelectric stimulation in picosecond single-photon and femtosecond two-photon modes.
Volume Electrical Failure Analysis for Product-Specific Yield Enhancement
Authors: Kasapi Steven , Liao Joy , Cory Bruce , Kapilevich Izak , Portune Richard , Ng Yin Shyang , Kardach Cathy , Cheng Elaine
Published: December 2020

Yield on specific designs often falls far short of predicted yield, especially at new technology nodes. Product-specific yield ramp is particularly challenging because the defects are, by definition, specific to the design, and often require some degree of design knowledge to isolate the failure. Despite the wide variety of advanced electrical failure analysis (EFA) techniques available today, they are not routinely applied during yield ramp. EFA techniques typically require a significant amount of test pattern customization, fixturing modification, or design knowledge. Unless the problem is critical, there is usually not time to apply advanced EFA techniques during yield ramp, despite the potential of EFA to provide valuable defect insight. We present a volume-oriented workflow integrating a limited set of electrical failure analysis (EFA) techniques. We believe this workflow will provide significant benefit by improving defect localization and identification beyond what is available using test-based techniques.
Sample Preparation and Analysis on Full-Thickness Silicon Wafers for Wafer-to-Wafer Bonding Process Development
Authors: Young Richard J. , Buxbaum Alex , Senowitz Corey , Deeb C. , Teh W.H.
Published: December 2020

Focused ion beam (FIB) systems use a gallium liquid metal ion source as the source of the ions, providing a typical beam current range of 1 pA to 20-60 nA. Using a reactive gas in addition to the FIB usually enhances the etch rate from 1 to 15 times, but with the combination of xenon difluoride gas and a silicon substrate the enhancement can be over 1000 times. Such an enhancement makes the removal of large volumes of Si more practical, even with the typical upper end of FIB currents of 20-60 nA. This paper discusses the application of full-thickness silicon trenching to the process development of WtW bonding. With the increase in 3DIC, it is expected that fresh process characterization and failure analysis techniques will be required. The work presented shows the feasibility of extending FIB techniques to the process development of wafer-to-wafer bonded samples even on full-thickness wafers.
Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation
Authors: Ng William , Weaver Kevin , Gemmill Zachary , Deslandes Herve , Schlangen Rudolf
Published: December 2020

This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.
Scanning Capacitance Microscopy for Failure Analysis of SOI-Based Advanced Microprocessors
Authors: Huat Lim Soon , Hnin-Ei Lwin , Narang Vinod , Chin J.M.
Published: December 2020

Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.
Tester-Driven Dynamic Laser Stimulation for Hard Functional Failure
Authors: Goh S.H. , Chan Y.H. , Zheng F. , Tan H. , Ting J.W. , Chen Robin , Mai Z.H. , Lam Jeffrey , Hsia L.C. , Chua C.M. , Phang J.C.H.
Published: December 2020

Dynamic Laser Stimulation (DLS) fault isolation techniques involve using an Automated Test Equipment (ATE) to run the device under certain test patterns together and a scanning laser beam to localize sites sensitive to laser stimulation. Such techniques are proven effective for localizing soft failures. In this paper, we demonstrate the feasibility of using such dynamic techniques for functional hard failures and design debug applications. We illustrate experimentally the significance of achieving sufficient signal to noise ratio (SNR) before such applications can be realized effectively, due to the large irregular noise that couples through as the functional pattern is run. We adopted a combination of hardware noise reduction and test program modification to overcome this challenge.
Characterizing Gate Disturb Embedded Flash Memory Cells by Atomic Force Probing
Authors: Hoffmann M. , Nowak C. , Haase A. , Eckl S.
Published: December 2020

There are two known failure mechanisms that cause Gate Disturb failures in flash devices. One main electrically classified failure is the Gate Disturb failure. A second mechanism is the Floating Gate charging caused by high energetic electrons, so-called channel hot electrons, jumping above the energetic barrier of tunnel oxide. This paper describes the characterization of a single transistor Flash cell with the nano-probing approach and introduces a test algorithm to distinguish between these mechanisms at a Gate Disturb affected Flash cell. A Keithley parameter analyzer in combination with Atomic Force Probing (AFP) has been used for the Flash cell device characterization. A Gate Disturb defect can be induced by different defect mechanisms. Two of them, TRAP's in tunnel oxide and channel hot electrons as a result of leaky PN-junctions, were identified as the main root causes. These mechanisms can be distinguished by AFP-analysis with the tests presented in the paper.
Debugging an Invisible Flaky Scan Chain Defect
Authors: Shukla Rahul , Billings Richard , Bakhshi Anurag , Schulze John , Gorti Atchyuth , Tamarapalli Nagesh
Published: December 2020

In general, scan shift failures are difficult to debug. Usually we use the compressed-mode chain test or scan capture-based chain diagnosis to ascertain the small chain segment or the position of the sequential element in the chain that is the cause of the failure. This method of diagnosis works well when the failures are static and limited to a chain segment, but fails to give results when the failure is caused by intra chain or inter chain segment interactions. This paper presents a scenario in which the root cause of the chain failures was due to interaction between chains. We call it the “invisible flaky chain defect” because -- although we were able to replicate failure at a test point (voltage-frequency) on the Shmoo -- the failing cycles changed from run to run.
Multiple-Post In-Situ Lift-Out Grids Preparation Using a Dicing Saw
Authors: Luo Jian-Shing , Lee Hsiu-Ting , Liew San-Lin , Sung Ching-Shan , Wu Yi-Jing
Published: December 2020

The use of in-situ lift-out combined with focused ion beam milling has become a favorable choice as it offers several indispensable advantages compared to the conventional mechanical and ex-situ lift-out sample preparation techniques. This paper discusses the procedures of the multiple-post in-situ lift-out grids preparation using a dicing saw. In addition, a real case is described to show that the multiple-post in-situ lift-out grids have been successfully applied to failure analysis. The multiple-post in-situ lift-out grids provide more positions and flatter surfaces for TEM sample mounting. The flat surface greatly increases the mounting efficiency and success rate. For the real case application, a thick Al fluoride oxide layer and Al corrosion were found above the Al bond pads, which had NOSP problem, and their neighbor area, respectively.
Influence of Laser Radiation on Embedded Non Volatile Memories and Its Application for Descrambling Verification
Authors: Österreicher I. , Skuras J. , Haase A.
Published: December 2020

This paper presents a fast method for descrambling verification of a flash array using an IR laser. The basic effect of how the flash cell reacts to the irradiation is studied first; and then, it is shown how to take advantage of this reversible effect to quickly verify the descrambling of the flash array of a modern microcontroller. The goal of this study is to find a way to deliberately affect the programming state of a specific flash memory cell, so the altered state can be read out by standard test equipment and be correlated to the physical position of the cell. Information on the mechanism of Fowler Nordheim tunneling, ONO-tunneling, hot electrons, and laser-induced hot electron injection is provided. The application for fast descrambling of a NVM array is shown.
Novel Gox Inspection Methodology in Advanced Silicon Process
Authors: Wang Kuo Yu , Chen Kuo Hsiung , Lin Jian Chang , Wu W. S.
Published: December 2020

This paper describes a new gate oxide (Gox) inspection method that uses nanoprobing and capacitive-atomic force microscopy (C-AFM) along with optimized etch chemistries and polishing techniques. It presents several examples showing how the new method outperforms conventional Gox inspection approaches in its ability to locate defects such as oxide pin holes and impurities that cause leakage current. It also discusses the electrical behavior of pin holes and soft defects.
Chromatic Aberration Correction of Silicon Aplanatic Solid Immersion Lens for Photon Emission Microscopy of Integrated Circuits
Authors: Yurt A. , Ramsay E. , Köklü F. H. , Ünlü M. S. , Goldberg B. B.
Published: December 2020

We investigate a complementary objective lens design for correcting chromatic aberration in the use of a silicon aplanatic solid immersion lens for back-side photon emission microscopy of metal-oxide-semiconductor circuits. Our simulations demonstrate that the chromatic aberration due to material dispersion of aplanatic silicon solid immersion lenses can be reduced by more than an order of magnitude in the spectral window 1.5µm-2.1µm, providing new diffraction limited performance. On-axis and off-axis imaging performance of the proposed optical design is evaluated.
Microstructural Considerations on the Reliability of 3D Packaging
Authors: Huang Zhiheng , Wu Zhiyong , Xiong Hua , Ma Yucheng
Published: December 2020

Microstructure and its effect on mechanical behavior of ultrafine interconnects have been studied in this paper using a modeling approach. The microstructure from the processes of solidification, spinodal decomposition, and grain growth in ultrafine interconnects has highlighted its importance. The size, geometry and composition of interconnects as well as the elastic energy can influence microstructure and thus the mechanical behavior. Quantification of microstructure in ultrafine interconnects is a necessary step to establish the linkage between microstructure and reliability.
Photon Emission Spectra of FETs as Obtained by InGaAs Detector
Authors: Glowacki Arkadiusz , Boit Christian , Yokoyama Yoshiyuki , Perdu Philippe
Published: December 2020

In this work we present spectrally resolved photon emission microscopy (SPEM) measurements for short-channel FETs acquired through the backside of the Si substrate using InGaAs detector. Two spectrum resolution methods have been used: continuous using a prism and discrete using a set of interference band-pass filters. The photon emission (PE) spectra have been corrected for the background / noise of the detector; they have been calibrated with respect to the system optical transmission function and corrected for the absorption on free carriers in the remaining layer of Si substrate. We discuss all the standardization aspects thoroughly as they are crucial in order to obtain correct device-intrinsic PE spectral information. Finally, we present the spectral results for FET devices operated in various operating conditions.
3D Tomography Analysis of Dark Voltage Contrast Failure in PCRAM Device
Authors: Oh Jangwon , Kim Jonghyeop , Lee Taekwon , Jeon Seungjoon , Kim Won , Kim Hojoung , Kim Changreol
Published: December 2020

The failure analysis using transmission electron microscopy (TEM) has been actively preceded in semiconductor industry. But due to the overlap issue and structural complexity of devices, it has become harder and harder to perform failure analysis using normal projected bright field (BF) and high angle annular dark field (HAADF) TEM images. To overcome these problems, 3-dimensional (3D) tomography technique has been suggested. In this work, we clarify the root cause of dark voltage contrast (DVC) failure at the bottom electrode contact region in PCRAM by using 3D tomography analysis. The 3D tomography samples were prepared in lamella shape by using focused ion beam (FIB). The electron energy loss spectroscopy (EELS) and 3D tomography analysis in scanning transmission electron microscope (STEM) HAADF mode were carried out. Through 3D tomography image reconstruction by AMIRA program, we observed ‘open contact fail’ between the BEC (Bottom Electrode Contact)-1 and the BEC (Bottom Electrode Contact)-2 at DVC region that could not be shown in 2D image.
A Proof for the Possibility of Ce-Oxide from CMP Residuals in Si-Wafers by Analytical TEM
Authors: Zhao Wayne , Thanh Liem Do , Gribelyuk Michael , Zaitz Mary-Ann , Lai Wing
Published: December 2020

Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.
Tomographic Study of Silicon Nanoparticles in Nanocrystalline Non-Volatile Flash Memory Devices by EFTEM
Authors: Zhou YongKai , Zhu Jie , Du AnYan , Hua YouNan , Mo ZhiQiang , Zhao SiPing
Published: December 2020

The distribution of Si nanoparticles, both dimensional and spatial, is a key factor affecting the performance of non-volatile flash memory devices. A new FIB method has been developed to prepare ultra-thin plan view specimens, containing only the Si nanoparticle matrix thin film layer, from fully processed nanocrystalline flash memory devices. The morphology and distribution of Si nanoparticles were then studied by EFTEM 3D tomographic reconstruction.
Simple and Fast Backside Sample Preparation Technique for Backside Fault Localization Analysis by Using Chemical Etching Method
Authors: Yen Gwee Hoon , Kay Ng Kiong
Published: December 2020

Deprocessing from the die backside provides a means of circuit inspection especially when the front side of die is fully covered with metallization. One of the most common techniques used is mechanical milling. It can provide good accuracy and consistency in backside preparation. However, the disadvantage of using this technique is the milling process is very time consuming. It takes at least 1-2 hours to complete the thinning and polishing process for only one unit. In addition, the equipment investment cost and later the maintenance cost (e.g. milling tools) is high. Therefore, an alternative way of backside opening is being proposed by chemical etching which is relatively fast and simple. It saves time and cost as the task can be done in less than 10 minutes while at the same time this new proposed method is still able to preserve the electrical functionality of the device.
Preparation of Wafer Level Packaged Integrated Circuits Using Pulsed Laser Assisted Chemical Etching
Authors: Chivas Robert , Dandekar Niru , Silverman Scott , Cruz Roddy , DiBattista Michael
Published: December 2020

Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation that etches backside silicon to ultra-thin remaining layer thickness for Focused Ion Beam (FIB) circuit edit and failure analysis of Wafer Level Packages (WLP). PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser.
3D Void Imaging in Through Silicon Vias by X-Ray Nanotomography in an SEM
Authors: Laloum David , Lorut Frédéric , Bleuet Pierre , Audoit Guillaume , Ribiere Celine
Published: December 2020

We have exploited an innovative X-ray tomography system, which is hosted in a Scanning Electron Microscope (SEM). The resolution reached by this equipment is closed to 160nm in 2 dimensions. We imaged Through Silicon Vias (TSV) which have undergone a manufacturing defect and characterized voids within these interconnections.
Computed Tomography as Failure Analysis Insurance
Authors: Martinez Gerald M.
Published: December 2020

Failure analysis of electronic components is almost always destructive, and there’s no going back once a destructive step is performed. Or, that’s the way it used to be, before the development of some of the more sophisticated nondestructive techniques such as computed tomography (CT). This paper presents a case study of an optocoupler, the suspected failure of which could not be confirmed until the last day of the month-long analysis, when the cause of failure was conclusively determined by a CT model captured weeks earlier.
Failure Analysis for SRAM Logic Type Failures
Authors: Song Zhigang , Beaudoin Felix , Lucarini Stephen , Sylvestri John , Safran Laura , Villallobos Manuel , Oldrey Richard
Published: December 2020

Failure analysis for Static Random Access Memory (SRAM) is the major activity in any microelectronic failure analysis lab. Originating from SRAM array structure, SRAM failure can be simple as single bit, paired bit or quad bit failures, whose defect is located at the failure location, or complicated as logic type failure involving WL or BL patterns or entire blocks, whose defect is often not at the failure location. For such SRAM logic type failures, failure analysis is more challenging and detailed fault isolation is necessary prior to physical failure analysis. This paper has demonstrated how to use SRAM decoder scheme knowledge, detailed layout tracing and Photon Emission Microscope (PEM) analysis to deal with the challenges and find the root causes for several cases of SRAM logic type failures.
Circuit Edit Geometric Trends
Authors: DiBattista Michael , Parley Martin , Lyons Don , Cruz Roddy , Wu Alan , Langley Jamie , Lau Jonathan , Stevens Ray
Published: December 2020

Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects in the design. This paper examines the geometries available for FIB nanomachining, via milling/etching, and deposited metal jumpers by analyzing polygon data from computer aided design (CAD) virtual layers gathered across four process technologies, from 180nm down to 28nm. The results of this analysis demonstrate that the combination of silicon nanomachining box length and FIB via box length identifies the most challenging aspects of the FIB edit. The smallest geometries include a 300 nanometer silicon access area with a FIB milled 200 nanometer via inside it. More advanced technology nodes will require the ability to make smaller geometries without the help of integrated design features typically referred to as design for FIB/Debug.
Gate Leakage Characterization and Fail Mode Analysis on 20 nm Technology Parametric Test Structures
Authors: Kodali Satish , Zhao Wayne , Johnson Greg M. , Beaudoin Felix
Published: December 2020

Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.
Comparison of C.W. Electro Optical Probing and Light Emission Techniques
Authors: Sanchez K. , Perdu P. , Melendez K. , Nakamura T.
Published: December 2020

Recent developments and improvements of laser probing techniques are a good complement to traditional techniques like emission microscopy (static and dynamic) or laser stimulation (also static and dynamic, based on thermal or photoelectric stimulus) for the investigation of failure analysis and diagnostic of integrated circuits. Laser probing techniques have in fact evolved from mainly pulsed approach with high bandwidth [1] to other methodologies based on Continuous Wave (CW) [2,3,4,5]. The bandwidth of these CW approaches is generally lower than pulsed techniques and fine characterization of rising and falling edges or measurement of very small timing shifts can be more difficult or not possible for high speed devices. This bandwidth limitation is most of the time due to the amplification chain. But, CW probing bandwidth is good enough, and continuously improving, to identify directly or indirectly timing issues and to identify bad digital or analog behavior. The setup is also much easier than pulsed laser systems which require complicated synchronization between the system timebase and the device. On this other side new internal analysis modes have been introduced with for example some mapping mode based on frequency analysis or on timing degradation identification through second harmonic analysis [6,7]. At the same time these techniques have pushed the capabilities of a lot of existing tools to investigate low current, low voltage and/or low frequency devices such as analog parts, transmission gates and configurations when the defect cannot be activated at normal or high voltage. Comparison with EMission MIcroscopy (EMMI) in dynamic mode, which can have the higher bandwidth [8] is then possible.
Dynamic Differential Thermal Measurements for Reliability and Failure Analysis
Authors: Falk R. Aaron , Pham Tram , Ruiz Anthony
Published: December 2020

Differential thermal measurements have been extended beyond simple fault isolation to quasi and fully dynamic test conditions. A new technique of Dynamic Digital Modulation has been developed that allows highly sensitive differential thermal measurements during active device operations. A quadrature version of the modulation also produces a thermal time constant map that allows for direct visualization of heat flow within a device structure. A wide range of potential applications in failure analysis, reliability and reverse engineering are opened up. Examples include in situ identification of resistive bonds, internal heat flow in packaged devices and die, dynamic heat loading, and localization of structural elements for reverse engineering.
A Reduction of Off-Leakage Current of SWD (Sub-WordLine Driver) pMOSFET for NWL-Based Mobile DRAM
Authors: Jeon Sanghyeon , Ha Taehong , Kim Youngwoo , Jung Hyuckchai , Lee Taewoo , Lee Kyupil , Cho Insoo
Published: December 2020

We demonstrate an effective way of reducing off-leakage current in sub-wordline driver pMOSFETs with lightly-doped source/drain, where gate-induced drain leakage current is much relaxed, compared with those of asymmetric source/drain. In mobile DRAM, one of key parameters is to achieve an extremely low level of standby current in power consumption. What has been found is that an increase of offleakage current in the pMOSFET is related closely to a contact-formation process, in particular, TiSi2 in p+/n junction. When a direct contact becomes close to a source/drain region, a titanium atom in TiSi2 tends not only to diffuse into a depletion region of p+/n junction but to play a critical role in leakage current. Maximizing a distance between p+ gate and its direct contact should be emphasized in order to control offleakage current in such a pMOSFET.
Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using E-beam Physical and Voltage Contrast Inspection
Authors: Patterson Oliver D. , Ryan Deborah A. , Tang Xiaohu , Lei Shuen Cheng
Published: December 2020

In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.
Spectrum Sharpening on Rotation Averaged TEM Nano Beam Electron Diffraction Patterns
Authors: Zhou Yongkai , Hua Younan , Li Xiaomin
Published: December 2020

The Rotation Averaged Spectrum of TEM diffraction patterns can be sharpened by a Maximum-Likelihood deconvolution algorithm. The sharpened spectrum will help to improve the precision of TEM diffraction-based techniques, e.g.: phase identification and strain analysis.
Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause
Authors: Tsang Yuk L. , VanVianen Alex , Wang Xiang D. , Theodore N. David
Published: December 2020

In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.
Failure Localization of Intermittent Short Failures Caused by Vertical Conductive Anodic Filament Formation
Authors: Nuez Daniel , Tan Phoumra
Published: December 2020

Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.
Safe Decapsulation Techniques Using Viton Caulk
Authors: Staller Kristopher D.
Published: December 2020

The decapsulation process in today’s failure analysis labs can become complicated with the smaller size of the package and the surface mount methods of attachment. Some failure modes recover when a part is removed from the application and remounted after decapsulation, and some parts are simply too fragile to handle for re-mounting after decapsulation. Decapsulating the failing device in-situ (on the board or DIP adapter) allows us to analyze the part in its original mounting condition, without exposing it to additional solder temperature stress, broken wires, or tweezer damage. This poses a challenge, as the fuming acids used for decapsulation most likely will spill onto the circuit board, dissolving the package leads, damaging the resin layers, and potentially corroding and shorting the circuit board traces.
TDR Analysis on Short Transmission Lines
Authors: Konkol Nicholas
Published: December 2020

Transmission line analysis is done in electrical failure analysis labs in order to find root causes that result in system level failures. After a fault is narrowed to a particular signal in a system, a Time Domain Reflectometer (TDR) can be used to analyze the physical transmission line associated with the signal. The transmission lines on smartphones often have inaccessible signal vias, few or no ground vias, probe points that are difficult to see, and short transmission lines. One solution that can alleviate these problems is to design a TDR Accessory Card. This paper discusses the processes involved in testing long and short transmission lines, providing the comparison between the expected and actual TDR measurement and the advantages and disadvantages of TDR, explaining four main points for using a TDR Accessory Card and two reasons for not using the TDR Accessory Card.
Productive Polishing TEM Sample Preparation Methodology Development
Authors: Yu Huisheng , Duan Shuqing , Li Ming , Zhang Qihua , Chien Wei-Ting Kary
Published: December 2020

In this paper, three productive polishing transmission electron microscopy (TEM) sample preparation methods are reported. The methods are studied to improve the efficiency and expand the application fields. Method 1 and 2 address expanding conventional polishing method application on same or similar pattern samples. Method 1 used a laser mark to identify one of the sample; and method 2 used a Pt coated glass inserted between samples or a direct deposition of Pt on one of the samples. Method 3 was developed facilitate stacking three or more samples into a single, batch process block and improved the efficiency greatly.
Determination of the Source of an Electrical Overstress Event to a Digital Variable Gain Amplifier Module
Authors: Htun Thiri , Brockett Steve
Published: December 2020

This paper presents a systematic approach of failure analysis to determine the source of electrical overstress condition to a digital variable gain amplifier (DVGA) module where the failure was due to attenuation accuracy. Having consideration of the physical evidence on the failed devices and the root cause of the failure gives an insight of how the mechanical damage caused an electrical overstress exposure to the devices. The paper provides information on destructive analysis and non-destructive analysis conducted for determining the root cause of the failure of the DVGA module. Analysis revealed that devices failed due to an electrical overstress exposure through mechanical damage to the passivation of the metal-2 lines. The mechanical damage occurred during die-sort testing due to misalignment of the probes which delivered unintended electrical stress to the devices.
Failure Analysis Induced by Memory Cell Plate Noise in High-Density DRAMs
Authors: Jung Mingu , Lee Myungjae , Kwon Hyungshin , Hong Heeil , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung
Published: December 2020

As the DRAM structure is miniaturized, the cell capacitance is reduced and resistance is increased. Because of this change, the DRAM operation is more sensitive than previous generations to changes of the device elements. The device elements consist of cell capacitance, Bit Line (BL) capacitance, cell node resistance, supply-voltage and the surround noise. The elements were changed by decreasing the cell node dimensions. The write time (tWR) is degraded by changing the elements. In particular, the noise is very variable element on change of surrounding cell phase which is data1 or data 0. In this paper, we show that one of the most dominant contributors to failure is the plate noise and explain how plate voltage level affects tWR delay. The effect of the plate voltage modulation can be correlated with ∆Vbl which is bit line level difference to read out the data. We define this phenomenon as the plate dc noise effect and propose a model in miniaturized DRAM.
Intra-Device Defect Localization through EBIC/EBAC Combined with Electrical Nanoprobing for FinFET Devices Composed of Multiple Sub-Elements
Authors: Dahanayaka Daminda H. , Bader Daniel A. , Prevost Dennis P. , Coster Michael T. , Mccullen Erik F. , Masters Mark E. , Stevens Keith C.
Published: December 2020

Physical failure analysis of nanoelectronic devices is typically performed using plan view or cross-sectional TEM, SEM or SPM techniques. While plan view SPM and SEM analyses are limited by the depth sensitivity of the technique, cross-sectional analysis requires at least approximate localization of the fail location within the device for effective sample preparation. Multi-finger wide 2D planar devices and multi-FIN 3D devices are structures which require an additional step in pinpointing the fail area within the device. This paper describes successful use of EBIC/EBAC techniques to localize the fail location within such devices in both the 22 nm and 14 nm technology nodes.
MEMS Failure Analysis In Wafer Fabrication
Authors: Ng Hui Peng , Teo Angela , Ang Ghim Boon , Quah Alfred , Dayanand N. , Xu Naiyun , Chen Chang Qing , Mai Zhi Hong , Lam Jeffrey
Published: December 2020

This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.
Conductive Thin Film Fail Detection in 20 nm and 14 nm Technologies
Authors: Kodali S. , Zhang C. , Schaeffer T. , Arva S. , Nedeau D. , Yu J. , Ma Y. , Vijay T. , Kalaiazhagan K. , Oh C.K. , Beaudoin F.
Published: December 2020

Conductive thin film residues often referred to as puddles could be challenging fails to detect. A large extant film with no distinct boundaries would make the task more challenging for a comparison between good and bad region. Advanced node 20nm and 14nm technologies mandate use of several conductive thin films in the front end of line processes, and hence a potential for high defects during initial product development stage. Use of other electrical characterization techniques in combination with scanning electron microscopy inspection will be a very powerful tool to detect the root cause affirmatively. Cross-sectional images are necessary to understand the root cause of the fails for corrective actions. This work uses three cases of power supply shorts as a platform to demonstrate the idea, demonstrating a few situations where traditional techniques might reach its limits while the authors depend on additional characterization tools to confidently detect and confirm fails.
Failure Analysis of Single-Bit Charge Loss after Stress and Studies on Silicon Dopant Profile
Authors: Gong Rong-Wei , Chang Hsiao-Tien , Chan Hui-Wen , Lee Lian-Feng , Shih Chih-Ching , Kuo Albert , Lin Ting-Chang , Wang Tse-Jen
Published: December 2020

The single-bit charge loss of flash memory after stress has been investigated using TEM with selective chemical etching and TCAD simulation for the effect of silicon dopant profile and electrical failure analysis technique. However, the abnormal dopant profile on the drain-side of the failing bit observed in the TEM does not match the leakage behavior from the simulation. A qualitative model for the degradation process is proposed based on the electrical failure analysis results, it is suggested that the hole generated by avalanche breakdown captured by oxide traps on the drain-side during the stress is the source of leakage current.
A Case Study of Failure Analysis and Root Cause Identification on ESD-Induced Breakdown
Authors: Liu Hongmin , Li Zhe , Weng Zheng
Published: December 2020

This paper describes the detailed process of failure analysis (FA) of a 16-bit transceiver. The FA included six steps: electronic parametric testing, visual inspection, optical beam induced resistance change to isolate failure location, SEM inspection of the breakdown, electro static discharge (ESD) root identification, and ESD test to prove the identification. FA showed that the short circuit was the result of a breakdown between the I/O resistor and the substrate, and the cause of the breakdown was most likely an ESD event. In a series of electrical over stress/ESD tests performed, the field failure signature was replicated with a MM ESD model, thereby identifying the root cause of the ESD failure.
Failure Analysis Process Improvement Using Barcode Equipment Management System
Authors: Sabate Andrew C. , De La Cruz Em Julius , Rieck Christopher
Published: December 2020

Failure Analysis (FA) process improvement is vital to cope with increasing demand on FA cycle time reduction from end customer. Real time failure analysis update, equipment usage data collection, and equipment security enhancement plays significant factor on cycle time reduction. This paper aims to discuss the barcode equipment management system in aiding FA Lab for process improvement.
Accelerating Technology Development and Yield Ramp on First Silicon Utilizing a Wafer-Level Dynamic EFA System
Authors: Chen Li-Qing , Sun Ming-Sheng , Chao Jui-Hao , Ng Soon Fatt , Izak Kapilevich , Tsao Chun-Cheng
Published: December 2020

This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.
Power Distribution Analysis of an Integrated Circuit Using FIB Passive Voltage Contrast
Authors: Sorkin Alexander , Pawlowicz Chris , Krechmer Alex
Published: December 2020

Competitive circuit analysis of an Integrated Circuit (IC) is one of the most challenging types of analysis. It involves various high technology steps of IC die de-processing/de-layering; keeping precise planarity from metal layer to metal layer, Scanning Electron Microscope (SEM) imaging and images mosaicking, image recognition and Graphic Database System (GDS) segmentation processes and finally logic and architecture level analysis. One of the most complicated analysis is Power Management and Power Distribution [2] on the entire IC die when no datasheet or other IC’s information is available. Power Distribution analysis requires the highest level of architecture analysis, not feasible by conventional Reverse Engineering (RE) methods or extremely costly. The current paper discusses and demonstrates a new inventive methodology of Power Distribution analysis using known FIB Passive Voltage Contrast (PVC) effects [1]. This patented technique provides significant time and resources saving.
Effects of Barrier Metal and Etch Profile on Galvanic Corrosion of Al Pad
Authors: Youn Sang Bae , Choi Pil Mook , Seong Suk Hyun , Cho Don Koo
Published: December 2020

Recently a phenomenon has been found that shows different corrosion rates over Al bond pad regardless of different densities of Cl, F components on Al bond pads in different products. According to the results of analysis, the products showed different corrosion rates for different etch conditions of the bond pad opening. For the cause analysis, we conducted a cross-sectional profile comparison between two products with Al bond pads. Based on the result of comparison, we discovered that the side wall profile of the Al bond pad is affected by the etch conditions of the bond pad opening. In some severe cases, it was observed that a small void was formed between the side wall and Al bond pad. Under moist conditions, this void provided moisture between Al bond pad and TiN barrier metal that the electricity contacted. Through this study, we could conclude that the moisture in the void between Al bond pad and TiN barrier metal may create a galvanic corrosive condition.
A Detailed Analysis Scheme to Interpret Multiple Photon Emissions Micrograph for Improved Diagnostic Resolution on Open Defects
Authors: Goh S.H. , Manlangit Edmund C , Susanto Edy , Yeoh B.L. , Hao Hu , Tan Alan , Ma Hnin Hnin W , Lin Zhao , Chan Y.H. , Lam Jeffrey
Published: December 2020

Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic emission micrographs that are caused by open defects in digital logic. This paper presents a methodology incorporating layout-aware trace analysis and post schematic extraction with test bench analysis to enhance the diagnostic resolution on the suspected defective net(s).
Fault Isolation of Leakage for a Device with Nonuniform Epoxy Encapsulation
Authors: Lin Ke-Ying , Ssang Hsiu-Li , Huang Shou-Ming
Published: December 2020

In this article, we demonstrate using lock-in thermography (LIT) to perform fault isolation of leakage on a board-mounted device with rough, heterogeneous epoxy encapsulation. It is interesting to observe LIT spot shifting either on the failing unit’s reference pin or the failed pin using a different lock-in frequency. The protection diode of the reference pin is triggered by LIT and the electrical behavior should not be affected by varying lock-in frequencies (0.1 Hz to 25 Hz). The reason for the shifting hot spot is a non-uniform morphology in the epoxy encapsulation, which consists of different thicknesses and voids. This complicated epoxy encapsulation morphology results in a non-uniform heat conduction pathway when a different lock-in frequency is used. In this study, a LIT hot spot will stabilize and remain in a fixed position when the lock-in frequency is increased to greater than 5 Hz and the phase shift is directly proportional to the square-root of the lock-in frequency. This indicates that the heat conduction becomes stable under such a condition, and the phase shift value can still be used for relative depth localization. By overlaying LIT and X-ray imaging, an accurate position of the fault location in the X-Y plane can be detected. A quick and non-destructive 3D fault isolation method for complicated system level failure can be achieved in this way.
Overcoming the Challenges on Electrically Damaged Devices
Authors: Norico Allan , Sabate Andrew
Published: December 2020

Finding the real root cause of electrically damaged devices is often challenging where it can mask out the real failure mechanism. The electrical damages might (might probably, one doubtful word is enough) be a consequence of the real failure mechanism. This paper aims to present cases and techniques to overcome the challenges of electrically damaged devices in identifying the real failure mechanism.