bluuebunny/crossref_metadata_2025 huggingface dataset:
Application of Backside Photo and Thermal Emission Microscopy Techniques to Advanced Memory Devices
Authors: Lee S.-S. , Seo J.-S. , Cho N.-S. , Daniel S.
Published: December 2020

Both photo- and thermal emission analysis techniques are used from the backside of the die colocate defect sites. The technique is important in that process and package technologies have made front-side analysis difficult or impossible. Several test cases are documented. Intensity attenuation through the bulk of the silicon does not compromise the usefulness of the technique in most cases.
Temperature-Dependent Electronic Circuit Analogy for Predicting Wire Temperature as a Function of Current
Authors: Ditz M. J.
Published: December 2020

A model has been developed accurately predicting the temperature along a length of wire heated by passing a current through it. The wire is modeled as a transmission line with its thermal properties mapped onto the appropriate electronic analogs. A program describing the model circuit has been written in PSPICE such that time versus temperature curves can be generated for any wire given the material, diameter, length, and stressing current. The model has been dynamically temperature corrected, and its accuracy has been demonstrated for two types of fuses and one type of bond wire. This model is useful for predicting fusing conditions of fuse elements or bond wires, assessing the reliability of a material for given operating conditions (by knowing the temperature the material would attain), derating for design, and as a failure analysis tool by providing insight into an overstress condition in which a wire has melted open.
Characterization of Californium – 252 (252Cf) as a Laboratory Source of Radiation for Testing and Analysis of Semiconductor Devices
Authors: Plante J. , Allen E. , Lum G.
Published: December 2020

Bipolar silicon transistors were exposed to Californium (252Cf) radiation and neutron radiation obtained from nuclear facilities. The effect of the radiation on the transistors was measured by recording the transistor's electrical characteristic as a function of radiation fluence. Correlation between Californium (252Cf) -induced and neutron-induced damage and previously published data for proton-induced radiation damage was made. Finally, the effect ofthenna1 annealing on gain recovery was also investigated.
Dendritic Growth Failure of a Mesa Diode
Authors: Singh P. , Cozzolino V. , Galyon G. , Logan R. , Troccia K. , Hurd J. L. , Tsai P.
Published: December 2020

The time delayed failure of a mesa diode is explained on the basis of dendritic growth on the oxide passivated diode side walls. Lead dendrites nucleated at the p+ side Pb-Sn solder metallization and grew towards the n side metallization. The infinitesimal cross section area of the dendrites was not sufficient to allow them to directly affect the electrical behavior of the high voltage power diodes. However, the electric fields associated with the dendrites caused sharp band bending near the silicon-oxide interface leading to electron tunneling across the band gap at velocities high enough to cause impact ionization and ultimately the avalanche breakdown of the diode. Damage was confined to a narrow path on the diode side wall because of the limited influence of the electric field associated with the dendrite. The paper presents experimental details that led to the discovery of the dendrites. The observed failures are explained in the context of classical semiconductor physics and electrochemistry.
Through-Transmission Acoustic Inspection of Ball Grid Array (BGA) Packages
Authors: Moore T. M. , Hartfield C. D.
Published: December 2020

The application of through-transmission acoustic inspection to packaging strategies such as ball grid array (BGA) circumvents many of the problems encountered applying conventional pulse-echo inspection to BGAs. A unique feature of pulse-echo acoustic inspection is detection of delaminations in internal interfaces, which is based on the inversion of the pressure pulse (1800 phase shift) at the delamination. This article describes the advantages and applications of pulse-echo acoustic inspection and presents an experimental comparison of pulse-echo and through-transmission methods. It discusses the difficulties that BGA packages present to pulse-echo inspection, such as the complexity of the pulse overlap problem in pulse-echo inspection of the laminate, the problem of multiple echo signals overlapping in time is the possibility of interference effects, and that phase inversion cannot always be relied upon to assist in delamination detection. Practical considerations for through-transmission inspection are also covered.
Breakup Sequence of the TWA Flight 800 Airplane: How it was Determined That an Explosion of the Wing Center Section Fuel Tank Initiated the Breakup
Authors: Wildey James F.
Published: December 2020

A group composed of representatives from the National Transportation Safety Board and the investigation parties used fire and soot patterns, recovery positions of the pieces, witness marks, fracture directions, deformations, and stress analysis to document the breakup sequence of the TWA Flight 800 airplane and to determine that an explosion of the wing center section fuel tank initiated the accident.
Metallurgical Examination of a Galled PH 13-8 Mo Stainless Steel Main Rotor Sub-Assembly
Authors: Grendahl Scott M. , Pepi Marc S.
Published: December 2020

The Aviation and Missile Command requested the US Army Research Laboratory to perform a metallurgical examination of a main rotor sub-assembly from an attack helicopter as vibration was noticed during a test flight after replacement of the main rotor head. This article presents the details of the metallurgical examination, the mechanical properties of and chemical analysis on the failed component, and the techniques adopted for the examination such as scanning electron microscopy, X-ray mapping, energy dispersive spectroscopy, and residual stress analysis. The discussion includes the details of crack origin, fatigue progression, and the circumstances which caused the point contact between a MP35N pin and a PH 13-8 Mo component. The failure of the main rotor strap pack outboard pitch cone bolt was attributable to galling. Several of the cracks may have propagated by fatigue and converged beneath the bolt inner diameter or adhesive wear may have induced a sub-surface crack origin.
ESD Induced Failure of an Internal MOSFET in a Mixed Signal IC due to Two Different Power Supplies
Authors: Bundhoo Fayik , Vedula Lakshmi , Khandekar Shekhar
Published: December 2020

During the ESD testing of a Dual T1/E1 line interface unit (LIU) at Level One, the circuitry in every pad cell was found to be robust to Electro-Static Discharge (ESD) threshold of up to 2000 Volts. Device failure was however observed on devices when functional tests were performed. These failures were observed on devices which were only subjected for 1250 Volts of ESD stress. The failure analysis revealed ESD induced damage at the Gate - Drain region of a MOSFET in the core of the die. A weak power supply clamp in the supply circuit caused this failure. The step by step analysis process and the redesign of this device with confirmation on new design revision is explained.
Evaluation of Pt/PZT/Pt Capacitors Using SIMS
Authors: Tomotani Miki , Ashida Hiroshi , Goto Yasuyuki , Otani Seigen
Published: December 2020

This paper presents the results of a study on the effects of N2-H2 annealing on Pt/PZT/Pt capacitors. By measuring the electrical properties of test capacitors before and after annealing and comparing the data with composition profiles obtained via secondary ion mass spectrometry (SIMS), the authors found that annealing causes an increase in hydrogen in the PZT layer (accompanied by a reduction in nonvolatile polarization) and a decrease in oxygen in the upper Pt film, which is associated with poor adhesion. The authors also found that oxygen annealing, after N2-H2 annealing, can restore electrical properties as well as adhesion states back to their original levels.
ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement
Authors: Patrick D.S. , Wagner L.C. , Nguyen P.T.
Published: December 2020

Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.
Faster Defect Localization with a New Development of IDDQ
Authors: Desplats Romain , Perdu Philippe , Benbrik Jamel , Dupire Michel
Published: December 2020

Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. To deal with the challenge of faster and more accurate defect localization with greater sensitivity, we have developed a new method based on voltage contrast capabilities for internal localization of IDDQ defects. This method covers an extended range of cases: functional or non functional devices, with or without CAD information, etc... Using only the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located. This approach can also be extended to coupling with netlist information. For example, the equipotential line previously found on the faulty circuit can be compared with the fault simulator output. Then, the site of the simulated defect corresponding to the physical failure can be extracted and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.
Comparison of Failure for HBM ESD Testers Meeting ANSI/ESD S-5.1 or the New ESDA Standard Test Method and JEDEC Standard
Authors: Khosropour Fred , Hatchard Colin , Morgan Ian , Henry Leo G.
Published: December 2020

The ESD Association standard ANSI/ESDA S-5.1 1993 for testing sensitivity to the Human Body Model (HBM) 1 forms the basis around which the majority of automated HBM ESD simulators have been constructed. As device pin counts increase it is unlikely that new larger simulators for > 512 pins will be capable of meeting this standard 2, since increased parasitics will increase the effective socket (stray) capacitance. However, such larger HBM simulators are expected to meet both the JEDEC Standard JESD-22-114A, 1997 3 and the newly issued ESDA Standard Test Method, ESD STM 5.1, 19984. This paper begins to evaluate the several questions regarding the correlation of HBM Withstand Voltage when used to characterize state-of-the-art semiconductor IC's, between simulators meeting the (NEW) standards JESD 22, ESD STM- 5.1 and those existing simulators presently in daily use, which typically meet the (OLD) ESDA S-5.1. This paper for the first time investigates the impact of "effective" socket capacitance in the same tester; i.e., with the same discharge model and the same pin selection mechanism. The experimental investigation was based on stressing three different sub-micron CMOS technology products; firstly on a simulator meeting the OLD standard and then on a modified version of this simulator meeting the NEW standards. Electrical properties of damaged pins and physical analysis was used to establish common Failure Signatures5 for the two mother boards.
Selective Wet-Etch of Silicon Nitride Passivation Layers
Authors: Malberti P. , Ciappa M.
Published: December 2020

Selective removal of silicon nitride passivation layers is of major importance in failure analysis of semiconductor devices. Typical applications are: cleaning of the die surface for optical microsccjpy and for removal of superficial contamination, electron microscopy, liquid crystals, voltage contrast, electron beam testing, mechanical microprobing, and . selective layer-by-layer strip. A new wet-etch for silicon nitride passivation layers has been developed, which is fully selective! over aluminum metallization and which preserves full device functionality after passivation removal. For the first time in the failure analysis literature, the chemical recipe and the etching procedure are given in details. This etchant has been experimented for more than two years in many failure analysis laboratories on a wide spectrum of discrete and integrated semiconductor devices, always with excellent results. Its capability and efficiency are illustrated by two failure analysis case histories.
Infrared Scanning Using Radiance vs. Temperature Calibration Techniques to Determine Actual Temperature of an Electronic Component
Authors: Dickey David
Published: December 2020

It is necessary to understand the limitations of an automated InfraRed (IR) system when using it for temperature measurements. These systems correct for emissivity of the test sample by heating the unpowered sample and taking radiance measurements at two temperatures. For the specific sample that was analyzed, the temperature of the area of interest of the powered sample was higher than the two temperatures used for emissivity correction. This resulted in a significant error in the temperature calculated by the system. The use of direct radiance measurements provided an accurate measurement of the sample temperature.
A Novel Fault Isolation Technique Using Noise Detection and Characterization of Light Emitted From Integrated Circuits
Authors: Zheng Hong , Patterson Joe , Li G. P.
Published: December 2020

This paper describes a new technique for identifying defects on integrated circuit. This technique detects the noise content in light emitted from defect sites. The purpose of this technique is to determine which of many light emission sites represent a defect and which represent normal devices. It reports the first phase of studies to evaluate the feasibility and potential effectiveness of this technique. The feasibility of this technique has been demonstrated by simultaneously monitoring electrical noise and the noise in the light emitted from a gallium arsenide light emission diode (LED) and a bipolar transistor. The paper will present the methodology and apparatus used to detect and analyze the noise in light emission.
Optical Probing of VLSI ICs from the Silicon Backside
Authors: Eiles Travis M. , Woods Gary L. , Rao Valluri
Published: December 2020

With the advent of C4 packaging technology, Intel has developed, in conjunction with a technology partner, an integrated, laser-based optical backside probing system. This article begins with a description of the basic system operation. This is followed by a discussion on the electro-optic effect in CMOS, which is used for the signal acquisition. The question of invasiveness of the photo-injected carriers is then discussed. Information on the entire probing environment is also provided. The article also discusses results and presents a comparison with other waveform acquisition techniques. It ends with a brief discussion on the developments needed to scale the technique to future processes.
Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits
Authors: Krieg Kenneth , Qi Richard , Thomson Douglas , Bridges Greg
Published: December 2020

A contact probing system for surface imaging and real-time signal measurement of deep sub-micron integrated circuits is discussed. The probe fits on a standard probe-station and utilizes a conductive atomic force microscope tip to rapidly measure the surface topography and acquire real-time highfrequency signals from features as small as 0.18 micron. The micromachined probe structure minimizes parasitic coupling and the probe achieves a bandwidth greater than 3 GHz, with a capacitive loading of less than 120 fF. High-resolution images of submicron structures and waveforms acquired from high-speed devices are presented.
Light Emission Spectral Analysis: The Connection Between the Electric Field and the Spectrum
Authors: Barton Daniel L. , Tangyunyong Paiboon , Soden Jerry M. , Henderson Christopher L. , Cole Edward I. , Danz Rainer , Steiner Reinhard , Iwinski Zbigniew
Published: December 2020

The device physics necessary to gain theoretical insight into the relationship between the bias conditions and the associated electric field for semiconductor structures in various failure conditions such as forward and reverse biased junctions, MOSFET saturation, latchup, and gate oxide breakdown are examined. The relationships are verified by light emission spectra collected from test samples under various bias conditions. Several examples are included that demonstrate the utility and limitations of spectral analysis techniques for defect identification and the associated, non-electric field related information contained in the spectra.
Short High Voltage Stress for Design-to-Process Characterization
Authors: Lisenker Boris , Veinger Dmitry , Mitnick Yuri
Published: December 2020

This paper discusses the use of failure analysis techniques, including high-voltage stress testing, to determine the product margin for a microprocessor manufactured on a 0.25-μm CMOS process. The first part of the approach is to define the parametric baseline of the product and differentiate normal from failure-prone behavior. The next step is to measure the margin on each unit (i.e., transistor gate) by temporarily increasing the supply voltage (Vcc) and observing its effect on leakage current. As the authors explain, the new approach facilitates the detection of potential design and manufacturing problems in a much shorter time than the hundreds of hours normally required.
Latch-Up Induced Slit Voiding in Aluminum Metal Lines
Authors: Zhang Chunyu , Vedula Lakshmi , Khandekar Shekhar
Published: December 2020

Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.
Nondestructive Detection of Cracks in Ceramics Using Vicinal Illumination
Authors: Hull Scott M.
Published: December 2020

Cracks and other defects in ceramic materials can be difficult or impossible to examine and photograph due to the extreme lack of contrast. A method for inspecting translucent ceramics using scattered light, also known as vicinal illumination, will be described. This method has been known in the ceramics industry for quite some time, but is not well known in the testing and failure analysis community. Electronics applications include substrates, packages, multilayer capacitors, and thin film resistors. Ceramic materials are used in electronic applications as microcircuit packages and substrates which carry signals and power between microcircuits. Fine cracks in ceramic materials can result in mechanical failures, electrical failures, and loss of hermeticity. Often, fine cracks are difficult or impossible to detect using standard nondestructive inspection techniques such as visual inspection, ultrasonic inspection, or vapor crack detection. Dye penetrant inspection is usually effective, but contaminates the part, which is unacceptable for space flight hardware. One effective nondestructive inspection method of detecting cracks involves examining the way in which light scatters through the ceramic material when viewed with a standard bright field reflected light microscope. This method, termed vicinal illumination, has been used for detecting cracks during failure analyses of several part types, and screening of space flight hardware. The technique has proven effective on several different types of ceramic materials as well. A related method for use with dark field equipment has also been used to successfully locate otherwise invisible cracks.
An Application of Passive Voltage Contrast (PVC) to Failure Analysis of CMOS LSIs Using Secondary Electron Collection
Authors: Nishikawa Akira , Kato Naoko I. , Kohno Yoshiteru , Miura Nobuhito , Shimizu Masao
Published: December 2020

This paper describes a method for applying passive voltage contrast (PVC) in the failure analysis of CMOS LSIs using a conventional scanning electron microscope (SEM), and demonstrates the effectiveness of this method. It was confirmed by measurement of the stage absorption current that the combined emission efficiency of secondary and backscattered electrons from aluminum is larger than 1 at acceleration voltages lower than about 2.5 kV. This means that local positive charges should be generated on a conductor in association with its irradiation with an electron beam at a relatively low acceleration voltage. However, a pn junction connected to the conductor would change the potential. The potential is still positive if the conductor is connected to a reverse-biased diode but becomes lower if such a diode is forward-biased. The PVC signal observed on the conductor should be defined according to the bias state of any diode connected to the conductor. Therefore, for failure analysis applications, if the bias state of a diode connected to a suspicious conductor is known, the PVC observation is useful for determining whether there is an open defect or a short-circuit defect. Some case studies are presented to demonstrate the effectiveness of the method. Cross-sectional TEM observations of defects localized in this way are also included.
Electrostatic Discharge (ESD) Failures in Thin Film Resistors
Authors: Hull Scott M.
Published: December 2020

Field failures of nichrome thin-film resistors have been investigated recently for several pieces of spaceflight hardware. These failures have involved resistance shifts ranging from a few percent to complete open circuits. Failure analysis and duplication of these failures have revealed that the failures were caused by electrostatic discharge. The failure characteristics and the circuit conditions necessary for failure have been studied for several types of thin-film resistors, including nichrome and tantalum nitride resistive elements. The effects of latent damage and resistive pattern design will also be discussed.
Electromigration and Electrochemical Reaction Mixed Failure Mechanism in Gold Interconnection System
Authors: Murayama Hide , Yamazaki Makoto , Nakajima Shigeru
Published: December 2020

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.
From IDDQ Fault Detection to Defect Localization in Logic CMOS Integrated Circuits: Key Issues
Authors: Perdu Philippe , Desplats Romain
Published: December 2020

IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.
Scanning Electron Acoustic Microscopy: A Novel Tool for Failure Analysis and Microcharacterization
Authors: Wong W-K , Thong J.T.L. , Phang J.C.H. , Yin Q.R. , Fang J.W.
Published: December 2020

This paper describes Scanning Electron Acoustic Microscopy (SEAM) applications, particularly to samples that are of interest to the microelectronics industry. Several applications of SEAM involving semiconductor and ferroelectric samples are discussed in this paper. The expanding scope of applications for SEAM presents exciting possibilities. The challenge ahead lies in understanding the contrast mechanisms in SEAM signal formation as well as correlating results to the physical properties of samples.
Data Analysis Tools and Methodologies for Quick Yield Learning in a High Volume Manufacturing Environment
Authors: Andrade L. , Taylor T.
Published: December 2020

High volume products in manufacturing require fast yield learning, root cause identification, and verification that process or tool problems are fixed. Yield losses of 1% correspond to very large dollar losses. Therefore, it is important to have sophisticated data analysis tools that handle large volumes of data to drive higher yields. This paper will present our methodology for defining yields, assessing wafer yield signatures, and using data analysis tools to determine tools or processes which drive yield loss. A SAS based data analysis tool will be shown which can identify tool or process related problems causing abnormalities in parametrics and impacting yield. Case studies illustrating the usefulness of the tool are shown for a Synchronous Dynamic Random Access Memory (SDRAM) product from our wafer fab. In the final analysis, it is clear that an efficient data analysis approach utilizes resources most effectively and pinpoints yield problems with minimal cycle time.
A Novel Method to Analyze the Deep Trench Capacitors in DRAM
Authors: Lee Jack , Huang Kuo-Hui , Lue Jen-Lang
Published: December 2020

A novel method has been developed to reveal the entire three dimensional (3D) deep trench (DT) capacitors for inspection in DRAM, especially NO capacitor dielectrics, ASG residues at corners, morphology etc., for process evaluation and failure analysis. It offers an alternative to conventional cross-section polishing, top down polishing or FIB milling methods. A DRAM chip was ground and polished down to a certain level from the chip backside. An etching solution was then applied to enhance the DTs appearance. 3D DTs can be inspected in scanning electron microscopy (SEM). The entire DTs or specific DT also can be lifted out for detailed investigation in transmission electron microscopy (TEM). The innovation of this technique is to provide a quick 3D observation in SEM, and much more flexibility to an entire DT inspection in TEM, which were not presented before.
Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor
Authors: Colvin Jim B. , Roy Anirban
Published: December 2020

Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.
Electronic Package Failure Analysis Using TDR
Authors: Smolyansky Dima A.
Published: December 2020

The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.
Failure Analysis of Tungsten Stud Defect from the CMP Process
Authors: Takagi K. , Kohno Y. , Nukii S.
Published: December 2020

This paper describes a failure analysis that effectively combined multiple analytic techniques to find the cause of I/O leakage in a flawed chip produced for an OEM (Original Equipment Manufacturer) product. Internal probing was initially used for defect isolation and a Tungsten (W) stud open circuit flaw was isolated by electrical characterization with internal probing. SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy, and FE-AES (Field Emission Auger Electron Spectroscopy) analysis with FIB (Focused Ion Beam) preparation were used for physical analysis. Cross-sectional SEM and TEM observations showed a gap with foreign material (FM) between the bottom of the metal line and the top of the W stud, possibly from the W CMP (chemical mechanical polish) process. FE-AES is effective for the analysis of light materials and their chemical composition, so a flat milling FIB process was used to prepare a cross-section for FE-AES analysis of the FM and the interfaces of the open defect. The spectra showed that the FM was traceable to the W CMP process. From these analytical results and problem reproduction experiments in the W CMP process on the manufacturing line, the failure mechanism was identified.
Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects
Authors: Wenger George M. , Coyle Richard J. , Solan Patrick P. , Dorey John K. , Dodd Courtney V. , Primavera Anthony , Erich Robert
Published: December 2020

A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.
High Temperature Solder (Au/Sn) Failures from Nickel Plating Impurities
Authors: Bunis Carl B.
Published: December 2020

High temperature gold/tin eutectic (80 Au/ 20 Sn) solder is used in manufacturing for multiple reasons. These motives may include the ability to post solder a part/device without reflow, high temperature field applications, and allow soldering to thick Au layers without the possibility of precipitating AuSn4 brittle intermetallics. In the following military case, Au/Sn eutectic was employed because of high temperature service and the guarantee of no occurrence of gold embrittlement when soldering to the thick Au outer plating. The Au was plated over an electroplated nickel (Ni) layer on a Kovar (iron/nickel/cobalt) housing. The soldering resulted in an extremely poor bond strength of a duroid circuit to the Kovar housing. The results showed contamination in the supplier’s electroplated Ni bath caused the plating to have poor bond strength. The failure occurred within the Ni plating layer.
Semiconductor Wear Out at Nuclear Power Plants
Authors: Riddle James B.
Published: December 2020

This paper will examine semiconductor wear out at San Onofre Nuclear Generation Station (SONGS). The topics will include case studies, failure mechanisms, diagnostic techniques, failure analysis techniques and root cause corrective actions. Nuclear power plants are unique in that instrumentation and control circuits are continuously energized, are periodically tested, and have been in operation for greater than 25 years. Root cause evaluations at SONGS have identified numerous semiconductor failures due to wear out. Case studies include light output deterioration in opto-isolators, junction alloying failures of transistors and integrated circuits and parametric shifts in operational amplifiers. In most cases the devices do not fail catastrophically but degraded to the point of circuit level functional failure. Failure analysis techniques include circuit analysis, board level troubleshooting to identify the degraded components. Intermittent failures require power cycling, thermal cycling, and long term monitoring to identify the responsible components. Corrective actions for semiconductor wear out at SONGS include enhanced monitoring and proactive change out of identified part types.
UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies
Authors: Wilkins Timothy C.
Published: December 2020

This paper describes the organization, process, and challenges of an international network of electrical and mechanical failure analysis labs that leverage lessons learned, resources, failure analysis techniques, and benchmarking of current common problems. Formed 11 years ago as just an electrical/electronic part failure analysis council within Otis Elevator and Carrier, this group has grown to be a network of 16 electrical and 22 mechanical labs. This council is a one of a kind network that also includes suppliers of parts to UTC. This paper will also illustrate the advantages of cross-functional and divisional leveraging with case study examples.
Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications
Authors: Rai Raghaw S. , Subramanian Swaminathan , Rose Stewart , Conner James , Schani Phil , Moss Jamey
Published: December 2020

Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.
Failure Analysis of a Transistor Lead
Authors: Deguchi Yasushi , Matsuda Sumio , Aoki Jiro , Tamura Takashi , Iwai Yasunobu , Kikui Shigeki
Published: December 2020

We investigated the cause of the whisker/discoloration which were found in the transistor lead of stocks (package type TO-18, low power use). In process of the investigation, we estimate two corrosion models that the first model is the remnant of sulfuric acid in cracks of the nickel-phosphorus plating layer in the transistor lead, the second model is the out-gassing or the dissolved ions from the stock container and conductive mat. As the results of the investigation which includes analyses of the whisker/discoloration cross section made by FIB (Focused Ion Beam), a reproductive experiment and so on, the whisker/discoloration were the corrosion reacted between the solder (Pb-Sn) on the transistor lead and SO42- ions of the stock container. We estimate that the new corrosion will not occur and grow in mounted devices because of rejecting the source of corrosion (stock containers). Further, in the worst case of the corrosion occurrence, protective coatings were applied to the mounted transistor lead, as the measure against falling away from the transistor lead.
Planar TEM Analysis of Nanoindented Samples Using the Focused Ion Beam Lift-Out Technique
Authors: Shofner T. L. , Brown S. R. , Rossie B.B. , Decker M. A. , Obeng Y. S. , Stevie F. A. , Drown J.L.
Published: December 2020

The focused ion beam system (FIB) has become a valuable tool for the preparation of transmission electron microscope (TEM) samples. Several FIB preparation techniques exist but of particular interest is the lift-out technique, which allows for the extraction of a thin membrane from a bulk material. This technique has seen great success in the preparation of cross sectional samples. We explore the use of this technique for planar sample preparation to examine grain deformation due to nanoindentation in a reference copper material.
Scanning SQUID Microscopy for New Package Technologies
Authors: Pacheco Mario , Wang Zhiyong
Published: December 2020

New package technologies are getting more complex, and thus isolating defects is becoming more challenging [1]. Analytical tools like Scanning SQUID Microscopes (SSM) are thus gaining relevance based on the capability to non-destructively detect electrical fails in very complex package technologies [2]. In this paper we report the use of SSM for the nondestructive isolation of electrical fails in novel microelectronic packages, where SSM has been found to be a unique fault isolation technique.
Fault Isolation of Large Nets Using Bridging Fault Analysis
Authors: Ontko George
Published: December 2020

Bridging faults are a common failure mechanism in integrated circuits and scan-based diagnosis does a good job of isolating these defects. Diagnosis, however, can sometimes result in large search areas. Typically, these areas are caused by long repeater nets. When this happens, physical failure analysis will become difficult or impossible. This paper concerns itself with using a bridging fault analysis as a means of reducing these large search areas.
Dislocation Induced Leakage of p+-Implanted ESD Test Macros in 90nm Technology
Authors: Zimmermann Gunnar , Riess Philipp , Chang W.T. , Tang Howard , Ou Homy , Cerva Hans
Published: December 2020

The introduction of p+ implanted areas at the drain side of source-drain-gate salicide-blocked electro-static discharge (ESD) protection diodes resulted in a better ESD robustness, however at the expense of increased leakage currents in up to 40% of the 90nm technology test structures. Leaky devices are found to be randomly distributed across a wafer. The leakage current exhibits only weak temperature dependence and is linearly increasing with the p-implanted area. Photoemission microscopy revealed spots located exclusively in the p+ implanted areas. TEM imaging visualized, that the leakage path is caused by dislocations, reaching from the silicon surface through the p+n junction zone into the substrate. Based on these results and the implant conditions, a theory of dislocation formation was postulated and countermeasures had been defined.
A Novel Approach for Enhancing Critical FIB Imaging for Failure Analysis and Circuit Edit Applications
Authors: Myers Joseph , Abramo Marsha , Anderson Michael , Phaneuf Michael W.
Published: December 2020

As semiconductor device features continue to decrease in size from merely sub micron to below 100 nanometers it becomes necessary to mill smaller and higher aspect ratio FIB vias with reduced ion beam current. This significantly reduces the number of secondary electrons and ions available for endpoint detection and imaging. In addition FIB gas assisted etching introduces a gas delivery nozzle composed of conductive material. This component is grounded to prevent charge build up during ion beam imaging or milling. The proximity of the nozzle to the sample surface creates a shielding effect which reduces the secondary electron detection level as well [1]. The ability to enhance secondary electron imaging for end point detection is required for successful FIB circuit edit and failure analysis applications on advanced technologies. This paper reviews the results obtained using FIB Assist, an image and signal enhancement product for the FEI / Micrion platform, for critical FIB endpoint determination. Examples of FIB fabricated probe points with 30 x 30 nm FIB vias and circuit edit applications endpointing on metal 1 with high aspect ratio holes are presented.
Timing Analysis of a Microprocessor PLL Using High Quantum Efficiency Superconducting Single Photon Detector (SSPD)
Authors: Song Peilin , Stellari Franco , Eckhardt James P. , McNamara Timothy , Tong Ching-Lung
Published: December 2020

This paper describes the analysis of a Phase-Locked Loop (PLL) internal phase detection circuit built in IBM’s 0.13 µm Silicon On Insulator (SOI) CMOS technology by using the Picosecond Imaging Circuit Analysis (PICA) [1,2] tool equipped with the high quantum efficiency Superconducting Single-Photon Detector (SSPD) [3,4]. Signals corresponding to the internal nodes of the PLL are for the first time measured and compared to circuit simulations in order to characterize the behavior of the different components of the circuit.
The Effect of Temperature and Strain Rate on Selected Lead-Free Solder Alloys
Authors: Vijayen Jayamalar , Maveety James G. , Allen Emily L.
Published: December 2020

The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.
Measurement of Solder Joint Strength and Its Dependence on Thermal Aging in Freestanding and Board-Mounted Packages using a Laser Spallation Technique
Authors: Gupta Vijay , Tian Jun , Hartfield Cheryl , Zeng Kejun , Chiu Cheng , Stierman Roger
Published: December 2020

The continuing evolution of semiconductor packages to finer solder ball pitches, shrinking solder ball volume, and new solder materials, mandates the availability of methods to accurately assess solder joint reliability both at the component and at the board level. Many tests in use for this purpose cannot provide direct measurements of solder joint interfacial strength. This paper reports on the investigation of laser spallation for interfacial strength assessments and understanding of failure mechanisms on chip scale package (CSP) solder joints.
In-Line Repair of Detectable, Same-Level, Killer Defects Affecting IC Chips
Authors: Patterson Oliver D. , Shuttleworth David M. , Jamison Michelle , Albers Brad J.
Published: December 2020

In-line repair of same-level killer defects is suggested as a method of the future for achieving higher yields. A methodology describing selection of killer defects and how to repair them is presented. A proof of concept experiment is presented where killer defects are removed from comb test structures using a FIB. An economic analysis is also included which indicates that this technique is economically viable for more costly chip designs. Therefore additional development work is merited.