bluuebunny/crossref_metadata_2025 huggingface dataset:
Polycrystalline SiC as Source Material for the Growth of Fluorescent SiC Layers
Authors: Kaiser Michl , Hupfer Thomas , Jokubavicius Valdas , Schimmel Saskia , Syväjärvi Mikael , Ou Yi Yu , Ou Hai Yan , Linnarsson Margareta K. , Wellmann Peter J.
Published: March 2013

Polycrystalline doped SiC act as source for fluorescent SiC. We have studied the growth of individual grains with different polytypes in the source material. We show an evolution and orientation of grains of different polytypes in polycrystalline SiC ingots grown by the Physical Vapor Transport method. The grain influence on the growth rate of fluorescent SiC layers grown by a sublimation epitaxial process is discussed in respect of surface kinetics.
Lateral Boron Distribution in Polycrystalline SiC Source Materials
Authors: Linnarsson Margareta K. , Kaiser Michl , Liljedahl Rickard , Jokubavicius Valdas , Ou Yi Yu , Wellmann Peter J. , Ou Hai Yan , Syväjärvi Mikael
Published: March 2013

Polycrystalline SiC containing boron and nitrogen are used in growth of fluorescent SiC for white LEDs. Two types of doped polycrystalline SiC have been studied in detail with secondary ion mass spectrometry: sintered SiC and poly-SiC prepared by sublimation in a physical vapor transport setup. The materials are co-doped materials with nitrogen and boron to a concentration of 1x1018 cm-3 and 1x1019 cm-3, respectively. Depth profiles as well as ion images have been recorded. According to ocular inspection, the analyzed poly-SiC consists mainly of 4H-SiC and 6H-SiC grains. In these grains, the boron concentration is higher and the nitrogen concentration is lower in the 6H-SiC compared to the 4H-SiC polytype. No inter-diffusion between grains is observed.
Optical Properties of the Niobium Centre in 4H, 6H, and 15R SiC
Authors: Ivanov Ivan G. , Gällström Andreas , Leone Stefano , Kordina Olof , Son Nguyen Tien , Henry Anne , Ivády Viktor , Gali Adam , Janzén Erik
Published: March 2013

A set of lines in the photoluminescence spectra of 4H-, 6H-, and 15R-SiC in the near-infrared are attributed to Nb-related defects on the ground of doping experiments conducted with 4H-SiC. A model based on a an exciton bound at the Nb-centre in an asymmetric split vacancy configuration at a hexagonal site is proposed, which explains the structure of the luminescence spectrum and the observed Zeeman splitting of the lines.
Persistent Photoconductivity in p-Type 4H-SiC Bulk Crystals
Authors: Okuda Takafumi , Miyake Hiroki , Kimoto Tsunenobu , Suda Jun
Published: March 2013

We investigated the photoconductivity decay characteristics of p-type 4H-SiC bulk crystals grown by a modified Lely method by differential microwave photoconductance decay (μ-PCD) measurements using a 349-nm laser as an excitation source. We observed persistent photoconductivity (PPC) in the p-type SiC bulk crystals. The decay time at room temperature was 2600 μs. The decay time decreased with increasing temperature, resulting in 120 μs at 250oC, and the activation energy of the decay times was determined to be 140±10 meV. Long decay characteristics were also observed by below-band-gap excitation at 523 or 1047 nm. On the other hand, no PPC was observed in p-type homoepitaxial layers grown by hot-wall chemical vapor deposition.
Photoluminescence Topography of Fluorescent SiC and its Corresponding Source Crystals
Authors: Wilhelm Martin , Kaiser Michl , Jakubavicius Valdas , Syväjärvi Mikael , Ou Yi Yu , Ou Hai Yan , Wellmann Peter J.
Published: March 2013

The preparation and application of co-doped polycrystalline SiC as source in sublimation growth of fluorescent layers is a complex topic. Photoluminescence topographies of luminescent 6H-SiC layers and their corresponding source crystals have been studied in order to investigate the dependence of the epitaxial growth on the source material. It is shown that the homogeneity concerning the dopant incorporation and the layer luminescence intensity does not depend on the characteristics of the PVT grown source material. Therefore co-doped polycrystalline SiC is a promising source material in fast sublimation growth of luminescent 6H-SiC.
Point Defects in SiC as a Promising Basis for Single-Defect, Single-Photon Spectroscopy with Room Temperature Controllable Quantum States
Authors: Baranov P.G. , Soltamov Victor A. , Soltamova Alexandra A. , Astakhov Georgy V. , Dyakonov Vladimir D.
Published: March 2013

The unique quantum properties of the nitrogen–vacancy (NV) center in diamond have motivated efforts to find defects with similar properties in silicon carbide (SiC), which can extend the functionality of such systems not available to the diamond. As an example, results of experiments on electron paramagnetic resonance (EPR) and optically detected magnetic resonance (ODMR) are presented suggests that silicon vacancy (VSi) related point defects in SiC possess properties the similar to those of the NV center in diamond, which in turn make them a promising quantum system for single-defect and single-photon spectroscopy in the infrared region. Depending on the defect type, temperature, SiC polytype, and crystalline position, two opposite schemes have been observed for the optical alignment of the high-spin ground state spin sublevels population of the VSi-related defects upon irradiation with unpolorized light. Spin ensemble of VSi-related defects are shown to be prepared in a coherent superposition of the spin states even at room temperature. Zero-field (ZF) ODMR shows the possibility to manipulate of the ground state spin population by applying radiofrequency field. These altogether make VSi-related defects in SiC very favorable candidate for spintronics, quantum information processing, and magnetometry.
Study on the Correlation between Film Composition and Piezoresistive Properties of PECVD SixCy Thin Films
Authors: Fraga Mariana A. , Koberstein Leandro L.
Published: March 2013

The effects of carbon content on the piezoresistive properties of non-stoichiometric silicon carbide (SixCy) films deposited on thermally oxidized (100) Si substrates by Plasma Enhanced Chemical Vapor Deposition (PECVD) from silane (SiH4) and methane (CH4) gas mixtures have been investigated. Four different film compositions have been obtained by varying SiH4 flow ratios from 1.0 to 4.0 sccm, while the other parameters were kept constant. In order to evaluate the piezoresistive properties of the SixCy films, we have developed test structures consisting of SixCy thin-film resistors defined by reactive ion etching (RIE) with Ti/Au pads formed by lift-off process. The gauge factor (GF) and temperature coefficient of resistance (TCR) of each SixCy film were measured.
The Integrated Evaluation Platform for SiC Wafers and Epitaxial Films
Authors: Kitabatake M. , Sameshima J. , Ishiyama Osamu , Tamura K. , Ohshima H. , Sigiyama N. , Yamashita Y. , Tanaka T. , Senzaki J. , Matsuhata H.
Published: March 2013

It has been widely accepted that wide-band-gap semiconductor SiC can provide low-loss semiconductor switches and diodes for the power electronics applications. The SiC devices enable the low-loss and compact converters and inverters.
Characterization of the Metal-Semiconductor Interface of Pt-GaN Diode Hydrogen Sensors
Authors: Irokawa Yoshihiro
Published: March 2013

In this paper, interaction mechanism of hydrogen with GaN metal-insulator-semiconductor (MIS) diodes has been investigated, focusing on the metal/semiconductor interfaces. As a result, the following three points are revealed: First, MIS Pt-SiO2-GaN diodes show a marked improvement in detection sensitivity, suggesting that the device interface plays a critical role in sensing. Second, exposure of the diodes to hydrogen is found to change the conduction mechanisms from Fowler-Nordheim tunneling to Pool-Frenkel emission. Third, interface trap level density of the diodes is found to be reduced by hydrogen exposure even at room temperature. These results support the validity of the hydrogen-induced dipole layer model.
Dislocation Analysis of 4H-/6H-SiC Single Crystals Using Micro-Raman Spectroscopy
Authors: Shin Y.J. , Kim W.J. , Kim H.Y. , Bahng W.
Published: March 2013

Micro-Raman spectroscopy is an excellent non-destructive analysis method, which compensates for disadvantages of KOH method. Raman shift of A1(LO) and E1(TO) band at threading screw dislocation(TSD) were investigated in n-type on/off-axis 4H- and 6H-SiC single crystal wafers by Micro-Raman scattering at room temperature. The results showed that A1(LO) band were shifted toward higher frequency while the E1(TO) band were shifted toward lower frequency on the on-axis wafers. The shifts are caused by increasing electron concentration and lattice disorder near the dislocation core, respectively. In the off-axis wafers, no shifts were observed possibly due to the measurement geometry which does not contain whole dislocation core.
Effects of Growth Parameters on SiC/SiO2 Core/Shell Nanowires Radial Structures
Authors: Dhanabalan Sathish Chander , Negri Marco , Rossi Francesca , Attolini Giovanni , Campanini Marco , Fabbri Filippo , Bosi Matteo , Salviati Giancarlo
Published: March 2013

Cubic silicon carbide - silicon dioxide core-shell nanowires have been synthesized in a thermal CVD system from carbon monoxide on silicon substrate. Using a non-ionic surfactant during the coating process of the substrate by the catalyst, the uniformity of the catalytic layer was improved, resulting in a more uniform nanowires growth. It is demonstrated that the core diameter is strongly correlated with the precursor concentration.
Hall Effect Characterization of 4H-SiC MOSFETs: Influence of Nitrogen Channel Implantation
Authors: Mortet V. , Bedel-Pereira E. , Bobo J.F. , Cristiano F. , Strenger Christian , Uhnevionak V. , Burenkov A. , Bauer Anton J.
Published: March 2013

Effect of a shallow nitrogen implantation in the channel region of n-channel 4H-SiC Hall bar MOSFETs on their electrical properties has been characterized by Hall effect. A significant improvement of Hall mobility in normally-off devices is observed with increasing nitrogen implantation dose up to 1013 cm-2 with a peak Hall mobility of 42.4 cm2.V-1.s-1. Coulomb scattering as dominant scattering mechanism up to room temperature is demonstrated using temperature dependent MOS-Hall effect characterization.
Evaluation of PBTS and NBTS in SiC MOS Using In Situ Charge Pumping Measurements
Authors: Habersat Daniel B. , Lelis Aivars J. , Green Ronald , El Mooro
Published: March 2013

Since power devices such as DMOSFETs will operate at higher temperatures with accelerated degradation mechanisms, it is essential to understand the effects of typical operating conditions for power electronics applications. We have found that SiC MOSFETs when gate-biased at 150 °C show an increasing charge pumping current over time, suggesting that interface traps (or perhaps near-interface oxide traps) are being created under these conditions. This trapping increase occurs slightly above linear-with-log-time and mimics previously observed threshold voltage instabilities, though a causal relationship has not yet been determined. We found the charge trapping after 104 s of BTS increased at a rate of 1x1011 cm-2/dec for NBTS (-3 MV/cm), 0.7x1011 cm-2/dec for PBTS (3 MV/cm), and 0.3x1011 cm-2/dec when grounded. The observed increase in charge trapping has negative implications for the long term stability and reliability of SiC MOS devices under operating conditions.
Gate Oxide Stability of 4H-SiC MOSFETs under On/Off-State Bias-Temperature Stress
Authors: Tadjer Marko J. , Constant Aurore , Godignon Philippe , Martin-Horcajo Sara , Bosca Alberto , Calle Fernando , Berthou Maxime , Millán José
Published: March 2013

On- and off-state bias-temperature instability (BTI) measurements of 4H-SiC field effect transistors fabricated in a gate-oxide-first process were performed in the 30-450 °C temperature range. Stable operation under off-state stress at 300 °C is reported. On-state bias-instability stress revealed behavior consistent with the presence of hole traps in the SiC channel. The interface state density Dit increased from 2.5 eV-1cm-2 to 6.6 eV-1cm-2 as a function of positive stress duration.
Contact-Free Micropipe Reactions in Silicon Carbide
Authors: Sheinerman Alexander G. , Gutkin Mikhail Yu. , Argunova Tatiana S. , Mokhov Evgeniy , Nagaluyk Sergey N. , Je Jung H.
Published: March 2013

We discuss a correlated reduction in the cross sections of two neighboring micropipes (MPs) along their axes (generally parallel to the growth direction). Such variations in MP cross sections can lead to MP healing. We provide experimental evidence of this effect and discuss its reasons and a possible mechanism. Our main idea is that MPs can remotely interact with each other by the exchange of full-core dislocations. We propose a theoretical model describing the energetics of this process.
Structural Perfection of Silicon Carbide Crystals Grown on Profiled Seeds by Sublimation Method
Authors: Mokhov Eugene N. , Nagalyuk Sergey
Published: March 2013

The distribution of extended defects in silicon carbide (SiC) crystals grown on profiled seeds by the sublimation (physical vapor transport) method has been studied by optical microscopy in combination with chemical etching. It is established that free lateral growth on protruding relief elements (mesas) is accompanied by a sharp decrease in the density of threading dislocations and micropipes. The decreased density of dislocations is retained after growing a thick layer that involves the overgrowth of grooves that separated individual mesas.
Conversion of Basal Plane Dislocations to Threading Edge Dislocations by Annealing 4H-SiC Epilayers at High Temperatures
Authors: Zhang Xuan , Nagano Masahiro , Tsuchida Hidekazu
Published: March 2013

Basal plane dislocations (BPDs) converting to threading edge dislocations (TEDs) has been observed in 4H-SiC epilayers after thermal annealing at high temperatures. Grazing incidence reflection synchrotron X-ray topography was used to investigate the dislocation behaviors. It is argued that the conversion is achieved by constricted BPD segments cross-slipping to the prismatic plane and TED glide on its slip plane. Higher conversion ratio and better surface morphology were achieved by performing ion implantation and annealing before epitaxial growth.
Electrophysical and Optical Properties of 4H-SiC Irradiated with Xe Ions
Authors: Chuchvaga N. , Bogdanova E. , Strel'chuk Anatoly M. , Kalinina Evgenia V. , Shustov D.B. , Zamoryanskaya M. , Shkuratov V.
Published: March 2013

A comparative research of the cathodoluminescence and electrical characteristics of the samples 4H-SiC irradiated with high energy Xe ions (167 MeV) in wide range fluencies 4x109 –1x1011 cm-2 at temperatures 250C and 5000C are presented. After irradiation these samples were thermal annealed at 5000C for 30 min. Far-action effect at a depth of more than one order of magnitude of stopping distance was observed under Xe ions irradiation in 4H-SiC. An increase of the ion Xe fluencies increased the concentration of radiation-induced defects that resulted in rise of the compensation effect of conductivity in samples. Irradiation of 4H-SiC by Xe ions at 5000C was accompanied with "dynamic annealing" some low-temperature radiation-induced defects, which led to a partial recovery of the electrical characteristics of devices. The thermal annealing of irradiated samples led to additional partial annealing of radiation defects, which increases the radiation resource of devices based on 4H-SiC.
Influence of Epilayer Thickness and Structural Defects on the Minority Carrier Lifetime in 4H-SiC
Authors: Kallinger Birgit , Berwian Patrick , Friedrich Jochen , Rommel Mathias , Azizi Maral , Hecht Christian , Friedrichs Peter
Published: March 2013

4H-SiC homoepitaxial layers with different thicknesses from 12.5 µm up to 50 µm were investigated by microwave-detected photoconductivity decay (µ-PCD), deep level transient spectroscopy (DLTS) and defect selective etching (DSE) to shed light on the influence of the epilayer thickness and structural defects on the effective minority carrier lifetime. It is shown that the effective lifetime, resulting directly from the µ-PCD measurement, is significantly influenced by the surface recombination lifetime. Therefore, an adequate correction of the measured data is necessary to determine the bulk lifetime. The bulk lifetime of these epilayers is in the order of several microseconds. Furthermore, areas with high dislocation density are correlated to areas with locally reduced effective lifetime.
Stability Investigation of High Heat-Resistant Resin under High Temperature for Ultra-High Blocking Voltage SiC Devices
Authors: Izumi Toru , Hemmi Tetsuro , Hayashi Toshihiko , Asano Katsunori
Published: March 2013

The reliability of three kinds of high heat-resistant resins has been evaluated under high temperatures. These resins were applied to insulation substrates and a high temperature storage test has been carried out. The insulation performance of the resins was evaluated by applying 20 kV between a pair of electrodes on the substrate covered with resin. The insulation performance at 20 kV was maintained in samples with two of the three kinds of resins for 1,000 hours at 225oC. In a higher temperature storage test at 250oC, samples with one of the kinds of resin were not able to maintain insulation of 20 kV for 200 hours, while the two remaining resins were not able to maintain the insulation for 1,000 hours. In most samples that were not able to maintain the insulation, cracks or detachments were seen. Hardening caused by oxidation of the resin and differences in the coefficient of linear thermal expansion (CTE) are considered as causes of the cracks or detachments. It is thought to be necessary to lower the CTE of the resin and inhibit its oxidation in order to use it at more than 250oC for long periods of time.
4H-SiC Trench MOSFET with Thick Bottom Oxide
Authors: Takaya Hidefumi , Morimoto Jun , Yamamoto Toshimasa , Sakakibara Jun , Watanabe Yukihiko , Soejima Narumasa , Hamada Kimimori
Published: March 2013

A 4H-SiC trench MOSFET has been developed that features trench gates with a thick oxide layer on the bottoms of the trenches. The maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFET. The drain-source breakdown voltage is 1400V and the specific on-resistance is 4.4mΩcm2 at a gate bias of 20V and a drain voltage of 2V.
An Improvement of Trench Profile of 4H-SiC Trench MOS Barrier Schottky (TMBS) Rectifier
Authors: Chu K.W. , Yen C.T. , Chung Patrick , Lee C.Y. , Huang Tony , Huang Chih Fang
Published: March 2013

A 4H-SiC TMBS diode with improved trench corners has been demonstrated. The trench profiles are improved by using 12sccm/28sccm of SF6/Ar mixture, and a working pressure of 12 mtorr for RIE etching. The depth of micro-trenching has been reduced to lower than 0.07 μm. The 4H-SiC TMBS diode with improved trench profiles shows a breakdown voltage over 725V.
A Nanoscale Look in the Channel of 4H-SiC Lateral MOSFETs
Authors: Fiorenza Patrick , Frazzetto Alessia , Swanson Lukas K. , Giannazzo Filippo , Roccaforte Fabrizio
Published: March 2013

In this work the field effect mobility measured on lateral n-channel MOSFETs in 4H-SiC with Al implanted body was correlated with the interface trap density measured on MOS capacitors. The test devices were fabricated on samples subjected to different post implantation annealing conditions (i.e. with or without a protective carbon capping layer) and to an identical post-oxidation annealing in N2O. Despite the improved interfacial morphology, a reduction of the peak mobility (from 40 to 24 cm2V-1s-1) was observed using the carbon capping layer. An increase in the density of interface traps was consistently found. Nanoscale measurements of the active dopant concentration in the SiC channel region by cross-sectional scanning capacitance microscopy showed an higher compensation of p-type SiC for the sample processed without the capping layer, which indicates a more efficient incorporation of nitrogen at the SiO2/SiC interface.
Growth of Low Basal Plane Dislocation Density 4H-SiC Crystals in Controlled Temperature Distribution inside the Crucible
Authors: Tsuge H. , Ushio S. , Sato S. , Katsuno M. , Fujimoto T. , Yano T.
Published: March 2013

For bulk growth of SiC crystal with higher quality, it is important to control the temperature distribution inside the crucible. We have performed numerical calculations of the temperature distribution inside the growing crystal, and discussed the relationship between the calculated sheer stress and the basal plane dislocation densities. We found that growth with lower basal plane dislocation defect densities, specifically at the front edge of the crystal, is possible by lowering the temperature gradient toward the growth direction.
Simulation and Optimization of 4H-SiC DMOSFET Power Transistors
Authors: Hung Chien Chung , Chen Young Shying , Yen Cheng Tyng , Lee Chwan Ying , Lee Lurng Shehng , Tsai Ming Jinn
Published: March 2013

Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The retrograde profile can have higher breakdown voltage as compared to the box profiles. The P-well concentration is also examined and optimized. The DMOS device can have a better avalanche behavior once the P-Well concentration is higher than 2E18 cm-3. In addition, the interfacial oxide effect on the channel mobility has also been studied. The interfacial charge density should be controlled to lower than 2E11 cm-2 so as to have a higher mobility and lower on-state resistance.
Improved Stability of 4H-SiC MOS Device Properties by Combination of NO and POCl3 Annealing
Authors: Yano Hiroshi , Araoka Tsuyoshi , Hatayama Tomoaki , Fuyuki Takashi
Published: March 2013

Effects of combination of NO and POCl3 annealing on electrical properties and their stability of 4H-SiC MOS capacitors and MOSFETs were investigated. Channel mobility of MOSFETs processed with both NO and POCl3 annealing did not exceed that of POCl3 annealed MOSFETs. As for the stability of flat-band voltage and threshold voltage using a constant field stress test, the combined annealed sample indicated very stable characteristics compared with single annealed devices with NO or POCl3. The reason for obtaining stable electrical properties is discussed based on nitridation and phosphorization effects at the interface.
High-Speed Growth of 4H-SiC Single Crystal Using Si-Cr Based Melt
Authors: Kado Motohisa , Daikoku Hironori , Sakamoto Hidemitsu , Suzuki Hiroshi , Bessho Takeshi , Yashiro Nobuyoshi , Kusunoki Kazuhiko , Okada Nobuhiro , Moriguchi Kouji , Kamei Kazuhito
Published: March 2013

In this study, we have investigated the rate-limiting process of 4H-SiC solution growth using Si-Cr based melt, and have tried high-speed growth. It is revealed that the rate-limiting process of SiC growth under our experimental condition is interface kinetics, which can be controlled by such factors as temperature and supersaturation of carbon. By enhancing the interface kinetics, SiC crystal has been grown at a high rate of 2 mm/h. The FWHM values of X-ray rocking curves and threading dislocation density of the grown crystals are almost the same as those of seed crystal. Possibility of high-speed and high-quality growth of 4H-SiC has been indicated.
Novel Approach for Improving Interface Quality of 4H-SiC MOS Devices with UV Irradiation and Subsequent Thermal Annealing
Authors: Watanabe Heiji , Ikeguchi Daisuke , Kirino Takashi , Mitani Shuhei , Nakano Yuki , Nakamura Takashi , Hosoi Takuji , Shimura Takayoshi
Published: March 2013

We report on the harmful impact of ultraviolet (UV) light irradiation on thermally grown SiO2/4H-SiC(0001) structures and its use in subsequent thermal annealing for improving electrical properties of SiC-MOS devices. As we previously reported [1], significant UV-induced damage, such as positive flatband voltage shift and hysteresis in capacitance-voltage curves as well as increased interface state density, was observed for SiC-MOS devices with thermally grown oxides. Interestingly, the subsequent annealing of damaged SiO2/SiC samples resulted in superior electrical properties to those for untreated (fresh) devices. These findings imply that UV irradiation of the SiO2/SiC structure is effective for eliciting pre-existing carbon-related defects and transforming them into a simple configuration that can be easily passivated by thermal treatment.
Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability
Authors: Sameshima J. , Ishiyama Osamu , Shimozato Atsushi , Tamura K. , Oshima H. , Yamashita T. , Tanaka T. , Sugiyama N. , Sako H. , Senzaki J. , Matsuhata H. , Kitabatake M.
Published: March 2013

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.
Sodium Enhanced Oxidation: Absence of Shallow Interface Traps after Removal of Sodium Ions from the SiO2/4H-SiC Interface
Authors: Hermannsson Pétur Gordon , Allerstam Fredrik , Hauksson Sigtryggur , Sveinbjörnsson E.Ö.
Published: March 2013

We investigate the strong passivation of shallow interface traps located near the SiC conduction band after enhanced oxidation of Si-face 4H-SiC in the presence of sodium. We find that removing the sodium ions present at the SiO2/SiC interface since oxidation by way of bias stress or annealing does not lead to a significant increase in the density of interface traps. The presence of sodium ions at the SiO2/SiC interface is therefore not responsible for the passivation of such interface traps in oxides formed by sodium enhanced oxidation.
Alloying of Ohmic Contacts to n-Type 4H-SiC via Laser Irradiation
Authors: Hürner A. , Schlegl T. , Adelmann B. , Mitlehner H. , Hellmann R. , Bauer Anton J. , Frey L.
Published: March 2013

In this study, we present the results of alloying nickel as ohmic contact material to n-type 4H-SiC via a continuous wave fiber laser with different laser beam powers and processing times. The laser system exhibits an emitting wavelength of 1070 nm and a beam propagation factor M2 smaller than 1.1. Contact resistance was determined by current-voltage measurement using the two-terminal contact resistance method. The results indicate that a laser beam power of at least 100 W is mandatory to initialize contact silicidation. Although the contact resistance is improvable by longer processing times, our experiments outline the much higher impact of laser beam power to contact silicidation compared with processing time. For laser beam powers of 300 W and processing times of 0.5 s a contact resistance of 6.5 , comparable to contacts alloyed in a lamp heated furnace at 910 °C for 2 min with a contact resistance of 10.3 , was achieved.
4H-SiC Trench Schottky Diodes for Next Generation Products
Authors: Zhang Qing Chun Jon , Duc Jennifer , Mieczkowski Van , Hull Brett , Allen Scott , Palmour John W.
Published: March 2013

A novel trench JBS structure has been developed to reduce the electrical field at the Schottky interface. Compared to the conventional planar JBS structure, the new design has reduced the reverse leakage current by 1 order of magnitude at rated voltage. The much reduced field at the Schottky interface allows an increase in the drift doping concentration, which enables a significant chip size reduction on next generation SiC Schottky diodes. This progress makes it possible to fabricate high current rating (>50 A) SiC diodes for module applications.
Development of SiC Super-Junction (SJ) Device by Deep Trench-Filling Epitaxial Growth
Authors: Kosugi Ryoji , Sakuma Yuuki , Kojima Kazutoshi , Itoh Sachiko , Nagata Akiyo , Yatsuo Tsutomu , Tanaka Yasunori , Okumura Hajime
Published: March 2013

We have tried to fabricate a super junction (SJ) structure in SiC semiconductors by the trench-filling technique. After the deep trench formation by dry etching, epitaxial layer is grown over the trench surface. Doping profile of the embedded p-type epitaxial region between the trenches is evaluated by a scanning spreading resistance microscopy (SSRM). The SSRM result reveals that the doping profile is not uniform and there exists a low concentration region along the trench side-wall. Based on the SSRM result, two-dimensional device simulations are performed using pn-type test structures with the non-uniform SJ drift layer. The simulation result shows that blocking voltage of the test structure can be optimized and becomes comparable to that of the ideal one by adjusting the concentration design of the embedded layer to balance the total charge in SJ structure.
Effect of Damage Removal Treatment after Trench Etching on the Reliability of Trench MOSFET
Authors: Miyahara Shinichiro , Watanabe H. , Yamamoto T. , Tsuruta K. , Onda S. , Soejima N. , Watanabe Y. , Morimoto J.
Published: March 2013

Guaranteeing the reliability of gate oxides is one of the most important topics to realize regarding the SiC power MOSFET. In the case of trench MOSFET, since the gate oxides are formed on the trench sidewall, the damage and roughness on the trench sidewall can affect the lifetime of the gate oxides. Generally speaking, damage removal treatment is processed after trench dry etching in most cases. In Si processes, sacrificial oxidation, H2 anneal and CDE (Chemical Dry Etching) are adopted commonly. In the case of SiC processes, sacrificial oxidation, H2 anneal, and SiH4/Ar anneal have been reported. Neverthless CDE which applied to SiC trench MOSFET has few precedents. We clarified the effect of CDE as a damage removal process. CDE has the effect of flattening the trench sidewall, and CDE makes the lifetime of gate oxides improve. CDE is an effective process for the reliability of SiC trench MOSFET.
Ni, NiSi2 and Si Secondary Ohmic Contacts on SiC with High Thermal Stability
Authors: Cichoň Stanislav , Macháč Petr , Vojtík Jiří
Published: March 2013

A method for formation of enhanced ohmic contacts on SiC for operation under adverse conditions has been studied. Ni, NiSi2 and Si ohmic contacts were prepared and tested at 300°C on air for hundreds of hours. NiSi2 and Si showed high thermal stability. Moreover, also the so called secondary contacts showed preserved good electrical and structural properties in the thermal test. The secondary ohmic contacts are formed from original ohmic contacts after they are etched off and replaced with new ones. Secondary ohmic contacts originate in a certain surface modification of the SiC substrate created during high temperature annealing of the original contact. All applied contact materials enable formation of quality secondary contacts which is especially noteworthy at NiSi2 and Si. The results bring new SiC device design perspectives with the application of secondary ohmic contacts. For example, the contact is designed so that the primary contact makes as good ohmic behavior as possible with the secondary contact providing further important contact properties as high corrosion resistance, wire-bonding simplicity etc.
Preparation and Characterization of Deposited Tetraethylorthosilicate-SiO2/SiC MIS Structure
Authors: Hemmi Mitsunori , Sakai Takashi , Yamakami Tomohiko , Hayashibe Rinpei , Kamimura Kiichi
Published: March 2013

The SiO2 layer was deposited on the 4H-SiC Si face by the thermal decomposition of tetraethylorthosilicate(TEOS) in N2 atmosphere to from MIS diodes. The post deposition annealing was effective to improve the interface properties. The interface state density of the deposited SiO2/SiC MIS structure was estimated to be the order of 1011 cm-2eV-1 by Terman method. The direct nitridation of SiC surface prior to the deposition of the SiO2 layer was effective to reduce the interface state density.
Large-Area Mapping of Dislocations in 4H-SiC from Carbon-Face (000-1) by Using Vaporized KOH Etching near 1000 °C
Authors: Yao Yong Zhao , Ishikawa Yukari , Sato Koji , Sugawara Yoshihiro , Danno Katsunori , Suzuki Hiroshi , Bessho Takeshi
Published: March 2013

To solve the problem that no preferential chemical etching is available for dislocation revelation from the carbon-face (C-face) of 4H-SiC, a novel etching technique using vaporized KOH has been developed. It was found that this etching technique can reveal the three commonly found dislocation types, i.e., threading screw dislocations (TSDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) as large hexagonal, small hexagonal and triangular, respectively. Centimeter-scale dislocation mapping has been obtained, and the pit positions on the C-face were compared with those on the Si-face, to study the dislocation propagation behaviors across the sample thickness. We have found one-to-one correlation for nearly 96% of the TSDs, indicating a dominant proportion of TSDs penetrate the whole wafer thickness. The vaporized KOH etching technique has provided an effective and inexpensive method of making inch-scale mapping of dislocation distribution for the C-face epitaxial and bulky 4H-SiC.
Slicing of Rotating SiC Ingot by Electric Discharge Machining
Authors: Yamamoto Norimasa , Yamaguchi Satarou , Kato Tomohisa
Published: March 2013

A new method of electric discharge machining (EDM) is proposed for slicing a large silicon carbide (SiC) ingot in order to realize low kerf loss and fast cut. This principle is based on the rotating ingot, and it is called the rotating slicing method (RSM). It would be defecate the cutting chip effectively and one-point discharge. In this paper, we reported results of examinations of the RSM experimentally. Unstable discharge was not observed. Discharge damages on the wire surface were fewer than those of the conventional method. Net cutting speed was almost the same as the present method for the 2-inches ingot. The rotation axis of the ingot should be perpendicular to the feed direction of the wire, and it is important to fix the performance of the EDM such as the kerf loss. Roughness of the cutting surface was 3.4 µm of Ra
Process Tolerant Single Photolithography/Implantation 120-Zone Junction Termination Extension
Authors: Veliadis Victor , Snook M. , Hearne H. , Nechay B. , Woodruff S. , Lavoie C. , Kirby C. , Imhoff Eugene A. , White J. , Davis Stuart M.
Published: March 2013

The multiple-zone junction termination extension (MJTE) is a widely used SiC edge termination technique that reduces sensitivity to implantation dose variations. It is typically implemented in multiple lithography and implantation events. To reduce process complexity, cycle time, and cost, a single photolithography/implantation (P/I) MJTE technique was developed and diodes with 3-zone and 120-zone JTEs were fabricated on the same wafer. Here, the process tolerance of the single (P/I) MJTE technique is evaluated by performing CCD monitored blocking voltage measurements on diodes from the same wafer with the 3-zone and 120-zone single (P/I) JTE. The 3-zone JTE diodes exhibited catastrophic localized avalanches at the interface between the 2nd and 3rd zones due to abrupt zone transitions. Diodes with the smooth transitioning 120-zone JTE exhibited no CCD detectable avalanches in their JTE regions up to the testing limit of 12 kV. Under thick dielectric (deposited for on-wafer diode interconnection), diodes with the single P/I 3-zone JTE failed due to significant loss of high-voltage capability, while their 120-zone JTE diode counterparts were minimally affected. Overall, the single (P/I) 120-zone JTE provides a process-tolerant and robust single P/I edge termination at no additional fabrication labor.
SiC High Power Devices – Challenges for Assembly and Thermal Management
Authors: Friedrichs Peter , Bayerer Reinhold
Published: March 2013

Silicon carbide power devices are intended and to enter new application regimes in power electronics, in fact, they are enabling components mainly if higher switching frequencies in power electronics are considered. This trend can be clearly observed since power density can be increased and efforts towards passive components and other mechanical contributions to the system can be reduced. However, this trend imposes new challenges towards the surrounding of the chips in form of the package itself and the whole system around. Stray components like inductances and impedance elements become crucial elements in the whole circuit what results in the fact that a simple exchange of silicon chips by silicon carbide in a given package can be ruled out. In addition different considerations regarding the thermal design especially in power modules arise when SiC chips are considered, triggered by the fact that the cost balance between assembly and chip is shifted compared to silicon based solutions. Thus, different optimization criteria can be used, leading to new design approaches for power modules. The following paper will give a first inside how those boundary conditions can be implemented in innovative solutions using SiC components.
Comparative Study of n-LIGBT and n-LDMOS Structures on 4H-SiC
Authors: Haeublein Volker , Temmel Gerhard , Mitlehner Heinz , Rattmann Gudrun , Strenger Christian , Hürner Andreas , Bauer Anton J. , Ryssel Heiner , Frey Lothar
Published: March 2013

N-LDMOS and n-LIGBT structures were manufactured with the same dimensions on a 4H-SiC wafer in order to allow for a direct comparison. The comparison of the devices includes output and transfer characteristics, blocking characteristics, and temperature behavior.
16 kV, 1 cm2, 4H-SiC PiN Diodes for Advanced High-Power and High-Temperature Applications
Authors: Cheng Lin , Agarwal Anant K. , O'Loughlin Michael J. , Capell Craig , Lam Khiem , Jonas Charlotte , Richmond Jim , Burk Albert A. , Palmour John W. , Ogunniyi Aderinto , O’Brien Heather , Scozzie Charles
Published: March 2013

In this work, we report our recently developed 16 kV, 1 cm2, 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×1014/cm3 doped n-type SiC drift layer with a device active area of 0.5175 cm2. Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (JF) of 350 ~ 400 A/cm2, the differential on-resistance (RON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm2 at 20°C to 5.12 mΩ·cm2 at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm2/°C, while the forward voltage drop (VF) at 100 A/cm2 reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower RON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.
Influence of in-Grown Stacking Faults on Electrical Characteristics of 4H-SiC Pin Diode with Long Carrier Lifetime
Authors: Nakayama Koji , Tanaka Atsushi , Asano Katsunori , Miyazawa Tetsuya , Tsuchida Hidekazu
Published: March 2013

The electrical characteristics of 4H-SiC pin diodes with 8H-type in-grown stacking faults are investigated. The pin diodes have epilayers with low Z1/2 center concentration formed by using the carbon implantation process. The forward voltage drops of the diode with 8H-type in-grown stacking faults are larger than those of the diode without a 8H-type in-grown stacking fault. At room temperature, the differential on-resistance of the pin diode with 8H-type in-grown stacking faults is larger than the value calculated from donor concentration in the drift layer by using the current transportation model of the unipolar device. Meanwhile, the differential on-resistances of the pin diode with 8H-type in-grown stacking faults decrease with an increase in temperature and become smaller than the calculated value at temperature of more than 200 °C.
Electrical Characterization of PiN Diodes with p+ Layer Selectively Grown by VLS Transport
Authors: Thierry-Jebali Nicolas , Lazar Mihai , Vo-Ha Arthur , Carole Davy , Soulière Véronique , Laariedh Farah , Hassan Jawad , Henry Anne , Janzén Erik , Planson Dominique , Ferro Gabriel , Brylinski Christian , Brosselard Pierre
Published: March 2013

This paper deals with electrical characterization of PiN diodes fabricated on an 8° off-axis 4H-SiC with a p++ localized epitaxial area grown by Vapour-Liquid-Solid (VLS) transport. It provides for the first time evidence that a high quality p-n junction can be achieved by using this technique followed by a High Temperature Annealing (HTA) process.
Design and Characterization of a Novel Dual-Gate 3.3 Kv 4H-Sic JFET
Authors: Chevalier Florian , Brosselard P. , Tournier D. , Grosset G. , Dupuy L. , Planson D.
Published: March 2013

This paper presents the methodology for the design of a novel 4H-SiC JFET structure able to sustain 3.3 kV. Comparisons between simulation and characterization res will be made. Taken into account the process limitation, we will also discuss the critical steps and their impact on the electrical characteristics. A design methodology based on Baliga's criterion is proposed to obtain the optimal structure. A 50 nm thick thermal oxide grown above vertical channel and the use of a buried p+ layer as second gate electrode are brand new in front of what is found in literature.
Steady-State Analysis of a Normally-Off 4H-SiC Trench Bipolar-Mode FET
Authors: Pezzimenti Fortunato , Bellone Salvatore , Della Corte Francesco Giuseppe , Nipoti Roberta
Published: March 2013

The steady state characteristics of a normally-off 4H-SiC Bipolar Mode FET (BMFET) with a low on-resistance are investigated in a wide range of currents and temperatures by means of an intensive numerical simulation study which clarifies what are the main design constraints. Specific physical models and parameters strictly related to the presently available 4H-SiC technology are carefully taken into account. A drain forward current density up to 500 A/cm2, a specific on-resistance lower than 2 mΩ∙cm2 and a current gain in the order of a few tens are calculated. The blocking voltage is in excess of 1.3 kV with a low leakage current. These results are compared with the experimental data measured in the same test conditions of another SiC power device already introduced to the market.
Evaluation of the Drive Circuit for a Dual Gate Trench SiC JFET
Authors: Rabkowski Jacek , Peftitsis Dimosthenis , Bakowski Mietek , Nee Hans Peter
Published: March 2013

The paper discusses the switching performance of the double-gate SiC trench JFET. In applications such as dc/dc converters, when fast switching is expected the standard totem-pole driver is not sufficient. The reason for this is that both the internal resistance and the parasitic capacitances of this device are significantly higher than for other designs. Instead, the gate driver with a dynamic current source is proposed in this paper to speed-up the switching process. Performed double-pulse measurements show improved dynamic performance of the tested DGTJFET with the new driver.
Sublimation Growth of Bulk AlN Crystals on SiC Seeds
Authors: Mokhov E.N. , Wolfson A.A. , Avdeev A.O. , Nagalyuk S.S. , Litvin D. P. , Vasiliev A.V. , Ramm M.G. , Helava Heikki , Makarov Yu.
Published: March 2013

AlN bulk crystals were grown by the sublimation “sandwich method” on the SiC substrates. Two types of containers were used: (i) Ta container with a surface layer of TaC created by the special annealing in contact with carbon, (ii) TaC container created by pressing of TaC powder. Cryptocrystalline AlN wafers grown by oversublimation of the original industrial high purity AlN powder were used as a vapor source. So a considerable decrease of oxygen concentration in the source (10 – 30 times) was achieved. 4H and 6H SiC bulk crystals grown by Nitride Crystals, Ltd., which were used as wafers, were crack-free, micropipe-free and have a low dislocation density (1- 4.103cm-2). The method allowed to grow thick AlN bulk crystals up to 5mm height and up to two inches in diameter with smooth mirror-like surface. X-ray diffractometry and topography of the grown AlN layers show that FWHMs of the rocking curves in ω-scan lie in the range of 60-120 arcsec.
1200 V, 3.3 mΩ SiC Bipolar Junction Transistor Power Modules
Authors: Domeij M. , Konstantinov A. , Buono B. , Bast M. , Eisele R. , Wang L. , Magnusson A.
Published: March 2013

Epoxy moulded power modules with a small footprint of 40 mm x 55 mm were fabricated with two switches, each consisting of six parallel 1200 V 50 A rated BJTs and Schottky diodes. The SiC-based power modules have very low on-resistance of 3.3 mΩ and a current gain of 80, both at room temperature. An inverter with specially designed drive circuits was constructed using the power modules and an efficiency of 98.5 % was shown for an output power of 12 kW.
Development of High-Voltage 4H-SiC GTOs for Grid-Tied Solar Inverters
Authors: Fursin Leonid , Hoffmann Frank , Hostetler John , Li Xue Qing , Fox Matthew , Alexandrov Peter , Gagliardi Mari Anne , Holveck Mark
Published: March 2013

A growing demand for smart and flexible photovoltaic power conversion and pulsed-power systems is leading to rapid development and commercialization of medium voltage 6.5 - 24 kV, wide-bang gap rectifiers and switches. Conventional silicon bipolar switches are limited to roughly 8 kV breakdown voltages and scaling up the voltage rating requires very thick wafers presenting significant manufacturing challenges. Very thick drift layers of silicon devices also translate into a very high minority carrier charge injected during forward conduction for an efficient conductivity modulation, hence leading to an extremely slow switching speed and poor efficiency. In this paper USCi presents the development of 6.5 kV 4H-SiC gate-turn-off thyristors (GTOs) with multiple floating guard-ring edge termination, and describes their application in an AC-link grid-tied solar inverter system.
Pulse Current Characterization of SiC GTO Thyristors with Etched JTE
Authors: Scharnholz Sigo , Hassdorf Ralf , Pâques Gontran , Vergne Bertrand , Planson Dominique
Published: March 2013

In this paper we highlight our latest results on high voltage SiC thyristors comprising an etched JTE. Compared to our previous design concepts, the thyristors described here are larger in size and have been investigated regarding pulsed power applications. Quasi-static on-state characteristics show that the devices withstand a repetitive current load of up to 16 A corresponding to a current density of 825 A/cm2. Their switching behavior was evaluated up to 1000 V demonstrating characteristic waveforms at turn-on and gate turn-off. Moreover, pulsed current characteristics show that the typical device under test sustained a current pulse of 20 μs with a peak value of 200 A and 10 kA/cm2, respectively.