bluuebunny/crossref_metadata_2025 huggingface dataset:
Fault Localization and Functional Testing of ICs by Lock-in Thermography
Authors: Breitenstein O. , Rakotoniaina J.P. , Altmann F. , Schulz J. , Linse G.
Published: December 2020

In this paper new thermographic techniques with significant improved temperature and/or spatial resolution are presented and compared with existing techniques. In infrared (IR) lock-in thermography heat sources in an electronic device are periodically activated electrically, and the surface is imaged by a free-running IR camera. By computer processing and averaging the images over a certain acquisition time, a surface temperature modulation below 100 µK can be resolved. Moreover, the effective spatial resolution is considerably improved compared to stead-state thermal imaging techniques, since the lateral heat diffusion is suppressed in this a.c. technique. However, a serious limitation is that the spatial resolution is limited to about 5 microns due to the IR wavelength range of 3 -5 µm used by the IR camera. Nevertheless, we demonstrate that lock-in thermography reliably allows the detection of defects in ICs if their power exceeds some 10 µW. The imaging can be performed also through the silicon substrate from the backside of the chip. Also the well-known fluorescent microthermal imaging (FMI) technique can be be used in lock-in mode, leading to a temperature resolution in the mK range, but a spatial resolution below 1 micron.
Visualisation of Electrically Active Areas Using Electron Holography
Authors: Muehle U. , Lenk A. , Lehmann M. , Lichte H.
Published: December 2020

In accordance with the predictions of the International Semiconductor Association, a further decrease in the structural widths of semiconductor devices is expected. For an in-depth characterization of actual structural details, the transmission electron microscopy (TEM)-technique is becoming more and more significant. An urgent requirement is in the visualization of dimensions of the doped regions and estimation of p-n-junctions profile with a high level spatial resolution. The off-axis electron holography, a special TEM-technique, is able to visualize electrically active areas in semiconductors. This article describes a way to achieve sample preparation for TEM-holography from actual memory products and also provides an idea of the potential of this technique for semiconductor failure analysis. It shows that different types and sizes of FET's and testing structures could be visualized by focusing on the physical basics, technical solutions, and sample preparation.
STEM (Scanning Transmission Electron Microscopy) in a SEM (Scanning Electron Microscope) for Failure Analysis and Metrology
Authors: Vanderlinde William E.
Published: December 2020

Recent developments in transmission electron microscopy (TEM) sample preparation have greatly reduced the time and cost for preparing thin samples. In this paper, a method is demonstrated for viewing thin samples in transmission in an unmodified scanning electron microscope (SEM) using an easily constructed sample holder. Although not a substitute for true TEM analysis, this method allows for spatial resolution that is superior to typical SEM imaging and provides image contrast from material structure that is typical of TEM images. Furthermore, the method can produce extremely high resolution x-ray maps that are typically produced only by scanning transmission electron microscope (STEM) systems.
A Working Method for Adapting the (SEM) Scanning Electron Microscope to Produce (STEM) Scanning Transmission Electron Microscope Images
Authors: Coyne Edward
Published: December 2020

This paper describes the problems encountered and solutions found to the practical objective of developing an imaging technique that would produce a more detailed analysis of IC material structures then a scanning electron microscope. To find a solution to this objective the theoretical idea of converting a standard SEM to produce a STEM image was developed. This solution would enable high magnification, material contrasting, detailed cross sectional analysis of integrated circuits with an ordinary SEM. This would provide a practical and cost effective alternative to Transmission Electron Microscopy (TEM), where the higher TEM accelerating voltages would ultimately yield a more detailed cross sectional image. An additional advantage, developed subsequent to STEM imaging was the use of EDX analysis to perform high-resolution element identification of IC cross sections. High-resolution element identification when used in conjunction with high-resolution STEM images provides an analysis technique that exceeds the capabilities of conventional SEM imaging.
Laser Decapsulation of Transfer Molded Plastic Packages for Failure Analysis
Authors: Carter George
Published: December 2020

Decapsulation of plastic packaged components is frequently necessary for failure analysis or product development. Conventional techniques utilize an acid etch process, which is not compatible with copper and other acid-sensitive materials. There is limited ability to alter etch geometry or selectively decapsulate individual circuit elements. Laser ablation using a raster scanned Nd:YAG laser was used for selective decapsulation of temperature sensitive passive components in a PDIP packaged DC-DC converter. Copper welds, nylon insulated ferrite, and polyesterimide insulated magnet wire were decapsulated without damage, allowing failure analysis of a miniature transformer and its associated welded leads.
Investigation of Microstructure Change on Ni-based UBM Systems in Lead Free Solder
Authors: Chun Tan Teck , Hang Tung Chih , Chong Chai Tai
Published: December 2020

The effect of interfacial reaction of Ti/Ni(V)/Au under-bump metallisation (UBM) systems in Pb free solder had been investigated. The objective was to examine the microstructure change and intermetallic formation of Ni-based UBM during isothermal annealing in lead free solder as well as to understand its impact on the UBM failure mechanism. Studies revealed that after IR reflow, spalling of Ni-Sn compound from the UBM took place. A layer of Ni-Sn-V was found to have form in the UBM. The formation of Ni-Sn-V layer was believed to have an impact on the failure mechanism of the Pb free solder. Studies also showed that doubling the Ni layer thickness in this UBM system did not have significant improvement to the overall integrity of the solder joint. However, samples with electroless Ni(P)/Au UBM in lead free solder showed relatively good thermal properties. No major change in the intermetallic composition was observed. More details on the microstructure change during thermal aging of the UBM systems were presented in this article.
Backside Hot Spot Detection
Authors: Beaudoin Félix , Perdu Philippe , Desplats Romain , de Morais Lionel Dantas , Crepel Olivier , Goupil Christophe , Haller Gérald , Beauchêne Thomas , Lewis Dean
Published: December 2020

Defects localization from the IC’s backside using hot spot detection techniques is discussed. Simulations are used to validate the applicability of hot spot detection from the silicon backside and to determine the optimal experimental conditions. The effects of the dissipated power, the substrate thickness and the defect position relative to the chip area are studied. These simulations take into account the thermal dependence of the silicon thermal conductivity. Transient simulations are also performed to evaluate the effect of modulating the power on the backside temperature difference. Backside Liquid Crystal Microscopy as well as Infrared Thermography and Thermal Laser Stimulation results on defective ICs are presented.
Infrared Microthermography for Integrated Circuit Fault Location; Sensitivity and Limitations
Authors: Kiefer S. , Nair M. , Sanders P. , Steele J. , Sutton M. , Thoma R. , Wilson S. , Albright G. , Li C. , McDonald J.
Published: December 2020

In order to understand spatial and temperature resolution limits of an infrared microscope used for fault location in semiconductor devices, numerical models and bench methods are correlated and discussed. Results clearly show fault identification capability in the sub-micron realm and “hot-spot” resolution of a few tenths of a degree K.
Failure Mechanism and Root Cause Analysis of UBGA Solder Ball Contamination
Authors: Martinez Vanessa Grace , Almero Alden , Gador Gerard
Published: December 2020

A comparison of the electrical performance and effect of different types of flux to Micro Ball Grid Array (ìBGATM) solder ball quality was conducted. The units using no clean flux were found to exhibit opens failures during off-board testing and programming. Initial analysis conducted showed that the failures were due to contact problems between the solder balls and the test/programming sockets resulting from the presence of a transparent residue on the solder balls. In-depth failure analysis, in parallel with experiments conducted in the assembly line, was performed to determine the root cause of the solder ball contamination. Three failure analysis techniques were employed, namely: Scanning Electron Microscopy (SEM), Energy Dispersive Xray Analysis (EDX), and Fourier Transform Infrared (FTIR) Spectroscopy. An initial experiment was conducted to isolate the cause of the contamination by examining the different modules in the ìBGATM assembly. Failure analysis and experimental data proved that the opens failures were due to the no clean flux residue that was deposited on the surface of the solder ball after the reflow process.
Methodologies for Isolating Faults in Multi Chip Fiber Optic Transceivers That Use GHz Mixed Signal ICs
Authors: Seo Kuhn , Wahl Brent , Mayonte Myrna , Kim Young Gon
Published: December 2020

This paper outlines a methodology which accurately identifies fault locations in Mixed Signal Integrated Circuits (ICs). The architecture of Mixed Signal ICs demands more attention during failure analysis because of the complexity of measuring both the analog and digital signals in a compact circuit. In this paper, the GHz range of data signal or radio frequency (RF) signal from an internal IC circuit will be extracted by a high-impedance active single probe in order to find the internal IC circuit failure locations. The advantages of using a single probe is that it can maneuver to extract data almost anywhere in the circuit, providing ranges of bandwidth in GHz with no loading effect on the circuits during measurement. The process of preparing a sample and extracting a signal will be described.
Missing Metal Pillar Failure Analysis-A Plug Technology Issue
Authors: Nguyen Dat , Campbell Tim , Whitlock Steven , Velaga Ankineedu
Published: December 2020

Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.
Reliability and Failure Analysis of RF MEMS Switches
Authors: De Wolf Ingrid , Jourdain Anne , Witvrouw Ann , Fiorini Paolo , Tilmans Harrie A. C. , van Spengen W. Merlijn , Modlinski Robert
Published: December 2020

In this paper we discuss reliability and failure analysis issues of RF-MEMS capacitive switches. We describe specific instrumentation and methods that can be used for testing and examination of these switches. These include SEM, AFM, SAM, static and dynamic optical investigation and electrical lifetime testing. Processing as well as testing and packaging issues are discussed.
Failure Analysis of the Digital Micromirror Device
Authors: Davis Cary , Mahin Wes , Holdford Becky
Published: December 2020

The Digital Micromirror Device (DMD) is a spatial light modulation Micro-Optical Electro-Mechanical Systems (MOEMS) device used in tabletop projectors, televisions and cinema projection systems. This device creates high resolution, high quality images by deflecting/modulating light with microscopic mirrors. Failure analysis of these devices requires superstructure, package, optics, and substructure approaches. Particles within the active array of a DMD are often killer defects, but those are the subjects of an entire discussion of their own. This paper will show evidence of failures associated with: windows in the package lids, failures of the superstructure area, and failures within the substructure. Methods for removal of the mirrors, as well as other structures, will be covered in greater detail. We will conclude with examples of analysis areas in DMD devices that show how they differ from other types of devices.
Wavefront Coded Imaging Systems for MEMS Analysis
Authors: Barton Daniel L. , Walraven Jeremy A. , Dowski Edward R. , Danz Rainer , Faulstich Andreas , Faltermeier Bernd
Published: December 2020

A new imaging technique called Wavefront Coding allows real-time imaging of three-dimensional structures over a very large depth. Wavefront Coding systems combine aspheric optics and signal processing to achieve depth of fields ten or more times greater than that possible with traditional imaging systems. Understanding the relationships between traditional and modern imaging system design through Wavefront Coding is very challenging. In high performance imaging systems nearly all aspects of the system that could reduce image quality are carefully controlled. Modifying the optics and using signal processing can increase the amount of image information that can be recorded by microscopes. For a number of applications this increase in information can allow a single image to be used where a number of images taken at different object planes had been used before. Having very large depth of field and real-time imaging capability means that very deep structures such as surface micromachined MEMS can be clearly imaged with one image, greatly simplifying defect and failure analysis.
Investigation of Choline Hydroxide for Selective Silicon Etch from a Gate Oxide Failure Analysis Standpoint
Authors: Korchnoy Valentina
Published: December 2020

A robust procedure for poly-silicon wet etch selective to SiO2 is presented. The procedure is applicable for CMOS devices and maintains the integrity of the gate oxide film. The technique uses a 50% wt. choline hydroxide aqueous solution. The optimum etching conditions, which allow exposure of gate oxide to enable its further inspection using SEM or AFM were determined. An investigation of general silicon etching characteristics of choline hydroxide, as etch rate, selectivity and surface quality, has been carried out as well.
In situ Decapsulation of Plastic Encapsulated Devices Mounted to a Printed Circuit Board
Authors: Hylton Ronald R.
Published: December 2020

In situ decapsulation of plastic devices can be used to avoid the removal or alteration of failure mechanisms caused by exposure to desoldering temperatures. This paper describes techniques to decapsulate devices mounted to a printed circuit board using materials that are readily available and easily customized to specific applications. The techniques are extended to the decapsulation of other packaging technologies, such as SBGA packages and chip-on-board assemblies. Finally, post decapsulation cleaning techniques that will not harm the printed circuit board material are presented.
Probeless FA Approach: A Breakthrough Simulation Based Failure Analysis Method
Authors: Lock ChoonHou , Wong YikChoong , Siek KahHee
Published: December 2020

A breakthrough approach was developed in which failure analysis (FA) of advanced microprocessor was carried out without the use of defect localization equipment. This technique enables the reading of internal signal value without the use of any physical probing method. This method demonstrates the same FA capability with higher success rate and shorter analysis time.
Electrical Faults Captured by In-line E-beam Inspection and Failure Analysis
Authors: Song Z.G. , Ang G.B. , Li H.Y. , Sane V. , Indahwan J. , Ansari S. , Tee S.F. , Richter W. , Oh C.K. , Redkar S.
Published: December 2020

Fault isolation is a critical step of failure analysis, which is most important for yield improvement for any new microelectronic device manufacturing. Conventionally, electrical faults are isolated by emission microscopy, liquid crystal, LIVA/TIVA and ORBIRCH etc. techniques after final test. As microelectronic devices are becoming more complicated and with multiple metal layers, failure analysis faces more challenges than before. These challenges are even tougher in wafer foundries because little device information is available. This makes yield ramp-up take longer time. Utilizing inline E-beam inspection equipment, the electrical faults can be captured at the source layer rather than after final test. E-beam inspection can be incorporated in the manufacturing line at any critical layer of front end and back-end. This paper describes the in-line E-beam inspection and presents three cases: (1) Gate-oxide issue, (2) Contact issue, and (3) Interconnect issue to demonstrate its application.
Effect of Corner Underfill Voids on Chip Scale Package (CSP) Performance Under Mechanical Loading
Authors: Canumalla Sridhar , Shetty Santosh , Hannan Nael
Published: December 2020

The critical impact of corner voids on the anticipated reliability of CSP subjected to mechanical stresses is demonstrated in this paper. Experimental and numerical simulation results indicate that the presence of a corner underfill void subjects the solder joint to stress values approaching that of a non-underfilled CSP. In the absence of underfill voids, the reliability in drop testing improved when the CSP was underfilled, and the improvement was inversely proportional to the modulus of the underfill in the range studied. Results indicate that underfill quality could potentially play a critical role in determining reliability in the field for products subjected to mechanical loading.
Method for Measuring Package to Board Interconnection Shear Strength for Area Array, Fine Pitch Packages
Authors: Yee Sridhar , Yang Hee Dong , Viswanadham Puligandla
Published: December 2020

The package to board interconnection shear strength (PBISS) test method yields an amalgamated measure of pad peel strength, solder/pad interfacial strength and bulk solder shear strength. This measure mirrors the reliability of the actual product better than any single component strength value. Using a novel fixture that ensures pure shear stresses on the package, the shear strengths of two different ball grid array packages with Sn62PbAg2 solder balls are characterized as a function of pad finish and board build-up layer type. The tests can be performed relatively quickly (< 15 minutes for an entire package on board) with good repeatability. Results indicate that the component shear test is sensitive to the variables studied and attractive as a candidate technique for quantifying solder joint quality and integrity on actual production samples for a variety of package types and sizes. Potential applications of this method are for materials/process/vendor evaluation during product development phase and as a production/supplier quality assessment tool in the factory. Key words: interconnection strength, shear test, area array package, solder joint, pad surface finish
Scanning SQUID Microscopy for Die Level Fault Isolation
Authors: Vallett David P.
Published: December 2020

This paper presents detailed results of scanning SQUID microscopy (SSM) analyses performed on the frontside and backside of both loose and packaged die. Optical and SEM images of localized defects are shown. Comparisons with alternative physical fault isolation (PFI) techniques like liquid crystal (LC), Schlieren thermal mapping (STM), temperature induced voltage alteration (TIVA), and photon emission microscopy (PEM) are included. Finally, limitations with and potential improvements for die level SSM are also discussed.
A Successful Failure Localization Approach for Defect Identification on High Resistance Interconnects
Authors: Lin Yu-Ting , Huang Y.S. , Lee C.S. , Cheng C.M. , Hsu Will
Published: December 2020

The emission microscopy effectiveness has been proven in detecting a variety of IC process leakage defects over the years. However this technique shows limitation on high resistance backend process defects localization, especially on function failures with frequency dependent but without leakage current. This paper introduces three trigger algorithms to enable precisely and directly defects localization of high resistance interconnects.
Backside FIB Device Modifications Through the BOX Layer of an SOI Device
Authors: Huynh Jeffery P. , Shannon Joseph P. , Johnson Richard W. , Santana Mike , Chu Thomas Y. , Gonzalez Manuel
Published: December 2020

Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.
Coaxial, Photon-Ion Technology Enables Direct Navigation to Buried Nodes on Planarized Surfaces, Including Silicon
Authors: Thompsona M. A. , Le Roya E. , Lundquista T. , Thompsona W. B. , Richardsonb C.
Published: December 2020

The limitation of Focused Ion Beam (FIB) and all charged beam technologies are their insensitivity to the internal composition of materials relative to surface composition. For the most part, charged particle technology cannot provide the resolution at a depth necessary for locating traces either buried under passivation or through silicon. Before CMP planarization was utilized in the industry, it was possible to correlate passivation topography with buried metal traces and manually navigate to the correct x-y coordinates necessary for edit placement. There was still a level of difficulty and CAD navigation helped immensely. With the advent of CMP-planarized metallization, CAD navigation became a necessity, yet still required passivation topography for precise alignment. Current manufacturing processes now planarize all layers, including the passivation, increasing the overall difficulty of navigation. Techniques of drilling “seeker” holes or surface demarcation using FIB and lasers to establish reference fiducials are used extensively [1,2]. Seeker holes and optical-to-FIB image correlation have been useful workarounds for the navigation-related problems presented by advanced ICs. In this paper we will discuss the advantages of Real-Time Optical Imaging coaxially integrated into the FIB, providing non-invasive navigation to nodes for front side and backside applications.
Electron Beam Induced Luminescence
Authors: Miller N.C. , Rispoli K.P.
Published: December 2020

A method to detect defects affecting laser diode radiation has been devised by imaging the induced luminescence resulting from a scanning electron beam. Electron Beam Induced Luminescence (EBIL) involves imaging the current from a sensor diode as the SEM electron beam scans across the laser diode surface. Defects preventing laser diode radiation will be shown as contrast variations in the EBIL image. This technique is similar to electron beam induced current (EBIC), reference 1, in which the electron beam provides the capability for measuring subsurface electrical and physical parameters that effect device electrical performance. However in the case of EBIL, laser diode radiation is utilized as the imaging parameter providing direct correlation between the semiconductor active layer and the resultant diode luminescence output. Alternative techniques such as Cathode Luminescence (CL), reference 2 and 5, in the scanning electron microscope (SEM) have been used for examination of semiconductor laser diodes for defects preventing radiation. However CL SEM analysis requires costly accessories, including at least an ellipsoidal mirror and a cooled photomultiplier tube sensitive to the particular laser diode output frequency. In addition the laser diode must be at the focal point of an ellipsoidal mirror, making CL SEM examination of a packaged laser diode difficult or impossible. This paper will describe the EBIL technique using several test diodes to demonstrate the ability of EBIL to image diode luminescence and defects affecting luminescent output. Deprocessing of the laser diode top electrode and EBIL operating parameters will be discussed.
What Can a Failure Analyst Do With an AFM?
Authors: Erickson Andrew N.
Published: December 2020

Atomic Force Microscopy (AFM) is gaining acceptance as a mainline failure analysis tool. Acceptance has come as the number of applications has multiplied. The serious analyst will find at his disposal a means of mapping minute changes in properties such as temperature, current, electric field, capacitance, resistance, voltage, and doping concentration. Each of these properties can be viewed in an image with resolution from microns to angstroms. Furthering its application the AFM is being used to probe sub-quarter micron nodes. The AFM’s intrinsic imaging and force control lend itself well to this job. However, traditional microscopes and probes are not well suited to the application. This paper describes the requirements and solutions to allow for nanometer probing applications.
Conducting Atomic-Force Microscopy Investigations on Thin Silicon Gate Oxides: Influence of Tip Shape and Humidity
Authors: Kremmer S. , Peissl S. , Teichert C. , Kuchar F.
Published: December 2020

Conducting Atomic-Force Microscopy (C-AFM) has a strong potential for the characterization of thin silicon oxides on the nanometer scale. Here we consider difficulties and possible errors that may arise during C-AFM experiments. Using electrostatic simulations it is shown that very sharp tips can cause an inhomogeneous electric field distribution leading to an error in the measured Fowler-Nordheim (FN) current. Further, it is found that a water film, which is ever present under ambient conditions, on the one hand homogenizes the electric field distribution but on the other hand decreases the resolution of the measurements. For increased oxide thickness this water film leads to a ring formation in the electric field maximum and therefore makes an interpretation of FN current maps difficult. The occurrence of protrusions after the applying of voltage pulses and voltage ramps to the sample is investigated by comparing experiments under ambient conditions with measurements in ultra high vacuum (UHV). From this comparison we can conclude that the observed protrusions are real topographic effects, when a water film is present on the surface. However, for UHV experiments on a baked sample it is not yet clear if the protrusions are due to charging effects or due to a reaction with a residual amount of water.
A Study on Non-Stick Aluminium Bondpads Due to Fluorine Contamination Using SEM, EDX, TEM, IC, AUGER, XPS and TOF-SIMS Techniques
Authors: Hua Y. N. , Redkar S. , Lau C. K. , Mo Z. Q.
Published: December 2020

Fluorine contamination on Al bondpads will result in corrosion, affect quality of bondpads and pose problem such as non-stick on pad (NSOP) during wire bonding at assembly process. In this paper, a fluorine contamination case in wafer fabrication will be studied. Some wafers were reported to have bondpad discoloration and bonding problem at the assembly house. SEM, EDX, TEM, AES and IC techniques were employed to identify the root cause of the failure. Failure analysis results showed that fluorine contamination had caused bondpad corrosion and thicker native aluminium oxide, which had resulted in discolored bondpads and NSOP. It was concluded that fluorine contamination was not due to wafer fab process, but was due to the wafer packaging foam material. XPS/ESCA and TOF-SIMS advanced tools were used to study the chemical and physical failure mechanism of fluorine-induced defects. An unknown Al compound was found using XPS technique and identified it as [AlF6]3- using electrochemical theories and TOF-SIMS technique. This finding was very significance, as it helped developing a theoretical electrochemical model for fluorine-induced corrosion and helped understanding of the mechanism of fluorine-induced corrosion on aluminium bondpads. It was found that fluorine contamination had formed [AlF6]3-on the affected bondpads and it had caused further electrochemical reactions and formed some new products of (NH4)+ and OH-. Then [AlF6]3- and (NH4)+ ions combined and formed a corrosive complex compound, (NH4)3(AlF6), while the OH- reacted with Al and caused further corrosion.
Hot Disk: A Transient Plane Source Technique for Rapid Thermal Conductivity Measurement
Authors: He Yi , Ng Grace S.
Published: December 2020

Hot disk metrology represents a transient plane source measurement technique for characterizing thermal conductivity and thermal diffusivity of a wide range of materials. In this technique, the hot disk sensor serves as a heat source and a thermometer. During the measurement, the sensor is sandwiched between two halves of a sample and a constant current is supplied to the sensor. The temperature increase at the sensor surface is strongly dependent on the thermal transport properties of the surrounding material. By monitoring the temperature increase as a function of time, one can determine the thermal conductivity and thermal diffusivity of the surrounding material. The main advantages of the hot disk technique include: wide thermal conductivity range, from 0.005 W/m·K to 500 W/m·K; wide range of materials, from liquid to solid; easy sample preparation; non-destructive; and more importantly, high accuracy (within 2% or better). In this paper, the basic theory of the hot disk technique will be discussed based on first principles. This technique has been successfully used to characterize a variety of thermal interface materials (TIMs) used in electronic packaging. The experimental results are in good agreement with the results obtained by another method.
Infrared Emission-based Static Logic State Imaging on Advanced Silicon Technologies
Authors: Bockelman Daniel R. , Chen Steven , Obradovic Borna
Published: December 2020

A technique is presented for mapping the logic states of CMOS integrated circuits by observing their static infrared emission. Application of the technique is shown in two case studies. The technique has the advantages of being non-invasive, having high observability and reduced complexity compared with dynamic probing techniques.
N-Channel Sub-Threshold Leakage “Pipes” Generated From Micro-Twinning Near Shallow Trench Isolation Interface
Authors: Spory Erick M.
Published: December 2020

The pursuit of shorter and narrower channel transistor processes, especially those employing Shallow Trench Isolation (STI), can readily produce devices that are increasingly susceptible to the formation of sub-threshold, leakage-generating defects. Specifically, STI N-channel devices exhibiting lengths at or below 0.35 um and with widths below 1 um, are at a heightened risk of developing a channel micro-twin defect “pipe” due to the very high compressive stress within the silicon lattice. Wider, sub-0.35 um devices can also exhibit the problem if their channels are in extremely close proximity to an active/STI corner region. Modification of the relevant process parameters can significantly alleviate this stress and reduce the frequency of “pipe” formation.
Functional Failure Analysis by Induced Stimulus
Authors: Colvin Jim
Published: December 2020

In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or e-beam to induce a parametric shift which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. RIL (Resistive Interconnect Localization) is a newer technique which can identify via anomalies functionally using induced thermal gradients to the metal but does not address how to uniformly inject the thermal energy required in the silicon to analyze timing design deficiencies and other defects.[1] With SIFT (Stimulus Induced Fault Testing), numerous stimuli will be used to identify speed, fault, and parametric differences in silicon. The heart of this technique revolves around intentionally disturbing devices with external stimuli and comparing the test criteria to reference parts or timing/voltage sensitivities. Synchronous interfacing is possible to any tester without any wiring or program changes.
Timing Characterization of Multiple Timing Domains
Authors: Weger Al an J. , McManus Moyra , Song Peilin , Muszynski Andy
Published: December 2020

Commonly used timing measurement tools are often limited to probing a circuit running at one single frequency [1,2]. In reality, multiple frequencies may be present on chip, and that can lead to timing problems which render the chip inoperable within certain frequency ranges. We will describe a simple modification to a Picosecond Imaging Circuit Analysis (PICA [3]) instrumentation whih permits the simultaneous measurement of timing in multiple frequency domains.
Methodology for TEM Analysis of Barrier Profiles
Authors: Lee Tan-Chen , Huang Jui-Yen , Chen Li-Chien , Hwang Ruey-Lian , Su David
Published: December 2020

Device shrinkage has resulted in thinner barriers and smaller vias. Transmission Electron Microscopy (TEM) has become a common technique for barrier profile analysis because of its high image resolution. TEM sample preparation and image interpretation becomes difficult when the size of the small cylindrical via is close to the TEM sample thickness. Effects of different sample thickness and specimen preparation methods, therefore, have been investigated. An automatic FIB program has been shown to be useful in via sample preparation. Techniques for imaging a TEM specimen will be discussed in the paper. Conventional TEM bright field (BF) image is adequate to examine the barrieronly via; however, other techniques are more suitable for a Cu filled via.
Studies on Chemical Methods to Expose Gate/Tunnel Oxide and Identification of Gate/Tunnel Oxide Defects in Wafer Fabrication
Authors: Hua Y. N. , Ang G. B. , Redkar S. , Yogaspari  , Richter Wilma
Published: December 2020

In failure analysis of wafer fabrication, currently, three different types of chemical methods including 6:6:1 (Acetic Acid/HNO3/HF), NaOH and Choline are used in removing polysilicon (poly) layer and exposing the gate/tunnel oxide underneath. However, usage is limited due to their disadvantages. For example, 6:6:1 is a relatively fast etchant, but it is difficult to control the etch time and keep the oxide layer intact. Also, while using NaOH to remove poly and expose the silicon oxide, the solution needs to be heated. It is also difficult to etch a poly layer with a WSix or a CoSix silicide using NaOH. In this paper, we will discuss these 3 etchants in terms of their advantages and disadvantages. We will then introduce a new poly etchant, called HB91. HB91 is useful for removing poly to expose the gate/tunnel oxide for identification of related defects. HB91 is actually a mixture of two chemicals namely nitric acid (HNO3) and buffer oxide etchant (BOE) in a 9:1 ratio. The experimental results show that it is highly selective in poly removal with respect to the gate/tunnel oxide and is a suitable poly etchant especially for removing polysilicon with/without WSix and CoSix in the large capacitor structure. Application results of this poly etchant (HB91) will be presented.
Diagnosis Using Quiescent Signal Analysis on a Commercial Power Grid
Authors: Patel Chintan , Staroswiecki Ernesto , Pawar Smita , Acharyya Dhruva , Plusquellic Jim
Published: December 2020

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses IDDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of IDDQ contour plots. A “family” of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.
A New Technique for Scan Chain Failure Diagnosis
Authors: Guo Ruifeng , Venkataraman Srikanth
Published: December 2020

In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain failure is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The experimental results based on simulation and silicon units for several products show the effectiveness of the proposed method.
SEM in-situ Study of Electromigaration Induced Degradation Processes in Embedded Copper Interconnects
Authors: Langer Eckhard , Meyer Moritz Andreas , Zschech Ehrenfried , Herrmann Marko
Published: December 2020

In this paper an experimental set-up is presented that allows the Scanning Electron Microscope (SEM) in-situ investigation of electromigration phenomena in fully embedded copper interconnect structures, both from a top-down and from a cross-sectional perspective. The condition that the interconnects under test are fully embedded during the in-situ experiment is achieved using a Focussed Ion Beam (FIB) preparation technique. A SEM is equipped with a custom-made heating stage. During the experiment the void formation, growth and agglomeration process can be observed. Post-mortem cross-section analysis after the interconnect failure reveals e.g. a relationship between the microstructure of the copper contact and the non-constant growth rate of the voids.
Single Element Time Resolved Emission Probing for Practical Microprocessor Diagnostic Applications
Authors: Varner Elizabeth B. , Young Chi-Lin (Kenny) , Ng Hung M.(Paul) , Maher Steven P. , Eiles Travis M. , Lee Birk
Published: December 2020

This paper presents the first single element time resolved emission (TRE) data collected from microprocessors fabricated with 0.13 µm process silicon using tester loop lengths, and in many cases acquisition times, comparable to laser voltage probing. The data presented here demonstrate that TRE tools with highly sensitive single element detectors can be used for practical microprocessor circuit diagnostics with reasonable acquisition times.
Next-Generation Optical Probing Tools for Design Debug of High Speed Integrated Circuits
Authors: Lo William , Wilsher Kenneth , Malinsky Richard , Boiadjieva Nina , Tsao Chun-Cheng , Leibowitz Martin , Deslandes Hervé
Published: December 2020

Time-resolved photon emission (TRPE) results, obtained using a new superconducting, single-photon detector (SSPD) are reported. Detection efficiency (DE) for large area detectors has recently been improved by >100x without affecting SSPDs inherently low jitter (≈30 ps) and low dark-count rate (<30 s-1). TRPE measurements taken from a 0.13 μm geometry CMOS IC are presented. A single laser, time-differential probing scheme that is being investigated for next-generation laser voltage probing (LVP) is also discussed. This new scheme is designed to have shot-noise-limited performance, allowing signals as small as 100 parts-per-million (ppm) to be reliably measured.
TEM Direct Observation of Gate Oxide Defects
Authors: Wang Nathan , Daniel Sabbas
Published: December 2020

This paper describes the FA technique to identify very tiny defects that cause gate oxide damage. These defects as examples include crystal originated pits, gate oxide pinhole and residual. The defects may have the same electrical signature; the same kind of holes in gate oxide will be seen when the sample is simply deprocessed with wet chemical and observed with SEM; but they are distinctly different mechanisms. Electrical test, emission microscope, FIB and SEM were used to localize the defect and TEM for the final analysis. The application of planeview, cross-sectional and three-dimensional TEM is discussed.
Debug and Fault Isolation of an RF/IF Circuit for 3G Cellular Applications With High Leakage: A Case Study
Authors: Wilson Syd , Nair Manoj , Vicker Michael , Meador Richard B. , Smoot George , Sanders Paul , Kiefer Scott , Steele John , Sutton Mauri
Published: December 2020

First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.
Scanning Magnetoresistive Microscopy for Die-Level Sub-Micron Current Density Mapping
Authors: Schrag B. D. , Liu X. Y. , Carter M. J. , Xiao Gang
Published: December 2020

In this paper, we will present a new technique for fault isolation and failure analysis in integrated circuits based on a scanning magnetoresistive imaging system. By detecting the stray magnetic fields at the surface of a chip using magnetic sensors with sub-micron spatial resolution, we are able to obtain a full map of in-plane current densities, resolving features smaller than 100 nanometers. We will briefly discuss the capabilities and limitations of the technique and will present results on a variety of frontside and backside samples.
High-Angle Electron Microscopy Technique for Analysis of Thin Film Contamination on IC Package Exteriors
Authors: Barbieri Thomas , Schaper Jake , Dimuzio Pete
Published: December 2020

Yield loss during final evaluation was occasionally associated with low level leakage current between neighboring pins on a Motorola IC product. A series of simple experiments on reject samples indicated that the source of the leakage was on or near the package surface and likely to be due to a conductive film on the backside of the package between the leads. A technique was developed to detect and analyze the film using high tiltangle and low accelerating voltage on the SEM and EDS. The shallow penetration depth of the electron beam permitted observation of a thin and continuous film on the backside of the failed package. Likewise, the EDS sampling volume was constrained to the outermost layers of the specimen surface, such that a significant signal was generated from the identified film, even at low accelerating voltage. An EDS line scan across a surface region containing the film resulted in an excellent correlation between increased levels of metallic elements gold and copper and the presence of the film.
X-ray Laminography Benchmarking and Failure Analysis of Solder Joint Interfaces
Authors: Thomson Barbara A. , Armendariz Norman J.
Published: December 2020

A new generation X-ray laminography (XRL) automated Xray inspection (AXI) tool was evaluated for surface mount technology (SMT) assembly defect detection and was qualified using formal “benchmark” comparative analysis processes. In addition, defect characterization was performed using the XRL AXI system in manual X-ray inspection mode to correlate various failure modes and mechanisms at SMT solder joint interfaces for selected non-destructive failure analyses and technology development. Since ball grid array (BGA) solder joint quality is a great concern in board assembly, test technology development and failure analysis teams explored the use of XRL AXI as a method to detect and monitor BGA ball abnormalities using XRL AXI-generated solder ball images and measurements. It was found that XRL AXI was able to successfully discern differences in the shape, location and diameter of the suspect BGA solder balls from XRL AXI horizontal image planes (slices) for physical failure analysis and reliability issues not previously detected using conventional X-ray transmission or electrical methods. Subsequent metallographic x-sectioning correlated the XRL AXI mages to the physical condition of the suspected second level interconnect (SLI) solder joint location.
SRAM Failure Analysis Strategy
Authors: Egger P. , Burmer C.
Published: December 2020

The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.
Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps
Authors: Zanon T. , Ferdman M. , Maly W. , Komeyli K.
Published: December 2020

SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently. We also demonstrate the usability of our analysis framework using real BFM test data from a large, modern SRAM test vehicle.