bluuebunny/crossref_metadata_2025 huggingface dataset:
Measurement properties of patient-reported outcome measures (PROMs) used in adult patients with chronic kidney disease: a systematic review protocol
Authors: Aiyegbusi Olalekan Lee , Kyte Derek , Cockwell Paul , Marshall Tom , Keeley Thomas , Gheorghe Adrian , Calvert Melanie
Published: October 2016

Introduction

Chronic kidney disease (CKD) is associated with symptoms that can significantly reduce the quality of life (QoL) of patients. Patient-reported outcome measures (PROMs) may facilitate the assessment of the impact of disease and treatment on the QoL, from a patient perspective. PROMs can be used in research and routine clinical practice.

Methods and analysis

A systematic review of studies evaluating the measurement properties of PROMs in adults with CKD will be conducted. MEDLINE, EMBASE, PsycINFO and CINAHL Plus will be systematically searched from inception. Hand searching of reference lists and citations of included studies will be carried out. 2 reviewers will independently screen the titles and abstracts of all the studies retrieved during the systematic search to determine their eligibility. The COnsensus-based Standards for the selection of health Measurement Instruments (COSMIN) checklist will be used to appraise the methodological quality of the selected studies following the full-text review. Data on the study population, questionnaire characteristics and measurement properties will be extracted from the selected papers. Finally, a narrative synthesis of extracted data will be undertaken.

Ethics and dissemination

Ethical permissions are not required for this study as data from published research articles will be used. Findings will be disseminated through publication in a peer-reviewed journal and presented at conferences. This systematic review will provide a comprehensive assessment of the measurement properties of PROMs currently available for use in adult patients with CKD and present evidence which may inform the selection of measures for use in research and clinical practice.

Trial registration number

CRD42016035554.
Separating the wheat from the chaff: region of interest combined with metal artifact reduction for completion angiography following cerebral aneurysm treatment
Authors: Duckworth Edward A M , Nickele Chris , Schafer Sebastian , Bauer Sebastian , Scholz Bernhard , Elijovich Lucas , Hoit Daniel , Doss Vinodh T , Arthur Adam S
Published: October 2016

Introduction

Following complicated endovascular or microsurgical treatments, assessment of radiographic outcome can be challenging due to device resolution and metallic artifact. Two-dimensional and three-dimensional angiography can reveal information about flow and aneurysm obliteration, but may be limited by beam hardening, overlapping vessels, and image degradation in the region of metallic implants. In this study, we investigated the combination of a collimated volumetric imaging (volume of interest, VOI) protocol followed by metal artifact reduction (MAR) post-processing to evaluate the correct positioning of stents, flow diverters, coils, and clips while limiting the radiation dose to the patient.

Methods

9 patients undergoing 10 procedures were included in our study. All patients underwent endovascular or surgical treatment of a cerebral aneurysm involving stents, flow diverting stents, coils, and/or clips followed by either immediate or early postoperative evaluation of our protocol.

Results

Image datasets corrected for metallic artifacts (VOI-MAR) were judged to be better—a statistically significant finding—than image datasets only corrected for field of view truncation (VOI alone). Qualitatively, images were more interpretable and informative with regards to device position and apposition to the vessel wall for those cases involving a pipeline, and with regards to encroachment on the parent artery and possible residual aneurysm, in all cases.

Conclusions

VOI acquisition combined with MAR post-processing provides for accurate and informative evaluation of cerebral aneurysm treatment while limiting the radiation dose to patients.
Subgrade resilient modulus prediction using light-weight deflectometer data
Authors: Mousavi S. Hamed , Gabr Mohammed A. , Borden Roy H.
Published: October 2016

Resilient modulus has been used for decades as an important parameter in pavement structure design. Resilient modulus, like other elasticity moduli, increases with increasing confining stress and decreases with increasing deviatoric stress. Several constitutive models have been proposed in the literature to calculate resilient modulus as a function of stress state. The most recent model, recommended by the Mechanistic–empirical pavement design guide (MEPDG) and used in this paper, calculates resilient modulus as a function of bulk stress, octahedral shear stress, and three fitting coefficients: k1, k2, and k3. Work in this paper presents a novel approach for predicting resilient modulus of subgrade soils at various stress levels based on light-weight deflectometer (LWD) data. The proposed model predicts the MEPDG resilient modulus model coefficients (k1, k2, and k3) directly from the ratio of applied stress to surface deflection measured during LWD testing. The proposed model eliminates uncertainties associated with needed input parameters for surface modulus (ELWD) calculation, such as the selection of an appropriate value of Poisson’s ratio for the soil layer and shape factor. The proposed model was validated with independent data from other studies reported in the literature.
Dynamics of growth-based survival mechanisms in Japanese anchovy (Engraulis japonicus) larvae
Authors: Takasuka Akinori , Sakai Ayumu , Aoki Ichiro
Published: October 2016

Three growth-based survival mechanisms were tested for multiple cohorts of Japanese anchovy (Engraulis japonicus) larvae in Sagami Bay. Through otolith microstructure analysis, growth trajectories and histories of samples of the survivors were compared with those of the original populations to examine size- and growth-selective mortality to test the “bigger is better” and “growth-selective predation” mechanisms, respectively. The effects of growth rates on the timing of metamorphosis were examined to test the “stage duration” mechanism. The bigger is better and growth-selective predation mechanisms were detected to be effective in two and six of eight seasonal cohorts, respectively. Results contrary to the bigger is better and growth-selective predation mechanisms were obtained from three and two of eight cohorts, respectively. The stage duration mechanism was evaluated to be effective for both of two cohorts that were testable. Overall, none of the three mechanisms were universally appropriate for all of the cohorts. The relative contributions of the three mechanisms were dynamic, although the growth-selective predation mechanism was identified to be the major one in anchovy larvae in the study site.
Subsidence around oceanic ridges along passive margins: NE Arabian Sea
Authors: Misra Achyuta Ayan , Banerjee Smita , Kundu Nishikanta , Mukherjee Brunti
Published: October 2016

The northern part of the western continental margin of India formed due to the separation of the Seychelles from India at
c.
63 Ma. This produced offshore tectonic elements such as the Gop Rift, the Saurashtra Volcanic Platform (SVP) and the Laxmi Ridge, as well as numerous seamounts, e.g. the Raman and Panikkar seamounts. The Laxmi Ridge and the Laxmi Basin have been studied using high-resolution 2D reflection seismic data and well data. Patch and pinnacle carbonate reefs, indicating shallow waters, are common in the north, whereas large, isolated platforms are usually noted in the south. Palaeo-depth estimates are made from well biostratigraphy. Subsidence studies of the SVP suggest that the burial history is consistent with the anomalously hot Réunion plume. We have performed a subsidence analysis south of the SVP on the Laxmi Ridge and Laxmi Basin. The sediment-unloaded basement depths, estimated using using flexural isostasy with effective elastic thicknesses of 10–40 km have been found to be 2000–4000 m in areas where carbonates exist. These carbonates indicate <200 m bathymetry at
c.
65 Ma, and the subsidence discrepancy is thus due to thermal cooling or anomalous heating due to the Deccan plume. Patch and pinnacle reefs in the north suggests that either the rise in sea-level or the rate of subsidence of the basement were fast. The presence of large platforms in the south indicates otherwise. This is possibly due to a greater influence from the Indus Fan sediments towards the north. In addition, the Laxmi Ridge is a spreading centre that remained emergent near or above sea-level due to plume support, which was also greater in the south due to proximity to the plume. When the plume support discontinued, the ridge subsided quickly to present-day depths, which matches the subsidence expected for 60–70 Myr old oceanic crust.

Supplementary material:
A table is available at
https://doi.org/10.6084/m9.figshare.c.3470751
Earliest microbial trace fossils in Archaean pillow lavas under scrutiny: new micro-X-ray absorption near-edge spectroscopy, metamorphic and morphological constraints
Authors: Grosch Eugene G. , Muñoz Manuel , Mathon Olivier , McLoughlin Nicola
Published: October 2016

Filament-shaped titanite microtextures in early Archaean (
c.
3.47 Ga) metabasalts from the Barberton Greenstone Belt of South Africa have been argued to represent Earth's oldest microbial trace fossils, but petrological data on the environmental conditions that led to the formation of these microtextures are sparse. We present here new metamorphic constraints on the equilibrium mineral assemblage containing the titanite microtextures, together with Fe speciation redox variations in the chlorite matrix surrounding the microtextures and morphospace analysis of the microtextures to test their biogenicity. Thermodynamic phase diagram modelling using a calculated rock microdomain composition indicated that the titanite mineral assemblage is stable at temperature conditions of
T
=240–360°C. The high-resolution quantitative mapping results combined with micro-X-ray absorption near-edge spectroscopy at the Fe
K
-edge in chlorite revealed that the titanite microtextures are located in low-temperature, high XFe
3+
chlorite bands, veins and microdomains, supporting an origin as abiotic, retrograde mineral cooling textures. These new data, combined with a late
c.
2.9 Ga U–Pb date for the titanite, are incompatible with the existing biological model, which invokes microbial micro-tunnel formation followed by titanite ‘infilling’ and preservation in the early Archaean sub-seafloor. The continuum of titanite morphologies reported herein indicates that titanite morphology cannot be used as reliable evidence in support of a biogenic origin in these metavolcanic rocks. It is proposed that the titanite microtextures of purported biogenic origin from other greenstone belts, such as the Pilbara Craton of Western Australia, also deserve to be scrutinized by high-resolution petrological investigations.

Supplementary material:
Representative electron microprobe analyses of retrograde minerals and µXANES spectra and corresponding fitted pre-edge peaks for all spot analyses are available at
https://doi.org/10.6084/m9.figshare.c.3498465
Game-Theory-Based Active Defense for Intrusion Detection in Cyber-Physical Embedded Systems
Authors: Wang Kun , Du Miao , Yang Dejun , Zhu Chunsheng , Shen Jian , Zhang Yan
Published: October 2016

Cyber-Physical Embedded Systems (CPESs) are distributed embedded systems integrated with various actuators and sensors. When it comes to the issue of CPES security, the most significant problem is the security of Embedded Sensor Networks (ESNs). With the continuous growth of ESNs, the security of transferring data from sensors to their destinations has become an important research area. Due to the limitations in power, storage, and processing capabilities, existing security mechanisms for wired or wireless networks cannot apply directly to ESNs. Meanwhile, ESNs are likely to be attacked by different kinds of attacks in industrial scenarios. Therefore, there is a need to develop new techniques or modify the current security mechanisms to overcome these problems. In this article, we focus on Intrusion Detection (ID) techniques and propose a new attack-defense game model to detect malicious nodes using a repeated game approach. As a direct consequence of the game model, attackers and defenders make different strategies to achieve optimal payoffs. Importantly, error detection and missing detection are taken into consideration in Intrusion Detection Systems (IDSs), where a game tree model is introduced to solve this problem. In addition, we analyze and prove the existence of pure Nash equilibrium and mixed Nash equilibrium. Simulations show that the proposed model can both reduce energy consumption by up to 50% compared with the existing All Monitor (AM) model and improve the detection rate by up to 10% to 15% compared with the existing Cluster Head (CH) monitor model.
MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs
Authors: Murillo Luis Gabriel , Bücs Ròbert Lajos , Leupers Rainer , Ascheid Gerd
Published: October 2016

Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi- and many-processor systems-on-chip (MPSoCs). VPs provide unrivaled controllability and visibility of the target, which can be exploited to examine bugs that cannot be reproduced easily in real hardware (e.g., bugs originating from races or happening during a processor stand-by state). However, VPs as employed in practice for debugging are generally underutilized. The accompanying debug ecosystem is based mostly on traditional tools, such as step-based debuggers and traces, that fall short to address the enormous complexity of modern MPSoCs and their parallel software. Finding a bug is still largely left to the developer’s experience and intuition, using manual means rather than automated or systematic solutions that exploit the controllability and visibility of VPs. Profiting from VPs for MPSoC software debugging is an open question. To bridge this gap, this article presents a novel framework for debug visualization and execution control that, relying on the many benefits of VPs, helps to identify and test possible concurrency-related bug scenarios. The framework allows examining and steering the target system by manipulating an abstract graph that highlights relevant inter-component interactions and dependencies. The proposed framework reduces the effort required to understand complex concurrency patterns and helps to expose bugs. Its efficacy is demonstrated on
(i)
a shared memory symmetric multi-processing platform executing Linux and parallel benchmarks, and
(ii)
a distributed automotive system for driver assistance applications.
Image-Content-Aware I/O Optimization for Mobile Virtualization
Authors: Chen Renhai , Wang Yi , Hu Jingtong , Liu Duo , Shao Zili , Guan Yong
Published: October 2016

Mobile virtualization introduces extra layers in software stacks, which leads to performance degradation. Notably, each I/O operation has to pass through several software layers to reach the NAND-flash-based storage systems. This article targets at optimizing I/O for mobile virtualization, since I/O becomes one of major performance bottlenecks that seriously affects the performance of mobile devices. Among all the I/O operations, a large percentage is to update metadata. Frequently updated metadata not only degrade overall I/O performance but also severely reduce flash memory lifetime.

In this article, we propose a novel I/O optimization technique to identify the metadata of a guest file system that is stored in a virtual machine image file and frequently updated. Then, these metadata are stored in a small additional non-volatile memory (NVM), which is faster and more endurable to greatly improve flash memory’s performance and lifetime. To the best of our knowledge, this is the first work to identify the file system metadata from regular data in a guest OS image file with NVM optimization. The proposed scheme is evaluated on a real hardware embedded platform. The experimental results show that the proposed techniques can improve write performance to 45.21% in mobile devices with virtualization.
A Lightweight Framework for the Dynamic Creation and Configuration of Virtual Platforms in SystemC
Authors: Sauer Christian , Loeb Hans-Peter
Published: October 2016

Virtual prototypes leverage SystemC/TLM for simulating programmable platforms comprising hundreds of modules. Their efficient creation and configuration is vital for acceptable turnaround times, for example, during performance exploration or software development. Therefore, our lightweight framework provides a factory that creates designs from abstract descriptions of module instances, properties, and connections. Modules mark properties as creation or runtime parameters. The resulting generic design descriptions are usable by non-experts and enable front-ends. The infrastructure is a small C++ library with only 1,350 lines of code that can be combined with existing SystemC/TLM models and simulation kernels. An industrial case study of a complex multiprocessor SoC shows a distinct productivity gain.
Cnvlutin
Authors: Albericio Jorge , Judd Patrick , Hetherington Tayler , Aamodt Tor , Jerger Natalie Enright , Moshovos Andreas
Published: October 2016

This work observes that a large fraction of the computations performed by Deep Neural Networks (DNNs) are intrinsically ineffectual as they involve a multiplication where one of the inputs is zero. This observation motivates
Cnvlutin
(
CNV
), a value-based approach to hardware acceleration that eliminates most of these ineffectual operations, improving performance and energy over a state-of-the-art accelerator with no accuracy loss.
CNV
uses hierarchical data-parallel units, allowing groups of lanes to proceed mostly independently enabling them to skip over the ineffectual computations. A co-designed data storage format encodes the computation elimination decisions taking them off the critical path while avoiding control divergence in the data parallel units. Combined, the units and the data storage format result in a data-parallel architecture that maintains wide, aligned accesses to its memory hierarchy and that keeps its data lanes busy. By loosening the ineffectual computation identification criterion,
CNV
enables further performance and energy efficiency improvements, and more so if a loss in accuracy is acceptable. Experimental measurements over a set of state-of-the-art DNNs for image classification show that
CNV
improves performance over a state-of-the-art accelerator from 1.24× to 1.55× and by 1.37× on average without any loss in accuracy by removing zero-valued operand multiplications alone. While
CNV
incurs an area overhead of 4.49%, it improves overall
EDP
(Energy Delay Product) and
ED
2
P
(Energy Delay Squared Product) on average by 1.47× and 2.01×, respectively. The average performance improvements increase to 1.52× without any loss in accuracy with a broader ineffectual identification policy. Further improvements are demonstrated with a loss in accuracy.
ISAAC
Authors: Shafiee Ali , Nag Anirban , Muralimanohar Naveen , Balasubramonian Rajeev , Strachan John Paul , Hu Miao , Williams R. Stanley , Srikumar Vivek
Published: October 2016

A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks.

This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8×, 5.5×, and 7.5× in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.
Towards statistical guarantees in controlling quality tradeoffs for approximate acceleration
Authors: Mahajan Divya , Yazdanbakhsh Amir , Park Jongse , Thwaites Bradley , Esmaeilzadeh Hadi
Published: October 2016

Conventionally, an approximate accelerator replaces every invocation of a frequently executed region of code without considering the final quality degradation. However, there is a vast decision space in which each invocation can either be delegated to the accelerator---improving performance and efficiency--or run on the precise core---maintaining quality. In this paper we introduce M
ithra
, a co-designed hardware-software solution, that navigates these tradeoffs to deliver high performance and efficiency while lowering the final quality loss. M
ithra
seeks to identify whether each individual accelerator invocation will lead to an undesirable quality loss and, if so, directs the processor to run the original precise code.

This identification is cast as a binary classification task that requires a cohesive co-design of hardware and software. The hardware component performs the classification at runtime and exposes a knob to the software mechanism to control quality tradeoffs. The software tunes this knob by solving a
statistical optimization problem
that maximizes benefits from approximation while providing statistical guarantees that final quality level will be met with high confidence. The software uses this knob to tune and train the hardware classifiers. We devise two distinct hardware classifiers, one table-based and one neural network based. To understand the efficacy of these mechanisms, we compare them with an ideal, but infeasible design,
the oracle.
Results show that, with 95% confidence the table-based design can restrict the final output quality loss to 5% for 90% of unseen input sets while providing 2.5× speedup and 2.6× energy efficiency. The neural design shows similar speedup however, improves the efficiency by 13%. Compared to the table-based design, the oracle improves speedup by 26% and efficiency by 36%. These results show that M
ithra
performs within a close range of the oracle and can effectively navigate the quality tradeoffs in approximate acceleration.
PowerChop
Authors: Laurenzano Michael A. , Zhang Yunqi , Chen Jiang , Tang Lingjia , Mars Jason
Published: October 2016

On-core microarchitectural structures consume significant portions of a processor's power budget. However, depending on application characteristics, those structures do not always provide (much) performance benefit. While timeout-based power gating techniques have been leveraged for underutilized cores and inactive functional units, these techniques have not directly translated to high-activity units such as vector processing units, complex branch predictors, and caches. The performance benefit provided by these units does not necessarily correspond with unit activity, but instead is a function of application characteristics.

This work introduces P
ower
C
hop
, a novel technique that leverages the unique capabilities of HW/SW co-designed hybrid processors to enact unit-level power management at the application phase level. P
ower
C
hop
adds two small additional hardware units to facilitate phase identification and triggering different power states, enabling the software layer to cheaply track, predict and take advantage of varying
unit criticality
across application phases by powering gating units that are not needed for performant execution. Through detailed experimentation, we find that P
ower
C
hop
significantly decreases power consumption, reducing the leakage power of a hybrid server processor by 9% on average (up to 33%) and a hybrid mobile processor by 19% (up to 40%) while introducing just 2% slowdown.
ASIC clouds
Authors: Magaki Ikuo , Khazraee Moein , Gutierrez Luis Vega , Taylor Michael Bedford
Published: October 2016

GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance.

In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost of ownership (TCO) of large, high-volume chronic computations, which are becoming increasingly common as more and more services are built around the Cloud model. On the surface, the creation of ASIC clouds may seem highly improbable due to high NREs and the inflexibility of ASICs. Surprisingly, however, large-scale ASIC Clouds have already been deployed by a large number of commercial entities, to implement the distributed Bitcoin cryptocurrency system.

We begin with a case study of Bitcoin mining ASIC Clouds, which are perhaps the largest ASIC Clouds to date. From there, we design three more ASIC Clouds, including a YouTube-style video transcoding ASIC Cloud, a Litecoin ASIC Cloud, and a Convolutional Neural Network ASIC Cloud and show 2-3 orders of magnitude better TCO versus CPU and GPU.

Among our contributions, we present a methodology that given an accelerator design, derives Pareto-optimal ASIC Cloud Servers, by extracting data from place-and-routed circuits and computational fluid dynamic simulations, and then employing clever but brute-force search to find the best jointly-optimized ASIC, DRAM subsystem, motherboard, power delivery system, cooling system, operating voltage, and case design. Moreover, we show how data center parameters determine which of the many Pareto-optimal points is TCO-optimal. Finally we examine when it makes sense to build an ASIC Cloud, and examine the impact of ASIC NRE.
Warped-slicer
Authors: Xu Qiumin , Jeon Hyeran , Kim Keunsoo , Ro Won Woo , Annavaram Murali
Published: October 2016

As technology scales, GPUs are forecasted to incorporate an ever-increasing amount of computing resources to support thread-level parallelism. But even with the best effort, exposing massive thread-level parallelism from a single GPU kernel, particularly from general purpose applications, is going to be a difficult challenge. In some cases, even if there is sufficient thread-level parallelism in a kernel, there may not be enough available memory bandwidth to support such massive concurrent thread execution. Hence, GPU resources may be underutilized as more general purpose applications are ported to execute on GPUs. In this paper, we explore multiprogramming GPUs as a way to resolve the resource underutilization issue. There is a growing hardware support for multiprogramming on GPUs. Hyper-Q has been introduced in the Kepler architecture which enables multiple kernels to be invoked via tens of hardware queue streams. Spatial multitasking has been proposed to partition GPU resources across multiple kernels. But the partitioning is done at the coarse granularity of streaming multiprocessors (SMs) where each kernel is assigned to a subset of SMs. In this paper, we advocate for partitioning a single SM across multiple kernels, which we term as intra-SM slicing. We explore various intra-SM slicing strategies that slice resources within each SM to concurrently run multiple kernels on the SM. Our results show that there is not one intra-SM slicing strategy that derives the best performance for all application pairs. We propose
Warped-Slicer
, a dynamic intra-SM slicing strategy that uses an analytical method for calculating the SM resource partitioning across different kernels that maximizes performance. The model relies on a set of short online profile runs to determine how each kernel's performance varies as more thread blocks from each kernel are assigned to an SM. The model takes into account the interference effect of shared resource usage across multiple kernels. The model is also computationally efficient and can determine the resource partitioning quickly to enable dynamic decision making as new kernels enter the system. We demonstrate that the proposed
Warped-Slicer
approach improves performance by 23% over the baseline multiprogramming approach with minimal hardware overhead.
Base-victim compression
Authors: Gaur Jayesh , Alameldeen Alaa R. , Subramoney Sreenivas
Published: October 2016

The memory wall has motivated many enhancements to cache management policies aimed at reducing misses. Cache compression has been proposed to increase effective cache capacity, which potentially reduces capacity and conflict misses. However, complexity in cache compression implementations could increase cache power and access latency. On the other hand, advanced cache replacement mechanisms use heuristics to reduce misses, leading to significant performance gains. Both cache compression and replacement policies should collaborate to improve performance.

In this paper, we demonstrate that cache compression and replacement policies can interact negatively. In many workloads, performance gains from replacement policies are lost due to the need to alter the replacement policy to accommodate compression. This leads to sub-optimal replacement policies that could lose performance compared to an uncompressed cache. We introduce a novel, opportunistic cache compression mechanism, Base-Victim, based on an efficient cache design. Our compression architecture improves performance on top of advanced cache replacement policies, and guarantees a hit rate at least as high as that of an uncompressed cache. For cache-sensitive applications, Base-Victim achieves an average 7.3% performance gain for single-threaded workloads, and 8.7% gain for four-thread multi-program workload mixes.
Bit-plane compression
Authors: Kim Jungrae , Sullivan Michael , Choukse Esha , Erez Mattan
Published: October 2016

As key applications become more data-intensive and the computational throughput of processors increases, the amount of data to be transferred in modern memory subsystems grows. Increasing physical bandwidth to keep up with the demand growth is challenging, however, due to strict area and energy limitations. This paper presents a novel and lightweight compression algorithm,
Bit-Plane Compression (BPC)
, to increase the effective memory bandwidth. BPC aims at homogeneously-typed memory blocks, which are prevalent in many-core architectures, and applies a smart data transformation to both improve the inherent data compressibility and to reduce the complexity of compression hardware. We demonstrate that BPC provides superior compression ratios of 4.1:1 for integer benchmarks and reduces memory bandwidth requirements significantly.
XED
Authors: Nair Prashant J. , Sridharan Vilas , Qureshi Moinuddin K.
Published: October 2016

Large-granularity memory failures continue to be a critical impediment to system reliability. To make matters worse, as DRAM scales to smaller nodes, the frequency of unreliable bits in DRAM chips continues to increase. To mitigate such scaling-related failures, memory vendors are planning to equip existing DRAM chips with On-Die ECC. For maintaining compatibility with memory standards, On-Die ECC is kept invisible from the memory controller.

This paper explores how to design high reliability memory systems in presence of On-Die ECC. We show that if On-Die ECC is not exposed to the memory system, having a 9-chip ECC-DIMM (implementing SECDED) provides almost no reliability benefits compared to an 8-chip non-ECC DIMM. We also show that if the error detection of On-Die ECC can be exposed to the memory controller, then Chipkill-level reliability can be achieved even with a 9-chip ECC-DIMM. To this end, we propose
eXposed On-Die Error Detection (XED)
, which exposes the On-Die error detection information without requiring changes to the memory standards or consuming bandwidth overheads. When the On-Die ECC detects an error, XED transmits a pre-defined
"catch-word"
instead of the corrected data value. On receiving the catch-word, the memory controller uses the parity stored in the 9-chip of the ECC-DIMM to correct the faulty chip (similar to RAID-3). Our studies show that XED provides Chipkill-level reliability (172x higher than SECDED), while incurring negligible overheads, with a 21% lower execution time than Chipkill. We also show that XED can enable Chipkill systems to provide Double-Chipkill level reliability while avoiding the associated storage, performance, and power overheads.
Production-run software failure diagnosis via

A

daptive

C

ommunication

T

racking
Authors: Alam Mohammad Mejbah ul , Muzahid Abdullah
Published: October 2016

Software failure diagnosis techniques work either by sampling some events at production-run time or by using some bug detection algorithms. Some of the techniques require the failure to be reproduced multiple times. The ones that do not require such, are not adaptive enough when the execution platform, environment or code changes. We propose ACT, a diagnosis technique for production-run failures, that uses the machine intelligence of neural hardware. ACT learns some invariants (e.g., data communication invariants) on-the-fly using the neural hardware and records any potential violation of them. Since ACT can learn invariants on-the-fly, it can adapt to any change in execution setting or code. Since it records only the potentially violated invariants, the postprocessing phase can pinpoint the root cause fairly accurately without requiring to observe the failure again. ACT works seamlessly for many sequential and concurrency bugs. The paper provides a detailed design and implementation of ACT in a typical multiprocessor system. It uses a three stage pipeline for partially configurable one hidden layer neural networks. We have evaluated ACT on a variety of programs from popular benchmarks as well as open source programs. ACT diagnoses failures caused by 16 bugs from these programs with accurate ranking. Compared to existing learning and sampling based approaches, ACT has better diagnostic ability. For the default configuration, ACT has an average execution overhead of 8.2%.
Decoupling loads for nano-instruction set computers
Authors: Huang Ziqiang , Hilton Andrew D. , Lee Benjamin C.
Published: October 2016

We propose an ISA extension that decouples the data access and register write operations in a load instruction. We describe system and hardware support for decoupled loads. Furthermore, we show how compilers can generate better static instruction schedules by hoisting a decoupled load's data access above may-alias stores and branches. We find that decoupled loads improve performance with geometric mean speedups of 8.4%.
Mellow writes
Authors: Zhang Lunkai , Neely Brian , Franklin Diana , Strukov Dmitri , Xie Yuan , Chong Frederic T.
Published: October 2016

Emerging resistive memory technologies, such as PCRAM and ReRAM, have been proposed as promising replacements for DRAM-based main memory, due to their better scalability, low standby power, and non-volatility. However, limited write endurance is a major drawback for such resistive memory technologies. Wear leveling (balancing the distribution of writes) and wear limiting (reducing the number of writes) have been proposed to mitigate this disadvantage, but both techniques only manage a fixed budget of writes to a memory system rather than
increase
the number available.

In this paper, we propose a new type of wear limiting technique,
Mellow Writes
, which reduces the wearout of individual writes rather than reducing the number of writes.
Mellow Writes
is based on the fact that slow writes performed with lower dissipated power can lead to longer endurance (and therefore longer lifetimes). For non-volatile memories, an
N
1
to
N
3
times endurance can be achieved if the write operation is slowed down by N times.

We present three microarchitectural mechanisms (
Bank-Aware Mellow Writes, Eager Mellow Writes, and Wear Quota
) that selectively perform slow writes to increase memory lifetime while minimizing performance impact. Assuming a factor
N
2
advantage in cell endurance for a factor
N
slower write, our best Mellow Writes mechanism can achieve 2.58× lifetime and 1.06× performance of the baseline system. In addition, its performance is almost the same as a system aggressively optimized for performance (at the expense of endurance). Finally, Wear Quota guarantees a minimal lifetime (e.g., 8 years) by forcing more slow writes in presence of heavy workloads. We also perform sensitivity analysis on the endurance advantage factor for slow writes, from
N
1
to
N
3
, and find that our technique is still useful for factors as low as
N
1
.
The anytime automaton
Authors: Miguel Joshua San , Jerger Natalie Enright
Published: October 2016

Approximate computing is an emerging paradigm enabling tradeoffs between accuracy and efficiency. However, a fundamental challenge persists: state-of-the-art techniques lack the ability to enforce runtime guarantees on accuracy. The convention is to 1) employ offline or online accuracy models, or 2) present experimental results that demonstrate empirically low error. Unfortunately, these approaches are still unable to guarantee acceptability of
all
application outputs at runtime. We offer a solution that revisits concepts from anytime algorithms. Originally explored for real-time decision problems, anytime algorithms have the property of producing results with increasing accuracy over time. We propose the Anytime Automaton, a new computation model that executes applications as a parallel pipeline of anytime approximations. An automaton produces approximate versions of the application output with increasing accuracy, guaranteeing that the final precise version is eventually reached. The automaton can be stopped whenever the output is deemed acceptable; otherwise, it is a simple matter of letting it run longer. We present an in-depth analysis of the model and demonstrate attractive runtime-accuracy profiles on various applications. Our anytime automaton is the first step towards systems where the acceptability of an application's output directly governs the amount of time and energy expended.
Accelerating markov random field inference using molecular optical gibbs sampling units
Authors: Wang Siyang , Zhang Xiangyu , Li Yuxuan , Bashizade Ramin , Yang Song , Dwyer Chris , Lebeck Alvin R.
Published: October 2016

The increasing use of probabilistic algorithms from statistics and machine learning for data analytics presents new challenges and opportunities for the design of computing systems. One important class of probabilistic machine learning algorithms is Markov Chain Monte Carlo (MCMC) sampling, which can be used on a wide variety of applications in Bayesian Inference. However, this probabilistic iterative algorithm can be inefficient in practice on today's processors, especially for problems with high dimensionality and complex structure. The source of inefficiency is generating samples from parameterized probability distributions.

This paper seeks to address this sampling inefficiency and presents a new approach to support probabilistic computing that leverages the native randomness of Resonance Energy Transfer (RET) networks to construct RET-based sampling units (RSU). Although RSUs can be designed for a variety of applications, we focus on the specific class of probabilistic problems described as Markov Random Field Inference. Our proposed RSU uses a RET network to implement a molecular-scale optical Gibbs sampling unit (RSU-G) that can be integrated into a processor / GPU as specialized functional units or organized as a discrete accelerator. We experimentally demonstrate the fundamental operation of an RSU using a macro-scale hardware prototype. Emulation-based evaluation of two computer vision applications for HD images reveal that an RSU augmented GPU provides speedups over a GPU of 3 and 16. Analytic evaluation shows a discrete accelerator that is limited by 336 GB/s DRAM produces speedups of 21 and 54 versus the GPU implementations.
LaPerm
Authors: Wang Jin , Rubin Norm , Sidelnik Albert , Yalamanchili Sudhakar
Published: October 2016

Recent developments in GPU execution models and architectures have introduced dynamic parallelism to facilitate the execution of irregular applications where control flow and memory behavior can be unstructured, time-varying, and hierarchical. The changes brought about by this extension to the traditional bulk synchronous parallel (BSP) model also creates new challenges in exploiting the current GPU memory hierarchy. One of the major challenges is that the reference locality that exists between the parent and child thread blocks (TBs) created during dynamic nested kernel and thread block launches cannot be fully leveraged using the current TB scheduling strategies. These strategies were designed for the current implementations of the BSP model but fall short when dynamic parallelism is introduced since they are oblivious to the hierarchical reference locality.

We propose
LaPerm
, a new locality-aware TB scheduler that exploits such parent-child locality, both spatial and temporal. LaPerm adopts three different scheduling decisions to i) prioritize the execution of the child TBs, ii) bind them to the stream multiprocessors (SMXs) occupied by their parents TBs, and iii) maintain workload balance across compute units. Experiments with a set of irregular CUDA applications executed on a cycle-level simulator employing dynamic parallelism demonstrate that LaPerm is able to achieve an average of 27% performance improvement over the baseline round-robin TB scheduler commonly used in modern GPUs.
ActivePointers
Authors: Shahar Sagi , Bergman Shai , Silberstein Mark
Published: October 2016

Modern discrete GPUs have been the processors of choice for accelerating compute-intensive applications, but using them in large-scale data processing is extremely challenging. Unfortunately, they do not provide important I/O abstractions long established in the CPU context, such as memory mapped files, which shield programmers from the complexity of buffer and I/O device management. However, implementing these abstractions on GPUs poses a problem: the limited GPU virtual memory system provides no address space management and page fault handling mechanisms to GPU developers, and does not allow modifications to memory mappings for running GPU programs.

We implement ActivePointers, a
software
address translation layer and paging system that introduces native support for page faults and virtual address space management to GPU programs, and enables the implementation of fully functional memory mapped files on commodity GPUs. Files mapped into GPU memory are accessed using
active pointers
, which behave like regular pointers but access the GPU page cache under the hood, and trigger page faults which are handled on the GPU. We design and evaluate a number of novel mechanisms, including a translation cache in hardware registers and translation aggregation for deadlock-free page fault handling of threads in a single warp.

We extensively evaluate ActivePointers on commodity NVIDIA GPUs using microbenchmarks, and also implement a complex image processing application that constructs a photo collage from a subset of 10 million images stored in a 40GB file. The GPU implementation maps the entire file into GPU memory and accesses it via active pointers. The use of active pointers adds only up to 1% to the application's runtime, while enabling speedups of up to 3.9× over a combined CPU+GPU implementation and 2.6× over a 12-core CPU-only implementation which uses AVX vector instructions.
All-inclusive ECC
Authors: Kim Jungrae , Sullivan Michael , Lym Sangkug , Erez Mattan
Published: October 2016

Increasing transfer rates and decreasing I/O voltage levels make signals more vulnerable to transmission errors. While the data in computer memory are well-protected by modern error checking and correcting (ECC) codes, the clock, control, command, and address (CCCA) signals are weakly protected or even unprotected such that transmission errors leave serious gaps in data-only protection. This paper presents All-Inclusive ECC (AIECC), a memory protection scheme that leverages and augments data ECC to also thoroughly protect CCCA signals. AIECC provides strong end-to-end protection of memory, detecting nearly 100% of CCCA errors and also preventing transmission errors from causing latent memory data corruption. AIECC provides these system-level benefits without requiring extra storage and transfer overheads and without degrading the effective level of data protection.
RelaxFault memory repair
Authors: Kim Dong Wan , Erez Mattan
Published: October 2016

Memory system reliability is a serious concern in many systems today, and is becoming more worrisome as technology scales and system size grows. Stronger fault tolerance capability is therefore desirable, but often comes at high cost. In this paper, we propose a low-cost, fault-aware, hardware-only resilience mechanism,
RelaxFault
, that repairs the vast majority of memory faults using a small amount of the LLC to remap faulty memory locations. RelaxFault requires less than 100KiB of LLC capacity, has near-zero impact on performance and power. By repairing faults, RelaxFault relaxes the requirement for high fault tolerance of other mechanisms, such as ECC. A better tradeoff between resilience and overhead is made by exploiting an understanding of memory system architecture and fault characteristics. We show that RelaxFault provides better repair capability than prior work of similar cost, improves memory reliability to a greater extent, and significantly reduces the number of maintenance events and memory module replacements. We also propose a more refined memory fault model than prior work and demonstrate its importance.