bluuebunny/crossref_metadata_2025 huggingface dataset:
Identifying teaching competencies for medical residents using a modified Delphi method
Authors: Hashimoto Tadayuki , Kikukawa Makoto
Published: February 2024

Purpose: This study aimed to identify the teaching competencies of medical residents.Methods: A modified Delphi study was conducted from January to March 2017. Twenty-four panelists (six medical educators, program directors, chief residents, and residents each) from various facilities in Japan participated in the study. The consensus criterion for this study was that more than 80% of the panelists gave a rating of 6 or higher on the 7-point Likert scale (“not at all important” to “extremely important”) without any comments. The modified Delphi approach resulted in a list of 27 resident teaching competencies after three rounds. These competencies were categorized based on Harden and Crosby’s 12 roles of medical teachers.Results: Our study revealed that, of the 12 roles, residents were primarily viewed as “clinical or practical teachers,” “teaching role models,” “on-the-job role models,” “learning facilitators,” and “student assessors.”Conclusion: The 27 resident teaching competencies indicate the importance of educational proximity for residents as teachers. It is expected that this finding will contribute to competency-based resident-as-teacher education.
Length-weight relationships of 15 mesopelagic shrimp species caught during exploratory surveys off the Canary Islands (central eastern Atlantic)
Authors: Guerra-Marrero Airam , Caballero-Méndez Catalina , Espino-Ruano Ana , Couce-Montero Lorena , Jiménez-Alvarado David , Castro José J.
Published: February 2024

Length-weight relationships (LWRs) were estimated for 15 mesopelagic shrimp species off the Canary Islands (central eastern Atlantic). Total length, cephalothorax length and total weight were taken for individuals collected during three research campaigns using a commercial semi-pelagic trawl net. The most represented families among the collected species were Sergestidae and Oplophoridae, with eight and three species, respectively. Overall, 60% of the species showed isometric growth, 33.3% negative allometry and 6.7% positive allometry. These 15 LWRs are the first contribution on mesopelagic shrimp species from the northwest Africa region, contributing to knowledge on the relative growth of these crustaceans.
Reinserção escolar na perspectiva de crianças e adolescentes com doenças crônicas
Authors: Leite Ana Carolina Andrade Biaggi , Sabatini Arielly Fernanda Bávaro , Alvarenga Willyane de Andrade , Neris Rhyquelle Rhibna , Nunes Michelle Darezzo Rodrigues , Lucca Milena de , Nascimento Lucila Castanheira
Published: February 2024

Objetivo: Analisar a experiência de crianças e adolescentes com doenças crônicas no processo de reinserção escolar. Método: Estudo qualitativo, de natureza descritiva-exploratória, conduzido em uma enfermaria pediátrica de um hospital público do interior paulista, com 15 crianças e adolescentes com doenças crônicas, que interromperam a frequência escolar por demandas associadas à terapêutica da doença. Entrevistas semiestruturadas foram conduzidas e os dados submetidos aos procedimentos da análise temática indutiva. O estudo seguiu todos os preceitos éticos (parecer nº. 2.911.290).Resultados: Com base nasanálises foram construídos quatro temas: (1) “Impacto social, acadêmico e emocional da hospitalização”; (2) “Rotina no hospital: estratégias para recuperar o rendimento escolar”; (3) “Desafios e alegrias consequentes ao retorno à escola”; e (4) “Redes de apoio à criança e ao adolescente com doença crônica no processo de reinserção escolar”. Conclusão: Crianças e adolescentes com doenças crônicas que vivenciam a reinserção escolar necessitam de apoio neste processo, principalmente para manutenção da conexão com a escola durante o afastamento e na fase de reinserção. Os resultados desta pesquisa podem auxiliar os profissionais de saúde no planejamento do cuidado, considerando as necessidades acadêmicas dessa população.
Optimizing the Gravity Data and Geological Observation for Mapping the Local Fault around the Jaboi Volcano
Authors: Yanis Muhammad , Nasrullah Zaini , Isa Muhammad , Riski Ananda , Zainal Muzakir , Paembonan Andri Yadi
Published: February 2024

Geothermal is a very expensive investment industry. Therefore, it is necessary to map a geological structure in the sub-surface, i.e., faults, and rock formations that control volcanic hydrothermal systems to reduce investment risk in the exploitation of geothermal. On the other hand, the hydrothermal system aims for flow paths connecting reservoir wells for fluid production. The Jaboi Volcano, with an estimated 80 MWe located on Weh Island, Indonesia, has been planned by the government to develop electrical energy, where the excess energy will be exported to Banda Aceh via undersea cables. We use global gravity model plus (GGM+) in a resolution of ~230m/px for mapping the geological structure of Jaboi volcano. Based on GGM+ data analysis, the Bouguer anomaly data shows low gravity values in volcanic areas, namely 46 – 69 mGal. These data only represent rock density values with low density in geothermal areas. We also calculate the residual anomaly from the Bouguer data using the high-pass-filtering technique, wherein the volcanic area, several high-gravity anomalies (1 – 1.4 mGal) correspond to the Leumomate fault in the direction of NW-SE. The same pattern is also obtained in the area with a suspected Ceunohot fault in the SW – NE direction. This research demonstrates the optimization of gravity satellite that free access to be used in mapping geological structures in geothermal Jaboi. Finally, we conclude that GGM+ data is a very efficient and cost-effective technique to detect geological structures around the Jaboi volcano, which developing countries can use as a preliminary study for evaluating and exploring geothermal energy
Designing Silicon Interposers for 2.5/3DIC Heterogeneous Integration - Meeting Foundry and OSAT Requirements
Authors: Cone Chris , Metcalfe Jamie
Published: February 2024

End market demand for higher performance, higher bandwidth and higher throughput processing such as AI, HPC, VR, 5G and even autonomous vehicles is driving the trend of heterogenous integration of ASICs, chiplets and memory, including HBM, onto advanced high-performance substrates using 2.5 and 3D IC assembly techniques that are manufactured using silicon or silicon-like processes.

There are multiple suppliers of such advanced high-performance substrates ranging from the one stop mega foundries to multiple OSATs of different sizes. It’s fair to say that all of them have common design requirements or constraints that must pass a rigorous verification process of the manufacturing mask files (GDSII or OASIS). Such GDSII or OASIS files are post processed or exported from the physical design tools making the need to create the mask files with 100% fidelity an additional challenge to the design team.

In this paper we will cover the major steps needed to design and implement an advanced silicon-based interposer that addresses common requirements of foundries and OSATs. We will talk about what each step is, why its required, any challenges that exist in addressing the step and actual design examples for each step. The major steps we will cover include:

• What information you need from your manufacturer? • Definition of connectivity floorplanning of the interposer • Defining the interposer materials stackup vias for routing • Breakout or fanout routing from chiplet or IC pads • Power and ground mesh creation • Routing of interposer connectivity • Generation of interposer manufacturing data (GDS/OASIS) • Verification of the design to meet foundry/OSATs rules • Handoff to foundry/OSAT

At the end of this paper attendees will understand what the major workflow steps for interposer design are and why. What general information they will need to obtain from their manufacturer in order to start design and how to use it. They will learn what each design step entails with clear examples which will enable creation of workflows to successfully handoff their designs to their chosen foundry or OSAT manufacturer.
EMI Shielding for System in Package Using Spray Coating and Silver Particle-Free Ink
Authors: Hannani Sima , Lemieux Melbs , McKerricher Garret
Published: February 2024

There is a constant drive to pack electronics into smaller spaces. Recently, IoT devices such as smart watches, wearables and other connectivity devices have been major drivers of further miniaturization and spurred System in Package ‘SIP’ innovations. SIP enables several integrated circuits (ICs) along with larger capacitors/inductors to be housed in one package. Many of these ICs operate at radio frequencies and the proximity increases electromagnetic interference (EMI). The traditional solution of soldering a ‘metal can’ is not feasible. On the other hand, 5G enabled devices and high frequency communication electronics require shielding well beyond RF, typically 5 ? 25 GHz and beyond. Compartmental and conformal shielding of the package is necessary and sputtered metal has typically been utilized to provide the shield.

The traditional sputtering method is a Physical Vapor Deposition process (PVD) that involves vaporizing a metal and depositing it onto the surfaces of the components. PVD is currently the most commonly used method to apply the EMI shield and it requires a complex, multi-step process. Alternatively, the technology is seeing a shift to sprayable or jettable conductive-based ink conformal shielding. This approach brings about substantial total cost of ownership and UPH/throughput advantages as the ink-based processes (spray/jet) does not require vacuum, and relatively low temperatures (at or below 180C in most cases). From a technology perspective, ink-based approaches have the advantage in shielding complex 3D, non line-of-sight packages and electronic module housings, directed (mask-less) shielding with no major drop in shielding performance or REL (reliability) behavior.
The Grinding and Polishing Technology for Various Materials
Authors: Pinto Bob , Clayfield Peter , Inoue Takeru
Published: February 2024

We (Okamoto Machine Tool Works, Ltd.) present our grinding and polishing technology for various materials such as resin, Cu, BG tape, SiC, GaN. Our technology is able to grind and polish various types of materials from soft materials to hard materials.

We have been developing a special grinding technology for soft materials. The technology is called HPD and enables to grind the soft materials which were not able to be ground with a standard grinding process or needed to be ground by rough grid size grinding wheels. You also had to make the grinding wheel wears a lot even the rough grid size grinding wheels are used in order to grind those soft materials due to the clogging. The HPD technology prevents this issue. Moreover, thanks to this technology, you can use high mesh wheels such as #4000 - #30,000. We believe that the HPD technology can be an effective technology for FOWLP, PLP, TSV grinding and BG tape grinding of flip-chip/high bumped wafers for flatness improvement.

Our technology is not only for soft materials but also for difficult cut materials such as SiC and GaN. We developed high power and high-rigidity grinder for these materials. We are going to look through the SiC grinding result with our technology.

Moreover, we have developed polishing technology for various types of materials including Si, SiC, GaN, InP, GaAs, and more.

Our grinding and polishing technology can cover various types of materials. It is hoped that our technology helps your current process issues.
Cost Analysis of Fan-out Processes for Chiplet Packaging
Authors: Lujan Amy
Published: February 2024

When building a design around chiplets, there are many factors to consider: industry standards, availability of chiplets within the supply chain, size requirements, and cost, to name a few. The cost of chiplet packaging is a particularly important factor that must be understood, because even if all design requirements can be met, the chiplet package will not come to fruition if the total cost is too high.

The basic tradeoff between a monolithic die and a series of chiplets is a reduction in silicon costs countered by an increase in packaging costs. This analysis will compare a monolithic die flip chip package to two fan-out processes that support chiplet packaging. In the first scenario, a two-chiplet chip-last fan-out on substrate package will be compared to a standard flip chip package. For the second comparison, a monolithic flip chip package will be compared to a four-chiplet fan-out package that utilizes embedded silicon for additional interconnect. For both scenarios, a detailed cost comparison will be provided.

Activity based cost modeling will be used for this analysis. In addition to looking at the direct costs of the substrate and assembly processes, yield considerations and the price of the incoming silicon (which varies by node) will be included. The goal of this analysis is to evaluate the cost of a monolithic flip chip package versus a chiplet scenario for two designs, and to highlight the cost drivers of the fan-out chiplet packaging processes.
Understanding Warpage Behavior on Different Handling Platforms of FOWLP
Authors: Sanchez Debbie Claire , Sutariya Ashish , Panchal Bhaumi , Song Wenxuan , Wagner Ronny , Marlakunta Sai
Published: February 2024

Warpage profile changes depending on platform or placement of wafer at different stages, which creates another variable when determining the best warpage reduction solution or structure alteration. In this paper, a method for obtaining information on deformity at different stages/platforms in the warpage tracking or reduction process will be presented.
iNEMI MAESTRO: Glass Substrates for mmWave/sub-THz Applications
Authors: Ballentine Paul , Nelson Shelby
Published: February 2024

This paper will explore the use of glass substrates for wireless components at frequencies ranging from 30 GHz - 240 GHz. Applications include both communications and radar/sensing. Examples of devices that can benefit from glass substrates include individual passive devices, filters, diplexers, and antenna arrays. We will discuss the properties of glass and how they translate into improved performance with lower power and size.
5G Electronics: Bridging the Measurement Challenges
Authors: Enright Lucas
Published: February 2024

iNEMI orchestrated an industrial round robin. 10 labs measuring identical samples with 4 different methods: split-cylinder resonators; split-post dielectric resonators; fabry perot open resonators; and balanced-type circular disk resonators. The results revealed a serious measurement problem: the semiconductor industry needs dielectric standards - a traceable standard to know which answer is “right”.
Performance Enablement Through VIPack FOPOP for Mobile and Networking
Authors: Gerber Mark , Lu Meiju , Lin Vincent , Chen Chienfan
Published: February 2024

Will address market drivers, mobile/network performance drivers and solutions, SiPh FOPOP, Electrical/Thermal modeling and test.
D2W Hybrid Bonding Using High Accuracy Carrier Solutions for 3D System Integration
Authors: Uhrmann Thomas , Burggraf Jürgen , Pires Mariana , Fan Chun Ho , Ng Hoi Ping , Li Ming
Published: February 2024

Die segmentation and chiplet integration is gaining considerable industry momentum and seen as one important integration process for 3D systems on chips. As interconnect pitches in 3D packaging become tighter with each new product generation, wafer and die bond alignment and overlay processes must also scale accordingly. 10µm pitch is setting a junction in interconnect technology. On the one hand, it is seen as the inflection point of hybrid bonding. At the same time, these extremely tight pitches enable functional partitioning of device functions onto different dies (chiplets) using die-to-wafer (D2W) hybrid bonding or wafer-to-wafer (W2W) hybrid bonding.

D2W hybrid bonding is evaluated in different integration processes. While direct placement of fusion bondable dies from a film frame is researched intensely, another option is to reconstitute dies on a carrier wafer and collectively transfer the dies using W2W bonding equipment. In the presentation we will elaborate on all aspects of the die to wafer bonding for a successful single chip type process towards a full system transfer approach. We will show alignment data of the dies on the transfer carrier targeting a pick and place accuracy of <500nm and report on the alignment evolution during the process until final annealing. Further elaboration will be done on different die sizes and die thicknesses. The die flatness and high variation over the whole wafer will be evaluated according to the die dimensions. Most importantly the die high variation and planarity will be shown for different carrier systems such as thermoset and thermoplastic materials, evaluating the bonding performance in terms of alignment propagation bond line integrity.
Optimizing New Power Switch Technology
Authors: Sadri Sam
Published: February 2024

Power switches are critical components in power conversion for a wide variety of applications, including DC-AC inverters for electric vehicles (EVs), solid state breakers, and energy storage devices. Improving the efficiency and performance of semiconductor power switch components can have wide benefits, improving the efficiency and accelerating deployment of these applications.

Compared to conventional power switches, such as insulated-gate bipolar transistors (IGBTs), the B-TRAN™ bidirectional power switch from Ideal Power offers significant improvements in efficiency, reducing power losses by 50% or more depending on the application. With its higher efficiency, B-TRAN results in less heat being generated and thus has significantly lower thermal management requirements. In addition, a single B-TRAN™ replaces multiple conventional power switches for bidirectional applications.

Beginning in mid-2020, Ideal Power teamed with QP Technologies, a leading provider of microelectronic packaging and assembly services, to package their B-TRAN switches in various TO packages (a wide range of small-pin-count packages often used for discrete parts such as transistors or diodes). The development work started with TO-247, then moved TO-264 packages, and finally transitioned to a custom direct-bond copper (DBC) solution.

To achieve a high-reliability design, QP Technologies and Ideal Power focused on developing die and packaging designs based on flip-chip technology in lieu of wirebonding to maximize the life cycle of the product. This paper investigates the challenges, solutions and finally the fabrication of the first double-sided B-TRAN device.
Glass Devices for Next-Generation Packaging and RF Signal Conditioning
Authors: Flemming Jeb H.
Published: February 2024

The push for higher communications frequencies, greater system integration, and smaller space imparts many unique challenges on RF and packaging engineers in the development of next generation cellular products for 5G, WiFi 6, Military, and other applications. Traditional materials, such as LTCC, organic laminates, and silicon face major limitations to dramatically improve system size, weight, and performance (SWAP).

Photosensitive Glass-Ceramics (PSG) have gained a lot of attention as a next generation RF and RF packaging substrate for their ability to simultaneously solve these two important challenges. In this paper the authors will present on our work using PSG for RF and RF packaging solutions. We will share (1) the advantages of using PSG for advanced RF packages, and (2) our work demonstrating glass as an RF substrate integrating discrete components and embedded die for passive RF filters, and (3) our work towards building vertically stacked glass packages for advanced RF systems-in-package (SiP).

The described work presents a manufacturing platform for the production of vertically stacked glass substrates with integrated high Quality Factor passive devices, such as inductors and capacitors, and heterogeneously integrated surface mount devices for advanced RF systems-in-package. The presented material demonstrates a production and assembly process for the manufacturing of advanced systems. In this paper, we present design, production, assembly considerations that impact size, weight, and performance (SWAP) metrics for a variety of product definitions and multiple simulation vs. product testing to demonstrate a reliable design to product flow.
Advanced Thermal Interface Materials: Assembly and Integration for System in Package
Authors: Brenner Kevin
Published: February 2024

Power dissipation is perhaps the greatest challenge facing modern electron devices. It has limited the performance of Si integrated circuits for nearly two decades, and is also limiting the performance of (high-power) GaN discrete devices. As such, many information technologies (ITs) have an urgent need for power dissipation solutions at the hardware level. The most feasible solution is via the device packaging, since self-heating of the device is deeply rooted in fundamental aspects of electron transport in imperfect semiconductors at normal temperatures. This packaging solution often occurs at the die attachment, whereby a thermal interface material (TIM) couples the device to the board. The interface/bulk thermal conductivity of this TIM determines the temperature rise of the device at a given operating power. Today, most TIMs rely on the thermal conductivity of metals, and are rapidly becoming a bottleneck for power dissipation in advanced ITs. This talk will discuss the limitations of metallic TIMs, and integration/characterization challenges for new materials that may extend the performance scaling of high-power devices.
Development of Electronic Packages with Integrated Environmental Mitigation
Authors: Rudd Carl , Bond Artie , English Brian , Hamlin Benoit , Adams Mark , Dean Robert
Published: February 2024

This paper demonstrates the techniques to integrate environmental protection into large format ceramic chip carriers using agile manufacturing techniques. Electronics packaging is critical for protecting integrated circuits and MEMS devices from austere environments. Typically, protecting packaged devices and circuit boards adds significant size to an assembly. Incorporating environmental mitigation strategies within the packages can reduce the total system size.

In this effort, we developed a multi-faceted strategy to vibration, thermal, RF, and radiation interference with packaged chip. This effort included development of a thermomechanical isolation platform and RF shielding designs compatible with agile manufacturing methods (e.g., additive manufacturing). Shielding design evaluated materials to block external RF or radiation damage. Thermal isolation and vibration stress control was demonstrated using a suspended interposer. Lastly, ceramic demonstrator packages were printed using stereolithography, and were shown to survive high heat environments via heating with a 2000°C torch. Collectively, these results show that it is possible to provide environmental protection to essential chip and sensors within the package itself, reducing the volume needed for integration into flight systems. Furthermore, EngeniusMicro and partners have done so in using methodologies that allow for their production on-demand, both domestically and at the point-of-need.
Incorporating Hierarchical Construction for Advanced IC Packaging
Authors: Cone Chris , Hudson Ed
Published: February 2024

Advancements in IC packaging manufacturing have given rise to the growing trend disaggregating large SoC into smaller die/chipets. This significantly raises the barrier for IC package designers with increasing design complexity and exploding pin counts. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production. In this paper, we present a new approach IC package floor-planning using hierarchical device modeling system assembly.

The key benefit of adopting hierarchy inside of a design is clear – a seemingly large and complex design can be disaggregated into smaller and easier to manage building blocks based on collection attributes such as function and position. In IC packaging there are two key classes of design structures which lend easily to disaggregation. These are die-to-die signal interfaces and power distribution networks. Die to die signal interfaces are implemented as uniform signal bump collections placed at least twice in the system but usually used several times to link several dies. Similarly, power distribution networks typically replicated in several regions of the system design and the bump assignment often assigned to meet a specific physical implementation such as checker-board bump pattern for a two-layer power ground mesh. These design structures can in turn be placed or arrayed in various combinations to create larger composite building blocks in the full design assembly.

Yet unlike in IC design, the key challenge with adopting hierarchical device modeling in IC packaging is that the top-level floorplan demands a unique signal connectivity definition regardless of the placement hierarchy. While there are brute force methods of doing this such as performing manual connectivity edits to add prefixes of suffices to the top-level signal, these are time consuming and error prone – particularly when design updates are required. To properly address the top-level connectivity, this paper introduces a novel method to assign connectivity based on topological pin regions defined over bump collections which can then be used to automatically define the top-level connectivity bump based on system attributes such as the parent instance and region names. Using topological pin regions in hierarchical construction allows design updates at the building block level to instantly propagate to the full design.

Package designers need to employ all tools available to address the significant device complexity and an explosion in pin count in today’s IC packaging designs. Through hierarchical device modeling construction with topological region-based connectivity, we highlight that large and seemingly complex designs are easily broken down into easily manageable building blocks.
CU Wirebond Technology in 16FFC High Performance Automotive Radar Processor with IR Drop Reduction Methodology
Authors: Tran Tu Anh , Lim Jasmine , Au YK , Song MJ , Benson Mollie
Published: February 2024

High performance automotive radar front-end processors normally use advanced semiconductor packaging such as Flip Chip, fan-in and fan-out wafer level Ball Grid Array (BGA) packages in order to provide superior performance in their applications. However, for a cost effective package in the competitive business market, wirebonded package can also provide similar uncompromised performance. Advanced Cu wirebond technology was evaluated on the 16FFc radar processor. However, the challenge of high voltage drop, also known as IR drop, in 16FFc technology has to be overcome. As wafer technology moves to smaller advanced nodes, the back-end-of-line (BEOL) metal thickness gets thinner, thus increasing the resistance per unit length. Another trend in semiconductor design has been a reduction in operating voltage, meaning that small changes in supply voltage may represent an increasing percentage of the digital swing and potentially lead to incorrect logic values. As current flows through a resistor, the high voltage drop could slow down the circuitry, impact the circuit timing and lead to functional failure. In order to reduce the IR drop in the radar processor when using Cu wirebond, a large quantity of intra-die wires was applied on the 16FFc silicon. IR drop simulation was performed on 3 layout conditions, 0%, 50% and 100% of the intra-die wires. Empirical data was also collected with actual Cu wirebonded samples. The fully populated intra-die wires reduced IR drop by 30%. To enable the reliable performance of the intra-die wires, Stand-off Stitch Bond (SSB) wirebond technology was introduced within the package. The development and reliability evaluation was conducted for Cu wirebonding on 16FFc automotive radar processor of 30mm2 die size in a 14mm x14mm 2-layer substrate BGA package. Wirebond recipe was developed based on detailed Design of Experiment to establish bonding parameters for both standard wires and the intra-die wires. Packages were tested per AEC Grade 1 and AEC Q006 qualifications requirements. All results from package reliability assessments passed with no abnormality. Board level temperature cycling reliability for the BGA package with the four depopulated corner solder balls was evaluated with results surpassing NXP requirement for AEC Grade 1. This paper will present the results and analysis from (1) IR drop simulation and empirical data collection, (2) wirebond development and reliability of standard and intra-die wires on 16FFc Silicon, and (3) board level reliability of a BGA package with four depopulated corner solder balls.
Establishing a Packaging Ecosystem for GlobalFoundries Leadership Silicon Photonics Wafers –2022 view
Authors: Berger Daniel
Published: February 2024

The continuous demand for faster and further data transfer with power efficiency drives innovation in the datacenter, as cloud computing, optical networks, and high-performance computing relies more and more on optics to support the bandwidth challenge. As the nanometer size transistors get closer to the physical limit, the data processing involved in the future applications needs to interface with optical interconnects. Silicon photonics enable light manipulation and processing inside the chips and is a key enabler for optics integrated system at high level of performance over a traditional CMOS-based technology. GLOBALFOUNDRIES has developed a CMOS/silicon photonics platform in an advanced 300mm fab that includes the monolithic integration of RF, digital elements, and silicon photonics features inside a single chip. Packaging features are a critical element of this offering, and this presentation will discuss the 2022 view of these advanced features and what it will take for establishing an ecosystem of packaging partners for customers to utilize these leading-edge features for their system needs.
Advanced Packaging Capabilities at Intel
Authors: Sotir John
Published: February 2024

Heterogeneous Integration (HI) is undeniably the vehicle to drive continued advances in Compute and Communications. Advanced Packaging Architectures today provide unprecedented levels of Heterogeneous Integration in Client, Server and Discrete Graphics.

Intel committed to a vision of developing heterogeneously integrated

leadership products using advanced packaging technologies to match the

functionality of a monolithic SOC and more…..

We continue to scale our Advanced Packaging Technologies Roadmap.

Federal Engagements in multiple programs (e.g. SHIP) allowing Intel to drive design and prototype diverse configurations for U.S. Government / and Defense Industrial Base; USG/DIB partnering critical for HI advancements.
Reshoring Advanced Packaging to Enable Modernization Activities
Authors: Smelker Tom
Published: February 2024

Globalization has migrated Advanced Packaging to the Pacific Rim for decades. Current geopolitics is driving instability in the region

and increasing the risk of access to leading edge microelectronics and packaging capabilities. This has created substantial risks to western

countries as they strategically modernize. At the same time, Advanced Packaging is more

critical in solutions as we transition to

Heterogeneous Integrated (HI) architectures enabling processing to move to the sensor.
Heterogeneous Integration of Chiplets, Lego-like IP for More than Moore
Authors: Felton Keith
Published: February 2024

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SOC device mounted and interconnected in a single packing using high speed/bandwidth interfaces that will then deliver monolithic or greater performance at a reduced cost, higher yield, and with only a slightly larger area as a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the fabless semiconductor industry to standardize on a set of interface protocols that will offer Lego-like plug and play compatibility between different suppliers chiplets creating a truly open ecosystem and supply chain.

When it comes to the physical heterogeneous integration of these chiplets it is typically achieved using a high-performance silicon-like interposer substrate. Such substrates typically require silicon-like design rules and design techniques along with their own specific analysis and verification requirements. The supply chain for these substrates does not change significantly, it is still typically the leading semiconductor foundries and OSATs however the level of interaction, requirements, and signoff approvals does change bringing often new demands and challenges. Is this a revolution or an evolution, it depends on your starting point? Does it need an entirely new set of workflows and design tools? Can we evolve in some stepwise linear process from where we are today with monolithic or traditional system-in-package type designs into this next-generation design environment? This paper will explore these new challenges and outline 5 key workflows that address and manage them. These 5 workflows span interlinked domain areas starting with architecture definition before progressing to design that incorporates planning, prototyping, and technology co-optimization of the chosen architecture as well as the detailed physical implementation of substrates before moving to multi-physics analysis, device-level test, and then manufacturing. This paper will then recommend workflow adoption focus areas that we have seen provide immediate heterogeneous integration capability benefits while providing a managed methodology adoption and migration process that minimizes disruption, risk, and of course cost that can bring heterogeneous integration based chiplet design within reach of the mainstream instead of only being accessible to the mega iDMs and fabless semi’s.
Direct Digital Manufacturing (DDM) Workflow for Printed Circuit Structures (PCS)
Authors: Newton C. Mike , Kulkarni Anand , Benoit Jason , Stoodt Kyle
Published: February 2024

Digitally based manufacturing has been around for years and has been the basis of turnkey lights out manufacturing processes and systems. Moving forward is the concept of Direct Digital Manufacturing (DDM) which brings together conceptualizing the electronic device, developing a digital twin of the product, and digitally merging workflow with the manufacturing process. This would further extend through to physical product. This paper will illustrate DDM is the basis of developing the capability of conceptualizing, designing, and digitally manufacturing electronic devices and more specifically printed circuit structures or PCS and printed circuit cylinders, PCC. Unlike tradition PCB’s or multichip module technology, the goal is fully printed electronic devices that can merge structure with electronic functionality. This paper will explore the current state of practice in manufacturing workflow and extend to the emerging factory in a Box concept of multi-material printing of next generation electronic controller and packaging technology. This will also include exploring design tools that provide the capability of co-design mechanical function with electronic function and modeling the manufacturing process and electronic device using digital twin concepts and workflow enabling smart manufacturing of printed electronic devices and precision of DDM technology.
Sustainment of Printed Hybrid Electronics: Reliability and Repairability Studies
Authors: Zhao Beihan , Riso Christopher , Leslie David , Dasgupta Abhijit , Das Siddhartha , Fleischer Jason , Hines Daniel
Published: February 2024

To understand the reliability and repairablityof electronics printed using the AJP process, through experimental and computational modeling, to take full advantage of this technology and realize its industrial potential. This work is sponsored by the members of the CALCE at the University of Maryland, College Park and Laboratory for Physical Science.
Dancing with literature: An overview of South African ballroom dancing
Authors: Green Alida
Published: February 2024

Hoewel baldanse deel maak van Suid-Afrika se ryk erfenis, is hierdie sosiale aktiwiteit se kulturele-en maatskaplike waarde tot dusvêr nie in diepte ondersoek nie. Hierdie artikel gee ‘n kort oorsig oor dansliteratuur wat tans in Suid-Afrika beskikbaar is; die stilisties aspekte en die teikenlesers van hierdie bronne word bespreek. Daar word ook kortliks na internasionale literatuur verwys aangesien dít die ontwikkeling van dans en plaaslike baldans, kontekstualiseer. Dancing with literature bespreek ook vlugtig die beperkinge wat deur vooropgestelde metodologieë op dansliteratuur geplaas word. Die leemtes in dansgeskiedenisbronne word uitgewys. Verder word die belangrikheid van dans as betroubare kultuurvorm, wat die gees van die samelewing reflekteer, bespreek.
“Your satisfaction, not mere profit is our aim”: A traditional English family enterprise and the textile industry – Arthur Bales and Son, from 1902
Authors: Maritz Leandie , Thorius Ingrid , Verhoef Grietjie
Published: February 2024

Die Britse setlaars van 1820 het ‘n setlaargemeenskap in die Oos-Kaap gevestig. Hierdie Engelse gemeenskap het onder andere ingesluit werklose Britse burgers, wat hulle hoop geplaas het op ‘n nuwe lewe in die Kaapkolonie. Onder die setlaars was daar vaklui, gewone nywerheidswerkers en boere. Uit ‘n netwerk van Britse entrepreneurs het die Bales familie hulle gevestig as handelaars. Die Bales- familie het ‘n algemene handelaarsonderneming gevestig en later uitgebrei om tekstiel en klerasie te verkoop. Na die Tweede Vryheidsoorlog het die Bales familiebesigheid verskuif na die Transvaalkolonie. Daar is ‘n materiaal- en klerasiebesigheid gevestig wat nog vir drie geslagte ‘n stewige vastrapplek in Johannesburg en omgewing sou verwerf. Hierdie artikel verwys na die mededinging in die tekstielhandel en die opkoms van die modebedryf in Johannesburg as die omgewing waarin die Bales familie hulle familiebesigheid gevestig het. Die sosiale kapitaalnetwerk van die Engelse kleinsakelui het die onderneming gehelp om in die mededingende klere- en modebedryf van Johannesburg ‘n gewaardeerde handelsnaam in tekstielhandel te vestig.
Healing the Herds: Disease, Livestock Economies and the Globalization of Veterinary Medicine
Authors: Van der Watt Lize-Marié
Published: February 2024

No abstract available.
Changing profile: The public face of the University of Pretoria over a century, 1908 - 2008
Authors: Van der Merwe Ria
Published: February 2024

In die tydperk na die eerste demokratiese verkiesing in 1994, het die meeste tersiêre opvoedkundige instellings in Suid-Afrika, insluitend die vorige sogenaamde “apartheid” universiteite, weens verskeie redes gepoog om hulle as demokraties en inklusief te bemark. Om ‘n instelling op so ‘n wyse te bemark dat dit blyk om aan die heersende politieke of sosiale norme te konformeer, is nie ‘n nuwe tendens in tersiêre opvoeding nie. Tersiêre opvoedkundige instellings in Suid-Afrika het sedert hulle totstandkoming verskeie vorme van media, insluitend koerantartikels, advertensies, publikasies, film en TV gebruik om hulle openbare beeld te bevorder. Die wyse waarop die Universiteit van Pretoria en sy voorganger, die Transvaal Universiteitskollege, bemarking gebruik het en hoe die invalshoek daarvan gewysig is na gelang die politieke en sosiale omstandighede in Suid-Afrika verander het, word as voorbeeld gebruik om hierdie stelling te illustreer.
Choosing the Right Angiotensin Converting Enzyme Inhibitors; Gender –Specific Approach
Authors: Varghese Neena Elsa , Jegaveerapandi K. , Yerrakula Goutham
Published: February 2024

This review article explores the importance of a masculinity- and feminine-specific approach in choosing the appropriate angiotensin-converting enzyme (ACE) inhibitors for patients with cardiovascular diseases. This review highlights the historical underrepresentation of women in clinical trials for cardiovascular medications, leading to a knowledge gap regarding the effectiveness and safety of these drugs in female patients. The article discusses the potential differences in treatment outcomes between men and women when it comes to ACE inhibitors and the gender-specific factors that can impact drug responses. The integration of bigender-specific data into clinical guidelines and decision-making processes can contribute to a more equitable and evidence-based approach to cardiovascular care. The article also references a report by the American College of Obstetricians and Gynecologists Force on Hypertension in Pregnancy, which emphasizes the importance of managing hypertension in pregnant women. By embracing a personalized medicine framework that accounts for gender-related differences, health-care professionals can optimize therapeutic interventions, minimize treatment disparities, and strive for improved cardiovascular health outcomes for all individuals. Overall, this review article provides insights into the potential mechanisms underlying sexuality-related differences in ACE inhibitor efficacy, safety, and adverse effects and discusses the implications of these findings in advancing personalized cardiovascular medicine.
Genetic diversity of the S-type small subunit ribosomal RNA gene of Plasmodium knowlesi isolates from Sabah, Malaysian Borneo and Peninsular Malaysia
Authors: Chong Eric Tzyy Jiann , Neoh Joveen Wan Fen , Lau Tiek Ying , Chua Kek Heng , Lim Yvonne Ai-Lian , Lee Ping-Chin
Published: February 2024

Objective:

To determine the genetic diversity of Plasmodium (P.) knowlesi isolates from Sabah, Malaysian Borneo and Peninsular Malaysia, targeting the S-type SSU rRNA gene and including aspects of natural selection and haplotype.

Methods:

Thirty-nine blood samples infected with P. knowlesi were collected in Sabah, Malaysian Borneo and Peninsular Malaysia. The S-type SSU rRNA gene was amplified using polymerase chain reaction, cloned into a vector, and sequenced. The natural selection and haplotype of the S-type SSU rRNA gene sequences were determined using DnaSP v6 and illustrated using NETWORK v10. This study's 39 S-type SSU rRNA sequences and eight sequences from the Genbank database were subjected to phylogenetic analysis using MEGA 11.

Results:

Overall, the phylogenetic analysis showed no evidence of a geographical cluster of P. knowlesi isolates from different areas in Malaysia based on the S-type SSU rRNA gene sequences. The S-type SSU rRNA gene sequences were relatively conserved and with a purifying effect. Haplotype sharing of the S-type SSU rRNA gene was observed between the P. knowlesi isolates in Sabah, Malaysian Borneo, but not between Sabah, Malaysian Borneo and Peninsular Malaysia.

Conclusions:

This study suggests that the S-type SSU rRNA gene of P. knowlesi isolates in Sabah, Malaysian Borneo, and Peninsular Malaysia has fewer polymorphic sites, representing the conservation of the gene. These features make the S-type SSU rRNA gene suitable for comparative studies, such as determining the evolutionary relationships and common ancestry among P. knowlesi species.
Liposomal dual delivery systems in visceral leishmaniasis enhance the synergistic effects of combination therapy: A promise for the future
Authors: Hazra Raghunath , Kar Amrita , Mahapatra Santanu Kar
Published: February 2024

Visceral leishmaniasis (VL) is a neglected tropical disease, and this review has summarized the current treatment scenario and its prospects. It also highlights alternative approaches used by research groups in India and around the world to develop cutting-edge and potent anti-leishmanial treatments. Even though numerous medications could be utilized to treat VL, the limitations of current treatments including their toxicity, cost, route of administration, and duration of doses, have contributed to the emergence of resistance. Combination therapy might be a better option due to its shorter duration, easier route of administration, and ability to extend the lifespan of individual drugs. However, there is a risk of not delivering both the drugs to the target site together, which can be overcome by the liposomal entrapment of those drugs and at a time knock an opportunity to reduce the dosage of amphotericin B if the combination drug provides a synergistic effect with it. Therefore, this review presents a novel strategy to fight against VL by introducing dual drug-loaded liposomes.
The Role of Central Oxytocin in Autonomic Regulation
Authors: Tsai Sheng-Feng , Kuo Yu-Min
Published: February 2024

Oxytocin (OXT), a neuropeptide originating from the hypothalamus and traditionally associated with peripheral functions in parturition and lactation, has emerged as a pivotal player in the central regulation of the autonomic nervous system (ANS). This comprehensive ANS, comprising sympathetic, parasympathetic, and enteric components, intricately combines sympathetic and parasympathetic influences to provide unified control. The central oversight of sympathetic and parasympathetic outputs involves a network of interconnected regions spanning the neuroaxis, playing a pivotal role in the real-time regulation of visceral function, homeostasis, and adaptation to challenges. This review unveils the significant involvement of the central OXT system in modulating autonomic functions, shedding light on diverse subpopulations of OXT neurons within the paraventricular nucleus of the hypothalamus and their intricate projections. The narrative progresses from the basics of central ANS regulation to a detailed discussion of the central controls of sympathetic and parasympathetic outflows. The subsequent segment focuses specifically on the central OXT system, providing a foundation for exploring the central role of OXT in ANS regulation. This review synthesizes current knowledge, paving the way for future research endeavors to unravel the full scope of autonomic control and understand multifaceted impact of OXT on physiological outcomes.