bluuebunny/crossref_metadata_2025 huggingface dataset:
SiC JFETs for Power Module Applications
Authors: Hilsenbeck Jochen , Xi Zhang , Domes Daniel , Rüschenschmidt Kathrin , Treu Michael , Rupp Roland
Published: May 2010

Starting with the production of Infineon´s first silicon carbide (SiC) Schottky diodes in 2001, a lot of progress was achieved during recent years. Currently, a 3rd generation of MPS (merged pn Schottky) diodes is commercially available combining tremendous improvements with respect to surge current capability and reduced thermal resistance. In this work we present the implementation of SiC switches in power modules and a comparison of these units with the corresponding Si-based power modules. Also the frequency dependence of the total losses of the 1200V configurations using Si-IGBTs or SiC-JFETs as active device is shown, indicating that modules solution with a state of the art SiC JFET outperforms all other options for switching frequencies of 20 kHz and beyond. Additionally a total loss vs. frequency study will be presented. Furthermore, it is show that the switching losses of JFET based modules can be further reduced by reducing the internal distributed gate resistivity.
Quality Control and Electrical Properties of Thin Amorphous (SiC)1-x(AlN)x Films Produced by Radio Frequency Dual Magnetron Sputtering
Authors: Gálvez de la Puente G. , Erlenbach Oliver , Guerra Jorge Andres , Hupfer T. , Steidl M. , De Zela Francisco , Weingärtner Roland , Winnacker Albrecht
Published: May 2010

Amorphous pseudobinary (SiC)1 x(AlN)x thin films have been produced by radio frequency dual magnetron sputtering from bulk SiC and AlN targets. For each target the emission characteristic, i.e. the spatial variation of the deposition rate was determined, in order to predict thickness distribution and spatial composition variation for the (SiC) (AlN) alloy. Impedance spectroscopy shows a high resistivity of the films in the SiC rich region, decreasing significantly towards the AlN rich region.
Calculations of the Spontaneous Polarizations and Dielectric Constants for AlN, GaN, InN, and SiC
Authors: Davydov Sergey Y. , Lebedev Alexander A.
Published: May 2010

Within the scope of the Harrison’s bond orbital model the spontaneous polarization, high- and low frequency dielectric constants are obtained in an analytical form. Theoretical results are in a reasonable agreement with the experimental data available and the numerical calculations based on the ab initio methods.
Energy Optimization of As+ Ion Implantation on SiO2 Passivation Layer of AlGaN/GaN HEMTs
Authors: Lim Ji Yong , Choi Young Hwan , Kim Young Shil , Kim Min Ki , Han Min Koo
Published: May 2010

We have fabricated SiO2 passivated AlGaN/GaN HEMTs and employed As+ ion implantation on the passivation layer and optimized the implantation energy. After As+ ion implantation with 120 keV energy and 1 × 1014 /cm2 dose, the maximum drain current, maximum transconductance and the breakdown voltage increased to 419.6 mA/mm, 87.9 mS/mm and 698 V while those of the conventional device was 317.0 mA/mm, 65.1 mS/mm and 639 V, respectively.
Field Effect Transistors Based on Catalyst-Free Grown 3C-SiC Nanowires
Authors: Rogdakis Konstantinos , Bano Edwige , Montes Laurent , Bechelany M. , Cornu David , Zekentes Konstantinos
Published: May 2010

Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowires (NWs) were fabricated and electrical characterization is presented. Silvaco simulation was used to fit the I-V characteristics and to extract information about the carrier (electrons) concentration and the oxide/NW interface quality. The high trap density and fixed charges at the nanowire/oxide interface, Dit~5x1011 cm-2eV-1 and Qf ~3x1013cm-2, and the high electron concentration (~3x1019 cm-3) originating from unintentional doping severely affect the electrical conduction through the nanowires which has as a result low values of mobility and transconductance, 0.11 cm2/Vs and 7x10-10 A/V, respectively.
Silicon-on-SiC, a Novel Semiconductor Structure for Power Devices
Authors: Jennings Michael R. , Pérez-Tomás Amador , Guy Owen James , Lodzinski Michal , Gammon Peter Michael , Burrows Susan E. , Covington James A. , Mawby Philip  Andrew
Published: May 2010

A physical and electrical analysis of Si/SiC heterojunctions formed by layer transfer based on the smartcut® process is presented in this paper. AFM and SEM have revealed a high bonding quality when Si wafers are transferred to SiC on-axis wafers. XRD points to the fact that the layers are monocrystalline in nature. A surface AFM analysis of the bonded wafers demonstrated a smooth surface (rms = 5.8 nm) suitable for semiconductor device fabrication. Capacitors have been fabricated from the Si/SiC heterojunctions, which have been totally oxidised. Oxidised Si/SiC structures yielded a lower density of interface states than conventional thermal oxidation techniques.
Characterization of Vanadium Doped 4H- and 6H-SiC Grown by PVT Method Using the Open Seed Backside
Authors: Racka Katarzyna , Tymicki Emil , Grasza Krzysztof , Raczkiewicz Marcin , Jakieła Rafał , Kozubal Michal , Jurkiewicz-Wegner Elzbieta , Brzozowski Andrzej , Diduszko Ryszard , Piersa Miroslaw , Kościewicz Kinga , Pawłowski Mariusz , Krupka Jerzy
Published: May 2010

Results of vanadium doping in PVT SiC bulk growth by the use of the seeding technique with an open seed backside are shown. Structural and electrical properties of 4H and 6H-SiC:V were investigated by a variety of experimental methods. In the crystal studied, the solubility limit of V in SiC was exceeded and structural defects consisting of V-rich precipitates occured. Electrical properties of this crystal were determined by the V3+/V4+ acceptor level. The V3+ charge state of vanadium was formed by compensating shallow donors (mainly nitrogen) and for both 4H and 6H polytypes it was detectable in optical absorption (in the near-IR range) and electron paramagnetic resonance.
Barrier Inhomogeneities of Mo Schottky Barrier Diodes on 4H-SiC
Authors: Naretto Marco , Perrone Denis , Ferrero Sergio , Scaltrito Luciano
Published: May 2010

In this work we present the results of electrical characterization of 4H-SiC power Schottky diodes with a Mo metal barrier for high power applications. A comparison between different Schottky Barrier Height (SBH) evaluation methods (capacitance-voltage and current-voltage measurements), together with the comparison with other authors’ works, indicates that thermionic current theory is the dominant transport mechanism across the barrier from room temperature (RT) to 450K, while at T < 300K some anomalies in J-V curves appear and SBH and ideality factor significantly change their values. These deviations from ideality are attributed to Schottky barrier inhomogeneities. In particular, a model based on two SBHs seems appropriate to properly describe the electrical behavior of our devices.
Status of 3" 6H SiC Bulk Crystal Growth
Authors: Makarov Yuri , Litvin D.P. , Vasiliev A.V. , Segal A.S. , Nagalyuk S.S. , Helava Heikki , Voronova M.I. , Scherbachov K.D.
Published: May 2010

In this paper, we report on the current status of our technology for the commercial production of 3” 6H-SiC substrates, including PVT growth [1] of more than 3” diameter and up to 20 mm long 6H-SiC boules, post-growth processing of the boules, and characterization of the produced wafers. We discuss the preparation of SiC sources and seeds, the initial transient stage of the growth, the distribution of temperature in the growth crucible, and the Si/C ratio in the vapor. Special attention is given to the rise of the process stability and the reduction of crystallographic defects, including micropipes (open core screw dislocations), low-angle grain boundaries, foreign polytype inclusions, and graphite inclusions [2,3].
On the Luminescence and Driving Force of Stacking Faults in 4H-SiC
Authors: Caldwell Joshua D. , Giles A.J. , Stahlbush Robert E. , Ancona M.G. , Glembocki Orest J. , Hobart Karl D. , Hull Brett A. , Liu Kendrick X.
Published: May 2010

Since it was determined that the formation and expansion of intrinsic stacking faults (SFs) induced a drift in the forward voltage (Vf) in 4H-SiC bipolar devices, significant effort has been made to understand the driving force causing SF motion as well as the various associated luminescence processes. The observation that annealing of faulted SiC devices and epilayers induced SF contraction and a recovery of the Vf drift enabled the studying of the impact of various parameters such as temperature, injection level and operation time upon SF motion, the Vf drift and luminescence within the same device. However, these observations in many cases contradicted the previously reported driving force models. Here we report on a basic driving force model explaining SF expansion in hexagonal SiC as well as discuss the observation of green luminescence from C-core partial dislocations bounding the SFs that may indicate an enhanced mobility of point defects within forward biased SiC pin diodes.
Nucleation of c-Axis Screw Dislocations at Substrate Surface Damage during 4H-Silicon Carbide Homo-Epitaxy
Authors: Dudley Michael , Zhang Ning , Zhang Yu , Raghothamachar Balaji , Sanchez Edward
Published: May 2010

Observations of dislocation nucleation occurring at substrate surface scratches during 4H-SiC CVD homoepitaxial growth are reported. Sub-surface residual damage associated with the scratches is observed to act as nucleation sites for basal plane dislocations (BPDs), threading edge dislocations (TEDs) and threading screw dislocations (TSDs) in the epilayer. TEDs and BPDs replicate from the surface intersections of basal plane dislocation half-loops injected into the substrate surface. A model for the nucleation mechanism of TSDs, which nucleate in opposite sign pairs, is presented which involves overgrowth of surface indentations associated with the scratch during step flow growth. Atomic steps which approach these local surface indentations can collapse creating pairs of opposite sign screw dislocations which have Burgers vector magnitude equal to the magnitude of the step disregistry created during the collapse.
High Quality 100mm 4H-SiC Substrates with Low Resistivity
Authors: Straubinger Thomas L. , Schmitt Erwin , Storm S. , Vogel Michael , Weber Arnd Dietrich , Wohlfart Andreas
Published: May 2010

One of the most crucial defects for the device fabrication on silicon carbide (SiC) substrates are areas with low crystalline quality and micro-pipe clusters which can still occupy several percent of the area in commercial available 4H-substrates. These defects originate from the seed or are generated by modification changes during growth and can be easily detected under crossed polarizers. In this presentation the historic development at SiCrystal from Acheson material to wafers with 100mm diameter, state of the art micro-pipe density and excellent crystalline quality (FWHM < 20 arcsec) on whole area will be shown. Additionally the influence of carbon inclusions on surface quality and the present dislocation densities in 4H substrates will be discussed. While carbon inclusions were reduced to uncritical levels dislocation densities are still in the range of 104 cm-2. Therefore strategies for further reduction will be pointed out. Finally a resistivity limit (16 mΩcm) for stacking fault formation during annealing at 1150°C will be defined.
Solution Growth and Crystallinity Characterization of Bulk 6H-SiC
Authors: Yashiro Nobuyoshi , Kusunoki Kazuhiko , Kamei Kazuhito , Yauchi Akihiro
Published: May 2010

The stable long time growth with the use of Si -C-Ti ternary solution was realized　by improving the thermal condition during the growth. We have succeeded in obtaining a maximum 10 mm thick bulk 6H-SiC crystal, which is the largest bulk crystal ever obtained by the solution growth technique. The obtained crystal was free of cracks and exhibited a homogeneous light green color. The crystallinity of the grown crystal was characterized by X-ray rocking curve measurements using (0006) reflection and by the molten KOH etching. The mapping of the full width at half maximum (FWHM) revealed the average FWHM around 30 arc seconds and the minimal FWHM under 16 arc seconds. The etch pit density (EPD) was typically in the range between 104 and 105 cm-2, which was comparable to that of the crystal seed.
Non-Polar SiC Crystal Growth with m-Plane(1-100) and a-Plane(11-20) by PVT Method
Authors: Yeo Im Gyu , Lee Tae Woo , Lee Won Jae , Shin Byoung Chul , Kim Il Soo , Choi Jung Woo , Ku Kap Ryeol , Kim Young Hee , Nishino Shigehiro
Published: May 2010

The present research was focused to produce 2 inch wafers from small rectangular seeds and to investigate the quality of non-polar SiC substrates grown by a conventional PVT method. The non-polar SiC seeds were prepared by cutting along <0001> direction of 6H-SiC crystal grown on (0001) basal plane. As SiC ingot grows, many defects in connected region were gradually diminished. While the full width at half maximum (FWHM) values of m-plane SiC substrate measured along a-direction and c-direction were 60 arcsec and 70 arcsec, respectively, and the FWHM values of a-plane SiC substrate measured along m-direction and c-direction were 27 arcsec and 31 arcsec respectively. The stacking faults lying in the basal plane can be detected by molten KOH etching as linear etch pits extending along <0001> on the (11-20) surface and the carrier concentration was observed by Raman spectrum.
Macrodefects in Cubic Silicon Carbide Crystals
Authors: Jokubavicius Valdas , Palisaitis Justinas , Vasiliauskas Remigijus , Yakimova Rositza , Syväjärvi Mikael
Published: May 2010

Different sublimation growth conditions of 3C-SiC approaching a bulk process have been investigated with the focus on appearance of macrodefects. The growth rate of 3C-SiC crystals grown on 6H-SiC varied from 380 to 460 μm/h with the thickness of the crystals from 190 to 230 μm, respectively. The formation of macrodefects with void character was revealed at the early stage of 3C-SiC crystal growth. The highest concentration of macrodefects appears in the vicinity of the domain in samples grown under high temperature gradient and fastest temperature ramp up. The formation of macrodefects was related to carbon deficiency which appear due to high Si/C ratio which is used to enable formation of the 3C-SiC polytype.
TEM and SEM-CL Studies of SiC Nanowires
Authors: Rossi Francesca , Fabbri Filippo , Attolini Giovanni , Bosi Matteo , Watts Bernard Enrico , Salviati Giancarlo
Published: May 2010

-SiC and -SiC/SiO2 core-shell nanowires (NWs) grown on silicon substrates by three different processes, based on the use of i) carbon monoxide, ii) silane with propane and iii) carbon tetrachloride precursors, are analysed by structural and optical techniques. Spectroscopic cathodoluminescence studies show a luminescence enhancement in core-shell structures, ascribed to an effective role of the shell as both carrier injecting barrier and passivation layer. In NWs grown using CCl4 precursor, a peculiar luminescence with dominant red component at about 2 eV has been detected and ascribed to point defects related to an unintentional oxygen incorporation.
Deep Levels Observed in High-Purity Semi-Insulating 4H-SiC
Authors: Alfieri Giovanni , Kimoto Tsunenobu , Pensl Gerhard
Published: May 2010

We report on the electrical characterization of high-purity semi-insulating 4H-SiC after annealing at temperatures between room temperature and 1700 oC by current-mode deep level transient spectroscopy (I-DLTS). I-V and Hall-effect measurements revealed that the investigated substrates possess p-type conductivity. Four deep levels were detected by I-DLTS with activation energies in the 0.15-1.29 eV range. We studied their thermal stability as well as their stability with respect to light illumination.
Thermal Activation and Cathodoluminescence Measurements of Tb3+-Doped a-(SiC)1-x(AlN)x Thin Films
Authors: Erlenbach Oliver , Gálvez Gonzalo , Guerra Jorge Andres , De Zela Francisco , Weingärtner Roland , Winnacker Albrecht
Published: May 2010

We produce amorphous terbium doped wide bandgap semiconductor thin films of the pseudobinary compound (SiC)1 x(AlN)x by rf triple magnetron sputtering. Cathodoluminescence measurements performed at samples having different compositions x show pronounced intra 4f shell transition peaks of the trivalent terbium. Thermal activation of the terbium emission by isochronal annealing of the films leads to a strong increase in emission intensity.
Preannealing Effect on Mobility of N-/Al-Coimplanted and Over-Oxidized 4H-SiC MOSFETs
Authors: Nanen Yuichiro , Zippelius Bernd , Beljakowa Svetlana , Trapaidze Lia , Krieger M. , Kimoto Tsunenobu , Pensl Gerhard
Published: May 2010

The authors investigated the effect of preannealing on N-/Al-coimplanted and over-oxidized Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). The preannealing process causes a decrease of the Hall mobility and the effective mobility, and an increase of the interface state density. Secondary ion mass spectroscopy (SIMS) measurements revealed that the N concentration at the SiO2/SiC interface in preannealed samples is lower than in not-preannealed samples, which might be the reason for in the increase of the interface state density. In MOSFETs without preannealing, more N atoms are piled up at the SiO2/SiC interface, leading to the lower interface state density and higher mobility.
Effect of NO Annealing on 6H- and 4H-SiC MOS Interface States
Authors: Basile Alberto F. , Rozen John , Chen X.D. , Dhar Sarit , Williams John R. , Feldman Leonard C. , Mooney Patricia M.
Published: May 2010

The electrical properties of the SiC/SiO2 interface resulting from oxidation of the n-type 6H-SiC polytype were studied by hi-lo CV, temperature dependent CV and constant capacitance deep level transient spectroscopy (CCDLTS) techniques. Several trap species differing in energy and capture cross section were identified. A trap distribution at 0.5 eV below the 6H-SiC conduction band energy and a shallower density of states in both the 6H and 4H polytyes are passivated by post-oxidation NO annealing. However, other ultra-shallow and deeper defect distributions remain after nitridation. The latter may originate from semiconductor traps.
Growth Rate and Thickness Uniformity of Epitaxial Graphene
Authors: Strupiński Wlodek , Drabińska Aneta , Bożek Rafał , Borysiuk Jolanta , Wysmolek Andrzej , Stepniewski Roman , Kościewicz Kinga , Caban Piotr , Korona K. , Grodecki K. , Geslin Pierre Antoine , Baranowski Jacek M.
Published: May 2010

The paper provides a deeper understanding of key-parameters of epitaxial graphene growth techniques on SiC. At 16000C, the graphene layer is continuous and covers a large area of the substrate. Significant differences in the growth rate could be observed for different reactor pressures and the polarity of SiC substrates as well as for the substrate miscut and surface quality. In addition, graphene thickness uniformity and mechanism of ridges creation was examined.
Graphene Growth on C and Si-Face of 4H-SiC – TEM and AFM Studies
Authors: Borysiuk Jolanta , Bożek Rafał , Strupiński Wlodek , Baranowski Jacek M.
Published: May 2010

Transmission Electron Microscopy (TEM) investigations of graphene layers synthesized on Si and C-terminated on-axis oriented 4H-SiC are presented. The high-resolution TEM (HRTEM) revealed distinctive distance differences between the first carbon graphene layer and SiC surface for both polarities. The prolonged annealing of SiC with carbon face shows, that in addition to the increase of number of graphene layers, there is also observed splitting between stack of graphene layers and the surface of SiC substrate. In addition, the density of so called “puckers” increases.
Differences between Graphene Grown on Si-Face and C-Face
Authors: Camara Nicolas , Caboni Alessandra , Huntzinger Jean Roch , Tiberj Antoine , Mestres Narcis , Godignon Philippe , Camassel Jean
Published: May 2010

Epitaxial graphene growth is significantly different depending on the polarity of the 6H-SiC surface: Si- or C-face. On the Si-face, a uniform coverage of few layers on the whole sample can be obtained, but with electrical properties disturbed by the presence of a Carbon-rich buffer layer at the interface. On the contrary, on the C-face, we demonstrated that almost free-standing very large monolayers of graphene can be obtained by covering the sample with a graphitic cap during the growth.
Epitaxial Graphene Elaborated on 3C-SiC(111)/Si Epilayers
Authors: Ouerghi Abdelkarim , Portail Marc , Kahouli A. , Travers L. , Chassagne Thierry , Zielinski Marcin
Published: May 2010

This article explores the formation of graphene layers on 3C-SiC(111) epilayers grown on silicon substrates using thermal annealing under Ultra High Vaccum (UHV) environment. The formation of graphene is demonstrated by use of near field microscopy (STM and AFM) and X-ray Photoelectron Spectroscopy (XPS). The evolution of the surface stoichiometry of the 3C-SiC(111) pseudo substrates during the graphitization process is similar to that of the commonly used Si terminated -SiC bulk substrates, starting from a Si rich to the C rich surface characterized by a diffraction pattern. Graphitization process leads to a strong modification of the surface at a microscopic scale which is compared to that reported in case of 6H-SiC substrates. XPS spectra reveal the presence of typical C-C bonds related to a graphitic arrangement. Its high level of ordering is attested by the observation both of (66)SiC and (11)graphene surface reconstructions by STM. These results demonstrate the formation of graphene on 3C-SiC(111)/Si pseudo substrates. They open perspectives for developing novel C/SiC/Si heterostructures and put light on the ability of 3C-SiC/Si templates to become a low cost alternative of onerous -SiC substrates.
Growth of Few Layers Graphene on Silicon Carbide from Nickel Silicide Supersaturated with Carbon
Authors: Vassilevski Konstantin , Nikitina Irina P. , Horsfall Alton B. , Wright Nicolas G. , Johnson C. Mark
Published: May 2010

Few Layers Graphene (FLG) films were grown on the carbon-terminated surface of 4H-SiC from nickel silicide supersaturated with carbon. The process was realised by annealing of thin Ni films deposited on silicon carbide followed by wet processing to remove the nickel silicide. To identify and characterize the fabricated FLG films, micro-Raman scattering spectroscopy, AFM and optical microscopy have been used. The films grown on samples with initially deposited nickel thinner than 20 nm show clear graphene footprints in micro-Raman scattering spectra, namely a single component, Lorentzian shape 2D band with FWHM remarkably lower than that of the 2D peak of graphite.
Heavily p-Type Doping of Bulk 6H-SiC and 3C-SiC Grown from Al-Si Melts
Authors: Mercier Frédéric , Galben-Sandulache Irina G. , Marinova Maya , Zoulis Georgios , Ouisse Thierry , Polychroniadis Efstathios K. , Chaussende Didier
Published: May 2010

We report in this work, the solution growth of heavily p-type doped 3C-SiC and 6H-SiC. Description of the 3C and 6H-SiC crystals in terms of defects and resistivity are presented and discussed with respect to growth conditions such as temperature, Al content in the melt and seed polarity. Crystals and thick layers are investigated by means of TEM, NDIC microscopy and Raman.
Strain and Charge in Epitaxial Graphene on Silicon Carbide Studied by Raman Spectroscopy
Authors: Röhrl Jonas , Hundhausen Martin , Speck Florian , Seyller Thomas
Published: May 2010

The phonon frequencies of epitaxial graphene on silicon carbide (SiC) depend on
mechanical strain and charge transfer from the substrate to the epitaxial layer. Strain and
doping depend on the preparation process and on the number of graphene layers. We measured
the phonon frequencies by Raman spectroscopy and compare the results between epitaxial
layers fabricated by high temperature annealing and by hydrogen intercalation of the covalently
bound graphene layer of the 6
p
3 6
p
3 reconstructed SiC surface. Only the latter graphene
layer shows tensile strain, which can partly be explained by lattice mismatch between substrate
and epitaxial graphene.
Uniformity of Epitaxial Graphene on On-Axis and Off-Axis SiC Probed by Raman Spectroscopy and Nanoscale Current Mapping
Authors: Sonde Sushant , Giannazzo Filippo , Huntzinger Jean Roch , Tiberj Antoine , Syväjärvi Mikael , Yakimova Rositza , Raineri Vito , Camassel Jean
Published: May 2010

Epitaxial graphene was grown on the surface of on-axis and off-axis SiC (0001) by solid state graphitization at high temperatures (2000 °C) in Ar ambient. The effect of the miscut angle on the lateral uniformity of the few layers of graphene (FLG) was investigated by combined application of micro-Raman spectroscopy and Torsion Resonance Conductive Atomic Force Microscopy, the latter method enabling a quantification of the FLG coverage on SiC with submicrometer lateral resolution. While the on-axis samples result in uniform coverage by thin (~ 3 monolayers) FLG, the coverage for off-axis samples is much less uniform, following closely the step bunching morphology of the SiC surface.
Density Functional Simulations of Physisorbed and Chemisorbed Single Graphene Layers on 4H-SiC (0001), (000-1) and 4H-SiC:H Surface
Authors: Goss Jonathan P. , Briddon Patrick R. , Wright Nicolas G. , Horsfall Alton B.
Published: May 2010

The nature of the interaction between the substrate and the graphene is critical
in terms of impact upon the graphene electron dispersion relation, and in terms of charge
transfer. We present here the results of density functional simulations of 4H-SiC–graphene
heterostructures using large, periodic simulation supercells. We show that covalent bonding
between the substrate and graphene leads both to changes in the electronic structure, and
extensive charge transfer, but that the larger simulation system yields qualitatively different
electronic structure to that from the more usual p3 ×
p3R30◦ cell.
Hydrogen Intercalation below Epitaxial Graphene on SiC(0001)
Authors: Riedl Christian , Coletti Camilla , Iwasaki Takayuki , Starke Ulrich
Published: May 2010

In this report we review how intrinsic drawbacks of epitaxial graphene on SiC(0001)
such as n-doping and strong electronic influence of the substrate can be overcome. Besides
surface transfer doping from a strong electron acceptor and transfer of epitaxial graphene from
SiC(0001) to SiO2 the most promising route is to generate quasi-free standing epitaxial graphene
by means of hydrogen intercalation. The hydrogen moves between the (6p3×6p3)R30◦ reconstructed
initial carbon (so-called buffer) layer and the SiC substrate. The topmost Si atoms
which for epitaxial graphene are covalently bound to this buffer layer, are now saturated by
hydrogen bonds. The buffer layer is turned into a quasi-free standing graphene monolayer, epitaxial
monolayer graphene turns into a decoupled bilayer. The intercalation is stable in air and
can be reversed by annealing to around 900 °C. This technique offers significant advances in
epitaxial graphene based nanoelectronics.
Techniques for the Dry Transfer of Epitaxial Graphene onto Arbitrary Substrates
Authors: Caldwell Joshua D. , Anderson Travis J. , Hobart Karl D. , Culbertson James C. , Jernigan Glenn G. , Kub Fritz J. , Tedesco Joseph L. , Hite Jennifer K. , Mastro Michael E. , Myers-Ward Rachael L. , Eddy Charles R. , Campbell Paul M. , Gaskill D. Kurt
Published: May 2010

Epitaxial graphene (EG) grown on the carbon-face of SiC has been shown to exhibit high carrier mobilities, in comparison to other growth techniques amenable to wafer-scale graphene fabrication. The transfer of large area (>mm2) graphene films to substrates amenable for specific applications is desirable. We demonstrate the dry transfer of EG from the C-face of 4H-SiC onto SiO2, GaN and Al2O3 substrates via two approaches using either 1) thermal release tape or 2) a spin-on, chemically-etchable dielectric. We will report on the impact that these transfer processes has upon the electrical properties of the transferred EG films.
Influence of Processing and of Material Defects on the Electrical Characteristics of SiC-SBDs and SiC-MOSFETs
Authors: Fukuda Kenji , Kinoshita Akimasa , Ohyanagi Takasumi , Kosugi Ryouji , Sakata T. , Sakuma Y. , Senzaki Junji , Minami A. , Shimozato Atsushi , Suzuki Takuma , Hatakeyama Tetsuo , Shinohe Takashi , Matsuhata Hirofumi , Yamaguchi Hiroshi , Nagai Ichiro , Harada Shinsuke , Ichinoseki Kyoichi , Yatsuo Tsutomu , Okumura Hajime , Arai Kazuo
Published: May 2010

The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.
Experimental Evaluation of Different Passivation Layers on the Performance of 3kV 4H-SiC BJTs
Authors: Ghandi Reza , Domeij Martin , Esteve Romain , Buono Benedetto , Schöner Adolf , Han Ji Sheng , Dimitrijev Sima , Reshanov Sergey A. , Zetterling Carl Mikael , Östling Mikael
Published: May 2010

In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 °C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.
TEM Observations of Ti/AlNi/Au Contacts on p-Type 4H-SiC
Authors: Tsao Bang Hung , Lawson Jacob W. , Scofield James D. , Baca Javier Francisco
Published: May 2010

Improved AlNi-based ohmic contacts to p-type 4H-SiC have been achieved using low energy ion (Al+)implantation, the addition of a thin Ti layer, and a novel two-step implant activation anneal process. AlNi/Au contacts with and without Ti were studied, which resulted in contact resistivities around 1.8x10-4 -cm2 and 2.0x10-3 -cm2 respectively. Even though these values were higher than those of the Ti/AlNi/W system, which was the focus of previous studies, the reduced anneal temperature (650 to 700°C) implies that Ti/AlNi/Au is a promising composite configuration. Cross-sectional TEM and EDX were used to investigate the interfacial structure of the contacts. One possible mechanism for the improved ohmic contact behavior is that the addition of Au and Ti resulted in a reduction barrier height.
Reliability Tests of Au-Metallized Ni-Based Ohmic Contacts to 4H-n-SiC with and without Nanocomposite Diffusion Barriers
Authors: Kuchuk Andrian V. , Guziewicz M. , Ratajczak Renata , Wzorek Marek , Kladko V.P. , Piotrowska Anna
Published: May 2010

The reliability of Ni2Si/n-SiC ohmic contacts with Au overlayer either without or with Ta-Si-N diffusion barrier was investigated after long-time aging in air at 400oC and rapid thermal annealing in Ar up to 800oC. It is shown that aging of the Au/Ni2Si/n-SiC contacts in air at 400oC resulted in complete degradation due to both oxygen penetration and interdiffusion/reaction processes. In contrast, only a small change in properties was detected on the contacts annealed in Ar at 800°C. The stability of both electrical and structural properties of Au/TaSiN/Ni2Si/n-SiC thermally stressed contacts at different conditions points out their superior thermal stability.
Recent Advances in Surface Preparation of Silicon Carbide and other Wide Band Gap Materials
Authors: Zielinski Marcin , Moisson Catherine , Monnoye Sylvain , Mank Hugues , Chassagne Thierry , Roy Sebastien , Bazin Anne Elisabeth , Michaud Jean François , Portail Marc
Published: May 2010

In this contribution we recapitulate the state of the art of silicon carbide and related materials polishing. Since the demonstration (by Vicente et al) of an ultimate preparation of Si-face -SiC wafers some important progresses were made in the field of surface preparation of silicon carbide and related materials. This concerns the industrial, high output treatments of substrates of increasing size, as well as the research studies of the feasibility of new preparation approaches for wide band gap materials. We also discuss the problems related to the polishing of the polycrystalline material and to the planarization of epilayers.
Reduction of Surface Roughness of 4H-SiC by Catalyst-Referred Etching
Authors: Okamoto Takeshi , Sano Yasuhisa , Hara Hideyuki , Hatayama Tomoaki , Arima Kenta , Yagi Keita , Murata Junji , Sadakuni Shun , Tachibana K. , Shirasawa Y. , Mimura Hidekazu , Fuyuki Takashi , Yamauchi Kazuto
Published: May 2010

Flat and well-ordered surfaces of silicon carbide (SiC) substrates are important for electronic devices. Furthermore, researchers have reported that 4H-SiC surface roughness increases by step-bunching during epitaxial growth and annealing. Degradation of device properties induced by surface roughening is of great concern. Therefore, a method to reduce this surface roughening is requested. We have developed a damage-free planarization method called catalyst-referred etching (CARE). In this paper, we planarized 4H-SiC substrates and evaluated the processed surface before and after the epitaxial growth. Then, we reduced the step-bunching on the epi-wafer surface and determined the electrical properties of the Schottky barrier diodes (SBD) on the processed surface.
Gate Oxide Long-Term Reliability of 4H-SiC MOS Devices
Authors: Yu Liang Chun , Cheung Kin P. , Dunne Greg , Matocha Kevin , Suehle John S. , Sheng Kuang
Published: May 2010

Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.
Rapid and Efficient Oxidation Process of SiC by In Situ Multiple RTP Steps
Authors: Constant Aurore , Camara Nicolas , Godignon Philippe , Berthou Maxime , Camassel Jean , Decams Jean Manuel
Published: May 2010

Rapid Thermal Processing (RTP) has been evaluated as an alternative to conventional furnace technique for oxidation of 4H- and 3C-SiC. We show that the growth of the SiO2 films in a RTP chamber is orders of magnitude faster than in a conventional furnace. As well as being fast, this process leads to oxide films with quality comparable or even better than the one grown in classical furnaces. Studying different gas for oxidizing and annealing ambient, we demonstrate that SiO2/SiC interface is significantly improved when using N2O instead of O2 or even N2-O2 dilution.
Comparative Study of Thermal Oxides and Post-Oxidized Deposited Oxides on n-Type Free Standing 3C-SiC
Authors: Esteve Romain , Schöner Adolf , Reshanov Sergey A. , Zetterling Carl Mikael
Published: May 2010

The electrical properties of oxides fabricated on n-type 3C-SiC (001) using wet oxidation and an advanced oxidation process combining SiO2 deposition with rapid post oxidation steps have been compared. Two alternative SiO2 deposition techniques have been studied: the plasma enhanced chemical vapor deposition (PECVD) and the low pressure chemical vapor deposition (LPCVD). The post-oxidized PECVD oxide is been demonstrated to be beneficial in terms of interface traps density and reliability.
Growth and Properties of SiC On-Axis Homoepitaxial Layers
Authors: ul Hassan Jawad , Bergman Peder , Palisaitis Justinas , Henry Anne , McNally Patrick J. , Anderson S. , Janzén Erik
Published: May 2010

Homoepitaxial growth has been performed on 3” Si-face on-axis 4H–SiC substrates using standard gas system in a horizontal Hot-wall chemical vapor deposition system. Substrate surface damages are found to act as preferential nucleation sites for 3C inclusions also, the surface morphology after in-situ etching is found to largely influence the polytype stability in the epilayer. Different in-situ etching conditions were studied where Si-rich conditions are found to be better. Growth parameters and starting growth conditions are refined to obtain stable polytype in the epilayer. High quality homoepitaxial layers with 100% 4H–SiC are obtained on 3” substrates. Different optical and structural techniques are used to characterize the layers and to understand the growth mechanisms. The layers are found to be of high quality and no epitaxial defects typically found on off-axis epitaxial layers are observed. A high surface roughness is observed in these layers, however higher growth rate significantly lowers the surface roughness without affecting the polytype stability in the epilayer.
Reliability of Thin Thermally Grown SiO2 on 3C-SiC Studied by Scanning Probe Microscopy
Authors: Eriksson Jens , Weng Ming Hung , Roccaforte Fabrizio , Giannazzo Filippo , Fiorenza Patrick , Lorenzzi Jean , Ferro Gabriel , Raineri Vito
Published: May 2010

This paper reports on the electrical characteristics of thermally grown SiO2 on cubic silicon carbide (3C-SiC). The 3C-SiC (111) was grown on Si-face 6H-SiC (0001) on-axis substrates by a non-conventional Vapor-Liquid-Solid (VLS) technique. Scanning probe microscopy techniques, including Atomic Force Microscopy (AFM), Scanning Capacitance Microscopy (SCM) and tunneling AFM (TUNA) were employed to study the morphology, local capacitance and local current variations across the sample surface. This nanoscale investigation allowed monitoring the homogeneity, as well as reliability in terms of dielectric breakdown (BD), of the thermally grown SiO2. In this way it was possible to gain insights into the breakdown related to pre-existing defects (extrinsic breakdown) as well as the actual intrinsic breakdown of the dielectric.
Temperature Facilitated ECR-Etching for Isotropic SiC Structuring
Authors: Niebelschütz Florentina , Stauden Thomas , Tonisch Katja , Pezoldt Joerg
Published: May 2010

In order to realize complex three dimensional or free standing structures on SiC substrates, an undercut, i.e. a selective isotropic etching process of SiC, is required. This was realized using an electron cyclotron resonance etching set up with pure SF6 and a SF6/Ar gas composition at elevated substrate temperatures. Above 350°C a significant lateral etch component was observed, which rose to a value of 50-70 nm/min increasing the substrate temperature up to 570°C during the etching process. Depending on substrate temperature the etching profiles and surface roughness were studied. Based on an analysis of the influence of microwave power, working pressure, bias voltage, gas flow and gas mixture on the etching behavior a novel isotropic, high selective, residue free etch process for SiC was developed, which allows for example the fabrication of piezoelectric actuated AlGaN/GaN resonators grown on SiC substrates.
Growth and Characterization of Large-Diameter 4H-SiC Crystals with High Crystal Quality
Authors: Nakabayashi Masashi , Fujimoto Tatsuo , Katsuno Masakazu , Tsuge Hiroshi , Aigo Takashi , Satoh S. , Yashiro Hirokatsu , Hoshino Taizo , Hirano Hosei , Ohashi Wataru
Published: May 2010

In-grown type stacking faults (SFs) like structures were observed in 100mm diameter 4H-SiC crystals by Photoluminescence (PL) mappings, and structural analyses using HRTEM clarified that the SF-like structures were comprised of 6H (3, 3) stacking sequences. The stacking sequences of the SF-like structures observed are different from the SFs formed in the a-face grown crystals, suggesting that it is due to 6H nucleation on {0001} plane terraces.
Optimization of Bipolar SiC-Diodes by Analysis of Avalanche Breakdown Performance
Authors: Bartsch Wolfgang , Schörner Reinhold , Dohnke Karl Otto
Published: May 2010

In this work we discuss measurements of the breakdown voltage of diodes with non-punch-through (NPT)- and punch-through (PT)-designs. From the experimental results we deduce the temperature dependent Fulop constants of the effective ionization rate. The data of this work agree very well with ionization rates for electrons and holes determined recently.
Analyses of High Leakage Currents in Al+ Implanted 4H SiC pn Diodes Caused by Threading Screw Dislocations
Authors: Tsuji Takashi , Tawara T. , Tanuma Ryohei , Yonezawa Yoshiyuki , Iwamuro Noriyuki , Kosaka K. , Yurimoto H. , Kobayashi S. , Matsuhata Hirofumi , Fukuda Kenji , Okumura Hajime , Arai Kazuo
Published: May 2010

The authors fabricated pn diodes with Al+ implantation in p-type epitaxial layers, and investigated the influence of the implantation dose on reverse leakage currents. Only in the highest dose with the Al concentration of 2x1020cm-3, more than 90% of the devices showed high leakage currents above 10-4A at the maximum electric field of 3MV/cm. In such devices, almost all of the emissive spots corresponded to threading screw dislocations (TSDs) by the analysis of emission microscopy and X-ray topography. These TSDs were defined as killer defects with the estimated density of 500cm-2 in the case of the highest dose. The emissions were supposed to be due to microplasmas, since the spectra of the emissions were different from those of heat radiation. Condensation of Al atoms, nitrogen atoms and DI defects were excluded as the origin of the emissions by secondary ion mass spectrometry and low temperature photoluminescence analyses.
Feasibility of Efficient Power Switching Using Short-Channel 1200-V Normally-Off SiC VJFETs; Experimental Analysis and Simulations
Authors: Veliadis Victor , Hearne Harold , Stewart Eric J. , Howell R. , Lelis Aivars J. , Scozzie Charles
Published: May 2010

A recessed implanted-gate short-channel 1290-V normally-OFF 4H-SiC vertical-channel JFET (VJFET), fabricated in seven photolithographic-levels, with a single masked ion-implantation and no epitaxial regrowth, is evaluated for efficient power conditioning. Under unipolar high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits prohibitively high on-state resistance. Comparison with 1200-V normally-ON VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V normally-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high current-gain VJFET operation. Recessed-implanted-gate VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial-regrowth) revealed that although aggressively increasing channel doping lowers resistance, the corresponding reduction in source mesa-width can prohibitively limit manufacturability.
Fast Switching with SiC VJFETs - Influence of the Device Topology
Authors: Elpelt Rudolf , Friedrichs Peter , Biela Jürgen
Published: May 2010

Since SiC VJFETs are believed to offer extremely fast turn on and turn off processes it is important to understand how these transients are tailored by the layout. Regarding the basic layouts two main topologies are under investigation today – structures with the well known SIT layout with purely vertical current flow and lateral vertical concepts where the current flow through the channel is in lateral direction and the vertical current flow takes place in the drift region only. In this paper we will focus on differences in the electric characteristics of both structures and the relation of the dynamic behavior to the topology and the layout of the switches. For the analysis, 1200V VJFETs based on the two basic topologies were manufactured having approximately the same total and active device area. It turns out that the SIT switches under investigation suffer from a high internal gate resistance in the p-doped layers and a relatively high gate drain capacitance.
Beginning of the Hungarian Space Metallurgy Activity: The BEALUCA Project
Authors: Fuchs Erik G.
Published: May 2010

The Hungarian research group which dealt with some solidification problems have obtained a possibility to work out an space metallurgy project in 1980 during the Hungarian-Soviet joint space mission. The goals of the experiment were to control the developed simulation method and the demonstration of some fundamental effects. The experiments were performed on the SALYUT 6 space station in the SPLAV and KRISTAL furnaces. The materials were Al-4%Cu alloy and pure aluminum rod covered by copper mantle. In case of the Al-4%Cu alloy the details of the solidification (microsegregation, dendritic structure) while in case of copper covered aluminum rod the diffusion in the melt were investigated. The results of the space experiments have confirmed the usability of the developed simulation and have established the further work. The experiences of this work have contributed to the developing of the so called Hungarian Space Furnace (Universal Multizone Crystallizator, UMC).
Ni Content Surface Layer Produced by Laser Surface Treatment on Amorphisable Cu Base Alloy
Authors: Svéda Mária , Janovszky Dóra , Tomolya Kinga , Sólyom Jenő , Kálazi Zoltán , Buza Gábor , Roósz András
Published: May 2010

The aim of our research was to comparatively examine Ni content surface layers on amorphisable Cu base alloy produced by different laser surface treatments. Laser surface treatment (LST) techniques, such as laser surface melting, laser alloying and laser cladding, provide a wide range of interesting solutions for the production of wear and corrosion resistant surfaces. [1,2] With LST techniques, the surface can be: i) coated with a layer of another material by laser cladding, ii) the composition of the matrix can be modified by laser alloying. [3] Two kinds of laser surface treatment technologies were used. In the case of coating-melting technology a Ni content surface layer was first developed by galvanization, and then the Ni content layer was melted together with the matrix. In the case of powder blowing technology Ni3Al powder was blown into the layer melted by laser beam and Argon gas. LST was performed using an impulse mode Nd:YAG laser. The laser power and the interaction time were 2 kW and 20÷60 ms. The characterization of the surface layer microstructure was performed by XRD, scanning electron microscopy and microhardness measurements.