SECURITY ANALYSIS AND EXPLOITATION OF IC CHIP LEVEL COUNTER QUANTITY AGAINST BODILY OCCURRENCES
Authors: KADIRE SUMALATA , ANJANI V SAI , P AKSHITHA  , SRI V RAMYA 
Published: December 2024

This article addresses the growing concern of security vulnerabilities in hardware systems, particularly in the context of integrated circuit (IC) chips used in cryptographic applications, which are increasingly susceptible to adversarial physical attacks in real-world environments. These attacks, often targeting the physical integrity of ICs, exploit weaknesses in both the design and manufacturing processes of cryptographic circuits. The paper provides a comprehensive overview of these threats, focusing on various physical attack methods, such as sidechannel attacks, electromagnetic (EM) attacks, and laser fault injection attacks, which compromise the confidentiality and functionality of secure systems. It also highlights the vulnerabilities inherent in IC chips, particularly in relation to how attackers can manipulate or exploit system weaknesses during operation. The article delves into the protection mechanisms that are being integrated into modern cryptographic IC chips to prevent or mitigate these physical threats. One of the key strategies discussed is the use of on-chip monitoring circuits, which can actively sense and respond to adversarial attempts, providing an early warning or immediate countermeasures. These monitoring circuits are designed to detect unusual patterns that could indicate an ongoing attack, such as fluctuations in power or electromagnetic emissions, enabling dynamic protection of the system during operation. Additionally, the paper explores innovative physical structures, such as backside buried metal (BBM) wirings in silicon (Si) substrates, which are combined with frontside complementary metal–oxide semiconductor (CMOS) circuits to create robust defenses against a variety of physical attacks. This integration of backside metal wirings with frontside CMOS technology is a novel approach that enhances the IC's resilience by providing a physical barrier that reduces the ability of attackers to exploit weaknesses in the power delivery network and other sensitive components. By creating a unified approach to IC design and packaging, the paper emphasizes the importance of incorporating multiple layers of protection, such as detection, avoidance, and resilience, against electromagnetic and laser-based attacks. The combination of these advanced technologies establishes a more secure architecture that can defend against multimodal attacks, thus ensuring the integrity of cryptographic systems. The article also highlights the practical implementation of these protective strategies, including tests with silicon demonstrators to validate the effectiveness of the proposed solutions. The results show promising outcomes, demonstrating the feasibility of creating secure hardware systems that can withstand physical attacks and provide reliable protection for sensitive data and cryptographic operations. Through the integration of on-chip monitoring, advanced IC design principles, and packaging innovations, this paper offers a roadmap for developing secure, resilient hardware systems capable of withstanding the evolving threat landscape posed by physical attacks on IC chips. Ultimately, the proposed protection schemes not only strengthen the security of cryptographic circuits but also contribute to the broader field of hardware security, providing insights for future designs and applications.