bluuebunny/crossref_metadata_2025 huggingface dataset:
Temperature and Process Dependent Material Characterization and Multiscale Stress Evolution Analysis for Performance and Reliability Management under Chip Package Interaction
Authors: Karmarkar Aditya P. , Xu Xiaopeng , El-Sayed Karim
Published: November 2017

Distinct temperature and process dependent deformation behaviors under packaging temperature cycles are characterized for various packaging materials. Substrate and underfill deformations are described using Maxwell viscoelasticity model. Solder bump deformation is represented by incremental plasticity model. Anisotropic deformation in silicon and orthotropic deformation in substrate are also considered. The material deformation effects on stress evolutions during fabrication and under chip package interaction (CPI) are analyzed for a large package structure. Complex geometries spread over a large range of length scales are simulated using multi-level and multiscale sequential submodeling technique. Global package simulations show that substrate orthotropy has a significant impact on the package warpage during the assembly process. Sequential package assembly simulations are performed to examine the residual stresses at package, bump and interconnect scales. The results show that the package material behaviors during the assembly process affect not only the residual stresses in the large package structure but also in the local bump regions and the interconnect structures. The temperature dependent material non-linear behaviors under operating conditions also affect residual stresses and carrier mobility. This work demonstrates that developing performance and reliability management strategies under CPI should consider temperature and process dependent material deformations during fabrication and packaging.
Fine Resolution Photosensitive Polyimide Dry Film with High Resistance to Electromigration under HAST condition
Authors: Tomikawa Masao , Matsumura Kazuyuki , Shoji Yu , Tatsuta Yoshiko , Okuda Ryoji
Published: November 2017

We investigated the effects of photosensitive system (positive and negative) and polymer structures on Cu migration under bias HAST test. The HAST condition is 130C for 85% RH. Bias condition is 2MV/m. We found that there is polyimide structure shows big effect is big effect of no big difference between negative photosensitivity and positive photosensitivity in photo sensensitive polyimides. Polyimide structure effects significant difference on Cu migration under bias HAST condition. Cu migration of soft polyimide seems better than that of rigid polyimide. From these results, we developed good reliable photosensitive polyimide B-sheet having fine pattern capability successfully.
Packaging and Miniaturization of a 2–18 GHz UWB Radar for Measurements of Snow and Ice: Initial Results
Authors: Morales F. R. , Leuschen C. , Feathers A. , McDaniel J. , Wolf A. , Garrison S.
Published: November 2017

We report recent progress towards miniaturizing and packaging an ultra wideband (UWB) radar developed for measurements of ice and snow over the 2–18 GHz range. The initial objective of this work is the close integration of the radar's RF section (composed of a receiver and a low-power transmitter) while maintaining or enhancing its electrical performance. First, we describe a connectorized reference system developed to serve as a performance benchmark for transmit and receive signal chains. Next, we discuss the use of drop-in modules to achieve a significant size reduction of the RF front-end. These modules are based on packaged chips and arranged in a planar configuration. We present system-level performance metrics of the reference system justifying the need for further integration. We briefly discuss other potential applications of the miniaturized radar and the direction of future packaging efforts as we work toward our future goal of integrating the complete radar “from antenna to bits” by using a system-in-package approach.
3D Printed Metalized Plastic Waveguides for Microwave Components
Authors: Ghazali Mohd Ifwat Mohd , Park Kyoung Youl , Gjokaj Vincens , Kaur Amanpreet , Chahal Premjeet
Published: November 2017

This paper investigates the design and fabrication of 3D printed waveguide and their application for the design of microwave passive components. This includes a simple waveguide structure, a band pass filter, and a leaky wave. A Lego-like approach is used to assemble together different 3D printed sub-sections after metal coating. These allow the structure to be fabricated in multiple layers. Simulation and measured results match closely. Details of modeling, fabrication and measurement are presented for these three passive components.
Building an EcoSystem for User-friendly Design of Advanced System in Package (SiP) Solutions
Authors: Reiter Herb
Published: November 2017

The Semiconductor Industry has followed “Moore's Law” for more than five decades and has made remarkable progress by continuously shrinking features sizes. However, meeting today's and future market requirements, such as shorter development times, lower up-front cost, lower unit cost, many more gates and pins in even smaller form-factors, integration of heterogeneous functions (logic, memory, analog, RF, MEMS, sensors, optical and others) and higher performance per Watt is becoming much more challenging. These requirements call for advanced IC packaging technologies to enable continued semiconductor revenue and profit growth.

In addition to IC packaging-specific expertise and development resources, very close cooperation with knowledgeable partners across all planning, design and manufacturing steps is needed, to create cost-effective and reliable electronic components, sub-systems, even entire systems in a package.

This paper analyzes why and where advanced IC packaging technologies are needed and suggests steps for developing Assembly Design Kits (ADKs) and Reference Design Flows, and other essential elements for building a strong “More than Moore”-focused semiconductor EcoSystem.
Printed Wiring for High-Power Electric Devices by Using Ag-sinter paste
Authors: Noh Seungjun , Choe Chanyang , Chen Chuantong , Nagao Shijo , Suganuma Katsuaki
Published: November 2017

This work introduces the possibility of using Ag sinter-paste as a novel high-temperature and high-current wire bonding solution. We investigated the electromigration (EM) behavior and lifetime of the sintered Ag wiring under high current density and high temperature required for the design of power electronic devices. The sinter Ag wiring fabricated on the two Cu substrates were tested under current densities of 2.7 × 104 A/cm2 at temperature of 250 °C. The microstructure evolution of sintered wiring was characterized after EM test. The resistance of sintered wiring did not change even after EM test for 300 hours, which confirms that the Ag-paste sinter wire bonding is rather stable than aluminum wire bonding under high temperature and high current density. No degradation was observed in microstructure of sintered wiring after EM test. Thus, it is expected that Ag paste sinter wire bonding is one of potential alternative interconnection technology for power electronic devices.
3D IPD on Thru Glass Via Substrate using panel Manufacturing Technology
Authors: Takano Takamasa , Kuramochi Satoru , Yun Hobie
Published: November 2017

As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes.

Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor.

This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers.

The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.
Ultra-fine Line Multi-Redistribution Layers with 10 μm Pitch Micro-Vias for Wafer Level and Panel Level Packaging realized by an innovative Excimer Laser Dual Damascene Process
Authors: Gernhardt Robert , Müller Friedrich , Woehrmann Markus , Hichri Habib , Hauck Karin , Toepper Michael , Arendt Markus , Lang Klaus-Dieter
Published: November 2017

Multi-chip integrated Fan-Out packages and high I/O CSPs demands for higher routing density on wafer level. Due to that, the classical mask aligner lithography and photosensitive thin-film polymers used for BEOL reach its limits and new technologies and materials are necessary to generate lines and space down to two μm. These multi-metal layers set also higher demands on the mechanical properties of the materials.

This paper presents a new excimer laser dual damascene process for ultra-fine routing for BEOL. Various materials like low cure temperature polyimide, BCB and 15-μm thick dry-film ABF material are structured by using an excimer laser stepper with a reticle mask to realize feature size below four μm with a high throughput.

Micro-vias with a diameter below five μm are realized with high aspect ratio, which overcome the photolithographic limitations of the common used photosensitive thin-film polymers. The laser structuring allows to use innovative dielectric materials for WLP with optimized mechanical and electrical parameters for example inorganic filled polymers like dry-film ABF materials, which do not have to be photosensitive. The ablations depth per laser pulse and the cross-section of the ablated structures in dependence of the ablation parameters was investigated. The depth of embedded lines was set by number of pulses aside of integrated micro-vias. The lines and micro-vias were metallized with copper by galvanic process and the following CMP step removes the copper outside the ablated structures. The CMP removes only the copper and the metal of the seed-layer, which has the functions of an adhesion and barrier layer, stays intact. The under-etching of the conventional wet etch seed layer removal is a major problem for the fine line structures realized by the Laser Dual Damascene process. Due to that, the removal of the seed layer (usually titan) was investigated and it could be shown, that this layer can be removed by the excimer laser system. The stepper like system allows a sub-micron alignment accuracy with no need of a capture pad of the embedded lines. Test structures have been designed and fabricated with lines and spaces below 10 μm to demonstrate the dense multi-layer routing capability where the excellent reliability can be proven by air to air thermal cycling (from −55°C up to 125°C), current leakage and electro migration test.
Separating Temporary Carrier from Large Thin Panel with Air Jetting
Authors: Tang Hao , Nguyen My , Yin Ming
Published: November 2017

As electronic components becomes thinner and more powerful than ever, substrates are being pushed to be so thin that they are flexible. Furthermore, both passive and active components are being embedded into substrates to further reduce packaging thickness. To fabricate a substrate that is too thin to be rigid and flat, a temporary carrier is applied onto the substrate to support the fabrication. However, but it must be removed upon completion, and the substrate and carrier must be bonded with very high adhesion strength during solder reflow cycles, due to a mismatch in the coefficient of thermal expansion (CTE). Such high adhesion strength typically creates more problems in the debonding process.

Unlike mechanical debonding, which generates significant peeling stress on a device's surface, air jet debonding introduces air streams between the carrier and the substrate, thus lifting the carrier from underneath and compressing the substrate surface downward. This results in the most uniform stress distribution, which is best suited for larger-area debonding processes.

In this paper, the air-jet debonding of a glass carrier from a 300 x 300 mm thick panel is demonstrated. The bonding adhesive Z-Coat 421G is developed to temporarily bond with panel substrate for lead-free assembly.
Enhanced In-Plane Heat Transport in Embedded Mini Heat Pipes PCB
Authors: de Sousa Jonathan Silvano , Fulmek Paul , Unger Michael , Haumer Peter , Nicolics Johann , Ras Mohamad Abo , May Daniel
Published: November 2017

We demonstrate the embedding of heat pipes as a solution for heat management in high density applications where heat spreading and heat guiding can be extremely important. Measurements results describe the advantages of the presented technology in comparison with thick copper inlays in the PCB. Further, this paper will also discuss the transient aspects of the heat transport in PCBs with embedded heat pipes.
Direct Measurement of Silicon Strain in a Fine Pitch Flip Chip BGA Package
Authors: Whitchurch Nathan , Rinne Glenn , Lin Wei , Balaraman Devarajan
Published: November 2017

A method for directly measuring the silicon strain in a flip chip ball grid array (FCBGA) package is disclosed. The method uses anisotropically etched holes in the die backside to reveal fiducial crosses on the front side of the die. A geometric model is proposed that allows extraction of the strain component of the measured displacement. A finite element model is described which correctly predicts the sign and magnitude of the strain.
Non-Destructive Testing for System-in-Package Integrity Analysis
Authors: Becker Karl-Friedrich , Minkus Mathias , Pauls Jeremias , Bader Volker , Voges Steve , Braun Tanja , Jungmann Gerd , Wieser Hubert , Schneider-Ramelow M. , Lang K.-D.
Published: November 2017

The constant drive of microelectronics towards ever higher degrees of integration leads to a wide variety of concepts to yield smallest packages with maximized functionality – while side by side packaging leads to thinnest packages a small footprint can typically only be achieved by using component stacking approaches. This leads to truly heterogeneous packages where a variety of materials are forming a complex potpourri of building blocks with different thermo-mechanical properties. While building such an integrated package needs high precision material dosing, component placement and fine pitch wire bonding and is already challenging – the non-destructive analysis of such packages for process and reliability characterization is even trickier. Additionally this NDT approach can not only be applied to determine the initial device quality but also during accelerated ageing tests as a tool for intermediate testing to determine the effects of chip-package interaction.

At Fraunhofer IZM a methodology has been applied to analyze a molded package using state of the art NDT equipment. A high resolution x-ray CT system by GE and a Gen6 CSAM system have been used as complimentary means to gain insight into a reference package that contains a four die stack assembled on PCB and is overmolded by a standard transfer molding process. To facilitate setting up the analysis procedure a variety of artefacts have been introduced to the package allowing the exact localization of layers and can be used to optimize the parameters for ultrasonic analysis for the variety of transducers used for package analysis. Additionally a simulation software is used to calculate the resulting ultrasound echoes for the different intra-package layers and the applicability of this tool for setting up an analysis procedure is provided.

As a result the paper describes an analysis methodology for highly integrated packages that uses CSAM analysis and x-ray CT for device analysis, while cross sectioning is used to confirm these results. Ultrasound simulation is applied to explain the findings of analysis process setup and will be evaluated on its potential to transfer the analysis method to SiP packages with varying geometry.
Silicon microfluidics: An enabling technology for life sciences application
Authors: Majeed Bivragh. , Zhang Lei , Fiorentino Giuseppe , Verbinnen Greet , Ashraf Huma , Walsby Edward , Roberts Kerry , Al Kuzee Jafar , Dawe Rhys , Thomas Dave , Sabuncuoglu Deniz.
Published: November 2017

In this paper we review the silicon microfabrication process that has been developed for various life science applications over the last several years. Silicon microfabrication is a key enabling technology in the developing personalized point of care or point of need systems. Silicon microfabrication allows for accurate control of fine features and it can combine active and passive components within a single chip. It is also very reliable, repeatable and it benefits from cost reduction due to mass production capabilities

Depending on the application, we have fabricated devices with either a single silicon etch or a two-step approach. Single step etches are typically 250–280μm deep. Two-step etching, the shallow features are 50μm while deeper are 250μm. We have developed an optimized deep silicon etch process that gives very straight profiles with minimum loss of critical dimension (CD) for different features. The minimum CD is 3μm while the largest features are 500μm wide The etching was done an SPTS Rapier DRIE system.

We describe the working principles of the various components in the system including PCR and micropillar filters. The filter has been used for high performance liquid chromatography (HPLC). It exhibits very low broadening of the components travelling through it and separation of a mixture of coumarin dyes is efficiently performed in a very short time. A micro PCR chamber with thermal isolation to the surrounding silicon is characterized and DNA amplification is achieved.
Plasma Dicing Process-Flows for Advanced Packaging Fabrications
Authors: Wei Frank , Tabuchi Tomotaka , Sando Hideyuki
Published: November 2017

Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified a few suitable process flows. Within the plasma dicing process flows, laser grooving before plasma etching was shown to be a key unit process to control the resulting die sidewall quality. Significant improvement on laser grooving quality has been demonstrated. Through these efforts, extremely narrow kerfs and near ideal dies strengths were achieved on Si dies. The Bosch-etching based plasma dicing process generates fluorinated polymer residues both on the Si die sidewalls as well as under the topography overhangs on wafer surfaces, such as under the solder balls or micro-bumps. The fluorinated polymers in certain areas cannot be cleaned by an in-chamber post-treatments. Multiple wet chemistry-based cleaning methods demonstrated excellent process capability, and are compatible with plasma singulated dies-on-tape handling. Lastly, many methods exist for backside metal and under Si die-attach-film (DAF) separations. The authors highlighted recent processing results suitable for post-plasma dicing die separations of such film materials.
Technology Transfer for MEMS and Advanced Packaging: Precision Surface Preparation Innovatively Applied to Emerging Technologies
Authors: Roberts Bob
Published: November 2017

The purpose of this presentation is to examine how certain mainline silicon substrate and semiconductor wafer manufacturing processes, can be and are being applied to applications in the manufacture of some of the most advanced digital devices including advanced packaging applications.

Periodically, the manufacturing steps and procedures of advanced semiconductor devices have changed dramatically enough that they are termed “paradigm shifts.” Two of the more dramatic manufacturing paradigm shifts in our professional lifetimes have been Precision Ultra-Thinning, and Chemical Mechanical Polishing to achieve planarization of substrates and specifically thin films that have been deposited on those substrates. In addition to the many activities in all or nearly all semiconductor IC manufacturing operations (Integrated Circuits), these two advanced technologies are now being applied to the manufacture of MEMS, MOEMS, LEDs, OLEDs, Nanotechnology and their associated Advanced Packaging methods and procedures.

In our technology driven world, it is safe to say that hardly anything in the world of microelectronics, semiconductors, and nanotechnology has been invented only for its awe-inspiring beauty alone, with no intrinsic value toward the improvements in form factor (miniaturization), and functional operation (speed, capacity, reliability, etc.). The same can be said about these two interesting technologies.
Thermally Stable Ag-Ag Joints Bonded by Ultrasound-assisted Stress Migration Bonding
Authors: Zhang Hao , Asatani Norio , Kimoto Yukiharu , Suetake Aiji , Nagao Shijo , Sugahara Tohru , Suganuma Katsuaki
Published: November 2017

We introduce a Ag-Ag direct bonding process with the aid of ultrasonic bonding, which uses silver “Nano-volcanic eruption of Ag” caused by stress migration at 250 °C. Various preheating temperatures before the ultrasonic pulse and various sputtering methods such as direct current (DC) and radio frequency (RF) have also been evaluated. A novel bonding process which combines ultrasonic bonding and stress migration bonding (SMB) method is established. The bonding achieved a die-shear strength of more than 50 MPa and a nearly-perfect voidless bonding interface. High temperature storage (HTS) test at 250 °C was used to evaluate the thermal-resist ability of bonded SMB joints. The results indicate that the bonded joints show no obvious changes in the interfacial morphology and the die-shear stress after HTS test for 1000 h is still higher than 30 MPa. The thermally-stable SMB joints can be applied to advanced devices such as thin-wafer multi-chip integrations and next-generation power devices.
Comparative Evaluation and Analysis of Gate Driver Impacts on a SiC MOSFET-Gate Driver Integrated Power Module
Authors: Zhang Liqi , Guo Suxuan , Liu Pengkun , Huang Alex Q.
Published: November 2017

SiC MOSFET-gate driver integrated power module is proposed to provide ultra-low stray inductance compared to traditional TO-247 or TO-220 packages. Kelvin connection eliminates the common source stray inductance and zero external gate resistor enables faster switching. This module can be operated at MHz switching frequency for high power applications with lower switching losses than discrete packages. Two different gate drivers and two different SiC MOSFETs are grouped and integrated into three integrated power modules. Comparative evaluation and analysis of gate driver impacts on switching speed of SiC MOSFET is shown in detail. The paper provides an insight of the gate driver impacts on the device switching performance in an integrated power module.
Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging
Authors: Tehrani Bijan K. , Bahr Ryan A. , Tentzeris Manos M.
Published: November 2017

This paper outlines the design, processing, and implementation of inkjet and 3D printing technologies for the development of fully-printed, highly-integrated millimeter-wave (mm-wave) wireless packages. The materials, tools, and processes of each technology are outlined and justified for their respective purposes. Inkjet-printed 3D interconnects directly interfacing a packaging substrate with an IC die are presented using printed dielectric ramps and coplanar waveguide (CPW) transmission lines exhibiting low loss (0.6–0.8 dB/mm at 40 GHz). Stereolithography (SLA) 3D printing is presented for the encapsulation of IC dies, enabling the application-specific integration of on-package structures, including dielectric lenses and frequency selective surface (FSS)-based wireless filters. Finally, inkjet and 3D printing technology are combined to present sloped mm-wave interconnects through an encapsulation, or through-mold vias (TMVs), achieving a slope up to 65° and low loss (0.5–0.6 dB/mm at 60 GHz). The combination of these additive techniques is highlighted for the development of scalable, application-specific wireless packages.
Lighting System Packaging for Smart Underwater Reefs for Sensing, Communications, and Robotics
Authors: Fries David , Tate Connor , Hutcheson Tim , Josef Noam , Millie David
Published: November 2017

Strings and ropes are a proven, common fisheries and aquaculture construction elements outside the US. Using them as scaffolding also enables a diversity of ocean sensing, communications and architectures, including our goal of sentinel reefs. Packaging of electronics is key to enabling such structures and systems. Our research is towards a demonstrable science-engineering-informed framework for 3D habitat designs critical to stock fish development & coastal protection. These ‘nature-inspired’ reef infrastructures, can enable novel instrumented ‘reef observatories’ capable of collecting real-time ecosystem data. Embedding lighting and electronic elements into reef systems are the first systems in development. This new approach of bringing light to the underwater world for optical sensing, communication and even a new breed of underwater robotic vehicle is an interdisciplinary research activity which integrates principles of electronic packaging, and STEM with art/design.
Environmentally Isolating Packaging for MEMS Sensors
Authors: Kranz Michael , Whitley Michael , Rudd Carl , Craven Jeff D. , Clark Steven D. , Dean Robert N. , Flowers George T.
Published: November 2017

Microelectronic systems employing MEMS devices are often constrained by limits on size, weight, power, and cost (SWaP-C), while also being exposed to severe shock and vibration during storage, transport, and operation. This combination of requirements has proven difficult to meet using current technology. Incorporating isolators into microelectronic systems improves performance through shock and vibration, but at the expense of cost and size metrics. Systems based on MEMS technologies have the potential to improve upon size and cost metrics for many applications. MEMS technology has made significant strides in performance in recent years. MEMS-based devices are commonly found in consumer applications for a variety of functions. However, MEMS based devices have been known to experience performance degradation while operating through stressing shock and vibration environments. The goal of this work was to develop MEMS technology that is sufficiently robust as to operate through the demanding environments of systems, and to include the design, simulation, and prototype of micro-isolators capable of attenuating shock and vibration prior to their input into the MEMS devices, thereby isolating them from the harsh environment.
Adhesion Characteristics of Epoxy Molding Compound and Copper Leadframe Interface: Impact of Environmental Reliability Stresses
Authors: Lakhera Nishant , Shantaram Sandeep , Sakib AR Nazmus
Published: November 2017

Delamination at the mold compound and leadframe interface is the most common failure mode observed during processing and qualification of the microelectronic package. Mold compound to leadframe delamination is typically observed after environmental reliability stresses like: moisture preconditioning and reflow, air-to-air thermal cycling, biased highly accelerated stress etc. Leadframe based packages constitutes majority of microelectronic packages that are manufactured today, which makes mold compound/leadframe interface of great interest requiring thorough understanding of the adhesion characteristics and its evolution as a function of reliability stresses. This study used four-point bend testing to evaluate the adhesion strength of commercially available mold compound to bare copper and silver plated copper leadframes exposed to automotive grade environmental stresses. Results show that adhesion of mold compound to silver plated leadframes is significantly lower than adhesion to bare copper leadframes. Results obtained from this study can be used to carefully select the qualification reliability stresses to prevent overstressing the package and causing failures related to wire bond cracking, delamination etc., which have significant time and cost implications. Finite element simulations were also performed to validate the empirical adhesion test results and can be extended to full package level models to enable delamination prediction.
Reliability of Coated and Alloyed Copper/Silver Ball Bonds
Authors: Murali Sarangapani , Danila Bayaras Abito , Xi Zhang
Published: November 2017

The paper discusses on the reliability of coated and alloyed copper/silver ball bonds on both epoxy molded and unmolded conditions:Moisture resistance test using unmolded device at 130°C 85%RH (humidity chamber) revealed no ball lift failure until 96hours for the ball size of 1.65 times the diameter of wireCorrosion resistance test using unmolded device at room temperature by dripping (or soaking) dilute chlorine (Cl) solution revealed no ball lift failure for gold wires. Copper base wire bonds failed after 6min of storage while silver (Ag) base wire bonds showed a few bond lifts within 2min. This shows that Ag base wires are more sensitive to Cl environment than copper (Cu) base wiresA case study of epoxy molded device using green mold compound and four types of Cu and Ag base ball bonds passed on thermal ageing (HTS) at 175°C for 4000h and on +5V bHAST for 500h. The test response is by measuring electrical resistance in order not to reduce below 10% of contact resistance measured during time zero bonding○ Cross-section analysis of the samples showed intact bonding of Cu and Ag base ball bonds after 4000h of HTS○ The result shows when Cu and Ag base wire bonds molded with a good compatible green mold epoxy compound satisfy the automotive electronic council (AEC – Q006 & Q100 Rev-H, for Cu) requirements of 2X stress test with respect to electrical resistance measurementAnother case study of epoxy molded device revealed Cu and Ag base wire bonds pass 3000cycles of thermal cycling (−55°C to +150°C) without any neck/heel cracks and stitch lifts

In addition, fine wires are baked at elevated temperature under vacuum or by purging nitrogen to find the quality of wire surface. As expected, Au, Cu and Ag base wires show clean surface. For palladium (Pd) coated Cu wire, a good Pd adhesion to Cu core surface without blisters is evident.
2.5D FPGA-HBM Integration Challenges
Authors: Gandhi Jaspreet , Ang Boon , Lee Tom , Liu Henley , Kim Myongseob , Lee Ho Hyung , Refai-Ahmed Gamal , Shi Hong , Ramalingam Suresh
Published: November 2017

FPGA partitioning and high density integration using interposer based 2.5D stacked silicon interconnect technology (SSIT) has been the pioneering work at Xilinx for several years enabling advanced applications in high performance computing, networking, hyper scale data center and cloud services etc. With the insatiable demand for acceleration workloads, FPGAs need to be coupled with in package memory to enable higher bandwidth, lower power and smaller form factor architecture. 3D stacking based high bandwidth memory (HBM) has paved the way to realize such applications providing 10X higher bandwidth, 4X lower power vs DDR4. This paper provides an overview of unique challenges involved with 2.5D FPGA-HBM SSIT integration from design, process/package development, test and reliability point of view
Next Generation Xeon Server Package Architecture
Authors: Swaminathan Raja , Viswanath Ram , Srinivasan Sriram , Chandrasekhar Arun
Published: November 2017

Semiconductor industry is moving towards more and more integration to provide more functionality and add value to the processor, thereby enabling better user experience. This integration can come in 3 categories: On-die integration, On-package integration, and On-board integration. On-board integration is the typical method being used for several generations and on-die and on-package integration architectures are getting more focus due to better performance and reduced power. The key vector to enable on-die/package architectures is reduced cost and maximum features for a given substrate and socket form factor. Silicon features are also moving at a faster pace compared to the board technology. This paper details a novel package (PoINT) architecture as well as the key technology challenges that were resolved to successfully enable this architecture.
Multiphysics Performance Evaluation of Flexible Substrate Based 1.2kV SiC Half Bridge Intelligent Power Module with Stacked Dies
Authors: Zhao Xin , Jagannadham K. , Hopkins Douglas C.
Published: November 2017

Wide Bandgap (WBG) power devices have become the most promising solution for power conversion systems, with the best trade-off between theoretical characteristics, real commercial availability and maturity of fabrications. Advanced packaging technology is being heavily developed to take full advantages of WBG devices, in terms of materials, mechanical design, fabrication and electrical performance optimizations. In this paper, a flexible substrate based 1.2kV SiC Half Bridge Intelligent Power Module with stacked dies is introduced. The module design is based on the concept “Power Supply in Package (PSiP)”, high functionality is integrated in the module. Together with power stages, gate driver circuits, Low Dropout Regulators (LDO), digital isolators, and bootstrap circuits are integrated in the module. An ultra-thin flexible epoxy-resin based dielectric is applied in the module as substrates, its thickness can be as low as 80μm, with 8W/mK thermal conductivity. The SiC switches are double-side solderable, with copper as topside metallization on pads. No bonding wires are applied in the SiC PSiP module. The highside and lowside SiC switches on the phase leg is stacked vertically for interconnections with low parasitic and high denstiy. This work mainly addresses performance evaluation of the PSiP SiC half bridge module by multiphysics simulations. Q3D is employed to evaluate the parasitic inductance and resistance in the module, showing that parasitic inductance is lower than 1.5nH in the design. The extracted parasitics is imported in spice circuit model, simulation results show limited ringing during switching transients. Thermal simulations are employed to compare junction temperature of power modules with DBC subtrates and flexible substrates, then to evaluate the thermal performance of the designed PSiP SiC model with stacked dies. It shows that junction temperature of designed IPM is higher than regular module at same condition. The paper also provides guideline for optimized heat sink design to lower junction temperature of the SiC IPM. Mechanical simulations are employed to evaluate the pre-stress induced in modules with DBC substrate and flexible dielectric substrate, and proves that mechanical stress induced by reflowing process can be reduced significantly by using ultra-thin flexible dielectric as substrate.
Direct Aerosol Printing of Lithium-ion Batteries
Authors: Yu Xiaowei , Chen I-Meng , Sarkar Susmita , Park Jonghyun , Pan Heng , Liu Yangtao , Wang Yan , Everhart Wesley
Published: November 2017

Recently, additive manufacturing (AM) has brought new opportunities to the manufacturing of lithium-ion batteries (LIBs). In this study, aerosol jet printing, as a branch of AM technologies was demonstrated to fabricate lithium-ion batteries for the first time. Printable inks of two pairs of active materials for cathode and anode were developed. The effect of ink composition on the printing characteristics was studied. The developed inks were printed into Li-ion battery electrodes with specific capacities comparable to conventional slurry cast electrodes. Next, to demonstrate fully-printed electrodes, gold and copper inks were printed on top of polymer substrates and thermal/flash sintered as the current collectors for cathode and anode.
Direct sapphire to ceramic bonding for CMOS image sensor packaging using room temperature bonding technology
Authors: Lundén H. , Määttänen A. , Murphy L.
Published: November 2017

The aim of the study was to evaluate the use of a novel bonding technology to create a sapphire-ceramic package for CMOS image sensor devices. The package must be robust enough to be used in space flight applications: it must protect the device from external environmental conditions during testing, storage and use. A series of tests were executed to ensure the package quality. The package needs to be radiation-tolerant to ensure reliability of data in high radiation environments, such as in space. Package hermeticity is an important reliability requirement not only in space but also in other applications such as medical implants, military, nuclear inspection and telecoms.

It was proved that novel bonding technique enables direct sapphire to ceramic bonding: robust packages were manufactured. A significant improvement in moisture levels was observed compared to (typically)epoxy sealed packages: detected moisture levels were of only one tenth of what is commonly seen in the stressed image sensor packages. Environmental changes had no influence on the package & device functionality or quality.
Thick Film Materials for High Power Hybrid Circuits on Aluminum Nitride
Authors: Sgriccia Matt , Sandoval Frank , Persons Ryan
Published: November 2017

For over 40 years, the substrate of choice for designing and fabricating traditional hybrid circuits has been alumina. It has provided the required mechanical strength, electrical resistivity, and thermal performance needed for proper circuit operation. Over the past several years however, we have experienced a shift in hybrid technology towards electronic devices with highly complex, dense circuit configurations that produce more power and consequently, more heat than previous designs. This requires the use of a substrate with a higher thermal conductivity to properly manage the heat transfer and dissipation in order to maintain optimum performance and functionality of the end device. The thermal properties displayed by aluminum nitride provide design engineers with a reliable alternative to traditional alumina.

While creating new and exciting possibilities, the use of aluminum nitride also creates a different set of challenges for thick film suppliers and circuit fabricators. Due to the thermal expansion mismatch, as well as the chemical changes that occur to the substrate which affect adhesion during the firing process, thick film pastes previously suitable for alumina are typically not compatible with aluminum nitride. To overcome this challenge and the performance demands of high power, high reliability circuit applications, a new line of RoHS and REACH compliant thick film pastes has been developed. The following conductors are available: silver, silver/palladium, silver/platinum, copper, and gold. In addition, we have developed two resistor pastes and a compatible overglaze. This paper will discuss the aforementioned thick films and their critical performance properties before and after reliability testing. This includes adhesion for the conductors, resistance and TCR for the resistors.
High Temperature Storage Reliability of Bond Resistance of Palladium-Coated Copper Ball Bonds
Authors: Hook Michael David , Mayer Michael , Hunter Stevan
Published: November 2017

Reliability of wire bonds made with palladium-coated copper (PCC) wire of 25 μm diameter is studied by measuring the wire bond resistance increase over time in high temperature storage at 225 °C. Ball bonds are made on two bond pad thicknesses and tested with and without mold compound encapsulation. Bond pads are aluminum copper (Al-0.5%Cu), 800 nm and 3000 nm thick. The wirebonding pattern is arranged to facilitate 4-wire resistance measurements of 12 bond pairs in each 28-pin ceramic test package. The ball bonding recipe is optimized to minimize splash on 3000 nm Al-0.5%Cu with shear strength at least 120 MPa. Ball bond diameter is 61 μm and height is 14 μm. Measurements include bond shear test data and in-situ resistance before and during high temperature storage. Bonds on 3000 nm pads are found to be significantly more reliable than bonds on 800 nm pads within 140 h of aging.
Aluminum Wedge-Wedge Bonding Using Capillary and Ball Bonder
Authors: Murali Sarangapani , Theint Ei Phyu Phyu , Fitri Hamdan Faizul , Tiong Tan Kean , Xi Zhang
Published: November 2017

The paper discusses on the bondability and reliability of aluminum (Al) wedge-to-wedge bonding using fine ceramic capillary and ball bonder. Initial trials revealed aluminum build-up and poor capillary life with touch down of 20K or less. Optimizing the process parameters, switching on air-scrub, reducing shape angle to 20° instead of usual 35° and using Al-1wt%Si wire processed with refined grains revealed better capillary life with touch down of 200K without surface burrs. The method is capable of bonding complex looping and sharp acute bends. The data comprising of 1st and 2nd wedge dimensions, wedge pull, wedge shear and fracture mode for 20μm and 50μm Al-1wt%Si wires are presented. High temperature storage of aluminum wedge bonding to different substrate surfaces such as Al-0.5wt%Cu metallization, bare copper and gold plating revealed stable bond. From the wedge pull and tensile data, floor and shelf life of the wire is recommended to be 7days and 6months respectively. Evaluation of gold, copper and silver base bonding wires by this method showed feasible to bond and needs detailed studies to practice. The fusing current of Al-1wt%Si wire for varying diameter from 0.6 to 3mil and wire length from 1 to 20mm are also stated.
Glass Solutions for Packaging and IoT
Authors: Lu Rachel , Shorey Aric
Published: November 2017

The interest in glass as a semiconductor packaging material has continually grown over the past several years. Glass, and its material properties, provides many opportunities for application in advanced packaging. As an insulator, glass is well-suited due to its low electrical loss, particularly at high frequencies. The relatively high stiffness and ability to adjust coefficient of thermal expansion gives the opportunity to better manage warp in glass core substrates as well as bonded stacks, either in carrier or interposer applications. Forming processes allow the potential to both manufacture in a panel format as well as at thicknesses as low as 100 um. Both of these give real opportunity to provide cost-effective packaging solutions. Via fabrication technology development continues to advance providing via diameters < 20 um in size in a production ready environment.

As the industry adopts glass solutions, significant advancements have been made in downstream processes such as glass handling and both via and surface metallization. Additionally, data showing the ability to achieve electrical and thermo-mechanical reliability is readily available. Here we provide the latest data on reliability and new product applications for glass-based solutions.
OPTIMIZATION OF CHEMISTRY FOR A VAPOUR PHASE PROCESS TO DEFLUX NO CLEAN LEAD FREE MATERIALS ON PCBS
Authors: Duchi Patrick J. , Cetier Jonathan , Levasseur Laurent , Coquio Jaquemine , Aguilar Rodrigo
Published: November 2017

The cleaning action to remove baked-on solder flux residues after reflow, also known as defluxing, from printed circuit boards has become more and more challenged because of the higher densities in today's electronics, miniaturization, lower stand off components, and complex geometries where the packaging has evolved from 2D to 3D. This situation becomes even more difficult in No Clean lead free assembly where higher process temperatures are applied causing charring to flux residues. In addition, traditional chemicals like CFC's, HCFC's, brominated solvents, detergents and glycols cannot longer do a good cleaning job anymore because most flux formulations have changed.

An hydrocarbon solvent used as co-solvent in vapour phase application has been re-formulated under three main criterias: environmental legislations, toxicity, and defluxing performance The results from the laboratory stage have been applied to clean the fluxes of three No Clean lead free solder pastes used in mass production of printed circuit boards assemblies with high densities interconnections and exposed to harsh environmental conditions.
UV-Vis Spectrophotometrical and Analytical Methodology for the Determination of Singlet Oxygen in New Antibacterials Drugs
Authors: Zoltan Tamara , Vargas Franklin , Izzo Carla
Published: November 2017

We have determined and quantified spectrophotometrically the capacity of producing reactive oxygen species (ROS) as 1O2 during the photolysis with UV-A light of 5 new synthesized naphthyl ester derivates of well-known quinolone antibacterials (nalidixic acid (1), cinoxacin (2), norfloxacin (3), ciprofloxacin (4) and enoxacin (5)). The ability of the naphthyl ester derivatives (6-10) to generate singlet oxygen were detecting and for the first time quantified by the histidine assay, a sensitive, fast and inexpensive method. The following tendency of generation of singlet oxygen was observed: compounds 7 >10 > 6 > 8 > 9 >> parent drugs 1-5.