bluuebunny/crossref_metadata_2025 huggingface dataset:
Hermetic Packaging of Micro Scanner for Laser Display Applications
Authors: Choi Won Kyoung , Cho Moon Gi , Seo Sun Kyoung , Lee Hyuck Mo , Jeong Byung Gil , Lee Hwa-Sun , Ko Young-Chul , Lee Jin-Ho , Moon Chang Youl
Published: April 2009

Laser display technologies have been developed for an excellent expression of natural color, low power consumption and a long lifetime compared to other advanced displays, such as LCD, PDP and other projection type displays. The micro scanner is one of the key devices to make possible the raster scanning type laser projection displays. And the hermetic package of the micro scanner should be required for the protection from the environmental variations so as to keep the driving behavior uniform. Hermetic package can be ensured when the package is sealed hermetically without generating any outgases in the cavity. Thus, the hermetic sealing process was optimized through DOE (Design of Experiment) method using the Sn-In-Ag solder alloys instead of adhesives. And the characterizations of the packages were carried out in terms of hermeticity, shear strength, and interface microstructures. As a result, we’ve got about 2E−9 atm cc/sec He leak rate, which is low enough to pass the standard (MIL-STD-883E). Shear strength was as high as ∼80 MPa. The C-mode SAM images showed the continuous sealing area without any voids. In addition, the interfacial microstructures revealed good adhesion to the both parts, the glass lid and the ceramic package.
Deformation and Fatigue Fracture of Pb-Free Solder Alloys Under Complicated Load Conditions
Authors: Liang J. , Dariavach N. , Callahan P. , Shangguan D. , Li X.
Published: April 2009

Fundamental study of deformation and fatigue fracture behavior of solder alloys under complex load conditions is a key to enabling implementation of sophisticated 3-D time-dependent nonlinear FEM stress and strain analyses and life assessment for electronic packages and assemblies. In this study, the rate-dependent deformation and fatigue fracture behavior of Sn3.8Ag0.7Cu Pb-free alloy and Sn-Pb eutectic alloy was investigated with thin-walled specimens using a bi-axial servo-controlled tension-torsion material testing system, with solder alloys subjected to a variety of complex load conditions: pure shearing at strain rates between 6.7×10−7 /sec to 1.3×10−1 /sec, creep at temperatures ranging from room temperature up to 125 °C, and cyclic loading with frequency of 0.001Hz to 3Hz. Bi-axial stress conditions were imposed for shearing tests to investigate effects of multi-axial stresses on deformation behavior. The effects of frequency and temperature on cyclic deformation and fatigue facture were investigated for lead-free Sn3.8Ag0.7Cu and Sn-Pb eutectic solder. Fractography of fatigue tested samples were also conducted to determine possible fatigue failure mechanisms.
Hierarchical Modeling and Trade-Off Studies in Design of Thermal Interface Materials
Authors: Zhang X. , Kanuparthi S. , Subbarayan G. , Sammakia B. , Tonapi S.
Published: April 2009

Particle laden polymer composites are widely used as thermal interface materials in the electronics cooling industry. The projected small chip-sizes and high power applications in the near future demand higher values of effective thermal conductivity of the thermal interface materials (TIMs) used between the chip and the heat-spreader and the heat-spreader and heat-sink. However, over two decades of research has not yielded materials with significantly improved effective thermal conductivities. A critical need in developing these TIMs is apriori modeling using fundamental physical principles to predict the effect of particle volume fraction and arrangements on effective behavior. Such a model will enable one to optimize the structure and arrangement of the material. The existing analytical descriptions of thermal transport in particulate systems under predict (as compared to the experimentally observed values) the effective thermal conductivity since these models do not accurately account for the effect of inter-particle interactions, especially when particle volume fractions approach the percolation limits of approximately 60%. Most existing theories are observed to be accurate when filler material volume fractions are less than 30–35%. In this paper, we present a hierarchical, meshless, computational procedure for creating complex microstructures, explicitly analyzing their effective thermal behavior, and mathematically optimizing particle sizes and arrangements. A newly developed object-oriented symbolic, java language framework termed jNURBS implementing the developed procedure is used to generate and analyze representative random microstructures of the TIMs.
Advanced Technology for Server Cooling
Authors: Webb Ralph L. , Nasir Hasan
Published: April 2009

This paper reports work on advanced cooling technology for servers. The air cooling load on the rack may be enhanced using highly compact Copper/Brass “flat tube” water-cooled heat exchangers that are integrated into the rack frame. The cooling water is supplied by a water chiller. Analysis shows that it is possible to provide cooling (UA/Afr) in the range of 670–1000 W/m2-K, where the m2 is the core frontal area. Also analyzed and compared are advanced technology CPU heat sinks — a thermo-syphon concept and a liquid micro-channel heat sink. The thermo-syphon may be used in a compact thermal-bus concept for heat removal from multiple CPUs. Used with boiling on an enhanced copper boiling surface in a thermo-syphon, heat loads in excess of 75 W/m2-K are possible. The heat removed at each CPU in the chassis is rejected to water flow in a compact water cooled condenser. Performance results of the thermo-syphon concept are predicted, obstacles associated with increasing performance are discussed, and possible solutions are proposed. Performance predictions were also made for water cooled: (1) Copper micro-channels as an attached external sink and (2) Silicon micro-channels integral to the silicon CPU die. It is shown that micro-channels integrated into the silicon die do not offer significant advantage over copper micro-channels.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
Electronic Board/System Nonlinearity Characterization for Dynamic Analysis
Authors: Liang Frank Z. , Hezeltine Wade , Williams Richard L.
Published: April 2009

Many electronic boards or systems exhibit nonlinear behaviors during shock or vibration tests. One of the challenges for dynamics analysis of electronic boards or systems is to deal with these nonlinearities. In order to solve the nonlinear problem, the nonlinearities need to be revealed and characterized and their effects understood. This paper demonstrates the methods in identifying the nonlinearities and supported with empirical tests. Shock, random vibration and static bending were used to reveal the board system nonlinearities. The empirical results provided direction to update shock FE models.
Realization of Ultra-Wideband, High-Resolution TDR for Chip-Carrier Packages
Authors: Han Dong-Ho , Xu Bao-Shu , Choi Myoung J. , He Jiangqi , Gardiner Scott , Lee Cliff
Published: April 2009

In this paper, a state of the art TDR with a rise time of 9ps was employed in the characterization of multi-layer ball-grid array (BGA) or land-grid array (LGA) packages. The hardware used for 9ps rising time was the Picosecond Pulse Lab’s 4022 Source Enhancement Module that reduces a standard TDR rise time of 35–40ps to 9ps. The high-resolution TDR can clearly indicates a root cause of a multi-layer package signal integrity problem (impedance mismatching) in vertical transitions consisting of vias and planes which cannot be observed with a conventional TDR. In addition, due to its high-resolution, it was observed that the size of characteristic impedance testing transmission lines can be significantly scaled down. For example, a minimum length of 15–20 mm long transmission lines with a standard TDR can be reduced down to 3–4mm long for 9ps TDR. Using the TDR waveforms, reflection loss S11 (dB) was computed using direct convolution method and short-open-load (SOL) calibration method. The resulting (TDR generated) S11 agrees excellently with direct vector network analyzer (VNA) measurements up to 50 GHz which is the highest frequency available with Agilent 8364A.
Fabrication of Sub-Micron Silicon Vias by Deep Reactive Ion Etching
Authors: Zhang Shawn X. D. , Hon Ronald , Lee S. W. Ricky
Published: April 2009

Deep reactive ion etching (DRIE) is a major microfabrication process for micro-electro-mechanical system (MEMS) devices. In recent years DRIE is also applied to make through-silicon-vias (TSVs) for 3D packaging. Typical DRIE-formed TSVs are in the range of a few microns to tens of microns. In the present study, silicon vias with diameters in the sub-micron range (0.5 μm and 0.8 μm) are attempted. For comparison purposes, larger silicon vias (1 μm and 3 μm) are fabricated as well. In this paper, the microfabrication processes are described. The experimental results and comparisons in terms of via uniformity, aspect ratio dependent etching, undercutting, and effects of various mask materials are discussed in detail.
Characterization of Novolac Based Photoresists to Fabricate 3D Polymer Dome Features
Authors: Muthukumar Sriram , Miller Tom W. , Pathangey Balu , Patel Neha M. , Hill Charles D.
Published: April 2009

Wafer level, 3D, free standing structures (e.g., domes or hemi-cylinders) can be fabricated using polymer dome features as sacrificial templates for MEMS and interconnect applications. Understanding the kinetics of dome formation and the material properties are essential for a robust and manufacturable process of controlling the size and shape of the photoresist features. In this paper, temporal and thermal characteristics of Novolac based photoresists are presented as a function of solid loading and solvent type using analytical techniques such as Thermogravimetric Analysis (TGA), Fourier Transform Infrared (FTIR) spectroscopy, hot stage microscopy, and Gas Chromatography/ Mass Spectrometry (GC/MS). The solid loading influences the thickness and processing ability of the resist. The solvent evaporation rate controls the final size and shape of the 3D polymer dome features. Solvent is the primary material lost during the dome formation and the onset of deformation is dependent on temperature and ramp rate.
Use of Array Capacitors to Improve the Power Delivery Performance of a Microprocessor System
Authors: Eilert Kimberly D. , Radhakrishnan Kaladhar , Hill Michael J. , Aygu¨n Kemal
Published: April 2009

We show system modeling and measurement results of a platform with array capacitor solution (ACS) within the frequency domain. A Pentium® 4 microprocessor package was redesigned for a single array capacitor, in place of all multiterminal capacitors. Its system power delivery impedance profile was found to have a more desirable high frequency response than the earlier system designed with discrete multiterminal capacitors. These measured results were also found to agree well with the behavior predicted by simulation models. Additionally we explore the impact and optimization of array capacitor parameters on the overall system frequency response.
Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects
Authors: Thacker Hiren , Ogunsola Oluwafemi , Bakir Muhannad , Meindl James
Published: April 2009

The bandwidth provided by optical interconnects makes them an attractive solution for chip-to-package and chip-to-chip communications. In such systems, chips will have optical I/O interconnects fabricated alongside their conventional electrical counterparts. Virtually no work has been previously reported relating to the testing of such chips at the wafer-level. The requirements for probe hardware needed to achieve this are identified, and probe module configurations based on these requirements are presented. A high-density micro-opto-electro-mechanical-systems (MOEMS)-based probe substrate prototype for interfacing with chips having electrical and optical polymer pillar-based I/Os has been designed, and built using microfabrication techniques. Successful probing of an array of polymer pillar-based optical I/Os is reported.
Accelerated Convergence for Lumped-Elements Based on-Package RF Passives Design by Using Curve Fitted Formula
Authors: Zeng Xiangyin , He Jiangqi , Xu Baoshu
Published: April 2009

Integrating passive components on package is getting more and more attractive. To speed up the lumped-elements-based RF functional blocks, like filters, matching networks and so on, fast synthesis of these lumped elements is necessary. Traditional synthesis method like try-error-try again is not only time consuming but also hard to find an optimal one. This is especially true for spiral inductor design due to many tunable parameters. Design based on library has also some disadvantages, such as lack of information of manufacture tolerances’ impact. This paper describes an optimal synthesis method based on curve fitted formula. Full wave electromagnetic simulator is first used to model a set of typical structures. Curve fitting technique is then used to express capacitance, inductance, Q-factor, SRF as functions of geometric parameters and frequency, which is then integrated in a software tool for package inductor and capacitor design. With these fitted curves, manufacture tolerance analysis becomes very easier, and one can easily find the optimal design for the real application, therefore speeds up the function block design.
Thermal Management of Fujitsu High-End Unix Servers
Authors: Wei Jie , Suzuki Masahiro
Published: April 2009

An overview of system packaging and thermal management of the Fujitsu high-performance Unix server PRIMEPOWER HPC2500 is introduced in the present paper. Each node of the HPC2500 comprises sixteen system boards containing up to 128 SPARC64V CPU processors, with the maximum power dissipation about 30kW. A full configuration of the HPC2500 can be further scaled up to the maximum of 128 nodes, resulting in 16,384 CPU processors installed. Thermal management is introduced from viewpoints of the server-cabinet, system-board and CPU processor module levels, respectively. A design strategy of the forced convection air cooling scheme is outlined, implemented to meet increased demanding requirements of high density packaging, high power and power-density dissipations. Furthermore, thermal challenges, arising from high asymmetric power distributions and dissipations of CPU processors, are investigated for high performance computers. Temperature distributions of the CPU processors, effects of heat spreading materials (HIS) and impacts of thermal interface materials (TIM) on the cooling and packaging designs are also analysed and illustrated.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
Embedded RF Filters for WLAN and Bluetooth Applications
Authors: Kamgaing Telesphor , He Jiangqi , Hsu Rockwell
Published: April 2009

This paper discusses the design and integration of RF filters in multilayer organic substrate. Using a methodic approach, several low-pass and band-pass filters have been designed, fabricated and fully characterized. The electrical analysis clearly indicates, which of the low-pass filters is less susceptible to process variations and therefore more appropriate for high volume manufacturing. It is shown that these filters provide electrical performance similar to their commercially available ceramic counterparts while using relatively smaller real estate. All filters are fabricated in the innermost layers of a multilayer organic package substrate with embedded passives capability.
An Overview of System in Package (SiP) Applications and Technologies for CPU and Communications Systems
Authors: Polka Lesley , Mahajan Ravi , Swan Johanna , Choksi Gaurang
Published: April 2009

Research and development on System in Package (SiP) technologies is prevalent now both in industry and academia. This paper provides an overview of SiP from a CPU and communications systems perspective. Some of the items that will be covered include what defines a “system” for SiP, what value a SiP architecture brings, the types of SiP packaging architectures and technologies, and the challenges involved with developing SiP solutions.
Self-Assembly for Three Dimensional Integration of Functional Electrical Components
Authors: Cannon Andrew H. , Hua Yueming , Henderson Clifford L. , King William P.
Published: April 2009

Current microelectronics manufacturing and packaging rely on pick-and-place methods, a serial manufacturing process. Self-Assembly (SA) is a parallel manufacturing process that can be three dimensional and as such could improve the manufacture of systems that require diverse integration of sensors, actuators, electronics, and power sources. This paper describes SA of millimeter-scale parts in which functional electronic components and electrical interconnects were cast into 5 mm cubes of Polymethylmethacrylate (PMMA). Surface forces induced both gross and fine alignment of the cubes. The cubes were bonded using low-melting temperature solder (47°C), resulting in a self-assembled three dimensional circuit. This technique could be expanded for assembly of systems having more than 104 components. The ultimate goal is to combine a large number of diverse active components to allow the manufacture of systems having dense integrated functionality.
Chip Scale Package for Image Sensor Device
Authors: Chao Yung-Ching , Liu John , Lee Yao-Jung , Liu De-Shin , Wang Jeff , Chen Ching-Yang , Huang Sam , Lu Alex
Published: April 2009

Chip on glass (COG) and chip on film (COF) package solutions for image sensor are introduced in this study. These packaging solutions are based on high precision, high reliability bumping and flip chip bonding technologies. To apply connection bumps on image sensor wafer, three bumping technologies are investigated; including gold stud bumps, electroless bumps and electroplated bumps. The issue of bumping technology on image sensor device is how to prevent damages and contaminations on microlens and sensing area. As a result, a series of well-controlled sputtering and stripping electroplated bumping process is developed and verified. The verified electroplated bumping process is also applied to produce RDL trace on 8” optical glass wafer. The gold stud bump is also an alternative low cost solution for image sensor package. The NCP and flip chip bonding technologies are used to bond the chip onto optical glass substrate and polyimide film. The lower processing temperature could ensure the microlens and color filter on image sensor will not be damaged during the assembly process. An innovative concept of image sensor with metal sealing ring is also investigated. The metal sealing ring could provide higher reliability and easy assembly process to reduce the risk of adhesive overflow to image sensing area. The reliability testing result show COG/COF image packages are low cost and high image quality solutions.
Tactile Temperature Analysis of Home Theater System
Authors: Ryu Ho Chul , Dan Byung Ju , Choi In Ho , Kim Jin Yong
Published: April 2009

In this work, the tactile temperature of home theater systems under natural convection conditions has been investigated through numerical approaches and experiment. The CFD analysis method was used to observe temperature changes of both the case top and the heat source. Based on numerical simulation results, four types of steel sheet mock-up having different vent sizes and locations were tested. As a consequence of the experiments, relationships in temperature variation between the case top and the heat source were investigated and verified. In addition, by using the validated and improved vent system, a fanless home theater system was proposed under high heat dissipating heat sources.
High Precision Young’s Modulus Extraction of Thin Films Through Measuring the Electric-Circuit Behavior of Microstructures
Authors: Hu Yuh-Chung , Gau Wei-Hsin , Tu Wei-Hsiang
Published: April 2009

This paper is aimed at developing a high precision algorithm for extracting the Young’s modulus of thin films through the capacitance-voltage measurement of microstructures at wafer level. Two flat micro cantilever beams made of single crystalline silicon are demonstrated. The average value of extracted Young’s modulus in (110) crystalline plane by the present methodology is about 169 GPa, compared to the well-defined value of 168 GPa, the error percentage is within 1% and the high precision and repeatability of the present methodology are verified. Since the driving and measuring signals of the present methodology are both electric, they could be accomplished using existing semiconductor testing equipments through probing on the bonding pads of devices. Because hardware replacement could be avoided, the present methodology shows substantial advantage over other property-extraction methods for large-scale implementation in semiconductor or MEMS fabs.
Determination of the Anand Viscoplasticity Model Constants for SnAgCu
Authors: Rodgers Bryan , Flood Ben , Punch Jeff , Waldron Finbarr
Published: April 2009

The major focus of this work was the determination of the nine constants required for Anand’s viscoplastic constitutive model for a lead-free solder alloy, 95.5Sn3.8Ag0.7Cu and to compare them with those for SnPb. The test specimen was a cast dog bone shape based on ASTM E 8M-01, with a diameter of 4mm and a gauge length of 20mm. A series of tensile experiments were carried out: constant displacement tests ranging from 6.5 × 10−5/s to 1.0 × 10−3/s at temperatures of 20°C, 75°C, and 125°C; constant load tests at a range of loads from 10MPa to 65MPa, also at temperatures of 20°C, 75°C, and 125°C. A series of non-linear fitting processes was used to determine the model constants. Comparisons were then made with experimental measurements of the stress-plastic strain curves from constant displacement rate tests: it was found that the model matched the experimental data at low strain rates but did not capture the strain hardening effect, especially at high strain rates. A finite element model of the test was also constructed using ANSYS software. This software includes the Anand model as an option for its range of viscoplastic elements, requiring that the nine constants be input. In this case, an 8-noded axisymmetric element (VISCO108) was used to model the test specimen under constant displacement rate loading. The model was then used to predict the stress-plastic strain curve and this was compared to both the experimental measurements and the fitted Anand model. Reasonable agreement was found between the Anand model and the FE predictions at small strain rates. Finally, a BGA device was simulated under accelerated temperature cycling conditions using ANSYS with the fitted Anand for the SnAgCu solder joints. A Morrow-type fatigue life model was applied using empirical constants from two published sources and good agreement was found between experiment and predicted fatigue life.
Mechanical Design and Analysis of Land Grid Array (LGA) Sockets
Authors: Pandey Vinayak , Subramanian Sankara , Rangaraj Sudarshan , Byquist Tod
Published: April 2009

Sockets offer a cost effective and high-volume manufacturing friendly interface between CPU packages and motherboards. Land-grid-array (LGA) technology offers avenues to enhance the electrical performance of sockets over its predecessors e.g. pin grid array (PGA) technology. The present paper will describe various technical challenges encountered in the design of Intel’s LGA sockets. The recently launched LGA775 socket will be used as a case study. Methods adopted to overcome these design challenges and successfully implement LGA sockets will be discussed. Design features like direct socket loading (DSL), various issues related to the design of socket housings, LGA contact design optimization and socket reliability enhancement under stresses such as thermal cycling, mechanical shock, vibration and bake will be discussed. DSL is an integrated mechanism that enables application of a compressive mechanical load between the LGA contact pins on the socket and the package LGA pads, so that their interfaces achieve and maintain electrical continuity through the socket design life. Similarly, optimizing the design of the socket contacts significantly impacts the stressing, reliability of the second level interconnect (SLI) ball grid array (BGA) that connects the LGA775 to the motherboard. The successful implementation of these designs is achieved through a combination of geometric tolerance stack analysis, numerical modeling studies, detailed experiments, reliability testing and correlation between these. The details of the same are be discussed in this article.
Thermal Characterization of Dual-Core Processor in Computer Equipment
Authors: Nagulapally Manoj , Refai-Ahmed Gamal
Published: April 2009

A methodology to automatically construct both the topology and characteristics of a compact network model for a dual-core package is presented. The method is based on the multi-grid agglomeration of the underlying mesh used in the finite volume discretization of the energy conservation equation for the package. The procedure starts with a detailed mesh, either structured or unstructured, of the package and utilizes the physics contained in the underlying finite volume discretization to deduce network connectivities and resistances. In the study report herein, the method is applied to a dual-core package. This package is characterized using the above methodology and then used in steady-state CFD simulations. In these simulations, the package is mounted on a four-layer JEDEC thermal test board inside a JEDEC characterization chamber and subjected to a number of boundary conditions. The simulation results using the network model are compared to the corresponding detailed package simulations.
A Simulated and Experimental Comparison of Lead-Free and Tin-Lead Solder Interconnect Failure Under Impact Stimuli
Authors: Heaslip Greg , Punch Jeff , Rogers Bryan , Ryan Claire , Reid Michael
Published: April 2009

There is considerable reported evidence that a large percentage of failures which afflict portable electronic products are due to impact or shock during use. Failures of the external housing, internal electronic components, package-to-board interconnects, and liquid crystal display panels may occur as the result of accidental drops. Moreover, the introduction of lead-free solder to the electronics industry will bring additional design implications for future generations of mobile electronic systems. In this paper, drop tests performed on PCBs populated with ball grid arrays (BGAs) are reported. During testing, measurements from strain gages were recorded using a high-speed data acquisition system. Electrical continuity through each package was monitored during the impact event in order to detect failure of package-to-board interconnects. Life distributions were established for both a lead-free and a tin-lead solder for various drop heights. In addition, failure analysis was carried out using microsection techniques, scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS). Resistance measurements throughout the drop event indicated that different failure mechanisms occurred for different drop heights. The explicit finite element (FE) method was employed to evaluate the peel stress at the critical solder joint and a stress-life model is then established for the lead-free solder. The maximum peel stress location was found to match the location of failure initiation revealed from the failure analysis. It was also discovered that, for board level drop testing, that there is a considerable difference between the lead-free solder characteristic life and the tin-lead solder characteristic life.
Moisture Effects on the Reliability of Anisotropic Conductive Film Interconnection for Flip Chip on Flex Applications
Authors: Yin Chunyan , Lu Hua , Bailey Chris , Chan Yan-Cheong
Published: April 2009

Anisotropic conductive film (ACF) which consists of an adhesive epoxy matrix and randomly distributed conductive particles are widely used as the connection material for electronic devices with high I/O counts. However, for the semiconductor industry the reliability of the ACF is still a major concern due to a lack of experimental reliability data. This paper reports the investigations into the moisture-induced failures in Flip-Chip-on-Flex interconnections with Anisotropic Conductive Films (ACFs). Both experimental and modeling methods were applied. In the experiments, the contact resistance was used as a quality indicator and was measured continuously during the accelerated tests (autoclave tests). The temperature, relative humidity and the pressure were set at 121°C, 100%RH, and 2atm respectively. The contact resistance of the ACF joints increased during the tests and nearly 25% of the joints were found to be open after 168 hours’ testing time. Visible conduction gaps between the adhesive and substrate pads were observed. Cracks at the adhesive/flex interface were also found. For a better understanding of the experimental results, 3-D Finite Element (FE) models were built and a macro-micro modeling method was used to determine the moisture diffusion and moisture-induced stresses inside the ACF joints. Modeling results are consistent with the findings in the experimental work.
Thermal Simulation Benchmark of Graphic Module Under Installed, Operating Conditions
Authors: Forghan Fariborz , Kowalski Gregory J. , Zenouzi Mansour , Metghalchi Hameed
Published: April 2009

The thermal performance of a graphic module on graphic card is theoretically and experimentally investigated. Unlike prior benchmark studies, this study involves a practical electronic device operating in a real software environment. The temperatures at five locations on the module and at one point on the board are measured as a function of time during the operation of a series of computer games. The theoretical model is developed using Flotherm to simulate the transient thermal response. There is close agreement from 3% to 10% between the numerical steady state case prediction and test data. The calculated transient trends using Flotherm model closely agree with experimental results and demonstrate the rapid increase in temperature as the number of module operations increases during the games. The results for the maximum temperature are directly linked to the software operation and exhibit a superposition type behavior in which the observed maximum operating temperature can exceed that estimated by steady state conditions. As expected, the results demonstrate that a carefully constructed thermal simulation can accurately predict the thermal response of a module under actual operating conditions.
Future Direction and Challenges for Microelectronics Packaging Materials
Authors: Wakharkar Vijay , Matayabas J. C.
Published: April 2009

The continual increasing performance of microelectronics products places a high demand on packaging technologies. This presentation will discuss the current environment, challenges, and technologies being pursued. Package technology migrations for microprocessors and communication products are described. Material needs for high thermal dissipation, high-speed signaling, and high-density interconnects are discussed. Microprocessor scaling for increased performance and reduced cost places significant challenges on power delivery and power removal due to reducing dimensions, operating voltages, and increasing power. Meeting these challenges indicates a need for advanced packaging solutions using advanced materials. New methodologies, metrologies, and materials/process technologies to address these challenges are also highlighted.
Airflow Uniformity Through Perforated Tiles in a Raised-Floor Data Center
Authors: VanGilder James W. , Schmidt Roger R.
Published: April 2009

The maximum equipment power density (e.g. in power/rack or power/area) that may be deployed in a typical raised-floor data center is limited by perforated tile airflow. In the design of a data center cooling system, a simple estimate of mean airflow per perforated tile is typically made based on the number of CRAC’s and number of perforated tiles (and possibly a leakage airflow estimate). However, in practice, many perforated tiles may deliver substantially more or less than the mean, resulting in, at best, inefficiencies and, at worst, equipment failure due to inadequate cooling. Consequently, the data center designer needs to estimate the magnitude of variations in perforated tile airflow prior to construction or renovation. In this paper, over 240 CFD models are analyzed to determine the impact of data-center design parameters on perforated tile airflow uniformity. The CFD models are based on actual data center floor plans and the CFD model is verified by comparison to experimental test data. Perforated tile type and the presence of plenum obstructions have the greatest potential influence on airflow uniformity. Floor plan, plenum depth, and airflow leakage rate have modest effect on uniformity and total airflow rate (or average plenum pressure) has virtually no effect. Good uniformity may be realized by using more restrictive (e.g. 25%-open) perforated tiles, minimizing obstructions and leakage airflow, using deeper plenums, and using rectangular floor plans with standard hot aisle/cold aisle arrangements.
Effect of Data Center Layout on Rack Inlet Air Temperatures
Authors: Schmidt Roger , Iyengar Madhusudan
Published: April 2009

The heat dissipated by large servers and switching equipment is reaching levels that make it very difficult to cool these systems in data centers or telecommunications rooms. Some of the highest powered systems are dissipating upwards of 4000 watts/ft2(43,000 watts/m2) based on the equipment footprint. When systems dissipate this amount of heat and then are clustered together within a data center significant cooling challenges can result. This paper describes the thermal profile of 3 data center layouts (2 are of the same data center but different points in time with a different layout). Detailed measurements of all three were taken: electronic equipment power usage; perforated floor tile airflow; cable cutout airflow; computer room air conditioning (CRAC) airflow, temperatures and power usage; electronic equipment inlet air temperatures. Although the detailed measurements were recorded this paper will focus at the macro level results of the data center to see if some patterns present themselves that might be helpful for future guidelines of data center layout for optimized cooling. Specifically, areas of the data center where racks have similar inlet air temperatures are examined relative to the rack and CRAC unit layout.
Exploring the Possibility of Approximating Viscoelastic Response of Underfill Materials Through the Use of Appropriate Linear-Elastic Material Models
Authors: Ganapathysubramanian Shankar , Sane Sandeep , Dimagiba Richard Raymond , Chandran Biju I.
Published: April 2009

Viscoelastic analysis for numerical modeling of IC assembly processes are generally non-linear and require extensive time and computational resources when compared to a linear elastic analysis. Experimental identification/approximation of the viscoelastic properties (in terms of the Prony series) of any polymeric material is also an exhaustive effort. These drawbacks in experimental procedures and modeling activities have forced us to explore the possibility of approximating viscoelastic response of a polymer with an appropriate linear-elastic model. This paper discusses the impact of different approximation methodologies for a viscoelastic material most commonly used in electronic packaging — the underfill material in flip-chip technology. The modeling methodologies discussed here include the use of long term modulus, short term modulus and other “effective” stiffness measures to approximate the response of underfills during assembly processes. The package response, from each of these models, has been compared to the package response from a linear viscoelastic analysis assuming underfill materials to behave as Maxwell solids. It has been observed that the short term modulus consistently over predicts the ILD (interlayer dielectric in the silicon backend) peel stress for various underfill materials. In addition, the paper also explores the existence of an “effective” stiffness that can be used in lieu of a full fledged viscoelastic analysis. The ability to estimate this “effective” stiffness using available temperature dependent modulus data (from DMA tests) is also discussed. The applicability of this effective metric to different underfill materials has also been explored. In conclusion, this study highlights the need for accurate characterization of polymeric materials so that numerical predictions can provide realistic risk assessments for future packaging technologies.
Comparison of Different Single-Phase Liquid Jet Impingement Cooling Configurations in the Context of Thermal Management in Power Electronics
Authors: Narumanchi Sreekant V. J. , Bharathan Desikan , Hassani Vahab
Published: April 2009

Jet impingement has been an attractive cooling option in a number of industries over the past few decades. Over the past fifteen years, jet impingement has been explored as a cooling option in microelectronics. Recently, interest has also been expressed by the automotive industry in exploring jet impingement as an option for cooling power electronics components. The main purpose of this paper is to compare the different single-phase jet impingement configurations, which have been reported in the literature, primarily from a heat transfer viewpoint. The discussion is also from the viewpoint of the cooling of IGBTs (insulated-gate bipolar transistors), which are found in inverters in hybrid automobiles. In the literature, single and multiple submerged as well as free-surface jets have been investigated. A number of correlations for heat transfer from the simulated chip surface have been presented. These correlations, as well as the results from them will be discussed in detail. We will also present results for the average heat transfer coefficient on the chip surface as a function of both coolant mass flow rate as well as velocity. All the results presented are for water jets. A numerical study of some of the single-jet cooling configurations (free-surface as well as submerged) is also performed and the CFD results are compared to the results obtained from the empirical correlations. The pressure drop associated with these jet impingement systems is also examined briefly. From the standpoint of practical implementation, high velocity jets have the potential to erode the material on which they impinge. This paper will briefly discuss erosion rates associated with jets impinging on aluminum and copper.
Creep Behavior of Lead Free Solder Interconnects in Microelectronic Packages: Impression Creep Testing and Constitutive Modeling
Authors: Dutta I. , Pan D. , Jadhav S. , Mahajan R.
Published: April 2009

The creep behavior of ball grid array (BGA) or flip-chip (FC) solder joints during thermo-mechanical cycling associated with service often limits the reliability of microelectronic packages. In addition, the fine intermetallic precipitates (Ag3Sn and/or Cu6Sn5) in the microstructures of the new lead-free solders (Sn-Ag and Sn-Ag-Cu) can undergo significant in situ strain-enhanced coarsening during TMC, resulting in in-service evolution of the creep behavior of the joints. Since there are significant microstructural/ compositional differences between bulk solder samples and tiny microelectronic solder joints, it is critical to develop accurate creep testing methodologies on tiny life-sized solder joints and microstructurally adaptive constitutive creep models for the emerging Pb-free solder alloys. In this paper, we present creep data obtained from tests conducted on individual Sn4Ag0.5Cu ball grid array (BGA) solder balls attached to a packaging substrate, using a newly developed miniaturized impression creep apparatus, which affords high test throughput with minimal sample preparation. Coarsening of intermetallic particles is demonstrated to influence creep behavior in two ways. At low stresses, the creep rate increases proportionately with precipitate size. At high stresses, precipitate coarsening influences creep response by altering the threshold stress for particle-limited creep. Based on the experimental observations, a microstructurally adaptive creep model, which accounts for the effects of coarsening on the creep response of solder joints, and is capable of adjusting itself as solder joint microstructures evolve during service, is presented, along with experimental determination of the relevant coarsening kinetics parameters.
Towards a Thermal Moore’s Law
Authors: Krishnan Shankar , Garimella Suresh V. , Chrysler Greg M. , Mahajan Ravi V.
Published: April 2009

The thermal design power trends and power densities for present and future microprocessors are investigated. The trends are derived based on Moore’s law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of the projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of an air-cooling limit consistent with Moore’s law is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
Optimization of Bulk Thermoelectric Modules for Chip Cooling Applications
Authors: Fukutani Kazuhiko , Shakouri Ali
Published: April 2009

The use of bulk thermoelectric (TE) coolers for thermal management of integrated circuit (IC) chips is analyzed by a detailed electrothermal model. Various ideal and non-ideal parameters that affect the maximum cooling performance are discussed. Thermal resistance between the hot side of the thermoelectric module and ambient is a key parameter determining maximum heat dissipation in the IC chip if its temperature should be kept below a critical value. We show that the thermoelectric geometry factor (the ratio of the leg’s cross sectional area to its length) and the TE module operating current can be optimized to significantly increase the maximum power dissipation. There is an optimum leg thickness that gives the highest cooling power density to the IC chip and further thinning of the TE module will degrade the performance. The optimum thickness and the corresponding maximum cooling power density are calculated. The effect of various material properties are also discussed.
A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects
Authors: Dang Bing , Joseph Paul J. , Wei Xiaojin , Bakir Muhannad S. , Kohl Paul A. , Joshi Yogendra K. , Meindl James D.
Published: April 2009

We demonstrate a prototype chip-scale microfluidic cooling scheme. CMOS compatible processes allow the monolithic integration of the microchannel heat sink into the backside of a Si chip at low temperature (≤260°C). At the front side of a chip, fine pitch area-array solder bumps are fabricated by electroplating for high-density electrical I/O interconnection, while a peripheral array of micro polymer pipes are fabricated as thermal-fluidic I/O interconnects. The resulting “microfluidic flip chip” can be bonded onto a liquid-cooled board substrate using conventional flip-chip assembly processes. The cooling liquid can, therefore, be transferred into a Si chip directly from the board-level manifolds to alleviate the thermal interface issues.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
A Slim Sector Model for the Analysis of Fatigue Life of Fine Pitch Flip Chip Packages
Authors: Zhao Bing , Tay Andrew A. O.
Published: April 2009

In the near future, it is likely that the interconnection pitch of flip chips will fall below 100 microns. For a flip chip of 20mm × 20mm at this pitch, there will be 40,000 interconnections on the chip. Even after taking advantage of symmetry whereby only a one-eighth model need be analyzed, there will be 5,000 interconnections. If solder were used to form the interconnection, plasticity and creep effects would need to be taken into account. Despite the great advances in computer technology, the computer memory and computation time required for a full 3D finite element analysis (FEA) of such a fine-pitch IC package is prohibitive. This paper presents a slim sector model which could be used to overcome this problem. Essentially, a slim sector of the package adjacent to the diagonal is analyzed rather than a 1/8 model. The appropriate boundary condition to be applied to the slim sector model is a critical issue. With the large number of interconnections, it is reasonable to expect that the displacement of points close to the diagonal plane of the package will tend to be directed radially outwards from the neutral point at the centre of the package. The validity of this assumption was investigated by performing a full 3D FEA of the 1/8 model of two flip chip packages of dimensions 4mm square and 6mm square. A few slim sector models have been developed and their accuracy and computational efficiency studied. The fatigue life of the critical solder joint was determined by performing a temperature cycling simulation between −40C and 150C. The elastoplastic and creep properties of solder were taken into account. As the 1/8 model is the most accurate model, its results were taken as reference. It was found that the accuracy of the best slim sector model ranged between 12% and 27%. A comparison was also made between the slim sector model and the popular strip model. It was found that the slim sector model was much more accurate than the strip model which gives error of 61–248%.
Flip-Chip Assembly of RF MEMS for Microwave Hybrid Circuitry
Authors: Hyman Daniel J. , Kuroda Roger
Published: April 2009

XCom Wireless is a small business specializing in RF MEMS-enabled tunable filters and phase shifters for next-generation communications systems. XCom has developed a high-yielding flip-chip assembly and packaging technique for implementing RF MEMS devices into fully-packaged chip-scale hybrid integrated circuitry for radio and microwave frequency applications through 25 GHz. This paper discusses the packaging approach employed, performance and reliability aspects, and lessons learned. The packaging is similar to a hybrid module approach, with discrete RF MEMS component dies flip-chipped into larger packages containing large-area integrated passives. The first level of interconnect is a pure gold flip chip for high yield strength and reliability with small dies. The use of first-level flip-chip and second-level BGAs allows the extremely large bandwidth MEMS devices to maintain high performance characteristics.