(Invited) GaN Buried Channel Normally Off MOSHEMT: Design Optimization and Experimental Integration on Silicon Substrate
Authors: Soman Rohith , Sharma Manish , Ramesh Nayana , Nath Digbijoy , Muralidharan R , Bhat K N , Raghavan Srinivasan , Bhat Navakanta 
Published: February 2020

AlGaN/GaN High Electron Mobility Transistors (HEMTs) find application in power electronics systems as high-frequency power switches. Low on-state resistance and high breakdown voltage in the off-state are the key features of AlGaN/GaN HEMTs. Achieving these qualities with a normally-off operation is a challenge.

Gate recess etching is the most widely used technique to realize a normally off AlGaN/GaN HEMT. On-state current of gate recess etched devices are limited by Scattering of electrons at the oxide-GaN interface. Free carriers in the buffer layers and nonuniform electric field distribution between gate and drain electrode limits the breakdown voltage of these devices. We address these issues by implementing a buried channel device architecture in normally-off AlGaN/GaN MOS-HEMTs. Buried channel architecture has been reported in Si, SiC and InGaAs devices. With this architecture, the on-state characteristics improve significantly since the conduction channel is formed away from the oxide-semiconductor interface, thus avoiding interface scattering. The off-state characteristics improve due to the presence of depletion region associated with a p-n junction in GaN buffer. The p-n junction in the buffer also helps to achieve uniform electric field distribution between gate and drain.

The schematic stack of the proposed buried channel normally-off AlGaN/GaN MOS HEMT is shown in fig. 1(a). Atlas silvaco simulator has been used to perform electrostatic simulation on the proposed buried channel device architechure. The thickness and doping concentrations of p-type and n-type regions in the GaN buffer are the important design parameters to be optimized. Fig. 1(b) and fig 1(c) show the electron concentration colour plot of the optimized device stack at VG = 0 V and at VG > VT respectively. The carriers bellow the gate electrode are depleted at VG = 0 V as shown in fig. 1(b) and the depletion region associated with p-n junction in the GaN buffer ensures low leakage current at off state. When VG > VT, a buried channel is formed below gate electrode as shown in the fig. 1(c), ensuring a buried conduction in the proposed device architecture.

The device stack growth was carried out in a horizontal flow AIXTRON MOCVD reactor on a 2' silicon substrate. Standard HEMT fabrication procedure with Ti/Al/Ni/Au as source/drain contact and recessed Ni/Au gate contact with ALD Al2O3 dielectric was followed for the realization of the device. Performance of a buried channel device is compared with a reference device here.

As shown in Fig. 2, VT of the device fabricated on buried channel stack and reference stack were 1.3 V and 1.7 V respectively, determined by extrapolating the linear region method. The lower VT of buried channel device compared to reference device is due to the presence of intentionally n-doped (1.5x1017 cm-3) region below UID GaN (1014 cm-3). This can be increased appropriately by increasing the p-type GaN doping, or reducing n-type doping. The field effect mobility of the buried channel device is 142 cm2/Vs compared to 25 cm2/Vs in case of reference device. More than five times increase in the field effect mobility is because of lesser interface scattering effect on electron transport in buried channel device. The off-state drain leakage current in devices on buried channel stack is four orders of magnitude lower than that on reference stack (4 nA/mm for buried channel device compared to 76 uA/mm for reference). The buried channel device has a breakdown voltage of 158V compared to 98V for reference device. The matching of calibrated device simulation and experimental results validate the advantages of buried channel architecture.

Figure 1