bluuebunny/crossref_metadata_2025 huggingface dataset:
DIELECTRIC PROPERTIES OF PLASMA POLYMERIZED N,N,3,5 TETRAMETHYLANILINE THIN FILMS
Authors: AKTHER H. , BHUIYAN A. H.
Published: September 2011

Plasma polymerized thin films of aluminium/thin film/aluminium configuration were deposited at room temperature by a parallel plate capacitively coupled glow discharge reactor using N,N,3,5 tetramethylaniline (TMA) as a precursor. The infrared spectroscopic analyses revealed that plasma polymerized TMA (PPTMA) films contained an aromatic ring structure with NC and CH side groups, presence of C = O was also evident. The differential thermal analysis and thermogravimetric analysis of PPTMA thin film was thermally stable up to about 505 K. The scanning electron microscopy of PPTMA thin film showed a smooth, flawless and pinhole free surface. The capacitance and ac electrical conductance of PPTMA thin films were measured as functions of frequency (100 < f < 105 Hz) and temperature (300 < T < 450 K). The electrical conductivity is more dependent on temperature in the low frequency region than that in the high frequency region. In PPTMA thin films the conduction may be dominated by hopping of carriers between the localized states at low temperatures and thermally excited at the high temperatures. The activation energies are estimated to be about 0.05 eV in the low temperature and 0.23 eV in the high temperature. Dielectric constant decreases with the increase of frequency and that decreases with the increase of temperature but dielectric loss increases with increasing frequency with a minimum in the low frequency region. The temperature-dependence of the Cole-Cole diagram shows the existence of distribution of dielectric relaxation times in the PPTMA thin films.
REDUCING DIMENSION IN GLOBAL OPTIMIZATION
Authors: DJALIL BOUDJEHEM , BADREDDINE BOUDJEHEM , ABDENOUR BOUKAACHE
Published: September 2011

In this paper, we propose a very interesting idea in global optimization making it easer and a low-cost task. The main idea is to reduce the dimension of the optimization problem in hand to a mono-dimensional one using variables coding. At this level, the algorithm will look for the global optimum of a mono-dimensional cost function. The new algorithm has the ability to avoid local optima, reduces the number of evaluations, and improves the speed of the algorithm convergence.

This method is suitable for functions that have many extremes. Our algorithm can determine a narrow space around the global optimum in very restricted time based on a stochastic tests and an adaptive partition of the search space. Illustrative examples are presented to show the efficiency of the proposed idea. It was found that the algorithm was able to locate the global optimum even though the objective function has a large number of optima.
THE METHOD OF APPROXIMATE PARTICULAR SOLUTIONS FOR SOLVING ELLIPTIC PROBLEMS WITH VARIABLE COEFFICIENTS
Authors: CHEN C. S. , FAN C. M. , WEN P. H.
Published: September 2011

A new version of the method of approximate particular solutions (MAPSs) using radial basis functions (RBFs) has been proposed for solving a general class of elliptic partial differential equations. In the solution process, the Laplacian is kept on the left-hand side as a main differential operator. The other terms are moved to the right-hand side and treated as part of the forcing term. In this way, the close-form particular solution is easy to obtain using various RBFs. The numerical scheme of the new MAPSs is simple to implement and yet very accurate. Three numerical examples are given and the results are compared to Kansa's method and the method of fundamental solutions.
FAST QUASI DOUBLE-PRECISION METHOD WITH SINGLE-PRECISION HARDWARE TO ACCELERATE SCIENTIFIC APPLICATIONS
Authors: NARUMI TETSU , HAMADA TSUYOSHI , NITADORI KEIGO , SAKAMAKI RYUJI , YASUOKA KENJI
Published: September 2011

The recent commodity hardware, such as the Cell processor in PLAYSTATION 3 or GeForce GTX280 GPU, has much more peak performance in single-precision than that of CPU of PCs, while the double-precision performance of these computers is comparable to it. Even though a quasi double-precision method achieves comparable accuracy to double-precision, the performance of it is relatively low. In this paper, the quasi double-precision method is modified, and it can deliver more performance than that by native double-precision of the GPU. Calculation of a Mandelbrot set and molecular dynamics (MD) simulation are used to test the method.
STUDY OF HIERARCHICAL CLUSTERING PARALLEL COMPUTATION ON PRAM MODEL
Authors: ZHOU Y. T. , HE Z. H. , WU Z. G.
Published: September 2011

An adaptive parallel algorithm for hierarchical clustering based on PRAM model was presented. The following approaches were devised to produce the optimized clustered data set, including the data preprocessing based on "90-10" rule to decrease the size of the data set, progressively the parallel algorithm to create Euclid minimum spanning trees on absolute graph, and the algorithm that determined the split strategies and dealt with the memory conflicts. The data set was clustered based on the noncollision memory, the lowest cost, and weakest PRAM-EREW model. N data sets were clustered in O((λn)2/p) time (0.1 ≤ λ ≤ 0.3) by performing this algorithm using p processors (1 ≤ p ≤ n/ log (n)). The parallel hierarchical clustering algorithm based on PRAM model was adaptive, and of noncollision memory. The computing time could be significantly reduced after original inputting data was effectually preprocessed through the improved preprocessing methods presented in this paper.
THE CHARACTERISTIC CAUCHY PROBLEM FOR DIRAC FIELDS ON CURVED BACKGROUNDS
Authors: HÄFNER DIETRICH , NICOLAS JEAN-PHILIPPE
Published: September 2011

On arbitrary spacetimes, we study the characteristic Cauchy problem for Dirac fields on a light-cone. We prove the existence and uniqueness of solutions in the future of the light-cone inside a geodesically convex neighborhood of the vertex. This is done for data in L2 and we give an explicit definition of the space of data on the light-cone producing a solution in H1. The method is based on energy estimates following Hörmander [A remark on the characteristic Cauchy problem, J. Funct. Anal.93(2) (1990) 270–277]. The data for the characteristic Cauchy problem are only a half of the field, the other half is recovered from the characteristic data by integration of the constraints, consisting of the restriction of the Dirac equation to the cone. A precise analysis of the dynamics of light rays near the vertex of the cone is done in order to understand the integrability of the constraints; for this, the Geroch–Held–Penrose formalism is used.
A UNIQUENESS CRITERION FOR VISCOUS LIMITS OF BOUNDARY RIEMANN PROBLEMS
Authors: CHRISTOFOROU CLEOPATRA , SPINOLO LAURA V.
Published: September 2011

We deal with the initial boundary value problem for systems of conservation laws in one space dimension and we focus on the boundary Riemann problem. It is known that, in general, different viscous approximations provide different limits. In this paper, we establish sufficient conditions to conclude that two different approximations lead to the same limit. As an application of this result, we show that, under reasonable assumptions, the self-similar second-order approximation [Formula: see text] and the classical viscous approximation [Formula: see text] provide the same limit as ε → 0+. Our analysis applies to both the characteristic and the non-characteristic case. We require neither genuine nonlinearity nor linear degeneracy of the characteristic fields.
NONLINEAR STABILITY OF PLANAR BOUNDARY LAYER SOLUTIONS FOR DAMPED WAVE EQUATION
Authors: FAN LILI , LIU HONGXIA , ZHAO HUIJIANG
Published: September 2011

We study the global stability of planar boundary layer solutions to the initial boundary value problem for the damped wave equation, in presence of a nonlinear convection term in the two-dimensional half space R+× R. By employing the energy method and a continuation argument, we establish that such an initial boundary value problem admits a unique global solution for a class of large initial perturbations, and that this global solution converges to the corresponding planar boundary layer solution, uniformly in (x, y) ∈ R+× R as t tends to infinity — provided the strength of the planar boundary layer solution is suitably small. Moreover, by exploiting the space–time weighted energy method and the properties of the planar boundary layer solutions, we also derive a convergence rate (both algebraic and exponential in nature) for the non-degenerate case.
Video quality for face detection, recognition, and tracking
Authors: Korshunov Pavel , Ooi Wei Tsang
Published: September 2011

Many distributed multimedia applications rely on video analysis algorithms for automated video and image processing. Little is known, however, about the minimum video quality required to ensure an accurate performance of these algorithms. In an attempt to understand these requirements, we focus on a set of commonly used face analysis algorithms. Using standard datasets and live videos, we conducted experiments demonstrating that the algorithms show almost no decrease in accuracy until the input video is reduced to a certain critical quality, which amounts to significantly lower bitrate compared to the quality commonly acceptable for human vision. Since computer vision percepts video differently than human vision, existing video quality metrics, designed for human perception, cannot be used to reason about the effects of video quality reduction on accuracy of video analysis algorithms. We therefore investigate two alternate video quality metrics, blockiness and mutual information, and show how they can be used to estimate the critical video qualities for face analysis algorithms.
Selecting vantage objects for similarity indexing
Authors: Van Leuken Reinier H. , Veltkamp Remco C.
Published: September 2011

Indexing has become a key element in the pipeline of a multimedia retrieval system, due to continuous increases in database size, data complexity, and complexity of similarity measures. The primary goal of any indexing algorithm is to overcome high computational costs involved with comparing the query to every object in the database. This is achieved by efficient pruning in order to select only a small set of candidate matches. Vantage indexing is an indexing technique that belongs to the category of embedding or mapping approaches, because it maps a dissimilarity space onto a vector space such that traditional access methods can be used for querying. Each object is represented by a vector of dissimilarities to a small set of
m
reference objects, called vantage objects. Querying takes place within this vector space. The retrieval performance of a system based on this technique can be improved significantly through a proper choice of vantage objects. We propose a new technique for selecting vantage objects that addresses the retrieval performance directly, and present extensive experimental results based on three data sets of different size and modality, including a comparison with other selection strategies. The results clearly demonstrate both the efficacy and scalability of the proposed approach.
Derivative-based audio steganalysis
Authors: Liu Qingzhong , Sung Andrew H. , Qiao Mengyu
Published: September 2011

This article presents a second-order derivative-based audio steganalysis. First, Mel-cepstrum coefficients and Markov transition features from the second-order derivative of the audio signal are extracted; a support vector machine is then applied to the features for discovering the existence of hidden data in digital audio streams. Also, the relation between audio signal complexity and steganography detection accuracy, which is an issue relevant to audio steganalysis performance evaluation but so far has not been explored, is analyzed experimentally. Results demonstrate that, in comparison with a recently proposed signal stream-based Mel-cepstrum method, the second-order derivative-based audio steganalysis method gains a considerable advantage under all categories of signal complexity--especially for audio streams with high signal complexity, which are generally the most challenging for steganalysis-and thereby significantly improves the state of the art in audio steganalysis.
Brain friendly technology: What is it? And why do we need it?
Authors: Dror Itiel
Published: September 2011

In this excerpt from "Technology Enhanced Learning and Cognition," Dr. Itiel Dror explores how to make eLearning more brain friendly and effective.
Backchannel Learning in an Organizational Setting
Authors: Kelly Dave
Published: September 2011

Social media not only creates a link to a like-minded community, but is also a useful tool for knowledge sharing. Unlike note passing in the classroom, the background chatter of Twitter can provide a wealth of information to learners separated by distance and time.
The Future of Online Learning
Authors: Borden Jeff
Published: September 2011

Today's era is one of pervasive technology. Encompassing laptops and smart phones to wikis and blogs, the digital environment makes communication, collaboration and information sharing easier than ever imagined. As a result, the world of higher education has been revolutionized by the digital age.
The gem5 simulator
Authors: Binkert Nathan , Beckmann Bradford , Black Gabriel , Reinhardt Steven K. , Saidi Ali , Basu Arkaprava , Hestness Joel , Hower Derek R. , Krishna Tushar , Sardashti Somayeh , Sen Rathijit , Sewell Korey , Shoaib Muhammad , Vaish Nilay , Hill Mark D. , Wood David A.
Published: September 2011

The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86).

The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.
Low power techniques for an android based phone
Authors: K Thimmarayaswamy , Dsouza Mary M. , Varaprasad G.
Published: September 2011

Android is the latest trend in mobile operating systems. Even though Android provides a complete set of application, middleware and Linux kernel for the phone applications developer, it does not fully utilize several standard kernel features. This work attempts to address the limitations of Android specific to power management at kernel level and proposes possible solutions for active and static power management in Linux to overcome these limitations. The developed solutions for active power management include selection of suitable governor algorithm and modification of its parameters and implementation of a daemon process, which performs voltage and frequency scaling. Application level low power techniques for Android are also proposed to help application developers to optimize their software. The objectives of the work are realized by designing and implementing low power techniques for OMAP3530 based Beagleboard. The functionality of the implemented low power techniques is verified through several test cases using benchmarking applications such as 2D/3D rendering, playing a movie file and decompressing. The test execution results are presented in terms of performance, execution time, total current consumed, standby time and battery life. From these tests, it is concluded that through low power techniques it is possible to achieve up to 29% increase in battery life and up to 117% increase in standby time at no or very little performance degradation.
Virtualizing performance asymmetric multi-core systems
Authors: Kwon Youngjin , Kim Changdae , Maeng Seungryoul , Huh Jaehyuk
Published: September 2011

Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric multi-core systems, operating systems are responsible for scheduling threads to different types of cores. However, system virtualization poses a challenge for such asymmetric multi-cores, since virtualization hides the physical heterogeneity from guest operating systems. In this paper, we explore the design space of hypervisor schedulers for asymmetric multi-cores, which do not require asymmetry-awareness from guest operating systems. The proposed scheduler characterizes the efficiency of each virtual core, and map the virtual core to the most area-efficient physical core. In addition to the overall system throughput, we consider two important aspects of virtualizing asymmetric multi-cores: performance fairness among virtual machines and performance scalability for changing availability of fast and slow cores.

We have implemented an asymmetry-aware scheduler in the open-source Xen hypervisor. Using applications with various characteristics, we evaluate how effectively the proposed scheduler can improve system throughput without asymmetry-aware operating systems. The modified scheduler improves the performance of the Xen credit scheduler by as much as 40% on a 12-core system with four fast and eight slow cores. The results show that even the VMs scheduled to slow cores have relatively low performance degradations, and the scheduler provides scalable performance with increasing fast core counts.
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Authors: Mishra Asit K. , Dong Xiangyu , Sun Guangyu , Xie Yuan , Vijaykrishnan N. , Das Chita R.
Published: September 2011

Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-core architectures. This is due to the many attractive features these memory technologies posses: high density, low leakage, and non-volatility. However, the latency and energy overhead associated with the write operations of these emerging memories has become a major obstacle in their adoption. Previous works have proposed various circuit and architectural level solutions to mitigate the write overhead. In this paper, we study the integration of STT-RAM in a 3D multi-core environment and propose solutions at the on-chip network level to circumvent the write overhead problem in the cache architecture with STT-RAM technology. Our scheme is based on the observation that instead of staggering requests to a write-busy STT-RAM bank, the network should schedule requests to other idle cache banks for effectively hiding the latency. Thus, we prioritize cache accesses to the idle banks by delaying accesses to the STT-RAM cache banks that are currently serving long latency write requests. Through a detailed characterization of the cache access patterns of 42 applications, we propose an efficient mechanism to facilitate such delayed writes to cache banks by (a) accurately estimating the busy time of each cache bank through logical partitioning of the cache layer and (b) prioritizing packets in a router requesting accesses to idle banks. Evaluations on a 3D architecture, consisting of 64 cores and 64 STT-RAM cache banks, show that our proposed approach provides 14% average IPC improvement for multi-threaded benchmarks, 19% instruction throughput benefits for multi-programmed workloads, and 6% latency reduction compared to a recently proposed write buffering mechanism.
Bypass and insertion algorithms for exclusive last-level caches
Authors: Gaur Jayesh , Chaudhuri Mainak , Subramoney Sreenivas
Published: September 2011

Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner levels, this wasted cache space leads to bigger performance losses compared to exclusive LLCs. However, exclusive LLCs make the design of replacement policies more challenging. While in an inclusive LLC a block can gather a filtered access history, this is not possible in an exclusive design because the block is de-allocated from the LLC on a hit. As a result, the popular least-recently-used replacement policy and its approximations are rendered ineffective and proper choice of insertion ages of cache blocks becomes even more important in exclusive designs. On the other hand, it is not necessary to fill every block into an exclusive LLC. This is known as selective cache bypassing and is not possible to implement in an inclusive LLC because that would violate inclusion. This paper explores insertion and bypass algorithms for exclusive LLCs. Our detailed execution-driven simulation results show that a combination of our best insertion and bypass policies delivers an improvement of up to 61.2% and on average (geometric mean) 3.4% in terms of instructions retired per cycle (IPC) for 97 single-threaded dynamic instruction traces spanning selected SPEC 2006 and server applications, running on a 2 MB 16-way exclusive LLC compared to a baseline exclusive design in the presence of well-tuned multi-stream hardware prefetchers. The corresponding improvements in throughput for 35 4-way multi-programmed workloads running with an 8 MB 16-way shared exclusive LLC are 20.6% (maximum) and 2.5% (geometric mean).
TLSync
Authors: Oh Jungju , Prvulovic Milos , Zajic Alenka
Published: September 2011

As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament barrier, a larger number of cores results in a longer latency for each round and a larger number of rounds. Hardware barrier implementations require significant dedicated wiring, e.g., using a reduction (arrival) tree and a notification (release) tree, and multiple instances of this wiring are needed to support multiple barriers (e.g., when concurrently executing multiple parallel applications).

This paper presents TLSync, a novel hardware barrier implementation that uses the high-frequency part of the spectrum in a transmission-line broadcast network, thus leaving the transmission line network free for non-modulated (baseband) data transmission. In contrast to other implementations of hardware barriers, TLSync allows multiple thread groups to each have its own barrier. This is accomplished by allocating different bands in the radio-frequency spectrum to different groups. Our circuit-level and electromagnetic models show that the worst-case latency for a TLSync barrier is 4ns to 10ns, depending on the size of the frequency band allocated to each group, and our cycle-accurate architectural simulations show that low-latency TLSync barriers provide significant performance and scalability benefits to barrier-intensive applications.
OUTRIDER
Authors: Crago Neal Clayton , Patel Sanjay Jeram
Published: September 2011

We present OUTRIDER, an architecture for throughput-oriented processors that provides memory latency tolerance to improve performance on highly threaded workloads. OUTRIDER enables a single thread of execution to be presented to the architecture as multiple decoupled instruction streams that separate memory-accessing and memory-consuming instructions. The key insight is that by decoupling the instruction streams, the processor pipeline can tolerate memory latency in a way similar to out-of-order designs while relying on a low-complexity in-order micro-architecture. Moreover, instead of adding more threads as is done in modern GPUs, OUTRIDER can tolerate memory latency with fewer threads and reduced contention for resources shared amongst threads.

We demonstrate that OUTRIDER can outperform single threaded cores by 23-131% and a 4-way simultaneous multithreaded core by up to 87% on data parallel applications in a 1024-core system. Moreover, OUTRIDER achieves these performance gains without incurring the overhead of additional hardware thread contexts, which results in improved area efficiency compared to a multithreaded core.
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
Authors: Lee Yunsup , Avizienis Rimas , Bishara Alex , Xia Richard , Lockhart Derek , Batten Christopher , Asanović Krste
Published: September 2011

We present a taxonomy and modular implementation approach for data-parallel accelerators, including the MIMD, vector-SIMD, subword-SIMD, SIMT, and vector-thread (VT) architectural design patterns. We have developed a new VT microarchitecture, Maven, based on the traditional vector-SIMD microarchitecture that is considerably simpler to implement and easier to program than previous VT designs. Using an extensive design-space exploration of full VLSI implementations of many accelerator design points, we evaluate the varying tradeoffs between programmability and implementation efficiency among the MIMD, vector-SIMD, and VT patterns on a workload of microbenchmarks and compiled application kernels. We find the vector cores provide greater efficiency than the MIMD cores, even on fairly irregular kernels. Our results suggest that the Maven VT microarchitecture is superior to the traditional vector-SIMD architecture, providing both greater efficiency and easier programmability.
Sampling + DMR
Authors: Nomura Shuou , Sinclair Matthew D. , Ho Chen-Han , Govindaraju Venkatraman , de Kruijf Marc , Sankaralingam Karthikeyan
Published: September 2011

With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting and isolating faulty cores, but the required fault detection coverage becomes effectively 100% as the number of permanent faults increases. Dual-modular redundancy(DMR) can provide 100% coverage without assuming device-level fault models, but its overhead is excessive.

In this paper, we explore a simple and low-overhead mechanism we call Sampling-DMR: run in DMR mode for a small percentage (1% of the time for example) of each periodic execution window (5 million cycles for example). Although Sampling-DMR can leave some errors undetected, we argue the permanent fault coverage is 100% because it can detect all faults eventually. Sampling-DMR thus introduces a system paradigm of restricting all permanent faults' effects to small finite windows of error occurrence.

We prove an ultimate upper bound exists on total missed errors and develop a probabilistic model to analyze the distribution of the number of undetected errors and detection latency. The model is validated using full gate-level fault injection experiments for an actual processor running full application software. Sampling-DMR outperforms conventional techniques in terms of fault coverage, sustains similar detection latency guarantees, and limits energy and performance overheads to less than 2%.
Releasing efficient beta cores to market early
Authors: Sudhakrishnan Sangeetha , Dicochea Rigo , Renau Jose
Published: September 2011

Verification of modern processors is an expensive, time consuming, and challenging task. Although it is estimated that over half of total design time is spent on verification, we often find processors with bugs released into the market. This paper proposes an architecture that tolerates, not just the typically infrequent bugs found in current processors, but a significantly larger set of bugs. The objective is to allow for a much quicker time to market. We propose an architecture built around Beta Cores, which are cores partially verified. Our proposal intelligently activates and deactivates a simple single issue in-order Checker Core to verify a buggy superscalar out-oforder Beta Core.

Our Beta Core Solution (BCS), which includes the Beta Core, the Checker Core, and the logic to detect potentially buggy situations consumes just 5% more power than the stand-alone Beta Core. We also show that performance is only slightly diminished with an average slowdown of 1.6%. By leveraging program signatures,our BCS only needs a simple in-order Checker Core, at half the frequency, to verify a complex 4 issue out-of-order Beta Core. The BCS architecture allows for a decrease in verification effort and thus a quicker time to market.
CPPC
Authors: Manoochehri Mehrtash , Annavaram Murali , Dubois Michel
Published: September 2011

Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist in other memory levels. While conventional error correcting codes can protect write-back caches, it has been shown that they are expensive in terms of area and power. This paper proposes a reliable write-back cache called Correctable Parity Protected Cache (CPPC) which adds error correction capability to a parity-protected cache. For this purpose, CPPC augments a write-back parity-protected cache with two registers: the first register stores the XOR of all data written to the cache and the second register stores the XOR of all dirty data that are removed from the cache. CPPC relies on parity to detect a fault and then on the two XOR registers to correct faults. By a novel combination of byte shifting and parity interleaving CPPC corrects both single and spatial multi-bit faults to provide a high degree of reliability. We compare CPPC with one-dimensional parity, SECDED (Single Error Correction Double Error Detection) and two-dimensional parity-protected caches. Our experimental results show that CPPC provides a high level of reliability while its overheads are less than the overheads of SECDED and two-dimensional parity.
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading
Authors: Yu Wing-kei S. , Huang Ruirui , Xu Sarah Q. , Wang Sung-En , Kan Edwin , Suh G. Edward
Published: September 2011

Large register files are common in highly multi-threaded architectures such as GPUs. This paper presents a hybrid memory design that tightly integrates embedded DRAM into SRAM cells with a main application to reducing area and power consumption of multi-threaded register files. In the hybrid memory, each SRAM cell is augmented with multiple DRAM cells so that multiple bits can be stored in each cell. This configuration results in significant area and energy savings compared to the SRAM array with the same capacity due to compact DRAM cells. On other hand, the hybrid memory requires explicit data movements in order to access DRAM contexts. In order to minimize context switching impact, we introduce write-back buffers, background context switching, and context-aware thread scheduling, to the processor pipeline and the scheduler. Circuit and architecture simulations of GPU benchmarks suites show significant savings in register file area (38%) and energy (68%) over the traditional SRAM implementation, with minimal (1.4%) performance loss.
Benefits and limitations of tapping into stored energy for datacenters
Authors: Govindan Sriram , Sivasubramaniam Anand , Urgaonkar Bhuvan
Published: September 2011

Datacenter power consumption has a significant impact on both its recurring electricity bill (Op-ex) and one-time construction costs (Cap-ex). Existing work optimizing these costs has relied primarily on throttling devices or workload shaping, both with performance degrading implications. In this paper, we present a novel knob of energy buffer (eBuff) available in the form of UPS batteries in datacenters for this cost optimization. Intuitively, eBuff stores energy in UPS batteries during "valleys" - periods of lower demand, which can be drained during "peaks" - periods of higher demand. UPS batteries are normally used as a fail-over mechanism to transition to captive power sources upon utility failure. Furthermore, frequent discharges can cause UPS batteries to fail prematurely. We conduct detailed analysis of battery operation to figure out feasible operating regions given such battery lifetime and datacenter availability concerns. Using insights learned from this analysis, we develop peak reduction algorithms that combine the UPS battery knob with existing throttling based techniques for minimizing datacenter power costs. Using an experimental platform, we offer insights about Op-ex savings offered by eBuff for a wide range of workload peaks/valleys, UPS provisioning, and application SLA constraints. We find that eBuff can be used to realize 15-45% peak power reduction, corresponding to 6-18% savings in Op-ex across this spectrum. eBuff can also play a role in reducing Cap-ex costs by allowing tighter overbooking of power infrastructure components and we quantify the extent of such Cap-ex savings. To our knowledge, this is the first paper to exploit stored energy - typically lying untapped in the datacenter - to address the peak power draw problem.
Rapid identification of architectural bottlenecks via precise event counting
Authors: Demme John , Sethumadhavan Simha
Published: September 2011

On-chip performance counters play a vital role in computer architecture research due to their ability to quickly provide insights into application behaviors that are time consuming to characterize with traditional methods. The usefulness of modern performance counters, however, is limited by inefficient techniques used today to access them. Current access techniques rely on imprecise sampling or heavyweight kernel interaction forcing users to choose between precision or speed and thus restricting the use of performance counter hardware.

In this paper, we describe new methods that enable precise, lightweight interfacing to on-chip performance counters. These low-overhead techniques allow precise reading of virtualized counters in low tens of nanoseconds, which is one to two orders of magnitude faster than current access techniques. Further, these tools provide several fresh insights on the behavior of modern parallel programs such as MySQL and Firefox, which were previously obscured (or impossible to obtain) by existing methods for characterization. Based on case studies with our new access methods, we discuss seven implications for computer architects in the cloud era and three methods for enhancing hardware counters further. Taken together, these observations have the potential to open up new avenues for architecture research.
A case for heterogeneous on-chip interconnects for CMPs
Authors: Mishra Asit K. , Vijaykrishnan N. , Das Chita R.
Published: September 2011

Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the entire network. While this homogeneous network design eases the burden on a network designer, partitioning the resources equally among all routers across the network does not lead to optimal resource usage, and hence, affects the performance-power envelope. In this work, we propose to apportion the resources in an NoC to leverage the non-uniformity in network resource demand. Our proposal includes partitioning the network resources, specifically buffers and links, in an optimal manner. This approach results in redistributing resources such that routers that require more resources are allocated more buffers and wider links compared to routers demanding fewer resources. This results in a novel heterogeneous network, called HeteroNoC, which is composed of two types of routers --
small
power efficient routers, and
big
high performance routers. We evaluate a number of heterogeneous network configurations, composed of big and small routers, and show that giving more resources to routers along the diagonals in a mesh network provides maximum benefits in terms of performance and power. We also show the potential benefits of the HeteroNoC design by co-evaluating it with memory-controllers and configuring it with an asymmetric CMP consisting of heterogeneous cores.
DBAR
Authors: Ma Sheng , Enright Jerger Natalie , Wang Zhiying
Published: September 2011

With the emergence of many-core architectures, it is quite likely that multiple applications will run concurrently on a system. Existing locally and globally adaptive routing algorithms largely overlook issues associated with workload consolidation. The shortsightedness of locally adaptive routing algorithms limits performance due to poor network congestion avoidance. Globally adaptive routing algorithms attack this issue by introducing a congestion propagation network to obtain network status information beyond neighboring nodes. However, they may suffer from intra- and inter-application interference during output port selection for consolidated workloads, coupling the behavior of otherwise independent applications and negatively affecting performance.

To address these two issues, we propose Destination-Based Adaptive Routing (DBAR). We design a novel low-cost congestion propagation network that leverages both local and non-local network information for more accurate congestion estimates. Thus, DBAR offers effective adaptivity for congestion beyond neighboring nodes. More importantly, by integrating the destination into the selection function, DBAR mitigates intra- and inter-application interference and offers dynamic isolation among regions. Experimental results show that DBAR can offer better performance than the best baseline algorithm for all measured configurations; it is well suited for workload consolidation. The wiring overhead of DBAR is low and DBAR provides improvement in the energy-delay product for medium and high injection rates.
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems
Authors: Udipi Aniruddha N. , Muralimanohar Naveen , Balasubramonian Rajeev , Davis Al , Jouppi Norman P.
Published: September 2011

It is well-known that memory latency, energy, capacity, bandwidth, and scalability will be critical bottlenecks in future large-scale systems. This paper addresses these problems, focusing on the interface between the compute cores and memory, comprising the physical interconnect and the memory access protocol. For the physical interconnect, we study the prudent use of emerging silicon-photonic technology to reduce energy consumption and improve capacity scaling. We conclude that photonics are effective primarily to improve socket-edge bandwidth by breaking the pin barrier, and for use on heavily utilized links. For the access protocol, we propose a novel packet based interface that relinquishes most of the tight control that the memory controller holds in current systems and allows the memory modules to be more autonomous, improving flexibility and interoperability. The key enabler here is the introduction of a 3D-stacked
interface die
that allows both these optimizations without
modifying commodity memory dies
. The interface die handles all conversion between optics and electronics, as well as all low-level memory device control functionality. Communication beyond the interface die is fully electrical, with TSVs between dies and low-swing wires on-die. We show that such an approach results in substantially lowered energy consumption, reduced latency, better scalability to large capacities, and better support for heterogeneity and interoperability.
Bilateral Temporal Triangular Alopecia Associated with Phakomatosis Pigmentovascularis Type IV Successfully Treated with Follicular Unit Transplantation
Authors: Unger Robin , Alsufyani Mohammed A.
Published: September 2011

Temporal triangular alopecia (TTA), also known as congenital triangular alopecia, is a nonscarring, noninflammatroy, circumscribed form of alopecia. TTA has been associated with several disorders, such as Phakomatosis Pigmentovascularis. Hair restoration surgery using follicular unit transplantation has been a successful treatment modality for TTA. Herein we report such a success that was sustained for over six years.
Disseminated Tuberculosis Mimicking Ankylosing Spondylitis
Authors: Huyge Valérie , Goldman Serge , Soyfoo Muhammad S.
Published: September 2011

Ankylosing spondylitis is a chronic inflammatory disorder affecting mainly the axial skeleton. Here we report a case of a man with a clinical suspicion of ankylosing spondylitis but with a persistence of increased inflammatory markers. In this case,18F-FDG-PET/CT revealed multiple hypermetabolic lesions in axial skeleton, lymph nodes, and the lung, suggestive of either disseminated tuberculosis or lymphoma. Histological analysis of the pulmonary lesion revealed mycobacterium tuberculosis. This case highlights, firstly, the importance of excluding other diagnoses in the presence of clinical picture of ankylosing spondylitis and high inflammatory markers and, secondly, the determining role of PET/CT.
Cocaine-Associated Myocardial Infarction: Should They All Be Stented?
Authors: Kasim Sazzli , O'Donabhain Ronan , Mcfadden Eugene
Published: September 2011

Cocaine use is a known cause of chest pain and acute myocardial infarction and frequently leads to cardiac catheterization procedure. The treatment of cocaine-related acute coronary syndromes presents unique challenges because a variety of mechanisms including atherosclerotic plaque rupture, platelet activation, and coronary vasospasm may contribute to the pathogenesis. Our case highlights important considerations taken in dealing with this acute scenario
Morphology and Ultrastructure of Brain Tissue and Fat Body from the Flesh Fly,Sarcophaga bullataParker (Diptera: Sarcophagidae), Envenomated by the Ectoparasitic WaspNasonia vitripennis(Walker) (Hymenoptera: Pteromalidae)
Authors: Rivers David B. , Keefer Donald A. , Ergin Ekrem , Uçkan Fevzi
Published: September 2011

This study tested the hypothesis that venom from the ectoparasitic waspNasonia vitripennistargets brain tissue and fat body from its flesh fly host,Sarcophaga bullata. By 1 h postenvenomation, some brain neurons began to show irregularities in nuclear shape, and though they were predominately euchromatic, there was evidence of heterochromatin formation. Irregularity in the nuclear envelope became more prominent by 3 h after envenomation, as did the condensation of heterochromatin. The severity of ultrastructural changes continued to increase until at least 24 h after parasitoid attack. At this point, cellular swelling and extensive heterochromatic inclusions were evident, multivesicular bodies occurred in the cytoplasm of some cells, and the rough endoplasmic reticulum was dilated in many of the cells. Immunohistochemical staining revealed significant apoptosis in neurons located in brain tissues. By contrast, there was no evidence of any morphological or ultrastructural disturbances in fat body tissues up to 24 h after envenomation, nor did any of the cells display signs of cell death.
Sexually Dimorphic Morphological Characters in Five North Atlantic Deepwater Skates (Chondrichthyes: Rajiformes)
Authors: Orlov Alexei M. , Cotton Charles F.
Published: September 2011

Skates exhibit a variety of manifestations of sexual dimorphism. However, this phenomenon has been poorly documented in deepwater species. New data on the sexual dimorphism of five species of deepwater skates from the North Atlantic Ocean are presented:Amblyraja jenseni, Bathyraja pallida, Bathyraja richardsoni, Rajella bigelowi,andR. kukujevi. These skates exhibit sexual dimorphism most frequently in interorbital width, disc length and width, length of the third gill slit, horizontal diameter of the orbit, length of the fifth gill slit, space between the first and fifth gill slits, length of the second dorsal fin base, mouth width, length and width of each lobe of the nasal curtain, distance from the snout to the center of anus, distance from the snout tip to the point of maximum disc width, length of the lateral fold, length of the orbit + spiracle (measured together), tail height at the pelvic fin tips, and the number of median thorns.
Severe Hemobilia from Hepatic Artery Pseudoaneurysm
Authors: Sansonna Fabio , Boati Stefano , Sguinzi Raffella , Migliorisi Carmelo , Pugliese Francesco , Pugliese Raffaele
Published: September 2011

Background. Hemobilia is a rare, jeopardizing complication of laparoscopic cholecystectomy coming upon usually within 4 weeks after surgery. The first-line management is angiographic coil embolization of hepatic arteries, which is successful in the majority of bleedings: in a minority of cases, a second embolization or even laparotomy is needed.Case Presentation. We describe the case history of a patient in which laparoscopic cholecystectomy was complicated 3 weeks later by massive hemobilia. The cause of haemorrhage was a pseudoaneurysm of a right hepatic artery branching off the superior mesenteric artery; this complication was successfully managed by one-stage angiographic embolization with full recovery of the patient.
Investigation into the Impact of Mutual Coupling on the Performance of a Multiuser MIMO System Employing Generalized Channel Inversion Technique
Authors: Wang Feng , Bialkowski Konstanty , Bialkowski Marek E.
Published: September 2011

In this paper, the performance of generalized channel inversion (GCI) technique for a multiuser MIMO system operating under antenna mutual coupling conditions is investigated. The investigation is performed via theoretical derivations and computer simulations. The theoretical derivations show that the presence of mutual coupling may result in an increased performance in terms of sum rate capacity. The simulation experiments confirm the theoretical findings in examples of three groups of numerical results. These results show that the existence of mutual coupling in an array antenna at base station (BS) results in an increased sum rate capacity when antenna interelement spacing at BS is smaller than 0.55 λ. Also it is shown that the presence of mutual coupling at mobile user (MS) terminals results in an increased sum rate capacity when antenna inter-element spacing at MSs is smaller than 0.4 λ. When mutual coupling is considered at both BS and MSs, the system configuration with antenna inter-element spacing equal to 0.45 λat BS and 0.4 λat MSs leads to the highest sum rate capacity.
Evaluation of Antioxidant Activity ofTetracarpidium conophorum(Müll. Arg) Hutch & Dalziel Leaves
Authors: Amaeze O. U. , Ayoola G. A. , Sofidiya M. O. , Adepoju-Bello A. A. , Adegoke A. O. , Coker H. A. B.
Published: September 2011

This study evaluated the antioxidant activity as well as bioflavonoid content of the methanol and ethanol-water extracts of the fresh and dried leaves ofTetracarpidium conophorum. Antioxidant activity was determined by spectrophotometric methods using DPPH free radical, nitric oxide radical inhibition and ferric reducing antioxidant power assays. In addition, total phenolics, flavonoids and proanthocyanidin content were also determined. The ethanol: water extract of the dried leaves had the highest antioxidant activity with a 50% inhibition of DPPH at a concentration of 0.017 mg/mL compared to the standards, Vitamin C and Vitamin E with inhibition of 0.019 and 0.011 mg/mL, respectively. This extract also showed nitric oxide radical inhibition activity comparable to that of rutin, 54.45% and 55.03% for extract and rutin, respectively, at 0.1 mg/mL. Ferric reducing power was also comparable to that of ascorbic acid (281 and 287 μM Fe (11)/g, resp.) at a concentration of 1 mg/mL. The methanol extract of both the dried and the fresh leaves had higher phenolic, flavonoids and proanthocyanidin content than the ethanol : water extract. The study reveals thatT. conophorumcan be an interesting source of antioxidants with their potential use in different fields namely food, cosmetics and pharmaceuticals.