bluuebunny/crossref_metadata_2025 huggingface dataset:
Measles and CAF in Printed Wiring Assemblies
Authors: Gandhi M.S. , McHardy J. , Robbins R.E. , Hill K.S.
Published: February 2008

Accelerated life tests on avionic PWAs (printed wiring assemblies) showed no relationship between measles and premature electrical failures. For the study, test samples with measles and crazes bridging up to 100% of the distance between adjacent conductors were exposed to different combinations of thermal cycling, humidity and DC voltage bias. The exposures were designed to accelerate electrochemical failure processes such as CAF (conductive anodicfilament) growth between conductors. The study was conducted in two phases. In Phase I, measled and non‐measled sites on six modules (including both epoxy/fibreglass and polyimide/fibreglass PWBs were tested. Bias voltages of 10,100 and 200 volts DC were applied during 10‐day tests and currents were monitored to detect the appearance of electrical shorts between individual conductor pads. Microscopic examination revealed no detectable change in the size or appearance of the measles during the exposure. Currents measured during the exposure were generally in the nanoamp range. They were similar for both measled and control sites and all sites passed the minimum criterion for insulation resistance of 500 megohms. Two of the modules were then tested at 320 and 500 volts. Short circuit failures were produced, but metallographic examination revealed them to be artifacts associated with reworked solder pads. There was no correlation between the incidence of failure and the presence of measles. In Phase II, test sites on two new polyimide/glass modules were exposed at voltages up to 500 V for a series of 5‐ or 10‐day periods, interspersed with precise measurements of insulation resistance under ambient conditions. Although no failures were produced in these tests, the ambient measurements showed some loss in insulation resistance with exposure time. Further testing revealed that the loss of insulation resistance was reversible and was unrelated to the presence or absence of measles.
The Effects of Ultrasonic Cleaning on Device Degradation — Quartz Crystal Devices
Authors: Richards B.P. , Burton P. , Footner P.K.
Published: February 2008

Although the use of ultrasonic agitation on quartz crystal devices during PCB cleaning has long been suspected to be detrimental, little or no data exist to substantiate or quantify the resultant effects. This paper summarises the results of a limited study into these effects for a range of quartz crystal devices, using both CFC and aqueous solvents. The variations with exposure time, and the types and mechanisms of failure are discussed. The results are encouraging and suggest that, although these devices are more susceptible to damage than ICs, once manufacturing defects have been screened out they will withstand ultrasonic exposure without deleterious effects for periods several times longer than those used for cleaning PCBs.
New Chemistries for Advanced Printed Circuit Board Fabrication
Authors: Goosey M.T.
Published: February 2008

The relentless demand for enhanced electronics processing capabilities is causing major changes in all sectors of the electronics industry, particularly in interconnection and packaging. Printed circuit board line widths and hole diameters are decreasing and new substrate materials are finding increasing use. In addition, newer high density interconnection and packaging techniques such as multi‐chip modules, chip on board and TAB are beginning to move into production. These developments are placing new demands upon PCB manufacturers, who are in turn driving their process suppliers to provide the enabling chemistries. These demands have, for example, encouraged the development of high resolution electrophoretically deposited photoresists, photoimageable solder masks and the chemical deposition of solder from solution. However, against this requirement for improved and new processing chemistries there are growing environmental pressures which have necessitated changes in both materials and processing methods, a typical example being the growing interest in direct plating of via holes. This paper reviews the challenges and opportunities in advanced PCB fabrication from a processing chemical supply perspective and discusses the new processes and chemistries that will enable the PCB industry to produce state‐of‐the‐art boards in an environmentally acceptable manner.
A Study of the Effect of Ultrasonic Cleaning on Component Quality — Hybrid Devices
Authors: Richards B.P. , Footner P.K. , Burton P.
Published: February 2008

The effect of ultrasonic agitation on hybrid devices during PCB cleaning has long been suspected as leading to device malfunction. However, little or no data exist to substantiate or quantify these effects. This paper describes a limited study into these effects using both test vehicles and commercial products, and discusses their variation with exposure time, the types and mechanisms of failure, and the rle of the hybrid package construction. It is demonstrated that the design of the hybrid package is critical in determining its susceptibility to ultrasonic damage.
‘The Purple of Cassius’ : A Recurrent Gold Finger, Tab‐plating Problem
Authors: Minten K. , Messer J.
Published: February 2008

Over the past 20 years there has been a recurrent problem of a purple‐bluish stain appearing on the laminate materials of finished printed circuit boards between the gold‐plated fingers. The origin of this staining has been traced back to the PWB fabrication plant and it is generally accepted to be related to either the gold plating bath and/or the solder stripper chemistry. In this paper the authors report their investigation of this phenomenon and show that, far from being a benign, cosmetic defect, this purple stain poses a potentially serious metallic contamination to the laminate surface of the PWB. The purple colour arises from generation of a colloidal gold chromophore known as the ‘Purple of Cassius,’ which has been known since ancient times and has been in commercial use in the glass and ceramics industry for at least 300 years.
Acid Copper Plating High Aspect Ratio Multilayer Circuit Boards
Authors: Fairweather W.A.
Published: February 2008

The throwing power of the acid copper plating process is affected by solution composition, organic additives, plating conditions and bath geometry. Recommendations for optimising these areas are given and production experiences reported.
An Evaluation of Via Hole Tenting with Solder Mask Designed to Pass MIL‐P‐55110D Thermal Shock Requirements
Authors: Davignon J.J. , Gray F.
Published: February 2008

The tenting of via holes has been a controversial issue in the military arena for several years. This issue has gained importance with MIL‐STD‐2000's requirement that all circuitry and vias under components be coated to preclude entrapment of flux. This paper addresses this issue by evaluating the MIL‐Spec thermal shock reliability of solder mask as a hole fill material and as a via tent cover. The relationship of via hole to pad size on tent reliability and solder mask thickness is also investigated. This paper concludes that solder mask as a hole fill material will not pass military thermal shock requirements and that standard dry film solder mask is very sensitive to via hole and pad dimensions. The thinner and more flexible high conformance solder mask is the only material capable of passing MIL‐Spec thermal shock requirements for all via hole to pad relationships.
Rework of Multi‐chip Modules: Device Removal
Authors: Chang J. , Spooner C.
Published: February 2008

This paper will review rework of multi‐chip modules (MCMs). The issues of die removal from substrates (i.e., PCBs) with different chip‐to‐substrate interconnect technologies will be explored in detail. These different interconnect technologies (e.g., wire bonding, tape automated bonding and flip chip bonding) and die‐attachment methods (e.g., eutectic and adhesive) have a strong influence on the MCM rework process and equipment selection. Traditional surface mount (SM) and current MCM rework technologies are also compared. It will be shown that traditional SMT rework processes and equipment are unable to solve the level of difficulty involved in fine‐pitch MCM device removal—especially for systems which require heat removal through the substrate.
Alternative Solders for Electronics Assemblies
Authors: Harris P.G. , Whitmore M.A.
Published: February 2008

This is the first of two papers reporting work carried out under a programme sponsored by the Department of Trade and Industry (DTI), involving collaboration between the International Tin Research Institute, GEC‐Marconi Ltd, BNR (Europe) Ltd and Multicore Solders Ltd. Part 1 describes the methodology used to select a number of candidate alloys as possible suitable lead‐free alternatives to tin‐lead solder.
Terpene Chemical Stability and Composition Monitoring
Authors: Ray U. , Artaki I.
Published: February 2008

Terpene based cleaning agents, such as Petroferm Inc.'s EC‐7,® are currently being used successfully for cleaning rosin based fluxes from a variety of electronics substrates. However, if rosin undergoes any thermal degradation during the various soldering operations, the effectiveness of the cleaning process becomes acutely dependent on the condition and control of the terpene bath. One of the problems associated with controlling the cleaning process is an ‘ageing’ effect of the cleaning solution as evidenced by a noticeable colour change, substantial increase in viscosity and decrease in cleaning effectiveness. There is, therefore, a critical need for accurately monitoring EC‐7 chemical composition during normal process use. FT‐IR was identified as a suitable analytical technique for convenient and accurate monitoring of the EC‐7 composition. The terpene and surfactant components of EC‐7 have characteristic fingerprints in the IR spectrum. Calibration curves were generated and used to determine the composition of ‘aged’ EC‐7 solutions. As rosin has its own unique IR absorption band, rosin contamination (bath loading) can also be easily determined. These studies demonstrated that the ageing process is governed by both the volatilisation and the oxidation of the terpene component in EC‐7, the relative rates being determined by the specific configuration of the cleaning equipment used.
Thermal‐mechanical Processing and Repairability Observations for FR‐4, Cyanate Ester and Cyanate Ester/Epoxy Blend PCB Substrates
Authors: Fehrer F. , Haddick G.
Published: February 2008

Thermal cycling tests and failure modelling were conducted on FR‐4 and cyanate ester printed circuit board (PCB) substrate materials to evaluate reliability limits tor solder and repair processes, particularly for high pin count, through‐ hole devices. The boards used were double‐sided, 0.125 in. thick with 0.029 in. diameter plated‐through holes (PTHs). Thermal cycling was accomplished using hot oil immersion at 240°C and 260°C followed by forced room‐temperature air. The average number of thermal cycles‐to‐failure was 10 for FR‐4, 20 for cyanate ester epoxy blend, and 50 for cyanate ester. Weibull statistics were used to predict failure rates for various pin count devices. Failure analysis was used to identify the mechanism of failure, and modelling was used to predict cycles‐to‐failure based on typical material properties. The primary failure mechanism was corner cracking in FR‐4 and a combination of corner cracking and barrel cracking in the cyanate ester materials. The modelling used a modified pad tilt geometry combined with Coffin‐Manson low cycle fatigue theory, which resulted in predictions of the same order as those for the cycling tests. Key material properties and process parameters were identified that controlled the failure response of the plated‐through hole and board substrate combinations.
Special Report
Authors: Cullen Lorna
Published: February 2008

After a five‐day exhibition, Electronica, Munich's international trade fair for electronic components, assemblies, related measuring devices and testing systems, has demonstrated for the 15th time that it continues to maintain its leadership function as an important trade event. The international range of semiconductor components and subsystems as well as equipment for development and quality assurance, which was presented by a total of 2,218 exhibitors and 577 additionally represented firms, met with the interest of some 90,000 trade visitors from 72 countries. Once again, strong participation and high demand are a clear indication that Electronica completely reflects market and base‐technology developments.
International Institute News
Authors: Hildred Stewart , Ross Alex , Runge Eckhard , Chellappa R.
Published: February 2008

For most of us in the industry, and certainly the members of CEMA, 1992 could have been much better. To look back over the black spots would serve only to remind us that we are not yet out of the woods. Despite the continuing recession with its attendant gloom and despondency, the Association has had some high points during the past year.
An Assessment of Cleaning Options for Soldered Electronic Assemblies (Phase II)
Authors: Richards B.P. , Footner P.K. , Prichard D.J. , Lea C.
Published: February 2008

With the advent of the Montreal Protocol, the removal of flux residues from printed circuit assemblies using solvents based on CFC‐113 is no longer an acceptable option. An alternative range of cleaning technologies is being developed and marketed for this purpose, and the aim of this work was to study the efficiency of a variety of these alternative cleaning regimes after IR reflow soldering. The results indicated that: (i) all the cleaning regimes were capable of removing flux and flux residues after standard IR reflow soldering; (ii) as the level of flux contamination under the components increased, the ability of the cleaning regimes to clean the boards decreased; (iii) the cleaning regimes had varying problems in removing the flux residues after the non‐standard (overheat) IR profile processing; (iv) when additional flux is introduced under the components (i.e., non‐standard IR reflow), the delay between soldering and cleaning becomes important; and (v) the cleaning regimes exhibited a wide variation in their ability to clean under components with small stand‐off heights.
Experimental and Analytical Studies of Encapsulated Flip Chip Solder Bumps on Surface Laminar Circuit Boards
Authors: Lau J. , Krulevitch T. , Schar W. , Heydinger M. , Erasmus S. , Gleason J.
Published: February 2008

The mechanical and thermal responses of encapsulated flip chip solder bumps on a surface laminar circuit (SLC) board have been determined in this study. The mechanical responses of the solder bumps and encapsulant have been obtained by shear, tension and torsion tests. The thermal stress and strain in the solder bumps and encapsulant have been determined by a non‐linear finite element method and the thermal fatigue life of the corner solder bump is then estimated based on the calculated plastic strains, Coffin‐Manson law and isothermal fatigue data of solders. Also, an assembly process of the test boards is presented.
Equipment Selection for Tape Automated Bonding (TAB)
Authors: Miller M.C.
Published: February 2008

The manufacturing process involving the bonding of ultra‐fine pitch TAB solder joints into printed circuit substrates requires precision equipment. This paper describes the basic components of any type of outer lead bonding (OLB) TAB equipment. It goes on to explain a selection methodology to be used when selecting equipment for customer applications. Specific examples are used to aid the equipment consumer in selecting the optimum equipment set and verifying the machine's accuracy and reliability.
Inner‐layer Registration Testing System
Authors: Siddons D.
Published: February 2008

Using a patented measuring technique, the perfecTest system has the ability to give a quantified and accurate measurement down to 25 micron (one mil) for any directional X‐axis and/or Y‐axis inner‐layer shift. Individual inner layers can be distinguished from each other and reviewed in either tabular or graphic format. Control limits are set within the software to provide pass/fail testing and all testing is performed in real time. With functions such as data storage, retrieval and SPC analysis, the system is a very powerful tool to monitor and manage inner‐layer registration problems and can lead the way to improved yield and reliability instead of creating more waste. Hole break‐out is the main cause of intermittent failure in PCBs. As the result of through‐hole plating, there is conductivity along the drill‐hole barrel. PCBs having such severe registration problems will pass in‐circuit and bare‐board tests. However, intermittent failure is often not detected until the product reaches the field and is in use.
Reliability of Surface‐mounted Anisotropically Conductive Adhesive Joints
Authors: Liu J.
Published: February 2008

The purpose of the work is to investigate the feasibility of using anisotropically conductive adhesives to join surface‐mount devices as solder replacement. The results from a literature and market survey are reported. Based on industrial demands, two anisotropically conductive adhesives were chosen for the experimental work. During the experimental work, the conductive adhesive joints were produced at various curing conditions. The joints were characterised by shear testing and electrical resistance measurement after ageing at 20, 70 and 120°C to 1000 hours. Optical and scanning electron microscopy were used to characterise the adhesive joints. In addition to this, temperature cycling tests, humidity test and pull tensile tests were used to qualify the adhesive joint reliability and quality. From the results of the present work, it can be concluded that the anisotropically conductive adhesive A joints are stable in the 85°C/85% RH environment and therefore have better corrosion resistance than adhesive B joints. Neither of the adhesives can pass temperature cycling from −55 to 125°C for 1000 cycles according to military standard 883C.
Two Novel Additive Processes to Create Circuitry: Direct Laser Writing and Direct Electrostatic Transfer Deposition
Authors: Soszek P.
Published: February 2008

Two new technologies are described for manufacturing circuitry commonly used in printed circuit boards (PCBs), multi‐chip modules (MCMs), hybrid circuits and other applications. Both processes involve the additive use of dry conductive powders which are in the micron and sub‐micron size range. Various conductive powders, such as copper, can be used. In addition, custom powder formulations to create resistive circuit elements can now be used during the same fabrication operations. The two new processes offer significant advantages over current methods. The laser in combination with sub‐micron powders allows extremely fine circuit lines and spaces to be written. Line widths of 1 mil (25 microns) can be produced. Three‐dimensional surfaces can have circuitry fabricated on them using both process methods. Lasers allow for a higher degree of accuracy, repeatability and product yield than currently experienced within the industry. Line widths and thicknesses can be software controlled and in real time. The processes do not use resists, etching or wet chemicals, thus providing substantial savings due to fewer process steps and the elimination of wet chemical handling and disposal, which is of mounting environmental concern. Use of clean process water is not required, which is an issue of cost and supply, especially in drought‐ridden areas. Very little waste is generated with the new processes as they are additive and unused powder can be reused. The first process utilises a laser to write the circuit lines on the substrate directly from a CAD/CAM database. No artwork is required for production purposes. All existing software can be used for inputting and driving the process equipment. In the process, a film of heat‐activated adhesive is laid on a substrate on top of which a layer of conductive powder is placed. The low‐power laser defines the circuitry by activating the powder and adhesive. Powder which is not activated is removed and reused. Applications include prototype production for the rapid turnaround of product to design engineers. The second process uses technology similar to that used in desktop laser printers. Instead of using toner and paper, conductive powder particles are deposited directly onto a substrate to create circuitry. The transfer and deposition of the powder are performed electrostatically and employ the same principles used in a photocopier. This allows for high volume production, with manufacturing times measured in seconds and minutes. CAD/CAM systems can be used directly; the equipment can be desk‐sized and is capable of operating in an office or laboratory environment. This yields savings on expensive custom facilities. Desktop manufacturing of circuitry using these new patented processes is within sight.
Soldering Techniques for Fine‐pitch SMDs
Authors: Judd M.C.
Published: February 2008

To better understand trends and user experiences with fine‐pitch surface mounted component assembly, the author's company has surveyed a number of manufacturing engineers involved in the processing of such devices, including telecommunications equipment, business equipment, computers and related peripherals, test instruments, automotive electronics and military electronics. This paper summarises the findings of this survey. It reviews the various fine‐pitch devices, the special process steps required to assemble these components, conditions under which mass reflow techniques have proved acceptable, and the reported advantages and limitations of the alternative localised reflow processes.
High Density Flex‐rigid Circuits — A Solution for Board‐to‐board Transmission Line Interconnects
Authors: Buck T.J.
Published: February 2008

Flex‐rigid circuits have been used for many years, primarily by the military, as a method to reduce the size and increase the reliability of electronic systems. However, in today's emerging designs where high speed ASICs are often the dominant components, flex‐rigid circuit assemblies are now an attractive solution for providing high density transmission line interconnects from board to board. Much of today's circuitry is being committed to ASIC designs to increase both circuit density and speed. Following this path, designers are faced with the task of interconnecting high lead count SMT packages often with as many as 300 to 500 leads per device, each dissipating several watts. At these power densities conductive cooling through the circuit board is often a necessity, dictating the use of either metal cores or heat exchangers. To make efficient use of the core and minimise weight, designs generally require SMT packages to be mounted on both sides of the core with electrical communication from side to side. However, as more exotic core materials (carbon fibre matrix, beryllium, etc.) and liquid cooled heat exchangers are used, electrical communication through the core has become difficult, if not impossible, in some cases. Instead, high density flex‐rigid assemblies are used to partition the circuit, allowing the board to ‘fold’ over the core. This results in hundreds of signal lines that must cross the flex, obeying the electrical design rules dictated by the rigid sections to maintain impedance values and crosstalk margins. This paper focuses on recent work at AIT, producing high density flex‐rigid circuits using embedded discrete wiring technology to meet the above requirements. Using 0.0025 in. diameter polyimide insulated wire, as many as 100 lines per linear inch can pass over the flex region on a single layer. This generally results in a single flex layer where all wires can be referenced to a continuous ground plane from board to board. Controlled impedance is easily maintained due to the uniform wire geometry, and high frequency attenuation is significantly lower than on equivalent etch circuit designs due to the smooth surface finish on the wire. In addition, the high interconnection density offered by this technique reduces the overall thickness of the rigid sections, thereby minimising the thermal resistance to the core.
Electromigration vs SIR
Authors: Jozefowicz M.E. , Lee N.‐C.
Published: February 2008

The IPC‐SF‐818 surface insulation resistance (SIR) test data taken with the use of a variety of halide‐free, no‐clean fluxes are analysed against Bellcore TR‐NWT‐000078 electromigration (EM) test data. Neither test results show correlation with bulk flux resistivity, flux water extract resistivity, flux residue moisture pick‐up, and flux corrosivity without bias. However, in the case of rosin fluxes, the insulation resistance behaviour in both SIR and EM tests is a function of the pH value of fluxes. This phenomenon is more significant in the SIR test. In the case of low‐residue, no‐clean fluxes, only the SIR test displays such a pH dependent relationship. Data suggest that the 50 volts bias voltage used in the SIR test may be responsible for this, and can be explained with a high‐bias‐voltage‐induced electrolysis mechanism which is further promoted by a high pH environment. This failure mechanism is absent in the EM test which utilises 10 volts bias voltage, and probably will not occur under the normal 5 volts application conditions. Overall, the SIR test seems to be more stringent while the EM test appears to be more realistic.
A Systematic Evaluation of Factors Influencing TAB Inner Lead Reliability
Authors: Evans H.E. , Harvey P.M. , Dabroski J.L. , Dearing G.O.
Published: February 2008

Reliability evaluations for new electronic components and assemblies regularly require extensive test cycles that are both time consuming and costly. Objectives of such test batteries are to identify failure mechanisms and the relationship between these mechanisms and product design or processing features. Optimisation of these critical factors or process steps results in optimised reliability. Statistically designed experiments can facilitate the optimisation process by minimising the amount of testing needed to identify factors affecting reliability, and by providing insight into how these factors can be specified to ensure optimum product design. Designed experimentation was utilised in this study to look at product design and process factors affecting the reliability of inner leads for tape automated bonding (TAB) components. Four factors are considered: outer lead compliancy; chip immobilisation; downset; and tape stiffness and rigidity. Experimental details and results are presented which assess the relative importance of these factors in determining ultimate inner lead reliability, and also provide guidance for final product design considerations.
Development of a Novel No‐clean Solder Paste
Authors: King C. , Ong T.S.
Published: February 2008

The electronics industry faces a serious challenge in its approach to the cleaning of printed circuit boards after reflow soldering. A unique approach has been adopted to give invariant viscosity, hot/wet slump resistance and low residue solder pastes. Carefully tailored activation systems provide effective reflow and benign no‐clean residues. High metal loadings are incorporated with fine pitch capability and consistency of product.
A Practical Solution for Low‐cost, High Performance MCMs
Authors: Hammond J.
Published: February 2008

An IC manufacturer's experience with a new technology for connecting bare chips to flexible PCBs is described. The process produces low‐cost fine line flexible PCBs and also direct chip to PCB connection as an integral step in PCB production. The paper is addressed to managers and technologists involved in MCM or bare chip packaging development and fabrication. The technology described was developed by AMEG in conjunction with a number of specialist companies and presents an approach of strategic significance to the industry. IC (integrated circuit) packaging technology is a priority issue, as systems' performance is no longer silicon driven, but is now determined by the interconnection systems used between ICs. This problem is not new, but is rapidly escalating. There is an abundance of technical offerings addressing this question. However, those capable of acceptable performance are distinguished by their high level of both complexity and cost. Of greater consequence is their inability to be effectively implemented in the ‘real world’. One IC house has identified this as a key strategic issue. It accepts that a solution must also make managerial sense, consider the logistics issues, be cost‐effective and enable a practical implementation strategy. The results of this development are the subject of this paper. Despite its divergent development terms of reference, technical performance is not compromised.
Solder Joint Reliability of a Thin Small Outline Package (TSOP)
Authors: Lau J. , Golwalkar S. , Boysan P. , Surratt R. , Forhringer R. , Erasmus S.
Published: February 2008

The reliability of 0.5 mm pitch, 32‐pin thin small outline package (TSOP) solder joints has been studied by experimental temperature cycling and a cost‐effective 3‐D non‐linear finite element analysis. Temperature cycling results have been presented as a Weibull distribution, and an acceleration factor has been established for predicting the failure rate at operating conditions. Thermal fatigue life of the corner solder joints has been estimated based on the calculated plastic strain, Coffin‐Manson law and isothermal fatigue data on solders. A correlation between the experimental and analytical results has also been made. Furthermore, failure analysis of the solder joints has been performed using scanning electron microscopy (SEM) and an optical method. Finally, a quantitative comparison between the Type‐I and Type‐II TSOP solder joints has been presented.
Excimer Laser Structuring of Epoxy Resin Layers for MCM‐L Applications
Authors: Kersten P. , Glaw V. , Reichl H.
Published: February 2008

Multichip module packaging enables a significant increase of interconnect densities and performance of electronic systems. Multichip module technology based on laminate materials (MCM‐L) is attractive due to low cost and use of the standard equipment used by PCB manufacturers. The most limiting factor for higher wiring densities in PCB technology is the mechanical drilling of plated‐through holes. Using 0.3 mm drill diameters, 0.5 mm land diameters are required, which limit the area for routing of tracks. Therefore, alternative dielectric materials, which can be structured photolithograpically, by plasma etching or laser drilling, are very attractive for MCM‐L technology. In this paper an epoxy resin layer, commercially available as a solder mask, is investigated as an interdielectric layer. Via hole drilling is investigated using an excimer laser. To show process feasibility, a two‐layer wiring system is fabricated using the excimer laser structured epoxy resin as an interdielectric layer on conventional epoxy board (FR‐4).
Conformal Coating Adhesion … To Stick or Not to Stick?
Authors: Naisbitt G.K.
Published: February 2008

Increased sophistication in the manufacture of electronic circuits, together with the ever more widespread adoption of conformal coatings, has led to new problems which are frequently the result of an interaction between residual surface chemicals and the electronic circuits themselves. In some instances poor adhesion between the conformal coating and the substrate may be experienced. This paper intends to assist the engineer in identifying where the problem may lie which only through appropriate quality process control and testing can be suitably resolved. It is important for the reader to consider whether there is a problem, if a circuit assembly has been exposed to, and passed, the required environmental testing regime, yet upon subsequent examination the coating is found to have an unusually poor level of adhesion. It is also particularly relevant to appreciate that there are currently no formal standards of entirely suitable test methods to determine what is an acceptable level of adhesion.
Computer Aided Design (CAD) for Printed Circuits Part 2
Authors: Ferrari G.
Published: February 2008

This paper, which will be published in two parts in consecutive issues of Circuit World, reproduces a chapter of the recently published book ‘Handbook of Printed Circuit Technology: New Processes, New Technologies’, edited by G. Herrmann and K. Egerer and published by Electrochemical Publications Ltd, Port Erin, Isle of Man.
Company Profile
Authors: Cullen Lorna
Published: February 2008

Situated in Scotland's ‘Silicon Glen’ and close to two of Scotland's great championship golf courses, Royal Troon and Turnberry, is Ayr's rurally located Mosshill Industrial Estate — home to Prestwick Multitech Ltd. In the heart of Robert Burns' country and just two miles from a coastline whose climate is reputedly tempered by the Gulf Stream, Prestwick Multitech is the multilayer manufacturing subsidiary of the Interconnection Division of Prestwick Holdings plc.
PCIF News
Authors: Galbraith T.
Published: February 2008

Setting off on the short trip from the Isle of Man to London, it was a wet and windy day signalling the imminent arrival of another British winter. However, on arrival at Heathrow, the stormy weather had abated and there was an almost calm serenity which made the 15 minute drive to Egham in Surrey pleasantly uplifting.
EC/Japan PCB Procurement Project
Authors: Haken B. , Starkey P.
Published: February 2008

To improve the competitiveness of the European single‐sided PCB industry as supplied to the European Consumer Electronics Industry.
A Voyage to the End of the World!
Authors: Ellis B.N.
Published: February 2008

The title of this review may be slightly misleading because Lannion is really a few kilometres from Finisterre, but it certainly seemed as if we were getting to the end of the world travelling there in a fierce equinoctial tempest, one of the worst for several years! Fortunately, the weather cleared up for the opening of the conference the following day and revealed the beauty of the Britanny landscape. Nevertheless, the remark must be made that Lannion was a peculiar choice for an International Conference in view of the fact that it is 500 km from the nearest international airport. A number of participants complained of the difficulty of communications and it is known that others abstained from participating purely because of the difficulties of reaching such an isolated spot. However, some 210 delegates arrived by all possible means. Let it nevertheless be said that the organisation was impeccable — one of the best conferences I have ever attended from that point of view. As just one example, Lannion is essentially a small, mediaeval market town that has outgrown its clothes by the advent of modern technology and the enterprises that surround it. The result is a severe lack of modern hostelries capable of lodging an influx of a couple of hundred or more persons. However, there are an adequate number a few kilometres away, in Perros‐Guirec, a small town situated over three picturesque coves on the Pink Granite Coast. The organisers had the forethought to ensure coaches were always available to shuttle the delegates between their hotels and the various events. They also engaged the services of a caterer to produce lunch and dinner each day, probably otherwise impossible if the delegates had to make their own arrangements.
PWB Surface Finishes for COB
Authors: Landis D. , Notman J.
Published: February 2008

When implementing chip‐on‐board (COB), the surface finish on the printed wiring board needs to be chosen with several key considerations in mind. The choice of bonding technology dominates the selection of finishes. Wire bonding, tape automated bonding and flip chip assembly all have their own special requirements for effective assembly. The considerations must also examine the presence of intermetallics in the solder joints. These issues are discussed along with several advanced techniques for applying solder coating and organic solderability preservatives on bare copper PWBs.
Manufacturing Cost Analysis of Surface Mount PCB Designs
Authors: Alexander M. , Srihari K. , Emerson C.R.
Published: February 2008

A product's design influences its manufacturing process and the associated costs. Consequently, design engineers need to review their designs from a manufacturing perspective. While ‘Design For Manufacturing’ (DFM) tools often identify the manufacturing problems associated with a design, they would be more effective if these problems could be represented to the designer in terms of a cost value. This research developed a cost estimation tool for the designer in the surface mount printed circuit board (PCB) domain by integrating computer aided design, computer aided process planning (CAPP) and cost estimation techniques using a knowledge based framework. The cost estimation can be done in two design stages. First, an initial approximation of the manufacturing cost can be obtained using information such as the component mix, type of substrate and the size of board. After the detailed design of the PCB has been developed, a more accurate PCB assembly cost can be obtained using computer aided design (CAD) data. Both cost determination strategies would require the generation of a macro‐process plan. The cost advisor considers tangible and intangible factors. This cost advisor and the DFM environment have been developed using C ++ and object oriented programming constructs under the MS Windows operating system.
Ionograph Sensitivity to Chemical Residues from ‘No Clean’ Soldering Fluxes: Comparison of Solvent Extract Conductivity and Surface Conductivity
Authors: Adams K.M. , Anderson J.E. , Graves Y.B.
Published: February 2008

This study examines solvent extract conductivity (SEC) testing, e.g., Ionograph or Omega Meter testing, which measures ionic cleanliness of printed wiring boards (PWBs). SEC has been a quality control (QC) monitor to assure product electrical reliability. Typical SEC measurements occur after wave soldered products have been solvent‐cleaned. This study concerns SEC testing on new wave soldering processes that involve no solvent cleaning, i.e., inert gas soldering with ‘no clean’ fluxes. Results show ionic residues from ‘no clean’ fluxes may have other characteristics that make QC testing for ionic cleanliness inappropriate. However, SEC may be appropriate as a process control monitor after soldering with these fluxes. An Ionograph measured SEC response for the following chemicals: NaCl, NaF, NaBr, KCl, MgCl2, CaCl2, HCl, succinic acid, malic acid, glutaric acid, adipic acid and ethylene glycol. The list includes inorganic salts, strong electrolytes, which may arise from manufacturing or PWB materials. The list also includes weak organic acids (WOAs) common to ‘no clean’ fluxes. One non‐ionic hygroscopic chemical, ethylene glycol, was studied. Ionograph response was measured via (i) direct injection of aqueous solutions and (ii) immersion of PWBs with individual chemicals as surface deposits. All ionisable compounds, including all WOAs, produced substantial SEC response. Surface conductivity was measured at 35°C/90% relative humidity (RH) with controlled amounts of the above chemicals deposited on clean PWB test circuits. Surface loadings corresponded to the molar‐ionic equivalent of 2.0 ?g/cm2 NaCl. In addition, NaCl, adipic acid and polyethylene glycol (PEG 400) were examined as a function of concentration. Several ionisable chemicals including all WOAs produced no measurable effect, i.e., surface conductivities were indistinguishable on clean and deposited specimens. Surface conductivity increased for ionic contaminants with critical RH below ∼80% and for the non‐ionic hygroscopic glycol. SEC measurements and surface conductivities were compared. The latter is more directly related to electrical reliability. Although all ionic compounds including the WOAs showed a SEC response, not all enhanced surface conductivity. Achievement of critical RH appears to be the important factor. Adipic acid required the presence of hygroscopic glycol to enhance surface conductivity. Therefore, SEC can be a misleading QC test for electrical reliability when WOA flux residues are present.
PWB Interconnect Strategy Using a Full Build Electroless Copper Plating System
Authors: Minten K. , Kitchens K. , Cisson J.
Published: February 2008

In the preceding three parts of this series, the authors have extensively reviewed and quantified the special processing sequences required for the ‘additive’ and ‘semi‐additive’ process strategies of PWB manufacture. In this, the fourth part of the series of five, they wish to present a series of full build processes which meet all the interconnect requirements of the 1990s while eliminating the drawbacks traditionally associated with additive processes.
Asian Electronics and PWB Production, Market and Technology
Authors: Nakahara H.
Published: February 2008

The economic growth of Pacific Asian countries in the last three decades is unmatched elsewhere. Financial muscle in Tokyo, Hong Kong and Singapore is comparable to that in New York, London and Frankfurt. Electronics has been one of the industries favoured by this region of poor natural resources but rich in well‐trained manpower. Fuelled by desire and strong financial backing, Pacific Asia is now responsible for 70% of the world output of consumer electronic products. Malaysia is becoming a central focus for IC assembly and the manufacture of consumer electronic goods. Singapore is the disc drive manufacturing centre of the world. Taiwan accounts for 10% of the world PC production. Hong Kong may be a model for future China when the British colony is returned to China in June 1997. Korea is becoming a power house in IC memory. Japan is a threat to the United States in every industrial field imaginable. In this paper, the author will examine the status today and in the year 2000 and beyond of Asian electronics with a special emphasis on the Asian PWB industry which already accounts for 45% of the world production. In addition to production and market assessment, technologies and manufacturing costs will be studied in comparison with the rest of the world.
The World Printed Circuit Industry
Authors: Custer W.D. , Linsdell R.C. , Shoemaker S.W.
Published: February 2008

This paper examines the size, scope and electronic equipment end‐market ‘drivers’ of the world printed circuit industry. Topics include general industry trends, the captive/merchant producer balance, semiconductors as they relate to PCB demand, regional comments on the European, Americas and Asia/Pacific markets, process consumable consumption and a detailed discussion of the relationship of electronic equipment to PCB demand.
Enabling Technologies for Low‐count Chip Packaging
Authors: Hashemi H. , Olla M. , Spooner C. , Walshak D.
Published: February 2008

This paper explores the enabling technologies and thermal performance trade‐offs associated with inserting small multichip modules (MCMs) into surface mount packages. Using assembly and interconnect technologies available today, ‘few‐chip’ packages can lead to less costly solutions than traditional single chip package approaches, and may be practical depending on system size and modularity constraints. The key enabling technologies required include fine‐line interconnect substrate technology, direct leadframe attachment and chip bonding to fine‐line laminate substrates, the moulding of large substrates with multiple components in a thin surface mount package, and cost‐effective cooling techniques. The thermal performance of a moulded few‐chip package is analysed and cooling methods are discussed. A screening experiment was performed in which several geometric and material parameters were studied to determine their impact on thermal performance. The size of the heat slugs appears to be the variable with the greatest effect on thermal performance. The effects of external board size, board material and the design of the internal substrate on the thermal performance of a few‐chip packaqe are also discussed.
Desmear — The Key Processes for Reliable Through‐plating of Printed Circuitry
Authors: Angstenberger A.
Published: February 2008

The paper describes in detail the basics of manufacturing printed circuits and all relevant interactions with the currently used methods of desmearing. A matrix proposes the optimal method to choose depending on the given needs of an application. The first part discusses the general layup of printed circuits, the commonly used sequences of manufacturing, different types of construction and, of most importance to the desmear processes, the polymeric nature of widely used laminates. Single processes of the through‐plating sequence, as well as the consequences of desmearing for subsequent assembly operations, are highlighted. An overview of currently used methods of desmearing is given with respect to commonly used process parameters as well as the basics of the relevant chemical reactions. The second part of the paper focuses on selection of the optimal desmear method, depending on the nature of the material for a given application, namely the different polymers utilised in rigid, rigid‐flex and microwave circuits. The paper ends with a survey of practical ways to monitor the process capability of any desmear process.
Small Steps or a Large Stride?
Authors: Kingsley D.
Published: February 2008

The electronics interconnection industry has progressed from the early invention of the thermionic valve to today's surface mount technology, where the development of large‐scale integration on silicon is the major driving force. The paper considers the changes that lie ahead in board and assembly technology in both the short and long term. It gives the author's view on whether interconnection technology will be subjected to a major change or just small incremental steps.
Organic Microelectronic Packages: Challenges for a PCB Manufacturer
Authors: zur Nieden T.
Published: February 2008

The driving forces behind recent significant improvements in organic packages for microelectronic applications are electrical performance, product weight, size and manufacturing cost. A very careful selection of optimum manufacturing processes, equipment and materials, and stringent control of critical manufacturing operations are prerequisites for success in this emerging market place. Major technical and business related challenges to a printed circuit board manufacturer who plans to enter this market are discussed.
A Large Format Modified TEA CO2 Laser Based Process for Cost‐effective Small Via Generation
Authors: Morrison J.M. , Tessier T.G. , Gu B.
Published: February 2008

Recently, a Transverse Excited Atmospheric (TEA) CO2 laser technology has been developed for the micro‐machining of vias in non‐reinforced glass laminates. This system has been designed to accommodate the large panel sizes associated with PWB processing. The salient features of this modified CO2 laser technology are summarised. A joint Lumonics/Motorola study was carried out to assess the applicability of this laser processing technology for use in higher density PWB and MCM‐L substrate processing and its compatibility with currently available classes of dielectrics used in high density interconnect applications. A 10x improvement in cycle time/throughput over the existing raster scanning laser ablation process has been demonstrated.