bluuebunny/crossref_metadata_2025 huggingface dataset:
Ultrathin WLP Die Embedded Polyimide Multi-Layer Wiring Board
Authors: Okude Satoshi , Okamoto M. , Sano Y. , Ueta N. , Nakao O.
Published: October 2015

We have developed an ultrathin IC-embedded polyimide multi-layer wiring board utilizing a wafer level packaging (WLP) technology. The IC die is wafer level packaged with no solder bump (i.e. just copper land), thinned less than 100 micron and then sandwiched between multi-layer printed wiring boards composed of thin polyimide films with the thickness of several tens of microns used in standard flex boards. Therefore, the realized embedded board has a very thin structure, e.g. the thickness of a 4 layers board with 1 die embedded is 220 micron. For the electrical connection between circuit layers including redistribution layer of the embedded die, the means employed in our standard wiring board process is applied. The electrical connection is made by the conductive paste, which consists of several kinds of metal filler and resin adhesive and makes alloy between copper of circuit layer thorough pressing and heating processes. The alloying feature of the paste assures the robustness of the connection.

The reliability of the board under several environmental test conditions has been confirmed so far, however, the board performance under bending stress was unclear. The realized board is still flexible and bendable to some extent, although the board has higher stiffness than standard flex board owing to its multi-layer structure. To confirm whether this feature affect on the board's performance or not, we have investigated the performance of the embedded board under the condition that the bending stress is applied to the die embedded die. The experimental results show no significant change due to the bending stress and the high durability against bending is confirmed.
Impact of Process Improvements on Reliability of RCP Technology During Scale-up
Authors: Leal George R. , Hayes Scott , Koey Dominic , Gong Tony , Mitchell Doug , Wei Gao , Wright Jason , Vessa Tony
Published: October 2015

The start-up of the 300mm RCP prototype production line using automated tools was challenged by significant differences in tool sets when compared to the manual and semi-automatic lab based equipment used to develop the baseline RCP fabrication process. Thus, process transfer to automated tools required key parameter adjustments in an attempt to match the process output and reliability performance previously achieved with the 200mm lab based flow. During reliability testing of early parts from the 300mm prototype line, failures in the build-up layers were observed after thermal cycling test. The failure mechanisms were previously observed and resolved during the technology development phase using the 200mm lab based tools.

An experiment was developed to identify the root cause of the build-up failures. A single die, 9x9mm, 258 I/O, 0.5mm pitch package with 2 metal routing layers was chosen as a test vehicle for the experiment. Moisture preconditioning and air to air thermal cycling at 2 different conditions followed by electrical test and visual inspection for dielectric cracks were used to gage reliability performance. Several factors were evaluated related to the dielectric and metallization processes as well as the backend interconnect process. The results from the experiment indicated the appropriate tool parameters that allowed the 300mm prototype line process output to closely match that of the 200mm lab based tools. The optimized process combined with the use of an alternate solder material allowed the 300mm RCP prototype line to successfully achieve line certification status and demonstrated RCP reliability performance beyond standards.
Cost Effective Production of Glass Interposers for 3D ICs Using APEX(TM) Glass Ceramic
Authors: Flemming Jeb H. , Dunn Kevin , Gouker James , Schmidt Carrie
Published: October 2015

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; electrical leakage and lack of improved electrical performance beyond 16nm. As a result, industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost.

In this talk, we will present on our efforts in glass interposers fabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. Life MicroFab's APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitchs, in 125 micron thick APEX™ Glass ceramic. We will present (1) on our efforts producing high aspect ratio TGVs in thin (500-250 micron) and ultra thin (250-75 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.
3D-IC Integration Using D2C or D2W Alignment Schemes Together with Local Oxide Reduction
Authors: Lecarpentier Gilbert , Mottet Jean-Stephane , Cooper Keith , Stead Michael
Published: October 2015

3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements.
Cu-Cu Thermocompression Bonding using Ultra Precision Cutting of Cu Bumps for 3D-SIC
Authors: Sakai Taiji , Toshiya Akamatsu , Imaizumi Nobuhiro , Toyoo Miyajima , Mizukoshi Masataka
Published: October 2015

We have developed a new Cu-Cu thermocompression bonding technique by using cut Cu bumps in order to achieve high density 3D-stacked IC (3D-SIC). Currently, Sn layer is formed between Cu bumps, and then solid-liquid bonding is made by tin melting to connect Cu bumps. But using Sn layer can cause undesirable issues, such as electro-migration and Kirkendall voids formation between Cu/Sn interfaces, which could decrease bonding reliability. Therefore we believe that Cu-Cu thermocompression bonding is an essential technology especially in 3D interconnection.

In the present study, cut Cu bumps were obtained by ultra-precision cutting using a single crystal diamond bite that would give a highly smooth Cu surface (Ra:7nm). A major advantage of cut Cu bumps is that they have an amorphous-like layer on the surface. In TEM observation, it was found that about 120nm thick amorphous-like layer was formed after cutting of Cu bumps. This layer has a potential to connect bumps each other at a low temperature similar to solder bonding because amorphous-like layer accelerates a recrystallization reaction of Cu crystal.

Cut Cu bumps on both sides of LSI and substrate have been successfully bonded at 250 degrees C condition. From the analysis of crystal orientation by EBSD, it was found that the bonding interface had disappeared, which means solid diffusion was occurred and crystal grain grew across the interface.
Temperature and Humidity Effects on MEMS Vibratory Gyroscope
Authors: Patel Chandradip , McCluskey F. Patrick , Lemus David
Published: October 2015

MEMS vibratory gyroscopes are increasingly used in applications ranging from consumer electronics to aerospace and are now one of the most common MEMS products after accelerometers. Despite their widespread use, the performance of MEMS gyroscopes in harsh environments is still under question. While some studies have been conducted to understand the temperature dependent performance of MEMS gyroscopes, the effects of sustained exposure to temperature combined with other harsh environment stresses have not been well researched. Thus, it is necessary to quantify MEMS vibratory gyroscope performance under such conditions. This paper will focus on the combined effects of temperature and humidity only. Performance of the MEMS vibratory gyroscope will be evaluated over time at high temperature and high humidity conditions by conducting an aging test on a COTS (commercial of the shelf) single axis MEMS vibratory gyroscope having an operating temperature range from −40°C to 80°C. The gyroscope sensor will be exposed to 60 °C and 90% RH (Relative humidity) for 500 hours. In-situ data will be monitored to track any shifts in device output. Any permanent changes in the output signal will be traced back to their fundamental root cause damage mechanism.
Packaging HB LEDs with Integrated Beamshaping
Authors: Hoeftmann Thomas
Published: October 2015

LED light will dominate in future a lot of application fields in everyday life and it already started not only in consumer market. Therefore more and more applications require new ideas and approaches for packaging to fulfill upgraded requirements for protection, reliability, beam shaping and cost reduction, especially for High Brightness (HB) LEDs in e.g. automotive and other markets.

This presentation will give an overview about the developed monolithic window with integrated anti-glare shield for HB LED packaging used in the automotive market for low and high beam headlights and other special lighting functions of modern cars.

Apart from the component protection, the monolithic window ensures that there is sufficient contrast and thus glare protection in the irradiation area of the LED array.

In addition future packaging technologies will be introduced to provide 3D interconnection and beam shaping by glass lenses. All discussed packaging ideas will meet the requirement of vacuum tight wafer level packaging by building monolithic packaging boards or capping wafers made of micro processed silicon and glass material.
Laser Technology for Through-Silicon Via and Microvia Drilling in Silicon for 3D Packaging Applications
Authors: Hooper Andy , Finn Daragh , Noel Shane , Anderson Gregg , O'Brien Jim , Lin Chi-Cheng
Published: October 2015

Presented here are laser processes for drilling debris-free and recast-free vias in silicon that are suitable for subsequent process integration. The process strategy consists of an integrated laser via drill system combined with an isotropic dry etch system. By careful selection of both the laser and etch process parameters it is possible to control the via depth, diameter, sidewall slope/taper, and to eliminate the damaged Si material in the laser heat affected zone. Because the etch process is highly selective to Si, this is a mask-free and cost-effective process. Two different laser processes are demonstrated. For Part 1 we demonstrate a process for TSVs with diameters in the range of 50–250 um for <500 um thick Si wafers. For Part 2 we demonstrate a process for blind vias in Si stopping on a metal layer with diameters ≤50 um for ≤50 um thick Si wafers.
Novel Wet Chemical Copper Metallization for Glass Interposers
Authors: Bamberg Simon , Bruening Ralf , Etzkorn Johannes , Bruening Frank
Published: October 2015

The focus of the chip and IC substrate manufacturing industry for interposers is currently shifting from organic substrates to inorganic materials. Interposers overcome the dimensional mismatch between a die and an organic PWB substrate and need to buffer the differences in thermal expansion between these two materials.

While inorganics like silicon and glass, have a low CTE value compared to organic material, glass has some significant advantages over silicon. These are namely material cost, availability in panel size and a better electrical insulation. In order to further increase the cost advantage, metallization could be done by either electroless or electrolytic copper plating as an alternative route to sputter technology. Both wet chemical processes are well established in PWB manufacturing and need adaptation to glass substrates. Compared to sputtering, 3D-features can be covered with a wet chemical treatment in a comparatively economical process.

Filling of TGVs (Through Glass Vias) by electrolytic copper plating requires the presence of a conductive film which is created by applying electroless copper deposition of typically 300–500nm thickness. The general issue is poor adhesion to the smooth glass surfaces. To improve adhesion between glass and metal, various treatments were assessed in this study: Mechanical anchoring was achieved by etching the substrate (subtractive) as well as by depositing nano-sized silica particles (additive). Both treatments are in solution and 3D-features are accessible in contrast to a purely mechanical approach. Surface treatments without inducing additional roughness included the adsorption of functional metal-affine polyelectrolytes and silanization for conditioning which enhanced the adhesion of the copper layer to various degrees.

To study the impact of chemical formulation on strain/stress development and relaxation in the film as a key impact factor for blister (adhesion) performance, the electroless copper layer growth was monitored by in-situ XRD methods during and after deposition.
Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer
Authors: Tsang Cornelia , Okada Janet , Huenger Eric
Published: October 2015

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions.

In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths.

This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.
CMOS Analog Front-End IC for Gas Sensors
Authors: Kim Hyuntae , Bakkaloglu Bertan
Published: October 2015

An electrochemical sensor readout analog front-end (AFE) IC for recording long term chemical and gas exposure is presented. The AFE readout circuit enables the detection of exhaust fumes in hazardous diesel and gasoline equipment, which helps correlate atmospheric pollutants with severe illnesses. The AFE reads out the output of eight conductometric sensor arrays and eight amperometric sensor arrays. The IC consists of a low noise potentiostat and associated 9 bits current-steering DAC for sensor stimulus, followed by the first order nested chopped ΣΔ ADC. The conductometric sensor uses a current driven approach for extracting resistance change of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage for measuring current out of the sensor after a chemical reaction. The core area for the AFE is 2.65x0.95 mm2. The IC is fabricated in 0.18μm CMOS process and achieves 91dB SNR with 1.32mW power consumption per channel from a 1.8 V supply. With digital offset storage and nested chopping, the readout IC achieves 500 μV input referred offset. In order to use the system with AFE as part of a compact badge with battery, the entire gas detection system has been designed in 3D layers with a bio sensor mounted layer, an AFE layer, power management layer, a micro controller layer, and battery.
Flip Chip Fine Pitch PBGA Yield Study
Authors: Pham Tim , Yeung Betty , Uehling Trent , Wilkerson Brett
Published: October 2015

With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.
Flip Chip for Image Sensor Packaging
Authors: Kim Deok-Hoon , Cho Young-Sang , Elenius Peter
Published: October 2015

The use of flip chip interconnects for image sensor packaging provides several unique challenges during packaging as well as benefits to the customer.

The principal challenges during assembly include the requirements of: no contamination of the image sensor during reflow, fabrication of a sealing structure to prevent future environmental contamination of the image sensor, and fabrication of a solder joint structure for the seal ring that can pass pre-conditioning. To achieve these requirements, the use of a fluxless solder reflow process and transient liquid phase (TLP) bonding will be explained.

Benefits to the customer for this type of flip chip image sensor packaging as compared to chip on board (COB) and thru silicon via (TSV) packages is a thinner camera module and versus TSV packages the ability to pass all required reliability tests without the use of an underfill. Reliability test results will be shown for thermal cycling, drop, and bending tests.
Low Profile Silicon Interposer using Passive Integration (PICS)
Authors: Bunel Catherine , Bellenger Stephane , Leruez Sebastien , Lenoir Lionel , Murray Franck
Published: October 2015

Thanks to their 3D structure, the Silicon Capacitors offer drastic improvements in terms of performances compared to the commonly used ceramic and tantalum capacitors. They are also a smart way to reduce the application volume and increase the IP protection level.

With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, IPDIA is offering for a large range of products, customized or standard components, a low cost packaging solution: the Wafer Level Chip Scale Packaging. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance. More than interacting on electrical functionality, WLCSP is interacting on mechanical and thermo mechanical properties with a higher miniaturization and a transfer directly on printed circuit boards without additional packaging steps.

This paper presents the main characteristics of the 3D-IPD advanced technology emphasizing on its capability and advantages versus discrete components illustrated by different applications using ultra-thin IPD ( down to 60 μm ) and WLCSP.
Silicon Interposers Enable High Performance Capacitors
Authors: Savastiouk Sergey , Marcoux Phil , Hewlett Jim
Published: October 2015

Thin film capacitors without TSVs have been used previously. However, with the interconnect inductance being high, benefits of thin film capacitors have not been fully realized. TSV interposers with embedded capacitors provide the shortest electrical path between devices and power supply decoupling capacitors. TSVs with their very low inductance interconnects thus will enable very high electrical performance when integrated with embedded thin film capacitors.

ALLVIA, on behalf of it's foundry customers, has been conducting studies of various capacitors on silicon interposers. The data presented in this paper shows after several thermal cycles that planar capacitors on silicon results in stable, reliable capacitors operating at very high frequencies. Unlike an issue of parallel resonance seen with chip capacitors, planar capacitors in interposers don't exhibit this property.
200mm & 300mm Processes & Characterization for Face to Back Flow Chart for Wide I/O
Authors: Cheramy Severine , Garnier G. , Jouve A. , Colonna J.-P. , Coudrain P. , Chausse P. , Segaud R. , Aumont C. , Hotellier N. , Brunet-Manquat C. , Laviron C. , Sillon N.
Published: October 2015

3D integration so far has often been investigated through a face to face point of view: the top die FEOL is in front of bottom die FEOL. This allows a dense connectivity between both dies, but TSV are mandatory on the bottom die for each external exchange.

Another flow chart, which main application is identified as the Wide I/O, is “face to back”: the FEOL of the top die faces to the back side of the bottom dies. To communicate between top & bottom, interconnections then TSVs are needed. Advantage is that the bottom die, for Wide I/O the logic dies, faces directly to the board allowing a rapid communication with external. Also, the Wide I/O interface delivers high bandwidth at relatively low power consumption level.

The objective of this paper is to show latest integration at Leti, both on 200mm & 300mm wafers, using face to back integration. If we compare both flow charts, using via middle technology, the main challenge consists of the temporary bonding. The temporary adhesive needs to be at least 50 μm thick, even more depending on staking technology on board, and in presence of the macro connection. The choice of the adhesive is crucial for the final stability of the stack during back side process and also during debonding, even more on 300mm wafers.

Technical developments are introduced in the paper. A specific focus is done on temporary adhesive & the associated thermal stability of the stack. Impact of the temporary bonding on copper pillar is evaluated. Assembly of best processes for a full integration on daisy chain wafers, both 200 & 300 wafers is described.

Finally, a comparison of electrical datas (resistance, capacitance, isolation) for both wafer diameters is given. Morphological characterization finalizes this first integration and leads to further potential improvements.
Thermal Cycling Analysis of BGA Solder Joint Reliability
Authors: Yeung Betty H. , Hauck Torsten , Wilkerson Brett , Koschmieder Thomas
Published: October 2015

The solder joint reliability of semiconductor package interconnects is critical to product durability. A dominant failure mode is solder fatigue due to the CTE mismatch between BGA component and PCB at thermal cycling. It is well known that besides thermal expansion mismatch of component and board, the solder joint geometry has a great impact on fatigue behavior and time to failure.

In this study, a combination of Surface Evolver and finite element analysis are use to predict the solder joint shapes for the assembly of medium pin count BGA's and to estimate the reliability at accelerated temperature cycling conditions. Results of Surface Evolver are compared with the assumption of a truncated sphere. The solder shape predictions are applied for a subsequent thermo-mechanical analysis of the BGA assembly. Inelastic creep deformation is evaluated for critical solder balls, and the Coffin-Manson relation is used to estimate the solder joint lifetime. The entire simulation procedure will be demonstrated for a product design study for high reliability automotive BGA's. A fractional factorial design is defined that considers solder sphere diameter and solder pad sizes on BGA substrate and on PCB side. Resulting creep values and lifetime estimates will be compared.
IC Package Route Planning Methodology Designs Better Products
Authors: Acito William , McCaleb Harry
Published: October 2015

As package design complexity increases, and design cycle times are increasingly subject to aggressively truncated timelines, the need to achieve efficient one-pass physical routing of complex, I/O dense, IC packages becomes critical. Critical high-speed interfaces such as DDR2, DDR3, PCI Express, and HDMI now constitute a high percentage of signals in an electronic package. This presentation will focus on utilizing an integrated route-planning tool to quickly and effectively plan the physical layout of package design interfaces, without the expenditure of time and dedication of resources required to perform traditional routing iterations. Route-planning allows package design teams to easily communicate with customers and other engineering teams to make intelligent trade-off decisions for layer usage, space allocation, Power Delivery Network (PDN) solutions, signal referencing and Die-to-Pkg netlist feasibility and optimization.
Performance of MEMS Vibratory Gyroscope under Harsh Environments
Authors: Patel Chandradip , McCluskey Patrick
Published: October 2015

Microelectromechanical systems (MEMS) gyroscope is a sensor that measures the rate of change in an angular position of an object. MEMS vibratory gyroscopes are increasingly used in applications ranging from consumer electronics to aerospace and are now one of the most common MEMS products after accelerometers.With advances in fabrication technologies, the low-cost MEMS gyroscope has opened up a wide variety of applications with environmental conditions ranging from medium to harsh. Despite their widespread use, the performance of MEMS gyroscopes in harsh environments is still under question. While some studies have been conducted to understand the effects of high mechanical shock, high frequency vibration and high frequency acoustic environment on the MEMS gyroscopes,the effects of sustained exposure to temperature combined withother harsh environment stresseshave not been well researched.Thus, it is necessary to quantify MEMS vibratory gyroscope performance under such conditions.This research reviews current harsh environment studies anddemonstrates the effects of an elevated temperature and sustained exposure to temperature combined humidity on the MEMS vibratory gyroscope. In order to quantify such effects, several tests have been performed. A short-term temperature effect on MEMS gyroscope was examined through temperature characterization test forfive thermal cycles at wider temperature ranges. A long-term temperature effect on the MEMS gyroscope was inspected through 500 thermal cycles; while, combined effects of temperature and humidity was studied through temperature humidity bias(THB) test and highly accelerated stress test (HAST).
Comparative Test Data for TIM Materials for LED Applications
Authors: Papanu Victor
Published: October 2015

Developments in thermal interface materials (TIMs) continue across the industry with a variety of different types of materials. Thermal and mechanical design engineers are often confronted with the need to select which type or category of TIM material is the most appropriate for a specific LED module application, which can be confusing, and how to determine which materials provide the best thermal performance. The next step is understanding which TIM material types meet requirements for ease of shipping, handling, placement, cost, and rework. These are important distinctions, in addition to thermal performance.

This presentation will illustrate comparative testing results for a set of thermal interface materials (TIMs) in different categories, using different TIM testing procedures. Test data prepared using three different test methods will be compared:1. ASTM D5470-06 with known temperatures and clamping forces;2. In-situ testing with industry-standard semiconductor modules, at known temperatures and estimated clamping forces;3. In-situ testing utilizing a thermal test vehicle (TTV) for TIM2 performance for a processor module.

In-situ testing has been performed at an independent power semiconductor manufacturer, using both industry-standard and commonly-available modules and a custom-designed module with a relatively small footprint, capable of high operating junction temperatures. This testing data can illustrate how different types of TIM materials perform in laboratory testing conditions, for precise comparisons on thermal performance alone; and how different types of materials perform in what are termed as “in-situ” test procedures. This term is used for application-specific conditions, where additional variables are encountered in the testing (such as non-flat surface conditions and unknown clamping force values), which is significantly different from the laboratory conditions used to generate ASTM D-5470 test values.

The comparative testing that has been undertaken will be described, showing that images of various power semiconductors with several different materials tend to correlate with the thermal resistance of materials measured with the ASTM D 5470-06 method. These thermal interface materials were also tested on a TTV supplied by a major processor module. The relevance of the thermal imaging, the TTV and the ASTM values will be discussed.

This presentation is intended to illustrate the differences in experimental data from one TIM material to another, as well as the differences in testing procedures.
Evaluating Thermal Cycling Fatigue Resistance for LED Chip-on-Board Applications
Authors: Bhatkal Ravi M. , Pandher Ranjit , Lifton Anna , Koep Paul , Fard Hafez Raeisi
Published: October 2015

LED chip-on-board applications typically involve assembling an LED die stack directly on to a high thermal conductivity substrate such as a Metal Core PCB. If solder is used for die-substrate attach for such chip-on-board applications, one needs to consider the CTE mismatch between the die stack and the MCPCB and its impact on thermal cycle-induced creep fatigue of the solder material. This paper presents a methodology to compare relative performance of different solder materials with varying thermo-mechanical properties, and compare the impact of CTE mismatch and temperature swings on transient thermal properties and relative reliability of the solder attach materials. Implications for LED chip-on-board applications are discussed.
The Evolution of LED Packaging: New Approaches for Solid State Lighting
Authors: Karlicek Robert F.
Published: October 2015

The rapid evolution of solid state lighting is driving rapid and innovative approaches to LED packaging. While the bulk of LEDs are still packaged using decades old technology, the cost and performance needs of solid state lighting are forcing the development of new light emitter packaging technology, some of it being imported from more conventional electronic packaging. Concepts like wafer level packaging, chip on flex technology and SIP technology are infiltrating the LED packaging landscape, but with innovations developing from the need to simultaneously manage input power, thermal dissipation and light extraction for energy efficient lighting. Lighting cost constraints are also driving new requirements for higher packaging speeds and LED integration directly into lighting fixtures rather than through the conventional die-to-package-to-board-to-system sequence. Finally, lighting system performance specifications like intensity, color quality, glare, and beam pattern, all dependent on how light moves from inside the die to the user, are forcing new system level requirements into the LED packaging arena.

This talk will discuss how the development and evolution of solid state lighting systems are working to drive innovation and evolution in the development of LED packaging materials, structures and methods. With the need for energy efficient lighting driving a rapid transition from bulbs and tubes to solid state devices, LED packaging is poised for a revolution where the conventional roles of semiconductor packaging are redefined in new and exciting ways that are needed to make solid state lighting a practical reality.
Low-Cost Adhesives for Temporary Substrate Support
Authors: Moore John , Pettit Jared
Published: October 2015

Temporary adhesives are a key part to 3DIC integration. Choosing the right adhesive is critical as it defines your process, tooling needs, and by virtue of its chemistry, will control throughput and yield. Although several products and tooling exist in the market, few offer a clear path to achieve HVM at an affordable cost. [1] A wide range in materials and processes are available, most which can be tailored to a specific design or tooling objective. Multiple options in adhesives allow grinding and polishing to <20um, protection during backside processing (e.g. TSVs), thermal resistance to >400C, [2] CVD acceptance (Fig. 1), and rapid removal with cleans on a film frame (Fig. 2). Using batch processing, throughput is increased by a factor of 5 while cost is reduced by 50%, suggesting a COO that is 10% relative to current practice. Instituting simple materials and processes matched to a customer's design will provide benefits beyond cost savings, including “green factory” certification. This presentation reviews several current practices in the market and contrasts these options with alternative low-cost adhesives and processes that are tuned to a customer's product design and tooling. Examples include excerpts from handling thin substrates in semiconductor, solar, and TFT/LCD fabrication lines.
Plating Opportunities in 3D
Authors: Uhlig Albrecht , Bera Holger , Jaeger Cornelia , Rohde Dirk
Published: October 2015

Through Silicon Via's (TSV) are one of the key enabling technologies towards 3D packaging. Copper electroplating is frequently mentioned as candidate to fill TSV's besides polySi or ink-jetting conductive inks and attracts high attention. In addition to copper plating solder plating offers the next opportunity. Last but not least the ultimate target of an “all wet TSV” where also barrier and seed layers are electroplated, was demonstrated already. This paper targets to introduce the 3D related plating technologies and will encourage a discussion about targets to be meet in order to enable 3D. Even so copper plating is well introduced to the IC industry for Dual Damascene plating, TSV copper filling challenges the plating technology. One of the reasons why is that TSV dimensions are almost one magnitude larger than dual damascene structures. So in order to meet the industries target of fast and void free copper filling, type and function of organic additives applied in copper plating bathes need to be re investigated. Galvanic copper electrolytes contain three organic additives.

Carrier is a mild plating suppressor, Brightener is an accelerator, and Leveler is a strong suppressor and locally deactivates the Brightener. The Leveler component mainly affects the properties of the copper deposits. This paper will give an overview about type and role of organic additives used for TSV application. We will also discuss how namely the Leveler controls the filling mechanism and copper deposit properties. Two different acidic copper systems were used for TSV-filling. System A shows a super-conformal filling behavior and different copper grain structures at the surface compared to the TSV body. System B shows a bottom-up filling with similar copper grain structure at surface and TSV body. Both systems vary further regarding stress of the copper deposits, recrystallization temperature, incorporation of additives, and coefficient of thermal expansion. The paper discusses the influence of organic copper additives to the mechanical, thermal, and electrical properties of the copper deposits. Even so process technology to fill TSV's is still fast progressing we like to give a snapshot of fill times per TSV dimension reached using System B. Other potential plating applications in 3D stacking are eventually plating solder and/or diffusion barriers. This paper intends to introduce the basic principles of electrochemical and electroless plating and give application examples for Tin and Nickel/Palladium electroless plated layers applied for 3D packaging applications. Last but not least the concept of “all wet TSV” appears in the literature, targeting to substitute the barrier and seed layer so fare deposited by vacuum deposition technology by plating technologies. We will shortly review the literature and will introduce work currently under progress in Atotech towards an “all wet TSV”.
Study of Factors Which Influenced to Bump Shape and Voids in Bumps during Bump Formation with Solder Paste
Authors: Ishikawa Masayuki , Uno Hironori , Yamaji Takashi , Uesugi Ryuji , Masuda Akihiro , Hirano Shingo , Mawatari Fuyumi , Tanaka Natsuko , Okada Kohki
Published: October 2015

Regarding to inner bump formation using solder paste for FC-BGA and FC-CSP, the voids and abnormal bump shape generation are undesirable problems to achieve high quality assembly. The solder pastes which contain small solder particle and flux are applied to wafer bumping and substrate bumping method. However, as the bump pitch becomes tighter, the influence of those problems gets more serious especially for yield issue.

In this study, we tried to solve the following issues 1)voids generation using 99.3mass%Sn-0.7mass% Cu solder paste and other alloys, 2)the dint bumps generation on the top of bumps using 95mass%Pb-5mass%Sn paste and 3)the needle and plate like intermetallic compound generation on the top and side of bumps using 96.5mass%Sn-3mass%Ag-0.5mass%Cu paste and 95.5mass%Sn-4mass%Ag-0.5mass%Cu paste.

In terms of 1), it was available to understand when and where voids were generated by in-situ soft x-ray observation, and we could construct our original consideration why voids were generated during bumping process. In terms of 2) and 3), it was found that some kind of impurities affected on the dint, needle and plate like IMC generation. Furthermore, we tried to understand from the influence of reflow profile.

By understanding these defects, we believe we can bring benefits to operating solder paste for printing method.
Proven Cleaning Technology Solutions for Lead-Free Micro-Bumping Processes
Authors: Pollard Kimberly D. , Gilbert Nichelle , Pfettscher Don , Hochstetler Spencer
Published: October 2015

Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them.

In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success.

In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.
Wafer-Level Bonding using Anisotropic Conductive Adhesive for 3D MEMS Applications
Authors: Tvedt Lars G. W. , Lietaer Nicolas , Bakke Thor , Redford Keith , Kristiansen Helge
Published: October 2015

As opposed to planar ICs, micro-electro mechanical systems (MEMS) are three dimensional structures with movable parts, membranes and cavities. Fragile movable structures are generally encapsulated inside a cavity by bonding a cap wafer to a MEMS device wafer. The use of through silicon vias (TSVs) in MEMS allows a significant miniaturization of the devices. TSVs through the cap wafer require an electrical connection between the TSVs and bond pads on the device wafer. This paper presents a novel bonding method that allows to do this in a simple and cost-effective way. We demonstrate the use of Benzocyclobutene (BCB) containing metal coated monodisperse polymer spheres (MPS) as an anisotropic conductive adhesive (ACA) for wafer-to-wafer bonding. The technology is demonstrated by bonding glass cap wafers with cavities and a patterned metallization to silicon wafers with a patterned metallization. The ACA is spray-coated onto the cap wafer and the bonding is performed in vacuum at 250 °C for 60 minutes with 300 mbar pressure applied. The electrical performance is evaluated using daisy-chain and kelvin structures, and the bond strength is verified by shear testing. Variations in bond frame size, contact area and minimum distance between conductor lines are investigated. Four wafers with a total of 880 dies are electrically tested. An average resistance of34 ±14mΩ is obtained for a contact area of 300 × 300 μm2 and 78 ±55 mΩ for 200 x 200 μm2. Daisy chains with 16 contact areas have a yield of 98 % for a 300 × 300 μm2 contact area and 95 % for 200 x 200 μm2. The technology is expected to be scalable to smaller contact areas by increasing the amount of MPS in the BCB. An average bond shear strength of 36 ± 9MPa is measured.
TGV Microfabrication Technology for 3D Packaging
Authors: Takahashi Shintaro , Schmidt Christian , Dittmann Leander , Hoyer Svend , Chaize Adrien , Ono Motoshi , Kitaoka Kenji , Tatsukoshi Kentaro , Konishi Shoichi
Published: October 2015

Glass is expected to be applied to a core material for panel size interposer for 3D package system nowadays. The most important challenge for glass as an interposer is the development of through hole formation with cost-effective and high-throughput. Several through hole drilling technologies such as wet etching, deep reactive-ion etching, sandblasting, laser ablation and the use of photosensitive glass have been studied and reported so far. However, the glass microfabrication technology combining both high-throughput and large area processability have not been reported yet.

This study explored the new glass fabrication method by means of electrical discharge to realize high throughput and fine pitch hole drilling. An alkali-free glass substrate was used. Focused and controlled electrical discharge induced dielectric breakdown of glass material and also created Joule heat induced ablation and ejection of glass. Approximately 50 – 60 micron in diameter through hole was made. The result shows, even serial process can have a potential for high high-throughput solution, because this phenomenon can complete as an ultrashort process time of 1msec or less. In terms of fine pitch processability, 100um pitch hole drilling was confirmed.

In this study, several glass fabrication technologies were compared by SEM and optical microscope observation for hole shape characteristic. Additionally a potential of industrialization and fine pitch hole drilling were considered. This study pointed out necessary development subjects towards an application, glass core material for 3D interposer substrate.
Development of Substrates for Through Glass Vias
Authors: Shorey Aric , Pollard Scott
Published: October 2015

Through-substrate vias are critical for 3DS-IC integration. The choice of glass as an interposer substrate, TGV, present some interesting challenges and opportunities, making glass a compelling alternative to silicon.

There are two primary challenges to begin building a precision interposer in thin glass. The first is high quality thin glass wafers (300 mm OD, thickness 0.05 to 0.10 mm, warp and TTV of 30 μm and 1 μm respectively). The second challenge is developing a process capable of providing small (5–10 μm) precision vias in a cost-effective way.

“Glass” represents a large class of materials with a wide range of material properties. The first step in developing TGV is to identify the most appropriate glass composition for the application, which furthermore defines important properties such as coefficient of thermal expansion (CTE) and other mechanical properties, chemical durability and electrical properties.

The manufacturing process used to develop the glass has a significant impact on quality and manufacturability. Fusion formed glass provides a solution for high volume manufacturing supply in an as-formed, ultra-thin, pristine glass manufactured to tight tolerances, and avoids the issues associated with polishing or thinning. The supply of 50 μm to 100 μm as-formed ultra-thin glass wafers can compare very favorably in cost relative to polished or thinned glass as well as thinned silicon wafer.

While there are many technologies that have demonstrated vias in glass, challenges relating to via size and pitch, wafer strength and reliability remain to be resolved. However, substantial progress has been made to meet these challenges. Specific characterization data from some of these processes to demonstrate vias on the order of 10 μm diameter with a 100 μm glass thickness in alternative glass materials will be presented.