(Invited) Advanced Plated Cu Metallization for Hybrid Bonding and 3D Interconnects
Authors: Aizawa Ryo , Shiina Urara , Nampo Jinta , Sawa Masahiro , Ohno Akinobu , Murugesan Mariappan , Fukushima Takafumi 
Published: December 2024

Semiconductor packaging has been developed to meet the requirement of high-density input/output terminals and downsizing. For further high performance and functionality, the research and development on System in Package (SiP), which achieves interconnection between heterogeneous devices in a package, goes on. There are various packaging configurations suggested, such as 2.1D SiP and 2.3D SiP using organic substrates, 2.5D SiP using Si substrates with TSV, and 3D SiP using TSV with microbump or Cu-SiO2 hybrid bonding [1][2][3]. Hybrid bonding using Cu-Cu direct bonding technology is gaining greater momentum owing to its ability to form the ultra-scaled interconnection at much reduced pitches below 5 µm. While improving the quality of Cu-Cu bonding plays a critical role in enhancing the performance of 3D SiP, reducing the resistance of Cu-Cu junctions is one of the most important strategies. Therefore, the additive chemistry for plated Cu plays a significant impact in advanced 3D packaging.

In our recent study, we succeeded in making large Cu grain at low temperature, which shows good physical properties by controlled Cu grain size and orientation We defined plating solution A as the low crystal growth process and solution B as the high crystal growth process. Fig.1 shows the SIM images of the cross-section of Cu pretreated with FIB; it was indicated that Cu film plated with solution A shows a grain size under 2 µm, while solution B shows a grain size over 5 µm. Plated Cu with large grains showed high electrical conductivity and thermal conductivity. We concluded that the results are due to the large Cu grains exhibited less grain boundary than polycrystalline Cu having various orientations; therefore, the large grains are appropriate as an interconnecting material [4]. Additionally, we applied the large Cu grains to Cu-SiO2 hybrid bonding and confirmed quite low electrical resistance. We demonstrated that the interface of Cu bonding plated with solution B showed large Cu grains, and Cu crystal orientation of the top and bottom are identical compared with solution A.

On the other hand, it is also important to control oxidation since copper oxide film is expected to affect electrical properties in Cu-Cu direct bonding. Therefore, we have investigated the dominant factors that affect the oxidation of plated Cu. Generally, the oxidation reaction of Cu first produces the monovalent Cu ion Cu+, which undergoes CuOH to form a cuprous oxide Cu2O film on the Cu surface. When exposed to an oxidizing environment, cupric oxide CuO is grown. The thickness of copper oxide film formed after annealing at 150 degrees Celsius for 1 hour was measured by the sequential electrochemical reduction analysis (SERA) method, which is capable of distinguishing CuO and Cu2O. Consequently, the copper oxide film grown after annealing mainly consisted of Cu2O, and we have confirmed that the thickness of Cu2O was highly related to additive factors such as concentration and molecular weight. For instance, it was increased logarithmically with increasing molecular weight of polyethylene glycol (PEG), a commonly used suppressor in acid plating solution. The concentration of the brightener showed a proportional relationship to the thickness of Cu2O, and the charge density of the levelers was one of the most significant factors affecting the oxidation of plated Cu among the factors examined in this study. Further evaluation of how additives in the plating solution affect oxidation and its applications, such as Cu-Cu bonding, will be presented at the conference.

References

[1] T. Shirasaka, T. Okuda, T. Shibata, S. Yoneda, D. Matsukawa, M. Mariappan, M. Koyanagi, and T. Fukushima, “Comprehensive study on advanced chip on wafer hybrid bonding with copper/polyimide systems,” ECTC 2022 Proceedings pp. 317-323, 2022

[2] M. Murugesan, K. Mori, E. Sone, M. Sawa, M. Koyanagi, and T. Fukushima, “Cu-SiO2 hybrid bonding yield enhancement through Cu grain enlargement,” ECTC 2022 Proceedings pp. 685-690, 2022

[3] T. Fukushima, Y, Yamada, H. Kikuchi, and M. Koyanagi, “New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration,” Japanese Journal of Applied Physics, 45 pp. 3030-3035, 2006

[4] M. Sawa, “Acid copper plating in surface technology,” Journal of The Japan Institute of Electronics Packaging, Vol. 25, No. 3, pp. 196-203, 2022

Figure 1