bluuebunny/crossref_metadata_2025 huggingface dataset:
Novel Polymeric Protective Coatings for Hydrofluoric Acid Vapor Etching during MEMS Release Etch
Authors: Tang Tingji , Planje Curt , Trichur Ramachandran K. , Zhong Xing-Fu , Fowler Shelly , Xu Gu , Yess Kimberly , Shao Xie , Vestyck Daniel J.
Published: October 2015

Micro-electro-mechanical system (MEMS) is rapidly becoming a critical part of advanced fabrication technology such as cellular phones, micromirrors, radio frequency (RF) devices, microprobes, and pressure sensors. Release etching of a sacrificial layer of silicon oxide plays an important role in creating the moving parts during these MEMS device fabrication. Traditionally, wet fluorinated etchants have been applied in order to achieve release etching, by which liquid surface tension can cause the MEMS microstructures to stick together (“stiction”) upon removing from aqueous bath or during the drying of released wet-etched structure. It has been demonstrated that using a hydrofluoric acid (HF) vapor release etch can efficiently circumvent stiction phenomena owing to the fact that it substantially eliminates the surface tension that causes the stiction. Conventionally, inorganic based films such as silicon nitride, alumina, SiC, polysilicon, amorphous silicon, and aluminum etc were used as vapor HF etch-resistant mask materials, which require very high temperature and vacuum deposition techniques often lengthy, complicated and costly. Herein, a novel spin-on and polymeric blanket HF-resistant coating material is presented to provide protection of both silicon oxide and aluminum against HF attack during vapor HF etching. Our newly developed polymeric coatings can be processed at lower temperature (<250 °C) and thinner films (less than 10μm) for extended vapor HF etching period (longer than 1 hour). Hence, our vapor HF resistant materials will enable the MEMS industry to significantly lower the cost of manufacturing MEMS devices and will significantly simplify the manufacturing process as well.
Enabling Thin Wafer Metal to Metal Bonding through Integration of High Temperature Polyimide Adhesives and Effective Copper Surface Cleaners
Authors: Rardin Anthony B. , Kirk Simon J. , Zussmann Mel P
Published: October 2015

This paper will examine the use of high temperature Polyimide temporary adhesives and advanced copper cleaning solutions for thin wafer handling during metal to metal (Cu-Cu) bonding. In the case of Cu to Cu solid state diffusion bonding, temperature requirements can be up to 400C for as long as 40 minutes. These extreme conditions pose a significant challenge with existing materials used for temporary bonding.

Polyimides are ideally suited for high temperature application and polyimide adhesives have been developed which can withstand 400°C processing without significant failure in adhesion. As well, Cu to Cu bonding processes will require the need for contamination free surfaces, which becomes increasingly important if lower temperature processes (<400C) are desired. Close-coupled copper cleaning immediately prior to the bonding step offers an excellent approach for providing process reproducibility while achieving increased electrical yields. Utilizing advanced wet cleaning solutions to obtain optimal Cu surface preparation through the removal of undesirable copper oxide layers as well as organic contaminants such as Benzotriazole (BTA) is also discussed in detail.
Micro IMU Utilizing Folded MEMS Approach
Authors: Rivers Montgomery C. , Trusov Alexander A. , Zotov Sergei A. , Shkel Andrei M.
Published: October 2015

In this paper, we propose a novel wafer-level approach for fabrication and 3-D integration of MEMS devices in miniature multi-axis assemblies of inertial, acoustic, and optical sensors. The approach is based on simultaneous fabrication of all sensors on the same substrate connected by flexible electrical interconnects, mechanical hinges and latches. A multi-axis sensor system is then obtained by folding the fabricated structures into 3-D cubes, pyramids, or other rigid shapes, and subsequently micro-welded. In the current work, we demonstrate feasibility of the folded cube approach for creation of miniature MEMS IMU with <1 cm3 volume.

Design of the IMU consists of a folded cube or pyramid backbone structure with micromachined accelerometers and gyroscopes on its sidewalls. Silicon-on-insulator (SOI) wafers are used as a substrate for fabrication of both the inertial sensors and the folded backbone structure. Fabrication of the sensors consists of lithography, deep reactive ion etching (DRIE), and HF acid release of the inertial proof masses. Flexible polymer hinges connecting faces of the folded structures are defined on the same substrate and incorporate electrical interconnects. To provide rigidity to the assembled 3-D structure, interlocking silicon latches are fabricated along the edges of each sidewall, which are silicon-to-silicon welded after assembly.

The approach allows for creating miniature multi-axis sensor systems without compromising performance of individual sensors. Gyroscopes integrated in the current folded cube IMU have experimentally demonstrated 3-dB bandwidth of 250 Hz and angle random walk (ARW) below 0.1 (deg/s)/rt-Hz in atmospheric pressure. Measured uncompensated temperature coefficients of gyroscope bias and scale factor were 313 (deg/h)/degC and 351ppm/degC, respectively. Accelerometers on the cube have been characterized, yielding a noise floor of 570μG/√Hz. Sensitivity of the accelerometers is measured at 40mV/G with a bandwidth of 100 Hz.
Challenges Facing Resonant MEMS Sensors
Authors: Kranz Michael
Published: October 2015

Many MEMS/NEMS sensors, including gyroscopes, chemical sensors, and RF filters utilize the mechanical resonance of the MEMS/NEMS structure as a highly sensitive detector. Typically, changes in the external environment lead to changes in the resonant frequency or amplitude. Due to the low-loss of micro and nano mechanical structures, large quality factors are achievable, leading to sharp resonance curves that change greatly after only small changes in the environment. This allows sensitive detectors, but also leads to poor stability and tight fabrication tolerances. This paper will discuss these issues as well as mitigation techniques including feedback control, tuning, differential operation, and sensor fusion, amongst others.
Boron Nitride in Thermoplastics (for LED Housings)
Authors: Rappelt Thomas , Raman Chandrashekar
Published: October 2015

Boron nitride (BN) is increasingly being used as a filler in thermoplastics, primarily to increase the thermal conductivity of the resins. Filler-reinforced plastics are being considered to replace traditionally metal parts in a number of markets, with applications such as under-hood automotive parts, sensors and housings for motors, LEDs, and other electronic devices.

When BN powders are used as fillers in resins, the BN-resin composite materials also demonstrate anisotropic properties, largely determined by the orientation of the platy BN crystals in the final part. To overcome this problem of anisotropy, boron nitride powders have been developed which are agglomerates of single crystal. In such agglomerate grades, platy BN crystals are held together to form a larger particle to randomize their orientation. Such BN powder grades, broadly called agglomerate grades, demonstrate more isotropic properties than do single crystal BN grades.

One of the biggest challenges of using agglomerate BN grades is to preserve the structure through all the processing steps. In the case of thermoplastics, the BN agglomerates can break down during the extrusion step and/or the molding step. Both the screw configuration during extrusion and the flow configuration during molding determine the extent of shear of the BN agglomerates.

The thermal conductivity of single crystal platelet and agglomerate boron nitrides in a thermoplastic resin is examined in this paper to consider and explain the effect of particle morphology. The anisotropic properties will be characterized on BN-plastic composite parts. The effect of screw configuration during extrusion and molding conditions on the thermal conductivity and other physical strength properties will also be examined and the trade-offs will be discussed.
Polyamide 4T: A New Lead-Free Solderable Polymer Enabling Packaging Technology Through Micro Molding and LDS
Authors: Sidiki Tamim
Published: October 2015

The continuous trend towards convergence and miniaturization is recently generating significant interest in new technologies for Electronics. This requires the integration of Semiconductors and Magnetics, two entirely different industries with different players in the value chain. In this paper, we demonstrate, a packaging technology which allows three dimensional stacking of Magnets and Semiconductors. We realized the integration of a Semiconductor chip - which provides protection against electro static discharge (ESD) – and a common mode filter (CMF) into one thermoplastic package. For the first time ever, this filter is integrated directly into the thermoplastic part which is used as the substrate, filter and housing at the same time. Laser direct structuring in combination with Stanyl® ForTiiTM as an ultra high performance, entirely halogen-free high temperature thermoplastic omits any wires for the realized coil, and also facilitates high flexibility in design and manufacturing, allowing ultra small footprints and the realization of components suitable for surface mount technology. As an example of this new technology, we demonstrate a component which can provide full ESD protection and common mode filtering for a high speed USB2.0 interface.
Analysis of Silicon Micromachining by UV Lasers, and Implications for Full Cut Laser Dicing of Ultra-Thin Semiconductor Device Wafers
Authors: Hooper Andy , Finn Daragh
Published: October 2015

3D packaging technologies such as FLASH rely on die-to-die stacking of ultra-thin silicon devices with individual die thicknesses below 100 um. Because ultra-thin silicon wafers are very fragile, mechanical saw dicing of sub 100 um thick wafers tends to be more challenging, requiring slower processing and reduced throughput and/or yields. These challenges make full cut laser dicing an attractive solution. This presentation provides an investigation for machining of 50 um thick silicon wafers using a Gaussian-shaped, nanosecond pulsewidth, 355 nm UV laser. A range of machining speeds and laser fluences are compared, from single laser pulses to highly overlapped slow-velocity machining. 3D Laser Scanning Microscope and FIB/TEM cross sections are employed to characterize the state and depth of heating damage into the Si material. Implications for laser machining rates and die break strength are investigated for full cut laser dicing.
Bimorph Diaphragm Formed by Two PZT Sheets on Micromachined Silicon for Sound Generation
Authors: Choe Youngki , Chen Shih-Jui , Kim Eun Sok
Published: October 2015

This paper describes a microspeaker (composed of a mechanically-polished PZT bimorph diaphragm and bulk-micromachined silicon top cover) that shows flat diaphragm displacement from DC to 16kHz. A bimorph diaphragm is formed by gluing two 127μm thick PZT sheets and attaching them to a micromachined silicon substrate. The front-side pre-deposited nickel electrode was patterned to maximize the stress distribution over a diaphragm with its four edges clamped, when it goes through bending displacement. With un-patterned floating electrode on one side of the diaphragm, the PZT bimorph can generate stresses with opposite signs along the thickness direction without the need of fine alignment among the electrode patterns. It is important to reduce the thickness of the glue layer between the two PZT sheets, in order to maximize the electrical fields inside the PZT sheets, since the glue layer takes some of the applied voltage away. With mechanical polishing and spin-coating of low viscosity resin epoxy, we have been able to reduce the glue layer thickness to about 1 μm with variation less than 0.5 μm from a typical 25μm thickness. The microspeaker with an encapsulating cylindrical package of about 0.5 cc inside volume produces sound pressure level (SPL) of 103.6 ~ 110 dB between 1.3 and 12 kHz when measured 5 mm away from the diaphragm with 190Vpeak-to-peak driving signal. The measured SPL drops as the frequency is reduced below 1 kHz, due to increasing wavelength and thus reduced total acoustic intensity over the measurement area. The diaphragm was measured (with a laser vibrometer) to produce uniform displacement from DC to 16kHz. With 190Vpeak-to-peak sinusoidal input, the displacement at the center of the diaphragm was measured to have 1.86μm displacement at the fundamental resonant frequency of 16.2 kHz.
3D Passive Integrated Capacitors Towards Even Higher Integration
Authors: Gaborieau Sophie , Bunel Catherine , Murray Franck
Published: October 2015

IPDIA is involved in Silicon based 3D-IPD advanced technology. This very flexible technology is using standard processing techniques to integrate passive components such as inductors, resistors or capacitors into a silicon substrate.

3D high-density capacitor is at the forefront of IPDIA development program. First process generation with 25nF/mm2 and second generation reaching 80nF/mm2 have been in production for several years. The third generation with multiple metal-insulator-metal (MIM) layer stacks in the pores is reaching 250nF/mm2 and is being qualified now.

Intrinsic low parasitic elements of these capacitors (low ESR and ESL) make it very attractive for DC decoupling and very competitive with the ceramic technology. Assembly can be performed using standard reflow soldering and its low profile also allows PICS capacitor integration in embedded module board technology. Sensors, healthcare and medical applications can benefit from this new development.

To enable even higher integration, development activities are now focused on the third and fourth generation of high-density capacitors targeting ambitious 1μF/mm2.

In this presentation, main characteristics of the PICS high-density capacitors will be described emphasizing on its capability, main applications and advantages versus discrete components. Then, in a second part, challenges raised by the increase of the capacitor density while keeping an acceptable breakdown voltage will be discussed. This includes the integration of high-k materials with adequate electrode and the research for maximizing the 3D silicon surface.
High Directivity Couplers using Multilayer Organics (MLO)
Authors: White George , Valayil Minu , Russell Charlie , Dalmia Sid
Published: October 2015

This paper presents the design and fabrication of a stand-alone high directivity coupler using high dielectric constant multilayer organic (MLO) technology. MLO is a low cost high density interconnect technology that allows for the realization of high Q and low loss inductor and capacitor elements that allow for the miniaturization of RF and mixed signal circuits. Q values above 300 have been measured for MLO with costs being lower than both LTCC and TFOS technologies. Low-loss lumped and distributed elements were realized using a novel multilayer build up process that supports both land grid array (LGA) and edge terminations. The couplers which support frequencies between 700 MHz and 2GHz exhibit coupling coefficients above 20db and isolation greater than 40db. The couplers can be combined with low pass harmonic filters in the same technology.
3DIC & TSV Interconnects: Applications, Market & Infrastructure Readiness
Authors: Baron Jerome
Published: October 2015

ABSTRACT TO COME.
Can High Density 3D Through Silicon Stacking Replace Lithography-Driven CMOS Scaling as the Engine for the Semiconductor Industry?
Authors: Nowak Matt , Henderson Brian
Published: October 2015

High density 3D Through Silicon Stacking (TSS) offers opportunities for form factor miniaturization, cost reduction, and performance and energy improvement for advanced semiconductor systems. We will explore the value propositions for TSS compared to CMOS scaling to consider if TSS could replace lithography-driven CMOS scaling as the engine for the semiconductor industry. TSS can provide major reduction in volume form factor compared to 2D CMOS scaling. As the industry moves to advanced lithography and complex device structures at 16nm and below, the cost improvement resulting from CMOS scaling is expected to diminish. The cost reduction opportunities of TSS compared to traditional System on Chip (SOC) solutions enabled by lithography-driven CMOS scaling will be explored. The realized technology value propositions are strongly dependent on the specific system architecture and application. Architectural and software innovation enabled by HD 3D TSS and Architectural Pathfinding could provide an additional vector for continuing the improvements from semiconductor miniaturization.
Flexible Metamaterials RF Filters Implemented through Micromachining LCP Substrates
Authors: Richard Jonathan , Dean Robert
Published: October 2015

Metamaterials have a wide range of potential uses in areas such as optics, transmission lines, and RF design. The simplest metamaterial structures are Split-Ring Resonators (SRR) and Complementary Split-Ring Resonators (CSSR). Through the combination of various forms of these structures, different applications in the areas previously stated can be achieved. Under this investigation, a metamaterials transmission line was realized through micromachining a Liquid Crystal Polymer (LCP) substrate. Not only does LCP possess useful RF properties, it can also be easily micromachined. This transmission line consisted of several CSSRs in series, which performed as a high-order, high-frequency high-pass filter. This structure was unique to most metamaterial structures because LCP is a flexible substrate. It was observed that the resonant frequency of the filter did not change when the LCP transmission line was flexed in various ways. Next, micromachined vias were etched through the LCP substrate to demonstrate that these features do not affect the filter's response. Through utilization of these vias, the metamaterial structures can be physically conformed to nearly any shape or mounted onto another object without affecting the filter's response. As demonstrated in a simple filter structure, the shape manipulation has very little effect. Theoretically, extrapolating these methods to the development of metamaterials 3D RF invisibility cloaks, that are easily realizable and mountable onto an object, could prove useful.
3D Transmission Line Design for High Power RF Components in Laminates
Authors: Kim Sungjun , Zhang Arthur Yang , Bachman Mark , Li G. P.
Published: October 2015

High power (> 30 dBm) RF components such as switches, passives and RF MEMS can be embedded in an advanced 3D package in laminates. We report a novel transmission line and interconnection design for these embedded high power devices. Typical RF signal path consists of input signal lines (microstrip sand coplanar waveguides), interconnections between laminate layers, and RF devices. 3D configurations of multiple buried via holes are first simulated in the HFSS environment and then tested on laminate prototypes for optimized RF performance. Loss points are carefully identified and removed in the design by distributing RF current in a network of interconnections. Extra cooling considerations are included to significantly reduce thermal stress on the system as well as individual components. The final transmission line design can supply over 50 W of RF power into a 12 layer laminate system.
High-speed SnAG Solder Electroplating Process and Developments on Cost Reduction
Authors: Forman Bob
Published: October 2015

The use of wafer level packaged ICs with Lead (Pb) free Tin Silver (SnAg) solder bumps is prevalent in consumer electronics. One method of making these bumps is by electroplating. The current process requires the use of a complex and expensive, single use chemistry. These chemistries do provide smooth, void free bumps, but with a very high Cost of Ownership (COO). Up to now these chemistries were expensive to operate, mainly because they are used for a short time and then disposed. This paper will discuss a new process using chemistry that provides improved COO by incorporating higher plating rates with recycling of used chemistry. With this process it is possible to recover nearly 100% of the metals, acids and organic agents previously discharged as waste. The recovered chemistry is then processed and certified to be reused in the originating fab, resulting in virtually zero waste. In addition to closed loop recycling, the process also forms bumps at a higher rate, by plating at higher current densities, with no trade-off in bump performance.
Through Package Defect Localization by Lock-In Thermography
Authors: Schlangen Rudolf , Deslandes Herve , Toda Toru , Nagatomo Toshinobu , Sako Shigeki , Sawaya Hiromichi
Published: October 2015

Root cause analysis for package defects is currently performed by de-processing the package until such defects can be physically seen. However, many such defects within the package are removed, or are confused with defects created during de-processing itself. 3D X-ray has been used to analyze such physical defects within a packaged device in a non-destructive manner. However, the increasing density and associated shrinkage of components such as multi-layered substrates require significantly higher resolutions, which translates to longer times. High resolution X-ray is impractical when searching for a defect over a wide area due to the time to acquire detailed 3D images (~24 hrs).

Thermal emission analysis has been widely used for localizing defects on ICs. Recent advancement in thermal emission camera technology coupled with lock-in thermography has allowed orders of magnitude better sensitivity ( < 1μW) and improvement in localization resolution (x,y to < 3 um). However, the application of lock-in thermography has been primarily limited to defect localization at the die level [1]. A a highly sensitive MWIR camera combined with a real time lock-in technique demonstrates the capability to localize defects within packaged devices, even through its mold compound. The technique accurately predicts the depth (z) of a thermal defect within the device (< + 5%)

This paper will demonstrate multiple examples of the successful combination of advanced lock-in thermography analysis and high resolution 3D X-ray for totally non-destructive defect location within a packaged device. This initial accurate thermal localization in x, y and z enables the high resolution 3D X-ray system to focus analysis to a few microns so that the defect can be seen quickly (< 1 hr), enabling detection and analysis of previously undetected defects with highest throughput.
3D-TSV Test Options and Process Compatibility
Authors: Smith Ken , Hanaway Peter , Jolley Mike , Gleason Reed , Strid Eric
Published: October 2015

3D-TSV stacking with non-reworkable bonding processes implies known-good die screening with high test coverage to be economical.Depending upon the stack architecture, the need to contact TSVs directly or TSV bonding pads during wafer test ranges from minimal to mandatory. An example of minimal need to contact is a low-power logic or memory chip powered and tested through a small number of test pads for scan chains or built-in self-test (BIST) signals. Examples of mandatory TSV pad contact during wafer test include power delivery pins (up to thousands), analog or RF I/Os, stacked logic functions, or more complex requirements.With appropriate design, test throughput (and therefore test cost) can dramatically benefit from contacting the many more I/Os available at the TSVs or TSV pads, just as the speed of the stack benefits from the many more I/Os when in mission mode.Probes and probing processes that touch TSVs and thin pads with minimal forces and pad marking are described herein. Feasibility of tip forces ~1 gram or less and very low pad damage are demonstrated at 40 micron array pitch. The lithographically printed probe structures are scalable to even smaller pitches, and fabrication costs scale by probe area, not by pincount.The degree of pad marking from probe tips depends on pad material choices. A non-oxidizing metal surface, such as ENIG, requires <0.1 gm for good contact, thus disturbing the surface so little that marks are difficult to detect. By contrast, a Sn surface requires ~1 gm for low and consistent contact resistance.

Probe contacting at TSV pitches is practical with evolutions of existing probe technology, and enables test strategies which probe some or all of the TSV pads, whether on the face or back of the wafer.
Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates
Authors: Lewis Brian J. , Baldwin D. F. , Houston P. N. , Smith B. , Kwok P. , Mueller J. Thompson. A. , Racz L.
Published: October 2015

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements.

The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.
Cu Pillar Bumping Technology with Solder Alloy Versatility
Authors: Burgess Guy , Curtis Anthony , Nilsson Tom , Stout Gene , Tessier Theodore G.
Published: October 2015

There is considerable interest in the semiconductor industry regarding Cu pillar bumping for finer pitch flip chip and 3D packaging applications. A common Cu Pillar method of production incorporates a combined Cu plated post topped with a plated solder pillar cap, usually of a Sn or SnAg alloy. Compared with this, a unique method of Cu pillar bump production developed at FlipChip International, LLC (FCI) creates the solder cap by applying and reflowing a solder paste on top of the plated Cu post. This method of production offers several benefits; the most important include a broader solder alloy selection, better alloy control, and improved overall pillar height uniformity. FCI has qualified a wide range of Cu pillar bump sizes, heights and shapes including Cu pillar bumps for fine pitch applications as low as 35um pitch (NANOPillarTM). FCI's Cu pillar bump structures in overmolded SiP have passed JEDEC 22-A104C board level thermal cycle testing, JEDEC J-STD-20A MLS 3@260C, as well as other board level corrosion and shock testing. FCI has demonstrated capping Cu pillar bumps with a broad range of solder alloys tailored to specific application requirements.
Electromigration in Solder Joints for High Temperature Flip-Chip Application
Authors: Nowottnick Mathias , Fix Andreas
Published: October 2015

The electromigration effects in chip metallization and wire bonds are well known and detailed investigated. Current density could be extremely high because of the small size of the cross sectional area of conductors. This can cause a migration of metal atoms toward the electrical field, so current densities up to 106 A/cm2 are possible. In comparison with chip structures are the usual solder joints of flip chips relatively thick. But the homologue temperature of solder alloys, typically based on tin, is also much higher than for gold or aluminum wires. For instance a SAC solder alloy is naturally preheated up to 0.6 homologue temperature, for high temperature application with 125 °C operating temperature even more than 0.8. This means, that atoms are very agile and a directed movement needs only lower field strength. Additionally is the specific resistance of solder alloys tenfold higher than for aluminum, copper or silver. So is the self-heating of solder joints not negligible. This contribution shows the test results of flip-chip assemblies, loaded with different current densities and stored at 125 °C ambient temperature. At the end of life of a significant number of test chips, a metallographic analysis shows the causing failure effects and weak spots of assemblies. Accompanying simulations help to explain the interaction between current density and migration effects.
3D Packages with TSV Silicon Interposers
Authors: Kelly Mike
Published: October 2015

This paper presents the development status overview for large die assembly of 3D packages with TSV bearing silicon interposers and logic devices at Amkor Technology. Combining discrete silicon devices and their attendant functionality onto a silicon interposer has garnered a great deal of interest in the high performance community, driven by considerations such chip to chip bandwidth, lower latency and even lower power. Interposers with silicon fab back-end routing density and new ultra fine pitch copper pillar joining techniques promises to offer a timely performance stepping stone for high performance devices, who in some cases are now finding that the incremental performance benefit from advancing transistor performance alone is less that gratifying. The design motivations and tradeoffs for taking this bold step are reviewed and their influence on assembly technologies. Assembly process and supply chain alternatives to achieve this offering are reviewed and discussed. Technical process development challenges along the way are briefed, as well as the materials selection criteria and reliability testing results.
Advanced 3DIC Die Stacking for Memory and Mobile Applications
Authors: Hiner Dave
Published: October 2015

This paper presents the developmental progress and status for the assembly of multi-die, stacked 3D IC packages. Die stacking with TSV technology represents a critical path for future memory and mobile devices. The assembly of these complex stacks involves the extension of existing methods combined with the development of advanced backside wafer finishing. Assembly options including memory to logic, 2+memory to logic, and 2+memory configurations will be reviewed, including perspective assembly methodologies. Alternative assembly methodologies including die to die, die to substrate and die to wafer will be reviewed.
Diatom-based Sensors: Organic/Inorganic Interfaces and Health Science Application
Authors: Goryll Michael , Wang Xiaofeng , Ramakrishnan Shankar , Lin Kai-Chun , Rege Kaushal , Dey Sandwip , Ramakrishna B. L.
Published: October 2015

Nanopore membranes exhibit tremendous potential for applications such as molecular filtration and DNA sequencng studies. However, the large-scale manufacturing of these nanopore membranes using MEMS technology is challenging, requiring slow serial electron or ion-beam patterning. Marine diatoms on the other hand feature biomineralized silica shells with the smallest pore diameters being 40 nm. Their hierarchical pore architecture makes these nanomembranes exceptionally mechanically stable. Moreover, the nanopores are homogeneous in size and have a low aspect ratio, enabling fast diffusion-driven transport.

The drawback of the biomineralized structures is that they are single entities, which have to be combined with a support structure to integrate them into a microsystem. Our solution consists of immobilizing the biomineralized structures on silicon substrates. With the diatom shells growing up to 200 μm in diameter, they are easy to manipulate on the oxidized silicon surface. Through-wafer via holes with diameters between 5 μm and 30 μm were etched using a dry etching technique to allow free access to the bottom of the immobilized diatom shell. Two pathways towards immobilization of the diatom shells were used, one being a chemical linkage approach using poly-L-lysine and the other involving UV-polymerizable epoxy. Controlled etching of the silica structure has been employed to manipulate both the dimensions of the nanopores as well as the pore hierarchy.

Studies of transport phenomena were carried out after mounting the silicon chip in a fluidic chamber with reservoirs for aqueous solution on either side of the chip. Electrical contact was made via Ag/AgCl electrodes and the transmembrane current was measured by a transimpedance amplifier. Results on our transport studies based on size and chemical considerations will be presented for ions, such as potassium and sodium, present in physiologically relevant isotonic buffers, polystyrene nanobeads and gold nanoparticles.
Realization of Power Modules by Chip Embedding Technology
Authors: Boettcher Lars , Manessis D. , Karaszkiewicz S. , Ostmann A.
Published: October 2015

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies.

This paper will briefly discuss the necessary process steps of the embedded chip technology, which is based on printed circuit board manufacturing processes, and will also demonstrate the transfer of the technology from a smaller size lab scale equipment environment to an industrial comparable process line, capable of processing large panel formats up to 18” x 24”. The paper will also briefly describe this development and categorize today's embedding technologies.

First modules with embedded chips are in production in Asia, mainly for telecom and computer applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential.

In a number of European cooperation projects with partners from industry and research, embedding of power chips, like IGBTS and power MOSFET, is of high interest. In this paper current achievements of these projects will be shown, especially examples of realized devices and their characteristics. The dominating technology for power chip embedding is a face-up technology. Chips are bonded with their backside (drain contact) to a Cu substrate using highly conductive adhesive or solder. Using the face up assembly, a direct contact to the backside of the die is possible, allowing a lot of benefits for driving high currents and applying an efficient thermal management for the power devices. Then Chips are embedded by vacuum lamination of prepreg or RCC (resin coated copper) layers. Via holes to the top contacts (gate and source) are formed by laser drilling. The vias are metallized using conventional Cu plating. Finally conductor structures are etched in the top Cu layer, finalizing the circuit. Details will be given about device manufacturing, related yield issues and strategies to overcome them.

Finally scenarios for the implementation of embedding technology and concepts for future applications will be discussed.
Solutions for Wafer-Level Packaging of High Brightness LEDs
Authors: Uhrmann Thomas , Kim B. , Matthias T. , Lindner P.
Published: October 2015

High brightness LEDs (HB-LEDs) carry a high prospect for general lighting applications. Competing with the cost/performance ratio of current light sources demands an increase of the overall efficiency as well as the reduction of the device cost.

Since packaging accounts for 30%–50% of the cost of HB LED manufacturing, moving from die- level to wafer-level processes is one likely potential solution for reducing cost per lumen. Silicon-based WLP, using the established processing technology of the MEMS and IC industry, offers high fabrication reliability, high yield and the direct integration of the driver IC in the package. The already small form factor of WLP can be further reduced using Through-Silicon-Vias (TSV), increasing the maximum amount of chips per wafer. Silicon WLP also offers superior thermal management, with the relatively high thermal conductance of silicon. Redistributing LED dies on silicon wafer submounts, with metal bonding and copper TSVs, further improves the heat conductance away from the active region of the chip, resulting in increased device performance. Wafer-level optics can further improve performance and reduce packaging costs.

Wafer-level lens molding based on imprint lithography is in high volume manufacture for cell phone camera modules. It allows creation of spherical and a-spherical lenses as well as lens stacks with minimized form factor. In contrast to the currently applied drop dispensing technique for LED lens fabrication, the shape of the lens can be accurately tailored and the decrease of the lens size results in lower absorption and higher light output.

Most of these technologies are already in high volume production in other sectors. We will discuss the field proven solutions at each process step, from the formation of the silicon interposer, through the chip-to-wafer bonding, to the final imprinting of the wafer-level optics.
Advanced Laser Scribing for Emerging LED Materials
Authors: Mendes Marco , Sercel Jeffrey , Hannon Mathew , Porneala Cristian , Song Xiangyang , Fu Jie , Sarrafi Rouzbeh
Published: October 2015

Lasers are becoming increasingly important in today's LED revolution and are essential for increasing the efficiency and reducing manufacturing cost of LEDs. Diode pumped solid state lasers excel in scribing horizontal type LEDs on sapphire, silicon, silicon carbide, III-nitrides (gallium nitride and aluminum nitride), as well as III-V semiconductors (gallium arsenide, gallium phosphide). These lasers are also used for dicing vertical type LEDs, which are becoming increasingly more important, often using high thermal conductivity metallic substrates such as copper, CuW and molybdenum. In this paper we will discuss some of the recent laser scribing/dicing techniques and how adequate selection of laser parameters and beam delivery optics allows for a high quality high throughput singulation process for the various materials listed above.
Packaging of High Brightness, Big-Chip LEDs
Authors: Lee Lidia , Panaccione Paul
Published: October 2015

A common approach for designing HB-LEDs into a variety of lighting systems is to arrange an array of many emitters over a large area in order to provide the required photometric flux. In certain applications, this common approach of arraying a large number of small chip LEDs introduces a number of challenges that can be solved by using a single package of big-chip LEDs with enough light output to meet the system requirements. This presentation will discuss package design for big-chip LEDs, compared to an array of many small emitter packages.

In addition to big-chip package design, the impact on system design including optics, drivers, thermals, reliability, and form factor will be addressed. For illustration, a reference example will be presented in detail, consisting of an easy to use plug and play single package with 36mm2 of emitting area capable of up to 6000 lumens.
Formulation of Percolating Thermal Underfill by Sequential Convective Gap Filling
Authors: Brunschwiler T. , Goicochea J. , Wolf H. , Kuemin C. , Michel B.
Published: October 2015

In 3D chip stacks, heat dissipation through wiring layers and the bonding interface contributes to the total temperature gradient. The effective thermal impedance of micro solder-ball arrays filled with a poorly-conducting silica underfill can be as high as 30 K*mm2/W, three times the value of a thermal grease interface. Efforts to improve the underfill conductivity to 5 W/(m*K) are underway, which would translate into in a significant interface-resistance reduction.

To achieve thermal conductivities >1 W/(m*K), alumina particles were introduced in capillary underfills at particle loadings above the percolation threshold, but at these loading levels the high viscosity of the resulting underfill no longer permits capillary filling.

We propose a novel sequential gap-filling method. Particles are suspended in a carrier fluid at a low concentration (0.1 vol%). Using forced convection, the suspension is injected into the cavity formed between the IC dies by the C4 array. A filter element at the cavity outlet triggers particle accumulation in the cavity. The particles form a percolation network with an effective thermal conductivity of >1 W/(m*K). Next an evaporation step removes the carrier fluid, and the exposed pores between the particles are refilled with a particle-free adhesive using capillary forces. Finally, the matrix is cured at 65 °C.

10x10 mm2 standard and micro-C4 cavities (>30 μm) can be completely filled in 2 min at 0.2 bar, resulting in a homogeneous volumetric fill of 36%. Percolation was identified by SEM inspection. For the micro-C4 arrays filler particles of < 10 μm were used. Uniform particle filling is precluded because of the longer filling time due to the small pore sizes. Particle trapping sites are introduced to form local stacks that provide an additional drainage network to guarantee acceptable filling times. Effective thermal-conductivity values of the percolating thermal underfill method proposed here are reported.
A Novel Frequency Addressable Micro Switch Array
Authors: Wang Minfeng , Zhang Yang , Li G. P. , Bachman Mark
Published: October 2015

Addressable switch arrays are widely used in telecommunication, radar and satellite systems for many applications, such as switch network controlling, modularity and expansion. The existing method to achieve addressability of the switch is to design a grid structure switch array and to individually actuate switches with multiplexed control lines , . The MEMS switch array presented in this work addresses individual switches according to the unique intrinsic resonance frequencies of different mechanical structures driven by electro-magnetic force. This approach eliminates the need to have a dedicated control line for each switch, which readily enables the switch array with minimal complexity of control line design thus minimizes the overall footprint.

The frequency addressable switch array (FASA) is fabricated directly on printed circuit boards using patented laminate MEMS technology.

Instead of building everything bottom-up, three layers including top cantilever structure, middle spacer, bottom electrode and coils are fabricated separately through different processes and later laminated together. The switches are electro-magnetically actuated at operation voltage (~1V), which is much lower than the one of the conventional electrostatic actuation (>30V) . Alternating electro-magnetic force is exerted on a mini neodymium magnet by a series of coils. Only when the maximum vibration stroke is obtained at the resonant frequency of individual switch, the mini magnet mounted on the top cantilever will make contact with the bottom electrode for signal transmission. The quality factors of the switches were measured to be nearly 100 with air damping. The related switch density (defined by the number of the switches per kHz in desired frequency range for individual addressing) in the array is around 10 per kHz. By improving the quality factor of the switch such as hermetic packaging avoiding the air damping, a high value (>200 per kHz) of the switch density is expected.
Flip-Chip Technologies, Applications, Market Status and Forecasts
Authors: Zinck Christophe , Yannou Jean-Marc , Baron Jérôme , Garou Phil
Published: October 2015

Renewed interest in flip-chip technologies in concurrently motivated in many application areas by such factors as the rising cost of gold used for wire bonding, the need for low thickness devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages.

Today, many sophisticated devices can no longer be packaged with wire bonding technology and the mobile applications are more and more requiring footprint and weight reduction coupled with higher electrical performances (signal propagation and power distribution). The emergence of the 28nm CMOS technology node in particular, poses new quality and reliability constraints on interconnect technologies so as to cope with the increasing fragility of the back end of line, which may disqualify wire bonding for good. Not to mention the ever increasing IO density, making it necessary to develop new bumping and substrate technologies. It is not any longer only about higher performance and lower cost reliable interconnect, assembly and packaging technologies: if remained unresolved, the above constraints will prove to be bottlenecks if not obstacles to the continuation of Moore's law.

In this presentation, we will first focus on Flip-Chip technologies and their evolution. We will present the main players, their facilities and technologies. We will sketch a worldwide roadmap of flip-chip featuring such varied applications as wireless digital, PC processors, RF and power devices. We will then present our market forecasts and explain how we see these innovations will modify the market of packaging interconnections and assembly in the years to come.