Low Temperature Epitaxy Processes for Contact Resistivity Reduction
Authors: Margetis Joe , Breil Nico , Tolle John , Dube Abhishek , Chopra Saurabh 
Published: December 2024

With the continued scaling of CMOS logic devices the contact resistivity at the semiconductor/silicide interface has become a limiting factor for device performance. High active dopant concentration at this interface is critical to realizing low contact resistance, and ion implantation is conventionally used to achieve this. We have previously reported [1] that contact cavity shaping to increase the contact area can be used to decrease the contact resistivity. This etching process produces convex (111) facets from a (100) starting surface in the source-drain volume, thereby increasing the contact area. The etched-recess shape can be varied from a “U” to a “V” as seen in figures 1(b) through (d). The ρc for these shapes was measured after integrating a 385°C SiGe:B in the recessed layer on TLM structures decreases with increasing (111) facet-length and for the longest facet length a ρc = 8.0 x10-10 Ωcm-2, where the implant + anneal control sample had ρc = 1.5x10-9 Ωcm-2. On FinFET structures the cavity shaping + low temp SiGe:B achieved a ρc = 5.2 x10-10 Ωcm-2 compared to the implant + anneal control of ρc = 1.5x10-9 Ωcm-2 as shown in figures 1(e) and (f).

Cavity shaping can be a helpful knob to improve contact resistance, however thermal budget and integration constraints necessitate that the epitaxial growth of these layers are at temperatures ≤ 400°C. These low growth temperatures can be beneficial to dopant activation, however the growth rate and selectivity are negatively impacted. Next generation contact epitaxy processes will integrate etch cavity shaping with novel deposition chemistries to surmount these challenges. For PMOS SiGe:B deposition acceptable growth rates are more easily realized due to the intrinsic growth rate benefit from Ge and B incorporation, as well as the higher reactivity of Ge precursors compared to their Si analogs. However maintaining selective deposition requires large flows of HCl which decrease the growth rate and the boron concentration. We have employed an alternative Cl-containing precursor to maintain selectivity during Si0.5Ge0.5:B deposition at temperatures as low as 350°C, with a growth rate of 13 Å/min. Whereas to achieve selectivity with HCl at this temperature results in a growth rate of 6 Å/min. Figures 2(a) through (d) show a patterned wafer images with and without the addition of this precursor at 350°C.

The situation for NMOS Si:P deposition is more difficult, as PH3 does not increase the growth rate as drastically as GeH4 or B2H6 do, and the gas-phase reactivity of conventional Si-hydrides and hydrochlorides is quite low. Higher-order silanes such as Si3H8 and Si4H10 can be used however the cost of these precursors is high and their efficiency at 400°C is typically between 0.01% and 1%. Ideally a phosphorus doping precursor, which is ostensibly used at lower flow rates, could enhance the growth rate similar to the effect of B2H6 in the growth of p-type materials. The other major concern for low temperature Si:P deposition processes is the selectivity to dielectric surfaces. A fully selective process in unlikely for Si:P at these temperatures and etch-back cycles will be required to remove the materials which nucleate on the dielectric surfaces. It is therefore desired to identify a P precursor with higher intrinsic selectivity than Si2H6-PH3 and/or Si3H8-PH3 processes.

Here we present a Si2H6-based process in which the P dopant precursor (PDOP-1) is engineered to enhance the epitaxial growth rate and delay the nucleation of material on the dielectric surface. Figure 3(a) compares the growth rate vs. temperature for a Si2H6-PH3 process and Si2H6-PDOP-1. The growth rate of the PH3 process falls-off rapidly below 400°C, whereas a measurable epitaxial growth rate is maintained down to ~ 385°C in the PDOP-1 process. We find that for equivalent growth conditions and %P that PDOP-1 can increase the growth rate by 60-80% relative to PH3 processes. In figure 3(b) the amorphous growth rate on SiO2 is plotted vs time for a Si2H6-PH3 benchmark and Si2H6-PDOP. From this plot we have determined a nucleation delay of ~ 90 seconds for PDOP-1, whereas the benchmark PH3 does not exhibit a nucleation delay. This behavior is further explored in figure 4 where we have deposited SiP non-selectively on a simple patterned wafer using Si2H6-PH3, Si3H8-PH3, and Si2H6-PDOP1. We have used the epi to amorphous thickness ratio as metric for the intrinsic selectivity of each process. Based on these results the intrinsic selectivity is improved to 4:1 using PDOP-1, from 2:1 and 3:1 for the, Si3H8-PH3 and Si2H6-PH3 benchmarks, respectively.

[1] N. Breil et. al. IEEE Symposium on VLSI Technology, 2023

Figure 1