bluuebunny/crossref_metadata_2025 huggingface dataset:
Multiplet Theory for Conduction Band Edge and O-Vacancy Defect States in SiO2, Si3N4, and Si Oxynitride Alloy Thin Films
Authors: Lucovsky Gerald
Published: April 2011

This article, the second of a two-part sequence, combines X-ray absorption spectroscopy (XAS) and many-electron theory to develop a model for intrinsic bonding defects in non-crystalline and nanocrystalline thin films used primarily as gate dielectrics for field effect transistors and related devices. In SiO2 these defects are O-atom vacancies and their spectral features in O K pre-edge spectra are assigned to multiplet transitions based on a d2 model for the electrons in a neutral O-vacancy site. This model is applied to (i) non-crystalline (nc-) SiO2, and extended to (ii) Si oxynitride alloys, (nc-SiO2)1-x
(Si3N4)
x
, and nc-Hf Si oxynitrides. As in Part I, this relies on Tanabe–Sugano (TS) energy diagrams to identify spin-allowed X-ray transitions and negative ion states. Differences between band edge states in (i) nc-SiO2, and (ii) nc-Si3N4 explain quantitative differences in trapping and trap-assisted tunneling. Preliminary results for nc-GeO2 films prepared by remote-plasma-enhanced chemical vapor deposition shows these films exhibit surface stability similar to nc-SiO2, suggesting that local nc-GeO2 bonding involves the same 4-fold Ge, and 2-fold O coordination as Si and O in nc-SiO2.
Low Gate-Induced Drain Leakage and Its Physical Origins in Si Nanowire Transistors
Authors: Zaitsu Koichiro , Saitoh Masumi , Nakabayashi Yukio , Ishihara Takamitsu , Numata Toshinori
Published: April 2011

Gate-induced drain leakage (GIDL) in Si nanowire transistors fabricated on silicon-on-insulator substrates is systematically studied. In narrow nanowire transistors, GIDL current is obtained by relatively small potential difference between the gate and the drain due to the superior electrostatic control by gate voltage. On the other hand, variation of GIDL current with gate voltage is drastically reduced in nanowire transistors with the wire width of around 10 nm, which realizes devices with extremely small off-current. The reduction of local electric field around the drain junction due to low impurity concentration in source/drain extensions and the relatively large source/drain parasitic resistance are identified as the main mechanisms of small GIDL current.
Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology
Authors: Han Jin-Ping , Shimizu Takashi , Pan Li-Hong , Voelker Moritz , Bernicot Christophe , Arnaud Franck , Mocuta Anda , Stahrenberg Knut , Azuma Atsushi , Eller Manfred , Yang Guoyong , Jaeger Daniel , Zhuang Haoren , Miyashita Katsura , Stein Kenneth , Nair Deleep , Park Jae Hoo , Kohler Sabrina , Hamaguchi Masafumi , Li Weipeng , Kim Kisang , Chanemougame Daniel , Kim Nam Sung , Uchimura Sadaharu , Tsutsui Gen , Wiedholz Christian , Miyake Shinich , Meer Hans van , Liang Jewel , Ostermayr Martin , Lian Jenny , Celik Muhsin , Donaton Ricardo , Barla Kathy , Na MyungHee , Goto Yoshiro , Sherony Melanie , Johnson Frank S. , Wachnik Richard , Sudijono John , Kaste Ed , Sampson Ron , Ku Ja-Hum , Steegen An , Neumueller Walter
Published: April 2011

High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance G
m, conductance G
ds, G
m/I
d, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., I
on–I
off, I
off–V
tsat, DIBL, C
jswg) and reliability (HCI) have also shown the comparability of HPA devices over control.
Experimental Study of Physical-Vapor-Deposited Titanium Nitride Gate with An n+-Polycrystalline Silicon Capping Layer and Its Application to 20 nm Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Kamei Takahiro , Liu Yongxun , Endo Kazuhiko , O'uchi Shinichi , Tsukada Junichi , Yamauchi Hiromi , Ishikawa Yuki , Hayashida Tetsuro , Matsukawa Takashi , Sakamoto Kunihiro , Ogura Atsushi , Masahara Meishoku
Published: April 2011

We have comparatively investigated the electrical characteristics including threshold voltage (Vth) variability and mobility by fabricating n+-polycrystalline silicon (poly-Si) gate and physical-vapor-deposited (PVD) titanium nitride (TiN) gate fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs), and demonstrated 20-nm-thick PVD-TiN gate FinFETs with a symmetricalVth. It is experimentally found that the gate stack of a 20-nm-thick PVD-TiN layer capped with a 100-nm-thick n+-poly-Si layer is very effective for setting a symmetricalVthfor undoped FinFETs keeping almost the sameVthvariability and mobility as those in the case of the n+-poly-Si gate only. On the other hand, mobility degradation was observed in the case of pure 50-nm-thick PVD-TiN gates. These results indicate that mobility degradation probably caused by the thick metal gate induced mechanical stress can be effectively suppressed by reducing the PVD-TiN thickness to 20 nm or less.
Effects of Quantum Confinement on Electrical Characteristics of 12-nm Silicon-on-Insulator Fin Field-Effect Transistors by Quantum Transport Analysis
Authors: Liu Keng-Ming
Published: April 2011

Quantum confinement in nanoscale silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) is significant and will affect their electrical characteristics. In this paper, we investigate this phenomenon by an in-house quantum transport simulator, Schrödinger equation Monte Carlo in three dimensions (SEMC-3D), which can provide the quantum transport simulation of nanoscale 3D metal–oxide–semiconductor field-effect transistor (MOSFET) geometries such as FinFETs as well as take various scattering processes into account. Our simulation results indicate that the degradation of the drain current and transconductance due to scattering is still significant even at 12 nm gate length. Under the ballistic limit, the drain currents per unit periphery of different fin height are almost the same. However, when scattering is considered, reducing the fin height, i.e., increasing the quantum confinement, will degrade the drain current per unit periphery because of increasing the scattering rate around the barrier top of the channel. The square fin cross section should be avoided since the degenerate subbands will increase the scattering rate and degrade the drain current per unit periphery.
Investigation of Stress Memorization Process on Low-Frequency Noise Performance for Strained Si n-Type Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Kuo Cheng-Wen , Wu San-Lein , Lin Hau-Yu , Huang Yao-Tsung , Chang Shoou-Jinn , Hong De-Gong , Wu Chung-Yi , Cheng Yao-Chin , Cheng Osbert
Published: April 2011

The use of low-frequency (1/f) noise to evaluate low-cost stress-memorization technique (SMT) induced-stress in n-type metal–oxide–semiconductor field-effect transistors has been investigated. As compared to device without SMT process, the comparable 1/f noise level obtained for strained Si devices with the low-cost SMT process indicates that adding the low-cost SMT process will not affect the Si/SiO2 interface quality. Moreover, through observing experiment result and Hooge's parameter αH, the mechanism of 1/f noise in the both devices can be properly interpreted by the carrier number fluctuations correlated mobility fluctuations (unified model).
Nanosized-Metal-Grain-Induced Characteristic Fluctuation in 16 nm Complementary Metal–Oxide–Semiconductor Devices and Digital Circuits
Authors: Li Yiming , Cheng Hui-Wen
Published: April 2011

In this work, we investigate the effect of random work functions (WKs) resulting from the nanosized grains of a metal gate on 16 nm metal–oxide–semiconductor field-effect transistor (MOSFET) devices and circuits. The random number and position of nanosized metal grains induce rather different random WKs on a MOSFET gate, which cannot be modeled using an averaged WK; thus, we consider each WK of the metal gate, according to the size of partitioned grains, in three-dimensional device simulation. The results of this study indicate that the random-WK-induced threshold voltage fluctuation of N- and P-MOSFETs are about 1.5 and 1.6 times higher than the results calculated by the recently reported averaged WK fluctuation method. This is because even if the devices have similar threshold voltages, they may exhibit quite different combinations of WKs owing to the random position of nanosized metal grains on the devices' gate. Coupled device-circuit simulation is further adopted to explore the timing fluctuations of complementary metal–oxide–semiconductor (CMOS) inverter circuits. The random position of nanosized metal grains results in 10 and 12% variations in the timing fluctuation and power consumption of the CMOS inverter circuit.
Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology
Authors: Ryu Seong-Wan , Yoo Minsoo , Choi Deuksung , Cha Seonyong , Jeong Jae-Goan
Published: April 2011

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (D
it). It is worthwhile to note that the D
it as well as the GIDL current is a still meaning parameter to analyze the data retention time.
Collective Tunneling Model in Charge-Trap-Type Nonvolatile Memory Cell
Authors: Muraguchi Masakazu , Sakurai Yoko , Takada Yukihiro , Shigeta Yasuteru , Ikeda Mitsuhisa , Makihara Katsunori , Miyazaki Seiichi , Nomura Shintaro , Shiraishi Kenji , Endoh Tetsuo
Published: April 2011

A new tunneling model between an inversion layer and the trap sites for the charge-trap-type (CT-) nonvolatile memory (NVM) cell is proposed. By considering the geometrical mismatch between the inversion layer and the trap site of the CT-NVM cell, we can conclude that electron tunneling is induced by a rare event, which causes the localization of electrons in the inversion layer near the trap sites. In addition, we also reveal that the successive tunneling of electrons is triggered by this rare event tunneling by focusing on the temporal fluctuation of the electronic state in the inversion layer. On the basis of these phenomena, we propose the collective tunneling model in the charge injection of the CT-NVM cell, where the electrons tunnel to the trap sites collectively with a long waiting time. This insight is important in designing the CT-NVM cell. By using collective tunneling, the amount of injection charge can be controlled discretely by adjusting the charge injection time. This enables us to realize a multilevel charge trap cell.
Atomistic Design of Guiding Principles for High Quality Metal–Oxide–Nitride–Oxide–Semiconductor Memories: First Principles Study of H and O Incorporation Effects for N Vacancies in SiN Charge Trap Layers
Authors: Yamguchi Keita , Otake Akira , Kamiya Katsumasa , Shigeta Yasuteru , Shiraishi Kenji
Published: April 2011

We theoretically investigate H- and O-incorporation effects on memory characteristics of N vacancies in the SiN layer of metal–oxide–nitride–oxide–semiconductor (MONOS) type memory. The present calculations show that N vacancy maintains high program/erase (P/E) cycle endurance characteristics, regardless of the existence of H and O atoms. It is also found that the incorporation of an H atom is energetically favorable for N vacancy, whereas the incorporation of such an atom is unfavorable for O-incorporated N vacancy. The present results indicate clearly that realistic process conditions, in which incorporation of H and O atoms is inevitable, do not affect memory characteristic of MONOS-type memory having N vacancies in the SiN layer, and, therefore, such a memory is desirable and feasible for future memories.
Mechanism of Date Retention Improvement by High Temperature Annealing of Al2O3 Blocking Layer in Flash Memory Device
Authors: Park Jong Kyung , Park Youngmin , Lee Seok-Hee , Lim Sung Kyu , Oh Jae Sub , Joo Moon Sig , Hong Kwon , Cho Byung Jin
Published: April 2011

The mechanism underlying improved data retention via high-temperature oxygen annealing of the Al2O3 blocking layer in a charge-trap type flash memory device is investigated in comparison with the case of high-temperature nitrogen annealing. The results show that significant improvement of the retention property can be achieved by oxygen annealing at 1100 °C, compared to nitrogen annealing. Experimental evidence indicated that the underlying mechanism does not arise from suppression of the trap-assisted tunneling current through the blocking oxide; instead it is caused by a reduction of the thermionic emission component of the charge loss factor. This is possibly due to changes of the conduction band offset of the crystallized Al2O3.
Improved Resistive Switching Characteristics of NiO Resistance Random-Access Memory Using Post-Plasma-Oxidation Process
Authors: Okamoto Koichiro , Tada Munehiro , Ito Kimihiko , Hada Hiromitsu
Published: April 2011

A practical approach to oxygen compensation is investigated to improve a resistive change characteristic of NiO films. The stoichiometry of a physical vapor deposited NiO (PVD-NiO) is changed by post-plasma-oxidation (PPO) process at 350 °C. The PPO process eliminates oxygen vacancies and compensates for a loss of oxygen during Cu back-end-of-line (BEOL) process, which results in a lower forming voltage and a higher OFF/ON resistance ratio. The PPO also improves the surface roughness of the PVD-NiO film, reducing a cell-to-cell variation of the forming voltage. The developed NiO resistance random-access memory (ReRAM) integrated in Cu-BEOL coupled with the PPO process is applicable for realizing a low-power and stable resistive switch.
Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics
Authors: Ryoo Kyung-Chang , Oh Jeong-Hoon , Jung Sunghun , Jeong Hongsik , Park Byung-Gook
Published: April 2011

We firstly propose a novel U-shape resistive cell structure which is the best fit for generating low power resistive random access memory (RRAM) with forming-less process. We find that irregular resistive switching behavior in the initial transition and the characteristics associated with it. Controlling the conducting filament (CF) dimension and deposition orientation of resistive material are expected to reduce the distribution and forming voltage, which enables low power RRAM to be feasible without forming state. Simple fabrication flow and device performances are also evaluated in the aspect of forming-less process. Numerical simulation is performed using random circuit breaker model (RCB) to confirm the proposed structure.
Confocal Imaging System Using High-Speed Sampling Circuit and Ultra-Wideband Slot Antenna
Authors: Toya Akihiro , Sasaki Nobuo , Kubota Shinichi , Kikkawa Takamaro
Published: April 2011

A low-power impulse-radio ultra-wideband (IR-UWB) confocal imaging system was developed using a low-power complementary metal oxide semiconductor (CMOS) equivalent time sampling circuit and UWB slot antennas. The proposed imaging system uses a Gaussian monocycle pulse with 3 GHz center frequency to detect a target. The sampling circuit is fabricated by 65 nm CMOS technology, and it can achieve a high sampling rate of 28.2 GS/s, input bandwidth of 3.3 GHz and PLL RMS jitter of 3.44 ps with a low power consumption of 50.7 mW. The UWB slot antenna having a 1.53–4.80 GHz input bandwidth is developed for the confocal imaging. An aluminum target was detected using a confocal imaging algorithm.
2.4–10 GHz Low-Noise Injection-Locked Ring Voltage Controlled Oscillator in 90 nm Complementary Metal Oxide Semiconductor
Authors: Lee Sang-yeop , Amakawa Shuhei , Ishihara Noboru , Masu Kazuya
Published: April 2011

A wide-frequency-range low-phase-noise voltage controlled oscillator (VCO) with subharmonic injection locking is proposed and an implementation in 90 nm complementary metal oxide semiconductor (CMOS) is demonstrated. The result is a combination of the scalability and wide frequency tuning range naturally expected of a ring VCO and phase-noise performance close to that of an LC VCO using injection locking. The fabricated circuit is only 0.00054 mm2 in area, and its frequency tuning range is from 2.4 to 10 GHz. For a 500 MHz input reference signal and a 9.0 GHz (=18×500 MHz) output frequency, the 1-MHz-offset phase noise was -125 dBc/Hz. This is a 54 dB improvement over the free-running VCO phase noise of -71 dBc/Hz. The power consumption at 9.0 GHz is 9.5 mW.
Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM
Authors: Ansari Tania , Imafuku Wataru , Kawabata Akio , Yasuda Masahiro , Koide Tetsushi , Mattausch Hans Jürgen
Published: April 2011

Process-related variations are becoming a major concern for complementary metal–oxide–semiconductor (CMOS) technologies as the transistor size is scaled down. Hence, it is necessary to characterize the within-die (WID) and die-to-die (D2D) variations to establish a design methodology for the correct operation of ICs in the presence of such variations. Here, we have analyzed the stage-delay variation in ring oscillator arrays, fabricated in 180 nm CMOS technology, with large stage numbers and the possibility of flexible replacement for all ring oscillator stages. These allow an experimental analysis of the two-dimensional (2D) properties of the WID variation over the 1.69×1.59 mm2 area covered by the ring oscillators. Our results show that the measured variation data over this large area is still mainly of a Gaussian nature. Simulation of the delay stages of these ring oscillator arrays using the compact Hiroshima University STARC (Semiconductor Technology Academic Research Center) insulated gate field effect transistor (IGFET) Model (HiSIM) and some of the measurement data suggest that a systematic variation component, which does not change the Gaussian nature of the overall measurement data, may be present in the vertical direction of the ring oscillator array.
A 65 nm Complementary Metal–Oxide–Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit
Authors: Matsumoto Takashi , Makino Hiroaki , Kobayashi Kazutoshi , Onodera Hidetoshi
Published: April 2011

We propose a negative bias temperature instability (NBTI) recovery sensor with a 400 ns measurement delay. The measurement delay is about 30 ms when the leakage current of a small single transistor is measured by the conventional method. This sensor contains many unit cells. One unit cell includes 10 p-channel metal–oxide–semiconductor (PMOS) Device-under-tests (DUTs) and two assist n-channel metal–oxide–semiconductor (NMOS) devices. Parallelizing many unit cells can amplify the leakage current and the assist circuit can reduce the rush current to the ammeter, which keeps the measurement range of the ammeter constant during measurement. A short measurement delay is achieved by these two factors. It is confirmed that from 50 to 125 °C, NBTI recovery follows log
t from 400 ns to 3000 s. By stressing and recovering thousands of PMOS transistors at the same time, we can observe that the time constants of positively charged defects, which are related to NBTI, are log-uniformly distributed in the PMOS devices. Also, this circuit has the highest fidelity to NBTI recovery measurement because off-leak current is used for NBTI recovery characterization and stress is not added during measurement.
A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems
Authors: Yoshida Takeshi , Sueishi Katsuya , Iwata Atsushi , Matsushita Kojiro , Hirata Masayuki , Suzuki Takafumi
Published: April 2011

This paper describes a low-noise amplifier with multiple adjustable parameters for neural recording applications. An adjustable pseudo-resistor implemented by cascade metal–oxide–silicon field-effect transistors (MOSFETs) is proposed to achieve low-signal distortion and wide variable bandwidth range. The amplifier has been implemented in 0.18 µm standard complementary metal–oxide–semiconductor (CMOS) process and occupies 0.09 mm2on chip. The amplifier achieved a selectable voltage gain of 28 and 40 dB, variable bandwidth from 0.04 to 2.6 Hz, total harmonic distortion (THD) of 0.2% with 200 mV output swing, input referred noise of 2.5 µVrms over 0.1–100 Hz and 18.7 µW power consumption at a supply voltage of 1.8 V.
Temperature-Compensated Nano-Ampere Current Reference Circuit with Subthreshold Metal–Oxide–Semiconductor Field-Effect Transistor Resistor Ladder
Authors: Osaki Yuji , Hirose Tetsuya , Kuroki Nobutaka , Numa Masahiro
Published: April 2011

We have developed a low-power current reference circuit with little temperature dependence for micro-power LSIs in a 0.35-µm standard complementary metal–oxide–semiconductor (CMOS) process. The proposed circuit consists of a bias-voltage subcircuit, a current-source subcircuit, and an offset-voltage generation (OVG) subcircuit. The OVG subcircuit consists of a subthreshold MOS resistor ladder. It is used to generate a small offset voltage that is independent of temperature and compensates for the temperature dependence of the reference current. Experimental results demonstrated that the proposed circuit generated a 95-nA reference current and that the total power dissipation was 598 nW. The temperature coefficient of the reference current can be kept within 523 ppm/°C at temperatures from -20 to 100 °C.
Low-Phase-Noise, High Switching Speed Digitally Controlled Ring Oscillator in 0.18 µm Complementary Metal Oxide Semiconductor
Authors: Tomar Abhishek , Lingala Shashank , Pokharel Ramesh Kumar , Kanaya Haruichi , Yoshida Keiji
Published: April 2011

In this paper a 14-bit digitally controlled oscillator (DCO) with operating frequency up to 4.2 GHz in 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented. To improve the phase noise, digital control is used that avoids continuous conduction of transistors and controlling transistors operate either in triode or cutoff region. The circuit uses multiple-loop feed forward architecture to increase the switching speed. The DCO has a wide frequency tuning range from 490 MHz to 4.2 GHz. The measured phase noise of the DCO is -121.2 dBc/Hz at a 4-MHz offset from a 3.86-GHz center frequency and power consumption of 48 mW. Due to the phase noise reduction and high switching speed, the DCO has a -164.1 dBc/Hz figure of merit (FOM) that is an improvement of -4 dBc/Hz over the previously published results in the same technology. The chip area is 300×300 µm2.
Low-Voltage and High-Speed Voltage-Controlled Ring Oscillator with Wide Tuning Range in 0.18 µm Complementary Metal Oxide Semiconductor
Authors: Tiao Yu-Sheng , Sheu Meng-Lieh , Tsao Lin-Jie
Published: April 2011

A new complementary metal oxide semiconductor (CMOS) differential delay cell for a voltage-controlled ring oscillator with a wide tuning range and high speed is proposed in this paper. The new differential delay cell employing a complementary current control scheme can increase not only the control voltage range but also the operation frequency in low-voltage operation. Using the new delay cells, a ring voltage-controlled oscillator employing a three-stage structure and multiple-pass loop techniques is implemented in the 0.18 µm single-poly–six-metal (1P6M) CMOS process at a 1.8 V supply voltage to achieve a wide tuning range and high speed. Measured results show that a wide operation frequency range from 8.36 to 1.29 GHz is accomplished for the full-range control voltages from 0 to 1.8 V. When the supply voltage is 1 V, the operation frequencies are from 4.09 to 0.479 GHz for the full-range control voltages from 0 to 1 V. The measured phase noise is -100.22 dBc/Hz at 1 MHz offset from the 8.35 GHz center frequency and the figure of merit (FOM) is -159.95 dBc/Hz. The chip core area without PAD is 106×76.2 µm2.
Suppression of Gate Leakage and Enhancement of Breakdown Voltage Using Thermally Oxidized Al Layer as Gate Dielectric for AlGaN/GaN Metal–Oxide–Semiconductor High-Electron-Mobility Transistors
Authors: Freedsman Joseph J. , Kubo Toshiharu , Selvaraj S. Lawrence , Egawa Takashi
Published: April 2011

A synthetic route for alumina based dielectric layer for AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMT) has been developed. The approach is based on oxidative annealing of thin Al layer deposited prior to Schottky gate metallization. The MOS-HEMT exhibits good pinch off features withIdsmaxandgmmaxof 421 mA/mm and 121 mS/mm, respectively. Frequency dependent conductance measurements yielded a minimum trap density (DT) and trap transient time (TT) of 2.2 ×1012cm-2eV-1and 1.3 µs, respectively. The oxide layer suppresses the gate leakage by two orders of magnitude and enhances the breakdown voltage (BV) of the devices. A highBVof 431 V and figure of merit (FOM) of 1.89 ×108V2Ω-1cm-2for 15 µm device at (Lgd≤4 µm) was observed for Al2O3based MOS-HEMT.
Drift Phenomena of Forward and Reverse Recovery Characteristics in 0001 4H-SiC p–i–n Diode
Authors: Nakayama Koji , Sugawara Yoshitaka , Tsuchida Hidekazu , Kimura Chiharu , Aoki Hidemitsu
Published: April 2011

4H-SiC p–i–n diodes fabricated on the (0001) C-face showed smaller forward voltage drift and minimal changes in reverse recovery characteristics after a forward bias stress test compared to those observed on the (0001) Si-face. These drift phenomena in 4H-SiC p–i–n diodes could be explained by increased recombination along the perimeter of single Shockley-type stacking faults. It is suggested that the number of single Shockley-type stacking faults significantly decreased in the drift layer fabricated on (0001) C-face in comparison with that on (0001) Si-face.
Reduced Contact Resistance and Improved Surface Morphology of Ohmic Contacts on GaN Employing KrF Laser Irradiation
Authors: Wang Grace Huiqi , Wong Ting-Chong , Wang Xin-cai , Zheng Hong-Yu , Chan Taw-Kuei , Osipowicz Thomas , Foo Yong-Lim , Tripathy Sudhiranjan
Published: April 2011

We employ excimer laser annealing for ohmic contact formation to n- and p-type GaN layers grown on sapphire substrates. The laser irradiation of the n-GaN layers led to increased nitrogen vacancies at the nitride surface, which promoted tunneling currents with a less resistive n-contact. For p-GaN layer, the laser irradiation increased the effective hole concentration that resulted in a reduced contact resistivity. The lowest specific contact resistance measured using the transmission line method was about 2.4 ×10-7 and 3.2 ×10-4 Ω cm2 for n- and p-contacts, respectively. Laser irradiation also resulted in a comparatively good surface morphology as compared to rapid thermal annealing, which in turn improved the transmittance of contacts for light extraction from active layers. It was found out that both the electrical and optical characteristics of the p-GaN contacts exhibited a good thermal stability and an improved transmittance in the blue–green spectral range. An increased forward current with a reduced ohmic contact resistance in such high thermal stable contacts enable the fabrication of GaN light emitting diodes.
Low-Pressure Direct-Liquid-Cooling Technology for GaN Power Transistors
Authors: Otsuka Nobuyuki , Nagai Shuichi , Yanagihara Manabu , Uemoto Yasuhiro , Ueda Daisuke
Published: April 2011

Power concentration due to tremendous chip size reduction requires superior thermal conductivity. We first demonstrate the reduction in junction temperatures in low-pressure direct liquid cooling (LP-DLC) of GaN power devices for high-power and high-voltage switching applications. In the LP-DLC structure, junction temperature reductions of up to 55 K or 100% higher power levels were demonstrated by introducing a working fluid to a package. The thermal resistance has decreased to 28% in the LP-DLC structure with a radiator.
Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection
Authors: Bidzinski Piotr , Miczek Marcin , Adamowicz Boguslawa , Mizue Chihoko , Hashizume Tamotsu
Published: April 2011

The influence of interface state density and bulk carrier lifetime on the dependencies of photocapacitance versus wide range of gate bias (-0.1 to -3 V) and light intensity (109 to 1020 photon cm-2 s-1) was studied for metal/insulator/n-GaN UV light photodetector by means of numerical simulations. The light detection limit and photocapacitance saturation were analyzed in terms of the interface charge and interface Fermi level for electrons and holes and effective interface recombination velocity. It was proven that the excess carrier recombination through interface states is the main reason of photocapacitance signal quenching. It was found that the photodetector can work in various modes (on–off or quantitative light measurement) adjusted by the gate bias. A comparison between experimental data and theoretical capacitance-light intensity characteristics was made. A new method for the determination of the interface state density distribution from capacitance–voltage-light intensity measurements was also proposed.
Enhanced Device Performance of AlGaN/GaN High Electron Mobility Transistors with Thermal Oxidation Treatment
Authors: Liu Shenghou , Wang Jinyan , Gong Rumin , Lin Shuxun , Dong Zhihua , Yu Min , Wen C. P. , Zeng Chunhong , Cai Yong , Zhang Baoshun , Xu Fujun , Zhang Jincheng , Shen Bo
Published: April 2011

We systematically investigated the effect of the thermal oxidation treatment on the performance of AlGaN/GaN high electron mobility transistors (HEMTs). The HEMTs with thermal oxidation treatment exhibit four orders of magnitude reduction in gate leakage current, 80% reduction of trap density, and more than two times improvement of off-state drain breakdown voltage, compared with those shown by HEMTs without thermal oxidation treatment. The simplicity in the thermal oxidation treatment process, coupled with the drastic improvement in device performance render the thermal oxidation treatment highly promising for GaN-based microwave power amplifier applications in communication and radar systems.
Transparent Oxide Thin-Film Transistors Using n-(In2O3)0.9(SnO2)0.1/InGaZnO4 Modulation-Doped Heterostructures
Authors: Taniguchi Satoshi , Yokozeki Mikihiro , Ikeda Masao , Suzuki Toshi-kazu
Published: April 2011

We investigated transparent oxide thin-film transistors (TFTs) using n-(In2O3)0.9(SnO2)0.1/InGaZnO4 (n-ITO/IGZO) modulation-doped heterostructures, which are effective in achieving high carrier mobilities. From transmittance measurements and UV photoemission spectroscopy, n-ITO/IGZO modulation-doped heterostructures are expected to realize the type-II energy band lineup, in which both the conduction band minimum and the valence band maximum of n-ITO are higher in energy than those of IGZO. Van der Pauw Hall measurements revealed Hall mobility enhancement and two-dimensional behavior of electrons at the n-ITO/IGZO interface. Using the n-ITO/IGZO modulation-doped heterostructures, we obtained TFTs with higher electron mobility than that of IGZO TFTs. We consider that modulation doping is a promising method for performance improvements of TFTs using transparent oxide semiconductors.
Optical Kerr Signals Markedly Enhanced by Increasing Quality Factor in a GaAs/AlAs Multilayer Cavity
Authors: Morita Ken , Takahashi Tomoya , Kitada Takahiro , Isu Toshiro
Published: April 2011

Optical Kerr signals markedly enhanced by increasing quality (Q) factor in a GaAs/AlAs multilayer cavity have been demonstrated using time-resolved optical measurements. In the optical Kerr measurements, the spectral width of a laser pulse was well tuned to the peak of the cavity mode using the wavelength-restricted optical system. Although the Q of a 30-pair cavity is only 1.6 times larger than that of a 26-pair cavity, the optical Kerr signal intensity of the 30-pair cavity is 10 times larger than that of the 26-pair cavity. We have revealed that the optical Kerr signal of the GaAs/AlAs multilayer cavity is markedly enhanced nearly proportional to the Q
4 as a result of the enhanced nonlinear phase shift owing to the strong internal optical field and the long photon lifetime of the cavity-mode light.
Time-Resolved Measurements of Sum-Frequency Generation Strongly Enhanced in (113)B GaAs/AlAs Coupled Multilayer Cavity
Authors: Tanaka Fumiya , Takimoto Toshikazu , Morita Ken , Kitada Takahiro , Isu Toshiro
Published: April 2011

Time-resolved measurements of sum-frequency generation (SFG) of two cavity modes, which were realized in a GaAs/AlAs coupled multilayer cavity structure grown on a (113)B-oriented GaAs substrate, were performed. Strongly enhanced SFG and second-harmonic generation (SHG) signals have been demonstrated by the simultaneous excitation of two cavity modes using 100 fs laser pulses. In the time-resolved measurements, the sample was irradiated by two 100 fs laser beams with a time delay and the SFG and SHG signals generated by combining two beams were detected using a small slit. The delay-time-dependent measurements have revealed that the SFG and SHG signals decay with the photon lifetime (0.6 ps) of the coupled multilayer cavity, and the oscillating behavior with the period (0.3 ps) corresponding to the optical frequency difference (3.3 THz) between two cavity modes is significant only for the SFG. The experimental results were well explained by the simulated light electric field inside the coupled cavity under two Gaussian pulse excitation.
Developing a Half-Cladding Semiconductor Photonic Device Structure for Surface Transmission of Light Waves
Authors: Yamamoto Naokatsu , Fujioka Hiroki , Murakami Daisuke , Akahane Kouichi , Kawanishi Tetsuya , Sotobayashi Hideyuki , Takai Hiroshi
Published: April 2011

A control of the light-wave properties is critical issue in developing attractive photonic devices. In conventional photonic devices such as semiconductor waveguide light sources, complicated techniques were required to fabricate the high-aspect-ratio artificial periodic structures that help controlling the light-wave properties. This is because the conventional photonic devices are constructed with thick cladding layers for an optical confinement. In this paper, we propose and fabricate a half-cladding semiconductor light source as an attractive photonic device structure. We successfully demonstrated a light emission from the light source under current injection at room temperature. With a half-cladding structure, the total thickness between the device surface and the top of the active layer is on the sub-µm scale. Controlling the light-wave properties should therefore be possible with artificial surface microstructures fabricated by a low aspect ratio process sequence.
Design Rules and Characterisation of Electrically Pumped Vertical External Cavity Surface Emitting Lasers
Authors: Orchard Jonathan R. , Childs David T. D. , Lin Li Chih , Stevens Ben J. , Williams David M. , Hogg Richard A.
Published: April 2011

We present an experimental study of the effect of substrate doping on the operating characteristics of substrate emitting electrically pumped vertical external cavity surface emitting lasers. We demonstrate a reduction in substrate doping from 2×1018to 4×1017cm-3leads to reduced optical loss and enhanced current–gain characteristics. Spatial carrier distributions, evidenced by near field profiling of devices without external feedback indicates essentially identical behavior for the two substrate dopings. Devices with diameter greater than 100 µm and current spreading layer thickness of 100 µm suffer from non-uniform carrier injection into the active region, below this diameter output power scales linearly with device diameter. We show CW powers of 130 mW from a 100 µm device with 4×1017cm-3substrate doping at 0 °C can be obtained.
Enhanced Light Output of Vertical-Structured GaN-Based Light-Emitting Diodes with TiO2/SiO2 Reflector and Roughened GaOx Surface Film
Authors: Lee Wei-Chi , Wang Shui-Jinn , Uang Kai-Ming , Chen Tron-Min , Kuo Der-Ming , Wang Pei-Ren , Wang Po-Hung
Published: April 2011

GaN-based thin-film vertical-structured light-emitting diodes (VLEDs) with a GaO
x
film atop an n-GaN layer roughened via KrF laser irradiation and a TiO2/SiO2 distributed Bragg reflector (DBR) are proposed and investigated. As compared with regular VLEDs with an Al reflector and without a roughened GaO
x
film, the proposed VLEDs with a chip size of 1 mm2 show a typical increase in light output power by 68% at 350 mA and by 51% at 750 mA, which is attributed to the enhanced reflectivity and current blocking capability of the DBR layer, the surface roughening with circular GaN protrusions, and the formation of a surface GaO
x
film by KrF laser irradiation.
High Performance of GaN-Based Light Emitting Diodes Grown on 4-in. Si(111) Substrate
Authors: Zhu Youhua , Watanabe Arata , Lu Lin , Chen Zhitao , Egawa Takashi
Published: April 2011

We have demonstrated GaN-based light emitting diodes (LEDs) grown by metal-organic chemical vapor deposition on 4-in. Si(111) substrates. The structural property has been revealed by the measurement of X-ray diffraction. One of the full widths at half maximum of ω-scans of the GaN (0002) reflection is around 630 arcsec. Also, it can be found that the GaN epitaxial quality can be improved by increasing the thickness of n-GaN. The device properties have been evaluated through current–voltage, electroluminescence, and light output power–current measurements. As the n-GaN thickness increases from 1 to 2 µm, the light output powers of the LEDs have enhanced approximately two times under the injection current of 20 mA. Moreover, the maximum values of respective external quantum efficiency are achieved as 0.3 and 0.6%, respectively.
Tunable Light Emission from GaN-Based Photonic Crystal with Ultraviolet AlN/AlGaN Distributed Bragg Reflector
Authors: Chen Cheng-Chang , Chiu Ching-Hsueh , Yang Yi-Chun , Shih M. H. , Chen Jun-Rong , Li Zhen-Zu , Kuo Hao-Chung , Lu Tien-Chang
Published: April 2011

In this paper, the characteristics of GaN-based two-dimensional (2D) photonic crystal bandedge coupling operation with an ultraviolet AlN/AlGaN distributed Bragg reflector (DBR) have been investigated and analyzed. The 25-pair AlN/Al0.2GaN0.8 DBR shows a high reflectivity of 85% at 375 nm with the stop-band width of 15 nm. A strong light emission was observed from GaN photonic crystals within high reflectivity region of DBR. The emission wavelength can be also manipulated by varying the radius to lattice constant ratio. The photonic crystal bandedge mode was also characterized with three-dimensional plane-wave expansion (PWE) and finite-difference time-domain (FDTD) simulation.
Integration of Micro-Light-Emitting-Diode Arrays and Silicon Driver for Heterogeneous Optoelectronic Integrated Circuit Device
Authors: Shin Sang-Baie , Iijima Ko-Ichiro , Chiba Jun-Ichi , Okada Hiroshi , Iwayama Sho , Wakahara Akihiro
Published: April 2011

In this paper, we proposed the possibility of implementing a single chip device for realizing optoelectronic integrated circuits (OEICs). Micro-light-emitting-diode (LED) arrays and a complementary metal–oxide–semiconductor (CMOS) pulse width modulation (PWM) silicon driver were proposed, designed, and fabricated on a single chip. The micro-LED arrays were separated by a dry etching method into 64 pixels of 8×8, each with a size of 30×30 µm2 and operated in 3 V at 100 µA. The PWM Si driver was well operated and modulated using various control signals. Furthermore, to investigate the driver for handling massive parallel information, a simple multifunctional driver was designed, fabricated, and flip-chip-bonded using a gold compliant bump and anisotropic conductive adhesive with micro-LED arrays.
Dry Etching of Al-Rich AlGaAs for Photonic Crystal Fabrication
Authors: Mochizuki Masaya , Kitabayashi Yuta , Nakajima Tomoya , Satoi Daiki , Ishikawa Fumitaro , Kondow Masahiko , Hara Makoto , Kimura Chiharu , Aoki Hidemitsu , Sugino Takashi
Published: April 2011

We investigate inductively coupled plasma deep dry etching of Al0.8Ga0.2As for photonic crystal (PC) fabrication using Cl2, BCl3, and CH4 chemistry. The characteristic AlO
x
deposition is observed during the etching, resulting in the reduction of etching rate. BCl3 is considered to scavenge the deposited AlO
x
by its reductive reaction. CH4 passivates the etching sidewall, as well as enhances the deposition of AlO
x
. Concerning the impact of pattern size, a pronounced inverse reactive ion etching (RIE) lag is observed, which is beneficial for small-size PC fabrication typically with a hole diameter of 100–500 nm. From the findings, we successfully fabricated a PC structure with air holes having an aspect ratio of 8 and a diameter of 110 nm.
Optical Characterization of an Asymmetric Quantum Well Structure for Broadband Laser Array Application
Authors: Chen Wei-Li
Published: April 2011

Distributed feedback (DFB) lasers based on AlGaInAs asymmetric quantum wells (AQWs) have been designed and fabricated. The active region comprises of three 6.4 nm and six 5 nm wells, with +1.3448% compressive strain in quantum wells and -0.7379% tensile strain in barriers. Material quality was characterized by photoluminescence (PL) and photorefletance (PR) investigation. Broadband characteristic was confirmed by a 98 nm wide room temperature PL spectrum centering at 1520 nm. The details of transition energies and their associated quantized energy levels in both types of wells were studied by PR measurement and the results were compared with numerical simulation results and PL spectra. DFB lasers worked in the wavelength range from 1502.8 to 1535.2 nm. Although channels at longer wavelength failed due to process defect in grating, numerical simulation and laser performance analyses indicated that the modal gain of the channel at 1532.2 nm was supported by wide wells.
Growth and Characterization of a GaAs Quantum Well Buried in GaAsP/GaAs Vertical Heterostructure Nanowires by Selective-Area Metal Organic Vapor Phase Epitaxy
Authors: Fujisawa Shota , Sato Takuya , Hara Shinjiro , Motohisa Junichi , Hiruma Kenji , Fukui Takashi
Published: April 2011

We developed a growth method for forming a GaAs quantum well (QW) buried in GaAsP/GaAs heterostructure nanowires (NWs) by selective-area metal organic vapor phase epitaxy (SA-MOVPE). To determine the optimum growth conditions of GaAsP NWs, we varied the [(C4H9)PH2+ AsH3]/[(CH3)3Ga] ratio between 20 and 185. As a result, we could obtain NWs with good height uniformity when the ratio was 20. To form such NWs with a GaAs QW, we fabricated GaAs NWs of about 60 nm in diameter before the GaAsP growth. The NW uniformity was considerably improved by introducing GaAs growth. Photoluminescence (PL) measurements at 4.2 K indicated that the QW had a spectral peak about 150 meV higher than the acceptor-related recombination emission peak of GaAs, which is near 1.5 eV. The QW thickness estimated from the spectral peak energy of PL was 5.2 nm, which is in fair agreement with the value calculated from the GaAs growth rate.
Energy Transfer in Multi-Stacked InAs Quantum Dots
Authors: Akahane Kouichi , Yamamoto Naokatsu , Naruse Makoto , Kawazoe Tadashi , Yatsui Takashi , Ohtsu Motoichi
Published: April 2011

We fabricated a modulated stacked quantum dot (QD) structure to investigate energy transfer among QDs using a strain compensation technique that allowed us to fabricate a vertically aligned, highly stacked structure without any degradation in crystal quality. Enhanced photoluminescence (PL) intensity for the ground state of large QDs was clearly observed in a sample where the ground state of small QDs was resonant to the first excited state of large QDs, indicating energy transfer from small QDs to large QDs. Long-range energy transfer reached approximately 200 nm and can be considered from the measurement of N dependence of PL intensity.
Strain-Induced Back Channel Electron Mobility Enhancement in Polycrystalline Silicon Thin-Film Transistors Fabricated by Continuous-Wave Laser Lateral Crystallization
Authors: Fujii Shuntaro , Kuroki Shin-Ichiro , Kotani Koji , Ito Takashi
Published: April 2011

Four-terminal (4T) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) having both front and back gates were fabricated to investigate the effect of the internal tensile strain induced by continuous-wave (CW) laser lateral crystallization (CLC) on the carrier mobility. The tensile strain values at the surfaces and back interfaces were estimated to be approximately 0.3% and over 0.4%, respectively. In both front and back channel operations, the successful operation of a variable threshold voltage (V
th) scheme was confirmed. Front and back channel effective electron mobilities of 4T CLC poly-Si TFTs were evaluated under bias conditions so as not to form an inversion layer on the V
th-control gate side. Because of the larger tensile strain at the back interface, the back channel effective electron mobility was 1.2 times larger than the front channel effective mobility.
Effects of Deposition Conditions of First InSb Layer on Electrical Properties of n-Type InSb Films Grown With Two-Step Growth Method via InSb Bilayer
Authors: Khamseh Sara , Yasui Yuichiro , Nakayama Koji , Nakatani Kimihiko , Mori Masayuki , Maezawa Koichi
Published: April 2011

The n-type InSb films were prepared on Si(111) substrates with a two-step growth method via an InSb bilayer. This growth method consists of an initial low-temperature InSb layer growth and a subsequent high-temperature InSb layer growth. In order to obtain a heteroepitaxial InSb film with a high electron mobility, the growth conditions of the first InSb layer were optimized. The first InSb layer was prepared at higher growth temperatures. Moreover, the thickness of the first InSb layer with a lower crystalline quality and poor electrical properties decreased. InSb films prepared with new deposition conditions showed a higher crystalline quality, a lower defects density, and better electrical properties than the films indicated in our previous report. An InSb film with a high electron mobility of 38,000 cm2/(V·s) which shows a high potential for new high-speed device applications was obtained.
Fabrication and Photocurrent Generation of Multilayer Assemblies Consisting of Silver-nanoparticles, Polydiacetylene, and Polyions
Authors: Akiyama Tsuyoshi , Masuhara Akito , Matsuda  , Arakawa Taichi , Munaoka Takatoshi , Onodera Tsunenobu , Oikawa Hidetoshi , Yamada Sunao
Published: April 2011

The fabrication of silver nanoparticle and polydiacetylene nanocrystal multilayer assemblies was successful on indium–tin-oxide transparent electrodes by repeating electrostatic layer-by-layer deposition. Adsorbed amount of silver nanoparticles and polydiacetylene nanocrystals was confirmed by visible absorption spectroscopy. The surface conditions and morphologies of the assemblies were investigated by scanning electron microscopy. In the presence of a sacrificial reagent, these multilayer assemblies generated a stable photocurrent. It has become apparent that polydiacetylene nanocrystals are not also photoexciting material in the present system, but also act as an electron relay or transport material. Therefore, photocurrent generation is assisted under the co-existence of polydiacetylene nanocrystals in the assemblies.