bluuebunny/crossref_metadata_2025 huggingface dataset:
Tensor Evaluation of Anisotropic Stress Relaxation in Mesa-Shaped SiGe Layer on Si Substrate by Electron Back-Scattering Pattern Measurement: Comparison between Raman Measurement and Finite Element Method Simulation
Authors: Tomita Motohiro , Nagasaka Masaya , Kosemura Daisuke , Usuda Koji , Tezuka Tsutomu , Ogura Atsushi
Published: March 2013

A strained SiGe layer will be used in next-generation transistors to improve device performance along with device scaling. However, the stress relaxation of the SiGe layer may be inevitable in nanodevices, because the SiGe layer is processed into a nanostructure. In this study, we evaluated the anisotropic stress relaxation in mesa-shaped strained SiGe layers on a Si substrate by electron backscattering pattern (EBSP) measurement. Moreover, we compared the results of EBSP measurement with those of anisotropic Raman measurement and finite element method (FEM) simulation. As a result, the anisotropic stress relaxation obtained by Raman spectroscopy was confirmed by EBSP measurement. Additionally, we obtained a good correlation between the results of EBSP measurement and FEM simulation. The σxxand σyystresses were markedly relaxed and the σzzand σxzstresses were concentrated at the SiGe layer edges. These stresses were mostly relaxed in the distance range from the SiGe layer edges to 200 nm. Therefore, in a SiGe nanostructure with a scale of less than 200 nm, stress relaxation is inevitable. The results of EBSP and Raman measurements, and FEM simulation show a common tendency. We believe that EBSP measurement is useful for the evaluation of stress tensors and is complementary to Raman measurement.
Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits
Authors: Vollebregt Sten , Chiaramonti Ann N. , Cingel Johan van der , Beenakker Kees , Ishihara Ryoichi
Published: March 2013

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects (vias) in three-dimensional integrated circuits due to their excellent thermal and electrical properties. To investigate the electrical resistivity of CNT, test vias were fabricated using both a top-down and bottom-up approach. The measured resistivity for the top-down process of 10 mΩ cm is among the better values found in literature. Beside this, the ability to grow CNT directly on single-grain thin-film transistors (SG-TFT) was demonstrated. The electrical performance of the SG-TFT was found not to be influenced by the CNT growth.
Radio-Frequency Inductors on High-Resistivity Silicon Substrates with a Nanocrystalline Silicon Passivation Layer
Authors: Wang Ruey-Lue , Chen Chao-Jung , Lin Yu-Ru , Liu Pin-Yi , Su Yan-Kuin , Hsueh Ting-Jen
Published: March 2013

In this paper, spiral inductors on high-resistivity silicon (HR-Si) substrates, which surfaces were passivated by different process methods, were fabricated and measured. The comparison of inductances and quality factors between these inductors shows that the inductances and quality factors of spiral inductors significantly depend on process method and thickness of surface passivation layer. The differently generated passivation layer results in different effective substrate resistivity and hence gives rise to different substrate loss. The experimental results show that using thicker nanocrystalline silicon (nc-Si) as a passivation layer will result in a smaller substrate loss and hence spiral inductors on the substrate have larger inductances and larger quality factors. In this study, the metal thickness of inductors is 1.2 µm and is about half that of the inductors provided by foundries. At higher frequencies, the thinner spiral inductors on the SiO2/nc-Si/HR-Si substrate have larger inductances and larger quality factors as compared with the inductors provided by foundries. With the same metal thickness as that adopted in standard processes of foundries, the identical-geometry inductors on the SiO2/nc-Si/HR-Si substrate probably exhibit superior quality factors.
Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Mao Ke , Saraya Takuya , Hiramoto Toshiro
Published: March 2013

In this paper, we report the direct measurement of intrinsic carrier mobility in “single”-silicon-nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) for the first time. To obtain intrinsic carrier mobility with high accuracy by the split capacitance–voltage (C–V) method, ultralong single-silicon-nanowires, instead of multiple parallel nanowires, were designed and fabricated. The open-circuit method was utilized to remove the parasitic effect in measured capacitance. It is found that, although mobility degradations in narrower nanowires are seen in both electrons and holes, the hole mobility is higher than the universal mobility on the (100) surface even in a “single”-nanowire thanks to the high hole mobility on the (110)-oriented side surface of the [110]-directed nanowire. The extracted mobility indicates that surface orientation plays a key role in nanowire mobility.
Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications
Authors: Veloso Anabela , Keersgieter An De , Aoulaiche Marc , Jurczak Malgorzata , Thean Aaron , Horiguchi Naoto
Published: March 2013

In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (I
OFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (I
ON/I
OFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.
Novel Extraction Method for Source and Drain Series Resistances in Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect-Transistors Based on Radio-Frequency Analysis
Authors: Kim Kyung Rok , Shin Sunhae , Cho Seongjae , Lee Jung-Hee , Kang In Man
Published: March 2013

In this work, we present a novel analytical method based on radio-frequency (RF) analysis for the accurate and reliable extraction of source and drain (S/D) series resistances in silicon nanowire (SNW) metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed method provides decomposed RF model equations for the gate-bias-independent off-state and gate-bias-dependent on-state components from both Y- and Z-parameters. The validity of our extraction method for S/D series resistances in SNW MOSFETs has been carefully tested in comparison with that of a previously reported method as well as with the physical three-dimensional (3D) device simulation. The schematically modeled Y- and Z-parameters have demonstrated excellent agreement with the numerical 3D device simulation results for various SNW MOSFET structures up to the 100 GHz frequency regime.
A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped Polycrystalline Silicon Nanowires
Authors: Lin Horng-Chih , Lin Zer-Ming , Huang Tiao-Yuan
Published: March 2013

In this study, we proposed a new methodology for probing the electrical properties of heavily doped polycrystalline silicon (poly-Si) nanowires (NWs), including active doping concentration, mobility, and interface fixed charge density. Implementation of this procedure is based on the modulation of the device operation of a gate-all-around (GAA) junctionless (J-less) transistor from the gated resistor mode to the ungated one. The extracted carrier concentration in the NW is found to be much lower than that of Hall measurements, while a negative fixed charge density is identified with the procedure. Dopant segregation at the oxide interface is postulated to be closely related to these observations.
Performance Fluctuations in 10-nm Trigate Metal–Oxide–Semiconductor Field-Effect Transistors: Impact of the Channel Geometry
Authors: Granzner Ralf , Schwierz Frank , Engert Sonja , Töpfer Hannes
Published: March 2013

Off-current and threshold voltage fluctuations in trigate (TG), and single-gate (SG) silicon-on-insulator (SOI) MOSFETs with a gate length of 10 nm are studied by means of three-dimensional (3D) device simulations. Special emphasis is paid to the role of the channel design. We demonstrate that both geometry fluctuations and the presence of single charged impurities in the active device regions can easily alter the off-currents of SG and TG MOSFET designs that nominally meet the I
on/I
off requirements by more than one order of magnitude. It will be shown that regarding the robustness against geometry fluctuations, neither the SG MOSFET nor one of the possible TG MOSFET designs can be preferred in general. The SG concept, however, turns out to be exceptionally robust against threshold voltage fluctuations caused by single charged impurities.
Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Liao Ming-Han , Chen Ci-Hua , Chang Li-Chen , Yang Chen , Yu Ming-Yuan , Liu Gan-Han , Kao Si-Cha
Published: March 2013

The comprehensive investigation on the effect of dislocation edge stress for Si N-type metal–oxide–semiconductor field-effect transistors (N-MOSFETs) is presented in this work by the experimental measurement and proposed simulation model. The accurate stress measurement in Si oxide dimension (OD) region with and without dislocation edge stress treatment is extracted by atomic force microscope (AFM)–Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment is observed successfully and has its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment are the more stress relaxation of the shallow trench insulator (STI) intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM–Raman spectra experimentally, the simulated stress from proposed finite element method, and its corresponding electrical characteristics agrees well with each other in this work. After the comprehensive understanding and calibrated model for the dislocation edge stress, the relationship between channel stress and dislocation edge shapes, including the angle and length of dislocation lines, is simulated and investigated clearly. It can be found that longer dislocation line and smaller dislocation angle can relax the intrinsic STI compressive stress more and should have the better electron carrier mobility and device performance for N-MOSFETs.
Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress
Authors: Choi Do-Young , Sohn Chang-Woo , Sagong Hyun Chul , Jung Eui-Young , Kang Chang Yong , Lee Jeong-Soo , Jeong Yoon-Ha
Published: March 2013

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔV
th) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔV
th caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of V
th. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.
Effect of Annealing Process on Trap Properties in High-k/Metal Gate n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors through Low-Frequency Noise and Random Telegraph Noise Characterization
Authors: Chiu Hsu Feng , Wu San Lein , Chang Yee Shyi , Chang Shoou Jinn , Huang Po Chin , Chen Jone Fang , Tsai Shih Chang , Lai Chien Ming , Hsu Chia Wei , Cheng Osbert
Published: March 2013

In this research, trap properties in n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with different annealing sequences have been studied on the basis of low-frequency (1/f) noise and random telegraph noise (RTN) analyses. The 1/f noise results indicate that the source of the drain current fluctuation is electron trapping. The higher trap density in the devices annealed before the TaN layer causes serious noise and lower trap energy in RTN results. The substitution mechanism explains that the increment of defects is due to the additional nitrogen atoms in HfO2. On the contrary, fewer defects in the devices annealed after the TaN layer are due to the effect of passivation in the TiN layer. The defect in HfO2 is the source of trapping/detrapping; thus, fewer defects cause the decrement of the fluctuation and the increment of the drain current. We believe that this process has a potential to remove defects in advanced MOSFETs.
1/f Noise Characteristics of Fin-Type Field-Effect Transistors in Saturation Region
Authors: Sakai Hideo , O'uchi Shin-ichi , Endo Kazuhiko , Matsukawa Takashi , Liu Yongxun , Ishikawa Yuki , Tsukada Junichi , Nakagawa Tadashi , Sekigawa Toshihiro , Koike Hanpei , Masahara Meishoku , Ishikuro Hiroki
Published: March 2013

In this work, we measured 1/f noise of independent-double-gate- (IDG-) fin-type FET (FinFET) which has two independent gates. Flicker noise of common-double-gate- (CDG-) mode which both gates are applied with the same voltage and IDG-mode that has one gate voltage grounded and the other gate voltage applied with arbitrary voltage, and both result were compared with the same drain current (I
d). First, we measured relationship between characteristic of the normalized 1/f noise by I
d (S

I
d
/I
d
2) and characteristic of I
d. Both the S

I
d
/I
d
2 of IDG- and CDG-modes show nearly equal values and tendency. Next, this work also shows the relationship between 1/f noise and vertical electric field (E
⊥) of surface of gate oxide film. As a result we could not definitely see a large margin of 1/f noise between CDG- and IDG-modes from E
⊥. This work also discovered that 1/f noise was greatly influenced by I
d density.
Characterization of Oxide Traps in 28 nm n-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Different Uniaxial Tensile Stresses Utilizing Random Telegraph Noise
Authors: Wang Bo-Chin , Wu San-Lein , Lu Yu-Ying , Huang Chien-Wei , Wu Chung-Yi , Lin Yu-Min , Lee Kun-Hsien , Cheng Osbert , Huang Po-Chin , Chang Shoou-Jinn
Published: March 2013

In this study, the effect of uniaxial tensile on the SiO2/Si interface of the 28 nm n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs) has been investigated. nMOSFETs were fabricated with different thicknesses of the stress-memorization technique (SMT) films to further increase channel stress because the SMT films can provide a higher uniaxial tensile to the channel. Trap behaviors such as activation energy and depth were characterized on the basis of drain current random telegraph noise (RTN). By RTN analyses, we found that the trap energy level is closer to the channel conduction band as the tensile strain in the channel increases higher, resulting in the trap being located close to the SiO2/Si interface.
A Column-Parallel Hybrid Analog-to-Digital Converter Using Successive-Approximation-Register and Single-Slope Architectures with Error Correction for Complementary Metal Oxide Silicon Image Sensors
Authors: Li Tsung-Ling , Sakai Shin , Kawada Shun , Goda Yasuyuki , Wakashima Shunichi , Kuroda Rihito , Sugawa Shigetoshi
Published: March 2013

In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximation-register (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-µm 1-poly 5-metal standard CMOS process. The conversion time is 1.225 µs with a maximum operation clock frequency of 40 MHz and it consumes 48 µW. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/-0.44 least significant bit (LSB) and +1.21/-1.12 LSB, respectively.
Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device
Authors: Nishitani Yu , Kaneko Yukihiro , Ueda Michihito , Fujii Eiji , Tsujimura Ayumu
Published: March 2013

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.
125 mW 102.4 GS/s Ultra-High-Speed Sampling Circuit for Complementary Metal–Oxide–Semiconductor Breast Cancer Detection System
Authors: Toya Akihiro , Sogo Kenta , Sasaki Nobuo , Kikkawa Takamaro
Published: March 2013

For application to an impulse-radio ultra-wideband (IR-UWB) portable breast cancer detection system, a 102.4 GS/s sampling circuit is developed. The high sampling rate is realized by an equivalent-time sampling technique and a low-power multi-clock generation circuit using a phase interpolator. The phase interpolator achieved a minimum phase resolution 9.8 ps. Using the sampling circuit, a tumor phantom buried by a breast phantom was detected.
Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm
Authors: Hou Zuoxun , Ma Yitao , Zhu Hongbo , Zheng Nanning , Shibata Tadashi
Published: March 2013

A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25 MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 µs, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.
High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa
Authors: Kashiwano Masashi , Hirai Jun , Ikeda Shunsuke , Fujimatsu Motohiko , Miyamoto Yasuyuki
Published: March 2013

We fabricated a vertical metal–insulator–semiconductor field-effect transistor (MISFET) with a heterostructure launcher and an undoped channel. Vertical MISFETs exhibit a high drain current density; however, their large output conductance is a disadvantage for the open-circuit voltage gain. In a previous study, a maximum voltage gain of 4.0 was found in a vertical MISFET with a heavily doped drain region and a 45-nm-wide channel mesa. The heavily doped drain region and a narrower channel width are effective in reducing the output conductance. In this study, we fabricated a device with the heavily doped drain region and a 23-nm-wide channel mesa structure. It was observed that the output conductance decreased from 120 to 57 mS/mm at a drain current density of 0.3 MA/cm2 with a narrower channel mesa. The maximum open-circuit voltage gain increased from 4.0 to 5.7.
Effects of Deep Trapping States at High Temperatures on Transient Performance of AlGaN/GaN Heterostructure Field-Effect Transistors
Authors: Tanaka Kenichiro , Ishida Masahiro , Ueda Tetsuzo , Tanaka Tsuyoshi
Published: March 2013

Kinetic studies on the current collapse of a normally-OFF AlGaN/GaN heterostructure field-effect transistor under a high voltage have been performed above room temperature. The ON-state resistance after the ON switching from the OFF state increases at high temperatures, contrary to the expectation that the emission of electrons is enhanced at elevated temperatures. This result indicates that elevating the temperature enhances not only the emission of electrons but also their capture. We experimentally observe that the enhancement of the capture process at high temperatures originates from the energy barrier for the capture of electrons, the value of which is determined to be 0.17±0.04 eV. The origin of the energy barrier for the capture process is explained by a configuration coordinate diagram.
Design of Silicon Photonic Crystal Waveguides for High Gain Raman Amplification Using Two Symmetric Transvers-Electric-Like Slow-Light Modes
Authors: Hsiao Yi-Hua , Iwamoto Satoshi , Arakawa Yasuhiko
Published: March 2013

We designed silicon photonic crystal (PhC) waveguides (WGs) for efficient silicon Raman amplifiers and lasers. We adopted narrow-width WGs to utilize two symmetric transvers-electric-like (TE-like) guided modes, which permit efficient external coupling for both the pump and Stokes waves. Modifying the size and shape of air holes surrounding the line-defect WG structures could tune the frequency difference between these two modes, at the Brillouin-zone edge, to match the Raman shift of silicon. Thus, small group velocities are also available both for pump and Stokes waves simultaneously, which results in a large enhancement of Raman gain. The enhancement factor of the Raman gain in the designed structure is more than 100 times that reported previously.
GaAs/AlAs Multilayer Cavity with Er-Doped InAs Quantum Dots Embedded in Thin Strain-Relaxed In0.45Ga0.55As Barriers for Ultrafast All-Optical Switches
Authors: Morita Ken , Ueyama Huga , Yasunaga Yukinori , Nakagawa Yoshinori , Kitada Takahiro , Isu Toshiro
Published: March 2013

A GaAs/AlAs multilayer cavity with a λ/2 AlAs cavity layer, which includes Er-doped InAs quantum dots (QDs) embedded in a thin strain-relaxed In0.45Ga0.55As barrier, was fabricated. Structural and optical properties were characterized by scanning electron microscopy and optical reflection measurements, respectively. We found that the cavity quality of the Er-doped QD cavity was improved by reducing the thickness of the strain-relaxed In0.45Ga0.55As barriers in the λ/2 AlAs cavity layer. Furthermore, time-resolved optical measurements were performed to study the relaxation time of the photogenerated carriers in the Er-doped QD cavity. A full width at half maximum of a 1 ps with a large reduction of slowly decaying carriers was obtained for the Er-doped QD cavity with a thin strain-relaxed In0.45Ga0.55As barrier.
Thermal Conductive Properties of a Semiconductor Laser on a Polymer Interposer
Authors: Amano Takeru , Ukita Shigenari , Ma Laina , Aoyagi Masahiro , Sugaya Takeyoshi , Komori Kazuhiro
Published: March 2013

We have calculated the thermal conductive properties and rate of temperature increase of a semiconductor laser on a polymer substrate. The temperature rises to 27 °C on the polymer interposer and the heat radiation effect is almost saturated in the case where the Au film has a thickness of 500 nm at 10 mW. Also, we have fabricated a 1.3 µm quantum dot (QD) laser with a stripe structure for the polymer interposer. We can achieve a low operating current threshold of 7 mA for the QD laser with a high mirror loss of 16 cm-1 at 1.3 µm emission because of the high quality of the QDs and the low scattering loss structure. Moreover, we have measured the heat distribution and rising temperature speed of a QD laser on a polymer substrate. These results indicate that we need to realize a high-efficiency laser source to achieve high transmission speeds in the future.
Optically Pumped Lasing Action with Unusual Wavelength of Approximately 390 nm in Hexagonal GaN Microdisks Fabricated by Radio-Frequency Plasma-Assisted Molecular Beam Epitaxy
Authors: Kouno Tetsuya , Sakai Masaru , Kishino Katsumi , Hara Kazuhiko
Published: March 2013

Hexagonal GaN microdisks exhibiting lasing action with unusual wavelengths of approximately 390 nm under an optically pumped condition have been investigated. The lasing action was caused by the resonant modes of the whispering gallery mode and/or quasi-whispering gallery mode in the hexagonal microdisks. A cross-sectional transmission electron microscopy observation indicated that multiple crystalline boundaries, which are formed by stacking faults, were included in the specific GaN microdisks exhibiting such an unusual lasing action. The origin of the optical gain was discussed, based on the modification of the crystal structure associated with the stacking faults.
Channel Length Scaling and Surface Nitridation of Silicon Nanocrystals for High-Performance Electron Devices
Authors: Ferdous Susoma Jannatul , Nakamine Yoshifumi , Kodera Tetsuo , Usami Koichi , Kawano Yukio , Oda Shunri
Published: March 2013

Silicon nanocrystal (SiNC)-based thin-film devices have been fabricated, where the idea of scaling down of channel length was implemented in such a way that very few SiNCs can be fitted inside the channel in the channel length direction in order to decrease the number of barriers to increase electrical conductivity. In this study, we have demonstrated the scaling down of channel length to 20 nm in order to reduce the number of barriers provided by each of the SiNCs, which are fabricated using a very high-frequency (VHF) plasma-enhanced chemical vapor deposition (CVD) system with a diameter of 10±1 nm. A high electrical conductivity has been achieved by optimizing channel length. In addition, we have demonstrated the surface nitridation of SiNCs to protect the highly reactive surface of SiNCs from further natural oxidization and successfully suppressed the degradation of transport properties.
Disorder-Induced Enhancement of Avalanche Multiplication in a Silicon Nanodot Array
Authors: Mori Nobuya , Tomita Masanori , Minari Hideki , Watanabe Takanobu , Koshida Nobuyoshi
Published: March 2013

Impacts of atomic disorder on avalanche multiplication in a one-dimensional silicon nanodot (SiND) array have been theoretically studied. The disorder lifts the degeneracy of the energy levels and reduces the impact-ionization threshold. This leads to a larger carrier multiplication factor in the disordered SiND array compared to an ideal SiND array without disorder or strain.
Integration of Complementary Metal–Oxide–Semiconductor 1-Bit Analog Selectors and Single-Electron Transistors Operating at Room Temperature
Authors: Suzuki Ryota , Nozue Motoki , Saraya Takuya , Hiramoto Toshiro
Published: March 2013

Silicon-based single-electron transistors (SETs) and complementary metal–oxide–semiconductor (CMOS) devices have been integrated onto a single chip, and the operation of SET/CMOS integrated circuits has been demonstrated at room temperature. The fabrication process of SETs has been improved in terms of parasitic resistance suppression, threshold voltage control, and reduction in required time for electron-beam lithography for integration with CMOS devices. There is no significant degradation in the characteristics of CMOS devices owing to the special fabrication process of SETs operating at room temperature. CMOS 1-bit analog selectors, which are building blocks of multibit address decoders, have been combined with SETs, and the circuit operation has been demonstrated at room temperature for the first time. These results show the feasibility of SET/CMOS integrated circuits composed of high-density arrays of SETs and high-performance CMOS peripheral circuits, which fully leverage the advantages of SETs and CMOS.
Influence of Coulomb Blockade on Wave Packet Dynamics in Nanoscale Structures
Authors: Shiokawa Taro , Fujita Genki , Takada Yukihiro , Konabe Satoru , Muraguchi Masakazu , Yamamoto Takahiro , Endoh Tetsuo , Hatsugai Yasuhiro , Shiraishi Kenji
Published: March 2013

Influence of Coulomb blockade on electron scattering by a quantum dot has been theoretically investigated using a multielectron wave packet simulation technique based on the time-dependent Hartree–Fock approximation. In our simulation, the bound states of electrons in the dot are self-consistently determined. We confirmed that Koopman's theorem keeps its validity only for weak Coulomb interactions. Moreover, we show that the maximum number of electrons trapped in the dot does depend on the strength of Coulomb interactions. Consequently, the transmission and reflection probabilities of an incident wave packet toward the dot are strongly influenced by the number of trapped electrons in the dot.
Resistance Switching Memory Characteristics of Si/CaF2/CdF2 Quantum-Well Structures Grown on Metal (CoSi2) Layer
Authors: Denda Junya , Uryu Kazuya , Watanabe Masahiro
Published: March 2013

A novel scheme of resistance switching random access memory (ReRAM) devices fabricated using Si/CaF2/CdF2/CaF2/Si quantum-well structures grown on metal CoSi2 layer formed on a Si substrate has been proposed, and embryonic write/erase memory operation has been demonstrated at room temperature. It has been found that the oxide-mediated epitaxy (OME) technique for forming the CoSi2 layer on Si dramatically improves the stability and reproducibility of the current–voltage (I–V) curve. This technology involves 10-nm-thick Co layer deposition on a protective oxide prepared by boiling in a peroxide-based solution followed by annealing at 550 °C for 30 min for silicidation in ultrahigh vacuum. A switching voltage of lower than 1 V, a peak current density of 32 kA/cm2, and an ON/OFF ratio of 10 have been observed for the sample with the thickness sequence of 0.9/0.9/2.5/0.9/5.0 nm for the respective layers in the Si/CaF2/CdF2/CaF2/Si structure. Results of surface morphology analysis suggest that the grain size of crystal islands with flat surfaces strongly affects the quality of device characteristics.
Nanogap Resistance Random Access Memory Based on Natural Aluminum Oxide
Authors: Miyabe Toru , Nakaoka Toshihiro
Published: March 2013

We report unipolar and bipolar resistive switchings in naturally oxidized Al
x
O1-x
thin films. We find a relationship between the switching behavior and the electrode gap distance. The macro-gap device with the electrode separation of 20 µm shows a unipolar switching behavior while the nano-gap device with the separation of 40 nm shows a bipolar behavior. The result is explained by a model in which the unipolar or the bipolar switching is governed by the way of the carrier injection into oxygen vacancies.
Efficient Solution-Processed Green Phosphorescent Organic Light-Emitting Diodes Using Bipolar Host Material
Authors: Tsai Yu-Sheng , Chittawanij Apisit , Juang Fuh-Shyang , Hong Lin-Ann , Ou Chih-Yuan
Published: March 2013

Solution-based processing was applied to fabricate green phosphorescent organic light-emitting diodes (OLEDs). EPH31 was used as a phosphorescent host, doped with guest dopant green phosphorescent Ir(ppy)3, and dissolved in chlorobenzene solvent to form the emitting layer. Device structural parameters were controlled by changing the spin coating speed of the emitting layer and hole injection layer [poly(3,4-ethylene dioxythiophene):poly(styrene sulfonate), PDOT:PSS] to adjust the thickness of the electron transport layer [tris(8-hydroxyquinolinato)aluminum, Alq3]. In addition, the differences in using CsF and LiF materials as the electron injection layer were investigated. A maximum current efficiency of 13.6 cd·A-1 was obtained at a high emitting layer spin coating speed. Despite the close resemblance in both the luminance intensity and current efficiency when using CsF and LiF as the electron injection layer, CsF devices had a low driving voltage. Smooth and stable films resulting from the spin coated hole injection layer, along with the control of the thickness of the electron transport layer (Alq3) and electron injection layer (CsF), effectively improved the performance of green OLEDs. The emitting layer host material (CBP) and three guest dopants [Firpic, Ir(ppy)3, and Ir(piq)2] were dissolved in toluene solvent during solution preparation to fabricate white OLEDs. The properties of the resulting solution-processed white PHOLEDs are a current efficiency of 2.4 cd·A-1 at 20 mA·cm-2 and CIE coordinates of (0.33, 0.33) at 9 V. Results of these experiments demonstrate that solution processing can be used as an alternative to and in conjunction with thermal evaporation.
A Novel Microscope for Visualizing Electric Fields in Organic Thin Film Devices Using Electric-Field-Induced Second-Harmonic Generation
Authors: Taguchi Dai , Manaka Takaaki , Iwamoto Mitsumasa , Karasuda Tetushu , Kyomasu Mikio
Published: March 2013

We have developed a novel microscope for visualizing electric fields in organic thin film devices on the basis of electric-field-induced second-harmonic generation (EFISHG) measurement. By using a radial polarized laser beam as a probing light, we showed that the electric field formed in metal–C60–metal diodes in the film-thickness direction is visualized. The developed microscope has a potentiality in directly visualizing carrier motion in thin-film devices such as organic solar cells.
Photocurrent Enhancement in Porphyrin–Silver Nanoparticle Composite Films Using Nanostructures of Silver Nanoparticles
Authors: Matsumoto Ryuji , Yamada Sunao , Yonemura Hiroaki
Published: March 2013

The fabrication of tetraphenyl porphyrin (TPP)–silver nanoparticle (AgP) composite films on indium–tin oxide (ITO) electrodes was carried out by the electrostatic layer-by-layer adsorption technique. Maximum enhancement in photocurrent action spectra as well as in fluorescence emission spectra was observed at an immersion time of 2 h. The effects of AgP on photocurrent and fluorescence suggested the effects of enhanced electric fields resulting from a localized surface plasmon resonance on the enhancement of photocurrent and fluorescence signals. The effect of AgP on the lifetime of the singlet excited state of TPP (1TPP*) indicated that the lifetime of 1TPP* decreases as compared with that in the absence of AgP substrate. The results on fluorescence lifetime suggested that the difference between the effects of AgP on photocurrent and fluorescence is most likely ascribed to the notion that the energy transfer from 1TPP* to surface plasmons due to AgP aggregates competes with photoinduced electron transfer from 1TPP* to O2 during photocurrent measurement.
Three-Dimensional Simulation of DNA Sensing by Ion-Sensitive Field-Effect Transistor: Optimization of DNA Position and Orientation
Authors: Nishio Yuki , Uno Shigeyasu , Nakazato Kazuo
Published: March 2013

Full three-dimensional simulation of DNA detection by ion-sensitive field-effect transistor technology is presented. DNA conditions for improving the sensing characteristics, namely, increased hybridization signal, are clarified. Poisson's equation is solved using a full three-dimensional finite element method for the model, where the model space consists of an electrolyte, DNAs, a self-assembled monolayer, and an insulator. The flatband voltage shift due to the hybridization of randomly positioned and oriented DNA is similar to experimental data, and indicates the possibility of experimental prediction. We examine the effects of DNA position and orientation on flatband voltage shift, and it is noted that the hybridization signal becomes largest when the DNAs are tilted 90° and distributed at equal intervals. It is also noted that a large hybridization signal can be obtained when upright DNAs are tightly immobilized even if it is difficult to tilt the DNAs.
Biomimetic Trehalose Biosensor Using Gustatory Receptor (Gr5a) Expressed in Drosophila Cells and Ion-Sensitive Field-Effect Transistor
Authors: Lau Hui-Chong , Bae Tae-Eon , Jang Hyun-June , Kwon Jae-Young , Cho Won-Ju , Lim Jeong-Ok
Published: March 2013

The development of potential applications of biosensors using the sensory systems of vertebrates and invertebrates has progressed rapidly, especially in clinical diagnosis. The biosensor developed here involves the use of Drosophila cells expressing the gustatory receptor Gr5a and an ion-sensitive field-effect transistor (ISFET) sensor device. Gustatory receptor Gr5a is expressed abundantly in gustatory neurons and acts as a primary marker for tastants, especially sugar, in Drosophila. As a result, it could potentially serve as a good candidate for potential biomarkers of diseases in which the current knowledge of the cause and treatment is limited. The developed ISFET was based on the outstanding electrical characteristics of the metal–oxide–semiconductor field-effect transistor (MOSFET) with a subthreshold swing of 85 mV/dec, low leakage current of <10-12 and high on/off current ratio of 7.3×106. The SiO2 sensing membrane with a pH sensitivity of 34.9 mV/pH and drift rate 1.17 mV/h was sufficient for biosensing applications. In addition, the sensor device also showed significant compatibility with the Drosophila cells expressing Gr5a and their response to sugar, particularly trehalose. Moreover, the interactions between the transfected Drosophila cells and trehalose were consistent and reliable. This suggests that the developed ISFET sensor device could have potential use in the future as a screening device in diagnosis.
A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure
Authors: Suzuki Daisuke , Lin Yuhui , Natsui Masanori , Hanyu Takahiro
Published: March 2013

A single-ended circuit using three-terminal magnetic tunnel junction (3T-MTJ) devices is proposed for a compact nonvolatile lookup-table (NV-LUT) circuit. The use of 3T-MTJ devices makes a high tunnel magneto-resistance ratio used in the circuit, because read-current path is separated from the write-current path. By utilizing single-ended circuit structure, the NV-LUT circuit becomes quite simple without reference circuit. In fact, the effective area of the proposed 6-input NV-LUT circuit is only 29% the size of the corresponding CMOS-based implementation using two-terminal-MTJ-based nonvolatile static random access memory cells, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS technology.
Molecular Beam Epitaxy of Co2MnSi Films on Group-IV Semiconductors
Authors: Kawano Makoto , Yamada Shinya , Oki Soichiro , Tanikawa Kohei , Miyao Masanobu , Hamaya Kohei
Published: March 2013

We explore epitaxial growth of Co2MnSi films on Si(111) or Ge(111) by means of low-temperature molecular beam epitaxy. We find that as-grown Co2MnSi films consist of mixed phases with L21-ordered structures and microcrystalline ones. As a result, the magnetic moment, which is nearly half of the ideal value, can be obtained even at very low growth temperature. Post-growth annealing was effective to crystallize the microcrystalline phases observed in the as-grown layer, leading to a further enhancement in the magnetic moment. We discuss a difference in growth mechanism between Co2MnSi and other Heusler alloys examined in our previous works.
Wafer-Level Electrical Evaluation of Vertical Carbon Nanotube Bundles as a Function of Growth Temperature
Authors: Vereecke Bart , Veen Marleen H. van der , Sugiura Masahito , Kashiwagi Yusaku , Ke Xiaoxing , Cott Daire J. , Hantschel Thomas , Huyghebaert Cedric , Tökei Zsolt
Published: March 2013

We have evaluated the resistance of carbon nanotubes (CNTs) grown at a CMOS-compatible temperature using a realistic integration scheme. The structural analysis of the CNTs by transmission electron microscopy (TEM) showed that the degree of graphitization decreased significantly when the growth temperature was decreased from 540 to 400 °C. The CNTs were integrated to form 150-nm-diameter vertical interconnects between a TiN layer and Cu metal trenches on 200 mm full wafers. Wafers with CNTs grown at low temperature were found to have a lower single-contact resistance than those produced at high temperatures. Thickness measurements showed that the low contact resistance is a result of small contact height. This height dependence is masking the impact of CNT graphitization quality on resistance. When benchmarking our results with data from the literature, a relationship between resistivity and growth temperature cannot be found for CNT-based vertical interconnects.
Analytic Compact Model of Ballistic and Quasi-Ballistic Cylindrical Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors Including Two Subbands
Authors: Cheng He , Uno Shigeyasu , Numata Tatsuhiro , Nakazato Kazuo
Published: March 2013

We propose a compact model of drain current in the ballistic and quasi-ballistic modes for cylindrical gate-all-around (GAA)-MOSFETs with two subbands based on the perturbation theory. By setting one unknown parameter, we can use it to express surface potential and electron confinement energy levels to calculate drain current analytically. With our compact model, we obtained a good agreement with the numerical compact model. In addition, we carry out a NMOS inverter circuit simulation using this model.
First Principles Calculations for Diffusion Barriers of Lithium Intercalation into Graphite with Various Edge Terminations
Authors: Kawai Takazumi
Published: March 2013

Lithium atom intercalation into a graphite layer from the step edge to the interlayer region with various edge terminations of graphite is investigated by first-principles electronic structure calculations. The interactions between the step edge and a Li atom depend on the functional group. There is little interaction of the edge with hydrogen termination, while a large interaction traps diffusing Li atoms for termination by oxidative functional groups. The hydroxylic termination would reduce the initial diffusion barrier for the intercalation. Therefore, the controlled edge termination would successfully enhance the charge and discharge properties of Li ion batteries; on the other hand, the progress of oxidative termination would decrease capacity and charge and discharge rates. The diffusion barrier heights of Li is comparable to or larger than those of other rate-limiting factors during charge and discharge, such as desolvation of Li from electrolyte.
Investigation of Cell Structure and Doping for Low-On-Resistance SiC Metal–Oxide–Semiconductor Field-Effect Transistors with Blocking Voltage of 3300 V
Authors: Hamada Kenji , Miura Naruhisa , Hino Shiro , Kawakami Tsuyoshi , Imaizumi Masayuki , Sumitani Hiroaki , Oomori Tatsuo
Published: March 2013

We have investigated the effect of n-type doping into the junction field-effect transistor region (JFET doping) on the static characteristics of 3300-V-class 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs). The JFET doping technique is significantly effective in reducing the on-resistance of SiC MOSFETs without degradation of the blocking characteristics when the MOS cells are properly designed. The JFET doping reduces the temperature coefficient of the resistance in the JFET region, leading to lower on-resistance of the SiC MOSFETs at high temperatures.
Reduction in Operating Temperature of 25 Series-Connected 820X Concentrator Photovoltaic Module
Authors: Ota Yasuyuki , Sueto Tsuyoshi , Nagai Hirokazu , Araki Kenji , Nishioka Kensuke
Published: March 2013

Under concentration conditions, it is important to manage the operating temperature of a concentrator photovoltaic (CPV) module, because a high-density solar energy enters into the solar cell. We measured the receiver temperature of the CPV module and evaluated the relationship between the temperature and output of the CPV module. 25 series-connected 820X CPV modules with 2- and 4-mm-thick back chassises were fabricated. In the case of a CPV module with a 4-mm-thick back chassis, the receiver temperature was markedly reduced owing to the effective thermal diffusion of the thicker chassis. The absolute conversion efficiency of the CPV module with the 4-mm-thick back chassis was 1.5% higher than that of the module with the 2-mm-thick back chassis. Moreover, we developed a thermal transfer model of the CPV module and calculated the thermal distribution in the CPV module using a thermal transfer simulator.
Post-annealing Effects on Characteristics of Crystalline Germanium Solar Cells with the Double Heterostructure
Authors: Kaneko Tetsuya , Kondo Michio
Published: March 2013

We fabricated crystalline germanium (c-Ge) heterojunction solar cells with a double heterostructure (DH) which consists of hydrogenated amorphous silicon (a-Si:H) layers. In the a-Si:H/c-Ge DH solar cell, the improvement of the conversion efficiency is obtained compared to the c-Ge solar cell having single heterostructure. We investigated effects of post-annealing on characteristics of Ge heterojunction solar cells. The open-circuit voltage (V
OC) of Ge heterojunction solar cells increases with increasing post-annealing temperatures above 150 °C. The increase of V
OC by post-annealing could be mainly explained by the improvement of passivation quality of a-Si:H for the c-Ge surface. Our results suggest that the a-Si:H double heterostructure is beneficial not only for c-Si-based heterojunction solar cells but also for c-Ge-based heterojunction solar cells.