(Invited) Process Development of CMOS TFTs for Monolithic 3D-IC Applications
Authors: Liao Kuei-Shu , Ruan Dun-Bao , Chiu Po-Chen 
Published: December 2020

Three-dimensional integrated circuit (3D-IC) technology has been used for vertical integration of multi-chip or stacked process in three-dimensional space for the scaling trend of sub-1 nm technical node, in order to overcome the physical limits of electronics and materials in the semiconductor process. Among them, monolithic 3D-IC has many features that can solve the challenge of stacking 2D molds and connecting them in the third dimension. 3D-IC has many significant advantages, such as heterogeneous integration, a smaller footprint but more powerful features, lower costs, reduced power, and higher bandwidth.

In this talk, process development of CMOS thin film transistor (TFT) for monolithic 3D-IC will be presented. The channel material of upper layer is the key concern for fabricating device stacked in 3-D space due to the process thermal budget. An amorphous indium gallium zinc oxide (a-IGZO) with activation temperature under 350 ℃ is regarded as the most promising transparent amorphous oxide semiconductor (TAOS) channel material for the advanced TFT device. However, the TAOS TFT is lack of p-channel device. Hence in this work, a top gate poly-Si p-channel TFT (pTFT) device was formed with tri-gate structure by using a self-aligned double patterning (SADP) process. Then, an a-IGZO n-channel TFT (nTFT) based on a bottom gate process were stacked with a monolithic architecture on the same wafer.

At first, the process development and optimization of individual AOS nTFT and poly-Si pTFT were carried out. The device structure of AOS nTFT includes a 100 nm-thick TiN metal bottom-gate, 10 nm-thick HfO2 gate dielectric, and IGZO channel. On the other hand, a 100 nm-thick TiN metal top-gate, 10 nm-thick HfO2/ 1 nm-thick SiO2 gate stack, p-type JL poly-Si channel, and tri-gate structure were applied for the poly-Si pTFT. Results show that the on/off current ratio (Ion/Ioff) values of AOS nTFT and poly-Si pTFT are 7 and 6.8 orders, respectively. And the subthreshold swing (S.S.) values are135 and 128 mV/decade, respectively. The device performance of the individual n/p TFTs in this work is similar to that of state-of-the-art devices.

Afterwards, hybrid CMOS inverter devices were fabricated and stacked with a monolithic 3D-IC architecture. The Ion/Ioff values of AOS nTFT and poly-Si pTFT are 7.1 and 6.3 orders, respectively. And the S.S. values are135 and 133 mV/decade, respectively. The device performance is quite similar to those of individual n/p TFT fabricated in our group before. Results indicate that the process integration of the AOS nTFT and poly-Si pTFT for monolithic IC is successful. The electrical characteristics of CMOS TFT inverter are pretty good. The voltage gain is ~ 25, the mid voltage is ~ 0.5 Vdd, and the high/low noise margins are large and approximately equal.

In order to further improve the performance of nTFT, a novel tungsten (W) dopant was applied to replace gallium (Ga) for ASO film due to its lower price and higher oxygen bond dissociation energy. With higher oxygen bond dissociation energy, the oxygen vacancy can be well controlled and the device may achieve better electrical and reliability characteristics. It is found that the a-IWZO nTFT shows a ION/IOFF value of 7.8 order and a S.S. value of 109 mV/decade. Furthermore, the mobility of a- IWZO TFT is about 2 times higher than that of a-IGZO TFT. The a-IWZO TFT with tiny W dopant as the carrier suppressor can exhibit a smaller S.S. value, suggesting that the channel can be effectively controlled even with higher channel conductivity.

To further improve the performance of pTFT, a polycrystalline germanium (poly-Ge) junctionless (JL) TFT is studied. The implantation and activation processes are not required for poly-Ge JL device because the vacancy and interstitial in poly-Ge film can act as acceptors, which naturally turn the film into p-type. However, Ge with poor thermal stability is very sensitive to process temperature. The Ge sub-oxides at Ge surface have lower bandgap, more oxide traps, and interface states, and they may diffuse into gate dielectric after thermal process, resulting in degradation of gate dielectric. The desorption and diffusion of GeOx can be suppressed by nitridation process on interfacial layer (IL) at high-k/Ge. Therefore, in this work, poly-Ge JL pTFT devices with various ILs including GeO2, GeON, O2 plasma-treated HfN, and O2 plasma-treated Al2O3 HfO2 are investigated and compared. The optimal IL for poly-Ge pTFT could be expected. Then, a CMOS device by integrating AOS nTFT and poly-Ge pTFT with a monolithic architecture will be performed as well.