bluuebunny/crossref_metadata_2025 huggingface dataset:
Investigation of Boudouard Reactions on Carbon-Based Solid Oxide Fuel Cells by Transient Techniques
Authors: Chien Andrew C. , Siengchum Tritti , Chuang Steven
Published: March 2011

Carbon-based solid oxide fuel cell (C-SOFC) is an effective approach for electric power generation because of its simplicity. The basic principle of the carbon-based fuel cell is electrochemical oxidization of solid carbon to CO2 on the anode. CO2 produced can further react with carbon fuel to generate CO via Boudouard reactions (C+CO2 → 2CO). Transient techniques consisting of pulse injection and step switch were used to study Boudouard reaction on C-SOFCs. The step switch and pulse transient studies showed that up to 90% of CO2 can be converted to CO, which was involved in electrochemical oxidation to increase power densities. The contribution of CO to increased power densities was confirmed by separating solid carbon and fuel cells in varying flow patterns. CO2 and CO were also found to displace adsorbed H2 on carbon fuels. The desorbed H2 was then oxidized to produce H2O on C-SOFCs.
Embedded Non-Volatile Memory Technologies
Authors: Shum Danny
Published: March 2011

The embedded Nonvolatile Memories (eNVM) technologies offer in-system re-programmability along with low voltage (LV), low power (LP), noise reduction, more reliable, and reduced system cost while maintain high speed, high density system performance over other NVM that including stand-alone Flash memory. The extent of market opportunity is driven by product cost. Manufacturability is the primary concern, rather than mere cell-size scalability. The design simplicity with integration compatibility of the logic core process to the additional NVM flow is a key factor when choosing memory cell. In this paper we will review different NVM concepts including cell design, from ROM to Flash, and to non-Si based memories and their applications in support of the diverse and emerging consumer market.
A Novel High Programming Efficiency and Highly Scalable Flash Memory Cell Based on Tunneling FET (TFET)
Authors: Qin Shiqiang , Tang Poren , Cai Yimao , Huang Qianqian , Tang Yu , Huang Ru
Published: March 2011

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is proposed and investigated in this paper. Based on the TFET structure, the proposed novel flash memory cell shows high programming efficiency, low power consumption, and good punch-through immunity. Unlike traditional NOR Flash cell which adopts the channel hot carrier (CHE) injection near drain side for programming operation, the TFET flash memory cell utilizes hot electrons injection introduced by band-to-band tunneling near source side for programming, which can achieve 3 orders higher programming efficiency due to greatly alleviated competition between the vertical electric field and lateral electric field. Moreover, the programming leakage current is 2 orders lower due to the high punch-through immunity for TFET structure. The obtained results and theoretical analysis demonstrate that the newly proposed flash cell can be a potential candidate for low power, and high density NOR-type flash applications.
Design of a 1-T Image Sensor by Simulation
Authors: Liu Xin-Yan , Zang Song-Gan , Lin Xi , Cao Cheng-Wei , Wang Peng-Fei , Zhang David Wei
Published: March 2011

A 1T silicon-based image sensor has been investigated in this paper. This device can fully accomplish the functions of the conventional 3T CMOS image sensor. In this paper, the basic performances including the dynamic range, read margin (signal-to-noise ratio) and information storage of the 1-T image sensor have been discussed. The applied voltages have been studied in detail, including the reset operation, read operation and exposure operation. The advantage of this device is the minimized cell size. The structure with a photo-diode integrated into the 1-T image sensor may give a higher density in the same chip area while the performance is not degraded. With more pixels in the same area, the fill factor will be raised to a large extent, and the resolution can be further improved.
Simulations of FDSOI CMOS with Sharing Contact between Source/Drain and Back Gate
Authors: Xu Miao , Liang Qingqing , Zhu Huilong , Yin Haizhou , Luo Zhijiong , Chen Dapeng , Ye Tianchun
Published: March 2011

In this paper, a new ultra-thin fully-depleted SOI CMOS structure with sharing contact between source/drain and back gate is presented to save area and increase threshold voltage tuning capability. TCAD simulations are used to investigate the back-gate effect on the ultra-thin SOI CMOS. A new process flow to make the fully-depleted SOI CMOS structures is also proposed.
Extraction and Analysis of Substrate Parameters in On-Chip Spiral Inductor Model
Authors: Li Xi , Ren Zheng , Chen Dawei , Shi Yanling
Published: March 2011

Inductors on high resistivity substrate, such as quartz or high resistivity silicon(HR-Si), can get better Q factor than those on low resistivity substrate, which makes it necessary to research the substrate influence on inductors. In this paper, a lumped element model for on-chip inductor that includes skin and proximity effects, substrate electric and magnetic losses at high-frequency range is presented. The proposed model has been verified with square spiral inductors with various geometrical configurations on quartz, SOI and high-resistivity silicon substrate. It shows good agreement with the simulation and tested results. This model can be easily used in circuit simulations and optimization design.
Opportunities and Challenges of FinFET as a Device Structure Candidate for 14nm Node CMOS Technology
Authors: Yamashita Tenko , Basker Veeraraghavan , Standaert Theodorus , Yeh Chun-Chen , Faltermeier Johnathan , Yamamoto Toyoji , Lin Chung-hsun , Bryant Andres , Maitra Kingsuk , Kulkarni Pranita , Kanakasabapathy Sivananda , Sunamura Hiroshi , Wang Junli , Jagannathan Hemanth , Inada Atsuro , Cho Jin , Miller Robert , Doris Bruce , Paruchuri Vamsi , Bu Huiming , Khare Mukesh , O'Neill James , Leobandung Effendi
Published: March 2011

FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain process. Key process improvements to resolve the FinFET unique challenges are presented. High drive currents have been obtained for both nFET and pFET. All these results show FinFET is the most promising candidate for 14nm node CMOS technology.
STI CMP: Exploration of a Colloidal Silica Based Slurry System
Authors: Song Peter , Yaoying Daisy Yao , Daw Sun Jack
Published: March 2011

With the size shrinking of IC transistors, more stringent polishing performance in shallow trench isolation (STI) CMP processes is requested in advanced fabrication processes. Up to date, most available STI slurries are ceria based. Technical challenges, such as scratches, rate instability, and handling, are the challenges to overcome. In addition, lower CoO is also desired. In this paper, colloidal silica based STI slurries are explored as an alternative. Different types of colloidal silica abrasives and chemicals are examined to understand their effects on HDP oxide removal rate and polishing selectivity of silicon nitride to silicon oxide. Planarization efficiency and slurry colloidal stability are also investigated. The results show that an abrasive type can make great difference on the removal rates of silicon nitride and silicon oxide. Certain proprietary chemicals can also greatly increase the selectivity of silicon oxide to silicon nitride without significant oxide losses in trenches. The capability of step height repairing can be tuned by carefully selected additives. The possible mechanism is also proposed. In addition, slurry handling can be improved by special designed dispersion agents. The preliminary data from the studies indicate that it is feasible to develop a silica based STI slurry to replace the traditional ceria based STI slurry. It also shows the potential to offer additional performance and cost benefits.
Linearity Improvement on MIM Capacitors
Authors: Chu Tsui Ping , Yang Peng , Kho Evie S. , Ang Yong Kheng , Tia Swee Hua
Published: March 2011

A study has been carried out to improve metal-insulator-metal (MIM) capacitor's capacitance density and linearity performance. The scopes of the study included single MiM and stack MIM structures. Different dielectric schemes were evaluated with their corresponding capacitance density, breakdown voltages and linearity coefficient to voltage and temperature variation etc. characterised. Trade-off of capacitance density and linearity observed with respect to the dielectrics thickness. In this paper, a special layout design and a new integration concept from stack MIM device will be introduced, with this, we can achieve both high capacitance density as well as ultra low voltage coefficients of capacitance for the desirbale good analog performance on MIM passive devices.
Fast Flexible Electronics Based on Printable Thin Mono-Crystalline Silicon
Authors: Ma Zhenqiang , Zhang Kan , Seo Jung-Hun , Zhou Han , Sun Lei , Yuan Hao-Chih , Qin Guoxuan , Pang Huiqing , Zhou Weidong
Published: March 2011

Traditional flexible electronics employ amorphous Si, poly Si and organic materials, but these materials cannot be used for fast (radio-frequency, RF) flexible electronics due to their low carrier mobilities. Instead, we employ monocrystalline Si as the active materials. These high quality materials were released from silicon-on-insulator by undercutting the buried oxide layer. They have equivalent mobility values as their bulk counterpart, yet with high mechanical flexibility. We realized the first RF flexible thin-film transistors by performing pre-release doping and changing the transistor fabrication process to gate-after-source/drain to avoid high temperature process on plastic substrate and achieve low source/drain contact resistance. We further increased the device speed with reduced source/drain access resistance through careful device structure design. By realizing smaller feature size (1µm) with local gate alignment and higher fidelity membrane registration/transfer technique, 12 GHz flexible thin-film transistors were demonstrated. Strained channel and nanolithography are projected to further increase device speed.
HHNEC 0.18um BCD Technology for High Density Power Integration
Authors: Shuai Zhang , Wensheng Qian , Ke Dong
Published: March 2011

A new 0.18um Bipolar CMOS DMOS (BCD) integrated platform is presented. This technology provides both N type and P type power LDMOS with capability of voltage up to 40V applications; these power LDMOS devices have competitive specific on-resistance; the parasitical miller capacitance and SOA of power LDMOS devices are optimized by careful device and layout design; it also provides HVCMOS with voltage up to 40V analog application; the bipolar devices in this technology are also optimized for power switching as standard bipolar process offers. The 1.8V/5.0V CMOS devices are performance compatible with industry main stream 1.8V/5.0V CMOS technology. This platform is modularized with various options; it can be separated into 1.8V/5.0V mixed 40V HVCMOS process, 5.0V Vgs 40V Vds 0.18um backend BCD process and 1.8V/5.0V Vgs 40V Vds 0.18um BCD process, which customers can easily choose for their product needs without any process tuning.
Dual Floating Gate Flash Cell Using Single Poly Processes
Authors: Lin Xi , Liu Lei , Liu Xin-Yan , Zanga Song-Gan , Cao Cheng-Wei , Wang Peng-Fei , Zhang David Wei
Published: March 2011

A novel memory device with dual floating-gate is investigated in this paper. The fabrication process of this device is compatible with the standard logic CMOS process flow using single gate poly. It can store 2 bits in a single cell without increasing the cell size. This study provides the fabrication process flow of the dual floating-gate devices. The transfer characteristics, programming, reading, and erasing performances are investigated. The crosstalk between these two floating-gates is also studied. Simulation results show a prosperous prospect of this device. It is promising for high density embedded FLASH applications.
Anomalous Behaviors of Cubic GaInN Ternary Alloys
Authors: Tit Nacir
Published: March 2011

The electronic and optical properties of cubic Ga_1-xIn_xN ternary alloys are theoretically investigated using the sp3s* tight-binding model, with the inclusion of spin-orbit interaction, versus composition and valence-band offset (VBO), stimulating the lattice-relaxation effects. Usually, the bowing of the band-gap energy in the common-anion ternary alloys should be vanishingly small as far as the virtual-crystal approximation remains valid. In contrary to this, the present alloys are shown to possess three unusual characteristics: (i) They possess rather strong bowing character with b > 2.0 eV; (ii) the bowing parameter is composition dependent b = b(x); and (iii) the Stokes shift between emission and absorption is so large that can even reach 200 meV when x ≈ 0.5. Two reasons are claimed to cause such behaviors; namely: the strong electro-negativity of nitrogen atoms and the large lattice relaxation as being induced by the large lattice-mismatch between the two constituents (GaN and InN). The favorable comparison with the available experimental data corroborates the above claims.
0.18um Scalable 7~45V pLDMOS for Smart Power Application
Authors: Liu Zhengchao , Tang Shushu , Shen James , Shao Chris
Published: March 2011

This work describes a 0.18um CMOS process based wide range scalable p-channel LDMOS transistor which targeted for power management application. The scalable pLDMOS is to use one process to cover different operation voltage devices, with the drain voltage scaling the device's specific on resistance (Rdson) must be always kept at a reasonable level and it is comparable with standalone technologies. The rated drain voltage can be continuously operated from 7V up to 45V, mean while the corresponding blocking voltage and Rdson are at 14V/6.5 mohm.mm2 and 60V/102 mohm.mm2 respectively.
A Fast OPC Algorithm for IC Layout Based on 1-D Cells after Optimization of Gap Distribution
Authors: Lin Bin , Xie Chenlei , Shi Zheng
Published: March 2011

As VLSI technology scales down to 45nm process node, reliable printing becomes a persistent huge challenge to IC's manufacturability. The limitation of RETs now forces people to adopt a regular 1-D cell design methodology. A method of extending the line-ends and inserting dummies to optimize the gap distribution, with which the layout based on 1-D cells could get better printability, has been proposed in recent studies. In this paper, we present a fast OPC algorithm for IC layout based on 1-D cells after the previously proposed optimization of gap distribution. With this algorithm, during the OPC process, the extended parts and dummies of the layout are excluded from correction to save run time, and only the functional parts of the layout will be corrected. Experimental results on 45 nm process show excellent efficiency of this algorithm.
Extension Use of Immersion Lithography for the 22nm Half-Pitch and Beyond
Authors: Kanaya Reiji
Published: March 2011

In double patterning process, exposure tools are required for better accuracy and productivity. NSR-S620D, which is Nikon immersion scanner, meets these requirements. This paper discusses the current status of Nikon immersion scanner and possibility to extend use of immersion lithography for the 22nm half-pitch and beyond
Cymer LPP EUV Source System Development Status
Authors: Lin Benjamin , La Fontaine Bruno , Brandt David , Farrar Nigel
Published: March 2011

In this paper, the technologies developed by Cymer to deliver clean EUV power will be reviewed. A high average power (>20kW) pulsed CO2 laser is used to create a Sn plasma by irradiating 30μm Sn droplets at a repetition rate of approximately 50kHz. The EUV light emitted by the Sn plasma is collected using a 5sr multi-layer mirror (MLM) collector and refocused at the intermediate focus (IF). The integrity of the MLM collector is maintained over time using debris mitigation techniques based on H2. A number of diagnostics are used to characterize the EUV light past IF. We will describe the performance of multiple laser-produced plasma (LPP) EUV sources, integrated with a 5sr MLM collector and debris mitigation.
Advanced Packaging Stepper for 300mm Wafer Process
Authors: Chang Zhou , Ling Huang
Published: March 2011

With development of advanced package technology, requirements for lithographic process become tighter than before. When dealing with 200mm or 300mm wafer, stepper shows better uniformity of CD and overlay. SS B500 stepper can be used in RDL and Bump process. This paper introduces features of SS B500 stepper, such as wide band exposure lightsource, large field size, flexible alignment strategy, direct focus measurement, and proposes absolute overlay error concept and measurement mothod based on golden wafer. It also provides test data for CDU, UDoF, overlay for single machine and matching, thick photo resist performance, which shows specification of the stepper meeting well with advanced package process.
Foundry Efficiency Gains Through Common Photolithography Themes
Authors: Lamb James E. , Chris Cox , Zhu Zhimin , Drain David , Sullivan Daniel
Published: March 2011

Here we examine photolithography methodologies to improve the efficiency of foundry and ASIC manufactures that have many part numbers with relatively low run volumes. In such cases, a fab must accommodate a large variety of device layers, topography dispersion, and layout parameters. These factors reduce the lithography process margin and limit design freedom and throughput in the lithography module. These factors also increase design complexity, optical proximity correction (OPC) design loops, mask cost, exposure dose, and number of material sets to meet layer requirements. Consequently, these factors impact the fab's overall efficiency. The primary method proposed to improve efficiency is to use a system that includes a planarizing etch transfer layer, an image transfer layer, and an image capture layer. By combining these elements, the lithography process becomes very predictable, simple, and repeatable, independent of the device
Evaluation of 193 nm Photoresist Material at Advanced Immersion Nodes
Authors: Hao Jing An , Xu Yao , Liu Chang
Published: March 2011

As 193 nm immersion lithography under single exposure moves toward the limit of 38 nm half pitch, more and more understanding has been achieved in the illumination. With the availability of same exposure tool and illumination condition, the key to the successful development of the photolithographic process will weigh toward good choice of and good process condition for the photoresist. Though different approaches exist for the evaluation of photoresists among major industrial players, the key understanding of the resist material has converged to some conservation quantity, which related to spatial resolution, line edge roughness, and resist sensitivity (RLS). Such quantity seems to be related to the formulation of modern chemically amplified photoresist. Although it is well-known that usual 193 nm photoresists needs a top coating for exposure tools that need water immersion since the water will interact with the acid that is created by photo-chemical reactions and caused patterning failure, recently, topcoat-less photo resist process was developed for immersion lithography with a small amount of additives blended into the conventional resist material. The availability of such resist has simplified the resist process and saved process cost, but may make the resist material more complicated. We have explored a number of normal immersion and topcoat-less immersion photoresists in the limit of 193 nm immersion lithography. We will present our data in the study of RLS and the resist profile.
248nm Process Is Capable for sub 0.09 um Groundrules
Authors: Wang Lei , Guo Xiaobo , Tong Yufeng , Meng Honglin , Su Bo , Xiao Shen'an
Published: March 2011

While the mainstream wafer production is at 0.065 and 0.045 um with 300 mm diameter wafers with ArF exposure tools systems, an idea to explore production feasibility under groundrules smaller than 0.09 um while maintain the cost advantages in KrF exposure tools systems becomes more and more popular and important to all companies including 300mm/200mm FAB. But the k1 factor for sub 0.09um with current popular KrF exposure tools will be about 0.31, which has the same level of complexity in optical proximity correction compared to 0.045 um at 0.93 NA with 193 nm exposure tools. Several RET (Resolution Enhancement Technology) techniques have been proposed for low k1 case and some good results have been achieved. However, each RET techniques has their own merits and demerits. It is still attractive to find out a solution with current KrF exposure tools, popular illumination settings and cost effective masks. In this paper, we will introduce our study for sub 0.09 um design rule with maximum 0.82NA KrF scanner tools. No special RET techniques are used and acceptable DOF, EL, MEEF, LWR and CD proximity are achieved. A novel photoresist optimization solution is both discussed.
Study to Transfer 0.11μm DRAM ArF Process to KrF Process in Litho
Authors: Liu Joe , Yao Eric , Fan Erics , Chang Kent , Lv Ted , Zhang Jeff , Liang Lee , Hong Jerry , Li Mars
Published: March 2011

To improve the 0.11μm DRAM capacity of foundry and save cost, with series of tests, we successfully transferred 0.11μm DRAM M0 (Bit Line) layer lithography process from the ArF(NA=0.7) process to high NA (0.8) KrF process.
Active Area Width and Topography Effects on Sub 45nm Poly Gate CD
Authors: Shen Man-Hua , Meng Xiao-Ying , Huang Yi , Zhang Hai-Yang , Chang Shih-Mou , Lee Kwok-Fung , Gu Yiming
Published: March 2011

Gate critical dimension (CD) is an important parameter in determining the CMOS device performance. During the process of aggressive feature size shrinking in 45nm node and beyond, aside from the recognized topographical impact on the wafer-to-wafer CD variation, the active area (AA) width has to be taken into consideration for the thorough analysis and the rigid control of within-wafer gate CD variation. Roughly 5%~8% within-wafer CD difference was observed on six gate structures (the same defined gate with different AA widths) right after the gate etch. Both topography wafer and blank wafer (deposited merely with gate oxide plus poly-Si) were utilized to identify the potential key contributors to such within-wafer CD variation. Results demonstrate that the shallow trench isolation (STI) step height, one of notorious topography factors, heavily relies on the local AA width. This leads to the instability of poly-Si film thickness, therefore resulting in the inconsistency of gate bottom profile. Despite, the optical proximity correction (OPC) based on the post-gate etch CD could be utilized to assuage the AA width related CD difference to some extent, the dependence of step height on AA width from the synergetic action of CMP and WET process should be solved for the fundamental solution to such within-wafer gate CD variation.
Plasma Etch Challenges for Porous Low k Materials for 32nm and Beyond
Authors: Labelle Catherine , Srivastava Ravi , Arnold John C. , Yin Yunpeng , Ishikawa Masao , Mignot Yann , Yusuff Hakeem , Linville Joseph , Horak David , Fuller Nicholas , Patz Ryan , Darlak A. , Zhou Kevin , Zhou Yifeng , Pender Jeremiah
Published: March 2011

The challenges facing back-end-of-line (BEOL) etch are becoming increasingly difficult as shrinking dimensions are compounded by new materials integration. As critical dimensions decrease, key dimension-related etch challenges include CD control, trench litho stack aspect ratios, RIE lag, and LER. The move to low k and ultra low k dielectrics requires the etch to consider the sensitivity of the films to compositional modification, polymer interactions with the pores, and diffusion effects possible with porous materials. As the minimum pitch reaches sub-100nm, new interactions of the materials with the critical dimensions need to be considered. The ability of low k materials to be patterned at the required aspect ratios without losing structural integrity will be the key challenge for future technologies' success. This paper will review the key etch challenges as a function of dimensions vs. materials and highlight where their interactions which will drive future work.
Dry Etch Process Effects on Cu/low-k Dielectric Reliability for Advanced CMOS Technologies
Authors: Zhou Jun-Qing , Sun Wu , Zhang Hai-Yang , Hu Min-Da , Li Fan , Song Xing-Hua , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2011

Cu and low-k dielectric based back-end-of-the-line (BEOL) interconnects is indispensable in advanced CMOS technologies for its significant improvement of chip resistance-capacitance (RC) delay. In this paper, we investigate the effects of dry etch process on the reliability of copper interconnects such as electromigration (EM), time dependent dielectric breakdown (TDDB) and stress migration (SM). Both the via height of its vertical part and the bevel profile of via isolation in dual damascene (DD) structure are detected to remarkably impact the final EM performance. Main contributors for TDDB include the low-k sidewall damage from ash, the interface necking right after the diluted HF (DHF) wet owing to insufficient sidewall passivation and the bowling profile from non-optimized integration process. EM enhancement related profiles are usually associated with smaller line top critical dimension (CD). This might degrade TDDB performance. We proposed the optimized etch method to address this trade-off issue. SM performance is normally defined by the mechanical and thermal properties of copper interface in DD structure. It can also be improved in etch process by post etch scheme such as N2/H2 treatment from the point view of polymer residue removal and copper interface repair.
WAT and VBD Distribution Improvement on Low-K Trench All-in-one Process
Authors: Hendrianto Jemmy , Zhijie Hao , Liu Andrew
Published: March 2011

WAT (Wafer Acceptance Test) and VBD (Voltage Breakdown) distribution are not merely a function of critical dimension and oxide thickness as were seen on conventional BEOL process on larger technology node. The complexity of electrical and reliability parameter becomes more on advanced technology node, i.e. 65nm and sub 65nm, as its k value and Cu surface plays some significant role on the parametric distribution result. This study is addressed to improve the WAT and VBD distribution by minimizing the Cu surface and low-k damage, such that the impact to the electrical parameter is small enough that can be negligible, hence the WAT and VBD will be more predictable and controllable. Optimization on this study would be focused on the chemical selection of the PR stripping and PET (Post Etch Treatment) steps, which are the critical steps for low-k and Cu surface damages.
Clean Mode Al Etch Process Development for Defect Reduction
Authors: Qiang Fan , Huang Cheng Lien , Hendrianto Jemmy , Song Jeff , Lv Mil , Wang Ken , Shi Cris
Published: March 2011

Clean mode chamber condition controlling provides a good method to improve Al etch defect performance. In the same time, it brings significant difference of physical performance such as CD, side wall, corrosion etc. In this study, in order to maintain clean chamber condition, Wafer-less Auto Clean(WAC) is introduced to clean out by-products deposition and optimized to achieve stable particle performance during full MTBC(mean time between clean). To compensate process shift because of chamber condition change, Al etch process and PR strip process are optimized. Cl2/BCl3 ratio, bias power and Cl2 gas flow in DARC step were found having significant impact on CD controlling. PR strip process adjusting has been proved to have great help to enlarge corrosion process window. One question that different Cl2/BCl3 ratio affect plasma sustaining when etching through TiN/Al interface was found during this study and need further efforts to find out the detail mechanism.
Theoretical And Experimental Development Of Advanced Dopant-Sensitive Systems
Authors: Zhang Ping Linda , Zhang Luchuan , Ye Yuda , Yang Y.
Published: March 2011

X-ray diffraction of antimony doped single crystal (100) surface with the concentration of 1.4~4.7x1018/cm3 is reported. The lattice constant is the same as Si. The anisotropic etching changed the very top fourfold rotational symmetrical (100) surfaces into the six-fold rotational symmetrical (111) surfaces. The etch rate is 100 times faster for our Sb doped (100) substrate vs. the pure silicon (100), using 20wt% KOH at 80~100ºC. The advanced wet etch develops facets that correspond to crystallographic planes and the advanced dopant-sensitive etching system which was measured.
Dry Etch Fin Patterning of a Sub-22nm Node SRAM Cell: EUV Lithography New Dry Etch Challenges
Authors: Altamirano-Sanchez Efrain , Yamaguchi Yoko , Lindain Jeffrey , Horiguchi Naoto , Ercken Monique , Demand Marc , Boullart Werner
Published: March 2011

This work describes the dry etching process for patterning crystalline Silicon (c-Si) on a 6T-SRAM cell using Extreme UV (EUV) lithography. The target fins consist of straight structures (30nm height and 15nm of critical dimension) patterned on a sub-22nm node with 80nm fin pitch. Scaling down the fin pitch had a direct influence on the fin critical dimension and profile. We found out that the fin etching process developed for a 22nm node process with 90nm fin pitch was no longer functional for patterning fins on a sub-22nm node with 80nm fin pitch. In order to pattern straight fins with 15nm of critical dimension, we had to improve the selectivity towards EUV photo resist, redesign the patterning stack thickness and eliminate the typical softlanding step used in previous nodes.
Porous SiOCH Integration: Etch Challenges with a Trench First Metal Hard Mask Approach
Authors: Possémé Nicolas , David Thibaut , Chevolleau Thierry , Darnon Maxime , Brun Philippe , Guillermet Marc , Oddou Jean Pierre , Barnola Sebastien , Bailly Fanny , Bouyssou Regis , Ducote Julien , Hurand Romain , Vérove Christophe , Joubert Olivier
Published: March 2011

The use of a metallic hard mask approach for porous dielectric film integration implies for patterning processes, different difficulties like dimensional control, bottom line roughness and residue formation or chamber conditioning. In this paper we propose to present these issues and associated solutions for p-SiOCH integration in dual damascene structure using a trench first metallic hard mask approach.
Plasma Etching Parameters Impact To Low-k Damage
Authors: Zhang Jihong , Pei Huiyuan , Cheng LH
Published: March 2011

Mechanical strength of low-k material greatly decreases; material composition change will also give dry etching a lot of problems which have never met before. This paper explores the approaches to solve new problems when plasma etching low-k material, such as avoiding low-k damage and other defects, keeping anisotropic and needed selectivity; finding out the process parameters with the biggest influence, such as gas species, pressure, RF frequency, power, etc. Applies the process trend to plasma etching low-k material (BD) of 40nm dual damascene trench etch and achieves the critical target.
Discovering Practical Use of Sensor Wafers in CCP Reactors
Authors: Milenin Alexey , Demand Marc , Boullart Werner , Arleo Paul
Published: March 2011

This paper reviews two types of sensor wafers that fit into the niche of spatially resolved in situ plasma diagnostics. The effect of both the incident power and the backside He flow on wafer surface temperature map was studied with the temperature sensor wafer. Another sensor wafer is designed to measure the distribution of displacement current passing through the wafer. Calibrated at 13.56 MHz, it is capable of working in a wider range of source frequencies which has successfully been demonstrated in CCP reactors. It was found that the particular type of plasma reactor and the process chemistry can impact the level of correlation between the sensor and the blanket etch rate uniformity data.
Study on Silicon Sieve Holes Array for Future Lithography Application
Authors: Si Weihua , Yin Ming , Qin Jian , Liu Zewen
Published: March 2011

Silicon sieve with nano-scale holes array used as atomic lithography aperture had been realized with a method combining of deep dry etching and silicon anisotropic wet etching. The influence of etchant concentration and temperature on the etching rate is carefully studied. Unusual bath temperature at 40° was used in the wet etching process. With a sputtered layer of Cr (300nm) as the wet etching mask and a layer of Al (700nm) as the deep dry etching mask nano holes array with 108nm feature size are obtained on single crystalline silicon.
Wafer Backside Particle Reduction By Optimizing AC3 Coating for Poly Etch Chamber
Authors: Ma Baoshan , Liu Wen-Jun , Niu Feng , Xia Jian-Jun , Cheng Lien-Huang , Liang Kun-Yueh
Published: March 2011

As semiconductor devices are being scaled down to CD (Critical Dimension) of 65nm and below, the control of chamber condition in Poly Etch chamber is critical to achieve stable CD and defect performance from wafer to wafer, lot to lot. AC3 (Advanced Chamber Condition Control) coating is widely used after traditional WAC (Waferless Auto Clean): an SiCl4 coating step is added after WAC to coat a thin layer on both chamber wall and ESC chuck. This layer maintains chamber in good condition for every wafer to achieve stable Etch Rate, CD and defect performance, while low quality coating makes wafer backside particle high. This paper introduces two key factors for SiCl4 coating quality control which affects wafer backside particle performance. One is SiCl4 gas overshoot, the other one is ESC temperature effect. The wafer backside particle high can finally cause wafer frontside high defect count.
Selective Epitaxial Growth: Trends in a Modern Transistor Device Fabrication
Authors: Hikavyy Andriy Y. , Vanherle Wendy , Dekoster Johan , Witters Liesbeth , Hoffmann Thomas , Loo Roger
Published: March 2011

Although selective epitaxial growth (SEG) of Si and SiGe is a recognized technology used by the semiconductor industry, continuing device scaling and appearance of new architectures impose new, more stringent and challenging requirements to it. SiGe growth with high Ge concentrations, layers integration in 3D structures, growth on alternatively oriented Si wafers and decrease of thermal budget are only few trends which we would like to address in this article. Problematic points raising concerns from the epi point of view are highlighted and solutions used at Imec are described in detail together with once proposed in literature.
Electron States at Interfaces of Semiconductors and Metals with Insulating Films
Authors: Afanas'ev Valeri V. , Houssa Michel , Stesmans Andre
Published: March 2011

Evolution of electron energy barriers at interfaces of AIV (Si, Ge), AIVBIV (GexSi1-x, SiC), and AIIIBV (GaAs, InxGa1-xAs, InP, GaSb) semiconductors with wide-gap oxide insulators is overviewed. Over a wide spectrum of studied materials no significant interface dipole contribution to the barrier height is found. Instead, it appears that the energy position of the top of the O2p-derived oxide valence band remains nearly constant, which can be used to evaluate the interface band alignment between oxides and semiconductors as well as between dissimilar oxides materials. By contrast, barriers for electrons at metal/oxide interfaces appear to be strongly affected by the interface processing indicating that near-interface oxide charges in combination with a resulting polarized metal surface may provide significant dipole contribution to the interface barrier height.
Annealing Effect on the Electrical Properties of La2O3/InGaAs MOS Capacitors
Authors: Kanda Takashi , Zade Dariush , Lin Yueh C. , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Nishiyama Akira , Sugii Nobuyuki , Chang Edward Y. , Natori Kenji , Hattori Takeo , Iwai Hiroshi
Published: March 2011

The electrical characteristics of InGaAs MOS capacitors with 8-nm-thick La2O3 gate dielectrics have been measured. The effect of annealing temperature and the annealing time on the interface state densities (Dit) have extracted. It has been found that the small Dit can be achieved with annealing of lower temperature for longer time.
Characteristics of HfSiAlON Gate Dielectric Prepared by Physical Vapor Deposition
Authors: Xu Gaobo , Xu Qiuxia
Published: March 2011

A gate stack with HfSiAlON as gate dielectric and MoAlN as gate electrode has been developed to obtain p-type band-edge metal gate stack. A corresponding gate dielectric equivalent oxide thickness (EOT) of 18Aå, and effective work function (EWF) of ~5.14eV were obtained by a gate last process. HfSiAlON dielectric is formed by depositing HfSiON with a AlNx cap at the top or bottom of interface on an ultrathin SiO2 by physical vapor deposition (PVD), and followed by an annealing at 900° for 30s. Further studies found that the EWF enhancement is dependent on not only the AlNx thickness but also its location. The EWF enhancement increases with the increase of the AlNx thickness. And the EWF enhancement is more pronounced cap for AlNx at the bottom interface. The corresponding mechanism is discussed.
Deposition of VOX Films by Reactive Sputtering and its Properties
Authors: Wei Xiaoying , Zhang Kailiang , Fang Wang , Wang Lanlan , Zhang Yang , Song Kai
Published: March 2011

In this paper, VOX thin films were deposited on the Cu/Ti/SiO2 substrates by reactive sputtering at room temperature and annealed under vacuum with different temperature. The crystal structure and morphology of VOX films with different annealing temperatures were characterized respectively by XRD and AFM, and the electrical switching properties were tested by Semiconductor Device Analyzer. The effects of annealing temperatures on structure and morphologies were discussed. Results showed that the film as-deposited was amorphous, and with the increasing of annealing temperature, there were V2O5, V2O3 etc mixture phases in the films. AFM results indicated that the crystal particles of the VOX thin films were enlarged from 300 to 500°. The in-suit morphologies have obvious changes from RT to 75°. The device unit by films annealed under 400° can achieve reversible metal-insulator transition (MIT), whose reset and set voltage are 0.56V and 1.12V.
ALD Ru and its Application in DRAM MIM-Capacitors and Interconnect
Authors: Schaekers Marc , Swerts Johan , Altimime Laith , Tőkei Zsolt
Published: March 2011

Ruthenium is proposed as electrode for next generation DRAM metal-insulator-metal capacitors and interconnect barrier/seed. This study compares different ALD processes to deposit Ru and RuO2 films. ALD with oxygen results in the deposition of either Ru or RuO2, depending on deposition conditions. We also report the growth and scalability of Ru films by plasma-enhanced ALD (PEALD) with ammonia. The inorganic precursor RuO4 was studied as an alternative chemical pathway, of which the characteristics and film properties were studied at temperature range 100-250ºC using various process conditions. The quality of films deposited with thermal ALD and PEALD is compared with respect to the targeted applications. In particular, the investigation of the thermal stability of the different Ru and RuO2 films under typical DRAM anneal conditions is presented.
Temperature and Stress effects on IMC Behavior of Thin Film Cu-Al System in Wire Bond
Authors: Ming XueFei , Fan KunQuan
Published: March 2011

Wire bond is widely accepted as the predominant method for the area of electronic packaging. Copper wire has been studied to instead of the gold and aluminum owing to its advantages. In this paper, authors focus on the nanoscale interfacial characteristics of thermosonic copper ball bonding on the aluminum metallization. A serious of examinations and a 2.5D finite element simulation have been designed to find the IMC generation and the stress distribution. After the data and results are demonstrated in detail, some conclusions are drawn from the previous work. By TEM and SEM analysis, authors found at different temperature, the IMC layers showed great difference in the thickness. By X-rd and TEM analysis, the IMC also show difference in the organization. By the finite element analysis, authors found the stress distribution when copper was bonding on the aluminum pad. As the IMC layer's material characteristics are different form the copper and aluminum material, so when bonding at improper temperature, the IMC layer will show a bad behavior under the stress. By SEM picture of the real situation, some cracks can be easily found. On the other hand, by doing the research, people can have a general idea of the proper temperature and force when using copper wire bond.
Influence of the Pressure on ZnO:Al Film Deposited by DC Magnetron Reactive Sputtering
Authors: Yu Song , Yang H. D. , Huang Bo , Shi J.D. , Zeng L. X.
Published: March 2011

Films were deposited on glass substrates by a DC magnetron sputtering method using a ZnO target doped with 2wt% Al2O3. Effects of sputtering on the structural, optical, and electrical properties of ZnO:Al films were investigated. The results showed that film's crystalline quality could be improved along the c-axis direction by increasing the sputtering pressure. Below 12.5Pa, grain size became more refined and the film's surface became more uniform. The resistivity of ZnO:Al films reached a minimum of 1.66×10−3 Ω·cm at 12.5Pa. The films' average transmittances were higher than 80% in the visible (400nm-800nm) region. Furthermore, the bathochromic shift phenomenon of absorption edge had been found in this process. Consequently, the properties of optical, electrical degraded with the increase of pressure above 12.5 Pa.
A Highly Conductive Bimodal Isotropic Conductive Adhesive and Its Reliability
Authors: Li Dongsheng , Cui Huiwang , Chen Si , Fan Qiong , Yuan Zhichao , Ye Lilei , Liu Johan
Published: March 2011

In this paper, micro silver flakes and micro spherical particles were incorporated into the matrix resin of isotropic conductive adhesives (ICAs). Their electrical properties were investigated. The total weight ratio of silver fillers was kept at 75 wt% for all samples. When the content of micro spherical particles was 8 wt%, the bulk resistivity of the bimodal ICAs reduced dramatically to as low as 1.26×10-4 Ω•cm and its viscosity was 24,289 cP under 5rpm at 25°. Scanning electronic microscopy (SEM) images of the bimodal ICAs showed silver fillers well distributed in the matrix resin. In addition, the lap shear strength of different metal surfaces, and the bulk resistivity shifts during aging time under85°/85% RH for more than 500 hours were also measured. The results showed that bulk resistivity shifts of bimodal ICAs remained stable after further cured and the bond strength on the copper surface was the greatest among the three metal surfaces tested.
A Study on Optimized Conditioner for Soft Pad in Cu Barrier Removal
Authors: Yoon So Young , Lee Joohan H.
Published: March 2011

In removing the Cu barrier in Cu CMP process, high- porosity soft pads have been commonly used. However, due to its high surface roughness of its initial state, the high-porosity pads have caused the continuous increase in wafer removal rate until being conditioned by diamond conditioners for a certain period of time which results in process instability and the excessive waste of consumables including slurries and dummy wafers. In this paper, the mechanism that soft pads causes the increase in wafer removal rate at the early stage of Cu barrier polishing and the methodology to stabilize the polishing process by minimizing the period of increase in wafer removal rate are studied. In order to do so, the pad morphology, pad wear rate, wafer removal rate, wafer non-uniformity of soft pads were evaluated as a function of the configurations of diamond conditioners, diamond protrusion, diamond density, grit size, diamond distributions.
Ge- and III/V-CMP for Integration of High Mobility Channel Materials
Authors: Ong Patrick , Witters Liesbeth , Waldron Niamh , Leunissen L.H.A.
Published: March 2011

For devices beyond the 15 nm generation the introduction of high mobility channel materials is foreseen. Ge has a very high hole mobility and is thus an interesting candidate for pMOS transistors. III/V-materials have very high electron mobility and thus provide interesting candidates for nMOS transistors. In this work we present a process-flow for the integration of Ge and III/V-materials as channel materials on bulk silicon wafers. The Ge- and III/V-CMP process is a critical step for this integration approach, as excessive material needs to be removed and the surface needs to be smoothened. Ideally, the use of high mobility channel materials, in combination with a high-k material as gate oxide, will result in a significantly improved transistor performance compared to devices with Si channels. In this paper we show results of the development for the Ge- and III/V-CMP.
Advanced Direct-Polish Process on Organic Non-Porous Ultra Low-k Fluorocarbon Dielectric on Cu Interconnects
Authors: Gu Xun , Nemoto Takenao , Tomita Yugo , Duyos Mateo Ricardo , Teramoto Akinobu , Kuroki Shin-Ichiro , Sugawa Shigetoshi , Ohmi Tadahiro
Published: March 2011

A direct-polish process has applied to the ultra low-k dielectric without the etch stop layer to reduce effective dielectric constant in damascene interconnects. In this study, the direct-polish process on organic non-porous dielectric, fluorocarbon (k=2.2), was demonstrated and an optimum direct-polish process condition was investigated. Mechanical effect, not chemical effect, on fluorocarbon degraded electrical properties by changing of chemical structure of fluorocarbon. A surface plasma treatment of fluorocarbon before polishing was applied to avoid the degradation of electrical characteristics during direct-polish and this result revealed that the surface plasma treatment of fluorocarbon is a practical technique in advanced Cu interconnects.
Study on the Ring Type Crater Defect Reduction in Cu CMP Process
Authors: Xu Jin-Hai , Lin Paulchang , Xing Charles , Li Pei , Ma Zhiyong
Published: March 2011

Copper has been used as inter-wiring in deep-submicron integrated circuit (IC) for its lower resistivity and potentially higher resistance to electro migration. Copper Chemical-mechanical polishing/planarization (Cu CMP) is used to remove the redundant Cu and Ta/TaN/oxide to achieve dual damascene interconnect structure. Crater defect is one of the most dangerous killer defects in Cu CMP process. In this research, we will focus on study the forming mechanism of one typical ring type crater defect. Also the solution is studied and carried out to eliminate this ring type crater defect.
Modeling Copper Chemical Mechanical Polishing Processes Using Linear System Method
Authors: Wu Lixiao , Yan Changfeng
Published: March 2011

In this paper, a solid-solid contact model is established for Cu CMP. The effects of different pattern structure on dishing and erosion during Cu CMP are investigated by the linear system method. The simulation results of the evolution of different pattern structure are given and are compared with experimental data. The effects of down force on the evolution of different pattern structure during overpolishing stage are also discussed. The simulation results show low down force will reduce dishing and erosion during Cu CMP.