bluuebunny/crossref_metadata_2025 huggingface dataset:
Measurement of Critical Thickness for the Formation of Interfacial Dislocations and Half Loop Arrays in 4H-SiC Epilayer via X-Ray Topography
Authors: Wang Huan Huan , Wu Fang Zhen , Dudley Michael , Raghothamachar Balaji , Chung Gil Yong , Zhang Jie , Thomas Bernd , Sanchez Edward , Mueller Stephan G. , Hansen Darren M. , Loboda Mark J.
Published: February 2014

Synchrotron X-ray Beam Topography (SWBXT) and KOH etching observations are presented of interfacial dislocations (IDs) and half-loop arrays (HLAs) which can form under certain growth conditions during homoepitaxy of 4H-SiC on off-cut substrates. The HLAs and IDs are observed to form from pairs of opposite sign basal plane dislocations in the substrate which intersect the substrate surface in screw orientation. These dislocations glide in opposite direction in the epilayer once critical thickness has been exceeded. Half-loop arrays are formed at the same time as the screw-type basal plane dislocations (BPDs) side-glide inside the epilayer. From knowledge of the formation mechanism of the HLAs [, if the line of the HLA is extended to intersect the original threading dislocation line direction, then the distance between this intersection point and the ID along the line direction of the original BPD provides a measure of the critical thickness. It is also calculated that the critical thickness in this case is largely determined by the mutual attractive force between the pairs of opposite sign threading BPDs in the substrate. In addition we observed both interfacial dislocations and HLAs generated from: (a) surface sources of BPDs; (b) micropipes; (c) 3C inclusions; and (d) substrate/epilayer interface scratches.
Study of V and Y Shape Frank-Type Stacking Faults Formation in 4H-SiC Epilayer
Authors: Wang Huan Huan , Wu Fang Zhen , Byrapa Sha Yan , Yang Yu , Raghothamachar Balaji , Dudley Michael , Chung Gil Yong , Zhang Jie , Thomas Bernd , Sanchez Edward , Mueller Stephan G. , Hansen Darren M. , Loboda Mark J.
Published: February 2014

Nomarski optical microscopic, KOH etching and synchrotron topographic studies are presented of faint needle-like surface morphological features in 4H-SiC homoepitaxial layers. Grazing incidence synchrotron white beam x-ray topographs show V shaped features which transmission topographs reveal to enclose 1/4[0001] Frank-type stacking faults. Some of these V-shaped features have a tail associated with them and are referred to as Y-shaped defects. Geometric analysis of the size and shape of the V-shaped faults indicates that they are fully contained within the epilayer and appear to be nucleated at the substrate/epilayer interface. Detailed analysis shows that the positions of the V-shaped stacking faults match with the positions of c-axis threading dislocations with Burgers vectors of c or c+a in the substrate and thus appear to result from the deflection of these dislocations onto the basal plane during epilayer growth. Similarly, the Y-shaped defects match well with the substrate surface intersections of c-axis threading dislocations with Burgers vectors of c or c+a in the substrate which were deflected onto the basal plane during substrate growth. Based on the observed morphology of these defect configurations we propose a model for their formation mechanism.
Three-Dimensional Imaging of Extended Defects in 4H-SiC by Optical Second-Harmonic Generation
Authors: Tanuma Ryohei , Tsuchida Hidekazu
Published: February 2014

This paper demonstrates optical second-harmonic generation (SHG) and two-photon excited photoluminescence (2P-PL) imaging of 3C-SiC inclusions forming triangular and carrot-type defects in 4H-SiC epilayers. Triangular defects exhibit clear SHG images because 3C-SiC is SHG active, but not 4H-SiC host crystal in c-axis incidence. A carrot defect provides SHG and 2P-PL images in different regions in a basal-plane fault area. The spectrums of the SHG and 2P-PL are also investigated, and their emission mechanisms discussed.
Structure and Origin of Carrot Defects on 4H-SiC Homoepitaxial Layers
Authors: Dong Lin , Sun Guo Sheng , Yu Jun , Yan Guo Guo , Zhao Wan Shun , Wang Lei , Zhang Xin He , Li Xi Guang , Wang Zhan Guo
Published: February 2014

A kind of broken carrot defects which are not parallel to the step flow direction are observed on 4H-SiC epilayer surfaces. We use the molten KOH and polishing methods to reveal the structure and source of the broken carrots. It is shown that the broken carrot defects still contain the prismatic stacking fault (SF) and basal plane SF and originate from threading screw dislocation on the substrate. The presence of other substrate threading dislocation can disturb the expansion of prismatic SF. This leads to the appearance of the broken carrot.
Origin Analyses of Trapezoid-Shape Defects in 4-Deg.-off 4H-SiC Epitaxial Wafers by Synchrotron X-Ray Topography
Authors: Yamashita Tamotsu , Matsuhata Hirofumi , Miyasaka Yoshihiko , Momose Kenji , Sato Takayuki , Kitabatake Makoto
Published: February 2014

The trapezoid-shape defects are one of the most common surface defects on current 4H-SiC epitaxial film surface since they give rise negative impact for MOS-devices. We have investigated structures and origins of the defects. It is discovered that the possible origins of the trapezoid-shape defects are basal plane dislocations (BPDs), threading edge dislocations (TEDs), threading screw dislocations (TSDs),and the short dislocation loops introduced under scratches.
Micro-Raman Characterization of 4H-SiC Stacking Faults
Authors: Piluso Nicolo’ , Camarda Massimo , Anzalone Ruggero , La Via Francesco
Published: February 2014

Micro-Raman characterization has been used as alternative technique to the photoluminescence in order to detect and study 4H-SiC stacking faults. The alteration of the crystalline stacking sequence perturbs the phonon-plasmon coupling which acts between the crystalline phonon modes and the electronic plasma, due to the doping element (N). The shape and the symmetry of the Longitudinal optical Raman mode is strongly correlated to the doping level of the material thus, through the monitoring of the Raman mode, the spatial morphology of the defect can be completely recovered and compared to the results provided by photoluminescence technique. The results show that such a technique allows a very fast inspection on large wafer, because it is totally independent of the stacking fault photoluminescence signals, which cover a large energy range, up to 0.7 eV.
Spiral Step Dissociation on PVT Grown SiC Crystals
Authors: Seiss Martin , Ouisse Thierry , Chaussende Didier
Published: February 2014

Under specific and reproducible conditions we observed that the top bilayer of a spiral step can detach from the remaining bunched step. This dissociated bilayer is located in the middle of a terrace. In this work we detail the parameters for which the spiral step dissociation appears. Furthermore the possible origins of this effect and the reasons why the dissociated step is located in the center of a terrace are discussed.
Formation of Double Stacking Faults from Polishing Scratches on 4H-SiC (0001) Substrate
Authors: Ushio Shoji , Fujimoto Tatsuo , Tsuge Hiroshi , Katsuno Masakazu , Sato Shinya , Tani Komomo , Hirano Hosei , Yano Takayuki
Published: February 2014

Epitaxial layers grown on mechanically lapped 4H-SiC (0001) substrates were analyzed by using scanning ion microscopy (SIM), photoluminescence (PL) mapping and transmission electron microscopy (TEM). Even in the use of substrates with standard nitrogen concentration of 1.3 × 1019 cm-3, double Shockley-type stacking faults were observed to be formed in the epitaxial layer from the interface between the epitaxial layer and the substrate without any external stresses. Surface damaged layer seems to cause the formation of not only 2SSFs but also threading edge dislocation (TED) half-loops during epitaxial growth.
Nanoscale Characterization of SiC Interfaces and Devices
Authors: Giannazzo Filippo , Fiorenza Patrick , Saggio Mario , Roccaforte Fabrizio
Published: February 2014

This paper reviews some recent advances in the application of scanning probe microscopy (SPM) electrical characterization techniques to several critical surface and interface issues in SiC technology. High resolution carrier profiling capabilities in SiC of scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) were employed for several applications. These included two-dimensional (2D) imaging of doped regions in SiC devices (to be used as input for device simulations or as a feedback for device processing) and the quantitative evaluation of the electrically active profiles of P (or N) and Al implanted 4H-SiC after high temperature treatments. Furthermore, the electrical modification of the SiO2/4H-SiC interface in MOS devices subjected to post-oxide-deposition treatments in NO or N2O and POCl3 have been investigated, providing quantitative information on the electrical activation of incorporated N or P in the few-nm-thick SiC interfacial region. The lateral homogeneity of metal/SiC interfaces was probed at nanoscale by conductive atomic force microscopy (CAFM), with a special emphasis given to the case of Schottky contacts on 3C-SiC, where the diode behaviour is strongly affected by the high density of electrically active defects in the substrate. Finally, CAFM has been employed to study the current transport in epitaxial graphene (EG) grown on 4H-SiC (0001), revealing the impact of the substrate morphology (terraces and steps or facets) on the local conductivity.
C-Face Interface Defects in 4H-SiC MOSFETs Studied by Electrically Detected Magnetic Resonance
Authors: Umeda Takahide , Okamoto Mitsuo , Arai Ryo , Satoh Yoshihiro , Kosugi Ryouji , Harada Shinsuke , Okumura Hajime , Makino Takafumi , Ohshima Takeshi
Published: February 2014

This paper reports an EDMR (electrically detected magnetic resonance) observation on 4H-SiC(000-1) “C face” MOSFETs. We found a new strong EDMR signal in wet-oxidized C-face 4H-SiC MOSFETs, which originates from intrinsic interface defects on C-face SiC-SiO2 structures.
Accurate Characterization of Interface State Density of SiC MOS Structures and the Impacts on Channel Mobility
Authors: Yoshioka Hironori , Nakamura Takashi , Senzaki Junji , Shimozato Atsushi , Tanaka Yasunori , Okumura Hajime , Kimoto Tsunenobu
Published: February 2014

We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.
Low Frequency Noise Analysis of Monolithically Fabricated 4H-SiC CMOS Field Effect Transistors
Authors: Martin Lucy Claire , Chan Hua Khee , Clark David T. , Ramsay Ewan P. , Murphy A.E. , Smith Dave A. , Thompson Robin. F. , Young R.A.R. , Goss Jonathan P. , Wright Nicholas G. , Horsfall Alton B.
Published: February 2014

Low frequency noise in 4H-SiC lateral p-channel metal oxide semiconductor field effect transistors (PMOSFETs) in the frequency range from 1 Hz to 100 kHz has been used to investigate the relationship between gate dielectric fabrication techniques and the resulting density of interface traps at the semiconductor-dielectric interface in order to examine the impact on device performance. The results show that the low frequency noise characteristics in p-channel 4H-SiC MOSFETs in weak inversion are in agreement with the McWhorter model and are dominated by the interaction of channel carriers with interface traps at the gate dielectric/semiconductor interface.
Estimation of Surface Recombination Velocities for n-Type 4H-SiC Surfaces Treated by Various Processes
Authors: Mori Yuto , Kato Masashi , Ichimura Masaya
Published: February 2014

We evaluated the carrier lifetime to estimate surface recombination velocities for 4H-SiC whose surfaces were treated by various processes. We found that the reactive ion etching (RIE) increased the surface recombination velocity, and we considered that point defects introduced by RIE influence the surface recombination velocity.
Mechanical Properties and Residual Stress of Thin 3C-SiC(111) Films Determined Using MEMS Structures
Authors: Hähnlein Bernd , Stubenrauch Mike , Michael Steffen , Pezoldt Jörg
Published: February 2014

3C-SiC(111) was grown on Si (111) in a thickness range between 20 and 600 nm by low pressure chemical vapour deposition. The mechanical properties and the residual stress were determined using cantilevers and beams. The Youngs modulus of the 3C-SiC(111) decreases with decreasing thickness of the epitaxial layer.
Influence of P+-Implantation and Post-Annealing on Warpage Structure of 4H-SiC Wafers
Authors: Ishiji Kotaro , Kawado Seiji , Hirai Yasuharu , Nagamachi Shinji
Published: February 2014

We examined the warpage structure in epitaxial 4H-SiC wafers subjected to phosphorus-ion (P+) implantation and post-annealing with varying implantation and annealing temperatures, using glazing-incidence monochromatic synchrotron X-ray topography. Using Raman spectroscopy, we then studied the relationship between the warpage of the crystal plane in the underlying epilayer and the recovery of lattice disorder in the implanted layer. We determined that the warpage structure of the underlying SiC epilayer was closely correlated with the recovery of lattice disorder in the implanted layer.
Residual Stress Measurements of 4H-SiC Crystals Using X-Ray Diffraction
Authors: Nakabayashi Masashi , Fujimoto Tatsuo , Tsuge Hiroshi , Kojima Kiyoshi , Abe Kozo , Shimomura Kohta
Published: February 2014

The room temperature residual stress of 4H-SiC wafers has been investigated using a precise X-ray diffraction method. A large strain was observed for the circumferential direction of wafers, more than ten times larger than those measured along the principal plane direction and the radial direction. Optimizing the lateral temperature distribution in growing crystals leads to reduction of residual stress of wafers with high crystal quality.
Evaluation of Mechanical and Optical Properties of Hetero-Epitaxial Single Crystal 3C-SiC Squared-Membrane
Authors: Anzalone Ruggero , D'Arrigo Giuseppe , Camarda Massimo , Piluso Nicolo’ , La Via Francesco
Published: February 2014

The aim of this work is to develop the bulge test technique combined with the micro-Raman analysis and a refined load-deflection model for high quality 3C-SiC squared-membranes. By the minimization of the total elastic energy, starting from the isotropic relation between the stress tensor and the strain tensor, it is possible to calculate the relationship between the maximum deflection and the applied pressure, in both regime of small and large deflection. Furthermore, the relationship between the measured shift of Raman Transverse Optical (TO) phonon modes and the total residual strain (Δa/a) within the epitaxial 3C-SiC layer was found and in order to understand the stress distribution within the membrane, TO Raman shift maps were performed along the corner and the border of the membrane.
Temperature Dependence of Impact Ionization Coefficients in 4H-SiC
Authors: Niwa Hiroki , Suda Jun , Kimoto Tsunenobu
Published: February 2014

Impact ionization coefficients of 4H-SiC were measured at room temperature and at elevated temperatures up to 200°C. Photomultiplication measurement was done in two complementary photodiodes to measure the multiplication factors of holes (Mp) and electrons (Mn), and ionization coefficients were extracted. Calculated breakdown voltage using the obtained ionization coefficients showed good agreement with the measured values in this study, and also in other reported PiN diodes and MOSFETs. In high-temperature measurement, breakdown voltage exhibited a positive temperature coefficient and multiplication factors showed a negative temperature coefficient. Therefore, extracted ionization coefficient has decreased which can be explained by the increase of phonon scattering. The calculated temperature dependence of breakdown voltage agreed well with the measured values not only for the diodes in this study, but also in PiN diode in other literature.
Crystallographic Structure of 8H- and 10H-SiC Analyzed by Raman Spectroscopy and Diffraction Methods
Authors: Hatayama Tomoaki , Hori Ryota , Yano Hiroshi , Fuyuki Takashi
Published: February 2014

Crystallographic structures of 8H-and 10H-SiC crystals were analyzed by the Raman spectroscopy and diffraction methods. Two and four transverse-optical modes for 8H-and 10H-SiC were observed, and their values were different from those of 4H-and 6H-SiC. Crystallinity for the wide and narrow areas of these crystals was analyzed by the Laue diffraction and the transmission electron microscope, respectively. Based on these results, the stacking sequences of these polytype were discussed.
Temperature and Electrical Field Dependence of the Ambipolar Mobility in N-Doped 4H-SiC
Authors: Hürner Andreas , Bonse C. , Clemmer G. , Kallinger B. , Heckel T. , Erlbacher T. , Mitlehner H. , Häublein V. , Bauer A.J. , Frey L.
Published: February 2014

In this study, we present results on electrical characterization of bipolar pn-diodes to investigate the temperature and electrical field dependent behavior of ambipolar mobility in n-doped 4H-SiC. Therefore, static current-voltage measurements to calculate the specific differential resistance and dynamical reverse recovery measurements to determine the mean carrier concentration were carried out for different temperatures and forward current densities. The specific differential resistance of the drift layer decreased from 10 mΩcm2 at 80 Acm-2 to 6.6 mΩcm2 at 180 Acm-2, whereas the mean carrier concentration only increased from 4.1015 cm-3 to 8.1015 cm-3, indicating a decreasing ambipolar mobility. The calculated reduction of the ambipolar mobility from 800 cm2V-1s-1 to 650 cm2V-1s-1 in dependence on the current density has to be attributed to an increasing electric field from 150 Vcm-1 to 250 Vcm-1 and increasing carrier scattering due to higher carrier concentrations. For example, at a constant conduction current density of 160 Acm-2, the ambipolar mobility decreases from 710 cm2V-1s-1 at 300 K to 650 cm2V-1s-1 at 450 K.
Theoretical Investigation of the Single Photon Emitter Carbon Antisite-Vacancy Pair in 4H-SiC
Authors: Ivády Viktor , Abrikosov Igor A. , Janzén Erik , Gali Ádám
Published: February 2014

Well addressable and controllable point defects in device friendly semiconductors are desired for quantum computational and quantum informational processes. Recently, such defect, an ultra-bright single photon emitter, the antisite carbon carbon vacancy pair, was experimentally investigated in 4H-SiC. In our theoretical work, based on ab initio calculation and group theory analysis, we provide a deeper understanding of the features of the electronic structures and the luminescence process of this defect.
First Principles Investigation of Divacancy in SiC Polytypes for Solid State Qubit Application
Authors: Szasz Krisztian , Ivády Viktor , Janzén Erik , Gali Ádám
Published: February 2014

We calculated the hyperfine structure and the zero-field splitting parameters of divacancies in 3C, 4H and 6H SiC in the ground state and in the excited state for 4H SiC within the framework of density functional theory. Besides that our calculations provide identification of the defect in different polytypes, we can find some carbon atoms next to the divacancy that of the spin polarizations are similar in the ground and excited states. This coherent nuclear spin polarization phenomenon can be the base to utilize 13C spins as quantum memory.
Impact of Carrier Lifetime on Efficiency of Photolytic Hydrogen Generation by p-Type SiC
Authors: Miyake Keiko , Yasuda Tomonari , Kato Masashi , Ichimura Masaya , Hatayama Tomoaki , Ohshima Takeshi
Published: February 2014

The photolytic hydrogen generation using sunlight attracts attention as a next generation energy technology. A key of this technology is a selection of materials for the photolysis and SiC is one of the candidate materials for this application. The conversion efficiency from the solar to the hydrogen energy would be affected by the carrier lifetime in SiC. Therefore, in this study, we measured carrier lifetimes in SiC and compared them with photocurrents in electrolytes that is directly correlated to the conversion efficiency.
Direct Observation of the Edge Termination of Surface Steps on 4H/6H-SiC {0001} by Tilted Low-Voltage Scanning Electron Microscopy
Authors: Ashida Koji , Kajino Tomonori , Kutsuma Yasunori , Ohtani Noboru , Kaneko Tadaaki
Published: February 2014

We demonstrate a simple method for direct observation of the stacking orientation on 4H/6H-SiC {0001} surfaces by low-voltage SEM. The difference in the direction of the stacking orientation is observed as SEM contrast. By utilizing this technique, the bond configuration at {1-10n} steps can be determined by the SEM contrast.
4H-SiC Bulk Growth Using High-Temperature Gas Source Method
Authors: Tokuda Yuichiro , Kojima Jun , Hara Kazukuni , Tsuchida Hidekazu , Onda Shoichi
Published: February 2014

Our latest results of SiC bulk growth by High-Temperature Gas Source Method　are given in this paper. Based on Mullins-Sekerka instability, optimal growth conditions to preclude dendrite crystals, which are one of the pending issues for high-speed bulk growth, was studied. First, the simulation studies showed that high temperature gradient in a growing crystal is required for high-speed bulk growth without dendrite crystals. Second, high-speed bulk growth was demonstrated under high temperature gradient.
Thin PSG Process for 4H-SiC MOSFET
Authors: Sharma Yogesh K. , Ahyi Ayayi C. , Isaacs-Smith Tamara , Modic Aaron , Xu Yi , Granfukel Eric , Jennings Michael R. , Fisher Craig , Thomas Stpehen M. , Mawby Philip  Andrew , Dhar Sarit , Feldman Leonard C. , Williams John
Published: February 2014

The use of phosphorous as a passivating agent for the SiO2/4H-SiC interface increases the field effect channel mobility of 4H-SiC MOSFET to twice the value, 30-40cm2/V-s, that is obtained with a high temperature anneal in nitric oxide (NO). A solid SiP2O7 planar diffusion source is used to produce P2O5 for the passivation of the interface. Incorporation of phosphorous into SiO2 leads to formation of phosphosilicate glass (PSG) which is known to be a polar material causes device instability. With a new modified thin phosphorous (P) passivation process, as described in this abstract, we can improve the stability of MOSFETs significantly with mobility around 75cm2/V.s.
Depletion-Mode TDDB for n-Type MOS Capacitors of 4H-SiC
Authors: Watanabe Tomokatsu , Hino Shiro , Ebiike Yuji , Miura Naruhisa , Imaizumi Masayuki , Yamakawa Satoshi
Published: February 2014

TDDB for n-type 4H-SiC MOS capacitors depleted by DC bias (named as depletion-mode TDDB) has been investigated. The lifetime distribution can apparently be classified into two groups: shorter and longer tBD. Breakdown for the shorter tBD occurs at a point close to a threading dislocation. In contrast, the capacitors possessing longer tBD include no dislocation. An increase in the stress temperature and/or EOX leads to a decrease in tBD, indicating that the breakdown is caused by gate-oxide degradation. On the other hand, the tBD distributions acquired by accumulation-mode TDDB are relatively even, and the breakdown point is independent of dislocations. We presume that holes excited in the SiC layer by hot electrons play an important role at a threading dislocation for depletion-mode TDDB.
Unexpected Effect of Thermal Storage Observed on SiC Power DMOSFET
Authors: Chbili Zakariae , Shreshta Pragya R. , Campbell Jason P. , Suehle John S. , Ioannou Dimitris E. , Cheung Kin P.
Published: February 2014

In this paper we report an unexpected improvement in the SiC DMOSFET transistor characteristics after a long temperature treatment at 150 C. The evolution of the device characteristics during a TDDB stress is compared to that after an elevated temperature treatment. The improvement in characteristics after storage at high temperature is believed to be due to instabilities caused by the quality of the SiO2/SiC interface and its large density of defects.
Reliability Improvement and Optimization of Trench Orientation of 4H-SiC Trench-Gate Oxide
Authors: Kojima Takahito , Harada Shinsuke , Ariyoshi Keiko , Senzaki Junji , Takei Manabu , Yonezawa Yoshiyuki , Tanaka Yasunori , Okumura Hajime
Published: February 2014

Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.
Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment
Authors: Yamada Keiichi , Ishiyama Osamu , Tamura Kentaro , Yamashita Tamotsu , Shimozato Atsushi , Kato Tomohisa , Senzaki Junji , Matsuhata Hirohumi , Kitabatake Makoto
Published: February 2014

This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.
High Mobility 4H-SiC MOSFETs Using Lanthanum Silicate Interface Engineering and ALD Deposited SiO2
Authors: Yang Xiang Yu , Lee Bong Mook , Misra Veena
Published: February 2014

In this work, we have developed a novel gate stack to enhance the mobility of Si face (0001) 4H-SiC lateral MOSFETs while maintaining a high threshold voltage. The gate dielectric consists a thin lanthanum silicate layer at SiC/dielectric interface and SiO2 deposited by atomic layer deposition. MOSFETs using this interface engineering technique show a peak field effect mobility of 133.5 cm2/Vs while maintaining a positive threshold voltage of above 3V. The interface state density measured on MOS capacitor with lanthanum silicate interfacial layers is reduced compared to the capacitors without the silicate. It is shown that the presence of the lanthanum at the interface reduces the formation of a lower quality SiOx interfacial layer typically formed at the SiC surface during typical high temperature anneals. This better quality interfacial layer produces a sharp SiC/dielectric interface, which is confirmed by cross section Z-contrast STEM images.
Reduction of Density of 4H-SiC / SiO2 Interface Traps by Pre-Oxidation Phosphorus Implantation
Authors: Sledziewski Tomasz , Mikhaylov Aleksey , Reshanov Sergey A. , Schöner Adolf , Weber Heiko B. , Krieger M.
Published: February 2014

The effect of phosphorus (P) on the electrical properties of the 4H-SiC / SiO2 interface was investigated. Phosphorus was introduced by surface-near ion implantation with varying ion energy and dose prior to thermal oxidation. Secondary ion mass spectrometry revealed that only part of the implanted P followed the oxidation front to the interface. A negative flatband shift due to residual P in the oxide was found from C-V measurements. Conductance method measurements revealed a significant reduction of density of interface traps Dit with energy EC - Eit > 0.3 V for P+-implanted samples with [P]interface = 1.5 1018 cm-3 in the SiC layer at the interface.
Experimental Studies on Water Vapor Plasma Oxidation and Thermal Oxidation of 4H-SiC (0001) for Clarification of the Atomic-Scale Flattening Mechanism in Plasma Assisted Polishing
Authors: Deng Hui , Endo Katsuyoshi , Yamamura Kazuya
Published: February 2014

4H-SiC is difficult to be polishing due to its high hardness and chemical inertness. We proposed a novel polishing technique named plasma assisted polishing (PAP), in which oxidation by water plasma and polishing soft abrasive were combined. In order to increase the material removal rate of PAP and clarify the atomic-scale flattening mechanism, experimental studies on water vapor plasma oxidation and thermal oxidation of 4H-SiC (0001) were conducted. Experimental results indicated that the initial oxidation rate of water vapor plasma oxidation (185 nm/h) was much higher than that of thermal oxidation (29nm/h). In the case of water vapor plasma oxidation, the oxide/SiC interface was rough when the oxide layer was thin and it became flatter along with the increase of the thickness of the oxide layer. In contrast, the oxide/SiC interface was atomically flat regardless of the thickness of the oxide layer in the case of thermal oxidation. CeO2 abrasive polishing was conducted on the oxidized SiC surfaces, well-ordered step/terrace structures were obtained in both cases. The step height was about 0.25 nm, which corresponds to a one-bilayer structure of 4H-SiC.
Deep Traps in 4H-SiC MOS Capacitors Investigated by Deep Level Transient Spectroscopy
Authors: Sveinbjörnsson E.Ö. , Gíslason Olafur
Published: February 2014

Using Deep Level Transient Spectroscopy (DLTS) on n-type MOS capacitors we find that thermal oxidation of 4H-SiC produces deep traps at or near the SiO2/SiC interface with two well defined DLTS peaks. The traps are located ~ 0.85 V and ~ 1.0 eV below the SiC conduction band edge and are present in wet and dry oxides as well as oxides produced by sodium enhanced oxidation and oxides grown in N2O. The deep traps are located at the SiO/SiC interface after oxidation at 1150°C but do extend further into the SiC epilayer after oxidation at 1240°C. We identify these traps as ON1 and ON2 which been observed in epitaxial layers after oxidation at very high temperatures (1200-1500°C) [.
Step-Bunching Dependence of the Lifetime of MOS Capacitor on 4o Off-Axis Si-Face 4H-SiC Epitaxial Wafers
Authors: Bandoh Akira , Suzuki Kenji , Miyasaka Yoshihiko , Osawa Hiroshi , Sato Takayuki
Published: February 2014

The step-bunching dependence of the lifetime of metal–oxide–semiconductor capacitors on 4° off-axis 4H-SiC epitaxial wafers was investigated. The effects of the C/Si ratios in epitaxial growth and the substrate properties were examined. Step-bunching was observed at the base of triangle or trapezoid defects. Step-bunching decreased as the C/Si ratio was reduced. Time-dependent dielectric breakdown (TDDB) measurements showed that the locations of short lifetime breakdowns closely matched step-bunching positions. TDDB measurements of four different commercial substrates showed clear differences in capacitor lifetime.
Growth of Gate Oxides on 4H-SiC by NO at Low Partial Pressures
Authors: Haasmann Daniel , Dimitrijev Sima , Han Ji Sheng , Iacopi Alan
Published: February 2014

In an attempt to significantly reduce the amount of nitric oxide (NO), commonly used to improve the quality of gate oxides on 4H–SiC, a series of alternative gate oxidation processes using a combination of O2 and NO gas mixtures at low partial pressures were investigated. The properties of 4H–SiC/SiO2 interfaces on n-type MOS capacitors were examined by the measurement of accumulation conductances over a range of frequencies. Oxide integrity was evaluated by current–voltage measurements and by the extraction of the conduction band offset barrier heights through Fowler–Nordheim (F–N) analysis. A notable reduction of accumulation conductance, indicating a reduction of near-interface traps (NITs), was observed over all measured frequencies for oxidation processes containing NO with a partial-pressure of only 2%. Gate oxides grown in mixture of O2 and NO at low-partial-pressures demonstrated a considerable improvement of dielectric properties, increasing the barrier height to near theoretical values.
Preparation and Characterization of Nitridation Layer on 4H SiC (0001) Surface by Direct Plasma Nitridation
Authors: Akahane Yoshiyuki , Kano Takuo , Kimura Kyosuke , Komatsu Hiroki , Watanabe Yukimune , Yamakami Tomohiko , Kamimura Kiichi
Published: February 2014

A nitride layer was formed on a SiC surface by plasma nitridation using pure nitrogen as the reaction gas at the temperature from 800°C to 1400°C. The surface was characterized by XPS. The XPS measurement showed that an oxinitride layer was formed on the SiC surface by the plasma nitridation. The high process temperature seemed to be effective to activate the niridation reaction. A SiO2 film was deposited on the nitridation layer to form SiO2/nitride/SiC structure. The interface state density of the SiO2/nitride/SiC structure was lower than that of the SiO2/SiC structure. This suggested that the nitridation was effective to improve the interface property.
Applications of Vapor-Liquid-Solid Selective Epitaxy of Highly p-Type Doped 4H-SiC: PiN Diodes with Peripheral Protection and Improvement of Specific Contact Resistance of Ohmic Contacts
Authors: Thierry-Jebali Nicolas , Lazar Mihai , Vo-Ha Arthur , Carole Davy , Soulière Véronique , Henry Anne , Planson Dominique , Ferro Gabriel , Konczewicz Leszek , Contreras Sylvie , Brylinski Christian , Brosselard Pierre
Published: February 2014

This work deals with two applications of the Selective Epitaxial Growth of highly p-type doped buried 4H-SiC in Vapor-Liquid-Solid configuration (SEG-VLS). The first application is the improvement of the Specific Contact Resistance (SCR) of contacts made on such p-type material. As a result of the extremely high doping level, SCR values as low as 1.3x10-6 Ω.cm2 have been demonstrated. Additionally, the high Al concentration of the SEG-VLS 4H-SiC material induces a lowering of the Al acceptor ionization energy down to 40 meV. The second application is the fabrication of PiN diodes with SEG-VLS emitter and guard-rings peripheral protection. Influence of some process parameters and crystal orientation on the forward and reverse characteristics of the PiN diodes is discussed.
n- and p-Type Doping of 4H-SiC by Wet-Chemical Laser Processing
Authors: Nishi Koji , Ikeda Akihiro , Marui Daichi , Ikenoue Hiroshi , Asano Tanemasa
Published: February 2014

Silicon carbide (SiC) is a promising semiconductor for high-power devices due to its superior material properties; high breakdown field, high electron saturation velocity, and high thermal conductivity. To implement SiC power devices, pn junction must be formed in the SiC. However, ion implantation for impurity doping has several issues for the SiC. For example, while a high-temperature (~1700 °C) post-implantation annealing is required to electrically activate implanted species [, it induces generation of crystallographic defects in the SiC, such as segregation of carbon atoms at the surface from the SiC bulk [. Therefore, development of new technology for local doping of SiC is highly demanded.
Properties of Al Ohmic Contacts to n-type 4H-SiC Employing a Phosphorus-Doped and Crystallized Amorphous-Silicon Interlayer
Authors: Hanafusa Hiroaki , Ohta Akio , Ashihara Ryuuhei , Maruyama Keisuke , Mizuno Tsubasa , Hayashi Shohei , Murakami Hideki , Higashi Seiichiro
Published: February 2014

Contact property of aluminum and 4H-SiC wafer with crystallized amorphous-silicon (a-Si) interlayer was investigated. A phosphorus-doped a-Si layer on SiC wafer was crystallized by annealing at 1377 °C. Good ohmic contact behavior and contact resistivity of 2.1 × 10-6 Ωcm2 were obtained without silicidation annealing process. Furthermore, non-doped crystallized a-Si layer insertion layer also showed ohmic contact property. However, high contact resistivity of 8.2×10-4 Ωcm2 was obtained in the non-doped a-Si sample. X-ray photo-electron spectroscopy analysis suggests that conduction band offset is significantly reduced between crystallized a-Si and SiC wafer. Therefore, a-Si insertion layer is effective for Schottky barrier height decreasing and high doping into Si layer forms low contact resistivity between Al and SiC, indirectly.
Microwave Annealing of Al+ Implanted 4H-SiC: Towards Device Fabrication
Authors: Nath Anindya , Parisini Antonella , Tian Yong Lai , Rao Mulpuri V. , Nipoti Roberta
Published: February 2014

Carrier transport in Al+ implanted 4H-SiC for Al concentrations in the 5 × 1019 5 × 1020 cm-3 range and after 2000°C/30s microwave annealing are characterized. Each sample resistivity decreases with increasing temperature and attains values of about 102 Ωcm for temperatures > 600 K. At room temperature, resistivity decreases from 4 × 10-1 Ωcm to 3 × 102 Ωcm with the increase of implanted Al concentration. The onset of an impurity band conduction around room temperature takes place for implanted Al concentrations > 3 × 1020 cm-3. Al+ implanted and microwave annealed 4HSiC vertical p+-i-n diodes have shown promising forward characteristics.
Development of a Novel Cap-Free Activation Annealing Technique of 4H-SiC by Si-Vapor Ambient Annealing Using TaC/Ta Composite Materials
Authors: Torimi Satoshi , Nogami Satoru , Kaneko Tadaaki
Published: February 2014

As a new post-implantation activation annealing of Silicon Carbide (SiC), we propose the Si-vapor ambient anneal using Tantalum Carbide / metal Tantalum composite materials (TaC/Ta). In this technique, semi-closed TaC/Ta container which can supply Si-vapor ambient is used, and Si vapor compensates thermal desorption Si atoms from the SiC surface above 1500°C and can maintain the original surface morphology by controlling a process temperature and Ar back pressure. Therefore the Si-vapor ambient anneal is able to simplify the process of conventional activation anneal methods using refractory cap-layers for protecting SiC surface from thermal damage of Si-atom desorption. Experiments were performed under Ar 1.3kPa at 1600/1700°C for 5min optimized conditions in a 6inch TaC/Ta container, and the Al+ ion-implanted 4H-SiC properties after annealing were characterized by atomic force microscopy (AFM), Rutherford Back-scattering Spectrometry (RBS) channeling method, and four-point probe method. According to evaluation, there was no roughening of SiC surface from AFM topographic images and recovery of crystallinity at the ion-implanted layer was equivalent to by the conventional cap-layer method from RBS channeling measurement. The sheet resistance of 12kΩ/ at 1700°C equal to the typical Al+ ion implanted p-type SiC is confirmed by four-point probe method.
Low Cost Ion Implantation Process with High Heat Resistant Photoresist in Silicon Carbide Device Fabrication
Authors: Fujiwara Takenori , Tanigaki Yugo , Furukawa Yukihiro , Tonari Kazuhiro , Otsuki Akihiro , Imai Tomohiro , Oose Naoyuki , Utsumi Makoto , Ryo Mina , Gotoh Masahide , Nakamata Shinichi , Sakai Takao , Sakai Yoshiyuki , Miyajima Masaaki , Kumura Hiroshi , Fukuda Kenji , Okumura Hajime
Published: February 2014

Cost of silicon carbide (SiC) wafer has been improved owing to the development of larger and higher quality wafer technologies, while the process stays long and complicated. In this paper, we propose a novel short process of ion implantation and provide the fabrication model SiC schottky barrier diodes (SiC-SBDs) devices. Currently common mask layer of ion implantation employs high heat resistant materials such as metal oxides. Because the ion is implanted to SiC wafer at high temperature between 300 °C and 800 °C due to avoid the damage of SiC crystal structure. The process using oxide layer tends to became long and complicated. On the other hand, our proposal process uses a heat resistant photoresist material as the mask instead of the oxide layer. The heat resistant photoresist is applied to newly developed SP-D1000 produced by Toray Industries, Inc.. We demonstrated to fabricate model SiC-SBDs devices based on our proposal process with SP-D1000 and confirmed the device working as same as a current process.
Characterization of Ohmic Ni/Ti/Al and Ni Contacts to 4H-SiC from -40°C to 500°C
Authors: Smedfors Katarina , Lanni Luigia , Östling Mikael , Zetterling Carl Mikael
Published: February 2014

Extreme temperature measurements of Ni/Ti/Al contacts to p-type SiC (Na = 1∙1018cm-3), with a specific contact resistivity ρc = 6.75∙10-4 Ωcm2 at 25 °C, showed a five time increase of the specific contact resistivity at -40 °C (ρc = 3.16∙10-3 Ωcm2), and a reduction by almost a factor 10 at 500 °C (ρc = 7.49∙10-5 Ωcm2). The same response of ρc to temperature was seen for contacts on lower doped epitaxial layer. Also N-type nickel contacts improved with higher operational temperature but with a considerably smaller variation over the same temperature interval. No degradation of the performance was seen to either the Ni/Ti/Al or the Ni contacts due to the high temperature measurements.
Microstructure Characterization of Si/Ni Contact Layers on n-Type 4H-SiC by TEM and XEDS
Authors: Wzorek Marek , Czerwiński Andrzej , Ratajczak Jacek , Borysiewicz Michał A. , Kuchuk Andrian V. , Piotrowska Anna B. , Kątcki Jerzy
Published: February 2014

Distribution of chemical composition in nickel-based ohmic contacts to n-type 4H-SiC was investigated with XEDS mapping performed on plan-view and cross-sectional TEM samples. Obtained results indicate that local deviations in stoichiometry from that of Ni2Si phase significantly contribute to degradation of surface morphology.
Electrical Characteristics of Schottky Contacts on Ge-Doped 4H-SiC
Authors: Vivona Marilena , Al Assaad Kassem , Soulière Véronique , Giannazzo Filippo , Roccaforte Fabrizio , Ferro Gabriel
Published: February 2014

We report on the electrical characteristics of Ni/4H-SiC Schottky contacts fabricated on a Ge-doped 4H-SiC epilayer. The morphology and the current mapping carried out by conductive atomic force microscopy on the epilayer allowed observing nanoscale preferential conductive paths on the sample surface. The electrical characteristics of Ni contacts have been studied before and after a rapid thermal annealing process. A highly inhomogeneous Schottky barrier was observed in as-deposited diodes, probably related to the surface electrical inhomogeneities of the 4H-SiC epilayer. A significant improvement of the Schottky diodes characteristics was achieved after annealing at 700°C, leading to the consumption of the near surface epilayer region by Ni/4H-SiC reaction. After this treatment, the temperature behavior of the ideality factor and Schottky barrier height was comparable to that observed on commercial 4H-SiC material.
Junction Formation via Direct Bonding of Si and 6H-SiC
Authors: Sasada Yukihiro , Kurumi Takamasa , Shimizu Hideo , Kinoshita Hiroyuki , Yoshimoto Masahiro
Published: February 2014

Si wafers were directly bonded to 6H-SiC wafers without the formation of an intermediate layer. Heterojunctions of n-Si/n-SiC and p-Si/n-SiC exhibited ohmic and rectifying characteristics, respectively, as expected based on their band lineups. Band bending of Si at the bonded interface was observed for Si/semi-insulating 6H-SiC heterointerfaces. This band bending can be explained by either heterojunction formation based on Anderson’s model or the existence of negative charge with a density of ~2 × 1010 cm−2 at the Si/SiC interface.
4H-SiC Planarization Using Catalyst-Referred Etching with Pure Water
Authors: Isohashi Ai , Sano Yasuhisa , Sadakuni Shun , Yamauchi Kazuto
Published: February 2014

A novel abrasive-free polishing method called catalyst-referred etching (CARE) has been developed. CARE can be used to chemically planarize a silicon carbide (SiC) surface with an etching agent activated by a catalyst. Platinum (Pt) and hydrofluoric (HF) acid are used as the catalyst and etchant, respectively. CARE can produce an atomically flat and crystallographically highly ordered surface of 4HSiC (0001) with a root-mean-square roughness of less than 0.1 nm regardless of the cut-off angle. However, industrial use of CARE is difficult because of HF acid usage. In this study, pure water was investigated as an alternative etchant to HF acid. We examined CARE using pure water by applying it to the planarization of a 4HSiC substrate and observed a feasible performance. The removal mechanism is considered to be the dissociative adsorption of water molecules to the SiC bonds of the topmost Si atom, namely the hydrolysis of the back bond, and the catalysis of Pt is considered to enhance the reaction. CARE with pure water is expected to represent a breakthrough method for surface processing of SiC, and will be widely applied in industrial processes such as planarization after high temperature processing in device fabrication.
Hydrogen Effects in ECR-Etching of 3C-SiC(100) Mesa Structures
Authors: Hiller Lars , Stauden Thomas , Kemper Ricarda M. , Lindner Jörg K.N. , As Donat J. , Pezoldt Jörg
Published: February 2014

An anisotropic etching process for mesa structures using fluorinated plasma with hydrogen addition was developed in an electon cyclotron resonance setup. The evolution of the mesa morphology was studied in dependence on the gas composition, the applied bias and the pressure. The achieved side wall slope approached 90° with a negligible trenching. The aspect ratios of the fabricated structure in the developed residue free ECR plasma etching process were between 5 and 20.
Development of Silicon Carbide Dry Etcher Using Chlorine Trifluoride Gas
Authors: Yajima Dairi , Habuka Hitoshi , Kato Tomohisa
Published: February 2014

A SiC dry etching reactor using chlorine trifluoride (ClF3) gas was designed and evaluated with the help of numerical calculations and experimental results. The etching rate was about 16 μm/min when the ClF3 gas concentration, the total flow rate and the SiC substrate temperature were 90%, 0.3 slm and 500 °C, respectively. The gas stream above the substrate surface was concluded to significantly affect the etching rate profile.
Investigation of Trenched and High Temperature Annealed 4H-SiC
Authors: Banzhaf Christian T. , Grieb Michael , Trautmann Achim , Bauer Anton J. , Frey Lothar
Published: February 2014

This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight enlargement of the trench width along with a considerable increase of the substrate surface roughness. In addition, X-ray photoelectron spectroscopy (XPS) depth profiles indicate an increased carbon atom concentration at the 4H-SiC surface after the high temperature PTA. The non-stoichiometric surface composition affects the quasi-static capacitance-voltage (QSCV) behavior of MOS structures using a deposited gate oxide (GOX). We assume that a sacrificial oxidation directly after the PTA could restore a stoichiometric 4H-SiC surface.