(Invited) Stress Simulations of Fins, Wires, and Nanosheets
Authors: Eneman Geert , Veloso Anabela , Favia Paola , Hikavyy Andriy Yakovitch , Porret Clement , Arimura Hiroaki , De Keersgieter An , Pourtois Geoffrey , Loo Roger , Spessot Alessio , Matagne Philippe , Ryckaert J. , Horiguchi Naoto 
Published: December 2020

As the scalability of FinFET architectures is stretched to its limits in the most advanced technologies, industry and research are looking to the next candidates to scale the gate lengths a few nanometers closer to 10nm. Nanosheets and nanowires are such candidates, and specifically the introduction of the former is considered by a major industry player [1]. The inflection point of the transition from fins to sheets and wires depends on multiple trade-offs, of which channel stress is one: stress in the new architectures should preferably match the one in fins to become a viable contender to FinFET technologies. The introduction of stress in fins, wires and sheets, including devices with alternative channel materials, has been studied by several excellent publications from others [2-5], as well as by us [6-8].

This work will focus on TCAD simulations of channel stress in fins, wires and sheets with typical 5nm-node dimensions. We focus on stress generation resulting from the following interacting stressors: 1. Lattice mismatch stress resulting from a different Ge composition between the substrate and the channel 2. lattice mismatch stress between the source/drain regions and the substrate (and channel) 3. for the case of wires and sheets, lattice mismatch stress from the sacrificial layers that are grown in between the wires and sheets, and that are removed in the replacement gate module. All simulations are performed with Sentaurus Process [9].

For Si0.5Ge0.5 nanowires on a Si0.75Ge0.25 virtual substrate (Fig. 1) with Si0.5Ge0.5 epitaxially grown source/drains, the longitudinal channel stress at the end of processing in the top, middle and bottom wires is plotted in Fig. 2, and compared to the stress in corresponding fin structures. The following observations can be made: 1. Compressive (i.e. negative) channel stress is found, making this configuration suitable for p-type devices. 2. stresses are strongly dependent on the original fin or wire length, as stress relaxation occurs during fin/ wire cut. 3. there is significant difference between the stress in the top, middle and bottom wire, especially for short wire lengths. 4. (absolute) stresses in wires are higher than in fins, thanks to the presence of the sacrificial layers that limit stress relaxation in wires during wire cut [6].

Scaling the devices from 8nm-node to 3nm-node dimensions decreases the absolute stress in fins and wires, Fig. 3. However, significant stress values are predicted down to the smallest nodes, especially for nanowires (> 1GPa). For all nodes, the stress in wires outperforms the one in fins by 50-70%.

Fig. 4 shows the channel stress in nanowires and sheets versus device width. Moving from wires (i.e. a device width of 7nm) to larger widths, corresponding to sheets, tends to decrease the volume ratio of the source/drain stressor to the channel. As a consequence, lower absolute stresses are predicted for wider sheets, even when the wire/sheet pitch is scaled along with the device width. In general the highest stresses are found when the channels are thin, provided the mechanical stability of the channel is not compromised, which is something that has not been assessed in this work.

Finally, the goal of this work is to study one particular concern for source/drain epitaxy in nanowires and nanosheets: in the presence of internal spacers, the source/drain epi starts from the nanowires as well as from the substrate, and may not join perfectly, leading to stress loss (Fig. 5). This work will perform a worst-case estimate of the stress loss in the presence of various defective interfaces. The TCAD results will be compared with experimentally measured strain using nano-beam diffraction [7-8].

References

[1] G. Bae et al., IEDM Tech. Dig., 656 (2018).

[2] S. Barraud et al, IEDM Tech. Dig., 464 (2016).

[3] G. Tsutsui et al., VLSI Tech. Dig., 122 (2017).

[4] S. Reboh et al., IEDM Tech. Dig., 246 (2019).

[5] G. Yeap et al., IEDM Tech. Dig., 879 (2019).

[6] H. Arimura., IEDM Tech. Dig., 496 (2018).

[7] P. Favia et al., submitted to EMC 2020.

[8] A. Veloso et al., to be submitted to SSDM 2020.

[9] Sentaurus Process Reference Manual, Synopsys, M-2016.12 (2016).

Figure 1