bluuebunny/crossref_metadata_2025 huggingface dataset:
MOP-DDPG: Multiple Observation Points Oriented Deterministic Diagnostic Pattern Generation for Compound Faults
Authors: Wang Fei , Hu Yu , Ye Jing , Huang Yu , Li Xiaowei , Yang Haigang
Published: March 2010

Scan-based design is a widely used Design-for-Testability (DFT) technique to improve test and diagnosis quality. As scan chains and relative control logic can take up as much as 40% of transistors in logic part, defects are prone to impact both scan chains and system logic simultaneously. When these defects manifested as scan chain faults and system logic faults, we call such faults as compound faults. In this paper, we present a Multiple Observation Points Oriented Deterministic Diagnostic Pattern Generation (MOP-DDPG) technique that targets compound faults. We further propose a fault suspect analysis technique to find root cause of the faults either on scan chains or on system logic or both. Experimental results show that on average scale, MOP-DDPG can accurately locate a dozen of compound faults.
A Case Study of Hierarchical Diagnosis for Core-Based SoC
Authors: Wang Eric , Huang Yu , Cheng Wu-Tung , Yang Wu , Fu James
Published: March 2010

In this paper, a silicon debug case study was given in the context of a hierarchical diagnosis flow for core-based SoC. We discuss (1) how to design a simple core wrapper that supports at-speed test, (2) how to map the failures collected from the chip level to core level, and (3) how to perform failure analysis and silicon debug under the guidance of diagnosis results.
CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing
Authors: Wen Xiaoqing , Enokimoto K. , Miyase K. , Kajihara S. , Aso M. , Furukawa H.
Published: March 2010

At-speed scan testing is essential in guaranteeing LSI chip quality in the deep-submicron era; however, chip/package damage, yield loss, and reliability degradation may occur in at-speed scan testing due to excessive test power, which can be several times higher than functional power. This problem is especially severe for low-power devices. In this paper, the background of the test power problem is reviewed, and the characteristics of two different types of test power (shift and capture) are highlighted. Then, a general strategy for test power reduction is described. After that, information on a novel CAT (critical-area-targeted) technique for tackling the more challenging problem of capture power reduction is provided. This unique and sophisticated technique can effectively reduces launch switching activity in a pinpoint manner by targeting at areas around long sensitized paths (called critical areas). Evaluation results on industrial circuits demonstrate the need for such CAT techniques.
Effectiveness Indices for Statistical Process Control Chart Performance
Authors: Yang Siyuan F. , Chien Wei-Ting K.
Published: March 2010

The current standard practice in manufacturing industries and SPC textbooks only specify how to set up control limits and how to choose different run rules (such as the WECO rules) for control charts for process quality characteristic under monitoring. The cost modeling has also been developed in literature to determine the control chart settings for economic design; however, it has very limited applications in semiconductor manufacturing because the complexity of many process steps and multiple process equipments at each step made it nearly impossible to do cost modeling. For process characteristics with wide conformance specification, control limits width wider than 3σ has been widely in practical applications and a simple WECO rule of one point beyond control limits is popularly used. However, no index is designed to evaluate the effectiveness of control chart settings (the width of control limits). We define alarm types and the corresponding rates to distinguish alarms without root causes found during diagnostics from statistical false alarms. A new alarm type of non-OOC excursions is also defined and introduced. We use them to form indices and inequalities to evaluate whether the control limits are set too wide. When inexperienced engineers are unable to perform effective troubleshooting and root cause diagnostics, some true alarms are treated as false ones. These new indices and inequalities have made it possible to evaluate whether engineers need to improve their engineering troubleshooting skills. An overall index is also designed to judge the relative performance with different control limit settings.
Relating Extrinsic Breakdown Statistics to the Initial Current Leakage Distribution in Gate Oxides
Authors: Suñé Jordi , Tous Santi , Wu Ernest Y.
Published: March 2010

By fitting the statistical distribution of leakage current in as-grown gate oxides, we extract information about the density and severity of defects that cause extrinsic breakdown. With this information and the well-established percolation model of oxide breakdown we model the complete oxide failure distribution including intrinsic and extrinsic breakdowns. These results might have strong impact on product reliability assessment procedures since measuring the initial current leakage distribution at low voltage is a relatively cheap non-destructive test which can limit the use of extremely costly product reliability stress experiments.
Ag Migration Induced Reliability Concern on Micro-Electro-Mechanical Structure
Authors: Zheng Pengfei , Dong Weichun , Chang Venson , Liu Yunhai , Li Gang , Ji Chunkui , Li Ming
Published: March 2010

A structure with 70μm space between two Ag bulks was designed to evaluate the reliability performance of micro-electro-mechanical structure. THB (Temperature Humidity with Bias), 85°/85%RH (Relative Humidity) with 4.0V DC bias, was used as the environmental test conditions. SEM (Scanning Electron Microscope) and EDX (Energy Dispersive X-ray Detector) analysis showed that Ag migration over the isolating space induced about hundreds of times of the leakage current increase between the two Ag bulks after THB 200-hr and 500-hr stress. Chlorine element was also found in the migrated particles combined with Ag. It is inferred that the electrochemical reaction between Ag and H2O with the presence of Cl anion contributed to the Ag migration. This case can also be taken as a reference for failure analysis engineers who encounter the similar failure phenomena.
A New BSIM3v3 SPICE Model for Reliability of Hot Carrier Injection Effect in MOSFET
Authors: Yu Yueyun Y. , Li Xi , Ren Zheng , Shi Ling Y. , Deng ZhangPeng , Hu Shaojian , Tang Yi , Zhou Wei
Published: March 2010

This paper reports a new BSIM3v3 SPICE reliability model for describing the reliability of hot carrier injection (HCI) in MOSFET, which can be widely used in traditional process MOSFET. In this work, thousands of BSIM3v3 model parameters are analyzed, seven parameters primarily affected by HCI are extracted and optimized in original BSIM3v3 source code.The I-V simulation results after parameter extraction fits the measured results very well, so an accurate new model of MOSFETs reliability model is achieved. Using the new BSIM3v3 SPICE reliability model, the idvd curves at the stress time from 10 to 50000s of the nMOSFET with 10µm gate length and 0.5µm gate width can be achieved. So the device characters variation with time can be monitored. Besides, the typical Idsat, Vth, Idlin and Gmax degradation as a function of stress time are also plotted and the lifetime of MOSFETs can be evaluated from these functions.
UVision Solution for High Detection Sensitivity at the Stitches
Authors: Xiang Yin , Luo Xiaojun , Li Wensheng
Published: March 2010

The sensitivity on stitch areas is always a problem for defect inspection. As the design rule shrinks, small defects in any dense area are becoming critical including in the stitches. Therefore to improve the sensitivity on stitch areas is now become a must for the new generation device. Applied UVision Brightfield inspection system provides the capability to combine different cells in one scan. This feature makes it possible to define the repetitive stitches as cell and scan with Cell-to-Cell mode. Two different approaches are discussed in this paper. (1) Small stitches combined with memory Cell and scanned with Cell-to-Cell as a whole; (2) Large stitches defined as new standalone Cell and scanned with Cell-to-Cell. The result shows that with the application of the Cell-to-Cell to the stitch areas, the sensitivity was significantly improved, and the DOI capture rate could be increased by as high as 10 times.
Challenges of Smart System Integration
Authors: Gessner Thomas , Vogel M. , Hiller K. , Otto T. , Bertz A. , Billep D.
Published: March 2010

As a result of the growing complexity and miniaturization of innovative products systems integration is becoming more and more important for scientific and technical development. The micro and nano system technologies as well as electronics are playing a key role in today's product development and industrial progress. They enable the integration of mechanical, electrical, optical, chemical, biological and other functions into a very small space with dimensions ranging from sub micrometers up to some millimeters. This paper presents three examples of MEMS sensors developed at Fraunhofer ENAS and Chemnitz University of Technology and the approaches for their integration into smart systems. The first one is an active radio frequency identification label for the monitoring of shock, inclination and temperature during transportation processes. A MEMS spectrometer and gyroscopes will be demonstrated. Special emphasis is given to MEMS /nanointegration.
Optimization of Film Uniformity by Electrochemical Copper Deposition Chamber Design
Authors: Wang Xi , He Chuan , Ma Yue
Published: March 2010

The impact of chamber design parameters on the non-uniformity of Cu film deposited by electrochemical method were investigated quantitatively by simulating the film growth process. These parameters include chamber geometry, electrolyte flow path, electrode configuration, and electrical field division and isolation. Further studies were conducted to optimize basic process parameters such as deposition current and current distributions on electrodes.
Method to Reduce Crystal Defects in AlCu Bond Pad
Authors: Luo Victor , Ding John , Zhan Willim , Peng Libbert , Wang Andrew , Liu Bing , Song Yuxin , Yin David D.
Published: March 2010

AlCu bond pad crystal defect is observed after wafer processing and before die sawing. It affects wire bonding or bump performance resulting in lower bond pull and ball shear force, even adhesion failure. There are many factors contributing to the crystal defect, such as: polymer removal status, storage condition, humidity and fluorine concentration in the environment etc. Up to date, the impact of humidity and fluorine concentration to crystal defect has been broadly studied, but the polymer remover's effect is somewhat unknown. In this paper, two different chemistry based polymer removers are studied to correlate to crystal defect behavior. After processed by the polymer remover, AlCu bond pad wafers are subject to different environment conditions including wet box (44% and 63% humidity separately). Subsequently, each wet box is filled with fluorine at the concentration of 524ug/pod. The crystal defect growth is examined as a function of time using optical methodology. The results reveal that the polymer chemistry is also critical to crystal defect growth as well as the impact on queue time and storage conditions. An optimized fluoride containing polymer remover can substantially lower the crystal defect risk leading to a wider process windows.
WCVD Seam Hole Improvement to Prevent BEOL Copper Diffusion
Authors: Li Xia , Ji Justin , Ou-Yang Dong , Jiang Ronnie , Zhang Jiwei , Chiu Robin , Lin Paul-Chang , Xing Charles
Published: March 2010

With the feature size shrinking in IC manufacturing, copper is to be used in BEOL metallization to decrease RC delay and improve electro-migration for 0.13um technology node and below. Moreover, tungsten still remains as the material of choice for the contact. As reported in most papers, copper is easily to diffuse through the seam of tungsten plug. Many researches focus on the dielectrics or Ta/TaN barrier layer enhancement to prevent Cu diffusion. In our study, another copper diffusion mechanism, which tunnels through the contact Tungsten seam hole and induces product device failure, is proposed. WCVD process optimization for seam hole improvement is also studied to prevent copper diffusion.
Mechanism and Solution of Isb Failure on Deep Trench DRAM
Authors: Li Zhi-Chao , Mo Ting-Ting , Lin Yi-Hui , Sun Peng , Zhang Jiwei , Chiu Wen-Pin , Lin Paul-Chang , Xing Charles
Published: March 2010

Poly doped with phosphor and WSix are generally used as the gate-stack for deep trench DRAM product. These two films are critical ones that influence CP yield. In manufacturing, yield can gain much after solving Isb (I-standby) failure caused by gate WSix extrusion. Researches presented tungsten rich during WSix deposition or O2 leak during gate anneal process could lead to WSix extrusion (1), (2). Our study reveals that the concentration of phosphor, [P] in gate poly is another critical parameter to cause WSix extrusion after polycide pull-back process. In this paper, the mechanism of WSix extrusion is described and an optimized poly deposition process is proposed to solve Isb failure.
Achieving Fast Yield Improvement by Defect to Bit Failure Overlay Method
Authors: Chen Cinti , Zhao Joe W. , Qian Gang , Fan Jenny , Li Xiao-Yu
Published: March 2010

In this paper, we present a new proven methodology, which identifies the killer defects and marginal designs by overlaying the electrical failure signatures and addresses from wafer sort to the inline defect inspection results. Not only have this new approach helped identifying killer defects that are difficult to PFA, it also benefits inspection recipe tuning and finding the root causes of different defects. This approach has been successfully implemented in 40/45nm products, and shortened the yield learn cycle significantly.
HVM LPP EUV Source System Development Status
Authors: Lin Benjamin , Brandt David , Farrar Nigel
Published: March 2010

Laser produced plasma (LPP) EUV systems have been considered as a viable and scalable approach for the EUV scanners at sub-32nm and beyond nodes on the ITRS roadmap. High EUV power and reduction of chamber contaminations inside EUV vacuum chambers or to EUV scanner optics are two main concerns for the LPP EUV source system development. In this paper, a review of Cymer LPP EUV development progress will be provided along with productization status for LPP EUV sources with performance goals targeted to meet specific requirements from leading scanner manufacturers. The latest results on high EUV power generation, debris mitigation and clean transmission of EUV light through the intermediate focus will be described. Finally, a development roadmap to achieve high LPP EUV source power will be illustrated.
Simulation and Experimental Study on Multilayer Double-Patterning Processes
Authors: Guerrero Douglas J. , Sullivan Daniel M. , Zhu Zhimin , Mercado Ramil Marcelo L.
Published: March 2010

The imaging constraints imposed by the optics of current lithographic tools now require double-patterning (DP) processes. As lithography pushes past 32-nm resolution, the need to optimize material stacks, including resist, bottom anti-reflective coating (BARC), and substrate has never been greater for IC manufacturers. With thinner resists, DP, dual BARCs, and tri- and quad-layer schemes in the 193-nm immersion technology, the potential combinations are almost endless. Many approaches to DP have been devised, of which most have been designed to reduce the number of process steps. In this paper, we model several DP processes using our simulation software. Reflectivity control and resist profile optimization was maintained in the simulations using organic BARCs and spin-on multilayer stacks consisting of a silicon hardmask on top of a carbon underlayer. DP lithography results of these optimized tri- and quad-layer schemes are presented.
Bottom-Anti-Reflective Coatings (BARC) for LFLE Double Patterning Process
Authors: Sakamoto Rikimaru , Endo Takafumi , Ho Banghing , Kimura Shigeo , Ishida Tomohisa , Kato Masakazu , Fujitani Noriaki , Onishi Ryuji , Hiroi Yoshiomi , Maruyama Daisuke
Published: March 2010

Double patterning process with ArF immersion lithography has been developed as one of the most promising candidate for hp32 node and beyond. However complicated process flow and cost of ownership are the critical issue for this process. LELE (Litho-Etch-Litho-Etch) is the one of the standard process, but in order to reduce the process and cost, that LFLE(Litho-Freezing-Litho-Etch) and LLE (Litho-Litho-Etch) process have been investigated as the alternative process. In these processes, Organic Bottom-Anti-Reflective coating (BARC) is used two times with same film in both 1st Litho and 2nd Lithography process. In 2nd Lithography process, resist pattern will be printed at space area where exposed and developed in 1st lithography process. Therefore, organic BARC needs to have process stability in Photo and development step to keep good litho performance between 1st and 2nd lithography in LFLE / LLE process. This paper describes the process impact of 1st exposure and development for organic BARC, and the LFLE / LLE performance with optimized organic BARC will be discussed.
Lithographic Significance of Wafer Back Surface Nanotopography
Authors: Veeraraghavan Sathish , Sinha Jaydeep K.
Published: March 2010

Wafer topography plays a critical role in the performance of lithography at smaller nodes. The contribution of low to medium spatial frequency components of wafer topography to overlay error is currently a topic of interest within the lithography community, especially as double patterning techniques have reduced overlay error budgets by a factor of two. Nanotopography, comprised of the higher spatial frequency components of wafer topography can contribute to non-correctable errors (NCE) for the scanner. In this paper we use finite element analysis to investigate the transfer of back-surface nanotopography to the front surface as the wafer is chucked either on a pin chuck or a flat vacuum chuck. The results are found to be lithographically significant, suggesting that fabs may benefit from measuring back-surface nanotopography, and developing appropriate specs for incoming wafers.
Effective Poly Gate CDU Control by Applying DoseMapper to 65nm and Sub-65nm Technology Nodes
Authors: Tian Peter , Qin Lisa , Shu Andy , Gu Yiming
Published: March 2010

How effectively to control ACLV (across chip line variation) and AWLV (across wafer line variation) in 65nm and sub-65nm technology nodes becomes a very challenging task In this paper, our discussion will be focused on the most important part of CDU, which includes ACLV and AWLV. By using an ArF exposure tool, a DoseMapper application can successfully obtain the full wafer CDU of poly gate across wafer around 2.0nm (3σ, including ACLV and AWLV) in 65nm node. Moreover, with a state-of-the-art immersion ArF exposure tool the DoseMapper can even deliver the full wafer CDU around 1nm (3σ) in sub-65nm nodes. In addition, it has been proved that the DoseMapper application at post-etching is more effective than at post-litho stage because it also includes the systematic CD variation induced by etcher. However, the DoseMapper application at post-etch stage introduces a new challenge in litho CDU control. The CDU metric of 3σ or range is no longer meaningful at post-litho stage. A new methodology of CD control at post-litho will be presented in this paper.
High Productivity Combinatorial Analysis of Cu Post-CMP Cleans: Corrosion Protection and Queue Time
Authors: Barnes Jeff , Liu Jun , Medd Steve , Tran Cuong , Yin David D. , Zhang Peng
Published: March 2010

High Productivity Combinatorial (HPC) technology was used to evaluate post-CMP clean chemistries and their impact on copper surface corrosion protection and queue time performance. Cleaning formulations at low pH and high pH, both with and without functional additives, were used to produce a wide range of surface conditions typical in semiconductor processing. X-ray photoelectron spectroscopy (XPS) results show that low pH cleans remove most oxides, but that within 20 hrs copper oxide re-growth occurs in the form of Cu (I) and Cu (II) oxide species. Electrochemical analysis is a simpler and higher throughput method to study oxide growth over time. Good agreement existed between electrochemical and XPS techniques when both were used to study copper surfaces for 0 to 20 hours after clean. The electrochemical tests were continued after 48 hours of queue time to develop a better understanding of oxide growth trends, and showing continued oxidation of Cu surfaces treated with low pH cleans. For extremely long queue times, SEM analysis shows growth of visible copper oxide nodules on Cu lines and pads for low pH treated M1 test structures. Leakage of comb structures monitored as a function of queue time was inconsistent, indicating that standard leakage measurements at 1V for comb structures with 0.125 / 0.175 line/space dimensions are not sensitive to the copper surface instability of oxidation.
A Novel Post-CMP Electrochemical Cleaning Process Using the BDD Film Anode Combined with Special Chemical Agents
Authors: Gao Baohong , Zhu Yadong , Liu Yuling , Wang Shengli , Zhou Qiang , Liu Xiaoyan
Published: March 2010

This paper presents a novel post-CMP cleaning process using the boron-doped diamond (BDD) film electrode as anode in the electrochemical cleaning combined with non-ionic surfactant. With wide potential window and high oxygen evolution potential compared with other electrode materials, the BDD film electrode is able to electrochemically generate super-advanced oxidation free radicals, such as hydroxyl radicals, oxygen free radicals and so on, the sub-product of which are ozone and hydrogen peroxide. And the BDD film electrode electrochemically oxidation is an advanced oxidation technology. Using the surfactant to remove particles contaminants in the first step, the novel post-CMP cleaning process can effectively remove organic as well as the adsorbed surfactant on the surface. The experiments of cleaning Silicon wafer in point are introduced in this paper, and the results indicated that the effective cleaning process can meet the continuous development of microelectronic industry cleaning needs.
Study on Surface State Control Technique of InSb Material Ultraprecision Machining
Authors: Niu Xinhuan , Tan Baimei , Xu Wenzhong , Zhao Haitao , Liu Yuling
Published: March 2010

Indium antimonide is one of the important materials which can be used to make semiconductor devices such as infrared detection device. Due to the low hardness and great brittleness, the surface scratching always appears and surface roughness is hard to lower during surface preparation. So it should be increasing the InSb surface quality during ultraprecision machining. In this paper the InSb surface adsorption-control technology was introduced. Through controlling surface roughness during chemical mechanical polishing(CMP) and using preferential adsorption during cleaning, the adsorptions of InSb surface were controlled. Through experiments, the CMP optimal process parameters under the alkaline conditions were gotten. Under such conditions, the preferable surface statewere realized. According to the preferential adsorption model, through using FA/O non-ionic surfactant the polished wafer surface can be kept in physical adsorption and easy cleaning state, so the wafer surface adsorption can be controlled effectively and the clean surface was obtained.
On the Process and Material Sensitivities for High-k Based Dielectrics
Authors: Van Elshocht Sven , Adelmann Christoph , Popovici Mihaela , Swerts Johan , Delabie Annelies , Nyns Laura , Shi Xiaoping , Tielens Hilde , Pourtois Geoffrey , Menou Nicolas , Breuil Laurent , Pierreux Dieter , Maes Jan-Willem , Hardy An , Van Bael Marlies K. , Jurczak Malgorzata , Kittl Jorge A.
Published: March 2010

Multi-element and multilayer high-k dielectric stacks are being explored for future generation logic and memory devices. The increased material complexity can have a significant impact on the thermal stability and crystallization behavior of the stacks directly or indirectly affecting their material and electrical properties. We have studied the effect of composition and layer thickness for hafnium and rare earth based (lanthanum and dysprosium) systems on crystallization and intermixing (silicate formation). Our results show that for multilayer dielectric stacks, the thermal stability and intermixing is function of the composition and thickness of the individual layers.
Influence of the Top Chamber Window Temperature on the STI Etch Process
Authors: Shamiryan Denis , Danilkin Evgeny , Tinck Stefan , Klick Michael , Milenin Alexey , Baklanov Mikhail M. , Boullart Werner
Published: March 2010

During shallow trench isolation etching it was found that etch stop appears at the center of a 300 mm wafer as the temperature of the top quartz window of the etch chamber exceeds 85°C. We attributed the etch stop to redeposition of some low-volatile SiOxCly etch products. At low quartz window temperature part of the products are deposited on it, but as the window temperature rises well above the wafer temperature (which is constant at 60°C), the products primarily are deposited on the wafer causing the etch stop.
Impact of Etching Chemistry and Sidewall Profile on Contact CD and Open performance in Advanced Logic Contact Etch
Authors: Wang Xin-Peng , Zhang Hai-Yang , Chang Shih-Mou , Lee Kwok-Fung , Sun Wu , Huang Yi
Published: March 2010

Contact etch is one of the most key processes in advanced sub-micron logic technology. It has been proven to play an important role in yield enhancement. As the advanced logic semiconductor technology moves to 65nm node and beyond, contact etch has attracted more attention for its notorious issues: A) The desirable top-view achievement with much higher aspect ratio of contact hole and insufficient amount of photo-resist (PR). B) The trade-off between polymer-rich etch process for great capability of critical dimension (CD) shrink and polymer-lean etch process for the enlargement of marginal contact open window. In this paper, we focus on these challenges. Results demonstrate that A) CHF3 delivers the best top-view of contact hole. B) Lower ratio of source power to bias power gives more vertical profile of contact hole. C) The gas ratio of O2 is an effective knob to control contact open window.
The Mechanism of Over-Etch in Poly-Gate Etching
Authors: Zhang Qingzhao , Xing Tao , Yang Weifeng , Wang Baoquan , Li Bing , Yang Xia
Published: March 2010

The over-etch mechanism in poly-gate etching is investigated. The relationships between the final poly-gate profile and the over-etch process parameters are presented. The oxygen flow and temperature of electrostatic chuck (ESC) both sensitively contribute to the notch of the poly-gate profile. Two corresponding process models are suggested.
300mm Cu BEOL Top Trench Etch Process Development for 65nm Logic Technology
Authors: Ren Wei , Song Jeff , Liu Andrew , Zhao Ganming , Huang Ying , Hsieh Peter , Gu Binxi , Wang Judy
Published: March 2010

The challenges for the top trench etch of small size technology node logic products, include how to get minimal etch depth loading and superior CD (critical dimension) uniformity, free faceting or fencing and free striations. Enabler dielectric etch chamber is designed to provide excellent etch performance and productivity for 65nm technology and beyond. Enabler chamber is equipped with an NSTU (neutral species tuning unit), a CSTU (charged species tuning unit), and 2 MHz and 13.56MHz dual frequency bias power, as well as 162MHz high frequency source power, which is used to re-shape the plasma density distribution. In this work, a 5-step in-situ process (including two ashing steps) was developed using an Enabler chamber. Overall, mass production demonstrated excellent inline and electrical performance with high reliability and MTBC of as high as 460 RF hours was achieved.
Use of Neural Network to Model the Refractive Property of PECVD Silicon Nitride Films used to Prevent Water Permeability of Piezoresistive Pressure Sensor
Authors: Thongvigitmanee Thongchai , Srihapat Arckom , Khompatraporn Charoenchai , Jiraprayuklert Adsada , Titiroongruang Wisut
Published: March 2010

A plasma-enhanced chemical vapor deposition (PECVD) silicon nitride is used for the passivation layer of ICs and sensors. For example, in blood pressure sensor, the piezoresistive pressure sensor is immerged into liquid and the silicon nitride film is expected to prevent water permeability into it. In this paper, we first applied a design of experiment (DOE) and neural network to discover the relationship between input parameters and refractive indexes of PECVD silicon nitride films. Later we introduced the metrology developed to quantify the water permeability into the film based on the resistance test structure measurement and the break down measurement. These two performance tests could further use to identify the optimal silicon nitride deposition recipe which could prevent water permeability of piezoresistive pressure sensor.
Interconnect Technologies and Advanced Packaging for High Performance Computing
Authors: Shi Jing , Sze Theresa , Song Deqiang , Huang Dawei , Cunningham John E.
Published: March 2010

The quest for high speed data processing continues to drive the industry to increase L1 and L2 on -chip caches and near-processor memories in large-scale computer systems. However, the increased latency and process yields limit chip area for L1 and L2 caches. Therefore alternative solutions beyond on-chip memory are being aggressively pursued. In this paper a high-level computer memory hierarchy and the corresponding interconnect technologies on each level of memory structures are summarized. We introduce a new MCM package technology based on proximity communication (PxC-MCM package) and discuss its merits compared to conventional MCM. Challenges and recent research results on PxC-MCM solution are presented as well.
Studies on Cure Kinetics of a Novel Imidazole Derivative Curing Agent for Epoxy Resin
Authors: Liu Li , Li Ming , Gao Ting
Published: March 2010

We used phenyl glycidyl ether (PGE) to modify 2-methylimidazole (2MI) and obtained a novel imidazole derivative named as 2MI-g-PGE. FTIR spectroscopy and 1H NMR spectroscopy have been used to characterize the chemical structure of 2MI-g-PGE. The curing kinetic of diglycidyl ether of bisphenol A (DGEBA) with 2MI-g-PGE as curing agent was studied by dynamic differential scanning calorimetry (DSC) technique. Dynamic DSC scans indicated that 2MI-g-PGE was an effective curing agent of epoxy resin. Both Kissinger method and Ozawa method were adopted to calculate the activation energy (Ea) of DGEBA/2MI-g-PGE system and the values were 74.23kJ/mol and 76.58kJ/mol respectively. By using Crane and Kissinger equations, the characteristic parameters of the curing kinetics including the order of reaction (n) and the pre-exponential factor (A) of DGEBA/2MI-g-PGE system were calculated to be 0.92 and 2.38×1012s-1 respectively.
Power SO-8: An Interconnect Case Study
Authors: Wong Garrett
Published: March 2010

With the rising cost of Au base material, many power semiconductor device manufacturers are evaluating alternative interconnect technologies to reduce manufacturing costs. In addition, shrinking package sizes, increasing electrical performance requirements and environment-friendly packaging objectives are additional considerations when choosing an alternative interconnect technology. Presently, three primary technologies compete to become the dominant Au wire replacement in the small outline, discrete power semiconductor market. Each alternative, Cu Wire, Cu Clip, and Al Ribbon, attempts to strike the best balance of electrical performance, manufacturing cost, and production yield. The small outline, discrete power semiconductor market can be broadly described as the sub-category of discrete semiconductors presently utilizing multiple 2-mil (or larger) diameter Au ball bonds as the interconnect between the die and the package leads. This paper explores observed benefits of these competing technologies in two example Power SO-8 packages that are presently ball-bonded with 2-mil Au Wire. In this comparison, we will examine the electrical performance (Rds(on) reduction), reported productivity (UPH), production yields, manufacturing cost-per-part, product-line flexibility and lead-free compliancy for each interconnect method. From this case study, similar extrapolations can be made for applying these interconnect technologies to similar packages, such as Small Outline Non-leaded (SON or PDFN), Power QFNs (PQFN), Driver MOSFETs (DrMOS), and Bi-Polar Transistor packages.
PBGA Cost Reduction by Reducing Plated Au Thickness of Substrate Pads
Authors: Wang Robert Q.
Published: March 2010

In the past decade, we have witnessed the significant increase of gold price. Coupled with continuous price decrease of electronic products, the reduction of gold consumption has been explored in every possible area. This paper is related to reducing gold consumption on wire bonding pads of low density interconnect substrates. A layer of gold is plated on the substrate pads with typical minimum thickness of 0.5um to facilitate wire bonding process using gold wire. The objective of this study was to reduce gold thickness on the substrate pad to 0.3um minimum without compromising wire bond integrity. DOE considering different substrate sources wire bonded by different assembly suppliers were conducted. Wire bonding process optimization was followed by package level reliability stress testing, heat aging, and board level solder joint reliability testing was carried out for validation. The results showed plated gold thickness on the wire bond substrate pads can be reduced to a minimum of 0.3um without compromising package reliability performance. With the success of thinner gold on the substrate pads, we can use the same natural resources - gold to build more units, 'better for environment, if we consume less'
Bond Ball Optimization on UCP Die for Chip Card Module
Authors: Shen Juan , Shan KangPing
Published: March 2010

Wire bonding damage on die shield was detected on UCP (inline pads) die, and the root cause was the bonded ball touch the die shield due to big ball size which already out of bond pad area. In order to resolve this problem, a feasibility study on free air ball (FAB) size & 1st bond ball size with 24um diameter of Au wire and indentified capillary had been carried out at wire bonder Esec 3006 and Esec 3088. Therefore two DOEs were performed, first was the FAB size as response of EFO's current and time as factors.Second was bond force and power (ultrasonic) as factors while 1stbond's ball shear test, ball height, ball size (diameter), percentageof intermetallic (IMC) and cratering were responses. Nevertheless2nd bond performance was also taken into assessment namely nonstick on lead and lifted stitch. Relibility tests temperature cycling and temperature humidity test were performed to prove the robustness of this smaller ball diameter. Overall, experimental results revealed that the die shield damage could be resolved & prevented by smaller bond ball
DDR2/DDR3 Interface Signal Integrity Analysis Based on IBM Generic Package Model
Authors: Yin Wen , Pang Ze Gui , Han Hai Tao
Published: March 2010

The data rate of Double Data Rate (DDR) memory interface has become higher, Signal Integrity (SI) analysis is very important for current DDR system design to meet performance requirement. The chip/package types, board level interconnection, driver/receiver modes and power supply network are key factors for the design specification, analysis based on design applications should be performed to evaluate delay, reflection, jitter, simultaneous switching power noise, timing budget for the DDR system. This paper presents the method of performing DDR2/DDR3 interface SI simulation by using IBM Generic Package Model (GPM).
Chip Card Globe Top Module Robustness Study
Authors: Tan Chip King , Zhang YuJun , Juan Shen , Haimerl Alfred , Gisela Wurdack
Published: March 2010

Usage of security smart card is growing rapidly in recent electronic world. Unquestionably in the next decade, each individual would need at least one smart card to store and secure his or her confidential information for daily application. Therefore the robustness of chip card module plays the most important role in the smart card application. This paper discusses about the robustness of Globe Top (GT) Module through a complete qualification flow which includes module level and card level reliability tests. The objective of this qualification is to prove the quality of current GT module manufactured in house for market application. Basically in this study, two modules type namely Memory M3.2-SLE55XX and Controller M5.1-SLE66XX had been selected. These two modules coupled with two types of glass epoxy (FR4) tape were evaluated. Internal assembly level reliability data including die shear, wire ball size, wire ball height, wire pull, ball shear, loop height, wire sweep, encapsulation dam & fill dimension and thickness were collected and analyzed. Meanwhile reliability tests for modules level and card level which include thermal, climatic, chemical and mechanical resistance were tested. Reliability results revealed that these two packages passed the entire qualification requirements and proven to be robust for smart card application.
Recent Advances in Thermal Processing for c-Si Solar Cell Manufacturing
Authors: Bao Tianming , Guo Yan , Li Lihua , Zheng Xu , Bottari Frank
Published: March 2010

Thermal processing is an integral part of crystalline silicon (c-Si) solar cell manufacturing technology. It is often applied to achieve diffusion, annealing, oxidation, deposition, or reaction process steps in a production environment. This paper reports recent developments in thermal process technology that enable the industry to improve cell efficiency and manufacturing productivity for the standard c-Si cell technology. Especially, continuous inline thermal equipment is adopted in many critical c-Si cell fabrication stages, from emitter formation by dopant diffusion, contact formation by rapid thermal sintering of metallic pastes, to hydrogen annealing to rescue low-efficiency cells.
Polysilicon Materials FBR Technology for Solar and Semiconductor Silicon
Authors: Fisher Graham R. , Kulkarni Milind
Published: March 2010

The chaotic nature of fluid flow within a fluidized bed reactor (FBR), the high surface area of the product which requires special handling to prevent contamination, the size of the reactors and the construction materials present significant engineering challenges, but, once overcome the benefits of the FBR polysilicon production are significant. FBR technology can used with either silane or TCS feed. In this paper, the reaction paths for silane conversion are discussed. Sophisticated predictive modeling and simulation capabilities allow optimization of both reactor design and operating conditions to maximize productivity and reduce reactor downtime. These attributes enable production of high purity polysilicon for both the solar and the semiconductor industries.
Modeling the Early Stages of Oxygen Agglomeration
Authors: Kissinger G. Z. , Dabrowski J. , Kot D. , Akhmetov V. , Sattler A. , Von Ammon W.
Published: March 2010

The results of ab initio calculations and rate equation modeling of the early stages of oxide precipitation are compared with the results of highly sensitive FTIR spectrometry of oxygen and vacancy oxygen containing complexes in silicon after RTA treatment. The ab initio calculations have shown that the binding energy of interstitial oxygen in VOn is higher than in On for n {less than or equal to} 6. For higher n, the energy gain is comparable. The point defect species O1, O2, O3, and VO4 were detected by highly sensitive FTIR in high oxygen Czochralski silicon wafers after RTA at 1250{degree sign}C. The concentrations obtained from the ab initio modeling approach for I, V, On with n = (1-4) and VOn with n = (1-8)without fitting parameters are in good agreement with the experimental data for O1, O2, O3, and VO4 as determined by highly sensitive FTIR.
Oxygen Precipitate Nucleation in Heavily Antimony-Doped Czochralski Silicon
Authors: Zhu Weijiang , Ma Xiangyang , Chen Jiahe , Zeng Yuheng , Yang Deren
Published: March 2010

Oxygen precipitate nucleation behaviors have been comparatively investigated in the heavily antimony (Sb)-doped and lightly phosphorus (P)-doped Czochralski silicon (CZ-Si) wafers subjected to the high temperature anneal at 1000 oC for 16 h following the nucleation anneal at 450, 650 or 750 oC for up to 64 h. It is found that in the heavily Sb-doped CZ-Si the oxygen precipitate nucleation at 450 or 750 oC is always suppressed, while that at 650 oC is hardly suppressed in the case of sufficient length of annealing. It is believed that oxygen precipitate nucleation based on the Sb-V complexes occurs at 650 oC, whereas, this is not the case at 450 or 750 oC. Therefore, oxygen precipitate nucleation at 650 oC is enhanced in the heavily Sb-doped CZ-Si. Moreover, it can be comparable to that in the lightly P-doped CZ-Si as the annealing time is long enough.
Development and Application of a Structured/Unstructured Combined Mesh Scheme for Global Modeling of a Directional Solidification Process of Silicon
Authors: Li Zaoyang , Liu Lijun , Kakimoto Koichi
Published: March 2010

In order to improve the accuracy and efficiency of global modeling of a directional solidification process for solar silicon, we developed a structured/unstructured combined mesh scheme. The multi-block structured mesh was used to discretize those sub-domains with regular boundaries. The unstructured mesh was used to discretize those sub-domains with highly irregular boundaries. Then it was applied in the global modeling of heat transfer for a directional solidification process to investigate the effect of argon flow rate on heat transfer and impurities transport (oxygen as an example) in the furnace. It was found that the argon flow has little effect on the global heat transfer compared with thermal radiation, while its effect on impurities transport is remarkable. The amount of oxygen carried away by the argon flow at the melt surface is closely correlated with the argon flow rate.
Wet Etching Technology for Semiconductor and Solar Silicon Manufacturing: Part 1 - Fundamentals
Authors: Erk Henry F.
Published: March 2010

Wet etching is an important step in the manufacturing of semiconductor and solar wafers and for the production of MEMS devices. While it has been replaced by the more precise dry etching technology in advanced semiconductor device fabrication, it still plays an important role in the manufacture of the silicon substrate itself. It is also used for providing stress relief and surface texturing of solar wafers in high volume. The fundamentals of wet etching silicon for semiconductor and solar applications will be reviewed. Different classes of etchants: isotropic and anisotropic: acid and alkaline will be summarized. Key features and attributes for these different etchants will be presented to give the rationale for the use of a particular etchant for a specific application.
An Overview of Current Research on Simultaneous Double Side Grinding of Silicon Wafers
Authors: Lin Bin , Li Zhichao , Sun Wangping , Zhang Xiaohong
Published: March 2010

Simultaneous double side grinding (SDSG) is one of the state-of-art processes to flatten silicon wafers. This paper presents an overview of current research on SDSG of silicon wafers, which includes process applications, process modeling, and possible topics for future research.
The Application of Reactive Ion Etching (RIE) in Texturing of Multicrystalline Silicon Wafers for Solar Cells
Authors: Hu Liqiong , Zhao Lei , Tan Zongliang
Published: March 2010

Anti-reflection effect of three different surfaces including blank, wet acidic etched and RIE etched are compared on the basis of reflectance measurements. RIE has been to be found as the most effective method to reduce reflection of multicrystalline silicon surface, and as a result, can afford high efficiency of solar cells. We also optimized the RIE parameters. For SF6/O2 flow ratio of 2:1, crowded and dense crater-like structures on silicon surface were observed. Reflectance measurement results show that such a figure exhibits good anti-reflectance behavior. The lowest reflectance we got has been reached about 15.7%. Further increase SF6/O2 flow ratio, the reflectance increased instead of decreased. That means SF6/O2 flow ratio of 2:1 is the most appropriate flow ratio. Another important parameter is etching time. We maintained plasma conditions as earlier and keep SF6/O2 flow ratio of 2:1, then varied the etching time. At etching time of 15min, we got a perfect reflecting result on the surface of multicrystalline silicon.
An Extraction Method of Solar Cell Parameters with Improved Particle Swarm Optimization
Authors: Ye Meiying , Zeng Siqin , Xu Yousheng
Published: March 2010

This paper presents an approach for determining the solar cell model parameters from current-voltage (I-V) characteristics using improved particle swarm optimization (IPSO). The performance of the proposed approach was compared with the popular genetic algorithm (GA) in terms of the objective function values. The validity of the approach has been confirmed with a set of experimental I-V data. It was demonstrated that the experimental I-V data and the I-V curve processed by the IPSO approach were very close. A low objective function value can be obtained by the IPSO approach. So the IPSO outperforms the GA in solving the parameter extraction problem of solar cell model.
Performance of Silicon Ballistic Nanowire MOSFET with Diverse Orientations and Diameters
Authors: Abudukelimu Abudureheman , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori Takeo , Iwai Hiroshi
Published: March 2010

To investigate the performance of silicon ballistic nanowire MOSFET with diverse orientations and diameters, the subband structure of silicon nanowire has been calculated by using the tight binding simulator, and observed the changing of minimum energy in conduction and valence subband and effective mass of electron and hole. This paper also present a compact model, which is used in numerical evaluation of the current vs. voltage characteristics of ballistic devices. Finally, the drain saturation current of n- and p-channel device with different orientations and diameters is shown.
Electrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate Dielectric
Authors: Matano Katsuya , Funamizu Kiyohisa , Kouda Miyuki , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori Takeo , Iwai Hiroshi
Published: March 2010

Metal-oxide-semiconductor (MOS) capacitors with rare earth (La, Ce, Pr and Tm) oxides/silicates were fabricated to investigate the effective fixed charges density (Qfix) in the gate dielectrics from the slope of EOT-Vfb plots. In the small EOT region, a diffusion of gate metal atoms caused to increase fixed charge at the interface between RE-oxide and RE-silicate. TmOx/ Tm-silicate capacitors exhibit small Qfix of -6.5 ×1012 cm-2 in the small EOT region.