(Invited) Silicene: Silicon at the Two Dimensional Limit and Its Applications to Nanoelectronics
Authors: Molle Alessandro , Grazianetti Carlo , Cinquanta Eugenio 
Published: February 2020

The evolution of semiconductor nanoelectronics demands for a progressive miniaturization of the device feature size. Downscaling the silicon channel down to the ultra-thin film regime is a current trend in the semiconductor technology roadmap for digital devices such as ultra-thin body silicon-on-insulator field (UTB-SOI) or Fin field effect transistors. Future technology nodes are to require a turning point in the choice of alternative semiconductors replacing silicon. One approach is to make use of mobility boosters such as germanium or III-V’s in order to overcome the physical limits of silicon in the CMOS technology. However, new emerging materials are yet to come which imply a reduced dimensionality of the silicon channels (see the Figure below for a silicon roadmap).[1] This route inspired the concept of silicene as a silicon at the extreme two-dimensional (2D) limit. Silicene can be thought of as a structural analogue of graphene as well as a graphene follower in the periodic table. Silicene has recently attracted a tremendous attraction for its potential to bring the current silicon technology down to an ultimate thickness limit. Apart from the technology drivers, the existence of a silicene monolayer paves the way to the exploration of new exotic physical effecs such as the quantum spin Hall effect in an elementary crystal and to a new class of 2D materials, the so-called Xenes (X denoting other group IV semiconductors such as Ge and Sn). Despite the natural tendency of silicon to hybridize sp3 instead of sp2as carbon in graphene, the concept of silicene was previously proposed in its theoretical terms as a pseudo planar free-standing lattice.

However, unlike graphene, silicene is not free-standing in nature. Silicene can be artificially forced to grow upon epitaxy on substrates with a commensurate surface lattice. The details of the silicene epitaxy are reported from the monolayer to the multilayer regime taking the growth onto Ag(111) substrates as paradigmatic example.[2] According to the ideal case of free-standing silicene, the epitaxial silicene is buckled in nature and can be grown in number of differently buckled phase depending on the growth temperature and the deposition rate. A full exploitation of silicene for device applications is hurdled by stability issues at its top and bottom interfaces. At its top interface, silicene is highly reactive under environmental condition thereby suffering from fast structural degradation and oxidation. Encapsulation with an Al2O3 ultra-thin capping films is shown to prevent silicene from degradation thus allowing for ex situ characterization and further processing steps. At the bottom interface of silicene is the hosting substrate. Previously studied hosting substrates are metallic in character, serve as stabilizers for the silicene lattice and strongly interact with it thereby suppressing the formation of Dirac cones in the silicene band structure and ultimately causing a metallization of the silicene itself. The latter fact is a detrimental obstacle for silicene handling. Two approaches are outlined to bypass this drawback.

A) On one hand, a methodology for the silicene encapsulation, delamination, and isolation is presented as enabling technology for device integration. The key-point is this procedure relies on the use of epi-Ag(111) film on mica as cleavable substrates for the silicene epitaxy. A silicene-based transistor can be then fabricated by patterning the native Ag as source/drain contacts of a pure silicene channel.[3] Room temperature operation of field effect transistor incorporating silicene monolayer and multilayer as active channel materials is demonstrated. The observation of an ambipolar behavior in the transistor transfer curves turns out to be the electrical hallmark of silicene.

B) On the other hand, template engineering is also explored as alternative approach to create a metal-free platform for the technological implementation of silicene. As a representative case, the epitaxy of silicene on MoS2 templates is reported and the electronic band alignment between the two terms described. [4] Silicene-on-MoS2 is then integrated into a heterosheet junction transistor making evidence of an effective electrical transport at the Si/MoS2interface.

Possible advances in the functionalization of silicene are discussed which pave the way to a multifunctional applications based on the same silicene platform. Finally, an outlook of silicene contemporaries, germanene, stanene, etc., is proposed aiming at the exploitation of their non-trivial topological properties in nanoelectronics.

[1] “2D Materials for Nanoelectronics”, Eds. M. Houssa, A. Dimoulas, A. Molle, CRC Press, Taylor&Francis Group, 2016 Boca Raton, FL

[2] C. Grazianetti, E. Cinquanta, and A. Molle, 2D Materials 3, 012001 (2016) (Topical Review).

[3] L. Tao, et al., Nature Nanotech. 10, 227 (2015).

[4] A. Molle, et al., Adv. Mater. Interf. (2016), DOI: 10.1002/admi.201500619.

Figure 1