Substitutional Carbon Loss in Si:C Stressor Layers Probed by Deep-Level Transient Spectroscopy
Authors: Simoen Eddy , Dhayalan Sathish Kumar , Hikavyy Andriy Yakovitch , Loo Roger , Rosseel Erik , Vrielinck Henk , Lauwaert Johan 
Published: February 2020

Further scaling of CMOS transistors goes hand in hand with continued straining of the channel, in order to boost the device performance. However, in a bulk FinFET architecture several of the standard techniques lose their effectiveness, so that stress engineering becomes more and more difficult [1]. It has been shown that for n-channel bulk FinFETs, Si:C source/drain stressors are very effective [1], explaining recent research interest [2]-[4]. Si:C hetero-epitaxial layers with about 1% C and highly P-doped can be deposited by a selective Chemical Vapor Deposition (CVD) epitaxial growth based on a cyclic deposition and etching process [5]. One important issue, however, is to maintain throughout further processing as high as possible substitutional carbon in the stressors in combination with an as high as possible active P concentration, to reduce the contact resistance [3],[6]. It has been observed that application of a post-deposition laser anneal (LA) increases the dopant activation level [7] but at the same time results in lower layer stress [6], suggesting the loss of substitutional carbon. In this paper, a Deep-Level Transient Spectroscopy (DLTS) analysis is performed to address this issue.

            Undoped Si:C layers have been deposited on p-type CZ silicon substrates by a cyclic CVD process as described previously [7]. Al Schottky barriers with different diameters have been thermally evaporated. Typical current-voltage (I-V) and 1 MHz capacitance-voltage (C-V) curves are represented in Fig. 1. Fourier-transform (FT) DLTS has been performed from 75 K to room temperature using different bias pulses from VR to VP, as indicated schematically in Fig. 2, showing the depth probed by the measurements. The analysis was performed on as-grown layers and after an 850 oC Rapid Thermal Annealing in N2 for 5 min. As shown in Fig. 3, a hole trap around 180 K is clearly observed in the -0.5 V-->0 V spectrum after RTA, which is absent (or much smaller) in the as-grown sample. Closer to the surface, some hole trap appears as well in the as-grown layer (Fig. 4). Focusing on the RTA sample in Fig. 5, it is clearly shown that in the silicon substrate, a hole trap with activation energy of 0.4 eV is present, which, according to the comparison in Fig. 6 most likely corresponds with the CiOi level. It indicates that during RTA, interstitial carbon (Ci) is formed, next diffuses in the silicon substrate where it becomes trapped by interstitial oxygen (Oi). Similar Cidiffusion has been reported before even during laser annealing [8]. Closer to the epi layer, a broad band of hole trap states is present in Fig. 5, which could correspond with some active carbon cluster type of defects.

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Figure 1