bluuebunny/crossref_metadata_2025 huggingface dataset:
Effects of phenology and sex on social proximity in a gregarious ungulate
Authors: Vander Wal E. , Paquet P.C. , Messier F. , McLoughlin P.D.
Published: July 2013

Structure in sociality is known to relate to intrinsic and extrinsic factors. Less understood are the mechanics of sociality expressed as fine-scale behaviours that maintain hierarchies, mediate competition, or transmit pathogens. A recent novel approach to quantifying fine-scale social behaviour has been to use proximity-logging biotelemetry collars. This technology continuously records data whenever collars are within a predefined distance of each other, at times of day, and in habitats where traditional ethological approaches to focal-individual sampling of behaviours are unfeasible. We tested a series of expectations on fine-scale (≤1.4 m) interaction rates and durations consistent with competing hypotheses of seasonal and sexual segregation for elk (Cervus canadensis Erxleben, 1777). Female–female dyads interacted 4 times more frequently than male–male dyads (mean interaction rate per year: female–female = 62 vs. male–male = 14; P < 0.001), and male–male interactions were 1.5 times longer in duration than female–female interactions (mean interaction length: female–female = 30 s vs. male–male = 45 s; P < 0.001). We propose that fine-scale interactions among members of a population can be modeled as a trade-off between the frequency (quantity) and the duration (quality) of interactions. Our results have implications for understanding sex-based differences in sociality in gregarious herbivores and for disease transmission, which may follow from social intercourse.
Changes in cultured dermal fibroblasts during early passages across five wild bird species
Authors: Calhoon E.A. , Miller M.K. , Jimenez A.G. , Harper J.M. , Williams J.B.
Published: July 2013

With the advent of the usage of primary fibroblasts in comparative and evolutionary biology, it is important for researchers to know the extent to which cells might be altered during the culturing process and how much species might differ in response to cell culture. We compared early changes in cell size and lipid composition of primary dermal fibroblasts grown at physiologically relevant oxygen concentrations (5% O2) from wild-caught species of birds. Fibroblasts from American Robins (Turdus migratorius L., 1766) and Bobwhite Quails (Colinus virginianus (L., 1758)) increased in size early in the culture process and cells from all five species of wild-caught birds exhibited changes in lipid-class composition. The two most common phospholipids, phosphatidylcholine and phosphatidylethanolamine, increased in concentration in all species between early passages and later passages of fibroblasts. Some less abundant lipid species, such as cardiolipin and sphingomyelin, exhibited similar concentrations in all three passages that we measured. Other lipid classes, such as cholesterol, increased in some species in later passages and decreased in others. Although results may vary with cell-culture conditions, this study points to a need for researchers comparing multiple species to take precautions when using cell culture, such as experimenting on the earliest possible passage of cells.
AUTOMORPHISMS OF A NON-TYPE I C*-ALGEBRA
Authors: NOGUCHI AKIRA
Published: July 2013

Glimm's theorem says that a UHF algebra is almost embedded in a separable C*-algebra not of type I. Applying his methods we obtain a covariant version of his result; a UHF algebra with a product type automorphism is covariantly embedded in such a C*-algebra equipped with an automorphism with full Connes spectrum.
HYBRID LATTICE BOLTZMANN METHOD FOR THE SIMULATION OF BLENDING PROCESS IN STATIC MIXERS
Authors: LATT JONAS , KONTAXAKIS DIMITRIOS , CHATAGNY LAURENT , MUGGLI FELIX , CHOPARD BASTIEN
Published: July 2013

A lattice Boltzmann method is proposed to simulate the blending of two fluids in static, laminar mixers. The method uses a mesh-based algorithm to solve for the fluid flow, and a meshless technique to trace the interface between the blended fluids. This hybrid approach is highly accurate, because the position of the interface can be traced beyond the resolution of the grid. The numerical diffusion is negligible in this model, and it is possible to reproduce mixing patterns that contain more than one hundred striations with high fidelity. The implementation of this method in the massively parallel library Palabos is presented, and simulation results are compared with experimental data to emphasize the accuracy of the results.
LATTICE BOLTZMANN METHOD TO STUDY THE CONTRACTION OF A VISCOUS LIGAMENT
Authors: SRIVASTAVA SUDHIR , DRIESSEN THEO , JEURISSEN ROGER , WIJSHOFF HERMAN , TOSCHI FEDERICO
Published: July 2013

We employ a recently formulated axisymmetric version of the multiphase Shan–Chen (SC) lattice Boltzmann method (LBM) [S. Srivastava et al., Phys. Rev. E88, 013309 (2013)] to simulate the contraction of a liquid ligament. We compare the axisymmetric LBM simulation against the slender jet (SJ) approximation model [T. Driessen and R. Jeurissen, Int. J. Comput. Fluid Dyn.25, 333 (2011)]. We compare the retraction dynamics of the tail-end of the liquid ligament from the LBM simulation, the SJ model, Flow3D simulations and a simple model based on the force balance (FB). We find good agreement between the theoretical prediction FB, the SJ model and the LBM simulations.
Efficacy of Acupuncture for Chronic Constipation: A Systematic Review
Authors: Zhang Tao , Chon Tony Y. , Liu Baoyan , Do Alexander , Li Guangxi , Bauer Brent , Wang Linpeng , Liu Zhishun
Published: July 2013

This study was to evaluate the efficacy and safety of acupuncture for chronic functional constipation. Randomized controlled trials were searched in several databases. The primary outcome was a change in the number of weekly spontaneous bowel movements. The secondary outcomes included colonic transit activity, effective rate, Cleveland Clinic Score, and health-related quality of life score. Meta-analysis was done by using RevMan 5.1. After strict screening, 15 RCTs were included, containing 1256 participants. All of them were conducted in China and published in Chinese journals. Meta-analysis indicated that acupuncture for chronic functional constipation was probably as effective as conventional medical therapy in the change of bowel movements. For the colonic transit activity, acupuncture might be the same as conventional medical therapy and could be better than sham acupuncture. For the Cleveland Clinic Score, acupuncture was unlikely inferior to conventional medical therapy and the deep acupuncture was better than normal depth acupuncture in abdominal region. No obvious adverse event was associated with acupuncture for constipation. In conclusion, acupuncture for chronic functional constipation is safe and may improve weekly spontaneous bowel movements, quality of life, and relevant symptoms. However, the evidence was limited by the small sample size and the methodological quality.
The Efficacy and Safety of Standardized Allergen-Removed Rhus verniciflua Extract as Maintenance Therapy after First-Line Chemotherapy in Patients with Advanced Non-Small Cell Lung Cancer
Authors: Lee Jinsoo , Chae Jean , Lee Sookyung , Kim Kyungsuk , Eo Wankyu , Kim Sehyun , Choi Woncheol , Cheon Seong Ha
Published: July 2013

Chemotherapy improves the survival of patients with advanced non-small cell lung cancer (NSCLC), but tumor progression is often inevitable. Strategies are needed to improve the therapeutic efficacy of chemotherapy. Over recent years, there has been increasing interest in the role of maintenance therapy after first-line chemotherapy. We investigated the efficacy and safety of standardized allergen-removed Rhus verniciflua Stokes extract (aRVS) as maintenance therapy in patients with non-progressive disease following first-line chemotherapy. We reviewed the medical records of 33 patients with advanced NSCLC, who started treatment with aRVS in a state of tumor regression or stable disease after completion of four or six cycles of induction chemotherapy at the Integrative Cancer Center, Kyung Hee University Hospital at Gangdong from June 2006 to April 2012. The primary objective of this study was progression-free survival (PFS) of aRVS as maintenance therapy. Secondary objectives included assessments of disease control rate (DCR), overall survival (OS), and the safety of aRVS treatment. The median PFS was 5.2 months with a 6- and 12-month PFS rate of 40.6% and 12.9%, respectively. The DCR was 93.9% and the median OS was 34.8 months. The overall survival rates at 12, 24, and 36 months were 84.2%, 76.7% and 49.9%, respectively. We observed no hematologic toxicity, nephrotoxicity, or hepatotoxicity during aRVS treatment. In conclusion, maintenance therapy with aRVS for patients with advanced NSCLC is well-tolerated and offers encouraging improved PFS and OS compared with historical controls. Our data provide further evidence that aRVS may be used beyond disease progression in this clinical setting.
Hypertensive Cardiac Remodeling Effects of Lignan Extracts from Eucommia ulmoides Oliv. Bark — A Famous Traditional Chinese Medicine
Authors: Li Zhen-Yu , Gu Juan , Yan Jin , Wang Jun-Jie , Huang Wei-Hua , Tan Zhi-Rong , Zhou Gan , Chen Yao , Zhou Hong-Hao , Ouyang Dong-Sheng
Published: July 2013

The lignan extracts from the tree bark of Eucommia ulmoides Oliv., a famous traditional Chinese medicine, have been demonstrated to have inhibitory effects on aldose reductase activity in spontaneously hypertensive rat myocardium. This study was aimed to investigate the hypertensive cardiac remodeling effects of the lignan extracts together with epalrestat. Ten-week-old male spontaneously hypertensive rats were randomly divided into three groups (n = 12, each) and administered 100 mg/kg/d of captopril (angiotensin converting enzyme inhibitor), 100 mg/kg/d of epalrestat (aldose reductase inhibitor) or 300 mg/kg/d of lignan extracts by gavage for 16 weeks. Sex-, age-, and number-matched normotensive Wistar Kyoto rats with spontaneously hypertensive rats were treated with distilled water (vehicle) as controls. Systolic blood pressures were measured periodically. Echocardiography examination was taken when rats were 24 weeks old. We found that both captopril and lignan extracts lowered blood pressure, and inhibited aldose reductase activity similarly to epalrestat. Echocardiography examination and histomorphometry indices were improved in all treated groups (p < 0.05). Therefore, lignan extracts could prevent hypertensive cardiac remodeling, which is likely related to aldose reductase inhibition.
AN ANALYSIS OF 178Pb TO 238U ISOTOPES WITH THE UNIVERSAL AND YUKAWA PROXIMITY POTENTIALS
Authors: JAVADIMANESH E. , HASSANABADI H. , ZARRINKAMAR S.
Published: July 2013

The alpha particle preformation and the penetration probability by the Yukawa proximity potential in the even–even nuclei from 178 Pb to 238 U are studied. Using the experimental values of the alpha decay half-lives and the decay energies, we extract the preformation factors and the penetration probabilities. We also calculate the assault frequencies and the decay constants. The obtained results are motivating.
A FEEDBACK CONTROL STRATEGY FOR AIRFOIL FLUTTER UNDER RANDOM EXCITATION
Authors: HUANG YONG , TAO GANG
Published: July 2013

In this paper, a study was conducted regarding the stability of a binary airfoil under stochastic disturbances with feedback control. A new stochastic controller has been developed and investigated via Monte Carlo simulation. In order to design the new controller, the original system is transformed to the second-order moment one. Then the optimal control parameters can be obtained by searching for the effectual control parameters in the second-order moment system. Finally, the numerical simulations are included to visualize the good performances in flutter suppression.
SERVICE COMPETITION, FIRM PERFORMANCE AND RESOURCE ALLOCATION IN MANUFACTURING: EVIDENCE FROM FIRM-LEVEL DATA IN CHINA
Authors: LIN LEI , WU GUISHENG
Published: July 2013

Service-based differentiation competitive strategy has been hugely adopted by manufacturing firms in both developing and developed countries, which would influence firm performance and resource allocation mode. Against the background of developing countries such as China, this empirical study has two purposes. The first is to investigate the impact of service competition on firm performance. The second is to summarize the resource allocation mode which executives would adopt to implement service competition. Based on service-dominant (SD) logic, resource-based view (RBV) and service marketing theory, this paper constructs a theoretical framework to link the organizational resources (product-related resources and service-related resources), competitive advantage (product quality and service quality) and firm performance (financial performance and non-financial performance), and proposes several hypotheses about the relationships among these constructs. Based on the survey data obtained from manufacturing firms in China in 2006, this paper employs a structural equation modeling (SEM) approach with interaction effect involved to test the hypotheses. Several findings are found through data analysis. First, service competition has positive and significant impact on firm performance, and the contribution of product-related inputs on performance is much larger than that of service-related inputs. This implies that though the impact on performance of service competition is comparatively lower, service can still be the source of product differentiation and act as a positive complement to product-based competition. Second, consistent with our theoretical expectation, the finding indicates that there is a substitutive relationship between service-related resource and product-related resource to a certain degree, though weakly supported by data. This can be explained by the factors such as China's initial resource endowment, low-level stage of the market and the industry, etc. Finally, the paper discusses the theoretical and managerial implications of the research findings, which would provide empirical supports for the implementation of service-based differentiation strategy in manufacturing in developing countries.
ENABLERS OF KNOWLEDGE MANAGEMENT ACROSS BORDERS: A STRUCTURAL APPROACH
Authors: MAGNIER-WATANABE R. , BENTON C.
Published: July 2013

Although knowledge has been cited as one of the most important strategic assets, the creation and sharing of knowledge at the organizational level is a difficult process that will not proceed without incentives and conscious efforts by management. The complexity of knowledge management (KM) is further compounded by the influence of a wide variety of factors such as leadership, ba, organizational culture, organizational control and individual work styles.

Based on a large dataset gathered from a questionnaire survey of a multi-national Japanese pharmaceutical company and its subsidiary in the US, we compare how the aforementioned organizational factors influence KM, expressed through the SECI model of socialization, externalization, combination and internalization. The results of a structural equation modeling path analysis show that a single model of KM should not be applied unilaterally to both organizations, although part of the same company, and instead may need to be adapted to each stage of KM maturity.
Fault localization prioritization
Authors: Yoo Shin , Harman Mark , Clark David
Published: July 2013

Test case prioritization techniques seek to maximize early fault detection. Fault localization seeks to use test cases already executed to help find the fault location. There is a natural interplay between the two techniques; once a fault is detected, we often switch focus to fault fixing, for which localization may be a first step. In this article we introduce the Fault Localization Prioritization (FLP) problem, which combines prioritization and localization. We evaluate three techniques: a novel FLP technique based on information theory, FLINT (Fault Localization using INformation Theory), that we introduce in this article, a standard Test Case Prioritization (TCP) technique, and a “test similarity technique” used in previous work. Our evaluation uses five different releases of four software systems. The results indicate that FLP and TCP can statistically significantly reduce fault localization costs for 73% and 76% of cases, respectively, and that FLINT significantly outperforms similarity-based localization techniques in 52% of the cases considered in the study.
Bounded satisfiability checking of metric temporal logic specifications
Authors: Pradella Matteo , Morzenti Angelo , Pietro Pierluigi San
Published: July 2013

We introduce bounded satisfiability checking, a verification technique that extends bounded model checking by allowing also the analysis of a
descriptive model
, consisting of temporal logic formulae, instead of the more customary
operational model
, consisting of a state transition system. We define techniques for encoding temporal logic formulae into Boolean logic that support the use of bi-infinite time domain and of metric time operators. In the framework of bounded satisfiability checking, we show how a descriptive model can be refined into an operational one, and how the correctness of such a refinement can be verified for the bounded case, setting the stage for a stepwise system development method based on a bounded model refinement. Finally, we show how the adoption of a modular approach can make the bounded refinement process more manageable and efficient. All introduced concepts are extensively applied to a set of case studies, and thoroughly experimented through Zot, our SAT solver-based verification toolset.
An algebra of design patterns
Authors: Zhu Hong , Bayley Ian
Published: July 2013

In a pattern-oriented software design process, design decisions are made by selecting and instantiating appropriate patterns, and composing them together. In our previous work, we enabled these decisions to be formalized by defining a set of operators on patterns with which instantiations and compositions can be represented. In this article, we investigate the algebraic properties of these operators. We provide and prove a complete set of algebraic laws so that equivalence between pattern expressions can be proven. Furthermore, we define an always-terminating normalization of pattern expression to a canonical form which is unique modulo equivalence in first-order logic.

By a case study, the pattern-oriented design of an extensible request-handling framework, we demonstrate two practical applications of the algebraic framework. First, we can prove the correctness of a finished design with respect to the design decisions made and the formal specification of the patterns. Second, we can even derive the design from these components.
Finite satisfiability of UML class diagrams with constrained class hierarchy
Authors: Balaban Mira , Maraee Azzam
Published: July 2013

Models lie at the heart of the emerging model-driven engineering approach. In order to guarantee precise, consistent, and correct models, there is a need for efficient powerful methods for verifying model correctness. Class diagram is the central language within UML. Its correctness problems involve issues of contradiction, namely the
consistency
problem, and issues of finite instantiation, namely the
finite satisfiability
problem.

This article analyzes the problem of finite satisfiability of class diagrams with class hierarchy constraints and generalization-set constraints. The article introduces the
FiniteSat
algorithm for efficient detection of finite satisfiability in such class diagrams, and analyzes its limitations in terms of complex hierarchy structures. FiniteSat is strengthened in two directions. First, an algorithm for identification of the cause for a finite satisfiability problem is introduced. Second, a method for propagation of generalization-set constraints in a class diagram is introduced. The propagation method serves as a preprocessing step that improves FiniteSat performance, and helps developers in clarifying intended constraints. These algorithms are implemented in the
FiniteSatUSE
tool [BGU Modeling Group 2011b], as part of our ongoing effort for constructing a model-level integrated development environment [BGU Modeling Group 2010a].
Using a functional size measurement procedure to evaluate the quality of models in MDD environments
Authors: Marín Beatriz , Giachetti Giovanni , Pastor Oscar , Vos Tanja E. J. , Abran Alain
Published: July 2013

Models are key artifacts in Model-Driven Development (MDD) methods. To produce high-quality software by using MDD methods, quality assurance of models is of paramount importance. To evaluate the quality of models, defect detection is considered a suitable approach and is usually applied using reading techniques. However, these reading techniques have limitations and constraints, and new techniques are required to improve the efficiency at finding as many defects as possible. This article presents a case study that has been carried out to evaluate the use of a Functional Size Measurement (FSM) procedure in the detection of defects in models of an MDD environment. To do this, we compare the defects and the defect types found by an inspection group with the defects and the defect types found by the FSM procedure. The results indicate that the FSM is useful since it finds all the defects related to a specific defect type, it finds different defect types than an inspection group, and it finds defects related to the correctness and the consistency of the models.
Convolution engine
Authors: Qadeer Wajahat , Hameed Rehan , Shacham Ofer , Venkatesan Preethi , Kozyrakis Christos , Horowitz Mark A.
Published: July 2013

This paper focuses on the trade-off between flexibility and efficiency in specialized computing. We observe that specialized units achieve most of their efficiency gains by tuning data storage and compute structures and their connectivity to the data-flow and data-locality patterns in the kernels. Hence, by identifying key data-flow patterns used in a domain, we can create efficient engines that can be programmed and reused across a wide range of applications.

We present an example, the Convolution Engine (CE), specialized for the convolution-like data-flow that is common in computational photography, image processing, and video processing applications. CE achieves energy efficiency by capturing data reuse patterns, eliminating data transfer overheads, and enabling a large number of operations per memory access. We quantify the tradeoffs in efficiency and flexibility and demonstrate that CE is within a factor of 2-3x of the energy and area efficiency of custom units optimized for a single kernel. CE improves energy and area efficiency by 8-15x over a SIMD engine for most applications.
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
Authors: Mukundan Janani , Hunter Hillery , Kim Kyu-hyoun , Stuecheli Jeffrey , Martínez José F.
Published: July 2013

Recent DRAM specifications exhibit increasing refresh latencies. A refresh command blocks a full rank, decreasing available parallelism in the memory subsystem significantly, thus decreasing performance. Fine Granularity Refresh (FGR) is a feature recently announced as part of JEDEC's DDR4 DRAM specification that attempts to tackle this problem by creating a range of refresh options that provide a trade-off between refresh latency and frequency.

In this paper, we first conduct an analysis of DDR4 DRAM's FGR feature, and show that there is no one-size-fits-all option across a variety of applications. We then present
Adaptive Refresh (AR)
, a simple yet effective mechanism that dynamically chooses the best FGR mode for each application and phase within the application.

When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call
command queue seizure
, whereby the memory controller's command queue seizes up temporarily because it is full with commands to a rank that is being refreshed. To attack this problem, we propose two complementary mechanisms called
Delayed Command Expansion (DCE)
and
Preemptive Command Drain (PCD)
.

Our results show that AR does exploit DDR4's FGR effectively. However, once our proposed DCE and PCD mechanisms are added, DDR4's FGR becomes redundant in most cases, except in a few highly memory-sensitive applications, where the use of AR does provide some additional benefit. In all, our simulations show that the proposed mechanisms yield 8% (14%) mean speedup with respect to traditional refresh, at normal (extended) DRAM operating temperatures, for a set of diverse parallel applications.
Improving memory scheduling via processor-side load criticality information
Authors: Ghose Saugata , Lee Hyodong , Martínez José F.
Published: July 2013

We hypothesize that performing processor-side analysis of load instructions, and providing this pre-digested information to memory schedulers judiciously, can increase the sophistication of memory decisions while maintaining a lean memory controller that can take scheduling actions quickly. This is increasingly important as DRAM frequencies continue to increase relative to processor speed. In this paper we propose one such mechanism, pairing up a processor-side load criticality predictor with a lean memory controller that prioritizes load requests based on ranking information supplied from the processor side. Using a sophisticated multi-core simulator that includes a detailed quad-channel DDR3 DRAM model, we demonstrate that this mechanism can improve performance significantly on a CMP, with minimal overhead and virtually no changes to the processor itself. We show that our design compares favorably to several state-of-the-art schedulers.
Agile, efficient virtualization power management with low-latency server power states
Authors: Isci Canturk , McIntosh Suzanne , Kephart Jeffrey , Das Rajarshi , Hanson James , Piper Scott , Wolford Robert , Brey Thomas , Kantner Robert , Ng Allen , Norris James , Traore Abdoulaye , Frissora Michael
Published: July 2013

One of the main driving forces of the growing adoption of virtualization is its dramatic simplification of the provisioning and dynamic management of IT resources. By decoupling running entities from the underlying physical resources, and by providing easy-to-use controls to allocate, deallocate and migrate virtual machines (VMs) across physical boundaries, virtualization opens up new opportunities for improving overall system resource use and power efficiency. While a range of techniques for dynamic, distributed resource management of virtualized systems have been proposed and have seen their widespread adoption in enterprise systems, similar techniques for dynamic power management have seen limited acceptance. The main barrier to dynamic, power-aware virtualization management stems not from the limitations of virtualization, but rather from the underlying physical systems; and in particular, the high latency and energy cost of power state change actions suited for virtualization power management.

In this work, we first explore the feasibility of low-latency power states for enterprise server systems and demonstrate, with real prototypes, their quantitative energy-performance trade offs compared to traditional server power states. Then, we demonstrate an end-to-end power-aware virtualization management solution leveraging these states, and evaluate the dramatically-favorable power-performance characteristics achievable with such systems. We present, via both real system implementations and scale-out simulations, that virtualization power management with low-latency server power states can achieve comparable overheads as base distributed resource management in virtualized systems, and thus can benefit from the same level of adoption, while delivering close to energy-proportional power efficiency.
Efficient virtual memory for big memory servers
Authors: Basu Arkaprava , Gandhi Jayneel , Chang Jichuan , Hill Mark D. , Swift Michael M.
Published: July 2013

Our analysis shows that many "big-memory" server workloads, such as databases, in-memory caches, and graph analytics, pay a high cost for page-based virtual memory. They consume as much as 10% of execution cycles on TLB misses, even using large pages. On the other hand, we find that these workloads use read-write permission on most pages, are provisioned not to swap, and rarely benefit from the full flexibility of page-based virtual memory.

To remove the TLB miss overhead for big-memory workloads, we propose mapping part of a process's linear virtual address space with a
direct segment
, while page mapping the rest of the virtual address space. Direct segments use minimal hardware---base, limit and offset registers per core---to map contiguous virtual memory regions directly to contiguous physical memory. They eliminate the possibility of TLB misses for key data structures such as database buffer pools and in-memory key-value stores. Memory mapped by a direct segment may be converted back to paging when needed.

We prototype direct-segment software support for x86-64 in Linux and emulate direct-segment hardware. For our workloads, direct segments eliminate almost all TLB misses and reduce the execution time wasted on TLB misses to less than 0.5%.
STREX
Authors: Atta Islam , Tözün Pinar , Tong Xin , Ailamaki Anastasia , Moshovos Andreas
Published: July 2013

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove some instruction stalls in exchange for error-prone instrumentation to the code base, or a sharp increase in the L1-I cache unit area and power. Others reduce instruction miss latency by better utilizing a shared L2 cache. SLICC [2], a recently proposed thread migration technique that exploits transaction instruction locality, is promising for high core counts but performs sub-optimally or may hurt performance when running on few cores.

This paper corroborates that OLTP transactions exhibit significant intra- and inter-thread overlap in their instruction footprint, and analyzes the instruction stall reduction benefits. This paper presents STREX, a hardware, programmer-transparent technique that exploits typical transaction behavior to improve instruction reuse in first level caches. STREX time-multiplexes the execution of similar transactions dynamically on a single core so that instructions fetched by one transaction are reused by all other transactions executing in the system as much as possible. STREX dynamically slices the execution of each transaction into cache-sized segments simply by observing when blocks are brought in the cache and when they are evicted. Experiments show that, when compared to baseline execution on 2--16 cores, STREX consistently improves performance while reducing the number of L1 instruction and data misses by 37% and 14% on average, respectively. Finally, this paper proposes a practical hybrid technique that combines STREX and SLICC, thereby guaranteeing performance benefits regardless of the number of available cores and the workload's footprint.
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors
Authors: Bacha Anys , Teodorescu Radu
Published: July 2013

Lowering supply voltage is one of the most effective approaches for improving the energy efficiency of microprocessors. Unfortunately, technology limitations, such as process variability and circuit aging, are forcing microprocessor designers to add larger voltage guardbands to their chips. This makes supply voltage increasingly difficult to scale with technology. This paper presents a new mechanism for dynamically reducing voltage margins while maintaining the chip operating frequency constant. Unlike previous approaches that rely on special hardware to detect and recover from timing violations caused by low-voltage execution, our solution is firmware-based and does not require additional hardware. Instead, it relies on error correction mechanisms already built into modern processors. The system dynamically reduces voltage margins and uses correctable error reports raised by the hardware to identify the lowest, safe operating voltage. The solution adapts to core-to-core variability by tailoring supply voltage to each core's safe operating level. In addition, it exploits variability in workload vulnerability to low voltage execution. The system was prototyped on an HP Integrity Server that uses Intel's Itanium 9560 processors. Evaluation using SPECjbb2005 and SPEC CPU2000 workloads shows core power savings ranging from 18% to 23%, with minimal performance impact.
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
Authors: Cook Henry , Moreto Miquel , Bird Sarah , Dao Khanh , Patterson David A. , Asanovic Krste
Published: July 2013

Computing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on disjoint sets of resources, but this incurs additional energy, power, and capital costs. In this paper, we evaluate the potential of hardware cache partitioning mechanisms and policies to improve efficiency by allowing background applications to run simultaneously with interactive foreground applications, while avoiding degradation in interactive responsiveness. We evaluate these tradeoffs using commercial x86 multicore hardware that supports cache partitioning, and find that real hardware measurements with full applications provide different observations than past simulation-based evaluations. Co-scheduling applications without LLC partitioning leads to a 10% energy improvement and average throughput improvement of 54% compared to running tasks separately, but can result in foreground performance degradation of up to 34% with an average of 6%. With optimal static LLC partitioning, the average energy improvement increases to 12% and the average throughput improvement to 60%, while the worst case slowdown is reduced noticeably to 7% with an average slowdown of only 2%. We also evaluate a practical low-overhead dynamic algorithm to control partition sizes, and are able to realize the potential performance guarantees of the optimal static approach, while increasing background throughput by an additional 19%.
Catnap
Authors: Das Reetuparna , Narayanasamy Satish , Satpathy Sudhir K. , Dreslinski Ronald G.
Published: July 2013

Multiple networks have been used in several processor implementations to scale bandwidth and ensure protocol-level deadlock freedom for different message classes. In this paper, we observe that a multiple-network design is also attractive from a power perspective and can be leveraged to achieve energy proportionality by effective power gating.

Unlike a single-network design, a multiple-network design is more amenable to power gating, as its subnetworks (subnets) can be power gated without compromising the connectivity of the network. To exploit this opportunity, we propose the Catnap architecture which consists of synergistic subnet selection and power-gating policies. Catnap maximizes the number of consecutive idle cycles in a router, while avoiding performance loss due to overloading a subnet.

We evaluate a 256-core processor with a concentrated mesh topology using synthetic traffic and 35 applications. We show that the average network power of a power-gating optimized multiple-network design with four subnets could be 44% lower than a bandwidth equivalent single-network design for an average performance cost of about 5%.
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
Authors: Jing Naifeng , Shen Yao , Lu Yao , Ganapathy Shrikanth , Mao Zhigang , Guo Minyi , Canal Ramon , Liang Xiaoyao
Published: July 2013

The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for traditional SRAM designs in the future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative in future GPGPUs. Compared with SRAM, eDRAM provides higher density and lower leakage power. However, the limited data retention time in eDRAM poses new challenges. Periodic refresh operations are needed to maintain data integrity. This is exacerbated with the scaling of eDRAM density, process variations and temperature. Unlike conventional CPUs which make use of multi-ported RF, most of the RFs in modern GPGPU are heavily banked but not multi-ported to reduce the hardware cost. This provides a unique opportunity to hide the refresh overhead. We propose two different eDRAM implementations based on 3T1D and 1T1C memory cells. To mitigate the impact of periodic refresh, we propose two novel refresh solutions using bank bubble and bank walk-through. Plus, for the 1T1C RF, we design an interleaved bank organization together with an intelligent warp scheduling strategy to reduce the impact of the destructive reads. The analysis shows that our schemes present better energy efficiency, scalability and variation tolerance than traditional SRAM-based designs.
SIMD divergence optimization through intra-warp compaction
Authors: Vaidya Aniruddha S. , Shayesteh Anahita , Woo Dong Hyuk , Saharoy Roy , Azimi Mani
Published: July 2013

SIMD execution units in GPUs are increasingly used for high performance and energy efficient acceleration of general purpose applications. However, SIMD control flow divergence effects can result in reduced execution efficiency in a class of GPGPU applications, classified as divergent applications. Improving SIMD efficiency, therefore, has the potential to bring significant performance and energy benefits to a wide range of such data parallel applications.

Recently, the SIMD divergence problem has received increased attention, and several micro-architectural techniques have been proposed to address various aspects of this problem. However, these techniques are often quite complex and, therefore, unlikely candidates for practical implementation. In this paper, we propose two micro-architectural optimizations for GPGPU architectures, which utilize relatively simple execution cycle compression techniques when certain groups of turned-off lanes exist in the instruction stream. We refer to these optimizations as basic cycle compression (BCC) and swizzled-cycle compression (SCC), respectively. In this paper, we will outline the additional requirements for implementing these optimizations in the context of the studied GPGPU architecture. Our evaluations with divergent SIMD workloads from OpenCL (GPGPU) and OpenGL (graphics) applications show that BCC and SCC reduce execution cycles in divergent applications by as much as 42% (20% on average). For a subset of divergent workloads, the execution time is reduced by an average of 7% for today's GPUs or by 18% for future GPUs with a better provisioned memory subsystem. The key contribution of our work is in simplifying the micro-architecture for delivering divergence optimizations while providing the bulk of the benefits of more complex approaches.
Die-stacked DRAM caches for servers
Authors: Jevdjic Djordje , Volos Stavros , Falsafi Babak
Published: July 2013

Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories --- block-based and page-based. The former organize data in conventional blocks (e.g., 64B), ensuring low off-chip bandwidth utilization, but co-locate tags and data in the stacked DRAM, incurring high lookup latency. Furthermore, such designs suffer from low hit ratios due to poor temporal locality. In contrast, page-based caches, which manage data at larger granularity (e.g., 4KB pages), allow for reduced tag array overhead and fast lookup, and leverage high spatial locality at the cost of moving large amounts of data on and off the chip.

This paper introduces Footprint Cache, an efficient die-stacked DRAM cache design for server processors. Footprint Cache allocates data at the granularity of pages, but identifies and fetches only those blocks within a page that will be touched during the page's residency in the cache --- i.e., the page's footprint. In doing so, Footprint Cache eliminates the excessive off-chip traffic associated with page-based designs, while preserving their high hit ratio, small tag array overhead, and low lookup latency. Cycle-accurate simulation results of a 16-core server with up to 512MB Footprint Cache indicate a 57% performance improvement over a baseline chip without a die-stacked cache. Compared to a state-of-the-art block-based design, our design improves performance by 13% while reducing dynamic energy of stacked DRAM by 24%.
Resilient die-stacked DRAM caches
Authors: Sim Jaewoong , Loh Gabriel H. , Sridharan Vilas , O'Connor Mike
Published: July 2013

Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache storage. For server and high-performance computing markets, however, such DRAM caches must also provide sufficient support for reliability and fault tolerance. While conventional off-chip memory provides ECC support by adding one or more extra chips, this may not be practical in a 3D stack. In this paper, we present a DRAM cache organization that uses error-correcting codes (ECCs), strong checksums (CRCs), and dirty data duplication to detect
and
correct a wide range of stacked DRAM failures, from traditional bit errors to large-scale row, column, bank, and channel failures. With only a modest performance degradation compared to a DRAM cache with no ECC support, our proposal can correct all single-bit failures, and 99.9993% of all row, column, and bank failures, providing more than a 54,000x improvement in the FIT rate of silent-data corruptions compared to basic SECDED ECC protection.
The locality-aware adaptive cache coherence protocol
Authors: Kurian George , Khan Omer , Devadas Srinivas
Published: July 2013

Next generation multicore applications will process massive amounts of data with significant sharing. Data movement and management impacts memory access latency and consumes power. Therefore, harnessing data locality is of fundamental importance in future processors. We propose a scalable, efficient shared memory cache coherence protocol that enables seamless adaptation between private and logically shared caching of on-chip data at the fine granularity of cache lines. Our data-centric approach relies on in-hardware yet low-overhead runtime profiling of the locality of each cache line and only allows private caching for data blocks with high spatio-temporal locality. This allows us to better exploit the private caches and enable low-latency, low-energy memory access, while retaining the convenience of shared memory. On a set of parallel benchmarks, our low-overhead locality-aware mechanisms reduce the overall energy by 25% and completion time by 15% in an NoC-based multicore with the Reactive-NUCA on-chip cache organization and the ACKwise limited directory-based coherence protocol.
On the feasibility of online malware detection with performance counters
Authors: Demme John , Maycock Matthew , Schmitz Jared , Tang Adrian , Waksman Adam , Sethumadhavan Simha , Stolfo Salvatore
Published: July 2013

The proliferation of computers in any domain is followed by the proliferation of malware in that domain. Systems, including the latest mobile platforms, are laden with viruses, rootkits, spyware, adware and other classes of malware. Despite the existence of anti-virus software, malware threats persist and are growing as there exist a myriad of ways to subvert anti-virus (AV) software. In fact, attackers today exploit bugs in the AV software to break into systems.

In this paper, we examine the feasibility of building a malware detector in hardware using existing performance counters. We find that data from performance counters can be used to identify malware and that our detection techniques are robust to minor variations in malware programs. As a result, after examining a small set of variations within a family of malware on Android ARM and Intel Linux platforms, we can detect many variations within that family. Further, our proposed hardware modifications allow the malware detector to run securely beneath the system software, thus setting the stage for AV implementations that are simpler and less buggy than software AV. Combined, the robustness and security of hardware AV techniques have the potential to advance state-of-the-art online malware detection.
Virtualizing power distribution in datacenters
Authors: Wang Di , Ren Chuangang , Sivasubramaniam Anand
Published: July 2013

Power infrastructure contributes to a significant portion of datacenter expenditures. Overbooking this infrastructure for a high percentile of the needs is becoming more attractive than for occasional peaks. There exist several computing knobs to cap the power draw within such under-provisioned capacity. Recently, batteries and other energy storage devices have been proposed to provide a complementary alternative to these knobs, which when decentralized (or hierarchically placed), can temporarily take the load to suppress power peaks propagating up the hierarchy. With aggressive under-provisioning, the power hierarchy becomes as central a datacenter resource as other computing resources, making it imperative to carefully allocate, isolate and manage this resource (including batteries), across applications. Towards this goal, we present
vPower
, a software system to virtualize power distribution. vPower includes mechanisms and policies to provide a
virtual power hierarchy
for each application. It leverages traditional computing knobs as well as batteries, to apportion and manage the infrastructure between co-existing applications in the hierarchy. vPower allows applications to specify their power needs, performs admission control and placement, dynamically monitors power usage, and enforces allocations for fairness and system efficiency. Using several datacenter applications, and a 2-level power hierarchy prototype containing batteries at both levels, we demonstrate the effectiveness of vPower when working in an under-provisioned power infrastructure, using the right computing knobs and the right batteries at the right time. Results show over 50% improved system utilization and scale-out for vPower's over-booking, and between 12-28% better application performance than traditional power-capping control knobs. It also ensures isolation between applications competing for power.