Optimizing TSV Fill Phases for Improved Fill Rate, Process Stability and Void Performance
Authors: Ghekiere John , Mikkola Robert , Kebreab Daniel , Burnham James , Hoerner Bridger , Erickson David 
Published: February 2020

Through Silicon Via integration provides enabling technology as the semiconductor industry continues to implement 2.5D and true 3D device and system packages. The drive for improved performance and the foray into the era of the Internet of Things promises a continued need for TSV advancement including different barrier/seed schemes and aggressive aspect ratios.

While the industry has developed fairly robust gap filling processes for conventional interposer and via middle features in the range of 5X50µm and 10X100µm, continued scaling of aspect ratio ensures that TSV plating will require new innovations to provide a stable process free of killer voids such as seam and pinch off voids. Reliability performance will demand a reduction and/or elimination of the microvoid formation between grains. Additionally, the costs associated with TSV integration will continue to drive the need for faster fill and thinner overburden in order to minimize cost of ownership.

For this reason, the continued optimization of plating conditions is critical and includes factors such as control of the current density at via bottom during nucleation and initiation of gap filling, sidewall grain orientation, degree of sidewall suppression, additive diffusion rate, etc.

This paper will explore optimal electrochemical polarization conditions within the via during the key phases of gap filling, such as nucleation, conformal filling, and the transition to bottom-up filling. As an example, the plating process begins with the nucleation of plated copper onto the seed layer. This phase targets the formation of a high density of nucleation sites in order to form a uniform and conformal initial layer of ECD copper. The theoretical optimal conditions include uniform seed layer from top to bottom, full concentration of additives present homogenously throughout the via at time zero, and uniform current density at each point along the via sidewall and via bottom. Additionally, the field area must be polarized to a high degree.  In actual practice, the seed layer is typically thinner toward the bottom of the via and can often be discontinuous. For conventional TSV fill, the diffusion of the plating chemistry takes time and by design the diffusion rate of the various additives is different. Current density is unlikely to be uniform the entire length of the sidewall due to variations in seed thickness.

Despite this gap between the theoretical optimal condition and the actual conditions, continued management of additive activity and waveform has enabled the development of a robust gap filling process. However, the opportunity for further innovation remains with respect to the various the phases of fill: Immersion –> Nucleation; Nucleation –> Mixed Growth Phase; Mixed Growth –> Bottom-Up Dominated Fill; Bottom-Up Dominated Fill –> Top Off; Top Off –> Overburden.

This paper will discuss optimal conditions at each phase and present results of several innovations from Applied Materials which take advantage of the gaps between phases and provide improvements such as: significant fill time reduction, supreme stabilization of electrochemical activity against bath aging, and improvements in the formation of microvoids between grains.