bluuebunny/crossref_metadata_2025 huggingface dataset:
Thermal-Electrochemical Lithium-Ion Battery Simulations on Microstructure and Porous Electrode Scale
Authors: Latz Arnulf , Zausch Jochen
Published: October 2015

Heat production within a battery cell is governed by local fluxes of ions and electrical currents in the microstructure of the battery electrodes. These fluxes are strongly coupled with thermal transport, leading to a fully coupled reaction transport model for batteries. By applying the volume-averaging technique to our thermal-electrochemical microscopic theory the corresponding thermal-electrochemical porous electrode theory can be derived. Implementation of both models in our simulation software BEST allows to compare the results of the homogenized theory with numerically averaged simulations on micro scale. Whereas the numerically averaged results agree very well with the results of porous electrode theory, strong fluctuations around this average (e.g. of the overpotential) are observed in microstructures. Our results raise the question to which extent porous electrode theory can be used to predict degradation phenomena in batteries.
Reaction and Mass Transport Simulation of 3-Dimensional All-Solid-State Lithium-Ion Batteries for the Optimum Structural Design
Authors: Itoh Fumiya , Inoue Gen , Kawase Motoaki
Published: October 2015

In order to increase energy density and enhance safety, all-solid-state lithium-ion battery has been developed as a storage battery for electric vehicles. However, its power density is too low to be applied for EV. In recent years, 3-dimensional electrode such as an interdigitated electrode is proposed, which can increase both energy density and power density. In this study, electrochemical reactions and mass transport phenomena of 3D all-solid-state battery were simulated with a porous electrode theory. Discharge property was improved by complicating 3D structures and Str. 2 displayed excellent discharge property at a rate of 1 to 10C and a solid electrolytes ionic conductivity of 0.01 to 1 S/m. Furthermore, the structure of which diffusion length is shorter than 36.57 μm can realize the full charge within 6 minutes at more than 1 S/m, and the diffusion length within 8 μm is necessary at 0.01 S/m to 1 S/m.
Simulating an Applied Voltage in Molecular Dynamics Using Charge Optimized Many Body (COMB3) Potentials
Authors: Antony Andrew Charles , Akhade Sneha A. , Liang Tao , Janik Michael J. , Maranas Janna K , Sinnott Susan B.
Published: October 2015

The work presented here gives an atomic level description of applying an external voltage during a molecular dynamics (MD) simulation. We present the methodology behind simulating an applied voltage and implement the method to a Cu/H2O (electrode/electrolyte) system. Water molecules are found to be less mobile at the interface due to a disruptive influence of metal-water interactions on the hydrogen bonded network found in bulk water systems but the effect of an applied voltage on the interfacial dynamics is found to be negligible. Molecular structure is determined by analyzing the degree of orientational ordering near the metal surface and it is concluded that the metal surface polarizes the molecules, causing an alignment of the molecular dipoles. Future results and additional analysis are also addressed towards the end of the results section.
A Double-Layer Model for Describing the Effect of Solvation and Adsorption of Ions on Electrode Surfaces in Batteries
Authors: Lück Jessica , Latz Arnulf
Published: October 2015

We developed a consistent model to describe the effect of the electrochemical double-layer on the exchange reaction occurring at the interface of an electrode and a concentrated electrolyte. This model includes electrosorption, i.e. an accumulation of surface charges, and the screening of these charges within the electrochemical double-layer. We determine charges of the double-layer only from fundamental thermodynamic and electrostatic considerations, without assuming any specific structural properties of the electrolyte-electrode interface. This mathematical description is integrated in a thermodynamic consistent reaction-transport model for lithium-ion batteries (6).
Effective Ionic Resistance in Battery Separators
Authors: Hattendorff Johannes , Landesfeind Johannes , Ehrl Andreas , Wall Wolfgang A. , Gasteiger Hubert A.
Published: October 2015

The ionic transport properties of battery materials such as separators can be measured by AC impedance. We show data from two measurement setups and demonstrate how a reliable measurement of the high frequency resistance and thus tortuosity of typical separators can be achieved.
Material Deposition into Porous Silicon Template
Authors: Harraz Farid A. , Ismail Adel A. , Al-Sayari Saleh A. , Al-Hajry Ali , Al-Assiri Mohammad S.
Published: October 2015

A wide range of materials can be prepared using porous silicon template. The shape and pore size of the starting silicon template, along with the type of material and deposition conditions determine the final synthesized structures. In this work, chemical and electrochemical deposition of various metals and conducting polymers into porous silicon templates are demonstrated, with an emphasis on the processing issues associated with the deposition approach. The electrochemical deposition of polypyrrole into porous silicon template as a case study is addressed and thoroughly discussed.
Porosity Control and Transfer in Silicon Nanostructures through Electrochemical & Chemical Etching
Authors: Defforge Thomas , Vijayakumar Sanahan , Loni Armando , Chaix Arnaud , Sauldubois Audrey , Andreazza-Vignolle Caroline , Cunin Frédérique , Di Renzo Francesco , Canham Leigh T , Gautier Gaël
Published: October 2015

High surface area and controlled pore diameter silicon nanostructures were prepared using a two-step etching procedure. Firstly, the experimental conditions of silicon electrochemical etching leading to the formation of high surface area porous silicon thin films were described. Thereafter, the porous silicon layers were either lifted off the substrate to collect the porous particles or subjected to metal-assisted chemical etching (MaCE) in a hydrofluoric acid - silver nitrate solution to produce high aspect ratio porous silicon nanowires with controlled pore dimensions. The consecutive electrochemical and chemical (MaCE) silicon etching procedures enabled the synthesis of porous silicon nanowires with high specific surface area (up to 460 m²/g) along with low average pore diameter (below 6.5 nm).
Low Doped n-type Localized Porous Silicon Made by Hole Injection from Back-side p+/n Junction for Power Switches Application
Authors: Fèvre Angélique , Menard Samuel , Defforge Thomas , Gautier Gael
Published: October 2015

The macropore morphology in low doped n-type silicon depending on hole supply technique is investigated. Electron-hole pair generation by illumination and hole injection through p+/n- back-side junction are compared in a highly concentrated HF electrolyte (30 wt. %). Then, the morphology similarities generated by the two techniques are verified towards anodization current density and electrolyte additives. Porous silicon layer is realized in low-doped n-type silicon as part of a device fabrication in industrial environment. Consequently, illumination technique induces implementation complexity. Then, porous silicon etching was investigated using hole injection from back-side p+/n- junction technique. In addition, implanted p+ regions were incorporated in the low-doped n-type silicon at the anodic surface. We studied these regions in the capacity of masking layers. It was shown to be ineffective to prevent porous silicon formation as a mesoporous layer was observed after anodization.
Nanoporous Silicon-Based Platforms for Biological Applications Fabricated by UV Laser Techniques
Authors: Recio-Sanchez Gonzalo , Pelaez Ramon J , Afonso Carmen N. , Vega Fidel , Martin-Palma Raul J
Published: October 2015

One- and two-dimensional fringe patterns were fabricated on nanostructured porous silicon (nanoPS) layers. These patterns are created by phase-mask laser interference using single pulses of an ultraviolet excimer laser. The method constitutes a single-step and flexible approach to produce a large variety of patterns formed by alternate regions of almost untransformed nanoPS and regions where its surface has melted and transformed into Si nanoparticles. Finally, direct binding (with no previous functionalization) of human mesenchymal stem cells to the different patterns is analyzed aiming at using these structures for biological applications.
Response Simulation and Extraction of Gas Concentrations for Nanostructure Decorated Nano-/Microporous Silicon Interfaces
Authors: Laminack William , Baker Caitlin , Gole James L.
Published: October 2015

A simple MEMS/NEMS platform facilitates the modeling of the interaction of nanostructured metal oxide decorated porous silicon interface with gas phase analytes. These conductometric sensors operate at room temperature and atmospheric pressure, and are simple to construct. Nanostructured metal oxide deposition provides a matrix of responses to various gas species, facilitating the extraction of ambient gas concentrations from the sensor response. The sensors are simulated using a combination diffusion-interaction model that considers adsorption and electronic Fermi distribution dominated responses. The sensor simulation model provides insight into the interaction mechanisms that occur between the gas analyte and porous silicon sensor interface. Ambient gas concentrations are extracted from the sensor response through an analysis of the time derivatives of the response and an application of the nanostructured metal oxide deposition sensitivity matrix.
Porous Layers Composed of Oxide Crystallites Formed by the Combination of Laser Ablation and Anodization of Metal
Authors: Ganas Abbie S. , Znamensky Dmitry A. , Méndez Alba Nahúm , Hernández-Pozos José Luis , Kolasinski Kurt W
Published: October 2015

High-voltage anodization is well known for producing nanostructures such as porous alumina and TiO2 nanotubes. The formation mechanisms involve an intricate balance between oxide growth and dissolution in which pore initiation and propagation is convoluted with the need for strain relief. Laser ablation with a nanosecond pulsed Nd:YAG laser (532 nm) produces texture e.g. arrays of pillars, macropores and ripples. Nanoparticles produced in the ablation plume can also be deposited on the target or a remote substrate. These substrates are anodized in solutions typically used for porous film and nanotube production (including viscous fluoride-containing electrolytes). A number of metals have been investigated, with emphasis here on Al and Ti as well as Zn. Laser pre-texturing results in the formation of structures unattainable by anodization alone. Deposited nanoparticles of Al and Zn are found to act as seeds for the growth of oxide crystallites that fuse into porous crystallite films.
Catalytic Activity of Ru for Metal-Assisted Etching of Si
Authors: Sadakane Daisuke , Yamakawa Kano , Fukumuro Naoki , Yae Shinji
Published: October 2015

Metal-assisted etching of Si is an electroless method that can produce porous Si by immersing metal-modified Si in a HF solution without electric bias. We reported that the etching rate of noble metal-modified Si in a simple HF solution including oxygen under dark conditions depended on the catalytic activity of metal for oxygen reduction. Only palladium exhibits high activity for the etching under dissolved oxygen-free and dark conditions. In this study, the catalytic activity of Ru for the etching of Si has been investigated. Ru nanoparticles are electrodeposited on Si substrates. Electroless displacement deposition using RuCl3 solution including HF can form Ru nanoparticles not on mirror-polished n-Si substrate but on roughed one. The etching rate of Ru-particle-deposited Si is similar to that of Rh case which is changed with dissolved oxygen concentration. On the roughed Si substrates, the Ru nanoparticles assist the etching even under oxygen-free and dark conditions.
Corrosion Product Structures of Steel Samples Exposed to Amine Solutions Used for H2s Removal.
Authors: Alpuche-Aviles Mario A , Waite Scott , Malkiewich Ryan , Parajuli Suman , Muñoz Maria , Chhetri Pushpa
Published: October 2015

We present the corrosion effects of heat stable salts (HSS), i.e., amine salts and amino acids that occur during removal of H2S from petroleum and natural gas with methyl diethanolamine (MDEA) solutions. The salts include heat stable salts and amine degradation products. Corrosion rates were measured using coupon weight loss in liquid and vapor phases in stirred solutions that model amine plant environment (e.g., refinery systems) in a chamber that enables exposure of samples to the gas and liquid phases. At increasing concentration of HSS the corrosion products show well-defined structures in the nanometer scale for the samples exposed to the liquid phase. However, this was not observed in the vapor phase. The corrosion products include amorphous, columnar and disk-shaped structures depending on exposure conditions. We propose that the substrates become initially passivated and that localized corrosion takes place under the conditions of our study that mimic the HSS build-up.
(Invited) Formation of Self-Organized Porous Anodic Films on Iron and Stainless Steels
Authors: Habazaki Hiroki , Shahzad Khurram , Hiraga Takuya , Tsuji Etsushi , Aoki Yoshitaka
Published: October 2015

High purity iron and commercial Type 304 and 430 stainless steels were anodized in ethylene glycol electrolytes containing fluoride and water. When iron was anodized in the electrolytes containing relatively high water concentrations (≥1.5 mol dm−3) at 50 V, porous anodic films with scalloped metal/film interface were developed. In contrast, the anodic films formed in the electrolytes with low water concentrations (≤0.5 mol dm−3) resulted in the flat metal/film interface. In addition, the interpore distance became smaller with respect to the thickness of barrier layer when the water concentration is reduced. These morphological changes may be associated with the change in the composition of the anodic films. Anodizing of stainless steels was dependent upon the type of stainless steel; a steady-state current continued up to ~160 V on Type 430 stainless steel, while exponential current increase occurred above ~50 V on Type 304 stainless steel during potentiodynamic anodizing. The thickness of the barrier layer and the morphology of the porous layer were largely dependent upon the type of stainless steel. Based on such findings, the mechanism of film growth was discussed.
Nanoporous α-Alumina Membranes with Pore Diameters Tunable over Wide Range of 30-350 nm
Authors: Asoh Hidetaka , Masuda Tatsuya , Ono Sachiko
Published: October 2015

Nanoporous and α-alumina membranes with pore diameters tunable over a wide range of approximately 30–350 nm were successfully fabricated by optimizing the conditions for anodizing, subsequent detachment and heat treatment. Flat α-alumina membranes, each with a diameter of 25 mm and a thickness of approximately 50 μm, were obtained without thermal deformation. The present process is promising for fabricating free-standing and flat α-alumina membranes with various pore diameters; such membranes have potential technological and scientific applications in various fields.
(Invited) Improving Memory Performance of Cu/HfO2/Pt Conducting-Bridge RAM by Solvent Substitution
Authors: Kinoshita Kentaro
Published: October 2015

A ‘pore engineering’, which is a method for controlling the memory performance of conducting-bridge random access memory (CB-RAM) by regarding the polycrystalline oxide memory layer as a nano-porous body, is proposed. This method is intended to control the resistive switching properties by providing appropriate solvents to the pores, and by controlling the size, physical and chemical properties of the pores. In this paper, a forming voltage, set voltage, and their dispersions were confirmed to be decreased by supplying solvents which have high solubility of Cu to the polycrystalline HfO2 layer of Cu/HfO2/Pt structures. In particular, the robustness of resistive switching ability against environmental change and the robustness against the device destruction by voltage stress were enhanced by supplying ionic liquid (IL) without impairing the excellent switching performances, due to the high liquid phase stability and high ion solubility of IL.
Set and Reset Voltage Interdependence in Resistive Switching Memory Cells
Authors: Ghosh Gargi , Orlowski Marius K
Published: October 2015

A statistical correlation between set voltage, Vset, and the preceding reset voltage, Vreset, has been observed on a multitude of devices in a resistive RRAM memory array. This correlation can be reproduced on a single device by generating a spread in Vreset values by varying the linear voltage ramp rate during the reset operation. The dependence of Vreset on voltage ramp rate is modeled successfully by assuming a fixed critical Joules heat required to trigger the rupture of the filament. The observed dependence of Vset and Vreset on the voltage ramp rate may be used to tighten Vset and Vreset distributions, by applying during the reset operation low voltage ramp rates to cells with high Vset and high ramp rates to cells with low Vset values.
Low Stress and High Ductility Copper Electroplating Additive Development
Authors: Wei Lingyun , Kao Yu Hua , Hazebrouck Rebecca , Corona Robert , Lieb Bryan , Wang Ying , Lowe Michael A. , Lefebvre Mark , Pyo Sung-Ho , Tachikawa Wataru , Calvert Jeffrey
Published: October 2015

Due to cost concerns, significant changes have been made in the silicon manufacturing process leading to thinner Si wafers. This change brings many challenges for copper metallization. One of the biggest challenges is to maintain low internal stress of the copper deposit. This is key to avoid solar wafer warpage and maintain good adhesion. Copper deposits with high ductility are also desired to prevent or reduce the potential for the copper deposit to crack under stress over time. Ideal copper deposits exhibit low internal stress and high ductility. However, development of this plating chemistry is a challenge, as improvement in one attribute typically comes at the expense of another. In this paper, the performance of new acid copper electroplating bath capable of achieving both low internal stress and good ductility will be highlighted. Additive impact on copper deposit material properties and correlation between these properties and performance will be discussed.
Ternary Blend Bulk-Heterojunction Solar Cells Based on Active Layers of PTB7, PC71BM, and PC61BM
Authors: Qiu Jiayu , Kiriishi Koudai , Hashiba Kousei , Fujii Shunjiro , Kataura Hiromichi , Nishioka Yasushiro
Published: October 2015

Bulk-heterojunction solar cells were fabricated using ternary blend dichlorobenzene solutions of poly[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]-thiophenediyl] (PTB7):[6,6]-phenyl-C61-butyric acid methyl ester (PC61BM):[6,6]-phenyl C71 butyric acid methyl ester (PC71BM) with different weight ratios between PC61BM and PC71BM. In all the solar cells, the overall weight ratio of polymer to fullerene was maintained at 1:1.5, while the composition of the fullerene component (PC61BM:PC71BM) was varied. The measurement results of the solar cell performance showed that the open-circuit voltage notably increased for PC61BM weight fractions between 10% and 90%, while it decreased at 100%. The short-circuit current showed the most significant increase in the PC61BM weight fraction range between 50% and 60%. A power conversion efficiency of 3.4% was achieved when the PC61BM weight fraction was between 50% and 60%. These results may suggest that the transport of the photoexcited electrons between the cathode and the PC61BM/PC71BM nanodomains was enhanced.
(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices
Authors: Takagi Shinichi , Chang Chih-Yu , Yokoyama Masafumi , Nishi Koichi , Zhang Rui , Ke Mengnan , Han Jae-Hoon , Takenaka Mitsuru
Published: October 2015

Critical issues for high quality Ge/III-V MOS gate stacks have been reviewed and discussed. For Ge gate stacks, a plasma post oxidation method can realize high quality ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks. We have evaluated limiting factors of electron and hole mobility in Ge MOSFETs. The Ge MOS channel mobility in a high Ns region is significantly degraded by surface roughness scattering as well as trapping of free carriers into interface states inside the Ge bands. It is shown that reduction in surface roughness through low temperature PPO and reduction in Dit inside the bands due to atomic Deuterium annealing can improve the effective mobility in the high Ns region. For InGaAs gate stacks, ALD La2O3 gate stacks yield lower Dit than the Al2O3 ones. For GaSb gate stacks, high ALD temperature or annealing temperature increases Dit at Al2O3/GaSb interfaces. InAs passivation for GaSb surfaces can effectively significantly improve the MOS interface properties and the thermal stability of the Al2O3/GaSb interfaces.
(Invited) Surface Passivation of High-k Dielectric Materials on Diamond Thin Films
Authors: Kovi Kiran Kumar , Majdi Saman , Gabrysch Markus , Suntornwipat Nattakarn , Isberg Jan
Published: October 2015

Single-crystalline CVD diamond films have excellent electrical and material properties with potential in high power, high voltage and high frequency applications that are out of reach for conventional semiconductor materials. For realization of efficient devices (e.g. MOSFET), finding a suitable dielectric is essential to improve the reliability and electrical performance of devices. In the current study, we present results from surface passivation studies by high-k dielectric materials such as aluminum oxide and hafnium oxide deposited by ALD on intrinsic and boron doped diamond substrates. The hole transport properties in the intrinsic diamond films were evaluated and compared to unpassivated films using the lateral time-of-flight technique. The MOS capacitor structure, which forms the basic building block of the MOSFET, is discussed.
(Invited) Defects and Dopants in Silicon and Germanium Nanowires
Authors: Fanciulli Marco , Belli Matteo , Paleari Stefano , Lamperti Alessio , Molle Alessandro , Sironi Mauro , Pizio Antonio
Published: October 2015

The current status of the investigation of defects in silicon and germanium nanowires and at the interface between the group IV semiconductor and its oxide in 1D nanostructures is reviewed and discussed. The paper concentrates on nanowires produced by metal assisted chemical etching for silicon and by the vapor-liquid-solid (VLS) growth method for germanium. For silicon nanowires the role of defects at the interface between the semiconductor and its oxide and of hydrogen in passivating donor atoms is addressed. The experimental data on germanium nanowires are scarce and we report here only evidence of dislocations.
Utilization of a Non-Ionic Surfactant in the Fabrication of Water-Borne Polymeric Semiconductor Nanoparticles for High-Performance, Green Organic Electronics
Authors: Cho Jangwhan , Yoon Seongwon , Ha Jaeun , Chung Dae Sung
Published: October 2015

Despite great advances in the field of organic semiconductors, especially regarding charge carrier mobility, most fabrication processes still involve toxic organic solvents. Aqueous colloids of polymeric semiconducting nanoparticles may be good alternatives to address this environmental issue. Here, we demonstrate the use of a non-ionic surfactant to realize high-performance, green organic electronics, based on an inherently high-mobility liquid-crystalline polymeric semiconductor.
Electrical Studies on Parylene-C Columnar Microfibrous Thin Films
Authors: Khawaji Ibrahim H , Chindam Chandraprakash , Orfali Wasim , Awadelkarim Osama Osman , Lakhtakia Akhlesh
Published: October 2015

Columnar microfibrous thin films (μFTFs) of Parylene C are deposited on top of p-type Si substrate using physicochemical vapor deposition to form metal-insulator-semiconductor and metal-insulator-metal structures utilizing the Parylene-C μFTFs as the gate dielectric. The columnar μFTFs were characterized for their electrical properties and dielectric integrity using leakage-current and capacitance measurements at temperatures in the 200K - 500 K range and at frequencies in the range 1 kHz to 1 MHz. Observed variations in leakage current and capacitance were found to be consistent with transport mechanisms involving the Poole–Frenkel and Schottky emission mechanisms as well as carrier trapping/detrapping at interfacial traps.
The Effect of CoSi2 Formation Process on the CMOS Transistor Electrical Properties for Sub 100nm Memory Applications
Authors: Park Jeong Hoon , Kim Sang Jin , Lee Jung Ho , Yoo Chang Jun , Kang Hyo Jin , Lee Byung Cheol , Jeong Jae Goan
Published: October 2015

We investigated the effect of various processing conditions on the abnormal CoSi2 formation and the electrical properties in real sub 100nm ULSI devices. We tried to check the full chip level drain leakage current (DLC_chip), and unit transistor level drain leakage current(DLC_unit). It was found that with varying dopant species and concentration, the source-drain junction depth, dopant spatial distribution and local electric field could change, which brought about the drain leakage current(DLC) phenomenon.. When we used the Ti/TiN capping layer and hot temperature PVD, the abnormal growth was suppressed and the interface became smooth. For electrical properties, the DLC_chip of both cases showed the significant improvement, however, the DLC_unit showed a negligible change. We concluded that, in spite of the degradation of DLC in typical transistor, the overall level of DLC_chip has improved due to the significantly decreased amount of defective sites like abnormal growth.
(Invited) Variability in FinFET SRAM Cells
Authors: Endo Kazuhiko , O'uchi Shinichi , Matsukawa Takashi , Liu Yongxun , Masahara Meishoku
Published: October 2015

Double-gate (DG) device technology has been proposed and investigated for many years. Variability of the device due to the various random sources is increasing and will reduce the yield of the circuit. This paper presents variability issues in the scaled FinFETs and their effects on the SRAM performance. The effectiveness of Vth controllable independent-DG technology to enhance circuit performance is also shown.
(Invited) Novel Selector and 3D RRAM Development for High Density Non-Volatile Memory
Authors: Yang Hongxin , Tan Chun Chia , He Wei , Li Minghua , Jiang Yu , Yang Yi
Published: October 2015

The development of a higher density non-volatile memory with the 3D vertical resistive random access memory (VRRAM) has attracted great interest from the memory industry. However, VRRAM currently faces the challenges in selecting the specific cell due to a large number of leakage paths, and fabrication process difficulties. In order to eliminate the sneak path and reduce the power consumption, we have developed a novel selector, which shows nearly ideal selector performances with >107 on/off ratio, 0.2 V holding voltage, 10 pA off-state leakage current, sharp on-switch slope of 7 mV/dec, <10 ns turn on speed, >109 endurance, >1.6 MA/cm2 on current density. To investigate the VRRAM performance, we have developed a process flow to fabricate VRRAM and demonstrated a single level sidewall TaOx based VRRAM device. Beside the novel selector and VRRAM integration investigation, we have also proposed a transistor-based novel VRRAM (TB-RRAM) architecture.
(Invited) White-Light-Induced Annihilation of Percolation Paths in SiO2 and High-k Dielectrics - Prospect for Gate Oxide Reliability Rejuvenation and Optical-Enabled Functions in CMOS Integrated Circuits
Authors: Ang Diing Shenp , Kawashima Tomohito , Zhou Yu , Yew Kwang Sing , Bera Milan Kumar , Zhang Haizhong
Published: October 2015

The formation of nanoscale percolation paths or conducting filaments in oxide materials such as SiO2, HfO2, etc. presents both a challenge to gate oxide reliability as well as an opportunity to a next-generation resistive memory technology, as these materials have already been heavily deployed in mainstream integrated circuit manufacturing. In this paper, we present novel experimental evidence showing that electrical conduction through a nanoscale conducting filament can be disrupted upon illumination by white light. The disruption is either permanent or temporary, depending on the current which passed through the filament at the instant of its formation before the process was interrupted. The underlying mechanism is believed to involve photon-induced migration of neighboring interstitial oxygen ions, leading to their recombination with the vacancy sites which made up the conducting filament. This finding suggests possible exploitation for gate oxide reliability renewal and implementation of optical functions in SiO2 or HfO2 based devices whose functionality thus far is only limited to electrical excitation.
Three-Dimensional Fully-Coupled Electrical and Thermal Transport Model of Dynamic Switching in Oxide Memristors
Authors: Gao Xujiao , Mamaluy Denis , Mickel Patrick R , Marinella Matthew
Published: October 2015

We present a fully-coupled electrical and thermal transport model for oxide memristors that solves simultaneously the time-dependent continuity equations for all relevant carriers, together with the time-dependent heat equation including Joule heating sources. The model captures all the important processes that drive memristive switching and is applicable to simulate switching behavior in a wide range of oxide memristors. The model is applied to simulate the ON switching in a 3D filamentary TaOx memristor. Simulation results show that, for uniform vacancy density in the OFF state, vacancies fill in the conduction filament till saturation, and then fill out a gap formed in the Ta electrode during ON switching; furthermore, ON-switching time strongly depends on applied voltage and the ON-to-OFF current ratio is sensitive to the filament vacancy density in the OFF state.
(Invited) The Influence of Defects on the Electronic Properties of Hafnia
Authors: Islamov Damir R. , Gritsenko Vladimir A. , Perevalov Timofey V.
Published: October 2015

This study reviews the modern knowledge about the electronic properties of oxygen vacancies in the hafnia. Hafnia is a key dielectric for use in the modern electronics. Oxygen vacancies in the hafnia largely determine its electronic properties. It is shown that electronic transitions to states, localized on the oxygen vacancies, determine the optical properties. The oxygen vacancies act as traps in the charge transport via hafnia films. It is demonstrated that the hafnium oxide conductivity is limited by phonon assisted tunneling between traps that are the oxygen vacancies.
(Invited) The Assessment of Border Traps in High-Mobility Channel Materials
Authors: Simoen Eddy , Alian AliReza , Arimura Hiroaki , Lin D , Mertens Hans , Mitard Jerome , Sioncke Sonia , Fang Wen , Luo Jun , Zhao Chao , Mocuta Anda , Collaert Nadine , Thean Aaron , Claeys Cor
Published: October 2015

The assessment of border traps in the gate stack of so-called high-mobility material MOSFETs by low-frequency (1/f) noise spectroscopy is described. In a first part, the theoretical basis of the method is given, with special emphasis on the role of inelastic tunneling in the capture process. It is shown that depending on the energy barrier for capture, the real tunneling depth corresponding with a certain noise frequency f may be smaller compared with the elastic tunneling limit. In a second part, the border trap behavior in Ge n- and pMOSFETs with different gate stacks is discussed. Finally, the impact of the surface passivation and pre- and post Al2O3 deposition treatments on the 1/f noise of InGaAs-based nMOSFETs will be outlined.
Quantitative Characterization of Near-Interface Oxide Traps in 4H-SiC MOS Capacitors by Transient Capacitance Measurements
Authors: Fujino Yuki , Kita Koji
Published: October 2015

A method to characterize near-interface oxide trap density in SiC MOS capacitors using transient capacitance measurements was investigated, taking account of the distribution of de-trapping time of traps of various locations in oxide. The measurements at room and low temperatures enables us evaluate the responses of the raps of spatially deep and shallow locations, respectively. We found that the sample with low Dit
showed smaller density of near-interface traps especially in spatially shallow region in the oxide.
Tunneling Current Induced Frequency Dispersion in the C-V Behavior of Ultra-Thin Oxide MOS Capacitors
Authors: Yang Chang-Feng , Hwu Jenn-Gwo
Published: October 2015

Huge frequency dispersion appears in the capacitance-voltage (C-V) characteristic of metal-oxide-semiconductor capacitors (MOSCAPs) in depletion bias region especially when the oxide thickness is extremely small. The low frequency C-V curves have large capacitance value and behave as a peak at depletion bias. By using TCAD simulation, it was proven that the tunneling effect which is significant in thin oxide MOSCAPs plays an important role for the contribution of the frequency dispersion. The conventional theory of interface traps density is not the only cause of frequency dispersion. Consequently, extraction of interface traps density by the conventional high-low frequency method will introduce misleading error of interface property in ultra-thin oxide MOS devices.
Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region
Authors: Ahmed Imtiaz , Khosru Quazi D. M.
Published: October 2015

In this paper, we propose an analytical 2D model to calculate the potential in the channel for all types of double gate junctionless field effect transistors (DG JLFETs), which is valid in the subthreshold regime. Model is derived by solving 2D Poisson’s equation along the channel while assuming a cubic potential distribution across the silicon thickness. Threshold voltages of different structures are obtained from the proposed potential model. A comparison of subthreshold behavior i.e. threshold voltage roll-off (TVRO) and drain-induced barrier lowering (DIBL) has been made between symmetric and asymmetric DG JLFETs. The effect of bottom gate flat band voltage of asymmetric structures and bottom gate voltage of dissimilar gate biased structures on the threshold voltage are also investigated.
Non-Uniform Hole Current Induced Negative Capacitance Phenomenon Examined by Photo-Illumination in MOS(n)
Authors: Lin Huang-Hsuan , Lin Yen-Kai , Hwu Jenn-Gwo
Published: October 2015

The photo-induced negative capacitance (NC) phenomenon in MOS(n) is firstly observed and investigated by both experiments and simulations. The possible mechanism for NC phenomenon is proposed. It is shown that NC is resulted from non-uniform hole-electron recombination process due to lateral diffusion of photo-induced holes. The insufficiency of bulk holes for hole-electron recombination leads to voltage-current lag and NC behavior.
CMOS Compatible Growth of High Quality Ge, SiGe and SiGeSn for Photonic Device Applications
Authors: Alher Murtadha A. , Mosleh Aboozar , Cousar Larry , Dou Wei , Grant Perry , Ghetmiri Seyed Amir , Al-Kabi Sattar , Du Wei , Benamara Mourad , Li Baohua , Mortazavi Mansour , Yu Shui-Qing , Naseem Hameed A
Published: October 2015

Germanium films were deposited on silicon substrate by an ultra-high vacuum chemical vapor deposition system using GeH4 as Ge precursor and different carrier gases (Ar, N2 and H2). Silicon-germanium and SiGeSn films were deposited using optimized growth conditions of Ge growth. Silane and SnD4 were used as precursors for Si and Sn, respectively. A complete study of SiGe growth at chamber pressure from 0.1 to 1.0 torr and at temperatures from 350-450ºC for different SiH4 flow rate is performed. Silicon incorporation in Ge films varied from 1% to 17%. Tin incorporation of 2% was observed in the films with 17% Si incorporation. Investigation of film quality has been done using etch pit measurement, scanning electron microscopy and transmission electron microscopy. Threading dislocation density for Ge, SiGe and SiGeSn films were 1.7×107 cm-2, 2.3 ×107 cm-2 and 4.0 ×107 cm-2
, respectively.
Ultra-Low Temperature (~180°C) Solid-Phase Crystallization of GeSn on Insulator Triggered by Laser-Anneal Seeding
Authors: Matsumura Ryo , Moto Kenta , Kai Yuki , Sadoh Taizoh , Ikenoue Hiroshi , Miyao Masanobu
Published: October 2015

Solid-phase crystallization (SPC) of amorphous-GeSn (a-GeSn) films on insulating substrates has been developed combining with laser-anneal seeding, to realize next generation thin-film devices. By this technique, we have realized crystallization of GeSn (>10%) at low temperatures (~180oC), which is applicable to flexible thin-film devices on low cost plastic substrates with low softening temperatures (~200oC). In addition, the starting point of crystallization can be controlled by seeding, which is a big advantage in circuit designing.
Electrical Characterization of Dry and Wet Processed Interface Layer in Ge/High-K Devices
Authors: Ding YI Ming , Misra Durga , Bhuyian Mdnasiruddin , Tapily Kandabara , Clark Robert D. , Consiglio Steven , Wajda Cory S. , Leusink Gert J.
Published: October 2015

Even through Ge/high-k interface has been extensively studied, the high leakage current associated with these gate stacks and interface defects continue to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit
and equivalent oxide thickness (EOT). In this work, the dry and wet processed interface layers for three different p type Ge/High-K samples on 300 mm wafers were studied at different low temperatures by CV and GV measurement. Since low temperature measurements are more reliable several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are reported and interface quality is being discussed.
(Invited) Excellent Wetting Behavior of Yttria on 2D Materials
Authors: Addou Rafik , Batzill Matthias , Wallace Robert M
Published: October 2015

The integration of two-dimensional materials into nanoelectronic devices requires contact with high-κ dielectric. For better performance, it is indispensable to grow uniform and conformal dielectric materials. In this paper, we show the excellent wetting behavior of yttrium oxide (yttria, Y2O3) thin films on graphene using several interface and surface science techniques. The uniformity of the Y2O3 was characterized using scanning tunneling microscopy, atomic force microscopy, transmission electron microscopy, and low energy ion scattering. Photoemission was used to investigate the surface chemistry and the charge doping level of graphene by evaluating the C 1s core level. Furthermore, the favorable wetting behavior of yttria is exploited as an effective buffer layer for atomic layer deposition of Al2O3 on non-functionalized graphene surface.
(Invited) Is the Silicene a 2D Dirac Material?
Authors: Shirasawa Tetsuroh
Published: October 2015

Silicene, a 2D honeycomb layer of Si, has attracted much attention, since a Dirac fermion character like graphene was predicted. Furthermore the silicene has a 2D topological insulator due to the 1000 times stronger spin-orbit coupling than graphene. The hypothetical silicene is a free standing layer, but in practice, experimentally fabricated silicenes so far are 2D layers of silicon epitaxially grown on substrates. We will discuss, on the basis of the structure determination on an atomic scale by using quantitative LEED analysis, the nature of the epitaxial silicenes on Ag(111) surface; the influence of the silicene-substrate interaction for the single layer silicene and if the multi-layer silicene fabricated on the substrate has the features expected for the free-standing silicene.
(Invited) Initial State of Graphene Growth on Ge(001) Surfaces
Authors: Dabrowski J , Lippert G , Lupina G
Published: October 2015

Graphene electronics is most likely to complement the mainstream Si technologies instead of replacing them. Large area graphene that can be grown on Cu or on Ni must be subsequently transferred to Si, which is problematical. A process in which graphene grows directly on a Si wafer would thus be welcome; yet SiC formation makes this hardly realizable. Researchers search therefore for growth methods on CMOS-compatible substrates, as Ge/Si(001). We discuss the results of ab initio density functional theory (DFT) calculations for the interaction between carbon and germanium during deposition of C atoms (molecular beam epitaxy, MBE) and of small hydrocarbon molecules (chemical vapor deposition, CVD) on the Ge(001)-p(2×2) surface, during graphene nucleation that follows this deposition, and during the initial stage of graphene growth. The major difference between MBE and CVD process is that liberation of germanium from surface dimers by subsurface diffusion of carbon are suppressed in CVD.
(Invited) Vertical Field Effect Transistor Based on Graphene/Transition Metal Dichalcogenide Van Der Waals Heterostructure
Authors: Moriya Rai , Yamaguchi Takehiro , Inoue Yoshihisa , Sata Yohta , Morikawa Sei , Masubuchi Satoru , Machida Tomoki
Published: October 2015

We demonstrated exfoliated-graphene/transition metal dichalcogenide (TMD)/metal vertical field-effect transistor (vFET). The van der Waals junction between graphene and TMD exhibit Schottky barrier. Owing to the low density of state of graphene, the position of graphene’s Fermi level can be modulated by the external electric field, thus enable us electric field modulation of Schottky barrier height at graphene/TMD interface. Based on this mechanism, a vertical transport in the heterostructure exhibits large current modulation of >105, and at the same time the heterostructure reveal operation current density of ~104 A/cm2. These results reveal potential high performance of vFET for electronics applications.
(Invited) Electronic Properties of Self-Assembled Trimesic Acid Monolayer on Graphene Layers
Authors: Shayeganfar Farzaneh
Published: October 2015

The adsorption of trimesic acid (TMA) on graphene surface has been studied with density functional theory (DFT). By considering the adsorption of a single TMA molecule on different sites on graphene, we have been able to perform a detailed analysis of the equilibrium geometry, charge transfer, electronic properties in terms of density of states and band structure, and finally scanning tunnelling microscopy (STM) simulations on those simple systems. The results for isolated adsorption were then compared to the behaviour of TMA unit within two different self-assembled monolayers. Our results indicate that structural deformations of TMA may significantly contribute to the magnitude of p-doping and band gap opening in graphene.
Plasma Dicing: Current State & Future Trends
Authors: Westerman Russ , Grivna Gordon , Mackenzie Ken , Lazerand Thierry , Doub Jason
Published: October 2015

Die singulation by mechanical sawing has been the primary technology used in semiconductor device fabrication for decades. However, as device structures continue to evolve to meet increasing performance requirements, fundamental limitations of the sawing operation have been exposed. Obtaining reasonable dicing throughput and yield for die less than 100µm thick is a challenge for the sawing operation. One alternative to saw-based dicing is die singulation using plasma etching. This paper compares and contrasts plasma dicing on tape (PDOT) processes to conventional mechanical saw and laser processes. While saw- and laser-based processes are serial in nature, plasma dicing is a parallel process, which significantly increases equivalent cutting speeds, particularly for die that are less than 150µm thick. Along with higher die throughput, plasma dicing can deliver higher-quality die than alternative methods. Die singulated by plasma dicing have shown up to 9 times greater die strength than mechanically sawed die. Finally, the paper discusses issues and solutions related to PDOT process integration, including maintaining tape integrity, street definition / masking approaches, and downstream integration.
Miniaturization and Biocompatible Encapsulation for Implantable Biomedical Silicon Devices
Authors: Souriau Jean-Charles , Herrera Morales Jorge Mario , Castagné Laetitia , Simon Gilles , Amara Karima , Boutaud Bertrand
Published: October 2015

This paper presents a new strategy of packaging developed for medical applications which includes a sensor and an integrated circuit inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration. The electronic components are placed on a silicon interposer wafer which was bonded by AuSi solder with a silicon wafer lid containing cavities. Different metal stacks of the sealing ring including a barrier and Au have been studied. The gas content and hermeticity of the package were analyzed using Residual Gas Analysis (RGA) and biodegradation were tested in saline solution. The final silicon package was encapsulated with biocompatible materials that have high conformality deposition and act as good bi-directional barrier. Materials behavior that had been reported in literature as biocompatible and compatible with fabrication in standard clean rooms were studied. Finally, packaging materials were tested in cytotoxicity.
Optimizing TSV Fill Phases for Improved Fill Rate, Process Stability and Void Performance
Authors: Ghekiere John , Mikkola Robert , Kebreab Daniel , Burnham James , Hoerner Bridger , Erickson David
Published: October 2015

This paper will explore the differences between the theoretical optimal electrochemical polarization conditions within the via during the key phases of gap filling (e.g. nucleation, conformal filling, and the transition to bottom-up filling), and compare to the actual conditions of conventional processing. The gaps between the optimal and actual conditions identify opportunities for innovation to significantly reduce fill time, provide supreme stability of the bath and minimize overburden thickness. The paper describes several such innovations.
Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits
Authors: Obeng Yaw S. , Okoro Chukwudi A. , Ahn Jung-Joon , You Lin , Kopanski Joseph J.
Published: October 2015

The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.