bluuebunny/crossref_metadata_2025 huggingface dataset:
Effect of Temperature and Strain Rate on Low-Cycle Fatigue Life of Bi-Sn Eutectic Alloy
Authors: Sato Takuma , Kariya Yoshiharu , Fukui Kazuma
Published: January 2014

In this study, the effects of temperature and strain rate on low cycle fatigue life of Bi-Sn eutectic alloys have been studied. The fatigue life improves with the increasing of temperature and the decreasing of strain rate. This is a reverse phenomenon from characteristics found in general metals. As temperature increases and strain rate decreases, grin boundary sliding becomes the dominant deformation mechanism and the fatigue ductility coefficient increases, resulting in an improvement of fatigue life. To the extent of this study, dependence on temperature and strain rate can be expressed by Manson-Coffin’s law modified using Z-parameters.
Design of Cost-Effective Water-Cooled Pinfin Heatsinks
Authors: Horiuchi Keisuke , Nishihara Atsuo , Sugimura Kazuyuki
Published: January 2014

This paper presents the multi-objective optimization of cost-effective pinfin heatsinks. Heat transfer rate and pressure drop were the objective functions, and four parameters (height, diameter, longitudinal pitch, and transverse pitch) were the design variables. The relationship between the objective functions and the design variables for pinfin heatsink was calculated by using our own empirical equations using the aspect ratio and the minimum gap considering cost-effectiveness and manufacturability. Non-dominated solutions to the objective functions were illustrated, and we derived the design rules for design variables. We found the similarity of the optimum trade-off curves between the heat transfer rate and the pressure drop if the multiplication of the height and the minimum gap were the same for the different constraints. We validated our calculated solutions by comparing them with experimental results and attained reasonable agreement between the calculation and experiment.
Analytic Optimization of Cost Effective Thermoelectric Generation on Top of Rankine Cycle
Authors: Yazawa Kazuaki , Koh Yee Rui , Shakouri Ali
Published: January 2014

Thermoelectric (TE) generators have a potential advantage of the wide applicable temperature range by a proper selection of materials. In contrast, a steam turbine (ST) as a Rankine cycle thermodynamic generator is limited up to more or less 630 °C for the heat source. Unlike typical waste energy recovery systems, we propose a combined system placing a TE generator on top of a ST Rankine cycle generator. This system produces an additional power from the same energy source comparing to a stand-alone steam turbine system. Fuel efficiency is essential both for the economic efficiency and the ecological friendliness, especially for the global warming concern on the carbon dioxide (CO2) emission.

We report our study of the overall performance of the combined system with primarily focusing on the design parameters of thermoelectric generators. The steam temperature connecting two individual generators gives a trade-off in the system design. Too much lower the temperature reduces the ST performance and too much higher the temperature reduces the temperature difference across the TE generator hence reduces the TE performance. Based on the analytic modeling, the optimum steam temperature to be designed is found near at the maximum power design of TE generator. This optimum point changes depending on the hours-of-operation. It is because the energy conversion efficiency directly connects to the fuel consumption rate. As the result, physical upper-limit temperature of steam for ST appeared to provide the best fuel economy. We also investigated the impact of improving the figure-of-merit (ZT) of TE materials. As like generic TE engines, reduction of thermal conductivity is the most influential parameter for improvement. We also discuss the cost-performance. The combined system provides the payback per power output at the initial and also provides the significantly better energy economy [$/KWh].
Dynamic Analysis of Hybrid Cooling Data Centers Subjects to the Failure of CRAC Units
Authors: Gao Tianyi , Samadiani Emad , Schmidt Roger , Sammakia Bahgat
Published: January 2014

Thermal management of high power data centers poses challenges due to the high operational cost which is made worse due to the many inefficiencies that arise in them. Additional challenges arise due to the dynamic behaviors that occur during normal operation, and also during emergencies such as power outages or failure of some or all of the cooling equipment. Water and hybrid air plus water cooled data centers are an alternate cooling solution combining liquid cooling systems, such as rear door heat exchangers located within the racks themselves, in addition to the traditional raised floor cold aisle air cooling system. Such a solution may be used when some of the equipment in a data center is upgraded to higher end and higher power equipment which may not be manageable with the existing air cooling system. For a data center with a hybrid cooling system, the cold air supply and the cold water supply should increase in case of an emergency, such as a CRAC (Computer Room Air Conditioner) units’ failure. In this paper, a detailed computational study is conducted to investigate the dynamic response of the impact of a CRAC failure on both water side and air side in a representative hybrid cooling room. The room studied is an air cooled data center using the common cold aisle approach, with rear door heat exchangers installed on all of the racks. CRAC failure is investigated in a hybrid cooling room. The variation and fluctuation in an average rack inlet temperature, and inlet temperatures at different detail locations are presented in plots, showing the dynamic performance of a hybrid cooling data center subjected to the different CRAC failure scenarios. Different response time studies are also presented in this paper.
Computational Strategies to Minimize Transient Response During Time-Domain Analysis of Structures Under Vibratory Loading
Authors: Ernst Matthew , Choi Cholmin , Dasgupta Abhijit
Published: January 2014

Time-domain dynamic analysis of vibratory systems becomes useful in finite element analysis (FEA) when the structure’s response can no longer be assumed linear, as frequency-domain (spectral superposition) methods require. Time-domain analysis also permits the use of cycle-counting methods when assessing the vibration durability of electronic assemblies. The analyst is often limited to simulating only the first few cycles of the vibration response in very complex models, to minimize the computational burden. However, the accuracy of time domain analysis can be questionable during these first few cycles, due to unwanted transients, unless the initial conditions are properly modeled to correctly produce the steady state response. This paper explores this sensitivity to initial conditions for undamped and damped structures. Strategies for calculating and implementing proper initial conditions within FEA are discussed. Two illustrative examples are presented for simplicity. The first consists of a simple cantilever beam so that the numerical results can be compared to known analytic solutions and the basic theory can be demonstrated. The second example is a 2D representation of a circuit card assembly containing multiple leadless chip resistor components, so that implementation details can be demonstrated for more complex structures. This paper is intended to have tutorial value to FEA users who have to conduct time-domain dynamic analysis.
A Hierarchical Framework for Thermal Modelling of Electronic Devices: From Atoms to Chips
Authors: Romero David A. , Pakseresht Elham , Sellan Daniel , Nabovati Aydin , Amon Cristina
Published: January 2014

In this work, we provide an overview of a hierarchical computational framework to predict thermal transport in electronic devices through integration of physics-based models at different length scales. Information from atomistic simulations at the smallest length scales are transferred to upper levels of the hierarchy, up to thermal models for the chip. The proposed methodology includes five levels of length scales in electronic devices, namely (i) atomistic level, (ii) thin film and nanowire level, (iii) transistor and logic gate level, (iv) functional block level, and (v) chip level. At the first level of the hierarchy, properties of energy carriers in a semiconductor material (e.g., phonons) are obtained from atomistic level simulations, such as Molecular Dynamics (MD) and Lattice Dynamics (LD) calculations. At the second level, thermal transport in thin silicon films is modelled using a Lattice Boltzmann Method (LBM) for phonons. The outcome of these simulations is a size-dependent thermal conductivity for silicon films. At the third level of the hierarchy, these effective thermal conductivities are used in thermal modelling of logic gates. Detailed structures of different types of logic gates are reconstructed based on different manufacturing technologies (MOSFET and FinFET) at different technology nodes. Since the characteristic sizes of different parts of the logic gates are comparable to the mean free path of energy carriers, we use the size-dependent, effective thermal conductivities that were calculated at lower levels of the hierarchy to build simulation models for the logic gates. Based on these models, we calculate an equivalent thermal conductance for the logic gates, which would then be used in the upper level simulations to determine an equivalent thermal conductance for different functional blocks of the die based on their internal structure and the number and type of logic gates found in each functional block. Overall, the proposed hierarchical model enables us to include the effect of atomistic-level physics into package-level simulations, and thus, have an accurate prediction of thermal transport in an electronic device.
Experimental Investigation of the Effect of Synthetic Jets in Minichannels With Subcooled Boiling Flow
Authors: Sykes David M. , Carpenter Andrew L. , Cole Gregory S.
Published: January 2014

Microchannels and minichannels have been shown to have many potential applications for cooling high-heat-flux electronics over the past 3 decades. Synthetic jets can enhance minichannel performance by adding net momentum flux into a stream without adding mass flux. These jets are produced because of different flow patterns that emerge during the induction and expulsion stroke of a diaphragm, and when incorporated into minichannels can disrupt boundary layers and impinge on the far wall, leading to high heat transfer coefficients. Many researchers have examined the effects of synthetic jets in microchannels and minichannels with single-phase flows. The use of synthetic jets has been shown to augment local heat transfer coefficients by 2–3 times the value of steady flow conditions. In this investigation, local heat transfer coefficients and pressure loss in various operating regimes were experimentally measured. Experiments were conducted with a minichannel array containing embedded thermocouples to directly measure local wall temperatures. The experimental range extends from transitional to turbulent flows. Local wall temperature measurements indicate that increases of heat transfer coefficient of over 20% can occur directly below the synthetic jet with low exit qualities. In this study, the heat transfer augmentation by using synthetic jets was dictated by the momentum ratio of the synthetic jet to the bulk fluid flow. As local quality was increased, the heat transfer augmentation dropped from 23% to 10%. Surface tension variations had a large effect on the Nusselt number, while variations in inertial forces had a small effect on Nusselt number in this operating region.
TIM Selection for an IGBT Cold Plate Using Experimental and Numerical Modeling
Authors: Maddox John F. , Knight Roy W. , Bhavnani Sushil H.
Published: January 2014

Experimental measurements were used in conjunction with a numerical model to perform an in situ analysis of an IGBT cooling solution with a cold plate utilizing an 85–90°C ethylene glycol-water mixture as the cooling fluid. This process was used to aid in the selection of an appropriate thermal interface material (TIM) for the application. The effects of elevated temperature and thermal cycling on the performance of the TIM were investigated during the selection procedure. Applying the thermal grease with the cold plate at 70°C rather than 30°C caused a reduction in the junction to case resistance of 74% and 78% for the two thermal greases tested.
Open and Contained Cold Aisle Experimentally Validated CFD Model Implementing CRAC and Server Fan Curves for a Data Center Test Laboratory
Authors: Alkharabsheh Sami A. , Muralidharan Bharathkrishnan , Ibrahim Mahmoud , Shrivastava Saurabh K. , Sammakia Bahgat G.
Published: January 2014

This paper presents the results of an experimentally validated Computational Fluid Dynamics (CFD) model for a data center with fully implemented fan curves on both the servers and the Computer Room Air Conditioner (CRAC). Open and contained cold aisle systems are considered experimentally and numerically. This work is divided into open (uncontained) cold aisle system calibration and validation, and fully contained cold aisle system calibration and leakage characterization.

In the open system, the CRAC unit is calibrated using the manufacturer fan curve. Tiles flow measurements are used to calibrate the floor leakage. The fan curves of the load banks are generated experimentally. A full physics based model of the system is validated with two different CRAC fan speeds. The results showed a very good agreement with the tile flow measurements, with an approximate average error of 5%, indicating that the average model prediction of the tile flow is five percent lower that the measured values.

In the fully contained cold aisle system, a detailed containment CFD model based on experimental measurements is developed. The model is validated by comparing the flow rate through the perforated floor tiles with the experimental measurements. The CFD results are in a good agreement with the experimental data. The average error is about 6.7%. Temperature measurements are used to calibrate other sources of containment and racks leaks including mounting rails and clearance between racks. The temperature measurements and the CFD results agree well with average error less than 2%.

Detailed and equivalent modeling methods for the floor and containment system are investigated. It is found that the simple equivalent models are able to predict the flow rates however they did not succeed in providing detailed fluid flow information. While the detailed models succeeded in explaining the physical phenomena and predicting the flow rates with noticeable tradeoffs regarding the computational time.

Important conclusions can be drawn from this study. In order to accurately model the containment system, both the CRAC and the load banks fan curves should be simulated in the numerical model. Unavoidable racks and containment leaks could cause inlet temperature increase even if the cold aisle is overprovisioned with cold air. It is also noted that heat conduction through the floor tiles causes a slight increase the inlet temperature of the cold aisles. Finally, it is noteworthy that using detailed modeling is necessary to understand the details of the thermal systems, however simpler and faster to compute equivalent models can be used in extended optimization studies that show relative rankings of different designs.
A Numerical Steady State and Dynamic Study in a Data Center Using Calibrated Fan Curves for CRACs and Servers
Authors: Alkharabsheh Sami A. , Sammakia Bahgat , Shrivastava Saurabh , Ellsworth Michael , David Milnes , Schmidt Roger
Published: January 2014

This study presents the results of a detailed parametric study for a data center that is air cooled using a set of four CRAC units in a cold/hot aisle raised floor configuration. The fans of the CRAC units and the servers are calibrated using their practical characteristics fan curves. A commercial CFD code is utilized for this purpose in which the buoyancy forces are taken into account. The k-epsilon model and the Boussinesq approximation are used to model the turbulent airflow and the buoyancy effect, respectively. A dynamic model is developed to take into account the changes in flow rates and power dissipation in the data center environment. The current dynamic model does not take into account the thermal mass of the CRAC units or the servers. The effect of the CRAC fan speed, instantaneous change in power dissipation, tiles perforation ratio, and servers fan speeds on the total flow rate in the room and the inlet temperatures of the racks are investigated. In the transient model, we investigate the effect of different CRAC failure scenarios on the time history of the temperatures and the flow pattern in the data center. Time constants and safe time are estimated from this study. A fundamental understanding of the effect of different data center entities on the flow and the temperatures is developed. Interesting flow patterns are observed in the case of different CRAC failures that could be used to recommend general design guidelines.
Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors
Authors: Cunningham Shawn J. , Heng Yvonne , Idrisi Nabeel , Nelson Brad , McKillop John
Published: January 2014

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place.

In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability.

In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.
Enhancement of the Power-Conversion Efficiency for Thermoelectric Generators
Authors: Zhou Siyi , Sammakia Bahgat G. , White Bruce , Borgesen Peter , Chen Cheng
Published: January 2014

Constrained by low thermodynamic efficiencies, thermoelectric generators (TEGs) require a comparatively large amount of heat to produce a given quantity of electricity. Therefore, further improvements in thermoelectric designs are needed. In this paper, a coupled-field thermoelectric model, which presents a rigorous interfacial energy balance by capturing Joule heating, Seebeck, Peltier and Thomson effects, is developed to gauge the feasibility of the two promising solutions to enhance power generated by the TEGs, utilizing the commercial FEA package COMSOL™ through the Physics Interface Builder. First, the patterned topography on wall surfaces is implemented and the improved performance has been observed by introducing stirred flows into the heat exchangers and equalizing the temperature across the channels. Referring to the analysis, approximately 10% enhancement in power generation can be addressed for the base-relief TEG. Second, the prospect of increasing the thermal transport capability of water by loading CuO nanoparticles in the TEGs with multi-scale heat exchangers is explored. It is found that the conversion performance of the water/CuO nanofluid-based TEG is superior when compared to the water-based TEG at the micro-scale, where the flow rate is relatively low. The significant insight is gained to fabricate the ideal TEGs with optimum power performance.
Effect of TSV Joule Heating on Device Performance
Authors: Mirza Fahad , Naware Gaurang , Raman Thiagarajan , Jain Ankur , Agonafer Dereje
Published: January 2014

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs.

TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.
The Influence of Uniaxial Normal Stress on the Performance of Vertical Bipolar Transistors
Authors: Hussain Safina , Gnanachchelvi Parameshwaran , Suhling Jeffrey C. , Jaeger Richard C. , Hamilton Michael C. , Wilamowski Bogdan M.
Published: January 2014

In this paper, we have explored the response of bipolar junction transistors (BJT) to the controlled application of mechanical stress. Mechanical strains and stresses are developed during the fabrication, assembly and packaging of the integrated circuit (IC) chips. Due to these stresses and strains, it has been observed by many researchers that changes can occur in the electrical performance of both analog and digital devices. Stress-induced device parametric shifts affect the performance of analog circuits that depend upon precise matching of bipolar and/or MOS devices, and can cause them to operate out of specifications. In the past the authors have extensively investigated the stress effects on resistors embedded on integrated chips and were successful in characterizing die stresses for various packaging architectures. We have also observed stress effects on diodes, field effect transistors (FETs), van der Pauw structures and CMOS sensor arrays. In this present work, the stress dependence of the electrical behavior of bipolar transistors has been investigated. Test structures have been utilized to characterize the stress sensitivity of vertical bipolar devices fabricated on (100) silicon wafers. In the experiments, uniaxial normal stresses were applied to silicon wafer strips using a four-point-bending fixture. An approximate theory has also been developed for stress-induced changes in the current gain of bipolar junction transistors. Both the theoretical and experimental results show similar trend for DC current gain vs. stress plots. Multi-Physics based finite element simulations (coupled electro-mechanical-thermal) have been performed to understand the device level mechanisms that cause the stress induced changes in the BJTs and also to characterize and model stress dependence of fundamental silicon material parameters such as bandgap, intrinsic carrier concentration, and electron/hole mobilities. In the future, the developed formulations can be applied to theoretically optimize transistor design, placement, orientation, and processing to minimize the impact of fabrication and packaging induced die stresses.
On the Thermal Management Challenges in Next Generation Handheld Devices
Authors: Wagner Guy R. , Maltz William
Published: January 2014

Handheld devices are increasingly capable of running applications that used to require laptop and desktop computers. The requirement that these devices provide better performance with a smaller form factor or size presents significant challenges, especially with the limitations of passive cooling.

The current study presents a summary of the cooling solutions of several popular, commercially available tablets. The trends in power dissipation and thermal management techniques of handheld devices are presented.

The factors affecting the maximum possible power dissipation are discussed. The effects of the selection of the outer shell materials, the thermal interface materials, heat spreaders and air gaps are presented.

For all considered thermal management techniques of handheld devices, a figure of merit for the cooling solutions is defined as: Figure of Merit = Maximum Power Dissipation / Surface Temperature Rise, in (W/degC). This figure of merit allows for an objective comparison of the available cooling solutions.
Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly
Authors: Roberts Jordan C. , Motalab Mohammad , Hussain Safina , Suhling Jeffrey C. , Jaeger Richard C. , Lall Pradeep
Published: January 2014

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings.

Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.
Four-Wire Bridge Measurements of van der Pauw Stress Sensors on (100) and (111) Silicon
Authors: Jaeger Richard C. , Motalab Mohammad , Hussain Safina , Suhling Jeffrey C.
Published: January 2014

Four-wire resistance characterization of van der Pauw stress sensors is discussed. Under the proper orientations and excitations, the output of the four-contact sensors can be shown to depend upon only the in-plane shear stress or the in-plane normal stress difference on (100) silicon. The other stress terms are cancelled out by the symmetry of the structure, and the measurements are inherently temperature compensated. In bridge-mode, each sensor requires only one measurement and produces an output voltage that is directly proportional to the shear stress or in-plane normal stress difference, and the sensitivity is 3.16 times that of the equivalent resistor sensors, just as in the normal van der Pauw mode. Experimental, theoretical, finite-difference and finite-element and simulation results are presented demonstrating the behavior of the sensor. The two sensors can be merged into one eight-contact device, or n- and p-tye sensors can be overlaid in standard IC processes. Similar results apply to sensors on (111) silicon.
Damage Pre-Cursors Based Prognostication of Accrued Damage and Assessment of Operational Readiness of Leadfree Electronics
Authors: Lall Pradeep , Harsha Mahendra , Suhling Jeff , Goebel Kai
Published: January 2014

Electronics in high reliability applications may be stored for extended periods of time prior to deployment. Prior studies have shown the elastic modulus and ultimate tensile strength of the SAC leadfree alloys reduces under prolonged exposure to high temperatures [Zhang 2009]. The thermal cycle magnitudes may vary over the lifetime of the product. Long-life systems may be re-deployed several times over the use life of the product. Previously, the authors have identified damage pre-cursors for correlation of the damage progression with the microstructural evolution of damage in second level interconnects [Lall 2004a-d, 2005a-b, 2006a-f, 2007a-e, 2008a-f, 2009a-d, 2010a-j]. Leadfree assemblies with Sn3Ag0.5Cu solder have been subjected to variety of thermal aging conditions including 60°C, 85°C and 125°C for periods of time between 1-week and 2-months, thermal cycling from −55°C to 125°C, −40°C to 95°C and 3°C to 100°C. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify accrued damage in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. Damage equivalency relationships have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. Accrued damage between different thermal cyclic magnitudes has also been mapped for from −55°C to 125°C, −40°C to 95°C and 3°C to 100°C thermal cycles. The presented method for interrogation of the accrued damage for the field deployed electronics, significantly prior to failure, may allow insight into the damage initiation and progression of the deployed system. The expected error with interrogation of system state and assessment of residual life has been quantified.
Strain Transfer Analysis of Integrated Surface Acoustic Wave Sensors
Authors: Hempel Jochen , Zukowski Elena , Berndt Michael , Anees Sohaib , Wilde Jürgen , Reindl Leonhard M.
Published: January 2014

This paper presents a strain transfer investigation for Surface Acoustic Wave (SAW) strain sensors. For evaluation, a SAW strain sensor is assembled with a pre-tested bond material for potentially high strain transfer on a test holder. The setup is stressed with an axially homogeneous strain up to 500 ppm. The strain transfer ratio is computed from the applied load, the reference measurements with foil strain gauge, and the measured SAW strain sensor signal. The strain transfer performance of the bond material is also investigated with respect to the temperature dependency in the range between 22 °C and 85 °C. At this elevated temperatures an average strain transfer ratio of 0.606 ± 0.7% was measured. Mechanical load cycling tests up to 1000 cycles are used for the evaluation of the elastic fatigue of the bond material. The effects of mechanical load cycling and aging of the bond layer are analyzed with the SAW strain sensor response. After 1000 mechanical load cycles the transferred strain into the SAW strain sensor is 0.582 ± 0.153%. Finally, the experimental results are compared with the results of a 3D FEM simulation which are deviating less than 10%.
3D Stacks of Microprocessors and Memories With Backside Two-Phase Multi-Microchannel Cooler
Authors: Marcinichen Jackson B. , Thome John R.
Published: January 2014

For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.
Cooling of a Many-Core Multiprocessor: Experimental Results for OLTP Workloads
Authors: Sreenivasan Krishnamachar
Published: January 2014

Stochastic heat conduction differential equation in spite of its complexity allows stationary solutions valid over a certain range of variables characterizing heat flow in multi-processor cores. Heat conduction equation is recast to account for anisotropy of a many core multi-processor in which heat generated at various locations depends on whether it is a cache, processor, bus controller, or memory controller: within the core generated heat depends on the hit rate, processor utilization, cache organization, and the technology used. Thermal conductivity of and heat generation in the core are treated as stochastic variables and influence of workloads, hitherto unrecognized, is explicitly accounted for in determining temperature distribution and its variation with processor clock frequency. Relationships derived from first principles indicate that rise in temperature with processor frequency for OLTP workload is not as catastrophic as predicted by some Industry brochures! A general framework for heat conduction in an orthotropic rectangular slab (representing a many core processor) with stochastic values of thermal conductivity and heat generation is developed; the theoretical trend is validated using published data for OLTP workloads to obtain temperature at the core surface as a function of clock frequency for the deterministic case. Transaction Processing Councils (TPC) openly available data from controlled, closely audited experiments for TPCC workloads during the period 2000–2011 were analyzed to determine the relation between throughput, clock frequency, main memory size, number of cores, and power consumed. Operating systems, compilers, linkers, processor architecture, cache, main memory, and storage sizes have changed drastically during this ten year period, not to mention hyper-threading was unknown in 2000! This analysis yields the following equations for throughput and power consumed, which for a specific case of 64 processors with a main memory of 32 GB and a million users, becomes W = 1075f0.22. For the isotropic case the temperature difference at the surface may be expressed for the case under study as ΔT = 71.1f0.22. This demonstrates that chip temperature for OLTP workloads does not increase to catastrophic values with increase in frequency. This behavior varies for other types of workloads.
Assessment of the Energy Performance of Cogeneration Systems for Powering and Cooling Data Centers
Authors: Ringham Dale C. , Rice Dan J. , Granetz Brian S. , Erden Hamza Salih , Khalifa H. Ezzat , Schmidt Roger R.
Published: January 2014

The Syracuse/IBM Green Data Center utilizes micro turbines in combination with exhaust fired heat exchangers and absorption chillers to produce electrical power, cooling and heating for the data center and surrounding infrastructure. The overall efficiency of cogeneration systems depend greatly on the utilization of turbine exhaust heat. This makes a data center (where cooling load and electrical power requirements are closely correlated) an excellent candidate for cogeneration technology. Over 200 data points collected in the data center allow for in-depth energy analysis of this unique data center and the surrounding infrastructure. This paper provides information on the Syracuse/IBM Green Data Center systems as well as analysis of the data center over all four seasons. In addition to PUE, the common data center metric, a new metric defined as ERE1 is used to measure data center efficiency when energy is exported to the surrounding infrastructure.
Integration of Point Field Detectors Within Power Electronic Packages to Achieve Multifunctional Sensing
Authors: Hoffman J. D. , Dow B. A. , Lorenz R. D.
Published: January 2014

The spatially varying magnetic field within a power electronics package contains information of the semiconductor junction temperature and the interconnect currents, temperature, displacement, and strain. The design of semiconductor interconnects for point field detector based high bandwidth current and strain sensing is investigated using finite element analysis (FEA) and verified by experimental results. High bandwidth (10MHz) current sensing was achieved by interconnect design based field shaping and concentration. A displacement sensing resolution of 0.6 μm was achieved by eddy current based high frequency field shaping. Design methodologies to achieve this multifunctional integration of sensing are the primary new contribution of this work.
Estimation of Heat Generation From Power Si MOSFET Using Electro-Thermal Analysis
Authors: Kibushi Risako , Hatakeyama Tomoyuki , Ishizuka Masaru
Published: January 2014

This paper describes thermal properties of power Si MOSFET. The problem of hot spot in sub-micron scale Si MOSFET has been widely known. Recently, power Si MOSFET is a key device in a lot of area, for example car electronics. In power Si MOSFET, high voltage is applied and high current is generated. Therefore, heat generation becomes higher and thermal management is important. In this paper, thermal properties of power Si MOSFET is evaluated with Electro-Thermal Analysis and impurity dependency of temperature of power Si MOSFET is discussed. Under high electric field, electron thermal energy becomes much higher than thermal energy of crystal lattice. Therefore, in this paper, non-equilibrium energy state between electron and lattice is considered. Calculated results showed that hot spot appears in power Si MOSFET. Further, it is investigated that the impact of donor density on hot spot temperature is strong.
Thermal Management of Ultra Intense Hot Spots With Two-Phase Multi-Microchannels and Embedded Thermoelectric Cooling
Authors: Marcinichen Jackson B. , d’Entremont Brian P. , Thome John R. , Bulman Gary , Lewis Jay , Venkatasubramanian Rama
Published: January 2014

This study concerns cooling of electronic components of intense background heat flux with one ultra intense hot spot (e.g. 1000 Wcm−2 on a footprint of 1 cm × 1 cm with 5000 Wcm−2 applied to a 0.02 cm × 0.02 cm region at the center). To manage these extreme heat fluxes and consequently surpass the thermal-hydrodynamic challenges and design paradigms, for example as specified in a recent DARPA request for proposals (Intrachip/Interchip Enhanced Cooling Fundamentals - ICECool Fundamentals [1]), on-chip two-phase multi-microchannel cooling integrated with a superlattice (SL) thin-film thermoeletric cooling (TEC) technology was investigated via computer simulations.

The simulations showed that increasing TEC electrical current results in greater enhancement of heat flow through the TEC, but at high currents this benefit is offset by a net addition of heat to the system, which must also be evacuated by the microchannels. When optimized, a minimum peak junction temperature of about 86 °C for a current of about 8 A was found, which represented a reduction of about 4 °C from a maximum allowed 90 °C at the ultra-intense hot-spot, thus potentially significantly capable of exceeding the DARPA [1] requirement, due to the embedded SL TEC within the microevaporator (ME) structure.
Examination of Solder Interconnects Formed on ENEPIG Finished Printed Wiring Boards Under Drop Loading Conditions
Authors: Pearl Adam , Osterman Michael
Published: January 2014

Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), which has been used in component packaging, has been gaining attention as a surface finish for printed wiring boards. The primary role of a printed wiring board surface finish is to provide a solderable surface for assembly, creating a reliable solder interconnect. With regards to reliability, the increased use of mobile electronics has resulted in the need to consider the ability of interconnects to withstand repeated mechanical shocks. This paper examines the drop reliability of both SnPb and SAC305 interconnects formed on ENEPIG finished printed wiring boards. For comparison, the drop reliability test results for similar boards with Immersion Silver (ImAg) board finish are included. Test boards include BGA and resistor packages. The boards are dropped 500 times to achieve failure across the components. Failure analysis revealed that the dominant failure mode for BGA packages on the ENEPIG finish was cracking in the solder balls at the component interface, while for the ImAg finish the dominant failure mode was cratering in the board laminate below the solder pad. For the resistor packages, cracking through the solder joint at the component interface was the dominant failure mode for both the ENEPIG and ImAg finishes. The drop results indicate that both finishes are suitable for systems that could experience mechanical shock due to drop, with components soldered onto ENEPIG with a SAC 305 solder having the highest survivability. The combination of SnPb and ImAg was found to be superior to SAC 305 and ImAg.
A Fracture Mechanics Based Parametric Study of the Copper-to-Copper Direct Thermo-Compression Bonded Interface Using Finite Element Method
Authors: Park Ah-Young , Chaparala Satish , Park Seungbae
Published: January 2014

Through-silicon via (TSV) technology is expected to overcome the limitations of I/O density and helps in enhancing system performance of conventional flip chip packages. One of the challenges for producing reliable TSV packages is the stacking and joining of thin wafers or dies. In the case of the conventional solder interconnections, many reliability issues arise at the interface between solder and copper bump. As an alternative solution, Cu-Cu direct thermo-compression bonding (CuDB) is a possible option to enable three-dimension (3D) package integration. CuDB has several advantages over the solder based micro bump joining, such as reduction in soldering process steps, enabling higher interconnect density, enhanced thermal conductivity and decreased concerns about intermetallic compounds (IMC) formation. Critical issue of CuDB is bonding interface condition. After the bonding process, Cu-Cu direct bonding interface is obtained. However, several researchers have reported small voids at the bonded interface. These defects can act as an initial crack which may lead to eventual fracture of the interface. The fracture could happen due to the thermal expansion coefficient (CTE) mismatch between the substrate and the chip during the postbonding process, board level reflow or thermal cycling with large temperature changes. In this study, a quantitative assessment of the energy release rate has been made at the CuDB interface during temperature change finite element method (FEM). A parametric study is conducted to analyze the impact of the initial crack location and the material properties of surrounding materials. Finally, design recommendations are provided to minimize the probability of interfacial delamination in CuDB.
Leading Indicators for Prognostication of Impending Failures on Cu-Al Interconnects
Authors: Lall Pradeep , Deshpande Shantanu
Published: January 2014

Wire bonding is predominant mode of interconnect in electronics packaging. Traditionally material used for wire bonding is gold. But industry is slowly replacing gold wire bond by copper-aluminum wire bond because of the lower cost and better mechanical properties than gold, such as high strength, high thermal conductivity etc. Numerous studies have been done to analyze failure mechanism of Cu-Al wire bonds. Cu-Al interface is a predominant location for failure of the wirebond interconnects. In this paper, the use of intermetallic thickness as leading indicator-of-failure for prognostication of remaining useful life for Cu-Al wire bond interconnects has been studied. For analysis, 32 pin chip scale packages were used. Packages were aged isothermally at 200°C and 250°C for 10 days. Packages were withdrawn periodically after 24 hours and its IMC thickness was measured using SEM. The parts have been prognosticated for accrued damage and remaining useful life in current or anticipated future deployment environment. The presented methodology uses evolution of the IMC thickness in conjunction with the Levenberg-Marquardt Algorithm to identify accrued damage in wire bond subjected to thermal aging. The proposed method can be used for equivalency of damage accrued in Cu-Al parts subjected to multiple thermal aging environments.