bluuebunny/crossref_metadata_2025 huggingface dataset:
The Representations of the Poincaré Group in the Framework of Free Quantum Fields
Authors: Łopuszański Jan T.
Published: July 2007

This review article arose while the author tried to get acquainted with the recent developments in the domain of the representations of the Poincaré group in the quantum field theory. Special emphasis was put in this article on the case of massless free fields. Some ideas concerning general restrictions imposed upon the spinorial fields in order to get irreducible representations seem to be new and original.
Extended Objects in Field Theory with Non‐Abelian Group Symmetry
Authors: Matsumoto H. , Umezawa H. , Umezawa M.
Published: July 2007

This paper presents a general formalism for the description of topological objects created in quantum field systems with non‐Abelian symmetries. This formalism utilizes relations of differential form and therefore is suitable for the description of the local properties of the topological structure. The presentation of the general considerations is followed by several examples.

Even when there is no gauge field, the analysis requires use of a gauge transformation matrix. This coincides with the usual gauge transformation matrix when a gauge field is introduced.
New standards for old
Authors: Beasley Keith
Published: July 2007

The purpose of this paper is to highlight the current changes in the world of standards for electronic components. These changes relate to the whole attitude and approach to standards and the attainment of product that has appropriate levels of quality and reliability. Standards being developed within the European electronic components standards organization (CECC) represent the best industrial practices and are thus, unlike many earlier standards, flexible and user friendly.

European initiatives in the field of reliability emphasize the new approach to component approval and reliability. Through its CECC/WG‐

See Appendix I for explanations of the abbreviations used in this paper.

Reliability and the TIG‐ICs Reliability, the European Community is doing much to highlight harmonization and communication as key aspects in obtaining reliable product in the era of 1992.
The role of quality engineering in the 1990s
Authors: Jones David R.
Published: July 2007

The business environment of the 1990s will be affected in a major way by two major catalysts for change: one driven by technology and one driven by organizational change. This paper reviews the impact of major catalysts for change expected in the 1990s. Organizational change strategies will enable a corporation to be able accurately to assess the performance and success of each engineering group in the design, manufacturing, and customer installation and life cycle support. The strategies for the development of the methods and tools and long‐term career development strategies to support the ability of the organization to catalyse change are also discussed, with the conclusion that the quality engineering profession, correctly structured and empowered, will be the driver of the successful implementation of organizational change strategies in the 1990s.
Applying a physics‐of‐failure model to predicting surface mount solder joint reliability
Authors: Helling D. E. , Wong Boon
Published: July 2007

To address the wide variety of solder joint configurations, the authors have developed and applied a physics‐of‐failure model to predicting the service life of solder joints under thermal cycling conditions. The wide variety of solder joint geometries, materials and environments makes it impractical to develop and apply empirical models to predicting the service life of solder joint interconnects. On the other hand, a physics‐of‐failure model that describes the failure mechanisms in solder joints can be applied to a wide range of conditions. The physics‐of‐failure model framework is described and a model is demonstrated for predicting the failure of a leadless surface mount solder joint under slow thermal cycling conditions.
Product certification and standards for testing
Authors: Loll Valter
Published: July 2007

This note is a short tutorial overview on the standardization activities of interest for testing, together with an overview on the role of testing in the European open market. Activities and problems are listed and discussed. A number of reliability and test standards are listed.
Taguchi methods in practice: An analysis of Goh's paradox
Authors: Goh T. N.
Published: July 2007

The background of ‘Goh's paradox’ in connection with the application of the common version of Genichi Taguchi's parameter design routine is examined. A detailed case study is used to show how the paradox can be resolved, as well as to assess the probability of success of marginal analysis in Taguchi's prescribed procedure for quality and reliability improvement.
Control charts for processes subject to random shocks
Authors: Xie W. , Xie M. , Goh T. N.
Published: July 2007

In this paper, a charting technique for controlling processes subject to random shocks is presented. This type of process is common in a high‐yield production environment and the conventional Shewhart control charts are not efficient for its monitoring and control. This technique is able to detect process improvement, easy for decision making, and more concise and informative than other methods used for this type of process. In addition, it could provide diagnostic information which is highly useful in practice.
A data‐driven execution control scheme and its experimental study
Authors: Nishikawa Hiroaki , Asada Katsuhiko , Terada Hiroaki
Published: July 2007

The authors have proposed a high‐level parallel processing system representing the data‐drive principle (including history‐sensitive processing by diagrammatical language) and have been investigating its realization. Realization of high‐level processing by the data‐driven principle requires a load and function distribution scheme to secure the smooth data flow corresponding to the input stream into the system. Together with the results of experiment, this paper describes a systematic control scheme for load and function distribution of the data‐driven execution function through the construction of clusters adapted to the hierarchical diagrammatical program structure. In other words, the proposed system realizes the data‐driven execution functions of the hierarchical system by an iterative structure composed of fundamental functions, namely input‐output, function processing, history‐sensitive processing and firing control. This paper first describes the load and function distribution scheme for the fundamental function in the data‐driven execution control. Then, using an experimental system with common‐bus multiprocessor structure, it is shown that the proposed system is useful in realizing high‐level parallel processing. Lastly, based on the geometrical connection structure of the diagrammatical program, a semiquantitative guideline is presented for the distributed assignment of fundamental functions in the hierarchical cluster structure.
Effects of data sampling rate on image quality in fan‐beam CT system
Authors: Iwata Aklra , Yamagishi Nobutoshi , Suzumura Nobuo , Horiba Isao
Published: July 2007

The X‐ray computed tomography system has found widespread use worldwide in recent years. It is still requested that the system should provide further diagnostic information by providing CT images with higher quality. For this purpose, it is necessary to improve the high‐contrast spatial resolution and the low‐contrast density resolution. It is necessary also to establish a reduction method for various kinds of artifacts which are major causes of image deterioration. This paper examines quantitatively the spatial resolution and artifact, among various factors determining the CT image quality, and discusses their relation to the measured data sampling rate using computer simulation. As a result, it is shown that when other reconstruction parameters are kept constant in the fan‐beam CT system, the spatial resolution is determined largely by the projection data sampling interval rather than the angle sampling interval. The mechanism of artifact generation due to an insufficient angle sampling interval is examined. It is shown that to suppress this kind of artifact below a certain value, a certain condition must be satisfied by the measurement area, angle sampling interval, and projection data sampling interval. It is shown also that the artifact due to the projection sampling interval is proportional to the spatial frequency components of the object above the Nyquist frequency of the projection data.
Texture analysis based on the markov random
Authors: Model Field , Kaneko Hiroshi , Yodogawa Eiji
Published: July 2007

A recent tendency in the study of texture is the analysis based on mathematical models rather than the analysis of intuitively clear geometrical features. This type of study is advantageous in that a systematic and theoretical viewpoint can be provided to various kinds of related texture image processings. This paper considers the Gaussian‐Markov random field as a mathematical model for the texture image, and applications of the theory are discussed for texture classification and boundary extraction of texture regions. The determination of parameters for the Markov model is discussed first. Then the distance between textures is defined using the model parameters and a method of texture classification is proposed. The extraction of the boundary between texture regions is formulated as a testing of the parameters of the Markov model, and a method of texture region partition is proposed using the statistical testing variable as the discrimination function for the texture boundary. A classification experiment was performed for texture images with 13 categories, each containing 23 patterns. A 100% rate of classification was obtained, indicating the effectiveness of the proposed classification method. The region partition experiment was performed for the patched texture image. The result of partition was satisfactory, indicating the effectiveness of the proposed boundary extraction method.
Speaker‐independent isolated word recognition based on multiple templates using split method
Authors: Sugamura Noboru , Shikano Kiyohiro , Kohda Masaki
Published: July 2007

A speaker‐independent word recognition based on multiple word templates is described using the SPLIT method. Since the spectral distance calculation amount is independent of the number of word templates in the SPLIT method, it can be made best use of in speaker‐independent word recognition based on multiple word templates.

Phoneme‐like templates and multiple word templates are selected automatically by a clustering technique. The effectiveness of this system was verified via several experiments using telephone switch. Recognition accuracy of 96.9 and 96.2 percent was obtained for training and test speech samples, respectively.
Design and implementation of the s & t net software
Authors: Murai Jun
Published: July 2007

Flexibility, extensibility and reliability of a computer network are efficiently achieved by a design with hierarchical architecture. In an actual network system the network design should be implemented by modules corresponding to the layers of the hierarchical architecture in order to realize its inherent advantages. Generally, in highly modularized software the problem of overhead in transferring data between modules has to be solved. This paper presents a method of network software design which is easily implemented by a highly modularized software structure and describes implementation of the architecture through separate communication control and data processing in an operating system. These presentations are made by introducing the methods employed in constructing a local computer network called the S & T net. The methods presented in this paper can be applied generally to the design and realization of network software.
The measurement of the 3‐d position of the polyhedra
Authors: Guo Heng‐Li , Yachida Masahiko , Tsuji Saburo
Published: July 2007

The scene containing polyhedra has been studied as one of the interesting subjects in research on robot vision, and several methods for extracting the line drawing of the polyhedron have been proposed. However, few have dealt with estimation of the location and orientation of the polyhedron in 3‐D space. This paper proposes a method for measuring the 3‐D position (location and orienation) of the known polyhedron by effectively utilizing the shade information. In other words, the relations among the polyhedron, its image and shadow image are analyzed, by which the 3‐D coordinates of four noncoplanar vertices of the polyhedron, are determined. The candidates for mapping of the measured vertices to those of the polyhedron are found by the distance search method or by the feature reference method. Using the coordinates of the candidates, the polyhedron is reconstructed, together with its shadow. By comparing these reconstructed shadows SR' with the original shadow SP', the one providing the best fit is adopted as the solution. The method is applicable even if there is no difference among the brightness of the surfaces. The experiment shows that the error in measurement of the 3‐D location and orientation by the proposed method are within 2 and 5 percent of the visual field, respectively.
A Hierarchical General‐Purpose Pipeline System
Authors: Endo Noboru , Nakamura Tadao , Shigei Yoshiharu
Published: July 2007

The intelligent links that orient realization of the computer system integrating data communication and processing have been proposed. However, the practical system configuration and control have not yet been discussed. Based on the general‐purpose pipeline concept to implement the intelligent link, this paper presents the hierarchical pipeline system configuration that is designed to obtain high efficiency of the total system by overlapped data communication and processing. The decision method of the processing time in the segment at a higher level which is a processing unit in the pipeline, is shown.

The decision is made independently at each segment. Therefore, this hierarchical pipeline system enables parallel processing by distributed control. The routing algorithm in the general multitrack bus is proposed as a communication medium executing high‐speed data transmission among the lower‐level pipeline processing elements in the segment.
Equilibrium point analysis of memory interference in multiprocessor systems
Authors: Fukuda Akira
Published: July 2007

An approximate analytic tool called equilibrium point analysis is applied to the problem of memory interference in multiprocessor systems. This is a simple and powerful analytic tool based on the fluid approximation. It has been used widely in packet broadcast systems. It is shown that quite general multiprocessor systems can be studied by this technique with amazing simplicity. For example, systems made up of many classes of processors and memory modules with arbitrary static memory reference patterns and systems with dynamic memory reference patterns are considered. In most cases, the approximation of the analysis is shown to be sufficiently good. One of the advantages of this technique is that the error is smaller for larger systems for which there have been no appropriate analytic tools thus far.
Complexity to determine containment among inequality tableau queries
Authors: Terada Tomoyuki , Hagihara Ken'Ichi , Tokura Nobuki
Published: July 2007

Tableau queries are known as abstract models of queries for relational databases. When two tableau queries are given, the problem of determining whether the result of one of the tableau queries always contains that of the other (containment decision problem), is of fundamental importance in obtaining the optimization procedure of tableau queries. The tableau queries defined by Aho et al. can express joins, projections and selections by equalities in the relational algebra. Under this definition, Aho et al. have shown that the containment decision problems are generally NP‐complete and that there exist a class of problems which can be decided in a polynomial time. In this paper, we classify the tableau queries which are obtained so as to be able to express the selections by inequalities into two groups by whether or not they are totally ordered. We show that if inequality selections are added to problems which can be solved in a polynomial time without inequality selection, then the containment decision problems are NP‐complete even though the tableau queries are totally ordered. Also, for queries which are not totally ordered, it is shown that even if stronger restriction is added, the containment decision problems are co‐NP‐complete.
Performance Evaluation for Memory Subsystem of Hierarchical Disk‐Cache
Authors: Miyachi Taizo , Mitsuishi Akitoshi , Mizoguchi Tetsuo
Published: July 2007

The memory subsystem hierarchical disk‐cache (MESSIAH) discussed in this paper aims at realization of high‐speed access to secondary memory. MESSIAH uses a large‐capacity buffer memory (A) for the input‐output device and a small‐capacity buffer (B) for each disk‐device. (A) realizes the traditional disk‐cache function. (B) realizes reduction of the disk‐rotations waiting time due to a miss in RPS (rotational position sensing), reduction of overlap between disk write‐in and search time, and immediate delivery of look‐ahead data. In other words, in MESSIAH (A) realizes a cache memory of sufficient capacity and (B) copes with RPS misses, which increase with size of the transfer block between disk and (A). (B) also realizes high‐speed write‐in and read‐out of the disk. Thus, MESSIAH provides greater advantage than the multiple effects of disk‐cache function and the B‐disk (buffer‐installed disk device). This paper proposes an architecture for MESSIAH and verifies its usefulness by simulation.
Performance analysis of line scheduling methods for multilink procedures
Authors: Kobayashi Tetsuji
Published: July 2007

A data link with multiple lines can be implemented by using the standard protocol of a multilink procedure. The multilink procedure achieves performance flexibility and reliability improvement. This paper proposes line scheduling methods at a sending station, which is an important factor for implementing multilink procedures, and evaluates their performance. A line scheduling for a multilink procedure selects a line to which a multilink frame, which is the transfer data unit, is assigned. The speed of the lines may be equal or different. The following methods are studied: (1) rotational scheduling, (2) stochastic scheduling and (3) adaptive scheduling. The adaptive scheduling method is shown to have the best performance. For easy implementation it is shown that the rotational scheduling method can be applied to lines with equal speeds and that the stochastic scheduling method can be applied to the lines with equal or different speeds.
A square root hardware algorithm using redundant binary representation
Authors: Takagi Naofumi , Yajima Shuzo
Published: July 2007

This paper proposes a square root hardware algorithm using the redundant binary representation in the internal computation. A discussion is made for the realization of a combinational square‐rooter based on the algorithm. This paper considers the computation of the mantissa in square‐rooting for the binary normalized floating‐point representation. The proposed algorithm is a kind of subtract‐and‐shift square‐root method. Partial remainders are represented by the redundant binary representation, where each digit is an element of {‐1, 0, 1}. Then each digit of the square root is determined from {‐1, 0, 1}, by examining the upper three digits of the partial remainder. The computation for the partial remainder is affected in the redundant binary number system. Finally, the square root determined in the redundant binary representation is converted into the ordinary binary representation. In the redundant binary representation, the addition of two numbers can be effected without carry propagation. Consequently, by using the combinational circuit, each digit of the square root can be determined in a constant time, independently of the number of digits of the operand. The computation time for the n‐bit square rooter (number of stages) is proportional to n. The number of logic elements in the circuit is proportional to n2. The hardware structure is a regular cellular array, which is suited for VLSI implementation. When the circuit is implemented on a VLSI chip, the chip is proportional to n2. The proposed square rooter has nearly the same circuit structure and the hardware complexity, compared with the conventional subtract‐and‐shift square rooter using ripple carry adder. The computation time is approximately one‐fifth for 32‐bit and one‐tenth for 64‐bit, compared with earlier circuits.
Deadlock detection algorithm with level number
Authors: Eguchi Yoshikazu , Yoshinaga Tsunehiro
Published: July 2007

The detection of deadlock is one of the important problems in the database system. This paper proposes an efficient algorithm for detecting the deadlock in the concentrated database system, and demonstrates its correctness. The algorithm works as follows. When a process makes an access to a resource which is locked by another process, the process must wait for the resource. The algorithm detects the deadlock by tracing the edges of the resource graph, starting from the waiting process. By attaching the level number to each node, the number of edge tracings can be reduced, which helps to reduce the overhead for deadlock detection. To evaluate the efficiency of the proposed algorithm, an experiment was performed by computer simulation. The cases of the algorithm with and without the proposed level number are compared, indicating the effectiveness of the proposed method.
Transparent memory: A hardware solution to the memory conflict problem
Authors: Hisano Takumi
Published: July 2007

The paper proposes a memory organization aiming at reduction of memory conflict produced by the multiple access. The proposed memory organization has the effect of suppressing not only the memory conflicts but also the write memory conflicts. The conflict of read access is suppressed by using more than one memory module of the same content, and the conflict of write access is suppressed by restricting the write area and using the distributed communication mechanism. It is shown by the performance evaluation simulation that the memory conflict is sufficiently small compared with the number of multiple read memory and approaches a constant with the increase of the number of processors n. The hardware complexity is relatively large. The physical memory is n times compared with the logical address space and the number of memory control circuits is n2. There is one connection between the memory control circuit and the connection network. By specifying the area of applications and simplifying the connection configuration, the hardware complexity can be reduced.
Method of pattern positioning for automatic verification of seal imprint
Authors: Ueda Katsuhiko , Nakamura Yoshikazu
Published: July 2007

In automatic computer verification of seal imprints accurate positioning of an examined seal imprint over a registered imprint is of great importance. This paper proposes a method which positions an examined seal imprint in relation to a parallel shift and rotation by using the centroid of its frame figure and the pixels on a circle of a certain radius from the centroid. Since this method achieves positioning by using local features of the examined seal imprint, rapid positioning is possible. In the presence of small defects in the imprint frame this method has the advantage that the centroid of the seal imprint is accurately obtained and is not affected by distortion of the imprint frame. In a positioning experiment based on this method 240 actual seal imprints were used. All imprints were positioned within a ±0.1‐mm parallel shift error and more than 99% of the seal imprints were positioned within ±1.76° rotation angle errors. A verification experiment was conducted using a seal imprint verification system which incorporated the principles of this method. As a result, the verification error which was caused by the positioning error was found to be 0.83%. The experimental results show that the proposed positioning method is efficient for automatic verification of seal imprints.
The application of tense logic to database behavioral description
Authors: Tarabe Koichiro , Suzuki Atuyuki
Published: July 2007

This paper defines a presupposition‐free many‐sorted tense theory MQRT*=. This theory is applied to behavior description of historical database. Using this theory makes it possible to express clearly not only the usual schema information but also such behavioral aspects of schema as event, dynamic integrity constraint, etc. This is the first time behavior description has been provided by a complete theory. This theory is also applied to schema description of historical database. Providing both schema description and behavior description amounts to total, full description of historical database.
A restoration scheme for images with missing parts
Authors: Maeda Hiroyuki , Takahashi Kenichi , Ohta Masamitsu
Published: July 2007

This paper proposes a restoration scheme which restores a group of pixels by malfunctioning of imaging equipment or a part of an object hidden by another object. This restoration starts on the circumference of the group of missing pixels and proceeds to the interior to make the restored image acceptable for the human viewer. First, edges of objects in the neighborhood of the missing pixels are extracted. Second, the direction of the edge passing through a pixel to be restored is estimated by the least‐square method. The estimated edge direction is used to determine reference pixels from which the missing pixel is restored. Care is taken so that the restored gray level of the missing pixel is not extremely different from those of its neighbors. If an edge enters a missing part of an image and another edge goes out of this part, the two edges are connected to produce a single, smooth edge. Computer simulations will demonstrate the effectiveness of the proposed method.
System design of a special‐purpose computer for LSI design rule checking
Authors: Tamaru Keikichi , Onodera Hidetoshi
Published: July 2007

This paper describes a hardware system for pattern operations and design rule checking (DRC) in LSI layout design. This is a multimicrocomputer system which performs the parallel processing in the pattern data of each of the divided areas and the pipeline processing of input, pattern operation and output stages. The system consists of two upper‐level computers and a number of lower‐level computers. The upper‐level computers perform input/output of pattern data, control over the system and pattern operations for figures which spread over more than two divided areas. Each lower‐level computer executes pattern operations and DRC against figures of the assigned area by the sliced‐vector method.
Three‐state neumann neighbor cellular automata capable of constructing self‐reproducing machines
Authors: Serizawa Teruo
Published: July 2007

This paper defines the 3‐state Neumann‐neighbor cellular automata, and shows that its space is construction‐universal. The proof for this is achieved by presenting a realization of self‐reproducing machines. The state‐transition rule and the basic operations of configurations of the cellular automata are described first. Then methods are shown to construct AND circuit, pulse generator, signal‐line, delay circuit and memory circuit. Finally, the structure of the self‐reproducing machine is shown, which is realized by combining those circuits, The machine has two construction arms, a Turing tape and a timing loop. It can make a replica of its own using the Turing tape. The machine can also be operated as a universal construction machine or a universal Turing machine.
Consonant recognition methods for unspecified speakers using bpf powers and time sequence of LPC cepstrum coefficients
Authors: Niyada Katsuyuki , Hoshimi Masakatsu
Published: July 2007

This paper discusses the recognition of the consonant (except the consonant at the top of the word) in a word for unspecified speakers. First, the consonant section is detected based on the power dips extracted from the low‐ and high‐frequency power information, together with the nasal and unvoiced properties.

Applying the discrimination diagram to the detected low‐ and high‐frequency dips, the phoneme is classified into the four phoneme classes (rough classification). Then methods are discussed which discriminate the individual phonemes in the phonemes group by pattern matching (fine classification). Using the time‐series pattern of the LPC cepstrum coefficient as the parameter, it is shown that the comparison with the standard phoneme patterns using the Bayes' discriminant and the Mahalabinos distance is the most useful. The result of recognition experiment using the segmentation, rough classification, and fine classifications is presented. For twenty subjects of both sexes, the mean recognition rate of 78.1 percent was achieved.
Parallel searches of game trees
Authors: Usui Hiromoto , Yamashita Masafumi , Imai Masaharu , Ibaraki Toshihide
Published: July 2007

A two‐person perfect‐information game is represented by a minimax game tree and, by solving the tree, we can obtain the result of the game when both players choose perfect moves at all the positions. To this end, various search procedures have been proposed. In this paper, these procedures are modified to implement them on a parallel computer consisting of m processors, and variations of the computation time are investigated with m being a parameter. As a theoretical result, we point out that the speedup ratio of the computation time of solving a game tree by m processors to that by 1 processor may become larger than m (acceleration anomaly) or smaller than 1 (detrimental anomaly) in general. Also, we show that the detrimental anomaly does not occur as long as the five search procedures investigated in this paper are used. Next, through simulation experiments, it is shown that the speedup ratio is considerably smaller than m, and its cause is discussed. The eligible search is considered to be the best among the search procedure investigated.
Characteristics of a programmable logic unit
Authors: Member Takahiko Murayama, Associate , Yamada Hidekazu , Nakamura Tadao , Shigei Yoshiharu , Yoshioka Yoshio
Published: July 2007

This paper considers a programmable logic unit (PLU) which is a computing‐in‐memory device with stepwise programmable computing logics and the data transmission lines/buses, and discusses its operational characteristics. The PLU is combined with the memory device in a Neumann‐type computer with a great number of computing logics. From the viewpoint of Flynn's classification in the Neumann‐type computer, we consider the level‐1 PLU and the level‐2 PLU as structures for the PLU, and discuss their configurations in detail. First, we discuss the mapping method and the number of steps for the program of the mathematical expression. It is shown that the PLU can map directly the program written in the inverse‐Poland notion and that the connection lines/buses can easily be assigned. Second, we discuss the comparison between the computing time of the computer with the PLU and the processing time of the Neumann‐type computer. It is shown that the computer with the PLU is several times faster than the Neumann‐type computer in processing the program. On the other hand, it is seen that the level‐2 PLU with the distributed buses is suited to the general‐purpose computer, although the processing speed is somewhat low.
A built‐in test for functional testing in semiconductor random access memory
Authors: Miura Yukiya , Tamamoto Hideo , Narita Yuichi
Published: July 2007

The increasing time for functional testing of the logical circuit has become a problem in recent years. As a solution a built‐in test is proposed as a means to make testing easier. In the proposed method, the testing circuit is built in the IC chip, and the test is executed within the chip to verify whether the function is fault‐free. This paper proposes a new built‐in test for the semiconductor memory by considering its internal operation. In the method, all the data from memory cells on the same word‐line can be treated at the same time, using the built‐in test circuit in the chip. As a result, the length of the test sequence is of the order of N1/2, realizing a high‐speed testing. Another feature is that the tests for the memory‐cell array and the decoder can be executed independently, making it possible to cope with the multiple fault in those circuits. The built‐in test circuit can be implemented in a relatively simple way, and the extra hardware overhead becomes almost negligible with the increase of the memory capacity.
Performance evaluation of asynchronous distributed processing system with limited‐advance processing
Authors: Watanabe Takashi , Nakanishi Hikaru , Sanada Hidehiko , Tezuka Yoshikazu
Published: July 2007

The traditional parallel processing assumes synchronous jobs, for which the processing can easily be planned before execution. On the other hand, the parallel processing is not usually considered for asynchronous jobs of a stochastic nature, such as the queueing network simulation, since the synchronization control of the processors is a problem. The advance processing has already been proposed as a control scheme for the processors in the asynchronous job parallel processing system. In this scheme, each processor performs the processing, thereby ignoring its relation to other processors. Thus the result of the processing is cancelled when a contradiction is found. Unfortunately, the processor may be too advanced in the execution, which results in a large number of cancelling, thus decreasing the processing ability per processor. From such a viewpoint, this paper discusses the limited‐advance processing which is the improved scheme of advance processing. In this scheme, if the processor performs a certain amount of processing, it judges itself as too advanced, and awaits the progress of other processors. It is shown that there exists the optimum advance limit in this scheme, which is a function of the number of processors. The proposed scheme is analyzed to predict the optimum advance limit. In the analysis, the relation between the simulation time and the real time is specified, and the distribution overhead, cancelling time and the number of iterations are discussed. Comparing the result of numerical computation in the analysis and the result of measurement in the prototype system, the validity of the analysis is verified.
Verification of progress property of algebraically specified communication protocols
Authors: Higashino Teruo , Taniguchi Ken'Ichi , Kasami Tadao , Fujii Mamoru , Mori Masaaki
Published: July 2007

This paper considers the communication protocol whose specification is described algebraically in a style of an “abstract sequential machine.” A method is presented to verify the progress property of the protocol, such that the transmitted data will eventually be received. First, by the algebraic method, we verify some static properties (invariants) which hold in any state reachable by the execution of the state transitions permitted by the protocol. Also, we verify the relations which hold between the states before and after the execution of each state transition. These relations are transformed into the formulas of the temporal logic by using some transformation rules. At the same time, the formulas of the temporal logic are provided as the assumptions for the stations and communication lines, which are needed in the discussion of progress property of the protocol, such that the communication lines are not functionally cut off. Using these formulas and standard axioms in the temporal logic (inference rules), it is shown that the predicates representing the progress property of the protocol are true. The foregoing is the outline of the discussions in this paper. This paper applies the method to Stenning's data transfer protocol, and the progress property is verified.
A single public‐key authentication scheme for multiple users
Authors: Okamoto Tatsuaki
Published: July 2007

This paper proposes a new user authentication scheme, which does not require a management file for users' passwords. It has a high security, realizing the authentication of a large number of users by a single public key. Because of this property, the proposed system has merits in the application to off‐line and mutual authentication. The scheme is also useful in the authentication in a large system with a large number of users. The system is constructed using the public‐key digital signature and a oneway function with the commutative property. An example is presented where RSA is employed as the digital signature and the congruent exponential function is employed as the one‐way function. It is described that the security of the proposed system appears to be equivalent to that of RSA or the digital signature based on RSA. Following the same idea, a digital signature system is proposed, where the authentication of a large number of users can be performed by a single public‐key. A variation of the scheme is presented which has the same performance as the proposed scheme.
A built‐in testing scheme for ic memories by considering address decoder and cell array separately
Authors: Tamamoto Hideo , Sakusabe Hirotomo , Narita Yuichi
Published: July 2007

In the built‐in testing of the IC memory, the testing efficiency can be improved by building the testing circuit into the IC memory, that can observe and/or control the part which is difficult or impossible to be observed and/or controlled by the traditional method. From the functional viewpoint, the IC memory can be divided into the address‐part (address decoder, etc.) and the data part (memory cell, etc.). In the traditional testing, the address‐part is tested through the data part. In this paper, a built‐in testing scheme is discussed in which the testing circuit is built in so that the address and the data part can be tested separately. Restricting the faults to be the stuck‐at fault of the address decoder, the stuck‐at fault of the memory cell, and the interference fault by the 1‐neighborhood cells, those faults can be tested by compressing the response by a simple compression function, using the O(N) test sequence (where the sequence length is proportional to the memory capacity N). The test sequence generation circuit and the response compression circuit can be implemented simply by employing counters and shift registers. The extra hardware complexity becomes negligible with the increase of the memory capacity. Thus, it was proved as effective that the testing circuit is built‐in that can observe and/or control the part, which is difficult or impossible to be observed and/or controlled by the traditional method.
A color monitor system for color anomaly inspection
Authors: Yamada Kenshi , Sugie Noboru , Inaba Akira
Published: July 2007

This paper reports on the four kinds of inspections that can be performed by a system using a color monitor. The aim is to perform various kinds of inspection by a single system to provide a comprehensive decision for the color anomaly.

The system used in this paper is a modified version of a system controlled by a minicomputer developed by Inaba et al. [1]. Measurement examples are also presented.
Data transmission and diagnosis in bus networks derived from block design
Authors: Ozawa Takao
Published: July 2007

This paper presents a method for constructing bus networks interconnecting a large number of data processors based on the block design. Properties of the bus networks constructed, an algorithm for finding data routing paths, and conditions for a distributed diagnostic procedure are presented. In the construction method considered, we regard a block and an object in the block design as a processor and a bus, respectively. Then two processors are either connected to the same bus or interconnected via a single intermediate processor. There are almost as many such independent data routing paths through a single intermediate processor as I/O ports of a processor. In fault diagnosis it is a general practice to assume an upper bound on the number of failed processors. For our bus network, we can show that it is possible to diagnose all the processors correctly by a distributed diagnostic method if the number of failed processors is less than min(n/2, d), where n is the number of processors and, with q and m denoting the number of I/O ports per processor and of buses, respectively, d = 4(m ‐ q)/q (q: even) or d = 4q(m ‐ q)/(q2 ‐ 1) (q: odd).
A functional description of brain mechanics in the writing movement control
Authors: Taguchi Hideo , Fujii Katsuhiko
Published: July 2007

This paper postulates the brain mechanism as a control center of writing acts of characters by summarizing various recent partial findings about brain functions. Specifically, brain functions of writing control are classified into three categories.
Design of a time‐optimal digital control system for a dc‐servomotor with amplitude limitation
Authors: Huang Xi Yue , Kameyama Michitaka , Higuchi Tatsuo
Published: July 2007

The time‐optimal control problem for a dc servomotor with an amplitude limitation in the manipulated variable is a complicated nonlinear problem. The problem has been investigated extensively from a theoretical viewpoint. However, little study has been made on the practical digital control system, even for a small‐scale controller using a microcomputer. This paper discusses the time‐optimal position control for a dc servomotor from such a viewpoint, and proposes a design method of the system based on the linear state feedback with the predetermined optimum sequence of a manipulated variable and the optimum sequence of the state trajectory. In other words, the optimal sequence of a manipulation variable and the optimum sequence of the state trajectory are predetermined by the linear programming, and the results are stored in ROM. In the actual control, the optimum sequence is read out from ROM to generate the desired sequence. The linear state feedback can reduce the effects of the external disturbance and the modeling error caused by the system fluctuation. Traditionally, the effects of the temporary disturbance and the modeling error have been a problem from the viewpoint of practical implementation, processing speed, and stability. The control minimizing these effects is the most remarkable feature of the proposed method. This method is suited to the controller using the microcomputer, and can be effective for the reduction of complexity and cost of the controller.
A fast algorithm for color image quantization using only 256 colors
Authors: Watanabe Takashi
Published: July 2007

In the recent workstation for CAD and CG, a color map display is often used, which can display 256 colors selected from 224 (approx. 16000000) colors using a look‐up table. Even in the computer system with such a color display with such a limited number of colors, it is desired that the continuous color image should be processed. In most cases, by determining colors which are important to the image (representative colors), the color image can approximately be displayed without much degrading the image quality. This paper proposes a new method for the approximate display of the color image by 256 colors. In the method, RGB color space is successively partitioned to determine 256 representative colors, so that the quasi‐optimum solution is obtained in the sense of the least‐mean‐square error. By the proposed method, a highly accurate approximate image is obtained with several times faster speed, compared with the traditional methods. The work memory required in the program is only 100 to 200 kBytes, which is less than in the traditional method.
Plex grammars for predicate logic programming and its application to the structural analysis of electronic circuits
Authors: Peng Ke Juan , Onda Kunio , Yamamoto Tsuyoshi , Aoki Yoshinao
Published: July 2007

In the syntactic analysis and recognition of patterns, the grammar to describe the pattern structure is the most basic theoretical problem. In regards to this problem, various kinds of grammars have been proposed, for example, Plex grammar which aimed at a more natural model description of the patterns. It can model a more general structure than graph grammar. On the other hand, the theory of grammar based on the logical programming such as Prolog, has recently been considered. It has advantages in that the grammatical rules can be described in the predicate form and the parsing can easily be performed using the inference mechanism. But in fact, the description by Plex grammars does not match the predicate logic, and there has been no study which combines Plex grammar and logic programming. This paper proposes C‐Plex grammar as another description of Plex grammar by the clauses of predicate logic, as well as the top‐down parsing of context‐free C‐Plex grammar based on logic programming by Prolog. C‐Plex grammar based on predicate logic programming has the advantage of high descriptive ability and easy parsing. The feature of C‐Plex grammar is demonstrated using the structural analysis of the electronic circuit as an example. By this elaboration, not only the hierarchical structure among circuit elements and the macroelements, but also the connection relation among them can be analyzed.
An implementation of multiple‐valued logic circuit with cmos multiple‐valued output gates
Authors: Sakata Izumi
Published: July 2007

With the progress of high‐density information handling technology, multiple‐valued logic is considered interesting. Studies have been made on the applications to the high‐density VLSI and the optimally multiple‐valued information processing systems. This paper considers the use of a CMOS multiple‐valued output gate, and proposes an implementation of the multiple‐valued logic circuit, which is suited to the integration from the viewpoints of the integration density and the power consumption. The CMOS multiple‐valued output gate produces a multiple‐valued output from the predetermined number (n ‐ 1 for n‐valued case) of binary inputs. Compared with similar multiple‐level output circuits proposed up to now, the gate has the feature of simple structure and easy correspondence to arbitrary n‐valued function. In the design of the multiple‐valued logic circuit by the proposed method, the inputs to the multiple‐valued output gate are determined first from the required multiple‐valued output. Then the logic circuit satisfying the inputs is constructed from the literal circuit with multiple‐valued inputs and binary logic circuits. Design examples by the proposed method are presented. It is shown especially for the arbitrary n‐valued case that the design is simplified since the inputs to the multiple‐valued output gate can be represented in the general form. Several rules for deriving the general form are described. Finally, it is made possible to implement the multiple‐valued logic circuit, which is simple and suited to integration.