bluuebunny/crossref_metadata_2025 huggingface dataset:
Achievement of Excellent C-V Characteristics in GeO2/Ge System Using Post Metal Deposition Annealing
Authors: Koumo Hideo , Suzuki Yuya , Oniki Yusuke , Iwazaki Yoshitaka , Ueno Tomo
Published: October 2010

Impacts of structural transformations of top and bottom interface of metal/GeO2/Ge structure on electrical properties were investigated. The GeO2/Ge interface that was formed by low temperature oxidation achieved negligible hysteresis because of suppressing GeO volatilization. On the other hand, the metal/GeO2 interface with post metal deposition annealing attained disappearance of VFB shift. XPS and TDS measurements show that GeOx at the interface of the as-deposited metal/GeO2 vanished after annealing. It suggests that the improvement of the VFB shift was achieved by volatilization of GeOx including defects at the metal/GeO2 interface.
Comparative Experimental Study between Diamond and Conventional MOSFET
Authors: Gimenez Salvador P. , Alati Daniel M.
Published: October 2010

The focus of this work is to perform the experimental comparative study between Diamond and the conventional MOSFET counterpart in order to verify the benefits observed by three dimensional numerical simulations, considering the same geometric factor, die area and bias conditions, as described in first publication of Diamond style layout. The devices were manufactured by using the commercial manufacture CMOS process from 0.35μm AMI (On-Semiconductor) that is available in MOSIS Educational Program (MEP). The experimental results prove that Diamond MOSFET presents a better performance than one found in equivalent conventional transistor, except in relation to the Early voltage, due the higher impact ionization in the drain region than one observed in the conventional counterpart. Therefore the Diamond layout style is an important alternative to improve the performance of the analog, current drivers and pass switches integrated circuits applications.
Growth of Epitaxial Silicon-on-Insulator Substrates by Solid State Epitaxy
Authors: Arkun Erdem F. , Vosters Gary , Semans Scott , Clark Andrew , Smith Robin S.
Published: October 2010

The growth of monolithically integrated silicon-on-insulator (SOI) substrates using rare earth oxide insulator layers is presented. Rare earth oxides may be grown epitaxially on Si(111) substrates due to their unique cubic crystal structure and lattice matching to twice the silicon lattice spacing. Growth of silicon on top of epitaxial rare earth oxides is achieved and several variations of growth schemes are investigated. The current process has been developed on 100mm silicon wafers and may be scaled up to 200mm wafer sizes in a production type cluster tool.
Laser-Induced Epitaxial Growth (LEG) Technology for Multi-Stacked MOSFETs
Authors: Son Yong-Hoon , Hwang Kihyun , Kang Chang-Jin , Yoon Euijoon
Published: October 2010

Laser-induced epitaxial growth (LEG) process has been developed to obtain single crystalline silicon on insulator using a seed which is fabricated by selective epitaxial growth (SEG) process. It was found that when the energy density of the laser beam is high enough to melt the deposited amorphous silicon completely, the lateral epitaxial growth of molten silicon occurs until the impingement of neighbor melting fronts. The location and size of such single crystalline grain was precisely controlled since the seed for lateral epitaxial growth has been pre-patterned on an oxide layer. This novel process enables the realization of high-quality multi-stacked MOSFETs for three-dimensional integration.
Modeling of NPN-SiGe-HBT Electrical Performance Improvement through Employing Si3N4 Strain in the Collector Region
Authors: Al-Sa'di Mahmoud S. , Fregonese Sébastien , Maneux Cristell , Zimmer Thomas
Published: October 2010

A new NPN-SiGe-HBT device architecture utilizing a Si3N4 strain layer is proposed. The impact of introducing a Si3N4 strain layer in the collector region on the device's electrical properties and frequency characteristics has been studied using TCAD modeling. An approximately, 8% of improvement in fT, and 5% of improvement in fMAX have been achieved in the new NPN-SiGe-HBT device's architecture in comparison with an equivalent standard conventional NPN-SiGe-HBT device. Despite of the very small decrease in the breakdown voltage BVCEO value (1%─4%), the fT×BVCE0 product enhancement is about 6% by means of strain engineering.
> 1020 cm-3 n-Doping in Ge by Sb/P Co-Implants: n+/p Diodes with Improved Rectification
Authors: Kim Jeehwan , Bedell Stephen , Sadana Devendra K.
Published: October 2010

One of the greatest challenges for fabricating a Ge channel n-MOSFET is to achieve high n-type dopant activation within the source and drain regions. Currently, p+ doping greater than 1020 cm-3 can be routinely achieved which is close to the theoretical solid solubility limit of B in Ge. However, typical n+ doping of Ge is limited to less than 5×1019 which is far below the solid solubility limit of P in Ge. This work is aimed at achieving n+ doping of greater than 1020 cm-3 in Ge. In this paper, we describe a Sb and P co-implantation process to enhance n+ activation in Ge. N-carrier concentration more than 1.0×1020/cm3 has been demonstrated by this method. Furthermore, higher forward bias current in Ge n+/p junction diode is obtained from n+ formation by Sb and P co-implantion, as a consequence of the high n-type dopant activation in Ge.
Improving the Performance of SiGe-Based IR Detectors
Authors: Kolahdouz Mohammadreza , Afshar Farniya Ali , Östling Mikael , Radamson Henry H.
Published: October 2010

During recent years, single crystalline (Sc) SiGe has been recognized as a new low cost thermistor material for IR detection. In this study the effect of Ge content, pixel size and the Ni silicide on the performance of SiGe/Si thermistor material have been presented. The noise level was decreased for more than one order of magnitude when the Ni silicide layer was integrated below the metal contacts. The silicidation slightly improved TCR values for the detectors (+0.22%/K). However, Increasing the Ge content had the most significant effect on the TCR. A statistical analysis was applied to evaluate the effect of each parameter. It was found using the factorial method that decreasing the pixel size will enhance the TCR value.
Formation of Al2O3 Film on Si Substrate by Microwave Generated Remote Plasma Assisted Atomic Layer Deposition Technique
Authors: Ishizaki Hiroki , Iida Masataka , Otani Yohei , Fukuda Yukio , Sato Tetsuya , Takamatsu Toshiyuki , Ono Toshiro
Published: October 2010

Al2O3 films were grown on Si substrates by microwave generated remote plasma assisted atomic layer deposition technique (PA-ALD). The thickness of the Al2O3 films would be controlled by the ALD cycles. For the X-ray photoelectron spectroscopy results of Al2O3 film, carbon compounds didn't exist into Al2O3 film. The MOS capacitor obtained by PA-ALD had small hysteresis and the interface trap density of 4.5x1010cm-2eV-1.
Characterization of Interface States of HfO2/Ge with Fluorine Treatment by Using DLTS/ICTS
Authors: Kanashima Takeshi , Yoshioka Yuichi , Lee Dong-Hun , Okuyama Masanori
Published: October 2010

Deep level transient spectroscopy (DLTS) technique that has some merits such as no assumption of leakage mechanism and characterization of both majority and minority carrier traps is applied for characterization of interface state density to HfO2/Ge gate stack. DLTS and isothermal capacitance transient spectroscopy (ICTS) signals of HfO2/Ge gate stack can be detected, and the results of these measurements show that interface state densities of majority and minority carriers can be reduced by fluorine treatment, and no new traps are created by this treatment. So, fluorine treatment is useful to improve the device performance. Moreover, DLTS and ICTS signals can be simultaneously obtained, and capture cross-section can be estimated by using these results.
Effect of Heteroatom for Nitrogen Vacancy in SiN/SiO2 Interface Layer in MONOS-Type Memories
Authors: Yamaguchi Keita , Otake Akira , Shiraishi Kenji
Published: October 2010

We have investigated the effect of heteroatom for nitrogen vacancy in SiN/SiO2 interface layer in MONOS-type memories based on first principle calculation. It has been reported that oxygen and hydrogen atom are incorporated in SiN charge trap layer, and that nitrogen vacancies in SiN is one of the most suitable charge trap of MONOS-type memories for high program/erase cycle endurance. In this study, we found that nitrogen vacancies are suitable charge traps with high program/erase cycles endurance even if hydrogen or oxygen atoms are incorporated. This result indicates that heteroatom near nitrogen vacancies do not affect its high program/erase cycle endurance properties in MONOS-type memories.
Characterization of Interfaces between Chemically Cleaned or Thermally Oxidized Germanium and Metals
Authors: Murakami Hideki , Fujioka Tomohiro , Ohta Akio , Bando Tatsuya , Higashi Seiichiro , Miyazaki Seiichi
Published: October 2010

To implement a Ge channel in MOSFETs and to fulfill its potential, it is imperative to have a good understanding the natures of both metal/Ge and dielectric/Ge interfaces and to control them as precise as possible. It is well known that the Fermi-levels at any metal/Ge interfaces are pinned near the valence band edge of Ge. Recently, it has been reported that by inserting the GeOx and AlOx film into metal/Ge junction, the junction properties have been drastically changed from Schottky to Ohmic and Ohmic to Schottky characteristics on n-Ge and p-Ge, respectively. The interface properties remain a matter of research. In this work, we have characterized surface band bending and chemical bonding features of interfaces between chemically-cleaned or thermally-oxidized Ge and metals, and also examine their correlation with electrical properties.
Electrical Properties of Yttrium-Titanium Oxide High-k Gate Dielectric on Ge
Authors: Bera Milan K. , Ahmet P. , Kakushima K. , Tsutsui K. , Sugii Nobuyuki , Nishiyama Akira , Hattori T. , Iwai H.
Published: October 2010

The feasibility of YTiOx as a high-k gate dielectric for germanium-metal-oxide-semiconductor (MOS) devices has been investigated. The effects of different concentration of TiOx on electrical properties of YTiOx-based MOS capacitors are reported. It has been demonstrated that higher TiOx concentration in YTiOx may help to boost up dielectric constant while it causes serious damage to the interfacial properties. It has been observed that YTiOx film can effectively prevent re-growth of GeOx-based interfacial layer likely due to formation of stable Y-Ti-germanate at the interface in consequence of strong interaction of YTiOx with underlying Ge substrate. Indeed, YTiOx with 22% TiOx exhibits fairly good electrical characteristics with high dielectric constant value of κ~21{plus minus}1. The potentiality of YTiOx has further been examined with gate oxide downscaling and the results are compared with that of regularly used high-κ dielectrics promising for Ge MOSFETs.
Enablement and Optimization of SiGe HBTs for Extreme Environment Electronics
Authors: Niu Guofu
Published: October 2010

This paper reviews recent progress in SiGe HBT compact model development and SiGe profile optimization aimed specifically at extreme environment electronics applications. Wide temperature range compact modeling has been achieved by more physically accounting for effects like carrier freeze out and Mott transition, as well as including higher order temperature dependences of critical model parameters. New insight into the physics of fT roll-off in SiGe HBTs is offered, and used to optimize SiGe profile for improved high injection performance. Single event upset (SEU) in SiGe HBT logic circuits is shown to improve with cooling.
Technology Computer-Aided Design (TCAD) Feasibility Study of Scaling SiGe HBTs
Authors: Camillo-Castillo Renata , Stricker Andreas , Johnson Jeffrey B. , Appaswarmy Aravind , Malladi Ramana , Joseph Alvin , Harame D.
Published: October 2010

Technology computer-aided design (TCAD) feasibility studies for for scaling a SiGe-based NPN with cutoff frequencies, fT/fMAX of 200/250GHz were conducted, in which the critical process and device design components were self-consistently addressed. The calibrated 200/250GHz calibration was verified by utilization for scaling to a 300GHz performance level, which was subsequently used as the baseline for scaling to a 500 and 630GHz fT performance level. Comparison of the transit time components reveal the base and collector-base transit times as being the predominant electron delay components for performance levels less than 500GHz. At 630GHz the device was observed to be limited primarily by the collector-base transit time.
Direct Parameter Extraction Of Base and Emitter Resistances For SiGe HBTs Using DC Data Only
Authors: Mudholkar Mihir , Mantooth Alan , Niu Guofu , Cressler John
Published: October 2010

A new method to directly extract base and emitter resistance parameters for SiGe HBTs using the Mextram bipolar compact transistor model has been presented. The method only requires a standard forward Gummel measurement and accounts for several second order effects like high-injection base conductivity modulation, Early effect and emitter current crowding. Base and emitter resistance parameters have been extracted over a wide temperature range (300K - 93K) for a first generation 0.5µm SiGe HBT with a peak cut-off frequency of 50 GHz at 300K. The HBT features a heavily doped poly-silicon emitter, an extrinsic base region doped well above the Mott's transition (3e18 cc for boron in silicon) and an intrinsic base region doped very close to the Mott's transition. The extracted parameters have been verified by comparison with several different methods.
2.4/5.7-GHz Dual-Band Dual-Conversion Low-IF Downconverter Using 0.35 μm SiGe HBT Technology
Authors: Syu Jin-Siang , Meng Chinchun , Yu Sheng-Wen , Huang Guo-Wei
Published: October 2010

A 2.4/5.7-GHz dual-band dual-conversion low-IF downconverter is demonstrated using 0.35 μm SiGe heterojunction bipolar transistor (HBT) technology. The first image signal is shifted away from the IF band by a complex Weaver architecture while the second image signal is eliminated by a complex Hartley architecture. The downconverter achieves a 45/44-dB image-rejection ratio of the first image (IRR1) and a 50/48-dB image-rejection ratio of the second image (IRR2) for 2.4/5.7-GHz modes, respectively, when IF frequency ranges from 20 to 40 MHz.
(Invited) Are Si/SiGe Tunneling Field-Effect Transistors a Good Idea?
Authors: Koester Steve , Lauer Isaac , Majumdar Amlan , Cai Jim , Sleight Jeffrey , Bedell Stephen , Solomon Paul , Laux Steve , Chang Leland , Koswatta Siyu , Haensch Wilfried , Tomasini Pierre , Thomas Shawn
Published: October 2010

Tunneling field effect transistors (TFETs) are a device technology that has the potential to achieve sub-60-mV/decade subthreshold slope and therefore could potentially overcome the power / performance bottleneck facing the CMOS industry today. It would be highly desirable to fabricate such devices using Si-based materials due to the proven capability of Si for VLSI circuits. However the large, indirect band gap of Si is not conducive to achieving large band-to-band tunneling currents. This paper presents experimental results on Si/SiGe heterojunction tunneling transistors (HETTs), where it is demonstrated that increasing the heterojunction band offset leads to enhanced device performance. An analysis is also provided addressing whether or not Si-based materials are suitable for TFETs or if material systems with direct band gaps and that allow more aggressive heterostructure engineering will be required to achieve the performance levels necessary for practical applications.
(Invited) Boosting the On-Current of Si-Based Tunnel Field-Effect Transistors
Authors: Verhulst Anne S. , Vandenberghe William G. , Leonelli Daniele , Rooyackers Rita , Vandooren Anne , Pourtois Geoffrey , De Gendt S. , Heyns Marc M. , Groeseneken Guido
Published: October 2010

Tunnel-FETs (TFETs) have the potential for a sub-60 mV/dec subthreshold swing and therefore allow for scaling the supply voltage beyond the 1 V plateau of metal-oxide-semiconductor FETs (MOSFETs). The latter scaling is a necessary condition for a reduction of the power consumption per transistor. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon results in low on-currents. Therefore, the incorporation of heterostructures is proposed. In particular, a germanium-source silicon-channel n-TFET and, as complementary p-TFET, an indium(gallium)arsenide-source silicon-channel TFET reach on-currents comparable to MOSFETs. To beat the MOSFET performance and allow ultra-low voltage operation, additional performance boosters are required. We analyze the impact of the device configuration and of heterostructure strain. The former is illustrated with experimental data of all-silicon FinFET-based TFETs.
Axial Ge/Si Nanowire Heterostructure Tunnel FETs
Authors: Dayeh Shadi A. , Picraux S. Tom
Published: October 2010

The vapor-liquid-solid (VLS) growth of semiconductor nanowires allows doping and composition modulation along their axis and the realization of axial 1D heterostructures. This provides additional flexibility in energy band-edge engineering along the transport direction which is difficult to attain by planar materials growth and processing techniques. We report here on the design, growth, fabrication, and characterization of asymmetric heterostructure tunnel field-effect transistors (HTFETs) based on 100 % compositionally modulated Si/Ge axial NWs for high on-current operation and low ambipolar transport behavior. We discuss the optimization of band-offsets and Schottky barrier heights for high performance HTFETs and issues surrounding their experimental realization. Our HTFET devices with 10 nm PECVD SiNx gate dielectric resulted in a measured current drive exceeding 100 μA/μm (I/πD) and 105 Ion/Ioff ratios.
(Invited) Cyclic Deposition/Etch Processes for the Formation of Si Raised Sources and Drains in Advanced MOSFETs
Authors: Hartmann Jean Michel , Py M. , Morel P. H. , Ernst T. , Prévitali B. , Barnes J.P. , Vulliet N. , Cherkashin N. , Reboh S. , Hyütch M. , Paillard V.
Published: October 2010

We have studied the Cyclic / Deposition Etch (CDE) of Si with either SiH4 or SiH2Cl2 + HCl for the deposition steps and HCl for the etch steps. The HCl etch rate of poly-Si is indeed several times higher than the one of mono-crystalline Si. We have demonstrated that at 650{degree sign}C, 300 Torr, SiH4 / HCl CDE processes were selective versus SiO2 for high numbers of cycles. We have also showed that 20 Torr, SiH2Cl2 + HCl - based CDE processes enabled to selectively grow 85 - 140 nm thick Si Raised S/Ds on each side of multi-bridge channel FETs with Si3N4 internal spacers. Finally, we have demonstrated the efficiency of various CDE process in suppressing mushrooming on top of un-capped poly-Si gates of FD-SOI FETs after the formation of Si RSD ({116} facets at the boundary between the gate stack and the S/D regions and moat recess, however).
(Invited) High-Mobility Ge on Insulator (GOI) by SiGe Mixing-Triggered Rapid-Melting-Growth
Authors: Sadoh Taizoh , Miyao Masanobu
Published: October 2010

High-quality orientation-controlled Ge on insulator (GOI) structures are essential to realize high-performance thin-film transistors (TFTs) and epitaxial templates for multifunctional 3-dimensional large-scale integrated circuits (3D-LSIs). We have investigated the Si-seeding rapid-melting process and demonstrated formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO2 films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The transmission electron microscopy observations revealed no-defects in the laterally grown Ge regions. The Ge layers showed a high hole mobility exceeding 1100 cm2/Vs owing to the high crystallinity. This novel SiGe mixing-triggered growth technique opens up the possibility of the next-generation TFTs and multifunctional 3D-LSIs.
(Invited) Ge Surfaces and Its Passivation by Rare Earth Lanthanum Germanate Dielectric
Authors: Dimoulas Athanasios , Tsoutsou Dimitra , Galata Sotiria , Panayiotatos Yerassimos , Mavrou Georgia , Golias Evangelos
Published: October 2010

Germanium is considered to be an alternative channel material for advanced CMOS devices. Due to its small bandgap and high mobility, it can allow operation of devices at low supply voltage without loss of performance. The main obstacle for implementation of an all-Ge CMOS technology is the frequently observed underperformance of Ge n MOSFETs. Part of the problem could be that acceptor interface states in Ge lie in the low part of the energy gap close to the valence band so that the interface is easily charged negatively affecting transport in the n-channel. Additional and perhaps more severe complications arise from defects generated by poor quality oxides. Improving the quality of GeO2 large progress in Ge n MOS has been made albeit not without concerns about scalability to low equivalent thickness. Rare earth La germanate dielectrics exhibit good passivationg properties probably due to the suppression of harmful reactions of the dielectric with the substrate and maintain these good properties at low equivalent thickness suggesting a good potential for scalability.
Monolayer Passivation of Ge(100) Surface via Nitridation and Oxidation
Authors: Lee Joon S. , Bishop Sarah R. , Kaufman-Osborn Tobin , Chagarov Evgueni , Kummel Andrew C.
Published: October 2010

The monolayer passivation of Ge(100) surface via formation of Ge-N and Ge-O surface species was studied using scanning tunneling microscopy (STM) and density functional theory (DFT). Direct niridation using an electron cyclotron resonance (ECR) plasma source formed an ordered Ge-N structure on a Ge(100) surface at 500oC. DFT calculation found the hydrogen passivation on this Ge-N ordered structure could reduce the bandgap states by decreasing the dangling bonds and the bond strain. Oxidation of Ge(100) using H2O produced an -OH and -H terminated surface with very few Ge ad-atoms, while e-beam evaporation of GeO2 formed semi-ordered Ge-O structures and Ge ad-species at room temperature. Annealing above 300oC formed suboxide rows on both H2O and GeO2 dosed surfaces, and the scanning tunneling spectroscopy (STS) showed that the Fermi level was pinned near the valence band edge on the n-type Ge surfaces covered by suboxides.
(Invited) In Situ XPS in Atomic Layer Deposition of Oxides on Ge (100)
Authors: Swaminathan Shankar , McIntyre Paul C.
Published: October 2010

Atomic layer deposition (ALD) is a film growth method that offers unprecedented control of film thickness, uniformity of deposition and low temperature processing on substrates with complex topography. Because ALD occurs by a series of self-limiting surface reactions of vapor phase precursors, there is great interest in understanding the mechanisms of precursor adsorption and how they affect the structure and properties of ALD-grown films and their interfaces with technologically-relevant substrates. In this paper, we describe experiments in which a differentially-pumped x-ray source and photoelectron spectrometer installed in an ALD chamber is used to probe ALD growth of metal oxide films. This in situ XPS system is capable of collecting data within 10's of seconds of an ALD precursor pulse, without moving the substrate or changing its temperature. An application of this system to oxidant treatment of the initial surface of Ge (100) substrates prior to alumina ALD is also discussed.
(Invited) Formation of Dipole Layers at Oxide Interfaces in High-k Gate Stacks
Authors: Kita Koji , Zhu Li Qiang , Nishimura Tomonori , Nagashio Kosuke , Toriumi Akira
Published: October 2010

The formation of High-k/SiO2 dipole layer is experimentally observed as the flatband voltage shift of MIS capacitors without high-k film thickness dependence. It is also deduced from the band bending of SiO2 and high-k at the interface by using XPS measurements. As a model to explain the driving force to form the dipole, the areal density difference of oxygen atoms at high-k/SiO2 interface is taken account to predict both the direction and magnitude of the dipoles. This is the only model to give a reasonable explanation to the experimentally observed directions of the dipoles.
Control of Gate Metal Effective Work Functions and Interface Layer Thickness by Designing Interface Thermodynamics Based on Heteroatom Incorporation into High-k HfO2 Gate Dielectrics
Authors: Shiraishi Kenji , Hosoi Takuji , Watanabe Heiji , Yamada Keisaku
Published: October 2010

We have proposed a new approach for controlling both gate metal effective work functions and interface layer thickness at the same time based on the incorporation of hetero atoms into HfO2 gate dielectrics. We investigated C atom incorporation into HfO2 by the first principles calculations. The results indicate that additional C atoms in HfO2 can reduce an interfacial SiO2 layer, which also causes modification of a gate metal effective work function. Redesigning interface thermodynamics by incorporating hetero atoms can be a crucial recipe for controlling both gate metal work functions and thickness of interfacial SiO2 layers in high-k gate stacks
(Invited) Strain Engineering for Fully-Depleted SOI Devices
Authors: Khakifirooz Ali , Kulkarni Pranita , Bedell Stephen , Cheng Kangguo , Sadana Devendra K. , Doris Bruce , Shahidi Ghavam
Published: October 2010

Limitations of conventional strain engineering methods for fully-depleted SOI structure are reviewed and methods to extend these approaches to future FDSOI devices are discussed. The application of global strain engineering combined with biaxial to uniaxial strain conversion is shown to be promising. Finally, methods to utilize oxidation-induced strain engineering are introduced.
Strain Stability in Nanoscale Patterned Strained Silicon-On-Insulator
Authors: Moutanabbir Oussama , Reiche Manfred , Hähnel Angelika , Erfurth W. , Tarun A. , Hayazawa N. , Kawata S. , Naumann F. , Petzold M.
Published: October 2010

Nowadays, strain engineering plays a key role in boosting the performance of Si-based nanoelectronics. So far a tremendous progress has been made in establishing methods for strain manipulation in Si nanodevices. This has brought up further challenges in terms of development of reliable probes to characterize the strain on the nanoscale. In this paper, we discuss strain imaging using multi-wavelength micro-Raman spectroscopy. As a model system, we investigate the strain behavior upon nanoscale patterning of ultrathin strained silicon-on-insulator (SSOI). We show that valuable details on the strain depth distribution can be obtained by combining deep UV and visible Raman microprobes. Additionally, we also demonstrate that strain mapping with high lateral resolution can be achieved using UV-Raman with glycerin-immersed high numerical aperture objective lens. Results from nano-beam electron diffraction and peak-pairs analysis of high-angle annular dark field images are also presented. Detailed 3D finite element simulations of edge-induced strain relaxation in SSOI nanostructures augment our experimental studies.
Effects of Growth and Surface Cleaning Conditions on Strain Relaxation on SiGe Films beyond a Critical Thickness on Si(001) Substrate
Authors: Park Jeongwon , Ishii Masato , Balasubramanian Ramachandran , Kim Yihwan , Kuppurao Satheesh
Published: October 2010

We describe our work investigating strain relaxation behavior of epitaxial Si0.7Ge0.3 films on silicon (001) substrates beyond the critical thickness by using High Resolution X-Ray Diffraction (HRXRD). The effects of thickness, growth rate, dopant concentration and surface cleaning on strain relaxation on the SiGe films were investigated.
(Invited) Assessment of Ge1-xSnx Alloys for Strained Ge CMOS Devices
Authors: Takeuchi Shotaro , Shimura Yosuke , Nishimura T. , Vincent B. , Eneman G. , Clarysse T. , Demeulemeester J. , Temst K. , Vantomme A. , Dekoster J. , Caymax Matty , Loo Roger , Nakatsuka Osamu , Sakai A. , Zaima S.
Published: October 2010

In this paper, we propose the fabrication of whole strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation, in situ Ga doping, and Ni(Ge1-ySny) formation) is characterized. A low thermal budget has been determined for those processes on Ge1-xSnx alloys: temperatures must be lower than 600{degree sign}C for B activation and lower than 450{degree sign}C for Ni(Ge1-ySny) formation.
(Invited) Characterizations of Direct Band Gap Photoluminescence and Electroluminescence from epi-Ge on Si
Authors: Cheng Szu-Lin , Shambat Gary , Lu Jesse , Yu Hyun-Yong , Saraswat Krishna C. , Vuckovic Jelena , Nishi Yoshio
Published: October 2010

Characterizations of direct gap emission from epi-Ge through both optical and electrical pumping were studied for the application of Si compatible light sources such as on-chip optical interconnect. In-situ doping technique with PH3 during the epi-Ge growth was first applied to achieve high n-type doping concentrations. Photoluminescence (PL) measurements show that the direct band emission of Ge increases with higher doping concentration. This confirms that the Ge direct radiative recombination efficiency can be improved by band filling of electrons. A Ge n+/p light emitting diode (LED) on a Si substrate was then fabricated to study the electroluminescence (EL) properties related to the band filling. Direct band gap EL at 1.6 μm was also obtained from this Ge LED. Unlike ordinary electrically pumped devices, this LED shows a superlinear luminescence enhancement at high current. Thermal enhancement effects observed in temperature dependent EL spectra show the capability of this device to be operated at room temperature or above.
Extrinsic Effects of Indirect Radiative Transition of Ge
Authors: Jan Sun-Rong , Lee Cheng-Han , Cheng Tzu-Huan , Chen Yen-Yu , Peng K.-L. , Chan S. T. , Liu C. W. , Yamamoto Yuji , Tillack Bernd
Published: October 2010

The effects of surface roughness and defects on Ge indirect radiative transition was observed. The oxide roughness scattering can conserve the momentum during electron-hole recombination and enhance the indirect radiative transition. The indirect transition is affected more sensitively by the non-radiative transition resulting from defects in Ge. The passivation of GeO2 on Ge also decreases the surface defect density and leads to intensity enhancement of photoluminescence.
Enhancements of Direct Band Radiative Recombination from Ge
Authors: Cheng Tzu-Huan , Peng K.-L. , Ko C. -Y. , Chen C.-Y. , Chan S. T. , Liu C. W.
Published: October 2010

Both direct and indirect transitions of photoluminescence and electroluminescence are observed in a Ge n+p diode. The relative intensity of direct radiative recombination with respect to indirect radiative recombination increases with the increase in the n type doping level, optical pumping power, injection current density, temperature, and strain. The increase in electron population in the direct valley is responsible for the enhancement. The spectra can be fitted by the combination of direct and indirect transition models. The reduction in bandgap difference between the direct and indirect valleys by biaxial tensile strain increases the electron population in the direct valley, and further enhances the direct transition. The bandgap reduction in the direct and indirect valleys can be extracted from the photoluminescence spectra and is consistent with the calculations using k. p and deformation potential methods for conduction bands and valence bands, respectively.
Kinetic Model of SiGe Selective Epitaxial Growth Using RPCVD Technique
Authors: Kolahdouz Mohammadreza , Maresca Luca , Ghandi Reza , Khatibi Ali , Radamson Henry H.
Published: October 2010

Recently, selective epitaxial growth (SEG) of B-doped SiGe layers has been used in recessed source/drain (S/D) of pMOSFETs. The uniaxial induced strain enhances the carrier mobility in the channel. In this work, a detailed model for SEG of SiGe has been developed to predict the growth rate and Ge content of layers in dichlorosilane(DCS)-based epitaxy using a reduced-pressure CVD reactor. The model considers each gas precursor contributions from the gas-phase and the surface. The gas flow and temperature distribution were simulated in the CVD reactor and the results were exerted as input parameters for Maxwell energy distribution. The diffusion of molecules from the gas boundaries was calculated by Fick's law and Langmuir isotherm theory (in non-equilibrium case) was applied to analyze the surface. The pattern dependency of the selective growth was also modeled through an interaction theory between different subdivisions of the chips. Overall, a good agreement between the kinetic model and the experimental data were obtained.
(Invited) Atomic Control of Doping during Si Based Epitaxial Layer Growth Processes
Authors: Tillack Bernd , Yamamoto Yuji , Murota Junichi
Published: October 2010

Atomic-level processing based on surface reaction control is used for B and P doping during Si, SiGe or Ge epitaxy. The concept of atomic layer processing is base on the separation of adsorption of the dopant gases from the layer growth. By this way the doping process is controlled by surface adsorption / desorption of dopant gas mainly. For B atomic layer doping of SiGe and pure Ge using B2H6, high doping levels and steep doping profiles have been reached. The process was found to be self-limited at ~100oC indicating preferred adsorption of B2H6 on Si and Ge sites and suppression of B cluster formation. For P atomic layer doping on Si and SiGe self-limitation of the process has been observed for temperatures between 200-600oC allowing very precise dopant dose and location control.
(Invited) Selective Epitaxial Growth (SEG) of Highly Doped Si:P on Source/Drain Areas of NMOS Devices Using Si3H8/PH3/Cl2 Chemistry
Authors: Bauer Matthias , Thomas Shawn
Published: October 2010

In this paper we demonstrate the successful integration of in-situ doped Si:P epitaxially grown into the source/drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process employing a Si3H8/PH3/Cl2 based chemistry. A distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We report on material characterization results of the Si:P selective epitaxial growth (SEG). An optimized Si:P SEG process with a SEG rate of ~25 nm/min enables a 80-170s short deposition for typical epitaxial layers (35-70 nm), well suitable for high volume manufacturing (HVM). By integrating an isothermal in-situ removal of Si0.65Ge0.35 (protecting/covering the NMOS areas) with a high etch rate selectivity against the underlying thin SOI at process temperature allows to eliminate the in-situ H2 prebake and the cool-down to process temperature, significantly reducing recipe overhead and the need for a separated, dedicated pre-clean module.
Surface Orientation Effects on SiGe Quantum Dots and Nanorings Formation
Authors: Lee Cheng-Han , Tu Wen-Hsien , Lin Cheng-Ming , Chang Hung-Tai , Lee Sheng-Wei , Liu C. W.
Published: October 2010

Surface orientation effects on SiGe quantum dots and nanorings have been investigated in this work. The base shapes of SiGe QDs and nanorings can be controlled by different surface orientation. Moreover, the hydrogen desorption rate is different in three kinds of surface orientation. The surface diffusion, which plays an important role in Ge out-diffusion mechanism, is dominated by the hydrogen desorption rate, and thus the formation rate of SiGe nanorings becomes different.
Self-Align Formation of Si Quantum Dots
Authors: Makihara Katsunori , Ikeda Mitsuhisa , Deki Hidenori , Ohta Akio , Miyazaki Seiichi
Published: October 2010

One-dimensionally aligned Si quantum dots (Si-QDs) on ultrathin SiO2 have been prepared by controlling the selective growth conditions of low-pressure chemical vapor deposition (LPCVD) using pure SiH4 or 5% GeH4 diluted with He, the oxidation of the dots and the selective etching. Atomic force microscopy (AFM) observations and X-ray photoelectron spectroscopy (XPS) measurements confirm the selective etching of Ge oxide on pre-grown Si-QDs by annealing under vacuum condition and the subsequent selective growth of 2nd Si-QDs on the 1st Si-QDs. The temporal change in surface potential of the self-aligned Si-QDs after one electron injection from the tip to the dots changed in a stepwise manner with time due to electron transfer from the 2nd-dot to the 1st-dot. For the semitransparent Au-gate diodes, when carriers were injected to self-aligned Si-QDs from n-Si(100) substrate for electrons and from Au top electrode for holes, electroluminescence (EL) in the near-infrared region at room temperature becomes observable with an increase in the current at positive gate biases over the thresholds. It should be noted that the self-aligned Si-QDs enhance the emission intensity by a factor of ~2 compared with Si-QDs stacked structure under the same current density. This result indicates that self-aligned structure is suitable for an increase in recombination efficiency for EL.
(Invited) Fabrication and Properties of Abrupt Si-Ge Heterojunction Nanowire Structures
Authors: Wen Cheng-Yen , Reuter Mark , Tersoff Jerry , Stach Eric , Ross Frances
Published: October 2010

Fabrication of Si-Ge nanowire heterostructures offers great design flexibility in device applications, provided the interfaces are defect-free and compositionally abrupt. We use in-situ transmission electron microscopy to study nanowire growth, and find that abrupt Si-Ge interfaces can be fabricated in nanowires by a growth method that uses a solid AlAu2 catalyst. Growth of uniform segments of SiGe alloy in Si nanowires with sharp interfaces can also be realized using this method. We present in-situ measurements of nanowire growth kinetics and discuss the strain distribution and thermal stability in Si/Ge and Si/Ge/Si nanowire junction structures.
Ge/Si Core/Multishell Heterostructure FETs
Authors: Dayeh Shadi A. , Picraux S. Tom
Published: October 2010

Concentric heterostructured materials provide numerous design opportunities for engineering strain and interfaces, as well as tailoring energy band-edge combinations for optimal device performance. Key to the realization of such novel device concepts is the complete understanding and full control over their growth, crystal structure, and hetero-epitaxy. We report here on a new route for synthesizing Ge/Si core/multi-shell heterostructure nanowires that eliminate Au seed diffusion on the nanowire sidewalls by engineering the interface energy density difference. We show that such control over core/shell synthesis enable experimental realization of heterostructure FET devices beyond those available in the literature with enhanced transport characteristics. We provide a side-by-side comparison on the transport properties of Ge/Si core/multi-shell nanowires grown with and without Au diffusion and demonstrate heterostructure FETs with drive currents that are ~ 2X higher than record results for p-type FETs.
Vapor-Liquid-Solid Growth of Si1-xGex and Ge/Si1-xGex Axial Heterostructured Nanowires
Authors: Minassian Sharis , Weng Xiaojun , Redwing Joan
Published: October 2010

The effect of growth conditions on the composition of Si1-xGex nanowires fabricated by vapor-liquid-solid growth using Si2H6 and GeH4 sources was investigated. The use of Si2H6 resulted in an increase in Si incorporation in the Si1-xGex nanowires at lower growth temperatures compared to SiH4 which is more commonly used. A wide range of Ge compositions from ~20-80% was achieved by changing the inlet gas ratio at a constant temperature in the range of 350-425ºC. Using these conditions, Ge/Si1-xGex axial heterostructured nanowires were also fabricated at 375ºC with Ge compositions of 92% and 66% in the SiGe segment and the morphology and interfacial compositional profile of the nanowires were examined.
(Invited) Practical Strategies for Tuning Optical, Structural and Thermal Properties in Group IV Ternary Semiconductors
Authors: Chizmeshya A. V. , Kouvetakis John
Published: October 2010

Recently synthesized SiGeSn ternary alloys offer the possibility of varying their composition and thus their optical behavior while maintaining the lattice parameter at a constant value. In this paper we use theoretical calculations to show that the bandgap of Ge1-X(Si0.8Sn0.2)X derivatives can be varied from 0.8 to 1.1 eV (X =0 - 0.5) at a fixed lattice constant identical to Ge. We also show that Sn clustering in the diamond cubic structure can alter both the magnitude and character (direct/indirect) of the bandgap in these systems, particularly at high Sn concentrations. First principles thermochemistry simulations were finally used to calculate the Gibbs free energy and demonstrate that the mixing entropy is responsible for the stabilization of the ternary alloys with respect to GeSn binaries of the same Sn content consistent with experimental observations.
(Invited) Performance and Reliability of a 25Gb/s Ge Waveguide Photodetector Integrated in a CMOS Process
Authors: Sahni Subal , Song Dan , Sharp Michael , Kucharski Daniel , Guckenberger Drew , Masini Gianlorenzo
Published: October 2010

This paper describes the monolithically integrated Germanium photo-detectors used by Luxtera in their 4x10Gbps CMOS photonics based transceiver products. When used with optimized receivers, these detectors show exceptional optical sensitivities of ~-24dBm at 10Gbps & 10-12 BER and also support open eyes up to 25Gbps. Aging tests have also demonstrated that these detectors exhibit a very high level of reliability.
Near IR Photodiodes with Tunable Absorption Edge Based on Ge1-y Sny Alloys Integrated on Silicon
Authors: Mathews Jay , Roucka Radek , Weng Change , Beeler Richard , Tolle John , Menéndéz Jose , Kouvetakis John
Published: October 2010

Ge1-ySny materials represent a viable path to silicon-based electronic devices for optical communications. In this paper, we present the results of heterostructure photodiodes fabricated from Ge0.99Sn0.01 films grown on Si(100) substrates. The results are compared with those of similarly fabricated devices from pure Ge and Ge0.98Sn0.02 to demonstrate the tunability of device response through precise control of material composition.
(Invited) Si, SiGe, Ge, and III-V Semiconductor Nanomembranes and Nanowires Enabled by SiGe Epitaxy
Authors: Orlowski Marius , Ndoye Coumba , Liu Tong , Hudait Mantu
Published: October 2010

SiGe epitaxy in conjuction with selective etching lends itself as an excellent method for manufacturing of nanomembranes and nanowires for a variety of semiconductor materials and nano-geometries. Early device application of this technique has been demonstrated for the device architecture of Silicon-On-Nothing (SON) MOSFET and localized SON MOSFET allowing accommodation of a SOI-type MOSFET on a bulk Si wafer. In the meantime, this approach has been successfully extended to multichannel and multi-nanowire devices. Together with the availability of thin Ge layers (e.g. by virtue of Ge condensation), SiGe epitaxy opens up the possibility of a heterogenous co-integration of high efficiency III-V multijunction solar cells, III-V complementary logic, thermovoltaic device structures, lasers, modulators and detectors with Si-based electronics collocated on the same Si substrate. SiGeC epitaxial layers offer an additional engineering window for lattice mismatch and stress control, as well for achieving desirable selectivities of the required selective etches. Furthermore, the nanomembranes and nanowires made available by SiGe epitaxy and selective etches on ubiquitous Si substrates are excellent vehicles for exploration of the differences between the material properties of 3D (bulk)) and 2D (nanomembranes) and 1D (nanowire) systems.
Diffusion and Interface Segregation of Phosphorus and Boron in Bulk Germanium, Germanium Nanomembranes, and Nanowires
Authors: Liu Tong , Ndoye Coumba , Orlowski Marius
Published: October 2010

This work investigates the diffusion and segregation of boron and phosphorus in bulk germanium, germanium membrane and nanowire. The diffusion simulation indicates the phosphorus diffusion is first enhanced in Ge nanomembrane due to preservation of high dopant concentration. However, the segregation at Ge-SiO2 interfaces slows down the diffusion of phosphorus because it results in the reduction of dopant dose. The lateral diffusion of boron does not change much in bulk and nanomembrane structures and it is hardly impacted by the interface segregation.
Elastically Strain-Sharing Si(110) Nanomembranes
Authors: Paskiewicz Deborah M. , Scott Shelley A. , Savage Donald E. , Lagally Max G.
Published: October 2010

Defect-free, smooth, tensilely strained Si(110) has been fabricated via elastic strain relaxation of trilayer Si/SiGe/Si(110) nanomembrane heterostructures grown on silicon-on-insulator (SOI), in which the middle layer is compressively strained. We release these trilayer structures via selective etching to allow elastic strain sharing between the Si/SiGe/Si(110) layers, thus creating tensilely strained Si(110). We use low-temperature molecular beam epitaxy (MBE) to grow the SiGe and top Si layers to create smooth films and incorporate more strain in the Si(110) layers; the low growth temperatures suppress relaxation, allowing for thicker SiGe(110) films. The strain in the Si(110) layers can be controlled with elastic strain engineering up to ~0.7%.
(Invited) Epitaxial Growth of III-Nitrides on Silicon Substrates
Authors: Degroote Stefan , Leys Maarten , Cheng Kai , Sijmus Bram , Derluyn Joff , Borghs Gustaaf , Germain Marianne
Published: October 2010

Hetero epitaxial structures with strained layers are widely used in electronic and optoelectronic semiconductor devices. Over the last decades the group III-Nitride semiconductor materials have been extensively used for light emitting applications and are nowadays emerging as promising candidates for high power electronic applications. As no native substrates are available for the III-Nitrides, growth is performed on foreign substrates such as sapphire, silicon carbide or silicon. III-Nitride epi layers grown on Silicon substrates offer a lower cost technology compared to other substrates because of the scalability towards larger wafer size and the leverage on Si technology. However, the large thermal mismatch between III-Nitrides and Silicon requires advanced deposition schemes to allow compensating for the huge tensile thermal stresses and to reduce the dislocation density of these materials.
(Invited) Direct Heterointegration of III-V Materials on Group IV Substrates
Authors: Ahmari David A. , McDermott Brian , Thomas Shawn , Roof Bradley , Hartmann Quesnell , Li Xiuling
Published: October 2010

This work describes using metal-organic chemical vapor deposition (MOCVD) to directly deposit III-V materials on Si/Ge-based substrates, with the primary focus being the methodology used to develop a manufacturable heterointegration process.