Ω-Gate Nanowire P-FET with cSiGe Channel Epitaxied on Strained-SOI Substrates
Authors: Nguyen Phuong , Barraud Sylvain , Cassé Mikael , Pelloux-Prayer Johan , Tabone Claude , Hartmann Jean-Michel , Arvet Christian , Bernier Nicolas , Hutin Louis , Ecarnot Ludovic , Maleville Christophe , Nguyen Bich-Yen , Mazure Carlos , Faynot Oliver , Vinet Maud 
Published: February 2020

Introduction.Aggressively scaled Si NanoWire (NW) transistors have already been fabricated and their electrical properties assessed [1-3]. In order to further continue the Moore’s law, strain-induced performance enhancement is needed for both n and p type Field Effect Transistors (FETs). In a previous work, we demonstrated high-performance uniaxial tensely-strained NW n-type FETs down to 10nm gate length [4]. Symmetrically, compressively-strained SGOI [5-8] yielded improved short-channel performances for p-type FETs. In this work, we propose to integrate compressive SiGe (p-FETs) on strained-SOI substrates for a future hybrid CMOS integration with sSi channels for n-FETs and cSiGe channels for p-FETs.

Devices Fabrication. The fabrication of NW p-FETs started with the epitaxy of 10nm thick Si0.7Ge0.3 films capped by 2nm of Si on 300mm s-SOI substrates (~1.4GPa biaxial tensile strain) with the following thicknesses: 4nm sSi and 145nm buried oxide. P-type transistors were then processed on top of such stacks and on regular SOI substrates (as references) with channels along the <110> directions. Gate length LG scaled down to 20nm were achieved after patterning. The Si and Si0.7Ge0.3/sSi thickness (HNW) under the HfSiON/TiN gate stack are around 10.5nm and 12.5nm respectively. For Si0.7Ge0.3/sSi transistors, the Si0.7Ge0.3 layer in the source/drain (S/D) regions was recessed down to the sSi etch-stop layer just after spacer etching. Then in-situ boron-doped Si0.7Ge0.3 raised S/Ds were used to thicken by 18nm and 25nm the access regions of the reference Si and the Si0.7Ge0.3/sSi devices, respectively. A second offset spacer was fabricated prior to S/D implantations, activation spike anneal and silicidation (NiPtSi silicide). Finally, tungsten contacts and standard Cu back-end-of-the-line process were used.

Results. Long-channel hole mobility was extracted in Si0.7Ge0.3/sSi devices with NW widths varying from 10µm down to 20nm. As compared to SOI references, a higher hole mobility is observed for wide devices (W=10µm) but a lower hole mobility is obtained when reducing W to 20nm. Indeed, for wide devices, the biaxial compressive strain removes the degeneracy of the valence band and modifies the band structure in a manner that reduces the hole effective mass. On the contrary, the tensile strain raises in the narrowest devices the heavy hole subbands, which degrades mobility. At short LG, the strain induced by the cSiGe channels epitaxied on sSOI, the SiGe:B S/D and the CESL is analyzed and characterized. The top part of Fig. 1 shows a cross-sectional TEM image of a Si0.7Ge0.3/sSi device. The strain has been investigated using the geometric phase analysis (GPA) of high-angle annular dark-field images (HAADF). The strain distribution map is extracted with high resolution scanning transmission electron microscopy (STEM) along the S-D direction. As expected, a compressive strain is induced close to the Si0.7Ge0.3:B S-Ds (green color in Fig. 1). This results in enhanced short-channel performances. The tensile strain of sSOI substrate is then compensated and the saturation current definitely improved compared to SOI references for the same 0.9V over drive gate voltage (Fig. 2). Obviously the cSiGe channel also reduces the VTH and contributes to improved performances at VDD[9].

Finally, the electrical properties of Ω-gate Si0.7Ge0.3/sSi NW p-FETs are systematically examined for a wide range of NW widths (20nm<W<10µm) and gate lengths (20nm<LG<10µm). We show that the tensile strain can be compensated by Si0.7Ge0.3:B S-Ds at short gate length. A higher Ge concentration in the channel will allow to further improve p-FET performances on strained-SOI substrates.

References

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[4] S. Barraud et al., VLSI, p.230 (2013)

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[7] P. Nguyen et al., S3S Conference (2014)

[8] P. Nguyen et al., IEDM, p.309 (2014)

[9] Y.-M. Niquet et al., Nanoletter 12, p.3545 (2012)

Figure 1