bluuebunny/crossref_metadata_2025 huggingface dataset:
4H-SiC Homoepitaxial Growth on Substrates with Different Off-Cut Directions
Authors: Kallinger Birgit , Thomas Bernd , Berwian Patrick , Friedrich Jochen , Trachta Gerd , Weber Arnd Dietrich
Published: March 2011

Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.
Proton Irradiation of 4H-SiC Ultraviolet Single Photon Avalanche Diodes
Authors: Gaskill D. Kurt , Hu Jun , Xin X. , Zhao Jian Hui , VanMil Brenda L. , Myers-Ward Rachael L. , Eddy Charles R.
Published: March 2011

The effects of proton irradiation on uv 4H-SiC single photon avalanche photodiodes (SPADs) are reported. The SPADs, grown by chemical vapor deposition, were designed for uv operation with dark count rates (DCR) of about 30 kHz and single photon detection efficiency (SPDE) of 4.89%. The SPADs were irradiated with 2 MeV protons to a fluence of 1012 cm-2. After irradiation, the I-V characteristics show forward voltage (<1.9 V) generation-recombination currents 2 to 3 times higher than before irradiation. Single photon counting measurements imply generation-recombination centers created in the band gap after irradiation. For threshold voltage ranging from 23 to 26 mV, the 4H-SiC SPAD showed low DCR (<54 kHz) and high SPDE (>1%) after irradiation. The SPADs demonstrated proton radiation tolerance for geosynchronous space applications.
Avalanche Diodes with Low Temperature Dependence in 4H-SiC Suitable for Parallel Protection
Authors: Nguyen Duy Minh , Pâques Gontran , Dheilly Nicolas , Raynaud Christophe , Tournier Dominique , Konrath Jens Peter , Scharnholz Sigo , Planson Dominique
Published: March 2011

Avalanche diodes have been fabricated on 4H-SiC substrate. These diodes show an abrupt avalanche voltage of about 59 V which corresponds to the calculated theoretical one using our previously determined impact ionization coefficients. This avalanche voltage increases by as small as 3.7 mV/K over the investigated temperature range (150K-420K).
Low Switching Energy 1200V Normally-Off SiC VJFET Power Modules
Authors: Sheridan David C. , Ritenour Andrew , Bondarenko Volodymyr , Casady Jeff B. , Kelley Robin L.
Published: March 2011

This work presents the progress in developing an all SiC based power module for use in high frequency and high efficiency applications. Using parallel combinations of 1200V enhancement mode SiC VJFETs (36mm2) and Schottky diodes (23mm2), a total on-resistance of only 10mOhm (2.7m-cm2) was achieved at ID=100A in a commercially available standard module configured as a half-bridge circuit. Careful attention to module layout, gate driver design, and the addition of optimized snubbers resulted in excellent switching waveforms with low total switching losses of 1.25mJ when switching 100A at 150oC.
1200V SiC JFET in Cascode Light Configuration: Comparison versus Si and SiC Based Switches
Authors: Björk Fanny , Treu Michael , Hilsenbeck Jochen , Kutschak M.A. , Domes Daniel , Rupp Roland
Published: March 2011

A 1200 V SiC JFET has been demonstrated to achieve ultra-low switching losses ten times lower than for industrial grade 1200V Si IGBT. The low switching losses are also shown to compete with the fastest 600V class MOSFET in the market, yielding 1.1% higher PFC stage efficiency for 340 kHz switching frequency, when same device on-resistances were measured. The proposed normally-on JFET also differentiates over the IGBT by its purely Ohmic output characteristics without any voltage threshold, and by a monolithically integrated body diode with practically zero reverse recovery. In this paper we outline as well how the other pre-requisites for a 1200 V SiC switch in applications such as photovoltaic systems and UPS can be fulfilled by the proposed JFET solution: long-term reliability, product cost optimization by low specific on-resistance combined with reasonable process window expectations. Finally, a normally-off like safe operation behavior is ensured by a dedicated driving scheme utilizing a low-voltage Si MOSFET as protection device at system start-up and for system failure conditions.
Chloride-Based CVD at High Rates of 4H-SiC on On-Axis Si-Face Substrates
Authors: Leone Stefano , Lin Yuan Chih , Beyer Franziska Christine , Andersson Sven , Pedersen Henrik , Kordina Olof , Henry Anne , Janzén Erik
Published: March 2011

The epitaxial growth at 100 µm/h on on-axis 4H-SiC substrates is demonstrated in this study. Chloride-based CVD, which has been shown to be a reliable process to grow SiC epitaxial layers at rates above 100 µm/h on off-cut substrates, was combined with silane in-situ etching. A proper tuning of C/Si and Cl/Si ratios and the combination of different chlorinated precursors resulted in the homoepitaxial growth of 4H-SiC on Si-face substrates at high rates. Methyltrichlorosilane, added with silane, ethylene and hydrogen chloride were employed as precursors to perform epitaxial growths resulting in very low background doping concentration and high quality material, which could be employed for power devices structure on basal-plane-dislocation-free epitaxial layers.
Instability of 4H-SiC MOSFET Characteristics due to Interface Traps with Long Time Constants
Authors: Yano Hiroshi , Oshiro Yuki , Okamoto Dai , Hatayama Tomoaki , Fuyuki Takashi
Published: March 2011

Instability of metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics was evaluated by DC and pulse current-voltage (I-V) measurements. MOSFETs with nirided gate oxides were fabricated on C-face 4H-SiC. Their interfaces have near interface traps (NITs) with long time constants, depending on the cooling down process after nitridation. Such devices exhibited a large hysteresis in DC I-V and a large transient current in pulse I-V measurements. These phenomena can be explained by the charge state of NITs due to capture/emission of electrons in the channel.
1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)
Authors: Kono Hiroshi , Suzuki Takuma , Takao Kazuto , Furukawa Masaru , Mizukami Makoto , Ota Chiharu , Harada Shinsuke , Senzaki Junji , Fukuda Kenji , Shinohe Takashi
Published: March 2011

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.
Design and Yield of 9 kV Unipolar Normally-ON Vertical-Channel SiC JFETs
Authors: Veliadis Victor , Stewart Eric J. , Hearne Harold , McNutt Ty , Chang W. , Snook Megan , Lelis Aivars J. , Scozzie Charles
Published: March 2011

Normally-ON 9.1 kV (at 0.1 mA/cm2), 1.52 x 10-3 cm2 active-area vertical-channel SiC JFETs (VJFETs), were fabricated at a 52% yield with no epitaxial regrowth and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped sidewall. The VJFETs exhibit low gate-to-source leakage currents of less than 1 nA up to VGS = -60 V, and sharp onsets of breakdown occurring at VGS ~ -80 V. The gate-to-source and gate-to-drain diodes turn on at 2.75 V, with the latter diode exhibiting higher resistance due to the thick epitaxial drift layer. To realize unipolar operation with low on-state resistance, the VJFET is designed very normally-ON which minimizes the channel resistance contribution. Consequently, threshold voltages are in the -3 V to -4.5 V range and transconductance is relatively low at < 0.36 mS. At a gate bias of 0 V, the VJFETs output a drain current of 73 mA with a forward drain voltage drop of 5 V (240 W/cm2), a specific on-state resistance of 104 mΩ-cm2, and a current gain of ID/IG = 6.4 x 109. Thus, these VJFETs are capable of efficient power switching, i.e., high current-gain voltage-controlled operation at a low unipolar resistance.
Optimization of SiC MESFET for High Power and High Frequency Applications
Authors: Ejebjörk Niclas , Zirath Herbert , Bergman Peder , Magnusson Björn , Rorsman Niklas
Published: March 2011

SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.
Effects of Nitrogen Doping on Basal Plane Dislocation Reduction in 8° Off-Cut 4H-SiC Epilayers
Authors: Wheeler Virginia D. , VanMil Brenda L. , Myers-Ward Rachael L. , Chung S. , Picard Yoosuf N. , Skowronski Marek , Stahlbush Robert E. , Mahadik Nadeemullah A. , Eddy Charles R. , Gaskill D. Kurt
Published: March 2011

The effectiveness of an in-situ growth interrupt in nitrogen doped 8° off-cut epilayers was investigated using ultraviolet photoluminescence imaging. Low-doped n-type epilayers (<1016 cm-3) exhibited an abrupt increase in BPD to TED conversion at the growth interrupt and achieved 96-99% conversion overall (< 10 BPDs/cm-2), while high-doped epilayers had minimal conversion at the interrupt (< 1%) and overall (< 30%). This large discrepancy suggests nitrogen prohibits or alters the conversion mechanism at the growth interrupt. Therefore, a novel SEM technique was developed to "freeze-in" the interface morphology and help elucidate the conversion mechanism. Preliminary results suggest that preferential etching at the point of BPD intersection with the surface is greatly reduced in highly doped layers, which inhibits the conversion mechanism.
4kV Silicon Carbide MOSFETs
Authors: Stum Zachary , Bolotnikov A.V. , Losee Peter A. , Matocha Kevin , Arthur Steve , Nasadoski Jeff , Rao R. Ramakrishna , Saadeh O.S. , Stevanovic Ljubisa , Myers-Ward Rachael L. , Eddy Charles R. , Gaskill D. Kurt
Published: March 2011

Doubly-implanted SiC vertical MOSFETs were fabricated displaying a blocking voltage of 4.2kV and a specific on-resistance of 23 mΩ-cm2, on a 4.5mm x 2.25mm device. Design variations on smaller (1.1mm x 1.1mm) devices showed on-resistance as low as 17 mΩ-cm2 with a blocking voltage of 3.3kV. Analysis is presented of the on-resistance and temperature dependence (up to 175°C), as well as switching performance. Switching tests taken at 1000V and 6A showed turn-on and turn-off transients of approximately 20-40ns.
3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
Authors: Kobayashi Motoki , Uchida Hidetsugu , Minami Akiyuki , Sakata Toyokazu , Esteve Romain , Schöner Adolf
Published: March 2011

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.
Comparison of Total Losses of 1.2 kV SiC JFET and BJT in DC-DC Converter Including Gate Driver
Authors: Lim Jang Kwon , Tolstoy Georg , Peftitsis Dimosthenis , Rabkowski Jacek , Bakowski Mietek , Nee Hans Peter
Published: March 2011

The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5•104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.
Extraordinary Characteristics of 4H-SiC Trench MOSFETs on Large Off-Axis Substrates
Authors: Ueoka Yoshihiro , Yano Hiroshi , Okamoto Dai , Hatayama Tomoaki , Fuyuki Takashi
Published: March 2011

We investigated electrical properties of 4H-SiC trench metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on (000_,1) C-face substrates with various off-axis angles. Off-axis angles and directions are 4o, 8o, and 15o towards [__,1120] and 8o towards [1_,100] directions. Most trench MOSFETs showed good on-state performance. Peculiar characteristics that field-effect mobility was 103 cm2/Vs in spite of a relatively high acceptor concentration of 1 × 1017 cm−3 in the channel region were observed for trench MOSFET on 15o-off substrates. From crystallographic analysis, this face is (11_,20) with 15o off towards [000_,1] direction. We can expect that this face has quite good MOS interface properties.
Reduction of the Surface Density of Single Shockley Faults by TCS Growth Process
Authors: Canino Andrea , Camarda Massimo , La Via Francesco
Published: March 2011

Spatially resolved micro-photoluminescence has been used to study the Single Shockley faults surface density and properties on 4H-SiC epitaxial layers. The improvement of quality of epitaxial layers due to the chemical vapor deposition process has been studied by measuring the reduction of mean density of Single Shockley faults. The change of faults density has been correlated to the different precursor gas used for the growth. In fact trichlorosilane has been used instead of silane. The change of precursor led to two different advantages: the reduction of basal plane dislocation surface density and the capability to increase the growth rate of the process. Both these features allow reducing the density of Single Shockley faults.
Comparison of Inversion Electron Transport Properties of (0001) 4H and 6H-SiC MOSFETs
Authors: Naik Harsh , Chow T. Paul
Published: March 2011

The effect of using two different polytypes, 4H-SiC and 6H-SiC, on the performance of (0001) SiC MOSFETs has been studied. 4H-SiC and 6H-SiC MOSFETs have been fabricated with deposited gate oxides followed by oxidation in dry O2 or NO. Device parameters, particularly field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. We have also compared the mobility-limiting mechanisms of (0001) 4H and 6H-SiC MOSFETs and found that inversion mobility can be further improved in 4H-SiC, but not 6H-SiC.
1200 V SiC BJTs with Low VCESAT and High Temperature Capability
Authors: Domeij Martin , Lindgren Anders , Zaring Carina , Konstantinov Andrei O. , Gumaelius Krister , Grenell Hakan , Keri Imre , Svedberg Jan Olov , Reimark Mats
Published: March 2011

Vertical epitaxial NPN SiC BJTs for 1200 V rating were fabricated. Very low collector-emitter saturation voltages VCESAT=0.5 V at IC=6 A (JC=140 A/cm2) and T=25 °C and VCESAT=1.0 V at IC=6 A and T=250 °C were measured. The common emitter current gain at IC=6 A is 71 at T=25 °C and 32 at T=250 °C, respectively. A SPICE model was developed for the BJT including the parasitic capacitances of the internal pn junctions, as well as temperature dependence of the current gain and the collector series resistance. The IC-VCE characteristics of the BJT are in good agreement with the SPICE model between 25 °C and 250 °C. Fast switching measurements were performed showing a VCE voltage fall-time of 22 ns and a VCE voltage rise-time of 11 ns.
Improved Current Gain in 4H-SiC BJTs Passivated with Deposited Oxides Followed by Nitridation
Authors: Miyake Hiroki , Kimoto Tsunenobu , Suda Jun
Published: March 2011

We report the improvement of current gain in 4H-SiC bipolar junction transistors (BJTs) by using deposited oxides as a surface passivation layer. Various post-deposition annealing processes were investigated. We successfully demonstrated SiC BJTs with a high current gain (β) of 86 using deposited oxides annealed in NO. This is 70% higher current gain compared with that of BJTs with the same structure with conventional thermally-grown oxides.
Current Gain Degradation in 4H-SiC Power BJTs
Authors: Buono Benedetto , Ghandi Reza , Domeij Martin , Malm B. Gunnar , Zetterling Carl Mikael , Östling Mikael
Published: March 2011

SiC BJTs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.
High Voltage, Low On-Resistance 4H-SiC BJTs with Improved Junction Termination Extension
Authors: Ghandi Reza , Buono Benedetto , Domeij Martin , Zetterling Carl Mikael , Östling Mikael
Published: March 2011

In this work, implantation-free 4H-SiC bipolar transistors with two-zone etched-JTE and improved surface passivation are fabricated. This design provides a stable open-base breakdown voltage of 2.8 kV which is about 75% of the parallel plane breakdown voltage. The small area devices shows a maximum dc current gain of 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4 mΩ•cm2. The large area device shows a maximum dc current gain of 52 at Ic = 9.36 A (JC=312 A/cm2) and VCESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ•cm2. Also these devices demonstrate a negative temperature coefficient of the current gain (β=26 at 200°C) and positive temperature coefficient of the ON-resistance (RON = 10.2 mΩ•cm2).
High Voltage 4H-SiC BJTs with Deep Mesa Edge Termination
Authors: Zhang Jian Hui , Zhao Jian Hui , Wang Xiao Hui , Li Xue Qing , Fursin Leonid , Alexandrov Peter , Gagliardi Mari Anne , Lange Mike , Dries Christopher
Published: March 2011

This paper reports our recent study on 4H-SiC power bipolar junction transistors (BJTs) with deep mesa edge termination. 1200 V – 10 A 4H-SiC power BJTs with an active area of 4.64 mm2 have been demonstrated using deep mesa for direct edge termination and device isolation. The BJT’s DC current gain () is about 37, and the specific on-resistance (RSP-ON) is ~ 3.0 m-cm2. The BJT fabrication is substantially simplified and an overall 10% reduction in the device area is achieved compared to the multi-step JTE-based SiC-BJTs.
600V-30A 4H-SiC JBS and Si IGBT Hybrid Module
Authors: Li Yu Zhu , Ni Wei Jiang , Li Zhe Yang , Li Yun , Chen Chen , Chen Xiao Jian
Published: March 2011

600V-30A 4H-SiC Junction Barrier Schottky（JBS）diodes were designed and fabricated using SiC epitaxy and device technology. SiC JBS diodes were packaged in Si IGBT module，and switching measurements were done at 125°C. As free-wheeling diode for Si IGBT, 600V SiC JBS diode was compared to 600V ultra-fast diode from International Rectifier. SiC diode achieved 90% recovery loss reduction and corresponding IGBT showed 30% lower turn-on loss. However, SiC JBS diode has larger on-state voltage drop due to small chip area. On-state power loss will be lowered by increasing SiC chip area.
Lifetime Control of 4.5 kV SiCGT by High-Energy Electron Irradiation
Authors: Asano Katsunori , Nakayama Koji , Miyanagi Yoichi , Tanaka Atsushi , Nishimura Masahiko , Izumi Toru , Ogata Shuuji , Hayashi Toshihiko
Published: March 2011

The measured turn-off waveforms of 4.5 kV SiCGTs by using electron irradiation with various electron doses are reported. The turn-off time decreased with an increase in the electron dose. Furthermore, the turn-off characteristics of SiCGTs with p-type drift layer, which assumed the various trap concentrations, are simulated. The relation between the turn-off characteristics and the trap is also investigated. The simulated results show good correlation to measured data and the simulated turn-off times decrease with an increase in the electron dose as well as measured data.
High Temperature Silicon Carbide CMOS Integrated Circuits
Authors: Clark David T. , Ramsay Ewan P. , Murphy A.E. , Smith Dave A. , Thompson Robin. F. , Young R.A.R. , Cormack Jennifer D. , Zhu C. , Finney S. , Fletcher John
Published: March 2011

The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.
Forced-Air-Cooled 10 kW Three-Phase SiC Inverter with Output Power Density of More than 20 kW/L
Authors: Sato Shinji , Matsui Kohei , Zushi Yusuke , Murakami Yoshinori , Tanimoto Satoshi , Sato Hiroshi , Yamaguchi Hiroshi
Published: March 2011

A forced-air-cooled three-phase inverter built with SiC-JFETs and -SBDs as power semi-conductor devices was designed and fabricated. The inverter can operate steadily at a rated power of 10 kW in a junction temperature range up to 200°C. Output power density of more than 20 kW/L was achieved. The design specifications, the power module fabrication process, the results of a high-temperature operating test and a continuous switching test are described in turn.
Fault Protection System for Current Source Inverter with Normally on SiC JFETs
Authors: Rabkowski Jacek , Zdanowski Mariusz , Nowak Mietek , Barlik Roman
Published: March 2011

This paper describes a simple fault protection system for Current Source Inverter built with normally-on SiC JFETs. Because all transistors are in on-state after loss of the gate drive(s) supply, list of possible fault modes is extended in reference to standard inverters. That is also why an additional normally off switch is introduced in the DC link. Operation principles of the protection system which follows the drain-source voltages of JFETs and the current of the DC link are presented. The 2kVA/100kHz model of the inverter equipped with the proposed system is validated via various laboratory tests including short-circuits and the auxiliary supply turn off.
Measurements and Simulations of Lateral PNP Transistors in a SiC NPN BJT Technology for High Temperature Integrated Circuits
Authors: Lanni Luigia , Ghandi Reza , Domeij Martin , Zetterling Carl Mikael , Malm B. Gunnar , Östling Mikael
Published: March 2011

In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.
The Formation of an Epitaxial-Graphene Cap Layer for Post-Implantation High Temperature Annealing of SiC and its In Situ Removal by Si-Vapor Etching
Authors: Ushio Shoji , Adachi Ayumu , Matsuda Kazuhiro , Ohtani Noboru , Kaneko Tadaaki
Published: March 2011

As a new graphene functionality applicable to post-implantation high temperature annealing of SiC, a method of in situ formation and removal of large area epitaxial few-layer graphene on 4H-SiC(0001) Si-face is proposed. It is demonstrated that the homogeneous graphene layer formed by Si sublimation can be preserved without the decomposition of the underlying SiC substrate even in the excess of 2000 oC in ultrahigh vacuum. It is due to the existence of the stable (6√3×6√3) buffer layer at the interface. To ensure this cap function, the homogeneity of the interface must be guaranteed. In order to do that, precise control of the initial SiC surface flatness is required. Si-vapor etching is a simple and versatile SiC surface pre/post- treatment method, where thermally decomposed SiC surface is compensated by a Si-vapor flux from Si solid source in the same semi-closed TaC container. While this Si-vapor etching allows precise control of SiC etch depth and surface step-terrace structures, it also provides a “decap” function to remove of the graphene layer. The surface properties after the each process were characterized by AFM and Raman spectroscopy.
High Temperature Graphene Formation on Capped and Uncapped SiC
Authors: Göckeritz Robert , Schmidt Denny , Beleites Moritz , Seifert Gerhard , Krischok Stefan , Himmerlich Marcel , Pezoldt Joerg
Published: March 2011

Epitaxial graphene was grown on Si-face 4H-SiC. A SiC pretreatment with a carbon cap¬ping technique was used as well as slow heating rates and a temperature of 1800 °C under atmos¬pheric argon pressure. The surface morphology was investigated by atomic force microscopy and Raman spectroscopy was performed for samples with different graphitization times.
Observations on C-Face SiC Graphene Growth in Argon
Authors: Gaskill D. Kurt , Hite Jennifer K. , Culbertson James C. , Jernigan Glenn G. , Tedesco Joseph L. , Nyakiti Luke O. , Wheeler Virginia D. , Myers-Ward Rachael L. , Garces N.Y. , Eddy Charles R.
Published: March 2011

The growth of epitaxial graphene on C-face 6H-SiC substrates is investigated using pro-cess conditions that can form small, local areas of graphene. The thickness of SiC lost to Si sublimation is not completely countered by the thickness of the resulting graphene and so graphene-covered basins (GCBs) are formed. The GCBs are most likely nucleated at threading dislocations from the substrate. The GCB morphology exhibits ridges, similar to those found on continuous films. The GCBs expand through erosion of the surrounding SiC substrate walls, eventually coalescing into continuous films. The ratio of the Raman D and G peaks was used to estimate the crystallite length scale and it was found to be about 200 nm for small GCBs and > 1 m for continuous films.
Analytical Model of Stress Relaxation in 3C SiC Layers on Silicon
Authors: Zielinski Marcin , Michaud Jean François , Jiao S. , Chassagne Thierry , Bazin Anne Elisabeth , Michon A. , Portail Marc , Alquier Daniel
Published: March 2011

In this work we analyze the static behavior of cantilevers elaborated on the basis of 3C SiC thin films grown by chemical vapor deposition on (100) and (111) oriented silicon substrates. A direct microscope observation of cantilever bending indicates the opposite sign of stress gradient (respectively negative and positive) for both film orientations. The correlation of this observation with the commonly admitted nature of intrinsic stress for each orientation (respectively compressive and tensile) leads us to an unexpected conclusion: instead of relaxing, the absolute value of the intrinsic stress increases from the interface to the layer surface. We propose an analytical model that could explain this phenomenon.
Influence of Intercalated Silicon on the Transport Properties of Graphene
Authors: Goss Jonathan P. , Briddon Patrick R. , Nagareddy V. Kartheek , Wright Nicolas G. , Horsfall Alton B. , Caldwell Joshua D. , Gaskill D. Kurt , Jernigan Glenn G.
Published: March 2011

Epitaxial graphene produced from SiC substrates exhibits a carrier mobility re- duction thought to arise from intercalated silicon. We present the results of density functional simulations and show that individual silicon atoms are highly mobile on and between graphene sheets, suggesting that thermally stable structures involving individual Si impurities are likely to result from the interaction of silicon with defects in the graphene sheets.
Temperature Dependent Structural Evolution of Graphene Layers on 4H-SiC(0001)
Authors: Sonde Sushant , Vecchio Carmelo , Giannazzo Filippo , Bongiorno Corrado , Di Franco Salvatore , Rambach Martin , Rimini Emanuele , Raineri Vito
Published: March 2011

In this study we examined the structural evolution of graphene grown on 8° off-axis 4H-SiC(0001) substrates at temperatures from 1600°C to 1700°C in Ar ambient. Morphological transformation of SiC substrate after annealing was examined by Tapping Mode Atomic Force Microscopy. Moreover, by etching-out graphene layers from graphitized SiC substrates in selective trenches we determined the number of graphene layers. Numbers of graphene layers were then independently confirmed by Transmission Electron Microscopy imaging.
Electrical and Structural Properties of AlGaN/GaN Heterostructures Grown onto 8°-Off-Axis 4H-SiC Epilayers
Authors: Roccaforte Fabrizio , Greco Giuseppe , Weng Ming Hung , Giannazzo Filippo , Raineri Vito
Published: March 2011

In this work the electrical and structural properties of AlGaN/GaN heterostructures grown onto 8°-off-axis 4H-SiC epilayers were investigated. A morphological and structural analysis of the samples showed the presence of “V-shaped” near-surface defects in the AlGaN layer, with a preferential orientation along the miscut direction [11-20]. In the presence of these defects an anisotropy of the current-voltage characteristics of high electron mobility transistors (HEMTs), fabricated with two different orientations, was observed. The sheet carrier density ns and the channel mobility n were determined from the device characteristics. The results were discussed considering the possible implications for AlGaN/GaN HEMT technology.
Al-Si-Ti Ohmic Contacts on N-Type Gallium Nitride
Authors: Thierry-Jebali Nicolas , Ménard Olivier , Yvon Arnaud , Collard Emmanuel , Zhe Miao , Dezellus Olivier , Brylinski Christian , Viala Jean Claude
Published: March 2011

Ohmic contacts represent a major technological brick for the development of high power devices on Gallium Nitride. Al(200 nm) Ti(70 nm) metallization on n+-GaN, annealed at 650 °C, provides a “Specific Contact Resistivity” (SCR) in the range mid 10-5 Ω.cm², which is low enough for the main switching power applications. However, the Al-Ti metallic compound phases formed during the annealing step result from solid-solid reactions, which may lead to high stress and / or poor cohesion, possibly deleterious to contact reliability. In this work, we have investigated several configurations of Ti-Al-Si based contacts, aiming at favoring liquid-solid reactions and / or Si element diffusion, in order to get better SCR and / or morphology and cohesion of the metallic phase. Surprisingly, only contacts annealed at low temperature (450 °C) provide low contact SCR, comparable to that of Ti-Al only contact, but systematically higher.
Ohmic Contact Resistance to GaN Devices Dependence with on Temperature for GaN Devices T
Authors: Pérez-Tomás Amador , Fontserè A. , Placidi Marcel , Baron N. , Chenot Sébastien , Cordier Yvon , Moreno J.C. , Gammon Peter Michael , Jennings Michael R.
Published: March 2011

The temperature dependence of Ohmic contacts to GaN devices is investigated in this paper via by measuring TLM contact resistances TLM vs Tas a function of temperature. measurements. In particular, the two types of Ohmic contacts are considered: (1) Contacts to highly doped implanted regions (such as the MOSFET drain/source contacts or the back contact of Schottky diodes) and (2) contacts to the 2 dimensional electron gas (2DEG) of an AlGaN/GaN heterojunction.
Characterization of Fast Switching Capability for Diamond Schottky Barrier Diode
Authors: Funaki Tsuyoshi , Kodama Kazuya , Umezawa Hitoshi , Shikata Shinichi
Published: March 2011

Wide band gap semiconductors have been attracted as the material for fabricating power switching devices to obtain lower power conversion loss in high voltage circuit, and to operate harsh environment of high temperature. This paper focuses on diamond as the wide band gap semiconductor material and elucidates the dynamic characteristics in switching operation. To this end, Schottky barrier diode (SBD) is fabricated with p type diamond semiconductor and static I-V characteristics is evaluated. Then, the switching operation of diamond SBD is demonstrated, and forward current dependency of the recovery phenomena is characterized. The diamond SBDs show superior fast switching capability with low reverse recovery current, which is inherent in uni-polar switching device.
Single-Crystal Silicon Carbide: A Biocompatible and Hemocompatible Semiconductor for Advanced Biomedical Applications
Authors: Saddow Stephen E. , Frewin Christopher L. , Coletti Camilla , Schettini N. , Weeber E. , Oliveros A. , Jarosezski M.
Published: March 2011

Crystalline silicon carbide (SiC) and silicon (Si) biocompatibility was evaluated in vitro by directly culturing three skin and connective tissue cell lines, two immortalized neural cell lines, and platelet-rich plasma (PRP) on these semiconducting substrates. The in vivo biocompatibility was then evaluated via implantation of 3C-SiC and Si shanks into a C57/BL6 wild type mouse. The in vivo results, while preliminary, were outstanding with Si being almost completely enveloped with activated microglia and astrocytes, indicating a severe immune system response, while the 3C-SiC film was virtually untouched. The in vitro experiments were performed specifically for the three adopted SiC polytypes, namely 3C-, 4H- and 6H-SiC, and the results were compared to those obtained for Si crystals. Cell proliferation and adhesion quality were studied using MTT [3-(4,5-dimethylthiazol-2-yl)-2,5-diphenyltetrazolium bromide] assays and fluorescent microscopy. The neural cells were studied via atomic force microscopy (AFM) which was used to quantify filopodia and lamellipodia extensions on the surface of the tested materials. Fluorescent microscopy was used to assess platelet adhesion to the semiconductor surfaces where significantly lower values of platelet adhesion to 3C-SiC was observed compared to Si. The reported results show good indicators that SiC is indeed a more biocompatible substrate than Si. While there were some differences among the degree of biocompatibility of the various SiC polytypes tested, SiC appears to be a highly biocompatible material in vitro that is also somewhat hemocompatible. This extremely intriguing result appears to put SiC into a unique class of materials that is both bio- and hemo-compatible and is, to the best of our knowledge, the only semiconductor with this property.
Polarity Control of CVD Grown 3C-SiC on Si(111)
Authors: Pezoldt Joerg , Schröter Bernd
Published: March 2011

XPD and XRD measurements revealed a difference in the crystallographic polarity of 3C-SiC(111) grown on Si(111) carbonized by ethene diluted in hydrogen at atmospheric pressure in a rapid thermal chemical vapour deposition reactor and the crystallographic polarity of 3C-SiC(111) formed in an ethene hydrogen gas mixture at low pressures. In the first case C-face polar material was formed, whereas in the second case the grown expitaxial layer exhibits Si-face surface polarity.
Neutron Stress Measurement of Coarse Crystal Grain in Aluminium Casting Alloy
Authors: Masayuki Nishida , Takao Hanabusa , Tatsuya Matsue , Suzuki Hiroshi
Published: March 2011

Internal stresses in aluminum casting alloy were measured by the neutron stress measurement method with the apparatus RESA in the Japan Atomic Energy Agency (JAEA). In most cases, coarse crystal grains are included in aluminum casting alloy. These coarse crystal grains make it extremely difficult to estimate the internal stresses by the neutron diffraction [1]. The two problems arise because of the existence of the coarse crystal grains. The first problem is the production of an unstable diffraction profile in the necessary direction. The second is the edge effect which is generated by the exclusion of the coarse crystal grains from the neutron irradiation area (gage volume). In this study, two kinds of new techniques used were proposed to resolve these problems. Firstly, the elastic theory based on the sin2ψ method is shown. Diffraction peaks in several directions were found by use of the rocking curve method. Following that, the lattice spaces in each principal direction were calculated from these diffraction peaks using the elastic theory. Secondly, the edge effect was canceled out by the modified measurement method which was done symmetrically. Finally, the aluminum casting sample which included coarse crystal grains was set to the tensile testing machine on RESA’s measurement table and the applicability of these new techniques were confirmed experimentally.
On Faulting in Nanocrystallites of FCC Metals
Authors: Beyerlein Kenneth R. , Leoni Matteo , Snyder Robert L. , Scardi Paolo
Published: March 2011

Patterns calculated by applying the Debye function to faulted spherical nanoparticles are used to test the accuracy of modern Line Profile Analysis theory of faulting for small crystallites. The relative deviation of the determined fault density is found to be dependent on the fault position, and on the particle size. The study of the average pattern from systems of 100 particles (D = 9.8nm) shows an overestimated deviation of the determined fault density by as much as 30%.
Residual Stresses and Strength of Hard Chromium Coatings
Authors: Pfeiffer Wulf , Koplin Christof , Reisacher Eduard , Wenzel Johannes
Published: March 2011

Experimental and numerical investigations have been performed on the relationships between coating parameters, residual stresses, micro-cracks and the near surface strength of electrochemically deposited hard chromium coatings. The experimental investigations included: X-ray measurements of residual and externally-applied stresses; crack density measurements using microscopy; and load-bearing measurements using ball-on-plate tests. The numerical investigations in combination with analytical conclusions focused on the influence of different crack lengths and densities on the effective elastic modulus of the chromium coating and the stress-enhancing or shielding effect of micro-crack networks respectively. The results show that the residual stresses and crack networks are influenced by the current density used during deposition. Coatings with high tensile residual stresses have low crack densities. This correlation is associated with stress relaxation by formation of micro-cracks and, to a lesser extent, to a direct reduction in residual stresses due to the deposition process. The load bearing capacity is dominated by the crack density and can be significantly increased by shot-peening-induced compressive residual stresses. Thus, optimization of hard chromium deposition parameters for applications needing high surface strength should predominantly focus on minimizing the crack density.
Experimental Verification of the Hole Drilling Plasticity Effect Correction
Authors: Beghini M. , Santus Ciro , Valentini Emilio , Benincasa A.
Published: March 2011

The Hole Drilling Method introduces a hole in a (residual) stressed volume of material, typically a metal, then a stress concentration follows. A portion of the volume near the hole can experience a stress concentration and then plasticity. The relaxed strains measured by the rosette strain gage grids are then affected by this plasticity volume especially when the residual stress is quite large with respect to the material yield stress. This is the so called Hole Drilling Plasticity Effect. The authors recently proposed a numerical procedure to correct this perturbation effect and retrieve more accurate residual stress components values. An experimental validation of this correction procedure is reported in the paper.
The Contour Method for Residual Stress Determination Applied to an AA6082-T6 Friction Stir Butt Weld
Authors: Richter-Trummer Valentin , Moreira Pedro Miguel Guimarães Pires , Ribeiro João , de Castro Paulo Manuel Salgado Tavares
Published: March 2011

Residual stresses parallel to the welding direction on a cross-section of a 3 mm thick friction stir butt-welded aluminum alloy AA6082-T6 plate were determined using the contour method. A full contour map of longitudinal residual stresses on a weld cross section was determined in this way, revealing detailed information on the residual stress distribution in the inside of a friction stir weld, especially in the nugget zone. The typical M-shape, usually described for the residual stress distribution in friction stir welds, was found. The maximum residual stresses are below the yield strength of the material in the shoulder region and, outside of the welding region, low tensile and compressive residual stresses are responsible for the necessary stress equilibrium on the plane of interest. A comparison was made with the established incremental hole drilling technique on an equivalent plate for validation and good agreement of both techniques was obtained. The distribution, as well as the magnitude of the residual stresses measured by both techniques, is very similar, thus validating both the experimental and numerical procedures used for the contour method application, presented and discussed in the present paper.
Influence of Laser Remelting Process on Strain and Residual Stresses in Nodular Iron
Authors: Šturm Roman , Grum Janez
Published: March 2011

The present paper deals with residual stress and strain changes in thin flat specimens of nodular cast iron during laser remelting process. In laser remelting process of a workpiece we have used several laser beam passages across the workpiece surface. The state of internal stress in the workpiece changes because of different ways of guiding the laser beam across the workpiece surface, and consequently strain of the workpiece may occur. In the process of gradual remelting of the specimen surface, i.e. during its heating and cooling, volume changes in the specimen surface layer occur due to thermal and microstructural changes. To find out more about volume changes in the thin surface layer of specimens, the latter were monitored by measuring the strain at the lower side of the specimens during and after the remelting process, and also by residual stress measurement in the thin surface layer. The results obtained confirm that the laser remelting process could be successfully optimised on the basis of knowing the residual stresses and the strain generated during the remelting process.
PRECIX, Robotic System for Residual Stress Analysis by X-Ray Diffraction
Authors: Lefebvre Fabien , Le Roux J.M. , Charles C. , Pillière H. , Berthier E. , Fontugne C.
Published: March 2011

In the last years, a new residual stress analysis system by X-ray diffractions has been developed by CETIM and INEL companies. This system called PRECIX is based on an industrial 6 axis robot. The technological performance is, like a 4 circle goniometer, to set together at the end of the sixth axes an x-ray source with a conventional size X-ray source, energy and position sensitive linear detector and an embedded long distance positioning system. PRECIX is an all-in-one system including all electrical and electronic items to perform residual stress analysis. This paper presents PRECIX in detail with a contactless positioning system, a new software getting a fully transparent utilisation for the users. Internal round-robin analysis with external reference samples and different geometries parts performed are presented to compare PRECIX results and other already validated X-ray diffraction systems.
Stress/Strain Effects on Industrial Superconducting Composites
Authors: Ito Takayoshi , Harjo Stefanus , Osamura Kozo , Hemmi Tsutomu , Awaji Satoshi , Machiya Shuichiro , Oguro Hidetoshi , Nishijima Gen , Takahashi Kohki , Matsui Kunihiro , Tsuchiya Yoshinori , Arima Hiroshi , Aizawa Kazuya , Koizumi Norikiyo , Nakamoto Tatsushi , Ogitsu Toru
Published: March 2011

Researches to study internal stress/strain behaviors in industrial superconducting composites have been started at TAKUMI of J-PARC, as soon as the completion of TAKUMI construction. Preliminary results obtained from strains measurements during tensile deformation of Nb3Sn strands and YBa2Cu3O7tapes, strains measurements during heating of Nb3Sn strands and residual strains measurements in a Nb3Sn Cable-In-Conduit Conductors are briefly described. The results can demonstrate possibilities of neutron engineering diffraction to solve problems in industrial superconducting composites by using J-PARC high flux neutron beam, even the volume fractions of superconducting phases in the composites are small and the superconducting phases locate inside the real components.