bluuebunny/crossref_metadata_2025 huggingface dataset:
Chlorosilane Interactions with Iron at High Temperatures
Authors: Aller Joshua L , Mason Ryan , Baber Michael , Tatar Greg , Ellingwood Kevin , Jacobson Nathan S. , Gannon Paul E.
Published: February 2020

Chlorosilane species are commonly used at high temperatures in the manufacture and refinement of ultra-high purity silicon and silicon materials. They are highly corrosive in these processes, necessitating the use of high cost alloys for the construction of reactors, pipes, and vessels required to handle and produce them. In this study, iron, the primary alloying component of low cost metals, was exposed to a variety of silicon tetrachloride-hydrogen-hydrogen chloride vapor streams at industrially-relevant times (0-100 hours), temperatures (500-700°C), and compositions. Post exposure analyses including FE-SEM, EDS, XRD, and gravimetric analysis revealed formation and growth of stratified silicide and chloride surface layers, which vary as a function of time, temperature and gas composition. Additionally, there was evidence for various regimes of diffusion-limited and reaction-limited surface layer growth. Speculated mechanisms to explain these observations were supported by thermodynamic equilibrium simulations of experimental conditions. This study furthers the understanding of metals in chlorosilane environments, which is critically important for manufacturing the high purity silicon required for silicon-based electronic and photovoltaic devices.
(Invited) Thin Porous Silicon Produced By Metal-Assisted Etching
Authors: Yae Shinji
Published: February 2020

Metal-assisted etching of silicon can produce porous silicon and silicon nanowires by simply immersing metal-modified silicon in a hydrofluoric acid solution without electrical bias (1). Such etching proceeds by a local galvanic cell mechanism consisting of local anodic dissolution of silicon and local cathodic reduction of an oxidizing agent on metal. The structure of porous silicon is widely controlled from nm to sub-mm scale in pore size and from straight to an ants’ nest like in pore morphology by changing etching conditions (1-3). We have been studying the metal-assisted etching of silicon to produce porous structures for antireflection of solar cells (2), and for autocatalytic electroless formation of metal-nanorods and metal films on Si surfaces (4). In this paper, we present size-controlled thin porous silicon layers consisting of straight pores and those applications.

Noble metal nanoparticles were deposited on crystalline silicon wafers by electroless displacement deposition immersing the wafers into a metal salt solution containing hydrofluoric acid. The metal-particle-deposited silicon wafers were immersed in a hydrofluoric acid solution including hydrogen peroxide as an oxidizing agent.

Under suitable etching conditions, uniform porous silicon thin layers consisting of straight pores were formed on silicon wafers. The diameter of pores was consistent with the size of metal nanoparticles remained at the bottom of each pore. Thus, the diameter of pores, that is, the porosity of porous layers is easily controlled in the nm scale with the deposition time of nanoparticles. The thickness of porous layers, that is, the length of the straight pores is also easily controlled by the etching time. Optical properties of the porous layers thinner than 1 μm depends on those porosity and thickness (5). This is applicable for antireflection of solar cells. The strength of metal nanorods, which were produced by electrolessly filling the pores, increased with the diameter of pores from 10 to 25 nm. These nanorods work as nanoanchors of metal films on silicon wafers. 

Acknowledgements

The present work was partly supported by JSPS KAKENHI (26289276).

References

1) Z. Huang, N. Geyer, P. Werner, J. de Boor, U. Gösele, Adv. Mater., 23, 285 (2011).

2) S. Yae, H. Tanaka, T. Kobayashi, N. Fukumuro, H. Matsuda, Phys. Stat. Sol. (c), 2(9), 3476 (2005).

3) S. Yae, M. Tashiro, M. Abe, N. Fukumuro, H. Matsuda, J. Electrochem. Soc., 157, D90 (2010).

4) S. Yae, K. Sakabe, N. Fukumuro, S. Sakamoto, and H. Matsuda, J. Electrochem. Soc., 158, D573 (2011).

5) K. Yamakawa, S. Sakamoto, N. Fukumuro, S. Yae, ECS Trans., 69(2), 185 (2015).
Enhanced Electrochemical Performance of Porous Electrodes for All-Solid-State Li-Ion Microbatteries
Authors: Djenizian Thierry
Published: February 2020

Nowadays, lithium-ion batteries (LIBs) are widely used to power portable devices, microelectronics, vehicles, etc. With many advantages such as high surface area and improved charge transport, self-supported 3-D nanostructured metal oxides are promising electrode materials for LIBs and their impact is particularly significant when considering the miniaturization of energy storage systems and the development of 3D microbatteries [1-3].

During this talk, it will be presented the fabrication and use of porous electrodes based on titania nanotubes (TiO2nts) as anode [4–8] and LiNi0.5Mn1.5O4 (LNMO) as cathode. This kind of 3D nanostructured electrodes is particularly interesting due to better electrochemical performance in terms of kinetics and stability during cycling.

Then, the fabrication of an all-solid-state Rocking-chair battery composed of vertical arrays of TiO2nts as anode, a polymer thin film as electrolyte, and a LiNi0.5Mn1.5O4 (LNMO) layer as cathode will be shown [9]. According to the electrochemical tests, this 2D full-solid microbattery exhibits high performance such as good discharge capacity and good capacity retention.

Finally, the current approaches developed to achieve the fabrication of a full 3D microcell will be highlighted. Particularly, the conformal electrodeposition of polymer electrolytes onto the electrodes will be discussed [10-12].

References

[1] B.L. Ellis, P. Knauth, T. Djenizian, Adv. Mater., 26 (2014) 3368.

[2] L. Baggetto, J.F.M. Oudenhoven, T. van Dongen, J.H. Klootwijk, M. Mulder, R. a. H. Niessen, M.H.J.M. de Croon, P.H.L. Notten, J. Power Sources 189 (2009) 402.

[3] M. Nathan, D. Golodnitsky, V. Yufit, E. Strauss, T. Ripenbein, I. Shechtman, S. Menkin, E. Peled, Microelectromechanical Syst. J. 14 (2005) 879.

[4] G. Ortiz, I. Hanzu, T. Djenizian, P. Lavela, J.L. Tirado, and P. Knauth, Chem. Mater. 21 (2009) 63.

[5] N.A. Kyeremateng, C. Lebouin, P. Knauth, T. Djenizian, Electrochim. Acta 88 (2012) 814.

[6] N.A. Kyeremateng, V. Hornebecq, P. Knauth, T. Djenizian, Electrochim. Acta 62 (2012) 192.

[7] T. Djenizian, I. Hanzu, P. Knauth, J. Mater. Chem. 21 (2011) 9925.

[8] N.A. Kyeremateng, N. Plylahan, A.C.S. dos Santos, L. V Taveira, L.F.P. Dick, T. Djenizian, Chem. Commun. 49 (2013) 4205.

[9] N. Plylahan, M. Letiche, M. Barr, and T. Djenizian, Electrochem. Commun., 43, 121 (2014).

[10] N. Plylahan, N.A. Kyeremateng, M. Eyraud, F. Dumur, H. Martinez, L. Santinacci, P. Knauth, T. Djenizian, Nanoscale Res. Lett. 7 (2012) 349.

[11] N. Plylahan, A. Demoulin, C. Lebouin, P. Knauth, T. Djenizian, RSC Adv., 5, 28474 (2015).

[12] N. Plylahan, M. Letiche, M. Barr, B. Ellis, S. Maria, T. N. T. Phan, E. Bloch, P. Knauth, and T. Djenizian, J. Power Sources, 273, 1182 (2015).
(Invited) Electrolyte Solutions Confined in Porous Silicon Electrodes
Authors: Fukami Kazuhiro , Koyama Akira , Kitada Atsushi , Abe Takeshi , Murase Kuniaki
Published: February 2020

Electrolyte solutions confined in nanopores are of importance in the development of electrochemical devices such as batteries and electric double layer capacitors. We reported that tuning of hydration properties of porous silicon wall and metal ions can accelerate the deposition of metal within nanoporous silicon electrodes. To promote electrochemical deposition of metal within nanoporous silicon electrodes, combination of a hydrophobic pore wall and low charge density metal ions is desired when metal deposition is carried out in aqueous electrolyte solutions. In the present paper, three examples that show the role of hydration properties of pore wall and ions in aqueous solutions are given. First, accelerated penetration of Pt complex anion that results in fast deposition of Pt within nanoporous silicon is explained in detail. We prepared porous silicon electrodes with three different pore diameters such as 4 nm, 15 nm and 30 nm. The diffusion of Pt complex anions is gradually suppressed with decreasing pore size. However, porous silicon with the smallest nanopores shows drastic acceleration of the penetration of the Pt anions into the pores. The penetration rate of Pt anions becomes faster when using [PtBr4]2– than using [PtCl4]2–. This accelerated penetration is explained by considering the charge density of the anions. Second, we show that Zn complex ions also penetrate very quickly and the fast penetration realizes the high-rate charging Zn negative electrodes for metal anode batteries. When the current density for Zn deposition reaches the diffusion-limitation, the depletion of Zn cations in the vicinity of electrode surface occurs. If one uses nanoporous electrodes, the depletion is generally unavoidable under diffusion-limited conditions. However, under the occurrence of such fast penetration of Zn complex ions, we show that Zn is preferentially deposited within the nanopores. The continuous deposition of Zn within the nanopores enables the high-rate charging without roughening the top surface of the porous electrode. Third, we report that such accelerated penetration occur also in the case of alkylammonium cations. As observed in Pt and Zn deposition, it is observed that alkylammonium cations with low charge density are advantageous for the accelerated penetration into the nanopores.

We believe that the mechanism of the accelerated penetration of ions into nanopores is crucially important for further developments of electrochemical energy devices.
Self-Organized TiO2 Nanotube Arrays: Towards Improved Ordering
Authors: Macak Jan M. , Sopha Hanna , Hromadko Ludek , Krbal Milos
Published: February 2020

Synthesis of highly-ordered nanostructures of valve metal oxides has recently attracted huge scientific and technological interest motivated by their possible use in many applications. The nanoporous Al2O3 – most established member of this group of materials – has been prepared by anodic oxidation of Al under suitable electrochemical conditions two decades ago into perfectly ordered, honeycomb-like porous structures (1). Owing to the flexibility of the pore diameter/length and the relative ease of the Al2O3 dissolution, its porous membranes have been since than widely used as template material of the choice for a range of materials (2-4).

It is the TiO2 that has received the highest attention after Al2O3 motivated by its range of applications, including photocatalysis, water splitting, solar cells and biomedical uses. Very significant research efforts have led to reproducible synthesis of self-organized TiO2 nanotube layers by means of anodic oxidation, during which the starting Ti substrate is converted into highly-ordered nanotubular layer by anodization in suitable electrolytes (5-7). Although advancements in the anodic synthesis of self-organized TiO2 nanotube layers have been presented over past years (8), the degree of ordering has not reached so far the level known from porous alumina (1). Numerous factors influence the ordering and the homogeneity of the TiO2nanotube layers.

In the presentation, we aim to demonstrate significant advancements in the ordering of anodic TiO2nanotubes compared to known state-of-art. In particular, we will show recent results on the extremely ordered nanotube arrays. In addition, utilizing AFM, SEM and optical measurements, we will show how to obtain via tailored anodization protocols a very decent degree of uniformity and homogeneity of the nanotube layers. Moreover, based on SEM, EBSD and TEM measurements, we will demonstrate how the Ti grain structure influences the lateral uniformity of the nanotube layers (9-11). References

1. H. Masuda, K. Fukuda, Science, 268 (1995) 1466.

2. K. Nielsch, F. Müller, A.-P. Li, U. Gösele, Adv. Mater. 12 (2000) 582

3. H. Asoh et al., J. Electrochem.Soc. 148 (2001) B152.

4. J. Kolar, J. M. Macak, K. Terabe, T. Wagner, J. Mater. Chem. C 2 (2014) 349.

5. J. M. Macak, H. Tsuchiya, P. Schmuki, Angew. Chem. Int. Ed. 44 (2005) 2100.

6. J.M. Macak et al., Curr. Opin. Solid State Mater. Sci. 1-2 (2007) 3.

7. K. Lee, A. Mazare, P. Schmuki, Chem. Rev. 114 (2014) 9385

8. J.M. Macak, S. P. Albu, P. Schmuki, Phys. Stat. Sol. (RRL) 1 (2007) 181.

9. H. Sopha, L. Hromadko, K. Nechvilova, J. M. Macak. J. Electroanal. Chem. 759 (2015) 102.

10. H. Sopha, A. Jäger, P. Knotek, K. Tesar, M. Jarosova, J. M. Macak, Electrochim. Acta 190 (2016) 744.

11. J. M.Macak. M. Jarosova, A. Jäger, H. Sopha, M. Klementova, Appl. Surf. Sci. 371 (2016) 607.
Modeling Film Thicknesses and Estimating Corrosion Depths Under Climate Control
Authors: Van den Steen Nils , Simillion Hans , Thierry Dominique , Deconinck Johan
Published: February 2020

Atmospheric corrosion and accelerated corrosion tests are inherently subjected to dynamic film variations. Modeling and understanding these variations in combination with corrosion processes is therefore of high relevance. From a modeling point of view, accelerated corrosion tests have the advantage of well defined conditions which can be used as an input for the models. From experimental point of view, these models can be of high value because notwithstanding the defined conditions, experimental results of accelerated tests are often difficult to reproduce exactly. This is where models may be able to help in the understanding of the phenomena. In [1] a model to predict the time dependent film thickness was presented, taking into account the relative humidity, temperature, substrate material and the presence of hygroscopic salts. A simple corrosion model was used to calculate a simulated corrosion depth. A simple corrosion model allows to focus on the effect of the film thickness. Based on this work, we present experimental and simulated corrosion depths in accelerated corrosion tests. The corrosion depth is measured using AirCorr loggers. The electrical resistance of a thin metal track is measured and registered over time. As the corrosion processes will decrease the cross-sectional area of the track, the resistance will increase. A reference electrode provides the possibility to compensate for temperature effects. We focus on corrosion depths as measurements on the liquid film thickness itself are not directly available in literature. Several cycles VDA, N-VDA, GMW, etc are simulated and compared with measurements considering a iron substrate. An exact match between the experiments and simulations is not expected, as important phenomena are not (yet) included in the model. For example, run-off effects on the film thickness and the amount of salt on the surface, effects of the corrosion products on the corrosion processes (passivation, blocking) and on the film thickness (hygroscopic effects). What we expect to see similar trends between measurement and simulation, linked with the electrolyte thickness. We study also the effects of different parameters on the results. During the saltspray, a constant film thickness is assumed. In the figure we show the simulated corrosion depths obtained in a partial N-VDA test when different film thicknesses during this spraying phase (50micron, 100micron, 150micron) are assumed. These results are compared with experimental data. Based on the comparison, conclusions are formulated about the accuracy of the model, the applicability, the shortcomings and the points of interest for future work are identified. [1] Van den Steen, N., et al. "An integrated modeling approach for atmospheric corrosion in presence of a varying electrolyte film." Electrochimica Acta 187 (2016): 714-723.

Figure 1
(Invited) Relating Paint Structure to Electrochemical Impedance Spectroscopy
Authors: Hughes Anthony ewart , Ranade Shyama Deepak , Tan Mike yongjun , Yang Y Sam , Forsyth Maria
Published: February 2020

Recent advances in the area of computed tomography (CT) for materials such as paint systems has provided a better understanding of the internal structures of different components that constitute a complicated material like a typical protective paint coating. Recent studies have shown differences in the density of the polymer component and the formation of clustering among inorganic particles. In the case of leachable inhibitors, the dissolution of the clusters dictates the kinetics of release of the inhibitor as well as leaving behind a cluster void through which many species can migrate. In some instances these cluster voids have fractal dimensions well below three. In the current paper the authors use EIS to follow the change in impedance of a pipeline coating during strain including in immersion conditions. This coating consists of a number of inorganic components in an epoxy binder. The same samples have been examined using CT to follow the development of changes in the coating, with a particular focus on the evolution of void space, with respect to the mechanical strain applied to the coating. The EIS data show dispersion effects under conditions, such as environmental exposure, and applied mechanical strain, for which the CT may provide some explanation.
(Invited) in-Situ Impedance of Lithium-Ion Rechargeable Batteries during Charge and Discharge
Authors: Itagaki Masayuki , Hoshi Yoshinao , Shitanda Isao
Published: February 2020

An electrochemical impedance spectroscopy (EIS) is useful method to investigate inner structure and conditions of lithium-ion rechargeable batteries (LIRB) because EIS is nondestructive method to discriminate time constants related to electrolyte/electrode interfaces and protective film formed on negative electrode. The almost impedance measurements of LIRB are generally carried out at an equilibrium-state. The authors would like to emphasize that the galvanostatic control should be employed to measure impedance spectra of LIRB because the information of batteries during operation is more important than that at the equilibrium-state. For example, high power batteries require low charge transfer resistance during the high rate discharge. Stoynov et al. [1] measured impedance spectra of lead acid battery during charge and discharge at galvanostatic polarization. Itagaki et al. [2-4] determined time-dependent impedance spectra of LIRB’s during charge-discharge sequence.

Figure 1 shows charge curve of a LIRB and 3D impedance spectra measured during the charge simultaneously. Three impedance spectra were determined by arranging a reference electrode in a laboratory cell of LIRB. The axes of 3D impedance are real and imaginary parts of impedance and time. For example, charge transfer resistance related to the diameter of capacitive loop of (c) positive electrode in high frequency range decreased with increasing the state of charge. In this presentation, the authors show the experimental results of 3D impedance spectra of LIRB, and discuss the intercalation/deintercalation mechanisms of lithium-ion at negative and positive electrodes.

 

References:

[1] Z. B. Stoynov, B. S. Savova-Stoynov, T. Kossev, J. Power Sourses,
30 (1990) 275.

[2] M. Itagaki, N. Kobari, S. Yotsuda, K. Watanabe, S. Kinoshita, M. Ue, J. Power Sources, 135 (2004) 255.

[3] M. Itagaki, N. Kobari, S. Yotsuda, K. Watanabe, S. Kinoshita, M. Ue., J. Power Sources, 148 (2005)78.

[4] M. Itagaki, K. Honda, Y. Hoshi and I. Shitanda, J. Electroanal. Chem., 737 (2015) 78.

Figure 1
Electrochemical Synthesis of Ammonia: Status, Challenges and Opportunities
Authors: Xu Hui , McCallum Tom
Published: February 2020

Ammonia (NH3) is an extremely important feedstock producing nitrogen fertilizers that provide essential nutrition for crop vitality. The worldwide production of ammonia is more than 100 million tons per year. The conventional Haber–Bosch ammonia production process requires high pressure and temperature (up to 300 atm and 500°C) and is, as such, extremely energy-intensive.

Electrochemical synthesis of ammonia via an ion exchange membrane (IEM) may proceed at lower temperature and pressure thus potentially reducing the energy consumption 1. However, the application of this technology has been restricted by lower ammonia production (< 10-7 mol/s-cm2) and Faradic efficiency, making the initial capital cost very prohibitive.  

This work will present current status and challenges of electrochemical synthesis of ammonia, based on our technology development and other noteworthy researches in this area. The strategies to improve the ammonia production rate, efficiency and stability have been elaborated, which include advanced catalyst development, alternative membranes 2 (e.g. alkaline membrane, proton or oxygen ion-conducting metal oxide electrolyte) and optimized operating conditions (e.g., temperature, pressure, and humidity). In particular, the electrochemical synthesis of ammonia using water (free of H2) and nitrogen as reactants is analyzed. Finally, the integration of this technology with off-peak renewable energy towards building distributed ammonia plants will be evaluated. 

The successful application of this technology may lead to ammonia synthesis via a more environmentally-benign and economically viable approach, compared to the conventional Haber-Bosch process. The synthesized ammonia using renewable energy can be widely used as a feedstock for fertilizers in agriculture. The ammonia can also be considered as a means of storing surplus renewable energy during off-peak hours. 

Reference:

Marnellos, G., and M. Stoukides, “Ammonia synthesis at atmospheric pressure,” Science, 282(2), 98-100 (1998).

Licht, S, Cui, B., Wang, B., Li, F-F, Lau, J., and Liu, S., “Ammonia syhthesis by N2 and steam electrolysis in molten hydroxide suspensions of nanoscale Fe2O3”, Science, 345, 637-640 (2014)
(Invited) Non-Visual Defect Monitoring with Surface Photovoltage Mapping
Authors: Findlay Andrew David , Marinskiy Dmitriy , Edelman Piotr , Wilson Marshall , Savtchouk Alexandre , Almeida Carlos , Lagowski Jacek
Published: February 2020

Non-Visual Defects (NVD) is a category of semiconductor material and process induced defects that cause electrical failures, but are not detected with visual wafer inspection tools. This paper gives an overview of our non-contact electrical NVD metrology that uses fast whole wafer inspection with standard mm resolution Kelvin probe surface voltage mapping. In an advanced approach the detected NVD regions are imaged in high resolution (mm range) using Force Kelvin Probe Microscopy. In depth NVD characterization is done with the corona-Kelvin method that quantifies dielectric and interfacial properties in the defect sites. This characterization is performed in a non-invasive fluence range of corona charging and all measurements are non-contact, and do not require fabrication of test devices.

Principles of non-contact surface voltage are explained for whole wafer mapping using a high throughput dual Kelvin-probe approach, and for high-resolution micro-Kelvin Force Probe mapping of defect sites. Application examples are discussed in chronological order of the metrology development, starting with monitoring of plasma damage first introduced about 20 years ago. Further examples include surface voltage mapping of surface alkali-metals including novel high resolution micro-Kelvin Force Probe results. Recent trends in monitoring are illustrated with patterned wafer mapping and micro-scale intra die NVD’s. Finally an extension of the technique to defect mapping in SiC is presented together with in-depth corona-Kelvin characterization of defect sites. A broad application range is demonstrated with examples relevant to silicon IC, silicon photovoltaics and to wide bandgap epitaxial SiC.
Combined Effect of Rapid Thermal Annealing and Crystal Nature on the Gate Oxide Reliability of Czochralski Silicon
Authors: Shin Jung-Won , Lee Woo-Sung , Kim Ja-Young , Lee Anselmo Jaehyeong , Kang Hee-Bog , Lee Sung-Wook
Published: February 2020

Internal gettering (IG) of metallic impurities (MI) in Czochralski silicon (CZ-Si) is one of the key techniques in modern microelectronic engineering to manufacture high-performance devices with high process yield. Various silicon substrates such as EPI wafers with heavily boron-doped substrates, ion-implanted wafers, and rapid-thermal annealing (RTA) treated wafers have been used to enhance IG ability [1-2] and retain denuded zone (DZ) for the active area of devices. Especially, RTA-treatment is an easy way to form IG and DZ simultaneously with a rapid heat process that injects the intrinsic point defects, mainly vacancies, into the bulk. However, it was reported that vacancy clusters, or ‘nano voids’ whose size was less than 50nm [2-3] could be formed in the near-surface region after RTA process via vacancy self-trapping [4], which can possibly degrade the performance and yield of device. In this study, we investigated the effect of RTA treatment on the gate oxide reliability and their relation to the crystal nature, i.e., as-grown point defect distribution in silicon wafers.

As shown in Fig. 1 a), we performed the Cu-contamination method [5] on the prepared samples to verify the crystal nature of each sample. After that, we separated the samples into two groups whether they treated by RTA or not, and carried out time-zero dielectric breakdown (TZDB) reliability tests on the patterned poly-Si/oxide/Semiconductor capacitors with the gate oxide thickness of 10 nm. As shown in Fig. 1 b), distribution of TZDB failed cell on the wafer was closely related to the crystal nature. Moreover, it was revealed that a vacancy-dominant region tends to have lower breakdown field than an interstitial-dominant region. These phenomena were only found in RTA-treated wafers and entire fail rate was drastically increases when RTA effect was combined with vacancy-dominated region, which was shown in Fig. 1 b). We assumed that as-grown vacancies contained in the vacancy-dominated region tend to enhance the supersaturation of vacancy beneath the oxide-semiconductor interface, so the formation of nano voids was accelerated and the breakdown field was lowered due to the presence of such defects. A detailed mechanism of the experimental result will be discussed.

Figure 1. a) Crystal nature measured by Cu contamination method and b) TZDB frequency with or without RTP

References

1. Jea-Gun Park, Gon-Sub Lee, Jin-Seo Lee, Kazunari Kurita, Hisashi Furuya, Mater. Sci. Eng., B, 134, 249 (2006).

2. G.Kissinger, D.Kot, W.Häckl, ECS transactions, 33(11), 113 (2010).

3. Thomas A. Frewen, Talid Sinno, Appl. Phy. Lett, 89, 191903 (2006).

4. M.Gao, X.F.Duan, L.-M.Peng, Appl. Phy. Lett., 73, 2311 (1998).

5. Sang-Wook Wee, Sung-Wook Lee, Ki-Man Bae, and Kwand-Salk Kim, U. S. Patent 7,901,132.

Figure 1
(Invited) Characterization of Group IV Based Nanowires Manufactured on Advanced Engineered Substrates
Authors: Radamson Henry H. , Noroozi Mohammad , Toprak Muhammet , Luo Jun , Wang Guilei , Zhao Chao
Published: February 2020

Advanced substrate engineering is gaining new applications for nano-scaled devices where such substrates offer unique possibility to tailor the strain and the carrier transport. In general, XOI is a notation for wafers with a semiconductor-on-insulator where X is any alloy from SiGeSnC materials or III-V compounds.

In special, strained XOI substrates (s-XOI) are widely used to manufacture nanowire transistors where the carrier mobility is enhanced by strain.

So far, wafer bonding or condensation methods have been applied to manufacture XOI wafers. In case of SiGe-on-insulator (SGOI), a thin SiGe layer is grown on SOI and subsequently oxidized to create a single SiGe layer on oxide. During oxidation the Si atoms are preferably consumed and Ge atoms are driven toward the oxide box acting as a diffusion barrier. Therefore SGOI wafers suffer from point defects which have a strong influence on the carrier mobility, thermal conductivity and even optical properties. Post annealing may improve the layer quality and majority of the defects could be disappeared.

The wafer bonding is more complicated and sensitive method. This relates to the requirements e.g. surface flatness, layer quality of the semiconductor and the amount of exerting bonding force.

In manufacturing of Ge-on-insulator wafers, a high quality Ge layer is grown at 700-750 °C on a low quality Ge (grown at 300-400 °C). The Ge layers are transferred and bonded to oxide wafers by using a uniform force of few kNs. Afterwards, the wafers are annealed at 500-600 °C before etch back step (see Fig.1). It is important to mention here that the annealing step has to be decreased for bonding of GeSn-on-insulator wafers in order to avoid strain relaxation.

In this work, manufacturing methods for different sizes of XOI and s-XOI wafers are presented and an attention is paid for using the manufactured XOI wafers for the thermoelectric application, where lateral nanowires are formed. As an example, for SiGe nanowires the seebeck coefficient is enhanced in presence of defects, however, any kind of defects in XOI wafers degrade the channel mobility in the processed MOSFETs.

Characterization techniques e.g. high-resolution reciprocal maps using synchrotron x-ray beam, high resolution transmission electron microscopy, and photoluminescence were applied to detect the defects and estimate the strain relaxation. The experimental data is linked to explain the electrical properties of XOI wafers and finally to nanowires and MOSFETs.

Figure 1
Chemical Bath Deposited ZnO:Al Thin Films and Their Application to CuInGaSe2 Thin Film Solar Cells
Authors: Choi Yesol , Jang Hyun Jun , Hong Ki-Ha , Chung Choong-Heui
Published: February 2020

ZnO:Al thin films have been widely used as transparent conductors in variety of optoelectronic devices including CuInGaSe2 thin film solar cells. However, high cost sputtering process has been typically employed to prepare high quality ZnO:Al thin fil simultaneously having both high optical transmittance and low sheet resistance. In this study, we present the ZnO:Al thin films prepared by the chemical bath deposition using NH4OH-based aqueous solution on seeded glass substrates. We also report their properties and application to CuInGaSe2 thin film solar cells as a top transparent electrode. A seed layer on glass substrate was prepared by spin-coating of ZnO nanoparticles with size of a few tens of nanometer. For the chemical bath deposition process, ZnO powder was dissolved in NH4OH-based aqueous solution and un-dissolved ZnO powder was removed by transferring the ZnO solution through 1 um filter. Retrograde solubility of ZnO in NH4OH-based aqueous solution allows us to deposit ZnO thin films by raising temperature of the bath from room temperature to 80 oC. To obtain compact film by enhancing growth rate of crystal in lateral direction, a certain amount (~0.5-2 mM) of ammonium citrate was added into the bath. A various amount of Al(NO3)3 was added into the bath as a aluminum source to maximize electrical conductivity by forming Al substitution in Zn site. The prepared ZnO:Al films were irradiated by UV for 1 min. Optimized ZnO:Al films showed (0002) preferred orientation, optical transmittance of 90% and sheet resistance of 75 ohm/sq. Furthermore, the prepared ZnO:Al thin film was successfully implanted to CIGS thin film solar cells as a top electrode showing power conversion efficiency of 12.5% comparable to the performance (~13.7%) of CIGS solar cells having a sputter-deposited ZnO:Al film transparent electrode.
Ab-Initio Studies of Acceptor Impurities and Stability of Complexes in Ge
Authors: Emmanuel Igumbor , Mapasha Edwin R , Richard Andrew C , Meyer Walter E
Published: February 2020

The application of germanium (Ge) as a promising material for complementary metal-oxide semiconductors (CMOS) technology is attracting attention due to its narrow band gap, high carrier mobility and low voltage operations. Recent experimental and theoretical studies revealed that dopants in Ge cluster with vacancies forms with lower energies and contribute to low activation of dopants impurity in Ge.  DFT electronic simulation have been used to  provide concise information about the formation of  defect clusters and complexes that influence diffusion mechanisms in Ge. Our  main objective in this study is to use simulations based on ͑DFT to calculate the  structural, electronic properties  and  interactions between acceptors and Ge in different configurations with a view to finding the most energetically stable configuration of various defect complexes in Ge.

By means of density functional theory (DFT), we present ab-initio calculation of interactions between A (A: Be,Mg, Ca, Sr, Ba, Ga, In) vacancy complexes (A-VGe) and  vacancy-interstitial complexes (A-VGeIA) in two configurations of the hexagonal (H) and tetrahedral (T)  in Ge. These calculations employed a projector augmented wave (PAW) pseudopotentials within the generalized gradient approximation (GGA). The geometric structures and  formation energies of A-VGe and A-VGeIA  in both the T and H configurations for the neutral charge state were obtained. The formation energies of A-VGe were low and energectically favourable with Ga-VGe and Ca-VGe forming with the lowest  formation energies at -1.24 and -0.38 eV respectively. For the A-VGeIA,  the results of  the  H configuration were   more energetically favourable  and forms with lower formation energies  than the T configuration. The Ca-VGeICa and Be-VGeIBe forms with  the lowest formation energies of -2.59 and -1.49 eV respectively. The stability of the A-VGeIA and A-VGe complexes in Ge were obtained from their binding energies. The binding energies (Eb ) which are defined as the energy required to split up the defects cluster into well separated non-interacting defect  is given as

Eb =  E(formation)(VGe) + E(formation)(AGe) - E(formation){defect-complex},

where E(formation)(VGe),   E(formation)(AGe) and E(formation)(defect-complex) are the formation energies of the neutral charge state of the germanium vacancy, interstitials and defect-complexes. The above equation could be interpreted as  the energy gain of the bonded structure with respect to the isolated components. Positive binding energies suggest that the defect complexes are stable and cannot easily dissociate. The calculated binding energies of both the A-VGe and the A-VGeIA  displayed  the ability of these complexes to form without dissociation.  For the  A-VGeIA,  the H configuration forms with more favourable binding energies than the  T configuration.   In summary the detailed  calculated results we have presented are  expect  to be useful in the process modeling of Ge-based devices.
Advanced Wet Clean Technology at Lightly Doped Drain Layers in FinFET
Authors: Li Jian , Sih Vincent , Zhan Hui
Published: February 2020

Along with fast-paced development of semiconductor industry, circuit patterns become much smaller and finer. Currently the pattern design migrates from traditional planar structure to three-dimensional FinFET. Therefore how to remove surface particles in various sizes effectively without damaging the pattern structures in the higher aspect ratio is more and more essential to achieving critical rapid yield ramps in the advanced technology node.

In the FinFET process scheme, after formation of poly gate, Lightly Doped Drain (LDD) implants are invented to alleviate the short channel effect between Source and Drain Junction. In LDD layers, low density impurity of B+ and As+are implanted into PFET and NFET, respectively. The repeated implant steps will inevitably bring certain amount of surface particles, which are defined in higher killer ratio, since they can be embedded defect after few nitride spacer layers are deposited, causing the poor device performance and low product yield.

Figure 1 shows the typical SEM images of various surface particles generated during repeated LDD implant steps. Standard RCA Clean 1 (SC1) with the mixture of hydrogen peroxide, ammonium hydroxide and deionized water usually would be applied to reduce organic and surface particle. But particles removal efficiency (PRE) is not satisfied for advanced FinFET manufacturing. Aerosol or nanospray to dispense chemical solution with the mixture of nitrogen gas in high pressure is another candidate to possess higher PRE, however, the traditional aerosol technique would create liquid droplets in a large range of size, so the non-uniformed momentum of liquid droplet can result in severe pattern damage on poly gate at LDD layers.

In this paper, we report an advanced wet clean method based a single wafer clean toolset. By using this state-of-the-art wet clean technology, we can control the size and velocity of liquid droplets accurately during the clean chemical dispense. In this sense, with high PRE for surface particles, in the meantime, there is no sacrifice of gate pattern damage in LDD layers. It was demonstrated on FinFET production wafers that surface particles were reduced by as much as 30% with the new clean technology implementation. Also, about 5% yield improvement was observed for the new clean process.

Figure 1: Typical SEM images of surface particle defect in LDD layers

Figure 1
Impact of Sacrificial Cosumption of Substrate By Thermal Oxidation on Electron Mobility of 4H-SiC Mosfets
Authors: Kita Koji , Hirai Hirohisa
Published: February 2020

4H-SiC MOSFETs are extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. A significant degradation of electron mobility in inversion channel has been often reported, however, the dominant factors which deteriorate the channel characteristics have not yet been clarified well. In this study we investigated the effects of thermal oxidation during MOSFET fabrication processes on the quality of substrate surface, from the view point of channel mobility degradation.

Lateral n-MOSFETs with various gate length, Lg=80~500 μm, were fabricated on p-type 4H-SiC (0001) wafers with Al-doped epitaxial layers. Source/drain (S/D) regions were formed by P implantation, followed by an activation annealing at 1650°C with a carbon cap. Ni Ohmic contacts for n+ S/D were formed by PMA at 1000°C for 1 min in N2 ambient. Finally Al was deposited and patterned as the gate electrode. Before the gate oxide formation, we intentionally consumed 5~60 nm of SiC substrate by a thermal oxidation followed by a chemical etching of SiO2 in HF solution. The gate oxide was thermally-grown in dry-O2 at 1300°C, followed by a post-oxidation-annealing in O2 at 800°C [1]. The consumed SiC thickness in total, including the gate oxide formation process as the final step, was varied from 9 to 72 nm. As a result, a degradation of field-effect-mobility was clearly observed when the sacrificially-consumed SiC thickness increased. To avoid the additional effects of surface damage due to the high-temperature activation annealing, we also prepared a MOSFET without 1650°C annealing, and successfully observed a further enhancement of channel mobility ~10% by minimizing the consumed SiC thickness during the device fabrication processes. Even though we expected the activation of only a few percentage of implanted P atoms, thanks to the thermal oxidation process at 1300oC for this sample, we could extract the channel mobility after the calibration of the effects of the parasitic resistance from Lg-dependence of channel resistance.

These results clearly indicate that the sacrificial consumption of SiC substrate surface results in a monotonic degradation of channel mobility. The mechanism of such deterioration has not been clarified yet, but we believe that a degradation of SiC surface quality, possibly due to an accumulation of Al dopants [2] or interstitial C atoms near the SiC surface during the oxidation processes, would explain such change of MOSFET performance.

[1] R. H. Kikuchi and Koji Kita, Appl. Phys. Lett. 105, 032106 (2014).

[2] T. Kobayashi et al., Appl. Phys. Express 7, 121301 (2014).
(Invited) Plasma-Enhanced Quasi-ALE and ALD Processing for Leading-Edge Microfabrication
Authors: Honda Masanobu , Katsunuma Takayuki , Tabata Masahiro , Tsuji Akihiro , Oishi Tomoyuki , Hisamatsu Toru , Ogawa Shuhei , Kihara Yoshihide
Published: February 2020

In recent years, the progression of very large scale integration of semiconductor devices and miniaturization require extension of ultra-high selectivity process and CD control technique exhibiting atomic-layer-level control. We introduce herein a state-of-the-art self-aligned contact (SAC) etching process and multilayer patterning process developed by a new patterning technology using Atomic Layer Etch (ALE) and Atomic Layer Deposition (ALD) towards the 5/7nm generation.

SAC etch processes are known to require SiO2 etching capability with ultra-high selectivity to SiN. We developed a modified ALE process [Quasi-ALE] to make it more suitable for SiO2 etch. By adopting this technology to the SAC process, conventional trade-offs between SiO2 etch through capability and SiO2selectivity to SiN in the fine slit pattern is significantly improved. This achievement is enabled by Quasi-ALE’s independent controllability of the radical flux and ion flux, which precisely controls the reaction layer thickness on the surface, allowing etch process at lower ion energy region which is most effective to improve etch selectivity.

The advancement of EUV lithography toward manufacturability has accelerated the need for innovation in multilayer lithography stack etches. The patterning of high quality sub lithographic patterns is becoming more challenging, especially in regards to line-roughness (LER/LWR) reduction, and selectivity enhancement of thin EUV-resist. Furthermore, patterning with universal CD shrinkage independent of the pattern types (hole, oval, L/S) is also being required. As a result of various techniques were studied for enhancement of fine pattern formation, “fusion of ALD technology and etching” was confirmed to be very beneficial for its capability of atomic-level formation of surface protection film during the etch process. This technology enabled line-roughness reduction with CD shrink control independent of the pattern-size, since the ALD step is used according to the optimum timing during the etch process, which forms uniform deposition on any type of patterns.

As described, precise control of the microfabrication at atomic layer level utilizing Quasi-ALE and ALD technology is becoming mandatory in the generation of 5/7nm.
Novel Anhydrous Hydrazine Delivery for Low Temperature Silicon Nitride Passivation of Sige(110)
Authors: Alvarez Daniel , Spiegelman Jeffrey , Holmes Russell , Ramos Chris , Kummel Andrew , Edmonds Mary , Sardashti Kasra , Wolf Steven
Published: February 2020

New high mobility channel materials such as SiGe, Ge, and InGaAs create difficult thermal constraints on Metal-Nitride deposition, where limits range from 300-400C. It is necessary to: limit atomic diffusion; prevent undesirable phase transitions, strain relaxation and defect formation. Feasibility for low temperature hydrazine (H2NNH2) ALD was reported by George.3  In addition, a new technology that is capable of generating and delivering stable and highly concentrated anhydrous hydrazine gas has been developed by RASIRC.

A thin layer of silicon nitride or silicon oxynitride can act as a diffusion barrier or channel passivation layer prior to dielectric deposition in FinFets or MOSFETs. When employed as a channel passivation layer, further oxidation with anhydrous peroxide leaves Si-N-OH termination, thereby providing good nucleation for High K deposition (Figure 1). This study focuses on developing <400C silicon nitride ALD process. STM/STS and XPS are employed to characterize SiNx film growth on Si0.5Ge0.5(110) (Figure 2). HfO2 is then grown on a Si-N-OH functionalized surface. Electrical characterization of MOSCAP structures has been obtained will be compared to other passivation methods such as ammonia plasma.

Figure 1
(Invited) Atomic Layer Deposition for Catalyst “Bottom-up” Synthesis
Authors: Lu Junling
Published: February 2020

Catalyst synthesis with precise control over the structure of catalytic active sites at the atomic level is of essential importance for the scientific understanding of reaction mechanisms and for rational design of advanced catalysts with high performance. Such precise control is achievable using atomic layer deposition (ALD). ALD is similar to chemical vapor deposition (CVD), except that the deposition is split into a sequence of two self-limiting surface reactions between gaseous precursor molecules and a substrate. The unique self-limiting feature of ALD allows conformal deposition of catalytic materials on a high surface area catalyst support at the atomic level. The deposited catalytic materials can be precisely constructed on the support by varying the number and type of ALD cycles. As an alternative to the wet-chemistry based conventional methods, ALD provides a cycle-by-cycle “bottom-up” approach for nanostructuring supported catalysts with near atomic precision [1, 2].

In this presentation, the capability of achieving precise control over the particle size of monometallic nanoparticles by ALD is emphasized. The possibility of the preparation of single-atom metal catalysts by ALD at elevated temperatures will be discussed [3]. For supported bimetallic catalyst synthesis, I will show the challenges of combing two metal ALD processes to form bimetallic nanoparticles synthesis. Then our recent the strategy developed for selective metal-on-metal ALD for precise synthesis of supported bimetallic catalysts while excluding monometallic formation are particularly highlighted [4, 5]. In the final part of my presentation, I will focus on oxide ALD on metals for precise synthesis of nanostructured metal catalysts, therein, I will discuss the methods of tailoring the catalytic performance of metal catalysts including activity, selectivity and stability, through selective blocking of the low-coordination sites of metal nanoparticles, the confinement effect, and the formation of new metal-oxide interfaces [6, 7].

References

(1) J.L. Lu, J.W. Elam, P.C. Stair, Acc. Chem. Res. 46 (2013) 1806-1815.

(2) J.L. Lu, J.W. Elam, P.C. Stair, Surf. Sci. Rep. 2016, doi:10.1016/j.surfrep.2016.1003.1003.

(3) H. Yan, H. Cheng, H. Yi, Y. Lin, T. Yao, C.L. Wang, J.J. Li, S.Q. Wei, J.L. Lu, J. Am. Chem. Soc. 2015, 137, 10484-10487

(4) J.L. Lu, K.B. Low, Y. Lei, J.A. Libera, A. Nicholls, P.C. Stair, J.W. Elam, Nat. Commun. 2014, 5 3264.

(5) H.W. Wang, C.L. Wang, H. Yan, H. Yi, J.L. Lu, J. Catal. 2015, 324, 59-68.

(6) J.L. Lu, B. Fu, M.C. Kung, G. Xiao, J.W. Elam, H.H. Kung, P.C. Stair, Science 2012, 335, 1205.

(7) H. Yi, H.Y. Du, Y.L. Hu, H. Yan, H.-L. Jiang, J.L. Lu, ACS Catal. 2015, 5, 2735-2739.