(G02 Best Presentation Award Winner) Elaboration and Characterization of CMOS Compatible, Pico-Joule Energy Consumption, Electrochemical Synaptic Transistors for Neuromorphic Computing
Authors: Nguyen Ngoc-Anh , Schneegans Olivier , Rouchou Jouhaiz , Salot Raphael , Lamy Yann , Boissel Jean-Marc , Allain Marjolaine , Poulet Sylvain , Oukassi Sami 
Published: July 2022

Non-Von Neumann computing application constituted by artificial synapses based on electrochemical random-access memory (ECRAM) has aroused tremendous attention owing to its capability to perform parallel operations, thus reducing the cost of time and energy spent [1-3]. Existing ECRAM synapses comprise two-terminal memristors and three-terminal synaptic transistors (SynT). While low cost, scalability, and high density are the highlights for memristors, their nonlinear, asymmetric state modulation, high ON current withdrawal, and sneak path in crossbar array integration prevent them from becoming the ideal synaptic elements for artificial neural networks (ANN) [4]. SynT configuration, on the other hand, offers an additional electrolyte-gated control from which ion doping content can be monitored via redox reactions, thus decoupling write-read actions and improving the linearity of programming states [5-6]. Nevertheless, existing SynTs suffer from different integration issues stemming from liquid-based ionic conductors and manually exfoliated channels. Moreover, several kinds of SynTs possess highly conductive channels in the range of µS to mS, significantly scaling up the energy spent for analog states reading. Despite having numerous communications on the performance of different ECRAM, a comprehensive electrochemical view of ion intercalation into the active material, the main root of conductance modulation, is clearly missing.

In this work, we present the elaboration procedure of an all-solid-state synaptic transistor composed of nanoscale electrolyte and channel layers. The devices have been elaborated on 8’’ Silicon wafers using microfabrication processes compatible with conventional semiconductor technology and CMOS back end of line (BEoL) integration. (Figure 1a)

We demonstrate the excellent synaptic plasticity properties of short-term potentiation (STP) and long-term potentiation (LTP) of our SynT. We performed tests to study the correlation between linearity, asymmetry, and the number of analog states. By averaging the amount of injected ions per write operation, we estimated the energy consumed for switching among adjacent states of this device is 22.5 pJ, yielding area-normalized energy of 4 fJ/µm2. In addition, operating in the range of nS, our SynTs meet the critical criteria of low energy consumption for both write and read operations. Endurance was highlighted by cycling in ambient conditions with 100 states of potentiation and depression for over 1000 cycles with only a slight variation of Gmax/Gmin ratio of 6.2 % (Figure 1b, c). Approximately 95 % accuracy in MNIST pattern recognition test on ANN in the crossbar array configuration has been obtained by simulation with SynTs as synaptic elements reassured SynT is a promising candidate for future neuromorphic computing hardware.

To shed light on the properties of intercalation phenomena of Li ions into the TiO2 layer, a further electrochemical study on a cell comprising Ti/TiO2/LiPON/Li corresponding to the SynT gate stack was performed. This understanding will help to elucidate the correlation with conductance modulation characteristics for a synaptic transistor. Multiple tests were carried out, including cyclic voltammetry (CV) with different scan rates, rate capability with Galvanostatic cycling with potential limit (GCPL), and electrochemical impedance spectroscopy (EIS) on different states of charge. A circuit model was introduced to fit the frequency response of the cell, and it explained well the behavior of charging capability at different OCV (Figure 1d).

References

[1] P. Narayanan et al., “Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory,” IBM J. Res. Dev., vol. 61, no. 4/5, p. 11:1-11:11, Jul. 2017, doi: 10.1147/JRD.2017.2716579.

[2] J. Tang et al., “ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018, p. 13.1.1-13.1.4. doi: 10.1109/IEDM.2018.8614551.

[3] Y. Li et al., “In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory,” Front. Neurosci., vol. 15, p. 636127, Apr. 2021, doi: 10.3389/fnins.2021.636127.

[4] M. A. Zidan, H. A. H. Fahmy, M. M. Hussain, and K. N. Salama, “Memristor-based memory: The sneak paths problem and solutions,” Microelectron. J., vol. 44, no. 2, pp. 176–183, Feb. 2013, doi: 10.1016/j.mejo.2012.10.001.

[5] Y. van de Burgt et al., “A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing,” Nat. Mater., vol. 16, no. 4, pp. 414–418, Apr. 2017, doi: 10.1038/nmat4856.

[6] E. J. Fuller et al., “Li-Ion Synaptic Transistor for Low Power Analog Computing,” Adv. Mater., vol. 29, no. 4, p. 1604310, Jan. 2017, doi: 10.1002/adma.201604310.

Figure 1