bluuebunny/crossref_metadata_2025 huggingface dataset:
An Engineering Approach to Hertzian Contact Elasticity—Part I
Authors: Houpert Luc
Published: April 2007

Results given in this paper are threefold. In the case of Hertzian line contact, a new load/deformation relationship is derived analytically and use is made of the thickness of the outer race section. A minor effect of the section thickness is shown. The exponent on the deformation is 1.074 (instead of 1.1 usually accepted). Results calculated with the new relationship are successfully compared to results calculated with other published relationships and also are compared successfully to some available experimental results. For the case of point contact, useful relationships, obtained by curve-fitting, are given to calculate easily the load versus deformation, maximum Hertzian pressure and ellipse contact dimension as a function of a dimensionless load parameter and ratio k of equivalent radii (instead of sum of curvatures and elliptical integrals before). A large range of k is covered, from 0.05 (found at roller rib contact) to 13,000 to cover all bearing cases, from ball bearings to spherical and tapered roller bearings. Finally, an important analytical relationship, based on curve-fitting, also is suggested to describe a smooth transition from point contact to line contact as the load increases. It is recommended to define bearing setting and bearing preload with the suggested relationship.
A Three-Dimensional Thermal-Mechanical Asperity Contact Model for Two Nominally Flat Surfaces in Contact
Authors: Liu Geng , Wang Qian , Liu Shuangbiao
Published: April 2007

The rough surface contact in a tribological process involves frictional heating and thermoelastic deformations. A three-dimensional thermal-mechanical asperity contact model has been developed, which takes into account steady-state heat transfer, asperity distortion due to thermal and elastic deformations, and material yield. The finite-element method (FEM), fast Fourier transform (FFT), and conjugate gradient method (CGM) are employed as the solution methods. The model is used to analyze the thermal-mechanical contact of typical rough surfaces and investigate the importance of thermal effects on the contact performance of surface asperities.
Investigation of Slider Vibrations Due to Contact With a Smooth Disk Surface
Authors: Kohira Hidekazu , Tanaka Hideaki , Matsumoto Masaaki , Talke Frank E.
Published: April 2007

The dynamic behavior of pico sliders is investigated during slider-disk contacts as a function of velocity, pitch angle, crown height, and lubricant thickness using laser Doppler vibrometry and acoustic emission sensors. Analog and digital filtering methods are applied to distinguish air bearing and slider body resonances from frequencies related to disk runout, load beam design, and gimbal structure. Sliders with high pitch angle and small crown were found to exhibit smaller vibration amplitudes after slider-disk contacts than sliders with low pitch angle or large crown. The lubricant thickness of the disk was found to affect both the glide avalanche height of the disk and the dynamic behavior of the slider. The results show that roll and pitch frequencies of the air bearing increase with decreasing disk velocity.
Three-Dimensional Contact Analysis of Elastic-Plastic Layered Media With Fractal Surface Topographies
Authors: Komvopoulos K. , Ye N.
Published: April 2007

Three-dimensional rough surfaces were generated using a modified two-variable Weierstrass-Mandelbrot function with fractal parameters determined from real surface images. The number and size of truncated asperities were assumed to follow power-law relations. A finite element model of a rigid sphere in normal contact with a semi-infinite elastic-plastic homogeneous medium was used to obtain a constitutive relation between the mean contact pressure, real contact area, and corresponding representative strain. The contact model was extended to layered media by modifying the constitutive equation of the homogeneous medium to include the effects of the mechanical properties of the layer and substrate materials and the layer thickness. Finite element simulations of an elastic-plastic layered medium indented by a rigid sphere validated the correctness of the modified contact model. Numerical results for the contact load and real contact area are presented for real surface topographies resembling those of magnetic recording heads and smooth rigid disks. The model yields insight into the evolution of elastic, elastic-plastic, and fully plastic deformation at the contact interface in terms of the maximum local surface interference. The dependence of the contact load and real contact area on the fractal parameters and the carbon overcoat thickness is interpreted in light of simulation results obtained for a tri-pad picoslider in contact with a smooth thin-film hard disk.
Structural Acoustic Problems With Absorbent Layers Within Laminated Composite Enclosures
Authors: Guha Niyogi Arup
Published: April 2007

Studies on coupled structural acoustic problems within laminated composite enclosures are presented. Isoparametric quadratic boundary element formulation for the acoustic domain is coupled to the structural properties of the enclosure through mobility relations obtained from free vibration finite element analysis of the dry enclosure visualized as a folded plate with first order transverse shear deformation and rotary inertia. Velocity amplitudes and forcing frequency is specified over certain parts of the boundary. The rest is interactive boundary. Absorbent layers at the boundary are accommodated through admittance relation. Results show that impact of absorbent layers is frequency dependent while modifying structural damping has a better prospect.
Acoustic-Structural Resonances of Thin-Walled Structure—Gas Systems
Authors: Kruntcheva Mariana R.
Published: April 2007

This paper summarizes a theoretical study, which is a natural continuation of approximately 50 years of research in the field of acoustoelasticity. Recently, the researchers’ interest has been directed towards considering compressible fluid in contact with thin walled structures as it was found that the acoustic-structural coupling significantly changes the dynamic behavior of the system. Despite the interesting findings the main results still need additional, numerical, or experimental verification. The present work is intended to cast more light on the acoustic-structure coupling of light fluid-shell systems using a numerical approach, namely 3-D finite element (FE) modeling. Two different acoustoelastic systems are considered. The first system is a thin circular cylindrical shell containing light fluid in a coaxial annular duct and the second system is a thin-walled vehicle passenger compartment interacting with the enclosed cavity. Both systems are studied using ANSYS finite element code. The modeling involved shell finite elements for the structure and 3-D acoustic elements for the cavity. The 3-D FE modal analysis used produced results visualizing the complex picture of acoustic-structure coupling. It was confirmed that (1) in both fluid-elastic systems the strongest acoustic-structural coupling exists if the resonances of uncoupled acoustic and mechanical systems are close and (2) the nature of the acoustic-structural coupling is identical in the two cases studied. However, it was found that strong coupling between the thin-walled structure and the acoustic cavity exists in the vicinity of any uncoupled acoustic resonance. Thus, the coupled properties of the systems were found to be dominated by the uncoupled acoustic resonances. As the focus of this study is on the mode shapes of vibration, it was found that coupled acoustic-structure modes of vibration exist in the neighborhood of an uncoupled acoustic resonance, which means that the coupled system manifests a specific type of energy exchange. These modes were termed coupled “combined” modes to differentiate from the coupled component responses. It was also found that the coupled “combined” modes are clustered around a rigid-walled cavity mode, and any acoustic-structure resonance of a given group involves this particular uncoupled acoustic mode. In conclusion, it is shown that the acoustic-structure interaction causes the appearance of coupled “combined” modes not existing in the shell in vacuo or rigid-walled acoustic spectrum. It was found also that the subsystems preserve their capability of independent vibration responses, i.e., the response at the component modes is believed to be strong at their uncoupled frequencies.
A Genome-Wide Association Study of Type 2 Diabetes in Finns Detects Multiple Susceptibility Variants
Authors: Scott Laura J. , Mohlke Karen L. , Bonnycastle Lori L. , Willer Cristen J. , Li Yun , Duren William L. , Erdos Michael R. , Stringham Heather M. , Chines Peter S. , Jackson Anne U. , Prokunina-Olsson Ludmila , Ding Chia-Jen , Swift Amy J. , Narisu Narisu , Hu Tianle , Pruim Randall , Xiao Rui , Li Xiao-Yi , Conneely Karen N. , Riebow Nancy L. , Sprau Andrew G. , Tong Maurine , White Peggy P. , Hetrick Kurt N. , Barnhart Michael W. , Bark Craig W. , Goldstein Janet L. , Watkins Lee , Xiang Fang , Saramies Jouko , Buchanan Thomas A. , Watanabe Richard M. , Valle Timo T. , Kinnunen Leena , Abecasis GoncÌ§alo R. , Pugh Elizabeth W. , Doheny Kimberly F. , Bergman Richard N. , Tuomilehto Jaakko , Collins Francis S. , Boehnke Michael
Published: April 2007

Identifying the genetic variants that increase the risk of type 2 diabetes (T2D) in humans has been a formidable challenge. Adopting a genome-wide association strategy, we genotyped 1161 Finnish T2D cases and 1174 Finnish normal glucose-tolerant (NGT) controls with >315,000 single-nucleotide polymorphisms (SNPs) and imputed genotypes for an additional >2 million autosomal SNPs. We carried out association analysis with these SNPs to identify genetic variants that predispose to T2D, compared our T2D association results with the results of two similar studies, and genotyped 80 SNPs in an additional 1215 Finnish T2D cases and 1258 Finnish NGT controls. We identify T2D-associated variants in an intergenic region of chromosome 11p12, contribute to the identification of T2D-associated variants near the genes
IGF2BP2
and
CDKAL1
and the region of
CDKN2A
and
CDKN2B
, and confirm that variants near
TCF7L2
,
SLC30A8
,
HHEX
,
FTO
,
PPARG
, and
KCNJ11
are associated with T2D risk. This brings the number of T2D loci now confidently identified to at least 10.
The Future of CMOS -- Limits and Opportunities
Authors: Ning Tak H.
Published: April 2007

The development of CMOS technology is always driven by system needs. Traditionally, these needs have been met quite satisfactorily by simply reducing the physical size of the transistors as guided by the MOSFET scaling theory and increasing the chip-level integration density as anticipated from Moore's Law. Now that CMOS has reached some of its key scaling limits, continued progress has to come from innovations beyond the traditional development paths, again guided by anticipating and addressing system designers' concerns and needs. To make real progress, we need to understand where CMOS scaling has run into limits and where the new barriers are. In this talk, we examine the factors limiting the scaling of CMOS as well as the opportunities for extending current CMOS technology to continue satisfying the needs of system designers.
Integration Challenges for Advanced Process-Strained CMOS on Biaxial-Strained-SOI (SSOI) Substrates
Authors: Wei Andy , Duenkel Stefan , Boschke Roman , Horstmann Manfred
Published: April 2007

This work reviews the integration of process-induced stressors into transistors fabricated on biaxially-strained-SOI substrates. Tensile and compressive overlayers, embedded-SiGe, and multiple stress memorization techniques have been evaluated on strained-SOI substrates. All process-induced strain techniques are compatible with strained-SOI, except for a stress memorization technique which requires amorphization of the source/drain regions. The compatible techniques increase NMOS drive current and PMOS drive current comparably on strained-SOI and standard unstrained-SOI. This results in no loss of short channel PMOS performance but only a moderate gain in short channel NMOS performance, when SSOI is compared to standard unstrained-SOI.
Correlation of Local Strain in a TEM Sample and in the Bulk for a Recessed SiGe CMOS Structure
Authors: Zhao Wenjun , Duscher Gerd , Zikry Mohammed , Chopra Saurabh , Öztürk Mehmet C. , Rozgonyi George
Published: April 2007

The strain distribution of a strained Si channel in a embedded SiGe PMOS test structure was investigated with experimental convergent beam electron diffraction (CBED) measurements and finite element (FE) calculations. The strain distribution both in a TEM sample and in the bulk sample was examined and correlated. It was found that the magnitude of the longitudinal strain, εx along the [-1,1,0] channel direction, is about 20% higher in the TEM sample than in the bulk; whereas the transverse strain, εy along [-1,-1,0] parallel to the TEM sample thinning direction, is tensile in the TEM sample due to the loss of constraints, while it is zero in the bulk. This combined approach can be sued to successfully explain data from other CBED studies of strained Si devices and is generally applicable for nano scale strain determination in advanced generation CMOS technology nodes.
Origin and Suppression of Junction Leakage in Germanium-On-Silicon Structures
Authors: Claeys Cor , Sonde Sushant , Simoen Eddy , Satta Alessandra , De Jaeger Brice , Nicolas Gareth , Meuris Marc
Published: April 2007

Diode structures fabricated on Germanium-On-Silicon (GeOS) are investigated for junction leakage current pertinent to the origin and different processing parameters. It is observed that the prime cause of the leakage at room temperature is the defects in the bulk and the interface states associated with the Ge-SiO2 interface. Higher well doping is seen to have a positive impact on total junction leakage while the perimeter leakage shows improvement with Post Metallization Annealing (PMA) temperature.
Relaxation of Strained Si1-XGeX by Dry Oxidation
Authors: Min Byoung Gi , Ko Dae-Hong , Cho Mann-Ho , Lee Tae-Wan , Choi Kyu Jin
Published: April 2007

We investigated strain changes in Si1-XGeX layers on silicon substrates upon oxidation. We grew Si1-XGeX layers with different Ge fractions (x=0.15 and 0.3) on chemically cleaned silicon substrates by the UHV CVD process. Oxidation in a vertical furnace at 800C and 900C in an O2 gas ambient produced a silicon oxide layer and a silicon germanium layer that was richer in Ge-content than initial Si1-XGeX films. Initial compressively strained Si1-XGeX films are fully strained in this range of Ge fractions. The strain in the Ge- rich layer increased and then decreased as the oxidation temperature and time increased. In comparison, the strain of the remaining initial Si1-XGeX gradually relaxed with an increase in oxidation time and temperature. The relaxation occurred through the generation of dislocations and defects at the interface of the Si (100) substrate.
A Step Towards a Better Understanding of Silicon Passivated (100)Ge p-Channel Devices
Authors: Pourtois Geoffrey , Houssa Michel , De Jaeger Brice , Leys Frederik , Kaczer Ben , Martens Koen , Caymax Matty , Meuris Marc , Groeseneken Guido , Heyns Marc
Published: April 2007

An asymmetric shift of the capacitance-voltage characteristics of n-Ge/Si/SiOx/HfO2/TaN p-FET is reported, namely a shift of the threshold voltage (Vth) towards positive values in inversion, while the flat-band voltage (Vfb) remains constant. First-principles calculations on silicon-passivated germanium surfaces reveal the formation of a dipole layer at the Ge/Si interface, which leads to a decrease of the substrate work-function/threshold voltage by 0.5-0.6V. Silicon-induced surface states are also found in the germanium band-gap. When the substrate Fermi level is located near these states, electrons are transferred to the silicon layer and compensate the work-function shift, explaining the absence of Vfb shift. We propose a possible remedy for this asymmetry by inverting the strain at the Ge/Si interface. The growth of Si/strained- Ge/Si layers reduces the interface dipole and cleanses the electronic gap from interface states. The combination of these two factors is expected to restore the symmetry between Vth and Vfb.
Silicon Nanowire: Technology Platform, Devices, Applications and Challenges
Authors: Lo Patrick , Singh Navab , Rustagi Subhash , Balasubmaramian Narayanan , Kwong Dim-Lee , Ngyuen Hoi
Published: April 2007

This paper gives a brief overview of the semiconductor nanowires, in particular the Si- and Ge-nanowires, and summarizes the status of CMOS-compatible nanowire devices. Results were based on the research conducted recently in the Institute with the nanowire technology platform. To facilitate the realization of controllable, scalable and increasing functionality, top-down approach was adopted for the platform establishment on our 8 CMOS fabrication line. Gate-All-Around (GAA) nanowire FET is chosen as test vehicle, which is projected as the final architecture carrying the CMOS towards the end-of-the-roadmap for Si-devices. Fabrication technology is presented with various gate stacks. Excellent transistor characteristics of GAA Si-nanowire FETs are illustrated with near-ideal subthreshold, low DIBL, high ION/IOFF, accompanied with the demonstration of high gain CMOS Inverter. Impact of low temperature on device behavior is discussed. Ge-wire devices are also presented along with the well behaved vertically stacked device structures. Lastly, the challenges are also discussed.
Fabrication of InP/SiO2/Si Substrate using Ion-Cutting Process and Selective Chemical Etching
Authors: Chen Peng , Xu Dapeng , Mawst Luke , Henttinen Kimmo , Suni Tommi , Suni Ilkka , Kuech T.F. , Lau S. S.
Published: April 2007

In this study, an InP layer was transferred onto a Si substrate coated with a thermal oxide, through a process combining ion-cutting process and selective chemical etching. Compared with conventional ion-cutting of bulk InP wafers, this layer transfer scheme not only takes advantage of ion- cutting by saving the remaining substrates for reuse, but also takes advantage of selective etching to improve the transferred surface conditions without using the chemical and mechanical polishing. An InP/InGaAs/InP heterostructure initially grown by MOCVD was implanted with H+ ions. The implanted heterostructure was bonded to a Si wafer coated with a thermal SiO2 layer. Upon subsequent annealing, the bonded structure exfoliated at the depth around the hydrogen projected range located in the InP substrate. Atomic force microscopy showed that after selective chemical etchings on the as-transferred structure, a final structure of InP/SiO2/Si was obtained with a relatively smooth surface.
Improved Current Drivability and Gate Stack Integrity using Buried SiC Layer for Strained Si/SiGe Channel Devices
Authors: Zang Hui , Loh Wei Yip , Oh Hoon Jung , Choi Kyu Jin , Nguyen Hoai Son , Lo Patrick , Cho Byung Jin
Published: April 2007

We report a novel Si/Si1-xGex channel with improved current drivability and reliability using a buried Si0.99C0.01. It is also found that the Si/Si1-xGex/Si0.99C0.01 structure is effective in reducing Ge out-diffusion which helps to improve gate dielectric interface quality.
DyScHfOx as High-κ Gate Dielectrics: Structural and Electrical Properties
Authors: Adelmann Christoph , Van Elshocht Sven , Lehnen Peer , Conard Thierry , Franquet Alexis , Zhao Chao , Ragnarsson Lars-Ake , Chang Vincent , Cho Hag-Ju , Hong-Yu Yu , De Gendt Stefan
Published: April 2007

DyScHfOx high-κ dielectric thin films have been grown by atomic vapor deposition using Dy(EDMDD)3, Sc(EDMDD)3, and Hf(OBut)2(mmp)2. It was found that the entire DyxScyHfzOw com-positional range can be realized with this process. XRD showed that DyScO3 was amorphous as grown, whereas ScHfOx and Dy-HfOx were crystalline. The crystalline phase of both HfxSc1-xOy and HfxDy1-xOy changed from monoclinic to cubic around x = 0.1. Electrical characterization of nMOS capacitors and long-channel transistors showed that the EOT-leakage scaling of DyScOx was comparable to that of HfO2, whereas both DyHfOx and ScHfOx were comparable to HfSiO4. For the DyScHfOx materials, the elec-tron mobility was improved with respect to devices with HfO2 as a gate dielectric.
The Study of Hafnium Silicate by NO Gas Annealing Treatment
Authors: Suh Dong Chan , Lee Dongwon , Chung Kwon Bum , Cho Mann-Ho , Ko Dae-Hong
Published: April 2007

The physical and electrical properties of nitrided Hf-silicate films, incorporated by NO gas annealing, were investigated by XPS, NEXAFS, TEM and C-V measurement. We confirmed the nitrogen incorporation during NO gas annealing treatment effectively enhances the thermal stability of Hf-silicate. The suppression of phase separation was observed in Hf-silicate films with high nitrogen contents. The negative shift of threshold voltage is caused by the incorporation of nitrogen in the hafnium silicate films.
Mechanisms of and Solutions to Moisture Absorption of Lanthanum Oxide as High k Gate Dielectric
Authors: Zhao Yi , Kita Koji , Kyuno Kentaro , Toriumi Akira
Published: April 2007

Moisture absorption is a big problem of lanthanum oxide (La2O3) as a high permittivity (k) gate dielectric which can degrade properties of La2O3 films. In this study, two possible mechanisms were proposed. One is oxygen vacancies related mechanism. And the other is the intrinsic reaction between La2O3 and H2O due to the small lattice energy of La2O3. To suppress these two mechanisms of moisture absorption, two solutions were proposed respectively. One is ultraviolet (UV) ozone post treatment to suppress the oxygen vacancies related mechanisms via healing oxygen vacancies in La2O3 films. Our experiment results show that UV ozone treatment can suppress the moisture absorption of La2O3 film. The other solution is to dope larger lattice energy oxide to suppress the intrinsic moisture absorption reaction. We tried the Y2O3 doping (LaYOx film). Experiment results indicate that LaYOx films show much stronger moisture resistance than La2O3 film.
Investigations of Work Function Shift in Lanthanum Silicate High-K Dielectric MIS Capacitors
Authors: Jur Jesse S. , Lichtenwalner Daniel , Kingon Angus
Published: April 2007

The effective work function for lanthanum silicate high-k dielectric MIS capacitors with TaN electrodes is reported in comparison to devices with thin lanthanum oxide capping layers on HfSiO and HfSiON dielectric layers. For the hafnium-based dielectrics, La2O3 capping results in a Vfb shift of up to -184 mV after a 1000 {degree sign}C, 5 sec anneal in nitrogen. LaSiOx films were formed by reacting La2O3 and a chemical oxide. Annealing of these films resulted in a negative Vfb shift of higher magnitude. Ozone or ammonia pretreatment of the chemical oxide prior to silicate formation reduces the magnitude of the shift, allowing for effective work function values between 3.75 and 4.25 eV after annealing. After a 700 {degree sign} C, 10 sec anneal, work function tuning of +/- 150 mV was a achieved while maintaining EOT (0.9 nm) and leakage (0.6 A/cm2 at Vfb + 1 V) for all samples with and without pretreatments.
Challenge for High-k/Metal Gate CMOSFETs in 32 nm Generation and Beyond
Authors: Takayanagi Mariko
Published: April 2007

High-k/metal gate stack is highly expected in 32 nm generation CMOSFETs. However, adjustment of threshold voltage, Vth, is still the major challenge for high-k/metal gate CMOSFETs at this point. This paper reviews the current situation and suggested solutions of Hf-related gate dielectrics/metal gate stacks mainly focused on work function control.
Surface Treatment and Functionalization Effects on Chemical Vapor Deposition and Atomic Layer Deposition Grown HfO2
Authors: Consiglio Steven , Mo Renee , Tai Tsong-Lin , Krishnan Siddarth , O'Meara David , Wajda Cory , Chudzik Michael
Published: April 2007

Ultrathin HfO2 films were deposited on various pre-treated Si surfaces by chemical vapor deposition using a hafnium-t-butoxide/O2 process and atomic layer deposition using a tetrakis(ethylmethylamino)hafnium/O3 process. The pre-treatments included aqueous based treatments for chemical oxide growth, HF-last, thermal nitridation, and dry oxidation with and without plasma nitridation. Growth rate differences of CVD grown films were observed, with HF-last based treatments exhibiting the highest barrier to nucleation. ALD grown films exhibited similar growth rates (~1Aå/cycle) and Hf coverage (~29% monolayer coverage/cycle) on all starting surfaces although differences in incubation cycles were observed. Starting surfaces containing nitrogen were shown to have improved nucleation and electron tunneling characteristics with increasing proximity of nitrogen to the starting surface. In device test structures utilizing ALD HfO2, interface nitridation was observed to reduce linear threshold voltage (Vtlin), inversion thickness (Tinv), high field (1 MV/cm) mobility and linear drain current (Idlin), while HF-last treatment was shown to have the highest mobility and Idlin at Tinv = 14.6 Aå.
Vacuum UV Spectroscopic Ellipsometry and X-Ray Reflectance Combined on the same Platform for the Characterization of High-k Gate Dielectrics
Authors: Defranoux Christophe , Bondaz Alexis , Kitzinger Laurent , Piel Jean Philippe
Published: April 2007

VUV spectroscopic ellipsometry down to 135nm is applied to the characterization of HfO2, Al2O3 and HfAlOx thin layers prepared by atomic layer chemical vapor deposition. It is shown that the absorption of the different kinds of layers becomes important in the VUV range. So, the optical contrast is enhanced and more precise structural information can be deduced and in particular the composition and crystalline character of the HfAlOx layers. Results are compared to those provided by other experimental techniques like x-ray reflection (XRR) and high resolution transmission electron microscopy (HRTEM).
Inverse-Vg Dependence of PBTI Lifetime of HfSiON Gate Dielectrics Measured by a High-Temperature Pulsed-IV Method
Authors: Ootsuka Fumio , Eimori Takahia , Nara Yasuo , Ohji Yuzuru
Published: April 2007

This paper describes a new NBTI/PBTI evaluation method which uses high-temperature pulsed IV. The benefit of this method is that because the bulk charge is detrapped during the interval before each measurement sequence, only the interfacial component can be extracted. PBTI lifetime of HfSiON, when measured by pulsed IV, is found to be on the line of log(t) vs 1/Vg, contrary to NBTI lifetime which is defined by log(t) vs Vg. Moreover, it is found that temperature dependence of PBTI is smaller than that of NBTI. These findings lead to the conclusion that electric field, rather than thermodynamic energy, affects the reaction at/near Si interface under PBTI stress. PBTI lifetime of TaSiN/HfSiON becomes larger than NBTI lifetime of TiN/HfSiON because of the different Vg dependence.
Structural and Electrical Properties of Er2O3 Thin Films Deposited by RF Sputtering for Gate Dielectric Applications
Authors: Deepak G C. , Bhat Navakanta , Shivashankar S A.
Published: April 2007

We report the structural and electrical properties of Erbium Oxide (Er2O3) thin films grown on p-Si (100) by RF sputtering. The structural and electrical of the films properties are correlated with the processing conditions. The structural characterization reveals that the films annealed at 900ºC, has large grain size as compared to the as-grown ones. A dielectric constant in the range 6-8 and an equivalent oxide thickness (EOT) of 4-5nm is observed. Annealing has reduced the hysteresis in the bi-directional capacitance-voltage characteristics by ~75%. Fixed oxide charges and interface charges, both of the order of 1012/cm2 is observed.
Excellent Electrical Characteristics of Praseodymium Oxide Dielectrics on Si Substrate by Reactive RF Sputtering
Authors: Pan Tung-Ming , Hsieh Chun-I , Tsai Feng-Ji , Wu Tin-Wei
Published: April 2007

Praseodymium oxide film was grown on Si substrate by reactive RF-sputtering from a Pr target for TaN metal gate. We found that Pr2O3 gate dielectric with TaN metal gate annealed at 700 o C exhibits a higher capacitance value and lower flatband voltage in C-V curves, and shows the leakage value of ~5x10-7 A/cm2 at a bias of 2 V. This Pr2O3 gate dielectric appears to be very promising for future ultra-large scale integration devices.
Fabrication of CeO2 Dielectric Films by Chemical Vapor Deposition with a Liquid Metal Organic Source
Authors: Ishibashi Keiji , Setsu Suzuki , Keiichi Nakamura , Kazunari Tagui , Masatsugu Ogawa , Kiyotaka Saito , Yasuhiro Yamamoto
Published: April 2007

Cerium dioxide films were deposited by chemical vapor deposition using tetrakis (3-methyl-3-pentoxy) cerium. In the present CVD process, Arrhenius plots indicated the existence of two activation energies of 0.85 eV and 0.29 eV. For the samples deposited under the condition of the lower activation energy of 0.29 eV, electrical properties were improved after annealing at 500 {degree sign}C in Ar, O2, and O-radical ambient. A hysteresis of 2.0 V and a flat band voltage shift of 3.0 V for the as-deposited film decreased to 0.15 V and almost 0 V after annealing, respectively. The leakage current decreased by 4 orders of magnitude after annealing in an oxidizing ambient, and even more improved value of the order of 10-7 A/cm2 was obtained after annealing in the O-radical ambient. For the samples deposited under the condition of the higher activation energy of 0.85 eV, however, electrical properties were not improved even after annealing.
On the Verification of EEDFs in Plasmas with Silane using Optical Emission Spectroscopy
Authors: Boogaard Arjen , Kovalgin Alexey , Brunets Ihor , Aarnink A. A. I. , Holleman Jisk , Wolters R. A. M. , Schmitz Jurriaan
Published: April 2007

We measured the electron density and electron energy distribution function (EEDF) of plasmas in our reactor which is intended for silicon oxide and nitride deposition. Langmuir- probe measurements showed that the EEDF of Ar plasma could largely be described by the Maxwell-Boltzmann (MB) distribution function, but it also contained a fraction (~0.5 %) of fast electrons in the energy range between 20 and 40 eV, strongly deviating from the MB distribution. We also measured relative mean electron temperatures (kTe) by optical emission spectroscopy (OES) which were calibrated by the absolute Langmuir-probe measurements. The kTe as measured by OES in Ar plasma decreased from 1.7 eV at 1.1 Pa to 1.4 eV at 12 Pa, while Langmuir-probe measurements showed a decrease from 1.7 eV to 0.8 eV. This difference is caused by the OES method, which is especially sensitive to the fraction of fast electrons in the plasma. OES can be used instead of Langmuir-probe measurements when depositing plasmas are used. Combining both methods, we demonstrated that EEDFs as measured by the Langmuir probe in Ar-N2, and Ar-N2O plasmas, resemble EEDFs in plasmas with small additions of silane, provided that (a) precursor fractions in plasma are small (SiH4 {less than or equal to} 0.8 % and N2O {less than or equal to} 15 %), and (b) total pressure does not exceed 3.6 Pa (27 mTorr). As such, the measured EEDF without silane can be used as input for chemical modeling and optimization of deposition processes in plasmas containing silane.
Full Range Work Function Tuning of MOSFETs using Interfacial Yttrium Layer in fully Germanided Ni Gate
Authors: Yu Hong Peng , Pey Kin Leong , Choi Wee Kiong , Antoniadis Dimitri A. , Fitzgerald Gene A. , Dawood Mohammed Khalid , Ow Kai Qun , Chi Dong Zhi
Published: April 2007

In this work, the tuning of the nickel fully germanided metal gate workfunction via a Y/Ge/Ni gate stack structure was demonstrated. By varying the yttrium interlayer thickness from 0 to 9.6nm, a full range of workfunction tuning from 5.11eV to 3.8eV can be achieved. We showed that the chemical potential of the material adjacent to the gate electrode/gate insulator plays an important role in the determination of the workfunction. The gate stack is thermally stable up to 500 oC annealing.
Low-Temperature Nickel Silicide Formation on SiO2 Films with a Cl Plasma Containing NiCl
Authors: Hirose Fumihiko , Fujiwara Naoto , Ohshima Shigetoshi , Sakamoto Hitoshi
Published: April 2007

Nickelsilicide-metalgate MOS structures have been successfully fabricated at a low temperature of 280åC by treating poly Si films stacked SiO2/Si substrates with a Cl plasma containing NiCl. In this process, NiCl in the Cl plasma is adsorbed to the poly Si surface and Ni atoms from NiCl are diffused into the poly Si films while Cl from NiCl binds with Si to desorb as SiCl. By changing the NiCl flux and process time, Ni content in the poly Si films can be controlled in the range from 0 to 80%. The present technique is available to fabricate metal gate MOS devices with various Ni contents at near room temperatures.
Recent Advances in Search for Suitable High-k/Metal Gate Solutions to Replace SiON/Poly-Silicon Gate Stacks in CMOS Devices for 45nm and Beyond Technologies
Authors: Linder Barry , Paruchuri Vamsi , Narayanan Vijay , Cartier Eduard , Bojarczuk Nestor , Guha Supratik , Brown Stephen , Wang Y
Published: April 2007

The criterion for a suitable high-K dielectric/metal gate stack for replacing SiON/Poly-Si stacks in conventional CMOS devices are i) Equivalent oxide thickness (EOT) of {less than or equal to} 1.1 nm, ii) Electron and hole mobilities that are comparable to conventional stacks, and iii) Near Band-Edge (BE) threshold voltages for both nFET and pFET devices. Aggressive scaling and competitive mobilities have been demonstrated using HfO2/metal gate stacks [1] through optimization of interfacial layer composition, choice of suitable metal electrodes and deposition processes, and high thermal budgets that are compatible with conventional FET fabrication. A suitable NFET BE solution compatible with gate first process flow achieved by inserting capping layers containing gp. IIA (e.g., Mg) & gp. IIIB (e.g., La) elements into proven high mobility mid-gap HfO2/TiN gate stacks thereby moving the effective work function (EWF) to nFET BE [2,3]. On the pFET front, the challenge remains that elements with high bulk workfunction exhibit Vt instability as well as inherent scaling limitations after high temperature processing that is required in a gate first process flow.
A New Liquid Precursor for Pure Ruthenium Depositions
Authors: Gatineau Julien , Dussarrat Christian
Published: April 2007

High purity ruthenium films were deposited using a new metal organic precursor, dubbed CHORUS. This liquid precursor is very volatile and is delivered without the addition of solvents to the reaction system. CHORUS enables to deposit ruthenium films from temperature as low as 250{degree sign}C using hydrogen as a reducing co-reactant in Chemical Vapor Deposition (CVD) mode. This new process is characterized by the high purity of the obtained ruthenium films, the non-oxidation of the sub-layer during the process, the good adherence to many kinds of substrates and the absence of incubation time.
Gate Quality Al2O3 by Molecular-Atomic-Deposition (MAD) and its Potential Applications in III-V Semiconductor CMOS Technology
Authors: Cui Sharon , Li Ning , Zheng Jun Fei , Shim Sunil , Ma T.P.
Published: April 2007

We report a simple technique for making high quality Al2O3, which is compatible to standard CMOS processes, and can be readily applied to III-V substrates. Our preliminary study indicates that such Al2O3 deposited on III-V semiconductors, without any additional surface treatment, gives rise to MOS CV characteristics comparable to their state-of-the-art counterparts that have gone through far more complicated processes. Our data also suggest that the recent advance in making functional III-V MOSFETs may be attributed primarily to the right choice of the gate dielectric material (i.e. Al2O3) and secondarily to the availability of suitable process techniques to produce high quality Al2O3.
The Effect of Interfacial Layer of High-K Dielectrics on GaAs Substrate
Authors: Tong Yi , Dalapati Goutam K. , Oh Hoon-Jung , Cho Byung Jin
Published: April 2007

We have studied the interfacial layer formation for atomic layer deposited Al2O3, HfO2, and HfAlO and physical vapor deposited HfO2 and Gd2O3/HfO2 gate stack on GaAs substrates by electrical and physical analysis. It is found that the HfAlO gate dielectric on p-GaAs exhibits excellent electrical properties compared with Al2O3 and HfO2. The HfAlO gate dielectric has low frequency dispersion (~2%), which are attributed to the reduction of interfacial oxides (GaAsO) at the interface. On the other hand, the presence of thin layer of Gd2O3 between HfO2 and GaAs is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current
Structure and Stability of Small Self-interstitial Clusters in Si: Prediction by First Principles-based Monte Carlo Simulations
Authors: Lee Sangheon , Hwang Gyeong S.
Published: April 2007

We present an efficient computational method for determining the ground-state configurations of self-interstitial clusters in Si, based on a combination of continuous random network model, Metropolis Monte Carlo sampling, and Keating-like valence bond model. Using the new approach, we have determined the structure and stability of small interstitial clusters (In, 3 < n < 12). The results are in good agreement with first principles results.
Structure and Diffusion of Phosphorus in Monohydride Si(001)-2×1-H
Authors: Kweon Kyoungeun , Harrison Scott , Hwang Gyeong S.
Published: April 2007

Using density functional calculations, we have investigated the structure and diffusion of phosphorous (P) in various charge states near the monohydride Si(001)-2×1-H surface. Surface P is found to be far more energetically favorable than bulk P, due primarily to the stronger bonding and smaller strain associated with the flexible surface. The predicted energy gains range from 1.5 to 2.3 eV, depending on the charge state and location of P. Our calculation results also show that with a moderate barrier bulk P will undergo out-diffusion to the surface, and surface P will migrate along a dimer row.
Junction Architectures for Planar Devices
Authors: Pawlak Bartlomiej J. , Duffy Ray , Hoffman Thomas , Severi Simone , Felch Susan , Eyben Pierre , Van Daele Benny , Vandervorst Wilfried , Lander Robert J.
Published: April 2007

Planar devices have been used for manufacturing integrated circuits for many decades already. Further device shrinkage and performance improvement by conventional size scaling are reaching their limits because of increasing difficulty to control short channel effects (SCE). In this paper, various approaches for source and drain doping in planar transistors are presented and discussed. The conventional approach based on implant and dopant activation anneal is analyzed versus other technologies. Especially many new developments in thermal treatment of the wafer in order to activate dopants and control their diffusion are presented.
Defect Engineering for Ultrashallow Junctions using Surfaces
Authors: Seebauer Edmund G. , Yeong Sai Hooi , Srinivasan M P , Kwok Charlotte , Vaidyanathan Ramakrishnan , Colombeau Benjamin , Chan L.
Published: April 2007

The behavior of point defects within silicon can be changed significantly by controlling the chemical state at the surface. In ultrashallow junction applications for integrated circuits, such effects can be exploited to reduce transient enhanced diffusion and increase dopant activation. The present work demonstrates such effects experimentally for arsenic and boron.
Relaxation-Induced Excess Leakage Current in Recessed Si1-xGex Source/Drain Junctions
Authors: Gonzalez Mireia B. , Chowdhury Mohammad Kamruzzaman , Bhouri Nada , Verheyen Peter , Leys Frederik , Richard Olivier , Loo Roger , Claeys Cor , Simoen Eddy , Machkaoutsan Vladimir , Tomasini Pierre , Thomas Shawn , Lu Jiong Ping , Weijtmans J.W , Wise R.
Published: April 2007

This paper presents an investigation of the effect of the relaxation on the electrical performance of recessed Si1-xGex source/drain junctions. It is shown, that the peripheral leakage current density scales exponentially with the total epilayer thickness, which allows the estimation of the characteristic length in good agreement with previously published values. In addition, the area leakage current density shows for relaxed Si0.7Ge0.3 recessed S/D junctions an exponential increase with the position of the epi interface with respect to the junction. For strained Si0.8Ge0.2 recessed S/D junctions, an unusual dependence of the area leakage current density on the etch depth is revealed. At the same time, for 48 nm etch depth, the leakage current components are not monotonically increasing with the Ge content. This could point to a size effect of the active areas, affecting the strain relaxation in the SiGe layers and the tensile strain in the underlying silicon substrate.
Growth Kinetics and Boron-Doping of Very High Ge Content Si1-xGex for Sources and Drains Engineering
Authors: Hartmann Jean-Michel , Gonzatti Frédéric , Barnes Jean-Paul , Fillot Frederic , Billon Thierry
Published: April 2007

We have studied the in-situ boron-doping of high Ge content Si1- xGex layers (x = 0.3, 0.4 and 0.5). Those layers have been grown at low pressure (20 Torr) and low temperature (600{degree sign}C to 650{degree sign}C) with a heavily chlorinated chemistry (in order to be selective versus SiO2 (isolation) and Si3N4 (sidewall spacers)). We have quantified the impact of the diborane flow on the SiGe layer crystalline quality, its resistivity, the SiGe:B growth rate and the apparent Ge concentration. We have also probed the in-situ boron and phosphorus doping of Si @ 750 {degree sign} C, 20 Torr with a chlorinated chemistry. All the know-how developed will be most handy for the formation of in-situ doped recessed or raised sources and drains.
Chlorine Etching for In-Situ Low-Temperature Silicon Surface Cleaning for Epitaxy Applications
Authors: Chung Keith H. , Sturm James C.
Published: April 2007

Chlorine in a nitrogen ambient is used to clean silicon surfaces of impurities by etching a thin layer from the surface prior to silicon epitaxial growth. Silicon etch rates of 1-10 nm/min are from 525oC to 575oC. The etching of a thin layer of silicon from the surface is also capable of removing phosphorus from the surface, which conventionally is difficult to remove. Smooth surfaces and high epitaxial quality after chlorine etching are also demonstrated.
Selective Si:C Epitaxy in Recessed Areas and Characterization of the Material Properties
Authors: Kim Yihwan , Ye Zhiyuan , Lam Andrew , Zojaji Ali , Cho Yonah , Kuppurao Satheesh
Published: April 2007

Si:C epitaxy was investigated to increase the substitutional carbon concentration, to achieve selectivity, and to understand growth characteristics on different Si crystallographic planes. A defective microstructure was observed next to the recess sidewalls. It was found that Si:C epitaxial growth on (110) crystallographic plane is heavily defective while the same epitaxy on (100) plane shows defect- free microstructure. By process optimization and using the appropriate chemistries for deposition and etch steps, we have developed a selective Si:C epitaxy process which result in a defect-free epitaxial layer that fills a 60 nm deep recessed area with 1.5 % substitutional [C] with 100 % substitutionality, and 100 % selectivity on dielectrics. Also, thermal stability of the substitutional [C] in Si:C epitaxy was tested with spike annealing at 1050 oC. No loss of substitutional [C] was observed after the spike annealing from a Si:C film with 100 % carbon substitutionality.
Defect Free Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices
Authors: Bauer Matthias , Zhang Yangting , Weeks Doran , Machkaoutsan Vladimir , Thomas Shawn
Published: April 2007

Embedded Si1-y-zCyPz films selectively grown into recessed source drain areas of NFET devices has been shown to produce a tensile strained Silicon channel, which in turn enhances electron mobility and transistor performance [1]. In order to obtain and maintain high substitutional carbon levels during deposition/processing low growth temperatures and high growth rates (GR) have to be employed. Carbon substitutionality was demonstrated to be almost complete for Si0.97C0.02P0.01. Excellent crystalline quality was demonstrated on bare wafers by XRD. The absence of crystalline defects and perfect selectivity were confirmed by TEM and SEM on patterned 200 and 300 mm wafers.
Dopant Segregated Pt and Ni Germanosilicide Schottky S/D p-MOSFETs with Strained Si-SiGe Channel
Authors: Zang Hui , Chua Chun Kiat , Loh Wei Yip , Cho Byung Jin
Published: April 2007

Dopant segregated Pt and Ni germanosilicide (PtSiGe and NiSiGe) Schottky source/drain (S/D) transistors were demonstrated on Si1-xGex substrates. The Schottky barrier height of Pt-Si0.7Ge0.3 was decreased by 0.2 eV compared to Pt- Si due to the smaller band-gap of SiGe and the dopant segregation effect. Schottky p-MOSFETs with Pt germanosilicided S/D junctions and strained Si/SiGe channels have also been demonstrated with 65 % higher drive current and lower leakage current compared with their Ni counterparts.
Nickel Silicide and Nickel Germanosilicide Processing in a Near-Isothermal Cavity: Sheet Resistance Curves for Blanket Ni/Si and Ni/SiGe Substrates and Electrical Data for CMOS Devices
Authors: Malik Igor J. , Ouaknine Michel , Fukada Takashi , Ueda Takeshi , Yoo Woo Sik , Press Patrick , Binder Robert
Published: April 2007

NiSi has become the preferred material in CMOS technology for source and drain contacts and is being considered as a metal gate material as well. With strain engineering demanding different types of strain for NMOS and PMOS transistors, Ni metal reacts with substrates that have a wide variety of properties (i.e. chemical composition, doping level, different crystalline phases). All of the relevant material combinations need to be taken into account when designing and optimizing an IC manufacturing process. The first part of this study was performed on 300 mm diameter blanket wafers and focuses on Ni metal reactions with lightly doped single-crystal Si and Si0.8Ge0.2. The former is typically used for sources and drains for NMOS transistors (need tensile stress in the channel for electron mobility enhancement), the latter for PMOS transistors (need compressive stress in the channel for hole mobility enhancement). The phase transformation curves for Ni/Si and Ni/Si0.8Ge0.2 are used for identifying the IC process window. In the second part of this study, we used 300 mm diameter device wafers (K8 microprocessor, 65 nm design rule) and targeted four distinct annealing conditions that were chosen based on the blanket wafer experiments.
An Original Selective Etch of Pt vs. PtSi using a Low Temperature Germanidation Process
Authors: Breil N. , Halimaoui A. , Dubois E. , Larrieu G. , Laszcz A. , Ratajczak J. , Rolland Guy , Pouydebasque A. , Skotnicki T.
Published: April 2007

A novel route to selectively etch Pt against PtSi is presented here. The suggested process is based on the transformation of Pt into PtxGey without altering PtSi. This paper reports a detailed investigation on the impact of a Ge overlayer on the integrity of Pt and PtSi. A Ge/Pt/SiO2/Si stack was annealed at different temperatures to simulate PtGe and Pt2Ge3 phase formation and to demonstrate their solubility in H2O2. Starting from a Ge/PtSi/Si stack annealed at temperatures as high as 600C, morphological and electrical characterizations allowed us to check that a Ge overlayer has a negligible impact on both the sheet resistance and the morphology of the active PtSi contact. As a final demonstration, the proposed etching procedure was applied to the integration of PtSi Schottky S/D in a 65nm CMOS technology.