Finding pinholes in carrier selective polycrystalline Si / crystalline Si contacts: like a needle in a haystack
Authors: Tetzlaff Dominic , Krügener Jan , Larionova Yevgeniya , Reiter Sina , Turcu Mircea , Folchert Nils , Peibst Robby , Höhne Uwe , Kähler Jan‐Dirk , Wietler Tobias 
Published: December 2016

Reducing surface recombination is a key factor in the race for high efficient silicon‐based solar cells. One solution is the use of carrier selective contacts, which have been investigated extensively by several groups in the last years [1]‐[5]. Even though polycrystalline (poly‐)Si/SiO
x
/crystalline (c‐)Si junctions were subject of research decades ago for use in bipolar transistors [6]‐[7] there are still different point of views about the physical principles of current transport in these junctions [8],[2]. Besides tunneling, current transport through pinholes is discussed [2]. It was already shown that high fractions of oxide disruptions lead to inferior electrical properties [5]. However, as stated in the model [2], only pinhole densities as low as 8 × 10
5
to 3 × 10
9
cm
‐
² are needed to describe the current flow / the junction resistance correctly.

Analyzing such hole densities in poly‐Si/SiO
x
/c‐Si junctions is very difficult. If we assume, that the existence of holes leads to an increased diffusion of dopants from the poly‐Si into the c‐Si we can indirectly prove the existence by measuring the local dopant concentration. However, methods like electrochemical capacitance‐voltage profiling or secondary ion mass spectrometry show the averaged distribution of dopants in a larger area and can only be used to compare different samples qualitatively. Conductive AFM is possible in general but it is not suitable for our samples due to the high transverse conductivity of the highly doped poly‐Si of about 150 nm thickness. We have to remove or at least drastically reduce the thickness of the poly‐Si, but therefore an etch process with a high selectivity ratio to SiO
2
with a thickness well below 2 nm is needed. Even when all these issues are solved, we don't get detailed information about hole diameter (expected to be around 5 nm [2]) and structure of the oxide around these holes. These questions can be answered by TEM, but the probability of finding holes with densities that low is very small. However, proving the existence of holes in the oxide by TEM for samples with good electrical results would be the first step of proving that current through poly‐Si/SiO
x
/c‐Si junctions is not only related to tunneling.

In this paper we investigate the influence of annealing temperature on the structural properties of
in situ
boron doped p+‐poly‐Si/SiO
x
/c‐Si interfaces after annealing at temperatures between 800 °C and 1050 °C. We analyze the evolution of holes for 1.7 nm thin wet‐chemically grown SiO
x
in comparison to thermally grown oxide using high resolution TEM and compare our findings to electrical results.

We confirm that a massive break‐up of the oxide leads to poor electrical properties. Additionally, we prove the existence of pinholes in a sample with wet‐chemically grown oxide annealed at 800 °C showing good electrical results with an emitter current density

J
0e

as low as 41 fA/cm
2
. These results indicate a certain area fraction of pinholes is not in contradiction with good passivation properties of poly‐Si/SiO
x
/c‐Si junctions. The flow of charge carriers through these pinholes possibly poses an important current transport mechanism besides the superposed tunneling in the region in which the interfacial oxide is still intact.