bluuebunny/crossref_metadata_2025 huggingface dataset:
dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits
Authors: Pendyala Sweta , Albert Dave , Hawkins Katherine , Tenney Michael
Published: December 2020

Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.
32 nm CMOS SOI Test Site for Emission Tool Evaluation
Authors: Weger Alan J. , Stellari Franco , Kim Seongwon , Ainspan Herschel A. , Kwark Young , Baks Christian W. , Maliuk Dzmitry , Song Peilin
Published: December 2020

We describe a test chip designed and fabricated in 32nm CMOS SOI. The test chip was developed to assist in the characterization and testing of hot electron emission based test systems for both existing and forthcoming technology nodes, and contains circuit structures of increasing density and complexity. We also describe some unique circuit functions that may be of use in other applications
Realizing Dynamic Thermal Laser Stimulation by Lock-in IR-OBIRCH Assisted with a Current Detection Probe Head
Authors: Wu Chunlei , Yao Suying
Published: December 2020

Lock-in IR-OBIRCH analysis, as a kind of static thermal laser stimulation (S-TLS) technique, is very effective to isolate a fault for the parametric failure cases. However, its capability is limited to localize a defect when the IC is operated under a defined operating condition. Whereas the dynamic thermal laser stimulation (D-TLS) technique is good at locating a fault while the IC is operated under some functions to activate the failure. In this paper, a novel method is presented to realize DTLS just by Lock-in IR-OBIRCH assisted with a Current Detection Probe Head. Two cases are studied to demonstrate the effectiveness of this method.
Silicon Fringe Sample Metrology—A Thickness Measurement Technique
Authors: Kimball Mark
Published: December 2020

Silicon’s index of refraction has a strong temperature coefficient. This temperature dependence can be used to aid sample thinning procedures used for backside analysis, by providing a noncontact method of measuring absolute sample thickness. It also can remove slope ambiguity while counting interference fringes (used to determine the direction and magnitude of thickness variations across a sample).
A Sample Preparation Methodology for Effective Failure Analysis of Trench Power MOSFET
Authors: Li Yan , Loh S.K. , Chen C.Q. , Ang G.B. , Quah A.C.T. , Neo S.P. , Oh C.K. , Yao Y.J. , Zhao S.P.
Published: December 2020

This paper describes a sample preparation methodology for Trench Power MOSFET that significantly improved our failure analysis success rate for trench bottom defect. With precise fault localization and subsequent a unique physical failure analysis using parallel polishing method on Trench Power MOSFET, This enabled defect detection from the trench top to the trench bottom.
Evolution of Wafer Level Tester-Based Diagnostic System—More Than Just a Dynamic Electrical Fault Isolation Tool
Authors: Goh S.H. , You G.F. , Yeoh B.L. , Chan Y.H. , Yap C.P. , Lam Jeffrey , Chua C.M.
Published: December 2020

Wafer level tester-based fault isolation (FI) tool exists back in 2008 but is not widely adopted by industry. This is expected because such tool is commonly known for its primary role in dynamic electrical FI. Since packages are readily available, there is little motivation in using wafers. This paper provides a different perspective to consider such tool as part of a wafer level debug solution to enhance current failure pre diagnostic and diagnosis capabilities, to meet requirements for fast and effective yield ramp. Test cases are presented to support this perspective and a roadmap that guides next generation wafer level FI tool is also proposed at the end of the paper.
Resolution Improvement through Sparse Image Reconstruction Techniques for Dark Field Subsurface Microscopy of Integrated Circuits
Authors: Cilingiroglu T. Berkin , Karl W. Clem , Konrad Janusz , Grogan Michael D.W. , Yurt Abdulkadir , Tuysuzoglu Ahmet , Goldberg Bennett B. , Unlu M. Selim
Published: December 2020

Sparse image reconstruction techniques have been used to recover high frequency information lost during the acquisition process in different imaging domains, such as ultrasound, synthetic aperture radar, optical microscopy, and astronomical and microscopic imaging. In this work, a signal processing framework is proposed to estimate the Point Spread Function (PSF) of the dark-field subsurface microscopy system from observation data. This PSF is incorporated into an image reconstruction framework, which can be formulated with two different image reconstruction techniques, regularized image reconstruction and dictionary-based image reconstruction. It is observed that both techniques provide at least 12% resolution improvement; lines with 224 nm spacing were localized after resolution improvement while lines with 252 nm spacing are at the limit of localization in experimental data. However, dictionary-based image reconstruction provides higher edge resolution and maintains the homogeneity of the intensity within the structures.
Analysis of InGaAs Epi Defects by Conductive AFM
Authors: Cordes Aaron , Dyer Tom , Hand Sean
Published: December 2020

As the semiconductor industry continues to push the boundaries of Moore’s law, new device structures and materials are being introduced to increase device speed and lower power consumption. This work uses InGaAs as representative samples to investigate the capability of conductive AFM to image and characterize electrical defects in thin films. As the AFM is a non-destructive technique, the defects may be re-located by complimentary reference metrology techniques. Once the capability of defect detection and characterization of AFM is demonstrated with respect to the reference metrology techniques, conductive AFM is used to characterize the defect density of a set of InGaAs samples grown under varying process stressed epitaxial conditions.
Failure Analysis Methodology on Systematic Missing Cu in RAM Due to Cu CMP
Authors: Ang Ghim Boon , Chen Changqing , Ng Hui Peng , Quah Alfred , Teo Angela , Yip Kim Hong , Neo Soh Ping , Lam Jeffrey , Mai Zhihong
Published: December 2020

This paper places a strong emphasis on the importance of applying Systematic Problem Solving approach and use of appropriate FA methods and tools to understand the “real” failure root cause. A case of wafer center cluster RAM fail due to systematic missing Cu was studied. It was through a strong “inquisitive” mindset coupled with deep dive problem solving that lead to uncover the actual root cause of large Cu voids. The missing Cu was due to large Cu void induced by galvanic effects from the faster removal rate during Cu CMP and subsequently resulted in missing Cu. This highlights that the FA analyst’s mission is not simply to find defects but also play a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically/ physically) to Fab.
Ex-Situ Lift Out of Plasma Focused Ion Beam Prepared Site Specific Specimens
Authors: Chan Lisa , Hiller Jon M. , Giannuzzi Lucille A.
Published: December 2020

Ex situ lift out (EXLO) was historically the first lift out technique to be developed for site specific removal and manipulation of focused ion beam (FIB)-prepared specimens to a suitable carrier. In this paper, fast plasma FIB (PFIB) preparation of large scanning/transmission electron microscope specimens is combined with fast conventional EXLO and EXpressLO "pick and place" solutions. The combination of large material removal rates with PFIB and EXLO allows for efficiency and high throughput of FIB lift out specimens.
Applications of AFP Nanoprobing for Localization of Implant Related Issues
Authors: Dayanand N. , Yip K.H. , Quah A.C.T. , Neo S.P. , Ng H.P. , Ang G.B. , Lam J.C. , Mai Z.H.
Published: December 2020

The case study in this paper describes how collaboration between customer design and test teams and a thorough FAB investigation triggered by a detailed electrical analysis using the Atomic Force Nanoprober (AFP) resulted in the effective resolution of a challenging implant related issue on LDMOS structure that caused yield loss. The quick success in this case has led to a shorter yield ramp cycle on this new product for mass production.
Optimization of TEM Sample Preparation to Reduce the Overlapping of TEM Images
Authors: Duan Shuqing , Chen Summer , Yu Paul , Li Ming , Zhang Mark , Chien Kary
Published: December 2020

This paper reports optimized Transmission Electron Microscopy (TEM) sample preparation methods with Focus Ion Beam (FIB), which are used to reduce or avoid the overlapping of TEM images. Several examples of optimized cross-section sample preparation on 38nm and 45nm pitch are provided with general and novel FIB methods. And its application to plan view TEM sample preparation is also shown. The results establish that the proposed method is useful to reduce or remove pattern overlapping effects in dense structures and can produce higher quality TEM images than can be obtained using conventional top-down FIB-based TEM preparation methods.
Failure Analysis of Embedded Non-Volatile Memory with Nano- and Micro-Probing Techniques
Authors: Wang Xiang-Dong , Yazzie Arnold , Buchert John , Will Laurel , Wang Ping , Guisinger Scott
Published: December 2020

Embedded non-volatile memory (NVM) technologies are used in almost all areas of semiconductor chip applications, as it becomes increasingly vital to retain information when the electronics power is off. Nano-probing techniques, such as atomic force probe (AFP), allow us to access individual devices at contact or via levels and characterize the details as much as possible before a decision can be made for physical analysis. This paper reports the application of AFP to characterize each individual bit at contact level or individual column at via1 level. It presents two cases to identify the failures encountered in fabricated embedded NVM: column-column leakage and single bit erase failure. The first case shows that silicide residual could cause column to column leakage by creating electrical path between active areas of adjacent columns, while the second case shows that single bit failures due to low erase current can be recovered with repeated program/erase cycle.
Observation of Polarization and Two-Dimensional Electron Gas in AlGaN/GaN Heterostructure Using Scanning Nonlinear Dielectric Microscopy
Authors: Hirose K. , Chinone N. , Cho Y.
Published: December 2020

We measured AlGaN/GaN heterostructure using scanning nonlinear dielectric microscopy (SNDM) [1], which can measure both carrier and polarization profile in AlGaN/GaN heterostructure. As a result, GaN spontaneous polarization and AlGaN polarization which is sum of spontaneous polarization and piezoelectric polarization were clearly distinguished. Two dimensional electron gas (2DEG) was observed at the AlGaN/GaN interface. This results show that SNDM is useful method for evaluation of 2DEG profile and polarization profile in AlGaN/GaN heterostructure.
Corrosion Mechanisms of Cu Bond Wires on AlSi Pads
Authors: Qin Wentao , Anderson Harold , Anderson Tom , Chang George , Barrientos Denise
Published: December 2020

Cu wires were bonded to AlSi (1%) pads, subsequently encapsulated and subjected to uHAST (un-biased Highly Accelerated Stress Test, 130 °C and 85% relative humidity). After the test, a pair of bonding interfaces associated with a failing contact resistance and a passing contact resistance were analyzed and compared, with transmission electron microscopy (TEM), electron diffraction, and energy-dispersive spectroscopy (EDS). The data suggested the corrosion rates were higher for the more Cu-rich Cu-Al intermetallics (IMC) in the failing sample. The corrosion was investigated with factors including electromotive force (EMF), self-passivation of Al, thickness and homogeneity of the Al-oxide on the IMC, ratio of the Cu-to-Al surface areas exposed to the electrolyte for an IMC taken into account. The preferential corrosion observed for the Cu-rich IMC is attributed to the high ratios of the surface areas of the cathode and anode that were exposed to the electrolyte, and the passivation oxide of Al with the lower homogeneity. The corrosion of the Cu-Al IMC is just a manifestation of the well-known phenomenon of dealloying. With the understanding of the corrosion mechanisms, prohibiting the formation of Cu-rich IMCs is expected be an approach to improve the corrosion resistance of the wire bonding.
Repeatable Method for Automated Decapsulation of Silver Alloy Wire Packages
Authors: Lefevre Matthew , Noraz Emmanuel , Veychard Damien
Published: December 2020

Over the past several years there has been a large industry wide effort to change over from gold bonding wires to copper in order to minimize production costs. In certain cases this is not possible due to the relatively high hardness values of Cu [1], which leads to reliability issues in the manufacturing process. Silver (Ag) wire has been proposed and successfully implemented in many instances where Cu wire was not practicable. Unfortunately, currently integrated decapsulation methods severely damaged or destroyed the silver wires and bonds, making it impossible to perform production controls and failure analysis. In this article we present a reliable and repeatable automated method to expose these die and wire bonds. By adding a dilute iodine solution to the nitric acid in an acid decapsulator, these packages can be fully opened without degrading the silver wires, allowing both mechanical and electrical testing on these devices.
Further Localization of the Minor Junction Leakage Fault by Nanoprobing
Authors: Wang H.S. , Lin C.C. , Sung T.Y. , Chang K.C. , Yang S.C. , Hung W.S. , Liou H.C.
Published: December 2020

Localizing a tiny fault causing abnormal leakage current in a large area P/N junction for a large MOS, diode or BJT structure by nano-probing was demonstrated. The localization was realized through probing the contacts on the junctions and comparing the reversed bias junction current for each contact which maintain the same polarity on the P/N junction. The tiny fault location which is causing the leakage in the large area P/N junction is indicated by the contact with the largest current due to the lowest sheet row resistance path to the fault as measured by nano-probing. Therefore, the success rate to identify the real physical fault by TEM and the ability to take the precise process action to correct the problem is greatly increased by this method. An artificial fault experiment induced by use of FIB as well as real case studies also verifies this method is valid and useful.
Failure Analysis Methodology on Systematic Polar Failing Pattern Due to Higher Solder Bump Resistance Issue in RF SOI Device
Authors: Ang Ghim Boon , Changqing Chen , Ng Hui Peng , Quah Alfred , Dayanand Nagalingam , Teo Angela , Teo Hanwei , Mai Zhihong , Lam Jeffrey
Published: December 2020

This paper placed a strong emphasis on the importance of applying Systematic Problem Solving approach, deep dive and use of right/appropriate FA approach/tools that are essentially critical to FA analysts to understand the “real” root cause. A case of low yield with polar failing pattern was seen and matched well with the Al Pad etch E chuck configuration. Customer also reported of passivation crack issue at the solder bumps. All these evidences suggested the root cause was related to wafer fabrication issue. However, it was through a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach that led to uncover the actual root cause. Although customer test condition was not able to be duplicated due to limited information available in foundry industry, a four point probing alternative method was engaged to overcome this limitation. Unlike typical case, the AlOx thickness was comparable for bad and good dies. Further in depth analysis subsequently revealed the higher O content in the AlOx for the bad dies that was the real culprit for the higher bump resistance. This paper highlights the job of FA analyst is not simply finding defect but also plays a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically / physically) to Fab. It would serve as a good reference to wafer Fab that encountered such issue.
Characterizing Organic Nanocontamination in Semiconductors by Resonance Enhanced AFM-IR
Authors: Roy Anirban , Dillon Eoghan , Hu Qichi , Anderson Jay , Kjoller Kevin , Shetty Roshan , Prater Craig
Published: December 2020

Continuous development in the semiconductor process technology has led to the fabrication of devices with nanometer scale feature resolution. Resonance enhanced atomic force microscopy infrared (AFM-IR) is a novel technique with potential to overcome some limitations of existing tools. This manuscript illustrates chemical characterization of the nanoscale skin and polyester contaminant on silicon wafer using resonance enhanced AFM-IR spectroscopy. Resonance enhanced AFM-IR offers superior sensitivity for nanoscale organic contaminants. To demonstrate this capability, AFM-IR spectra were obtained from contaminants on silicon wafers, and the spectra correlated with a high confidence to a standard transmission FTIR spectral database. In addition, a newly developed high speed spectral acquisition scheme, which augments the reliability of nanoscale defect characterization by reducing the overall data acquisition time and enabling users to perform repeated measurements for statistical analysis, is established.
Automated 3D STEM-EDS for Spatially Resolved Elemental Characterization of Semiconductors
Authors: McIlwrath Kevin , Furukawa Hiromitsu , Horii Noritaka , Nakano Kazutoshi
Published: December 2020

With semiconductor geometries approaching sub 10 nanometer gate levels in the not too distant future and with higher levels of integration, new ways of characterizing defects and examining the 3D distribution visually and elementally on the nanometer level are required to keep up with the demands of the modern FA lab. The purpose of this study is to demonstrate the workflow and show the results of an automated 3D STEM-EDX data acquisition & visualization system that can be utilized for the failure analysis of semiconductor devices.
The Removal of Thin Oxygen and Carbon Surface Films by H2/Ar Plasmas as Characterized by Low kV EDS
Authors: Tracy B. , Sharma U. , Casenave J. , Nylese T. , Rafaelsen J. , Carlino V. , Fahey M.
Published: December 2020

Improved Scanning Electron Microscope (SEM) vacuum conditions have been of considerable interest during the past decade, especially as low landing energies are employed to perform surface sensitive imaging [1][2][3]. To further improve instrument performance plasma cleaning can be applied. In general, the cleaning chemistry is a plasma formed from laboratory air (nitrogen+oxygen). TEM and SEM samples can be cleaned ex-situ with this plasma. Alternatively, other gas mixtures have been reported such as 75% Argon + 25% Oxygen [4]. In this study, we report on the use of 95% Argon + 5% Hydrogen mixture for the removal of carbon and oxygen containing films on Indium using low Energy Dispersive Spectroscopy (EDS). This gas mixture is not pyrophoric and is well suited for the laboratory environment.
Optimization of EeLADA for Circuit Logic Defect Localization Using Defect Simulation
Authors: Lee M. , Yeoh B.L. , Goh S.H. , You G.F. , Tan Alan , Hao Hu , Chan Y.H. , Zhao Lin , Gupta Varun , Ma H.H.W.T. , Neo S.P. , Ang G.B. , Ngow Y.T. , Lam Jeffrey , Tay C.C.
Published: December 2020

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.
Case Study of Physical Failure Analysis Method for Microcrack Detection in Laser Via of Printed Circuit Boards
Authors: Kim Hyunsoo , Woo Jaehyeong , Lim Dongju , Kim Youngje , Jeong Munmo
Published: December 2020

This paper describes the failure analysis methods used to characterize micro cracks that resulted in laser vias of printed circuit boards (PCBs) through case studies of destructive failure analysis. Defects such as cracks in laser vias of PCBs can cause open or low leakage failure mode of module due to improper cleaning during the PCB process, natural oxide films such as brown oxide, or physical forces by use. Therefore, it’s difficult to identify the causes of these phenomena unless proper analytical techniques are used. In this study, multiple analytical techniques are employed to characterize micro cracks in laser vias. The destructive analysis with cross section and ion milling process is used to detect and inspect an accurate micro crack phenomenon of laser via. The characterization analysis using TEM, EDX and SIMS equipment after separating laser vias from a PCB is used to analyze failure cause of micro crack in laser via. This paper will be concluded with a discussion about what physical analysis methods should be used to analyze the causes of micro cracks for laser vias of PCBs.
A Quantitative Method for Measuring Remaining Silicon Thickness during XeF2 FIB Trenching for Backside Circuit Operations
Authors: Salazar G.P. , Shul R.J. , Ball S.N. , Rye M.J. , Phillips B.S. , DiBattista M. , Silverman S.
Published: December 2020

Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.
Practicality of Single Microscope Failure Analysis for Fault Isolation, Analysis, and Advanced TEM Sample Preparation by the Integration EBAC and EDS on FIBSEM
Authors: Lindsay John , Sagar James , Holland James , Goulden Jenny
Published: December 2020

Device failure analysis typically requires multiple systems for fault identification, preparation and analysis. In this paper we discuss the practicalities and limits of using a single FIBSEM system for a complete failure analysis workflow. The theoretical requirements of using a nanomanipulator for both lamella lift out and electrical testing are discussed and the current capabilities of windowless X-rays detectors for chemical analysis demonstrated. When the required resolution for failure analysis exceed the limits of a FIBSEM and TEM is required, the combination of the nanomanipulator and X-ray detector for advanced lift out and thickness controlled thinning techniques are demonstrated to prepare exceptional quality lamellae.
Failure Analysis and Defect Inspection of Electronic Devices by High-Resolution Cathodoluminescence
Authors: Monachon C. , Zielinski M.S. , Gachet D. , Sonderegger S. , Muckenhirn S. , Berney J. , Poppitz D. , Graff A. , Breuer S. , Kirste L.
Published: December 2020

Quantitative cathodoluminescence (CL) microscopy is a new optical spectroscopy technique that measures electron beam-induced optical emission over large field of view with a spatial resolution close to that of a scanning electron microscope (SEM). Correlation of surface morphology (SE contrast) with spectrally resolved and highly material composition sensitive CL emission opens a new pathway in non-destructive failure and defect analysis at the nanometer scale. Here we present application of a modern CL microscope in defect and homogeneity metrology, as well as failure analysis in semiconducting electronic materials.
Investigation of Switching Mechanism in HfO2-Based Oxide Resistive Memories by In-Situ Transmission Electron Microscopy and Electron Energy Loss Spectroscopy
Authors: Dewolf T. , Cooper D. , Bernier N. , Delaye V. , Grenier A. , Grampeix H. , Charpin C. , Nardelli F. , Pauliac S. , Bernasconi S. , Jalaguier E. , Audoit G. , Schamm-Chardon S.
Published: December 2020

Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.
Automated End-Point Detection and Targeted Ar+ Milling of Advanced Integrated Circuit FIB TEM Specimens
Authors: Bonifacio C.S. , Nowakowski P. , Campin M.J. , Harbaugh J.T. , Boccabella M. , Fischione P.E.
Published: December 2020

The sub-nanometer resolution that transmission electron microscopy (TEM) provides is critical to the development and fabrication of advanced integrated circuits. TEM specimens are usually prepared using the focused ion beam, which can cause gallium-induced artifacts and amorphization. This work presents the use of a concentrated argon ion beam for reproducible TEM specimen preparation using automatic milling termination and targeted ion milling of device features; the result is high-quality and electron-transparent specimens of less than 30 nm. Such work is relevant for semiconductor product development and failure analysis.
High Resolution Localization Using Lock-in Based Electron Beam Methods
Authors: Rolf Felix , Hollerith Christian , Feuerbaum Christian
Published: December 2020

With decreasing transistor sizes accurate failure localization becomes more and more important in order to find the root cause of failures with high efficiency. Field returns are a special challenge, since there is usually only one sample for preparation. Hence, reliable high resolution localization is mandatory for a successful preparation. Optical beam induced resistance change (OBIRCH) is a powerful tool for localization but has resolution limitations due to the diameter of the optical beam. The tool can be further improved by the lock-in technique. In this paper we demonstrate that the lock-in technique can also be applied for electron beam localization methods like electron beam induced current (EBIC) / electron beam absorbed current (EBAC) and resistance change imaging (RCI) / electron beam induced resistance change (EBIRCH).
Use of 3D X-Ray Microscopy for BEOL and Advanced Packaging Failure Analysis
Authors: Schmidt Christian , Kelly Stephen T. , De Wolf Ingrid
Published: December 2020

With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-Ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, 2 different approaches of X-Ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with Nanoscale 3D X-Ray Microscopy for Chip-Package-Interaction and Back-end-of-line feature imaging is introduced.
Uncover Buried Hidden Defects through Fast Selective Chemical Etching and Mechanical Polish
Authors: Ng Hui Peng , Teo Angela , Ang Ghim Boon , Chen Chang Qing , Tam Yong Seng , Xu Naiyun , Nagalingam Dayanand , Mai Zhi Hong , Lam Jeffrey
Published: December 2020

This paper places a strong emphasis on the importance of applying the correct FA approach in physical sample preparation to identify hidden defects that can be easily removed during analysis. A combination of mechanical parallel polishing and chemical etching was used during the sample preparation after electrical fault isolation. Such a combination is both effective and efficient in identifying the single Via punch-through from a sea of Via in MIM structure as well as finding the thin layer of barrier bridging under the Al metal. It serves as a quick way to verify any suspect without time consuming FIB progressive cuts at the hotspot location which sometimes turns out to be an induced spot with a defect located at other site due to the circuitry connection. It would serve as a good reference to wafer fab that encountered such issues.
Case Study—Failure Analysis of a Printed Circuit Board Latent Failure and Resulting Implication of Weaknesses in Panel Coupons and Lot DPA
Authors: Tuite Tom
Published: December 2020

Multiple, independent, system level test failures that occurred around the same time were traced back to a short circuit on the same type of printed circuit board (PCB). The PCBs were removed from the application and sent to the authors' lab for analysis. This paper reviews the analysis techniques and results that led to the failure mechanism being identified. The discussion focuses on steps taken to exonerate the authors' lab and processes as possible sources of contamination. Additional investigation that leads to the conclusion that the issue is systemic is also covered. The paper then focuses on the containment effort as well as root cause identification at the manufacturers. It was concluded that the failure mechanism causing the short circuit in the failed PCB is due to ionic contamination trapped inside the PCB. The normal chemistry required to process the plated through holes contaminated the voids/fractures created by drilling process.
A Discussion of Dielectric Film Deformation by E-Beam Energy
Authors: Chen Yu-Xiu , Hsu Pei-Ning , Chung Yu-Min , Hsu Hsin-Cheng , Ku Huai-San , Yeh Chin-Chih , Lian Nan-Tzu , Yang Tahone , Chen Kuang-Chao , Lu Chih-Yuan
Published: December 2020

A recently developed technique known as Electron Beam Induced Resistance Change (EBIRCH) equipped with a scanning electron microscope (SEM) utilizes a constant electron beam (e-beam) voltage across or current through the defect of interest and amplifies its resistance variation. In this study, EBIRCH is applied for a 3D NAND structure device fault isolation but suffered from nearby dielectric film deformation. The characterization of such dielectric deformation and the possible mechanisms of e-beam induced damage are discussed. As well, a threshold condition to avoid from triggering the occurrence of dielectric damage is presented for shallow defect analysis in EBIRCH application.
Electron Beam Probing of Active Advanced FinFET Circuit with Fin Level Resolution
Authors: Tong T. , Ryu H.J. , Wang Y. , Chuang W.-H. , Huening J. , Joshi P. , Ma Z.
Published: December 2020

This paper shows for the first time chip level electron beam probing on fully functional 10nm and 14nm node FinFET chips with sub-fin level resolution using techniques developed in house. Three novel electron beam probing techniques were developed and used in the debug and fault isolation of advanced node semiconductor devices. These techniques were E-beam logic state imaging, electron-beam signal image mapping, and E-beam device perturbation. Two tools that can offer all three techniques were constructed and used in production. The techniques have been successfully applied to real case chip debug and fault isolation on advanced 10nm and 14nm FinFET on production tools developed in-house. Sub-fin level resolution was achieved for the first time.
Failure Analysis of Micro Defective Structure on a pnp Power Device
Authors: Krishnan Arul , Murugalogeswaran Permal
Published: December 2020

In this paper we introduce a physical analysis approach using focus ion beam (FIB) and scanning electron microscopy (SEM) to investigate a micro defective structure at active contact trench which caused a voltage breakdown of power device. In this case study, a lower probe current through FIB milling and a lower accelerating voltage in SEM imaging have been applied to identify the micro structure defect.
The Investigation of Fluorine Induced Novel Probe Marker Discoloration
Authors: Hsieh W.F. , Lin Henry , Chen Vincent , Ou Irene , Lou Y.S.
Published: December 2020

This paper describes the investigation of donut-shaped probe marker discolorations found on Al bondpads. Based on SEM/EDS, TEM/EELS, and Auger analysis, the corrosion product is a combination of aluminum, fluorine, and oxygen, implying that the discolorations are due to the presence of fluorine. Highly accelerated stress tests simulating one year of storage in air resulted in no new or worsening discolorations in the affected chips. In order to identify the exact cause of the fluorine-induced corrosion, the authors developed an automated inspection system that scans an entire wafer, recording and quantifying image contrast and brightness variations associated with discolorations. Dark field TEM images reveal thickness variations of up to 5 nm in the corrosion film, and EELS line scan data show the corresponding compositional distributions. The findings indicate that fluorine-containing gases used in upstream processes leave residues behind that are driven in to the Al bondpads by probe-tip forces and activated by the electric field generated during CP testing. The knowledge acquired has proven helpful in managing the problem.
Effective Method for Analyzing IGBT Leakage Failures Related to the Exposed Junction on the Die Sidewall
Authors: Dang Chi , Vo Thanh
Published: December 2020

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.
Finite-Element Modeling and Quantitative Measurement Using Scanning Microwave Microscopy to Characterize Dielectric Films
Authors: Rubin K. A. , Jolley W. , Yang Y.
Published: December 2020

Scanning Microwave Impedance Microscopy (sMIM) can be used to characterize dielectric thin films and to quantitatively discern film thickness differences. FEM modeling of the sMIM response provides understanding of how to connect the measured sMIM signals to the underlying properties of the dielectric film and its substrate. Modeling shows that sMIM can be used to characterize a range of dielectric film thicknesses spanning both low-k and medium-k dielectric constants. A model system consisting of SiO2 thin films of various thickness on silicon substrates is used to illustrate the technique experimentally.
GHz-SAM for Warped Samples using HiSA
Authors: D. Le C. Hollerith , Hoffrogge P. , Böckler M.
Published: December 2020

GHz-SAM using toneburst transducers is a method currently lacking the possibility to measure warped samples easily because large parts of such samples are out of focus due to the limited depth of focus of these types of transducers. This paper shows an approach to use the already established HiSA (High Speed Axis) method to overcome this disadvantage. Therefore warpage of the sample is measured by a white-light interferometer. The detected bow is parametrized and submitted in the control electronics of the HiSA. With this data the HiSA is enabled to keep the distance between sample and transducer precisely constant. This allows eliminating the influence of the warpage on the performance of this method and therefore highly increases the image quality.
Understanding Water Ingress in Scanning Acoustic Microscopy and a Method to Observe Defects that are Open to the Surface
Authors: Benak Adam , Devaney Roger
Published: December 2020

Scanning Acoustic Microscopy (SAM) is a very important tool in the evaluation of molded plastic electronic components. SAM is used to non-destructively determine the configuration and quality of components using ultrasonic sound waves and consequently is an important test step in the screening, Destructive Physical Analysis (DPA) or Failure Analysis (FA) of plastic components. SAM is performed in a water bath so if internal defects are open to the surface of the device they can fill with water and become invisible to SAM.
Automated Gas-Enhanced PFIB Surface Preparation Enabled Metrology and Statistical Analysis of 3D NAND Devices
Authors: Hakala Chris , Clarke James , Biedrzycki Mark , Price Kesley , Johnson Jamie , Mitchson Gavin
Published: December 2020

The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis, involving a critical etch step with aspect ratios of ~50:1. These high aspect ratio process steps present both fabrication and metrology challenges where the channel holes can bend, bow, and pinch off throughout the stack. Work presented herein demonstrates the capability of an automated workflow developed using the Thermo Scientific™ Helios™ G4 HXe DualBeam™ platform. The workflow iteratively exposes desired layers within the NAND stack, collects high resolution SEM images, and performs metrology to enable statistical analysis of trends as a function of depth within the stack. Results will be presented from 3 sites in an automatically delayered 72-layer 3D NAND die. Automated SEM metrology was performed every 10 layers, capturing more than 6000 devices. Over 19000 measurements were made on imaged devices yielding assessment of statistically significant trends in the planar cell area, eccentricity, and position of the bits as a function of depth.
Stress Analysis of Damage in Active Circuitry beneath Redistribution Layer (RDL) Bonding Pad and Improvements for Reliability
Authors: Shih Chih-Ching , Hsiao Wei-Hao , Chan Leo , Chang Hsiao-Tien , Kuo Li-Kuang , Lin Ding-Jhang , Chao Yen-Hai , Lu Chih-Yuan
Published: December 2020

Redistribution layer (RDL) bonding pad over active circuitry is utilized to re-route the original bond pad to other location for wire bonding using RDL. The damages in the active circuitry beneath the RDL bond pad induced by stress from wire bonding and package must be evaluated for reliability in the product development. The experimental approach and test structures are proposed in this paper. Functional fail was detected in electrical test after reliability tests on packaged IC. The dielectric cracking initiated by wire bonding that corresponds to the functional fail is identified by physical failure analysis and Transmission-Electron-Microscopy (TEM) at a specific location beneath the RDL bond pad. Finite element simulations are used to analyze the wire bonding stress distribution and circuit-under-pad design effect. The predicted maximum stress for the dielectric cracking matches to the location observed in the physical failure analysis. Based on the experiment and the simulation data, design rules for the circuit routing beneath the RDL bond pad have been successfully developed that all product reliability tests pass later with extend bonding power. The results lead to significant improvements in the robustness of circuit routing structure beneath the RDL bond pad for dielectric cracking without modifications of the existing processes for the product.
Novel X-ray Microscopic Chemical Imaging for Rapid Non-Destructive Identification of Structural and Compositional Defects from Microbumps to FinFET
Authors: Lau S. H. , Stripe Benjamin , Lewis Sylvia , Yang Xiaolin , Yun Wenbing
Published: December 2020

New heterogeneous 3D integration schemes and continuing miniaturization of semiconductor packaging components, such as micropillars, are driving demand for substantive changes to conventional PFA (physical failure analysis). In particular, desired performance capabilities include the ability to nondestructively determine failures within seconds to minutes. New tools should be quantitative, have sufficient resolution to determine sub-micron sized defects and voids in TSVs at the wafer or package level. It should also measure thickness and their material composition of multilayer structures above the wafer surface, such as microbumps, or those below the surface including UBM and RDL. In this paper we are introducing a novel x-ray fluorescence microscope technique capable of solving the above applications in advanced packaging for PFA and process development. The same technique can also be applied in the front end metrology of new gate materials, 3D FinFET structures within test structures in patterned wafers. Characterization of sub nanoscopic changes (sensitivity of sub-angstrom) in film and dopants deposited in 3D structures will also be shown. With its high sensitivity for trace materials, contamination analysis of post hard mask residue, post metal etch residue especially in high aspect ratio structures is also possible.
LADA Synchronization for Symmetric and Asymmetric ATE Test Program Cycles
Authors: Karunanithi Arun Kumar , Caroselli Joseph , Christensen Jason , Espitia Michell
Published: December 2020

Laser Assisted Device Alteration (LADA) or Soft Defect Localization (SDL) is commonly used to root cause device marginality due to functional or structural failures. At a high level, LADA involves setting the device under test (DUT) at its marginal state and using focused near infra-red laser beams to perturb sensitive circuitry [1]. Scanning the focused laser beam over the die can be a long and time-consuming process. In this paper, two LADA cases are presented, which involve a parametric measurement failure while running a dynamic ATE test. Using LADA technique, these two cases were root caused. These two cases also explain how a parametric measurement-based LADA can be setup on ATE, as well as a synchronization method independent of vectors in a pattern. Synchronization was necessitated in the 2nd case due to the asymmetric test program loop, as well as the long test program cycle time. There are many factors which impact LADA turnaround time and it can take anywhere between few seconds to one day. The two major factors are the size of the Area of Interest (AOI) and test program cycle time. Test program cycle time influences the laser “dwell time” for LADA. Dwell time, in simple terms, is the total time the laser is parked at each pixel. The laser can also be synchronized with the test program cycle, keeping the two always in phase. This is explained in Case 2, where LADA synchronization was implemented, and the analysis was successfully completed in time, even though the test cycle time was very long.
A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults
Authors: Estores Rommel , Gucht Karo Vander
Published: December 2020

This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.
Site-Specific Low Angle Plasma FIB Milling for Cross-Sectional Electrical Characterization
Authors: Zhang Chuan , Li Jane Y. , Aguada John , Marks Howard
Published: December 2020

This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.
Cervical Radiculopathy Focus on Characteristics and Differential Diagnosis
Authors: Kang Kyung-Chung , Lee Hee Sung , Lee Jung-Hee
Published: December 2020

Cervical radiculopathy is characterized by neurological dysfunction caused by compression and inflammation of the spinal nerves or nerve roots of the cervical spine. It mainly presents with neck and arm pain, sensory loss, motor dysfunction, and reflex changes according to the dermatomal distribution. The most common causes of cervical radiculopathy are cervical disc herniation and cervical spondylosis. It is important to find the exact symptomatic segment and distinguish between conditions that may mimic certain cervical radicular compression syndromes through meticulous physical examinations and precise reading of radiographs. Non-surgical treatments are recommended as an initial management. Surgery is applicable to patients with intractable or persistent pain despite sufficient conservative management or with severe or progressive neurological deficits. Cervical radiculopathy is treated surgically by anterior and/or posterior approaches. The appropriate choice of surgical treatment should be individualized, considering the patient’s main pathophysiology, specific clinical symptoms and radiographic findings thoroughly.