bluuebunny/crossref_metadata_2025 huggingface dataset:
Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays
Authors: Acciaro Vincenzo , Nayak Amiya
Published: September 2007

A common technique widely used to achieve fault tolerance in systolic arrays consists in
incorporating in the array additional processing elements (PEs) and extra bypass links.
Given a sufficient number of PEs and a large enough set of bypass links, it might seem
that the array can easily tolerate a large number of faults provided they do not occur in
consecutive locations. It is not always the case as shown in this paper. In fact, certain
fault patterns exist and may occur which would prevent any kind of restructuring of the
aray, thus making the structure unusable. For a given set of bypass links from each PE
in the array, it is possible to identify such fault patterns which will prevent any
reconfiguration. In this paper, we identify the class of fault patterns that are
catastrophic for linear systolic arrays, examine their characteristics, and describe a
method for constructing such fault patterns.
Simulation of Si‐MOSFETs with the Mutation OperatorMonte Carlo Method
Authors: Jakumeit Jürgen , Duncan Amanda , Ravaioli Umberto , Hess Karl
Published: September 2007

The Mutation Operator Monte Carlo method (MOMC) is a new type of Monte Carlo
technique for the study of hot electron related effects in semiconductor devices. The
MOMC calculates energy distributions of electrons by a physical mutation of the
distribution towards a stationary condition. In this work we compare results of an one
dimensional simulation of an 800nm Si‐MOSFET with full band Monte Carlo
calculations and measurement results. Starting from the potential distribution resulting
from a drift diffusion simulation, the MOMC calculates electron distributions which are
comparable to FBMC‐results within minutes on a modern workstation. From these
distributions, substrate and gate currents close to experimental results can be calculated.
These results show that the MOMC is useful as a post‐processor for the investigation of
hot electron related problems in Si‐MOSFETs. Beside the computational efficiency, a
further advantage of the MOMC compared to standard MC techniques is the good
resolution of the high energy tail of the distribution without the necessity of any
statistical enhancement.
New Approach to Hot Electron Effects in Si‐MOSFETsBased on an Evolutionary Algorithm Using a Monte CarloLike Mutation Operator
Authors: Jakumeit J. , Ravaioli U. , Hess K.
Published: September 2007

We introduce a new approach to hot electron effects in Si‐MOSFETs, based on a mixture of
evolutionary optimization algorithms and Monte Carlo technique. The Evolutionary Algorithm
searchs for electron distributions which fit a given goal, for example a measured substrate
current and in this way can calculate backwards electron distributions from
measurement results. The search of the Evolutionary Algorithm is directed toward physically
correct distributions by help of a Monte Carlo like mutation operator. Results for bulk‐Si
demonstrate the correctness of the physical model in the Monte Carlo like mutation operator
and the backward calculation ability of the Evolutionary Algorithm. First results for Si‐MOSFETs
are qualitatively comparable to results of a Full Band Monte Carlo simulation.
Transverse Patterns in the Bistable Resonant TunnelingSystems Under Ballistic Lateral Transport
Authors: Kochelap V. A. , Glavin B. A. , Mitin V. V.
Published: September 2007

We report the theoretical investigation of the phenomenon of the formation of patterns
transverse to the tunneling current in resonant tunneling double‐barrier heterostructures
in the case of wide range of bistable voltages. In contrast to the case of the patterns in
the structures with small region of bistability, for pronounced bistability electron lateral
transport is strongly nonlocal. We performed numerical simulations of the stationary
and mobile patterns using special variational procedure. Our results revealed that
though the possible types of patterns remains the same as for the structures with small
bistability region, their characteristics are modified considerably.
A Hot‐Hole Transport Model Based on SphericalHarmonics Expansion of the Anisotropic Bandstructure
Authors: Kosina H. , Harrer M.
Published: September 2007

To represent the valence bands of cubic semiconductors a coordinate transformation is proposed
such that the hole energy becomes an independent variable. This choice considerably
simplifies the evaluation of the integrated scattering probability and the choice of the state
after scattering in a Monte Carlo procedure. In the new coordinate system, a numerically
given band structure is expanded into a series of spherical harmonics. This expansion technique
is capable of resolving details of the band structure at the Brillouin zone boundary and
hence can span an energy range of several electron‐volts. Results of a Monte Carlo simulation
employing the new band representation are shown.
Rate Equation Modelling of NonlinearDynamics in Directly Modulated MultipleQuantum Well Laser Diodes
Authors: Bennett Stephen , Snowden Christopher M. , Iezekiel Stavros
Published: September 2007

A theoretical (using rate equations) and experimental study of the nonlinear dynamics
of a distributed feedback multiple quantum well laser diode is presented. The analysis is
performed under direct modulation. Period doubling and period tripling are identified
in both the measurements and simulations. Period doubling is found over a wide range
of modulation frequencies in the laser. Computational results using rate equations show
good agreement with the experimental results.
Modeling Nonlinear and Chaotic Dynamicsin Semiconductor Device Structures
Authors: Schöll Eckehard
Published: September 2007

We review the modeling and simulation of electrical transport instabilities in semiconductors
with a special emphasis on recent progress in the application to semiconductor microstructures.
The following models are treated in detail: (i) The dynamics of current filaments in the
regime of low‐temperature impurity breakdown is studied. In particular we perform 2D simulations
of the nascence of a filament upon application of a bias voltage. (ii) Vertical electrical
transport in layered semiconductor structures like the heterostructure hot electron diode is
considered. Periodic as well as chaotic spatio‐temporal spiking of the current is obtained. In
particular we find long transients of spatio‐temporal chaos preceding regular spiking.
Advantages of Semiconductor Device SimulatorCombining Electromagnetic and ElectronTransport Models
Authors: Sohel Imtiaz S. M. , El-Ghazaly Samir M. , Grondin Robert O.
Published: September 2007

Physical simulation of semiconductor devices at high frequencies involves not only
semiconductor transport issues but also electromagnetic wave propagation issues. In
order to obtain the nonlinear and the large‐signal characteristics of the semiconductor
devices, an electromagnetic model should replace the traditional quasi‐static model in
the device simulator. In this paper, the advantages of a semiconductor device simulator
combining an electromagnetic and an electron transport models are presented. This
study is based on a semiconductor device simulator that couples a semiconductor model
to the 3D time‐domain solution of Maxwell′s equations. The electromagnetic wave
propagation effects on the millimeter‐wave FETs are thoroughly analyzed. The use of
the electromagnetic model over the conventional quasi‐static model provides the actual
device response at high frequencies. It also shows the nonlinear energy build‐up along
the device width whereas the quasi‐static model provides a linear increase of energy. The
combined model is capable of predicting the device nonlinearity and harmonic
distortion of amplifier circuits at large signal.
Semiconductor Device Noise Computation Basedon the Deterministic Solution of the Poissonand Boltzmann Transport Equations
Authors: Piazza Alfredo J. , Korman Can E.
Published: September 2007

Numerical simulation results of noise due to current fluctuations along an n+ − n − n+ submicron structure are presented. The mathematical framework is based on the
interpretation of the equations describing electron transport in the semiclassical
transport model as stochastic differential equations (SDE). According to this formalism
the key computations for the spectral density describing the noise process are reduced to
a special initial value problem for the Boltzmann transport equation (BTE). The
algorithm employed in the computation of the space dependent noise autocovariance
function involves two main processes: the stationary self‐consistent solution of the
Boltzmann and Poisson equations, and a transient solution of the BTE with special
initial conditions. The solution method for the BTE is based on the Legendre
polynomial method. Noise due to acoustic and optical scattering and the effects of nonparabolicity
are considered in the physical model.
Electron Mobility and Monte Carlo device simulation of MOSFETs
Authors: Yamakawa S. , Ueno H. , Taniguchi K. , Hamaguchi C. , Miyatsuji K. , Masaki K. , Ravaioli U.
Published: September 2007

The electron mobility in the inversion layer of a MOSFET, formed on the (100) silicon surface,
is calculated by using a Monte Carlo approach which takes into account size quantization,
acoustic phonon scattering, intervalley phonon scattering and surface roughness
scattering. Degeneracy is also considered because it is important at higher normal effective
fields (high gate voltages). The main emphasis is placed on the influence of the specific autocovariance
function, used to describe the surface roughness, on the electron mobility. It is
found that the electron mobility calculated with roughness scattering rates based on the exponential
function shows a good agreement with experiments. Device simulation of a MOSFET
is carried out to demonstrate the usefulness of the present model, where 3D electron states are
taken into account in addtion to the 2D electron states.
Hyperbolic Hydrodynamical Model of CarrierTransport in Semiconductors
Authors: Anile Angelo Marcello , Romano Vittorio , Russo Giovanni
Published: September 2007

A hydrodynamical model for semiconductors based on Extended Thermodynamics is
presented and a suitable numerical scheme is proposed.
Distributed Algorithms for Three‐dimensionalSemiconductor Device Simulations
Authors: Ieong Mei-Kei , Tang Ting-Wei
Published: September 2007

We describe a newly developed parallel three‐dimensional semiconductor device simulator.
The program utilizes the message passing architecture and has been developed on a network
of workstations. Two iterative algorithms to solve the nonlinear semiconductor device equations
are presented. The algorithms are tested by simulating a three‐dimensional MOSFET
structure. A near‐ideal speedup for the distributed algorithms has been obtained for Poisson’s
equation.
A β‐SiC MOSFET Monte Carlo Simulator IncludingInversion Layer Quantization
Authors: Gámiz F. , Roldán J. B. , López-Villanueva J. A.
Published: September 2007

Electron transport properties in SiC quantized inversion layers have been studied by
means of a Monte Carlo procedure. It has been observed that the contribution of polaroptical
phonon scattering produces a significant influence of the effective‐electric field
on the high longitudinal field transport regime, this being the main difference of SiC
with respect to standard Si inversion layers. The energy‐ and momentum‐relaxation
times have been calculated and the results suggest that electron velocity overshoot
effects are less important than in Si MOSFETs. The electron mobility is not very
different from their silicon counterparts, but the saturation velocity is higher.
A High Level Synthesis System for VLSI Image Processing Applications
Authors: Verdier François S. , Zavidovique Bertrand
Published: September 2007

We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a “front‐end” data‐flow emulator for validation of the algorithms and the RTL‐synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the “restricted” domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data‐path synthesis (scheduling and module selection) and then for control synthesis and data‐path completion (binding). An interesting feature of the first optimization is the use of the data‐flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis
Authors: Masselos K. , Merakos P. , Stouraitis T. , Goutis C. E.
Published: September 2007

A novel architectural transformation for low power synthesis of inner product
computational structures is presented. The proposed transformation reorders the sequence
of evaluation of the multiply‐accumulate operations that form the inner products.
Information related to both coefficients, which are statically determined, and data,
which are dynamic, is used to drive the reordering of computation. The reordering of
computation reduces the switching activity at the inputs of the computational units
but inside them as well leading to power consumption reduction. Different classes of
algorithms requiring inner product computation are identified and the problem of
computation reordering is formulated for each of them. The target architecture to which
the proposed transformation applies is based on a power optimal memory organization
and is described in detail. Experimental results for several DSP algorithms show that the
proposed transformation leads to significant savings in net switching activity and thus in
power consumption.
Concurrency Preserving Partitioning Algorithm forParallel Logic Simulation
Authors: Kim Hong K. , Jean Jack
Published: September 2007

A partitioning algorithm for parallel discrete event gate‐level logic simulations is
proposed in this paper. Unlike most other partitioning algorithms, the proposed
algorithm preserves computation concurrency by assigning to processors circuit gates
that can be evaluated at about the same time. As a result, the improved concurrency
preserving partitioning (iCPP) algorithm can provide better load balancing throughout
the period of a parallel simulation. This is especially important when the algorithm is
used together with a Time Warp simulation where a high degree of concurrency can lead
to fewer rollbacks and better performance. The algorithm consists of three phases and
three conflicting goals can be separately considered so to reduce computational
complexity.

To evaluate the quality of partitioning algorithms in terms of preserving concurrency,
a concurrency metric that requires neither sequential nor parallel simulation is
proposed. A levelization technique is used in computing the metric so to determine
gates which can be evaluated at about the same time. A parallel gate‐level logic
simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the
performance of the iCPP algorithm. The results are compared with several other
partitioning algorithms to show that the iCPP algorithm does preserve concurrency
pretty well and reasonable speedup may be achieved with the algorithm.
Principles for Language Extensions to VHDL to Support High‐Level Modeling
Authors: Ashenden Peter J. , Wilsey Philip A.
Published: September 2007

This paper reviews proposals for extensions to VHDL to support high‐level modeling
and places them within a taxonomy that describes the modeling requirements they
address. Many of the proposals focus on object‐oriented extensions, whereas this paper
argues that extension of VHDL to support high‐level modeling requires a broader
review. The paper presents a detailed discussion of issues to be considered in adding
high‐level modeling extensions to VHDL, including concurrency and communication,
abstraction using entity interfaces, object‐oriented data modeling, encapsulation, signal
assignment semantics, shared variables, multiple inheritance, genericity and synthesis.
Emphasis is placed on the importance of designing simple orthogonal semantic
mechanisms that interact in well defined ways, and that integrate cleanly with existing
language features.
Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes
Authors: Middendorf Martin , Schmeck Hartmut , Schröder Heiko , Turner Gavin
Published: September 2007

Algorithms for multiplying several types of sparse n x n‐matrices on dynamically
reconfigurable n x n‐arrays are presented. For some classes of sparse matrices constant
time algorithms are given, e.g., when the first matrix has at most kn elements in each
column or in each row and the second matrix has at most kn nonzero elements in each
row, where k is a constant. Moreover, O(k
) algorithms are obtained for the case that
one matrix is a general sparse matrix with at most kn nonzero elements and the other
matrix has at most k nonzero elements in every row or in every column. Also a lower
bound of Ω(
) is proved for this and other cases which shows that the algorithms are
close to the optimum.
Finding Combined L1 and Link Metric ShortestPaths in the Presence of Orthogonal Obstacles:A Heuristic Approach
Authors: Lim Joon Shik , Iyengar S. Sitharama , Zheng Si-Qing
Published: September 2007

This paper presents new heuristic search algorithms for searching combined rectilinear
(L1) and link metric shortest paths in the presence of orthogonal obstacles. The Guided Minimum Detour (GMD)
algorithm for L1 metric combines the best features of mazerunning
algorithms and line‐search algorithms. The Line-by-Line Guided Minimum
Detour (LGMD) algorithm for L1 metric is a modification of the GMD algorithm that
improves on efficiency using line‐by‐line extensions. Our GMD and LGMD algorithms
always find a rectilinear shortest path using the guided A* search method without
constructing a connection graph that contains shortest paths. The GMD and the LGMD
algorithms can be implemented in O(m+eloge+NlogN)
and O(eloge+NlogN) time,
respectively, and O(e+N) space, where m is the total number of searched nodes, e is the
number of boundary sides of obstacles, and N is the total number of searched line
segments. Based on the LGMD algorithm, we consider not only the problems of finding
a link metric shortest path in terms of the number of bends, but also the combined L1
metric and link metric shortest path in terms of the length and the number of bends.
Modeling Crystallization Dynamics when the Avrami Model Fails
Authors: Gough Terry , Illner Reinhard
Published: September 2007

Recent experiments on the formation of crystalline CO2 from a newly discovered binary
phase consisting of CO2 and C2H2 at 90° K fail to be adequately simulated by Avrami
equations. The purpose of this note is to develop an alternative to the Avrami model
which can make accurate predictions for these experiments. The new model uses empirical
approximations to the distribution densities of the volumes of three‐dimensional
Voronoi cells defined by Poisson‐generated crystallization kernels (nuclei). Inside each
Voronoi cell, the growth of the crystal is assumed to be linear in diameter (i.e., cubic in
volume) until the cell is filled by the CO2 crystals and the C2H2 (thought of as a waste
product). The cumulative growth curve is computed by averaging these individual growth
curves with respect to the distribution density of the volumes of the Voronoi cells. Agreement
with the experiments is excellent.
Tuning Strategies for Global Interconnectsin High‐Performance Deep‐Submicron ICs
Authors: Kahng Andrew B. , Muddu Sudhakar , Sarto Egino
Published: September 2007

Interconnect tuning is an increasingly critical degree of freedom in the physical design of
high‐performance VLSI systems. By interconnect tuning, we refer to the selection of line
thicknesses, widths and spacings in multi‐layer interconnect to simultaneously optimize
signal distribution, signal performance, signal integrity, and interconnect manufacturability
and reliability. This is a key activity in most leading‐edge design projects, but has
received little attention in the literature. Our work provides the first technology‐specific
studies of interconnect tuning in the literature. We center on global wiring layers and
interconnect tuning issues related to bus routing, repeater insertion, and choice of
shielding/spacing rules for signal integrity and performance. We address four basic
questions. (1) How should width and spacing be allocated to maximize performance for
a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at
which repeaters Should be inserted into global interconnects? (3) Under what circumstances
are shield wires the optimum technique for improving interconnect performance?
(4) In global interconnect with repeaters, what other interconnect tuning is possible?
Our study of question (4) demonstrates a new approach of offsetting repeater placements
that can reduce worst‐case cross‐chip delays by over 30% in current technologies.
An ILP Formulation for Minimizing the Numberof Feedthrough Cells in a Standard Cell Placement
Authors: Yan Jin-Tai
Published: September 2007

It is well known that standard cells have been widely used to implement VLSI circuits in
the automation of physical design. Since one major aim of a cell‐based design is to minimize
total layout area in a standard cell placement, the number of feedthrough cells will
be minimized to reduce total cell area in a standard cell placement. In this paper, first,
we model a partitioning‐based row assignment (PRA) problem to minimize the number
of feedthrough cells in a standard cell placement. Furthermore, an integer linear programming
(ILP) approach is proposed to solve the PRA problem in a standard cell
placement. Finally, the ILP approach has been implemented and two standard‐cell netlists,
Primary 1 and Primary 2, have been tested by the proposed approach, Bose′s approach
[4] and an exhaustive search approach, respectively. The experimental results show
that the ILP approach obtains fewer feedthrough cells than Bose′s approach in a
partitioning‐based standard cell placement.
Design and Implementation of DynamicLoad Balancing Algorithms for Rollback Reductionin Optimistic PDES
Authors: Sarkar Falguni , Das Sajal K.
Published: September 2007

In an optimistic parallel simulation, logical processes (Ips) proceed with their
computation without any constraints. However, if the computing requirements of
different lps are not balanced or if the processors are not homogeneous, some lps may
lag behind in simulation time while others surge forward. In other words, if the
simulation clocks of different lps are not progressing at the same rate, cascading
rollbacks may occur nullifying the potential benefit of an optimistic parallel discrete
event simulation (PDES). Hence it is necessary to balance the computational load on
different lps in such a way that their local simulation clocks advance almost at the same
rate. In this paper, we propose two algorithms for dynamic load balancing which reduce
the number of rollbacks in an optimistic PDES system. Our first algorithm is based on
the load transfer mechanism between lps; while the second algorithm, based on the
principle of evolutionary strategy, migrates logical processes between several pairs of
physical processors. We have implemented both of these algorithms on a cluster of
heterogeneous workstations and studied their performance. The experimental results
show that the algorithm based on the load transfer is effective when the grain size is
greater than 10 milliseconds. The algorithm based on the process migration yields good
performance only for grain sizes of 20 milliseconds or larger. In both of these cases the
speed up ranges mostly between and 2 using four processors.
Single Step Undirected Reconfigurable Networks
Authors: Ben-Asher Yosi , Schuster Assaf
Published: September 2007

The reconfigurable mesh (RN‐MESH) can solve a large class of problems in constant
time, including problems that require logarithmic time by other, even shared memory,
models such as the PRAM with a similar number of processors [3]. In this work we show
that for the RN‐MESH these constants can always be reduced to one, still using a
polynomial number of processors. Given a reconfigurable mesh that computes a set of
values in constant time, we show that it can be simulated by a single step reconfigurable
mesh with maximum size that is polynomial in the size of the original mesh. The proof is
constructive, where the construction of the single step RN‐MESH holds for the
relatively weak undirected RN‐MESH model. In this model broadcasts made on buses
arrive at all nodes that belong to the undirected connected component of the
transmitting processor. A result similar to the one that is obtained in this work was
previously obtained for the directed reconfigurable mesh model (DRN) [5]. However,
the construction for the DRN‐MESH relies on the fact that the buses are directed, and
thus cannot be applied to the undirected case. In addition, the construction presented
here is simpler and uses significantly fewer processors than the one obtained for the
DRN‐MESH.
Partitionable Bus‐based String‐matching Algorithmfor Run‐length Coded Strings With VLDCs
Authors: Chen Hsiu-Niang , Chung Kuo-Liang
Published: September 2007

String matching (SM) problem is to find the occurrences of a pattern within a text. A
vanable length don′t care (VLDC) is a special symbol, not belonging to a finite alphabet
∑ but in ∑*. Each VLDC in the pattern can match any substring in the text. Given a
run‐length coded text of length 2n over ∑ and a run‐length coded pattern of length 2m
over ∑*, this paper first presents an O(1) time parallel SM algorithm for run‐length
coded strings with VLDCs on a reconfigurable mesh (RM) using O(nm) processors.
Consider the hardware limitation in VLSI implementation. In order to be suitable for
VLSI modular implementation, a partitionable parallel algorithm on the RM with
limited processors is further presented. For N < n and M < m, the SM for run‐length
coded strings with VLDCs can be solved in O
time on the RM using
O(NM)(= O((nm)/()) processors, where = [(n – 1)/(N – 1)] and
= [(m – 1)/(M – 1)].
Dispersion Lemmas Revisited
Authors: Gasser I. , Markowich P. A. , Perthame B.
Published: September 2007

We investigate regularizing dispersive effects for various classical equations, e.g., the
Schrödinger and Dirac equations. After Wigner transform, these dispersive estimates are
reduced to moment lemmas for kinetic equations. They yield new regularization results for
the Schrödinger equation (valid up to the semiclassical limit) and the Dirac equation.
Rigorous Derivation of the Pauli Equation With Time‐dependentElectromagnetic Field
Authors: Mauser Norbert J.
Published: September 2007

In this work we discuss relativistic corrections for the description of charge carriers in a
quantum mechanical framework. The fundamental equation is the Dirac equation
which takes into account also the electron′s spin. However, this equation intrinsically
also incorporates positrons which play no role in applications in solid state physics. We
give a rigorous derivation of the Pauli equation describing electrons in a first order
approximation of the Dirac equation in the limit of infinite velocity of light. We deal
with time‐dependent electromagnetic potentials where no rigorous results have been
given before. Our approach is based on the use of appropriate projection operators for
the electron and the positron component of the spinor which are better suited than the
widely used simple splitting into ‘upper (large)’ and ‘lower (small) component’. We also
systematically derive corrections at second order in 1/c where we essentially recover the
results of the Foldy‐Wouthuysen approach. However, due to the non‐static problem,
differences occur in the term which couples the electric field with the spin.
Analytical Engines are Unnecessary in Top‐down Partitioning‐based Placement
Authors: Alpert C. J. , Caldwell A. E. , Chan T. F. , Huang D. J.-H. , Kahng A. B. , Markov I. L. , Moroz M. S.
Published: September 2007

The top‐down “quadratic placement” methodology is rooted in such works as [36, 9, 32]
and is reputedly the basis of commercial and in‐house VLSI placement tools. This
methodology iterates between two basic steps: solving sparse systems of linear equations
to achieve a continuous placement solution, and “legalization” of the placement by
transportation or partitioning. Our work, which extends [5], studies implementation
choices and underlying motivations for the quadratic placement methodology. We first
recall some observations from [5], e.g., that (i) Krylov subspace engines for solving
sparse linear systems are more effective than traditional successive over‐relaxation
(SOR) engines [33] and (ii) that correlation convergence criteria can maintain solution
quality while using substantially fewer solver iterations. The focus of our investigation is
the coupling of numerical solvers to iterative partitioners that is a hallmark of the
quadratic placement methodology. We provide evidence that this coupling may have
historically been motivated by the pre‐1990’s weakness of min‐cut partitioners, i.e.,
numerical engines were needed to provide helpful hints to weak min‐cut partitioners. In
particular, we show that a modern multilevel FM implementation [2] derives no benefit
from such coupling. We also show that most insights obtained from study of individual
min‐cut partitioning instances (within the top‐down placement) also hold within the
overall context of a complete top‐down placer implementation.
Abstract Architecture Representation Using VSPEC
Authors: Baraona Phillip , Alexander Perry
Published: September 2007

Complex digital systems are often decomposed into architectures very early in the design
process. Unfortunately, traditional simulation based languages such as VHDL do not
allow the impact of these architectural decisions to be evaluated until a complete,
simulatable design of the system is available. After a complete design is available,
architectural errors are time‐consuming and expensive to correct. However, there is an
alternative to simulation based techniques: formal analysis of abstract architectures at
the requirements level. This paper describes VSBEC′S approach for defining and analyzing
abstract architectures. VSBEC is a Larch interface language for VHDL that allows a
designer to specify the requirements of a VHDL entity using the canonical Larch
approach. VHDL structural architectures that instantiate VSPEC entities define abstract
architectures. These abstract architectures can be evaluated at the requirements level to
determine the impact of architectural decisions. This paper briefly introduces VSPEC
provides a formal definition of VSPEC abstract architectures and presents two examples
that illustrate the architectural definition capabilities of the language.
An Efficient Parallel VLSI Sorting Architecture
Authors: Zhang Yanjun , Zheng S. Q.
Published: September 2007

We present a new parallel sorting algorithm that uses a fixed‐size sorter iteratively to
sort inputs of arbitrary size. A parallel sorting architecture based on this algorithm is
proposed. This architecture consists of three components, linear arrays that support
constant‐time operations, a multilevel sorting network, and a termination detection tree,
all operating concurrently in systolic processing fashion. The structure of this sorting
architecture is simple and regular, highly suitable for VLSI realization. Theoretical
analysis and experimental data indicate that the performance of this architecture is
likely to be excellent in practice.
Multilevel k‐way Hypergraph Partitioning
Authors: Karypis George , Kumar Vipin
Published: September 2007

In this paper, we present a new multilevel k‐way hypergraph partitioning algorithm that
substantially outperforms the existing state‐of‐the‐art K‐PM/LR algorithm for multi‐way
partitioning, both for optimizing local as well as global objectives. Experiments on
the ISPD98 benchmark suite show that the partitionings produced by our scheme are on
the average 15% to 23% better than those produced by the K‐PM/LR algorithm, both
in terms of the hyperedge cut as well as the (K – 1) metric. Furthermore, our algorithm
is significantly faster, requiring 4 to 5 times less time than that required by K‐PM/LR.
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self‐checking Circuits
Authors: Metra Cecilia , Favalli Michele , Riccò Bruno
Published: September 2007

In this paper we propose signal coding and CMOS gates that are suitable to self‐checking
circuits with combinational functional blocks implemented also by next generation,
very deep submicron technology. In particular, our functional blocks satisfy
the Strongly Fault‐Secure property with respect to a wide set of possible, internal
faults including not only conventional stuck‐ats, but also transistor stuck‐ons, transistor
stuck‐opens, resistive bridgings, delays, crosstalks and transient faults, that are very
likely to affect next generation ICs. Compared to alternative, existing solutions, that
proposed here does not imply any critical constraint on the circuit electrical parameters.
Therefore, it is suitable to be adopted to design very deep submicron self‐checking circuits
which, compared to todays′ circuits, will present significantly increased sensitivity
to parameter variations occurring during fabrication.
An Analytical, Temperature‐dependent Modelfor Majority‐ and Minority‐carrier Mobilityin Silicon Devices
Authors: Reggiani Susanna , Valdinoci Marina , Colalongo Luigi , Rudan Massimo , Baccarani Giorgio
Published: September 2007

A new analytical model for carrier mobility in silicon is presented, which is strongly
oriented to CAD and suitable for implementation in device simulators. The effects of
the electric field, temperature, and doping concentration are accounted for. In particular,
the model unifies the descriptions of majority‐ and minority‐carrier mobility and
includes the full temperature dependence. The effects of a high longitudinal field are
included in the conventional velocity‐saturation form; the doping dependence is also
incorporated in the latter. The model has been worked out starting from a preliminary
investigation using a Boltzmann solver, and has been validated by a number of comparisons
with published experiments on silicon.
Tabu Search: A Meta Heuristic for Netlist Partitioning
Authors: Areibi Shawki , Vannelli Anthony
Published: September 2007

The main goal of the paper is to explore the effectiveness of a new method called Tabu
Search [1] on partitioning and compare it with two techniques widely used in CAD tools
for circuit partitioning i.e., Sanchis Interchange method and Simulated Annealing, in
terms of the running time and quality of solution. The proposed method integrates the
well known iterative multi‐way interchange method with Tabu Search and leads to a
very powerful network partitioning heuristic. It is characterized by an ability to escape
local optima which usually cause simple descent algorithms to terminate by using a
short term memory of recent solutions. Moreover, Tabu Search permits backtracking to
previous solutions, which explore different directions and generates better partitions.

The quality of the test results on MCNC benchmark circuits are very promising in
most cases. Tabu Search yields netlist partitions that contain 20%–67% fewer cut nets
and are generated 2/3 to (1/2) times faster than the best netlist partitions obtained by
using an interchange method. Comparable partitions to those obtained by Simulated
Annealing are obtained 5 to 20 times faster.
A New 2‐way Multi‐level Partitioning Algorithm
Authors: Saab Youssef
Published: September 2007

Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, the
multi‐level partitioning approach has been used with success by a number of
researchers. This paper describes a new multi‐level partitioning algorithm (PART) that
combines a blend of iterative improvement and clustering, biasing of node gains, and
local uphill climbs. PART is competitive with recent state‐of‐the‐art partitioning
algorithms. PART was able to find new lower cuts for many benchmark circuits. Under
suitably mild assumptions, PART also runs in linear time.
A Chip for a Routing Table Based on a Novel Modified Trie Algorithm
Authors: Torres D. , Larios A. , Guzmán M.
Published: September 2007

The design for a routing table circuit for Ethernet‐, IP‐ and ATM‐applications is
presented. Starting point for the design was an object‐oriented general behavior of the
routing table. The selected data structure for the routing table is based on a modification
of the structure denominated trie, saving one search level and memory space. The
architecture for searching and sorting of data, implemented in hardware, is explained.
This modified trie stores 64 K addresses and the associated data, achieving a high
performance too. The circuit, which can support a flow of 500000 frames/s, is connected
to the PCI Bus. For the implementation a FLEX10K100 from Altera Company was
used.
Discretization of Anisotropic Convection‐diffusionEquations, Convective M‐matrices and their IterativeSolution
Authors: Rose Donald J. , Shao Hai , Henriquez Craig S.
Published: September 2007

We derive the constant‐j box method discretization for the convection‐diffusion
equation, ∇j = f, with j = −α∇u + βu
. In two dimensions, α is a 2 × 2 symmetric, positive
definite tensor field and β is a two‐dimensional vector field. This derivation generalizes
the well‐known Scharfetter‐Gummel discretization of the continuity equations in
semiconductor device simulation. We define the anisotropic Delaunay condition and
show that under this condition and appropriate evaluations of α and β, the stiffness
matrix, M, of the discretization is a convective M‐matrix. We then examine classical
iterative splittings of M and show that convection (even convection dominance) does
not degrade the rate of convergence of such iterations relative to the purely diffusive (β=0) problem under certain conditions.
A Low‐Voltage Floating‐Gate MOS Biquad
Authors: Rodríguez-Villegas Esther O. , Yúfera Alberto , Rueda Adoración
Published: September 2007

A second‐order gm‐C filter based on the Floating‐Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage
supply with a full differential input linear range and a THD below 1%. Programming
and tuning are performed by means of a single voltage signal. The transconductor incorporates
a novel Common‐Mode Feedback Circuit (CMFB) based also on FGMOS
transistors.
Simulation of Optoelectronic Devices
Authors: Lugli Paolo , Compagnone Fabio , Carlo Aldo Di , Reale Andrea
Published: September 2007

In the spirit of reviewing various approaches to the modeling and simulation of optoelectronic
devices, we discuss two specific examples, related respectively to Semiconductor
Optical Amplifiers and to Quantum Cascade Lasers. In the former case, a
tight‐binding analysis is performed aimed at the optimization of the polarization
independence of the device. Further, a rate‐equation model is set up to describe the
dynamics of gain recovery after optical pumping. A Monte Carlo simulation of a
superlattice quantum cascade laser is then presented which provides an insight into the
microscopic processes controlling the performance of this device.
Scaling of pHEMTs to Decanano Dimensions
Authors: Kalna K. , Asenov A. , Elgaid K. , Thayne I.
Published: September 2007

The effect of scaling into deep decanano dimensions on the performance of pseudomorphic
high electron mobility transistors (pHEMTs) is extensively studied using
Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and
30nm is performed in both lateral and vertical directions. The devices exhibit a
significant improvement in transconductance during scaling, even though external
resistances become a limiting factor.
An Upstream Flux Splitting Methodfor Hydrodynamic Modelingof Deep Submicron Devices
Authors: Shen Min , Yip Wai-Kay , Cheng Ming-C. , Liou J. J.
Published: September 2007

The advective upstream splitting method (AUSM) developed for fluid dynamics
problems has been applied to solving hydrodynamic semiconductor equations coupled
with the Poisson’s equation. In the AUSM, the flux vectors of a fluid system are split
into a convective component and a diffusive pressure component. Discretization of these
two physically distinct fluxes is thus performed separately in AUSM. Application of the
developed hydrodynamic AUSM to a GaAs MESFET with a gate length of 0.1 μm has
demonstrated its simplicity, efficiency and effectiveness in dealing with the highly
nonlinear hydrodynamic device system.
Test Generators Need to be Modified to Handle CMOS Designs
Authors: Savir Jacob
Published: September 2007

CMOS designs have some unique properties that prevent existing test generators from
computing a test vector for a fault when one might exist. The problem lies in the
premises laid out on what it takes to detect a stuck‐at fault. The basic premise that states
that it is required to set a line to 0(1) in order to detect a stuck‐at 1(0) fault, and then
propagate the error to an observable point, needs to be re‐examined. This is due to the
existence of indeterminate states throughout the logic. The paper distinguishes between
the traditional test vector (here called a hard-detect), and a potential test vector (here
called a soft-detect). Our proposed test set is the union of hard and soft‐detects. We also
re‐examine the issue of redundancy and show that it needs to be re‐defined in order to
comply with CMOS technology behavior.

This paper shows several examples to illustrate the problem; describes what it takes in
order to remedy it; proposes possible enhancements to existing test generation
algorithms, and outlines the risks faced in the event that no correcting steps are taken.
Low Power Digital Multimedia Telecommunication Designs
Authors: Cho Koon-Shik , Cho Jun-Dong
Published: September 2007

The increasing prominence of wireless multimedia systems and the need to limit power
capability in very‐high density VLSI chips have led to rapid and innovative
developments in low‐power design. Power reduction has emerged as a significant
design constraint in VLSI design. The need for wireless multimedia systems leads to
much higher power consumption than traditional portable applications. This paper
presents possible optimization technique to reduce the energy consumption for wireless
multimedia communication systems. Four topics are presented in the wireless
communication systems subsection which deal with architectures such as PN
acquisition, parallel correlator, matched filter and channel coding. Two topics include
the IDCT and motion estimation in multimedia application.

These topics consider algorithms and architectures for low power design such as using
hybrid architecture in PN acquisition, analyzing the algorithm and optimizing the
sample storage in parallel correlator, using complex matched filter that analog
operational circuits controlled by digital signals, adopting bit serial arithmetic for the
ACS operation in viterbi decoder, using CRC to adaptively terminate the SOVA
iteration in turbo decoder, using codesign in RS codec, disabling the processing
elements as soon as the distortion values become great than the minimum distortion
value in motion estimation, and exploiting the relative occurrence of zero‐valued DCT
coefficient in IDCT.
An Efficient Test Pattern Generation Scheme for an On Chip BIST
Authors: Varaprasad B. K. S. V. L. , Patnaik L. M. , Jamadagni H. S. , Agrawal V. K.
Published: September 2007

Testing and power consumption are becoming two critical issues in VLSI design due to
the growing complexity of VLSI circuits and remarkable success and growth of low
power applications (viz. portable consumer electronics and space applications). On chip
Built In Self Test (BIST) is a cost‐effective test methodology for highly complex VLSI
devices like Systems On Chip. This paper deals with cost‐effective Test Pattern Generation
(TPG) schemes in BIST. We present a novel methodology based on the use of
a suitable Linear Feedback Shift Register (LFSR) which cycles through the required
sequences (test vectors) aiming at a desired fault coverage causing minimum circuit
toggling and hence low power consumption while testing. The proposed technique uses
circuit simulation data for modeling. We show how to identify the LFSR using graph
theory techniques and compute its feedback coefficients (i.e., its characteristic
polynomial) for realization of a Test Pattern Generator.
Optimization of FIBMOS Through 2D SilvacoATLAS and 2D Monte Carlo Particle‐basedDevice Simulations
Authors: Kang J. , He X. , Vasileska D. , Schroder D. K.
Published: September 2007

Focused Ion Beam MOSFETs (FIBMOS) demonstrate large enhancements in core device
performance areas such as output resistance, hot electron reliability and voltage stability
upon channel length or drain voltage variation. In this work, we describe an optimization
technique for FIBMOS threshold voltage characterization using the 2D Silvaco ATLAS
simulator. Both ATLAS and 2D Monte Carlo particle‐based simulations were used to
show that FIBMOS devices exhibit enhanced current drive capabilities when compared to
normal MOSFETs. It was also found that the device performance is very much dependent
upon the FIB implant profile. High and narrow doping of the FIB implant leads to high
drain current and low hot carrier reliability, whereas low and wide doping gives rise to
lower drain current and higher hot carrier reliability.
A Novel Low‐power Shared Division and Square‐root Architecture Using the GST Algorithm
Authors: Kuhlmann Martin , Parhi Keshab K.
Published: September 2007

Although SRT division and square‐root approaches and GST division approach have
been known for long time, square‐root architectures based on the GST approach have
not been proposed so far which do not require a final division/multiplication of the scale
factor. A GST square‐root architecture is developed without requiring either a
multiplication to update the scaled square‐root quotient in each iteration or a division/multiplication by the scaling factor after completing the square‐root iterations.
Additionally, quantitative comparison of speed and power consumption of GST and
SRT division/square‐root units are presented. Shared divider and square‐root units are
designed based on the SRT and the GST approaches, in minimally and maximally
redundant radix‐4 representations. Simulations demonstrate that the worst‐case overall
latency of the minimally‐redundant GST architecture is 35% smaller compared to the
SRT. Alternatively, for a fixed latency, the minimally‐redundant GST architecture
based division and square‐root operations consume 32% and 28% less power,
respectively, compared to the maximally‐redundant SRT approach.
Simulation of Submicron Silicon Diodeswith a Non‐Parabolic Hydrodynamical Model Basedon the Maximum Entropy Principle
Authors: Muscato O. , Romano V.
Published: September 2007

A hydrodynamical model for electron transport in silicon semiconductors, free of any
fitting parameters, has been formulated in [1,2] on the basis of the maximum entropy
principle, by considering the energy band described by the Kane dispersion relation and
by including electron‐non polar optical phonon and electron‐acoustic phonon
scattering.

In [3] the validity of this model has been checked in the bulk case. Here the
consistence is investigated by comparing with Monte Carlo data the results of the
simulation of a submicron n+–n–n+ silicon diode for different length of the channel,
bias voltage and doping profile.

The results show that the model is sufficiently accurate for CAD purposes.