Ultra-Low Temperature Flattening Technique of Silicon Surface Using Xe/H2 Plasma
Authors: Suwa Tomoyuki , Teramoto Akinobu , Goto Tetsuya , Hirayama Masaki , Sugawa Shigetoshi , Ohmi Tadahiro 
Published: February 2020

(1) Introduction

The interface microroughness between the insulator film and the silicon substrate is one of the critical issues to the gate insulator film reliability and the performance of MOSFETs [1-2]. The atomically flat surface of Si(100) has been obtained by the ultra-pure Ar annealing at the temperature of 800 ºC or above [3-7]. The MOSFETs having atomically flat interface between the silicon substrate and the radical gate SiO2 film show higher performances than the MOSFETs having conventional interfaces [3,4,7]. The decreasing flattening temperature is effective to apply the flattening process to the patterned wafer just before the gate oxide formation. We have reported that the 800 oC annealing can be applied to the wafers having the shallow trench isolation (STI), and the breakdown field intensity (Ebd) improved and the random telegraph noise decreased [8]. In order to introduce the flattening process just before the gate oxide formation in the latest LSI manufacturing process such as Fin-FET, it is considered that lower flattening temperature is strongly required. Thus the flattening technique of silicon surface was developed by using Xe/H2 plasma at 400 oC. In this paper, MOS devices are fabricated by an introduction of Xe/H2plasma flattening technique and these electrical characteristics are evaluated.

(2) Experimental details

In this study, MOS capacitors were fabricated using Cz-n type Si(100) wafers (8-12 Ω·cm) as follows. For the device isolation, 300 nm-thick field oxide films were grown by a pyrogenic wet oxidation at 1000 oC followed by patterning the active region. These patterned wafers were cleaned by APM (29% NH4OH : 30% H2O2 : H2O = 0.05 : 1 : 5) solution with megasonic and  the native oxides were removed by 0.5% dilute HF. Just before the gate oxides formation, Xe/H2 plasma flattening process was performed by a microwave-excited high-density Xe(90%)/H2(10%) plasma at a pressure of 266 Pa and temperature of 400 °C for 3 min. The 7 nm-thick gate oxides were fabricated by radical oxidation followed by forming n+ poly-Si gate electrode and Al buck side electrode. Finally the forming gas (10 %H2/90 %N2) annealing at 400 oC was carried out for 30 min.

(3) Results and discussion

Fig 1 shows the 3×3 μm2 AFM images (a) before and (b) after flattening Si(100) surface by using the Xe/H2 plasma. The average roughness (Ra) of Si(100) surface was decreased from 0.12 nm to 0.039 nm by the Xe/H2 plasma treatment. Fig. 2 shows the variations of the breakdown field intensity (Ebd). Here, Ebd was determined at breakdown field in the current density versus the electric field (J-E) characteristics of MOS capacitors whose area was 10-4 cm2. By an introduction of the Xe/H2 plasma flattening, Ebd was improved more than 1 MV/cm and obtained the much smaller fluctuation of Ebd than that of conventional. From these results, improving Si surface flatness before gate oxide formation can be effective to reduce the variations of Ebd. The reason is considered that the local spots, where the excess electric field is induced in the roughened SiO2/Si interface, are drastically decreased by the Xe/H2 plasma flattening at even 400 oC. Consequently the Xe/H2plasma flattening technique can be effective to the advanced integrated circuit with very shrunk transistors such as three dimensional MOFET (Fin-FET).

Acknowledgments

This work was partially supported by JSPS KAKENHI Grant Number 22000010.

Reference

T. Ohmi, et al., Electron. Device Lett., 12, p.652 (1991).

T. Ohmi, et al., T-ED 39, p.537 (1992).

R. Kuroda, et al., T-ED, 56, p.291 (2009).

R. Kuroda, et al., Jpn. J. Appl. Phys., 48, p.04C048 (2009).

X. Li, T et al., ECS Trans. 28 p.299 (2010).

X. Li, et al., Microelec. Eng., 88, p.3133 (2011).

X. Li, et al., Jpn. J. Appl. Phys., 50, p.10PB05 (2011).

T. Goto, et al., Extended Abst. SSDM, F-1-3, p.670 (2014).

T. Suwa, et al., ECS Trans., 61, p.401 (2013).

Figure 1