(Invited) TmSiO As a CMOS-Compatible High-k Dielectric
Authors: Dentoni Litta Eugenio , Hellström Per-Erik , Östling Mikael 
Published: February 2020

High-k/metal gate stacks have been a core enabler of CMOS technology for almost a decade, allowing sub-nm equivalent oxide thickness (EOT) while keeping the gate leakage current density at acceptable levels [1]. State-of-the-art high-k/metal gate stacks employ a Hf-based high-k dielectric (typically HfO2) deposited on top of a thin interfacial layer (IL), which usually consists of chemical oxide (SiOx) and whose presence is crucial in order to guarantee the overall electrical quality of the gate stack [2]. It has indeed been shown that a thinner IL, while desirable from the point of view of EOT scaling, leads to problematic degradations in channel mobility [3], threshold voltage control [4], and device reliability [5].

Further scaling of high-k/metal gate stacks has been a central subject in recent research, and is usually addressed by replacing HfO2 with a higher-k material and/or by replacing SiOx with a high-k IL. The latter strategy is especially interesting, since the IL contributes ~1/2 of the total EOT of a scaled gate stack and since there are viable options to replace SiOx with a dielectric exhibiting significantly higher dielectric constant (~3x), whereas the same is not true for higher-k dielectrics. Lanthanide silicates have especially been shown to provide controllable thickness of the IL in the sub-nm regime and device-grade interface state density, rendering them extremely interesting as a potential replacement for SiOx IL [6].

Careful consideration of the material properties from the point of view of achieving controllable and reproducible formation of a sub-nm interfacial layer has led to the identification of thulium silicate (TmSiO) as a promising candidate IL for sub-10nm CMOS nodes. A straightforward process flow, compatible with industry-standard gate-first and gate-last integration schemes, has been demonstrated for integration of TmSiO in a high-k/metal gate stack, achieving EOT of the IL of 0.25±0.15 nm and interface state density ~1·1011 cm-2eV-1 [7]. Integration of TmSiO in Hf-based gate stacks has also been shown to be compatible with threshold voltage control techniques commonly used in gate-first and gate-last integration schemes [8], and gate-last MOSFETs achieving sub-nm EOT, 10 year device reliability and higher mobility than state-of-the-art SiOx/HfO2 devices have been demonstrated [9-10].

Replacing the SiOx IL with TmSiO can be especially advantageous in terms of channel mobility and device reliability, since both device properties have been shown to degrade strongly with decreasing IL thickness. Reliability in TmSiO/HfO2 MOSFETs has been investigated from the point of view of time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI), achieving expected lifetimes of 10 years for both nFETs and pFETs at EOT~0.8 nm and gate voltage ~1V (compatible with supply voltage in sub-10nm CMOS nodes). The effect of TmSiO on channel mobility has been analyzed by measuring electron mobility at high temperature and after constant voltage stress and comparing the observed trends with published data on SiOx/HfO2 devices, with the conclusion that replacing the SiOx IL with TmSiO can improve mobility by 20% at high effective field due to reduced remote phonon scattering. In this talk, the main advantages and challenges in the adoption of TmSiO as interfacial layer in scaled CMOS technology nodes will be addressed.

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