Proximity Gettering of Copper via Oxygen Precipitates for Silicon-on-Insulator Wafer
Authors: Park Jun-Seong , Kim Il-Hwan , Lee Gon-Sub , Park Jea-Gun 
Published: February 2020

Silicon-on-insulator (SOI) technology has attributed attention because it enables device to operate in high speed with reducing parasitic capacitance and body effect. However, in the conventional SOI wafer without any gettering site, a very small amount of metallic contaminants degrades the transistor. During fabrication of copper through-silicon-via (TSV) for 3D device structure, copper contaminants after copper damascene chemical-mechanical-polishing (CMP) are accumulated at top silicon layer, BOX layer and silicon substrate resulting in gate oxide leakage, junction leakage current, and threshold voltage shift, etc. Particularly, since the copper solubility in oxide layer is higher than that in silicon, the implementation of gettering sites for copper contaminants in SOI wafers is fundamentally difficult. Thus, a design of gettering for copper contaminants in SOI wafers has been a key engineering to improve device characteristics.

In this study, we investigated the effect of oxygen precipitates, produced by rapid-thermal annealing (RTA), on gettering efficiency of copper for SOI wafers after a dynamic-random-access-memory (DRAM) heat-treatment. To design a desirable distribution of oxygen precipitates for the gettering sites, the wafers were subjected to a RTA at 1150, 1175 and 1200 ºC for 10 s in an NH3 and Ar gas mixture. In addition, the substrate wafers were annealed at 800 ºC for 4 h in a nitrogen ambient to grow the oxygen precipitates and then followed at 1000 ºC for 16 h. Then, the bonded SOI wafers with proximity gettering sites and conventional SOI wafer were intentionally contaminated with copper of 1 × 1012 atoms/cm2 on the wafer surface, and then all SOI wafers were subjected to a typical DRAM heat-treatment. We correlated concentration of the oxygen precipitate with gettering efficiency of copper contaminants.

Figure. 1 shows the distribution of bulk micro defects (BMDs) in the substrate wafer with a different heat-treatment condition. It shows that the substrate wafer subjected to a RTA and two-step heat-treatment has the highest density of BMDs. A SOI wafer was conventionally fabricated and subjected to a DRAM heat-treatment after copper contamination intentionally. In this wafer, concentration of copper contaminants was measured via dynamic secondary ion mass spectroscopy (D-SIMS). As shown in Fig. 2, concentration of copper on top silicon, BOX layer and bulk silicon is high because there is no gettering site. In Fig. 3, a substrate wafer was subjected to a RTA at 1175 ºC for 10 s and then followed two-step heat-treatment. The concentration of copper contaminants was relatively lower than that of Fig 2. This means that coppers were well gathered at oxygen precipitates located at underneath buried oxide after DRAM heat-treatment, verifying an excellent gettering efficiency for copper contaminants. In our presentation, we will discuss the detailed gettering mechanism for copper contaminants in SOI wafers and report proximity gettering of copper via oxygen precipitates for SOI wafer.

* This work was financially supported by the Brain Korea 21 Plus Program in 2013 and SiWEDS (Silicon Wafer Engineering and Defect Science).

Reference

[1] S.M. Myers et al., J. Appl. Phys. 88 (2000) 3795

[2] Lixia Lin et al., Solid-State and Integrated Circuit Technology (2010) 1563