(Invited) Tunneling FET Device Technology for Ultra-Low Power Integrated Circuits
Authors: Takagi Shinichi , Kato Kimihiko , Ahn Dae-Hwan , Gotow Takahiro , Takaguchi Ryotaro , Bae Tae-Eon , Toprasertpong Kasidit , Takenaka Mitsuru 
Published: February 2020

A tunnel FET (TFET) [1-3] is regarded as one of the most promising steep slope devices, which are effective in reducing the power consumption of LSIs. Here, low Ioff and high ratio of Ion/Ioff are also needed for practical logic devices, in addition to low S.S. However, S.S. values of reported TFETs, averaged over a wide sub-threshold region, are still too high [3]. Also, Si-based TFETs are known to have difficulties in high Ion because of the low tunneling probability due to high and indirect bandgap. Thus, TFETs using Ge/III-V semiconductors and the type-II hetero-structures are expected to boost the TFET performance [1-3]. We are currently working for TFETs using the following material systems, (1) InGaAs TFET [4-9] (2) GaAsSb (source)/InGaAs (channel) TFET [10] (3) Ge TFET [11-13] (4) Ge (source)/strained Si (channel) TFET [4-6, 14] (5) (Si, Ge) (source)/oxide semiconductor (channel) TFET [15]. In this presentation, we address the critical issues of high performance TFETs and the device engineering to solve these issues. After that, we introduce the recent results of the TFETs using the above materials.

For InGaAs TFETs, we introduced solid-phase Zn diffusion from Zn-doped SOG films [4-7], in order to realize the source junction with steep impurity profiles. Also, we have proposed an ultrathin quantum well (QW) channel InGaAs TFET [6, 8, 9], where high Ion due to electron confinement into QW and low S.S due to suppression of the junction leakage current are expecxted. In addition, thin EOT and the low interface defect density are also critical to TFETs. We introduced ZrO2/InGaAs gate stacks [9]. However, TFETs without Al2O3 passivation exhibited higher Ioff, higher S.S. and lower Ion, bcause of the higher interface state density at ZrO2/InGaAs interfaces. Insertion of only 1-to-2-cycle Al2O3 can provide the optimal TFET performance. As a result, InGaAs QW TFETs with In0.75Ga0.25As and the ZrO2/Al2O3 gate stack shows the minimum S.S. of 50 mV/dec. at room temperature.

On the other hand, one of the ideal TFET structures to realize small S.S. and high Ion can be a bi-layer TFET with vertical tunneling [15]. The small S.S. is attributed to direct modulation of the DOS overlap between the source and the channel over the entire channel region by Vg. Also, high Ion is due to the large tunneling area and the short tunneling distance determined by the channel thickness. In addition, introduction of type-II hetero-structures into bi-layers is quite effective. Thus, we have proposed a novel bi-layer TFETs using a column IV semiconductor (Si, SiGe, Ge)/oxide semiconductor type-II hetero-structure. It has been found from the results of device simulation that extremely-steep minimum S.S. of 1~2 mV/dec. and high Ion of ~100 μA/μm at Vdd can be realized in comparison with the pn-junction-based Ge TFETs. We have experimentally demonstrated the Si/ZnO and Ge/ZnO TFET operation [15]. Here, ZnO films were deposited by PLD. It is confirmed that the ZnO channel layer with the columnar-shaped poly-crystalline structure with the grain size of ~20 nm and the TiN/Al2O3 gate stack [16] have the relatively smooth interfaces. The higher Ion is obtained for the Ge/ZnO TFETs. The minimum S.S. for the p-Si/n-ZnO TFET is 71 mV/dec, which is still higher than expected. Further improvements in the quality, the defect density and the thickness uniformity of oxide semiconductors are expected to provide superior electrical characteristics.

This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT. The authors would like to thank Drs. M. Yokoyama and T. Yamamoto in Sumitomo Chemical Corporation, and Dr. M. Mitsuhara in NTT for their collaborations.

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