bluuebunny/crossref_metadata_2025 huggingface dataset:
Monitoring of Polymer Removal Process for Copper Interconnect
Authors: Shalyt Eugene , Liang Guang , Wang Jingjing , Pavlov Michael , Dozortsev Vladimir , Bai Chuannan , Bratin Peter
Published: October 2013

Transition of interconnect technology to copper elevated challenges for polymer removal. Electrolyte has to provide efficient removal of organic material while preserving Cu surface with controlled regrowth of copper oxide. Spectroscopy in combination with electrochemical method can provide comprehensive characterization of electrolyte for concentration of major components (H2O2, H2O, organic, pH). In addition, local electrochemical analysis provides information on copper oxide removal/regrowth.
Non-Stiction Performance of Various Post Wet-Clean Drying Schemes on High-Aspect-Ratio Device Structures
Authors: Chen Han-Wen , Gouk Roman , Verhaverbeke Steven , Visser Robert J.
Published: October 2013

Line collapse or distortion of high-aspect-ratio nanostructures during drying step in wet process has been an issue in semiconductor industry due to feature size shrinkage following rapid technology advancement. In this work, three drying schemes, including drying with solvent vapor exposure, by sublimation, and following surface modification, were compared on 2x NAND STI structures. Acetone vapor assisted drying achieved non-stiction performance on high-aspect-ratio trenches with both 40nm and 20nm spacing. Sublimation and SAM formation only worked on the features with 40nm spacing. Further investigation to follow for failure mechanism study and stiction-free drying development.
Translation of Particles to Wafers during Spin Coating
Authors: Extrand C. W. , Moon Sung In , Monson Loxie
Published: October 2013

In this work, we developed a model to quantify the translation of particles from bulk liquid chemicals to the surface of wafers during spin coating. We tested the model by depositing dispersions of spherical particles of different concentrations onto spinning wafers, allowed the liquid to evaporate while spinning and then determined the areal density of spherical particles on the wafers. The model well described the experimental data.
Cryogenic Single-Component Micro-Nano Solid Nitrogen Particle Production Using Laval Nozzle for Physical Resist Removal-Cleaning Process
Authors: Ishimoto Jun , Oh U , Koike Tomoki , Ochiai Naoya
Published: October 2013

The innovative characteristics of the cryogenic single-component micro-nano solid nitrogen (SN2) particle production using super adiabatic Laval nozzle and its application to the physical resist removal-cleaning process are investigated by a new type of integrated measurement coupled computational technique. The originality to be noted in the present study is that the continuous production of micro-nano SN2 particle is achieved by using single component gas-liquid two-phase flow of subcooled nitrogen through a Laval nozzle (converging-diverging nozzle). As a result of present computation, it is found that high-speed ultra-fine SN2 particle is continuously generated due to the freezing of liquid nitrogen (LN2) droplet induced by rapid adiabatic expansion of subsonic subcooled two-phase subcooled nitrogen flow passing through the Laval nozzle. Furthermore, the effect of SN2 particle diameter, injection velocity, and attack angle to the wafer substrate on resist removal-cleaning performance is investigated in detail by integrated measurement coupled computational technique.
Selective Removal of Ashed Spin-On Glass (SOG)
Authors: Wu Hsing-Chen , Tu Sheng-Hung , Cooper E.
Published: October 2013

A wet etch/cleaning formulation with semi-aqueous composition was described here. The solution could remove the ashed SOG and its residues quickly (> 900A/min) in low process temperature and also showed compatibility for high-K/metal gate integration scheme including TiNx, TaNx, and work-function metals would contain aluminum
(Invited) A Novel Approach to Clean Surface for High Mobility Channel Materials with In Situ Atomic Hydrogen Clean
Authors: Park Jeongwon , Cruz Joe Griffith , Zheng Bo , Gelatos Jerry , Narasimhan Murali , Narwankar Pravin K
Published: October 2013

A number of non-silicon channel materials have been considered for advanced CMOS devices such as SiGe, Ge and GeSn (PMOS) as well as various III-V materials combinations including InGaAs and GaAs (NMOS). Surfaces cleaning process is critical to make a better interface contact in devices. This study demonstrates a method of surface cleaning on Ge/III-V channel using thermal atomic hydrogen source. This technique has several advantages over conventional wet, thermal, or plasma cleaning such as lower temperatures, no surface damage, less impurities, selective removal, and large area scalability. This will be a good candidate technology for the future non-Si CMOS technology beyond 10 nm node with scalability to 450 mm wafer size.
Selective Ni Removal Deposited on Ge at Different Annealing Temperatures
Authors: Otsuji Masayuki , Yoshida Y. , Takahashi H. , Snow J. , Sebaai F. , Mertens Paul W. , Sato M. , Shirakawa H. , Uchida H.
Published: October 2013

The effect of annealing temperature for selective Ni etching on NiGe was evaluated using various HCl mixtures. It was found that the best condition to achieve selectivity while maintaining good contact resistance was 0.37% HCl at 65ºC and 350ºC for the annealing temperature. To obtain favorable devices with NiGe electrode, the narrow process window for NiGe annealing and HCl concentration, temperature and process time were defined.
Quantitative Analysis of the Metallic Contamination On GaAs and InP Wafers by TXRF and ICPMS Techniques
Authors: Fontaine Hervé , Lardin Thierry
Published: October 2013

The quantitative analysis of the metallic contaminants both by chemical collection coupled to ICPMS and TXRF were implemented on GaAs and InP 100mm wafers. VPD-DC-ICPMS and LPD-ICPMS were developed respectively for GaAs and InP substrates. These methods present CE higher than 85% for usual metallic contaminants except for Cu & noble metals, and very sensitive detection thresholds are reached (108 to 1011 at/cm²). TXRF analysis conditions were optimized on both substrates. Na, Mg, Al, Ir and Ge on GaAs and K, Ca, Pd and Ag on InP are not analyzable due to substrate interferences. TXRF calibration was carried out from intentionally contaminated wafers in reference to ICPMS methods. Finally, TXRF enables to reach interesting detection limits (1010 to 1012 at/cm² range) and is able to measure Cu and some noble metals.
Effects of N-Rich TiN Capping Layer on Reliability in Gate-Last High-k/Metal Gate MOSFETs
Authors: Bae Kidan , Lee Kyung Taek , Sagong Hyun Chul , Choe Minhyeok , Lee Hyunwoo , Kim Sungeun , Kim Kwang-Soo , Park Junekyun , Pae Sangwoo , Park Jongwoo
Published: October 2013

Time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI) in gate-last technology are studied to characterize the gate-last HK/MG MOSFETs with enrichment of nitrogen inside HK/MG stack and its effects. Especially, to prevent Nitrogen-induced defect generation leading to extra NBTI degradation, it is needed that nitrogen should be mainly inside bulk HfO2 while interface layer (IL) is free from the effect of nitrogen. To explore this, N-rich TiN capping layer deposition and plasma nitridation (PN) approaches are introduced and compared.
High Temperature Annealing of the Interface State Component of Negative-Bias Temperature Instability (NBTI) in MOSFET Devices
Authors: Nguyen Duc , Kambour Kenneth , Kouhestani Camron , Hjalmarson Harold P. , Devine Roderick A.B.
Published: October 2013

We have performed negative bias instability (NBTI) measurements on 130 nm channel length Si MOSFETs with SiON gate dielectrics at different temperatures up to 220 °C. Using a pulsed stressiing and pseudo-DC measurements we have focused on the charging and annealing kinetics of only the interface state related component. At temperatures > 180 °C we find clear evidence for a diminution of the growth kinetics suggesting the onset of an annealing effect during interface state generation. We contrast the NBTI data with interface state growth in devices exposed to ionizing radiation. Possible physical mechanisms contributing to the “annealing” effect are discussed and associated with diffusing H2 molecules present in the substrate/gate insulator/polycrystalline Si gate structure.
(Invited) Multiphonon Processes as the Origin of Reliability Issues
Authors: Goes Wolfgang , Toledano-Luque Maria , Schanovsky Franz , Bina Markus , Baumgartner Oskar , Kaczer Ben , Grasser Tibor
Published: October 2013

Recently, correlated drain and gate current fluctuations have been observed in nano-scaled MOSFETs, indicating that their occurrence is linked to the same defect. One explanation for this observation can be given by the multi-state defect model, which has been developed to describe the hole capture and emission processes involved in the bias temperature instability (BTI). This model relies on a combination of metastable defect states and nonradiative multi-phonon transitions. Our detailed investigations demonstrate that the observed gate current fluctuations and their correlation with the drain noise can be well reproduced using a TAT mechanism based on the multi-state model.
Similarities between Ionizing Radiation Effects and Negative-Bias Temperature Instability (NBTI) in MOSFET Devices
Authors: Hjalmarson Harold P. , Nguyen Duc , Kambour Kenneth , Kouhestani Camron , Devine Roderick A.B.
Published: October 2013

The equivalent role of hydrogen cracking in radiation effects and Negative Bias Temperature Instability (NBTI) is described. A prediction concerning thickness dependence is compared with data. The temperature dependence of interface trap density is explained.
(Invited) SiC MOS Interface States: Difference between Si Face and C Face
Authors: Umeda Takahide , Okamoto Mitsuo , Kosugi Ryouji , Harada Shinsuke , Arai Ryo , Sato Yoshihiro , Makino Takahiro , Ohshima Takeshi
Published: October 2013

This paper discusses the differences between Si-face and C-face MOS interfaces in 4H-SiC MOSFETs. The two interfaces exhibit unique electrical characteristics, which will be linked with the differences in interface defects. We carried out an electrically detected magnetic resonance (EDMR) study on Si-face and C-face 4H-SiC MOSFETs, and found that there are different types and different amounts of interface defects on each interface. We discussed the EDMR results in comparison with the electrical characteristics of Si-face and C-face MOSFETs.
(Invited) Novel Graphene Devices
Authors: Corbet Chris M , Ramon Michael , Movva Hema CP , Reddy Dharmendar , Kang Sangwoo , Chowdhury Sk. Fahad , Akinwande Deji , Tutuc Emanuel , Register Frank , Banerjee Sanjay K
Published: October 2013

Graphene presents interesting opportunities but also faces unique challenges for applications in nanoelectronics. As a gapless semiconductor, with an inert surface that is difficult to grow high quality gate dielectrics on, or chemically dope, it can be challenging to make graphene field effect transistors (GFETs) with low leakage currents, low interface state densities, and low source/drain series resistance. However, the Dirac cone bandstructure with high a Fermi velocity enables high frequency GFETs with ambipolar characteristics which can be used, for instance, in simple frequency doublers. Beyond-CMOS low power device ideas include single particle 2D-2D interlayer tunnel FETs (ITFETs), or more esoteric many-body tunneling devices such as the Bilayer Pseudospin FET (BiSFET).
Oxidation Models for Crystalline Silicon Nanowires
Authors: Mertens Robert George , Velez Victor H. , Sundaram Kalpathy B
Published: October 2013

Mathematical techniques for calculating the thickness of a grown oxide layer on Silicon nanowires (SiNWs) are described here. Problems of this nature are considered to be “Stefan,” or “moving boundary” problems. This is a diffusion problem, but it is primarily the diffusion of oxygen through a solid, silicon dioxide (SiO2), with an interior moving boundary (Si converts to SiO2 as oxygen diffuses up to the boundary and combine with Si) and a growing exterior surface (SiO2 surface expands as the interior absorbs oxygen atoms).
(Invited) III-V Nanowires for Optoelectronic Applications
Authors: Tan Hoe , Jiang N. , Saxena D. , Lee Y. H. , Mokkapati S. , Fu L. , Gao Q. , Joyce H. J. , Jagadish Chennupati
Published: October 2013

We present an overview of our work on improving the crystal quality and carrier lifetimes of our GaAs-based nanowires. These two properties are crucial for optoelectronic device applications and which we report by showing two examples of nanowire lasers and nanowire solar cells.
(Invited) How to Dope a Semiconductor Nanocrystal
Authors: Amit Yorai , Fasut Adam , Milo Oded , Rabani Eran , Frenkel Anatoly , Banin Uri
Published: October 2013

The doping of colloidal semiconductor nanocrystals (NCs) presents an additional knob beyond size and shape for controlling the electronic properties. An important problem for impurity doping is associated with resolving the location and structural surrounding of the dopant within the small NCs, in light of tendency for driving of the impurity atom to the surface of the NC. A post-synthesis diffusion-based doping approach for introducing metal impurities into InAs NCs is described and characterized. This enables accurate correlation between the emerged electronic properties and the doping process. Optical absorption spectroscopy and scanning tunneling spectroscopy (STS) measurements revealed the n-type and p-type behavior of the doped NCs, depending on the identity of selected impurities. X-ray absorption fine structure (XAFS) spectroscopy measurements demonstrated the interstitial location of Cu within the InAs NCs, acting as an n-type dopant, which was found to occupy a single unique hexagonal interstitial site within the NC lattice for a wide range of doping levels.
(Invited) Resistive Switching in Metal Oxides: From Physical Modeling to Device Scaling
Authors: Ielmini Daniele , Ambrogio Stefano , Balatti Simone
Published: October 2013

Resistive switching memory (RRAM) devices are receiving considerable interest as future-generation high-density storage technology or possible enablers of storage class memory. For these applications, there is a strong push toward scaling, in terms of low current operation, low power consumption and small device area. To assess the scaling potential of RRAM, however, the physical mechanisms for switching and reliability issues, such as noise, must be understood in deep detail. This work reviews the current understanding of RRAM switching in terms of ion diffusion and migration mechanisms. The model is used to inspire new RRAM operation schemes, such as complementary switching (CS) which may allow self-select memory crossbar and novel multilevel storage approaches. The scaling dependence of random telegraph noise (RTN) is finally discussed based on numerical simulations of drift-diffusion transport and Poisson equation within the conductive filament.
(Invited) Theoretical Design of Desirable Stack Structure for Resistive Random Access Memories
Authors: Kamiya Katsumasa , Yang Moon Young , Magyari-Köpe Blanka , Niwa Masaaki , Nishi Yoshio , Shiraishi Kenji
Published: October 2013

We show the electronic roles in vacancy-filamentary-type switching of binary oxide-based resistive random access memories using ab initio modeling. We show that charge injection and removal determine the thermodynamic stability of the filament and the diffusion in the devices. The vacancy cohesion-isolation phase transition upon charge injection and removal is thus one of the main factors that govern resistive switching. Based on the physics, we propose desirable three-layer stack structures for further improvement of the memory characteristics, where spatial differences in the oxygen chemical potential in the device cell lead to an asymmetrical vacancy filament shape that can be used to improve the memory characteristics, such as ON/OFF ratio.
(Invited) Fundamentals in MoS2 Transistors: Dielectric, Scaling and Metal Contacts
Authors: Liu Han , Neal Adam T , Du Yuchen , Ye Peide D
Published: October 2013

The rise of two-dimensional (2D) crystals has given new challenges and opportunities to the device research. The semiconducting MoS2 has been considered as a promising ultrathin body channel for future microelectronic and optoelectronic devices. In this paper, we focus on the fundamental device properties in MoS2 transistors. In the first part we introduce the dielectric integration on MoS2 and other 2D crystals by atomic layer deposition, revealing the similarities and differences of dielectric integration on bulk and 2D crystals. Then we discuss scaling of channel length and width of MoS2 transistors. We also present the different metal contacts on MoS2, showing Fermi level pinning at metal/2D interfaces. Finally we demonstrate a statistical study on CVD based single layer MoS2 transistors, therefore to show potentials and limitations on these 2D crystals in device applications.
(Invited) Structural and Chemical Stabilization of the Epitaxial Silicene
Authors: Molle Alessandro , Chiappe Daniele , Cinquanta Eugenio , Grazianetti Carlo , Fanciulli Marco , Scalise Emilio , van den Broek Bas , Houssa Michel
Published: October 2013

The silicon counterpart of graphene, the so called “silicene”, has been so far a fascinating theoretical hypothesis, but only recent efforts have pushed it to concrete evidence thus triggering a tremendous interest in silicene for electronic applications and fundamental investigations. Indeed, in addition to graphene, silicene is expected to provide an intimate affinity with the Sibased technology but, unlike graphene, the silicene appears as a buckled lattice where various superstructures take place depending on the periodic distribution of buckled bonds. Here we elucidate the atomistic details of the 4x4 and √13 × √13 silicene superstructures epitaxially grown on Ag(111) substrates. These silicene layers have been successfully encapsulated with Al2O3 in order to access ex situ Raman spectroscopy. The Raman spectrum of the encapsulated silicene has been self-consistently interpreted upon comparison with ab initio calculated spectra. In addition to the presence of the double degenerate E2g mode, typical for honeycomb lattices, the non-uniform bond length and the nonsymmetric buckling in the silicene layer introduce an intrinsic disorder which gives rise to disorder activated Raman extra-peaks.
(Invited) Pseudopotential-Based Study of Electron Transport in Low-Dimensionality Nanostructures
Authors: Fischetti Massimo V , Aboud Shela J , Ong Zhun-Yong , Kim Jiseok , Narayanan Sudarshan , Sachs Catherine E
Published: October 2013

We argue that intrinsically low-dimensionality materials may be needed to scale VLSI devices beyond 10 nm. We present examples of the use of empirical pseudopotentials to study the electronic structure and transport materials such as thin semiconductor bodies used in scaled VLSI devices, graphene, and nanoribbons.
Engineering of the Interface between Silicon and Rare-Earth-Oxide Buffer for GaN Growth
Authors: Dargis Rytis , Clark Andrew , Arkun F. E. , Smith Robin
Published: October 2013

Epitaxial multilayer heterostructures based on rare earth oxides serve as stress mitigating buffers for the growth of GaN on a Si (111) substrate. The process for the formation a uniform amorphous silicon dioxide layer between a silicon substrate and single crystal rare-earth oxide is described. The amorphous silicon dioxide interlayer is formed between the gadolinium oxide and the silicon substrate for additional relief of thermal expansion and lattice mismatch induced stress because of its reduced viscosity at temperatures typical for rare earth oxides and gallium nitride growth.
Development of an All-Wet-Etch Process Chemistry for the Patterning of Metal Conductors in Igzo Thin-Film-Transistors
Authors: Leschkies Kurtis , Verhaverbeke Steven , Yim D. K. , Hsu H. C. , Kim H. , Lim R. , White J. M. , Visser Robert J.
Published: October 2013

Here, we discuss the development of an all-wet back-channel etch process chemistry with high metal selectivity that is capable of shaping the structures of an IGZO TFT to customer specifications. Our approach involves a two-step etching process that first selectively removes only the metal conductor (Cu) while temporarily stopping at the underlying metal adhesion layer (Mo or Ti). The chemistry then selectively removes the metal adhesion layer with minimal impact to the IGZO semiconductor. By pursuing a two-step approach, where each chemistry is designed to target a specific metal with high selectivity, the risk of excessive metal undercutting generally associated with wet-etch techniques can be mitigated. Furthermore, those issues associated with a dry-etch (i.e., degraded electron mobility and high threshold voltages due to structural damage to the semiconductor active layer) can be avoided.
Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region Due to Edge Fringing Field Effect
Authors: Lu Han-Wei , Hwu Jenn-Gwo
Published: October 2013

Interesting area and perimeter dependency mechanisms of dark gate current in Al/SiO2/p-Si capacitor is demonstrated. To study this lateral non-uniformity phenomenon, three different thicknesses of top aluminum gate are intentionally designed to our capacitors. According to C-V and I-V measurements carried out in the dark, it is found that the device with thin top Al-gate will result in entirely different electrical characteristics compared with the device with thick top Al-gate. Moreover, measurements with light illumination show that there is enhanced edge charge collection efficiency in inversion due to edge fringing field effect.
Extremely Large Refractive Indexes in Anodic Tantalum Pentoxide
Authors: Kulpa Alina , Jaeger Nicolas A. F.
Published: October 2013

We have investigated optical properties of tantalum pentoxide films obtained by anodization of thin tantalum layers that were deposited on BK7 glass in an e-beam system. Ellipsometric studies were conducted in the wavelength range 246nm to 1679nm. The ellipsometric complex reflection coefficient versus λ was optimized using the same routine for all samples and provided values of n, k, and α. Some extreme n (up to 1000) and large n (up to 23) and α values were obtained for some samples in the wavelength range 455nm to 531nm. These extreme values probably result from small polycrystalline clusters dispersed in amorphous tantalum pentoxide. Such clusters usually are not charge neutral; therefore, they can interact with electric fields, such as incident light. As for the large n values these are probably resulting from possible presence of some impurity molecules.
(Invited) Physical and Electrical Properties of Scaled Gate Stacks on Si/Passivated In0.53Ga0.47As
Authors: Marchiori Chiara , El Kazzi M. , Czornomaz L. , Pierucci D. , Silly M. , Sirotti F. , Abel S. , Uccelli E. , Sousa M. , Fompeyrine J.
Published: October 2013

In0.53Ga0.47As based capacitors and self-aligned transistors fabricated with HfO2/Al2O3/Si gate stacks in a gate-first process flow show promising electrical properties. With in-situ and ex-situ characterization methods, we review systematically the physical and chemical properties of the whole multilayered stack. Especially, critical instabilities which may potentially limit the achievement of sub-nanometer capacitance equivalent thickness and a low interface state density are described in detail. Finally we propose some alternative solutions to avoid the observed instability paths.
Electrical Properties and Charge Transport in the Pd/Al2O3/InGaAs MOS Structure
Authors: Gomeniuk Y. Y. , Gomeniuk Y. V. , Nazarov A. N. , Monaghan S. , Cherkaoui K. , O'Connor É. , Povey I. , Djara V. , Hurley P. K.
Published: October 2013

The paper presents the results of a study focused on electrical properties and determination of transport mechanism through dielectric layer in Pd/Al2O3/In0.53Ga0.47As/InP MOS system. We found the current to be governed by Fowler-Nordheim tunneling in case of electron injection from the metal electrode for all dielectric thicknesses and of injection from the semiconductor for 10 nm Al2O3 thickness. The potential barrier for electrons at the metal-dielectric interface equals to 2.40±0.10 eV. The conduction band offset at the dielectric-semiconductor interface equals to 2.50±0.06 eV. The optimal value for Al2O3 oxide thickness among the MOS structures under study is proposed to be 10 nm. Increase of the Al2O3 thickness results in increase of fixed positive charge in the dielectric and probably extension of transition layer between the dielectric and semiconductor.
Electrical Characterization of Atomic Layer Deposited La2O3 Films on In0.53Ga0.47As Substrates
Authors: Oomine Hiroshi , Zadeh Dariush Hassan , Kakushima Kuniyuki , Kataoka Yoshinori , Nishiyama Akira , Sugii Nobuyuki , Wakabayashi Hitoshi , Tsutsui Kazuo , Natori Kenji , Iwai Hiroshi
Published: October 2013

The effect of La2O3 atomic-layer-deposition (ALD) conditions by La(iPrCp)3 and H2O, on the electrical properties of metal/La2O3/In0.53Ga0.47As MOS capacitor has been investigated. We found that the low growth temperature can effectively improve the La2O3/In0.53Ga0.47As interface properties and gate leakage current. It is shown that by controlling the growth temperature of ALD, near ideal capacitance-voltage (C-V) characteristics with low interface state density (Dit) values (~8 x 1011 eV-1cm-2) can be obtained.
Investigation of the Current Stability of AlGaN/GaN High Electron Mobility Transistors in Various Liquid/Solid Interface on the Gate Area
Authors: Fang Jung-Ying , Hsu Chen-Pin , Kang Yen-Wen , Fang Kuan Chung , Ren Fan , Wang Yu-Lin
Published: October 2013

Variation of temperature, pressure, and pH values has been demonstrated for affecting the stability of AlGaN/GaN HEMTs sensors. In addition to the factors above mentioned, we found out other factors which are related to the stability of AlGaN/GaN HEMTs sensors. In this study, we found out the current variation of AlGaN/GaN HEMTs without gate metal sensors is inversely proportional to the viscosity of liquids. We also found out that dipole moment of liquids is related to the current variation of AlGaN/GaN HEMTs without gate metal sensors.
Nonpolar Light-Emitting Diodes Using Hydrothermally Grown a-Plane ZnO
Authors: Kim Hyonwoong , Baik Kwang Hyeon , Jang Soohwan
Published: October 2013

High quality a-plane (11-20) ZnO film has been successfully grown on a-plane GaN template by facile, low-cost, seed-layer-free hydrothermal solution method at low temperature. The surface of ZnO film consists of m-plane (1-100), which has the slowest growth rate and stable surface energy. Crystalline structure and morphology of a-plane ZnO were analyzed with XRD, TEM, SEM, and AFM. Furthermore, nonpolar a-plane n-ZnO/p-GaN light emitting diodes which showed sharp near-UV emissions at the low voltage of 3.5 V were fabricated.
Improved Passivation Techniques for AlGaN/GaN Hemts
Authors: Anderson Travis J , Koehler Andrew D , Tadjer Marko J , Hobart Karl D , Nepal Neeraj , Feygelson Tatyana I , Pate Bradford B , Eddy Charles R. , Kub Fritz J
Published: October 2013

AlGaN/GaN power high electron mobility transistor (HEMT) performance is limited by current collapse and off-state gate and drain leakage current. A series of studies to improve these properties through optimized surface cleaning, as well as the implementation of novel materials, such as AlN and nanocrystalline diamond, is presented. Reduced leakage currents, degradation of dynamic ON-resistance, and current collapse ratio quantify improvement in HEMT performance. DC I-V measurements, pulsed I-V measurements, and a boost converter test circuit is used to validate these properties.
Lattice-Mismatched Epitaxial Growth On Porous III-V Substrates
Authors: Grym Jan , Gladkov Petar , Vanis Jan , Hulicius Eduard , Pangrac Jiri , Pacherova Oliva , Dimitrakopulos George , Bazioti Calliope , Komninou Philomela
Published: October 2013

We report on the electrochemical preparation of GaAs porous substrates, their heat treatment in As rich environment and their overgrowth by metalorganic vapor phase epitaxy (MOVPE). The goal is to demonstrate that porous substrates are capable of accommodating strain at the interface with lattice mismatched In(x)Ga(1-x)As layers.
Printable Nanomaterials for Flexible Electronics
Authors: Takei Kuniharu
Published: October 2013

Printed electronics of inorganic nanomaterials are presented as macroscale flexible devices such as artificial electronic skin, high performance transistors, and biologically inspired devices. This talk was especially focused on active components consisted of printed nanomaterials for transistors and sensors on flexible substrates. The nanomaterials were uniformly patterned over the macroscale arbitrary substrates of polymer, plastic and silicon. Inorganic semiconductor materials used mainly here allow to achieve air-stable high performance devices. The flexible devices show impressively high mechanical robustness, high mobility, high radio frequency for wireless applications, and high sensitivity of sensors. By using the printable nanomaterials, heterogeneously integrated artificial electronic skin and whiskers were also demonstrated as proof of concept.
FDSOI Technology: A Power Efficient Solution Down to 10nm
Authors: Faynot Oliver , Vinet M. , Fenouillet C. , Weber O. , Perreau P. , Grenouillet L. , Andrieu F. , Poiroux T. , Deleonibus S.
Published: October 2013

This paper reports the technological details and the performance of the planar Fully Depleted SOI technology. Thanks to its intrinsic structure (SOI substrates, undoped channel, ultra-thin body and box thicknesses), FDSOI devices offer significant advantages over Bulk devices: better electrostatic control, better matching performance, improved drivability and better power efficiency. After the demonstration of a complete 28nm platform, scaling down to 14 and 10nm is highlighted in this paper.
(Invited) Mn5Ge3C0.8 Contacts for Spin Injection Into Ge
Authors: Fischer Inga Anita , Sürgers Christoph , Petit Matthieu , Le Thanh Vinh , Schulze Joerg
Published: October 2013

We investigate the properties of Mn5Ge3C0.8 contacts on Ge (100) and (111) with varying doping type and doping concentrations with the aim of fabricating low-resistance contacts. Specific contact resistivities on Ge (100) are very high in all cases. The lowest specific contact resistivity (1.25·10-4 Ω·cm2) was obtained for Mn5Ge3C0.8 contacts on n++-Ge (111) with N
D = 1∙1020 cm-3. We discuss means to further reduce specific contact resistivities.
(Invited) Development of Multifunctional Liner/Barrier Systems for Sub-14nm Metallization
Authors: Eisenbraun Eric
Published: October 2013

Mixed phase materials composed of refractory metal-based pairs such as Ru/TaN and Ru/WCN, grown by plasma enhanced atomic layer deposition (PEALD), can perform as directly platable Cu diffusion barriers which can be scaled to thicknesses of ~2-3nm. While such direct plate liners employ conventional barrier materials such as TaN and WCN, direct plate liner extendibility may be enhanced by employing a barrier metal with a lower intrinsic resistivity without the presence of carbide or nitride phases that are effective at preventing the diffusion of Cu. In considering suitable materials for this application, both the ability to support copper electrodeposition as well as good intrinsic copper and oxygen diffusion barrier performance are critical characteristics. Accordingly, dopant metals such as Co are selected as materials to investigate for replacement of conventional barrier materials in direct plate barriers by combining with Ru to form RuCo mixtures.
ALD W CMP for HKMG
Authors: Yang Tao , Wang Guilei , Xu Qiang , Lu Yihong , Yu Jiahan , Cui Hushan , Yan Jiang , Li Junfeng , Zhao Chao
Published: October 2013

ALD W CMP characteristic are examined for SiH4 and B2H6 base respectively. ALD W removal rate of B2H6 base is higher than that of SiH4 base. Potentiodynamic polarization scans results indicate that the amorphous structure of the B2H6 base has a higher tendency to be corroded than the polycrystalline structure of the SiH4 base in the W CMP slurry with 2 wt% H2O2. RMS of ALD W after CMP are all less than 1nm for SiH4 and B2H6 base.
(Invited) Si/SiGe Resonant Interband Tunnel Diodes Grown by Large-Area Chemical Vapor Deposition
Authors: Berger Paul , Ramesh Anisha , Loo Roger
Published: October 2013

Si/SiGe resonant interband tunnel diodes were successfully technology transferred from low-temperature molecular beam epitaxial growth to chemical vapor deposition (CVD) on 200-mm diameter p-doped silicon wafers in a production style reactor. The resonant interband tunnel diode structure consists of a p+-i-n+ diode that incorporates vapor phase doped δ-doping to enhance quantum mechanical confinement and tunneling probability. The tunneling barrier thickness was varied from 2 nm to 8 nm and a record high peak-to-valley current ratio of 5.2 for a CVD process is reported for a 6 nm barrier thickness. The CVD reactor is an active integral tool within a 200mm full CMOS process line and is suggestive that Si/SiGe RITDs could be seamlessly integrated into a full hybrid CMOS process flow.
(Invited) Wide Bandgap Heterojunctions on Crystalline Silicon
Authors: Sturm James , Avasthi Sushobhan , Nagamatsu Ken , Jhaveri Janam , McClain William E. , Man Gabriel , Kahn Antoine , Schwartz Jeffrey , Wagner Sigurd
Published: October 2013

We describe the use of organic and metal oxide semiconductors to form wide-bandgap heterojunctions to crystalline silicon. We use these semiconductors to demonstrate a heterojunction which both blocks electrons and passes holes, and a complementary heterojunction which blocks holes and passes electrons and blocks holes. The carrier transport functions are demonstrated through simple device structures as well as a photovoltaic application. In both cases, the ability to deposit layers at low-temperature (< 100 oC) is attractive for low-cost applications. The ability of organic molecules to passivate silicon surface states is also presented.
(Invited) Bio-MEMS Chip for Bacteria Detection -A Challenge of Si Technology to Biomedical Field-
Authors: Ishii Hiromu , Sawada Kazuaki , Ishida Makoto , Machida Katsuyuki , Iida Ken-Ichiro , Saito Mitsumasa , Yoshida Shin-ichi
Published: October 2013

This work describes a Bio-MEMS chip with Si-pillar structure for trapping a bacterium Legionella
pneumophila (L. pneumophila) and subsequently for making a bacteria sensor. Applying MEMS technology made a microfluidic chip having Si pillars. They operated as a sieve for trapping L. pneumophila cells injected into the microfluidic chip. Observation of fluorescence produced by the trapped L. pneumophila confirmed their capture in the Si-pillar structure. Spectroscopic analyses of the fluorescence found to have a broad peak at around 450 nm. The peak intensity was proportional to the square root of concentration for L. pneumophila cells injected into the microfluidic chip. This quantitative relationship indicates that a bacterial sensor that has Si pillar structure as a bacterial trap can be realized by using Si technology.
(Invited) Performance Enhancement Technologies in III-V/Ge MOSFETs
Authors: Takagi Shinichi , Zhang Rui , Kim Sang-Hyeon , Yokoyama Masafumi , Takenaka Mitsuru
Published: October 2013

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/ integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for enhancing the MOSFET performance with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. By using these HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated with high electron (690 cm2/Vs) and hole (550 cm2/Vs) mobility. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm By utilizing this channel engineering, 55 nm-Lch quantum well channel InAs-OI n-MOSFETs have been demonstrated with superior short channel effect immunity and fairly high on current.
(Invited) Heteroepitaxial Growth of Sn-Related Group-IV Materials on Si Platform for Microelectronic and Optoelectronic Applications: Challenges and Opportunities
Authors: Nakatsuka Osamu , Taoka Noriyuki , Asano Takanori , Yamaha Takashi , Kurosawa Masashi , Sakashita Mitsuo , Zaima Shigeaki
Published: October 2013

We have examined the heteroepitaxial growth of Ge1-xSnx and Ge1-x-ySixSny layers and investigated the crystalline and electrical properties of these Sn-related group-IV material thin films. We achieved the epitaxial growth of Ge1-xSnx on Ge(110) with suppressing the formation of twin defects. Ge1-x-ySixSny layers on Ge substrates show high thermal robustness without Sn precipitation even after annealing at 600°C. We also found that the incorporation of 0.1%-Sn and H2-annealing are effective to reduce the unintentional generation of holes due to the vacancy defects.
(Invited) Development of Metal Source/Drain Ge-CMOS Using TiN/Ge and HfGe/Ge Contacts
Authors: Nakashima Hiroshi , Yamamoto Keisuke , Wang Dong
Published: October 2013

Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS devices, it is desirable that the source/drain (S/D) junctions are composed by metal/Ge contacts. However, the Fermi-level pinning impedes the embodiments, by which the contact formation showing a low electron barrier height (ΦBN) is very difficult. We have found TiN on Ge is superior as a low ΦBN contact. In this paper, we present the detailed fabrication and the electrical performance of a TiN/Ge contact. Furthermore, we present the excellence of a HfGe/Ge contact showing a low hole barrier height (ΦBP). Finally, we present the fabrication and device performance of metal S/D n- and p-MOSFETs using TiN/Ge and HfGe/Ge contacts, respectively.
Characterization of Local Strain Structures in Heteroepitaxial Ge1−x
Sn
x
/Ge Microstructures by Using Microdiffraction Method
Authors: Ike Shinichi , Moriyama Yoshihiko , Kurosawa Masashi , Taoka Noriyuki , Nakatsuka Osamu , Imai Yasuhiko , Kimura Shigeru , Tezuka Tsutomu , Zaima Shigeaki
Published: October 2013

In this study, we have examined the local growth of Ge1
−

x
Sn
x
heteroepitaxial layers on micrometer-scale-patterned Ge substrates with molecular beam epitaxy method. We have investigated the strain relaxation behavior and microscopic local strain structure in both Ge and Ge1
−

x
Sn
x
by using x-ray microdiffraction and finite element method calculation. We found that the anisotropic strain relaxation of embedded Ge1
−

x
Sn
x
layers preferentially occurs along the direction which is perpendicular to the stripe line. Microdiffraction method revealed that the elastic strain relaxation of the embedded Ge1
−

x
Sn
x
layer occurs near the edge region. We demonstrated that the uniaxial compressive strain of 0.2% is locally induced in Ge with Ge1
−

x
Sn
x
stressors.
(Invited) Group-IV Semiconductor Quantum Heterointegration by Low-Energy Plasma CVD Processing
Authors: Sakuraba Masao , Murota Junichi
Published: October 2013

Low-energy plasma CVD processing is expected to be effective in application of high-performance group-IV semiconductor heterodevices under suppression of dislocation generation and intermixing, i.e. group IV semiconductor quantum heterointegration on Si large scale integrated circuits. Recent progress in (A) development of room-temperature resonanttunneling diode using group-IV semiconductors and (B) lowenergy plasma CVD processing for group-IV semiconductor quantum heterointegration are reviewed.
Formation and Characterization of Strained Si1-XGex Films Epitaxially Grown on Si(100) by Low-Energy ECR Ar Plasma CVD without Substrate Heating
Authors: Ueno Naofumi , Sakuraba Masao , Murota Junichi , Sato Shigeo
Published: October 2013

For quantum-effect nano heterostructures of group IV semiconductors, formation and characterization of Si1-xGex films epitaxially grown on Si(100) by using low-energy electron-cyclotron-resonance (ECR) Ar plasma chemical vapor deposition (CVD) without substrate heating were investigated. Epitaxial Si0.50Ge0.50 films with smooth surface can be obtained on Si(100), where the thickness is almost proportional to deposition time and an incubation period is scarcely observed. For a 12 nm-thick epitaxial Si0.50Ge0.50 film on Si(100), its lattice constant in the direction perpendicular to the interface shows that the lattice is highly strained compared to a case of strain-relaxed Si0.50Ge0.50. This indicates that our ECR plasma CVD process has a potential to achieve highly strained heterostructures with suppressed strain relaxation and thermal interdiffusion at the heterointerface which are necessary for quantum-effect devices.
(Invited) Low-Temperature Metal-Induced Crystallization of Orientation-Controlled SiGe on Insulator for Flexible Electronics
Authors: Sadoh Taizoh , Park Jong-Hyeok , Kurosawa Masashi , Miyao Masanobu
Published: October 2013

Low-temperature (≤250oC) formation of orientation-controlled large-grain (>10 μm) poly-SiGe on amorphous insulator is essential to realize flexible electronics. In line with this, metal-induced crystallization of SiGe is investigated. By employing Au and Sn as catalysts, SiGe crystallization at 250oC and 150oC, respectively, becomes possible. Moreover, a technique for formation of orientation-controlled large-grain crystals is examined by modulation of nucleation in gold-induced crystallization. This achieves selectively (100)- or (111)-oriented large-grain (≥20 μm) crystals on amorphous insulators. This technique is expected to facilitate integration of advanced functional devices onto flexible substrates.
(Invited) Study on Charge Storage and Optical Response of Hybrid Nanodots Floating Gate MOS Devices for Their Optoelectronic Application
Authors: Miyazaki Seiichi , Ikeda Mitsuhisa , Makihara Katsunori
Published: October 2013

We have designed and fabricated hybrid nanodots structures, in which Si quantum dots (QDs) and either Ni-silicide or Pt-silicide nanodots (NDs) are stacked with ultrathin SiO2 interlayer, as a novel functional floating gate (FG) to satisfy both multiple valued capability and large capacity on charge storage. Multiple-step charge injection to sililcide NDs through discrete energy states in Si-QDs and stable storage of many charges in deep potential wells in silicide NDs have been confirmed from electrical characteristics of MOS capacitors and transistors measured at room temperature. A unique optical response of the hybrid NDs FG to near-infrared light irradiation, which is caused by the transfer of photo-excited electrons from silicide NDs to Si-QDs, has also been demonstrated.
Source and Drain Contact Module for FDSOI MOSFETs : Silicidation and Strain Engineering
Authors: Carron Veronique , Nemouchi Fabrice , Hartmann Jean-Michel , Cooper David , Damlencourt Jean-Francois , Bernasconi Sophie , Favier Sylvie , Morand Yves
Published: October 2013

Strained SiGe and SiC sources and drains are planned to be used in sub-28nm FDSOI devices in order to improve the carriers mobility. Consequently, silicide-induced relaxation of strained epitaxial layers is a key issue to address in order to fully benefit from the desired effects of strain engineering techniques. This paper deal with the impact of the silicidation process conditions on the strain of Si1-xGex:B layers (x=0.3 and 0.45) and SiC:P with [C]≤1,5%. We show that the strain of epitaxial layers is not affected by the silicidation in the case of Si0.7Ge0.3 and SiC, while a strong degradation of strain occurs with Si0.55Ge0.45. The strain evolution in the channel of a device at various stages of the silicidation process has been followed using dark field electron holography. We show that process parameters can be tuned in order to minimize the reduction of strain induced by the silicidation
Liquid-Solid Coexisting Annealing of a-GeSn/Si(100) Structure for Low Temperature Epitaxial Growth of SiGe
Authors: Chikita Hironori , Matsumura Ryo , Sadoh Taizoh , Miyao Masanobu
Published: October 2013

To develop a new low-temperature crystallization technique, annealing characteristics of a-GeSn/Si(100) structures are investigated. It is revealed that epitaxial growth accompanying Si-Ge mixing is generated at temperatures in the liquid-solid coexisting region of the Ge-Sn system. The annealing temperature necessary for epitaxial growth is significantly decreased by increasing annealing time and/or Sn concentration. Consequently, epitaxial growth at 300°C becomes possible. These findings are expected to be useful to realize next-generation large-scale integrated circuits, where various multi-functional devices are integrated.
(Invited) Characterization of Oxide Traps Participating in Random Telegraph Noise Using Charging History Effects in Nano-Scaled MOSFETs
Authors: Tsuchiya Toshiaki , Tamura Naoyoshi , Sakakidani Akihito , Sonoda Kenichiro , Kamei Masayuki , Yamakawa Shinya , Kuwabara Sumio
Published: October 2013

We propose a novel method for characterizing the oxide traps that participate in random telegraph noise (RTN) by using charging history effects on the traps. In this method, the variation in the frequency of the high/low drain current derived from RTN with the charging history is monitored instead of the time-scale parameters that are usually used. Moreover, we also propose a method to determine the number and charging conditions of the traps. These methods are particularly effective for characterizing individual oxide traps in multi-trap RTN.
Diaphragm Durability Enhancement for Valves Supplying Gas for Atomic Layer Deposition
Authors: Yamaji Michio , Tanikawa Tsuyoshi , Yakushijin Tadayuki , Funakoshi Takashi , Yamashita Satoru , Hidaka Atsushi , Nagase Masaaki , Ikeda Nobukazu , Sugawa Shigetoshi , Ohmi Tadahiro
Published: October 2013

Semiconductor devices are manufactured from Silicon wafers via diverse processes and application-specific equipment that requires supply of various gases. The gas supply system consists of pressure regulators, pressure gauges, filters, flow controllers, valves, fittings etc. The valves in this system are important parts for controlling and stopping the flow of gases. A wide variety of valves are used throughout the industrial world, but those used for semiconductor manufacturing require special features such as external leak-free, particle-free and dead space-free, because the extremely fine patterns formed on the high grade wafers are made with ultrapure process gases. In addition to these features, the valves must be durable enough to operate several tens of millions of cycles because of faster processing requirements with ALD applications. This research work was done to develop a highly durable diaphragm valve and to verify its durability performance via stress analysis.
Microstructure Analysis of ALD Bi2Te3/Sb2Te3 Thermoelectric Nanolaminates
Authors: Nminibapiel David , Zhang Kai , Tangirala Madhavi , Baumgart Helmut , Chakravadhanula Venkata S , Kübel Christian , Kochergin Vladimir
Published: October 2013

The fabrication of thermoelectric nanolaminate structures of alternating Bi2Te3 and Sb2Te3 ALD layers for thermoelectric application is reported. Trimethylsilyl telluride ((Me3Si)2Te), bismuth trichloride (BiCl3) and antimony trichloride (SbCl3) were utilized as chemical ALD precursors for tellurium, bismuth and antimony, respectively. The results of field emission scanning electron microscopy (FE-SEM) indicate that both metal tellurides exhibit the prevalent Volmer-Weber island growth mechanism with characteristic hexagonal crystallites. High resolution TEM X-section analysis reveals localized epitaxial growth of alternating ALD Bi2Te3 and Sb2Te3 layers within the large islands.