bluuebunny/crossref_metadata_2025 huggingface dataset:
Thermal Challenges Due to Improved RF Performance
Authors: Parikh Mitesh , Montan˜ez Roberto , Loney Patrick
Published: January 2011

Transmit/Receive (T/R) modules are the heart of many Active Electroncially Scanned Antennas (AESA). AESA’s enable a great deal of modern radar technology used on many military platforms. In the case study presented, a radar design necessitated the modification of an existing T/R module to increase the output power by 3dB. The RF design of the module demonstrated that a 3× increase of input power would be needed to achieve the desired performance. Increasing the input power creates extra power dissipated on the chips within the module, in the form of heat, resulting in significant thermal challenges. Chip junction temperatures directly affect the performance and reliability of the T/R Module. That is why thermal management of the module became the driving engineering concern. In this project, significant redesign of the T/R module was not possible due to the cost and schedule implications for this program. Therefore multiple engineering techniques were used to adequately cool all portions of the T/R module. These included refined RF modeling of the module to determine operating duty cycles, a re-designed coldplate to better remove heat, a modification of the power supply to lower the T/R module overhead voltage, and a re-designed Power Amplifier/Low Noise Attenuator (PA/LNA) on the module. The end result was a T/R module, with only one of five chips redesigned, which met desired output power, and demonstrated a positive temperature margin on all module components. All of this was accomplished within an acceptable cost and schedule budget.
Improved Phonon Transport Modeling Using Boltzmann Transport Equation With Anisotropic Relaxation Times
Authors: Ni Chunjian , Murthy Jayathi Y.
Published: January 2011

A sub-micron thermal transport model based on the phonon Boltzmann transport equation (BTE) is developed using anisotropic relaxation times. A previously-published model, the full-scattering model, developed by Wang, directly computes three-phonon scattering interactions by enforcing energy and momentum conservation. However, it is computationally very expensive because it requires the evaluation of millions of scattering interactions during the iterative numerical solution procedure. The anisotropic relaxation time phonon BTE model employs a single-mode relaxation time idea, but the relaxation time is a function of wave-vector. The resulting model is significantly less expensive than the full-scattering model, but incorporates directional and dispersion behavior as well as relaxation times satisfying conservation rules. A critical issue in the model development is the accounting for the role of three-phonon N scattering processes. Direct inclusion of N processes into the anisotropic relaxation time model is not possible because such an inclusion would engender thermal resistance. Following Callaway, the overall relaxation rate is modified to include the shift in the phonon distribution function due to N processes. The relaxation times so obtained are compared with the data extracted from equilibrium molecular dynamics simulation by Henry and Chen. The anisotropic relaxation time phonon BTE model is validated by comparing the predicted bulk thermal conductivities of silicon and silicon thin-film thermal conductivities with experimental measurements.
Development of a Numerical Model for Non-Uniformly Powered Die to Improve Both Thermal and Device Clock Performance
Authors: Karajgikar Saket , Agonafer Dereje , Ghose Kanad , Sammakia Bahgat , Amon Cristina , Refai-Ahmed Gamal
Published: January 2011

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional blocks dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effect on computer performance and product reliability as well as yield. Moving the functional blocks may reduce the junction temperature but can also affect the performance by a factor as high as 35%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 82.4°C and 94.5°C with a corresponding penalty on the performance of 35% and 0% respectively. The optimized location of the functional blocks resulted in a temperature of 83.2°C for a performance loss of 5%.
Double-Sided Microchannel Cooling of a Power Electronics Module Using Power Overlay
Authors: Pautsch Adam G. , Gowda Arun , Stevanovic Ljubisa , Beaupre Rich
Published: January 2011

In the continuing effort to alleviate the increasing thermal loads for power electronics devices, numerous aggressive solutions have been developed, such as small-scale micro-channel heat exchangers. Although these methods can improve overall surface heat transfer to the order of 500 W cm−2, they are limited to single-sided cooling due to the typical wire-bonded electrical connections of the devices. Power overlay (POL) technology provides a stable planar structure for electrical connection, as well as attachment of an additional top-side heat exchanger. This study presents an analysis of double-sided microchannel cooling of a power electronics module. Two optimized, integral micro-channel heat sinks were attached above and below silicon power devices, with more traditional attachment on one side and a POL interface on the other. A compliant TIM was selected for low thermal resistance and good mechanical response, which allowed top-side connection to the POL surface. A theoretical model is presented that predicts the benefit of double-sided cooling based on the known performance of a single-sided heat sink and given addition thermal contact resistance for the top side. For microchannels with water, an enhancement of 26% was predicted. An experiment was also carried out to measure the actual performance benefit seen with double-sided cooling. An enhancement of over 30% was measured for a particular design. As the theory predicts, the benefit of double-sided cooling is limited for high performance designs. However, double-sided cooling could lead to high levels of thermal performance using low-performance technology.
Experimental Study on Applied Thin Vapor Chamber and Embedded Heat Pipe Heat Sinks
Authors: Glover Garrett A. , Chen Yongguo , Luo Annie , Chu Herman
Published: January 2011

The current work is a survey of applied applications of passive 2-phase technologies, such as heat pipe and vapor chamber, in heat sink designs with thin base for electronic cooling. The latest improvements of the technologies and manufacturing processes allow achievable heat sink base thickness of 3 mm as compared to around 5 mm previously. The key technical challenge has been on maintaining structural integrity for adequate hollow space for the working fluid vapor in order to retain high performance while reducing the thickness of the overall vapor chamber or flattened heat pipe. Several designs of thin vapor chamber base heat sink and embedded heat pipe heat sink from different vendors are presented for a moderate power density application of a 60 W, 13.2 mm square heat source. Numerous works have been published by both academia and commercial applications in studying the fundamental science of passive 2-phase flow technologies; their performance has been compared to solid materials, like aluminum and copper. These works have established the merits of using heat pipes and vapor chambers in electronic cooling. The intent of this paper is to provide a methodical approach to help to accelerate the process in evaluating the arrays of different commercial designs of these devices in our product design cycle. In this paper, the trade-offs between the different types of technologies are discussed for parameters such as performance advantages, physical attributes, and some cost considerations. This is a bake-off evaluation of the complete heat sink solutions from the various vendors and not a fundamental research of vapor chambers and heat pipes — for that, it is best left to the vendors and universities.
Visualization and Analysis of Venting From a Single Microchannel Two-Phase Copper Heat Exchanger
Authors: David Milnes P. , Steinbrenner Julie , Miler Josef , Goodson Kenneth E.
Published: January 2011

Two-phase microfluidic cooling solutions have the potential to meet the thermal and geometric requirements of high performance microprocessors. However, rapid nucleation and growth of the vapor phase in the micro-scale flow structures produce detrimental rise in the system pressure and create flow instabilities. In our previous work we developed a novel solution to these problems: to locally vent the vapor formed in the microstructures by capping the flow structures with porous, hydrophobic membranes that allow only the trapped vapor phase to escape the system. In this paper we present the results from a visualization study of this venting process in a copper microchannel with a porous hydrophobic Teflon membrane wall and determine the impact of varying flow conditions on the venting process. We tested liquid flow rates of 0.1, 0.25 and 0.5 ml/min with air injection rates varying from 0.2 to 6 ml/min, corresponding to mass qualities of 0.1% to 7%. Bubbly/slug and wavy flows are dominant at the lower liquid and air flow rates, with wavy-stratified and stratified flows becoming dominant at higher air injection rates. At the highest liquid flow rate, plug and annular flows were common. Analysis finds that venting effectiveness is insensitive to Reliq until the point where non-contact flow structures such as annular become dominant and result in a loss of effective venting area. We also find that venting area changes linearly with mass quality and that the maximum venting effectiveness can be improved by increasing the venting area or raising the total static system pressure. However, venting effectiveness is fundamentally limited by the membrane conductance.
Next Generation Solder-Systems for Thermal Interface and Interconnect Applications via Liquid Phase Sintering
Authors: Liu J. , Kumar P. , Dutta I. , Raj R. , Renavikar M.
Published: January 2011

This paper reports on a new paradigm for highly flexible solder design, proffering high electrical and thermal conductivity, in conjunction with good mechanical compliance, via a novel Liquid Phase Sintering (LPS) approach. The new LPS solders comprise a high melting point phase HMP (e.g., Cu or Sn) with a small amount of a low melting-point phase LMP (e.g., In) at grain boundaries, such that different properties can be controlled by different constituents. In general, conductivity is dominated by the majority HMP constituent, while deformation is controlled by the minority, LMP grain boundary constituent. The LPS solders are suitable for both thermal interface material (TIM) and interconnect applications. As the application space for solders shifts in the future, and requirements for new property-sets emerge, the flexibility of the LPS solder approach will allow integration of different materials into new LPS solder-systems.
A New Methodology for Cold Plate and Heat Sink Optimization
Authors: Rice Jeremy , Alyaser Monem
Published: January 2011

A new methodology of cold plate and heat sink optimization is presented which can reduce the computational time by more than two orders of magnitude when compared to CFD. This methodology is intended for high Prandtl number fluids or fully developed velocity fields. When compared to CFD, this model can predict the heat transfer to within 8% of the CFD solution for the intended operating ranges. The paper outlines the manipulation of established empirical and analytical correlations for developing thermal fields with constant wall temperatures using a scaling analysis. Since the real fin temperature is not constant, the proposed technique utilizes superposition to recreate the real fin temperature profile and enable the use of established analytical models. Finally, the fins are not individually modeled, which is computationally intensive, but captured using an assumption of anisotropic conduction, where the convective heat transfer is converted to a volumetric sink term.
Application of Frequency-Domain Thermal Measurements in Electronics Packaging
Authors: Yang Yizhang , Zhang Zhen , Touzelbaev Maxat
Published: January 2011

Increase of power densities has become the primary constraint for semiconductor industry to sustain the Moore’s law for microprocessor evolution. Further development of packaging technology and advanced thermal interface materials (TIMs) requires both maximization of the total thermal throughput of the system and mitigation of the thermal impact from non-uniformly distributed hotspots. Therefore, thermal characterization techniques capable of resolving partial thermal resistances at the component level have received increased emphasis in development of advanced packaging technologies. This work develops a practical method for thermal characterization of IC packages using the frequency-domain measurement technique. It is well suited for investigation of package thermal performance during various application-specific tests in field conditions, as well as a tool for development of TIM and optimization of packaging process. Both steady-state and dynamic thermal characterizations of the IC packages can be achieved using this technique. Various applications, such as thermal structure function measurement, silicon die hot-spot detection, and in-situ thermal/mechanical characterization of TIMs are discussed.
Packaging Technology Development for Silicon on Sapphire Based Commercial RF IC Products
Authors: Yang John Zhiyuan
Published: January 2011

This paper presents packaging solution for silicon on sapphire based commercial RF IC products for which package type is focused on traditional plastic packages such as MSOP, TSSOP, QFN and recently developed ultra thin QFN package. Package mechanical performance, reliability evaluation and electrical performance have been addressed.
Optimization of Cold Aisle Isolation Designs for a Data Center With Roofs and Doors Using Slits
Authors: Gondipalli Srujan , Sammakia Bahgat , Bhopte Siddarth , Schmidt Roger , Iyengar Madhusudan K. , Murray Bruce
Published: January 2011

Data centers are facilities that house large numbers of computer servers that typically dissipate high power. With the rapid increase in the heat flux of such systems, their thermal management represents an economic and environmental challenge that needs to be addressed [2]. Considering the trends of increasing heat loads and heat fluxes, the focus for users is in providing adequate airflow through the equipment at a temperature that meets the manufacturers’ requirements. Data centers house IT equipment in racks typically arranged in rows which face one another. Alternating cold and hot aisles are formed and this pattern is repeated across the data center. This approach helps to separate cold and hot air streams; but this does not always suffice in the separation of cold and hot air. The mixing of hot rack exhaust air with cold supply air, short-circuiting of cold air to the coolers and the recirculation of hot air to racks’ inlet are the common phenomena that lead to thermal inefficiencies in a typical data center. Typically in a raised floor data center, increase in rack inlet air temperature is seen because of the infiltration of hot air into the cold aisle from the top (ceiling of the cold aisle) and from edges or sides. Infiltration can be reduced to a certain extent if cold aisles are isolated from ceiling and hot aisles using partially or fully closed doors with slits to manage the airflow. The key is to redistribute the cold air entering the cold aisle along with any infiltration such that the overall average temperature at the rack inlets is below a predefined level. In this paper, different designs were generated with the criteria of achieving no hotspots, a relatively low pressure drop across the servers and low velocity of the air in the cold aisle based on an actual data center model. Several designs are proposed that meet all of the defined constraints.
Effect of Phonon Dispersion on Thermal Conduction Across Si/Ge Interfaces
Authors: Singh Dhruv , Murthy Jayathi Y. , Fisher Timothy S.
Published: January 2011

We report finite volume simulations of the phonon Boltzmann transport equation (BTE) for heat conduction across the heterogeneous interfaces in SiGe superlattices. We employ the diffuse mismatch model with full details of phonon dispersion and polarization. Simulations are performed over a wide range of Knudsen numbers. Similar to previous studies we establish that thermal conductivity of a superlattice is much lower than the host materials for superlattice period in the submicron regime. Details of the non-equilibrium between optical and acoustic phonons that emerge due to the mismatch of phonon spectrum in silicon and germanium are delineated for the first time. Conditions are identified for which this can lead to a significant additional thermal resistance than that attributed primarily to boundary scattering of phonons. We report results for thermal conductivity for various volume fraction and superlattice periods.
Cure Profile Effects on the Mechanical Behavior and Reliability of Flip Chip on Laminate Assemblies
Authors: Tian Guoyun , Lin Chang , Suhling Jeffrey C. , Lall Pradeep
Published: January 2011

In this work, the effects of underfill cure temperature and JEDEC MSL preconditioning on underfill mechanical and strength properties, as well as flip chip assembly reliability have been explored. Baseline stress-strain curves, mechanical properties, and interfacial shear strengths of a capillary underfill were recorded for curing at 150 °C and 165 °C (30 minutes). In addition, the changes in the mechanical and strength properties resulting from MSL3 and MSL2 moisture preconditioning were evaluated. The MSL preconditioning of the underfill samples included the JEDEC specified humidity and temperature exposures, plus three simulated reflows at 245 °C or 260 °C. Thermal cycling life tests from −55 to 125 °C were also conducted on daisy chain flip chip assemblies incorporating the same underfill. The test matrix for the reliability testing included both 150 °C and 165 °C curing profiles, and two levels of precondition (none and MSL3). Finally, the failure mechanisms in the flip chip assemblies were studied using CSAM, x-ray and SEM analyses. The results clearly indicate the advantages of the higher curing temperature including improved mechanical properties, superior thermal cycling fatigue life, and enhanced resistance to detrimental effects from moisture exposure and solder reflow.
IBM’s POWER6 High Performance Water Cooled Cluster at NCAR: Infrastructure Design
Authors: Schmidt Roger , Ellsworth Mike , Iyengar Madhu , New Gary
Published: January 2011

The increased focus on green technologies and energy efficiency coupled with the insatiable desire of IT equipment customers for more performance has driven manufacturers to deploy liquid cooling technologies for cooling IT equipment. In April, 2008 IBM announced the world’s fastest UNIX server using unique water cooling technologies. The first system (eleven racks) was shipped and installed at The National Center for Atmospheric Research (NCAR) in Boulder, Colorado in May, 2008 to be used for research on climate change and severe weather. The POWER6 575 system utilizes water cooling to cool the processors as well as a water cooled rear door to remove 80% of the 60 kW heat load generated by each rack. This cluster of eleven racks with this highly efficient cooling system achieves a performance of 76 teraflops within a small footprint. This paper will describe the infrastructure required to support this cluster of racks including the chilled water cooling loop, water thermal storage tanks, and the 480 VAC power distribution system. The time response of the various potential failure modes in the water cooling system will also be described.
Direct Measurement of Gyroscope Quadrature Error Using Interferometric Tools
Authors: Marinis Ryan T. , Pryputniewicz Ryszard J.
Published: January 2011

A tuning fork gyroscope (TFG) functions by sensing a Coriolis acceleration. Proof masses are excited in plane, such that the motion is sinusoidal. A rotation, normal to the excitation direction, results in a Coriolis acceleration based on the cross product of the input rotation and the proof mass in-plane velocity. The Coriolis force displaces the proof mass, normal to the chip by an amount related to input rotation. The in-plane (drive) and out-of-plane (sense) motions of the proof masses are offset by 90°, placing these positions in quadrature. Quadrature error is present when the proof masses do not oscillate in plane, but rather have a small degree of out-of-plane motion. This error may cause a zero rate output in the sensor, also known as a bias error. A methodology is presented for using interferometry to directly measure the quadrature motion. Optical interferometry uses non-contact methods for shape measurement, with high accuracy normal to the viewing plane. Measurements may be made on the proof masses, while running, by utilizing a strobe illumination source. By matching the strobe frequency with the gyroscope resonance the motion is frozen to the camera, during which time quantitative measurements are made. This process is repeated at various positions of the in-plane proof mass motion and analyzed to reveal the degree of out-of-plane displacements of the proof masses while running.
Approximate Analysis for Darcy-Flow Convection in Porous Media With Zero Fluid Conduction
Authors: Dukhan Nihad
Published: January 2011

The heat rejection device is a key component in virtually all electronic systems. New core materials for compact and efficient heat exchangers or heat rejection devices are contemporary porous media including metal and graphite foam. In such materials the solid phase has a relatively high conductivity, especially when the fluid phase has a low conductivity. This condition is realized in air-cooling thermal management systems. Simple models are needed for scientists and engineers who work with these materials. Approximate engineering analysis for the convection heat transfer inside a two-dimensional rectangular porous media subjected to constant heat flux on one side is presented. The analysis sets the conduction in the fluid’s governing equation to zero, and for simplicity assumes Darcian flow. The Darcian flow assumption is valid far enough from the solid boundaries, ant it prevails for most of the cross section. The non-local-thermal equilibrium equations are significantly simplified and solved. The solid and fluid temperatures decay in what looks like an exponential fashion as the distance from the heated base increases. The results are in good qualitative agreement with more complex analytical and numerical results in the literature. The proposed model may prove to be time-savings for design purposes.
Numerical Optimization of a Electroosmotically Enhanced Microchannel Heat Sink
Authors: Husain Afzal , Kim Kwang-Yong
Published: January 2011

A liquid flow microchannel heat sink has been studied with the help of three-dimensional numerical analysis for mixed (electroosmotic and pressure-driven) flow. The optimization of the microchannel heat sink has been performed with the help of surrogate method coupled with multi-objective evolutionary algorithms. The effects of ionic concentration represented by the zeta potential and Debye thickness are studied at various levels of externally applied electric potential. Temperature dependent coolant properties are considered to take into account the micro-scale effects for accurately predicting the thermal performance of the microchannel heat sink. Higher value of zeta potential leads to higher flow-rate and lower thermal resistance which consequently reduced the temperature of the microprocessor chip and load of micro-pump used to supply the coolant to the microchannels. Two design variables are selected related to the microchannel width, depth and fin width and design space is explored through four-level full factorial design. The channel width-to-depth ratio is found to be higher Pareto-sensitive (sensitivity along the Pareto-optimal front) than the other design variable. The trade-off between objective functions and Pareto-sensitivity of the design variables can be utilized to economically design the microchannel heat sinks. In view of the limiting pumping power available at the micro-level the application of the electroosmosis along with the commonly used pumping source can greatly enhance the performance of the microchannel heat sink.
In-Situ, Precise and High-Speed Measurement for Novel TIM Characterization
Authors: Ishida Yuichi , Ryoson Hiroyuki , Ota Toshiro , Yazawa Kazuaki
Published: January 2011

Due to the thermal compliance necessary for high-performance thermal interface material (TIM), precise thermal measurements are becoming more and more important. The interface thermal resistance of high-performance chips may easily exceed 30% of the total thermal resistance between chip and ambient. According to the general definition of thermal resistance, two surface temperatures and strictly accurate heat flow must be measured at the same time. The ASTM-D5470 method is suitable to do this. Clarification of the role of contact thermal resistance requires characterization of effective thermal conductivity of the material. This requires knowing accurate dimensions of cross section area and thickness. To achieve this fine measurement, equipment has been developed that enables the measurement of the thermal resistance with high accuracy as well as the measurement of interface thickness with sub-micrometer resolution in a simultaneous series. The thickness is determined by the optical pin-gap sensing method. Complete data can be obtained for each second after the data logging has started. The instantaneous temperature responses of TIM and heat rods take less time than the whole piece of equipment does to reach 99% temperature equilibrium. According to the data, sufficient accuracy can be obtained at local thermal equilibrium in around ten minutes to analyze the TIM performance in this measurement setup. Local small thermal mass plays a significant role in the measurement. This measurement technique is also helpful for pressure sensitive and soft TIM with minimum compressive creep deformation.
Analysis and Design of the IBM Power 575 Supercomputing Node Cold Plate Assembly
Authors: Campbell Levi A. , Ellsworth Michael J. , Sinha Arvind K.
Published: January 2011

IBM returned to indirect (cold plate) water cooling in 2008 with the introduction of the Power 575 Supercomputing Node [1]. The node, packaged in a super-dense 2U (88.9 mm) form factor, contains 16 dual core processor modules. An assembly of 16 cold plates was developed to cool the processors. The assembly consists of the cold plates (one cold plate for each processor module), copper tubing that connects 4 groups of 4 cold plates in series, copper tubing that connects each grouping of 4 cold plates, or quadrant, to a common set of supply and return headers, and two flexible EPDM hoses that connect the headers to system level manifolds in the rack housing the nodes (a rack can contain up to 14 nodes). Non-spill poppeted quick connects are used to connect the cold plate assembly to the system level manifolds. In addition to a detailed description of the cold plate assembly, an overview will be given of the analysis and design that went into its development. Conjugate computational fluid dynamics (CFD) modeling was done on the cold plate and processor module combination. CFD modeling was done on the headers to verify proper flow balancing. Finally, mechanical finite element analyses were performed to determine the cold plate tube routing necessary to minimize reactionary forces the tubes placed on the cold plates under land grid array loading of the module to the board.
Stress Measurement Errors in Flip Chip Packages Using Multi-Element Sensor Rosettes on (111) Silicon
Authors: Jaeger Richard C. , Suhling Jeffrey C. , Hussain Safina , Roberts Jordan C. , Motalab Mohammad A. , Cho Chun-Hyung
Published: January 2011

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. A previous paper initated a study of the errors in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients and temperature. In this work, we apply the earlier results to an analysis of the sensitivities and errors in the extracted stresses on an integrated circuit die in a flip-chip package. A finite-element model for a basic flip-chip configuration is utilized to estimate the stress across the surface of the silicon die. These results are used to evaluate the stress sensitivities to coefficient and temperature errors throughout the die surface. The sensitivities are stress dependent and vary widely from very small to very large over the die surface. The results confirm that temperature compensated rosette configurations should be utilized whenever possible.
Experimental Study of the High Cycle Fatigue of Thin Film Metal on Polyethylene Terephthalate for Flexible Electronics Applications
Authors: Alzoubi Khalid , Lu Susan , Sammakia Bahgat , Poliks Mark
Published: January 2011

Flexible electronics represent an emerging area in the electronics packaging and systems integration industry with the potential for new product development and commercialization in the near future. Manufacturing electronics on flexible substrates will produce low cost devices that are rugged, light, and flexible. However, electronic systems are vulnerable to failures caused by mechanical and thermal stresses. For electronic systems on flexible substrates repeated stresses below the ultimate tensile strength or even below the yield strength will cause failures in the thin films. It is known that mechanical properties of thin films are different from those of bulk materials; so, it is difficult to extrapolate bulk material properties on thin film materials. The objective of this work is to study the behavior of thin-film metal coated flexible substrates under high cyclic bending fatigue loading. Polyethylene terephthalate (PET) and polyethylene naphthalate (PEN) are widely used substrates in the fabrication of microelectronic devices. Factors affecting the fatigue life of thin-film coated flexible substrates were studied, including thin film thickness, temperature, and humidity. A series of experiments for sputter-deposited copper on PET substrates were performed. Electrical resistance and crack growth rate were monitored during the experiments at specified time intervals. High magnification images were obtained to observe the crack initiation and propagation in the metal film. Statistical analysis based on design of experiments concepts was performed to identify the main factors and factor’s interaction that affect the life of a thin-film coated substrate. The results of the experiments showed that the crack starts in the middle of the sample and slowly grows toward the edges. Electrical resistance increases slightly during the test until the crack length covers about 90% of the total width of the sample where a dramatic increase in the resistance takes place.
Refrigeration Heat Exchanger Systems for Server Rack Cooling in Data Centers
Authors: Tsukamoto Takeshi , Takayoshi Jyunji , Schmidt Roger R. , Iyengar Madhusudan K.
Published: January 2011

In 2005, IBM released a water cooled heat exchanger product that significantly enhanced data center cooling capability while also demonstrating substantial energy savings. In 2008, IBM released an enhanced water less solution to cool the electronic racks via a R410A refrigerant based vapor compression system, which is the focus of this paper. The paper provides a detailed description of device and coolant loop construction, the experimental thermal data collected, as well as a discussion of its’ cooling energy efficiency relative to both typical air cooled facilities and water cooled heat exchangers, respectively. A data center level case study was performed with experimental measurements collected and discussed herein. Significant energy savings were realized even when the heat exchanger devices were implemented on a small part of the data center. Based on the test data and the experimental data center study, the CRAC units based loops have a COP of 1.95, while the refrigerant refrigerant heat exchanger loop has a COP of 5.0.
Assessment of Relative Thermal Fatigue Life of SAC Lead-Free and Tin-Lead Solders With Custom-Made BGA Assemblies Creating Various Stress Ranges
Authors: Chan Y. S. , Yang C. , Lee S. W. Ricky
Published: January 2011

The present study evaluates the relative thermal fatigue life of tin-silver-copper (SnAgCu or SAC) lead-free and tin-lead (SnPb) solders with custom-made BGA assembly configurations generating various stress ranges under thermal cyclic loading. Although the SAC solder bears a lower creep strain rate compared with the SnPb solder in common thermal cycling conditions, it is found that there exits conditions at which the SnPb solder joint maintain a longer life than the SAC solder joint. The determination lies on the maximum normalized equivalent stress levels (σ/E) experienced by the two kinds of solder joint during the temperature cycles. Even under the same straining and thermal cycling condition, it is observed that the maximum σ/E induced in the two kinds of solder joint are normally different, as a result of their different rate of stress relaxation. The analysis shows that both the absolute and relative magnitude of σ/E experienced by the two kinds of solder joint affect the relative life. In general, the SAC solder joint sustain a longer life at low σ/E levels, while the SnPb solder joint outperform the SAC solder joint at high σ/E levels. There exists a critical σ/E level at which both solder joints acquire similar performance. However, this margin shifts with the relative magnitude of σ/E the two kinds of solder joint suffered. Having studied the variation of σ/E for the two kinds of solder joint under various loading conditions, this study uncovers the rationale for the difference in the relative thermal fatigue life of the two kinds of solder joint.
Thermal Mechanical Design and Validation of Memory Heat Spreaders
Authors: Lee Ted , Pederson Bruce , Qiu An
Published: January 2011

The design and validation of heat spreaders for server platform memory modules incorporates many challenges that are not present in typical CPU thermal solutions. While the total design power of the CPU has been relatively constant over the last few server generations, the power requirements for memory modules has continued to increase to the point where custom thermal solutions are now required. This paper will describe some of the design and validation challenges that were developed to ensure that memory modules would be sufficiently cooled in order to meet their performance targets.
Application of Phase Growth Approach to Prediction of Thermal Fatigue Crack Initiation Lifetime in Sn-3.0Ag-0.5Cu Solder Joints
Authors: Okamoto Yoshiyuki , Takayanagi Takeshi , Sayama Toshihiko , Ejiri Yasuhiro , Nakano Hiroyuki , Mori Takao
Published: January 2011

Thermal fatigue damage of solder joints is believed to be closely related to microstructure evolution, that is phase growth. In the previous researches, the authors have obtained the following results. The phase growth is characterized by phase growth parameter S, which is defined as average phase size to the 4th power, and proceeds such that S increases proportional to the number of thermal cycles. And a simple power low relation was found between average number of cycles to thermal fatigue crack initiation lifetime and average increase in the phase growth parameter per cycle ΔS. In this paper, in order to apply the relation to the evaluation of the crack initiation lifetime in actual solder joints, thermal cycle tests were carried out by using fabricated printed circuit board (PCB) on which chip resistors were mounted by Sn-3.0Ag-0.5Cu solder. Periodically, the specimen was taken out from thermal shock chamber and the phase growth of the β-Sn phase in the solder joints was observed by scanning electron microscope (SEM). The following results were obtained. The microstructure observation showed that the lifetime prediction based on the phase growth parameter measured by the data in low cycles of 20 to 100, was within the range of 90% confidence limits of the experimentally determined lifetime. Therefore, the estimation method by the phase growth parameter can be applied to the lifetime prediction of solder joint with sufficient accuracy.
Numerical Simulations for Digitized Heat Transfer
Authors: Baird Eric , Mohseni Kamran
Published: January 2011

This paper presents estimates of heat removal capabilities of a Digitized Heat Transfer (DHT) cooled device, a novel active thermal management technique for high power density electronics and integrated microsystems. In DHT, thermal energy is transported by a discrete array of electrostatically activated microdroplets of liquid metals, alloys or aqueous solutions with the potential of supporting significantly higher heat transfer rates than classical air-cooled heat sinks. Actuation methods for dispensing and transporting individual fluid slugs with a high degree of precision and programmability are described, and numerical results for the amount of heat flux removal a DHT device can obtain are presented.
Application of Thermo-Viscoelastic Laminated Plate Theory to Predict Warpage of Printed Circuit Boards
Authors: Mikami Takao , Kobayashi Takaya
Published: January 2011

The rapid assembly of printed circuit boards to meet the desired goal of thinning the board creates more complexity in the reflow process, to control the occurrence of warpage in the board. Therefore, certain methods are preferred for simply yet accurately predicting the amount of warpage inevitable in the reflow process. Responding to such a need, the study was carried out aiming to provide a specific numerical method based on the multilayered plate theory, resulting in a simple procedure capable of supplying an accurate estimation of the warped deformation of the board. The estimation results derived from this method were compared with the FEM analysis results and confirmed to be in good agreement. Application of this method is designed for ease of use to estimate the warpage at any stage of planning and design.
Numerical Analysis of Mist-Cooled High Power Components in Cabinets
Authors: Kumari Niru , Bahadur Vaibhav , Hodes Marc , Salamon Todd , Lyons Alan , Kolodner Paul , Garimella Suresh V.
Published: January 2011

The heat dissipation capacity of air-cooled computing and telecommunications cabinets is limited by acoustic noise and fan reliability considerations. The present work quantifies the potential for thermal management of a sealed cabinet using an evaporating mist introduced upstream of the high-power electronic components. The proposed concept consists of droplets of mist being dispersed in the air flowing through a heat sink. The evaporated mist is condensed at the outlet of the circuit packs and recycled back to the inlet. The flow and heat-transfer characteristics of mist flows in a representative heat sink inside the cabinet are explored through numerical analysis of the coupled mass, momentum and energy transport equations for an evaporating two-phase mixture. The effect of droplet size and the mist loading fraction on the heat sink temperature reduction is computed and parametrically analyzed. The results reveal significant insights into the complex transport processes associated with mist flows. Mist cooling is shown to offer significant promise as a feasible thermal management solution for telecommunications cabinets and data centers.
An Integrated Experimental and Theoretical Approach to Evaluate Si Strength Dependent on the Processing History
Authors: Brueckner John , Dudek Rainer , Rzepka Sven , Michel Bernd
Published: January 2011

Silicon is the most widely used semiconductor material for MEMS and electronic applications. The strength of silicon has a critical impact on the reliable and accurate function of these components. In packaging assembly, reliability tests as well as in operation life the silicon die can be exposed to high stresses. For a theoretical risk assessment of die cracking due to the mentioned loadings a failure criterion is needed, which is capable to account the processing history. Therefore, the experimental characterization via fracture tests, analysis of different Si surface structures by Laser-Scanning-Microscopy (LSM) and Transmission-Electron-Microscopy (TEM) and a numerical approach using Finite Element Simulation was combined to allow failure prediction. In the fracture tests the influences of the backside grinding and the stress relief processes were investigated. The test dies were fabricated using the Dicing-before-Grinding (DBG) process with different mesh sizes of the grinding wheel. Additionally dry polishing and plasma etching were applied as stress relief processes. Bending tests are commonly used for the strength characterization of brittle materials like ceramics and silicon. The ball-ring-test was conducted to exclude edge effects on the strength, which are still under investigation in an additional part of the study. It was found that the determined fracture stresses follow a three-parametric Weibull distribution. The surface topography and roughness, respectively, was measured via LSM. TEM was applied to determine the structure of the surface-near damage-layer. In addition to the experimental investigations numerical calculations by means of Finite Element Simulations were performed in order to calculate critical fracture stresses from testing including anisotropic and geometric nonlinear effects. Furthermore, a submodeling-technique was applied to understand the effects of experimentally observed surface states on the critical stress, i.e. roughness, grinding marks, flaws, and poly Si-layers. Detailed modeling included local modeling of surface roughness on the critical strength.
Strength Evaluation of Conductive Adhesive Paste for Die Bonding During Reflow Soldering
Authors: Ashida Kisho , Kawano Kenya , Tanaka Naotaka , Nishikizawa Atsushi , Koike Nobuya
Published: January 2011

Evaluating silver paste strength for die bonding during the reflow soldering process is important, as silver paste fracturing is one of the main causes of package failure. First, we assumed that the fracturing was caused by thermal stress and vapor pressure at the interface between the resin and the copper lead frame. Next, we measured the silver paste fracture strength using a three-point bending test and a bonded specimen with silver paste. Finally, we predicted the occurrence of silver paste fracturing by calculating the silver paste stress during reflow soldering process and comparing it with the measured fracture strength. Results obtained in strength evaluation analysis were consistent with those obtained in package reflow tests, indicating that this method can be used to predict the occurrence of silver paste fracturing.
High-Density Room-Temperature 3D Chip-Stacking Using Mechanical Caulking With Compliant Bump and Through-Hole-Electrode
Authors: Watanabe Naoya , Kawashita Michihiro , Yoshimura Yasuhiro , Tanaka Naotaka , Asano Tanemasa
Published: January 2011

In this study, we employ a novel compliant bump in 3D chip-stacking using mechanical caulking. The compliant bump prepared in this work has a cone-like structure and is made of Au. It is fabricated using an “undercut resist method,” which combines undercut resist pattern formation with electroplating. The size of the compliant bump (approximately 10–30 μm in diameter) is much smaller than that of the stud bump. We demonstrate that by using a mechanical caulking process with a compliant bump and a through-hole-electrode, high-density through-hole-electrode interconnection (I/O number: 8,000, pitch: 20 μm) becomes possible, even at room temperature.
Evaluating the Dominant Factor for Electromigration in High Purities Al Film Deposited by Sputtering
Authors: Zhao Xu , Saka Masumi , Yamashita Mitsuo , Togoh Fumiaki
Published: January 2011

A way of testing the electromigration (EM) resistance of different high purities Al based on atomic flux divergence (AFD) method has been proposed in our previous work. With the theoretical analysis, the EM resistance has been clarified to depend on various parameters which are related with the material properties such as diffusion coefficient and grain size. The present research compares the EM resistance of different high purities Al films with the same thickness of 5μm. For these films, the grain size, which is realized as a factor affecting the resistance, was changed compared with the 1μm thick samples, which have been used in the previous work. A narrow section was shaped in the film by introducing a double-L shaped slit by using a focused-ion-beam (FIB) system. The samples so fabricated were positioned on a ceramic heater with constant temperature, and a high current density was achieved in the narrow section to cause EM. After experiencing the same time for current supply and confirming having the same local temperature by using chemical reagents having known melting points, the different purities samples were observed with a magnified field emission scanning electron microscopy (FE-SEM). In addition, the comparison of the total hillock volume appeared in the sample with the time for current supply is achieved for the samples. It is known that for a given time, a smaller hillock volume corresponds to a higher resistance of the material against EM. Finally, according with the analysis by the synthesis of the obtained EM ranking for the 1 and 5μm thick films, the evaluation of the dominant factor, diffusion coefficient, for EM in high purities Al film deposited by sputtering was approached.