bluuebunny/crossref_metadata_2025 huggingface dataset:
Study of APFx as Etch Hardmask Application
Authors: Liang Xudong , Chen Yingjie , Chai Qinglin , Li Xianyuan , Zhao Ganming
Published: March 2014

This paper addresses refractive index (n), extinction coefficient (k), uniformity, and step coverage of APFx film, which can be optimized by varying process parameters, such as precursor flow rate, spacing, chamber pressure, and power. APFx shows good uniformity. APFx has a lower extinction coefficient at 633nm, which makes possible easier alignment. Moreover, APFx has good step coverage and a wide tuning range of conformality, which improves film integrity for photoresist rework.
Cu Barrier Seed Innovation for EM Improvement
Authors: He Weiye , Kang Jian , Luo Jeff , Wu Grant , Zhang Lei
Published: March 2014

Cu barrier seed is a key process in Cu interconnect. Continuous improvement in Cu barrier and seed processes and hardware has enabled improvement in Cu gap fill and effective suppression of Cu diffusion and EM (electron migration). This paper addresses innovations in Cu barrier and seed aimed at suppressing EM. Both barrier and seed processes are crucial for EM qualification. In vias, a robust and continuous barrier reduces Cu diffusion at the interface; robust punch through helps via clean; and the resputtering process can optimize via profile and current distribution. Most early failures in the via could be fixed by the PVD (physical vapor deposition) Ta(N) process. Cu alloy seed was later developed to increase EM life time. CuAl alloy can retard Cu migration at the grain boundary and interface; CuMn alloy can create a self-formed barrier. Co wetting and capping layers are the newest approaches for suppressing EM failures at 32nm and below. The entire Cu line can be encapsulated by a Co layer, leaving no weak spots in the top and sidewall interface and blocking the rapid diffusion path of Cu. Compared to CuMn, the Co solution also offers advantages for gap fill and Rc reduction.
(Invited) Application of Selective Epitaxial Growth in the Sub 20 nm FinFET Device Fabrication
Authors: Hikavyy Andriy Yakovitch , Rosseel Erik , Eneman Geert , Favia Paola , Loo Roger
Published: March 2014

Application of high Ge content (up to 70%) SiGe in the fin FET pMOS transistors for the following 14 and 10 nm nodes is suggested and reasoned. Use of Si:C and Si:P for nMOS counterpart is discussed and difficulties of selective epitaxial growth of such layers are evaluated. Merging of fins in source/drain areas is presented and main features are shown.
(Keynote) Atomic Layer Deposition Trends and Challenges in High-k/Metal Gate and Alternative Channel CMOS Processing
Authors: Chudzik Michael P , Krishnan S. , Dai M. , Siddiqui S. , Shepard J. , Kwon U.
Published: March 2014

The utilization of Atomic Layer Deposition (ALD) has gained wider adoption in FEOL CMOS processing over the last several technology generations and is expected to accelerate as the semiconductor industry migrates to FinFET device architectures. The primary drivers for the migration to ALD include: dimensional control, conformality (step coverage), reduction in pattern effects (especially micro-loading), low temperature processing requirements and the need for low damage/substrate interactions. The areas of greatest initial use center on the high-k and metal transistor gate (HKMG). Most significantly, the quality of these ALD films has improved to the point that they are now even used to replace thermal grown oxide films and are a key enabler for the next generation of channel materials where traditional oxide growth is not an option for certain devices.
Study on Undercut Produced in the Interface between Hardmask Film and Porous Low k Film
Authors: Zhou Ming , Tao Wang zong , Hao Deng
Published: March 2014

This paper was to investigate the mechanism of the undercut in the interface between oxide hardmask film and porous low k film and put forward the solution of improving undercut issue. Dilute hydrofluoric acid (DHF) concentration decreased from 300:1 to 1000:1, which did slightly improve the undercut. The dense low k film without O2 plasma was inserted between TEOS hardmask and porous low k film, however, it was not found for undercut profile after dry etching and wet clean. This indicates that O2 plasma caused the carbon loss of porous low k film surface, and porous low k film in the surface was converted into active SiOH. After dry etching and wet clean, dilute hydrofluoric acid (DHF:300:1) removed the SiOH to form the undercut. This clearly showed that oxygen plasma causing porous low k damage played and DHF played the important role of the forming undercut issue.
PVD TiN for Bottom Electrode of Phase Change Memory
Authors: Ren Wanchun , Liu Bo , Xu Zhen , Xu Jia , He Aodong , Jiang Li , Jing Xuezhen , Xiang Yanghui , Zhang Beichao , Ren Jiadong , Jan Yipeng , Rao Feng , Duan Shuqin , Yu Qinqin , Song Zhitang , Feng Songlin
Published: March 2014

Phase change memory (PCM) has been regarded as a promising candidate of the next generation nonvolatile memory. However, the application of PCM has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). TiN is proposed to be bottom electrode of PCM due to its lower thermal and more suitable electrical conductivity than that of tungsten, which can drastically reduce reset power by less thermal loss and higher heating efficiency. This article shall report several TiN films with different Ti/N ratio prepared by physical vapor deposition (PVD). The Ti/N ratio, resistivity, thermal stability, anti-erosion capability in HF and film density of PVD TiN films are characterized and optimized. We demonstrate the step coverage and contact resistance of the 10nm PVD TiN as the sidewall bottom electrode.
The Study on the Reflectance and Resistance of Ni/Ag/Ti/Au Electrode Contact to p-GaN
Authors: Huang Ya-Ping , Yun Feng , Ding Wen , Wang Yue , Wang Hong , Zhao Yukun
Published: March 2014

The combination of Ni, Ag, Ti and Au which form both reflective and ohmic multilayer contacts for vertical structure light emitting diode applications are studied. The specific contact resistance and reflectivity under different annealing temperature (200, 300, 400, 500 and 600 ℃) and different annealing atmosphere (nitrogen and oxygen) are measured. The annealing atmosphere of oxygen can lead to lower contact resistance than that of nitrogen as annealing temperature increase. However, a higher annealing temperature will lead to a lower reflectivity, especially in the oxygen atmosphere. Comprehensively considering the reflectance and resistance, we obtain the lowest contact resistivity of 5.5×10-3 Ωcm2 and relatively higher reflectivity of 88% at 450 nm.
An Exploration of PECVD Graphene Growth by Direct Optical Characterization
Authors: Wang Jian Yun , Chen Ran , Zhou Li Wei , Chen Chang Jun , Jiang Hao , Lu He Chao , Shao Xing Long , Zhang Kailiang , Zhao Jinshi
Published: March 2014

The synthesis of graphene on Cu foils by using PECVD was reported in this work. The influence of the process parameter on graphene growth was studied, through a facile detection method which directly characterizes discontinuous graphene on Cu foil substrates optically after a simple RTP process. After annealing, the region of Cu foil coated by graphene was away from oxidation, while the Cu foil uncoated by graphene was oxidized, which results in distinctive colors between Cu and CuOx. This method made it possible to observe discontinuous graphene directly by using optical microscope, without transferred, pretreated or other complex characterization techniques. From the point of the growth time and power, a relatively optimized parameter can be found, under which the quality of graphene was improved and the nucleation was easy to be observed.
32_28nm Beol Cu CMP Development for Ultra Low k Scheme
Authors: Liu Hong Tao , Chen Feng , Zhao Feng , Wang Dong , Liu Hao , Cao Junzhu , Hu Tony , Jiang Li , Shao Qun , Deng Wufeng
Published: March 2014

32/28nm BEOL Cu CMP process with ultra low k scheme is investigated in the different aspects. Firstly the barrier metal (BM) slurry selection with proper selectivity is the most critical part to reduce topography. The topography can be minimized by precisely control BM slurry’s selectivity. Secondly, the layout design, such as pattern density, line and space width, has significant impact on WID variation. The test results show more topography correction at more dense Cu line for thinner line where BM polishing is the dominate factor. While for fat line, it shows less topography correction at more dense Cu line, since Cu clearance polishing dominates the final topography. Next k value shift evaluation with different barrier metal slurry, cleaning chemicals and post CMP thermal treatment conditions is also studied. The results indicate that although k value shift occurs during polishing, proper chemicals clean and post thermal treatment can restore parts even the whole of k shift. In addition, the removal of moisture and chemical penetrated into ultra low k film is the key of k value shift and reliabilities improvement.
Barrier Slurry Innovation for Advanced Node
Authors: Cao Christian , Song Kerry , Yao Ying , Jing Jianfen , Wang Yuchun
Published: March 2014

As the development of technology node, ULK was used as isolation material in Cu damascene integration. ULK is a porous material with low mechanical strength and low adhesion. During CMP process, slurry additive and moisture will enter the hole of ULK material and result in the increasing of ULK K value, and also ULK film is easily damaged by mechanical force. To solve this problem, a capping layer is designed in Cu integration. In this paper, a novel barrier is developed to meet this integration need. Slurry chemistry/additives effect on RR selectivity and topo is evaluated in this paper.
(Invited) A Novel System for Slurry Recycling and Waste Water Permeation
Authors: Lee Peter , Tung Cher , Wang Ryan , Tsai Ming-Shih
Published: March 2014

Traditionally, CMP (chemical mechanical planarization) slurry waste requires significant amount of works including pH neutralization, solid precipitation and toxic separation before discharged into environment. Due to the stringent process control in IC manufacturing, the slurries typically cannot be reused, and it caused significant burden to the IC fabs¢ facilities. CMC has successfully developed a novel slurry recycling system which has been implemented in mass production IC fabs over 3 years.. The slurry waste is properly processed to collect both abrasives and permeated water. The abrasive can be further adjusted for continuous polishing usage while the permeated water will be feedback for DI water source. This system has been optimized for reliable slurry¢ s physical properties and well verified with stable polishing performance and no impact on polish defectivity.
(Invited) Barrier Slurry Innovation for Cu-ULK Process
Authors: Yao Ying , Jing Jianfen , Wang Yuchun , Qiu Tengfei , Cai Xinyuan , Chen Baoming , Zhang Jian
Published: March 2014

With the application of Ultra low-k dielectric material in the advanced nodes, more and more challenges are elevated on barrier CMP. High removal rates of TEOS and barrier films are required to enable an effective removal, while tunable Cu RR and low ULK RR are needed to control the topography and stop in ULK layer. The k value shift of polished ULK also should be minimized. In this paper, we will report a barrier slurry for this application including slurry additives effect on removal rate selectivity, topography and k value. The corrosion control capability is also evaluated by soaking test. Through slurry formulation tuning, an optimal topography with good within wafer and within die non-uniformity are obtained. The control capability in removal rate and selectivity, k value shift of polished ULK, topography, and Cu corrosion were demonstrated.
(Invited) Comparison of Slurry Film Distribution between a Novel Slurry Injection System and Conventional Slurry Application Method
Authors: Zhuang Y. , Sampurno Y. , Wu C. , Wu B. , Mu Y. , Borucki L. , Philipossian A. , Yang Ray
Published: March 2014

In this study, slurry film distribution on an embossed Politex pad was compared between a novel slurry injection system (SIS) and conventional slurry application method. The slurry injector was placed on top of the pad surface and it injected slurry in a thin layer at the device trailing edge using multiple injection points. Slurry was also applied to the pad center area using the conventional slurry application method. A fluorescent dye (4-methyl-umbelliferone) was added to the slurry. The slurry fluoresced under UV light and the fluorescent light was captured by a high resolution charged coupled device camera. Results showed that SIS provided a much more uniform slurry distribution to the pad-wafer interface than the conventional slurry application method.
Exploration of Novel Slurry on Hafnium Oxide Films Chemical Mechanical Planarization
Authors: Feng Yulin , Zhang Kailiang , Wang Fang , Yuan Yujie , Gu Pinchao , Chen Ning , Cai Zhaoyang
Published: March 2014

Hafnium oxide (HfOx) has attracted much more attention because of its superior optical and electrical properties in devices. However, with the decrease in minimum feature size, the requirement on surface planarization of each layer was almost harsh. Thus, chemical mechanical planarization (CMP) of HfOx thin films is one of the key processes to fabricate devices including HfOx functional layer. In this paper, the slurry used for HfOx-CMP was explored as well as the selectivity to SiOx, NaBF4 was added into the slurry as an accelerant to HfOx. The influence of slurry parameters including pH values, concentration and particle size of silica abrasive was investigated. The removal rate and root mean square roughness were measured by white-light interferometer and AFM, respectively. Based on the analysis of the results, it is concluded that 10wt% ~39.9nm silica abrasive at pH=6 has a better performance on HfOx polishing.
(Invited) Zenus®, a New Generation of Colloidal Ceria Abrasive
Authors: Tokuda Jun , Yuasa Manabu , Suda Eisaku
Published: March 2014

Zenus® is a colloidal ceria abrasive for CMP applications with monodispersed, well-crystallized particles of ceria with isotropic faceted morphology. These features of Zenus® HC60 were characterized by SEM/TEM observation, XRD analysis, particle size distribution measurement by laser diffraction particle size analyzer and Zeta potential measurement. The primary particle size of Zenus® HC60 was about 65nm by BET measurement, 80nm by TEM/XRD measurement, respectively. D50 of secondary particle size was 100 nm defined by laser diffraction particle size analyzer. The particle size distribution is smaller and narrower compared to that of calcinated ceria. Zeta potential measurement confirmed well dispersed particle condition.
Wafer Edge Yield Improvement by PMD CMP Process Optimization
Authors: Xu Ying , Zhang Han Xuan , Zhao Runtao Tao
Published: March 2014

New head pressure correction factors are tested and optimized to achieve comparable and acceptable profiles on a mature retaining ring. With application of a correction factor, the edge profile change with a mature retaining ring is less than 50A compared to a new ring. The edge pressure compensation function will be put into 45nm production with longer consumable parts life time and edge performance comparable to profiles at the wafer center as well as ones obtained using a newer retaining ring.
Fundamentals of Ion Implantation Technologies for Image Sensing Devices
Authors: Fuse Genshu , Sugitani Michiro
Published: March 2014

Ion implantation is one of the weightiest operations for image sensing device fabrication. In this paper several impacts of ion implantation for characteristics of image sensors are considered. Among metal contamination, implant damages, micro uniformity and so on, metal contamination is the most important issue for reduction of dark current and white blemish in image pixels and an immediate target of metal contamination level of less than 1E-9 cm-2 at popular implant conditions is successfully achieved. Ultra-high energy implants of 5MeV boron and over 8MeV phosphorous and arsenic for Rp deeper than 3 mm are very attractive to obtain superior characteristics of high-end image sensing devices. Implant damage, scan overlap, implant angle accuracy, and low-energy medium-dose implant are also discussed.
Formation of High-Oriented Epitaxial Ni(Si0.8Ge0.2) on Strained Si0.8Ge0.2/Si(100) via Adding a Thin Ti Interlayer
Authors: Hou C , Ping Y , Zhang Bo , Yu W , Xue Z , Wei X , Gao H , Peng W , Di Z , Zhang M
Published: March 2014

Ultrathin titanium (Ti) interlayer is introduced to the formation of nickel germanosilicide on strained Si0.8Ge0.2/Si(001). After rapid thermal annealing, a uniform flattened NiSi0.8Ge0.2 layer is finally formed. The incorporation of Ti increases the transition temperature from the Ni-rich germanosilicide phase to the mono-germanosilicide phase, and improves the surface and interface roughnesses of Ni(Si0.8Ge0.2). The achievement of the highly-oriented (010) Ni(Si0.8Ge0.2) on (001) Si0.8Ge0.2 is contributed to the balanced silicidation velocity for the existence of Ti interlayer.
Metal eFuse Test-Key Design with Electro-Thermal Modeling for 28 HKMG Technology
Authors: Ma Rice , Shi Xue Jie , Xia ChunQiu , Xu XiaoPeng , Ni Baibing , Chen Larry
Published: March 2014

This paper employs a novel electro-thermal modeling methodology to assist eFuse test-key design. The temperature distribution for eFuse is simulated based on electrical Joule-heating and thermal heat conduction in eFuse and surrounding materials. The electrical Joule-heating strongly depends on the contact pads and wiring shapes. The thermal heat conduction is important for the hot-spot to reach the burn-out temperature range. The final temperature distribution and hot-spot for each type of test-key under preset electrical operation condition depend on material electrical and thermal properties. Thermal boundary conditions are applied to establish thermal equivalent surrounding effects. Test structure design splits include anode/cathode shapes, wiring sizes, and via configurations. Simulated test-key designs with hot-spots in the desired position and failing in the melting temperature range are then selected to build actual test vehicles. This electro-thermal modeling assisted test-key design methodology effectively speeds up the turnaround time and reduces the development cost.
Interfacial Layer Development for 20nm High-k Last Integration Scheme
Authors: Gao Han Jie , Zhao Jie , Min Jia Hua , Zeng Yi Zhi , Awut Kurban , Song Woei Ji , Yu Shao Feng
Published: March 2014

With the characteristic dimension scaling down of CMOS device, the gate leakage increases significantly and the device gets low reliability performance. Then EOT (Equivalent Oxide Thickness) should be decreased, and more performance would be gained with leakage and reliability sacrifice by an optimized dielectric interfacial layer and high-k material. In this paper, the methods to form IL are the key point of EOT scaling down with gate leakage sacrifice and post replacement metal gate (RMG) treatment lead to work function improvement with hysteresis reduction beyond 20nm node of CMOS devices. Based on data analysis we want to get some optimized conditions to make this layer an enhancement in the research of HKMG logic product process development.
(Invited) Dielectric Damage
Authors: Shohet J. Leon , Lin Qinghuang , King Sean W. , Ren He , Banna Samer , Jakes Joseph E. , Agasie Robert J. , Naik Mehul , Nishi Yoshio , Nichols Michael T. , Mavrakakis Konstantinos , Hsu Kaiwen , Guo Xiangyu , Pei Dongfei , Li Weiyi , Choudhury Faraz , Zheng Huifeng
Published: March 2014

More and more high- and low-k dielectrics are used in microfabrication today. However, as is well known, these materials are easily damaged during processing or during operation in a device. Sources of damage include plasma and/or VUV exposure, water uptake, free radicals as well as cosmic rays. A description of the damage effects on dielectrics from water uptake, plasma and/or VUV exposure, and neutron exposure is presented. Although the results for neutron exposure are presented for a high-k dielectric, HfO2, they can easily be extended to low-k dielectrics.
Low-k Reliability Improvement with Optimal Dummy Insertion
Authors: Ma Rice , Shi XueJie , Xia ChunQiu , Xu XiaoPeng , Ni Baibing , Chen Larry
Published: March 2014

To improve low-k film reliability in BEOL, a process modeling methodology is employed to analyze stress and surface morphology evolution during BEOL fabrication process. The stress built-up in low-k dielectrics is found to be directly linked to material density increase, which correlates with laboratory measurement of low-k material volume shrinkage. Densification stress redistribution shows strong dependence on metal layout and curing process, but weak dependence on trench depth and etch stop layer. It is also found that volume shrinkage due to low-k material densification can lead to large vertical displacement, which causes surface recess and unevenness. To mitigate densification induced low-k reliability risks, dummy metal insertion becomes necessary to trade off stress concentration and surface recess. Various dummy insertion schemes are studied and their impacts on low-k material stress and surface recess are evaluated. Dummy metal insertion guidelines for low-k reliability optimization in BEOL structures are developed.
(Invited) A Comparison of Device Architecture, Electrical Performance and Process Flow between FinFET and Planar MOSFETs
Authors: Ju Jian Hua , Shi Xue Jie , Yu Shao Feng
Published: March 2014

In this paper, we compared the device architecture, electrical performance between bulk planar, SegFET, UTBB-SOI and FinFET MOSFETs based on TCAD simulation and we also listed the key fabrication process difference between bulk planar and FinFET devices. Results show that FinFET has best short channel effect (SCE) immunity due to its double gate structure. Hence, FinFET device demonstrates best DC performance, which includes Ion/Ioff, Sub-threshold Swing and DIBL. Analyses also show FinFET has best AC performance: smallest delay and dynamic power consumption. Besides some 20nm technology node’s processes, some brand new processes, such as Fin formation, low-k spacer, poly and HK/MG CMP, SiC/SiGe in-situ doping with Ti-silicide and SAC local interconnects, need to be introduced into the FinFET process flow as a necessary cost of achieving the superior performance.
(Invited) Copper Pillar Bumping Technology-the Promising Ecosystem Changer
Authors: Guo Hong-Yan , Zhang Li , Tan Kim-Hwee , Lai Chi-Ming
Published: March 2014

Copper Pillar Bump (CPB) has become increasing popular during the past 2 years with the OSATs because of the finer pitch and higher electrical performance requirements. CPBs were primarily used in flip chip on leadframe packages of power ICs in early 2003. Nowadays, the mentioned CPB actually specified to its fine pitch flip chip on substrate application. In this paper, the CPB manufacture process flow was illustrated, the bumping process key point and the subsequent assembly and reliability issues were discussed. Also, the CPB patent issue and the potential effects on the OSAT especially for China domestic companies were further discussed.
Accuracy and Uph Challenges and Solutions in Flip Chip Underfill Dispensing
Authors: Morita Akira
Published: March 2014

Flip chip configurations have changed in terms of both their package design and packaging process. These emerging flip chips have become more popular now. Compared to traditional ones, the new flip chips need different dispensing approaches to improve unit-per-hour production, and require more accurate fluid dispensing. Newly developed motion control and stiffer platforms for automatic fluid dispensers have addressed the challenges. This paper shows how the new system achieved significant improvements for both: 27% UPH improvement in packaging a certain flip chip configuration and +/-40um line dispensing accuracy for a few hundred micron tighter clearance from die edge.
Flip Chip Underfill for High Density Semiconductor Packaging
Authors: Qin Suqiong , Tao Jun , Han Jianglong , Yang Qi , Xie Lei
Published: March 2014

The trends of flip chip technology are lead free, reduced bump pitch design, low-k wafer, large die, etc. These technologies bring challenges to flip chip underfill. Lead free solder bumps also have less solder fatigue resistance compared to traditional solder. Low-k materials are mechanically weak and fragile which request underfill have higher modulus and Tg to lower stress on solder bump, and lower modulus and Tg to lower stress on Si die. Flip chip underfill need balances properties, such as Tg, modulus, and CTE. This study did research on hardener, filler and rubber. The new amine chemistry allows for leap in performance in large die, lead-free and low-k applications. The Features of the underfill are Low stress, tailored Tg and modulus, low CTE, High fracture resistance and large processing window.
A Novel Method to Reduce Accumulative Switching Errors in Multi-Sensor Incremental Measurement Systems
Authors: Ji Guofeng , Hu Jinchun , Zhu Yu , Gao Zhenyu , Yu Changliang
Published: March 2014

In order to cope with the problems such as nonlinearity and machining difficulty of large gratings or long reflector in the field of long-range and high-precision displacement measurement, multi-sensor incremental measurement systems that combining with switching operations among different sensors has proven to be a feasible solution. However, with large numbers of repetitive switching operations, the switching errors and subsequently generated accumulation become one of the main obstacles for achieving excellent performance. In this paper, a novel method is proposed to reduce the switching errors and their accumulation in the incremental displacement measurement systems. The initialization constant of each “to-be” used sensor is derived by analyzing the real-time measurement data of the adjacent sensors over an extended period and is used for the switching operations. By theoretical analysis and simulation experiments, the proposed method can effectively reduce the accumulative errors relative to conventional methods.
Smart Review Sampling Methodology in Huge Inspection Results
Authors: Luoh Tuung , Lv Rong , Chen Chi-min , Liao Hsiang-Chou , Yang Ling Wu , Yang Ta-hone , Chen Kuang Chao , Lu Chih Yuan
Published: March 2014

The defect inspection results for advanced technology nodes have extremely high defect counts frequently. Therefore, the defect review Pareto get high false rate due to the SEM non-visual defects, nuisance defects, or dummy fill patterns by traditional review sampling methodology. An integrated smart review sampling methodology is proposed to resolve the high false rate issue and dig out the DOIs and POIs effectively in huge big inspection results with aid of design data base.
2-D Modeling Capability Certification of Optical Critical Dimension (OCD) Metrology Tool by Sigma Shape PMOS Silicon Recess Structure
Authors: Huang Yi , Sui Yun-Qi , Yang Si-Yuan
Published: March 2014

Optical Critical Dimension (OCD) metrology is a much popular and efficient way to monitor structure sizes such as heights, side wall angles (SWAs), and critical dimensions (CDs). Due to the continuous shrinkage of feature sizes, the IC process is becoming more and more complicated. The growing demand on the OCD applications always outpaces the development of OCD-technology capabilities. Thus, we have to find a more reliable method and a special structure to certify the capability of OCD modeling and library stability, so as to improve the measurement performance as much as possible. In this paper, we selected a 2-D Sigma Shape PMOS Silicon Recess (Σ-PSR) structure for the OCD modeling evaluation and established a certification procedure as well as a relevant evaluation method, which includes the design of DOE (Design of Experiment) wafers, the handbook for data collections, the scoreboard for OCD result analysis for verifying both OCD 2-D modeling performance and library stability. The DOE wafers were processed to form different PSR structures such as total silicon recess depth, sigma height, pull back, tip-off-gate, undercut, and spacer width splits, etc. There are 17-output required parameters for the OCD modeling. At least, 9 floating parameters are necessary to build the Σ-PSR model. The accuracy of the DOE trend and the precision, stability, and GRR (Gauge Repeatability and Reproducibility) of all output parameters were analyzed to evaluate the capability of the OCD modeling. TEM data were also collected to demonstrate the OCD performance of Σ-PSR profile monitor. Finally, we summarized the evaluation method and discussed the future OCD certification work by advanced reference metrology tools.
New Approach to Surface Voltage Based Non-Visual Defect Inspection
Authors: Marinskiy Dmitriy , Lagowski Jacek , Wilson Marshall , Findlay Andrew , Almeida Carlos , Edelman Piotr
Published: March 2014

Measurement speed and resolution of surface voltage based non-visual defect inspection are examined. There is a tradeoff between high measurement speed in whole wafer inspection which requires a larger measurement probe and resolution of the method which requires a smaller measurement probe. In this paper we overcome this tradeoff by using different diameter Kelvin probes. Full wafer inspection is performed using a 2mm diameter Kelvin probe enabling high throughput. Only when a suspected failure is detected, an inspection of a localized smaller area is performed with a 10 μm diameter Kelvin probe.
Via Impact on the Upstream Electromigration of 40/45nm Low-k Cu Interconnect
Authors: Zhao Xiang Fu , Wu Jeff , Chang Venson
Published: March 2014

Via impact on the upstream electromigration (EM) of low-k Cu interconnects was investigated based on 40/45nm technology node. It is found that via height is the main factor to affect EM performance. Increasing via height can lead to more early failure. Besides, alloy seed layer and argon power during via deposition are also observed to be two important factors to affect EM lifetime.
SAS JMP Scripted Modeling Approach to Estimate FPGA Process Capability
Authors: Qiao Heng
Published: March 2014

In the development of Field Programmable Gata Array (FPGA) device, cross-factored characterization testing should be prescribed to estimate the effect of long-term process drifting. Process capability is usually estimated on the basis of one normal distribution. But the calculation cannot be applied to the cross-factored experiment data directly. This article is to introduce a novel modeling approach to estimate the process capability of FPGA’s. A statistical model is built to predict the worst case values and estimate the inherent process variation, then calculate process capability indices. Therefore, the process capability indices are not obtained on the basis of one normal distribution. They actually show the worst process capability based on the cross-factored experiment data. An automated tool coded with SAS JMP script language was also developed to optimize the model automatically, and to standardize the data process which includes four interlocked steps.
Effect of SiOx/SiNx Stacked Gate Dielectric Structure on the Instability of a-IGZO Thin Film Transistors
Authors: Shin Dongseok , Cho Edward Namkyu , Park Suehye , Yun Ilgu
Published: March 2014

Among amorphous oxide thin film transistors, amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT) is currently highlightened because of its advantages such as high mobility, transparent characteristic, flexibility and so on. It is required to ensure the stability of the device under various environments has to be verified before high-volume manufacturing. In this paper, the instability of amorphous InGaZnO TFT depending on the SiOx/SiNx stacked gate dielectric material is investigated through bias and light illumination stress test. Here, the TFT’s instability characteristics are examined by the density of total trap states at the channel/gate dielectric interface (Nit).
The Comparison of Various S/D Series Resistances Methods for Deeply Submicron MOSFETs
Authors: Xia Haoguang , Ji Xiaoli , Ma Lijuan , Chen Yuancong , Yan Feng
Published: March 2014

Accurate extraction of source/drain series resistance (Rs/Rd
) is crucial to the modeling and application of deeply scaled MOSFET devices. In this study, we investigate three methods of extracting source/drain series resistance for deep submicron MOSFETs, including the Y-function method, the trans-conductance method and the direct I-V method. The results show that resistance obtained from direct I-V method is smaller than both trans-conductance method and Y function method. Theory analysis illustrate that the trans-conductance method and Y-function method give an overestimation of resistance due to the neglect of the mobility degradation under the relative high gate voltage. Relatively, direct I-V method is a promising method for estimating source/drain resistance in deep submicron MOSFETs.
(Keynote) Requirements for the Emerging Memory Era
Authors: Lee Jung Hoon
Published: March 2014

As current computing system is changing to cope with the exponential growth of data, memory device in the near future should be able to provide huge memory capacity with lower power consumption; changes stem not only from computing system architecture, but from memory hierarchy. However, conventional charge-based memories such as DRAM and FG NAND Flash memory have difficulties in scaling due to the limited number of charges. Therefore, lots of researchers are currently working on emerging memory devices for the future computing system. In this paper we introduce emerging memory devices such as Phase Change RAM (PCRAM), Spin-Transfer Torque MRAM (STT-MRAM), and Resistance change RAM (ReRAM). We discuss the characteristics and scalability of each memory device and summarize the requirements to open the era of emerging memory.
Effect of Trench Depth Variation on Phase Change Memory Operation using Tcad
Authors: Lee Sang Myung , Shin Yong Hyeon , Yun Ilgu
Published: March 2014

As one of non-volatile memory devices, the flash memory is widely used in various areas of applications, especially for mobile application. However, it has problems such as physical nano-scale limitation and reliability. Thus, researchers investigated next-generation memory device candidates which can overcome these problems. The phase change memory (PCM) is one of the attractive next-generation non-volatile memory candidates. As a phase change memory device, both keyhole and μ-trench structures are widely used. Thus, it is crucial to examine the electrical characteristic variation by structure modification. So, in this paper, we analyze the electrical effect of upper side trench depth variation on phase change memory operation.
Effect of Tilted Angle in Trench Structure on Phase Change Memory Operation Using TCAD Simulation
Authors: Shin Yong Hyeon , Lee Sang Myung , Yun Ilgu
Published: March 2014

As the devices have faced limit of shrinking, a lot of candidates rise to lead the next generation of device technology. One of the well-known candidates is a phase change memory (PCM) which is based on a chalcogenide material, called Ge2Sb2Te5 (GST). Principle of PCM operation is decided by changing the phase of GST thermodynamically. Thus, structures of PCM cell such as keyhole and μ-trench are mainly used for Joule heating. However, in the process of making a trench, it has inevitably difference between top and bottom aperture of the trench, and affects electrical properties of PCM. In this study, we build a PCM cell structure using technology computer-aided design (TCAD) and analyze effect of tilted angle of trench on phase change memory operation.
The Temperature Optimization in RF Heating for a MOCVD Susceptor By Using Numerical Methods
Authors: Lu Jin Fu , Hu Chih Kai , Li Tomi T.
Published: March 2014

This analysis of numerical simulation indicates that the temperature distribution is greatly affected by the different distance between the coil and bottom susceptor as well as the coil spaces in a RF MOCVD reactor. This paper concludes that the uniformity in temperature difference with only 2.6 K on the surface of the susceptor can be achieved by adjusting the geometry of coil arrangements. This finding can be also used for a large-size susceptor of reactor for RF MOCVD system in an optimized process.
Study on Resistive Switching Characteristics and Mechanisms of Cu/SiOx/TiN Structure Resistive Random Access Memory
Authors: Chen Ran , Wang Jian Yun , Chen Chang Jun , Zhou Li Wei , Jiang Hao , Shao Xing Long , Zhang Kailiang , Zhao Jinshi
Published: March 2014

In this paper, three kinds of resistive switching device based on Cu/SiOx/TiN structure with different oxygen partial pressures were fabricated to examine and compare their characteristics to explore resistive switching mechanisms. Compared among three samples by I-V characteristics and uniformity, it turns out that 1% oxygen partial pressure device has a better resistive switching characteristic. According to I-V curve fitting, Ohimc and SCLC mechanism were concluded at LRS and HRS. And a resistive switching model is proposed based oxygen vacancies migration. Furthermore, the self-compliance behavior is found and explained.
Effect of Temperature on the Cut off Frequency of AlGaN/GaN High Electron Mobility Transistors
Authors: Yahyazadeh Rajab , Hashempour Z , Soudmand M
Published: March 2014

An analytical- numerical model for the drain source and gate source currents of AlGaN/GaN based HEMTs has been developed that is capable to predict accurately the effects of temperature on the cut off frequency in different gate source and drain source biases. Salient features of the model are incorporated of fully and partially occupied sub-bands in the interface quantum well, combined with a self-consistent solution of the Schrödinger and Poisson equations. In addition, current in the barrier of AlGaN, traps density in AlGaN are taken in to account. The calculated model results are in very good agreement with existing experimental data for HEMTs device.
(Invited) The Random Dopant Fluctuations of Ultra-Scaled CMOS Devices
Authors: Chung Steve S
Published: March 2014

This paper will demonstrate the methodology to understand the dopant fluctuation. The theoretical basis from an experimental discrete dopant profiling technique will first been introduced to analyze the RDF effect. It will be demonstrated on the advanced strain-silicon devices and advanced trigate devices. The discrete dopant distribution along the channel direction will be demonstrated. The dopant variation in a SiGe S/D strained and SiC S/D strained MOSFETs will first be demonstrated to understand the dopant fluctuation behavior. Then, experiments have been extended to the advanced bulk-trigate CMOS devices. The sidewall roughness effect in trigate has also been studied. This approach provides a direct-observation of the random dopant fluctuation (RDF) and is useful for the gate oxide quality monitoring of future generation trigate devices.
Effect of Temperature on the Total Mobility of AlGaN/GaN High Electron Mobility Transistors
Authors: Yahyazadeh Rajab
Published: March 2014

An analytical- numerical model for the total mobility of AlGaN/GaN based high electron mobility transistors has been developed that is capable to predict accurately the effects of temperature on the total mobility in different temperature , gate source biases. In addition taking into account the combined contributions from each of the individual electron scattering mechanisms. Salient features of the model are incorporated of fully and partially occupied sub-bands in the interface quantum well. Close agreement with the experimental data confirms the validity of the present model.
Coexistence of Bipolar and Unipolar in NiO Resistance Switching
Authors: Rite E , Zhang Kailiang , Wang Fang , Sun Kuo , Wang Baolin
Published: March 2014

In this paper, we reported a coexistence of bipolar and unipolar characteristics in Cu/NiO/Pt RRAM cells. We studied the unipolar resistive switching firstly. The Cu/NiO/Pt exhibits an extensibility performance in low power consumption. The reset current is higher than 1 mA when the current compliance is above 1 mA. However, the reset current can decrease to 300 μA when the current compliance decreases to 50 μA. Furthermore, the Cu/NiO/Pt device also shows a bipolar behavior. However, the decreasing reset current phenomenon and bipolar behavior were not observed in Pt/NiO/Pt structure. Then we compared the temperature dependence of the LRS resistance. The two structures showed positive temperature coefficients (α) in low resistance state (LRS), suggesting metallic filaments controlling the LRS. The temperature coefficient (α) of Cu/NiO/Pt structure is lower than that in Pt/NiO/Pt structure, which indicates different metal filaments are formed in the Cu/NiO/Pt structure. It is suggested that the coexistence of bipolar and unipolar and low power consumption is ascribed to the application of Cu electrode to NiO dielectric.
The Optimized Simulation for Uniformity of the Heater Temperature on OLED Source Susceptor
Authors: Kuo Zhe Wei , Hu Chih Kai , Tung Fu Ching , Lin Yi Jiun , Wang Yi Shan , Lai Shih Hsiang , Chen Chien Chih , Li Tomi T.
Published: March 2014

Since the surface evaporation technique is less cost compared to the point evaporation and the line evaporation technique, it is focused by the research and development from major OLED manufacturers recently. In this study, we use the finite element thermal analysis software, ANSYS, to simulate the arrangement of the large-area evaporation with deposition heating source of infrared lamp. Changing the arrangement of the infrared lamp can improve the uniformity on the susceptor surface temperature within ± 1 ~ 3% at 30 ~ 500℃. There are five improvement parameters for the arrangement of infrared lamp heating source: (a) the material of holder, (b) the material of susceptor, (c) the horizon distance between heaters, (d) the vertical distance between heater and cover, (e) the six zones power control. Besides we analyze the heating rate to make it greater than 100℃/min due to the requirement of rapid heating in the evaporation. We also observe the concentration distribution of the evaporation material (source) in the chamber and discuss the deposition efficiency on glass substrate. These studies will be used as base lines for the R2R (run to run) evaporation technologies in the future.
The Thermal Flow Field Optimization of a Self-Assembly MOCVD Vacuum Reactor
Authors: Hu Chih Kai , Chiu Hsien-Chih , Li Tomi T. , Chien Hung-I
Published: March 2014

The effects of operating conditions in a self-assembly of a horizontal reactor for metalorganic chemical vapor deposition are investigated and described by simulation and analysis. The parameters are involved such as space between the top wall and the susceptor (30-60 mm), the reactor top wall temperature (41-161 ºC), the chamber pressure (100-760 torr), and the susceptor rotation rate (0-150 rpm). The simulation results from these listed parameters show that an optimization for an ideal stagnation flow can be achieved in a horizontal reactor
(Invited) Smart Monitoring Systems for a Green Future
Authors: Saupe Ray , Stock Volker , Otto Thomas , Kurth Steffen , Hiller Karla , Meinig Marco , Neumann Norbert , Gessner Thomas
Published: March 2014

MEMS based devices have a huge potential in different monitoring applications ranging from environmental control to medicine. This paper shows principles and advantages of two miniaturized NIR/IR-spectrometers, based on different MEMS technologies. Small size, portability and cost efficiency as well as high accuracy and mechanical robustness make both spectrometers suitable for use in such applications. The paper depicts principles and advantages of both devices. Performance parameters and a selected application, the monitoring of biogas plants to raise their efficiency, are presented.
(Invited) Gas Sensing Properties of Formaldehyde Sensor Based on Zn-, Cu-Doped NiO Thin Film
Authors: Sun Shijiu , Zhang Kailiang , Wang Fang , Yuan Yujie , Han Yemei , Zhang Tiantian , Wang Meng , Li Chunjing
Published: March 2014

Formaldehyde (HCHO) gas sensors have been prepared with pure NiO, Zn-doped NiO and Cu-doped NiO thin films deposited on Si substrates by radio-frequency (RF) reactive magnetron sputtering. The changes of response were studied at different work temperatures (100℃~450℃) and different formaldehyde concentrations(100 ppm ~ 400 ppm). Doping with Zn, the gas response of NiO thin film increased from 36.7% to 51.3% for 400 ppm HCHO. The sensitivity was also improved for the Zn-doped samples for a series of HCHO concentrations ranging from 100 ppm to 400 ppm. The reasons for the significant enhancement of HCHO response by doping Zn and Cu into NiO films were discussed.
(Invited) An X-Band Class-E Power Amplifier with MEMS Output Impedance Tuner
Authors: Lu Yumin , Peroulis Dimitrios , Katehi Linda P. B.
Published: March 2014

This paper presents the design, fabrication and measurements of a hybrid X-band class-E power amplifier with a MEMS output tuner that enables the power amplifier to operate at optimum efficiency and output power level despite the fabrication uncertainties/tolerances of the device and circuit. The tuner is implemented with two 2.8 : 1 analog MEMS varactors and covers an impedance range of resistance between 10 to 30 Ω and reactance of -3 to -9 Ω. The designed PA delivers 605 mW output power with power added efficiency of 52% at 10.5 GHz.
(Invited) Effect of Annealing Temperature and Surface Adsorption（Fe-，Pd-） on SnO2 Gas Sensor
Authors: Zhang Tiantian , Zhang Kailiang , Yuan Yujie , Wang Fang , Han Yemei , Sun Shijiu , Sun Kuo , Fang Huayong , Li Kai
Published: March 2014

In this work, the response characteristics of PdCl2- and FeCl2-coated RF-sputtered SnO2 thin films for methane detection was reported. Influence of annealing temperature on the response characteristics was investigated for the pure sample and coated samples. The experimental results demonstrated that 1wt% PdCl2 annealed at 350℃ showed a high response for 200 ppm of methane at 200℃. It is also indicated that the annealing process increases the amount of adsorbed oxygen present on the SnO2 thin film surface and enhances the penetration of Pd into films, the combined effects likely contribute to the improvement of the response characteristics.
(Invited) Design and Simulation of a Novel Shock Accelerometer Based on Giant Piezoresistance Effect
Authors: Sun Zhen Yuan , Li Meng Wei , Liu Ze Wen
Published: March 2014

The design of a novel eight-beam uniaxial shock accelerometer is presented. This new multi-beam structure has a advantage of high anti-disturbance capability. The designed measurement rang of the sensor is 150,000g and the sensitivity is 23.4μV/g, which is about 20 times higher than conventional sensors of same measurement rang due to the exploiting of the giant piezoresistance effect in silicon nanowires. This achievement opens up new developments in the area of shock experiments where the high overload capability and high sensitivity are both needed.
(Invited) The Effects of Doping Pattern on Lattice Thermal Conductivity of Silicon Nanowires
Authors: Zhang Yuan Bo , Bi Ke Dong , Chen Wei Yu , Chen Min Hua , Chen Yun Fei
Published: March 2014

The thermal conductivity of silicon nanowire doped with Germanium in different geometrical distributions was investigated with nonequilibrium molecular dynamics method. Five different geometrical arrangements of the impurities that influence the thermal conductivity properties of silicon nanowires were investigated, which include centralization doping, uniform doping, non-uniform doping, random doping and cubic pattern doping. The results demonstrate that the uniformity of the impurity positions has a substantial influence on the thermal conductivity of silicon nanowires under the same impurity concentration.