Simulating dataflow accelerators for deep learning application in heterogeneous system
Authors:   , Hoang Quang Anh , Das Anup 
Published: November 2022

For the past few decades, deep learning has emerged as an essential discipline that broadens the horizon of the knowledge of humankind. At its core, Deep Neural Networks (DNN) play a vital role in processing input data to generate predictions or decisions (inference step), with their accuracy ameliorated by extensive training (training step). As the complexity of the problem increases, the number of layers in DNN models tends to rise. Such complex models require more computations and take longer to produce an output. Additionally, the large number of calculations require a tremendous amount of power. Therefore, improving energy efficiency is a primary design consideration. To address this concern, researchers have studied domain-specific architecture to develop highly efficient hardware tailored for a given application, which performs a given set of computations at a lower energy cost. An energy-efficient yet high-performance system is created by pairing this application-specific accelerator with a General-Purpose Processor (GPP). This heterogeneity helps offload the heavy computations to the accelerator while handling less computation intensive tasks on the GPP. In this thesis, we study the performance of dataflow accelerators integrated into a heterogeneous architecture for executing deep learning workloads. Fundamental to these accelerators is their high levels of concurrency in executing computations simultaneously, making them suitable to exploit data parallelism present in DNN operations. With the limited bandwidth of interconnection between accelerator and main memory being one of the critical constraints of a heterogeneous system, a tradeoff between memory overhead and computational runtime is worth considering. This tradeoff is the main criteria we use in this thesis to evaluate the performance of each architecture and configuration. A model of dataflow memristive crossbar array accelerator is first proposed to expand the scope of the heterogeneous simulation framework towards architectures with analog and mixed-signal circuits. At the core of this accelerator, an array of resistive memory cells connected in crossbar architecture is used for computing matrix multiplications. This design aims to study the effect of memory-performance tradeoffs on systems with analog components. Therefore, a comparison between memristive crossbar array architecture and its digital counterpart, systolic array, is presented. While existing studies focus on heterogeneous systems with digital components, this approach is the first to consider a mixed-signal accelerator incorporated with a general-purpose processor for deep learning workloads. Finally, an application interface software is designed to configure the system's architecture and map DNN layers to simulated hardware. At the core of this software is a DNN model parser-partitioner, which provides subsequent tasks of generating a hardware configuration for the accelerator and assigns partitioned workload to the simulated accelerator. The interface provided by this software can be developed further to incorporate scheduling and mapping algorithms. This extension will produce a synthesizer that will facilitate the following: · Hardware configuration: generate the optimal configuration of system hardware, incorporating the key hardware characteristics such as the number of accelerators, dimension of processing array, and memory allocation for each accelerator. · Schedule of execution: implement a mapping algorithm to decide on an efficient distribution and schedule of partitioned workloads. For future development, this synthesizer will unite the first two stages in system's design flow. In the first analysis stage, simulators search for optimal design aspects under a short time frame based on abstract application graphs and the system's specifications. In architecture stage, within the optimal design region from previous stage, simulators refine their findings by studying further details on architectural level. This inter-stage fusion, once finished, can bring the high accuracy of architectural-level simulation tool closer to analysis stage. In the opposite direction, mapping algorithms implemented in analysis tools can provide architectural exploration with near-optimal scheduling. Together, this stack of software can significantly reduce the time searching for specifications with optimal efficiency.