a Unique 3D Integration Approach for SOI Substrates - Mating Device Layer CVD W Filled Tsvs with Handle Layer ECD Cu Filled Tsvs
Authors: Hollowell Andrew E , Arrington Christian L. , Bauer Todd , Blain Matthew , Dominguez Jason , Goeke Ronald S. , Heller Edwin , Jarecki Robert , Loviza Rebecca , McClain Jaime , Menk Lyle Alexander , Pillars Jamin Ryan , Resnick Paul , Timon Robert 
Published: February 2020

In recent years microelectronic packaging development has focused on 3D integration in order to compensate for the decrease in traditional Moore’s Law scaling. 3D integration allows increased I/O counts, lower RC time constants, lower power consumption, and better thermal sinking. Furthermore, 3D integration decreases areal density through stacking chips and connecting their electrical signals with through substrate vias (TSVs) as opposed to wire bonding. A significant amount of development has been achieved integrating TSVs with standard silicon (Si) substrates; however, very little development has been made integrating this technology with silicon-on-insulator (SOI) substrates1. Certain MEMS applications take advantage of the use of SOI wafers with relatively thick device layer silicon, however the integration of TSVs with these unique SOI substrates (e.g., 600um handle, 1um buried oxide, and 25um thick device layer) presents distinct challenges when making electrical connections through the device layer Si, buried oxide (BOX), and the handle Si. This is particularly true for cases in which the handle Si is not thinned. In this work, we present a novel TSV integration approach in which electrochemical deposition (ECD) is used to connect copper (Cu) vias, filled in the handle of the substrate, to tungsten (W) vias filled by chemical vapor deposition (CVD) in the device layer of a SOI substrate.

Deep reactive ion etching (DRIE) has become the most accepted process for creating TSVs when working with semiconductor materials. After forming the vias, chemical vapor deposition, atomic layer deposition (ALD), and/or electrochemical deposition are used to deposit an insulating material for electrical isolation, a barrier layer to prevent diffusion, and a conductive material for electrical connection. CVD is typically used for all three of these purposes if the film thicknesses and aspect ratios are small enough and geometries are not overly complex. ALD is utilized for both the insulating layer and the diffusion barrier when CVD is not capable of conformally coating intricate geometries. ECD is used to fill the vias with a conductive material when via dimensions are too large for CVD, which is common in MEMS applications.

This work will utilize DRIE for etching topside vias through the device layer Si and CVD for filling these vias with W. DRIE is also used for etching the handle Si and BOX layers using a hardmask on the backside of the substrate. Two approaches are investigated and presented for utilizing ECD to form Cu TSVs and connect the backside of the wafer to the W TSVs imbedded in the device layer of the SOI substrate. In both of these approaches, ALD is used to deposit a conformal layer of Al2O3 to isolate the TSVs from the handle Si. A spacer etch is performed to remove the Al2O3 from horizontal surfaces, revealing the W TSVs previously fabricated in the device layer Si. The first approach is to fill the TSVs with Cu from the bottom up, initiating plating from a seed layer deposited only at the bottom of the backside vias. This approach allows a conventional makeup chemistry to be used with sulfuric acid (H2SO4) as the electrolyte in conjunction with a periodic reverse plating regime. The second approach is to fill the vias from the outside in, initiating plating from a conformal platinum (Pt) seed layer deposited by ALD and using methanesulfonic acid (MSA), rather than H2SO4, as the makeup chemistry electrolyte2. The higher solubility of Cu in MSA (80g/L) compared to H2SO4 (50g/L) reduces mass transport limited depletion of Cu ions in the vias, leading to conformal Cu deposition throughout the depth of the vias. The advantages, disadvantages, and challenges associated with each of these two integration approaches will be presented.

Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

G-K. Lau, J. Soon, H-Y Li, K. Chui, and Y. Mingbin, “Process Integration and Challenges of Through Silicon Via (TSV) on Silicon-On-Insulator (SOI) Substrate for 3D Heterogeneous Applications.” 17th Electron. Packaging Tech. Conf., (2015).

S. K. Cho, M. J. Kim, and J. J. Kim, “MSA as a Supporting Electrolyte in Copper Electroplating for Filling of Damascene Trenches and Through Silicon Vias.” Electrochemical and Solid-State Letters, 14 (5) D52-D56 (2011).