(Invited) Vertical Tunnel FET Technologies Using III-V/Si Heterojunction
Authors: Tomioka Katsuhiro , Gamo Hironori , Motohisa Junichi 
Published: February 2020

Conventional field-effect transistors (FETs) have inherent issues for lowering supply voltage because there is physical limitation of subthreshold slope (SS = 2.3 k
BT/q = 60 mV/dec), which determine supply voltage of FETs. This limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented. Thus, non-thermionic switches achieving steep SS have attracted much attentions as a building blocks for future low-power integrated circuits. Among the switches, tunneling FET (TFETs) are promising alternative FETs because their good Si-CMOS compatibility and very small off-state leakage current due to band offset across the tunnel junction. There are, however, still challenges in achieving steep SS with wide range of current, high conductance, and complementary operation. In this talk we reported on recent technologies for vertical TFET using III-V/Si tunnel junctions [1,2], which is formed by selective-area growth of III-V nanowires (NWs) on Si [3-5], and demonstrated vertical TFETs with steeper SS below physical limitation. Next, we investigate current-boosting technologies by using core-shell structure induced strain and modulation-doping of the NW-channels. Moreover, we demonstrate complementary switching operation with very steep SS and very high transconductance efficiency by using same device architecture.

This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials.

As for integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping. Thus, we integrated the InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [6]. Sn was used for n-type dopant, and Zn-pulse doping technique [7] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-long in this case).

AS for high-performance TFETs, we demonstrated a high-performance switch using a vertical nanowire-channel consisting of InGaAs/Si tunnel junction with two-dimensional electron gas. The device exhibit rapid enhancement in conductance with steep slope over four magnitude of decades, and complementary switching operation by inverting the ground terminal (minimum slope of 25 mV/decade as n-channel, or 6 mV/decade as p-channel at 0.25 V). Furthermore, the transconductance efficiency, meaning the current efficiency of integrated circuits, exceeds the theoretical limit in conventional circuits which was around 1900 /V (physical limitation of conventional MOSFET is 38.5 /V).

References

[1] K. Tomioka and T. Fukui, Appl. Phys. Lett., 98, 083114-1 – 3 (2011).

[2] K. Tomioka and T. Fukui, Appl. Phys. Lett., 104, 073507-1 – 4 (2014).

[3] K. Tomioka et al., Nano Lett., 8, 3475 – 3480 (2008).

[4] K. Tomioka et al., Nanotechnology, 20, 145302 – 145309 (2009)

[5] K. Tomioka et al., Nature, 488, 189 – 192 (2012).

[6] K. Tomioka et al., Nano Lett., 13, 5822 – 5826 (2013)

[7] K. Tomioka et al., IEEE IEDM Tech. Dig. 88 – 91 (2013).