(Invited) Recent Progress in 4H-SiC CVD Growth for High-Voltage Power Devices
Authors: Tsuchida Hidekazu , Kamata Isaho , Hoshino Norihiro , Murata Koichi , Miyazawa Tetsuya 
Published: February 2020

This paper reports recent progress in 4H-SiC CVD growth, aiming to obtain high-quality epilayers and bulk crystals with a high productivity for high-voltage power devices.

The production of 150 mm-diameter 4H-SiC wafers has become the industry standard and the practical use of 4H-SiC unipolar devices such as Schottky barrier diodes and MOSFETS with a blocking voltage from 600 to 3,300 V started in various fields, including power conditioners for photo voltaic systems, air conditioning equipment, power supplies for IT and manufacturing industries, and inverters for electric cars and trains. Although bipolar devices such as PiN diodes and IGBTs may be more suitable for very high-voltage classes over ten kilo volts, the practical application of the bipolar devices is hindered because of the degradation phenomenon (“bipolar degradation”) in which forward on-state voltage of the devices increases after current stress applied due to the expansion of stacking faults in the crystal during current conduction.

Based on the current understanding on the bipolar degradation phenomenon, basal plane dislocations (BPDs) are responsible for the nuclei of expanding single Shockley stacking faults (1SSFs) and the expansion of the 1SSFs is activated by minority carrier injection exceeding a certain level. Although epilayers with low-density BPDs (< 0.1 cm-2) were obtained by enhancing the conversion of BPDs in the substrate to threading edge dislocations (TEDs) at the beginning of epitaxial growth, the expansion of 1SSFs from the BPD segments below the conversion points was confirmed in the high current density operation [1]. This can be understood due to the injection of minority carriers into a region below the BPD-TED conversion points located near the epilayer and substrate interface or in the substrate where high-density BPDs (102 cm-2) are existing. Meanwhile, inserting a buffer layer with a short carrier lifetime between the substrate and drift epilayer has been proposed to prevent minority carrier injection into a region where BPDs remain.

At this time, a thinner buffer layer is more preferable and a technique to obtain shorter carrier lifetimes compatible with the practical epitaxial growth and device fabrication processes will be promising. High nitrogen (N) doping yielding high-density free electrons has been shown as a promising method to enhance direct and Auger recombination and reduce carrier lifetimes [2, 3]. Short carrier lifetimes of 66-120 ns were obtained at RT-250 ºC for an epilayer doped with N at 5×1018 cm-3. We also attempted intentional vanadium (V) doping during epitaxial growth of a buffer layer to realize much shorter carrier lifetimes. The highly N+V-doped epilayer (N=5×1018, V=7×1014 cm-3) shows very short carrier lifetimes of ~20 ns or less at RT-250 ºC. Inserting a N- or N+V-doped buffer layer between a substrate and n- drift epilayer in the PiN diodes was confirmed to be effective to prevent the formation of 1SSFs from BPDs in the substrate.

Besides continuous improvements in the quality of wafers, the strong demand to cut the cost of 4H-SiC devices from the application side may request to promote wafer productivity. Meanwhile, the development of 200 mm-diameter wafers has been demonstrated by sublimation growth in past conferences. Apart from enlarging wafer diameter, massively enhancing the growth rate or ingot length may pose the ultimate challenge in 4H-SiC bulk growth and trials featuring solution and high-temperature CVD growth methods are now underway. For high-temperature CVD growth, we attempted fast bulk crystal growth of 4H-SiC at a seed temperature of 2350-2550ºC using an H2-SiH4-C3H8-N2 gas system in a vertical CVD reactor [4]. By adjusting process parameters to enhance growth rates and improve crystal quality, fast 4H-SiC crystal growth at a growth rate exceeding 3 mm/h was achieved while maintaining the low dislocation density (threading screw dislocations: ~2.5×102 cm-2) of the seed crystal.

A part of this work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics/Consistent R&D of next-generation SiC power electronics” (funding agency: NEDO).

[1] A. Tanaka et al., J. Appl. Phys. 119, 095711 (2016), [2] T. Tawara et al., J. Appl. Phys. 120, 115101 (2016), [3] T. Tawara et al., J. Appl. Phys. 123, 025707 (2018), [4] N. Hoshino et al., J. Cryst. Growth 478, 9 (2017).