bluuebunny/crossref_metadata_2025 huggingface dataset:
Low Silicon and SiGe Loss in High Dose Implant Resist Strip
Authors: Meng Xiao-Ying , Shen Man-Hua , Huang Yi , Zhang Hai-Yang , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2011

The loss of both silicon and silicon germanium in resist strip process has attracted much attention for generic device development. Such loss mainly stems from the substrate re-oxidation during strip. In this paper, we focus on the high-dose implant resist strip to investigate the re-oxidation of substrate Si and SiGe without compromising the removal capabilities of photoresist (PR) and residue. Besides, the impact of ashing gas ratio on SiN offset spacer critical dimension (CD) is also addressed. Specifically, we studied the substrate re-oxidation performance under various ash process parameters such as pressure, gas ratio, pin position, process time in crust and over-ash (OA) steps. Aside from the re-oxidation effect, we also compared the defect removal capabilities with the above ashing conditions and the dependence of SiN offset spacer CD on ash gas ratio. Results indicate A) The high pressure in preheat step coupled with the low pressure in main-step can effectively preclude Si/SiGe loss. B) For SiGe substrate, the lower ratio of O2/forming gas (FG) exhibits the different impacts between N-MOS and P-MOS implant condition. C) Less OA time brings to better performance for residue removal. D) Continuous offset spacer CD shrink is noticed in each step of lightly doped drain (LDD) loop. The optimized strip scheme delivers not only a residue-free process with the minimum substrate loss but also the improved device performance on both N-MOS and P-MOS.
Effluent Management for Non-Oxidizing Plasma Strip Processes
Authors: Luo Shijian , Waldfried Carlo , Escorcia Orlando , Berry Ivan , Geissbühler Phillip , Srivastava Aseem , Roh Dwight
Published: March 2011

This paper reports on the techniques employed to control the re-deposition of the partially dissociated organic photoresist (PR) by-products in advanced non-oxidizing strip processes developed to meet the PR removal requirements of future technology nodes. System features, such as the design of heated process chamber walls and an on-board, RF-based oxygen plasma effluent abatement system are described in detail. The performance of these features to prevent or eliminate hydrocarbon buildup and manage effluent with non-oxidizing strip processes is also presented and discussed.
The Study of Dry Etching Process on Plasma Induced Damage in Cu Interconnects Technology
Authors: Zhou Jun-Qing , Zhang Hai-Yang , Sun Wu , Wang Xing-Peng , Hu Min-Da , Li Fan , Fu Li-Ya , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2011

As CMOS is rapidly shrunk and the plasma processing steps are increased in number at 65nm node and beyond, plasma-induced damage (PID) has become a serious reliability problem in state-of-the-art semiconductor manufacturing. In this paper, we only focus on the PID issues originating from the dry etching processes in back-end-of-the-line and utilize the in-line test structure to in-situ debug the possible PID impact from the specific layer. The effects of various etching process parameters such as power, power frequency, magnetic field and process time are examined. Results demonstrate metal 1 (M1) etch, passivation etch and Al-pad etch play the critical role in PID performance on the given test vehicles. Nevertheless, their sensitivities are quite different between N-MOS and P-MOS. Basically, N-MOS degradation strongly depends on Al-pad etch while P-MOS PID performance is closely related to M1 etch and passivation etch. More specifically, the over-etch percentage in M1 etch is one of effective knobs in alleviating PID while it is not in passivation etch. All the above discrepancies indicate the single PID failure mechanism could not be applied. We tentatively explain the existing phenomena from the point view of electron shading effect (ESE), reverse electron shading effect (RESE), plasma non-uniformity, photo-conductive effect and ultra-thin charging collector during the interface switch in etching.
Atomic-Layer Deposition of Lutetium Aluminate Thin Films for Non-Volatile Memory Applications
Authors: Adelmann Christoph , Swerts Johan , Conard Thierry , Brijs Bert , Franquet Alexis , Hardy An , Tielens Hilde , Opsomer Karl , Moussa Alain , Van Bael Marlies K. , Jurczak Malgorzata , Kittl Jorge A. , Van Elshocht Sven
Published: March 2011

Thin LuxAl2−xO3 films were deposited by atomic-layer deposition using Lu(thd)3, and TMA in combination with O3 as oxidizer. High-quality dielectric films were obtained with good process con-trol. The full range of the Lu/(Lu+Al) composition was found to be accessible. The films showed bulk density and low roughness. As a result, this process enables the study of LuxAl2−xO3 as dielectric in advanced non-volatile memory devices.
Evolution of STI Gap Fill Technology
Authors: Chen James C. , Chen Yingjie , Gao Rong , Cheng Charley , Li Xianyuan , Zhao Ganming , Chan Diana , Lee Terrance
Published: March 2011

As the IC industry progresses along the ITRS roadmap, continually producing more demanding devices at each technology node, new processes are required to realize yields necessary for success. In this paper, we present and review the evolution of STI (Shallow Trench Isolation) application, and recent developments in the High-Density Plasma Chemical Vapor Deposition (HDP CVD) process and High Aspect Ratio Process(HARP) CVD process. Aspects relevant to the HDP CVD process and using different process to achieve gap filling, and planarization are discussed.
Metal Inserted Poly-Si Stacks with La2O3 Gate Dielectrics for Scaled EOT and VFB Control by Oxygen Incorporation
Authors: Kawanago Takamasa , Kakushima Kuniyuki , Ahmet Parhat , Tsutsui Kazuo , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori Takeo , Iwai Hiroshi
Published: March 2011

Metal-Inserted Poly-Si (MIPS) stacks for gate oxide scaling have been presented with La2O3 gate dielectrics. An equivalent oxide thickness (EOT) of 0.69nm can be achieved with good interfacial property by high temperature annealing. The flatband voltage (VFB) can be modulated by oxygen incorporation in conjunction with Si removal process while EOT degradation is less than 1Aå.
Evaluation of Metallization Options for Advanced Cu Interconnects Application
Authors: Jourdan Nicolas , Carbonell Laureen , Heylen Nancy , Swerts Johan , Armini S. , Caro A. Maestre , Demuynck S. , Croes K. , Beyer G. , Tökei Zsolt , Elshocht S. Van , Vancoille E.
Published: March 2011

The traditional Cu interconnect barrier/seed process consisting of PVD-Ta based barrier/Cu-seed will reach its limit between 20 nm and 30 nm wide trench dimension. To extend Cu interconnect technology further, possible solutions such as PVD-RuTa, PEALD-Ru-based, CVD-Co, PVD/CVD-self-formed-MnSixOy and self-assembled monolayers (SAMs) are studied. It is shown that both PVD-RuTa and CVD-Co possess the so-called seed enhancement capability allowing Cu filling of narrow recesses. However, they exhibit limitations in terms of Cu-diffusion barrier efficiency, electromigration reliability and scalability. Despite, the concept of SAM [NH2-SAM(C3)] as Cu diffusion barrier is demonstrated, it requires maturity and compatibility within the process flow (e.g. adhesion with the Cu overlayer). Finally, it is considered that PEALD-Ru-based alloys and CVD-based MnSixOy films are serious candidates for sub-30 nm wide trench technologies because of their conformal nature and ability to act as an efficient Cu diffusion barrier in the range of 2 nm thickness.
Fine Pitch Micro-Bump Interconnections for Advanced 3D Chip Stacking
Authors: Zhang Wenqi , Limaye Paresh , La Manna Antonio , Beyne Eric , Soussan Philippe
Published: March 2011

3D integration requires the realisation of electrical interconnects between multiple vertically stacked Si devices. Solder based, fine pitch, micro-bump connections are a promising approach for making die-to-die or die-to-wafer interconnections mainly due to its lower bonding temperature as compared with Cu-to-Cu thermo-compression bonding. This paper presents thin die stacking using Cu/Sn micro-bumps with dies containing Through Silicon Via (TSV). Two different approaches named Transient Liquid Phase (TLP) bonding and Solid State Diffusion (SSB) bonding are investigated.
Effect of Film Thickness on Resistance Switching Characteristics for Cu/NiO/Pt Structure
Authors: Zhang Yang , Zhang Kailiang , Fang Wang , Wei Xiaoying , Zhao Jinshi
Published: March 2011

The effect of NiO film thickness on resistance switching characteristics of a Cu/NiO/Pt structure is investigated. I-V results show that forming voltage decreases with the reduction of film thickness, and finally drops down to the set voltage. NiO film thickness should be controlled under a typical thickness in order to implement lower power consumption device design. The underlying mechanism of the phenomenon is attributed to the important role that Cu atoms play in the structure. Due to redox existing in the interface between Cu and NiO film, Cu atoms are ionized and pushed to the opposite electrode when the positive voltage is applied to Cu electrode, Cu conductive filaments are formed. In opposite, Cu atoms lost their electrons and are pushed off from Pt electrode when the positive voltage is applied to the Pt electrode, resulting in the rupture of Cu filaments.
Optical Constants of ZnO Films
Authors: Huang Bo , Yang Huidong
Published: March 2011

ZnO films have been deposited on glass slides by RF magnetron sputtering under different power. The optical constants of the ZnO films have been determined by employed the Kramers-Kronig theory to obtain the spectral dependence of the real part of the refractive index. The advantage of this method is apparent for it only using the transmittance and reflectance spectra of the films.
Study of the Electrical and Optical Properties of the Silicon Carbide Thin Film
Authors: Luo Rui , Yang Huidong , Huang Bo , Xu B. Y.
Published: March 2011

Using the technology of Plasma Enhanced Chemical Vapor Deposition (PECVD), the boron-doped SiC thin films were prepared with the gas of SiH4,CH4, H2 and B2H6, the effects were investigated on the electrical and optical properties of the film caused by varying the carbon content and the concentration of boron doping. The results showed that when the flow ratio of CH4/SiH4 ranged from 0.3 to 0.4 and the flow ratio of B2H6/SiH4 ranged from 0 to 0.1, the optical band gap of the film was above 2.2eV, and the electrical conductivity was above 1×10-7 S/cm. The parameters of the ranges met the requirements on the aspects of electrical and optical properties as window layer for the solar cell.
Influence of Vacuum-Annealing Temperature on the Properties of Direct Current (DC) Magnetron Sputtered ZAO Thin Films
Authors: Shi Jundai , Yang Huidong , Huang Bo , Xu Baoyu , Yu Song
Published: March 2011

This study focused on the properties of optics and electrics as well as microstructure and morphology of the ZAO thin films which were annealed at different temperature. After vacuum-annealed at 160° or above, the films' quality can be significantly improved. The growth along (002) direction of ZAO thin films were found to be faster than the ZAO films which were not treated and reached a maximum at 330°. FWHM decreased to 0.74°at 330° and grain size grew to 12.02039nm at 400°. The shape of crystal grain changed from anomalous formation to roundness. At the same time, the resistivity of ZAO thin films decreased and reached a minimum of 9.36×10-4Ω•cm while the average transmittance increased to 82% in visible region.
Study of Phosphorus Out-Diffusion from High Density Plasma CVD Phosphosilicate Glass Process
Authors: Min Li , Ying Zhang Zi , Xu Qiang
Published: March 2011

High Density Plasma (HDP) CVD phosphosilicate glass (PSG) process applied on pre-metal dielectric (PMD) layer has plasma damage concern which can impact the device performance and reliability. A PETEOS cap layer is used for the plasma damage reduction. In this paper, the diffusion of phosphorus through PSG to PETEOS cap layer is investigated. The PMD film stack consists of 2000A PSG/6000A PETEOS. Secondary Ion Mass Spectroscopy (SIMS) was used to measure the P distribution in the PMD film stack. Transmission Electron Microscope (TEM) was used to confirm the contact glue layer and W encroachment along with the PSG and PETEOS interface. We found that with plasma treatment or DI-water cleaning to the PSG surface could effectively reduce the P accumulation at the interface. We also found that HDP USG transition layer between PSG and PETEOS could inhibit P out-diffusion. The fundamental of P out-diffusion also has been discussed at this work.
Effects of Substrate Temperature on Resistive Switching of TiOX Thin Film
Authors: Wang Lanlan , Zhang Kailiang , Fang Wang , Song Kai
Published: March 2011

Titanium oxide thin films (TiOx) were deposited on Cu (111)/Ti/SiO2/Si substrates by reactive sputtering with various substrate temperatures, ranging from room temperature (RT) to 350°. X-ray diffraction (XRD) analysis showed that the TiOx film at RT was amorphous. In contrast, some sub-stoichiometric oxide films (Ti2O3 and Ti3O5) were formed with the temperatures ranging from 200 to 350°. In addition, the peak of (104) Ti2O3 phase became higher before disappeared at 350° with substrate temperatures increasing from 200 to 300°. Electrical test results showed that both films deposited at 350° and RT exhibited stable resistance switching behaviors, while the sample at 350°C yields a set and reset voltage as low as 0.58V and 0.45V, respectively. However, the fluctuation of Vreset for the samples became too large for resistive switching to be reversible when the temperature increased from 200° to 300°.
Electrical and Optical Properties of Zinc Oxide Thin Films Deposited by Magnetron Sputtering
Authors: Ding Xiaoqin , Lai Yunfeng
Published: March 2011

The Al doped ZnO(ZnO:Al) films were deposited on glass substrates with direct current (DC) or radio frequency (RF) magnetron sputtering by using an alloy or ceramic target. The influence of the substrate temperature on the crystal structure, surface morphology, optical and electronic properties of the ZnO:Al films was investigated. Highly transparent ZnO:Al films with optical band gap of 3.25-3.29eV were deposited by sputtering a ceramic target. The X-ray diffraction results show that all ZnO:Al films grow in a hexagonal-wurtzite phase with highly c-axis preferred orientation and the average crystal size increases upon the promotion of substrate temperatures. The resistivity of ZnO:Al films decreases with an increasing substrate temperature. The resistivity further decreases to 3.566×10-3 Ω•cm with annealing in nitrogen.
Challenges and Mechanisms of CMP Slurries for 32nm and Beyond
Authors: Morinaga Hitoshi , Tamai Kazusei
Published: March 2011

CMP slurries for 32nm and beyond are required to effectively planarize surfaces with fine and delicate device patterns without causing any nanodefects, without contributing nanocontaminants, and without generating atomic-level-roughness. Key solutions to these challenges are material removal using homogeneous and efficient mechanical action, surface protection using appropriate additives, and thorough contamination control (from large particles to dissolved gasses and light). The important parameter for mechanical action with abrasives is friction energy. Key factors to increase friction energy are: i) the number of active particles, ii) the contact area of each particle, and iii) the friction coefficient of each particle. These factors can be controlled with size, shape, morphology or surface charge of abrasive particles. Controlling abrasive shape and surface charge are especially important to achieve higher removal rate.
Overcome Challenges in TSV CMP via Slurry Formulation
Authors: Luo Kai , Wang Carl , Jing Jianfen , Xu Sunny
Published: March 2011

Along with the advancement of IC 3D technology, TSV (through silicon via) has been paid close attention to practically enable the 3D integration and packaging processes with addressing various technical and economical concerns in most recent years. Due to its intrinsic nature of the via size and the amount of via filling materials, the technical requirements in TSV CMP are much more different than those in traditional IC CMP technology. These technical difficulties form new challenges for CMP users to enable TSV CMP process in 3D technology in IC industry. In this work, we are going specifically present some slurry formulation work to demonstrate how to address some of these challenges in two TSV CMP applications.
Investigation on the Correlationship between Process Performances and Composition of CMP Slurry Designed for GST Alloy Polishing
Authors: Pang Keliang , Chen Feng , Jiang Li , Li Mingqi , Zhong Min
Published: March 2011

Newly developed technology utilizes phase change materials in integrated circuit to produce a new type of memory device, namely PRAM. The delicate design of such device poses new challenges for CMP (Chemical Mechanical Polishing), which is one important process to construct memory cells in PRAM. In this paper, recent efforts in developing slurries for GST CMP are described. The preliminary investigation focuses on some of the most concerned issues in GST CMP, such as GST removal rate and removal rate selectivity, post-CMP surface roughness, galvanic effect between different materials and composition consistency of GST alloy. Performance of the testing slurries is analyzed on a laboratory level using physical analytical instruments, such as SEM, EDX, AFM, as well as electrochemical analytical tools.
Fundamental Characterization Studies of Condensed Chemical Mechanical Polishing Waste Slurry
Authors: Yamada Yohei , Kawakubo Masanori , Watanabe Shusuke , Sugaya Takahiro
Published: March 2011

We investigated the possibility of efficiently reclaiming fumed silica slurry in an oxide chemical-mechanical polishing (CMP) process in order to reduce the cost of consumables. We demonstrated the feasibility of reclaiming condensed waste slurry for reuse. The reclaimed slurry had a ten-fold increase in number of particles larger than 0.56 μm over the original slurry. However, there was significant decrease in the number of particles larger than 1.01μm in the reclaimed slurry compared with that in the original one because depth filters used during reclamation effectively remove agglomerated particles and foreign materials from the condensed waste slurry. The removal rate and uniformity of the reclaimed slurry was comparable with original one. Even though there was a slight increase in particles on the wafers, no changes in level of micro-scratches on wafers was observed. Therefore, the CMP performance of the reclaimed slurry is comparable to that of the original one.
Correlation of Pad Topography, Friction Force and Removal Rate during Tungsten Chemical Mechanical Planarization
Authors: Sampurno Yasa , Rice Adam , Zhuang Yun , Philipossian Ara
Published: March 2011

The evolution of coefficient of friction and removal rate during 8.5 hours of tungsten chemical mechanical planarization is correlated to pad surface topography via a novel pad surface descriptor termed 'abruptness'. Interferometric analysis results indicate that during the first 2.5 hours of polishing, pad abruptness remains stable. After 5.5 hours, pad abruptness decreases (i.e. surface becomes smoother). Results from polishing show similar trends whereby removal rate and coefficient of friction are stable during the first 2.5 hours period and decrease significantly thereafter. The coefficient of correlation between pad abruptness and coefficient of friction as well as pad abruptness and removal rate are 0.98 and 0.77, respectively.
Tribological and Kinetical Analysis of Barrier Metal Polishing for Next Generation Copper Interconnects
Authors: Duyos Mateo Ricardo , Gu Xun , Nemoto Takenao , Sugawa Shigetoshi , Zhuang Yun , Sampurno Yasa , Philipossian Ara , Ohmi Tadahiro
Published: March 2011

In this study, the tribological, thermal and kinetic attributes of Ti CMP process was investigated. Hitachi Chemical HS-T815 and HS-T605 slurries with different H2O2 concentrations were used to polish 200-mm blanket Ti wafers under different polishing conditions. Under the polishing pressure of 10.3 KPa, the measured shear force between the pad and wafer surface decreased significantly while the Ti removal rate increased significantly when small amount of H2O2 was added to the slurries. On the other hand, the shear force decreased and the removal rate increased slowly with further increase in the H2O2 concentration. A particle indentation model was used to explain the shear force behavior and Ti removal rate mechanism. The shear force decreases slightly when 0.06% H2O2 was added to the HS-T815 slurry and then remained stable with further increase in the H2O2 concentration
Finite Element Analysis (FEA) of Pad Deformation Due to Diamond Disc Conditioning in Chemical Mechanical Polishing (CMP)
Authors: Baisie Emmanuel , Lin Bin , Zhang Xiaohong , Li Zhichao
Published: March 2011

Chemical mechanical polishing (CMP) is widely used to planarize semiconductor wafers and smooth the wafer surface. In CMP, diamond disc conditioning is traditionally employed to restore pad planarity and surface asperity. Despite the advancement of studies on diamond disc pad conditioning, there are very few published reports about the effect of diamond disc conditioning on pad deformation. A two-dimensional (2-D) axisymmetric quasi-static finite element analysis (FEA) model is proposed to investigate the interaction between the diamond disc conditioner and the polishing pad for the first time. The FEA model is developed by using the ANSYS software to study the effects of process parameters (conditioning pressure, pad thickness and pad hardness) on pad deformation. The study leads to a better understanding of the relationship between the diamond disc conditioner and the polishing pad in CMP. It also provides a basis for three-dimensional and dynamic analysis in the future.
Data Driven CMP Manufacturing Modeling for Process and Design Optimization
Authors: Song Li J. , Mehrotra Vikas
Published: March 2011

A hybrid model for CMP process recipe and IC design optimization is introduced. It combines data mining techniques, CMP physical aspects, and uses existing CMP metrology data. The model has been validated to within 7% of the actual thickness measurements on a test chip, and the simulated topography profiles closely match those measured by an AFM. The hybrid model provides intermediate results for all the process steps, including ECD, bulk, touchdown and barrier removal and runs an order of magnitude faster than physical based model. The calibrated hybrid model has been used for wafer level CMP hotspots detection, CMP process recipe change, optimization, dummy fill generation, and rule file development. A novel CMP metal fill tool is also developed to incorporate a field solver for critical nets RC parasitic and timing impact estimation, and a mechanical model for ultra-low k dielectric mechanical strength consideration in addition to a hybrid model.
Effect of Slurry Application/Injection Methods and Polishing Conditions on Bow Wave Characteristics
Authors: Liao Xiaoyan , Sampurno Yasa , Zhuang Yun , Sudargho Fransisca , Rice Adam , Philipossian Ara
Published: March 2011

In this study, the effect of slurry application/injection methods and polishing conditions on slurry flow dynamics at the retaining ring bow wave was investigated. Two slurry application/injection methods (standard slurry application method and novel slurry injection method) were used. For each method, an ultraviolet enhanced fluorescence system was implemented to measure the slurry film thickness at bow wave for a polyetheretherketone (PEEK) retaining ring at different sliding velocities, slurry flow rates and ring pressures. Results indicated that the novel slurry injection method generated significantly thicker slurry film at the bow wave than that of the standard slurry application method. For both methods, slurry film thickness at the bow wave increased with increasing flow rate and ring pressure while it decreased with increasing sliding velocity.
Evolution of Post CMP Cleaning Technology
Authors: Banerjee Gautam
Published: March 2011

In the sub 40 nm technology nodes, new generation of materials are being incorporated into the complex film stack prior to planarization using CMP. The challenge of cleaning wafers after CMP step has evolved over the years from cleaning simply silicon dioxide to now cleaning porous ultra low-k film as well as various metallic films such as Cu, Ta, Al, Ru, Co, Mn, and sometimes alloy films such as GeSbTe(commonly called GST). It is no longer possible to have one common clean formulation working for all technologies. In this paper, evolution of post CMP cleaning technology will be discussed, primarily focused on Cu process but will address the post CMP cleaning challenges with some of the emerging materials applications.
Cleaning Aspects of Novel Materials after CMP
Authors: Vos Rita , Wada Masayuki , Arnauts Sophia , Takahashi H. , Cuypers Daniel , Struyf Herbert , Mertens Paul
Published: March 2011

High mobility channel materials such as Ge and III-V compound semiconductors, are explored for the sub-22nm technology node. In order to allow process integration and full scale manufacturing of these materials, they need to be introduced by epitaxial growth in narrow trenches on silicon carrier wafers. Consequently, CMP is needed to flatten the surface before constructing the gate stack. Similarly to silicon, trace contamination is expected to have a detrimental effect on the devices and therefore, an appropriate cleaning of the wafer consisting of areas with mixed substrates is an absolute requisite. This involves the removal of particulate, metallic and organic contamination while controlling surface etching of these novel materials integrated on the silicon wafer. This will be addressed in this paper and allows the development of efficient post-CMP cleaning strategies.
New Application of Optical Endpoint System: In Situ Cu Residue Detection
Authors: Zhang Weifeng , Wang Xucheng , Tan Changxing , Wang Shan , Shen Walters , Ge George
Published: March 2011

Based on the detection method of optical inspection tool, an in-situ Cu residue detection method was developed to check all the wafers through the optical endpoint system. This method will help to block the wafer which suffered Cu residue defect flowing to the next process step and monitor the hardware variation, consumable variation and process variation. It will also help to improve manufacture efficiency
The Mechanism of Organic Base and Surfactant in Silicon Wafer CMP Process
Authors: Weiwei Li
Published: March 2011

In silicon substrate polishing, slurry has important influence on polishing rate and surface quality. Organic base and surfactant are the key aspects which decide slurry quality. This paper researches action mechanism of different organic bases in polishing and the influence of different surfactants on polishing rate. The results show that, polishing rate of slurry with polyamine is higher than that of slurry with monoamine, polyhydroxyl non-ionic surfactant can improve the stability of slurry system, and speed up the quality transmission, which is benefit to improve polishing rate. Slurry with polyamine and polyhydroxyl non-ionic surfactant has higher polishing rate, good pH stability, while no surface defects, such as scratches and corrosion pits.
Analysis of the Temperature Dependence of Trap-Assisted-Tunneling in Ge pFET Junctions
Authors: Bargallo Gonzalez Mireia , Eneman Geert , Wang Gang , De Jaeger Brice , Simoen Eddy , Claeys Cor
Published: March 2011

In this work, the temperature behaviour of trap-assisted tunneling in Ge pFET junctions selectively grown in STI substrates is evaluated. The experimental results are compared with the TAT model for Si proposed by Hurkx et al. (1), where several parameters (such as the effective mass and trap level values) are adapted in order to obtain the best agreement between the model and the experimental results.
Precise Control of Spike Anneal Process for Advanced CMOS
Authors: Zhao Zhibiao , Tang Ji Yue , Zhao Ganming
Published: March 2011

Aggressive scaling of planar bulk CMOS device has resulted in the need for ultra-shallow junctions (USJ) formation. This represents some special concern are not only integration solution, but also the individual process precise control to meet the evolutional requirements. In the USJ particular, as junction thickness (depth) decreases, the series resistance of the junction increases. Therefore, the dopants concentration must to be increased to improve the resistance. Dilemma, the diffusion is an important issue in shallow junction technology. The spike anneal process was widely adopted at advanced CMOS fabrication to meet the device requirements. In this paper, how to precisely control the processes of spike anneal is discussed. The two major interacted process factors, peak-temperature and residence-time must be separately tunable, not only to meet the requirements of device parameter, but also to achieve an operational precise controlling for process setup, optimization and maintenance.
Improving Copper Interconnect Reliability via Ta/Ti Based Barrier
Authors: Hu Xiao-Wen , Lin Paulchang , Ma Jenny , Jiang Jian-Yong , He Peng
Published: March 2011

As copper line width tightens to 100nm and below, except integration issues, reliability is another challenge. Barrier's performance is critical for the significant impact to interconnect speed and reliability. Ti based barrier is reported as an excellent barrier material from the standpoint of cost and performance, especially for the porous low-k ILD materials. While Ta based barrier is used mainly for its good adhesion, diffusion prevention. In this paper, we demonstrate a composite barrier with Ti adding to the Ta based bi-layer, which shown stable metal resistance while significantly improving reliability performance. Better interface is confirmed by TEM. Our study proved that such kind of Ti doped Ta barrier is better than the standard Ta N/Ta barrier.
Glue Layer Study of Inter Via between Cu and Al Metal Lines
Authors: Chen John , Qiao Cheney , Yang Linhong , Chang Kevin
Published: March 2011

A 0.13um Cu-Al hybrid backend between a dual damascene process with Cu line and a conventional process with Al line is introduced in this paper. First 3 metal layers (M1~M3) interconnects with Cu line for process capability and circuit speed concern. Whereas following metal layers (M4~M7) interconnects with Al line for cost concern. The interconnection via between Cu and Al interface is the key process for Cu-Al hybrid process. This paper mainly focused on via process study between Cu and Al interconnection.
The Influence of The SIN Cap Process on The Voltage Breakdown and Electromigration Performance of Dual Damascene Cu Interconnects
Authors: Cao Ya-Lu , Xing Charles , Xu Neil , Zhou Hua , Bian Allen , Lin Paulchang
Published: March 2011

The influence of the SiN cap-layer deposition process including different pre-clean treatments on the voltage breakdown (VBD) and electromigration (EM) behavior of copper dual damascene metallization has been studied. A remarkable improvement for voltage breakdown and electromigration were revealed depending primarily on the pre-clean treatment before cap-layer deposition rather than the deposition process itself.
Effect of RF Power on Carbon Nanotubes Synthesized at Low Temperature by RF PECVD
Authors: Lin Xinyuan , Zhang Kailiang , Hu Kai , Qiang Xiaoyong , Wang Shiwei
Published: March 2011

The growth of carbon nanotubes (CNTs) at low temperature is one of the key obstacles on currently application in electronic device interconnection. In this paper, CNTs were grown from acetylene and hydrogen gas mixture on Si substrate by RF-PECVD, in which Fe was selected as catalyst. The effect of RF power on CNTs at low temperature was mainly discussed. SEM and Raman spectra were used to characterize the morphology and defects of CNTs. Results showed that the optimum RF power for CNTs growth at low temperature (450°) is 100W. When the RF power is too low, it can't provide enough energy for acetylene decomposition. When the RF power is too high, there are two aspects reasons that affect CNTs growth. One is that high density plasma can etch new-grown CNTs, and another reason is that lots of carbon atoms in the chamber are easy to make catalyst poisoned.
Study on the Reliability of Fast Curing Isotropic Conductive Adhesive
Authors: Du Wenhui , Cui Huiwang , Chen Si , Yuan Zhichao , Ye Lilei , Liu Johan
Published: March 2011

With the development of semiconductor technology, electronic packaging technology with increasingly high integration density is needed. Solder is a traditional interconnect material widely used in electronic packaging industry, but now more attention is being paid to isotropic conductive adhesive (ICA) as an environmentally friendly interconnect material with advantages of low processing temperature, simple processing conditions and good manufacturability. However, compared with solder, reliability studies of ICA are still scarce. This paper aims to enrich the reliability study of ICA, by studying the reliability of a novel fast curing ICA which has a curing degree of 97.8% with 3 min of curing time at 150 °. It was found that after 85 °/85% RH humidity and heat test for 160 h, the bulk resistivity of ICA decreased about 82% and then remained stable. Besides, ICA embrittled as aging time extending.
The Effect of Functionalized Silver on Rheological and Electrical Properties of Conductive Adhesives
Authors: Fan Qiong , Cui Huiwang , Fu Chune , Li Dongsheng , Tang Xin , Yuan Zhichao , Ye Lilei , Liu Johan
Published: March 2011

This research used low molecular surface modifiers, and observed that chemisorptions took place through the formation of a bond between silver surface and an adsorbed molecule, which improved the dispersion of silver flakes in the organic resin. Several different functionalizers, such as thioglycolic acid, silane and di-acid, were used to functionalize the silver surface. Results of shear viscosity, bulk resistivity etc. showed that by using these low molecular organic functionalizers, isotropic conductive adhesives (ICAs) with lower shear viscosity and better electrical conductivity at high silver fillers content were obtained. The adipic acid had the greatest effect on the rheological and electrical property of ICAs, so its weight percentage in silver flakes was also optimized; ICAs displayed the maximum electrical conductivity when there was 0.5 wt% of silver flakes.
Cost-effective Use of Gold Wire in Semiconductor Packaging
Authors: Vath Charles J. , Holliday Richard
Published: March 2011

The semiconductor industry has maintained an average 15% cost down per year over the range of products it offers. Continued cost reduction will be difficult to achieve based on current practices and raw material prices. The need to remain competitive has compelled integrated device manufacturers and subcontractors to look at alternative material types, most notably copper wire. A recent survey of the industry has revealed that there remain very widespread concerns on migrating away from the use of gold. It is important that the cost of using gold wire is minimized without compromising on product reliability and quality. We present a critical review of the wire bonding process focusing on various practices, procedures, and material choices. Such analyses indicate, for example, that a reduction of the FAB ratio in a 32 I/O QFN with 38 wires from 2 to 1.4, would save 1 km per 1,100 strips.
Copper Wire Bonding in High Volume Manufacturing
Authors: Appelt Bernd K. , Tseng Andy , Lai Yi-Shao , Chen Chun-Hsiung
Published: March 2011

Wire bonding is still by far the dominant interconnection technology with about 90% market share. Copper wire bonding has achieved approximately 15% penetration within two years. Considerable amount of fundamental characterization has been performed to understand the nature of Cu wire bonding and even more analysis has been done in manufacturing to ensure reliable packages can be shipped. Here, some of the methodology of successful, high volume manufacturing will be described. Rigorous process optimization and product characterization are key and will be detailed. Supportive data from extended reliability testing demonstrates that 2 x the standard JEDEC life can be achieved. This is in part due to the very slow intermetallic growth rate and in part due to the proper choice of mold compound. The other elements are strict adherence and control of bonding parameters and rigorous clean room management which is also reflected in yields being equivalent to gold wire bonding.
MUF Technology Development for SiP Module
Authors: Kweon YoungDo , Ha Job , Kim KiChan , Jang MinSeok , Doh JaeCheon , Lee ChangBae , Yoo Dojae
Published: March 2011

In this study, we developed the molded underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on minimizing voids between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding compound (EMC) selection approach, air vent design of cavity vacuum molding, and results of void free from Design of Experiment (DOE) of several SiP module layouts. In the end, Scanning Acoustic Tomography (SAT) result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.
Advanced Bump Structure for Improving the Board Level Characteristics of WLCSP
Authors: Lee ChangBae , Choi Jongwoo , Kim Jin-Su , Choi Sangsoon , Yoo Dojae , Park Seungwook , Kweon YoungDo
Published: March 2011

In this study, to increase solder joint reliability, we developed the epoxy reinforced bump structure surrounding the solder bump joint. The thermal-mechanical reliability of the epoxy reinforced solder bumped wafer level package was carried out during the thermal cycle and drop shock test of the package. The reliability of solder bump joint was evaluated by means of the thermal cycle in the range -40° to 125°. The experimental results revealed that the thermo-mechanical fatigue properties of the epoxy reinforced bump structure was better than that of the conventional solder bump structure. Epoxy reinforced bump structures improved the WLP characteristic life by at least 2 times. Also, the drop shock reliability of epoxy reinforced bump structure was enhanced 3 times better drop characteristic life than that of conventional single bump structure. The life time of epoxy reinforced solder bump joint was longer than that of the conventional WLCSP solder joint.
Packaging Issues for High-Voltage Power Electronic Modules
Authors: Ang Simon S. , Evans Tristan , Zhou Jinchang , Schirmer K. , Zhang Hoa , Rowden Brian , Balda Juan , Mantooth Alan
Published: March 2011

This paper addresses interconnect and passivation issues associated with the fabrication of high-voltage power electronic modules. A wire-bondless direct solder attachment hierarchy for interconnection was evaluated using two direct-bond copper (DBC) elements: one acting as a substrate connected to a base plate and the second as an interconnection lead-frame between the power semiconductor devices. Finite element modeling revealed their enhanced performance over wire-bonded modules due to at least an order of magnitude decrease in parasitic inductance and the added benefit of enhanced thermal performance. A two-step passivation/encapsulation method to provide higher breakdown voltages at high temperatures is proposed for future high-voltage power electronic modules.
Plasma Etching for Failure Analysis of Integrated Circuit Packages
Authors: Tang Jiaqi , Schelen J.B.J. , Beenakker C. I. M.
Published: March 2011

Plastic integrated circuit packages with copper wire bonds are decapsulated by a Microwave Induced Plasma system. Improvements on microwave coupling of the system are achieved by frequency tuning and antenna modification. Plasmas with a mixture of O2 and CF4 showed a high etching rate around 2 mm3/min. The role of O2 and CF4 in etching molding compound is described. Plastic package with 38 um Cu bond wires and a 2 mm * 3.5 mm die inside is fully decapsulated in 20 minutes. Cu wires remain undamaged after decapsulation proving the efficiency of this method.
Process Optimization of Contact Module in NOR Flash Using High Resolution e-Beam Inspection
Authors: Liao Hsiang C. , Hung Che L. , Luoh Tuung , Yang Ling-Wu , Yang Tahone , Chen Kuang-Chao , Lu Chih-Yuan
Published: March 2011

The inspection sensitivities and capture rate capabilities of high resolution e-beam inspection system with extracting and retarding mode are evaluated. E-beam with retarding mode inspection demonstrates better performance and reflects the wafer sort yield loss in contact failure items directly. After the contact module process optimization, the yield was improved almost two times above.
Verification of Systematic Defects Using e-Beam Defect Review System
Authors: Luoh Tuung , Yang Ling-Wu , Yang Tahone , Chen Kuang-Chao , Lu Chih-Yuan
Published: March 2011

High resolution e-beam review system with critical point inspection (CPI) function is implemented to verify the systematic defects in both array and periphery area of NOR Flash products. CPI inspection can help us to intercept with unobvious systematic defects and find the process variation to save the cost of yield loss from time to time, and it is important for debugging the systematic defects in irregularly periphery circuits.
TSV/3DIC Profile Metrology Based on Infrared Microscope Image
Authors: Tang Jing-Jou , Lay Young-Jinn , Chen Lih-Shyang , Lin Lian-Yong
Published: March 2011

3D IC can provide the advantages of heterogeneous integration through vertical interconnection and high performance without using advanced process. Basically, 3D IC can be implemented based on the technology of TSV (Through Silicon Via; TSV) and micro-bumps. Thus the quality of TSVs is critical to the yield of a 3D IC system. However, due to the nature of miniature and non-easy-probe, it is very difficult to validate the characteristics of topology or electricity of a TSV using traditional probing or metrology methodology during the process. In this paper, we are going to present a TSV profile metrology system for 3D IC based on the digital image processing (DIP) technique. The profiles of all TSVs in a 3D IC system can be constructed based on the images obtained from IR-microscope or SEM. The results show that our system is helpful to the inspection of TSV duing the 3D IC manufacturing.
Endpoint Detection in Plasma Etching Using Principal Component Analysis and Expanded Hidden Markov Model
Authors: Kim Min-Woo , Kim Seung-Gyun , Zhao ShuKun , Hong Sang Jeen , Han Seung-Soo
Published: March 2011

In current semiconductor manufacturing, plasma processes such as etch and CVD take the portion at least 40% throughout of integration processes. As the feature size of integrated circuit (IC) devices continuously shrinks, detecting endpoint in low open area plasma etch process becomes more difficult. To solve this problem, a combination of Principal Component Analysis (PCA) and Expanded Hidden Markov model (eHMM) technique is applied to optical emission spectroscopy (OES) signals. Selected patterns are used in PCA, which reduces dimension of the raw data and increases gap between classes. The eHMM is employed to detect endpoint using output of PCA. The eHMM combines the semi-Markov model to enable an arbitrary distribution on the location of the change-point and the segmental HMM to model the configuration in each segment. After modeling using eHMM, real-time OES data were fed to this model to detect endpoint.
Spectral Sensitivity Analysis of OCD Based on Muller Matrix Formulism
Authors: Yaoming Shi , Zhensheng Zhang , Guoxiang Liu , Zhijun Liu , Yiping Xu
Published: March 2011

The spectral sensitivities of scatterometry based on Mueller matrix formulism at the technology node of 65 nm and beyond were studied. The advantage of Mueller matrix based polarized light scattering technique over conventional ellipsometry technique in measuring patterned wafers was present. RCWA method was used to simulate the 2D gratings scattering. As the analysis shown, Mueller measures produce more signals than SE or SR measurement does and Mueller spectral sensitivities to structure features variation are stronger in most cases.
A Method to Determine Process Capability Cpk and Corresponding Percentage of Non-Conforming for Non-Normally Distributed and Limited Production Data
Authors: Yang Siyuan F.
Published: March 2011

For normal distributions, Cpk is determined by a popular formula . For non-normal distributions, the current practice in determining Cpk is the percentile method, i.e. to using 50% percentile (i.e. P(0.5) to replace the average, (P(0.99865) - P(0.5)) to replace 3s for Cpu and (P(0.5) - P(0.00135)) to replace 3s for Cpl. This seems to be a reasonable modification of Cpk formula to accommodate the non-normal distributions and has been accepted and widely used by many practitioners in industries. In order to evaluate process performance, the corresponding percentage of non-conforming (%NC) is a critical quantity and should be determined at the same time when Cpk is calculated for non-normal distributions. However, we are unable to use regular percentile method (such as the one popularly used in Excel) to estimate the upper and lower percentiles for limited process data. The same problem also occurs to the %NC when Spec limits are far away from the center location for limited production data. This work provided a practical means to resolve this problem by employing an extrapolation method based on the current percentile method to obtain very high and very low percentiles with limited production data assuming the probability curve is still straight up to lower or upper percentiles or Spec limits. This assumption has been further discussed to assure practicability of its applications.
High Voltage Device Negative Bias Temperature Instability Improvement with Different Process Conditions
Authors: Sim Poh Ching , Koo Sang Sool , Pal Deb Kumar
Published: March 2011

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.
LDMOS Thermal SOA Investigation of a Novel 800V Multiple RESURF with Linear P-top Rings
Authors: Herlambang Aloysius P. , Sheu Gene , Guo Yufeng , Wasisto Hutomo Suryo
Published: March 2011

In this paper, Technology Computer-Aided Design (TCAD) is used to investigate the thermal characteristic and Thermal Safe Operating Area (T-SOA) of a novel 800V Multiple RESURF LDMOS with linear P-top Rings. Two methods of critical temperature extraction are presented and the agreement between these two methods is proven. The effects of Initial Front Rise time (IFR) and other parameters on the thermal characteristic of the device are inspected. Finally, the simulation result has an agreement with the analytic solution. Therefore, the analytic solution can replace the 3D simulation for large device which is not able to be performed using current available TCAD tools.