bluuebunny/crossref_metadata_2025 huggingface dataset:
Realisation of High Temperature Electronics Packaging Technology for Sensor Conditioning and Processing Applications
Authors: Riches S T , Johnston C , Lui A
Published: October 2015

The requirement to install electronic power and control systems in high temperature environments in aero-engines and in down-well exploration has posed a challenge to the traditional limit of 125°C of electronics systems. The leap in operating temperature to above 200°C in combination with high pressures, vibrations and potentially corrosive environments means that different semiconductors, passives, circuit boards and assembly processes will be needed to fulfil target performance specifications.

Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of >200°C. Most of the applications to date have required performance for short times (<2,000 hours) at the highest operating temperatures of up to 225°C in down-well drilling applications. There is interest in extending the endurance of high temperature electronics into aero-engine and other applications where a minimum 20 year operating life is stipulated. Most of the reliability data on the high temperature endurance of the integrated circuit is generated with little consideration of the packaging technologies, whilst most of the reliability data pertinent to high temperature packaging technologies uses test pieces, which limits any conclusions relating to long term electrical performance.

This paper will present results of studies on high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. Different die attach and wire bond options have been included in the study and the performance of several functional blocks on a high temperature SOI device has been tracked over the endurance tests which have lasted for >11,000 hours at 250°C. Degradation phenomena such as thermal migration and material deterioration due to high temperature exposure in air and inert atmospheres will be described. An assessment of the availability of high temperature materials and components to meet long term requirements for operation at 250°C will be presented.
PoP Package Warpage Contributors' Characterization and Impact Analysis
Authors: Wen Shengmin
Published: October 2015

Package-on-package (PoP) technology has been widely adopted in application processor's construction for today's mobile equipment such as smart phones and tablets. One of the key tasks in a successful PoP configuration is the PoP bottom package's warpage control. Due to shorter and shorter schedule demand of such configuration's development and execution – sometimes it could be as little as half a year, the development process to identify a optimized PoP bottom package cannot take the traditional way of multiple iterations through large scale, time consuming and complex DOE's. It is therefore needed to study and understand the key warpage contributors and how significant each contributor's impact is so that educated preliminary packaging parameters can be set and intelligent DOE's can be designed. This is the major purpose of this paper.
Packaging of High Frequency, High Temperature Silicon Carbide (SiC) Multichip Power Module (MCPM) Bi-directional Battery Chargers for Next Generation Hybrid Electric Vehicles
Authors: Cole Z. , Passmore B. , Whitaker B. , Barkley A. , McNutt T. , Lostetter A.B.
Published: October 2015

The packaging design and development of an on-board bi-directional charger for the battery system of the next generation Toyota Prius plug-in hybrid electric vehicle (PHEV) will be presented in this paper. The charger implements a multichip power module (MCPM) packaging strategy. The Silicon Carbide (SiC) MCPM charger is capable of operating to temperatures in excess of 200°C and at switching frequencies in excess of 500 kHz, significantly reducing the overall size and weight of the system in comparison with Toyota's present silicon-based Prius charger. The present actively cooled Si charger is capable of delivering a peak power of 1kW at less than 90 percent efficiency, is limited to less than 50 kHz switching, and measures greater than 6.3 liters with a mass of 6.6 kg, resulting in a power density of 150 W/kg. The passively cooled SiC MCPM charger presented herein was designed to deliver a peak power of 5 kW at greater than 96% efficiency, while measuring less than 0.9 liters with a mass of 1 kg, resulting in a power density greater than 5 kW/kg. Thus, the novel SiC MCPM charger represents an increase in power density of more than 30×, a very significant power density achievement in size and weight for sensitive mobile applications such as PHEVs. This paper will discuss the overall mechanical design of the SiC MCPM charger, the finite-element modeling and analysis of thermal and stress considerations, characterization and parasitic analysis of the MCPM, and the development of high temperature solutions for SiC devices.
Novel ultra-compact quad-band System-in-Package (SiP) module with IC embedded in substrate based on SESUB technology.
Authors: Sieroshtan V. , Sevskiy G. , Komakha P. , Aleksieiev O. , Burygin A. , Chayka O. , Ruban O. , Shevelov M. , Kato K. , Horibe A. , Fujioka H. , Ruffing K. , Heide P. , Vossiek M.
Published: October 2015

This paper presents a novel ultra-compact System-in-Package (SiP) module with highly integrated wireless connectivity devices combining a set of 4 standards: WLAN, Bluetooth, FM and GPS. Besides an IC, the SiP module consists of RF filters, SMD components and a Single-Chip RF Front-end. The main IC is embedded inside the substrate and basics of SESUB technology are described. For electromagnetic compatibility and physical protection a metal EMI shield has been used. The total size of solution presented is 8.0×7.5×1.3mm3 demonstrating significant miniaturization over current module technology. The embedding process and SiP module routing has shown benefits in electrical and mechanical performance.
Embedded Die Substrates for Power Applications
Authors: Appelt Bernd K , Su Bruce , Yen Uno , Essig Kay
Published: October 2015

Historically, power die like MOSFETs have been packaged on lead frames using wire bonds as interconnects. To facilitate current carrying requirements, thick wires and sometimes also clips were used, to handle the total electrical and thermal conductivity requirements. As die are being thinned, it has become possible to take advantage of new electrical designs and locate source and drain on opposite sides of the die. Such die can now be easily packaged by embedding the power die in organic substrates. The die is bonded on a Cu pad and covered by prepreg and copper foil during lamination. Source, drain and gate pads are accessed from the top side with laser vias and filled with plated copper. Finally, the top side is patterned and protected with solder mask. Electrical and thermal modeling data can demonstrate the performance efficiency while reducing the form factor in accordance with the miniaturization requirements of mobile applications. Aside from single die packages, more advanced packages can be built containing multiple power die and controller die. The basic process flow remains the same but does require some adaptation. If so desired, additional components may be assembled on top of the embedded die package leading to further integration and miniaturization.
Hardware Design for Multiple Gas Detection System Using Zeolite Coated with Nile Red
Authors: Nguyen Son , Delalic Z. Joan , Kargbo David M. , Sheffield Joel B.
Published: October 2015

The research goal is to develop a multiple gas sensing device which integrates a zeolite-Y/nile-red sensing front end with optoelectronic detector. The highly fluorescent nile red dye, included in the nanoporous structures of zeolite Y, responses to different gases by emitting fluorescence of different wavelengths. In addition, the size of the pores of zeolite Y's can be utilized to allow gases whose molecule is smaller than the pores to enter and react with the included dye. Since nanoporous structures of zeolites are manipulated, the device is expected to be more accurate, and more sensitive. Also it is able to better differentiate and detect one target in a mixture of different gases. This is achieved by incorporating fluorescent dyes into the supercages of zeolite Y's, measuring gas absorption, desorption and photo-chromic interaction of dye and gases, interfacing the zeolite/dye sensor arrays with light source and electronic detectors.
Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications
Authors: Hung Jui-Feng , Lau John H. , Chen Peng-Shu , Wu Shih-Hsien , Hung Sheng-Che , Lai Shinn-Juh , Li Ming-Lin , Sheu Shyh-Shyuan , Lin Zhe-Hui , Lin Chih-Sheng , Lo Wei-Chung , Kao Ming-Jer
Published: October 2015

In this study, the electrical performance of a general TSV structure for high-frequency 3D IC integration applications is investigated. Emphasis is placed on the proposal of an analytical model and the analytical equations of a TSV with all its key parameters. Also, the model and equations are verified, both in the frequency and time domains, by more detailed finite element analyses. Finally, a TSV electrical design guideline is proposed.
Use of Wire Bonding to Study Bond Pad Damage from Wafer Probe
Authors: Hunter Stevan , Clark Jonathan L. , Hornberger Darin , Rubio Lance
Published: October 2015

Harsh wafer probing and harsh wire bonding have been used in previous work by our group to study cracking and ripple effect on various bond pad designs in technologies having aluminum (Al) alloy based metallization in SiO2 dielectric. One outcome of the previous experimentation is the confirmation that cracks due to wafer probe may not be visible even in a careful cratering test. Probing stress can bend the top SiO2 of the pad downwards, causing high tensile stress to the underside of the film. Cracks initiating in this region easily go undetected in routine monitor procedures, unless they propagate to the top surface and break the barrier film above. Latent probing cracks can result in reliability issues for circuit under pad (CUP) bond pad designs. A typical probe crack in a CUP pad's top SiO2 layer, detected in a cratering test, may actually be accompanied by one or more hidden cracks at the bottom of the film, which may only be detected in a focused ion beam (FIB) cross section. This study uses harsh probing to create cracks in various bond pad test structures and then follows them through the wirebond process, including harsh bonding experiments. Previously undetected probe cracks may be enhanced, lengthened, and made easier to detect in wirebond monitoring and in a cratering test after wirebond. Cracks due to wirebond have different characteristics than probe cracks. Distinguishing features of both crack types are compared after bonding. Monitoring of the ripple effect in both probe and bond helps to predict and track bond pad cracking tendencies. Methods to reduce cracking from both probe and bond are reviewed.
Gold Ball Wire Bonding with Heated Tool for Automotive Microelectronics
Authors: Rasmussen David J
Published: October 2015

Microelectronics used in automotive applications have grown considerably in the last few years with more high tech electronics controlling more functions in automobiles. In an effort to have more precise control and to reduce vehicle weight manufacturers are integrating more functions into smaller packages. Many of these packages are embedded in molded plastic. This causes challenges when it comes to wirebonding these devices. They often cannot be heated to traditional Gold Ball Thermosonic wirebonding temperatures of 120 – 150C. However, using a heated capillary to bond the parts which remain at room temperature simplifies the process considerably. Alternatives such as pre-heating the parts in an oven and complex hot gas handler systems are not required. With a resistive wire coil heater surrounding a standard (or long capillary for deep access) sufficient heat can be provided to the wire bond site for a strong and reliable interconnect. The bonding surface can be any material used in gold ball bonding: aluminum bond pads on die, plated contacts, ceramic substrates or plated copper traces on PCBs. This paper will show that this heated tool process has been successfully utilized with 1mil Au wire and many of the standard die and substrate materials with little impact on process parameters.
New Flip-Chip Interconnect Technology for High Performance and High Reliability Applications
Authors: Yamaguchi Eiji , Tsuji Mutsuo , Shimoishizaka Nozomi , Nakano Takahiro , Hirata Katsunori
Published: October 2015

As the current and next generation devices are embracing geometries below 28nm and requiring softer low-K dielectric isolation on very thin large silicon dies ∼ to perform a reliable die-to-package interconnect is becoming a challenge. Further, the high pressure from Cu wire bonding and high reflow temperature of conventional flip-chip bonding often results in damage of device structure.

A new flip-chip bonding technology has been developed for such critical applications, and is claimed to be “damage free”. It uses soft bump made by non-full cured conductive paste on the package substrate. These soft bumps require ultra-low bonding pressure on the pad of the die. Thus the bonding process don't make any damage on ULK isolation layer. Details of the process, material sets used for such fragile device structures have been discussed. Reliability results are shared, which further ensures the robustness of this process. Finally, the cost advantage through adaptation of this process has also been elaborated.
Underfill Dispensing for 3D Die Stacking with Through Silicon Vias
Authors: Le Fuliang , Lee S. W. Ricky , Wu Jingshen , Yuen Matthew M. F.
Published: October 2015

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.
Package-Interposer-Package (PIP): A Breakthrough Package-on-Package (PoP) Technology for 3D-Integration
Authors: Das Rabindra N. , Egitto Frank D. , Bonitz Barry , Kopp Erich , Poliks Mark D. , Markovich Voya R.
Published: October 2015

Package on Package (PoP) stacking has become an attractive method for 3D integration to meet the demands of higher functionality in ever smaller packages, especially when coupled with the use of stacked die. To accomplish this, new packaging designs need to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. A new 3D “Package Interposer Package” (PIP) solution is suitable for combining multiple memory, ASICs, stacked die, stacked packaged die, etc., into a single package. This approach also favors system integration with high density power delivery by appropriate interposer design and thermal management. Traditional Package on Package (PoP) approaches use direct solder connections between the substrates and are limited to use of single (or minimum) die on the bottom substrate, to reduce warpage and improve stability. For PIP, the stability imparted by the interposer reduces warpage, allowing assemblers of the PIP to select the top and bottom components (substrates, die, stacked die, modules) from various suppliers. This mitigates the problem of variation in warpage trends from room temperature to reflow temperature for different substrates/modules when combined with other packages. PIP facilitates more space-efficient designs, and can accommodate any stacked die height without compromising warpage and stability. PIP can accommodate modules with stacked die on organic, ceramic, or silicon board substrates, where each can be detached and replaced without affecting the rest of the package. Thus, PIP will be economical for high-end electronics, since a damaged, non-factional part of the package can be selectively removed and replaced. A variety of interposer structures were used to fabricate Package Interposer Package (PIP) modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP constructions on various stacked die or stacked packaged die configurations.
Characterization of silicate sensors on Low Temperature Cofire Ceramic (LTCC) substrates using DSC and XRD techniques
Authors: Ruales Mary , Jones Kinzy
Published: October 2015

Characterization of Silicate sensors using Differential Scanning Calorimeter (DSC), X-ray Diffraction (XRD) and Scanning Electron microscopy (SEM) is presented. These silicate sensors are based on three primary materials: Li2SiO3, K2SiO3, and CaSiO3. Silicate powders were transform into adequate inks that were added to a Low Temperature Cofire Ceramic (LTCC) substrates with thick film technology using screen printing which continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities. These silicate sensors are low power-high temperature heated ceramic sensors to detect halogen gases. Every sensor responded to the gas showing stability and reproducibility. Phase diagrams for these silicates were used to produce different combinations. The use of the eutectoid point in the phase diagrams was critical to reduce the operating temperature. Testing and characterization of these silicate sensors is presented. The impact of various parameters (e.g. materials design, structure, properties, performance and processing) for the sensors including their relationships for electronic packaging was reviewed and it was found critical to determine the microelectronics packaging reliability and integrity. The fundamentals of the sensor behavior including the sensitivity as well as response and recovery times were also determined.
A Process For Treating Woven Glass Cloth
Authors: Boday Dylan , Haag Michael , Kuczynski Joe , Schmidt Markus , Wahl Michael
Published: October 2015

Woven fiberglass cloths are by far the most common reinforcement material used in PCBs. The glass yarns are coated with silane-based coupling agents designed to improve the interfacial adhesion between the glass filaments and the resin matrix. Poor glass surface wetting and weak adhesion of the resin to the yarn are the major root causes for a number of PCB failure mechanisms. Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) was utilized in order to garner a better understanding of the observed poor glass surface wetting and weak adhesion of the resin to the yarn following standard thermolysis processes during preparation of the glass cloth. A solvent-based process was demonstrated to yield excellent retention of the glass cloth physical properties while simultaneously providing a clean glass surface for bonding of the coupling agent. ToF-SIMS verified the presence of silane at the cloth surface. The results were used to derive recommendations for the glass cloth suppliers in order to improve the efficiency of their silanation process.
Making New With Old
Authors: Renaud-Bezot Nick , Beesley Mark
Published: October 2015

In the past few years, embedding has emerged as a valid contender to traditional packaging technologies for specific applications. It uses PCB (Printed-Circuit Board) processes for 3D integration of active and passive elements to create SiPs (System in Package).

Just like MEMS (Micro Electro-Mechanical System) and IPD (Integrated Passive Device) emerged from standard semiconductor processes, and then were adapted to match the specific requirements, so does embedding build on decades-old techniques to create this new class of packages. Inherent advantages include:- Compatibility with traditional SMT processes, in particular with regards to pitch,- Production batch size,- Historical reliability and process data,- Thermal management,- Possibility to integrate EMI shielding,- CTE matching.

This paper will present the challenges and opportunities of this packaging technology in terms of processes, performance and reliability. It will focus on the solution developed by AT&S called ECP® (Embedded- Component Packaging). Whereas competition is integrating PCB processes to their semiconductor-packaging operations, AT&S is the only vendor building on its PCB tradition to enter the packaging industry, thereby presenting an alternative view of the subject.
Photostabilization of i-line Photoresist and ARC Layer
Authors: YILMAZ Zeliha , PAK Murat , İMRAHORILYAS Sema , ERSOY Aylin
Published: October 2015

Stabilization after the lithography process is crucial in order to prevent deformation of photoresist patterns by other thermal processes used in semiconductor production. UV hardening is capable of minimizing negative effects of thermal processes such as rounded shaped lines; line width widening or shrinkage and CD shift. The amount of UV energy absorbed and final process temperature are important process parameters; which effect directly the degree of cross-linking. So, this paper examines optimization of process parameters such as the ramp rate, which is the tangent of the temperature-time curve (°C/sec) and the final temperature. Also the ramp rate indicates the time; that wafer is exposed to the high degree of UV energy. Process parameters are optimised with respect to the improvement of etch selectivity, decrease of the CD shift. Profile photos have been taken with Scanning Electron Microscope. In the experiments, the novolak based i-line photoresist and ICON-7 as anti reflecting coating are used for the lithography process. Many variables have been taken into consideration while determining optimum process parameters. These are resist thickness, type of the surface layer of wafer, magnitude of the critical dimension (>1 μm & < 1 μm ) and the size of the open area on the reticle used during exposure.
Stacking Aspects in the View of Scaling.
Authors: De Vos Joeri , La Manna Antonio , Daily Robert , Rebibis Kenneth June , Beyne Eric
Published: October 2015

For 3D Si die to Si die stacking and connections between Si die and Si interposer, fine pitch microbump interconnections are needed next to TSV's. When scaling the pitch below 40μm, stacking accuracy is one of the main drivers to ensure yielding devices. Stacking tolerance are being discussed in the view of scaling. It is shown that stacking can be made less sensitive to misalignment by playing with the bump diameters. In the vertical direction, stacking tolerance can be increased by bump planarization or reflow. The demonstrated results are mainly based on CuSn-Cu microbumps but the discussed theory is generic, it is not restricted to this kind of interconnection.
Optimization of Ag Composition in Cu Pillar Bumps with Sn-xAg Solders
Authors: Cho Moon Gi , Lim Hwan Sik , Park Sun Hee , Kwon Yong Hwan , Chung Jaesik , Choi Jinho , Ahn Eun-Chul
Published: October 2015

In order to minimize the large plate growth of Ag3Sn intermetallic compounds (IMCs) adversely affecting the mechanical behavior and reducing the reliability of solder joints, the Ag content of less than 3wt% has been suggested in ball grid array (BGA) Sn-Ag solders. The suggestion (< 3wt% Ag in the solders) is invalid in small solder bumps, and moreover there is no available guideline of the Ag content in the small Sn-Ag solders. In this study, the optimum level of Ag content in small Sn-Ag Cu pillar bumps (CPBs) of less than 50um in diameter was investigated to suppress the large plate growth of Ag3Sn. Since the undercooling of Sn-Ag solders increases with a decrease of solder ball size, the Ag3Sn IMCs are more prone to become largely plate-like in small solders. Actually, in small Sn-Ag CPBs, the large plate growth of Ag3Sn was observed on the top surface of solder bumps even though the Ag content was less than 3.0wt%. For suppression of Ag3Sn plates in Sn-Ag CPBs, two ways were suggested; increasing the cooling rate of the reflow profile and reducing the Ag content in the solders. Reducing the Ag content was effective on reducing the large plate growth of Ag3Sn, while a high cooling rate was not effective. Through the thermal analysis and thermodynamic calculations, the optimized Ag content in Sn-Ag CPBs of less than 50um was suggested, and the large plate growth of Ag3Sn was effectively reduced within the suggested Ag content.
Electrografted insulator layer as copper diffusion barrier for TSV interposers
Authors: Mevellec V. , Raynal F. , Suhr D. , Dequivre T. , Religieux L.
Published: October 2015

Alchimer develops alternative wet solutions based on electrografting (eG™) and chemical grafting (cG™) proprietary technologies. eG is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces, and enables self-oriented growth of thin coatings of various materials, especially polymer and metals, initiated by in-situ chemical reactions between specific precursor molecules and the surface. Due to outstanding thermal, mechanical and electrical properties, electrografted polymer layers are an efficient insulation layer for TSV applications. In this paper, we fill focus on the copper diffusion barrier properties of this eG polymer layer and the associated Cost of Ownership (CoO) reduction for TSV metallization.
Moisture and Hydrogen Release in Optoelectronic Hermetic Packages
Authors: Albarghouti M. , El Dahdah N. , Perosevic G. , Jain S. , Papillon J-M , Fernandez S.
Published: October 2015

In this work we investigated the effect of Nickel (Ni) plating process on the Hydrogen (H) and moisture content of hermetic packages such as those used in optoelectronics. The work offers an explanation of moisture formation inside hermetic packages by showing that the problem arises from the electroless plating of Ni which is found to be inherently rich in H. The effects of the Ni plating process, baking, and Au thickness on the moisture and hydrogen content of hermetic packages were thoroughly explored. It was observed that baking the package components before sealing alleviates the problem of moisture formation inside the package but it doesn't fully eliminate it. It was only after changing the Ni plating process from electroless to electrolytic that the moisture problem actually disappeared. Our investigation showed that moisture formation inside hermetic packages is due to H evolution from the electroless Ni which eventually reacts with surface oxides to form H2O. SIMS analysis of electroless and electrolytic Ni showed that electroless Ni is around ten folds richer in H compared to its electrolytic counterpart. SIMS analysis also showed that H content in electroless Ni can be significantly reduced with heat treatment.
Effect of Fe content on the interfacial reliability of SnAgCu/Fe-Ni solder joint
Authors: Zhang Hao , Zhu Qing-Sheng , Liu Zhi-Quan , Zhang Li , Guo Hongyan , Lai Chi-Ming
Published: October 2015

Fe-Ni films with compositions of Fe-75Ni, Fe-50Ni, and Fe-30Ni were used as under bump metallization (UBM) to evaluate the interfacial reliability of SnAgCu/Fe-Ni solder joints through ball shear test, high temperature storage, as well as temperature cycling. The shear strength for Fe-75Ni, Fe-50Ni, and Fe-30Ni solder joints after reflow were 42.57, 53.94, 53.98 MPa respectively, which are all satisfied with the requirement of industrialization (>34.3 MPa ). High temperature storage was conducted at 150°C and 200°C respectively. It was found that higher Fe content in Fe-Ni layer had the ability to inhibit the mutual diffusion at interface region at 150°C, and the growth speed of intermetallic compound (IMC) decreased with the increase of Fe concentration. When stored at 200°C, the thickness of IMC would reach a limitation for all these three films after 4 days, and cracks occurred at the interface between IMC and Fe-Ni layer. Temperature cycling tests revealed that SnAgCu/Fe-50Ni solder joint had the lowest failure rate (less than 10%), which has the best interfacial reliability among three compositions.
Biomedical sensor packaging failures: Regulations are not design standards
Authors: Drummond Colin K.
Published: October 2015

Design of biomedical sensors and probes are limited by failure analysis tools that are unable to prediction product life, partially due to the absence of time-dependant materials property databases. “Design for reliability” lags “test for reliability,” thus less than optimal product designs reach the market. Regulatory agencies have identified several critical path design projects that could alleviate the situation. An argument is made that design standards are the province of Industry and an initiative for collaboration on pre-competitive material design data should be undertaken.
Assembly and Packaging Enabling System Integration
Authors: Pressel Klaus , Beer Gottfried , Wojnowski Maciej
Published: October 2015

More than Moore is a major trend to tackle the increasing difficulties of traditional Moore's law scaling. System in Package technologies, which allow heterogeneous integration, are appearing in ever more electronic applications. Furthermore we observe merging of silicon wafer technology with assembly and packaging technologies. Today a more coherent development taking into account chip, package, and the board is needed. In this paper we show how assembly and packaging can take up the slack because traditional More Moore downscaling is becoming more difficult. First, we introduce the Thin Small Leadless Package (TSLP) e.g. used in mobile systems. The TSLP is similar to the Quad Flat No-Lead (QFN) package, but thinner and with less parasitics. Second, we introduce wafer level type packages. The limits of standard wafer level packaging in respect to I/O counts pushed the development of the embedded Wafer Level Ball Grid Array (eWLB). We demonstrate the outstanding system integration capabilities of the eWLB including excellent mm-wave performance. For all the above mentioned packages chip and package technologies merge. They are door opener for nanoelectronic devices in respect to energy efficiency, mobility and security.
Compact Photonic Package for High-Power E-Band (60–90 GHz) Photoreceiver Modules
Authors: Rymanov V. , Palandöken M. , Dülme S. , Tekin T. , Stöhr A.
Published: October 2015

In this work, we present a novel photonic package for high-power photoreceiver modules operating within the E-band (60–90 GHz). The developed Kovar package features a compact size of only 6×3.5×2 cm3 and comprises an optical single-mode fiber (SMF) input, DC bias supply connections and a WR-12 output for coupling out of the radio frequency (RF) signal. As integration platform, a RF laminate submount with implemented planar bias-T based upon grounded coplanar waveguide (GCPW) transmission line circuitry is used for efficient mmW propagation, concluding in a GCPW-to-WR-12-transition. Finite element method (FEM) simulations have been carried out to analyze the frequency range of interest. Besides applied adhesive and wire bonding approaches for assembly inside the package, the RF submount exhibits sections for hybrid integration of single components, e.g. of a high-frequency waveguide photodiode. Optionally, up to two high-electron-mobility-transistor (HEMT) power amplifiers can be integrated within the GCPW circuitry. In addition, the RF laminate is mounted on a brass platform. For uniform thermal expansion within the module, a Peltier element is integrated. Concerning the saturation output power of given HEMT amplifiers, e.g. in the order of +17.5 dBm, corresponding power levels are achievable for packaged devices. For instance, an output RF power of only −19.5 dBm within the 71–76 GHz band is required from the photodiode in conjunction with two cascaded HEMT amplifiers, which results in a total gain of ~37 dB. A small series of the introduced device has been already fabricated. First experimental achievements with in-house fabricated modules will be presented.
Transient Thermal Analysis as a Test Method for the Reliability Investigation of High Power LEDs during Temperature Cycle Tests
Authors: Elger Gordon , Kandaswamy Shri Vishnu , Derix Robert , Wilde Jürgen
Published: October 2015

Light emitting diodes (LEDs) are today standard and mature light sources. They have several key advantages, like small size, low energy consumption and long lifetime. However, high reliability of the LED system is required to achieve long lifetime of the light source. Thermo-mechanical stress due to temperature cycle causes failure of electronic systems. The electronic component itself or the interconnect device, e.g. printed circuit board (PCB) might fail. In many cases, the weakest link is found to be the solder interconnect between package and the board. Cracking of the interconnect causes an open contact and the system fails.

In this paper we compare the existing methods to investigate LED interconnect failures during temperature cycle tests like the simple “light-on-test”, electric resistance measurement and the shear test. We describe and introduce the transient thermal analysis as a measurement method. We present the first reliability data analysis with transient thermal analysis of ceramic high power LED packages on Al-IMS during air to air thermal shock test (−40°C to +125°C) and correlate it with cross sections. We demonstrate the sensitivity of the thermal analysis to detect solder joint failures of the assembly. We compare the results with electric resistance measurements and light on tests and show that the resolution is significantly higher compared to the methods applied today. The sensitivity of the method enables us to detect the crack in a solder joint much earlier than the final failure of the joint, i.e. the open contact.
Non-contact characterization of printed resistors
Authors: Cordoba-Erazo Maria F. , Weller Thomas M.
Published: October 2015

In this work we demonstrate the use of a high resolution non-contact scanning microwave microscope for characterization of printed resistors. The resonant microwave probe operates at a frequency of 5.73 GHz and it is based on a dielectric resonator coupled to a gold-coated tungsten tip with radius of 200 μm protruding from a cavity wall. Direct print additive manufacturing was used to produce the resistive films. Non-contact measurements of the resonant frequency fr and quality factor Q of the resonant microwave probe at a standoff distance of 20 μm were performed. Quality factor images were obtained over a scan area of 160 μm × 1670 μm in steps of 10 μm. Measurements reveal that Q varies from 214 to 233 over the studied region. In this work, variations in Q are associated with non-uniformities on the resistor surface. The quality factor of the probe was also acquired as a function of the tip-sample distance and measured data was fitted to a polynomial equation. We converted Q images to sheet resistance images using the polynomial equation and the material resistivity (400 Ω/sq/mil). Using the proposed approach, we found that the average sheet resistance over the scan area is Rs = 1027 W/sq and that Rs variations up to 662 Ω/sq, due to non-uniformities in the resistor's thickness, were detected by the microwave microscope. The localized microwave characterization capability demonstrated by the non-contact microscope could be of interest for defect detection in printed microwave circuits.
Enabling a Manufacturable 3D Technologies and Ecosystem using 28nm FPGA with Stack Silicon Interconnect Technology
Authors: Kwon Woon-Seong , Kim Myongseob , Chang Jonathan , Ramalingam Suresh , Madden Liam , Tsai Genie , Tseng Stephen , Lai J.Y. , Lu Terren , Chiu Steve
Published: October 2015

Technology challenges and solutions in the development and manufacturing of Stacked Silicon Interconnect (SSI) Technology have been investigated with the established foundry and OSAT ecosystem. Key enabling technologies, such as TSV processing, interposer backside manufacturing yield enhancement, new stacking technology, interposer warpage control, micro-bump (μ-bump) processes and joining, that comprise the building blocks for SSI technology were developed. Xilinx 28nm FPGA with stacked silicon interconnect technology (SSIT) platform is used to develop and optimize the seamless integration of the processes, structures, parameter, as well as to evaluate the yield, reliability and device performance of them.
Non-Destructive Top Layer Bond Pad Cross Section
Authors: Collier Terence Q. , Gubeljic Indira
Published: October 2015

Contaminated and corroded aluminum bond pads can lead to a number of reliability failures. Poor wirebondability, false failures at electrical probe due to high contact resistance, opens on RDL layers due to incomplete sputter, and various early life failures during JEDEC testing can all be attributed to excess oxidation and corrosion on aluminum bond pads.

Understanding what layers exist on the bond pad surface is critical. Oxides, hydrates, xyfluorides and various soups of materials can be confirmed from combinations of Auger, SIMMS and FTIR but there is a chance the die can be damaged and the spot sizes can be problematic picking up information outside the bond pad target. Layer analysis of the pad can also be difficult since sputtering rates vary based on the contaminants on the pad and any thermal processing.

How does one evaluate bond pads without a destructive test? Is there a process for accurate bond pad evaluation while minimizing die damage? Sure. The cycle time and costs of these tests can also be a concern particularly for a customer wanting a quick response from failure analysis.

A better method is to bond the die with a gold stud bump followed by selectively etching away the gold. Etching the gold highlights the intermetallics and shows how much of the gold alloyed with aluminum versus blocked oxides. Voiding can be demonstrated, that might be misconstrued as Kirkendall voiding, by cross sectional analysis.
Study of Wirebonding on Thin Al Pads with Various Size Probe Marks
Authors: Forhan Andrew , Sharma Shashi , Subedi Prakash , Whittaker Dustin , Hunter Stevan
Published: October 2015

IC bond pads having thin pad aluminum (Al), less than 0.7μ thick, were probed multiple times by a variety of cantilever probe tips. Probe marks were created by an experimental high force probe card having various tip diameters. A finite element model of the probe tip was matched to the probe mark scrub length to gain a little more academic understanding of what to expect as probe parameters vary. Simulations using this model will be helpful in the future for situations where physical experiments are difficult or costly to run. Bond pads in the experiments include various ON Semiconductor circuit under pad (CUP) structures having Al metallization and silicon dioxide (SiO2) interconnect, previously demonstrated to be robust against cracking when compared against traditional IC bond pads. Smaller ball size and bond contact area are desirable as pads shrink on future products, but this will heighten any adverse effects of probe marks due to the relative % area increase beneath the bond. Experiment evaluations include bond pull strength (BPS), and bond shear (BS) for gold (Au) ball bonds of varying ball diameters over the wide range of probe marks, to begin checking the validity of a customary “probe mark area” maximum limit in wirebonding. Data indicates that large, deep probe marks can indeed bond ball lift fails, especially for non-optimized bonding recipes. It appears that probe mark depth, not area, is the most adverse factor in bond reliability. No issues relating to bonding over probe marks are expected in the more controlled and “gentle” manufacturing situations.
Ultra-Thin Flexible Ceramic Membranes for Electronic Applications
Authors: Olenick John A.
Published: October 2015

In 2010, ENrG Incorporated commercialized 40 microns thick, flexible zirconia based ceramic membranes as shown in Figure 1. Even though so thin, the membranes are gas-tight, fully dense, strong, thermal shock tolerant and chemically inert. Historically, zirconia membranes are used mainly for applications such as solid oxide fuel cells and oxygen sensors, making use of the ionic property of partially stabilized zirconia at elevated temperatures.
Thin-Wafer Handling with a Heat-Spreader Wafer for 2.5D/3D IC Integration
Authors: Lau J. H. , Chien H. C. , Wu S. T. , Chao Y. L. , Lo W. C. , Kao M. J.
Published: October 2015

Thin-wafer handling is one of the key enabling technologies for 2.5D/3D IC integration. Usually, it temporary bonds the TSV (through-silicon via)/RDL (redistribution layer) wafer (e.g., passive and active interposers) to a supporting carrier wafer with an adhesive, backgrinds the TSV/RDL interposer wafer to very thin (≤100μm), goes through all the necessary processes, and then de-bonds the thin TSV/RDL interposer wafer from the carrier wafer. In this study, a different route will be taken which eliminates the temporary bonding and de-bonding processes. Emphasis is placed on using a heat-spreader wafer as a supporting carrier wafer during the manufacturing processes and after the assembly is completed (diced), the heat-spreader remains on the thin TSV/RDL interposer. This is a very simple and low-cost thin-wafer handling method for 2.5D/3D IC integration.
Electroless Ni plating solutions for reproducible black pad analyses.
Authors: Kim K.H. , Yu Jin
Published: October 2015

A large-scale black pad of electroless nickel (EN) plated films were reproduced using pure chemicals: NiCl2·6H2O as the Ni source, NaH2PO2·H2O as the reducing agent, CH3COONa·3H2O and aminoacetate as the complexing agent and the buffer, respectively, and thiourea as the stabilizer. Plating baths with varying constituent compositions were investigated, and chemical compositions most suitable to the black pad study were sought. Cross-sectional scanning electron microscopy (SEM) and transmission electron microscopy (TEM) analyses showed that the nickel-phosphorus (Ni-P) film made out of the #5 bath best demonstrated the typical characteristics of the black pad phenomenon after the immersion gold (IG) process. Additions of a low level of Thiourea (0.6mg/L), slightly larger amounts of glycine (1∼1.25x) and the complexing agent (1.25x) were suggested from the standpoint of the black pad formation of Ni-P films.
Cost Comparison of 2.5D/3D Packaging to other Packaging Technologies
Authors: Palesko Chet , Palesko Amy , Vardaman E. Jan
Published: October 2015

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as an alternative to conventional packaging. Miniaturization and high performance product requirements are driving this move, although in many cases the cost of both 2.5D and 3D is still high.

In this paper we will identify the major cost drivers for 2.5D and 3D packaging and assess cost reduction progress, including current costs versus expected future costs. We will also compare these costs to alternative packaging.
Analysis of the Thick Film Deposited on Alumina Substrate and Effect of Different Parameters on the Response of Propanol Using Taguchi Method
Authors: Gaidan Ibrahim
Published: October 2015

It is well known that the gas sensor fabrication condition is affected by various parameters, such as the sensing materials, the amount of additive materials and several fabrication conditions. The goal of study of these parameters is to increase the sensitivity of the measurement system by reducing its variability. It is important that measurement systems provide an accurate and robust performance over a wide range of input conditions. Under these conditions, the system is said to have a robust design. However, the need for cost effective, sensitive and selective gas sensors led to the use of Taguchi methods to select the optimum sensor and its condition. Robust design gives us the tools to minimize the effects of chance and to maximize control of our process or experiments. This work deals with the effect of some factors on the response of the various composition of sensors to propanol. In this study the sensors were deposited on alumina substrates with copper thin film electrodes. The results were confirmed using two statistical methods, namely, analysis of mean (ANOM) and analysis of variances (ANOVA).
Inspection and Metrology Solutions from TSV through Reveal for High Volume Manufacturing
Authors: Dudley Russ , Marx David , Roy Rajiv , Grant David , Wilson Matt , Balak Scott
Published: October 2015

As the industry is investigating more cost-effective and reliable Cu Pillar Bumping as well as TSV, a key enabler is process control through inspection and metrology. In working with the industry, Rudolph has developed a suite of solutions that incorporate inspection, metrology and software enabling rapid yield ramp. The solution set applies to via etch, CMP, RDL, micro-bumping and all the way to Chip on Wafer mount and post-saw. As an example, within the TSV process a challenging inspection is that of detecting defects after CMP and nail reveal. The bonded wafers are warped, there are no alignment fiducials and the resolution requirement is high. Rudolph has developed a specific solution designed to address the nail reveal defectivity issue as well as metrology sensors to measure the nail height. Micro Pillar bumps and C4 bumps are the main bump geometries used in 3D packages as their small pitch and size allow the required number of I/Os. Rudolph will discuss an inspection system that incorporates multiple metrology sensors to provide complete 2D and 3D measurement and inspection solutions.