bluuebunny/crossref_metadata_2025 huggingface dataset:
Polypyrrole/Poly(Methylene Blue) Composite Electrode Films on Stainless Steel
Authors: Godwin Jonathan M. , Evitts Richard
Published: March 2011

Polymerized methylene blue films have been shown to be efficient electron mediators for biological redox compounds. Previously these films have been deposited on noble metal and carbon substrates. In this work, methylene blue has been polymerized on stainless steel by first applying a layer of an electronically conductive polymer to inhibit passivation or corrosion of the metal and to increase the active surface area. The redox activity of the resulting electrodes has been examined by electrochemical impedance spectroscopy and fit to an equivalent circuit model for conductive polymers. The film with methylene blue shows a large decrease in charge transfer resistance, from 130 Ω to 15 Ω, when compared to the bare polypyrrole film. The stability of the films was studied by measuring the impedance changes over time when stored in aqueous solutions. Degradation of the films was found to depend mostly on the doping ion used in the polypyrrole synthesis. NADH oxidation was also measured at different concentrations by CV.
Molecular Layer Deposition of Conductive Hybrid Organic-Inorganic Thin Films Using Diethylzinc and Hydroquinone
Authors: Yoon Byunghoon , Lee Younghee , Derk Alan , Musgrave Charles , George Steven
Published: March 2011

Conductive hybrid organic-inorganic thin films were fabricated by molecular layer deposition (MLD) methods using diethyl zinc (DEZ) and hydroquinone (HQ). Sequential exposures of DEZ and HQ led to linear MLD film growth. The mass gains measured by quartz crystal microbalance investigations were 52.3 ng/cm2 per MLD cycle. Scanning electron microscope images of focused ion beam milled cross-sections of the MLD film were consistent with a MLD growth of 1.6 Aå per cycle at 150oC. The DEZ/HQ MLD films were conductive based on four-point electrical probe measurements.
Formation and Oxidation Behavior of Diffusion-Barrier-Coating System on γ-TiAl
Authors: Żurek Zbigniew , Stawiarski Adam , Jaroń Artur , Gil Aleksander
Published: March 2011

The results of the work presented here refer to a high temperature oxidation of TiAl alloys coated with a protective layer of nickel aluminide. The nickel aluminide layer was formed by the method of pack aluminization of nickel coating which is electrochemically positioned onto the alloys surface. Prior to nickel plating, TiAl alloys underwent the process of aluminization leading to the formation on their surface of a layer enriched with Al. It has been established that during the aluminization the electrochemical nickel layer transforms into a protective layer of nickel aluminide Ni2Al3. The alloys Ti48Al2Cr2Nb and Ti48Al7Nb covered with the coating were exposed to oxidation in the air atmosphere at a temperature of 800oC. The layer of NiAl is covered with the Al2O3 scales during the oxidation. Inter-metallic phases containing Ni, Al, Ti, Nb are formed in the coating and in the near-surface alloy layer.
Effect of NO2
- in the Corrosion Behavior of Cerium Based Conversion Coatings on AA6061-T6
Authors: Kiyota Sayuri , Valdez Benjamín , Zlatev Roumen , Stoytcheva Margarita , Iñiguez Cesar
Published: March 2011

Cerium based conversion coatings were immersion deposited on AA6061-T6 and characterized to determine the effect of NO2- as an additive in the conversion solution on the anticorrosion behavior. The NO2- addition to the cerium chloride and hydrogen peroxide solution improved the corrosion resistance and coating morphology. Electrochemical measurements were performed by potentiodynamic polarization (PDP) and electrochemical impedance spectroscopy (EIS) in 0.01 M NaCl aqueous solution and the coating morphology was analyzed by Atomic Force Microscopy (AFM).
Microstructure, Corrosion Resistance and Adhesive Strength of Calcium Phosphate Coatings Formed on Pure Magnesium by a Simple Immersion Method
Authors: Tomozawa Masanari , Hiromoto Sachiko
Published: March 2011

Octa-calcium-phosphate (OCP) coatings were formed at weak acid on pure magnesium by a hydrothermal treatment. The microstructure of the coatings was investigated with XRD, SEM and TEM. At initial stage of treatment, a dual-layer coating consisting of an inner dense layer and an outer layer composed of plate-like crystals was formed. Both the layers grew with an increase in the treatment time up to 7.2 ks. Further increase in the treatment time caused the following change in the coating; (1) suppression of the coating growth, (2) partial change of OCP in the inner layer into hydroxyapatite (HAp) and (3) growth of a Mg(OH)2 layer at the interface between the coating and the Mg substrate. The adhesive strength of the coatings decreased with the growth of the Mg(OH) layer. The corrosion resistance of the specimens in a 3.5wt% NaCl solution increased with the growth of the coating.
Self-Lubricative Coatings Deposited by Microplasma Oxidation on 7075-T6 Aluminum Alloys in the Solution of Aluminate/Molybdenum Disulfide
Authors: Hua Chia-Jung , Lee Jeou-Long , Lu Chin-Yuan , Lin Yu-Chia , Yang Mu-Rong
Published: March 2011

The corrosion- and wear-resistant coatings on 7075-T6 aluminum alloy were prepared using micro-plasma oxidation in aqueous electrolytic solution with different amounts of solid MoS2 powder of 2μm. The bipolar rectangular pulse with a frequency of 1000Hz potentiostatically and galvanostatically is used in this work. The results indicate that the corrosion resistance and wear resistance can be further improved by the addition of MoS2 powders in solution. The optimal amount of solid MoS2 powder in electrolytic solution (2g/L) will substantially enhance the corrosion resistance, increase the hardness of MAO coatings and improve the wear resistance, irrespective of potentiostatic and galvanostatic power supply.
Evaluation of Credibility of Plasma Spray Biocompatible HAp Coatings by Electrochemical Impedance Technique
Authors: Take Seisho , Kasahara Manami , Itou Yuki , Kawaguti M. , Ohshima Mikihiro , Itoi Yasuhiko
Published: March 2011

Biocompatible plasma spray hydroxyapatite (HAp) coatings on metallic substrates have been conducted. The credibility of HAp coatings on SUS316L stainless steel and the effect of heat treatment were assessed by electrochemical impedance monitoring in physiological saline. The adhesion of HAp coating on SUS316L was evaluated by three-point bending test. It was found that post heat treatment improves not only crystallinity but also the credibility of HAp coatings on SUS316L stainless steel. Also, the corrosion resistance of HAp coating on SUS316L was improved by lowering the cooling or heating rate during post heat treatment process. It was found that plasma titanium intermediate layer played an important role both in improving corrosion resistance of HAp coating on SUS316L stainless steel and in increasing the adhesion of HAp coating layer to the metallic substrate. Zn doped HAp plasma spray coatings was prepared and its credibility was evaluated by electrochemical impedance measurements.
Anodic Dissolution of Refractory Metals in Choline Chloride Based Binary Mixtures
Authors: Abbas Qamar , Binder Leo
Published: March 2011

Choline chloride (CC) based binary mixtures have physicochemical properties that are comparable to the ionic liquids, that is why they are put in deep eutectic solvents (DESs) category of ionic liquids. Refractory metals like molybdenum (Mo) and tungsten (W) are studied for anodic dissolution in these DESs and faradaic current efficiency of dissolution was calculated for these metals. Anodic dissolution depends on the ability of hydrogen bond donors (HBDs) to engage and solvate the free chloride ions. Urea, ethylene glycol (EG) and glycerin (Gly) were used as HBDs with choline chloride for making deep eutectic solvents (DESs). Cyclic voltammeteric measurements show the large electrochemical window that these binary mixtures exhibit. Both the metals show almost no passivation in these media. Weight loss measurements show faradaic current efficiencies for both the metals up to 80% for choline chloride and glycerol, 30% for choline chloride and ethylene glycol, 17% for choline chloride and urea. It was also found that decreasing the current density increases dissolution efficiency.
The Synthesis of New Organic Polymers with Anticorrosive and Antiscaling Action for Protection of Industrial Cooling Water Systems
Authors: Branzoi Florina , Branzoi Ioan Viorel , Stanca Angela
Published: March 2011

Using microwave energy new organic polymers were synthesised by radical polymerization. These new organic compounds have anticorrosive and antiscale properties and for this reason, were used for cooling water systems protection. We presume that these new organic polymers inhibit corrosion of carbon steel by a protective mechanism, forming insoluble iron complexes and repairing the porous oxide layers. The methods employed were potentiodynamic polarization, electrochemical impedance spectroscopy and metallurgical microscopy techniques. The addition of the organic inhibitors led in all cases to inhibition of the corrosion rate. The corrosion parameters obtained from polarization curves and from EIS spectra are in good concordance and point out the inhibitory action of these new organic polymers. The adsorptions of the organic compounds on the carbon steel surface obeyed Langmuir's isotherm. Using Fourier transform infrared spectroscopy (FT-IR) the adsorption of organic inhibitors and the formation of corrosion products on the carbon steels surface was demonstrated.
Electrochemical Deposition of γ-Phase Zinc-Nickel Alloys from Alkaline Solution
Authors: Conrad Heidi , Corbett John , Golden Teresa D.
Published: March 2011

Zinc-nickel alloys with 8-15% nickel were deposited onto stainless steel for corrosion protection. Alkaline deposition conditions were utilized given that alkaline systems have been found to offer superior substrate coverage which results in better corrosion protection of the metal substrate (stainless steel) compared to acid bath depositions. This method utilizes ammonium hydroxide as the base source with a working pH range of 9-9.5. Sodium acetate was used as the complexing ligand as it was found to stabilize the metal ions in the electrolytic solution. Strongly adhering, quality deposits were obtained with electrodeposition at room temperature. Bath compositions and applied potential had an effect on morphology of the films as seen in scanning electron microscopy. Upon examination by x-ray diffraction and atomic absorption spectroscopy, all deposits were confirmed as γ phase zinc-nickel alloys with a nickel content of 8-15%. The corrosion potential for the γ-phase coatings was improved over the pure zinc coatings.
High Temperature Oxidation of TiAl Alloys Treated by Fluorine Resin
Authors: Gil Aleksander , Żurek Zbigniew , Stawiarski Adam , Dąbek Jarosław
Published: March 2011

Surface treatment of γ-TiAl based alloys by the small amounts of halogens leads to the formation the protective Al2O3 scale instead of the fast growing mixed TiO2/(TiO2+Al2O3) scale. The halogens can be applied by ion techniques as well as by spraying or dipping with halogen-containing inorganic and organic compounds. Deposition of the fluorine-containing resin on the surface of TiAl alloys is the easiest way to achieve the best results. This work presents the results of microscopic studies of the oxidation behavior of a Ti-48Al-2Cr and Ti-47Al-6Nb (at.%) alloys non-treated and treated with resin containing amino-fluoride. The oxidation runs were carried out in the temperature range 900-1000°C in pure synthetic air.
Corrosion Inhibitor for Use in Giant Magnetoresistance (GMR) Biosensors
Authors: Liu Zengcai , Wang Yi-Ju , Litvinov Julia , Chinwangso Pawilai , Willson Richard , Litvinov Dmitri
Published: March 2011

We use corrosion inhibitors, for the first time, to protect GMR biosensor from corrosion in phosphate buffer saline (PBS) solution. A very uniform thin protective film (5-10nm) is formed on the surface of biosensor (including contacts). To make this protective film more effective, a multi-step process is developed. In the first step, protective film is formed in deionized water containing corrosion inhibitors with minimum initial corrosion and defects. Biosensors are then immersed in PBS solution containing corrosion inhibitors. In this step, any defects due to the attack of chloride ions could be self-repaired in the presence of corrosion inhibitors. Finally, biosensors with protective film are ready to test in PBS solution without any corrosion inhibitors. The exciting results show that as-prepared protective film is stable in PBS solution without any inhibitors for up to 15 days.
Comparison of Diffusion Mechanisms in Si Bulk, Nanomembranes, and Nanowires
Authors: Ndoye Coumba , Liu Tong , Orlowski Marius
Published: March 2011

Diffusion of dopants in silicon is studied in nanostructures and benchmarked against the bulk diffusion. In thin Silicon On Insulator (SOI) MOSFET devices, the lateral diffusion of dopants in Si is expected to be different than in the bulk because of reduced dimension effects and segregation effects which become more severe due to the proximity of interfaces. The large spot size makes SIMS impractical to obtain the doping profile in lower dimensional structures. Thus, the lateral diffusion from source and drain regions into the channel is evaluated by electrical characterization after series of long anneals. In contrast to bulk, nanomembrane and nanoribbon structures which, as expected, show decrease of channel resistance with diffusion time, it is observed that in nanowires the channel resistance increases. This effect is a result of competing diffusion and strong interface segregation effects which slow up lateral diffusion and renders large portion of the dopants inactive.
Influence of Alkaline Chemicals on Electrical and Optical Characteristics of Ga-Doped ZnO Transparent Thin Films
Authors: Yamamoto Naoki , Osone Satoshi , Makino Hisao , Yamamoto Tetsuya
Published: March 2011

A wet-chemical etching technique was successfully developed for patterning Ga-doped ZnO (GZO) fine lines (line/space: 2/2 um) comparable to those of indium-tin-oxide (ITO) electrodes used in current leading-edge liquid crystal displays (LCDs). This includes the development or selection of alkaline solutions for the lithography process and the acidic solutions for the etching of GZO films, in addition to optimization of the processing recipes.
Misalignment Study by Etch Induced Silicon Damage in Single Crystal Etch Process for Shallow Trench Isolation Structure
Authors: Lee Jung-Chan , Lee Seung-Jae , Kim Mun-Jun , Lee Seung-Heon Lee , Oh Kyungseok , Lee Jun-Hee , Kang Man-Sug , Nam Seok-Woo , Roh Yonghan
Published: March 2011

We studied the misalignment between active and gate layer in terms of silicon dislocation caused by high temperature anneal process in SOG based STI gap-fill process. The SOG process is one of good candidates to overcome gap-fill limitation due to its excellent gap-fill characteristics. However, the SOG process needs high temperature anneal process to convert from Si-H, N-H to Si-O bond, which leads to the misalignment due to large stress change. We suggest that silicon defect is generated from ion bombardment at trench etch process and accelerated from hysteresis at anneal process. The O2 cure process is known as one of feasible methods to cure silicon damage through recrystallization. Based on this model, the misalignment was significantly improved as removing the defect through O2 cure process following trench etch process.
Characterization of Short Channel OTFTs Fabricated Using Ink Jet Print and Imprint Process
Authors: Kim Kyohyeok , Han Jaejun , Lee Sangmin , Chung Ilsub
Published: March 2011

We fabricated short channel organic thin film transistors on polyethersulphone (PES) substrate using ink jet printing combined with an imprint method. The channel lengths of organic thin film transistors (OTFTs) which were defined by imprinting Ag/PES film were 2.5 um, 3.8 um and 6.4 um, respectively. 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene and Polyvinyl alcohol (PVA) were used as an active material and as a gate insulator, respectively. The physical properties were obtained using Alpha step, SPM, and SEM. The gate transfer characteristics and drain family curves were measured using Keithley-4200. The field-effect mobility of OTFT was about 0.25 cm2/Vs in the saturation region, and the threshold voltage of OTFT was -2.5 V.
Study on 6,13-bis(Triisopropylsilylethynyl) (TIPS) Pentacene Crystalline Morphology for Organic Thin Film Transistor
Authors: Han Jaejun , Bae Injun , Chung Ilsub
Published: March 2011

We found that the crystallization of TIPS pentacene thin film plays an important role in determining the electrical property of organic thin film transistor (OTFT). OTFTs were fabricated using two different TIPS pentacenes, namely big grains and dendrite grains. Poly-4-vinylphenol (PVP) was used as a gate insulator, and Au electrode was evaporated using a shadow mask. The channel lengths of OTFTs with the bottom gate structure were 20-40 um. The mobility values of OTFTs fabricated with big grains reveal ten time higher values than those obtained from OTFTs fabricated with dendrite grains. The physical properties of the TIPS pentacene films were analyzed using optical microscope (OM), x-ray diffraction (XRD) and secondary electron microscopy (SEM). The electric characteristics of OTFT were obtained using Keithley-4200.
Synthesis and Photo Catalytic Studies of Nitrogen-Doped ZnO Particles
Authors: Jones Jason , Nandakumar Pat
Published: March 2011

The decomposition of zinc nitrate hexahydrate with molten ammonium pentaborate octahydrate resulted in nitrogen-doped ZnO particles. The homogenous mixture of nitrogen-doped ZnO particles was prepared by heating the mixture. Samples of increasing ammonium concentrations were synthesized and characterized and showed some increase in absorbency in the visible light region with increasing concentrations leading to an interest and application of more efficient solar cells and substantial advances in practices of the sort.
Deposition of ZnO Films by Sputtering and its Resistive Switching Properties
Authors: Wang Fang , Zhang Kailiang , Yang Baohe , Wang Lanlan , Song Kai
Published: March 2011

In this paper, ZnO thin films were deposited on the Cu/Ti/SiO2/Si substrates by radio frequency (RF) magnetron sputtering at different ratio of O2/Ar with 7:3, 6:4, 5:5, 4:6, 3:7. The effects of different ratio of O2/Ar on crystallinity and resistive switching behaviors of film were studied. XRD indicated that ZnO films are highly c-axis oriented, the crystal size is smallest at 60% oxygen ratio. AFM indicated the film has most uniform morphology at the same sample. Morphology and the resistive switching characteristics of this film were studied in situ by CSAFM. The results showed that the film was smooth and dense. The current image showed stable and superior electrical switching under different scan. This is proved by SPA (B1500A), which reveal the resistive switching characteristics of same sample.
Leakage Engineering Enabling PDSOI Ring Oscillators Operating in Sub-100pA/µm Ioff Regime
Authors: Ren Zhibin , Cai Jin , Robison Robert R. , Jagannathan Basanth , Park Dae-Gyu , Ning Tak H.
Published: March 2011

This work presents hardware demonstration of low power operation of PDSOI CMOS (Ioff down to ~10pA/µm at Vdd=0.9V, 45nm node) transistors, exhibiting successful operation of low leakage ring oscillators (channel and junction leakage ~30pA/invertor stage at Vdd=0.9V, 25C with 101 stages, pFET width=1.2µm, nFET width=0.8µm in each stage). The work highlights device and process feasibility study (through an asymmetric source/drain design) of enabling a PDSOI CMOS based low power application platform.
Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology
Authors: Liu Qing , Yagishita Atsushi , Kumar Arvind , Loubet Nicolas , Yamamoto Toyoji , Kulkarni Pranita , Monsieur Frederic , Khakifirooz Ali , Ponoth Shom , Cheng Kangguo , Haran Bala , Vinet Maud , Cai Jin , Khare Prasanna , Monfray Stephane , Boeuf Frederic , Mehta Sanjay , Kuss James , Leobandung Effendi , Hane Masami , Bu Huiming , Ishimaru Kazunari , Skotnicki Thomas , Kleemeier Walter , Takayanagi Mariko , Hook Terence , Khare Mukesh , Luning Scott , Doris Bruce , Sampson Ron
Published: March 2011

We report fully-depleted UTBB devices with a gate length (LG) of 25nm and BOX thickness (TBOX) at 25nm, fabricated with a 22nm technology ground rule, featuring conventional gate first high-K/metal and raised source/drain (RSD) process. Competitive drive currents are achieved. Effective Vt modulation is observed with back bias (Vbb) and different ground plane (GP) polarity. Excellent local Vt variation is demonstrated. A functional UTBB 0.108μm2 6-T SRAM is reported with Vdd down to 0.4V. We also present simulation studies that suggest UTBB device has superior scalability compared with thick BOX ETSOI device, thanks to better short channel effect (SCE) control.
Scaling MOSFETs with Self-aligned Super-Steep-Retrograded Halo (3SRH)
Authors: Wu Binneng , Xiao Weiping , Zhu Huilong , Liang Qingqing , Wu Hao , Yin Haizhou , Luo Zhijiong , Yu Hongyu , Chen Dapeng , Ye Tianchun
Published: March 2011

In order to take the advantages of the replacement gate process, improve the control of SCE, and enhance the performance of CMOSFETs, a novel method of self-aligned super-steep-retrograded halo (3SRH) implantation is designed and presented in this paper. With process and device simulations, it's demonstrated that 3SRH can be used to enhance MOSFET performance.
Electrostatic Discharge (ESD) Protection Challenges of Gate-All-Around Nanowire Field-Effect Transistors
Authors: Liu Wen , Liou Juin J. , Singh N. , Lo G. Q. , Chung J. , Jeong Y. H.
Published: March 2011

Electrostatic discharge (ESD) performance, including trigger voltage, failure current, on-resistance and leakage current, of the gate-all-around silicon nanowire field-effect transistor depends on nanowire diameter, gate length and nanowire numbers. The device with best ESD robustness has medium gate length, small diameter and a large number of nanowires with multi-finger-multi-channel layout.
Characterization of Random Telegraph Signal Effects for 0.18um Technology
Authors: Ji Yuanqian , Dai Sutter , Wei Minxia , Lu Xiangdang , Zhang Sunny , Xu Daniel
Published: March 2011

The paper gives a summary of RTS noise data captured from 0.18um technology. It can be a reference for the channel area and voltage bias selection for RTS measurement.
Effect of AlGaN Barrier Thickness on the Noise of AlGaN/GaN High Electron Mobility Transistors
Authors: Yahyazadeh Rajab , Hashempour Zahra
Published: March 2011

An analytical- numerical model for the drain source and gate source currents of AlGaN/GaN based HEMTs has been developed that is capable to predict accurately the effects of AlGaN barrier thickness on the cut off frequency and noise in different gate source and drain source biases. Salient features of the model are incorporated of fully and partially occupied sub-bands in the interface quantum well, combined with a self-consistent solution of the Schrödinger and Poisson equations. In addition current in the barrier of AlGaN, traps density in AlGaN are also take in to account. The calculated model results are in very good agreement with existing experimental data for HEMTs device.
Structural effects of Channel Cross-Section on the Gate Capacitance of Silicon Nanowire Field-effect Transistors
Authors: Sato Soshi , Kakushima Kuniyuki , Ahmet Parhat , Ohmori Kenji , Natori Kenji , Yamada Keisaku , Iwai Hiroshi
Published: March 2011

We investigated the gate capacitance of the SiNW FETs using T-CAD software. The smaller equivalent oxide thickness of the SiNW FETs was obtained compared with the planar FET that had the same oxide thickness down to sub-1 nm. Gate capacitance of the SiNW FET substantially increased with thinner physical oxide thickness compared with planar FET. SiNW structure with thinner gate oxide thickness is effective for improvement of off characteristics.
Process Impact and Design Optimization on the Soft Yield of 25nm FinFET SRAM Cells
Authors: Li Meng , Liang Qingqing , Zhu Huilong , Zhong Huicai , Chen Dapeng , Ye Tianchun
Published: March 2011

A simulation methodology to correlate process variations to the soft yield of 6-T FinFET SRAM cells is demonstrated. By using the TCAD tool which is calibrated to the recently published 25nm FinFET technology, process impacts on the device electrical characteristics are simulated and stored in behavioral models. Circuit simulations can then be carried out to calculate the read/write noise margin. Employing the linear function approximation of the noise margin with respect to the six individual process variation parameters in sigma, one can analytically solve the yield when noise margin drops to zero. The calculation results show that instead of Vt variation, parasitic resistance fluctuation dominates fails at high bias voltages. A simple design optimization guideline is also demonstrated to reduce Vmin of the given technology (to 0.5V in this work). This methodology can serve as useful guidelines for both process development and device design.
TiN/W/La2O3/Si High-k Gate Stack for EOT below 0.5nm
Authors: Ahmet Parhat , Kitayama D. , Kaneda T. , Suzuki T. , Koyanagi T. , Kouda M. , Mamatrishat M. , Kawanago T. , Kakushima Kuniyuki , Tsutsui Kazuo , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori T. , Iwai Hiroshi
Published: March 2011

Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved in the gate stack with a 3nm W inserted layer after annealed at 800oC in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates in realizing high-k gate stack with EOT 0.5nm and beyond.
PMOS Source/Drain Extension Dopant Species effect on Device and SRAM Performance
Authors: Liu Jinhua , Zhou June , Wang William , Guo Rita , Zhang Leo , Shen ZhaoXu , Wang Brisk , Zhou Allan , Hao Humbert , Cui Jimmy , Ning Jay
Published: March 2011

It is shown in the study that Arsenic improves 30% device Idsat variation compared to Ph implantation. SRAM Vccmin value may be improved around 4% too. While it is found that, compared to Ph implantation, Arsenic critically increases junction leakage current, which may account for more than half part of the total off current for high threshold voltage (Vth) device with gate length less than 50nm. The large junction leakage current also leads to 5% device performance degradation and SRAM stand by leakage current (Istby) 15% increasing. Device reliability study exhibits that PMOS negative bias temperature instability (NBTI) performance is deteriorated by Arsenic implantation.
A Novel Tunnel Oxide Based Tunnel FET
Authors: Wang Hefei , Luo Zhijiong , Yin Haizhou , Zhu Huilong , Liu Jia , Zhu Zhengyong
Published: March 2011

In this work, we propose a novel tunnel oxide based Tunnel FET. This novel Tunnel FET can achieve high drive currents, low SS, low off currents and many other superb device characteristics. From device simulation, this novel device can obtain drive currents 100x higher than that of a conventional Tunnel FET. This novel device also can realize SS as low as 30mV/dec. Moreover, this novel device has potential to significantly reduce off currents, and suppress the ambipolar behavior existing in conventional Tunnel FETs. In addition, the novel device can obtain the ability to scale down without performance degradation due to the unique scalability of tunnel oxide. These excellent device characteristics make the novel Tunnel FET an ideal device structure for future LSTP applications.
Modeling of Electron Transport in III- Nitride Compound Semiconductors for Low Field and Low Temperature Applications
Authors: Chakrabarti Souradeep , Gupta Chatterjee Shyamasree , Chattopadhyay Debasish , Chatterjee Somenath
Published: March 2011

The doping concentration, doping compensation and temperature dependency of electron mobility for GaN, InN, AlN have been calculated using the relaxation time approximation method considering parabolic nature of energy bands. The change in position of Fermi energy with the temperature as well as electron concentrations has been plotted to observe the level of degeneracy for different III-nitride samples. According to the change of Fermi level we have implemented different statistics for mobility extraction modeling at low temperature and low electric field. We compare our simulated results with experimental data and find reasonable correlations, but with evidence that structural imperfection and compensation play crucial roles in our studied samples. Compensation ratio e.g. 0.23 for GaN has been significant in charge neutrality condition. We observe that after 150K the theoretical mobility values deviate from the experimental data. The reasons for the discrepancy are discussed.
Performance Improvement of Si-NC Memory Device by Using a Novel Junction Assisted Programming Scheme
Authors: Jiang Dandan , Huo Zongliang , Zhang Manhong , Wang Qin , Liu Jing , Yu Zhaoan , Yang Xiaonan , Wang Yong , Zhang Bo , Chen Junning , Liu Ming
Published: March 2011

To enlarge memory window of Si nanocrystal (Si-NC) memory devices, a junction assisted programming scheme is proposed in this paper. Firstly, a negative drain voltage pulse is applied to forward-bias PN junction and charge junction capacitance. After that, a conventional channel hot electron (CHE) programming scheme is immediately used. Comparing with conventional CHE programming scheme, this proposed scheme shows a much larger memory windows. Meanwhile, high program speed, good endurance (over 104 cycling times) and better data retention have also been achieved from experiment.
0.18 Micron BiCMOS Process with Novel Structure SiGeC HBT
Authors: Liu Donghua , Qian Wensheng , Chen Xiong Bin , Chen Fan , Hu Jun , Xiao Sheng'An , Wang Yungchung , Chiu Tzu-Yin
Published: March 2011

This paper reports a manufacturable process of 0.18 micron SiGe BiCMOS integrating novel structure SiGe HBTs and 0.18 micron foundry-compatible CMOS devices. N-type SiGe HBT is newly designed by removing deep trench isolation, N+ sink collector pick-up and collector epitaxial growth. Instead, junction isolation, collector pick-up of deep contact through field oxide and implanted collector are used in SiGe HBT. The peak fT and fmax of N-type high speed SiGe HBT are 120GHz and 110GHz, respectively and the size of SiGe HBT is only half as conventional one. CMOS front-end process steps except P+ source/drain implants and RTA are prior to that of SiGe HBTs to minimize the impact of CMOS thermal budgets on SiGe HBT.
Low-Power Design of Double Edge-Triggered Static SOI D Flip-Flop
Authors: Xing Wan , Song Jia , Gang Du
Published: March 2011

In this paper, a double edge-triggered (DET), static SOI D flip-flop design suitable for low power and low area application is proposed. Silicon on insulator (SOI) is particularly good for low-power digital systems. Based on SOI technology instead of bulk silicon we realized a novel single edge-triggered (SET) static SOI D flip-flop using only ten transistors thus resulting in low-power consumption. Based on the SETDFF, a double edge-triggered D flip-flop is further constructed with an upper path and a lower path connected between the data input and an output node. Compared to single edge-triggered D flip-flop which processes data only at either the rising or falling transition of the clock, the DET D flip-flop doubles the rate of data thereby, increasing the data throughput. Simulation results indicated that the circuit is capable of significant power saving.
Effects of Oxygen Flow Ratios and Annealing on TiOx Deposited by Reactive Magnetron Sputtering
Authors: Wang Lanlan , Zhang Kailiang , Wang Qi , Wang Fang , Wei Xiaoying
Published: March 2011

Titanium oxide (TiOx) thin films were deposited on Cu (111)/Ti/SiO2/Si substrates by direct-current reactive magnetron sputtering at 3-15% oxygen flow ratios, then annealed by vacuum at 650° for 40min. The morphology, phase, and resistive switching behaviors of the as-deposited and annealed TiOx thin films were analyzed by atomic force microscope (AFM), X-ray diffraction (XRD), and semiconductor parameter analyzer (SPA), respectively. The results of X-ray diffraction (XRD) showed that annealing TiOx caused crystal structure changes compared to the as-deposited TiOx film. From XRD, the as-deposited TiOx films were practically amorphous. In contrast, the distinct crystalline peaks of anatase and rutile phases was detected at 10 FO2% by 650° annealing and exhibited stable and superior resistance switching behaviors due to deep-level emissions of oxygen vacancies in the rutile and anatase phases.
Robustness Enhancement in Optical Lithography: From Pixelated Mask Optimization to Pixelated Source-Mask Optimization
Authors: Jia Ningning , Lam Edmund Y.
Published: March 2011

Optical lithography is facing a great challenge from the continuous shrinkage of industry node toward 22nm or below. The increasing sensitivity to process variations becomes a key problem hindering further progress. To address this problem, inverse lithography, which designs pixelated masks with appropriate algorithms, is favored for its capacity of exploring a larger solution space. This search capacity, however, is limited by the fixed source configuration. To this end, optimization of pixelated source and pixelated mask together has come up for further performance improvement. In this paper, a source-mask co-optimization (SMO) algorithm, which incorporates process variations into the optimization scheme, is introduced. To further improve the process robustness, we apply weighted total variation and aerial image intensity control as regularization. Simulation results show that we achieve greater pattern fidelity and enhanced process robustness by using SMO.
Use of DBARCs Beyond Implant
Authors: Washburn Carlton , Lowes Joyce A. , Guerrero Alice
Published: March 2011

Almost a decade ago, the integrated circuit (IC) industry realized that traditional implant layers required new technology to achieve the specifications of the shrinking design rules and increased topography effects. In response, developer-soluble bottom anti-reflective coatings (DBARCs) were introduced as a solution. DBARCs offered the resolution and critical dimension (CD) control needed for the increasingly critical implant layers. In this paper the benefits DBARCs can bring to other lithographic processes are reviewed. Back-end-of-line (BEOL) dual damascene processes are surveyed. Front-end-of-line (FEOL) processes are examined, including high-k metal gate (HKMG), double patterning, and spacer. All processes are defined, and the value that a DBARC brings to each process is examined, along with potential challenges.
Development of Under Layer Material for EUV Lithography
Authors: Sakamoto Rikimaru , Ho Bang-Ching , Fujitani Noriaki , Endo Takafumi , Ohnishi Ryuji
Published: March 2011

For the next generation lithography (NGL), several technologies have been proposed to achieve the 22nm-node devices and beyond. Extreme ultraviolet (EUV) lithography is one of the candidates for the next generation lithography. For lithography processes, the Line width roughness (LWR) and the pattern collapse of resist are the most critical issues for NGL, because of the small target critical dimension (CD) size and high aspect ratio. In this study, we design the new concept of EUV Under layer (UL) material to meet these requirements and study the impact of polymer design for pattern collapse behavior, pattern profile and LWR control by using EUV exposure tool.
Limit of Line End Shortening Correction under Single Exposure in 193 nm Immersion Lithography
Authors: Wu Qiang , Xu Yao , Hao Jingan , Liu Chang , Shi Xuelong , Gu Yiming
Published: March 2011

As the lithography starts to approach the limit of 193 nm immersion imaging capability under single exposure, successful development of a lithographic process rely on the good balance of the process parameters, such as the exposure latitude and depth of focus for the dense, semi-dense, isolated structures, MEF, LWR, proximity bias, etc. Such balance requires very good understanding of the inter-relationship among them and ways to give reasonable specification to the important materials such as photoresist and photomasks. Although, relatively speaking, 1-dimensional structures, such as, line and space or even square contacts are relatively easy to understand and model with accurate simulations, which is close to perfect, 2-dimensional structures are not easy to understand physically and the simulation for them are up to larger errors. Since previous study on this subject was either done at larger ground-rules or lack of good physical understanding in the simulation, this paper will use both experimental wafer measurement data and physical modeling to probe the limits for the OPC correction of line (or space) end shortening structures at around 50 nm dimensions. Several structures will be studied in theory and wafer data.
Studying Photoresist Type for Sub-32nm Node Dense SRAM 2nd GT Layer
Authors: Xu Yao , Hao Jingan , Liu Chang , Shi Xuelong , Wu Qiang , Gu Yiming
Published: March 2011

With continuous shrinking of device dimensions, high performance, dense SRAM cells design has become more challenging than before, patterning quality is also more sensitive to fluctuations in lithography process. This inevitably calls for more aggressive lithography process conditions in terms of the required resolution. The tradeoff between process window optimization for random logic gates and dense SRAM is not always straightforward, and it sometimes necessitates design rule and layout modifications. In particular, patterning the small tip-to-tip gap for dense SRAM cells at gate level becomes extremely challenging. By delinking patterning of SRAM tip-to-tip from other geometries, one can optimize the patterning processes independently at the expense of cost. This can be achieved through a special double patterning technique that employs a combination of double exposure and double etch (DE2).
Selective Removal of High-k Dielectrics
Authors: Shamiryan Denis , Paraschiv Vasile
Published: March 2011

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. The best results could be achieved by combination of both.
Reverse Phase Solution for Mesa Chamber Uniformity Improvement
Authors: Ge Qiang , Huang Ying , Tang Xiaoduo
Published: March 2011

Applied Materials® newly launched advanced 300mm plasma etcher, Mesa® chamber implemented many key hardware modification to provide much more robust process knobs to improve the depth uniformity and CD uniformity for critical applications of <32nm technology. The new features including DMC,MRAD and others features focus on the innovation of Top ICP Source to optimize ion flux distribution uniformity to improve the Etch Rate uniformity and CD uniformity. As result the whole wafer uniformity can achieve 1~1.5nm (3σ). This article will focus on two of new features: DMC and MRAD which can solve the special distribution map to further improve uniformity significantly. The discussion includes hardware fundamental introduction and plasma simulation result as well as supporting wafer result.
New Al Post-Etch Residue Remover with Al Surface Passivation Function
Authors: Wei Joyce C. , Huang Micky
Published: March 2011

A new Al post-etch residue remover with Al surface passivation function was developed. It is capable of removing polymer and inorganic residues with good compatibility to thin Aluminum, TiN, TaN, NiSi, and various silicon oxide films. A monolayer of passivation on the Al surface can be deposited in situ to prevent further oxidation and corrosion of the thin Al film. The passivation layer can be easily removed by a short plasma clean or baking to prepare the pristine Al surface for the successive processes. This solution is recommended for cleaning in FEOL high k/metal gate processes and contacts.
Dummy Poly Silicon Gate Removal by Wet Chemical Etching
Authors: Young Tao , Yin Huaxiang , Xu Qiuxia , Zhao Chao , Li Jun Feng , Chen Dapeng
Published: March 2011

For the gate last integration scheme, dummy poly silicon gate removal is one of the indispensable processes either for a high-k first or a high-k last route. In this paper, experimental results of dummy poly silicon gate removal using TetraMethyl Ammonium Hydroxide (TMAH) chemical etching are presented. The preliminary results show that the poly silicon removal rate was highly sensitive to the wet etch conditions. By optimizing the wet etch conditions, high selectivity of poly silicon with respect to SiO2, Si3N4 and hafnium silicon oxynitride (HfSiON) was obtained. A gate trench of critical dimension (CD) of about 70 nm without poly silicon residue was fabricated using optimized conditions. The excellent etch capability of the optimized wet etch process was also demonstrated by controlling trench profiles.
Ultrapure Water-Related Problems and Waterless Cleaning Challenges
Authors: Hattori Takeshi
Published: March 2011

Ultrapure water can cause several serious problems in modern semiconductor manufacturing. With device geometry shrinking and becoming more complex, conventional aqueous cleaning and subsequent drying tends to collapse high aspect-ratio nano-structures due to the high surface tension of water. The high resistivity of water can cause flow electrification during wafer rinsing and the high reactivity of water with oxygen and silicon forms watermarks on silicon surfaces. Furthermore, in the FEOL, some high-k gate capping materials dissolve in water while, in the BEOL, Cu is corroded in water during rinsing. If high-permittivity water remains in porous low-k interlayers after aqueous treatments, the k-value of the film increases. The solutions to all of these problems will be discussed. Finally, as the ultimate solutions, waterless cleaning techniques are described and discussed, which include HF vapor cleaning, cryogenic nitrogen aerosol cleaning, supercritical carbon-dioxide cleaning, and pinpoint cleaning such as nano-tweezer pickup.
Effect of O2/Ar Ratio on Etching of Diamond Films by MPCVD
Authors: Wang Shasha , Zhang Kailiang , Taofeng Zhang , Ren Jun
Published: March 2011

Because of its good properties, diamond can be used as protective film of optical components, optical window materials and radiator materials of high power optoelectronic components. But its rough surface has been an obstacle for widespread application. In this paper, etching of diamond films by ICP (Inductively Coupled Plasma) oxygen plasma which was used to improve the surface of the diamond films. After evaluating etch rates under different O2/Ar conditions, the etch mechanism is investigated. The results show that the surface roughness is reduced after etching. Etching rate increases with higher O2/Ar ratio. At the same time, when etching with a high O2/Ar ratio, the surface roughness is low. In conclusion, O2 and Ar plasmas, especially O2 plasmas, have a significant effect on etching of diamond films.
Prevention of AlCu Line Galvanic Corrosion after Fluoride Containing Stripper Cleaning: A Case Study
Authors: Luo Victor , Chang Jason , Shi Kevin , Liu Bing , Peng Libbert , Wang Andrew , Sun Justan
Published: March 2011

In this paper, the status of galvanic corrosion on AlCu lines during the AlCu post etch and ashing residue removal process is studied with a fluoride containing stripper in details, including DIW rinse condition and dry process. The experimental data show that galvanic corrosion on AlCu lines is not observed in the chemical cleaning process, but inclined to be caused by the rinse and dry processes in this case. Different scenarios in the rinse process, such as overflow or quick dump rinse (QDR), the times of quick dump rinse cycles, CO2 bubbled DIW and metal protection solution rinse, are studied. At the same time, two kinds of dry processes are also evaluated. The results show the optimized rinse and dry processes can eliminate the galvanic corrosion on AlCu lines without the change of wafer manufacture prevenient process and cleaning solution.
Highly Selective Etching Solutions for Advanced Logic Technologies
Authors: Wang Xin-Peng , Zhang Hai-Yang , Chang Shih-Mou , Lee Kwok-Fung
Published: March 2011

As logic semiconductor moves to 65nm node and beyond, several process-enhancement technologies have come into prominence with the help of dry etch processes. In high-aspect ratio contact etch (CT) process, the sufficient over-etch during dielectric oxide etch without too much loss of SiN-based stop layer is required to maintain the enough process window for less silicide loss loading and leakage. Stress memorization technology (SMT) is designed to enhance the P-MOS performance. It removes the stressed nitride and stops on one thin oxide layer. The enough oxide remaining is also imperative to avoid silicon damage. Besides, the loading effect of nitride thickness in SRAM area has to be compensated. Highly selective etching process is indispensable to fulfill these tightening and newly-born process requirements. In this paper, we address the effect of etch parameters including pressure, chemistry, gas ratio and power on the etching selectivity between nitride and oxide film in the above two processes. Scanning Electron Microscope (SEM) is utilized to compare the final etched profile. Results demonstrate besides the etch chemistry and power ratio, the etcher selection also plays the vital role on etching selectivity and etch rate.
Controlled Etching of III-V Materials with Optical Emission Interferometry (OEI)
Authors: Johnson Chris , Johnson Dave , Westerman Russ , Geerpuram Dwarakanath , Martinez Linnell , Plumhoff Jason
Published: March 2011

For plasma etching processes, Optical Emission Interferometry (OEI) combines the advantages of Optical Emission Spectroscopy (OES) and laser interferometry. Radiation emitted by the plasma is reflected from the substrate surface and monitored using a multi-wavelength spectrometer. Analysis of the OEI signal can provide endpoint data, as well as etch rate and etch depth information for both single and multi-component materials. Examples of these applications are described.