Increasing the Operation Voltage of Integrated Solid-State Diodes through Nanostructured Porous Silicon Technology
Authors: Strambini Lucanos M , Marchesi Marco , Sambi Marco , Toia Fabrizio , Mariani Simone Dario , Morelli Marco , Barillaro Giuseppe 
Published: February 2020

Here, we report on the use of nanostructured porous-silicon (PS) technology as an alternative to standard field-plates technology to increase the operation voltage of silicon-based integrated solid-state devices. As a case study, we show that integration of nanostructured porous silicon in the high-field regions of a solid-state diode allows a significant increase of the breakdown voltage (VBR> 65V) to be achieved with respect to a reference diode (VBR=25V) under reverse-bias operation. On the other hand, the electrical characteristics of the diode under forward-bias operation are not affected from the presence of nanostructured PS. We argue that the nanocrystalline nature of PS reduces the mean-free path of charge carriers accelerated in high-field regions of the diode reducing, in turn, carrier velocity developed for a given applied voltage under reverse-bias operation.

A standard n+/p diode with size varying between 1 and 10 um is used as a reference in this work. Under reverse-bias operation, a depletion zone establishes across the np junction, with an intense electric field developing across the depletion zone at high reverse bias. The electric field has higher intensity in correspondence of the curved edges of the junction with respect flat central regions, due to the thinner depletion zone of the former. Therefore, charge carriers are highly accelerated in the curved regions of the np junctions giving rise to breakdown effects. Electrical measurements of the current-voltage curves of the diodes shows that: i) Ron in forward biasing is of a few tens to hundreds Ohm, depending on the size of the diodes; ii) the breakdown voltage VBD is of about 25 V.

The reference diode was modified through electrochemical conversion of p-type silicon to nanostructured porous-silicon in correspondence of the curved regions of the np junction. This allows the mean-free path of charge carriers in correspondence of the curved regions of the diode to be shorted and, in turn, carrier velocity developed at high electric field to be reduced under reverse-bias operation. Electrical measurements of the I-V curves of diodes modified with nanostructured PS highlight that: i) electrical characteristics of the diode in forward biasing are not affected by the presence of the PS layer (e.g. Ron changes of a few percent with respect to that of the reference diode); ii) the breakdown voltage of the diode in reverse biasing is increased to more than 65 V (i.e. a factor about 3). TO further verify our experimental findings, we carried out failure analysis through emission microscopy (EMMI). EMMI analysis of both reference and PS-modified diodes clearly shows that in the reference diode avalanche breakdown starts around 25V in correspondence of the curved regions of the n+/p junction; conversely, no breakdown effects are evident in the same regions for the diode modified with nanostructured porous silicon, which actually occurs above 65 V in other regions of the diode where PS was not produced, thus corroborating our hypothesis the presence of PS reduce the charge carrier velocity, increasing, in turn, the breakdown voltage.