bluuebunny/crossref_metadata_2025 huggingface dataset:
Creating 3D specific systems: Architecture, Design and CAD
Authors: Franzon Paul D. , Davis W. Rhett , Thorolfsson Thor , Melamed Samson
Published: October 2015

3D stacking and integration can provide significant system advantages. Following a brief technology review, this abstract explores application drivers, design and CAD for 3D ICs. The main 3D exploitation explored in detail is that of logic on memory. This application is explored in a specific DSP example, showing a 25% power advantage when implemented in 3D compared with 2D. Finally critical areas that need better solutions are explored. These include cost management, design planning, test management, and thermal management.
Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration
Authors: Reed Jason D. , Lueck Matthew , Gregory Chris , Huffman Alan , Lannon John M. , Temple Dorota S.
Published: October 2015

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10μm and 15μm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99 % individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 22 consecutive bond pairs was made with the mechanical key, resulting in 98 % aggregate channel yield at 10μm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The results of thermal cycling and humidity-temperature testing on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made. Low temperature bonding (at 210°C, below the melting point of tin) is demonstrated to produce high electrical yield, high shear strength and similar intermetallic compound formation to devices bonded at 300°C. The low temperature process may prove useful for integrating IC devices that have low thermal budgets.
A Ceramic Clevis Sensor For Online Substance Concentration Measurement, Manufactured By Ceramic Injection Molding
Authors: Hartmann Matthias , Doerner Steffen , Hirsch Soeren
Published: October 2015

The current research presents recent respective to the work development of a ceramic clevis sensor for online substance concentration measurements. The aim was to develop a robust and acid-resistant sensor device, which can be easily included in existing procedural pipeline systems. To archive those goals a lot of factors had to be checked. For the substance concentration measurements a capacitive sensor effect was chosen. With this method even low substance concentrations down to one-tenth of a per cent can be indentified.

For the package material zirconium oxide (tetragonal zirconia polycrystal – TZP) was used. Zirconium oxide is a technical ceramic which is wear-resistant, acid-resistant, has a low thermal conductivity, is electrically isolating and can be uses in a ceramic injection molding (CIM) process. In the phase of the sensor design process multiple geometries for the sensor effect and integration space for the evaluation electronics had to be considered. A standardized DN 40 DIN 32676 flanged joint was also added for an unproblematic connection to the pipelines. All these needed geometries had to be integrated into one ceramic element. As a result of these requirements a 3D CAD model of the sensor element was designed. The CAD-file has shown that there was only the CIM technology left to comprehend developed sensor geometry. CIM is a low cost process for large-scale production which is distinguished by high size accuracy. In the CIM process the material shrinkage, this is caused by the needed debindering and sintering steps, had to be considered.

The developed ceramic clevis sensor was successfully tested in multiple fluidic systems. It has left the test phase and is now ready for maturity phase.
Packaging of a Fingerprint Based Access Control System
Authors: Delalic Zdenka J. , Josyula Sandeepsarma , Anand B
Published: October 2015

Verification for access control is faster and cheaper than identification based access control systems. The aim of this project was to develop a fingerprint based access control system, where the verification or validation of the entry is based upon the data from a RFID card. The multi-hop unit is controlled by a PIC 18F series, RISC processor. The capacitive sensor employed extracts 40 minutiae points, which are verified based on the pre-stored data in the RFID card. The capacitive sensor is capable of detecting human tissue, eliminating brute-force or latent print attacks. The low power RFID reader makes the unit portable. The use of RFID cards and verification mechanisms eliminate the use of a centralized database to store the data of every valid entry. The Infineon RFID card has an operating distance of 5mm, as opposed to 0.5mm normally used in swipe based RFID systems, making it easier to use. The packaged fabricated unit was successfully designed to program new RFID cards with minutiae data obtained from the capacitive sensor. Additional features of the unit include blacklisting entries and emergency exit.
EE Cars Architecture & Linked ECU: Constraints and New Needs
Authors: Kadiri El Khamis , Fitterer Eric , Manson Bertrand Delord
Published: October 2015

The embedded EE systems complexity is still growing. During this decade, it is even going to accelerate with the deployment of Hybrids and Electrical Vehicles. To control the physical EE architecture complexity and ECU cost, car manufacturers must extend the functional perimeter of ECU and decrease the ECU number. This paper illustrates the needs and constraints on EE systems, notably linked to the Hybrids and Electric Vehicle. It is likely to foresee technological breakthrough in term of assembly and packaging for embedded EE systems over a 5 to 10 years period.
Investigation on the failure criterion of reliability testing for Pb-free BGA packages
Authors: Xie Weidong , Lee Tae-Kyu , Liu Kuo-Chuan , Xue Jie
Published: October 2015

Daisy-chained test vehicles are commonly used in board level reliability testing. By continuously monitoring the in-situ daisy chain resistance change over time, a failure could be captured during cycling and eventually the failure data could be used to establish the solder joints failure distribution under different testing conditions. One of the most debatable matters is that when should one to determine a failure to occur. Per IPC 9701A [1] a failure is defined as 10 1000-ohm events in 1 micro-second duration for event detector or 20% increase over the baseline resistance for data logger. Other threshold values such as 100, 300, or 500 ohms are also commonly used by packaging reliability community. Such a wide range of failure threshold values may introduce significant delta in terms of cycle numbers for Pb-free solder joints if different criteria would be used as reported by Henshall, etc [2]. Therefore a systematic study of the impact of using such diversified resistance values on the final failure distribution is necessary and important such that no big difference among reliability results from different sources.

The purpose of this study is to investigate the impact of different failure thresholds on Pb-free solder joint failure distribution for most commonly used packages. The test vehicle, designed on an 8″×15″ double-sided printed circuit board (PCB) with multiple test sites, was populated on both sides with daisy-chained components. To reflect the real situation, the components were selected to include different package types (FCBGA, PBGA, CSP, QFN, etc), different pitches (0.4–1.0 mm), and different package size (6–50mm). The assembled test vehicles then went through 0C–100C thermal cycling, the cycle numbers corresponding to different resistance thresholds were recorded and compared. The test results showed that the failure threshold has significant impact on Pb-free solder joint failure distribution, thus it is important to unify the failure criterion such that the reliability results from different sources could be compared side by side. For some packages especially small wire-bond packages that have relatively low baseline resistance, the 20% failure criterion may be too sensitive to the resistivity changes caused not by solder joint failure but other events such as connection cable resistivity change over time or temperature.
Improved Design of a High Density 3D Multichip Module for Class I Medical Devices
Authors: Link Doug , Kollar Michael
Published: October 2015

Today's powerful DSP based hearing instruments demand both high density and low cost microelectronic packaging solutions. In turn, this demand drives innovation and substantial collaboration among design and manufacturing personnel and suppliers. Conventional design and process envelopes are challenged and new problems arise. Rapid failure analysis and root cause identification are essential in this global, fast-paced development arena. Here we introduce a novel high density multichip module designed for placement onto a flexible, folded hearing aid SMD assembly and discuss the challenges faced by the design team. Delamination, electrochemical migration, and thermal stress failure mechanisms identified during design verification testing are examined, along with the techniques and tools of failure analysis and problem solutions.
Enabling MSL-1 Capability for QFN and Other Design Leadframe Packages
Authors: Hart Dan , Ganjei John , Kapadia Nilesh
Published: October 2015

As the conversion of the electronics industry to lead free soldering materials continues some unexpected negative side effects of higher lead free reflow temperatures have occurred. Defects such as delamination or “popcorning” in surface mount components have increased significantly since lead free soldering has become mainstream. Popcorning is a defect that manifests itself as a fracture between the epoxy based encapsulant and the metal, usually copper alloy, leadframe components used to form a surface mount component. This fracture occurs when moisture in the package volatilizes during reflow processes and forces its way through the encapsulation material and leadframe interface.

Peak reflow temperatures for leaded solder typically run around 215° – 225° C but due to the higher melting point of lead free solders, they require peak reflow temperatures of 240° to 260° C range. This 30° increase in reflow temperatures can have a significant effect on the electronic devices and any resident moisture in the component

The keys to popcorning, or delamination, defect reduction is twofold. The first objective is to enhance the bond between the encapsulant and the copper leadframe materials to form a stronger bond that can resist the vapor pressures induced during reflow. The other objective is to provide a superior bond between the leadframe and encapsulant thus minimizing moisture ingress.

New chemical treatment processes have been developed that pre-treat the copper surfaces of the leadframe and significantly enhance the bond between the encapsulant material and the metal leadframe. The chemical treatment process results in micro-roughening of the copper surfaces and at the same time depositing a thermally robust film that enhances the chemical bond between the epoxy encapsulant material and the copper.

This paper examines the possible issues and the real life successes when comparing standard component manufacturing methods to those that incorporate the aforementioned chemical adhesion promotion process. Components are assembled using both processes and final performance is tested using MLS-1 conditioning protocols, acoustic microscopy analysis (SAM), and final yield improvement.
THERMAL MANAGEMENT SOLUTIONS FOR THE LED MARKET
Authors: Kintz K. Andrew , Paisner Sara N. , Thompson M. Shane
Published: October 2015

High-brightness light emitting diodes (LEDs) are challenged with thermal management issues due to increased power and reduced surface area. This has led to the need for new materials with higher thermal conductivity that can quickly remove the heat from the active layer. LORD Corporation has developed two new thermal management materials, a “no pump-out” thermal grease and a low modulus die attach adhesive, as solutions to the heat dissipation problems facing LED manufacturers. These innovative technologies will help engineers solve complex fundamental thermal management problems.

A new 4 W/mK silicone thermal grease has been developed with significant resistance to in-package bleed-out or pump-out eliminating the reliability problem most commonly encountered with traditional thermal greases. A new 10–20 W/mK thermal epoxy adhesive has also been developed creating a new class of flexible adhesives with high adhesion. This combination allows the new LORD die attach adhesive to not only effectively transfer heat out of the package, but also to dissipate the stress caused by thermal expansion and contraction during thermal cycling thereby affording improved package reliability.
Thermoplastic Optical Polymers with Lead-Free Solder Reflow Resistance for HB-LED Packaging and Assembly
Authors: Zhou Weijun , Yuan Quan , Li Chris , Hahn Stephen F. , Koppi Kurt A. , Hoek Berend
Published: October 2015

A new class of thermoplastic optical polymers made by substantially fully hydrogenating block copolymers of styrene and butadiene, known as cyclic block copolymers (CBCs), were recently discovered to exhibit lead-free solder reflow resistance with peak reflow temperature up to 260°C. This kind of behavior is uncommon for traditional thermoplastic polymers. The block copolymer design and the resulting nanostructured morphology lead to strong elastic and soft solid material characteristics for CBC, which may explain why CBCs can maintain good dimensional stability at high temperatures (i.e., above its glass transition temperature, Tg) for a short period of time such as in a solder reflow process. This hypothesis was examined by computational fluid dynamics modeling on a molded CBC lens of LUXEON K2 LED package configuration. When the CBC lens is subjected to a simulated solder reflow process, the change in physical dimension due to thermal expansion and gravity effects is predicted to be negligible. However, the residual stress in the molded lens may play a profound role on its dimensional stability. There exists a critical stress value below which no observable deformation is predicted for the CBC lens. With excellent optical transparency and good long term optical stability, low moisture absorption, and good injection moldability, CBCs is a promising class of materials for LED packaging that contributes to improved LED manufacturing economics.
Effects of crystallographic orientation of Sn on electromigration behavior
Authors: Lee Kiju , Kim Keun-Soo , Yamanaka Kimihiro , Tsukada Yutaka , Kuritani Soichi , Ueshima Minoru , Suganuma Katsuaki
Published: October 2015

Electromigration behavior of SAC flip-chip joints with respect to the crystallographic orientation of Sn grains was investigated. The test sample had direct contact of Sn-3.0wt% Ag-0.5wt% Cu on Cu-OSP (organic surface preservative) and the applied current density was 15 kA/cm2 at 160 °C. Without current stressing, no microstructural change depending on the crystallographic orientation of Sn was observed. With current stressing, however, the bumps showed the substantial microstructural changes with respect to the crystallographic orientation of Sn. When the orientation of the current flow was parallel to the c-axis, fast failure of the bumps occurred due to the massive dissolution of the Cu electrode on the cathode side caused by the fast diffusion of Cu atoms along the c-axis of Sn grains while only a slight microstructural change was observed when the c-axis of Sn grains was perpendicular to the electron flow.
High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill
Authors: Lee Sangil , Baldwin Daniel F.
Published: October 2015

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield.

In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively.

This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.
Fine Feature Solder Paste Printing For Solder Sphere and Solder Trace Manufacturing
Authors: Dallman Nicole , Gerstner Kaycie , Jean Kristi , Haring Fred , Ahmad Syed Sajid , Reinholz Aaron
Published: October 2015

Fine round and oblong features were printed using fine solder paste. Diameters and spacings were measured and data was analyzed to show solder feature printing capabilities. The printed features varied from 50 to 450 micron diameters with 50 to 150 micron spacings. Analysis of the solder features showed that printing of round features was possible at every size and spacing, with minimal bridging of the very small spaced features after reflow.
Thermosonic Gold to Gold Intermetallic Advantages for CSP Packaging
Authors: Couts Philip
Published: October 2015

Flip chip thermosonic back end assembly method is a low cost clean gold to gold interconnection method. The advancement of flip chip thermosonic process for CSP packaging of HBLED and CMOS image sensors is occurring due to the precision intermetallic clean interconnection properties and ability to provide a small form factor packaging to consumer products. This paper will investigate thermosonic metal to metal interconnection process for these high growth assembly markets.

Thermosonic bonding uses a micro weld interconnection die attach method at lower bonding temperature (150°C). The thermosonic metal to metal interconnection method is lead free and the process does not use flux or solder alloys. Thermosonic flip chip die attach process uses a robust individual die “scrubbing” process which reduces assembly steps and eliminates the mass reflow oven used commonly in C4 solder process.

The metal to metal interconnection method provides excellent thermal performance for HBLEDs which require the Tj peak temperature to be controlled to maximize device MTBF and overall color temperature performance. The uses of metal to metal interconnection method provide superior thermal performance when compared to solder alloys.

The metal to metal interconnection method provides high precision with low particle generation for high performance bonding of CMOS image die using a low-k dielectric wafer. The line spacing for the substrate is 50 μm / 50 μm. Stud bumping machines have a ball placement accuracy of +/− 2.5 μm. Thermosonic GGI die bonders have a mounting accuracy of +/−7 μm.

Thermosonic bonding has fast process bonding times of < 500 msec which is important productivity factor in cost sensitive cell phone camera and flash modules.
Reliability Studies in Advanced Halogen-free Organic Laminates for Ultra-fine Pitch 3D Packaging
Authors: Ramachandran Koushik , Liu Fuhan , Kumbhat Nitesh , Lee Baik-Woo , Sundaram Venky , Tummala Rao , Wilson Mark
Published: October 2015

High I/O density and green materials are the two major drivers of package substrates for flip-chip and 3D IC packaging. Future organic laminate substrates will require 5–25 μm lines and spaces and through-package-via (TPV) pitch of 50–100 μm. This ultra fine pitch requirement will lead to serious substrate failures due to electrochemical migration and conductive anodic filament (CAF). Therefore, there is a need to develop new halogen-free materials and investigate their reliability in ultra-fine pitch applications. This work focuses on four areas, 1) Advanced halogen-free materials, 2) Surface insulation resistance (SIR) in fine lines and spaces, 3) Conductive anodic filament (CAF) in fine-pitch TPVs, and 4) Flip-chip interconnection reliability. The substrate materials selected for this study include resin formulations that incorporate halogen-free flame retardants onto the polymer backbone. The SIR was studied on substrates with 50 μm spaced copper traces and CAF was studied with TPVs of 150 μm and 400 μm spacing. In both the tests, the halogen-free substrates were observed to show better electrochemical migration resistance in comparison to brominated FR-4. Flip-chip reliability was studied by subjecting the test substrates to Thermal Cycling Test (TCT), Unbiased-Highly Accelerated Stress Test (U-HAST) and High Temperature Storage (HTS) test. Scanning Acoustic Microscopy (C-SAM) analysis and electrical resistance measurements were performed after each of the reliability tests. The test substrates passed 200 hours of HTS, 96 hours of HAST and 2000 cycles in TCT respectively. The flip-chip reliability results indicate that these materials have the potential for replacing the conventional halogenated substrates for high density packaging applications.
Modeling and Optimization of Bond Wires as Transmission Lines and Integrated Antennas at RF/Microwave Frequencies
Authors: Ndip Ivan , Tschoban Christian , Schmitz Stefan , Ostmann Andreas , Schneider-Ramelow Martin , Guttowski Stephan , Reichl Herbert , Lang Klaus-Dieter
Published: October 2015

In this contribution, we present a systematic approach for optimizing the RF performance of bond wires. First of all, a comparative analysis between two of the most commonly used bond wire signal configurations, the two-conductor and coplanar configurations, is done. Our results reveal that although the partial self-inductance of the signal wires is the same in both configurations, the partial mutual inductance of the coplanar configuration is higher, resulting in a smaller loop inductance. Consequently, the return and insertion losses are smaller. By reducing the distance between the signal and return currents, we further reduced the loop inductance, and significantly optimized the coplanar configuration. For example, considering a 1 mm long bond wire with a diameter of 25 μm, we successfully kept the power lost through the coplanar configuration below 10% at 15 GHz, in comparison to the 70% power lost through the two-conductor configuration at the same frequency. However, more than 30% of the entire power is lost through the optimized coplanar configuration at 40 GHz. At such frequencies where bond wires are unsuitable to be used as transmission lines, we demonstrate that they are very efficient as antennas by designing a half-loop integrated bond wire antenna having a bandwidth of 3 GHz. For experimental verification, test samples were designed, fabricated and measured. An excellent correlation was obtained between simulation and measurement.
High Frequency Measurement Techniques for On-Chip Inductors
Authors: Kim Bruce C. , Han Dae-Hyun , Noh Seok-Ho
Published: October 2015

This paper presents high frequency measurement techniques of on-chip inductors in giga Hertz range for wireless communication products. The on-chip inductors were fabricated on high resistive substrate to reduce loss. We compared several different on-chip inductors for self-resonance frequency and quality factors. The collection of measurement data could be used for the guideline of designing practical spiral inductors for wireless applications.
Evaluation of PulseForge Tool for Processing Metallic Conductive Inks on Low Temperature Substrates Part II: Screen Inks
Authors: Farnsworth S. , Rawson I. , Schroder K. A. , Pope D.
Published: October 2015

At this event in 2009, the authors discussed the need for advanced tooling and materials for printed electronics device development and manufacturing. We went on to describe and evaluate a novel toolset called PulseForge® which is based on photonic curing and capable of drying and sintering metallic-based inks on low-temperature substrates in milliseconds. Example inks manufactured by NovaCentrix used in the initial evaluation were silver and copper-based inkjet inks, with nanoparticles as the functional material. These inks were only 100's of nm thick when printed and dried. As part of on-going work, the authors are now presenting the same toolset applied to thicker screen print inks of silver and copper. A PulseForge 3100 in 12-inch width configuration is used to process improved silver screen ink on PET, and a new copper-based screen ink on copy paper. The tools produce equal or improved results over oven processing. Additionally, we demonstrate the PulseForge tools can process material at speeds consistent with volume manufacturing.
Direct Printing/Micro-dispensing Solution for 3D Coating Applications
Authors: Chen Xudong , Church Kenneth
Published: October 2015

Material deposition utilizing a dispensing approach has been widely used in microelectronics for decades. The trend towards more compact and complicated electronic devices at a lower cost has challenged traditional manufacturing and packaging processes, including dispensing. Dispensed coatings for applications such as EMI/RFI shielding, encapsulating, heat transfer, enhanced structural support, and shock protection bring additional benefits. Unfortunately there are challenges due to the component's increased density, the interconnects in a limited foot print, and the three dimensional nature of the components. Technologies and tools are greatly needed to provide not only accuracy, repeatability, and flexibility, but also a wide range of material choices, dimensionality and the ability for in-line integration. The high speed micro-dispensing/direct printing technology of nScrypt provides such a solution with pico-liter level volume control, advanced computerized motion platform, high resolution vision system and the ability of printing on 3D conformal surfaces. The materials that can be processed include but not limited to: conductive, dielectric, adhesive, epoxy, rubberized polymer and encapsulate.
Fabrication of Tall Structures for Microelectronics Application Using Selective Electrodeposition Process
Authors: Scholz Bernd , Lim WeiYang , Sarwar Ferdous , Ahmad Syed Sajid , Reinholz Aaron
Published: October 2015

Fabrication of tall features using selective electrodeposition is well known process and has several applications in microelectronics packaging. The use of conventional exposure and development processes is limited by the aspect ratio and sizes of the features obtained. This paper describes a novel approach to fabricated tall structures featured in thick photoresist . Tin and copper tall structures were made by selective electrodeposition. Also presented are results from experiments performed to fabricate tall tin and copper pillars with nearly vertical walls on bare dices to form interconnect.
Enabling Robust Copper Fill of High Aspect Ratio Through Silicon Vias
Authors: Willey Mark , Srinivas Damo , Varadarajan Sesha , Porter David , Srinivasan Easwar , Hausmann Dennis , Henri Jon , Kang Hu , Trivedi Mayur , Mountsier Tom
Published: October 2015

Today's Through Silicon Via (TSV) processes are limited to aspect ratios of 10:1. High performance logic devices drive the need for aspect ratios approaching 20:1 in order to achieve the desired performance while simultaneously reducing costs. The reduced via area required on the wafer enables the designer to utilize less real estate on the die to reduce cost or to potentially add redundant vias to improve yield. However, current conventional processes and techniques are not capable of achieving robust fill on aspect ratios greater than 12:1. This presentation will highlight the technical challenges in achieving robust copper fill on super high aspect ratio TSV structures. Additionally, a compelling, economic solution pathway will be presented that integrates a low temperature conformal high quality dielectric isolation layer, a high step coverage Cu barrier / seed technology and a void free high speed electroplating process with a wide process window that could accelerate the adoption of the high aspect ratio TSV design schemes.
HIGHLY IONIZED SPUTTERING FOR TSV-LINING
Authors: Elghazzali Mohamed , Weichart Jürgen
Published: October 2015

The barrier and seed layers for electroplating of copper play a critical role in the realization of through silicon vias (TSV) in 3D IC packaging. Physical vapour deposition (PVD) is still the preferred method for depositing these films, but must meet the technical challenges presented by the need to line high aspect ratio vias of 10:1 or more that often have rough sidewalls, and the market demand of low cost. A bilayer of TaNx/ α-Ta is the preferred diffusion barrier for copper metallization in CMOS multilevel damascene structures, providing a good adhesion and wetting layer for the PVD copper seed layer. A new method called Highly Ionized Sputtering (HIS) has been developed using power pulses of 50 to 200μsec length with a low duty cycle but very high peak current of several hundred amps. The high pulse current generates a very high ionization fraction of the sputtered material giving – with an appropriate bias voltage applied to the wafer – a high directionality of metal ions and providing very dense films as needed for the diffusion barrier. HIS uses regular sputtering equipment, planar targets and works at low target-to-substrate distances thus providing excellent transfer factors of the ionized PVD material, resulting in high target utilization and a low cost of ownership. HIS hardware and processes with competitive deposition rates, good uniformities and low stress have been developed on the Oerlikon 200mm and 300mm PVD cluster tools for TaNx, Ta, Ti and Cu. The applicability has been verified experimentally in TSVs with different sidewall qualities and supported by simulations.
Molded Underfill (MUF) Technology Development for SiP Module with Fine Flip Chip
Authors: Yoo Do-Jae , Kim Ki-Chan , Kwak Young-Hoon , Jang Min-Seok , Ha Job , Doh Jae-Cheon , Lee Chang-Bae , Kweon Young-Do
Published: October 2015

In this study, we developed the Molded Underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on the void free methodology to minimize void between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding Compound (EMC) selection approach, air vent design of cavity vacuum molding, and void formation mechanism by mold flow simulation and DOE(Design of Experiment) of several SIP module layouts.

The test vehicle used for this study of MUF by vacuum transfer molding shown as SiP module (8.2×7.7×1.13mm) which was sawn from 52.70×68.70×0.75mm mold area of 118.5*75.5*0.38 substrate. One segment mold inside (52.70× 68.70×0.75mm) had 35ea SiP modules (7X5 unit array). In addition, one SiP module included one Flip chip RF/BB IC(6.51×5.81×0.41mm) which had 339ea bumps and 95um Bump height, one Flip chip RF switch (0.705×0.705× 0.33mm) which had 4 bumps and 85um bump height, 1.6×0.8×0.6mm size of LC filter, and total 25ea passives.

In the end, SAT result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.
Electromigration Performance of Pb-Free μPILR™ Flip-Chip Packages
Authors: Katkar Rajesh , Mirkarimi Laura
Published: October 2015

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages. Electromigration performance of μPILR interconnects has shown a significant improvement and noticeably delayed electromigration induced failures. Voids initially begin to appear at Cu6Sn5 and solder interface on the die side, with eventual open failure due to excessive void formation along with a severe depletion of Cu Under Bump Metallization (UBM). No failure was observed on the substrate side of the interconnect regardless of the current direction. The enhanced performance of the μPILR interconnect along with other reliability benefits makes it an excellent alternative to conventional solder joints including thin film stack UBMs, thicker copper UBM as well as copper pillar on die.
Effect of Dielectric Selection on Sintering Behavior of LTCC
Authors: Krueger Daniel S. , Agee Laura , Fadner Cristie , Duncan J. Brent , Peterson Ken , Hilmas Greg , Zhang Shi C. , Huebner Wayne
Published: October 2015

Low Temperature Cofired Ceramic (LTCC) is a versatile ceramic packaging technology. LTCC's functionality and performance can be enhanced with the incorporation of passive devices such as resistors, capacitors, and inductors into the structure of the substrate. This incorporation, which eliminates surface mount solder joints is desirable for improving system reliability and allows for increased package density. Commercially available dielectrics for embedding capacitors into LTCC are limited and the incorporation of such systems into LTCC substrates poses processing challenges related to material compatibility. This paper will review multiple dielectric systems and techniques for embedding capacitors into LTCC as well as present new data related to the cofiring behavior of LTCC and custom dielectrics.
The Future of Maximum CAD/CAM Automation for Ceramic Hybrids
Authors: Sovinsky John
Published: October 2015

New concepts recently developed maximize CAD/CAM automation for all types of Ceramic Hybrids including Thick Film, Thin Film, LTCC and HTCC. Designs can now go quickly from concept to manufactured product, which will fuel more progress to bring a largely manual process to maximum automation, to include automatic masks, panels and generation of 3D analysis models. Maximum automation results in expanded use of technologies that are now shrinking. Technologies that have complex and difficult to understand design and manufacturing steps have a hard time gaining wide acceptance.

CDS is tackling this complex challenge and is designing and implementing the following processes to solve the most difficult CAD/CAM problems:Be a true CAM tool that reads in designs from any other EDA (layout) system. YRun all possible DRC checks necessary for high fabrication and assembly yield. YMake all manufacturing masks automatically from very basic designs by using settings in an automatically configurable table. YPanelize all types of Ceramic designs in preparation for manufacturing. YGenerate documentation automatically through from stored configuration files. DIn LTCC and HTCC, place cavity punches (nibbles and rubs) automatically and feed correct machine data to the punch machine. YExport resistor trimming data directly to the laser trimming machine. FFeed flying probe test data directly to the flying probe tester. DAutomatically make a 3D Image and export ACIS or STEP for thermal analysis. DExport data directly to all electrical analysis and thermal analysis tools. PSupport circuit fabrication on non-planar surfaces. FMake full 3D analysis models of circuits on non-planar surfaces.F

The purpose of this paper is to define what is required for the Ceramic Hybrid Microelectronics industry to realize full automation in design, checking and output to manufacturing. Your ideas are welcome.
Effects of Fe on the Kirkendall Void Formation of Sn-3.5Ag-xFe/Cu Solder Joints
Authors: Kim S. H. , Yu Jin
Published: October 2015

Ternary Sn-3.5Ag-xFe solders with varying amount of Fe; 0.1, 0.5, 1.0, and 2.0 wt. % were reacted with Cu UBM which was electroplated using SPS additive and characteristics of Kirkendall void formation at the solder joints were investigated. Results indicate that the propensity to form Kirkendall voids at the solder joint decreased with the Fe content. It showed that Fe dissolved in the Cu UBM and reduced the segregation of S atoms to the Cu3Sn/Cu interface, which suppressed the nucleation of Kirkendall voids at the interface.
Impact of isothermal aging on fine pitch BGA packages with Sn-Ag-Cu solder interconnects
Authors: Lee Tae-Kyu , Xie Weidong , Bieler Thomas R. , Liu Kuo-Chuan , Xue Jie
Published: October 2015

The interaction between isothermal aging and long-term reliability of fine pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects are investigated. In this study, 0.4mm fine pitch packages with 0.3mm diameter Sn-Ag-Cu solder balls are used. Two different die sizes and two different package substrate surface finishes are selected to compare the internal strain impact and alloy effect, especially the Ni effect during thermal cycling. To see the thermal impact on the thermal performance and long-term reliability, the samples are isothermally aged and thermal cycled from 0 to 100°C with a 10minute dwell time. Based on weibull plots for each aging condition, the lifetime of the package reduced approximately 44% with 150°C aging precondition. The microstructure evolution is observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and OSP surface finishes, focusing on the microstructure evolution near the package side interface. Different mechanisms after aging at various conditions are observed, and their impacts on the fatigue life of solder joints are discussed.
A Study on the Mechanism of Black Pad Formation during Electroless Nickel Immersion Gold process
Authors: Kim J. H. , Kim K. H. , Yu Jin
Published: October 2015

The “Black Pad” phenomenon referring to blackening of electrolessly plated nickel-phosphorous (Ni(P)) films after the immersion gold (IG) process was reproduced using pure chemicals for the first time. Chemical composition of the electrolyte most suitable for the black pad reproduction was proposed, and it was found that submicron scale nodular variation of the P content of the Ni(P) film induced potential differences large enough to drive galvanic corrosion when exposed to the electrolyte; gold cyanide solution in this case. Instead of conventional potential measurement techniques, corrosion couple experiments using Ni(P) films with different P content were performed to substantiate preferential corrosion, which occurred at the lower P side with the propensity of forming black pad getting more severe with the P content difference (ΔP) between films. Subsequent AFM analysis showed that variations of nodular shapes and curvatures among nodules led to submicron scale variations of the P content in the film, which could promote galvanic corrosion.
Nanoindentation Characterization of Lead-free Solders and Intermetallic Compounds under Thermal Aging
Authors: Jiang Tong , Song Fubin , Yang Chaoran , Lee S. W. Ricky
Published: October 2015

The enforcement of environmental legislation is pushing electronic products to take lead-free solder alloys as the substitute of traditional lead-tin solder alloys. Applications of such alloys require a better understanding of their mechanical behaviors. The mechanical properties of the lead-free solders and IMC layers are affected by the thermal aging. The lead-free solder joints on the pads subject to thermal aging test lead to IMC growth and cause corresponding reliability concerns. In this paper, the mechanical properties of the lead-free solders and IMCs were characterized by nanoindentation. Both the Sn-rich phase and Ag3Sn + β-Sn phase in the lead-free solder joint exhibit strain rate depended and aging soften effect. When lead-free solder joints were subject to thermal aging, Young's modulus of the (Cu, Ni)6Sn5 IMC and Cu6Sn5 IMC changed in very small range. While the hardness value decreased with the increasing of the thermal aging time.
Effects of Electromigration(EM) on the Kirkendall Void Formation in Sn-3.5Ag/Cu Solder Joints
Authors: Jung Yong , Yu Jin
Published: October 2015

Kirkendall voids and the micro voids induced by electromigration result in the serious failure in the solder interconnect. Interfacial reactions between Sn-3.5Ag solder and the electroplated Cu using SPS additive in the bath were investigated under high current condition. During subsequent isothermal aging at 150°C, the formation of Kirkendall voids was accelerated by S segregation at the void surface and Cu/Cu3Sn interface, and then the voids were preferentially localized at the interface. And under high current flow (1X104A/cm2) at the cathode side, electromigration caused the micro voids at the Cu6Sn5/Sn interface. The growth of Kirkendall voids and the micro voids were both affected by aging time and current density. Effects of current flow on the growth of Kirkendall voids and the micro voids were examined by applying high electric current during isothermal aging at 150°C. From the measurements of the fraction of voids at the Cu/Cu3Sn and Cu6Sn5/Sn interfaces on SEM micrographs and analysis of the kinetics of void growth, which voids are more dominant was examined according to the time and the current density. Furthermore, under current flow the intermetallic compounds (IMC) thickening as well as voids growth was affected by polarity. Even though Cu was consumed remarkably, the growth of both Cu3Sn and Cu6Sn5 IMCs was suppressed at the cathode side. On the other hands, the thickness of Cu6Sn5 at the anode side was increased by reaction with Cu flux atoms which migrate towards the anode from the cathode Cu line.
On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging
Authors: Huffman Alan , Garrou Philip
Published: October 2015

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..
The Role of Wafer Bonding in 3D Integration and Packaging
Authors: Hermanowski James , George Greg
Published: October 2015

There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail.
A Miniaturized Ground Surface Perturbation Lattice for Noise/Coupling Mitigation in Packaging Applications
Authors: Scogna Antonio Ciccomancini
Published: October 2015

The ground surface perturbation lattice (GSPL) is proposed to suppress parallel-plate noise in mixed signal systems. The design concept of the GSPL structure consists of circular pads and multiple vias in order to enhance the bandwidth of the mushroom like EBG structure. The present paper investigates the usability of a miniaturized GSPL for noise/coupling mitigation in packaging applications. A sensitivity analysis of the bandgap region with respect to the position of the vias, the radius of the patch and the dielectric permittivity is performed. It is proven how several parameters allow shifting the band gap region and designing the power bus according to the desired specifications. The signal integrity (SI) is also investigated by considering a line routed from top to bottom layer and comparing the GSPL structure with a standard PWR/GND layer. Because of the absence of etched PWR/GND layer, it is demonstrated how the GSPL represents a viable solution for the noise mitigation in mixed signal applications.
Successful Practices for the Modeling of Printed Circuit Boards and Substrates Using Electromagnetic Field Solvers
Authors: Pytel Steven G. , McMorrow Scott C. , Dagostino Tom , Polstyanko Sergey , Thiel Werner , Hall Richard
Published: October 2015

The aim of this work is to provide strategies for creating highly accurate models of printed circuit boards (PCBs) and substrates using electromagnetic field solvers. It will examine how to choose the correct field solver for a particular application from among full-wave, modal decomposition, finite element and boundary element methods. Tradeoffs between time and accuracy of the different solvers will be discussed. The focus is on model creation for use in time domain circuit simulators, but analysis of the frequency domain data will be used to correlate measurement to simulation. The problem of correlating simulation results with measurements is also discussed. A physical layer reference design (PLRD) board has been constructed, measured and simulated with the various field solvers. The results are analyzed to understand why differences occur between simulation and measured data. The impacts of these differences on system-level simulations of high-speed serial links are studied using a circuit simulator.
Debye Model Fitting for Time-Domain Modeling of Lossy Dielectrics
Authors: Engin A. Ege
Published: October 2015

In this paper, we will show a systematic procedure for fitting a Debye model to tabulated data of dielectric constant and loss tangent at discrete frequency points. Our approach is based on generation of a guaranteed passive RC macromodel, satisfying Kronig-Kramers relations for complex permittivity. We present for the first time an RC vector fitting method.