Fabrication of Top-Gate MoS2 FET with Transferred Al2O3 Gate Dielectric
Authors: Kawanago Takamasa , Oba Tomoaki , Oda Shunri 
Published: February 2020

This study describes the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) using transfer printing of an Al2O3 gate dielectric. Semiconducting MoS2 has been considerable attention for applications as channel materials of FETs because a two-dimensional (2D) crystal is free from dangling bonds at the surface [1]. On the other hand, atomic layer deposition (ALD) of high-k gate dielectric is incompatible with MoS2 since an ALD precursor cannot be chemisorbed onto the surface of MoS2 due to the absence of dangling bonds [2]. Furthermore, ALD disrupts the surface structure and induces the oxidation of the channel layer [2], leading to the degradation of FET characteristics or the failure of devices. This study addresses these issues by utilizing the transfer printing of a high-k gate dielectric on a MoS2 layer [2], [3]. Transfer printing can avoid the deposition of a high-k gate dielectric directly on a fragile MoS2 surface. An abrupt and sharp interface can be anticipated by implementing the transfer printing of high-k gate dielectric.

A key component for developing the transfer printing of the Al2O3 gate dielectric is to find out an appropriate sacrificial layer on the handling substrate. In this study, nickel (Ni) metal was adopted as the sacrificial layer for the transfer printing of the Al2O3 gate dielectric. It was revealed that the adhesion strength at Ni and thermally grown SiO2 interface is reduced by immersion in deionized water (DIW) [3]. The penetration of water into the interface results in the separation of Ni from the SiO2 surface. This Ni layer can be etched by using dilute nitric acid (HNO3). On the other hand, HNO3, which is an oxidizing agent, cannot etch an oxide gate dielectric.

A 50-nm-thick Ni layer was deposited on the SiO2 (400 nm)/Si substrate by thermal evaporation (Fig. 1 (a)). The Al2O3 gate dielectric was deposited on the Ni layer by ALD with trimethylaluminum (TMA) and a H2O oxidant at a substrate temperature of 300 oC. Polymethyl methacrylate (PMMA) was prepared on Al2O3 by spin-coating as a protective layer. Next, a thermal release tape was attached to the PMMA layer. Then, the entire substrate was immersed in DIW for 5 min to weaken the adhesion strength between Ni and SiO2. The laminated structure was peeled off from the SiO2 surface in DIW. After the etching of Ni layer with dilute HNO3 (60% HNO3 : H2O = 1 : 10), the Al2O3 gate dielectric was transferred on MoS2 flakes. The Al2O3 gate dielectric and PMMA bilayer can be released from the thermal release tape by baking on a hot plate. After the removal of PMMA by oxygen plasma ashing, Al (40 nm) for the gate and Au (40 nm)/Ti (10 nm) for the source/drain were fabricated by the lift-off process. Finally, forming gas annealing (FGA) was performed in ambient (H2 : N2 = 3% : 97%) at 300 oC for 30 min to improve the electrical contacts at source/drain.

The fabricated FET has small hysteresis, low leakage current, a subthreshold slope of 120 mV/dec, and a carrier mobility of 7.3 cm2/Vs (Fig. 1 (b)). The abrupt and sharp interface was demonstrated for transfer printing of the Al2O3 gate dielectric on the MoS2 channel layer. Process mismatches including temperature and chemical compatibility are avoidable by adopting the transfer printing method. The use of transferred high-k gate dielectrics is not restricted to MoS2 FETs. It is also applicable to various 2D layered materials. This study opens up the interesting direction for the research and development of 2D material-based functional devices.

Acknowledgments

The authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Young Scientists (B) (Grant No. 17K14662).

References

[1] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis, Nat. Nanotechnol. 6, 147 (2011).

[2] X. Duan, C. Wang, A. Pan, R. Yu, and X. Duan, Chem. Soc. Rev. 44, 8859 (2015).

[3] C. H. Lee, J. H. Kim, C. Zou, I. S. Cho, J. M. Weisse, W. Nemeth, Q. Wang, A. C. T. van Duin, T. S. Kim, and X. Zheng, Sci. Rep. 3, 2917 (2013).

Figure 1