bluuebunny/crossref_metadata_2025 huggingface dataset:
Impact of Grain Structure and Material Properties on Via Extrusion in 3D Interconnects
Authors: Jiang Tengfei , Wu Chenglin , Im Jay , Huang Rui , Ho Paul S.
Published: October 2015

In this article, the effects of Cu microstructure on the mechanical properties and extrusion of through-silicon vias (TSVs) were studied based on two types of TSVs with different microstructure. A direct correlation was found between the grain size and the mechanical properties of the vias. Both an analytical model and finite element analysis (FEA) were used to establish the relationship between the mechanical properties and via extrusion. The effect of via/Si interface on extrusion was also studied by FEA. The results suggest small and uniform grains in the Cu vias, as well as stronger interfaces between the via and Si led to smaller via extrusion, and are thus preferable for reduced via extrusion failure and improved TSV reliability.
Packaging Design and Assembly for Ultrahigh Energy Density Microbatteries
Authors: Bjune Caroline K. , Marinis Thomas F. , Chiang Yet-Ming
Published: October 2015

For commercially available lithium ion batteries, the package structures can account for as much as 70% of its volume. In a multiyear effort, we have developed designs, fabrications, and assembly processes for ultrahigh energy density microbatteries of 5 and 1 mm3. Over the course of the research, the packaging system evolved due to changes or limitation specific to the battery system itself. During the study, improvements in the construction of the housing for the cathodes were made. Anodized aluminum cans fabricated through our in-house micromachining facility replaced the electroformed gold cans used in earlier experiments. Throughout the iteration of the can design, a flange around its open end, which would be used for sealing, was present, and both designs were fabricated as arrays. The ability to fabricate the housings in an array format lends it to be implemented into a scalable production assembly process. Materials evaluated for the cover ranged from copper foil to the final design of metalized sapphire with a plated through via. One area which needed to be addressed was reducing the temperature of the assembly process due to a change in the cell materials. This resulted in developing a low-temperature hermetic sealing process. The seal between the cover and can was made using a novel composite ring of indium and epoxy. The indium provided the hermeticity needed for the battery chemistry and the epoxy provided mechanical robustness. Most of our experience was with sealing temperatures of 100°C, but the sealing temperature is only limited by the cure temperature of the epoxy. One experiment was conducted to look at the reliability of the seal. A dozen 1-mm3 cells were filled with lithium and sealed. They were aged in laboratory ambient environment and periodically weighed. There was no weight gain in any of the cells over the course of several months, but one cell that was opened at the end of the experiment rapidly gained weight as the lithium corroded. The microbattery cell developed in this program used a lithium cobalt oxide cathode in the form of a porous sintered compact. Its bottom surface was coated with a gold film so that it could be thermocompression bonded to a gold bump on the bottom of the can. Following bonding, the cathode assembly was spray coated with a polymer separator. The anode was a piece of lithium metal bonded to the battery cover. After the cover was sealed to the battery can, the cell was filled with electrolyte and charged. Then a plug was inserted in the via through the cover to seal the battery. Batteries assembled in this manner exhibited energy densities in excess of 200 Wh/L for the smaller volumetric package.
3D IC Technology: the Perfect Storm
Authors: Garrou Philip
Published: October 2015

IC technology, which has traditionally been dominated by dimensional scaling, is facing several technical and economic hurdles as it moves forward. Low K insulation has not been able to meet performance projections, copper traces are becoming more and more resistive, clock rates have been constrained due to thermal issues and multicore processors are demanding major increases in bandwidth and decreases in latency. Economic constraints will also begin limiting the number of IC companies able to develop leading-edge IC designs. Moving past 45 nm digital CMOS scaling will no longer guarantee lower cost and higher performance. All of these issues have crated a “perfect storm scenario” for the widespread adoption of 3D IC technology.
Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications
Authors: Vick Erik , Goodwin Scott , Temple Dorota
Published: October 2015

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.
Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging
Authors: Enquist Paul
Published: October 2015

3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.
Reliability Modeling to Enable Damage Assessments for Plated Through Holes
Authors: Sharon Gilad , Barker Donald
Published: October 2015

A modeling approach to assess the reliability characteristics of the copper used in printed circuit boards (PCBs) is presented. Plated Through Holes (PTHs) for electrical connections across PCBs are formed by drilling the PCB and electroplating the hole, often using a copper (Cu) finish. Although the mechanical strain on the Cu in the center of the PTH may be insignificant to disrupt circuit functioning in a single reflow soldering cycle, more substantial damage accrues over multiple reflow cycles. Loads applied after the reflow cycles are shown to contribute to subsequent mechanical disconnects.

Efforts to quantify the damage to the Cu are hindered by the difficulties of measuring direct strain or displacement inside a PTH and extrapolating the damage to the Cu in the first three reflow cycles.

The assessment of damage to the Cu is enabled by finite element analysis. The authors' finite element model is defined as a single load system based on PTHs with flanges on every side of the laminate board connected by a hollow cylinder, a configuration treated as symmetric from the center of the board. The critical area of focus is the inner ring of the PTH. Stress and strain measurements in the region of interest are obtained using numerical simulations. The two-dimensional axi-symmetric model is validated against a three-dimensional full model and several test cases.

Reliability assessments relying on undamaged circuits are shown to be less accurate than estimates incorporating Cu damage following three reflow cycles. An increased probability of intermittent connection for the PTH's remaining use is suggested. Accordingly, the authors propose that damage assessments of copper finishes be incorporated into models of PCB reliability.
Metal Coated Polymer Particles for Electronic Packaging
Authors: Halaciuga Ionel , Redford Keith , Goia Dan V.
Published: October 2015

Anisotropic conductive adhesives (ACA) are widely used as interconnect materials in the manufacturing of LCD screens. To be integrated in a broader range of interconnect applications several technical and economic issues still need to be addressed. One significant challenge is to encapsulate polymer particles with well controlled modal diameter and size distribution into continuous, compact, and uniform conductive metallic shells. This presentation describes a method to deposit layers of nickel with different thickness (30 – 120 nm) onto monosized polymer particles ranging in size from 1 to 10 micrometers. The novelty of the approach consists in a pre-treatment of the epoxy functionalized polymer particles with linear polymeric amines. We show that by increasing amine chain length the distribution of the palladium catalyst, and consequently the adhesion and distribution of nickel metal deposited, can be improved dramatically. The effect of several plating parameters is discussed and illustrated.
Global Technology Survey of Anisotropic Conductive Interconnect Technologies, Past Present and Future - An Industry Intellectual Property Approach
Authors: Amaya Edmar M. , Lang Gene A.
Published: October 2015

Anisotropic Conductive Technologies (ACT), and materials comprising films and epoxies, started as a solution to provide low-cost reliable interconnection for glass displays on small, cheap calculators. ACT is mature now and have encroached into other types of technologies, especially Flip Chip, LEDs, OELDS, MEMS, 3D packaging, Microwave/RF and Optics. In today's assembly lines, ACT have replaced gold bumps, solder balls, wire bonds, and created new, more cost efficient chip-on chip, chip-on-film, chip-on-board, and chip-on-ceramic applications. Companies around the globe have realized the advantages of this technology to control thermal management, failures, speed of production, and they have vigorously engaged in protection of their intellectual property. The author will present a survey of the technology from a patent, trade secret, and licensing approach. In his analyses of the findings, he will show how different companies around the globe are using ACT to solve their interconnection needs. The author will also present future types of ACT and its uses for military, aerospace, and other commercial applications.
Tape-Peel Testing as a Simple Method to Evaluate the Adhesion of Coated Layers on Metal Core PCB
Authors: Scholz Bernd , Pekmic Ismir , Ahmad Syed Sajid , Reinholz Aaron
Published: October 2015

Conventional printed circuit boards (PCBs) may be replaced by thinner metal-core boards for some applications, as well as for package substrates. Using thin, metal-core technology may provide advantages for radio frequency (RF) circuits and packages, and increase heat dissipation for high power applications.

The metal-core technology discussed in this paper has several layers including the metal core, electro-coated dielectric, sputtered metal layers, and electroplated copper. For PCB and substrate reliability, it is important to have sufficient adhesion between the dielectric layer and plated copper. Sputtered metal layers with cleaning pre-treatments are one of the methods to improve the interfacial adhesion.

This paper describes an efficient testing method for the adhesion of a thin sputtered metal layer to a dielectric substrate. In this method, adhesive tape was attached to the surface and peeled off at 90 degrees in a tensile tester. Due to the sub-micron thickness of the sputtered layers, conventional peel test methods could not be applied. Typical adhesion testing of upper layers like paint coatings use a lattice pattern. The new method provided a convenient, repeatable way to evaluate the adhesion of three different sputtered metals with fifteen different pretreatment combinations. The test results were used to choose the sputtered metal and were later confirmed by testing the copper plated assembly using the metal adhesion specification in the industry standard IPC-TM-650.

A review of other methods and the need to identify an easy to use method which can provide repeatable quantitative measurements.
A study of high Cu behavior on electrolytic Ni and electroless Ni pad finish
Authors: Lee Hyun-Kyu , Chu Yong-Chul , Chun Myung-Ho , Jeon Sang-Ho
Published: October 2015

It has been used various pad finish materials to enhance the reliability of solder joint and Electroless Ni Immersion Gold (the following : ENIG) pad has been used more than others.

This study is about reliability according to being used in commercial Electrolytic Ni pad and ENIG pad, and was observed behavior of various Cu contents.

After reflow, the inter-metallic compound (IMC) between solder and pad is composed of Cu6Sn5 (Ni substituted) by using EDS, and in case of ENIG, between IMC and Ni layer was observed the dark layer (Ni3P layer).

Additional, it could be controlled the thickness of dark layer according to Cu contents.

Investigated the different fracture mode between electrolytic Ni and ENIG pad after drop shock test, in case of soft Ni, accelerated stress propagated along the interface between 1st IMC and 2nd IMC, and in case of ENIG pad, accelerated stress propagated along the weaken surface such as dark layer.

The unstable interface exists through IMC, pad material and solder bulk by the lattice mismatch, so that the thermal and physical stress due to the continuous exterior impact is transferred to the IMC interface. Therefore, it is strongly requested to control solder morphology, IMC shape and thickness to improve the solder reliability.
Design, Fabrication, Electrical Characterization and Reliability of Nanomaterials Based Embedded Passives
Authors: Das Rabindra N. , Lauffer John M. , Rosser Steven G. , Poliks Mark D. , Markovich Voya R.
Published: October 2015

This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. Cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. In another design, we have used eight layer high density internal core and subsequent fine geometry n (1 to 3) buildup layers to form a n-8-n structure. The eight layer internal core has two resistance layers in the middle and 2 to 6 capacitance layer sequentially applied on the surface. The study also evaluates the resistor materials for embedded passives. Resistors are carbon based pastes and metal based alloys NiCrAlSi. Embedded resistor technology can use either thin film materials, that are applied on the copper foil, or screened carbon based resistor pastes that can achieve any resistor value at any level. For example, combination of 25 ohm per square material and 250 ohm per square material enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Similarly, printable resistors can be designed to cover the resistance in the range of 5 ohms to 1 Mohm. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded discrete capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1400 cycles DTC (Deep Thermal Cycle).
High Aspect Ratio Package Core Production with Electrolytic Deposited Copper
Authors: Kenny Stephen , Roelfs Bernd
Published: October 2015

A typical package core consists of copper clad dielectric which is drilled to produce the necessary through vias serving two functions either as electrical or as thermal conduits. The thermal vias are normally characterised by a low drill pitch and a localisation at the centre of the package core. The vias are plugged after metallisation with a resin material to give the core the required planar surface necessary to provide the basis for the subsequent build up layers. Use of electrolytic deposited copper has been introduced as a new method to fill such through vias, pure copper as a plugging material has obvious advantages due its higher thermal conductivity in comparison to any currently available plugging resins. Significant cost savings are also possible as a fully automated in line processing sequence is available for electrolytic copper deposition in comparison to the more labour intensive resin plugging methods. The package cores utilising this technology have however been restricted to a dielectric thickness in the range 60μm to 100μm and with through via diameter 75μm to 100μm due to limitations in the processing technology. With these dimensions a hole pitch of down to 250μm may be filled reliably and is currently in production, latest results from this technology are shown. Hole filling with higher aspect ratios and particularly with substrates thicker than 200μm has required improvements in processing to ensure uniform copper filling. This paper describes the optimised process for through hole filling and shows the results achieved with dielectric materials 200μm and up to 400μm thick. Current qualification results of substrate 400μm thick with through via 80μm diameter are shown together with the comparison of filling with via pitch variation between 1.0mm and 0.6mm
AuSi and AuSn Eutectic Die Attach Case Studies from Small (12 mil) to Large (453 mil) Die
Authors: Evans Daniel D. , Bok Zeger
Published: October 2015

High power transistor, laser, and LED devices require packaging to remove thermal energy from the die. Although some silver filled epoxies provide thermal conductivity approaching 60 W/mK, AuSi and AuSn solder have long proven superior thermal performance. Materials such as Si and GaAs on CuW and GaN on SiC will be discussed in three case studies for die sizes ranging from 12 × 21 × 4 mil thick to 453 × 274 × 12 mil thick, using AuSi or AuSn eutectic die attach processes. The cases provide an overview of material selection and methods for optimized utilization of eutectic solders. Bond quality metrics such as fillet, voiding, and shear will also be covered in this paper.
Impact of Mechanical Simulation Methodology on Electronic Package Reliability Assessment with Applications to 3D TSS Technology
Authors: Bao Zhongping , Burrell James
Published: October 2015

Mechanical reliability issues in electronic packages have drawn significant attention in semiconductor industry for decades and have increased product development cost significantly. Recent rapid growth of various portable electronic devices like smartphone and smartbook with increasing demand for more functionality in tighter space further challenges the limit of mechanical reliability. To reduce the product development cost and time-to-market, mechanical simulation has been extensively employed in semiconductor industry for the purpose of design optimization and reliability assessment. The importance of having the correct simulation methodology can't be overemphasized considering the extent of its utilization throughout the product development cycle. In this paper, we will discuss three fundamental mechanical modeling methodologies that are widely used for simulating flip-chip overmolded packages. These approaches are generally used to simulate package warpage at End-of-Line (EOL) as well as to assess package reliability from a stress point of view. The first approach we studied in this paper is to assume that the package is initially stress-free at a given uniform temperature, which is usually taken to be the peak temperature of the mold cure profile. However, this differs from the actual assembly process where package composition and cure profiles are different at each assembly processing step. The second approach simply accounts for that fact and assigns different stress-free temperature to each individual package component. For example, the die is assumed to be stress-free at the chip attach temperature and substrate is assumed to be stress-free instead at the substrate baking temperature. This approach captures more physics compared to the first approach. The last approach explores that idea further by simulating the actual assembly process, step by step, through element removal and addition techniques available in the software. Such study is also carried out for a flip-chip overmolded package with Through-Silicon-Stacking (TSS) technology. Both Die-to-Die-first (D2D) and Die-to-Substrate-first (D2S) processes are examined. Simulated warpage, as well as reliability assessment regarding different failure mechanisms using these three modeling methodologies are discussed in detail. The paper is prepared to the best knowledge of authors and those statements do not necessarily reflect opinions of Qualcomm Inc. Some data shared in this paper is normalized such that no commercial confidential information is published.
Filling and Planarizing Deep Trenches with Polymeric Material for Through-Silicon Via Technology
Authors: Trichur R.K. , Fowler M. , McCutcheon J.W. , Daily M.
Published: October 2015

A key driver for 3-D device integration has been through-silicon via (TSV) technology that enables through-chip communication between vertically integrated layers. The TSVs typically have an electrical isolation using a dielectric layer between the silicon and the interconnect metal (e.g., copper). Recently, polymers have been proposed for use as the dielectric isolation layer, and polymers have been shown to increase device reliability by reducing “copper pumping,' where copper pops out from the TSV holes during thermal cycling. Traditionally, spinor spray-coating techniques have been used to fill TSVs with polymer material. However, using those techniques to fill and planarize very deep trenches (∼ 400 μm) and high-aspect-ratio structures has many limitations and usually results in voids, nonplanar surfaces, and lack of polymer flow to the requisite depths. Here, we present a novel process and a tool to completely fill and planarize deep trenches with a polymeric material. We use a combination of a traditional spin-coating process together with a physical planarization and fill process using the contact planarization tool to evacuate the trenches or vias on the wafer and then force the polymeric material inside the features. Using this process, we successfully filled and planarized trenches and vias 180 μm deep with 50-μm wide patterns as well as 400-μm deep trenches with ∼ 400-μm wide patterns. Initial results show complete filling and planarization of the material in the trenches without any voids.
Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure
Authors: Ouyang Eric , Chae MyoungSu , Chow Seng Guan , Emigh Roger , Joshi Mukul , Martin Rob , Pendse Raj
Published: October 2015

In this paper, a novel flip chip interconnect structure called Bond-On-Lead (BOL) and its ability to reduce stress in the sensitive sub-surface ELK (Extra Low K) layers of the die is presented. BOL is a new low cost flip chip packaging solution which was developed by STATSChipPAC to dramatically reduce the cost of flip chip packaging. The BOL solution allows for efficient substrate routing by virtue of the use of narrow BOL pads and the removal of solder mask in the area of the BOL pads, which eliminates the limitations associated with solder mask opening sizes and positional tolerances. In addition to the compelling cost benefits, modeling results are confirmed with empirical reliability testing data to show that BOL is superior to the traditional Bond-on-Capture Pad (BOC) configuration from a mechanical stress and reliability perspective. The focus of this paper is on the theoretical analysis of the stress, strain, and warpage associated with the BOL configuration compared with the traditional BOC structure. For the package deformation, the global finite element method is used to simulate the package warpage. For the local bumping reliability, the focus is on the ELK layers which are the critical locations affecting the package's reliability. The local finite element simulation is conducted to compare the critical ELK layers stresses with BOL structure vs. with traditional BOC structure.
Drop Test Simulation for the Component-Level Reliability of Module Packages
Authors: Gu Yu , Jin Daniel
Published: October 2015

The component-level drop reliability of micro-electronic packages has been a concern. Proper modeling approaches can significantly reduce the time and costs and provide valued data support not only on the failure analysis but also on product development. Based on finite element methods, the presented study performed explicit dynamic drop modeling to simulate the actual drop tests using ANSYS and LS-DYNA. A generic over-molded LGA (land grid array) module was selected and 3D parametric models were utilized to carry out the study. As in the actual drop test, the standard JEDEC test board and JEDEC drop condition were applied. The over-molded modules together with the test board under 1500G gravity was simulated to identify the failure locations. The results were fairly correlated to the actual FA observation. Potential key factors such as solder pad size, pitch size, module size, and thickness were studied through the parametric modeling. The impact of board side defect, such as solder void, was also studied because it is common to have this kind of defect in assembly. Besides component-level drop reliability, we also studied the board-level drop reliability by investigating the LGA solder stress.
Investigation of Silver Migration Impacts on Microwave Systems Fabricated on LTCC Substrate Under High-Power RF Excitation and High Temperature and Humidity Conditions.
Authors: Nair Deepukumar M. , Nair K. M. , Souders Ken , Smith Michael , McCombs Mark , Parisi James , Mobley Tim , Thrasher Bradley
Published: October 2015

The demand for cost effective LTCC systems has led to increasing use of silver based thick film conductors for inner layers of RF modules. There exists some level of concern about the reliability of silver as a conducting material for electronic circuit packaging. This arises from the tendency of silver to migrate under the influence of electric fields when subjected to certain favorable environment conditions. However, previous research has shown that if silver is used in a properly designed LTCC system on inner layers, the LTCC dielectric forms a hermetic seal around the circuit pattern, which leads to a highly reliable circuit and a low cost solution. This paper describes the results of an investigation to characterize and quantify the impact of silver migration on real-life microwave systems fabricated with DuPont GreenTape™ 951 LTCC material system with silver metallization. A buried multilayer filter was chosen from an actual production design in a high-reliability application, and was tested at 15W of continuous RF power at 1.5 GHz under 85°C/85% temperature and relative humidity. The chosen test conditions were meant to simulate actual operating conditions encountered by the circuit in real-world, high reliability applications. The focus of this work is to collect useful operational information under environmental stresses encountered in typical applications. To this effect, unlike previously reported work [1 ], [2 ], [3 ] by proponents of silver, the work described in this paper is not forcing silver to migrate, but rather tries to evaluate the performance of an actual application circuit fabricated with silver under high-reliability test conditions and high power, high frequency RF excitation. Material characterization data as well as RF performance data – in terms of S parameters and power delivered – indicates no evidence of detrimental effects or performance impairments due to silver migration or other mechanisms.
Selected Applications and Processing for Low Temperature Cofired Ceramic
Authors: Peterson Ken A. , Krueger Daniel S. , Sandoval Charles E.
Published: October 2015

Low Temperature Cofired Ceramic technology has proven itself in microelectronics, microsystems (including microfluidic systems), sensors, radio frequency (RF) features, and various other non-electronic applications. We will discuss selected applications and the processing associated with those applications. We will then focus on our recent work in the area of electromagnetic isolation (EMI) shielding using full tape thickness features (FTTF) and sidewall metallization. The FTTF is very effective in applications with −150 dB isolation requirements, but presents obvious processing difficulties in full-scale fabrication. The FTTF forms a single continuous solid wall around the volume to be shielded by using sequential punching and feature-filling. Sidewall metallization provides another method for shielding. We discuss the material incompatibilities and manufacturing considerations that need to be addressed for such structures and show preliminary implementations.
New Mixed Metal Transition Via-Fill Conductors for Cost Effective DuPont GreenTape™ 951 & 9K7 LTCC Circuits
Authors: Nair K. M. , McCombs M.F. , Souders K.E. , Gordon S. E.
Published: October 2015

LTCC (Low Temperature Co-fired Ceramic) technology provides an option for circuit designers that combines the benefits of HTCC and thick film technologies and is the technology of choice for many complex automotive, consumer, and military applications. For demanding and high reliability applications, LTCC circuits containing gold conductors for all ground planes, signal traces, and via fills are common. With the rise in gold cost from $400/TO in 2005 to a recent peak of over $1,200/TO in 2009, OEMs and circuit designers are forced to seek lower cost alternatives to all gold LTCC structures. The use of all silver conductors raises questions of reliability, especially for the external silver layers, and wire-bonding to silver is not possible.

The traditional method employed to address cost and reliability has been the use of mixed metallurgies, rather than using gold throughout the LTCC module. Silver based conductors for signal and ground are used internally, with gold conductors for wire bonding, brazing, or soldering on the external surfaces. Today there are two primary options to achieve this type of structure: 1) Ni/Au plating the top silver surface; or 2) Use of precious metal based transition via fill compositions that interconnect the silver to the gold conductors.

Traditional LTCC transition via fills compositions have consisted of Pd/Ag or Pd/Pt/Ag mixtures. However, such systems may be disposed to certain phenomena at the surface interface(s) between dissimilar metals. For example, the Kirkendall Effect has been found in various alloy systems and can impact the bonding between different materials. In particular, it has been studied and is used to describe voids that are produced in the boundary region at a bonding interface especially during high temperature processes such as metallic powder sintering.

This paper introduces two new mixed metal via-fill conductors that are compatible with the DuPont GreenTape™ 951 and 9K7 LTCC systems. Reliability and refire stability are described in detail.
Advanced Thin Wafer Support Processes for Temporary Wafer Bonding
Authors: McCutcheon Jeremy , Bai Dongshun
Published: October 2015

The ZoneBOND™ process has been developed to allow temporary wafer bonding at acceptable temperatures (usually less than 200°C), survival through higher-temperature processes, and then demounting at room temperature. The technology utilizes standard silicon or glass carriers and current thermoplastic adhesives developed by Brewer Science, Inc. The separation process consists of three components: removal of the adhesive in the outer zone, lamination of the device side of the pair, and separation of the carrier wafer from the adhesive. Developments of these key areas are the focus of this paper.
Development on Silicon module with Cu-filled TSV and Integrated Passive Devices
Authors: Park Yun-Mook , Lee Jun-Kyu , Park Byung-Jin , Kim Byeung-Gee , Lee Jung-Won , Kang In-Soo
Published: October 2015

In recent years, market demands on more functionality, smaller form factor and higher speed is becoming strong increasingly. In order to come up with those, many new technologies are emerging in the market. Among them, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

In this work, we have developed the silicon module with Cu filled TSV and LPF [Low Pass Filter] in combination with Inductor and MIM Capacitor integrated at the surface of silicon interposer. And also have made very small form factor package with less than 0.8mm in thickness including 2 chips mounted side by side at the silicon interposer.

In order to make silicon module with Cu filled TSV, we have evaluated and optimized via etch, thin-film deposition and via filling process which characterized a high uniformity via etch, good step-coverage and void-free at 200um in depth and 65um in TSV diameter at wafer-level. Furthermore, the IL [Insertion loss] of 0.14dB and 0.11dB for 3rd order filter and 5th order filter at 2.4 GHz respectively was achieved through both front-end process capable of high uniformity insulator deposition and back-end process capable of forming thick Cu RDL [Redistribution]. A good matching between measured value and simulated one using 3D simulator was achieved.

We are currently running component reliability tests for Preconditioning, TC, HTS and 85%/85. So test results will be discussed and submitted at the full manuscript.
Capacitance Calculation for Offset Via Structures Using an Integral Approximation Approach Based on Finite Element Method
Authors: Wang Hanfeng , Zhang Yaojiang , Drewniak James L. , Fan Jun , Archambeault Bruce
Published: October 2015

A simple yet efficient approach is presented to extract the via-plane capacitances for an offset via structure. According to the integral approximation approach, the geometry of offset via is first divided into several segments with equally distributed angles from the origin. The two-dimensional FEM method for the concentric case is used for each segment based on its pad-stack parameters. Then, the final offset via-plane capacitance is approximated as the average of these ‘segmental’ capacitance values. Numerical examples demonstrated that the combined method has similar accuracy with a three-dimensional solver but it has much higher efficiency in both CPU time and memory cost.
Kinetic Heat Sink
Authors: Khanna Vijay , McVicker Gerard , Sri-Jayantha Sri M.
Published: October 2015

Conventional heat sinks for processors achieve improved heat transfer efficiency by impinging ambient air over stationary fins. Further improvement in the air film heat transfer coefficient through increased air speed becomes asymptotic and invariably results in undesirable acoustic noise. The Kinetic Heat Sink (KHS) is a novel concept that utilizes rotating metals fins to transfer heat to the ambient air. The configuration allows high-speed relative motion between surrounding air and fins with the potential of a high heat transfer coefficient at practical flow rates and rotational speeds. Improved efficiency of heat transfer is anticipated because of higher relative tangential velocities offered by the rotating fins and moving air compared to a conventional heat sink configuration. The need to move the fins relative to the stationary heat source, however, imposes a technical challenge. A highly conductive thin liquid film to couple the stationary heat source to the moving fins is required to demonstrate the merit of the KHS. The concept of the KHS has been evaluated in a number of prototypes that have been built and tested. The lessons learnt through a series of prototype KHS designs are summarized. The technical and performance challenges encountered during the feasibility testing of a KHS are then outlined.
The Microelectronic Wire Bond: Past, Present, and Future
Authors: Charles Harry K.
Published: October 2015

Since its very inception, the microelectronic wire bond has been the dominate form of first-level interconnection (chip to package or substrate). Wire bonds account for over 80% of first-level chip interconnections made by the microelectronic industry each year. Wire bonding is reliable, flexible, and low cost when compared to other forms of first-level interconnections. In this article a brief discussion of wire bonding is presented along with bond formation fundamentals. Aspects of wire bond reliability will be explored in conjunction with methods of wire bond testing. Particular attention is given to fine pitch bonding, bonding to stacked die, higher frequency bonding, ball bonding with copper wire, and advanced bond testing methods.
Improved Bond reliability through the use of Auxiliary Wires (Security Bumps and Stand-Off Stitch)
Authors: Rasmussen David J , Thompson Rodney
Published: October 2015

Whether the need is due to poorly bondable materials, non-flat bonding surfaces, odd packaging situations, or just the need for high reliability; the integrity of a wire bond interconnect can usually be greatly improved through the proper use of Auxiliary Wires. Auxiliary Wires are defined as Security Wires, Security Bumps, or Stand-Off Stitch (aka Stitch on Bump). The old stand-by Security Wire has been an asset for several decades, however, this is being replaced by Security Bumps which require a smaller second bond termination area. Further, Stand-Off Stitch (SOS) has many more applications and also has many side benefits that could be incorporated into a circuit design for better wire strength properties, fewer interconnects (die to die bonding), and lower loops. Stand-Off Stitch bonding involves the placement of a ball bump at one end of the wire interconnect, then placing a wire with another ball at the other end of the interconnect and stitching off the wire on the previous placed ball bump. This results in a near homogeneous stitch bond interconnect to the bump with an inherent improvement in stitch bond pull strength. Another use for SOS is Reverse Bonding (Stitch bond on bump on die bond pad) often resulting in a lower loop profile than standard forward wire loop and the loop is stronger because the wire hasn't been work annealed above the ball (in the Heat Affected Zone). A major impediment to the implementation of SOS is the retraining of visual inspectors and the approval of quality departments.
2 mils Au wire interchip wedge bond cratering study
Authors: ZhiJie Wang , Lim Tony , YingWei Jiang , ChangLiang Zhang , Choi Haengsun , Hwang Kwansun
Published: October 2015

Au wire thermosonic wedge bonding is applied for die to die interconnect on accelerometer device. With the fragile bond pad structure of MEMS device, bond pad cratering or bond pad metal peel is a fatal wedge bond defect during assembly packaging and reliability failure during field application. Typical interchip wedge bond failure mode and the cause of failures are studied through analyzing wedge bonding mechanism, packaging & tooling design and bond pad metallization. Comprehensive wedge bond process characterization was carried out to improve wedge bond quality and reliability. Critical wedge bond responses (wedge pull, wedge shear, Cratering) were studied during wedge bond process characterization. Post wedge bond cratering has good correlation with the wedge tool in both position and shape. Si nodule underneath the bond pad metal generates higher local stress to the bond pad during wedge bonding. Thinner bond pad metal could not act as a cushion to mitigate the wedge bond stress to the poly silicon layer beneath the bond pad. The initial post wedge bond cratering / bond pad damage will get deteriorated during following assembly reflow process as well as SMT process, eventually the weakest interface layer beneath the bond pad will be separated, reflected as the bond pad metal peel. Approaches to enhance interchip wedge bond integrity were explored and significant improvements were seen.
Predicting Fusing Current for Encapsulated Wire Bonds under Transient Loads
Authors: Mallik Aditi , Stout Roger
Published: October 2015

For high power IC chips, as device size inevitably decreases, the wire diameter unfortunately must decrease due to the need of finer pitch wires. Fusing or melting of wirebonds thus increasingly becomes one of the potential failure issues for such IC's. Experiments were performed under transient loads on dummy packages having aluminum, gold, or copper wires of different dimensions. A finite element model was constructed that correlates very well with the observed maximum operating currents for such wirebonds under actual experimental test conditions. A qualitative observation of typical current profiles, as fusing conditions were approached, was that current would reach a maximum value very early in the pulse, and then fall gradually. One goal achieved through the modeling was to show that the current in the wire falls with time due to the heating of the wire material. Correspondingly, the wire reaches the melting temperature not at the peak current but rather at the end of pulse. Further, modeling shows that knowledge of external resistance and inductance of the experimental set up are highly significant in determining the details of a fusing event, but if known along with the temperature-dependent wire properties, the simulation can predict the correct voltage and current response of the part with 2% error. On the other hand, lack of external circuit characteristics may lead to completely incorrect results. For instance, the assumption that current is constant until the wire heats to fusing temperature, or that current and temperature both rise monotonically to maximum values until the wire fuses, are almost certain to be wrong. The work has been carried out for single pulse events as well as pulse trains.
Chip-last Embedded Actives and Passives in Ultra-Miniaturized Organic Packages with Chip-First Benefits
Authors: Kumbhat Nitesh , Liu Fuhan , Sundaram Venky , Sridharan Vivek , Choudhury Abhishek , Chan Hunter , Tummala Rao
Published: October 2015

Embedded actives and passives are being pursued by chip-first and wafer-level fan-out approaches to address high functionality and miniaturization. A next generation embedding alternative- “chip-last embedding”, which retains all the benefits of chip-first, has been demonstrated at Georgia Tech for complex multi-component heterogeneous systems. This paper presents detailed results from the first demonstration of this novel technology called Embedded MEMS, Actives and Passives (EMAP) with Chip-Last (CL) interconnections. This technology is targeted at highly integrated modules and systems with multiple 2D and 3D ICs for RF, Digital, Analog, MEMS and passive devices.

Ultra-thin (55μm) silicon test dies were embedded in a 60μm deep cavity within 6-metal layer substrates yielding a total module thickness of 0.22mm. The robustness of substrate materials and processes was demonstrated using thermal cycling of the blind-vias and through-holes. The embedded IC was bonded to the substrate at 160°C by ultra-fine pitch (30–50μm) and low-profile (10–15μm) Cu-to-Cu interconnections with polymer adhesives. Two different die-sizes 3mm × 3mm and 7mm × 7mm were investigated for reliability performance of these interconnections, which passed 1000 thermal cycles, in addition to Highly Accelerated Stress Test (HAST) and High Temperature Storage Test (HTS).

Comprehensive analysis of new materials and processes used in the chip-last embedding technology has been carried out demonstrating the advantages and robustness of this promising technology. Due to manufacturing process simplicity and unparalleled set of benefits, the chip-last technology provides the benefits of chip-first while enabling highly miniaturized, multi-band, high performance modules with embedded actives and passives.
Advanced 3D Packaging of Miniature Biomedical Sensors
Authors: Ha Dohyuk , Lin Tse-Yu , Kim Byung Guk , Irazoqui Pedro P. , Chappell William J.
Published: October 2015

In this paper, a novel 3D packaging technique for miniature implantable wireless biomedical sensors for intraocular pressure (IOP) sensing in mice is introduced. Due to the limited size of a mouse eye, the packaging of the sensor and control integrated circuit (IC) is very challenging. The overall size of the packaged sensor must be less than 12 mils cubed. In order to achieve the desired thickness, a magnetically aligned Z-axis anisotropic conductive adhesive (ACA) is used to create the vertical interconnects and micro-vias in the packaging material to distribute signals vertically to limit the eventual area of the device. The first step is to demonstrate the layer-to-layer interconnection between a silicon IC and a liquid crystal polymer (LCP) layer using the Z-axis ACA. The total thickness of the IC and the packaging layer is less than 6 mils. The measured resistance through vertical interconnection is 1.15 ohms on average for 3 mil × 3 mil pads. The second step is to demonstrate 3D transitions through 0.8 mil via holes in a LCP layer. A transition from an antenna layer through the LCP to a rectifier circuit on the above layer is demonstrated. RF power received by a loop antenna on the bottom LCP layer is rectified and generates 5 volts of DC voltage. This miniature 3D packaging technique enables extremely tight integration of all the sensor's components in a small form factor package, which can be implanted into mice eyes for wireless monitoring of the intraocular pressure.