bluuebunny/crossref_metadata_2025 huggingface dataset:
“Front-end-ization” of the Back-End
Authors: Roy Rajiv
Published: October 2015

The trend towards 3D stacking and advanced packaging has significantly altered the requirements for manufacturing tools in the back-end. Techniques and processes being adopted are beginning to resemble the front-end of 20 years ago but with updated and more affordable cost-of ownership capabilities. As an example, 0.5um defect inspection would have been considered a front-end requirement 20 years ago. Today TSV and advanced packaging techniques such as fine-pitch RDL are demanding 0.5u level inspection but at perhaps 10x improvement in wafer throughput and 20x improvement in COO. Other Front-end capabilities ranging from metrology to Advanced Process Control (APC) that are being adopted by the back-end will also be discussed.
RF Device Integration on Glass Interposer toward 3D-IPAC Packages
Authors: Sato Yoichiro , Chou Bruce , Sukumaran Vijay , Min Junki , Ono Motoshi , Karoui Choukri , Dosseul Franck , Nopper Christian , Swaminathan Madhavan , Sundaram Venky , Tummala Rao
Published: October 2015

3D Integrated Passive and Actives Component (IPAC) is a new concept of ultra-miniaturized and highly functional sub-systems, which enables one to achieve higher RF functionality in a single module. As the first step, this paper demonstrates the concept of integrating passive components using 100μm ultra-thin glass and small Through Package Vias (TPVs) by ArF excimer laser. Passive low pass filters (LPF) for WLAN in thin dielectrics on glass were designed using circuit simulator and EM solver. The LPFs were fabricated using low-cost panel based processes, and then assembled onto the Printed Wiring Board (PWB). The filters on either side of the glass interposer were measured at the board level, and the results corroborated well with EM simulations. The measurement results showed low insertion loss (about −1dB) and high rejection (<−20dB). The integration of passive components using double-side and ultra-thin glass interposers with small TPVs, enables one to shrink RF module size.
Effect of Voiding in Solder Joints on Thermal Performance of the LED
Authors: Pan Jianbiao
Published: October 2015

Light-Emitting Diode (LED) lighting has potential to fundamentally alter lighting by replacing incandescent and fluorescent technologies because it offers significant energy saving, longer operational life, and many other advantages. Excellent thermal management and low-cost is vital for LED lighting to become the market standard for general lighting. The packaged LED is typically soldered to the metal-core printed circuit board (MCPCB). However, as the size of the packaged LED increases, voiding in solder joints becomes a major problem since voiding increases the thermal resistance. The research questions are: what is the effect of flux in solder paste and the LED size on the voiding? What is the relationship between the voiding and the thermal performance of the LED? In this study, packaged LEDs with three different sizes were assembled to MCPCBs using solder paste with two different types of fluxes. The voiding in solder joints was imaged by an X-Ray machine. The detailed void characteristics were analyzed. The LED's junction temperature was measured based on the diode's forward voltage junction temperature measurement method. The results show that both flux in solder paste and the LED size have significant effect on the voiding. There is weak positive correlation between the voiding and the thermal performance when the voiding is over 25% coverage. However, the effect of voiding on the thermal performance is insignificance when the voiding is less than 25% coverage.
Fully 3D Printed 2.4 GHz Bluetooth/Wi-Fi Antenna
Authors: Deffenbaugh Paul , Church Kenneth , Goldfarb Josh , Chen Xudong
Published: October 2015

3D printing and printed electronics are combined to demonstrate the feasibility of printing electrically functional RF devices. A combined process is used to demonstrate the feasibility of fabricating a 2.4 GHz antenna in a fully-3D printed object. Both dielectric, which also serves as the structure, and conductors are printed. Full-wave models are generated using Ansoft HFSS. Real-world tests using a Class 1 “100 m” Bluetooth module are conducted and compared against the performance of an industry-standard quarter wavelength monopole antenna.
Advanced Devices and Electronic Packaging for Harsh Environment
Authors: Elshabini Aicha , Barlow Fred , Islam Sharmin , Wang Pin-Jen
Published: October 2015

The paper addresses the challenges in electronic packaging for extreme environment based on experimental work of the researchers and conducted reliability testing to evaluate high speed devices suitable for these applications, substrates, die attach, wire bonding, and encapsulation and housing. In particular, the researcher's work has focused on SiC power devices with low loss high voltage Schottky diodes with significant applications, high temperature JFETs and SiC MOSFETs (double trench), and GaN microwave devices. The paper provides recommendations for selection of devices, substrates, die attach, and encapsulation and housing for these applications.
High Temperature Sintered Interconnects Formed by Transient Liquid Phase Sintering
Authors: Greve Hannes , McCluskey F. Patrick
Published: October 2015

Low Temperature Transient Liquid Phase Sintering (LT-TLPS) enables the formation of joints robust to high temperatures at low process temperatures. TLPS systems consist of one or more low temperature constituents (i.e. Sn) and one or more high temperature constituents (i.e. Cu). The sinter joints are formed by intermetallic compound formation between these constituents. In this paper a paste based LT-TLPS approach is demonstrated. The organic binders and fluxes used to mix the pastes prevent the metal particles from oxidation and facilitate a vacuum-free process in air without the need of a reducing atmosphere. Pastes based on the Cu-Sn system have been developed enabling a completely pressure-less process. Furthermore sinter pastes for LT-TLPS at low pressure (<0.5MPa) applied during the initial stage of the sintering process have been developed which form almost void free joints. To assess the strength of the sintered joints a high-temperature shear fixture has been designed. Shear tests have been performed at 25°C, 400°C, and 600°C to characterize the influence of high temperature conditions on the joint performance. The shear strength of the joints formed without pressure has been assessed for different Cu-to-Sn ratios at all temperature levels. It is shown that the maximum application temperature and shear strength depends on the ratio of low melting temperature and high melting temperature constituents. The pastes introduced here can be used to form joints resilient to application temperatures of up to 600°C. They show the potential to form joints for reliable operation under extreme temperature conditions.
Modeling of Failure in Aluminum Alloy Braze for a High Temperature Thermoelectric Assembly
Authors: Arifeen S. , Potirniche G. , Elshabini A. , Barlow F.
Published: October 2015

The objective of this work is to design a commercially viable thermoelectric generator (TEG) assembly that can be used in passenger vehicles to be able to withstand extreme environmental conditions. Since the operating temperatures of the TEGs can reach temperature levels higher than 500 °C, aluminum braze alloys offer a good high temperature solution for die attach. However, the evolution of fatigue damage in the aluminum braze must be understood in order to ensure an acceptable reliability of the TEG.

In this paper, the proposed design of TEG package assembly was evaluated under extreme temperature conditions. Three-dimensional models of full scale TEG were analyzed using finite element analysis (FEA). The failures of aluminum alloy based braze (high temperature form of solder) material in the TEG application was investigated. Low cycle fatigue using direct cyclic approach was considered for the reliability analysis. Continuum damage mechanics approach was used to study the fatigue failure due to power cycling. Different TEG assembly designs were investigated and compared to determine the best possible solution for the extreme environment application.
Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package
Authors: Lyakas Michael , Reichman Corey , Jimarez Miguel , Ocampo Romina Mimi , Elberg Aaron , Hasan Altaf , Hale Dierdre , Hamilton Fred , Kim Joon Dong
Published: October 2015

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices.

Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling.

Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion.

In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements.

The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.
Thermo-mechanical Stress of Underfilled 3D IC Packaging
Authors: Wang Ming-Han , Wu Mei-Ling
Published: October 2015

In recent years, there has been a dramatic proliferation of research concerned with electronic products because of more various functions are integrate into the device and product's size has become smaller. As a result of these functional requirements, through silicon via (TSV) was investigated, this are getting considerable attentions not only from reducing the packaging size but also from shortening the interconnection's distance that can achieve the effect of enhancing signal transmission. TSVs are the vertical hole through the stacked IC, and they are also responsible for transferring signals between the ICs. Thus, they can improve the time delay of the signal transduction and allow better electrical performance than stacked ICs with wire bonding technology. However, a review of the literature indicates that electronic components will be affected easily by environmental factors such as humidity, pressure, and temperature. In general, the stacked ICs with TSV structure is easily affected by temperature changes than others factors since each material have different deformation. In very recently, the stacked IC packaging has been primarily concerned with thermo-mechanical loadings than traditional single IC packaging, which leads some problems such as via cracking, die cracking and interfacial delamination and so on. The above problems not only affect the performance of the device but also lead the device fail. Hence, most of the studies [1–9] are focus on discussing thermal mechanical loading with simulation method. Some of them discuss the relationship between the TSV shape and the stresses [4, 5]. In addition, most of people just build local TSV structure to do their research [4–9]. Although it can save more time but it also increase the error percentage with real situation. And this paper build the three dimensional four layers stacked IC packaging model from Hsieh [1]'s paper which can more close to real situation. And setting the structure to be simulated from the temperature 150°C to −50°C which is as retreat temperature.

This paper use ANSYS software which is based on finite element theory in order to reduce time used and save money, as finite element simulation can provide results more quickly and cheaply than experiments. Moreover, the research mainly analyzes the average value of maximum von Mises stress in TSVs and chips. Besides, this paper will sort out geometries and material properties which will serious affect von Mises stress value by design of experiments (DoE) analysis. Through the DoE analysis, the critical factors are selected as main design factors to reduce the von Mises stresses. This study can provide the significant information to effectively design the products and increase the reliability. This information can also eliminate the testing time.
Stitch Bond Process of Pd-Coated Cu Wire: Experimental and Numerical Studies of Process Parameters and Materials
Authors: Rezvani A. , Mayer M. , Qin I. , Brunner J. , Chylak Bob
Published: October 2015

Cost reduction is the main driver in the recent transition to Cu wire bonding from predominate Au wire bonding. Other cost reduction in packaging comes from new developments in substrates and lead frames, for example, Pre-Plated Frames (PPF) and uPPF for QFP and QFN reduce the plating and material cost. However, 2nd bonds (stitch bonds) can be more challenging on some of the new leadframe types due to the rough surface finish and thin plating thickness. Pd-coated Cu (PCC) wire has been recently introduced to improve the wire bonding process with bare Cu wire, mainly to improve reliability and enhance the stitch bond process. More fundamental studies are required to understand the influences of bonding parameters and bonding tools to improve stitch bondability. The stitch bond process of 0.7 mil diameter PCC wire on Au/Ni/Pd-plated quad flat-no lead (QFN) PPF substrate is investigated in this study. Two capillaries with the same geometry but different surface finishes are used to investigate the effect of capillary surface finish on the stitch bond process. The two capillary types are a polished finish type which is commonly used for Au wire bonding, and a granular finish capillary that has a much rougher surface finish. Process window between no stick on lead (NSOL) and short tail is compared. The effect of process parameters including bond force and table scrub amplitude is studied. The process window test results revealed that the granular capillary has larger process window and a lower chance of short tail occurrence. It has been shown that a higher scrub amplitude increases the chance of successful stitch bond formation. To further compare the capillary surface finishes, 3 sets of parameter settings with different bond force and scrub amplitude are tested. For all three parameter sets tested, the granular capillary showed better quality in bond strength. The granular capillary resulted in higher stitch pull strength compared to the polished type. A finite element model (FEM) of the process was developed to better understand the experimental observations. The amount of surface expansion (plastic deformation) of the wire at the wire and substrate interface was extracted from the model and attributed to the degree of adhesion (bonding). The model was used to confirm the experimental observation of adhesion (bonding) with different surface finish.
Cu Heavy Wirebonding for High Power Device Interconnection
Authors: Lee Baik-Woo , Kim Chang-Sik , Jeong Changmo , Byun Younghun , Yoon Jeong-Won , Kim Che-Heung , Booh Seong Woon , Chung U-in
Published: October 2015

To replace conventional Al heavy wire bonding in interconnecting power devices, we have explored the use of Cu heavy wire bonding, which offers superior electrical, mechanical, and thermal properties compared to Al wires that leads to better interconnection reliability. Chip pad metallizations that are strong enough to support Cu wires firmly against chip pads and endure high bonding parameters were first evaluated by 3D finite element modeling (FEM) of the Cu heavy wire bonding process. The FEM results indicated that an electroless plated Ni layer may be used as the primary candidate for the pad metallization of Cu heavy wire bonding because it enables the reinforcement of standard Al pads in power devices and allows for metallurgical interaction with Cu wires. Further, the deposition of the Ni layer entailed a simple protocol. The three major bonding parameters including force, ultrasonic energy, and time were optimized to achieve successful wire bonding of 300-μm-thick Cu wires to pads strengthened with Ni layers in power devices. Microstructures and compositions of the bonded interface were analyzed by transmission electron microscopy, which provided insight into the bonding characteristics between the Cu wires and the Ni pads. Reliability tests of the bonding were also carried out by the thermal shock test and pressure cooker test.
Thick Copper and Aluminum Wire Bonding Technology for High Power Laser Devices
Authors: Lee Kong Weng , Xu Lei , Skidmore Jay
Published: October 2015

The trends of increasing demand of higher power laser devices with increased current capacity and total package cost reduction to improve dollars per watt of laser output power have resulted in the need for alternatives to traditional gold wirebonds on gold-plated substrates. Copper and aluminum wires are considered to be the leading candidates due to their vast reliability database in the semiconductor industry and cost advantages. Room temperature (25°C) wirebonding with a robust process window and high yield is required for high-volume, low-cost applications. The wirebonds must also meet or exceed the stringent reliability requirements of 1000 hours at 85°C/85%RH damp heat (DH) and 1000 hrs at 175°C high temperature storage (HTS) testing. In this study, 10 mils round thick copper and aluminum wire bonding has been successfully developed at room temperature with no intermetallic failure or void formation at the Al/Au and Cu/Au interfaces after 1000 hours of DH and HTS testing. Further investigation with corrosion-resistant Al wire shows excellent pull strength and wire shear per Mil-Std 883 after 2000 hours of DH and HTS testing with no evidence of void formation at the Al/Au interface. The thickness of the Au-Al intermetallic is found to be minimal at ∼4um after 1000 hours of HTS testing. This study has demonstrated that both thick copper and aluminum wire are capable of wire bonding at room temperature to function as a reliable interconnect with improved product performance and low cost.
Embedded Photonics Interconnect Eco-system for Data Center Applications
Authors: Pitwon Richard , Wang Kai , Worrall Alex
Published: October 2015

The exponential increase in data center system bandwidth densities necessitates the migration of optical connectivity into the system enclosure. This is reflected by the emergence of a new technology eco-system including board-mountable optical engines and board-level optical interconnect. We consider how data center architectures are evolving and investigate the relative maturity and viability of various optical interconnect technologies. We also discuss current European research activities to develop disruptive optical interconnect solutions across all hierarchical levels of the data system from rack-to-rack, board-to-board, chip-to-chip and ultimately on-chip photonic interconnect. An early outcome of these activities has been the successful demonstration of an optically enabled data storage system.
A Wide I/O Memory-on-Logic Product Prototype Enabled by Through-Silicon Stacking Technology
Authors: Ramachandran Vidhya , Kim Dong Wook , Gu Sam , Lindley Ron , Henderson Brian , Ray Urmi , Radojcic Riko , Nowak Matt , Gunterus Aurel , Cassier Amer , Chen Sharon , Chen M. F. , Wu C. H. , Jeng S. P. , Yu C. H.
Published: October 2015

We report on a 28nm product prototype test vehicle assembled back-to-face with a 4Gb 3× nm Wide I/O DRAM chip using Through Si Stacking (TSS) technology. The high bandwidth interface of the digital chip to the wide I/O memory chip is enabled by ∼1200 μ-bump joints with pitch as small as 40μm allowing for wide memory bandwidth. With appropriate chip floor-planning, we demonstrate the mitigation of any impact to digital circuit performance and yield from TSS and the possibility to re-use 2D circuit IP in a 3D product with minimal die size growth. Our 3DIC assembly process allows for a compact form-factor package with <1mm thickness. As part of an integrated product solution, we include a test methodology with test stages distributed throughout the integration flow which allow for selection of known-good die to maximize assembly yield.
3D Integrated Packaging Approach for High Performance Processor-Memory Module
Authors: Polzer S. C. , Wilkins W. L. , Fasig J. L. , Degerstrom M. J. , Gilbert B. K. , Daniel E. S.
Published: October 2015

As high performance computing (HPC) system performance requirements increase, it is necessary to investigate new methods for integrating system components. Of interest is the applicability of 3D packaging approaches to HPC systems. Using thermal test chips, we designed and assembled a 3D processor-memory module with an integrated power delivery network to investigate interconnect density, integration, testability, and rework issues with 3D integrated packaging in an HPC environment. The design was based on interconnection and power delivery requirements for a processor-memory module capable of supporting 64 full-duplex 30G SerDes, routing for 800 processor-to-memory pins, an integrated multi-tiered power delivery network, and a thermal management solution capable of dissipating a nominal processor heat flux of 100 W/cm2. The technologies selected—semi-rigid flex, power connectors, land grid array (LGA) attach with an anisotropic film, and cold plate-based cooling—are all commercially available technologies, which we adapted for this HPC module. As more advanced 3D packaging and integrated circuits become available, these assemblies and components can be incorporated into our approach to increase integration and performance. This design approach also accommodates substitution of thermal test chips in place of functional components, allowing validation of thermal management solutions ahead of the final module design. We will present the electrical-to-mechanical design strategy used to build this module and results of the thermal and electrical analyses, and point to several areas where further development work would be beneficial in the areas of interconnect, power delivery, and mechanical design.
Next-Generation Lead-Free Solder Plating Products for High Speed Bumping, Capping and Micro-Capping Applications
Authors: Prange Jonathan , Woertink Julia , Qin Yi , Montesinos Pedro Lopez , Lee Inho , Lee Yil-Hak , Imanari Masaaki , Dong Jianwei , Calvert Jeffrey
Published: October 2015

Flip-chip interconnect and 3-D packaging applications must utilize reliable lead-free solder joints in order to produce highly efficient, advanced microelectronic devices. The solder alloy most commonly utilized for these applications is SnAg, which is typically deposited by electroplating due to lower cost and greater reliability as compared to other methods. The electroplating performance and robustness of SnAg products for bumping and capping applications is highly dependent on the organic additives used in the process. Here, next-generation SnAg products that improve the rate of solder electrodeposition without compromising key requirements such as tight Ag% control, uniform height distribution and smooth surface morphology will be discussed. These plated solders were then evaluated for compatibility with bumping, capping and micro-capping applications.
Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages
Authors: Whitmore Mark , Schake Jeff , Ashmore Clive
Published: October 2015

With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged.

For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components.

With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage.

In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.
Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration
Authors: Chien Chun-Hsien , Lee Ching-Kuan , Yu Hsun , Liu Chang-Chih , Chen Peng-Shu , Chien Heng-Chieh , Cheng Jen-Hau , Liao Li-Ling , Dai Ming-Ji , Lin Yu-Min , Zhan Chau-Jie , Ko Cheng-Ta , Lo Wei-Chung , Lu Yung Jean (Rachel)
Published: October 2015

Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed, and has been compared in complete processes and electrical/thermal characteristics with silicon interposer. In order to simulate and measure the electrical/thermal performance, patterned interposer wafer with 30μm diameter and 100μm depth Cu-filled TSVs are designed and prepared in advance. Key technologies include via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation were well developed and integrated to perform for comparison. 30μm via, 60μm pitch, RDL line/space 20μm/30um, 100μm thin wafer/glass and 15um micro-bumping been successfully integrated in the integration platform. The glass interposer was characterized and assessed to have excellent electrical performance and is potentially to be applied for 3D product applications.
Development of TGV Interposer for 3D IC
Authors: Takahashi Shintaro , Tatsukoshi Kentaro , Ono Motoshi , Mikayama Masaki , Imajo Nobuhiko
Published: October 2015

This study explores Through Glass Via (TGV) formation technology and metallization technology for glass interposer. 3D packaging has presently attracted lots of attention. The interposer is recognized as one of key materials, and its development of new fine pitch, high dense, and low cost interposer are accelerated. Glass is expected as one of candidates as material of future interposer substrate because of its good electrical properties and scalability of substrate size leading to higher loading efficiency. This study demonstrates TGV formation showed capabilities of fine pitch and high dense, and TGV formation for standard thick glass aiming varied applications for packaging such as MEMS, Optical device, and RF devise. This study also demonstrates metallization for above fine pitch TGV substrate. Necessary future development and subjects are pointed out.
Improvement of Back-Side Cosmetic Defects And Wafer Strength
Authors: Calero-DdelC Victoria L. , Popova Irene , Bicknell Aaron , Indyk Richard , Sullivan Joe , Fitzsimmons John
Published: October 2015

The continued challenge to keep up with Moore's law with aggressive device scaling, and shrinking wiring dimensions established perpetual need for novel materials and dictates ever tighter semiconductor process fidelity. Despite large progress with reducing defect densities on the device side of Si wafers, considerably less attention is being paid to the wafer back-side. Back-side wafer defects have been shown to reduce yield by leading to die breakage during packaging processes. Scratches and voids formed on the back-side of the wafer during various manufacturing processes have been shown to create weak spots on the wafer, which can act as initiation points for die crack formation and propagation.

In this paper, we present the technical details of a back-side wet etch clean process which helps reducing back-side defect densities significantly. The process is set up on a single wafer wet etch tool at IBM's East Fishkill 300 mm wafer fabrication facility. The process removes the outer back-side layer of the silicon wafer which has become defective and damaged as a result of previous processing steps. This new defect removal process increases die strength, which is measured as wafer mechanical strength, and removes surface defects from the back-side of the wafer.

Our results show that removal of 15–30 microns from the wafer back-side reduces the amount of cosmetic defects on the back-side of the wafer by 90%, while increasing die strength by 60%. The effects of the back-side wet etch clean process on the wafer optical appearance and mechanical properties were characterized, and supporting data such as atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), defect inspection, thermal interface material adhesion test, and die strength is included. Results from package level modules indicate an increase in reliability compared to the uncleaned Si back-side. It can be concluded that wet Si removal process described in this paper is a viable method to reduce the back-side defect density with an associated increase in final module product yield.
A Low Loss Power Distribution Network Design in Low Temperature Co-fired Ceramic Technology
Authors: Glover Michael D. , Hamilton Michael C. , Decrossas Emmanuel , Porter Kaoru , Pfeiffenberger Alexander , Mantooth H. Alan
Published: October 2015

The development of power distribution networks in low temperature co-fired ceramic (LTCC) to deliver power to electronic chips with minimal power loss and/or voltage drop presents real challenges. In the last decade, the power consumption for some applications has increased considerably while the supply voltage has been reduced. A number of designs for low loss power distribution networks were investigated for implementation using low temperature co-fired ceramics (LTCC) technology. This paper discusses the fabrication of power distribution networks (PDNs) using LTCC technology that exhibit sub-milliohm resistance through the use of full tape thickness features and other structures. Experimental data is also presented to support the viability of the approaches presented. The results presented in this paper show that the finite DC conductivity of the silver conductor paste commonly used in LTCC fabrication presents a challenge when attempting to build PDNs with low losses at high current levels. By analyzing a number of scenarios, several approaches are proposed that reduce the DC resistance laterally as well as vertically in a multi-layered LTCC PDN. Experiments and simulations show that the use of various processing techniques to increase the thickness of metallic traces can significantly reduce the lateral DC resistance of the PDN structure. In addition, various via configurations were simulated and fabricated that demonstrate an improvement in the performance of structures that distribute power vertically. Experiments using LTCC to carry a 100 A current were conducted to confirm simulations.
High and Moderate-Level Vacuum Packaging of Vibratory MEMS
Authors: Prikhodko Igor P. , Simon Brenton R. , Sharma Gunjana , Zotov Sergei A. , Trusov Alexander A. , Shkel Andrei M.
Published: October 2015

We report vacuum packaging procedures for low-stress die attachment and versatile hermetic sealing of resonant MEMS. The developed in-house infrastructure allows for both high and moderate-level vacuum packaging addressing the requirements of various applications. Prototypes of 100 μm silicon-on-insulator Quadruple Mass Gyroscopes (QMGs) were packaged using the developed process with and without getters. Characterization of stand-alone packaged devices with no getters resulted in stable quality factors (Q-factors) of 1000 (corresponding to 0.5 Torr vacuum level), while devices sealed with activated getters demonstrated Q-factors of 1.2 million (below 0.1 mTorr level inside the package). Due to the high Q-factors achieved in this work, we project that the QMG used in this work can potentially reach the navigation-grade performance, potentially bridging the gap between the inertial silicon MEMS and the state-of-the-art fused quartz hemispherical resonator gyroscopes.
Active and passive component embedding into low-cost plastic substrates aimed at smart system applications
Authors: Cauwe Maarten , Vandecasteele Bjorn , De Baets Johan , van den Brand Jeroen , Kusters Roel , Sridhar Ashok
Published: October 2015

The technology development for a low-cost, roll-to-roll compatible chip embedding process is described in this paper. Target applications are intelligent labels and disposable sensor patches. Two generations of the technology are depicted. In the first version of the embedding technology, the chips are embedded in an adhesive layer between a copper foil and a PET film. While this results in a very thin (< 200 μm) and flexible system, the single-layer routing and the incompatibility with passive components restricts the application of this first generation. The double-sided circuitry embedding technology is an extension of the single-sided, foil-based chip embedding, where the PET film is replaced by a second metal foil. To obtain sufficient mechanical strength and to further reduce cost, the adhesive film is replaced by a substrate material which is compatible with the chip embedding concept. Both versions of the foil-based embedding technology are very versatile, as they are compatible with a broad range of polymer materials, for which the specifications can be tuned to the final application.
Novel Backside Grinding and Laser Dicing Process for Cu Pillar Generated Low-k Wafer
Authors: Tamadate Yuka , Maruyama Hideki , Aoki Katsunori , Ozawa Takashi , Sorimachi Haruo
Published: October 2015

One of the challenges in using very thin die, which is needed in thin package, is how to dice it cleanly without chipping, delamination of fragile low-k insulation material and contamination of bonding pads. A narrow scribe line is also highly preferable for high wafer area utilization. The authors developed a novel "grooving and stealth laser process" to satisfy all of these criteria. Grooves are formed on test pads in die sawing area by a grooving laser beam, and then a stealth laser beam is focused into the bulk silicon, causing defect regions in the bulk silicon. Dicing tape is expanded so that the wafer breaks into separated dice.
Electromigration in Lead – Free Solder: A Power IC Perspective
Authors: Wassick Thomas A.
Published: October 2015

Over the past few years, lead - free solder interconnects have been significantly incorporated into electronic products, and are increasingly found in high performance computing systems and in their associated power electronics. As power and current levels increase within these products, the overall reliability of a lead-free solder based system can be impacted by an increasing risk of finding electromigration (EM) degradation during the product lifetime, especially if the product is operating at higher temperatures and with very high current densities. This paper provides a high-level technical overview of lead-free electromigration and describes the key factors and issues that can influence the EM performance of lead-free interconnects, especially in the environments in which power electronics are typically found.
Improving System Performance with eGaN® FETs in DC-DC Applications
Authors: Reusch David , Strydom Johan , Lidow Alex
Published: October 2015

The intermediate bus architecture (IBA) is currently the most popular power system architecture in computing and telecommunications equipment. It typically consists of a +48 V system power distribution bus that feeds on-board isolated converters, which in turn supply power to a 12 V power bus. From the 12 V power bus, the final power is delivered to the end loads by regulated non-isolated point of load (POL) converters. In this paper we demonstrate substantial system gains using enhancement mode gallium nitride power transistors in high frequency isolated and non-isolated DC-DC converters. These transistors, also known as eGaN® FETs, have been commercially available for over three years and are making significant inroads replacing the aging silicon power MOSFET.
Photopatternable Laminate BCB Dielectric
Authors: O'Connor Corey , Barr Robert , Calvert Jeff , Choubey Anupam , Gallagher Mike , Iagodkine Elissei , Oh Joon-Seok , Politis Andrew , Wang Kevin
Published: October 2015

Divinylsiloxane-bis-benzocyclobutene (DVS-bis-BCB, or BCB) is a well-known dielectric material that has been used in high volume manufacturing for many years (Dow's CYCLOTENE™ 3000/4000-series Advanced Electronic Resins). Typically, the application of these products has been by spincoating or spray coating of the dielectric material from a solvent-based formulation. However, for certain applications - for example, those involving large area, square substrates such as glass panels - it is desirable to be able to apply the BCB-based dielectric material using a dry film coating process, such as vacuum or hot roll lamination. In this paper, we describe the concept of creating a laminate film utilizing DVS-bis-BCB as the primary dielectric material component. In creating the laminate dielectric material, it is important to maintain the unique combination of thermal and electrical properties of DVS-bis-BCB, including high thermal stability, excellent copper barrier properties, low moisture uptake, low dielectric constant, and low dielectric loss. However, DVS-bis-BCB alone is too rigid to produce a high quality laminate film, therefore, it is necessary to modify the formulation to improve flexibility and lamination quality. As the flexibility of the film is increased, higher fracture toughness (K1C) and higher elongation values should result. Novel formulation adjustments to the base DVS-bis-BCB polymer system have resulted in an experimental laminate dielectric product that will be the focus of this discussion.

Depending on the application, laminate films can vary in thickness from 2μm to 50μm or even thicker. A typical laminate film construct includes the BCB-based dielectric film with a base sheet of an optically-clear polyester (PET) film and a polyethylene (PE) cover sheet. The DVS-bis-BCB-based laminate can be tuned with appropriate additives to either pattern with UV exposure from a tool such as a Süss MicroTec Mask Aligner (50mJ/cm2 – 100mJ/cm2 exposure energy) or laser pattern with a tool such as a Süss MicroTec 248nm Excimer Laser. Aspect ratios of 1:1.5 have been achieved with a photopatternable DVS-bis-BCB film and aspect ratios of >1:1 are possible with a laser-patterned film. Beside the photopackage added to the film to enable UV patterning, toughening additives have also been incorporated to enhance the fracture toughness (K1C) and elongation properties. K1C for the laminate has been improved to 0.55Mpa·m1/2 vs. 0.35Mpa·m1/2 for DVS-bis-BCB. Elongation has been improved to 13% for the laminate vs. 8% for DVS-bis-BCB. Electrical properties are similar to DVS-bis-BCB. An additional attribute of the laminate dielectric is the ability to tent over and protect vias. Vias >100μm diameter have successfully been tented with a 10μm thick film. A DVS-bis-BCB-based laminate has been demonstrated with continued optimization and evaluation to follow.
Custom Thickness Bare Die Availability of Any Product Through Device Extraction, Thinning, and UBM Pad Re-Conditioning
Authors: Spory Erick M.
Published: October 2015

OEM bare die availability, when possible, presents business challenges with respect to lead-times, minimum order quantities, and required thicknesses for the target applications. Until recently, there has been no capability available to provide an economical, low or high volume manufacturable process for the production of bare die from packaged devices. Specifically, the die can be harvested from any package, the original bonds removed completely, the pads reconditioned with a UBM (Under Bump Metal) electroless process, and the die delivered in a condition which allows it to be used identically to an OEM bare die. The die can also be custom thinned up to 75 um if required by the application, while maintaining the same functionality and reliability compared to a die which has been diced from a wafer. The proposed process is extremely valuable for any organization requiring quick turn, low-volume quantities of bare die for prototyping or higher volumes for production manufacturing. The bare die can be custom thinned for any subsequent packaging assembly requirement. Thinning allows for die stacking and low-profile conventional packaging or CSP (chip-scale packaging) alternatives. End-customer assembly applications for harvested bare die range from prototyping, obsolescence solutions, high-temp ceramic assembly, and/or MCM's (multi-chip modules).
Impact of Grain Structure and Material Properties on Via Extrusion in 3-D Interconnects
Authors: Jiang Tengfei , Wu Chenglin , Im Jay , Huang Rui , Ho Paul S.
Published: October 2015

In this paper, the effects of Cu microstructure on the mechanical properties and extrusion of though-silicon vias (TSVs) were studied based on two types of TSVs with different microstructure. A direct correlation was found between the grain size and the mechanical properties of the vias. Both an analytical model and FEA were used to establish the relationship between the mechanical properties and via extrusion. The effect of via/Si interface on extrusion was also studied by FEA. The results suggest small and uniform grains in the Cu vias, as well as stronger interfaces between the via and Si led to smaller via extrusion, and are thus preferable for reduced via extrusion failure and improved TSV reliability.
Vibration Testing as a Tool to Optimize the Configuration of the PCBs
Authors: Szendiuch I. , Psota B. , Otáhal A. , Klapka M.
Published: October 2015

This paper is linked to the EU project Euripides Eureka BOB (Board on Board) which is a joint solution for companies from four European countries. Its goal is the development, design, implementation and validation of an innovative configuration of the PCBs in 2.5D arrangement, which is designed for applications with a high density of components, and must meet the requirements for reliability in harsh environment and the ability to repair. To minimize the effect of mechanical stress is one of the priorities of this new construction, where a high density of components occurs on both sides of the PCB configuration. Therefore, any new solution, especially in 2.5D configuration, designed for harsh environment, requires mechanical stress optimization, already in the board's design process. Shock and vibration tests are also essential steps to reliability and quality assurance. This paper suggests as a simple example of one possible way to achieve this goal using vibration testing, including vibration simulations in ANSYS, to optimize the layout during the PCB design process. The optimization process consists of a sequence of necessary steps that need to be performed. The main contribution of this work is to show the first approach in the simulation of vibrations, and demonstrate that this path can help you choose the best design and layout of PCB, so as to avoid later problems caused by mechanical influences. In summary, specific rules are provided for verification of mechanical reliability by vibration testing and the most important properties of PCBs are defined. This procedure is in general suitable for use primarily in the design of any PCB, where you can prevent possible complications due to the impact of mechanical stress on the reliability of newly developed products.
Impact of Reprocessing Technique on First Level Interconnects of Pb-Free to SnPb Reballed Area Array Flip Chip Devices
Authors: Arnold Joelle , Gulbrandsen Steph , Blattau Nathan
Published: October 2015

The risk of damage caused by reballing SnPb eutectic solder balls onto a commercial off-the-shelf (COTS) active flip chip with a ball grid array (BGA) of SAC305 was studied. The effects of reballing performed by five different reballers were examined and compared. The active flip chip device selected included manufacturer specified resistance between eight (8) differential port pairs. The path resistance between these pins following reballing, as compared to an unreballed device, was used to assess damage accumulation in the package. 2-dimensional x-ray microscopy, acoustic microscopy, and x-ray computer tomography were also used to characterize the effects of reballing. These studies indicated that no measureable damage was incurred by the reballing process, implying that reballed devices should function as well as non-reballed devices in the same application.
Consumable Anode Process for SnAg Electroplating
Authors: Bernt Marvin , McClure Adam
Published: October 2015

Near eutectic tin-silver (SnAg) is currently the alloy of choice for electroplated lead-free solder bumping and Cu pillar capping. While lead-tin (PbSn) is still used in some applications, there has been considerable momentum in moving away from the use of lead in semiconductor packaging. Both solders are normally electroplated as alloys with specific compositions to target a desired melting point. Since the deposition potentials of lead and tin are very close together, they plate with similar characteristics. This makes it possible for PbSn plating systems to use a consumable anode system where the anode composition matches the desired deposit composition. Metals are replenished into the bath in much the same ratio they are consumed. In a SnAg plating bath, the deposition potential of Ag is much more positive than Sn, so very low potential is required for Ag deposition. The plating rate of Ag is generally mass transfer limited. The plating rate of Sn is current controlled. While similar in concept to systems using consumable anodes for plating other metals, the SnAg alloy system presents some unique challenges. Because it is more noble, the Ag+ will deposit onto the Sn anode material by displacement reaction, and passivation will occur. Thus, the Sn anodes cannot come in contact with the Ag+ in the bath. Historically this problem is overcome by using an inert anode and metals replenishment by liquid concentrate. This paper outlines a method for plating SnAg using a consumable Sn anode, thereby reducing cost of ownership (CoO) and increasing bath stability compared to conventional SnAg wafer level packaging (WLP) plating.