Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application
Authors: Taniyama Keita , Takeda Yuki , Azuma Yuki , Zheng Ziye , Motohisa Junichi , Tomioka Katsuhiro 
Published: December 2024

INTRODUCTION

Conventional field-effect transistors (FETs) are expected to have new gate structures and channel materials to avoid serious issues caused by the miniaturization of FETs, such as enhanced leakage currents and short-channel effects. With this regard, III-V compound semiconductor nanowires (NWs) have attracted much attention as one of the alternative channel materials because of their fast carrier mobility and compatibility with the gate-all-around (GAA) structure. We have demonstrated vertical GAA (VGAA) field-effect transistors (FETs) using InGaAs NWs on Si [1]. For circuit applications, this demonstration must be expanded on silicon-on-insulator (SOI) platforms. Here, we demonstrated the selective growth of vertical InGaAs NWs on SOI (111) and InGaAs VGAA-FETs on SOI (111).

EXPERIMENTS

The InGaAs nanowires (NWs) were grown on n-type silicon-on-insulator (SOI) substrates by the selective-area epitaxy. The SOI layer had a thickness of 600 nm. First, a 15-nm-thick SiO2 film was formed on SOI (111) by thermal oxidation. Next, we formed circular mask openings using electron beam lithography, reactive ion etching (RIE), and wet etching. Then, after the formation of (111) B-polar surface [2], we grew InGaAs NWs by metal-organic vapor phase epitaxy (MOVPE). Trimethylgallium (TMGa), trimethylindium (TMIn), and arsine (AsH3) were used as precursor materials. In addition, silane (SiH4), diethylzinc (DEZn), and tetraethyltin (TESn) were used as n-type and p-type dopants.

Next, we fabricated VGAA-FETs. At first, we deposited a 10-nm-thick Hf0.8Al0.2O gate oxide film using atomic layer deposition (ALD). Next, we deposited a 200-nm-thick tungsten (W) film for the gate electrode by sputtering. Then, we covered the NWs with benzocyclobutene (BCB) by spin coating and etched the BCB, W, and Hf0.8Al0.2O, and top of the NWs, simultaneously. We repeated the BCB coating and the etching process to isolate the gate and drain electrodes. Then, we formed a drain electrode (Ti/Pd/Au) on top of the NWs, and a source electrode (Ni/Au) on the n-SOI surface by evaporation. Finally, to obtain an ohmic contact between the electrode and the NW, we annealed the devices at 420°C in N2.

RESULTS

The InGaAs NWs were vertically aligned on n-type SOI (111) substrates by the selective-area epitaxy, indicating (111) B-oriented surface was formed on SOI (111). The average diameter of the NW was 70 nm, and the average height was 2000 nm. The NWs had axial segments: Zn pulse-compensated intrinsic segment, Si-doped n-type segment, and Sn pulse-doped n-type segment. The segment heights were 800 nm, 240 nm, and 960 nm, respectively.

The VGAA-FETs using the InGaAs NWs on an SOI substrate exhibited moderate switching characteristics. The VGAA-FETs had a threshold voltage (VTH) of 1.0 V and a subthreshold slope (SS) of 178 mV/dec. The on-off current ratio was 104 and the on-state drain current (Ids) was 7.6×10-4 μA/μm at the drain-source voltage (VDS) of 0.5 V. The transconductance (gm) was 2.0×10-3 μS/μm and the gate leakage current was approximately 9.5×10-3 pA/μm at VDS of 0.5V.

The SS was slightly higher than the minimum SS at room temperature (60 mV/dec). This was caused by a high off-leakage current. The high off-leakage current originated from the quality of the oxide/NW interface and the gate-induced barrier lowering.

In the output characteristics, the linear region exhibited a nonlinear curve. This was because Schottky contact was formed between the Ni/Au and the Si interface due to the thin Ni layer. The output characteristics indicated that the off-state leakage current was also modulated by negative VGS. This was because the SOI layer was electrically floated due to the above incomplete Ohmic contact and may have been modulated by the gate voltage. In the conference, the details of the selective area growth method of vertical InGaAs NWs and the improvements in the VGAA-FETs properties will be discussed.

[1]. K. Tomioka et al., Nature 488 (2012) 189.

[2]. K. Tomioka et al., IEEE J. Selec. Top. Quant. Elec. 17 (2019) 1112.