Surface Protection for Semiconductor Direct Bonding
Authors: Knechtel Roy , Klingner Holger 
Published: February 2020

Semiconductor direct wafer bonding is a widely used process for fabricating 3-dimensional structures, especially engineered substrates such as SOI wafers or cavity wafers with and without insulating layers at the bonding interface. The investigations described here concern cavity SOI wafers without insulating layers, as used for discrete and integrated pressure sensors. Semiconductor direct bonding is the initial bonding by mechanical contacting of high-quality surfaces activated by wet chemical and/or plasma treatments, followed by thermal annealing at temperatures and times related to the chosen activation. This ultimately results in a very strong mechanical bond, which can survive all of the subsequent process steps, such as those needed to process MEMS pressure sensors. The requirement for the direct bonding is that the wafers to be bonded have a very high quality; this means very low roughness, low waviness and no surface residues or contamination. In this paper, the focus is on roughness in relation to the bonding process and process integration.

It is well known that prime wafers with vendor polishing as the finishing step have a very good mirror polished surface, and can be bonded very easily – therefore they are often used for basic wafer bonding investigations, such as the effectiveness of surface activation. On the other hand, fresh polishing as the final step before wafer bonding is often used to reconfigure the surface, to allow a very good wafer bonding. In practice, especially in industrial processes, the problem is that wafers need to be processed before bonding to generate the required functional structures (the reference pressure cavity in case of the pressure sensors and alignment marks on the wafer backside to retrieve the sealed cavities after bonding). On the other hand, fresh polishing directly before bonding is not possible, either due to availability or because it cannot be used for the already-structured wafers (either the structure on the wafers or the polishing pads would be damaged). Here, one option is to protect the bonding surfaces with a hard coating, such as by growing a thermal oxide on a silicon wafer. In the case of the pressure sensors, this layer can fulfil a double function – protecting the bonding surface and acting as a hard mask for the cavity etching. Hence, the flow of the cavity wafer can be summarized as follows: thermal oxidation, back side lithography of the alignment marks, plasma etching of oxide back side (hard mask structuring), resist removal, front-to-back side lithography, plasma etching of the cavity hard mask on the front side, resist removal, KOH etching of silicon in an etch bath (simultaneously etching of cavities on front side and alignment marks on wafer back side), hard mask stripping using oxide etching baths.

Due to availability, Buffered Oxide Etchant (BOE) has to be used for stripping the hard mask from the wafer, and it was found that this etchant can slightly attack the silicon surface, making it a little rougher, which makes the bonding more difficult. With respect to a safe process, the etching time has to be long enough to remove the oxide in all cases, (e.g. grown oxide thickness in upper spec range, BOE oxide etching range in lower spec range), to reduce all the oxide everywhere on the wafer, but it must be short enough to prevent the roughening of the surface. Therefore, the extra etching time the wafer is left in the bath after the oxide has been removed, which is needed to cover natural process variations, must be as short as possible. This was evaluated experimentally. As a measure of the surface roughness, the bonding process itself was used, in particular, the travelling speed (Figure1) of the bonding front across the wafer – since the higher this is, the better the surface and the safer the overall process. As result, it was found that reducing the over-etch time by about 50%, reduced the travelling speed of the direct wafer bonding front by 20%, which is very significant. From this, it can be concluded, that the bonding behaviour of the silicon is strongly influenced by the time the free silicon surface remains in the BOE – the longer this time, the rougher the silicon, and the more difficult the bonding. This is ultimately very important for the overall process integration and to achieve a safe bonding process for almost void-free engineered substrates such as cavity wafers (Figure 2).

Figure 1