bluuebunny/crossref_metadata_2025 huggingface dataset:
Coaxial Through-Strata-Via (TSV) Analysis and Modeling
Authors: Xu Zheng , Lu James Jian-Qiang
Published: October 2015

Through-strata-via (TSV) is well accepted as a critical component in 3D integration that would extend Moore's Law. Since its electromagnetic fields that carry the signal exist only between the inner conductor and outer shell, the coaxial TSV offers small coupling, reduced loss and high density to meet rigorous specifications. The published results also show that the signal integrity of coaxial TSVs is better than that of other TSV configurations, while lack of detailed analysis and modeling for TSV physical design guidelines. In comparison to other TSV configurations, there are some advantages in fabrication of tungsten-based coaxial TSVs, although the fabrication could be challenging and complex for copper-based coaxial TSVs. This paper examines the performance of various coaxial TSV physical designs using a 3D electromagnetic field solver and SPICE simulator. Based on the analysis in both frequency domain and time domain, we report a number of design notes (as listed below) to avoid undesired energy consumption and potential logic malfunction:* Compared with a signal-ground TSV pair, the proposed coaxial TSV reduces the signal loss by more than half (~53%).* The electrical performance of copper-based coaxial TSV is very close to that of tungsten-based one.* 3D bathtub curves suggest good timing characteristics of coaxial TSV at high data rates.* The impact of the thickness of the coaxial TSV outer ground shell is insignificant.* Keeping the outer ground shell radius (that determines the I/O density), an optimal value of the inner signal TSV conductor radius exists (i.e., neither big nor small is good).* A thick tubular dielectric medium (i.e., large spacing) between the inner and outer conductors favors the performance remarkably.* This tubular dielectric medium with a small dielectric constant and tangent loss can suppress the signal attenuation.* If the tubular dielectric material is silicon or poly-silicon, low doping is preferred.* The desired thickness of the isolation liner, which isolates the metals, depends on the material properties of the tubular dielectric medium.* By converting fullwave scattering (S) matrix to the corresponding impedance (Z), admittance (Y) and transmission (ABCD) matrices, frequency-dependent RLGC of the coaxial TSV are analytically extracted based on ‘T’, ‘Pi’ and ‘lossy transmission-line’ models, showing a good agreement.* A SPICE broadband modeling approach is applied to accurately fit the amplitude and phase of insertion loss S11 and return loss S21 from 100 MHz to 100 GHz in the proposed coaxial TSV.

This work can help designers optimize the coaxial TSV physical design, hence improving electrical performance and maximizing the benefits of 3D integration/packaging.
SiP(System in Package) Solutions with Wafer Level Packaging Technology
Authors: Kang In Soo , Kim Jong Heon (Jay)
Published: October 2015

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed.

Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package.

In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.
300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera's MVP (TSV) Technology
Authors: Thomas Dave , Muggeridge Matthew , Steel Mike , Sanz Dorleta Cortaberria , Griffiths Hefin , Ansell Oliver , Kriman Moshe , Grinman Andrey , Gershtenman-Avsian Hagit
Published: October 2015

Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies are increasingly required to deliver greater reliability within smaller form factors.

Tessera's OptiML™ Micro Via Pad (MVP) wafer-level packaging technology is in production on 200mm wafers. This paper will report on the first joint activity that scales this technology to 300mm. We focus on three critical silicon etches that form the back-bone of the structure. These etches are carried out from the wafer back-side while bonded to a glass carrier.

First there is a blanket dry etch. This removes stress introduced by the back-grind. Uniformity control to < ±5% is essential for this process. Second, after a lithography step, tapered silicon trenches are etched forming streets to a certain depth. The trench etch uniformity is critical because it defines the depth range for the subsequent Vias. Profile control is needed to ease the subsequent spray-coat lithography. Lastly, vias are then etched down to metal bond pads on the device side of the wafer. CD and taper control is required here both within wafer and between wafers. End-pointing represents a way of ensuring process reproducibility.

In 2010 Tessera carried out 300mm demos with key suppliers. As part of this activity SPTS scaled the above critical silicon etches. The wafers were further processed into functional die.

We will describe the etch equipment used, report on the critical processes developed emphasizing the relationships between 200mm and 300mm results and the essential control parameters. We will also demonstrate successful scaling by including data on the electrical performance of packaged devices.
Cu Pillar is Ready for Prime Time
Authors: Appelt Bernd K , Chung Harrison , Wang Raymond
Published: October 2015

fcCSP packaging was historically based on solder interconnects. The continued drive towards higher I/O and shrinking package sizes has lead to very dense bump pitches which exceed those of CPUs. At area array bump pitches below 150 um, solder bumps require very complex HDI or ABF-BU substrates which make them unaffordable for the mobile application space. Cu pillars are slim and tall when compared to solder bumps and thereby provide more space between interconnects at the same pitch. This increased space can be utilized on the substrate side to relax the trace pitch and/or to route escape traces between the pillars. The net effect is a simpler and lower cost substrate. The higher stand-off facilitated by the tall pillars allows undermolding which is significantly more cost effective than capillary underfilling. Here, design rules,process flow and reliability data will be presented from volume manufacturing processes. Modeling data for low K die with Cu pillar will be discussed as well.
Copper Migration in Flip-Chip Substrates Under Biased-HAST Conditions
Authors: Stahley Matthew E. , Osenbach John W.
Published: October 2015

Biased-humidity testing is a critical reliability qualification requirement for integrated circuit packages. The benchmark of THB (Temperature Humidity Bias) at 85C/85%RH/bias for 1000 hours is a long duration test, so biased-HAST (biased Highly Accelerated Stress Test) conditions are adopted. Accelerated biased-HAST durations are based on aluminum corrosion failure mechanisms and may not be applicable to other materials such as in flip-chip packages. One such failure mechanism is discussed here.

Flip-chip packages with build-up substrates were exposed to biased-humidity at 85C, 110C, or 130C and 85%RH. After 96 hours of 130C/85%RH/bias, failures occurred with signatures ranging from bake-recoverable leakage to shorts. Physical failure analysis revealed copper migration in the substrate build-up dielectric rather than classical CAF (Conductive Anodic Filament) within the substrate core. No copper migration occurred with conditions of 110C/85%RH/bias, 85C/85%RH/bias, or 130C/85%RH/no-bias. Given that the JEDEC biased humidity durations are 96 hours at 130C/85%RH, 264 hours at 110C/85%RH, or 1000 hours at 85C/85%RH, it is concluded that the JEDEC acceleration function is not applicable for this failure mechanism.

A failure model is proposed based on humidity induced reduction of the glass transition temperature (Tg) of the build-up dielectric. Bond strength decreases and free volume increases above Tg, and the combination results in the formation of localized channels in the build-up dielectric where electrochemical migration of copper occurs under bias and humidity. Copper migration does not occur for conditions of humidity/bias below Tg, humidity/no-bias above Tg, and no humidity/bias near Tg. This indicates there is likely a threshold in humidity and/or temperature, below which copper migration does not occur. These results further demonstrate that caution must be used when employing accelerated reliability tests, as they may introduce failure mechanisms that would not occur in the field.
Packaging of MEMS for Integrated RF Circuit Verifications
Authors: Kim Bruce C. , Evana Sai , Kasim Rahim
Published: October 2015

This paper provides development of MEMS switches and packaging of MEMS to test radio frequency circuits used in wireless products such as cell phones and network routers. We discuss fabrication of MEMS using low voltage magnetic materials and their configurations to achieve the optimum switch to test RF low noise amplifiers. We have accomplished a very unique methodology to test low noise amplifiers using built-in sellf-test technique and our MEMS switches are proposed to achieve the verification of low noise amplifiers. Furthermore, we have used MEMS switches that we developed to perform self calibration to correct for the parametric variations and faults within the deep submicron CMOS circuits. We also discuss packaging of MEMS and low noise amplifier using 3D TSV technology.
Cost Comparison of Fan-Out WLP vs. Embedded Die
Authors: Palesko Alan , Vardaman Jan
Published: October 2015

Fabricating the package after the die is placed can result in smaller form factors, increased performance, and improved supply chain logistics for OEMs. There are many different approaches for this packaging technique, but two of the most prominent are Fan-Out WLP and Embedded Die. Fan-Out WLP leverages existing semiconductor technology for a cost effective approach to achieve relatively tight package design rules. The Embedded Die strategy leverages existing PCB lamination technology for cost-reduction through scale: fabricating many small packages on large production panels.

We will examine the cost differences and similarities between Fan-Out WLP and Embedded Die strategies by developing a comprehensive cost model for each technology. We will then analyze the manufacturing costs (labor, material, depreciation, yield loss, and tooling) and yield impacts across a variety of designs to demonstrate the cost differences and similarities in each packaging technology.
A New Robust One-Shot Switch for High-Power Pulse Applications
Authors: Baginski Thomas A. , Dean Robert N. , Surgnier Steven P.
Published: October 2015

High Voltage (HV) switches capable of operating at high speeds and over a wide range of voltages and energies are used in a variety of pulse power applications in material science and plasma physics. Of particular interest is the use of small-scale capacitor discharges to measure the electrical properties of materials as they are heated from solid through liquid to a gas phase. In a capacitive discharge unit (CDU), energy stored in a capacitor is coupled through a switch into a low-impedance transmission line, which typically terminates with a thin sample of material. The energy coupled to the sample is sufficient to cause vaporization. Voltages in such systems range from a few volts to thousands of volts. These vaporized materials are used either as plasma sources for physics experiments, or to propel a thin layer of electrically insulating polymer for high-pressure-impact studies.

Several types of switches have been used to drive these systems, including triggered spark gap, dielectric breakdown, and mercury vapor switches. A wide variety of solid-state devices, such as the insulated gate bipolar transistors, are also being utilized for these applications. Inducing a high-pressure shock wave in a dielectric to produce a transition from dielectric to conductor has also been used as an efficient single-shot switch for capacitor discharges.

The high-voltage micro-machined switch presented in this document has been designed as a single-use alternative to the more expensive triggered spark gaps and solid-stage devices. The plasma-bridge switch is intended for large-volume, relatively inexpensive systems, and a cost-effective switch for use in destructive testing.
In-Situ Wafer-Level Polarization of Electret Films in MEMS Acoustic Sensor Arrays
Authors: Kranz Michael , Allen Mark , Hudson Tracy
Published: October 2015

MEMS-based electret and polymer piezoelectric transduction techniques have been reported for both acoustic sensors and energy harvesters. Common techniques employed in MEMS polymer polarization include corona discharge and backlighted thyratron. This paper reports a method for post-fabrication in-situ polarization of polymer films embedded within the MEMS device itself. The method utilizes microplasma discharges with self-aligned charging grids integrated within the device to charge fluoropolymer films in a fashion similar to the common corona discharge technique. This in-situ approach enables the integration of uncharged polymer films into MEMS and subsequent post-fabrication and post-packaging polarization, simultaneously enabling the formation of buried or encapsulated electrets as well as eliminating the need to restrict fabrication and packaging processes that might otherwise discharge pre-charged materials. CYTOP, a thermoplastic fluoropolymer encapsulant for electronics, is used as a polymer electret in the current process because it can be spin-cast, has a high resistivity, and is easily etched in oxygen plasma. A microscale charging grid structure is then fabricated and suspended a short distance above the polymer film. After fabrication of the charging grid, standard microfabrication steps are performed to build a single-chip array of MEMS capacitive acoustic sensors designed to capture and analyze waveforms from impacts. After completing the entire fabrication and packaging flow, the polarization process is performed. When energized by a high voltage, the sharp metal edges of the charging grid lead to high dielectric fields that ionize the air in the gap and force electric charge onto the polymer surface. Final sensor arrays have been demonstrated and applied in the classification of acoustic stress pulses generated during impacts of various materials.
MEMS Tornado to Challenge Next Generation Packaging
Authors: Bryzek Janusz
Published: October 2015

In the last decade multiple MEMS devices entered Tornado (avalanche sales growth), adopting along the way the IC packaging technologies with a “twist”. Consumer applications for MEMS devices exploded, with sensor shipments increasing from 10M units in 2007 to over 2B units in 2011. This explosion resulted from Steve Jobs vision converting a cell phone into a powerful computer. Computing power enabled creative user interfaces, such as touch sensitive screens and auto landscape-portrait rotation, opening a Tornado for MEMS. As more complex MEMS devices are finding its way to cell phones, they will be creating packaging challenges.

An emergence of even a bigger forthcoming Tornado is surfacing.History shows that all major technologies coming to market enabled advancement of world-changing productivity and balance of power. At a recent conference, a VP of Maxim Integrated Products stated that we have entered the 3rd technical revolution which will free humans for creative work through a fusion of computing, communication and sensing. This will enable MEMS component market to catch up with the semiconductor market ($300B).At the 2010 MEMS Technology Summit conference at Stanford University, Bosch presented a vision for 7 trillion devices driven by Sensory Swarms connected to the Internet to serve 7 billion people in 2017 (in 2010 there were already 5 billion mobile phone subscribers). This vision translates to 1,000 sensors per average person in 2017. We are already seeing high end applications supported by large number of MEMS sensors in advanced cars, smart homes, smart phones and medical diagnostics, to mention a few.In 2010 HP outlined a vision for CeNSE, a Central Nervous System for the Earth, which expected to deploy a trillion nano sensors and actuators. Processing the sensor information will require increasing the size of Internet 1,000 times; creating huge demand for computing and generating by 2013 a $70B global market for sensing systems, and $290B market for value added sensing services.

As device volumes start approaching a trillion units a year, packaging challenges will be created by:Complexity of emerging MEMS devices. The required “twists” to IC packaging will be in the areas such as low package stress, chemical and fluidic media compatibility, optical performance, etc.Cost pressure.

Due to a sheer size of expected market, packaging industry may expect very large changes.

Addressing these challenges will likely have a big impact on the packaging industry.
TSV Market Drivers, Demand & Product Readiness
Authors: Huemoeller Ron
Published: October 2015

The market has narrowed its approach and solidified its direction for the majority of 2.5 and 3D TSV product technologies. Forecasts have now become real for these technologies and the end game realized as evidenced by production launch of the Xilinx Virtex-7. This talk will discuss market trends, anticipated product launch dates as well as general capacity needs as the market begins to rollout these new products.
Assembly Challenges for Large Interposer 2.5D TSV Products
Authors: Mattei Marnie , Kelly Mike
Published: October 2015

Interposers provide a crucial intermediate step for next generation products to allow side-by-side integration of technology optimized devices ahead of a full 3D assembly. The interposer size in most cases is greater than 22mm on a side and in some designs exceeds 30mm. This large size combined with a thickness of ≤ 100 microns may result in high warpage which can significantly impact the assembly process. Materials and process selection become a key consideration to create a high yielding, multi-die stacked product.

This presentation will outline the challenges of a large 2.5D TSV product and how assembly strategies can be used to accommodate these challenges. Different process options and die attach sequences for interposer to substrate and chips to interposer will be discussed. The assembly methods for attaching multiple die with tens of thousands of I/O at 40 micron fine pitch will be compared in relation to the die size and interposer warpage. Product design requirements may also dictate that the optimum assembly approach is achieved by combining methods such as mass reflow and TCNCP bonding for die attach and underfill. Test considerations at intermediate assembly steps will also be reviewed for feasibility in the overall process flow.
The Reactive Bridge: A Novel Solid-State Low Energy Initiator
Authors: Baginski Thomas A. , Dean Robert N.
Published: October 2015

Within a broad variety of commercial (i.e. automotive airbags, mining) and government ordnance systems there exists an interface which utilizes electrical energy to initiate an exothermic reaction (i.e. combustion, deflagration, detonation). The structure that performs this function is commonly referred to as an Electro-explosive device (EED). The basic EED design is susceptible to initiation failures due to mechanical hazards such vibration and shock.

This paper discusses the fabrication and characterization of a micro-machined EED (the Reactive Bridge) which is mechanically robust, extremely reliable and inexpensive to manufacture. The structure is capable of directly initiating a wide variety of pyrotechnics and primary explosives. The Reactive Bridge offers the additional advantage of being able to be directly fabricated onto any custom integrated circuit. This feature may be of particular interest for adding anti-tamper features directly at the individual die level of electronic systems.

The structure consists of patterned sequential layers of titanium and boron which react exothermically when properly initiated. Design parameters will be discussed and compared to firing data for Reactive Bridge EEDs loaded with fine grain zirconium potassium perchlorate (ZPP). A number of different sized bridges were investigated. Scanning electron microscope photographs of cross-sectioned devices before and after firing will also be discussed.
MEMS Based Transducer Designs for Monitoring High Speed Impacts
Authors: Reiner Philip , Jenkins Arthur , Sanchez Sharon , Hudson Tracy D. , Kranz Michael
Published: October 2015

MEMS based technologies provide a unique opportunity to develop micro-machined mechanical transducers for a variety of sensing applications. The micro-machining techniques that have been widely used for MEMS sensors provide a viable path for developing miniature sensors required for monitoring stress and strain for high speed impacts. Moreover, this technology allows sensors to be tailored to respond to specific vibrational modes and mode types. In particular, the electro-mechnical properties must be able to support very short response times without compromising signal strength. In this paper, we present the design and fabrication of micro-miniature PNZT based transducers for short duration mechanical impacts. Comparisons of their performance with conventional PZT transducers are presented. A discussion is also given of key performance parameters and the effects of post-fabrication processing and packaging on transducer performance.
3D Packaging Solution Providing DDR & LPDDR Co-Support for Ultrabooks and Next Generation Servers
Authors: McElrea Simon , Solberg Vern
Published: October 2015

Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. To enable the new generations of processors to reach their performance potential many manufacturers have developed more efficient interface formats that enable greater memory bandwidth. This revolution in performance driven electronic systems continues to challenge the IC packaging industry. The challenge is clear. To ensure that the memory functions are able to support the increased signal speed, product developers will need to explore more innovative 3D package assembly techniques and process refinement methodologies. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and, from the users perspective, end product reliability.

For some applications companies have had limited success in stacking die elements directly onto an interposer substrate using wire-bond processes. High performance DRAM die, however, is especially difficult to stack. This is due to the center positioned wire-bond sites. This factor has complicated the DRAM die stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. Stacking individually packaged DRAM (package-on-package) has had considerable success but the package outline dimension and package height can be excessive. In this paper the authors will introduce a very innovative and very thin 3D package developed specifically for center-bond pad DRAM die. The package assembly methodology promises to remain economical because it requires no special die level process steps and it can utilize the existing package assembly infrastructure. Additionally, data compiled during extensive performance and reliability modeling will be presented along with the results from actual physical qualification testing.
Low-Temperature Indium Bonding for MEMS Devices
Authors: Harris Daniel , Dean Robert , Palkar Ashish , Palmer Mike , Ellis Charles , Wonacott Gary
Published: October 2015

Low–temperature bonding techniques are of great importance in fabricating MEMS devices, and especially for sealing microfluidic MEMS devices that require encapsulation of a liquid. Although fusion, thermocompression, anodic and eutectic bonding have been successfully used in fabricating MEMS devices, they require temperatures higher than the boiling point of commonly used fluids in MEMS devices such as water, alcohols and ammonia. Although adhesives and glues have been successfully used in this application, they may contaminate the fluid in the MEMS device or the fluid may prevent suitable bonding. Indium (In) possesses the unusual property of being cold weldable. At room temperature, two sufficiently clean In surfaces can be cold welded by bringing them into contact with sufficient force. The bonding technique developed here consists of coating and patterning one Si wafer with 500A Ti, 300A Ni and 1 μm In through electron beam evaporation. A second wafer is metallized and patterned with a 500A Ti and 1 μm Cu by electron beam evaporation and then electroplated with 10 μm of In. Before the In coated sections are brought into contact, the In surfaces are chemically cleaned to remove indium-oxide. Then the sections are brought into contact and held under sufficient pressure to cold weld the sections together. Using this technique, MEMS water-filled and mercury-filled microheatpipes were successfully fabricated and tested. Additionally, this microfabrication technique is useful for fabricating other types of MEMS devices that are limited to low-temperature microfabrication processes.
High-Aspect Ratio Planarization using Self-Leveling Materials
Authors: Fowler Michelle , Bai Dongshun , Planje Curt , Shao Xie
Published: October 2015

There are an increasing number of applications in the microelectronics industry that require materials that can fill and planarize high-aspect ratio topography. These applications call for the formation of a flat coating surface without the use of high bake temperatures or high-pressure processes. Potential device markets include MEMS, 3D-ICs, LEDs, semiconductors, flat panel displays and related microelectronic and optoelectronic devices. Various polymeric coating materials have been developed that have intrinsic self-leveling properties and are able to fill deep trenches and holes found on microelectronic substrates without forming voids. These new materials are able to reflow at modest baking temperatures (50–100 °C) and can fill high-aspect ratio features (10:1) by spin coating single or multiple layers of material over the topography. Several of these polymeric materials remain soluble in TMAH (and other aqueous bases), some are photosensitive, and all materials are compatible with industry-accepted solvents. Results from extended process development work on self-leveling polymeric materials will be discussed and comparisons made to industry-accepted practices.
3D Glass and Silicon Interposers with TPV vs. 3D ICs with TSV
Authors: Tummala Rao
Published: October 2015

3D Packaging has been emerging as the dominant theme for more than a decade. It started as package on package stacking in the 1970s for memory devices. More recently, it moved to stacked, wire bonded chips as well as miniaturized package-on-package (POP). Stacking with flip chip soon followed. In all these cases, ICs are fabricated in wafer fabs and packaging of these ICs was subsequently performed independently. The next natural evolution to be expected is to eliminate external interconnections outside the ICs by means of through vias, now called TSVs. But this became revolutionary, complex and costly. It impacted wafer fabrication by virtue of having to co-process transistors, BEOL wiring and TSV interconnections, all in the wafer fab. This is referred to as 3D ICs with TSV.

The benefits of 3D ICs are overwhelming. They include highest performance in smallest size by virtue of stacking many ultra-thin ICs and interconnecting them with through-silicon-vias. But such a technology is also complex and costly to manufacture. It presents many other problems that include thermal management, testability, and extendibility.

Georgia Tech PRC proposes to demonstrate lower cost and simpler 3D Interposers with TPVs to address most of the above challenges. In this scenario, through-package-vias (TPV) are fabricated in the ultra-thin and low-cost silicon or glass interposers at the same I/O density or pitch as in TSVs in the logic ICs but without the need for TSVs in the logic ICs. Such a concept is 3-dimensional; allowing stacking of ICs on both sides of the interposer with the same I/O pitch as TSVs and yet minimizes the thermal, testability and extendibility problems.

This paper presents the status, progress and remaining challenges of 3D Interposer concept at Georgia Tech involving more than 25 companies in a global consortium.
Embedded Chip Technology: Technologies, Applications and Future Developments
Authors: Boettcher Lars , Karaszkiewicz S. , Manessis D. , Ostmann A.
Published: October 2015

Technology approaches for the embedding of active and passive components using printed circuit board materials and processing gained an increasingly high interest over the last years. The use of such technologies for industrial fabrication has attracted increasingly interest by manufacturers and commercial products have been released.

The realization of embedded modules is quite a robust process for different applications. Several approaches for a laminate based embedding of components were developed and implement into the manufacturing. An overview and status of the different methods and their advantages for specific applications will be given.

The process flow, yield and challenges of such technologies for miniaturized packages and modules will be presented briefly.

By nature of the process, extremely flat packages can be realized. The routing of electrical contacts from the embedded components to the top and bottom side of the package allows the fabrication of highly versatile package layouts. The flatness and freedom in design makes these packages ideal candidates for package on package stacking. The main focus of the presentation will be the discussion of different applications. Single and multi-component packages will be presented. Extensive reliability testing of single die packages was done in order to compare different material sets for embedding, but also to compare the reliability of such embedded die packages with conventional packages. In addition, new process developments targeting the embedding of ultra-fine pitch dies, with pad pitches below 100 μm, will be shown.

Manifold applications targeting e.g. medical and power electronic modules will be presented and their way of manufacturing will be described.

Recent developments focus on the use of such embedding technologies for the integration of high-power modules e.g. for automotive applications (Hybrid and eCars). Beside the integration of semiconductors, to achieve miniaturization and high robustness of such modules, also the use of organic substrates as an alternative to currently used direct copper bonded (DCB) boards is of high interest. The need to handle high current and to realize an excellent thermal management are the main challenges for these modules. The concepts and first results of these latest developments will be presented in detail.

Rozalia/Ron ok move from 2.5/3D to Passive 1-3-12.
Ultra-Slim Packages
Authors: Appelt Bernd K.
Published: October 2015

What does thin or ultra-slim packaging mean? That of course depends on the particular cross-section of the substrate e.g. single layer vs. double layer vs. coreless or embedded component substrate, etc. The thinnest prepreg based substrate and concomitant package is a single layer substrate termed a-S3 ™ and can be as thin as 90 μ and 400 μ, respectively, with the appropriate mold cap. The manufacturing concept for a-S3 has inspired a new manufacturing concept for thin prepreg based coreless substrates with any number of layers. Layers two through five have been demonstrated successfully. The practical layer count is limited only by yield and cycle time. The same concept has been extended also to embedding active die as well as passives, a-EASI™. The total package height here is governed by the thickness of the embedded elements. The simplest embedded substrate is a two layer substrate with a MOSFET die. The advantage is a very low profile power package with excellent electrical and thermal performance. The interconnections to the die/passives are formed by plated laser vias as is common practice. Process flows and concepts will be introduced here. Thin substrates do pose many challenges during substrate manufacturing as well as during assembly. Some of the handling concepts will be elucidated. Sample pictures will be shown to demonstrate successful builds and some reliability data will be presented as well.
Silicon Wafer Thinning to Reveal Cu TSV
Authors: Mauer Laura , Taddei John , Youssef Ramey
Published: October 2015

3D Integration is becoming a reality in device manufacturing. The TSV Middle process is becoming the dominant integration scenario. For this process flow the silicon wafer needs to be thinned to reveal the Cu TSV. Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes CMP and plasma have been used to complete the final thinning of the silicon. This paper will describe a simple, cost effective method to wet etch the remaining silicon to reveal the Cu TSVs. KOH is selected as the etchant since it will not attack the TSV materials and has a higher etch rate than TMAH. The development of processes with optimum etch rates and uniformity for silicon etching along with no attack of the Cu via or oxide liner and effective post cleaning to remove residual Potassium will be presented.
Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers
Authors: Gallagher Michael , Kim Jong-Uk , Huenger Eric , Zoschke Kai , Lopper Christina , Toepper Michael
Published: October 2015

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade.

Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature.

Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state.

Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied.

Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.
Improvement of Plated Copper Adhesion in Glass Interposer Applications
Authors: Bamberg Simon , Sukumaran Vijay , Sundaram Venky , Tummala Rao , Etzkorn Johannes , Brüning Frank
Published: October 2015

Glass interposers offer a compelling alternative to silicon interposers with highest I/Os and excellent electrical performance, with potential for low cost from large panel processing. For sub-32nm IC nodes and 3D-IC packages at fine I/O pitch, organic substrates are reaching their limits in terms of I/Os, design rules and CTE mismatch. Glass offers the best combination of electrical insulation, dimensional stability, CTE match to Si ICs, and flat, smooth surfaces for ultra-fine line lithography. The biggest challenge in glass interposers is the formation and metallization of ultra-fine pitch through vias. The formation of small via diameters in thin glass substrate have been demonstrated. The focus of this paper will be on wet metallization of glass interposer with through via, and addressing the challenge of providing reliable adhesion on the copper-to-glass interface. Two main approaches are currently pursued in the wet-chemical metallization of glass interposers: the electroless and electrolytic copper deposition on a) bare glass with photo-structured or laser-ablated through vias and b) the deposition on an intermediate polymer surface layer, requiring glass metallization only on the via sidewalls. Therefore, in addition to the analysis and optimization of adhesion-improving techniques on different glass types, their performance on different polymer liners is also assessed. The techniques include surface conditioning with cationic polyectrolytes and deposition of silica. The effect of the above surface pretreatments on plated copper adhesion is analyzed and the results provide guidelines for reliable glass interposer TPV metallization.
Micromachined Snap-In Resonators
Authors: Stevens Colin , Dean Robert , Wilson Chris
Published: October 2015

MEMS resonators have many applications, including micromachined gyroscopes, resonating pressure sensors and RF devices. Typically, MEMS resonators consist of a proof mass and suspension system that allows the proof mass motion in one or two directions. Micromachined actuators provide kinetic energy to the proof mass, usually at its resonant frequency. In the simplest resonators, the actuators are driven with an AC signal at or near the resonant frequency. In more complex resonators, the actuator-proof mass system is placed in an amplifier feedback circuit so that the electromechanical system self-resonates.

MEMS parallel plate actuators (PPAs) are simple to realize, yet complex nonlinear variable capacitors. If a DC voltage is applied in attempt to move the proof mass greater than 1/3 of the electrode rest gap distance, the device becomes unstable and the electrodes snap into contact. A current limiting resistor is often placed in series with the PPA to limit short circuit current due to a snap-in event.

Consider the effect of placing a large resistor, on the order on 10 meg-Ohms, in series with the PPA. Then apply a DC voltage across the resistor-PPA pair of sufficient voltage to cause snap-in. Once the electrostatic force (ES) exceeds the spring force (SF), the electrodes will accelerate toward each other. The capacitance between the electrodes swells as the separation distance shrinks. Since the large resistor limits the charging rate of the capacitor, the voltage across it drops. Once the SF exceeds the EF, the momentum of the movable electrode brings it into contact with the fixed electrode, discharging the capacitor. The movable electrode then accelerates away from the fixed electrode while the resistor slowly allows recharging. After recharging, the cycle repeats resulting in stable oscillation. This resonator requires only a DC power supply, a resistor and a MEMS PPA.
Integration, Electrical Performance and Reliability Investigation of TSV
Authors: Lee Shih-Wei , Hu Yu-Chen , Chiang Cheng-Hao , Chen Kuo-Hua , Chiu Chi-Tsung , Chuang Ching-Te , Hwang Wei , Chiou Jin-Chern , Tong Ho-Ming , Chen Kuan-Neng
Published: October 2015

Three-dimensional (3D) integration method has become the candidate to extend the Moore's law due to its heterogeneous integration, multiple functionality, and low power consumption. To realize 3D integration, Through-silicon via (TSV) has emerged as a good approach to provide higher wiring density, shorter interconnect, and simpler structure. In this study, the overall processes of TSV including via etching, liner deposition, and copper filling are investigated. First of all, in the etching process, the mechanism and the solution of micro-masking effect were studied. Secondly, in the liner deposition, the analysis of different TSV liners was done by using its step coverage, stress, breakdown voltage, and leakage. Finally, in the process of the copper filling, a novel sealing bump method was proposed because of its advantages in less process steps and the self-formation of bonding pad. Test vehicles, including daisy chain, Kelvin structure, and comb structure, were designed with various sizes of TSV to verify the quality by using electrical measurements. In addition, the design rules of TSV were also investigated with reliability tests on different arrangement and pitch of TSV. This study not only proposes a novel design and structure of sealing bumping TSV method, but also summarizes the integration of this TSV with its excellent electrical property and reliability performance, providing a promising technique for TSV integration in 3D IC. Furthermore, the investigation results of design rules provide a useful guideline of TSV placement in the IC layout for future 3D integration.
Ultra-fine pitch Package on Package solution for high bandwidth mobile applications
Authors: Katkar Rajesh , Zhao Zhijun , Zhang Ron , Co Rey , Mirkarimi Laura
Published: October 2015

Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint.

BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.
Multi-scale materials data for 3D TSV stack performance simulation and model validation
Authors: Zschech Ehrenfried , Yeap Kong Boon , Sander Christoph , Mühle Uwe , Sukharev Valeriy
Published: October 2015

Within a DFM type of methodology, the application of physics-based models for a multi-scale simulation of mechanical stress in 3D TSV-stacked products was proposed in [1]. Highly accurate multi-scale materials data are needed as input for this approach of simulation and for model validation.

This paper focuses on the set of materials data for wafer-level and package-level structures, needed to feed a materials database that comprises the input parameters for simulation. Particularly the generation of materials data such as (local and effective) Young's modulus, Poisson ratio and (effective) coefficients of thermal expansion (CTE) on several scales will be described. The nanoindentation method was developed further to measure local and effective elastic modulus values and Poisson ratio for micro-bump, TSV and BEoL stacks. TCAD simulations show significant influence of the copper microstructure on the charge carrier mobility in transistors [2]. To consider the orientation dependence of elastic properties of copper, nanoindentation with extremely low penetration depths was applied. A high-resolution in-situ technique was developed to determine “composite CTE” values for BEoL stacks. A free-standing cantilever containing the region of interest was extracted using the FIB technique, and imaged in a SEM at several temperatures.

For model validation and calibration, local stress measurements are needed to determine the effect of the TSV/package-induced stress on the transistor performance. Due to the high resolution needed, the only direct technique to measure strain in transistor channels is TEM. For the first time, the strain in transistor channels will be reported as a function of the distance from the TSV, based on Convergent Beam Electron Diffraction (CBED) data.