Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures
Authors: Galembeck Egon henrique Salerno , Gimenez Salvador Pinillos 
Published: May 2020

Introduction: There is a growing interest in new electronic systems that must operate at high temperature (T) for automotive and space electronics, etc. To reach this purpose new device architectures have been proposed, such as the Gate-All-Around, double-gate, Multigate SOI MOSFETs, etc. [1]. However, there is a new concept, still little explored by the integrated circuits industries, which is based on the simple change of the gate geometry of MOSFETs [2]. This pioneering technique is capable for boosting the electrical performance of MOSFETs, thanks to two new effects of these structures, called “Longitudinal Corner Effect” (LCE) and “PArallel connection of MOSFETs with Different channel Lengths Effect” (PAMDLE) [2]. The Ellipsoidal layout style for MOSFET (EM) [4] is an example this new concept. Thus, this manuscript performs a comparative study by three-dimensional (3D) numerical simulations of the effects caused by the high T (300K-573K) in main electrical parameters of the EM in relation to the Rectangular MOSFET (RM) counterpart, regarding the same gate area, channel width and bias conditions. Furthermore, for the first time, is analyzed the electrical behaviors of LCE and PAMDLE in these conditions. Based on these results, we conclude that the EM always presents a better electrical performance {two times higher for the drain current normalized [IDS/(W/L)] and 77% higher for the transconductance normalized [gm/(W/L)]} than that found in the RM counterpart at high T. Besides, the LCE and PAMDLE always keep actives in the EM as the T increases.

Results: The 3D numerical simulations were performed by using of the Sentaurus TCAD/Synopsys. The doping concentrations of the drain/source and channel are 1019cm-3 and 1017cm-3, respectively, gate thin-oxide thickness is 4.2nm and work-function of polysilicon is 4.15eV. The threshold voltages for both devices are equal to 50mV in room T.

Fig.1 shows the IDS/(W/L) as a function of gate voltage (VGS) for different temperatures of the EM (Fig.1a) and RM counterpart (Fig.1b). Based on results, we observe that the Zero Temperature Coefficient (ZTC) biases of the EM and RM (VZTC) are practically similar (difference of 6%), while the EM IDS/(W/L) in the ZTC point is 142% higher than the one measured of RM, thanks the LCE and PAMDLE present in the EM structure.

Fig.2 illustrates IDS/(W/L) as a function of drain bias (VDS) considering different temperatures. The EM IDS/(W/L) in all temperatures studied, considering the triode and saturation regions, are always higher (2 times higher) than the ones observed in RM counterpart.

Based in these previous results, Fig.3 presents the gmmax/(W/L) and IDS_SAT/(W/L) as a function of the T. We have observed that the gmmax/(W/L) (72% and 81% for 300K and 573K, respectively, Fig.3a) and EM IDS_SAT/(W/L) (2 times higher, Fig.3b) are always higher than those found in the RM counterpart thanks to LCE and PAMDLE and they reduce with the T increases. Therefore, we have concluded that the LCE and PAMDLE are always active in this huge range of high temperatures, according Fig.4, which the resultant longitudinal electric field (RLEF) in the center of the channel length (L) of the EM (Fig.4a) reduces 6% as the T varies (300K-573K). The maps of the EM RLEF lines are illustrated in Fig.4b for different 2 Ts, wherein the width of the depletion region (d) composed by the source/channel regions reduces as the T increases. Furthermore, Fig.4c illustrates de map of the EM IDS lines which are curves near to the edges and straight in the center of the L, due to the interactions of the longitudinal electric field components (3 in the straight defined by the foci of the ellipse and 2 out of it).

Conclusion: We have concluded that the LCE and PAMDLE are always actives as the T increases and consequently are capable of boosting the EM electrical performance in comparison to the one of the RM counterpart, regarding all T studied. Furthermore, as the T increases, the magnitude of the RLEF reduces 6%, because of the reduction of the Fermi Potential that defines the surface potential. Besides, we observe that the width of the region where the RLEF acts along the channel region of the EM increases due to reduction of depletion region width between source/channel regions (from d1 to d2), as the T increases.

Acknowledgment: We thank to the São Paulo Research Foundation (FAPESP), grant #2017/10718-7 and CNPq, grant #308702/2016-6 for financial support.

References:

[1]Lee, C.-W., et al. IEEE TED,57,620-625,(2010).

[2]Gimenez, S.P., Layout Techniques for MOSFETs,(2016).

[3]Galembeck, E.H.S., et al. IEEE TDMR,17,221-228,(2017).

[4]Gimenez, S.P., et al. IEEE EDL,36,705-707,(2015).

[5]Filanovsky, I.M., et al. IEEE TCS,48,876–884,(2001).

Figure 1