bluuebunny/crossref_metadata_2025 huggingface dataset:
Manufacturing Substrates with Embedded Passives
Authors: Das Rabindra N. , Papathomas Konstantinos I. , Lauffer John M. , Poliks Mark D. , Markovich Voya R.
Published: October 2015

Passives account for a very large part of today's electronic assemblies. This is particularly true for digital products such as cellular phones, camcorders, computers and several critical defense devices. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on organic multilayered substrates. A variety of thin film capacitor and resistors were utilized to manufacture high-performance embedded passives. The electrical properties of capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide temperature range. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. In both cases, capacitance values are defined by the feature size, thickness and dielectric constant of the polymer-ceramic compositions. Nanocomposite can be directly deposited either by liquid coating or screen printing. Alternatively, nanocomposite thin films can be laminated and capacitor laminate can be used as the base substrate for subsequent build-up processing. For example, Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. The capacitor fabrication is based on a sequential build-up technology employing a first patternable electrode. After patterning of the electrode, RC3 nanocomposite can be laminated within PCB. Embedded passive cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. Reliability of the capacitors was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1000 cycles DTC (Deep Thermal Cycle).
Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies
Authors: Darveaux Robert
Published: October 2015

There are several application and device trends driving IC package development today. Among the most prevalent are:- Form factor reduction for handheld devices- Increased functionality requiring higher bandwidth- Higher power dissipation- Higher operating frequencies resulting in reduced electrical noise margins- Increased use of sensors- Full conversion to green material sets- Silicon node progression.

These trends occur concurrently in many applications, which often results in conflicting requirements. In addition, the market continues to apply relentless pricing pressure on the supply chain. Hence, simple, cost-effective solutions are mandatory. This presentation will highlight packaging technology developments that address the device and application trends listed above. Several innovative packaging platforms will be discussed:- Copper pillar CSP and BGA- Through Mold Via Package on Package (TMV ® PoP)- Flip Chip Molded BGA (FCMBGA)- Wafer Level CSP- Through Silicon Via CSP and BGA.

In each case a clear value proposition will be presented, along with key supporting data. It is truly an exciting time to be part of the industry solving complex packaging and interconnect challenges.
Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology
Authors: Bachman Mark A. , Liao Jerry , Osenbach John , Kutlu Zafer , Gim Jaeyun , Brady Danny
Published: October 2015

To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die size and package body size and inversely with bump pitch, manufacture of large die and package size flip chip devices made with extremely low K dielectrics has proven to be challenging. The stress challenge is further exacerbated by the RoHS requirements for lead free packaging which requires higher process temperatures and somewhat higher yield point solders. The combination of increased stress and reduced mechanical robustness of porous dielectrics has lead to significant reliability and assembly yield issues that have in some cases slowed the introduction of 45nm and 40nm large die lead free flip chip into the market.

The work summarized in this paper shows that devices designed to withstand stresses in combination with appropriate assembly processes and bill of materials, yield highly reliable, lead free flip chip packaged devices, with die sizes greater than 400mm2 and package sizes greater than 42.5mm on a side in commercial assembly production lines.
New Advances in 3D/2.5D Integration
Authors: Patti Robert
Published: October 2015

It is widely agreed that memory is the low hanging fruit of 2.5/3D integration. It demonstrates the advantages of bringing togther semiconductor processees and technologies that are difficult to cost effectively combine in an SOC. The presentation will describe the latest efforts to combine large memories with logic elements using interposers as well as a more full 3D stacking approach. Discussion of devices recently made and those in progress will include results and lessons learned.
Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die
Authors: Lecarpentier Gilbert , De Vos Joeri
Published: October 2015

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch
Cost-Effective Precision 3D Glass Microfabrication for Advanced Packaging Applications
Authors: Flemming Jeb , Cook Roger , Dunn Kevin , Gouker James
Published: October 2015

Today's packaging has become the limiting element in system cost and performance for IC development. Assembly and packaging technologies have become primary differentiators for manufactures of consumer electronics and the main enabler of small IC product development. Traditional packaging approaches to address the needs in these “High Density Portable” devices, including FR4, liquid crystal polymers, and Low Temperature Co-Fire Ceramics, are running into fundamental limits in packaging layer thinness, high density interconnects (HDI) size and density, and do not present solutions to in-package thermal management, and optical waveguiding.

In this talk, 3D Glass Solutions will present on our efforts to create advanced microelectronic packing solutions using our APEX™ Glass ceramic which offers a single material capable of being simultaneously used for ultra-HDI through glass vias (TGVs), optical waveguiding, and in-package microfluidic cooling. In this talk we will discuss our latest results in wafer-level microfabrication of packaging solutions. We will present on our efforts for creating copper filled vias, surface metallization, and passivation. Furthermore, we will present our efforts in exploring this material to produce (1) ultra-HDI glass interposers, with TGVs as small as 12 microns, with 14 micron center –to-center, (2) advanced RF packages with unique surface architectures designed to minimize signal loss, and (3) creating wave guiding structures in HDI packages.
Temporary Wafer Bonding Materials and Processes
Authors: Lueck Matthew , Huffman Alan , Butler Marianne , Temple Dorota , Garrou Phil
Published: October 2015

Temporary wafer bonding has been used for many years to provide mechanical support to device wafers during thinning processes. However, the advent of 2.5D and 3D integration is placing significantly higher demands on the performance of temporary bonding materials as more fabrication processes are required on progressively thinner wafers. In response, materials providers have recently developed several different types of temporary bonding solutions that seek to provide a robust carrier with a simple debond process.

Typical 2.5D or 3D integration process flows will require more types of processes than just backgrinding and CMP to be done on the backside of thinned wafers. RIE, PECVD oxide deposition, lithography, and electroplating are some of the process steps that will be needed to complete the TSV interconnects. Each of these steps, and the order in which they are done, will impose certain requirements on the temporary bond material. This presentation will examine the different categories of available temporary wafer bonding solutions with regard to their bonding and debonding methods as well as their resistance to and compatibility with various BEOL processing steps. In addition, ongoing work at RTI to evaluate temporary bond materials for silicon interposer and 3D-IC applications will be presented. This work has been focusing on the interaction between these materials and the processing requirements of several photoimageable dielectrics.
Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution
Authors: Yoon Seung Wook , Lin Yaojian , Jin Yonggang , Teysseyre Jerome , Baraton Xavier , Marimuthu Pandi C.
Published: October 2015

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size.

This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.
Development of Electronic Substrates for Medical Device Applications
Authors: Egitto Frank D. , Das Rabindra N. , Marconi Francesco , Wilson Bill , Markovich Voya R.
Published: October 2015

There is a strong desire to develop advanced electronic substrates that can meet the growing demand for miniaturization, high-speed performance, and flexibility for medical devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present study, we are developing flexible packages for a variety of medical applications. Here we discuss several classes of flexible materials that can be used to form high-performance flexible packaging. In addition, copper thinner than 5 μm is routinely used, with copper layers as thin as 0.2 μm used as a seed layer for semi-additive approaches. The use of semi-additive circuitization facilitates manufacture of fine-line circuit features, and traces narrower than 12μm have been produced routinely. A smooth copper-polymer interface is ideal for high speed applications and for fine line etching. Selection of an appropriate material provides good copper adhesion to the base film. Flexible materials with 1 or 2 metal layers provide the smallest possible roll diameter for systems such as catheters. Compatibility with well developed, high performance electronic materials represents a key advantage of flexible electronics systems that are enabled by high density fine line structures rather than unusual materials. Electrical interconnection between the chip and package can be made by a number of means. Solder-coated Cu-micro pillars for a variety of finer pitch applications are being developed. Cu micro pillars are grown through the dielectric or silicon and subsequently coated with solder to produce finer pitch 3D-interconnects. The paper also describes a novel approach for the fabrication of flexible electronics on PDMS substrates. The paper discusses the fabrication of PDMS substrates using different circuit patterns and geometries.

Rozalia/Ron ok move from 2.5/3D to FC/WLP 12-21-11.
Thermal Reliability for LED Lighting Design
Authors: Kolbe Justin , Misra Sanjay
Published: October 2015

Light output and quality of light will degrade over the lifetime of an LED assembly. Several failure mechanisms will determine the mode, rate and extent of degradation. Temperature exposure and temperature induced mechanical stresses are major culprits behind performance degradation. We will explain the physical-chemical nature of these mechanisms. In addition we will address tools to assess and model the robustness of a thermal design. Finally, we will highlight various solutions that will mitigate thermal degradation.
Gold Stud Bump on Sn Based Solders
Authors: Collier Terence Q.
Published: October 2015

When thick gold and tin come into contact the intermetallic formed is not one for long term reliability. AuSn intermetallics can lead to void formation, increased resistance and a very brittle joint that will fail in time.

Such intermetallic formations occur when gold stud bumps are brought into contact with Sn based allows. Fine pitched devices, such as optical, typically use gold studs due to the tight pitch and small pad sizes. By transforming the gold to a less benign state the gold stud bumps allow assembly using standard Sn based solders.

Such a process is beneficial when cheapers solders can be used as well as standard flip chip assembly equipment. This paper will provide cross sections of gold stud bumps with SAC305 solder after 3X reflow. The 3X reflow is required to demonstrate the capability and reliability of the modified solder joint.

Rozalia/Ron ok move from 2.5/3D to FC/WLP 12-21-11.
Stacked 3d package with improved bandwidth and power efficiency
Authors: Gupta Dev
Published: October 2015

Stacked die packages such as PoP are used in space - constrained portable systems e,g. SmartPhones. The processor ( SoC ) and Mobile DRAM chips are stacked vertically to fit the combination within the restricted board space. The use of wire bonds in the memory chips as well as package level interconnects introduces delays into the data transmitted between the chips and limits the max. clock rate ( at present about 533 MHz for LP DDR 2 memory ) and hence the data transfer rate / bandwidth to less than 6.4 GB per sec. For Smart Phones to become capable of PC quality Games and high speed video would require a doubling of the bandwidth to over 12.8 GB per sec. To achieve that target PoP type packages were to be replaced by 3-d stacks using TSVs and wide I/Os. However recently JEDEC has postponed the introduction of Wide I/O Mobile memory stacks ( using TSVs ) to 2015. So the bandwidth of PoP packages must be improved.

A physical way to increase the Bandwidth between the SoC and memory chips in a PoP is by increasing the max. no. of vertical I/Os as this allows more channels / higher parallelism in data transfer. This can be accomplished by shrinking the pitch ( from current 0.4 mm to 0.3 mm ) and doubling the number of rows of vertical I/Os ( from current 2 to 4 ) in PoP. However this requires major effort for the Packaging supply chain and would still fall well short of the future Bandwidth and interconnect Power efficiency targets.

In this paper we will describe modifications and additions to the baseline PoP package so that it can be operated at clock rates up to 800 MHz and deliver bandwidth of 12.8 GB per sec or more and match the Interconnect Power efficiency of 3-d stacks with TSVs.

Compensation features are introduced for ea. interconnect line between the SoC and Memory in the PoP package. The features are integrated on chips that are inserted between the two layers of the package. The vertical interconnection between the two levels of the PoP are replaced and routed through this additional chip.

Only minor changes are required in the baseline PoP package thus will not require long delay to shrink current PoP interconnect pitch etc. The additional chip is built with available technologies and would increase cost by only a fraction of that needed for stacks with TSV-based wide I/O.

Simulation results will be presented and compared with test results.
The Continued Adoption of ZiBond and DBI in Volume Applications
Authors: Cook Kathy
Published: October 2015

Abstract not available. Outline:

Company Background; Intellectual Property Status; Homogeneous Direct Bond (ZiBond) Technology; Hetergeneous Direct Bond (DBI) Technology; Wafer to Wafer (W2W) Applications; Implementation; and Summary
High Reliability Fine Pitch WLCSP for High Pin Count Applications
Authors: Lawhead David , Yazzie Ronnie , Curtis Tony , Burgess Guy , Tessier Ted
Published: October 2015

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements.

This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.
An Innovative 2.5D IC Interconnection Reliability System
Authors: Levy Andrew , Manhaeve Hans , McBain Ed
Published: October 2015

In this paper we present a new methodology that addresses the quality and reliability problems of applications that deploy “2.5D” packaging technology for integrated circuits (ICs). This technology employs through-silicon vias (TSVs), enabling greatly increased circuit density, performance, and functionality for a given volume. The 2.5D ICs require the use of an interposer to route signals between the chips and the package substrate. While this packaging solution has some distinct advantages over other packaging/mounting technologies, there are disadvantages as well. Qualifying and testing such connections is very difficult and expensive, and techniques for anticipating failure do not currently exist. Therefore, confidence in the reliability of 2.5D IC interconnects is lacking. Systems that use them may require a high level of preventive maintenance whenever possible, or such packaging may simply be avoided when such maintenance is not possible or practical.

The paper outlines an approach that combines embedded digital and analog measurement instruments that are capable of detecting and identifying opens and shorts in 2.5D IC TSV stacks. The monitors reside on the silicon interposer. This system is the first to address the difficult issue of 2.5D IC package interconnect integrity after assembly is done and when the related devices are deployed in larger systems. The innovation will improve reliability of TSV-based packaging by detecting and identifying faulty connections at package test during the manufacturing process. It also provides prognostic monitoring so that interconnect-related operational faults can be detected before actual system failure occurs after the packaged component is deployed in the field.
Micro-tube insertion into aluminum pads: Simulation and experimental validations
Authors: Bedoin Alexis , de Brugière B. Goubault , Marion F. , Berger F. , Fendler M. , Volpert M. , Ribot H.
Published: October 2015

Following the trend towards more densely integrated electronic devices; new flip-chip technologies are developed to address very fine pitch interconnection. Among them, it was demonstrated that the hybridization technique based on insertion of gold coated micro-tubes into aluminum pads (Al-0.5Cu) has the capability for a 10 μm bonding pitch and the advantage of a room temperature assembly process [1, 2] .

In this study, we propose to thoroughly study the electro-mechanical behavior of the micro-tube inserted into an aluminum pad.

A finite element model has been used to simulate the micro-tube insertion into an aluminum pad. This numerical model deals with critical issues such as contacts, large deformations and remeshing. It was used to predict the main process parameter: the minimum load required for the micro-tube insertion into the pad. On one hand, the load should be high enough to fracture the native alumina layer during insertion and to achieve an appropriate electrical contact. On the other hand it must be low enough to prevent over-stress and deterioration of the tube and the underneath technology.

The predicted load is then used in an experimental setting where the single micro-tube insertion into pads is conducted using a nano-indenter. The modified nano-indenter allows in-situ electrical measurements. The simulated load is confirmed and SEM inspections of the deformed pad are in accordance with the predicted shape. This load is shown to be influenced by the loading rate and the alignment between the micro-tubes and pads. A full understanding of the electromechanical insertion behavior is achieved thanks to these experimental setup and the simulation.

These results are generalized to assemble an array of over 100 000 micro-tubes into an array of pads using a pick and place equipment. The D2W bonding process has been optimized in order to reach a 100% yield of interconnection and a high mechanical strength. Electrical measurements show that these assemblies exhibit an electrical resistance lower than 300mΩ.
Direct Palladium-Gold on copper as a Surface Finish for next generation Packages.
Authors: Ozkok Mustafa , Lamprecht Sven , Ramos Gustavo , Kilian Arnd
Published: October 2015

A new surface finish is entering the market. The need for this finish comes from needs for new assembly technologies like copper wire bonding or chip assembly by thermo compression bond. Furthermore Nickel an element, which is the base of many surface finishes like ENIG or ENEPIG, is more and more regarded as an unpleasant element as of several disadvantages, such as for high frequency applications, for environmental issues or for fine line applications were a 5 μm Ni Layer is just simply too thick.

All these concerns supporting the introduction of a new surface finish, a direct EP and direct EPAG finish. In particular, its suitability for copper wire bonding and its fine line capability makes it very attractive from a cost standpoint of view. In addition, the mentioned technological handicaps of nickel based finishes could be solved by applying a revolutionary surface finish – A Direct Palladium with an optional gold layer.

The direct deposition of palladium on copper with an optional gold layer does have further technological, environmental and economical advantages. The suggested paper will describe and discuss the advantages and chances using this new surface finish, as well as demonstrate soldering on various wire bond tests on the Direct EP and EPAG finishes as well as soldering test results.
Copper, Nickel, and Lead-Free Solder Electroplating Solutions for Pillar and Micro-Pillar Capping Applications
Authors: Woertink Julia , Reddington Erik , Lee Inho , Qin Yi , Prange Jonathan , Montesinos Pedro Lopez , Lin Jui-Ching , Imanari Masaaki , Dong Jianwei , Tachikawa Wataru , Calvert Jeff
Published: October 2015

Control of height-uniformity, morphology, and interfacial properties is critical to achieving high-yield, high-reliability Copper Pillar and Copper Micro-Pillar capped structures for flip-chip and 3D Packaging applications. The plating chemistries selected for electrolytic copper, barrier layer, and lead-free solder deposition significantly affect these properties. A range of copper plating chemistries is evaluated for plating performance and deposit properties for 20um diameter and 75um diameter pillar plating. Height uniformity, pillar shape, surface morphology, and physical properties are compared. These electroplated copper pillars are then evaluated for compatibility with barrier layers and lead-free solder capping. Post-reflow IMC formation, interfacial properties, and micro-voiding phenomena are studied and the effect of the plating chemistry on the overall compatibility of layers in stacked structures is discussed.
Thermal Analysis of xFD DRAM Packages Through Simulation and Experimental Validation
Authors: Zhang Ron , Tseng John , Shaba Hala , Chau Ellis , Zohni Wael , Mirkarimi Laura
Published: October 2015

The design optimization for thermal management of systems relies heavily on accurate thermal models of the individual components. Invensas is developing new packaging concepts that provide enhanced and reliable performance electrically, thermally and mechanically. These development efforts use predictive finite element analysis to drive the optimization of package design for improved thermo-mechanical strain and thermal management. Therefore, it is important to validate such models through rigorous experimental thermal measurements.

This work represents the 2nd half of our effort in the area of multi-die face-down stack thermal analysis. As was presented last year for the dual die face-down stack analysis, we will present details of our quad die face-down package design, assembly and the thermal test protocols. We will outline our methodologies for measuring thermal performance and achieving tight tolerances in the experimental apparatus as well as guidelines for making appropriate assumptions for associated simulations. We examined JEDEC standard test conditions for natural convection and forced air flow at various air velocities. Comparing values obtained from experimental measurements with simulation data showed results that were within 10% margin in many cases. We will discuss in detail the important calibration protocol and considerations required in the experimental test area for enhanced precision.
Development of Embedded High Power Electronics Modules for Automotive Applications
Authors: Boettcher Lars , Karaszkiewicz S. , Manessis D. , Ostmann A.
Published: October 2015

The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Conventionally IGBTs and diodes are soldered to DCB (Direct Copper Bond) ceramics substrates and their top contacts are connected by heavy Al wire bonds. These ceramic modules are vacuum soldered to water-cooled base plates. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to further improve the thermal management by double-sided cooling and to reduce the thickness of the module.

In the recently started “HI-LEVEL” (Integration of Power Electronics in in High Current PCBs for Electric Vehicle Application) project, partners from automotive, automotive supplier, material supplier, PCB manufacturer and research teamed up to develop the technology, components and materials to realize high power modules.

The following topics of the development will be addressed in detail in this paper:Assemble of power dies (IGBT and diode) using new sinter die attach materials:The deployment of new no pressure, low temperature sinter paste for the assembly of the power dies is a mayor development goal. Here the development of a reliable process to realize a defect free bonding of large IGBT dies (up to 10x14mm2) is essentially. These pastes are applied by stencil printing or dispensing and the sintering will take place after die placement at temperatures of around 200 °C.Thick copper substrate technology:To handle the high switching current, suitable copper tracks in the PCB are required. The realization of such thick copper lines (up to 1mm thickness) requires advanced processing, compared to conventional multilayer PCB production.

In this paper the essential development steps towards a 10 kW inverter module with embedded components will be described. The process steps and reliability investigations of the different interconnect levels will be described in detail.
2.5D and 3D Integration Technology Update
Authors: Patti Robert
Published: October 2015

This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology including new wafer to wafer integration of InP and GaAs with CMOS devices and new work in bonded die to wafer assembly with sub 25um pitch. A manufacturing perspective of the evolving customer requirements and the unique challenges in testing these highly complex devices will be discussed.
Non-Conductive Film (NCF) with No Voiding and High Reliability
Authors: Anzures Edgardo , Choubey Anupam , Dhoble Avin , Fleming David , Barr Robert , Calvert Jeffrey , Oh Joon-Seok
Published: October 2015

There has been significant activity in recent years to develop Non-Conductive Films (NCF), which are also known as Pre-Applied Underfills (PAUF) and Wafer Level Underfills (WLUF), for use in the High Volume Manufacturing (HVM) of 2.5D and 3D packages. They are essentially underfills in laminate film form. Like other underfills, they ensure the integrity of the electrical interconnects in a package by mitigating stress, acting as an adhesive to bind the package together, and encapsulating to protect against moisture and other unwanted materials that can compromise electrical connectivity. NCF's are seen as an alternative to the more traditional capillary underfills, especially in devices with finer pitch, smaller gap, and larger size. Since the NCF can be applied to multiple devices simultaneously, this new technology has an advantage over capillary underfills in HVM. These film-type underfills can be applied to wafers (PAUF, WLUF, NCF) or substrates (PAUF, NCF). Two key attributes of any underfill are no voiding and high reliability. No voiding is an essential requirement for high reliability. Voiding in NCF materials can result from the lamination and thermocompression bonding (TCB) processes. Voiding under the die can manifest from a variety of causes, including some of the following: (1) volatilization of materials in the coating, (2) dimensional changes within the coating during processing, (3) poor fundamental conformation to surface topography during film lamination and (4) ineffective air release during TCB due to un-optimized material flow. Unwanted issues such as reduced adhesion, solder shorting, increased moisture uptake and reduced stress mitigation can result from the presence of voids in the NCF. Pressure cure after joining is one method for eliminating voids in NCF materials. An earlier version of the NCF discussed in this study required pressure to eliminate voids after TCB. Pressure curing, however, adds process steps and is not accepted by all manufacturers. An improved NCF formulation and bonding process has resulted in a void-free NCF that does not require pressure cure for void elimination. This improved version not only addresses voiding after bonding, but also it has been proven to be very reliable in the presence of extreme temperatures, high humidity and temperature cycling. No one test is sufficient to adequately determine the long term reliability of NCF materials so a battery of tests was run to conduct a comprehensive assessment. The reliability evaluation results demonstrate that this newly developed NCF exhibits not only no voiding after TCB without the need for pressure cure, but also high reliability to various forms of temperature and humidity stress testing.
Next Generation High Power Electronic Modules Based on Embedded Power Semiconductors
Authors: Böttcher Lars , Karaszkiewicz S. , Manessis D. , Hoene Eckart , Ostmann A.
Published: October 2015

The spectrum of conventional power electronics packaging reaches from SMD packages for power chips to large power modules. In most of these packages the power semiconductors are connected by bond wires, resulting in large resistances and parasitic inductances. Power chip packages have to carry semiconductors with increasing current densities. Conventional wire bonds are limiting their performance. Today's power modules are based on DCB (Direct Copper bonded) ceramic substrates. IGBT switches are mounted onto the ceramic and their top side contacts are connected by thick Al wires. This allows one wiring layer only and makes an integration of driver chips very difficult. Additionally bond wires result in a high stray inductance which limits the switching frequency. Especially for the use of ultra-fast switching semiconductors, like SiC and GaN, it is very difficult to realize low inductive packages.

The embedding of chips offers a solution for many of the problems in power chip packages and power modules. While chip embedding was an academic exercise a decade ago, it is now an industrial solution. A huge advantage of packaging using PCB technology is the cost-effective processing on large panel. Furthermore embedded packages and modules allow either double-side cooling or 3D assembly of components like capacitors, gate drivers or controllers.

The advanced results of research projects will be discussed in the paper. An ultra-low inductance power module with SiC switches at 20 A / 600 V has been realized and characterized. The DC link inductance of the module was 0,8 nH only. These results sparked a huge interest in currently starting follow up projects creating package for fast switches.

In a further project power modules for automotive power inverters for motor control are under development. As a project demonstrator, a 10 kW module with IGBTs and diodes at 400 V / 500 A, was manufactured. This demonstrator is based on high power PCB technology and was fully characterized; the results will be presented in detail.

Recently started research projects will face the challenges of MW solar inverters at 1000 A and 1000 V, using SiC semiconductors as switches. First concepts will be presented as an outlook.
Embedding Active and Passive Devices in Medical Electronics
Authors: Dzarnoski John , Johansson Susie
Published: October 2015

Efforts to increase the packaging efficiency of microelectronic systems have been extensive and continuous over the past few decades. Evidence of this can be seen even before the expansion of the space program by the United States in 1961 and the race to the moon; one of the first settings where size was truly limited and miniaturization of electronics was a necessity. In the 1950's the world saw its first major size reduction of electronic component with the phase out of the vacuum tube in favor of the transistor. The transistor saw its first major commercial use in 1952 via hybrid vacuum tube transistor technology. While many industries benefitted from the shift, in 1954 the hearing aid industry specifically experienced major improvements owing to the implementation of transistors, becoming smaller, requiring less power and having better functionality. The first 4-transistor AM radio product followed shortly thereafter. Much of today's effort since 1978 has been driven by the telecommunications industry that has succeeded in reducing cell phone size while simultaneously increasing functionality.

Just as in the 1950's, hearing aid technology continues to be at the forefront when it comes to miniaturization. The hearing aid business has always had the need to use extremely small electronic packaging. The first completely in the canal (CIC) hearing aids were produced in 1993 and required all electronic components to be small enough that they fit entirely inside the ear canal. The introduction of wireless systems into hearing aids has sharply increased component count. Due to the size and shape of a multitude of types of hearing aids, flexible circuits need to be folded and bent to fit inside hearing aid cases, with essentially all available space being used. More powerful processors and more memory are enabling sophisticated algorithms that are able to greatly improve sound quality. There is also a strong market desire to add more features to hearing products while at the same time making them smaller and less visible. The latest hearing aids have succeeded in the later demand, constructed so small they are not visible and consequently are called invisible in the canal (IIC). In order to continue meeting the markets want for smaller and more features, a new packaging method needed to be developed. One such option is embedded die packaging.

This paper will examine the use of embedded die packaging (or chip-in-flex) to drive significant further size reduction in custom and standard hearing instruments over what can be achieved using chip-on-flex or traditional ceramic hybrid based technologies. The historical drivers, available circuit board technologies, use of integrated passive devices, performance improvement, size reduction, device reliability, changes in supply chain, impact on wafer test, impact on device test, and challenges of working with wafers instead of die will be discussed.
A Flexible Manufacturing Method for Wafer Level Packages
Authors: Strothmann Tom , Pricolo Damien , Yoon Seung Wook , Lin Yaojian
Published: October 2015

The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the use of capital when the depreciation term is longer than the anticipated life cycle of the product.

Conventional methods of manufacturing wafer level packages require the use of equipment specifically sized to a given silicon wafer diameter although there is no technical requirement to maintain the round silicon format. The conventional method has been beneficial since it leveraged equipment and processes developed for the IC industry, however the equipment is very expensive for larger wafer diameters and the fine geometries required in advanced node IC products are not required for wafer level packaging. The problem is serious for 200mm and 300mm wafer bump lines, however the capital equipment cost for a future 450mm bumping line may well be prohibitive for wafer level packaging.

A new manufacturing method has been developed to produce a wafer level package that severs the link between wafer diameter and wafer level packaging methods. The new manufacturing method is wafer size agnostic, so one manufacturing module can produce fan-in, fan-out, and 3D fan-out products regardless of the incoming wafer size. The same bill of materials, manufacturing methods and manufacturing location can produce wafer level packages from any size silicon wafer. In this method the wafer is diced prior to processing and then the die are recombined into a uniform panel size. Once recombined into a panel format, the product is processed with conventional wafer level packing techniques, including dielectric deposition, metal plating and solder ball drop. Since the manufacturing module is wafer size agnostic, there is no risk of capital for investment in the manufacturing infrastructure. A change in loading between 200mm, 300mm, and 450mm wafers does not adversely affect the utilization of the manufacturing module. The process also enables new advanced wafer level packages otherwise unattainable with conventional manufacturing methods. This presentation will describe the new manufacturing module approach and the results of process characterization for products produced in the module.
Integrated Localized Cooling using Piezoelectrically-Driven Synthetic Jets
Authors: Kranz Michael , Hudson Tracy , Whitley Michael , English Brian
Published: October 2015

RF communication and radar systems present an extreme thermal management challenge. These systems are comprised of tightly packaged and high wattage components requiring a controlled temperature to meet performance and reliability parameters. In these systems, there is little space available for air flow or other traditional cooling methods. In addition, the heat generating components are typically microscale semiconductor devices fabricated on integrated circuit substrates buried deep within the system. Localized cooling using integrated microsystems may provide a solution to these thermal management issues.

One approach being pursued to meet this thermal challenge is the integration of miniature synthetic air jets near the heat generating components. These synthetic jets are generated using oscillating piezoelectric actuators that force air through a small nozzle at high flow rates and in very close proximity to the heat generating component. The resulting jets provide vorticity within the fluid, leading to enhanced mixing with the surrounding lower temperature fluid, and a subsequent increase in the heat transfer coefficient. The US Army AMRDEC is developing and operating microactuator test beds to mature these concepts and implement practical integration solutions. This investigation has modeled potential actuators and jets in using computational fluid dynamics and heat transfer codes, verified the results of these models with the prototype test beds, and demonstrated high-levels of localized cooling. This paper will present actuator designs, thermal modeling results, and actual cooling results using a high-stroke piezoelectric actuator as the drive element.
MEMS- Based Cryogenic Coolers - Micro Joule - Thomson Cryogenic Coolers
Authors: Wang Yunda , Lee YC
Published: October 2015

To be provided
Sapphire Surface Protection During Sapphire Micromachining and Through-Sapphire Via Formation for Device Densification, Backside Interconnect and Chip Stacking
Authors: Ahmad Syed Sajid , Haring Fred , Strommen Greg , Mattson Kevin , Reinholz Aaron
Published: October 2015

Through-vias in sapphire can aid in silicon-on-sapphire device densification and chip stacking. They can also help connect with electronic structures made on the back of the sapphire. Through-vias in sapphire can be formed using an appropriate laser. During the formation of through-vias in sapphire using a laser and during laser micromachining of sapphire, debris and heat affected zones are produced. Various methods were evaluated to protect the circuitry on the sapphire from damage by debris and heat produced during laser application. Results of the evaluations are outlined and an effective method to help remove debris and reduce the effect of heat is described.
Metrology and Inspection for New Interconnects in Advanced Packaging
Authors: Dudley Russ , Wilson Matt , Roy Rajiv
Published: October 2015

Interconnects for Advanced Packaging are getting smaller and come in a variety of sizes, shapes, and materials. The height, diameter, shape, and the absence/presence of these interconnects are critical and must be monitored across the device and wafer to ensure reliable connections during the bonding process.

Solder bump technologies have been utilized in the past, but cannot support the high density interconnects that are required. New interconnect technologies being utilized for wafer level packaging (WLP) and through silicon via (TSV) packages include copper pillar posts and TSV posts. These new interconnect technologies provide higher density, improved reliability, and better electrical performance.

This paper will highlight the critical metrology and inspection requirements for these new interconnect technologies and demonstrate the capability of a single platform to support these new interconnects for high volume manufacturing (HVM).

The single platform includes 3D metrology performed using a proprietary interferometric sensor technology that can measure the height of the post and the thickness of the surrounding polymer at the same time to optimize the measurement performance and system throughput. The platform also provides the ability to inspect for surface defects, irregular posts, missing posts, and a variety of other inspections typically performed on bumped wafers or substrates.

Both the metrology and inspection results from the single platform are output to a proprietary analysis package using industry standard Rudolph Result Files (RRF). The analysis will demonstrate the value these results provide for process control and the defect analysis, ultimately leading to improved yields and equipment utilization.