Electrical stress of graphene field effect transistor under different bias voltages Reliability studies
Authors: Wang SongWen  , Guo HongXia  , Ma Teng  , Lei ZhiFeng  , Ma WuYing  , Zhong XiangLi  , Zhang Hong  , Lu XiaoJie  , Li JiFang  , Fang JunLin  , Zeng TianXiang  ,   1 HSchool of Materials Science and Engineering, Xiangtan University, Xiangtan 411105, China;,   2 State Key Laboratory of Science and Technology on Reliability Physics and Application of Electronic Component, China Electronic Product Reliability and Environmental Research Institute, Guangzhou 511300, China;,   3 Northwest Institute of Nuclear Technology, Xi'an 710024, China
Published: November 2024

In this paper, graphene field effect transistors (GFET) with the top-gate structure are taken as the research object. Conducted electrical stress reliability studies under different bias voltage conditions. The electrical pressure conditions are Gate Electrical Stress (<i>V<sub>G</sub></i>=-10V, <i>V<sub>D</sub></i>=0V, <i>V<sub>S</sub></i>=0V), drain electric stress (<i>V<sub>G</sub></i>=0V, <i>V<sub>D</sub></i>=-10V, <i>V<sub>S</sub></i>=0V), and Electrical stresses applied simultaneously by gate and drain voltages (<i>V<sub>G</sub></i>=-10V, <i>V<sub>D</sub></i>= -10V, <i>V<sub>S</sub></i>=0V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage <i>V<sub>Dirac</sub></i> degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressure conditions, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions affect the drift direction and degradation of <i>V<sub>Dirac</sub></i> differently: Gate electrical stress and drain electrical stress cause <i>V<sub>Dirac</sub></i> drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate and drain voltages leading to <i>V<sub>Dirac</sub></i> degradation of GFETs. An analysis of the causes suggests that different electrical stress conditions produce different electric field directions in the device, which can affect the carrier concentration and direction of movement. Electrons and holes in the channel are induced to tunnel into the oxide layer and are captured by trap charge in the oxide layer and at the graphene\oxide interface, forming oxide trap charges and interface trap charges. This is the main reason for the reduced carrier mobility of GFETs. Different electric field directions under different electric stress conditions produce positively charged and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of <i>V<sub>Dirac</sub></i>drift in GFETs. When both trap charges are present at the same time, they have a canceling effect on the amount of <i>V<sub>Dirac</sub></i>drift of the GFETs. Finally, the paper combines TCAD simulation, further revealing the simulation model of the impact of electrical stress induced trap charge on the <i>V<sub>Dirac</sub></i>generation of GFETs. The result demonstrates that differences in the type of trap charge banding have different degradation effects on the <i>V<sub>Dirac</sub></i> of GFETs. The related research provides data and theoretical support for the practical application of graphene devices.