Chip to Wafer Hybrid Bonding Development for High Volume Manufacturing
Authors: Abdilla Jonathan 
Published: February 2024

The adoption of 3D architectures in advanced packaging between chips is driven by high performance computing and artificial intelligence requirements [1,2]. Hybrid bonding (HB) is essential for this transition, as it offers high I/O connectivity with fine pitch (<10µm), increases system level bandwidth and speed, and improves thermal budget. Chip-to-Wafer (C2W) HB further offers the benefit of using known-good-die to achieve higher yield, especially for heterogeneous integration. This paper describes the necessary conditions to achieve a successful C2W HB suitable for high volume manufacturing (HVM) production.

HB can be achieved in a 2-step process; firstly, by leveraging on the initial forces of surface interaction at atomic proximity of dielectric-dielectric interface to form the “tacking,” which is the initiation of the bonding, and finally, following up with a fusion process by annealing at an elevated temperature (100°C-400°C) to form both stronger dielectric-dielectric covalent bonds with the release of excessive water (H2O) molecules, as well as metal-metal diffusion which will enable the electrical connection. A successful bond can be achieved with careful surface engineering of the dielectric [3], typically with dielectric surface roughness values of <0.4nm. Figure 1 shows an optimized result, demonstrating C2W HB with Cu-Cu interdiffusion.

Die-to-die (D2D) or C2W HB has many challenges. Removal of barrier spikes/protrusions in the nm-scale that is not critical in wafer-to-wafer HB is paramount in C2W HB, likely attributed to the reduced volume/weight and no physical pressure applied after the die-tacking process. A chemical-mechanical polishing (CMP) is a critical step to create necessary pre-conditions for HB and must be carefully and meticulously optimized.

Prior to bonding, a proper activation step is required on the dielectric surfaces. The delay between activation and bonding can weaken the initial bonds. Q-time control and surface cleanliness are critical for consistent performance and high bonding yield. A repeatable process performance with low contact angles, no degradation of dielectric roughness, and Cu dishing performance is imperative. Results will show that such milestones were achieved with the state-of-the-art systems at the HB Centre of Excellence.

Cleanliness is undoubtedly a salient criterion for successful C2W HB. Contaminants such as particles and volatile organic compounds can be detrimental to bonding strength and metal-metal contact resistance. Unlike other advanced packaging methods such as TCB, there is no gap between the die and substrate, nor is there solder or glue that can help to mitigate the impact of any particles present. Since the bonding occurs between flat dielectric to dielectric surfaces, any particle entrapped will result in big voids, rendering the device useless. As such, this paper will also outline the cleanliness levels achieved in the system. Equivalent to this criterion is also the mechanics behind the bonding mechanism itself. At the core of an HB, the process is the bond front propagation, which, if not controlled, can lead to voids, die damage, and loss of accuracy, amongst other things. As such, BESI has developed a series of tools allowing controlled die shaping to initiate bonding at specific locations as well as to control the die release. Die placement accuracy is typically measured using IR equipment. This paper will show and analyze the accuracy results of actual C2W HB dies. This paper will also discuss additional data from post-bond confocal scanning acoustic microscopy (cSAM), contact resistance, and daisy-chain continuity E-test.