bluuebunny/crossref_metadata_2025 huggingface dataset:
Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool
Authors: Searls Damion T. , Don Anura , Dy Emilie , Goyal Deepak
Published: December 2020

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).
Combining FIB Sequential Cross-Sectioning with TEM for Small Defect Analysis in SRAM Array
Authors: Wang Nathan , Fang Rei
Published: December 2020

To find defects and their root cause in semiconductor devices has become more and more difficult as chip size dramatically drops. A novel method combining FIB sequential cross-sectioning and TEM is described in this paper. This combination has provided a powerful tool for defect mechanism analysis. FIB slicing through a failed cell can be controlled to a precision of 0.1 micron. Passive voltage contrast imaging with FIB enhances defect detection. After a defect is found, in-situ TEM sample is prepared with FIB milling. By putting together the series FIB images along side with the TEM images and its associated high resolution EDS data, the detailed defect formation mechanism was discovered and feedback to process engineering for process improvement.
Failure Analysis of Stacked-Chip Scale Package
Authors: Flores Christopher C.
Published: December 2020

Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest. Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (FI), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concern shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be performed further. This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure. Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness.
Advanced Analytical Chemistry Techniques Enable Rapid, Cheap and Concise Electronic Failure Analysis
Authors: Mazurkiewicz Paul
Published: December 2020

This article introduces several analytical chemistry techniques that are extremely useful in the electronics failure analysis (FA) laboratory, but are not normally found in FA laboratories. It presents the techniques in simple language and makes a case for the inclusion of chemists in the rapidly evolving and ever-shrinking world of microelectronic failure analysis. The article discusses the following techniques in terms of their applications, advantages, and operating principles: gel permeation chromatography, gas chromatography-mass spectrometry, Fourier transform-infrared spectroscopy, and electron spectroscopy for chemical analysis (ESCA). As we move into the world of nanotechnology, these techniques will become key in analyzing failures that cannot be visualized using traditional FA methods.
A Novel Electrical Test by C-AFM to Differentiate Gate-to-S/D Gate Oxide Short From Non-Gate Oxide Short Defect in Real Products
Authors: Lin Cheng-Piao , Wu Cheng-Hsu , Ting Cheng-Chun
Published: December 2020

A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.
A Simple FIB Method for Constructing Electrically Isolated Microprobe Pads for the Electrical Analysis of Failing 0.12μm Technology SRAM Bit Cells
Authors: Mulder Randal
Published: December 2020

This paper provides failure analysis engineers a simple method for constructing probe pads on failing 0.12um SRAM bit cells using the FEI 820 Focused Ion Beam (FIB) tool. This method allows for the easy location of the failing bit cell, results in good electrical isolation, and only takes a minimal amount of FIB time (2 hours for 6 pads). The method is effective for all technologies 0.12um or greater with a high success rate once the analyst is proficient in its use. Once probe pads have been constructed, it is then relatively easy for an analyst to perform electrical analysis to identify the defect type and location causing the bit cell failure before the physical analysis is performed.
On-Die Parametric Analysis of SRAM
Authors: Mauck Benjamin M. , Ravichandran Vishnumohan , Mughal Usman Azeez
Published: December 2020

Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. While regular raster and special cache patterns (i.e. weak-write test mode) detect many stuck-at faults, a parametric analysis is needed to identify which defect mechanism is the cause of a cache failure. Pico-probing is the most common method of parametric analysis on SRAM cells, but is becoming increasingly difficult on smaller geometries. These curves can also be taken non-destructively by muxing any bitline (BL) and bitline_bar (BL#) of an internal cache to an I/O pin and sweeping these pins with an external PMU (a test mode known as low yield analysis, or LYA). Unfortunately, a growing amount of leakage on each new process is distorting these LYA testmode I-V curves, making it increasingly difficult to find and differentiate defects. The goal of this paper is to discuss the simulation and silicon results of a concept On-Die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.
The Root of All “IVA”—A Quantitative Analysis of LSIM Bias/Detection Systems
Authors: Levin T. M.
Published: December 2020

The transfer functions of the bias/detection circuits used in various laser signal injection microscopy (LSIM) techniques, especially for those using constant current bias/detection schemes, are largely unknown. This article provides both qualitative and quantitative measures of various LSIM bias/detection schemes to develop a more complete understanding of the varying measurement systems. The authors have measured the characteristics of a variety of bias/detection circuits in ways that are similar to the characterization of a linear integrated circuit. They have concentrated on examining the frequency response, pulse response, and noise levels. It was found that the LSIM bias/detection systems have widely varying characteristics which, in turn will affect how they can be optimized. Furthermore, the relationship between the frequency and noise characteristics of the bias/detection systems and the input signal that is to be detected point to differing ways in which the systems can be modified for improved performance.
Logical-to-Physical Device Navigation using Place-and-Route Data as an Alternative to LVS
Authors: Nicholson Roger
Published: December 2020

Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming Layout-versus-Schematic (LVS) based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.
Development of a Circuit Edit Process Scalable in Dimension and Material
Authors: Makarov Vladimir V. , Antoniou Nicholas
Published: December 2020

The ability to edit a circuit in silicon quickly and confidently is extremely valuable as it permits verification of changes or fixes without the need to generate new reticles and fabricate new silicon. However, dramatic changes in the material used in IC’s combined with the downward scaling of dimensions required the development of a scalable process not only in three dimensions but also in material. Details of this process and results are presented in this paper.
A Novel Method to Inspect Deep Trench Capacitor Planar Profiles in DRAM
Authors: Lue J. L. , Huang A. , Wang T.
Published: December 2020

This paper presents a novel method to inspect deep trench (DT) planar profiles at any particular depths using the mechanical polishing method instead of the Focused Ion Beam (FIB) milling method. The sample is polished at a small beveled angle and then inspected in the Scanning Electron Microscope (SEM). This method creates a large area for the inspection of DT profiles. It is accurate and fast in providing the result on process evaluation and failure analysis. Since the FIB is not needed, it is also simple and cost effective.
Microelectronic Packages (FC with Ceramic Substrates) Solder Removal Method for Failure Analysis
Authors: Shih T. I. , Chen Tung Hung
Published: December 2020

In order to do the failure analysis on flip chip connected with ceramic substrate, solder bump should be completely removed from chip surface. The die soldered on ceramic substrate of flip chip package is likely damaged during the removing process for the high etching and abrasion resistance of ceramic substrate as well as the poor uniformity of mechanical polish. In this paper, a thermal method for the decapsulation of flip chip package is developed, which included heat sink removal, ceramic substrate and solder bump separation, and solder residue clean out from the chip surface. In the last step, three temperature levels of H2N2O6 – H2O (fuming Nitric acid) were selected for the removal of eutectic, high-lead and lead free solders, respectively.
Note on the Use of Principal Component Analysis (PCA) and Clustering for the Analysis of Wafer Level ATPG data
Authors: Ramanujachar Kartik , Draksharam Satish
Published: December 2020

This article explores the use of principal component analysis (PCA) and hierarchical clustering in the analysis of wafer level automatic test pattern generation (ATPG) failure data. The principle of commonality is extended by utilizing hierarchical clustering to collect die that are more similar to one another in their manner of failure than to others. Similarity is established by PCA of the patterns that the die in a wafer fail. Results demonstrated that PCA analysis and clustering are useful tools for dimensionality reduction and commonality analysis of wafer level ATPG data. The utility of PCA analysis and clustering in the extraction of die for physical failure analysis is also illustrated.
130nm Backend Reliability Failures—Analysis to Corrective Action
Authors: Garteiz Gil , Zylberman Amir
Published: December 2020

Tower successfully completed a product qualification of its 130nm copper process this year. The key to this achievement was finding and eliminating a dominant failure mechanism, which appeared during HTOL stress. This paper will cover the failure analysis, in-line problem identification, and corrective actions taken that eventually lead to successful product qualification.
Analysis of Delta Iddq Soft Fails on Pass Chips
Authors: Österreicher I. , Eckl S. , Tippelt B. , Döring S. , Prang R. , Werner W.
Published: December 2020

Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.
Challenges in Evaluating Thickness, Phase, and Strain in Semiconductor Devices Using High Resolution Transmission Electron Microscopy
Authors: Rai Raghaw , Conner James , Murphy Sharon , Subramanian Swaminathan
Published: December 2020

The aggressive scaling of metal oxide semiconductor field effect transistor (MOSFET) device features, including gate dielectrics, silicides, and strained Si channels, presents unique metrology and characterization challenges to control electrical properties such as reliability and leakage current. This paper describes challenges faced in measuring the thickness of thin gate oxides and interfacial layers found in high-K gate dielectrics, determining Ni silicide phase in devices, and characterizing strain in MOSFETs with SiGe stressors. From case studies, it has been observed that thin layers (gate oxide, high-K film thickness, and interfacial layer) can be measured using high-resolution transmission electron microscopy (HRTEM) with good accuracy but there are some challenges in the form of sample thickness, damage-free samples, and precise sectioning of the sample for site-specific specimens. Complementary information based on HRTEM, annular dark field, and image simulation should be used to check the accuracy of thin gate dielectric measurements.
Vanishing TiN ARC Coating as an Indicator of EOS in Aluminum Top Metal Lines
Authors: Barbieri Thomas J. , Wang James , Kottke Mike , Theodore David , Wetz Richard
Published: December 2020

Multiple parts failed during a 96 hour HAST (highly accelerated stress test) run. Electrical failure occurred on several pins stressed at 48V during the run. Visual inspection identified possible corrosion damage occurring on a top layer aluminum metal line linked to the failed pins. Additionally, significant lengths of this line and metallization at six other sites appeared white and reflective when viewed through an optical microscope. The device technology utilized a TiN ARC. Aluminum metal with a TiN ARC has a dull, amber color when viewed through an optical light microscope, as opposed to bare aluminum, which appears white and shiny. The initial assumption was that the passivation had lifted off during mold compound removal, along with the top TiN ARC layer at these seven locations. SEM inspection found that final passivation film was still intact over these shiny Al lines, but it was cracked extensively. Neighboring Al lines did not show cracked passivation. A hypothesis was generated that suggested that the TiN ARC was not removed, but rather was altered in some way so as to change its optical appearance. The change in the TiN was believed to be due to a combination of factors that resulted from electrical overstressing of the lines during HAST. A series of experiments utilizing FIB cross-sections, Auger mapping, Auger depth profiling, TEM inspection and EDS were used to show that the TiN ARC layer was still present on the affected lines but had been oxidized. The conclusions drawn from this investigation can be used to rapidly determine the root cause of failure through signature analysis. Shiny Al metal lines are easy to see with optical microscopes and are therefore a useful failure analysis tool to identify electrically and mechanically overstressed lines and circuits.
Nanoprobing Application on Characterization of 6T-SRAM Single Bit Failures with Different Gox Breakdown Defect
Authors: Lin Cheng-Piao , Tang Chin-Hsin , Wu Cheng-Hsu , Ting Cheng-Chun
Published: December 2020

This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.
A New Approach for SRAM Soft Defect Root Cause Identification
Authors: Egger Peter , Müller Stefan , Stiftinger Martin
Published: December 2020

With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.
Laser Assisted Lock-In Phase & Spectral Analysis Techniques at Advanced IC Failure Analysis with Application to Jitter and Soft-Defects
Authors: Brillert Christof , Qian Zhongling , Burmer Christian
Published: December 2020

New developments concerning lock-in phase detection and spectral analysis techniques applied to accessible IC signals are introduced in detail. These techniques combine the thermal laser stimulation (TLS) with the high sensitivity of lock-in to phase variation or the selectable frequency detection in spectrum analyzer. The difference to normal lock-in techniques utilizing pulsed lasers is exemplary pointed out. Moreover the applications to phase related soft-defects and to a design related jitter problem are shown. The power of such techniques for direct mapping a signal path is shown. Further benefits of lock-in phase methodology and spectral analysis technique applied to 65 nm and 90 nm technology is presented and illustrated using different case studies.
Localization of Cu/Low-k Interconnect Reliability Defects by Pulsed Laser Induced Technique
Authors: Tan T.L. , Quah A.C.T. , Gan C.L. , Phang J.C.H. , Chua C.M. , Ng C.M. , Du A.-Y.
Published: December 2020

In this paper, the application of pulsed-TIVA for the localization of Cu/low-k interconnect reliability defects in comb test structures is described. Two types of subtle dielectric defects which are otherwise not detectable with conventional TIVA can be detected with pulsed-TIVA.
Silicon Dislocation Enhanced by Dynamic Voltage Stress
Authors: Lin Yu-Cheng , Chen Rock , Liang Sanan , Liao Scott , Niou Chorng , Chien W.T.Kary
Published: December 2020

In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.
Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) Localization of 32nm SOI SRAM Array Failure
Authors: Kane Terence , Tenney Michael P.
Published: December 2020

The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of FEOL defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET and SOI embedded dynamic ramdon access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy have also been highlighted [2]. This paper is intended to describe the advantages of NCVS to localize defects in specific MOSFET devices at CA level as well as to identify resistive BEOL via interconnections and FEOL defective high k metal gate structures without the attendant time consuming delayering steps employed with classical SCM methods. Localization of a FEOL defect in a discrete 32nm SOI MOSFET device in SRAM array causing a vertical pair cell failure signature will be discussed.
The Novel TEM Sample Preparation Approach for Targeted via with Barrier/Cu Seed Layer Inspection
Authors: Hsieh Wen-Fei , Tseng Shih-Hsiang , She Bo Min
Published: December 2020

In this study, an FIB-based cross section TEM sample preparation procedure for targeted via with barrier/Cu seed layer is introduced. The dual beam FIB with electron beam for target location and Ga ion beam for sample milling is the main tool for the targeted via with barrier/Cu seed layer inspection. With the help of the FIB operation and epoxy layer protection, ta cross section TEM sample at a targeted via with barrier/Cu seed layer could be made. Subsequent TEM inspection is used to verify the quality of the structure. This approach was used in the Cu process integration performance monitor. All these TEM results are very helpful in process development and yield improvement.
Failure Analysis Methodology on Systematic Defect in ADC_PLL Ring Pattern Due to Plasma De-Chuck Process
Authors: Boon Ang Ghim , Changqing Chen , Quah Alfred , Magdeliza  , Jony Indahwan , Tat Lee Mern , Zhu David , Ping Neo Soh
Published: December 2020

In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.
A Novel Junction Profiling Methodology
Authors: Nakai Tomokazu
Published: December 2020

Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation.
Dynamic Power Analysis under Laser Stimulation: A New Dynamic Laser Simulation Approach
Authors: Deyine A. , Perdu P. , Sanchez K. , Courrège J.C. , Lewis Dean
Published: December 2020

Dynamic Laser Stimulation (DLS) techniques proved to be very efficient in soft defect localization bringing a lot of information about the device internal behavior. We need to use external parameter measurements such as frequency, delay, voltage etc to perform these techniques. So they can't be used to study internal signal propagation problems in latched device since signals are resynchronized. We will show that we can use the power analysis coupled with DLS techniques set up to characterize soft defect when we don't have a direct access to monitored signal propagation such as in some transistor transition issues. Laser stimulation in addition of power analysis is used to decrypt security codes in security chip, but in failure analysis it is a new way to reach internal information in order to localize soft defects.
Two-Photon Absorption Laser Assisted Device Alteration Using 1340nm CW Laser: Critical Timing Fault Isolation & Localization for 32nm MPU and Beyond
Authors: Niu Baohua , Pardy Pat , Davis Joe , Ortega Mel , Eiles Travis
Published: December 2020

In this paper, we report on the first observation and study of two-photon absorption (TPA) based laser assisted device alteration (LADA) using a continuous-wave (CW) 1340nm laser. The study was conducted using LADA systems equipped with high numerical aperture (NA) liquid and solid immersion lens objectives on Intel’s 45 nm and 32 nm multiprocessor units (MPU) and test chips. The power densities achievable using these lenses are similar to those reported in the literature for TPA in silicon of CW 1455nm light [1]. We show that the induced photocurrent has a quadratic dependence on the input laser power, a key indicator of two-photon phenomenon. Our results imply that even when using 1340nm wavelength CW lasers, there is a potential for laser invasiveness with the high power densities achievable using high NA objectives. Laser induced damage of the DUT is also a possibility at these high power densities, particularly with the solid immersion lens (SIL). However, we show that the DUT damage threshold can be increased by reducing the DUT’s temperature. Finally, we present results demonstrating a >40% improvement in localization of critical timing faults using TPA based LADA, when compared to traditional 1064nm wavelength (single-photon absorption) LADA.
Advanced Laser Preparation of Microsystems for Further FIB Processing
Authors: Walter Juergen , Martens Stefan , Mack Walter
Published: December 2020

The trends towards 3D integration in microsystems technology and electronic packaging require that failure-analysis methods and target-preparation procedures are adapted to these emerging packaging technologies. The feasibility of laser-target preparation in microsystems is addressed in this paper, especially 3D integrated electronic devices. Various laser technologies were evaluated and the laser of choice was demonstrated to be appropriate for use with stacked packages. In addition, the laser preparation related Heat-Affected Zones (HAZs) were studied. The laser-energy absorption was determined by in situ heating-rate measurement, which enables precise prediction of HAZ extension by the use of Finite Element (FE) simulation. The advantage of this technique for removal rates compared to conventional techniques is discussed, as well as the combination of the excellent ablation rates of pulsed-laser ablation with the high accuracy of Focused Ion Beam (FIB) milling.
Quantitative Phase Shift Analysis for 3D Defect Localization Using Lock-in Thermography
Authors: Schmidt Christian , Altmann Frank
Published: December 2020

It was already demonstrated, that the method of Lock-in Thermography (LIT) enables 3D localization of thermal active defects, e.g. electrical shorts and resistive opens, on die level and within fully packaged single and multichip devices [1,2]. The depth of a defect can be derived from phase shift measurements of the defective compared to a reference device For a general approach of this method, thermal modeling is used and verified by experimental data to investigate the internal heat propagation under periodic stimulation in correlation to the LIT measuring process. [3]. A basic requirement for the successful application of the method is a precise and reproducible measurement of both the thermal material properties of each material layer and the phase shift between the internal heat excitation and thermal response measured by LIT. Significant influences from the material and measurement setup to the detected phase shift have to be identified and taken into account. However, to identify and distinguish the relevant influences measurements with defined internal heat sources are necessary which are presented in this paper. First, the relationship between geometrical thickness of a material layer and the resulting thermal parameters for both homogeneous and heterogeneous materials are measured and discussed. A new measurement setup generating a defined point heat source will be presented to calibrate the LIT system for quantitative phase shift measurements and to determine the phase shift to thickness parameters of single material layers. In addition the variation of the phase shift caused by the defect geometry and the defect environment will be investigated. Finally, a case study is presented comparing the experimental results to the obtained results from a real stacked die device.
Development of an Automated TDR System for Package Failure Analysis
Authors: Basilioa Christopher C. , Nguyenb Hieu Trong , Aguinaldoc Arlene , Arboledac Jan Paul , Angd Richmond , Anod Daniel , Paranald Paul , Magpantayd Armand
Published: December 2020

This paper describes the successful effort to develop the Time Domain Reflectometry (TDR) tool by automating the equipment process. The current challenges in the tool usage brought about by miniaturization in the package technology presented itself as an opportunity for the tool improvement. The authors were able to devise an automated TDR system which is ergonomically safe, yielded a significant through put time reduction and provide a consistent and accurate result. This comes at a lower cost in comparison to the current system available in the Virtual Factory (VF).
Methodology and Application of Backside Physical Failure Analysis
Authors: Lai Li-Lung , Chen HungLing , Gao Huimin
Published: December 2020

There are some advantages to performing physical failure analysis from the backside as opposed to normal frontside analysis. However, there are challenges to be overcome with regard to sample preparation and scanning electron microscopy. Thus, we introduce this unusual technique to overcome the barrier of difficulty. This technique can eventually lead to the development of a versatile methodology that can be used in actual applications for failure analysis.
Leaky Device Channel Anomaly Identification and Case Study by Nano-Probing Technique, Curve Fitting, and Model Analysis
Authors: Wang Wei-Chih , Sung Ching-Shan , Lin Ya-Hsiu , Chen Haw-Shan , Luo Jian-Shing
Published: December 2020

This paper demonstrated the use of curve fitting method on device transfer characteristic curve for device carrier mobility analysis and failure mechanism verification. In the content, a systematic device characterization was performed to identify device failure mode and failure site. Based on physical observations and electrical results, a device gate oxide boron penetration failure mechanism and an unexpected subtle p-type dopant at p-MOS device channel area was conjectured. However, this unexpected p-type dopant was successfully proved by subsequent carrier mobility analysis results, and the gate oxide boron penetration failure mechanism was accordingly verified.
Dual-Phase Interferometric Confocal Imaging for Electrical Signal Modulation Mapping in ICs
Authors: Yurt A. , Ramsay E. , Köklü F. H. , Stockbridge C. R. , Lu Y. , Ünlü M. S. , Goldberg B. B.
Published: December 2020

This paper demonstrates a differential dual-phase interferometric imaging method in which the reflected probe beam modulated weakly by the charge carriers is mixed separately with two reference beams with a known phase shift in between. Performing a balanced detection scheme on these two channels, the common-mode-noise associated with strong DC background and its noise can be significantly reduced. The performance of the interferometric technique is systematically compared with the conventional mapping method through investigating inverter chains on two test chips of 180nm bulk silicon technology and 32nm SOI technology. The future work will focus on adapting the method for GHz frequency regime and time-domain implementation of the method. The method will find applications in failure analysis and testing of advanced technology IC chips for which the high sensitivity in modulation mapping is required.
Energy-Filtered Imaging of Polysilicon Defects, Gate Dielectric and Silicon Nanocrystals Using Plasmon Energy-Loss Electrons
Authors: Subramanian Swaminathan , Ly Khiem , Chrastecky Tony
Published: December 2020

Transmission electron microscope based elemental analysis techniques utilize X-ray photons in EDS and inelastically scattered electrons or the energy-loss electrons in electron energy-loss spectroscopy and energy-filtered transmission electron microscopy (EFTEM). This paper discusses the applications of EFTEM to visualize polysilicon defects, gate dielectric and silicon nanocrystals using inelastically scattered low energy-loss electrons. It focuses on features that are primarily composed of silicon and silicon-oxide. Various benefits of using plasmon energy-loss electrons to image silicon nanocrystals layer in thin film storage device are also outlined. Even though this work has focused on low-loss imaging of features and defects in the front-end of the process based on silicon/silicon-oxide integrated circuits, these techniques can also be applied to technologies based on other materials by selecting appropriate plasmon peaks corresponding to those materials.
A Superconducting Nanowire Single-Photon Detector (SnSPD) System for Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuits
Authors: Stellari Franco , Weger Alan J. , Kim Seongwon , Maliuk Dzmitry , Song Peilin , Ainspan Herschel A. , Kwark Young , Baks Christian W. , Kindereit Ulrike , Anant Vikas , Lundquist Ted
Published: December 2020

In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.
Optical Nanoprobe Electrical Microscopy
Authors: Ippolito Stephen , Tenney Michael , Pendyala Sweta , Fischer Larry , Sylvestri John , Miles Darrell , Oldrey Rich , Villalobos Manuel , Dinkel Scott , Kane Terry , Redder Bruce , McGinnis Pat
Published: December 2020

This paper describes novel concepts in equipment and measurement techniques that integrate optical electrical microscopy and scanning probe microscopy (SPM) capabilities into a single tool under the umbrella of optical nanoprobe electrical (ONE) microscopy. Optical imaging ONE microscopy permits non-destructive measurement capability that was lost more than a decade ago, when the early metal levels became electrically inaccessible to microprobers. SPM imaging techniques do not have sensitivity to many types of defects, and nanoprobing all of the transistors in an area pinpointed by optical electrical microscopy is often impractical. Thus, in many cases, ONE microscopy capability will permit analytical success instead of failure.
Electrical Modeling of the Effect of Photoelectric Laser Fault Injection on Bulk CMOS Design
Authors: Hériveaux Laurent , Clédière Jessy , Anceau Stèphanie
Published: December 2020

Fault injection from infrared laser is a common practice among Information Technology Security Evaluation Facility (ITSEF) labs for testing CMOS circuits, and obtained effects are very versatile. However, from our point of view, the details of the phenomenona that occur in the integrated circuit have yet to be investigated. The common hypothesis is that the photoelectric current created during the light stimulation flows through the P-N junctions, and corrupts voltage outputs of the cells. In this paper, we consider the vertical parasitic bipolar junction transistors inherent to CMOS bulk devices. We show that these parasitic transistors contribute to the injected fault at a higher rate than just the P-N junctions of the OFF MOS side. There are two features of such results. First, the space charge region of the N-well / P-substrate junction is wide and will induce a stronger photocurrent. Second, this current will be amplified by the parasitic bipolar transistor and thus lead to more effects. These results are obtained by electrical simulations on a CMOS inverter. The size of the laser spot is taken into account via neighboring cells that are also illuminated. To induce an effect, small spot size needs a very high-power density, which is not always achievable. Increasing the illuminated area to inject more power is then a solution; simulations illustrate this point.
Gate Bridge to Drain Contact Characteristic in Floating Gate Memory
Authors: Chiang Pei Wei , Ling Yu Ting , Chen Bo Chih , Chang Hsiao Tien
Published: December 2020

Gate-to-drain contact short issue in floating gate memory has been studied. Two cases will be discussed, floating-gate to drain contact short, and control-gate to drain contact short, both caused by leakage bridge defect. The abnormal electrical device characteristic combined with modeling gives further insight into the failure mode. Nano-prober measurement results not only provide an evidence of short-contact issue but also measures the current behaviors between drain and gate in floating gate configuration. These results help to predict the defect location and successfully monitor the bridge-failure through electrical analysis.
Backside Sample Preparation Challenges for Fault Localization Analysis of Flip Chip Package
Authors: Cao Lihong , Wallace Donna , Tuttle Lynda , Martin Kirk
Published: December 2020

Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation techniques such as laser base thermal emission and photon emission techniques. In this paper, two mechanical thinning techniques were applied by using the 3D die curvature thinning and 2D planar thinning on flip chip Si backside. The impact of process parameters on die planarity and fault isolation were also discussed. The experimental results demonstrate the milling system’s high uniformity across the large die size and provide a very good solution for fault isolation techniques.
Application of Laser Deprocessing Techniques in Physical Failure Analysis
Authors: Yap H.H. , Tan P.K. , Lam J. , Ng T.H. , Low G.R. , He R. , Feng H. , Zhao Y.Z. , Dawood M.K. , Tan H. , Huang Y.M. , Wang D.D. , Mai Z.H.
Published: December 2020

With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.
Alternative Sample Preparation Technique for Die Level Parallel Lapping Analysis
Authors: Gwee Hoon Ye , Ng Kiong Kay
Published: December 2020

Parallel lapping (often called delayering) is a commonly used process in failure analysis of integrated circuits. However, parallel lapping commonly gives rise to the issue of weak sample preparation method especially on specimen mounting. The traditional specimen mounting technique was done by mounted a single die to polishing fixture using drop of super glue. Using conventional methods, problems such as losing the die during polishing, serious edge rounding are often encountered. Further, loading the whole polishing fixture into Scanning Electron Microscopy machine for SEM imaging or Passive Voltage Contrast (PVC) fault localization can be complicated due to the size of polishing fixture. Therefore, an alternative, relatively fast and simple method to overcome the above mentioned obstacles is proposed.
Visible Light LVP on Ultra-Thinned Substrates
Authors: Beutler Joshua , Clement J. Joseph , Miller Mary A. , Stevens Jeffery , Cole Edward I.
Published: December 2020

Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultrathinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.
Using Energy Dispersive Spectroscopy (EDS) to Determine the Resistance of FIB Jumpers for Circuit Edit
Authors: DiBattista Michael , Senowitz Corey , Faraby Hasan , Bandaru Prabhakar
Published: December 2020

A key capability of focused ion beam (FIB) tools is the ability to deposit conductive materials by introducing organometallic precursors such as tungsten hexacarbonyl [W(CO)6] or (methylcyclopentadienl) trimethyl platinum [C9H17Pt]. The FIB deposited metal is often used in applications such as the modification of integrated circuits (ICs) by creating new electrical connection on the device. The electrical properties of the FIB material are of particular concern to high speed digital and radio frequency (RF) circuit designers because the resistivity of the FIB deposited metal is orders of magnitude higher in value than the near bulk resistivity value of the metals used in IC manufacturing. In this paper, we developed a correlation between the chemical composition of the FIB deposited metal and the electrical resistivity using an effective media theory (EMT) model. Analysis shows that gallium from the ion beam is the dominant contributor to lowering the resistivity of the jumper. The results of this work and model allow us to understand the role the chemical elements play in the electrical resistance of the FIB electrical jumper and to estimate the FIB metal resistance from energy dispersive spectroscopy (EDS) analysis and the geometry.
Auto-Metrology on TEM Images of FinFET
Authors: Biring Sajal
Published: December 2020

The FinFET has been introduced in the last decade to provide better transistor performance as the device size shrinks. The performance of FinFET is highly sensitive to the size and shape of the fin, which needs to be optimized with tighter control. Manual measurement of nano-scale features on TEM images of FinFET is not only a time consuming and tedious task, but also prone to error owing to visual judgment. Here, an auto-metrology approach is presented to extract the measured values with higher precision and accuracy so that the uncertainty in the manual measurement can be minimized. Firstly, a FinFET TEM image is processed through an edge detecting algorithm to reveal the fin profile precisely. Finally, an algorithm is utilized to calculate out the required geometrical data relevant to the FinFET parameters and summarizes them to a table or plots a graph based on the purpose of data interpretation. This auto-metrology approach is expected to be adopted by academia and/or industry for proper data analysis and interpretation with higher precision and efficiency.
Characterization and Simulation of a Body Biased Structure in Triple-Well Technology under Pulsed Photoelectric Laser Stimulation
Authors: Borrel N. , Champeix C. , Lisart M. , Sarafianos A. , Kussener E. , Rahajandraibe W. , Dutertre J-M.
Published: December 2020

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions inside an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed laser on a triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. It reveals possible bipolar transistor activation at high laser power. This activation threshold revealed its dependence on laser power and wells biasing. Based on the measurements made during our experiments, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.