bluuebunny/crossref_metadata_2025 huggingface dataset:
Reliability of die to wafer bonding using copper-tin interconnections
Authors: Garnier Arnaud , Franiatte Rémi , Bouchu David , Anciant Romain , Chéramy Séverine
Published: October 2015

One major step for 3D integration is the die stacking which has to meet mechanical and electrical requirements. Transient Liquid Phase bonding is studied because it is suitable with high interconnection density and also multiple stacking.

For this study, top and bottom wafers including redistribution layers were electroplated with CuSn and Cu respectively. Die to wafer bonding was carried out at 250 °C in neutral atmosphere. Capillary underfill was added in some cases to check its influence.

Interconnections quality was then assessed. Electrical tests were carried out using daisy chains. Shear tests enabled to check mechanical strength and failure location. Finally, cross sectional scanning electron microscopy and energy dispersive X-ray spectrometry allowed identifying metallurgical phases and potential defects. These characterizations were achieved before and after aging. This aging consisted either in thermal cycle test (TCT: 500 cycles between −40 °C and 125 °C with 10min soak time) or high temperature storage (HTS) applying the same thermal budget as during the TCT.

After assembling, interconnections have very good electrical and mechanical properties. Their degradations are measured after TCT but they are larger than after HTS. This reveals failure mechanisms is not only based on chemical aging but also involve thermomechanical stress. This last feature has been limited thanks to underfill addition. Its effect was investigated through TCT where electrical yield drop was lower than when the gap between the die and the wafer is not filled.

Moreover, SEM images reveal different kinds and densities of voids. Kirkendall voids are located at the Cu/Cu3Sn interface. Smaller voids are visible at the initial bonding interface in the case of CuSn to Cu bonding. After aging, some cracks develop mainly through Kirkendall voids which therefore seem to be the most detrimental defects to overcome.
Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages
Authors: Bhopte Siddharth , Galloway Jesse , Park Kyung-Rok , Park Hyun-Jin , Choi Jeong-Han , Yu Ho-Beob , Yang Sung-Hwan
Published: October 2015

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology.

Fine pitch (<60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects.

TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage.

TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.
Groove Geometry and Mold Shrinkage Effects on Die Stress in Flip Chip Molded BGAs (FCMBGA)
Authors: Baloglu Bora , Jimarez Miguel , Syed Ahmer
Published: October 2015

Exposed die flip chip molded BGA (FCMBGA) packages are preferred for their improved thermal performance and reduced system cost. In this package type, mold compound replaces the traditional capillary underfill and also provides a better stiffening option for the package without the need for additional structural support such as lid and/or stiffening ring. In addition, it allows better utilization of the board real estate as the passive components can be placed closer to the die. Groove or an undercut is the shape of the mold around the exposed die that is formed during the molding process. To ensure a mold-free top surface of the die, a seal (soft insert) that has a larger surface area than the die is being used to cover the die top surface. This larger portion of the seal outlines the groove geometry when it is compressed on top of the die. Seal size can be designed to establish certain groove geometry. Thus, it is important to characterize/understand the effects of the groove geometry as it is a design parameter and can be adjusted to create more robust molded packages. In this study, specific groove width and depth values for various package configurations are investigated using finite elements analysis, FEA. Initially, a detailed finite element model is prepared and warpage simulation is performed. Model correlation to the actual Shadow Moiré is obtained. Then, using the correlated finite element model, die back side stress and shear stresses, where die faces mold compound, are obtained for a thermal cool down simulation from the molding temperature. Mold compound shrinkage is also considered by using an adjusted thermal expansion coefficient value. As a validation study, a test mold chase/tool for varying insert sizes has been designed and, molded packages with different groove geometries and different mold compounds were build. Using the correlation between the test data and the simulation results an order of importance (based on the groove geometry parameters and mold compound's material properties) will be presented which then, can be used as a design guideline to change the groove geometry to produce more robust molded packages.
Detection and Mitigation of Electrostatic Pull-in Instability in MEMS Parallel Plate Actuators
Authors: Stevens Colin , Dean Robert
Published: October 2015

Electrostatic MEMS actuators are used in a wide variety of applications including micro-machined gyroscopes, high speed mechanical switches, variable capacitors, and vibration isolation devices. MEMS parallel plate actuators (PPAs) are simple to realize, yet complex nonlinear variable capacitors. If a DC voltage is applied in attempt to move the proof mass greater than 1/3 of the electrode rest gap distance, the device becomes unstable and the electrodes snap into contact. Most research into this pull-in phenomena is devoted to extending the operational range of motion past the 1/3 instability point. This usually involves the addition of complex external electronics. Many applications, however, only require that the actuator remain out of the pull-in region, and do not require an extended stable range of motion. If detection of the pull-in event is all that is required, then simpler solutions can be realized, minimizing the requirements on the driving signal. Once pull-in is reached, the velocity of the movable plate increases rapidly until the plates make contact. The decreasing distance causes a proportional increase in capacitance. To maintain a constant voltage across the plates, an inrush of current must flow into the actuator in response to the increased capacitance. This paper presents a method for detecting the inrush current using a transimpedance amplifier circuit to convert the current to a measurable voltage. Once pull-in is detected, the PPA is electrically shutdown to prevent damage to the actuator or the voltage source, thus mitigating pull-in. A simulation of the expected results was performed using a Simulink model for the actuator structure predicting the expected range of inrush current. This result was then verified using a silicon micro-machined PPA connected to the detection/mitigation circuit on a PCB. The experimental results follow closely with the simulation allowing precise control in mitigating the pull-in event.
Design, Simulation and Testing of High Density, High Current Micro-machined Embedded Capacitors
Authors: Beal Aubrey , Stevens C. , Baginski T. , Hamilton M. , Dean R.
Published: October 2015

Due to increasing speed, density and number of signal paths in integrated circuits, motivations for high density capacitors capable of quickly sourcing large amounts of current have led to many design and fabrication investigations. This work outlines continued efforts to achieve devices which meet these stringent requirements and are compatible with standard silicon fabrication processes as well as silicon interposer technologies. Previous work has been further developed resulting in devices exhibiting greater capacitance values by employing geometries which maximize surface area. The Atomic Layer Deposition (ALD) of thin layered high K materials, such as Hafnium Oxide, as opposed to previous silicon-dioxide based devices effectively increased the capacitance per unit area of the structures. This paper outlines the design, fabrication, and testing of high density micro-machined embedded capacitors capable of quickly sourcing (i.e. risetimes greater than 100A/nsec) high currents (i.e. greater than 100A). These devices were successfully simulated then tested using a standard ringdown procedure. Generally, the resulting device characterization found during testing stages strongly correlates to the expected simulated device behavior. Subsequent descriptions and design challenges encountered during fabrication, testing and integration of these passive devices are outlined, as well as potential device integration and implementation strategies for use in silicon interposers. The modification and revision of several device generations is documented and presented. Increased device capacitive density, maximized current capabilities and minimized effects of series inductance and resistance are presented. These resulting thin, capacitive structures exhibit compatibility with Si interposer technology.
Sealing dispensing requirements to meet MEMS packaging and throughput impact
Authors: Park Heakyoung
Published: October 2015

The MEMS industry has gained big momentum recently with significant unit growth, especially in the consumer market. While traditional MEMS devices like automotive accelerators have established high-volume manufacturing processes and packages with high reliability, most MEMS devices have been fragmented in packaging because of their unique requirements and small volumes, resulting in high packaging costs. In the cost-sensitive consumer market, devices such as MEMS microphones, accelerometers, and gyroscopes in mobile devices have rapidly increased their production volume and chased lower packaging cost while accepting relatively less reliability than traditional devices.

Sealing dispensing can be applied to device or cap wafer for wafer capping process. Wafer capping protects active MEMS from dicing process after release because the additional cavity wafer with sealing covers the MEMS structure. There are manufacturing challenges because wafer capping requires precise alignment and a variety of bonding methods have technical drawbacks. Printing is one way to deposit sealing lines to cap wafers, but consumes a relatively wide area and may not work if the sealing line must go onto the MEMS die wafer. Sealing line can also be applied to organic substrate that contains MEMS device and ASIC and then lid is attached for bonding in cavity packages.

Previous paper covered technical requirements for dispensing sealant, volumetric accuracy, and motion systems to meet packaging trends and addressed manufacturing cost reductions. This paper will include investigating the impact on the throughput model due to size reduction efforts in packaging. More dies can be produced per given wafer size, which means there is more dispensing area per wafer. In addition, sealing line requirements will be more challenging, and so this paper will address these demands.
Assembly Challenges for 2.5D Packages
Authors: Kelly Michael G , Mattei Marnie , Reed Rick
Published: October 2015

Interposers provide a crucial intermediate step for next generation products to allow side-by-side integration of technology optimized. The interposer size in most cases is greater than 22mm on a side and in some designs exceeds 30mm. This large size combined with a thickness of ≤ 100 microns may result in high warpage which can significantly impact the assembly process. Materials and process selection become a key consideration to create a high yielding, multi-die stacked product.

This presentation will outline the challenges of a large 2.5D TSV product and how assembly strategies have been used to accommodate these challenges. Different process options and die attach sequences for interposer to substrate and chips to interposer will be discussed and critically differentiated. The assembly methods for attaching multiple die with tens of thousands of I/O at 40 micron fine pitch will be compared in relation to the die size and interposer warpage. Product design requirements may also dictate that the optimum assembly approach is achieved by combining methods such as mass reflow and TCNCP bonding for die attach and underfill. Test considerations at intermediate assembly steps will also be reviewed for feasibility in the overall process flow.
3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics
Authors: Das Rabindra , Egitto Frank D. , Rosser Steven G. , Kopp Erich , Bonitz Barry
Published: October 2015

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 ï¬m to 250 ï¬m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.
Novel Low-Loss Photodefined Electrical TSVs for Silicon Interposers
Authors: Thadesar Paragkumar , Bakir Muhannad S.
Published: October 2015

Silicon interposers with through-silicon vias (TSVs) have been widely explored to connect multiple chips using high-density fine-pitch lateral interconnects. However, there are challenges with the TSVs in silicon interposers: (1) TSV losses increase as TSV height increases and are much higher in low-resistivity silicon substrates, which are more economical, than in high-resistivity silicon substrates, and (2) coefficient of thermal expansion (CTE) mismatch between the copper and silicon leads to stress generation. To address this set of challenges, we fabricated and characterized two novel photodefined TSVs for silicon interposers: polymer-clad TSVs and polymer-embedded vias.

The fabricated polymer-clad TSVs consist of a ~20 μm thick photodefined dielectric liner instead of a 1 μm thin SiO2 liner, while the polymer-embedded vias consist of copper vias embedded in photodefined polymer wells within the silicon wafer. Compared to the conventional TSVs with thin (~1 μm) SiO2 liner, ~3.5X and ~20X reductions in TSV insertion loss can be obtained at 25 GHz using the fabricated polymer-clad TSVs and polymer-embedded vias, respectively. Full-wave EM simulations were performed in HFSS to compare the insertion loss of the novel TSVs with the conventional TSVs. With respect to the polymer-clad TSVs, in addition to the reduction in TSV insertion loss, a possible reduction in TSV stresses can be obtained using a low Young's modulus material for the thick liner. Finite-element modeling (FEM) simulations were performed in ANSYS to analyze the possible stress reduction that can be obtained using the fabricated polymer-clad TSVs compared to the conventional TSVs. Finally, four-point resistance measurements were performed for the novel TSVs to prove their high yield.

In summary, this presentation will report fabrication and resistance measurements of the novel polymer-clad TSVs and polymer-embedded vias as well as HFSS and ANSYS simulations for the novel TSVs.
Polymer Based Interposer offering Si Matched CTE + ESD Protection
Authors: Shrier Karen
Published: October 2015

For 2.5 D package integration interposers based on silicon have widely been investigated. However, their high cost adder to the package is a major drawback. An alternative interposer based on polymer- nanoparticle compound material is introduced. It can be manufactured in large volume by low cost processes. Depending on polymer layer structure a CTE varying between 0 to 8 ppm/ °C can be adjusted. A polymer system which has a CTE close to Si of 2.6 ppm/ °C is used for a thermally matched interposer. The material is less fragile than silicon or glass. Copper vias through the polymer substrate have been manufactured with a diameter of 2 um by laser drill. The manufactured thickness of the interposer varies between 200 um and as low as 85 um. In addition, by choice of appropriate nano particles the interposer can act as overvoltage protection element where regions between wires become conductive under high voltage conditions. This enables an intrinsic ESD protection implemented into the interposer protecting the stacked dies against ESD discharges as high as 15 kV IEC.
Development of Plating Process for Micro Bump Formation
Authors: Katase Takuma , Tatsumi Koji , Hatta Tekeshi , Ishikawa Masayuki , Masuda Akihiro
Published: October 2015

Flip chip connection has been applied to a lot of applications in order to shorten the connection length of high performance devices. Solder bumping is one of the key technologies for flip chip connections, and its quality makes a large impact on the reliability after packaging. Recently, bump size has been getting smaller to correspond to the finer connection pitch, and these types of bumps are called “micro bumps”.

Electroplating is one of the methods for solder bump formation. Sn-Ag is considered as the best candidate for lead free alloy to be used for the electroplating method. Electroplating is a suitable method to form micro bumps. For micro bump connections, Cu pillar is necessary to obtain a suitable bump height.

Traditionally, there have been some technical difficulties to achieve smooth morphology on “micro bump” surfaces due to its small diameter and/or high aspect ratio.

Lately, we succeeded in developing a new Sn-Ag plating process for micro bump formation by optimizing the plating process.

We also successfully developed our Cu plating process for Cu pillar application with a high plating rate more than 10 ASD condition. Our Cu plating process is available to obtain various surface shapes of Cu pillar such as flat, dome, and concave.

In this study, we established our plating process with Cu pillar + Sn-Ag solder cap. We will review our current status and features of our plating chemical for micro bump formation.
Production of Uniform Dimension Copper Pillars for Flip Chip CSP
Authors: Kenny Stephen , Matejat Kai , Schauer Carsten , Lamprecht Sven
Published: October 2015

Copper pillars in FCCSP positioned on the substrate are being used instead of solder only joints to meet reliability targets and the demand for smaller feature size, thinner dies and to achieve a well defined stand off. The transfer of the copper pillars from the die to the substrate is required to ensure a reliable thinning process for the dies. The plated copper pillar geometry is dependent on the size of the solder resist opening and thickness. The uniformity and in particular the height of the pillar is very dependant on the electrolytic copper plating parameters used. The height uniformity of all pillars in an array is critical for reliable die attachment to the substrate.

This paper reviews conventional methods to produce electrodeposited copper pillars and introduces a new method for the production of uniform height copper pillars on a FCCSP substrate. Conventional photolithography is eliminated from the new process by use of laser ablation of the features which also prevents any misalignment issues. A sacrificial layer is used to ensure that the copper plated pillars have uniform height. Use of this sacrificial layer also ensures that no seed layer remains on the soldermask surface; conventional methods for pillar production have the disadvantage that seed layer residues may remain on the soldermask giving a pitch limitation. Use of the new process has no pitch limitation due to residual seed layer; initial results with pitch of 200 μm are shown with pillar height 50 μm above solder mask. Development is continuing to reach a pillar pitch of less than 100 μm.

The final solder finish on the plated copper pillar may be electroless tin or a further electrolytic nickel deposit may be used to give a barrier layer before solder deposit.
Microfluidic Technology using SU8 on top of PCBs
Authors: Gassmann Stefan , Pagel Lienhard
Published: October 2015

The usage of standard PCBs (Printed Circuit Boards) for the creation of micro fluidic systems was already reported. The combination of a standard micro technology using photolithography and photo sensitive layers and the PCB technology leads to interesting low cost solutions for micro systems. The technology and some examples will be presented in this talk.

Using PCBs as the substrate the integration of electronics is simple and the substrate is available at low cost. Putting the sophisticated SU8 based micro technology using photolithography on top, new systems can be created. Both technologies deliver their best, in the PCB technology integrated electrodes and electronics can be created while the SU8 technology adds high resolution high aspect-ratio micro systems which are not possible in a PCB implementation. Although this combination seems to be straight forward, several issues have to overcome for a successful realization. These are the surface roughness, adhesion problems and the uniform coating of rectangular substrates. In the talk these issues will be addressed.

As successful examples an electro-osmotic pump and an electrochemical DNA sensor will be presented.
Glass Carrier Wafers for the Si Thinning Process for Stack IC Applications
Authors: Shorey Aric , Wang Bor-Kai , Canale Joe , Thomas Windsor
Published: October 2015

Glass carriers have proven to provide a solution for carriers during wafer thinning operations for 3D-IC (Three-Dimensional Integrated Circuit). The attributes of the glass carrier, such as total thickness variation (TTV), flatness and properties such as coefficient of thermal expansion (CTE), are extremely important in their functional performance. Optimization of Corning's fusion forming process gives a platform that is very well suited to generate high precision glass carriers. This process provides glass at target thickness (no grind/polish required) with a pristine surface, extremely tight TTV, low warp/bow, and thickness tolerance over large volumes of material. Given that this material is formed in sheets as large as three meters in size, there is tremendous flexibility in the size of the wafers; as well as ability to scale to high volume manufacturing in a cost effective way. Furthermore, the ability to alter glass composition provides the opportunity to optimize material properties, such as CTE. This is important to accommodate the needs of various device structures which require thinning.

Non-uniformities (TTV, flatness) in the carrier directly impact the accuracy of the thinned wafer TTV. As important as the low TTV and warp/bow provided by Corning's optimized fusion process, is the method in which these attributes are characterized. Corning ® Tropel ® has developed a novel distance measuring interferometer based on a frequency stepping laser that is well-suited to characterize the flatness and TTV of glass wafers.

The work presented here will highlight the importance of high precision carriers and metrology techniques used to characterize and qualify these materials. The impact these have on the TTV of a bonded stack is just as critical. The ability to leverage all of these tools to provide bonded stacks with extremely low TTV and highly uniform silicon wafers after thinning operations will be demonstrated.
Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly
Authors: Oliver Mark , Kim Jong-Uk , Gallagher Michael , Wang Zidong , Okada Janet , Iagodkine Elissei , Zoschke Kai , Wegner Matthias , Töpper Michael
Published: October 2015

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, excellent thermal stability, and clean room-temperature release directly from the device wafer. We will present successful temporary wafer bonding using a new BCB (benzocyclobutene)-based material that can meet these requirements.

For this temporary wafer bonding technology, wafer preparation involves spin coating the device wafer with the BCB-based adhesive to a thickness of up to 100 μm and spin coating the carrier wafer with an adhesion promoter. The wafers can then be bonded at temperatures as low as 80 °C for as short as 30 seconds. The low bonding temperature means the wafers can be loaded into a preheated wafer bonding tool, eliminating the time needed to heat and cool the bonding chucks during the bonding cycle. Also, no curing of the material is required during the bonding, enabling a short process time and high wafer throughput. Curing of the adhesive is done as a batch oven cure at 210 °C for one hour after which the material is stable enough for backside processes up to 300 °C. The material has been designed to adhere well to the carrier wafer and debond directly from the device wafer without any chemical or radiation pretreatment, leaving a clean device wafer surface in need of only mild cleaning before further processing.
Effect of Substrate Layer Variation on Package Warpage
Authors: Wells Brendan C. , Lin Wei , Park HyunJin
Published: October 2015

As requirements for thinner packages continue to be driven by increased device functionality, warpage has become more and more of a concern in package design and processing. Designers are limited by available materials whose properties are not always capable of achieving low warpage targets. Outside of materials development, techniques in the fabrication processing of organic substrates have served as an important secondary approach to reducing package-level warpage. This is becoming more and more important as the substrate thickness is reduced. For a thin substrate, each layer has a marked impact on the substrate's mechanical character, so each must be specified carefully. In addition, a thin substrate is more sensitive to parameter variation within design tolerance and processing windows, resulting in higher warpage standard deviation, which is another challenge for warpage control.

In this paper, several substrate attributes are studied to determine the magnitude of their effect on overall package warpage and deviation. Packages are built using substrates with different variations of metal layer thickness, dielectric layer thickness, solder resist layer thickness, and metal layer density. Warpage data for these packages will be presented alongside statistical analysis. Warpage simulations are also performed and compared to assembly measurement data to rank the largest contributors. The goal of this paper is to inform package design teams of the best ways to limit warpage through processing, when bill of material changes are unavailable.
A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology
Authors: Caswell Greg , Hechfellner Rudi , Kruger Michiel , Heemstra Tewe , Lumileds Philips , Blattau Nathan , Kittlesen Gregg , More Vikrant
Published: October 2015

LEDs are quickly evolving as the dominant lighting solution for a wide variety of applications. With the elimination of incandescent light bulbs and the toxic limitations of fluorescent bulbs, there has been a dramatic increase in the interest in high-brightness light emitting diodes (HB-LEDs). Getting the light out of the die, with reliable color, while maintaining appropriate thermal control over a long service life is a challenge. These issues must be understood and achieved to meet the needs of unique applications, such as solid-state-lighting, automotive, signage, and medical applications. These applications have requirements for 15–25 years of operation making their reliability of critical importance.

Philips Lumileds, in conjunction with DfR Solutions, developed reliability models for the LUXEON Rebel LED carrier series with respect to multiple circuit board construction types and material sets. Solder fatigue lifetime was predicted based on strain energy calculations. Finite element models were developed to calculate shear stress and strain range.

Temperature cycling of the different material sets was performed to validate the models. The experimental results were integrated in DfR's Automated Design Analysis™ software to ascertain the Physics of Failure (PoF) based reliability predictions for the LEDs. In this paper, the model development methodology and validation approach will be described. Additionally, the Philips Lumileds tool used to demonstrate the long term reliability characteristics of their LEDs to customers will be presented.
Low temperature MOCVD TiN barrier deposition for high aspect ratio TSVs : A solution for 3D integration
Authors: MOURIER Thierry , Minoret Stephane , Fadloun Sabrina , Djomeni Larissa , Maitrejean Sylvain , Burgess Steve , Price Andy , Jones Chris , Roule Anne , Vandroux Laurent
Published: October 2015

In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality.

Via-Middle TSV is considered a reference integration scheme and requires void-free copper fill of very high aspect ratio TSVs.

Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step as barrier material to copper diffusion must provide good efficiency to copper diffusion for further integration and especially on TSV sidewalls, requiring sufficient step coverage.

Ionized PVD is today widely extended from BEOL to TSV metallization. This technique has, however , several limitations for 3D integration coming from its poor step coverage in 10:1 aspect ratio features thus requiring thick material deposition to cover sidewalls which will lead to expensive process both for deposition and further CMP steps and high stress leading to adhesion issues.

Considering the maturity level of the alternative processes, MOCVD metallization appears to be a very promising Solution. MOCVD TiN layers have been widely reported to provide excellent step coverage and diffusion barrier efficiency in BEOL processes.

The presented study describes a process based on an MOCVD TiN deposition that can be performed from 175 to 400 °C. This polyvalent process can be performed for anytype of 3D integration from Mid process TSVs where performance is the key factor to Via last integration for which low temperature and low cost processes are required.

The paper will first discuss the process development and characterization of this material with particular focus on key parameters for 3D integration. In addition, film integration in Via-Middle TSVs will be described, comparing step coverage performance in high aspect ratio TSVs with the I-PVD reference process.

Then, electrical measurements of daisy chains and interconnect lines from a 300 mm 3D demonstrator will be presented.
Strain in Electroless Copper Films: Analysis by in situ X-Ray Diffraction and Curvature Methods
Authors: Bamberg Simon , Bernhard (corresponding author) Tobias , Gregoriades (presenting author) Laurence J. , Brüning Frank , Brüning Ralf , Etzkorn Johannes , Friz Wolfgang , Merschky Michael , Muir Bruce , Perry Laura K. , Sharma Tanu
Published: October 2015

Strain in chemically deposited copper films on polymer substrates was determined by means of in situ X-ray diffraction (XRD), deposit stress analyzer (DSA) and spiral contractometer (SC). The strain evolution of the films was studied as a function of copper film thickness and electroless copper bath parameters, during and after deposition. The results are not indicative of a preferred crystallite orientation or texturing in the deposit. The copper film stress is controllable over a wide range of some 100 MPa from compressive to tensile stress by appropriate variation of bath parameters (e.g. temperature, concentration of bath components such as nickel, stabilizer and formaldehyde). A higher tendency of blister generation for relaxed or compressively stressed films is apparent, which implies that a sufficient level of tensile stress throughout the deposition promotes film adhesion. An observable change from tensile to compressive film stress during the cooling of the sample from bath operation to rinse water temperature is discussed in terms of substrate-induced thermal stress to the copper film. In this context, the difference in the substrate materials required for XRD (polymer), DSA (copper) and SC (stainless steel) may be a significant factor contributing to the diverging measured stress behaviors of the methods. Moreover, it is questionable whether SC stress data can be compared with XRD and DSA stress data, due to the low resolution of the SC method (~60 MPa).
Reliability and Performance Improvements of 3D System-in-Packages in Fan-Out Wafer Level Packaging
Authors: Hayes Scott , Gong Tony , Mitchell Doug , Vincent Michael , Wright Jason , Foong Yap Weng
Published: October 2015

Recent development efforts for fan-out wafer level packaging (FO-WLP) have focused on system-in-package (SiP) solutions using both 2D and 3D packaging structures. Creating connections between the various elements of the system is one of the critical requirements of the packaging technology. The connections must provide a low loss pathway, exhibit manufacturability and prove reliable. Effective system connections enable complex yet volumetrically and electrically efficient systems to be constructed. The combination of various system elements including, but not limited to, SMDs, CMOS, GaAs, MEMS, power devices, imaging sensors or IPDs gives system designers the capability to generate novel systems and differentiating solutions. Both 2D and 3D SiPs based upon the Redistributed Chi Package (RCP) have been developed for consumer, defense and medical applications. In RCP (i.e. FO-WLP), 2D systems are readily achieved through the use of existing packaging processes, materials and structures. For 3D embodiments, the FO-WLP technology must be expanded. 3D integration in FO-WLP can be achieved with the use of package-on-package (PoP), embedded substrates, package edge connections, die stacking or even TSV approaches. However, a more typical solution to the 3D integration challenge is the through package via (TPV). TPVs can resemble substrate vias but their construction is typically different. Regardless of materials selected or processes used to create the TPV, system connections using a TPV will require a certain level of performance and reliability. Reliability and performance improvements to the 3D RCP technology will be presented.
Low Residual Stress and High Performance Dielectric for WLP (Wafer Level Packaging) Applications
Authors: Thibault Raymond , Gallagher Michael , Wang Kevin , Yonkey Matthew , Romer Duane , Liu Xiang Qian , Ho Kim , Prokopowicz Greg , Lachowski Joe , Oliver Mark , Huenger Eric , Inaoka Seiji , Kisting Scott , Mills Lynne , McNamara Sue , Bell Rosemary
Published: October 2015

The advanced packaging application space continues to evolve as mobile devices pack more and more features into a limited space. This feature concentration is causing a deviation from the conventional shrinkage pathway predicted by Moore's law which, in turn, requires dielectric materials with ever more rigid thermal, chemical, and mechanical properties to meet the challenging requirements of next generation packages such as TSV and 3D chip stacking. One such challenge is the thinner substrates required for vertical integration in TSV and 3D packages. Cured dielectrics impart stress onto the underlying substrate and this wafer bow will only magnify with thinner substrates. Designing photodielectrics with inherently lower residual stress will greatly aide in the development of materials to meet future advanced packaging needs. This presentation will outline the development of a new photodielectric material that builds upon the excellent thermal, electrical, and chemical stability of BCB-based materials while providing a significant reduction in residual stress.
Integration of Passive Components into 3D PoP Fan-Out Packages
Authors: Strothmann Tom
Published: October 2015

Fan-Out Wafer Level Packages provide a flexible assembly platform for single die, multi-chip, and 3D structures in a minimal form factor. As a result, the FO-WLP has gained rapid acceptance as a competitive package in the fast growing market of mobile devices. The eWLB version of FO-WLP has achieved the greatest commercial success, with millions of units already assembled and shipped in mobile phones. Although multi-chip structures have been discussed previously, one capability of the technology that has not received wide attention is the incorporation of passive devices into the packages. There are two common implementations of 3D packaging with the FO-WLP technology. The first is fan-out packages with one sided redistribution layers (RDL) using laser drilled vias to enable the direct mount of top packages. The second is two sided packages with through-mold vias that enable RDL on both the top and the bottom of the package. Using multichip embedding technology, it is possible to embed discrete components such as capacitors, resistors, or inductors into the body of the fan-out package in very close proximity to the active device. This close proximity to the active device combined with Cu RDL routing provides exceptional performance for decoupling capacitors and other passive devices. In a two sided RDL implementation, routing can be provided on the top of the package to enable integrated inductors and pads for direct mounting of additional passive components. This two sided implementation can reduce the combined board footprint of active devices and their required passives through the use of 3D integration. This presentation will discuss the various implementations of embedded passives in the 3D FO-WLP and the form factors that can be achieved with this solution.
Thermal & mechanical challenges for 3DIC integration
Authors: Cheramy Severine
Published: October 2015

3DIC integration is considered as one of the biggest revolutions coming in the next few years in microelectronics and assembly: revolution for the integration & process - from front end to 3D final assembly; revolution for supply chain, design tools, test and characterization...Impact of 3D process and stacking on Cmos and associated design rules that this integration will generate is a key point to ensure the real interest of 3D stacking.

Many recent results tend to prove that some of those challenges are undertaken and on the good way to be solved: 2,5D integration, a step toward 3DIC, is already under production, and thus proposes some embryos of solutions. We can assume that when 2,5D will come with relevant yields and throughputs, the step toward 3DIC will be easier to climb.

Nevertheless, 3DIC will come with specific challenges: thermal impact, coupling effect, stress impact...This paper is an overview of past and current work at Cea-Léti on those thematic. Among others, thermal modeling and characterization is given. Technological solutions at device level are proposed to reduce areas & impacts of hot points.

Secondly, mechanical management of an interposer is detailed: especially with a large interposer, included high density of interconnections, warp management is a key point during 3D process steps, but also during 3D assembly. For this thematic also, some characterizations are given with some proposed solutions.

Finally, a review of major 3D technological steps with associated possible impacts on performances is given. It gives both the already done work, and some of the challenges still to address.
Trends in Automotive Packaging
Authors: Daves Glenn G.
Published: October 2015

The long-term trend in automobiles has been increasing electronics content over time. This trend is expected to continue and drives diverse functional, form factor, and reliability requirements. These requirements, in turn, are leading to changes in the package types selected and the performance specifications of the packages used for automotive electronics. Several examples will be given.

This abstract covers the development of a distributed high temperature electronics demonstrator for integration with sensor elements to provide digital outputs that can be used by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aircraft engine. This distributed electronics demonstrator eliminates the need for the FADEC or EHMS to process the sensor signal, which will assist in making the overall system more accurate and efficient in processing only digital signals. This will offer weight savings in cables, harnesses and connector pin reduction.

The design concept was to take the output from several on-engine sensors, carry out the signal conditioning, multiplexing, analogue to digital conversion and data transmission through a serial data bus. The unit has to meet the environmental requirements of DO-160 with the need to operate at 200°C, with short term operation at temperatures up to 250°C.

The work undertaken has been to design an ASIC based on 1.0 μm Silicon on Insulator (SOI) device technology incorporating sensor signal conditioning electronics for sensors including resistance temperature probes, strain gauges, thermocouples, torque and frequency inputs. The ASIC contains analogue multiplexers, temperature stable voltage band-gap reference and bias circuits, ADC, BIST, core logic, DIN inputs and two parallel ARINC 429 serial databuses. The ASIC was tested and showed to be functional up to a maximum temperature of 275°C.

The ASIC has been integrated with other high temperature components including voltage regulators, a crystal oscillator, precision resistors, silicon capacitors within a hermetic hybrid package. The hybrid circuit has been assembled within a stainless steel enclosure with high temperature connectors. The high temperature electronics demonstrator has been demonstrated operating from −40°C to +250°C.

This work has been carried out under the EU Clean Sky HIGHTECS project with the Project being led by Turbomeca (Fr) and carried out by GE Aviation Systems (UK), GE Research – Munich (D) and Oxford University (UK).
Die Stacking is Happening in Mainstream Computin
Authors: Black Bryan
Published: October 2015

Die stacking has proven effective in MEMs and FPGA solutions but has yet to impact mainstream computing CPUs and GPUs. This talk will walk through how die stacking will enter mainstream computing and how it will change the industry in the future

Operating 100kV downhole neutron tube power supplies at temperatures above 150 °C yield low operating efficiency due to excessive diode leakage in the series Cockroft - Walton multipliers typically used. Such circuits are usually limited to less than twelve stages due to N3 voltage regulation effects resulting in immoderate potentials across the switching rectifiers. This paper discusses the merits of using parallel multipliers with 30 stages or more to achieve higher conversion efficiencies at elevated temperatures in tools with 1.3 inch (32mm) diameters. By minimizing the per-stage voltage, definite improvements are realized due to reductions in reverse current leakage per device. Efficiencies of up to 50% may be achieved at 175 °C operating temperature by this technique. In addition, ripple voltages present on the output are not a function of the number of multiplying stages in parallel designs.
Cost Comparison of Temporary Bond and Debond Methods For Thin Wafer Handling
Authors: Palesko Amy , Palesko Chet
Published: October 2015

Miniaturization and increased performance demands are driving the industry to explore 2.5D and 3D packaging. Although progress has been made in recent years, many barriers remain. One primary cost driver for 2.5D and 3D processes is the temporary bond and debond method used for thin wafer handling. Various solutions are appearing on the market, but there is not a single method taking the lead as the obvious best choice. Many factors must be considered when looking at the total cost of a thin wafer handling solution. In this paper, we will use cost modeling to carry out detailed cost and yield trade-offs for temporary bond and debond methods. Instead of concentrating on one proposed solution that is available on the market, we will analyze a range of solutions, focusing on variables such as tool cost, material cost, throughput, and yield. With this analysis, we will determine the most significant cost drivers within the temporary bond and debond process and propose process details for a reasonable solution.