(Invited) A Discussion on the Latest Performance of Gan–Based Vertical Devices and the Paths Forward
Authors: Chowdhury Srabanti 
Published: February 2020

Recent progress in vertical Gallium Nitride (GaN)-based power electronic devices has been compelling. Thanks to dedicated programs like the ARPA-E SWITCHES, which led to the understanding of the challenges, while enabling several variants of vertical devices to be studied and compared. An overview of different flavors of vertical devices and their latest performance will be presented.

Under the SWITCHES program, in collaboration with UCSB, NRL and Transphorm, we pursued two novel and practical approaches that had the common theme of markedly reducing the required device chip size compared to commercially available lateral GaN-on-Si HEMTs. CAVET [1,2] was investigated where the gated region was implemented with p-type layer on an n-channel. The study allowed us to understand the limitation of an ion-implanted current blocking layer in a 3-terminal vertical FET configuration, eliminating restrictions imposed by poor gate dielectric. In order to achieve a ‘true’ vertical transistor, OGFET, a variant of MOSFET, was developed [3,4] where, unlike the CAVET, the gating was also performed on electrons traveling perpendicular to the surface. From a CAVET, we have successfully achieved dispersion-less switching under 500ns pulses (under Pulsed I-V measurements), and over 1100V blocking in OGFET where scaling of the devices to 1A was recently achieved. While the successes of these devices speak volumes about the future possibilities and roadmap, the technical challenges are substantial.

The overarching issue is related to the realization of a well-behaved buried p-n junction, which forms the basic building block of most vertical transistors for power electronics. Fundamentally, all of them require Mg based doping, and therefore the issues related to Mg activation in GaN impact everyone. Mg is a deep acceptor in GaN offering less than 1% activation under room temperature. In addition to the RT ionization related challenges, buried p-GaN activation (this strictly means the activation from hydrogen that tend to form Mg-H complexes passivating the acceptors) is a proven concern. In short, the difficulties in achieving well-behaved buried p-GaN have stunted the possibility of realizing well-behaved (buried) p-n junctions critical to vertical devices.

In a MOSFET the p-layer is grown during the initial growth of the structure. This guarantees a well-behaved p-type GaN. Similar to the reports by various groups like Toyoda Gosei and HRL[5,6], Gupta et al. (UCSB) [4] showed via OGEFT that trenched vertical devices deliver promisingly high voltage results with a path towards low On-resistance (Ron). Recently Ji et al (UC Davis) [7] successfully delivered scaled devices capable of offering 1A current with 144 unit cells in parallel. Ron <4.4mΩ.cm2 was achieved in these devices, which can be lowered further with improvement in the channel mobility. Normally-off in design, the MOSFETs definitely are attractive for the economic use of the chip area and their compatibility with presently used gate drivers

A parameter to address with future research is the channel mobility to deliver lower Ron. While the typical behavior of a good gate oxide (like low trapping and small threshold voltage (Vth) shifts) also apply for these devices, the gates being designed on the sidewalls (being a or m-plane) ensure higher threshold voltages compared to c-plane HEMTs or CAVETs. This definitely alleviates the well-known tradeoff of Ron and threshold Vth to a vast degree. This talk will go over all the major achievements made over the last three years, and lay out the challenges for achieving 1.2KV switches with Ron<3mΩ.cm2

S. Chowdhury, et al., “CAVET on bulk GaN substrates achieved with MBE-regrown AlGaN/GaN layers to suppress dispersion,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 41-43, Jan. 2012.

S. Mandal, et al., “All-GaN Mg ion-implanted current blocking layer CAVET demonstrating over 500V blocking voltage,” in International Workshop on Nitride Semiconductors (IWN), Orlando, USA, 2016.

W. Li, et al., “Design and fabrication of a 1.2kV GaN-based MOS vertical transistor for single chip normally off operation,” Phys. Status Solidi A., vol. 213, no. 10, pp.2714-2720, Oct. 201

C. Gupta, et al., “OG-FET: An in- situ Oxide, GaN interlayer based vertical trench MOSFET,” IEEE Trans. Electron Devices., vol. 37 , no. 12, pp. 1601-1604, Oct. 2016.

H. Otake, et al., "Vertical GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistors on GaN Bulk Substrates", Applied Physics Express, vol. 1, no. 1, p. 011105, 2008.

R. Li, et al., "600 V/ 1.7 Ω Normally-Off GaN Vertical Trench Metal–Oxide–Semiconductor Field-Effect Transistor", IEEE Electron Device Letters, vol. 37, no. 11, pp. 1466-1469, 2016.

D.Ji et.al, "Scaling GaN OGFET with MOCVD regrown n-GaN insert layer as the channel", 75th Annual Device Research Conference (DRC), Jun. 2017.