bluuebunny/crossref_metadata_2025 huggingface dataset:
Design of Drop Test Apparatus for Electronic Packages
Authors: Yeh Chang-Lin , Lai Yi-Shao
Published: October 2015

In this paper transient structural responses of a drop test apparatus are investigated during drop testing. Parametric studies are carried out to examine the effect of drop heights, composition of materials and component geometries of the apparatus on the pulse duration and the peak acceleration at an observation point. The finite element analysis applies an explicit time integration scheme, which is feasible in dealing with the nonlinear transient structural behavior. Results suggest that an effective design of the drop test apparatus could be performed by changing the composition material of the strike surface and subsequently by adjusting the height of the drop table.
Soldering Properties and Interfacial Microstructure of CSP Solder Joints with Lower Melting Lead-free Solder
Authors: Yamaguchi Atsushi , Yamashita Yuhei , Furusawa Akio , Nishida Kazuto , Hojo Takashi , Sogo Yosuke , Miwa Ayako , Hirose Akio , Kobayashi Kojiro F.
Published: October 2015

In this paper we investigate the appropriate reflow profiles for simulated CSP solder joints using Sn-Ag-Bi-In solder, which has a lower melting point than Sn-Ag-Cu solder. We have examined the relationship between the interfacial microstructure and mechanical characteristics of Sn-Ag-Bi-In solder at the solder joints compared with those of Sn-Zn-Bi solder. When soldering Sn-3Ag-0.5Cu CSP balls on a Cu/Ni/Au pad, Sn-8Zn-3Bi showed high joint strength at 503 K or higher, whereas Sn-3.5Ag-0.5Bi-8In showed strength at the lower temperature of 493 K. This implies that Sn-Ag-Bi-In solder is more appropriate for soldering at lower temperatures. On the joint interface, a stratified Ni-Sn layer was formed when the Sn-3Ag-0.5Cu CSP ball was soldered on the Cu/Ni/Au phases are pad using Sn-3.5Ag-0.5Bi-8In at 483 ~ 493 K. At 503 K or higher, clumped (Cu,Ni)6Sn5 unevenly formed on the joint interface, resulting in lower strength. These results suggest the appropriate reflow thermal profile for Sn-3.5Ag-0.5Bi-8In solder joints with the Sn-3Ag-0.5Cu CSP ball on the Cu/Ni/Au pads should be in the range of 483 ~ 493 K. Even if the reflow peak temperature is over 493 K, slowing down the cooling speed by 2 K/s can prevent loss of joint strength.
Lead Free Die Mount Adhesive Using Silver Nanoparticles Applied To Power Discrete Package
Authors: Ukita Yasunari , Tateyama Kazuki , Segawa Masao , Tojo Yoshihiko , Gotoh Hideyuki , Oosako Katsuhisa
Published: October 2015

Lead-free materials are required to replace conventional lead-containing solder for environmental protection. The Pb-rich solder die mount material in a high-power transistor package is required to be replaced by a silver adhesive paste. The silver paste has disadvantages such as low thermal conductivity and high electrical resistivity, since conduction paths are achieved only by mechanical contacts between silver particles. Recently, a new conductive paste containing silver particles and silver nanoparticles with a particle size of 3–7 nm in diameter was developed. The paste shows very low electrical resistivity of 6×10−6 ohm.cm, since the silver nanoparticles can be fused at temperatures below 200°C. We have been studying the possibility of the paste as a die mount material for high-power transistor packages. It was confirmed that the paste had a very high thermal conductivity of 51 W/mK. We fabricated a high-power transistor package using this paste. As a result, the package showed lower thermal resistance than that fabricated using silver paste or lead-containing solder. Moreover, the package is sufficiently reliable that it passed the thermal cycle and pressure cooker tests. This paste can be applied to a high-power transistor package in place of lead-containing solder.
Novel Method of Separating Probe and Wire Bond Regions without Increasing Die Size and Reducing Weak Fab-Back End of Line Adhesion Interfaces
Authors: Lee Chu-Chung (Stephen) , Tran Tu Anh , Williams Bill , Ross Jody
Published: October 2015

The drive for enhanced electrical performance and reduced silicon area has triggered significant changes in wafer fabrication, wafer level testing, and packaging technologies. In the wafer fabrication era, copper is quickly replacing aluminum as the interconnect metal of choice for technologies 0.13μm and below. To overcome the difficulty of wire bonding onto readily oxidized copper bond pads, capping copper bond pads with aluminum has been the industry standard method for wire bonding. In terms of wafer level testing and packaging, the resulting fine pitch geometry has created challenges for both cantilever probe and wire bond processes. Pad damage due to probe marks during probe process has been shown to cause “non-sticks” and “lifted bonds” at the wire bonding process. The wire bond yield loss due to pad damage is aggravated for fine pitch since increasingly smaller bonded ball diameters are formed on top of the same damage area caused by the probe mark. Wire Bond parameter optimization can minimize wire bond yield loss but cannot eliminate the problem. One logical solution is to lengthen the bond pad to create separate regions for probing and wire bonding. However, this method can result in a larger die size. This paper will reveal a unique bond pad structure that provides separate regions but yet results in no impact to the existing die size. This bond pad structure utilizes the aluminum cap layer to create a longer bond pad without changing the size of the underlying copper last metal, resulting in no impact to the existing die size. Evaluations were conducted on 0.13μm CMOS technology, with cantilever probing and wire bonding on 52μm bond pad size. Failure analysis and test methods to detect failures will be discussed. Designs of experiments for probing and wire bonding processes, characterization studies, and reliability results will be presented. Furthermore, a unique Extended Armored Pad (EAP) has been introduced for the purpose of reducing the Ta-Cu interface area under the Aluminum bond pad region because the Ta-Cu adhesion is known to be one of the weakest interfaces for Cu-interconnect BEOL processes.
Effect of Compatibility between Fluxes and Cyanate Ester Underfill on Lead Free Flip Chip Assembly and Reliability
Authors: Chaware Raghunandan , Stiborek Leon , Libres Jeremias , Marquez Manots , Odegard Charles , Cowens Marvin , Venkateswaran Muthiah
Published: October 2015

The quality and reliability of flip-chip assembly is severely impacted by the compatibility between various materials used in the package. Currently, no-clean fluxes are widely used for the assembly of flip chips. Poor compatibility between the flux residue and the underfill can lead to the formation of voids, and consequently, reliability problems. Therefore, a major concern for flip-chip assembly is the compatibility between the flux residues and the underfill. The principal objective of this research was to develop a flux for lead-free packaging, which would be compatible with high performance moisture resistant cyanate ester-based underfills. During this study, commercially available fluxes, along with tailor made epoxy-based flux, were tested for their compatibility with the underfill. The results indicated that the assembly process window for the rosin-based fluxes was much wider than the epoxy-based fluxes. Synthetic flux had poor soldering performance and relatively poor compatibility with the cyanate ester underfill than rosin-based flux. Epoxy flux exhibited narrow process window and the soldering performance was sensitive to flux thickness, reflow profile, substrate pad surface finish and topography. For smaller packages with die size of 10 mm by 10 mm, the compatibility between the cyanate ester underfill and the different fluxes was comparable. However, for the packages with die size of 22 mm by 22 mm, the compatibility between the epoxy-based flux and the cyanate ester underfill was relatively better than that with the other two flux chemistries.
Electro-migration behavior of Pb-free Flip Chip Bumps
Authors: Labie Riet , Webers Tomas , Swinnen Bart , Beyne Eric
Published: October 2015

Most reliability studies, carried out for characterising new Pb-free solder material, put main focus on the thermal-mechanical behaviour of the solder joints. However, it is seen that electro-migration has a big impact on the intermetallic formation between the pad finish (UBM) and the solder material. Electro-migration therefore has a strong impact on the stability and reliability of the joint. A special test structure for flip chip electro-migration has been developed and applied to a CuNiAu – Sn – CuNiAu solder joint. This novel test structure not only monitors the resistance change of the whole bump stack but also allows separating resistance changes at each side (anodic and cathodic) of the bump. It is noticed that at the cathodic UBM, which is the UBM where the electrons enter the solder joint, the UBM consumption is significantly faster than at the anodic side or at a thermal reference bump. It also results in void formation at the cathode which leads to an accelerated failure.
Electrical Characterization of High Performance Memory FBGA BOC Package
Authors: Gospodinova M. , Nan G. , Thomas J. , Subraya R. , Held J.
Published: October 2015

A multilayer Fine-pitch Ball Grid Array (FBGA) Board-on-chip (BOC) memory package used for applications running at more than 1 Gbit/p/s has been characterized using S-(distributed) parameter measurements and three types of test chips made using state of the art technology. The low parasitics FBGA test board itself was characterized for frequencies up to 5 GHz (the frequency range of interest) with the transmission being greater than −0.12 dB below 5 GHz. S-parameter model simulation of the package itself indicated that the transmission was greater than −1.5 dB up to 5 GHz. Correlation between the S-parameter simulation and measurements for the package and fixture combined was acceptable - in the order of tenths of dB in the frequency range DC to 2.5 GHz. Comparison of the S-parameter model versus lumped (RLC) model in the frequency range from DC to 5 GHz showed that the lumped model can be used for frequencies up to 2.9 GHz. A high degree of correlation between simulation and measurement has been shown. The lumped model bandwidth has been assessed and its application limits for time domain signal integrity simulations have been evaluated.
Simulation of Mold Filling for Non-Newtonian Fluids - Part 2
Authors: Kulkarni Venkatesh M. , Liang Chu Wee , Tan C.W. , Narayana P.A. Aswatha , Seetharamu K.N.
Published: October 2015

This paper deals with the flow in the resin transfer molding process commonly used for IC chip encapsulation in the electronic packaging industry. A solution algorithm is presented for modeling the flow of a non-Newtonian fluid obeying a Power-Law model and the algorithm is used to conduct parametric studies in transfer molding. The flow model uses the Hele-Shaw approximation to solve the Navier-Stokes Equations and a pseudo-concentration algorithm for tracking the interface between the resin and the air. The Finite Element Method is employed to reduce the governing partial differential equations to algebraic form. The model is used to study the flow from the transfer ram into the cavity for different dimensions of transfer molding tools. Parametric studies are carried out to obtain balanced filling for transfer molding configuration. Parametric studies could provide a design guideline to optimize the encapsulation process prior to the setting up of an actual manufacturing set.
Impact of Geometric Parameters of Capillary Design on Quality of Gold Ball Bonding
Authors: Su Jerry Chih-Tsong , Yu Cheng-Hsiang
Published: October 2015

0.13μm or smaller critical dimension of integrated circuits has driven the bonding pad pitch down to 50μm or even smaller. It has also had quite an impact on the adhesive force between the bonding pad and the gold ball. This study focuses on the correlation between the capillary geometric parameters (i.e. tip diameter, chamfer diameter, inner chamfer angle, and cone angle) and the bonding quality (i.e. ball size, ball thickness, ball shear force, specific ball shear force, and capillary vibration). An experimental design is utilized and the response is analyzed statistically. The results show that as the tip diameter and ball size increase, the ball thickness decreases, and the ball shear force increases first and then decreases afterward. As the cone angle decreases, the ball size increases, the ball thickness decreases, and the ball shear force increases. Therefore, both tip diameter and cone angle are significant factors that affect the bond quality. The empirical model, i.e. the correlation between the capillary geometric parameters and the bonding quality is also derived, and is quite useful in predicting the bonding pad size or bonding pad pitch required during process development. The predicted values and the experimental results are shown to have good agreement.
Experimental characterization of thermoelectric properties of thick film composites
Authors: Markowski Piotr , Dziedzic Andrzej
Published: October 2015

This paper presents thermoelectric properties of thick-film composites in relation to their potential use as power microgenerators. Several different combinations of composites were used to create thermopiles. One track of each thermocouple was made of PdAg or Pt and was the reference track and the second one of the tested material. After preliminary tests five composites with low resistance and adequate Seebeck coefficient were chosen (Ag, Ag+RuO2 and three kinds of RuO2). We measured the Thermoelectric Force, ET = f(T) and internal resistance Ri = f(T) characteristics over the temperature range 293 to 493 K. PdAg/Ag thermocouples have nearly two orders of magnitude higher output electrical power than the others. The change in values of electrical parameters of thermopiles after long-term ageing processes was also investigated.
LTCC Microsystems and Microsystem Packaging and Integration Applications
Authors: Peterson K.A. , Patel K.D. , Ho C.K. , Rohrer B.R. , Nordquist C.D. , Wroblewski B.D. , Pfeifer K.B.
Published: October 2015

Low Temperature Cofired Ceramic (LTCC) has proven to be an enabling medium for microsystem technologies, because of its desirable electrical, physical, and chemical properties coupled with its capability for rapid prototyping and scalable manufacturing of components. LTCC is viewed as an extension of hybrid microcircuits, and in that function it enables development, testing, and deployment of silicon microsystems. However, its versatility has allowed it to succeed as a microsystem medium in its own right, with applications in non-microelectronic meso-scale devices and in a range of sensor devices. Applications include silicon microfluidic ‘chip-and-wire’ systems and fluid grid array (FGA)/microfluidic multichip modules using embedded channels in LTCC, and cofired electro-mechanical systems with moving parts. Both the microfluidic and mechanical system applications are enabled by sacrificial volume materials (SVM), which serve to create and maintain cavities and separation gaps during the lamination and cofiring process. SVMs consisting of thermally fugitive or partially inert materials are easily incorporated. Screeding is an incorporation technique we describe that improves uniformity and eliminates processing steps. Recognizing the premium on devices that are cofired rather than assembled, we report on functional-as-released and functional-as-fired moving parts, including an impeller that has been exercised over thirty million cycles, and a cofired pressure sensor that requires only pressure source and electrical connections. Additional applications for cofired transparent windows, some as small as an optical fiber, are also described. The applications described help pave the way for widespread application of LTCC to biomedical, control, analysis, characterization, and radio frequency (RF) functions for macro-meso-microsystems.
LTCC Post Load Cell
Authors: Gongora-Rubio Mário R. , Roberti M. , da Rocha Z M. , Fraigi L
Published: October 2015

This paper presents the development of a force post compressive load cell, fabricated using Low Temperature Cofired Ceramics (LTCC) technology. It was implemented as an LTCC mechanical load cell structure with a z-axis thick film strain gage using two different approaches. Fabrication methods and materials are explored in this work and fabricated devices are presented. This paper will also present the results of initial electromechanical sensitivity to load force and temperature tests. Compressive force behavior is consistent, in a strain level up to 1.500 micro-strain.
Methods for Reducing Power Loss in On-Wafer Inductors
Authors: Karjalainen Päivi H. , Heino Pekka
Published: October 2015

The easist way to improve the quality and decrease the size of the passive components is to improve their layout. On-wafer CMOS inductors with different patterned ground shields (PGS) and different layouts of metal coils aimed at reducing component power losses are presented in this work. Narrow extra wires at the edges of spirals and continuous via arrays in the spirals have been found to be effective. Moreover, the small n-well areas in the middle of a component and small polysilicon parts beside the coils do not harm the operation of the inductor. These results provide motivation for processing passive components stacked on top of each other.
Fabrication and Testing of a Micromirror Device Actuated by PZT Thin Films
Authors: Xiao Z.M. , Chen B.J. , Fan H.
Published: October 2015

The paper describes the fabrication and characterization of two-dimensional resonant micromirror device actuated by sol-gel deposited PZT thin films. The actuation principle is based on the bimorph beam structure, which consists of an oxide layer and a piezoelectric PZT layer. The two-dimensional scanning performance can be achieved by applying AC voltages with phase shifts at resonance to the actuating beams. The devices are fabricated through thin film depositions, lithography, dry plasma etching and the ICP release process. For a micromirror structure with a 300μm ×300μm mirror plate, the first four resonance frequencies are measured to be in the range of 10–30 kHz. To investigate the vibration modes, the deflections on different locations of the mirror plate are measured. The two dimensional scanning angle is determined to be in one direction and 11° at 23.4 kHz in the perpendicular direction.
Electrical Characterization of FCBGA Package Based on Measurement Approach for High-speed SOC Applications
Authors: Chen Ming-Kun , Tai Cheng-Chi , Huang Yu-Jung
Published: October 2015

With high-speed computers and wireless communications system become more popular in the electronic market, these communication-oriented products require high packaging densities, clock rates and higher switching speeds over Gb/s. A multilayer flip-chip Ball grid array (FCBGA) package used for applications running at more than 1 Gb/s has been characterized in this work. Electrical characterization of the package becomes essential beyond 1 GHz considering that the interconnections on the package behave not only just as interconnections but also as transmission lines. In this paper, we present the measurement and simulation results for interconnection of an FCBGA package using the time domain reflectometry (TDR) method. Simulation and measurement results are compared to establish a proper equivalent circuit model of the FCBGA interconnections. The parasitics of the power network can be measured through TDR, vector network analyzer (VNA) and impedance analyzer (IA). The complete models generated in this work are targeted for high-speed system-on-chip (SOC) devices that have a wide range of uses across commercial electronic applications.
Improvement of High-Temperature Reliability of Ball Bond Using Platinum-Modified Gold Alloy Wires
Authors: Maki Kazunari , Nakata Yuji , Nagao Masayoshi , Mishima Akifumi
Published: October 2015

For superior Au/Al ball-bond reliability, we have developed the 3N (>99.9 wt% Au), 2N5 (>99.5 wt% Au) and 2N (>99 wt% Au) Au alloy bonding wires which contain less than 0.1, 0.5 and 1 wt% Pt, respectively. In the thermal aging test of squashed balls (40 μm in diameter), which consists of storage in air at 250°C and evaluation with wire pull and ball shear, it has been found that there are interesting differences in the ball-bond degradation as a function of wire type. Even the samples bonded using the 3N wire with a very small amount of Pt show superior ball-bond reliability compared with those using a 4N (>99.99 wt% Au) wire without any addition of Pt. The ball-bond degradation in the thermal aging test is reduced significantly with increasing Pt content of a wire. From microstructural analysis of the aged 2N ball bonds, the Pt-containing layer, which seems to play a crucial role in improvement of the ball-bond reliability, have been found in the upper part of intermetallic compounds.
Effect of Silane Functional Group on Adhesion of Selected Epoxies for Microelectronic Packaging
Authors: Borrego M. Jenkins , Dauskardt R. H. , Bravman J. C.
Published: October 2015

This paper describes experiments designed to evaluate the effect of various silane surface treatments on the thin-film adhesion of epoxies filled with spherical silicon oxide. Fracture mechanics-based methods evaluated adhesion of both filled and unfilled epoxies to silicon oxide. SEM was used to examine fracture surfaces and evaluate fracture mechanisms. Two different epoxies were tested, including one with four components and multiple intermediate cure reactions. It was found that the only silanes that augmented adhesion of the epoxies to silicon oxide were those with functional groups identical to those of the epoxies which take part in the final curing reaction. However, when these silanes were used to coat filler, adhesion of filled epoxies to silicon oxide wafers remained the same or was slightly reduced. In all cases, fracture occurred at or near the epoxy-wafer interface, suggesting that deformation within the epoxy layer was limited. Only one set of specimens, in which the silane was improperly prepared, resulted in augmented epoxy-wafer adhesion facilitated by filler-matrix delamination. In other words, filled epoxy-wafer adhesion increases with decreasing efficacy of silane adhesion promoter treatment.
Single Sample Cylinder for RGA Correlation
Authors: Schuessler Philipp wh , Rossiter Daniel J. , Lowry Robert K. , Sierzant Sheryl M.
Published: October 2015

A large portion the manufacturers of high reliability microelectronic devices must have those devices tested to be proven “dry”. A mass spectrographic technique, referred to as Residual Gas Analysis (RGA) has been the primary means of demonstrating that the devices contain less than the 5000 parts per million(ppm) of moisture. However, there are no standards for determining moisture levels of this nature when tested in this manner. Too often, the pass/fail criteria for a given production lot is exceeded and recourse becomes time consuming and expensive.

A small group of technologists has successfully fabricated and tested a Single Sample Cylinder (SSC) wherein moisture-laden air can be taken from one analytical facility to another for comparison analyses. The need for such a device is explained by a brief review of why “identical” microelectronic devices from the same production line have been found to contain different chemistries when analyzed via Residual Gas Analysis, per Test Method 1018 of the military standards.

The SSC is over two liters in volume; hence it can deliver hundreds of “air samples” that have the same chemical composition. It is maintained at 100° C during test but is kept at room ambient during non-analytical periods.

Several major problems had to be overcome in order to be able to continuously generate samples of the same chemistry. The primary two were moisture adsorption to all of the various exposed surfaces, and second was hydrogen diffusion from the materials of construction, with subsequent oxide reduction to form more water.

Some anomalies were experienced during initial preparation of the SSC and the early hours of equilibration. These again are believed to be adsorption/desorption related. Thereafter it was shown that the SSC could deliver samples that were within 2% of each other, or better, within a sample set. The level of precision between sample sets was +/− 2.5%.

This study was developed on a statistical basis, involving over 100 data points and was carried out over 1450 hours. The gas analyses were performed in a Defense Supply Center Columbus (DSCC) certified testing facility.

This study was conducted with the support of an additional analytical chemist and a statistician to assure that data generated met the goals of the stated objective.
Development of High Reliability Via on IVH (VONI) for High Density Interconnect Circuit Boards
Authors: Park Jong-Won , Hwang Yun-Seok , Jeun Il-Kyoon , Joung Da-Hee , Chong Myung-Gun , Yang Dek-jin
Published: October 2015

Via on interstitial via hole (VONI) technique is a complex set of technologies for blind and buried vias in traditional sequential lamination cycles with external layers, and micro via holes (MVH) for true high-density packaging. However, when VONI is repeatedly subjected to thermal stress, the interstitial via hole (IVH) in its structure often creates problems such as IVH barrel cracks, and layer-layer delamination. To solve VONI's reliability problems, such as IVH barrel crack and layer-layer delamination, the authors have investigated the relationship between the CTE difference and the effect of moisture. Through using different types of plugging inks, it was clearly indicated that delamination was related to the chemical properties of the plugging inks. For example delamination was dominated by the inks property of water adsorption, which induced vapor pressure when it undergoes thermal shock testing. The authors have solved the delamination problem by reducing the ratio of water adsorption in the plugging ink.
Failure Analysis of Lead-Free Solder Joints of an 1657CCGA (Ceramic Column Grid Array) Package
Authors: Lau John , Castello Todd , Shangguan Dongkai , Dauksher Walter , Smetana Joe , Horsley Rob , Love Dave , Menis Irv , Sullivan Bob
Published: October 2015

In this study, failure analysis of the 1657CCGA package with 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb solder pastes on lead-free PCBs with the Entek OSP (organic solderability preservative) surface finish is investigated. Emphasis is placed on determining the failure locations and failure modes of the solder joints of the 1657CCGA assemblies after they have been through 7,000 cycles of temperature cycling.
Design and Optimization of Piezoelectric Fans for Cooling of Microelectronic Devices
Authors: Ramana Maram Venkata , Almanar Indra Putra , Abdullah Mohd Zulkifly , Ripin Zaidi Mohd , Seetaramu K.N.
Published: October 2015

Static, modal, and dynamic finite element analyses have been performed for cantilever piezoelectric fans to understand their mechanical behavior and to aid in design-optimization studies. Three-dimensional analysis was carried out by using the finite element analysis software package, ANSYS. Various parameters—like length, thickness, location of the piezoelectric metal layer, temperature, damping ratio, and electric field—have been considered. The effects of these parameters on the vibration characteristics and performance are investigated and consolidated through artificial neural networks. Feed-forward single hidden layer perceptron neural networks and Levenberg–Marquardt back-propagation (LMBP) algorithms are used to train the neural network. Optimal geometrical dimensions for maximum performance are then obtained using genetic algorithms.
New Sacrificial Layer-Based Screen-Printing Process for Free-Standing Thick-Films Applied to MEMS
Authors: Lucat Claude , Ginet Patrick , Ménil Francis
Published: October 2015

Thick-film sacrificial layers based on inorganic materials have been used for the fabrication of free-standing screen-printed films. A specific polymer ink based on a mixture of epoxy and strontium carbonate has been prepared for screen-printing of the sacrificial layer. After deposition and subsequent heat treatments of the structural and sacrificial layers, the latter is removed in an aqueous solution. The harmlessness and efficiency of the process have been demonstrated with regard to the structural layer(s). This new process, initially developed in our laboratory for the fabrication of a cantilever type beam, has been extended to the elaboration of an electrothermal actuator, constituted of two linked copper beams of different widths. The beams are partially suspended above the substrate to which they are anchored. Other developments include the fabrication of heating resistors and microchannels. Moreover, the process has been shown to facilitate the implementation of microassemblies such as piezoelectric transformers.
Reliability Assessment: New Tools for the Next Generation of Packages
Authors: Bord Isabelle , Levrier Bruno , Deshayes Yannick , Béchou Laurent , Ousten Yves
Published: October 2015

Reliability assessment of components, integrated circuits, and microassemblies is clearly identified as a major factor in the on-going development of microelectronics. Since the last decade, the 3-D packaging and interconnections have emerged, and integrated packages have been developed. System-in-package (SIP) has become the principal support for integrated systems. Numerous problems are linked to their decreasing dimensions, the increasing numbers of interfaces (multichips stacked one on top of another), and plastic packages that must tolerate higher temperatures (RoHS). How is the reliability of such components assessed? What are the tools to investigate failure mechanisms in these new packages? This article gives some solutions mixing acoustic analysis, x-ray microscopy, electrical testing, and the use of specific tests points (sensors) placed in the package.
Study on the Effect of Stack Thickness During Encapsulation of Stacked-Chip Scale Packages (S-CSP)
Authors: Abdullah M. Khalil , Abdullah M.Z. , Mujeebu M.A. , Kamaruddin S. , Ariff Z.M.
Published: October 2015

Development of microelectronics continues toward further miniaturization. Stacked-chip scale packages (S-CSPs) can address the issues associated with high-density packaging with reduction in cost and greater improvements in functional performance. However, the problems involved in the encapsulation of S-CSPs are complex because of the crucial gap thickness between the die top and mold surface. Air traps, void formation, and flow retardation are major problems. In this paper, three-dimensional (3-D) mold filling with different arrangements of stacked dice in S-CSPs is investigated with the objective of determining the optimum number of stacked dice. A 2-D view on the top surface is chosen because it is easier to visualize the melt front compared with the 3-D view. It is found that the time needed to fill the package and the chance of void formation increase with increasing number of stacked dice.
Numerical Optimization of Silicon Stacked Module for 3-D Packaging Applications
Authors: Viswanath Akella G.K. , Zhang Xiaowu , Wang Y.Y. , Yoon S.W. , Khan Navas , Kripesh Vaidyanathan
Published: October 2015

Three-dimensional package format has gained more popularity for various applications because of the trend toward higher functional integration, miniaturization, and better electrical performance. This paper presents a design optimization study of a 3-D package using a silicon interposer. The package consists of three stacks with five dies. Electrical connections through the silicon interposers are done by through-silicone vias (TSVs) filled with electroplated copper. Initially, structural optimization of the package is conducted by a 2-D finite element analysis and later, statistical analysis is performed to estimate the coupled effects of parameters considered for the design. Carrier thickness variation is found to be the most significant effect on the package warpage. Interfacial stress between the copper plug and the silicon via hole has been investigated and reported. A 3-D model is constructed for the solder joint reliability study with SnAgCu material properties. Solder joint life with variation of parameters (i.e., board level underfill, higher standoff solder interconnect, and low CTE board) is studied, and all results are reported accordingly.
Interconnect Analysis for 80-Gbps Serial Link Design
Authors: Fasig Jonathan , Rash Gregory , Randall Barbara , Fritz Karl , Currie Steven , McCoy Bart , Riemer Paul , Wilkins Wendy , Gilbert Barry , Daniel Erik
Published: October 2015

This paper presents a case study of the modeling and simulation methods used to design the signal path for a proposed 80-Gbps serial data link between digital systems. This design includes flip-chip transitions from custom IBM 8HP integrated circuits to multilayer organic substrates, with coaxial-cable connections between substrates. Discussion topics include interconnect material selection, detailed 3-D electromagnetic modeling of the conductor transitions and signal paths, time-domain circuit simulation of the complete data path including the driver and receiver, and bit-error rate analysis of the complete link. Simulated data are presented.
Predicting the Thermal Conductivity of Low Temperature Co-fired Ceramic with Embedded Thermal via Arrays using the Rule-of-Mixtures and Interface Area Analytical Methods
Authors: Vincent T.S.
Published: October 2015

Increased power-density applications especially for front-end modules have created the need for adequate thermal management in microwave design. Although low-temperature co-fired ceramics (LTCCs) have a lower thermal resistance than PCB substrates, it is still desirable to lower the resistance further by introducing thermal via arrays. A thermal imaging system using an IR camera was used to measure the top surface temperature over a range of powers with samples that had varying via sizes and densities. The empirical data results from this study were compared with conventional and an interface area method. The conventional method used to compare the experimental results to predicated results is the simple rule-of-mixtures. The fact that the thermal conductivity and diffusivity of the filled via are so much greater than those of the LTCC material means that another method of theoretically calculating the resulting thermal conductivity can be used by studying the thermal path. The ceramic–conductor interface area is also calculated to predict material system conductivity and compared with the conventional method and experiments.
Ceramic Microwave Circuits for Satellite Communication
Authors: Kulke R. , Möllenbeck G. , Günner C. , Uhlig P. , Drüe K.H. , Humbla S. , Müller J. , Stephan R. , Stöpel D. , Trabert J.F. , Vogt G. , Hein M.A. , Molke A. , Baras T. , Jacob A.F. , Schwanke D. , Pohlner J. , Schwarz A. , Reppe G.
Published: October 2015

KERAMIS is the acronym of a German research and development project funded by the German Space Agency (DLR) and the Federal Ministry of Economics and Technology (BMWI). The consortium is developing an RF circuit technology for Ka band multimedia satellite applications. A set of modules has been designed, manufactured, and tested by the partners of the consortium. The goal of this effort is to qualify the KERAMIS technology for space applications and to participate in an on-orbit-verification (OOV) program of the DLR. The launch of the technology verification satellite (TET) is scheduled for late 2010. This paper will give an overview of innovative circuit and module designs as well as the assembly, integration, and test results of the project. The authors will present a modular circuit concept for state-of-the-art transmitters and receivers in space at around 20 GHz. Selected modules are a 4 × 4 switch matrix, two synthesizers, and other RF modules. All circuits are based on multilayer ceramic (LTCC) including passive components, transitions, housings, and DC supply.
Hermetic Package for Optical MEMS
Authors: Seigneur F. , Fournier Y. , Maeder T. , Ryser P. , Jacot J.
Published: October 2015

This paper describes the design and fabrication of a hermetic LTCC package for an optical MEMS chip designed for space applications. The package ensured electrical and optical connections, mechanical positioning, atmosphere control, and finally low thermally induced stress on the MEMS during the final packaging operation. The package consisted of a 10-layer LTCC case with a recessed cavity for the MEMS chip, and a glass lid (with antireflection coating and thin-film metallization for soldering) for optical I/O. The chip was mechanically attached to the bottom of the cavity with a silicone adhesive, and electrically connected through gold wire bonds. The gold wire bonding pads were routed through the LTCC module to a MegArray BGA connector. Hermetic closure of the cavity was carried out by soldering the glass lid onto the case in a controlled atmosphere. The two main difficulties involved in such a package were the high electrical connection density (400 connections) and low-temperature hermetic sealing. LTCC design rules for small-pitch lines, thick- and thin-film materials selection, screen printing, lamination techniques, and soldering methods are described in this paper.
Silver-Indium Transient Liquid Phase Sintering for High Temperature Die Attachment
Authors: Quintero Pedro O. , McCluskey F. Patrick
Published: October 2015

The demand for electronics capable of operating at temperatures above the traditional 125°C limit continues to increase. Devices based on wide band gap semiconductors have been demonstrated to operate at temperatures up to 500°C, but packaging remains a major hurdle to product development. Recent regulations, such as RoHS and WEEE, increase the complexity of the packaging task as they prohibit the use of certain materials in electronic products such as lead (Pb), which has traditionally been used in high temperature solder die attach. In this investigation, an Ag-In solder paste is presented as a die attach alternative for high temperature applications. The proposed material has been processed by a transient liquid phase sintering method resulting in an in situ alloying of its main constituents. A shift of the melting point of the system, confirmed by differential scanning calorimetry, provided the basis for a breakthrough in the typical processing temperature rule. The mechanical integrity and reliability of this novel attachment material is discussed.
A Feasibility Study of Lead Free Solders for Level 1 Packaging Applications
Authors: Chidambaram Vivek , Hald John , Hattel Jesper
Published: October 2015

An attempt has been made to determine the lead free ternary combinations that satisfied the solidification requirement for a solder used in level 1 packaging applications, using the CALPHAD approach. The segregation profiles of the promising candidates were analyzed after scrutinizing the equilibrium calculations by Scheil solidification simulations and optimization. A feasibility study has been carried out for the replacement of high-lead-containing solders with the focus on surface tension, natural radius of curvature, oxidation resistance, intermetallic compound formation, and environmental oriented issues.
Qualification Testing of Engineering Camera and Platinum Resistance Thermometer (PRT) Sensors for MSL Project Under Extreme Temperatures to Assess Reliability and to Enhance Mission Assurance
Authors: Ramesham Rajeshuni , Maki Justin N. , Cucullu Gordon C.
Published: October 2015

Package qualification and verification (PQV) of advanced electronic packaging and interconnect technologies and various other types of qualification hardware for the Mars Exploration Rover/Mars Science Laboratory flight projects has been performed to enhance the mission assurance. The qualification of hardware (engineering camera and platinum resistance thermometer, PRT) under extreme cold temperatures has been performed with reference to various project requirements. The flight-like packages, sensors, and subassemblies have been selected for the study to survive three times (3×) the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification has been performed by subjecting above flight-like qual hardware to the environmental temperature extremes and assessing any structural failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experiments of flight-like hardware qualification tests are described in this paper.
Solder Joint Reliability on 3-D MID LCP Substrates
Authors: Arra Minna , Pääkkönen Esko J , Härkönen Ilkka
Published: October 2015

This paper presents the results from an experimental reliability study. Two different kinds of SMD (surface mount device) components were assembled with Sn/Ag/Cu solder paste onto injection molded, thermoplastic LCP (liquid crystal polymer) substrates patterned with MID/LDS technology. Two different LCP grades were chosen for the experiments. The assembly was also realized on FR-4 PCBs (printed circuit boards), which served as control samples. The assemblies were exposed to a thermal cycling test followed by failure analysis.

As predicted, failures in solder joints occurred earlier on the LCP thermoplastic substrates than on the FR-4 PCB laminates. It was noticed that with one of the LCP grades, the CTE was not the major factor determining the lifetime of the solder joints. A more prominent factor was the dimensional changes that had occurred in the substrates. An SEM/EDS (scanning electron microscope/energy dispersive spectrometry) analysis on the microstructure of the LCP substrates was performed to explain the findings. The analysis showed that there were differences in the detailed microstructure between the two LCP grades. These differences seemed to be related to the different filler particles.
Chip on Board Packaging and Thermal Solutions for a 100 W Large Monolithic LED
Authors: Liu Jay G. , Xiong Daxi , Panaccione Paul
Published: October 2015

Thermal challenges are now widely recognized as one of the key barriers to LED's fast penetration to broader market. This paper demonstrates an effective packaging and thermal solution for a commercial realization of a large area monolithic LED of 12 mm2, with high current operation and total input power as high as 100 W. A direct chip on board (COB) die attach method was used to eliminate one level of interface such as existed in an SMD LED on an insulated metal substrate. High thermal conductivity LED submount and copper core board were designed for effective heat spreading without a dielectric in the thermal path. The thermal resistance of the 12 mm2 LED from junction to heat sink, including core board and associated TIM1 and TIM2, is as low as 0.7°C/W. A thermal model was developed using FEA to describe the temperature and thermal resistance at each interface, and is shown to be in agreement with measured data. The LED chipsets described here have been used to power systems such as rear projection TVs and front projectors.
Split-Post and Split-Cylinder Resonator Techniques: A Comparison of Complex Permittivity Measurement of Dielectric Substrates
Authors: Janezic Michael D. , Krupka Jerzy
Published: October 2015

We provide an overview of two nondestructive techniques, the split-post and split-cylinder resonator, which are under consideration as standard test methods for measuring the relative permittivity and loss tangent of bare low-temperature cofired ceramic (LTCC) substrates over the frequency range of 1–30 GHz. The capabilities and limitations of the split-post and split-cylinder resonator are outlined, and the level of agreement between the two techniques is examined through comparison of the relative permittivity and loss tangent measurements of a fused silica and an LTCC substrate.
Overview of Fatigue Failure of Pb-Free Solder Joints in CSP/BGA/Flip-Chip Applications
Authors: Chinen Sean M. , Siniawski Matthew T.
Published: October 2015

The purpose of this paper is to provide an overview of SnAgCu solder joint fatigue in BGA/CSP/flip-chip applications and the concern of long-term reliability. The most common mode of failure is ductile fracture due to creep strain. Several methods of predicting the overall life of the solder joint are the Coffin-Manson approach, a constitutive fatigue law, and a damage based model using FEM (finite element methods). The effects of underfill and its processes as well as design considerations that will increase reliability will also be discussed.
Evaluation of Via Shielding on Parasitic Coupling, Cavity-Resonance Modes, and Radiation in Multilayer Packages
Authors: Arnaudov Radosvet G.
Published: October 2015

Electromagnetic cavity-resonance modes and parasitic coupling between excitation ports in parallel-plate solid planes of power-return and ground structures are investigated. Such structures are widely used in microwave multilayer packages (MCMs) and could be the source of considerable electromagnetic interference (EMI) or simultaneous switching noise (SSI). Effective methods should be applied for damping and elimination of the radiated fields, especially in small areas and volumes. The developed three-layered LTCC microwave package possesses two separate grounding planes on different levels, connected through multiple vias. The estimation of the electromagnetic field distribution and radiation is conducted by full-wave analysis of the proposed cavity-resonance models. The article also discusses the influence of the layout, vias grid distribution and material properties on the performance of the exemplary structure in the frequency band of interest, 10–30 GHz.
Ferrofluid-Piston Based Micropump and Electromagnetic Actuation in LTCC Technology—First Results
Authors: Atassi I. , Atzlesberger C. , Fulmek P. , Nicolics J. , Smetana W.
Published: October 2015

Fluid control is a critical task in chemical processing. For integrated biological monitoring modules with chemical reactors the integration of micropumps is needed. In this paper we report first experiences with a DC-motor driven microfluidic pump fabricated using LTCC technology (low temperature cofired ceramic). The ceramic tapes carrying the required channel and hole structures were laser micromachined. The device contains plugs and pistons formed of ferrofluid, which were actuated by external magnets. The ferrofluid used for this application is a colloidal suspension of ferromagnetic particles in a hydrocarbon carrier fluid which is immiscible in water. On the basis of the first results and driven by the requirement to further decrease the device dimensions, an approach for electromagnetic actuation in LTCC technology has been studied. In order to achieve a magnetic excitation strong enough to drive the micropump, a high ampacity of the microcoils is one key requirement. Inductors with different tape setups including ferritic LTCC tapes and special conductor geometry were considered. An essential and new approach to achieve a large conductor cross section to suit the geometry constraints in the plane direction was carried out by machining channels into the tapes using an Nd: YAG laser and filling them with conductor paste. In this way, coil conductors with 100 μm × 75 μm cross section were successfully fabricated. Magnetic field simulations of two different multilayer arrangements—ferritic (Heraeus AHT03-003 and ESL 40011) and nonferritic tapes—were compared and ampacity measurements up to 3.5 A were performed successfully.