(Invited) Enabling Hetero-Integration of III-V and Ge-Based Transistors on Silicon with Ultra-Thin Buffers Formed by Interfacial Misfit Technique
Authors: Gong Xiao , Yadav Sachin , Goh Kian Hui , Tan Kian Hua , Kumar Annie , Low Kian Lu , Jia Bowen , Yoon Soon-Fatt , Liang Gengchiau , Yeo Yee-Chia 
Published: February 2020

III-V and Ge semiconductors have been researched as alternative channel materials for future technology nodes [1]-[26]. A key challenge is the integration of p- and n-FETs having different channel materials on Si substrates.

In this paper, we discuss the application of the interfacial misfit (IMF) technique to enable the heterogeneous integration of III-V and Ge-based transistors on Si substrates. IMFs are capable of relieving the large lattice strain and minimizing the formation of threading dislocations. Ge p-FETs and InAs n-FETs were co-integrated on a Si substrate using common contact formation, digital etch, and gate stack formation modules. In addition, vertically stacked GaSb nanowire p-FETs and InAs nanowire n-FETs on Si substrates were also realized with promising electrical characteristics.

GaSb Grown on GaAs with IMF Technique

IMF is a key technique used to enable the heterogeneous integration on Si substrate. For both integration schemes, the III-V layers were grown on the GeOI (100) substrate with a 6° offcut. After the growth of a 70 nm-thick GaAs, a ~50 nm-thick GaSb was grown using the IMF technique. An array of misfits can be observed at the GaAs/GaSb interface as shown in the HRTEM image in Fig. 1(a). These misfits relieve most of the strain in the 7.78 % lattice mismatched GaSb and GaAs system. Under optimized growth conditions, the separation between two misfits is ~5.6 nm, implying that every 14thGa atom from GaAs has a dangling bond [Fig. 1 (b)]. Thanks to confinement of the majority of the defects within a few nanometers at the GaAs/GaSb interface, subsequent layers with high quality can be grown for device fabrication.

Integration of Ge P-FETs and InAs N-FETs on a Si Platform

The first application of the IMF is in integrating Ge p-FETs and InAs n-FETs on a Si substrate using CMOS compatible modules (see Fig. 2). Key features include: First, a sub-120 nm-thick buffer growth technique was used to grow the high-quality channel materials; Second, a common digital etch was employed to precisely control the etch rates of n+ -InAs and Ge, enabling the formation of UTB structures; Third, Ge p-FETs and InAs n-FETs share the same process modules to form the gate stacks and raised S/D structure.

Both InAs n-FETs and Ge p-FETs show the highest reported ION
with good control of short channel effects, among all co-integrated III-V n-FETs and Si1-x
Ge
x
p-FETs on Si.

Integration of GaSb P-FETs and InAs N-FETs based on Vertically-Stacked Nanowires on a Si Platform

Using III-V as channel materials for both p- and n-FETs is another option for future low power and high performance logic applications. Here, we discuss the demonstration of monolithic integration of III-V on a Si platform with vertically stacked III-V nanowire CMOS (Fig. 3). The InAs n-FETs and GaSb p-FETs were integrated on a common Si platform with an extremely-thin buffer layer. Decent electrical characteristics were achieved for both InAs n-FETs with a L
CH of 20 nm and GaSb p-FETs with a L
CHof 500 nm.

References

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Figure 1