bluuebunny/crossref_metadata_2025 huggingface dataset:
Using the Ravenscar profile for space applications
Authors: Vardanega Tullio , Caspersen Gert
Published: October 2004

The Ravenscar Profile emerged in 1997 as a most promising approach to bringing mature, predictable and efficient concurrency into real-time systems with integrity requirements. One of the crucial questions that have arisen since is whether the expressive power of the profile would be truly sufficient for the effective construction of such systems. This paper provides positive evidence to this effect by discussing the merit of the Ravenscar compliant architecture of a reuse library that supports the construction of on-board embedded real-time systems of the new generation. This paper argues that the notions of the profile especially contributed to increase the maturity of the reuse product. As true object orientation is the next frontier of the product, this paper also reflects on the importance of integrating the profile with suitable flavours of object orientation.
Extensible protected types
Authors: Wellings A. J. , Johnson B. , Sanden B. , Kienzle J. , Wolf T. , Michell S.
Published: October 2004

At the last workshop, the issue of being able to extend protected types in the same manner as tagged types was discussed. The conclusion was that further consideration was needed before a definitive proposal could be made. This Position Paper summarises a full proposal and identifies the outstanding issues.
Overview of the Sun Java Community Process's Real-Time Expert Group specification of RT-Java
Authors: Dobbing Brian
Published: October 2004

The session was chaired by Ben Brosgol of Ada Core Technologies.Ben presented an overview of the main points of the specification. He pointed out that during the production of the reference implementation and conformance test suite, further modifications are possible and that the final definition would include all three components (specification, reference implementation and test suite). Andy Wellings presented some comments on the scheduling support offered by the Sun specification.
Attacking the process migration bottleneck
Authors: Zayas E.
Published: October 2004

Moving the contents of a large virtual address space stands out as the bottleneck in process migration, dominating all other costs and growing with the size of the program. Copy-on-reference shipment is shown to successfully attack this problem in the Accent distributed computing environment.
Logical
memory transfers at migration time with individual on-demand page fetches during remote execution allows relocations to occur up to one thousand times faster than with standard techniques. While the amount of allocated memory varies by four orders of magnitude across the processes studied, their transfer times are practically constant. The number of bytes exchanged between machines as a result of migration and remote execution drops by an average of 58% in the representative processes studied, and message-handling costs are cut by over 47% on average. The assumption that processes touch a relatively small part of their memory while executing is shown to be correct, helping to account for these figures. Accent's copy-on-reference facility can be used by
any
application wishing to take advantage of lazy shipment of data.
Recovery management in QuickSilver
Authors: Haskin R. , Malachi Y. , Sawdon W. , Chan G.
Published: October 2004

One price of extensibility and distribution, as implemented in QuickSilver, is a more complicated set of failure modes, and the consequent necessity of dealing with them. In traditional operating systems, services (
e.g.
, file, display) are intrinsic pieces of the kernel. Process state is maintained in kernel tables, and the kernel contains explicit cleanup code (
e.g.
, to close files, reclaim memory, and get rid of process images after hardware or software failures). QuickSilver, however, is structured according to the client-server model, and as in many systems of its type, system services are implemented by user-level processes that maintain a substantial amount of client process state. Examples of this state are the open files, screen windows, address space, etc., belonging to a process. Failure resilience in such an environment requires that clients and servers be aware of problems involving each other. Examples of the way one would like the system to behave include having files closed and windows removed from the screen when a client terminates, and having clients see bad return codes (rather than hanging) when a file server crashes. This motivates a number of design goals:

Properly written programs (especially servers) should be resilient to external process and machine failures, and should be able to recover all resources associated with failed entities.

Server processes should contain their own recovery code. The kernel should not make any distinction between system service processes and normal application processes.

To avoid the proliferation of ad-hoc recovery mechanisms, there should be a uniform system-wide architecture for recovery management.

A client may invoke several independent servers to perform a set of logically related activitites (a
unit of work
) that must execute
atomically
in the presence of failures, that is, either all the related activities should occur or none of them should. The recovery mechanism should support this.

In QuickSilver, recovery is based on the database notion of
atomic transactions
, which are made available as a system service to be used by other, higher-level servers. This allows meeting all the above design goals. Software portability is important in the QuickSilver environment, dictating that transaction-based recovery be accessible to conventional programming languages rather than a special-purpose one such as Argus [Liskov84]. To accommodate servers with diverse recovery demands, the low-level primitives of commit coordination and log recovery are exposed directly rather than building recovery on top of a stable-storage mechanism such as in CPR [Attanasio87] or recoverable objects such as those in Camelot [Spector87] or Clouds [Allchin&McKendry83].
An introduction to the transmission performance capabilities of IEEE 802-5 token-ring networks
Authors: Irvin D.
Published: October 2004

Transmission performance capabilities of the IEEE Standard 802.5 token-ring network are explored from the perspective of a network designer. Typical workloads are presented which quantify the demand placed on transmission resources by various classes of users. Next, a means of characterizing a network's size is developed, and several reference networks are presented. The performance of these networks under the demands of the typical workloads is then projected.
Enhancing Jini for use across non-multicastable networks
Authors: Al-Theneyan Ahmed , Mehrotra Piyush , Zubair Mohammed
Published: October 2004

Distributed heterogeneous systems are being increasingly used to execute a variety of large size simulation and computational problems. Resource management is one of the most important issues in building such systems. Recently, Sun introduced the Jini connection technology for building plug-and-play networks of resources. Jini relies on multicasting across the network for its internal protocols. However, in a distributed environment, such as the one under consideration here, multicasting may not be supported across the subnets for various reasons. In this paper we describe enhancements to Jini required to use it for building a middleware resource management system in a distributed environment that does not support multicasting. In particular, we introduce a lightweight service, called the
Tunneling Service,
which tunnels multicast messages across the subnets. We have implemented our mechanism and used it to successfully tunnel messages between subnets in a single domain and also between different domains. In this paper we describe our design choices and our implementation of the system.
DACIA
Authors: Litiu Radu , Prakash Atul
Published: October 2004

Future distributed applications will need to support computing devices with a wide range of capabilities, varying network connectivity, increasing mobility of users, and a wide variation in load placed by clients on services. This paper presents DACIA, a framework for building adaptive distributed applications. In DACIA, distributed applications are viewed as consisting of connected components that typically implement data streaming, processing, and filtering functions. DACIA provides mechanisms for run-time reconfiguration of applications to allow them to adapt to the changing operating environments. Components can be moved to different hosts during execution, while maintaining communication connectivity with other components. New components can also be introduced along data paths, for example, to provide compression on low-bandwidth connections. Keeping communication overheads low is a significant challenge in designing component-based services. DACIA is designed so that communication costs among co-located components are similar to those of procedure calls. Performance results, as well as examples of adaptive services that can be built using DACIA are presented.
Using SMV for cryptographic protocol analysis
Authors: Zhang Yuqing , Wang Chunling , Wu Jianping , Li Xing
Published: October 2004

SMV is a tool for checking finite state systems. In this paper, a methodology is presented for using SMV to analyze cryptographic protocols. We illustrate the feasibility of the approach by analyzing Needham-Schroeder Public-Key Protocol and discover the well-known attack upon the protocol.
Security problems in the TCP/IP protocol suite
Authors: Bellovin S. M.
Published: October 2004

The TCP/IP protocol suite, which is very widely used today, was developed under the sponsorship of the Department of Defense. Despite that, there are a number of serious security flaws inherent in the protocols, regardless of the correctness of any implementations. We describe a variety of attacks based on these flaws, including sequence number spoofing, routing attacks, source address spoofing, and authentication attacks. We also present defenses against these attacks, and conclude with a discussion of broad-spectrum defenses such as encryption.
A critique of Z39.50 based on implementation experience
Authors: Schoffstall Martin L. , Yeong Wengyik
Published: October 2004

The Z39.50 Information Retrieval Protocol is a proposed ANSI standard for the retrieval of bibliographic information that originates from the library community in the United States. Unlike previous interlibrary loan protocols designed by the library community, Z39.50 is intended to be the basis of an end-user service.This paper provides a brief introduction to Z39.50, then discusses the shortcomings of the protocol that were discovered as a result of implementation experience.
X.400 MHS
Authors: Genilloud Guy
Published: October 2004

Electronic Data Interchange (EDI) is an increasingly important application of computer communications. Until recently, EDI has developed independently of the communications technology and related standards. EDI users coped with this situation by setting up bilateral communications agreements or by using the services of Value Added Data Services centres, which provided protocol conversion. The introduction of X.400 MHS based systems and services is slowly modifying the general attitude towards EDI communications. For the first time, a CCITT rapporteur group is drafting a recommendation for EDI communications within the context of X.400 MHS. More importantly, there already exist official guidelines, both in the U.S.A. and in Europe, which explain how to take advantage of X.400 MHS systems today.The purpose of this paper is to comment upon these first approaches to an EDI communication standard. For this reason, and because we expect only a few readers to be familiar with both EDI and X.400 MHS, we begin with introductions to both subjects.
FDDI- A LAN among MANS
Authors: Ross Floyd E. , Hamstra James R. , Fink Robert L.
Published: October 2004

FDDI (Fiber Distributed Data Interface) is a 100 Mbit/sec local area network (LAN) based on a token ring protocol operating over an optical fiber medium. Though not a metropolitan area network (MAN), FDDI can operate over distances normally considered as the province of MANs. With the addition of FDDI-II capabilities, and the newly defined mapping for FDDI over SONET, FDDI now offers MAN functionality for large organizations needing to provide integrated services over a widely based high performance private network. This paper updates earlier efforts on this subject, giving an up-to-date overview of FDDI, FDDI-II and SONET mapping. At the end of the paper a brief look at the possible future for FDDI technology is given.
The use of connectionless network layer protocols over FDDI networks
Authors: Katz Dave
Published: October 2004

Methods for running the DoD IP and OSI connectionless network layer protocols over the FDDI medium are presented. Issues specific to the interaction between network layer protocols and FDDI are discussed, and some possible approaches to problems encountered are evaluated. The OSI protocol suite is examined in particular detail.This work was supported in part by National Science Foundation agreement no. NCR 8720904.
Kinder, gentler average-case analysis for convex hulls and maximal vectors
Authors: Dwyer Rex A.
Published: October 2004

While the derivations of precise asymptotic estimates found in the mathematical literature are not easily accessible to the non-specialist, there are rather simple arguments for deriving rougher "big-theta" bounds on the expected size of random convex hulls. These arguments are presented, then applied to verify a recently published conjecture on the expected number of maximal vectors among a set of random points chosen from a ball. A summary of recent progress follows. Results relevant for analyzing algorithms are emphasized.
Scheduling and page migration for multiprocessor compute servers
Authors: Chandra Rohit , Devine Scott , Verghese Ben , Gupta Anoop , Rosenblum Mendel
Published: October 2004

Several cache-coherent shared-memory multiprocessors have been developed that are scalable and offer a very tight coupling between the processing resources. They are therefore quite attractive for use as compute servers for multiprogramming and parallel application workloads. Process scheduling and memory management, however, remain challenging due to the distributed main memory found on such machines. This paper examines the effects of OS scheduling and page migration policies on the performance of such compute servers. Our experiments are done on the Stanford DASH, a distributed-memory cache-coherent multiprocessor. We show that for our multiprogramming workloads consisting of sequential jobs, the traditional Unix scheduling policy does very poorly. In contrast, a policy incorporating cluster and cache affinity along with a simple page-migration algorithm offers up to two-fold performance improvement. For our workloads consisting of multiple parallel applications, we compare space-sharing policies that divide the processors among the applications to time-slicing policies such as standard Unix or gang scheduling. We show that space-sharing policies can achieve better processor utilization due to the operating point effect, but time-slicing policies benefit strongly from user-level data distribution. Our initial experience with automatic page migration suggests that policies based only on TLB miss information can be quite effective, and useful for addressing the data distribution problems of space-sharing schedulers.
Resource allocation in a high clock rate microprocessor
Authors: Upton Michael , Huff Thomas , Mudge Trevor , Brown Richard
Published: October 2004

This paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
Authors: Maynard Ann Marie Grizzaffi , Donnelly Colette M. , Olszewski Bret R.
Published: October 2004

Experience has shown that many widely used benchmarks are poor predictors of the performance of systems running commercial applications. Research into this anomaly has long been hampered by a lack of address traces from representative multi-user commercial workloads. This paper presents research, using traces of industry-standard commercial benchmarks, which examines the characteristic differences between technical and commercial workloads and illustrates how those differences affect cache performance.

Commercial and technical environments differ in their respective branch behavior, operating system activity, I/O, and dispatching characteristics. A wide range of uniprocessor instruction and data cache geometries were studied. The instruction cache results for commercial workloads demonstrate that instruction cache performance can no longer be neglected because these workloads have much larger code working sets than technical applications. For database workloads, a breakdown of kernel and user behavior reveals that the application component can exhibit behavior similar to the operating system and therefore, can experience miss rates equally high. This paper also indicates that “dispatching” or process switching characteristics must be considered when designing level-two caches. The data presented shows that increasing the associativity of second-level caches can reduce miss rates significantly. Overall, the results of this research should help system designers choose a cache configuration that will perform well in commercial markets.
Surpassing the TLB performance of superpages with less operating system support
Authors: Talluri Madhusudhan , Hill Mark D.
Published: October 2004

Many commercial microprocessor architectures have added
translation lookaside buffer
(TLB) support for
superpages
. Superpages differ from segments because their size must be a power of two multiple of the base page size and they must be aligned in both virtual and physical address spaces. Very large superpages (e.g., 1MB) are clearly useful for mapping special structures, such as kernel data or frame buffers. This paper considers the architectural and operating system support required to exploit medium-sized superpages (e.g., 64KB, i.e., sixteen times a 4KB base page size). First, we show that superpages improve TLB performance only after invasive operating system modifications that introduce considerable overhead.

We then propose two subblock TLB designs as alternate ways to improve TLB performance. Analogous to a subblock cache, a
complete-subblock TLB
associates a tag with a superpage-sized region but has valid bits, physical page number, attributes, etc., for each possible base page mapping. A
partial-subblock TLB
entry is much smaller than a complete-subblock TLB entry, because it shares physical page number and attribute fields across base page mappings. A drawback of a partial-subblock TLB is that base page mappings can share a TLB entry only if they map to consecutive physical pages and have the same attributes. We propose a physical memory allocation algorithm,
page reservation
, that makes this sharing more likely. When page reservation is used, experimental results show partial-subblock TLBs perform better than superpage TLBs, while requiring simpler operating system changes. If operating system changes are inappropriate, however, complete-subblock TLBs perform best.
The performance impact of flexibility in the Stanford FLASH multiprocessor
Authors: Heinrich Mark , Kuskin Jeffrey , Ofelt David , Heinlein John , Baxter Joel , Singh Jaswinder Pal , Simoni Richard , Gharachorloo Kourosh , Nakahira David , Horowitz Mark , Gupta Anoop , Rosenblum Mendel , Hennessy John
Published: October 2004

A flexible communication mechanism is a desirable feature in multiprocessors because it allows support for multiple communication protocols, expands performance monitoring capabilities, and leads to a simpler design and debug process. In the Stanford FLASH multiprocessor, flexibility is obtained by requiring all transactions in a node to pass through a programmable node controller, called MAGIC. In this paper, we evaluate the performance costs of flexibility by comparing the performance of FLASH to that of an idealized hardwired machine on representative parallel applications and a multiprogramming workload. To measure the performance of FLASH, we use a detailed simulator of the FLASH and MAGIC designs, together with the code sequences that implement the cache-coherence protocol. We find that for a range of optimized parallel applications the performance differences between the idealized machine and FLASH are small. For these programs, either the miss rates are small or the latency of the programmable protocol can be hidden behind the memory access time. For applications that incur a large number of remote misses or exhibit substantial hot-spotting, performance is poor for both machines, though the increased remote access latencies or the occupancy of MAGIC lead to lower performance for the flexible design. In most cases, however, FLASH is only 2%–12% slower than the idealized machine.
The effectiveness of multiple hardware contexts
Authors: Thekkath Radhika , Eggers Susan J.
Published: October 2004

Multithreaded processors are used to tolerate long memory latencies. By executing threads loaded in multiple hardware contexts, an otherwise idle processor can keep busy, thus increasing its utilization. However, the larger size of a multi-thread working set can have a negative effect on cache conflict misses. In this paper we evaluate the two phenomena together, examining their combined effect on execution time.

The usefulness of multiple hardware contexts depends on: program data locality, cache organization and degree of multiprocessing. Multiple hardware contexts are most effective on programs that have been optimized for data locality. For these programs, execution time dropped with increasing contexts, over widely varying architectures. With unoptimized applications, multiple contexts had limited value. The best performance was seen with only two contexts, and only on uniprocessors and small multiprocessors. The behavior of the unoptimized applications changed more noticeably with variations in cache associativity and cache hierarchy, unlike the optimized programs.

As a mechanism for exploiting program parallelism, an additional processor is clearly better than another context. However, there were many configurations for which the addition of a few hardware contexts brought as much or greater performance than a larger multiprocessor with fewer than the optimal number of contexts.
Is information system a science? an inquiry into the nature of the information systems discipline
Authors: Khazanchi Deepak , Munkvold Bjørn Erik
Published: October 2004

The information systems (IS) discipline is apparently undergoing an identity crisis. Academicians question the need for IS departments in colleges, stating the absence of a core for the field and its integration within other business functions as a basis for its elimination. At the same time, many practitioners, as reflected in the U.S. government's recent IT labor shortage report, continue to ignore IS as a distinct field of study. This article briefly outlines these and other challenges and argues that notwithstanding underlying philosophical differences, it can be concluded that IS is an emerging scientific discipline. This conclusion is reached through an assessment of the debate surrounding the issue of whether IS should be a discipline and an analysis of the IS discipline using some key characteristics of "science." The arguments put forth in this paper have four key implications for the IS community: a continuing emphasis on adopting scientific principles and practices for conducting inquiry into IS phenomena; an enhancement of the self-concept of IS academics and professionals through a common identity; it enhances the ability of supporters of the IS field to defend against criticisms, integration with other disciplines, and resource rivalry; and it creates the potential of being well-situated to building a cumulative tradition in the field.
Access values pointing to any object
Authors: Green Geir
Published: October 2004

This proposal is an extension/generalization to ALIWG LI49: "Provide access values pointing to static objects". It incorporates two new features to Ada [Ada83]: Persistent objects and safe handling of access type objects designating any declared object or component thereof, including static objects (not only objects in a collection, created by the system allocator). All the suggested extensions to Ada are upward compatible.
A “To Be Determined” package for Ada development
Authors: Bardin Bryce M.
Published: October 2004

This paper illustrates how the Ada language supports simple and convenient techniques for maintaining the syntactic and semantic validity of unfinished designs, thereby enabling designers and implementors of software systems to benefit from the consistency checking that an Ada compiler performs on its libraries well before that would otherwise be possible. It is asserted that this capability is likely to be particularly useful for large systems development. Both a rationale for and a concrete example of an Ada package which supports the techniques are provided.
A note on redundancy in encrypted messages
Authors: Gong Li
Published: October 2004

In a cryptographic protocol, it is important for a recipient to determine that a message has not been modified during transmission. This is normally achieved by providing redundancy in the message. Typically, a message is described in the literature as containing enough redundancy, not enough redundancy, or no redundancy at all. This note shows that, because of the secrecy that comes with encryption, redundancy can be provided at two different levels. An example demonstrates that this distinction is useful in guarding against certain cryptographic attacks on weak keys.
Estimating disperse network queues
Authors: Gawlick Rainer
Published: October 2004

Recent work in queueing theory has provided a means by which queue lengths can be estimated based solely on information about service completions. The work yields algorithms that permit the estimation of invisible or disperse queues which would be difficult to measure directly. These algorithms may be applied to resources in communications networks at which difficult-to-measure queues exist. The following paper presents an algorithm for queue estimation and measures its accuracy on transmission data taken from an ethernet environment. Results show the algorithm to be fairly accurate despite its simplifying assumption that the arrival process of the data packets is Poisson; for about 2/3 of the queues analyzed, the ratio of the root mean square difference between the real queue and the estimated queue to the average real queue is less than 1/2.
Measurable characteristics of reusable Ada software
Authors: St. Dennis R. , Stachour P. , Frankowski E. , Onuegbe E.
Published: October 2004

Use of reusable software is key to significant gains in programmer productivity. However, in order to effectively develop it, measurable characteristics of reusability supported by guidelines for implementing them in source code are necessary. This paper describes an ongoing research project at the Honeywell Computer Sciences Center (CSC) to define these characteristics as well as specific guidelines for implementing them in Ada software.
Effective use of abort in programming mode changes
Authors: Burns A. , Quiggle T. J.
Published: October 2004

Mode changes are a crucial characteristic of a number of real-time systems. Ada does not easily deal with these events and hence it has been argued that language changes are required; in particular the introduction (or strictly speaking the re-introduction) of asynchronous exceptions. In this paper we present an idiom for programming mode changes. Moreover we argue that this structure can be implemented efficiently.
System object model (SOM) and Ada
Authors: Castellano G. Vincent
Published: October 2004

IBM's system object Model (SOM) provides a powerful toolset for
building object-oriented applications in multiple languages on multiple platforms. It is fully compliant with the Object Management Group's (OMG) Common Request Broker Architecture (CORBA). OC System' PowAda product allows Ada95 programmers “first-class” access to SOM. This article describes the use of SOM classes to build a simple “groupware” application in Ada95.
A reusable Ada package for scientific dimensional integrity
Authors: Macpherson George W.
Published: October 2004

Abstract -- Our recent experience in operations Desert Shield and Desert Storm has clearly demonstrated the criticality of software reliability end that truly reliable software Is indeed possible. One tool we can employ to enhance our software reliability is the classic scientific computational reliability technique of dimensional integrity, or unite checking. The Ads programming language makes it easy to implement units checking. A PHYSICAL_QUANTITY type Is declared which ham entries for both the floating point numeric value of s variable, and Integer entries for exponents of the fundamental physical unite of mass, length, and time. The Ads feature of "operator overloading" allows creation of symbols to porters arithmetic and relational operations on these variables . For example, the multiplication operation "*" ie overloaded eo that the numeric values of the two operande are multiplied, and the exponents of their fundamental units are added. An ASSIGN function Is then written to check that the units computed in an expression are equal to the units of the variable to which s new numeric value is assigned. Further reliability ie added by "information hiding" through limited private types, and reusability and modifiability are added by making the package generic. For scientific software, this generic package is as reusable as package Standard.
Crusade for a better notation
Authors: Brassard Gillea
Published: October 2004

In a well-known SIGACT/NEWS paper, Knuth sets forth the asymptotic notation by which we all now live [K76]. He closes his discussion with: "I propose that members of SIGACT (...) adopt the
O
, Ω and Θ notations as defined above, unless a better alternative can be found reasonably soon". Although one can hardly consider nearly a full decade later as being "reasonably soon", I would like to share with you my thoughts on the subject.
A practical turing machine representation
Authors: Nirenberg Robert M.
Published: October 2004

A tool is presented for research work on Turing machines and other abstract programming models. This tool is based on the use of the Recursive Function Algorithmic Language (Refal). A short background of this language is presented. Examples are given as to how this language may be useful for running simulations of Turing machines, and how it may be useful for the researcher into abstract machines.
Updating elements of a collection in place
Authors: Cohen Ellis S.
Published: October 2004

There are many data structures which store an object and provide a
handle
which may subsequently be used to identify the object stored. Ada makes it difficult to treat these data structures, which we call collections, in a general way. More specifically, without providing some knowledge of the internal structure of the collection, it is hard to provide the user of the collection with facilities for updating an element of the collection in place. This paper discusses some of the difficulties and then, through a sequence of solved problems, shows how such facilities can be constructed.
Protection in a distributed document processing system
Authors: Oliver Roger
Published: October 2004

A method of handling form-like documents is discussed. Documents which are protected from unauthorised access by encrypted checksums can be freely passed around a distributed, heterogeneous computer system. Multiple servers support multiple document types. A document may have several versions permitting parallel processing with optimistic concurrency control. Access control lists were found to be more suitable than capability-based schemes. Access control lists stored within the document (and protected by the checksum) were found to be useful in not requiring all servers to have information on all current instances of a document type and in permitting different document versions to have different ACLs. This allowed closer adherence to the principle of least privilege. Copyable access rights are supported to permit the flexible sharing thought most suitable for the application. The ability to audit the processing of a document was found to effect the choice of access control mechanism.
ICHU model for processor allocation in distributed operating systems
Authors: Shriram Alok , Sarangi Anuraag , S. Avinash
Published: October 2004

Process management techniques in distributed systems have been studied for decades. The general trend of the techniques rests upon a "Help Me" procedure wherein a processor which needs to migrate a process to a remote machine does so by locating a lesser loaded processor and transmitting the new process to it. In this paper we propose a new model that relies on the "I Can Help You" (ICHU) methodology of processor allocation. We take a look at the issues involved in deciding upon a suitable processor for transmission of a process in a heterogeneous network. A hypothetical scenario for the implementation of the theory and an algorithmic analysis are provided. Collective management as illustrated here provides a simpler, and more flexible approach to the problem rather than a single-handed approach.
Comparison of network protocol and architecture for distributed virtual simulation environment
Authors: Lee Bu-Sung , Cai Wen-Tong , Turner Stephen J. , Koh Jit-Beng
Published: October 2004

In any distributed virtual simulation environment, the underlying network architecture and its protocols play an important part in its performance. This paper describes the different underlying protocols used in the support of the RTI implementation in the Federated Simulations Development Kit (FDK). The communication FM and MCAST modules were modified to support different protocols. The performance of two different protocols: TCP and a new Lightweight Reliable Multicast, called Pseudo Reliable Multicast Protocol (PRMP), running on top of two different network architectures Ethernet and Asynchronous Transfer Mode (ATM) were compared. The latter protocol was developed specifically to support the distributed virtual simulation environment. Furthermore, in the case of the ATM network architecture, the use of native ATM-API was also implemented and its performance compared with the other protocols. The benchmarks used to compare their performance are Latency and Time Advance Request Benchmark. The results show that PRMP outperforms the other protocol techniques when the number of subscribers are large and when the bandwidth is limited. But it has some additional latency overhead, due to additional processing required to provide the reliability needed by the sender and receivers. Comparing the network architecture, the benchmark performance of the above protocols operating on top of 100BaseT switch network performs much better than over ATM network, although the transmission speed is much higher in the case of the latter.
Communication scheduling
Authors: Mattson Peter , Dally William J. , Rixner Scott , Kapasi Ujval J. , Owens John D.
Published: October 2004

The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect between functional units and register files. Communication scheduling enables scheduling to these emerging architectures, including those that use shared buses and register file ports. Scheduling to these shared interconnect architectures is difficult because it requires simultaneously allocating functional units to operations and buses and register file ports to the communications between operations. Prior VLIW scheduling algorithms are limited to clustered register file architectures with no shared buses or register file ports. Communication scheduling extends the range of target architectures by making each communication explicit and decomposing it into three components: a write stub, zero or more copy operations, and a read stub. Communication scheduling allows media processing kernels to achieve 98% of the performance of a central register file architecture on a distributed register file architecture with only 9% of the area, 6% of the power consumption, and 37% of the access delay, and 120% of the performance of a clustered register file architecture on a distributed register file architecture with 56% of the area and 50% of the power consumption.
System architecture directions for networked sensors
Authors: Hill Jason , Szewczyk Robert , Woo Alec , Hollar Seth , Culler David , Pister Kristofer
Published: October 2004

Technological progress in integrated, low-power, CMOS communication devices and sensors makes a rich design space of networked sensors viable. They can be deeply embedded in the physical world and spread throughout our environment like smart dust. The missing elements are an overall system architecture and a methodology for systematic advance. To this end, we identify key requirements, develop a small device that is representative of the class, design a tiny event-driven operating system, and show that it provides support for efficient modularity and concurrency-intensive operation. Our operating system fits in 178 bytes of memory, propagates events in the time it takes to copy 1.25 bytes of memory, context switches in the time it takes to copy 6 bytes of memory and supports two level scheduling. The analysis lays a groundwork for future architectural advances.
Power aware page allocation
Authors: Lebeck Alvin R. , Fan Xiaobo , Zeng Heng , Ellis Carla
Published: October 2004

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory is a particularly important target for efforts to improve energy efficiency. Memory technology is becoming available that offers power management features such as the ability to put individual chips in any one of several different power modes. In this paper we explore the interaction of page placement with static and dynamic hardware policies to exploit these emerging hardware features. In particular, we consider page allocation policies that can be employed by an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation environments: a trace-driven simulator with workload traces that are representative of mobile computing and an execution-driven simulator with a detailed processor/memory model and a more memory-intensive set of benchmarks (SPEC2000). Our results make a compelling case for a cooperative hardware/software approach for exploiting power-aware memory, with down to as little as 45% of the Energy• Delay for the best static policy and 1% to 20% of the Energy• Delay for a traditional full-power memory.
Thread-level parallelism and interactive performance of desktop applications
Authors: Flautner Kristián , Uhlig Rich , Reinhardt Steve , Mudge Trevor
Published: October 2004

Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear for desktop applications. Nevertheless, architects are designing processors that count on the availability of thread-level parallelism. Unlike server workloads, the primary requirement of interactive applications is to respond to user events under human perception bounds rather than to maximize end-to-end throughput. In this paper we report on the thread-level parallelism and interactive response time of a variety of desktop applications. By tracking the communication between tasks, we can focus our measurements on the portions of the benchmark's execution that have the greatest impact on the user. We find that running our benchmarks on a dual-processor machine improves response time of mouse-click events by as much as 36% and 22% on average---out of a maximum possible 50%. The benefits of multiprocessing are even more apparent when background tasks are considered. In our experiments, running a simple MP3 playback program in the background increases response time by 14% on a uniprocessor while it only increases the response time on a dual processor by 4%. When response times are fast enough for further improvements to be imperceptible, the increased idle time after interactive episodes could be exploited to build systems that are more power efficient.
Effective null pointer check elimination utilizing hardware trap
Authors: Kawahito Motohiro , Komatsu Hideaki , Nakatani Toshio
Published: October 2004

We present a new algorithm for eliminating null pointer checks from programs written in Java™. Our new algorithm is split into two phases. In the first phase, it moves null checks backward, and it is iterated for a few times with other optimizations to eliminate redundant null checks and maximize the effectiveness of other optimizations. In the second phase, it moves null checks forward and converts many null checks to hardware traps in order to minimize the execution cost of the remaining null checks. As a result, it eliminates many null checks effectively and exploits the maximum use of hardware traps. This algorithm has been implemented in the IBM cross-platform Java Just-in-Time (JIT) compiler. Our experimental results show that our approach improves performance by up to 71% for jBYTEmark and up to 10% for SPECjvm98 over the previously known best algorithm. They also show that it increases JIT compilation time by only 2.3%. Although we implemented our algorithm for Java, it is also applicable for other languages requiring null checking.
Frequent value locality and value-centric data cache design
Authors: Zhang Youtao , Yang Jun , Gupta Rajiv
Published: October 2004

By studying the behavior of programs in the SPECint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the
frequent value locality,
according to which a few values appear very frequently in memory locations and are therefore involved in a large fraction of memory accesses. In these six programs ten distinct values occupy over 50% of all memory locations and on an average account for nearly 50% of all memory accesses during program execution. This observation holds for smaller blocks of consecutive memory locations and the set of frequent values remains quite stable over the execution of the program.In the six benchmarks with frequent value locality, on an average 50% of all cache misses occur during the reading or writing of the ten most frequently accessed values. We propose a new data cache structure, the
frequent value cache
(FVC), which employs a
value-centric
approach to caching data locations for exploiting the frequent value locality phenomenon. FVC is a small direct-mapped cache which is dedicated to holding only frequently occurring values. The value-centric nature of FVC enables us to store data in a compressed form where the compression is achieved by encoding the frequent values using a few bits. Moreover this simple compression scheme preserves the random access to data values in a cache line.Our experiments demonstrate that by augmenting a direct mapped cache (DMC) with a direct mapped FVC of size no more than 3 Kbytes we can obtain reductions in miss rates ranging from 1% to 68%. In fact we observed that higher reductions in miss rates can he achieved by augmenting a DMC with a small FVC as opposed to doubling the size of DMC for the 124.m88ksim and 134.perl benchmarks.
OS and compiler considerations in the design of the IA-64 architecture
Authors: Zahir Rumi , Ross Jonathan , Morris Dale , Hess Drew
Published: October 2004

Increasing demands for processor performance have outstripped the pace of process and frequency improvements, pushing designers to find ways of increasing the amount of work that can be processed in parallel. Traditional RISC architectures use hardware approaches to obtain more instruction-level parallelism, with the compiler and the operating system (OS) having only indirect visibility into the mechanisms used.The IA-64 architecture [14] was specifically designed to enable systems which create and exploit high levels of instruction-level parallelism by explicitly encoding a program's parallelism in the instruction set [25]. This paper provides a qualitative summary of the IA-64 architecture features that support control and data speculation, and register stacking. The paper focusses on the functional synergy between these architectural elements (rather than their individual performance merits), and emphasizes how they were designed for cooperation between processor hardware, compilers and the OS.
A cost-effective, high-bandwidth storage architecture
Authors: Gibson Garth A. , Nagle David F. , Amiri Khalil , Butler Jeff , Chang Fay W. , Gobioff Howard , Hardin Charles , Riedel Erik , Rochberg David , Zelenka Jim
Published: October 2004

This paper describes the Network-Attached Secure Disk (NASD) storage architecture, prototype implementations oj NASD drives, array management for our architecture, and three, filesystems built on our prototype. NASD provides scalable storage bandwidth without the cost of servers used primarily, for transferring data from peripheral networks (e.g. SCSI) to client networks (e.g. ethernet). Increasing datuset sizes, new attachment technologies, the convergence of peripheral and interprocessor switched networks, and the increased availability of on-drive transistors motivate and enable this new architecture. NASD is based on four main principles: direct transfer to clients, secure interfaces via cryptographic support, asynchronous non-critical-path oversight, and variably-sized data objects. Measurements of our prototype system show that these services can be cost-effectively integrated into a next generation disk drive ASK. End-to-end measurements of our prototype drive andfilesysterns suggest that NASD cun support conventional distributed filesystems without performance degradation. More importantly, we show scaluble bandwidth for NASD-specialized filesystems. Using a parallel data mining application, NASD drives deliver u linear scaling of 6.2 MB/s per clientdrive pair, tested with up to eight pairs in our lab.
Performance counters and state sharing annotations
Authors: Weissman Boris
Published: October 2004

This paper describes a combined approach for improving thread locality that uses the bardware performance monitors of modem processors and program-centric code annotations to guide thread scheduling on SMPs. The approach relies on a shared state cache model to compute expected thread footprints in the cache on-line. The accuracy of the model has been analyzed by simmations involving a set of parallel applications. We demonstrate how the cache model can be used to implement several practical locality-based thread scheduling policies with little overhead. Active Threads, a portable, high-performance thread system, has been built and used to investigate the performance impact of locality scheduling for several applications.