Wafer Scale Graphene Field Effect Transistors on Thin Thermal Oxide
Authors: Ravichandran Arul Vigneswar , Lee Jaebeom , Cheng Lanxia , Lucero Antonio Tomas , Colombo Luigi , Young Chadwin D , Venugopal Archana , Polley Arup , Kim Jiyoung 
Published: February 2020

Graphene, an allotrope of carbon, shows ambipolar transfer characteristics with a linear dispersion relation where the conduction and valence band meets at the Dirac point 1. Owing to an absence of bandgap, it is not feasible to use graphene in logic applications though it is possible to use graphene in analog and RF circuits2. Significant efforts towards the growth and transfer of graphene onto arbitrary substrates 3
4
,
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6 has made it feasible to scale up graphene device fabrication – early focus on single, exfoliated devices has given way to large area, many-device wafers. From a practical standpoint, a lower operating voltage range, minimal unintentional doping of graphene during processing, and excellent device stability at room temperature is required. Most of the earlier graphene based devices were fabricated on thick (90nm or higher) thermal SiO2 substrate as they provide a better optical contrast after transferring graphene. Unfortunately, this attributes to a higher operating voltage in order to modulate the graphene device. In this work, we demonstrate the feasibility of making devices on thin, 10 nm thermal SiO­2 gate dielectric using CVD graphene with minimal shift in the Dirac point and excellent stability during subsequent operation cycles in air at room temperature. The 10nm thermal SiO2 has a breakdown field of ~9.7MV/cm and mobilities as high as 2200 cm2/V·S is achieved in a relatively small operating voltage (±8V). A higher mobility is typically seen for devices located at the center of the transferred graphene region. The 10nm dielectric used in our process is challenging for integration since graphene cannot be visually inspected during device fabrication, but we have overcome this limitation by implementing specialized characterization steps that allow us to monitor the graphene. A lower contact resistivity of 500 Ω-µm and sheet resistance (RSh) of 400Ω/□ is observed at a higher doping level achieved by applying a fixed back gate bias with Ni/Au contact. A similar trend is seen in the RSh extracted from a more appropriate test structure (Van der Pauw), wherein there is a minimal metal contact overlap with graphene. The hysteresis for these graphene devices are consistently less than or equal to 0.3V within the ± 8V sweeping voltage range. Therefore, we demonstrate the fabrication of wafer scale graphene devices with excellent process control on thin dielectric substrate with minimal doping and trapped charge. This could pave way for realization of high performance, low power consuming nanoelectronics with graphene.

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