bluuebunny/crossref_metadata_2025 huggingface dataset:
Model driven development of secure XML databases
Authors: Vela Belén , Fernández-Medina Eduardo , Marcos Esperanza , Piattini Mario
Published: January 2007

In this paper, we propose a methodological approach for the model driven development of secure XML databases (DB). This proposal is within the framework of MIDAS, a model driven methodology for the development of Web Information Systems based on the Model Driven Architecture (MDA) proposed by the Object Management Group (OMG) [20]. The XML DB development process in MIDAS proposes using the data conceptual model as a Platform Independent Model (PIM) and the XML Schema model as a Platform Specific Model (PSM), with both of these represented in UML. In this work, such models will be modified, so as to be able to add security aspects if the stored information is considered as critical. On the one hand, the use of a UML extension to incorporate security aspects at the conceptual level of secure DB development (PIM) is proposed; on the other, the previously-defined XML schema profile will be modified, the purpose being to incorporate security aspects at the logical level of the secure XML DB development (PSM). In addition to all this, the semi-automatic mappings from PIM to PSM for secure XML DB will be defined.
PicoServer
Authors: Kgil Taeho , D'Souza Shaun , Saidi Ali , Binkert Nathan , Dreslinski Ronald , Mudge Trevor , Reinhardt Steven , Flautner Krisztian
Published: January 2007

In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die containing several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency in turn reduces power and means that thermal constraints, a concern with 3D stacking, are easily satisfied.The PicoServer architecture specifically targets Tier 1 server applications, which exhibit a high degree of thread level parallelism. An architecture targeted to efficient throughput is ideal for this application domain. We find for a similar logic die area, a 12 CPU system with 3D stacking and no L2 cache outperforms an 8 CPU system with a large on-chip L2 cache by about 14% while consuming 55% less power. In addition, we show that a PicoServer performs comparably to a Pentium 4-like class machine while consuming only about 1/10 of the power, even when conservative assumptions are made about the power consumption of the PicoServer.
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
Authors: Gordon Michael I. , Thies William , Amarasinghe Saman
Published: January 2007

As multicore architectures enter the mainstream, there is a pressing demand for high-level programming models that can effectively map to them. Stream programming offers an attractive way to expose coarse-grained parallelism, as streaming applications (image, video, DSP, etc.) are naturally represented by independent filters that communicate over explicit data channels.In this paper, we demonstrate an end-to-end stream compiler that attains robust multicore performance in the face of varying application characteristics. As benchmarks exhibit different amounts of task, data, and pipeline parallelism, we exploit all types of parallelism in a unified manner in order to achieve this generality. Our compiler, which maps from the StreamIt language to the 16-core Raw architecture, attains a 11.2x mean speedup over a single-core baseline, and a 1.84x speedup over our previous work.
Recording shared memory dependencies using strata
Authors: Narayanasamy Satish , Pereira Cristiano , Calder Brad
Published: January 2007

Significant time is spent by companies trying to reproduce and fix bugs. BugNet and FDR are recent architecture proposals that provide architecture support for deterministic replay debugging. They focus on continuously recording information about the program's execution, which can be communicated back to the developer. Using that information, the developer can deterministically replay the program's execution to reproduce and fix the bugs.In this paper, we propose using
Strata
to efficiently capture the shared memory dependencies. A stratum creates a time layer across all the logs for the running threads, which separates all the memory operations executed before and after the stratum. A strata log allows us to determine all the shared memory dependencies during replay and thereby supports deterministic replay debugging for multi-threaded programs.
Accelerator
Authors: Tarditi David , Puri Sidd , Oglesby Jose
Published: January 2007

GPUs are difficult to program for general-purpose uses. Programmers can either learn graphics APIs and convert their applications to use graphics pipeline operations or they can use stream programming abstractions of GPUs. We describe Accelerator, a system that uses data parallelism to program GPUs for general-purpose uses instead. Programmers use a conventional imperative programming language and a library that provides only high-level data-parallel operations. No aspects of GPUs are exposed to programmers. The library implementation compiles the data-parallel operations on the fly to optimized GPU pixel shader code and API calls.We describe the compilation techniques used to do this. We evaluate the effectiveness of using data parallelism to program GPUs by providing results for a set of compute-intensive benchmarks. We compare the performance of Accelerator versions of the benchmarks against hand-written pixel shaders. The speeds of the Accelerator versions are typically within 50% of the speeds of hand-written pixel shader code. Some benchmarks significantly outperform C versions on a CPU: they are up to 18 times faster than C code running on a CPU.
Hybrid transactional memory
Authors: Damron Peter , Fedorova Alexandra , Lev Yossi , Luchangco Victor , Moir Mark , Nussbaum Daniel
Published: January 2007

Transactional memory (TM) promises to substantially reduce the difficulty of writing correct, efficient, and scalable concurrent programs. But "bounded" and "best-effort" hardware TM proposals impose unreasonable constraints on programmers, while more flexible software TM implementations are considered too slow. Proposals for supporting "unbounded" transactions in hardware entail significantly higher complexity and risk than best-effort designs.We introduce
Hybrid Transactional Memory
(HyTM), an approach to implementing TMin software so that it can use best effort hardware TM (HTM) to boost performance but does not
depend
on HTM. Thus programmers can develop and test transactional programs in existing systems today, and can enjoy the performance benefits of HTM support when it becomes available.We describe our prototype HyTM system, comprising a compiler and a library. The compiler allows a transaction to be attempted using best-effort HTM, and retried using the software library if it fails. We have used our prototype to "transactify" part of the Berkeley DB system, as well as several benchmarks. By disabling the optional use of HTM, we can run all of these tests on existing systems. Furthermore, by using a simulated multiprocessor with HTM support, we demonstrate the viability of the HyTM approach: it can provide performance and scalability approaching that of an unbounded HTM implementation, without the need to support all transactions with complicated HTM support.
Combinatorial sketching for finite programs
Authors: Solar-Lezama Armando , Tancau Liviu , Bodik Rastislav , Seshia Sanjit , Saraswat Vijay
Published: January 2007

Sketching is a software synthesis approach where the programmer develops a partial implementation - a sketch - and a separate specification of the desired functionality. The synthesizer then completes the sketch to behave like the specification. The correctness of the synthesized implementation is guaranteed by the compiler, which allows, among other benefits, rapid development of highly tuned implementations without the fear of introducing bugs.We develop SKETCH, a language for finite programs with linguistic support for sketching. Finite programs include many highperformance kernels, including cryptocodes. In contrast to prior synthesizers, which had to be equipped with domain-specific rules, SKETCH completes sketches by means of a combinatorial search based on generalized boolean satisfiability. Consequently, our combinatorial synthesizer is complete for the class of finite programs: it is guaranteed to complete any sketch in theory, and in practice has scaled to realistic programming problems.Freed from domain rules, we can now write sketches as simpleto-understand partial programs, which are regular programs in which difficult code fragments are replaced with
holes
to be filled by the synthesizer. Holes may stand for index expressions, lookup tables, or bitmasks, but the programmer can easily define new kinds of holes using a single versatile synthesis operator.We have used SKETCH to synthesize an efficient implementation of the AES cipher standard. The synthesizer produces the most complex part of the implementation and runs in about an hour.
Mapping esterel onto a multi-threaded embedded processor
Authors: Li Xin , Boldt Marian , von Hanxleden Reinhard
Published: January 2007

The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage.This paper presents a reactive processor, the Kiel Esterel Processor 3a (KEP3a), and its compiler. The KEP3a improves on earlier designs in several areas; most notable are the support for exception handling and the provision of context-dependent preemption handling instructions. The KEP3a compiler presented here is to our knowledge the first for multi-threaded reactive processors. The translation of Esterel's preemption constructs onto KEP3a assembler is straightforward; however, a challenge is the correct and efficient representation of Esterel's concurrency. The compiler generates code that respects data and control dependencies using the KEP3a priority-based scheduling mechanism. We present a priority assignment approach that makes use of a novel concurrent control flow graph and has a complexity that in practice tends to be linear in the size of the program. Unlike earlier Esterel compilation schemes, this approach avoids unnecessary context switches by considering each thread's actual execution state at run time. Furthermore, it avoids code replication present in other approaches.
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance
Authors: Reddy Vimal K. , Rotenberg Eric , Parthasarathy Sailashri
Published: January 2007

Redundant threading architectures duplicate all instructions to detect and possibly recover from transient faults. Several lighter weight Partial Redundant Threading (PRT) architectures have been proposed recently. (i) Opportunistic Fault Tolerance duplicates instructions only during periods of poor single-thread performance. (ii) ReStore does not explicitly duplicate instructions and instead exploits mispredictions among highly confident branch predictions as symptoms of faults. (iii) Slipstream creates a reduced alternate thread by replacing many instructions with highly confident predictions. We explore PRT as a possible direction for achieving the fault tolerance of full duplication with the performance of single-thread execution. Opportunistic and ReStore yield partial coverage since they are restricted to using only partial duplication or only confident predictions, respectively. Previous analysis of Slipstream fault tolerance was cursory and concluded that only duplicated instructions are covered. In this paper, we attempt to better understand Slipstream's fault tolerance, conjecturing that the mixture of partial duplication and confident predictions actually closely approximates the coverage of full duplication. A thorough dissection of prediction scenarios confirms that faults in nearly 100% of instructions are detectable. Fewer than 0.1% of faulty instructions are not detectable due to coincident faults and mispredictions. Next we show that the current recovery implementation fails to leverage excellent detection capability, since recovery sometimes initiates belatedly, after already retiring a detected faulty instruction. We propose and evaluate a suite of simple microarchitectural alterations to recovery and checking. Using the best alterations, Slipstream can recover from faults in 99% of instructions, compared to only 78% of instructions without alterations. Both results are much higher than predicted by past research, which claims coverage for only duplicated instructions, or 65% of instructions. On an 8-issue SMT processor, Slipstream performs within 1.3% of single-thread execution whereas full duplication slows performance by 14%.A key byproduct of this paper is a novel analysis framework in which every dynamic instruction is considered to be hypothetically faulty, thus not requiring explicit fault injection. Fault coverage is measured in terms of the fraction of candidate faulty instructions that are directly or indirectly detectable before.
A spatial path scheduling algorithm for EDGE architectures
Authors: Coons Katherine E. , Chen Xia , Burger Doug , McKinley Kathryn S. , Kushwaha Sundeep K.
Published: January 2007

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called
spatial path scheduling
that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.
A defect tolerant self-organizing nanoscale SIMD architecture
Authors: Patwardhan Jaidev P. , Johri Vijeta , Dwyer Chris , Lebeck Alvin R.
Published: January 2007

The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing to the exponentially increasing cost of top-down lithography. Bottom-up manufacturing techniques, like self assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. Therefore, regardless of fabrication methodology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities.This paper explores a defect tolerant SIMD architecture. A key feature of our design is the ability of a large number of limited capability nodes with high defect rates (up to 30%) to self-organize into a set of SIMD processing elements. Despite node simplicity and high defect rates, we show that by supporting the familiar data parallel programming model the architecture can execute a variety of programs. The architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. On a medium sized system (~1cm
2
area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). For larger systems (>1cm
2
), the proposed architecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores.
A new idiom recognition framework for exploiting hardware-assist instructions
Authors: Kawahito Motohiro , Komatsu Hideaki , Moriyama Takao , Inoue Hiroshi , Nakatani Toshio
Published: January 2007

Modern processors support hardware-assist instructions (such as TRT and TROT instructions on IBM zSeries) to accelerate certain functions such as delimiter search and character conversion. Such special instructions have often been used in high performance libraries, but they have not been exploited well in optimizing compilers except for some limited cases. We propose a new idiom recognition technique derived from a topological embedding algorithm [4] to detect idiom patterns in the input program more aggressively than in previous approaches. Our approach can detect a pattern even if the code segment does not exactly match the idiom. For example, we can detect a code segment that includes additional code within the idiom pattern. We implemented our new idiom recognition approach based on the Java Just-In-Time (JIT) compiler that is part of the J9 Java Virtual Machine, and we supported several important idioms for special hardware-assist instructions on the IBM zSeries and on some models of the IBM pSeries. To demonstrate the effectiveness of our technique, we performed two experiments. The first one is to see how many more patterns we can detect compared to the previous approach. The second one is to see how much performance improvement we can achieve over the previous approach. For the first experiment, we used the Java Compatibility Kit (JCK) API tests. For the second one we used IBM XML parser, SPECjvm98, and SPCjbb2000. In summary, relative to a baseline implementation using exact pattern matching, our algorithm converted 75% more loops in JCK tests. We also observed significant performance improvement of the XML parser by 64%, of SPECjvm98 by 1%, and of SPECjbb2000 by 2% on average on a z990. Finally, we observed the JIT compilation time increases by only 0.32% to 0.44%.
Quality measures for embedded systems and their application to control and certification
Authors: Rohloff Kurt , Loyall Joseph , Schantz Richard
Published: January 2007

Distributed, real-time embedded (DRE) systems, such as that being developed under the DARPA Adaptive Reflective Middleware System (ARMS) program, require predictable, controlled real-time behavior. It is a challenge to develop ways to measure and evaluate the quality, or utility, of DRE system performance in the context of the dynamic, unpredictable environments in which they operate. This difficulty runs hand-in-hand with the challenge of providing adequate control of the system to effect behavior in the system that will allow the controlled system to be certified as exhibiting correct behavior. As part of the ARMS program, we have been developing utility-based measures of system quality for assessing correct behavior of a system and for driving feedback control at runtime. This paper describes the real-time utility measures we have developed for ARMS and their use as feedback signals to a control system that manages the dynamic allocation of resources to applications in the system. We then explore the issues associated with using utility-based assessment as part of an evidence-based certification process for dynamic real-time systems.
Barriers facing women in the IT work force
Authors: Riemenschneider Cynthia K. , Armstrong Deborah J. , Allen Myria W. , Reid Margaret F.
Published: January 2007

The percentage of women working in Information Technology (IT) is falling as revealed by the 2003 Information Technology Association of America (ITAA) Blue Ribbon Panel on Information Technology (IT) Diversity report; the percentage of women in the IT workforce fell to 34.9% in 2002 down from 41% in 1996. Several studies have indicated this issue is reaching a crisis level and needs to be explored. Women working in IT at a Fortune 500 company were asked what workplace barriers they faced that had influenced their voluntary turnover decisions or the decisions of their female counterparts. Revealed causal mapping was used to evoke representations of the cognitions surrounding the barriers women face in the IT field. A causal map was developed that indicated women's actual turnover was linked to their views of their family responsibilities, the stresses they face within the workplace, various qualities of their jobs, and the flexibility they were given to determine their work schedule. Their statements regarding the barriers they faced in terms of promotion opportunities (both perceived and actual) were linked to the same four concepts. Interestingly, there was no link between promotion opportunities and voluntary turnover. Reciprocal relationships were identified between managing family responsibility and stress, work schedule flexibility and stress, managing family responsibility and job qualities, and job qualities and stress. Discrimination and lack of consistency in how management treated employees, while important, were not central to how the women in this sample thought about issues related to promotion and voluntary turnover.
Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated
Authors: Shindi Rajaa S. , Cooper Shaun
Published: January 2007

Building state-of-the-art processors is expensive and time consuming. Once the design is finalized and implemented, simulations are used to evaluate functionality and performance of the system. The Sim-alpha processor simulator is one of the most important tools for performance evaluations. Enhancing processor simulators is one of the major research field and many studies are underway related to this area. Current, open source, processor simulators do not account for the influences caused by multi-processing. In this study, we had shown that most processor simulations only test one program at a time on a virtual processor. The goal of the project was to demonstrate how processor simulators work when external influences are incorporated. Hardware or software interrupts are events that alter sequence of instructions executed by a processor. A context switch occurs when a multitasking operating system suspends the currently running process, and starts executing another. An additional code was added to the Sim-alpha program to allow for context switch. Benchmarks were executed with and without time slice context switch as well as different time slices. The results had shown that when the number of cycles before flushing the cache increases, the miss rate will decrease. For example if we are flushing the cache every 150 cycles, the cache miss rate is 48% compare to 2% without flushing the cache. The effect of flushing the cache is significant on the cache performance of processor simulators. In real life environments, processor must support multiple processes. We demonstrated with a simple change in the code that these simulators can have a more realistic workload. The effect of flushing the cache is significant on the cache performance of processor simulators. Current models do not account for this and may over estimate the performance gains of a particular processor design.
Integrating Ada 2005 into visual studio 2005
Authors: Carlisle Martin C. , Hamilton J. A.
Published: January 2007

In this paper, we describe the integration of an Ada 2005 compiler into Microsoft's 2005 Visual Studio and its implications for the Ada community and beyond.
Catch that speeding turtle
Authors: Markow Tanya , Ressler Eugene , Blair Jean
Published: January 2007

Graphics are a great way to keep students motivated early in a computer science program. This paper introduces a simple Ada graphics package that simultaneously meets two goals: it provides a easy to understand graphics package that leads to enjoyable projects in CS1, and it is an appropriate tool for teaching fundamental computer science concepts to beginning programmers. The package is an Ada implementation and extension of a Java TutleGraphics package used at a number of universities.
Schizophrenic middleware support for fault tolerance
Authors: Barbaria Khaled , Pautet Laurent , Perseil Isabelle
Published: January 2007

In this paper, we identify the middleware functionnalities andproperties that are required to efficiently implement the FaultTolerant CORBA specification. Our approach relies on certainproperties of PolyORB, our schizophrenic middleware to provide CORBA-based applications with fault tolerance. Our approach isvalidated by performance measures for the stateful replication stylesdefined in the standard and for the failure detection and notificationinfrastructure. Even if our current full Ada95 implementation requiresan optimization phase, it exhibits acceptable performances, compared toexisting implementations of this standard.
Time horizon in distributed object societies
Authors: Sotirovski Drasko
Published: January 2007

In a distributed system, it takes time for a software event to reach remote clients. In the same sense as used in physics, only when the event had reached the time horizon of a client, client becomes aware of it. Using this metaphor , we have developed a simple yet powerful model for software components to get back in sync after interruptions. The ideas described in this paper have been implemented on En Route Automation Modernization (ERAM) program, a Federal Aviation Administration (FAA) effort aimed at replacing the aging en route assets and planting a seed for the many future enhancements that the projected increase in air traffic requires. In many ways, this paper is a compendium to another paper at this same conference titled Publisher Framework (PFW), because it is within the auspices of PFW that these ideas have been implemented.
SPEC CPU2006 benchmark descriptions
Authors: Henning John L.
Published: January 2007

On August 24, 2006, the Standard Performance Evaluation Corporation (SPEC) announced CPU2006 [2], which replaces CPU2000. The SPEC CPU benchmarks are widely used in both industry and academia [3].
Masters level accreditation for information systems
Authors: Gorgone John T.
Published: January 2007

Is there a need to accredit graduate level programs in information systems and technology? The Association for Information Systems (AIS) seems to think so as it has expressed an interest in pursuing masters' level accreditation for information systems programs globally in the very near future. There is considerable value for AIS in taking this bold initiative. They currently participate in undergraduate computing accreditation through ABET via their membership and financial support of CSAB (AIS+ACM+IEEE-CS). Also, AIS is familiar with graduate level accreditation because of their involvement with AACSB International which accredits programs in the school of business at all levels.
Hidden squares
Authors: Ginat David
Published: January 2007

The current issue's new challenge involves lines of sight and objects (squares) in the plane. One may get the impression that Computational Geometry familiarity is required. However, this is not the case. The presented task involves very basic domain knowledge, and the main theme is problem solving through suitable insight.
Avoiding the pratfalls of program assessment
Authors: Chewar C. M. , Huggins K. L. , Blair Jean R. S.
Published: January 2007

Most agree that assessment is an important step in improving an academic program. However, implementation often falls short of expectations due to common missteps. In this paper, we identify and discuss common program assessment pratfalls. We also describe the assessment program and the manner in which we have taken steps to avoid each of these pratfalls.
On the role of proofs in a course on design and analysis of algorithms
Authors: Armoni Michal
Published: January 2007

This paper discusses the role of proofs in a course on design and analysis of algorithms. It argues that correctness proofs should always be considered as an integral part of algorithmic solutions, which should otherwise be considered as incomplete. Proofs and proof strategies should be emphasized in such a course, and active proof production should be required of students. Such an emphasis can improve mathematical as well as algorithmic skills, and can demonstrate the important and unique role of mathematics within computer science.
Knowledge discovery and dissemination
Authors: Buerck John , Feig David
Published: January 2007

One area of IT quickly becoming paramount for organizations is the field of Informatics. Informatics is receiving some recognition as a sub-discipline within computer science education with the distinct learning objectives of how to use IT for knowledge discovery and dissemination. This paper describes the growing need for informatics education; a suggested informatics curriculum framework, specific course descriptions; options on how to incorporate informatics as a cognate option for other university programs.
Classroom exercise demonstrating linked list operations
Authors: Rolfe Timothy J.
Published: January 2007

This paper describes a strategy whereby, using directly manipulable items, one can show the behaviors of a linked list, and even show some of the details of linked list manipulations. The students themselves operate as the linked list nodes, and retain the attributes of data value and next list node.
Concept inventories in computer science for the topic discrete mathematics
Authors: Almstrum Vicki L. , Henderson Peter B. , Harvey Valerie , Heeren Cinda , Marion William , Riedesel Charles , Soh Leen-Kiat , Tew Allison Elliott
Published: January 2007

This report describes concept inventories, specialized assessment instruments that enable educational researchers to investigate student (mis)understandings of concepts in a particular domain. While students experience a concept inventory as a set of multiple-choice items taken as a test, this belies its purpose, its careful development, and its validation. A concept inventory is not intended to be a comprehensive instrument, but rather a tool that probes student comprehension of a carefully selected subset of concepts that give rise to the most common and pervasive mismodelings. The report explains how concept inventories have been developed and used in other STEM fields, then outlines a project to explore the feasibility of concept inventories in the computing field. We use the domain of discrete mathematics to illustrate a suggested plan of action.
Adversarial information retrieval on the web (AIRWeb 2006)
Authors: Davison Brian D. , Najork Marc , Converse Tim
Published: January 2007

The attraction of hundreds of millions of web searches per day provides significant incentive for many content providers to do whatever is necessary to rank highly in search engine results, while search engine providers want to provide the most accurate results. The conflicting goals of search and content providers are adversarial, and the use of techniques that push rankings higher than they belong is often called search engine spam. Such methods typically include textual as well as link-based techniques, or their combination.
An object-oriented Tower Of Babel
Authors: Nelson Michael L.
Published: January 2007

Like many new ideas, object-oriented programming (OOP) does not yet have a universally accepted definition. Even the terminology of OOP can vary greatly from one system to another. One might even say that we have created something of an object-oriented 'Tower of Babel'.While it is expected that the syntax will vary from one language to another, there is no logical reason for using identical terminology in completely differently ways. If OOP is to be accepted by the computer science community in general, then it is time to put our idiosyncrasies aside and at least agree on the basics.
Book review: Multiple Access Protocols: Performance and Analysis by Raphael Rom and Moshe Sidi (Springer-Verlag, 1990)
Authors: Finkel David
Published: January 2007

The author's central thesis is that responsiveness, or performance, is crucial to the success of software systems. Thus performance considerations must be a part of all stages of software development, starting from the earliest stages of design. The approach uses a combination of straightforward data collection and analysis, and mathematically sophisticated techniques. The mathematical treatment is entirely self-contained, and no extensive mathematical background is assumed.
The implementation of a model-based belief revision system
Authors: Chou Timothy S. C. , Winslett Marianne
Published: January 2007

In this paper, we briefly describe Immortal, an implementation of a model-based belief revision system. We present our motivation for building Immortal, describe its basic components and properties, and discuss our method of evaluating Immortal.
The evolution of CycL, the Cyc representation language
Authors: Lenat Douglas B. , Guha R. V.
Published: January 2007

CycL is the language in which the Cyc Knowledge Base is being encoded. This paper reviews some of the methodological considerations and the technical decisions (resulting from these considerations) that are both different from conventional thinking and that have significantly influenced the design of the language.
The BACK system—an overview
Authors: Peltason Christof
Published: January 2007

The BACK project was begun at the Technical University Berlin in January 1985 as part of a larger project within the ESPRIT programme
1
. Our task in the project group was the specification, design and implementation of a knowledge representation system which we called BACK ("Berlin Advanced Computational Knowledge Representation System"). It is a based on a terminological logic (term description language) and supports complex representation of a domain terminology, description of domain objects using that terminology, and database access via a uniform interface language.
Preface for Special Section on Integrated Cognitive Architectures
Authors: Laird John E.
Published: January 2007

Over the years, AI has divided itself into many subfields corresponding roughly to different components of intelligence such as planning, knowledge representation, learning, vision, robotics, natural language, and interaction with other agents. Although this division has allowed the field to make progress in understanding each of these components, it often ignores the issues involved in creating integrated systems that draw from more than one of these subfields. SHRDLU was an early example of the integration of planning and natural language, but in general we find ourselves with individual capabilities that are not integrated within a complete system.
A design for the ICARUS architecture
Authors: Langley Pat , McKusick Kathleen B. , Allen John A. , Iba Wayne F. , Thompson Kevin
Published: January 2007

We describe our designs for ICARUS, an integrated architecture for controlling an intelligent agent in a complex physical environment. By navigating between locations and manipulating other objects, the agent influences the world and achieves its goals. The architecture includes components for perceiving the environment, for generating plans to solve problems, and for executing the plans generated. A fourth component manages the agent's long-term memory. Our assessment of the design suggests that it is general, versatile, scales well to larger problems, and is consistent with a variety of psychological results.
The agent network architecture (ANA)
Authors: Maes Pattie
Published: January 2007

The goal of my work is to develop and implement an architecture for an autonomous agent, which I refer to as "ANA". An ANA agent consists of a distributed set of "competence modules". Competence modules are linked in a network. A spreading activation process operates on the network to decide what the "relevance" or relative strength of a competence module is in the current context. This process implements a competition among modules for activation energy. The higher the activation energy level of a module, the more likely it is that this module determines what the autonomous agent does or communicates to believe. Learning is a central, completely integrated feature of the architecture. The competence module network is continuously being developed and changed on the basis of experience: links are added and deleted depending on real world observations and new "macro modules" are created whenever a goal is achieved. This paper presents an overview of the architecture. It describes the functionalities that have been implemented, the results that have been obtained with robotic and simulated ANA agents, and finally it discusses (current) limitations and future work.
Integrating perception, language-handling, learning and planning in the CHILDLIKE system
Authors: Mani Ganesh , Uhr Leonard
Published: January 2007

In this paper, we highlight the importance of the integrated perceive-reason-act-learn loop, which appears to be central to intelligence, and describe a system that we are developing to capture this loop. As a first step, the system learns about simple objects, their qualities, and the words that name them and describe their parts and relations. The visual-linguistic associations formed act as a bias in acquiring further knowledge about actions, which in turn aids the system in satisfying its internal needs (e.g., hunger, thirst, sleep, curiosity). We briefly describe the components of the system and discuss some of the salient properties of the CHILDLIKE integrated architecture.
Taking design seriously
Authors: Karat John , Dayton Tom
Published: January 2007

A workshop was held in Seattle on April 1st in conjunction with the CHI'90 conference. The call for participation in the workshop asked for position papers from individuals that described techniques found useful in some way in carrying out HCI design. For the purpose of the workshop, an intentionally broad view of what was considered as a technique was used (e.g., position papers that addressed design process, task-analysis methodologies, and skills-necessary for design, were all considered as addressing techniques). In this report we present an overview of the workshop. Additional reports of subgroup discussions, focused on some of the major themes that emerged during the day, are presented in papers by Braudes, Hix and Casaday, Carter, and Notess.
Group HCI design
Authors: Catterall Bernard J. , Harker Susan , Klein Gary , Notess Mark , Tang John C.
Published: January 2007

Design of human-computer interfaces is typically carried out by groups of designers rather than by isolated individuals. In this report, we characterize those groups and their contexts, examine the problems that such groups encounter, and evaluate the extent to which current HCI techniques address the needs of groups of designers.
GEdit
Authors: Kurtenbach Gordon , Buxton Bill
Published: January 2007

GEdit is a prototype graphical editor that permits you to create and manipulate three simple types of objects using shorthand and proof-reader's type gestures. The three types of objects that can be manipulated are: squares, circles and triangles. Using hand-drawn symbols, the user can
add, delete, move-
and
copy
these objects. Objects can be manipulated individually or in groups. Groups are specified with hand-drawn circling symbols.
A maple program that finds, and proves, recurrences and differential equations satisfied by hyperexponential definite integrals
Authors: Almkvist Gert , Zeilberger Doron
Published: January 2007

In [A-Z] we described an algorithm that given a hyperexponential function of two variables
F
(
x,y
), produces a differential equation satisfied by[EQUATION]
The modelling and retrieval of documents using index expressions
Authors: Bruza P. D. , van der Weide T. P.
Published: January 2007

In this paper we introduce
Index Expressions
as a means for modelling document content. From an index expression the the Power Index Expression can be derived, which is a powerful instrument for information retrieval. We describe the characterization of documents in the style of formal logic. The content of a document is then modelled by a set of axioms, of which the document is a model. Relating a document to a query is done by proving the query from the axioms of that document. We introduce three rules of inference. If such a proof is not possible, the relevance of the document for the query is derived by
plausible deduction.
We introduce two inference rules for plausible deduction.
The HCI Bibliography project
Authors: Perlman Gary
Published: January 2007

The HCI Bibliography project has just released its first collections of a free-access online extended bibliography on Human-Computer Interaction. The basic goal of the project is to put an online bibliography for most of HCI on the screens of all researchers and developers in the field through anonymous ftp access, mail servers, and Mac and DOS floppy disks. Through the efforts of volunteers, the bibliography is approaching 1000 entries, with abstracts and/or tables of contents; eventually, citation information and hypertext access will be added. The first release contains the complete contents of all the ACM CHI conference, the complete journal Human-Computer Interaction, and several other important sources. Eventually, all of HCI will be online and freely accessible around the world.
Interactive posters
Authors: Czerwinski Mary , Chrisman Steve , Schumacher Bob
Published: January 2007

Operators are often required to perform concurrent tasks, as well as attend to additional information (e.g., emergencies, changes of plans). This additional information has a tendency to interrupt the human operator's primary duties, requiring the operator to delay completion of these duties until a later time. Two experiments examined the effects of display similarity and the presence or absence of a warning on an operator's ability to remember information from (and hence, resume) multiple primary tasks. It was hypothesized that subjects' performance would be worse when interrupted by a task that was more similar to the primary task. It was also hypothesized that subjects would benefit from a warning prior to the interruption. In experiment 1, subjects monitored information from 4 different space station systems. After 4 minutes, an interrupting task replaced the information on the computer screen. Subjects were either warned or not warned of the upcoming interruption 30 seconds prior to its onset. The interruption task was either similar or dissimilar in display format to the primary task.
EMPIRICISM VERSUS JUDGEMENT
Authors: Desurvire Heather , Lawrence Debbie , Atwood Michael
Published: January 2007

In an attempt to reduce the time and cost of laboratory usability testing, new techniques for evaluating user interfaces are being developed by human factors researchers. In one such technique, heuristic evaluation (Nielsen and Molich, 1990), experts evaluate interfaces using pre-established usability guidelines. The current study attempts to test the heuristic method of evaluation under several conditions and user interface (UI) experts' "best guess" predictions, for comparing to laboratory performance testing results.
AN AFTER-SCENARIO QUESTIONNAIRE FOR USABILITY STUDIES
Authors: Lewis James R.
Published: January 2007

The purpose of this report is to (1) describe a psychometric evaluation of a printer scenario questionnaire (PSQ) that was used to assess user satisfaction during scenario-based usability studies of printers and (2) compare the psychometric properties of the PSQ with those of the After-Scenario Questionnaire (ASQ) (Lewis, 1991b). The PSQ is similar to the ASQ, but is composed of three five-point scales rather than three seven-point scales.
PERCEPTUAL-MOTOR CONTROL IN HUMAN-COMPUTER INTERACTION
Authors: Nilsen Erik
Published: January 2007

Information-oriented jobs are particularly well suited for persons with disabilities, requiring far less physical capability than many other jobs. However, computers themselves may present barriers to workers with physical limitations through poorly designed features and poorly selected adaptive aids. Current methods of input device selection for users with disabilities are unsystematic and rarely result in the selection of a device which allows maximum productivity of the user.
Using controlled experiments in layout
Authors: Meyer Steve
Published: January 2007

Since mathematically optimal layout algorithms seem unattainable, layout needs to become a more experimental science. This paper advocates the use of controlled experiments in layout. The physical design workshop bench mark layout environment, open problems solvable by experiment, and the relation of layout experiments to scientific methodology are discussed. The paper concludes by showing that layout synthesis of primitive cells by computer program is impossible since it is no easier than the general artificial intelligence problem.
A small calculus for concurrent objects
Authors: Honda Kohei , Tokoro Mario
Published: January 2007

This brief paper introduces a small anonymous formal system representing the core theory of concurrent object-based computing. Milner's π-calculus is its underlying formalism, but the original calculus is reinterpreted and reformulated to become a simple and powerful expression of concurrent object-based computing. We briefly describe its underlying computational framework, its syntax, transition rules, semantic equivalence, and its special properties concerning "naming", which makes this calculus unique among various concurrency formalisms.
Progress in the garbage collection of active objects
Authors: Kafura Dennis , Washabaugh Doug , Nelson Jeff
Published: January 2007

Research in object based concurrency has exposed a novel and difficult garbage collection problem. The novelty and the difficulty of the problem arise for the same reason - the unit of reclamation is an entity that possesses a thread of control. Such objects, termed
active
objects or
concurrent
objects, are explored in our work through the actor model of concurrency [Agha 1986].
Evolutionary algorithms
Authors: Bäck Thomas
Published: January 2007

Genetic Algorithms and Evolution Strategies, the main representatives of a class of algorithms based on the model of natural evolution, are discussed w.r.t. their basic working mechanisms, differences, and application possibilities. The mechanism of self-adaptation of strategy parameters within Evolution Strategies is emphasized and turns out to be the major difference to Genetic Algorithms, since it allows for an on-line adaptation of strategy parameters without exogenous control. Furthermore, the importance of selection as a mechanism to control the character of the search to be either more volume oriented or more path oriented is pointed out.