bluuebunny/crossref_metadata_2025 huggingface dataset:
Understanding Whisker Growth: Effect of Substrate and Underlayer
Authors: Jagtap Piyush , Kumar Praveen
Published: November 2016

The fundamentals of whiskering in pure Sn coatings electrodeposited on pure Cu and brass (65 wt. % Cu: 35 wt. % Zn) substrates with and without electrodeposited Ni underlayer was studied. These coatings were subjected to isothermal aging at 50 °C to accelerate the whisker growth, and whisker growth was studied using scanning electron microscope (SEM) equipped with focused ion imaging. Texture characterization was conducted using X-rays and electron backscatter diffraction (EBSD). It was observed that whisker growth was more accelerated in case of brass substrate compared to pure Cu substrate. No whisker growth was observed in coatings with Ni underlayer. It was observed that diffusion of substrate atoms along Sn grain boundaries plays major role in whiskering. Ni underlayer inhibited diffusion of Cu and Zn atoms into Sn coating and hence was very effective in mitigating whisker growth.
A Comparison of Immersion Gold and Tin Surface Finishes on Sensing Electrodes for PCB Environmental Saltwater Concentration Sensors
Authors: Dean Robert N. , Werner Frank T. , Bozack Michael J.
Published: November 2016

Printed circuit board (PCB) sensors using low-cost commercial printed circuit board fabrication processes have been demonstrated for environmental sensing applications. One configuration of these sensors uses exposed electrodes to measure saltwater concentration in freshwater/seawater mixtures, through monitoring the resistance between the electrodes when they are immersed in the saltwater/freshwater solution. The lowest cost commercial PCB processes use an immersion Sn HASL surface finish on exposed copper cladding, including the sensing electrodes. This commercial PCB process has been demonstrated to make an effective, low-cost, short-lifetime sensor for saltwater concentration testing. The Sn finish, however, may not be optimal for this application. Sn oxidizes, which can interfere with sensor performance. Additionally, Sn and Sn oxides are potentially reactive with chemical constituents in seawater and seawater/freshwater solutions. An immersion Au (ENIG) surface finish is certainly less reactive with the atmosphere and chemicals likely present in the testing environment. However, an immersion Au finish increases the cost of the sensors by 30% to 40%. To investigate if the possible benefits of the more expensive Au surface finish are worth the extra expense, a study was performed where identical PCB sensors were procured from a commercial vendor with their standard low-cost Sn HASL finish and with their standard ENIG surface finish. Both sets of sensors were then evaluated in concentrations of seawater and freshwater, from 0% to 100% seawater concentration, using freshwater samples from a natural freshwater source near the coast where the seawater was obtained. Testing demonstrated an insignificant difference in sensor performance between the Sn HASL and the ENIG coated sensing electrodes. The results of this investigation indicated that for applications where the sensors will not be used for long periods of time, the added expense of an immersion Au surface finish is not worth the added cost.
Measurement and Modeling of Nuclear Waste in the Double Shell Tanks at Hanford Nuclear Waste Site Using Miniature Sensors
Authors: Aravelli Aparna , McDaniel Dwayne , Abrahao Anthony , Awwad Amer , Davila Clarice
Published: November 2016

Double Shell Tanks (DST's) at the Hanford Site in Washington store nuclear waste and require an understanding of tank integrity. Depending on the chemical composition and pH of the waste, certain temperature requirements are specified. However, the DST's are complex tanks and the methods used to find the temperature data, chemical composition, and other parameters provide results that are often uncertain. Temperature measurements are usually recorded more than 10 feet away from the walls primarily because of technical constraints. Results are fed into basic simulation models to get an estimation of the wall conditions. Hence, there exists a need to accurately measure and model the wall and inside temperatures. To resolve the issue, the authors attempt the use of a miniature pyrometer (Infrared (IR) temperature sensor) to be deployed into the annulus of the DST's. The IR sensor can be mounted on an annulus inspection camera or an ultrasonic testing crawler for temperature measurement of the outer wall for the DSTs. Further, advanced heat transfer based thermal models are developed using the software Solid works 2013 (simulation application) for accurate prediction of the nuclear waste temperatures in the tanks. Successful implementation of the pilot scale testing would result in the deployment of the technology for testing the nuclear waste storage tanks at the Hanford Site in Washington.
Voiding Control at Preform Soldering
Authors: Dasgupta Arnab , Zito Elaina , Lee Ning-Cheng
Published: November 2016

Assembly of components with large pads such as high brightness LEDs or high power dies often is soldered with preform, mainly due to a lower voiding and lower flux fume generated when compared with solder paste, and also because of its better thermal and electrical conductivity compared with Ag epoxy. This is particularly true when the joints are to be formed within a cavity. Although lower than solder paste, the voiding in the solder joint is still a concern for high reliability and high performance devices. In this study, voiding at high power die attach reflow soldering using preform was simulated with the use of Cu coupons to mimic both die and substrate. The voiding behavior was studied by varying solder alloy type, flux quantity coated on preform, oxidation extent of Cu coupon, reflow peak temperature, and weight applied on the top of simulated die. For SAC305, with increasing weight, the bondline thickness (BLT) maintained constant initially due to solder surface tension, then reduced rapidly at weight higher than 50 g. The voiding area % increased with decreasing BLT first, then levelled off at lower BLT, although the voiding volume decreased with decreasing BLT due to constrained lamellar solder flow. Voiding was the highest for SAC305, followed by 57Bi42Sn1Ag, with 63Sn37Pb being the lowest, and increased with increasing oxidation of Cu coupon. With increasing flux quantity, voiding increased for SAC305 and 63Sn37Pb, but decreased for 57Bi42Sn1Ag, mainly due to the different temperature range at reflow. Voiding increased with increasing reflow temperature up to 170°C due to increasing vaporization, decreased with further increase in reflow temperature up to 210°C due to increasing flux activity, and increased again at temperature beyond 210°C due to rapid flux outgassing.
The True Cost of Hermeticity in Microelectronic Packaging
Authors: Dittman Timothy
Published: November 2016

Reliability in microelectronic packaging has been, and will continue to be, a major concern that must be taken into account early in the design of a package. Decisions made relative to packaging materials and the methods for achieving environmental protection drive many other aspects of the design, such as component selection and next higher assembly interfaces. A better understanding of current methods for achieving reliability allows the design community to determine the most appropriate packaging solution for use in a given application.

Environmental protection in microelectronic packaging may be achieved both with and without hermeticity. Hermetic solutions require a means of sealing the package via laser or seam weld type processes in order to provide environmental protection to the components within the package. These packages are typically in the form of either a metal box assembly or a ceramic substrate with a soldered lead frame. Non-hermetic packaging solutions can be accomplished on a wide variety of material sets but require environmentally protective coatings to prevent damage to the packaged components.

Hermetic and non-hermetic packaging solutions, in addition to various types of each, have unique advantages and disadvantages depending upon the application. Characteristics such as electrical performance, producibility, structural integrity and cost must be considered when choosing a packaging solution for an application. This paper will review current microelectronic packaging technology trends and present a trade study on the materials and methods used to achieve environmental protection.
Fire Damage and Repair Techniques for Flash Memory Modules: Implication for Post-Crash Investigations
Authors: Sivakumar Preeth , Lombardi Jack P. , Cain Stephen R. , Poliks Mark , Cash James , Gregor Joseph , Budinski Michael
Published: November 2016

As part of the investigation of accidents in mass transit, air travel in particular, the National Transportation Safety Board (NTSB) retrieves electronic devices from the crash scene. Analysis of flash memory recovered from these devices can provide clues as to the events leading to the crash. Unfortunately, the flash memory is often damaged and unreadable. This study was undertaken in order to address two issues: (1) how much damage the device can sustain before it becomes completely unreadable, (2) what repair techniques can be employed in order to retrieve information from damaged memory units.

The effect of thermal damage was investigated by subjecting flash memory modules to high temperature for three hours. Memory modules were found to be readable after exposure of up to 300°C for three hours. Small fissures evident in the overmold indicated thermal damage to the plastic, yet the chip retained the stored information. Above 300°C the plastic was completely consumed, leaving only the chip and wire bonds.

Repair techniques were investigated by decapsulating the module, then purposely breaking the interconnecting wire bonds. The broken wire bonds were reconnected with metallic ink deposited by a precision printer. After the repairs, the modules were read with no errors, indicating a successful repair. Several methods of decapsulation were tested: acid etch, laser etch, plasma etch, and mechanical polish. Data integrity was retained through each of these decapsulation techniques, except for the acid etch. Plasma etch was not an effective method of decapsulation due to the low etch rate.

Mechanical polish proved to be the simplest decapsulation technique. Bonded interconnect wires were first exposed by a grind/polish of the memory module surface. These wires were then “broken” by over polishing the sample. After confirming that the module could not be read, a repair was completed by printing the connections directly on the polished surface of the module. Subsequent re-reading of the stored data confirmed a successful repair. Of the decapsulation techniques employed, the most effective was laser etch. This method allowed targeted overmold removal at a specific location without disturbing the majority of the packaging - a desirable feature when relatively few circuit lines need to be repaired.
High-Temperature Acoustic Fluid Velocity Sensor Development
Authors: Moton Imran , DiFoggio Rocco , Liew Josh , Fanini Otto
Published: November 2016

There are numerous challenges to developing sensors for high-temperature and high-pressure hydrocarbon reservoir fluid analysis applications in the downhole environment. These challenges include material selection as well as processes for manufacturing, testing, and verification of the sensors. We were tasked with developing sensors for the analysis of subsurface formation fluid samples that required reliable operation up to 38,000 psi (262 MPa) and 450° F (232° C). This paper focuses on the technical challenges and our solution for one such sensor that measures the sound speed of the sampled formation fluid. The core of our acoustic transducer is a piezoelectric crystal, which serves as the acoustic transmitter and receiver. This paper-thin, coin-shaped crystal has even thinner silver electrodes deposited on both of its faces. Numerous wire-to-electrode bonding methods were investigated, which included soldering, sintering, and epoxying, the latter of which proved successful.
Anisotropic conductive film for fine-pitch interconnects
Authors: Wright Daniel Nilsen , Belle Branson D. , Schjølberg-Henriksen Kari , Nguyen Hoang-Vu , Gakkestad Jakob , Kristiansen Helge , Visser Taklo Maaike M.
Published: November 2016

An anisotropic conductive film (ACF) can be utilized to simultaneously form mechanical bonds and electrical connections during flip-chip assembly. The electrical connection is created by trapping randomly dispersed metallized polymer spheres (MPS) in the ACF that are deformed during the bonding process. This work postulates that the reliability of interconnects formed with ACF depends on the degree to which the MPS are deformed. Silicon samples with fine-pitch electrical test structures were flip-chip assembled using an ACF and measured in-situ during environmental testing. Interconnects with MPS deformation below 60% proved more stable than interconnects with higher deformation during exposure to 85% relative humidity at 20 °C, 45 °C, 60 °C and 85 °C, as postulated. On the other hand, the stability of the interconnects did not show a dependence on MPS deformation during exposure to thermal shock cycling (TSC) (−55 °C / +125 °C, 7 s transit time, 700 cycles). The results suggest that deformation of MPS is a central factor with respect to reliability of ACF-bonded fine-pitch samples exposed to humid conditions, but the results also indicate that other failure mechanisms are more important for samples exposed to thermally unstable conditions.
Innovative Uses for Plasma Surface Conditioning in the Assembly of Electronic Devices
Authors: Sahagian Khoren , Prack Ed
Published: November 2016

Plasma surface conditioning is now a commonly accepted practice in many applications. Three types of plasma systems are commonly commercially used: low pressure (LP), atmospheric plasma (AP) and corona (CP). This paper compares the attributes of each of these available types. We suggest there are many applications well suited to the use of atmospheric plasma jet in electronic manufacturing. This paper provides examples of the benefits of using atmospheric plasma for applications including: improving adhesion by plasma surface modification, reduction of metal oxide surfaces and deposition of protective barrier layers for LEDs. These examples demonstrate the unique potential of atmospheric plasma jets to provide advantages in applications important in electronic assembly and manufacturing including initial characterization data, references to final applications and next steps.
Packaging for medical and wellness applications
Authors: Rouzaud A. , Cartier M. , Souriau J-C. , Simon G. , Brun J. , Pares G.
Published: November 2016

Wellness and medical area are today identified among the next big markets, and the associated roadmaps show a global trend from the benchtop to portable devices then to longer term wearable and implantable devices. For these last devices new packaging technologies need to be developed in order to satisfy both size reduction, important reliability constraints, and moderate/low costs. Two divergent identified markets have been identified:-Consumerist healthcare market associated to high volume and low cost manufacturing,-Professional healthcare market associated to low volume and high cost manufacturing.

Based on these findings, we will present in this paper the main new packaging technologies developed at Léti to fit with the constraints of these markets:-In the field of wearable devices: an innovative package designed to be integrated in textiles offering low interaction with material structure and compatible with standard textile tooling and package-winding machines. A specific example of RFID tags will be presented.-In the field of implantable devices: an advanced implantable low profile silicon box for SiP including a MEMS chip and its ASIC. The emphasis will be put on the tests needed to satisfy the different constraints linked to implantability (biostability, biocompatibility).-Lastly, some generic building blocks for soft packaging will be presented, as well as the main trends in their use.
Proposal of Ultra-fine and High Reliable Trench Wiring Process for Organic Interposer
Authors: Mitsukura Kazuyuki , Toba Masaya , Urashima Kousuke , Ejiri Yoshinori , Iwashita Kenichi , Minegishi Tomonori , Kurafuchi Kazuhiko
Published: November 2016

An organic interposer technology with ultra-fine line and space is required in order to achieve high density interconnection between chips. In this paper we propose a high reliability, ultra-fine trench wiring process. Current trench wiring is made by laser ablation of dielectric, spattering, copper plating and then Chemical mechanical polishing (CMP). However, it is challenging for laser ablation to achieve fine trench with smooth side wall and CMP is not suitable because of high assembly cost. Reliability is another challenge because of the narrower and thinner insulator.

We have developed photosensitive insulation film (PIF) with fine resolution. The trench wiring of 2/2 μm line and space has been successfully assembled by photolithography, plating and surface planer method as the alternative to CMP. The wiring layer of 2/2 μm line and space, which was covered with the thin barrier metal layer and PIF, has passed the biased highly accelerated temperature and humidity stress test (HAST) screening.

In addition to the above process a copper paste has been applied as a seed layer instead of the spattering. The sintered copper filled with adhesive paste into the copper porous is compatible as the seed layer and the wiring layer of 10/10 μm line and space has passed the reliability tests such as MSL2, thermal cycling test and biased HAST.
Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging
Authors: Palesko Chet , Lujan Amy
Published: November 2016

Fan-out wafer-level packaging (FOWLP) offers many significant benefits over other packaging technologies. It is one of the smallest packaging options, but unlike fan-in wafer-level packaging, the IO count of FOWLP is not limited to the area of the die. Given these advantages, FOWLP continues to grow in popularity.

While the cost of FOWLP is usually reasonable, there are still opportunities for future cost reduction. Many FOWLP suppliers are exploring panel-based manufacturing instead of the current wafer-based approach. Since many more packages can fit on a large panel than on a wafer, the cost per package can be reduced. The surface area of a 370mm × 470mm panel is 1,739 sq.cm. compared to 706 sq.cm. for a 300mm wafer. This means more than twice as many packages can be manufactured on a single panel. However, this does not mean that the cost per package will be cut in half. Many of the costly manufacturing activities do not depend on the surface area of the panel or wafer and they will not be affected by a larger panel.

This paper analyzes the current cost of FOWLP activities and highlights which activities will benefit from a move to panels. An analysis of each manufacturing activity is presented comparing the cost impact of panel versus wafer. The total potential cost savings is also presented.
Optical Role of Die Bonding for Chip-on-Board White Light Emitting Diode Emitters
Authors: Kim Gunwoo , Shih Yu-Chou , Shi Frank
Published: November 2016

The role of die attach adhesive in influencing light output of the white chip-on-board (COB) light emitting diode (LED) emitters is investigated using Monte-Carlo simulations. It is demonstrated for the first time that the use of an optically clear adhesive for replacing conventional adhesive for multiple COB white LED emitters leads to a significant enhancement in light output of up to 22 %. An optimization of packaging materials and process for multiple COB LED emitter to enhance optical efficiency is also studied.
Investigations on the Wire Bonding Capability on Selective Laser Melted Structures
Authors: Kaestle Christopher , Syed-Khaja Aarief , Franke Joerg
Published: November 2016

The paper displays the influencing factors, as well as the possibilities and challenges that come along with the process combination of selective laser melting (SLM) and heavy wire bonding. For the investigations, test samples were created from bronze powder on a SLM-machine. Then, 300 μm aluminum and copper wires were bonded on the SLM generated structures. Wire bonding capability is analyzed on untreated as well as on post-processed surfaces. The influence and effectiveness of various steps of post-processing such as cleaning, sandblasting and grinding are analyzed. Thus, interdependencies between both manufacturing process as well as the post-processing can be revealed. The effect of surface roughness and hardness of the assembly partner are investigated as well. To draw statistically backed conclusions, all tests are performed using DoE (Design of Experiment) studies. The primary characteristics besides the bond parameters that influence the wire bonding capability are focused in this paper. The process stability as well as the interconnection quality are evaluated by optical non-destructive laser microscopic analysis. Destructive pull and shear tests and metallographic cross sections are performed to evaluate the adhesion characteristics. The process stability and the yield obtained are important factors to describe the process and to evaluate the industrialization potential. By a profound understanding of all interdependencies between the two processes, a flexible manufacturing technology for power devices can be established.
Advanced wire bonding for high reliability and high temperature applications
Authors: Guyenot M. , Reinold M. , Maniar Y. , Rittner M.
Published: November 2016

The next generation of switches for power electronic will be based on white band gap (WBG) semiconductor GaN or SiC. This materials supports higher switching current and high frequency. White band gap semiconductors enables higher application temperature.

Certainly, high temperature capability is also to discuss in combination with high number of thermal cycles. For a frame module concept shows these paper a comparison of different joining techniques with the focus on the reliability issue on wire and ribbon bonding.

Beside to the 1000 passive thermal cycles from −40°C to +125°C there are active thermals cycles for technology qualification required [3]. Depending on the application and mission profile a high thermal cycling capability is necessary. For this reason, new high temperature joining techniques for die attach, e.g. Silver sintering or diffusion soldering, were developed in the recent past [4]. All of this new joining techniques focusing on higher electrical, thermal and thermo-mechanical performance of power modules. By using an optimized metallization system for the WBG the numbers of thermal cycles can be increased and the maximum operating temperature advanced up to 300°C. In these new temperature regions silicon semiconductors will be substituted by WBG semiconductors.

The present work shows an active power cycling capability of different wire and ribbon bonds and the failure mechanism will be discussed. A calculation model explained the reliability for the different wire diameter and the impact of bonding materials. This reliability calculation explain the thermo-mechanical effects and based on materials and geometry data and is not optimized for evidence. Through these physical background understanding more than 1.000.000 thermal cycles with a 150 K temperature swing from +30°C to +180°C are now possible. These is a the basic knowledge for a design for reliability based on current, mission profile and reliability optimization for future high end applications with wire or ribbon bonding technique.
Effects of Probe Marks on Shear Test of Copper Ball Bonds in Two Pad Aluminum Thicknesses
Authors: Brown Priscila , Wynder Rachel , Tenney Dustin , Hunter Stevan
Published: November 2016

This paper continues the work of reference [1], evaluating shear test results of Cu ball bonds over a variety of probe marks in two different pad aluminum (Al) thicknesses (0.8μm and 3μm). The presence of invasive probe marks on thick Al bond pads lowers certain shear force results.. Lower values of shear force imply reduced Cu bond reliability. Physical factors are investigated relating to poor intermetallic (IMC) formation in the Cu wirebond and bond shear force. Optical microscopic image analysis of Cu bonds, bond contact areas and Al “splash” are studied for correlation with the shear test results. Percent IMC coverage of bond contact areas decrease when invasive probe marks are present beneath the bond, which in turn may reduce the shear force. Probe mark features are studied to discover the characteristics of greatest influence on % IMC coverage and shear test values in each of the pad metal thicknesses.
Aluminum bond pad corrosion of wirebond packages
Authors: Mathew Varughese , Chopin Sheila , Chyan Oliver , Ross Nick , Lambert Alex , Asokan Muthappan
Published: November 2016

Corrosion of aluminum bond pads in wirebonded packages can lead to device reliability issues under the harsh conditions in automotive applications. Corroded Al (aluminum) surface forms a mud-crack type appearance with a relatively very thick aluminum oxide/hydroxide (> 0.1μm) compared to thin protective native aluminum oxide (< 7nm). Various factors contributing to the formation of mud-crack type corrosion are identified. In all cases of mud-crack corrosion observed for packaged devices, Cl (chlorine) was detected on the corroded Al pad. The corrosive impact of high levels of Cl on the Al pad resulting in thick aluminum oxide growth will be discussed. The concentration levels of Cl to form mud-crack corrosion is far beyond the level of ionizable Cl typically present in packaging materials (such as mold compound or organic die attach) so the source of high levels of Cl is due to foreign contamination. The effect of Cl on mud-crack corrosion depends on other factors including pH and applied bias voltage. Corrosion susceptibility is found to be significantly reduced, even in the presence of high levels of Cl, when the pH > 6 and close to the neutral value of a pH of 7. It was also found that Cl is not essential to form mud-crack corrosion. Conditions leading to the corrosion in the absence of Cl are presented. F (fluorine) is a known contaminant in semiconductor processing and its influence on Al pad corrosion is examined. The differences on the impact of F vs. Cl on mud-crack corrosion will be discussed. Corrosion was observed irrespective of the wirebonds in the package (gold (Au) or copper (Cu)). However, the type of bi-metallic contact influences the extent of corrosion. The impact of bi-metallic contact on the mud-crack corrosion will be presented.
Reliability of Heavy Gage Aluminum Wire-bonds under High Temperature Aging
Authors: Lakhera Nishant , Labroye Emmanuel , Pronga Catherine , Molinie Florence , Lesnakowski Samuel
Published: November 2016

Thick aluminum (Al) wedge bonds have been widely used in analog microelectronic packages due their lower cost, ease of use and excellent thermal and electrical performance. Reliability of thick Al wedge bonds on bare copper (Cu) leadframes under high temperature aging conditions has not been studied at a fundamental level in the past. This study investigates the reliability performance of Al wedge bonds on bare Cu surfaces under isothermal aging conditions specified by the automotive grade product qualification requirements. Results obtained show that Al/Cu intermetallic formed at the interface is detrimental to the mechanical and electrical package reliability. Plating on the leadframe has been evaluated as a potential mitigation to prevent intermetallic growth and hence improve the overall wedge bond and package reliability under high temperature reliability testing conditions. Significant improvement in the wedge bond and package reliability was achieved by using nickel plating under the wedge bonds. The results presented in this study can be used to design a more robust package capable of meeting stringent automotive grade requirements.
Challenges in Fine Feature Solder Paste Printing for SiP Applications
Authors: Pei-Lim Sze , Thum Kenneth , Mackie Andy
Published: November 2016

The rapid development in the Internet of Things (IoT) has seen a surge in demand for System-in-Package (SiP), which is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller components and greater density.

01005 passive components are being used in most of the current SiP technology and the industry is looking at utilizing 008004 passive components for the next generation SiP. The stencil aperture design for 008004 will likely be about half of 01005, and a finer powder size solder paste will be used. The stencil design, stencil thickness, and the types of stencils being used, are crucial in achieving good solder paste printing performance. Due to the need of squeezing more components into a SiP, the gap between neighboring pads can be as close as 50μm; hence, it is crucial to avoid solder bridging for such applications. This paper will discuss the challenges in achieving consistent solder paste printing performance for fine feature applications using Type 6 (5–15μm) powder size solder paste. Test results with different stencil designs, printing parameters, and different solder pastes will be discussed in detail.
Digital Manufacturing and Performance Testing for Military Grade Application Specific Electronic Packaging (ASEP)
Authors: Newton C. Mike , Deffenbaugh Paul I. , Church Kenneth H. , Crane Nathan B. , Neff Clayton
Published: November 2016

I. Abstract

This paper will discuss the development of additive manufacturing as a process integration methodology for printed electronics and 3D printed structures. This integration enables the ability to move from printed circuit boards (PCBs) to printed circuit structures (PCS). Historically packaging has been identified as a hierarchical (or levels) approach to interconnect electronic products or systems. Level one packaging addresses the interconnection between bare die and the module while level four moves up in the packaging chain to connections between subassemblies. With the advent of digital manufacturing and emergence of more robust materials, the enabling technology provides a manufacturing tool for building electronic packages with integrated passives (some printed) and actives. This further enables the capability to adjust the form factor to the mission or product requirements - also known as personalization. This ability to become form factor agnostic has produced the ability for printing or digitally manufacturing application specific electronic packages, ASEPs. With this emerging capability it begs the question of reliability and in particular to qualification for harsh environment applications. This paper will discuss the application of current standards, Mil-Std-883 or JESD93 for example and how these might be applied to ASEPs and to also explore the development of new or hybridization of current standards.
Addressing Next Generation Packaging and IoT with Glass Solutions
Authors: Shorey Aric , Lu Rachel , Adriance Kevin , Smith Gene
Published: November 2016

New requirements are emerging in electronics packaging. The ever-growing need for solutions for mobile communications and sensors that address the Internet of Things (IoT) brings about interesting new challenges. RF applications strive to move to higher frequency bands, fan-out technology is being leveraged as an effective way to address interconnect demands, and there is a continuous search for more cost-effective solutions for difficult packaging challenges. Glass provides numerous opportunities to address these needs. As an insulator, glass has low electrical loss, particularly at high frequencies. The relatively high stiffness and ability to adjust coefficient of thermal expansion helps optimize warp in glass core substrates, and manage bonded stacks leveraging TGV and carrier applications. Glass forming processes allow to form in a panel format as well as wafer format at thicknesses as low as 100 μm, giving opportunities to optimize or eliminate current polishing type manufacturing methods and address packaging challenges in a cost effective way. As the industry adopts glass solutions, significant advancements have been made in downstream processes such as glass handling and via/surface metallization. Of particular interest is the ability to leverage tool sets and processes for panel fabrication to enable cost structures desired by the industry. We will provide the latest demonstrations of electrical, thermal and mechanical performance and reliability as well as describe areas where glass is being leveraged to achieve goals of next generation products.
3D SiP Assembly and Reliability for Glass Substrate with Through Vias
Authors: Tain Ra-Min , Hu Dyi-Chung , Yang Kai-Ming , Chen Yu-Hua , Chen Jui-Tang , Liu De-Shiang , Lin Chen-Hao
Published: November 2016

Applications of Glass substrate for high performance system-in-package (SiP) products have gradually become a promising technology in recent years. Research and development activities are reported in many journal papers and conferences [1,2]. Consortiums and Alliances are also formed to gather worldwide efforts for developing glass technology. In the past, we have published our development efforts on the process of producing glass substrate with through via and build-up redistribution circuit layers (RDLs) [3]. N. Koizumi [4] first reported glass reliability issues in 2013; and the phenomena he called SE-WA-RE has caused a great concern of using glass as a substrate. Model simulations have indicated that the glass crack is related to the stress buildup by the materials and structure. In this study, we selected a dielectric material/structure set that is designed to be less stressful to the glass substrate. A better reliability result can be expected.

In this paper, we will discuss an assembly structure of SiP module using the glass substrate with through-glass via (TGV) where the diameter of TGV is 100μm with thickness at 200μm. The copper plating technique to form the through via conductor is called direct-metal-on-glass (DMoG) which deposits titanium and copper directly on glass both in the wall of through vias and on glass surfaces of both sides. The first RDL is formed on both surfaces of glass substrate by semi-additive plating (SAP); then followed by build-up RDLs on top of the DMoG RDLs on both sides of the substrate also by SAP with interconnect vias to form connections between DMoG RDLs and build-up RDLs. Finally, solder mask is applied on both sides of the glass substrate leaving pad openings (SRO) for surface finish, die mounting and printed-circuit board connection purposes. At die mounting side, the SRO is 60μm in diameter with minimum pitch at 150μm. The TGV conductors connect the DMoG RDLs on both sides of the substrate. A mechanical test die with 18μm bump diameter is mounted on the build-up RDL at the substrate top side with daisy-chain design both in the test die and TGV substrate RDLs. Thus, the daisy-chain connection can go from the build-up RDL of the substrate back side to the test die on the top side of the substrate. 200 thermal-cycling test (TCT) has been performed and the daisy-chain resistances are measured before and after the 200 TCTs. It is found that 96% of daisy-chains have less than 10% of resistance change after 200 TCTs.
Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)
Authors: O'Toole Eoin , Kroehnert Steffen , Campos José , Barbosa Virgilio , Dias Leonor
Published: November 2016

NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment.

One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls <500um and for a LGA package with solder land pads only <300um is achievable today, and further development towards even thinner packages is on the way.
High viscosity paste dosing for microelectronic applications
Authors: Thomas T. , Voges S. , Braun T. , Raatz S. , Kahle R. , Becker K.-F. , Koch M. , Fliess M. , Bauer J. , Schneider-Ramelow M. , Lang K.-D.
Published: November 2016

Today's microelectronics packaging especially for SiPs relies on the processing of a wide variety of materials Such as materials for components, substrates, contact materials (solder & adhesives) and encapsulants. Most materials are processed as bulk material but precision dosing of pastes is key to many assembly processes. Examples are dosing of solder paste, typically done by stencil printing, underfilling for Flip Chip encapsulation, typically done by dispensing or jetting, or glob top encapsulation of Chip on Board assemblies, where also dispensing is the typical process. When working with those paste materials, viscosity is one of the key parameters for processing, and viscosities too high do not allow dosing of the materials, not even to transport the material from a reservoir to the dosing head, which may be a simple needle or a jet valve. [1,2]

To overcome this obstacle, i.e. to dose materials of high viscosity precisely and homogeneously from a syringe to the dosing head, a research program has been set up, where Vermes microdispensing as a valve manufacturer and TU Berlin/IZM as a research institute are cooperating. TU Berlin is working on material rheology effects and flow models; Vermes is researching valve modifications and material flow path optimization. Core of the research is to find methods that allow a reduction of paste viscosity without leading to irreversible changes in the material, as would be the case when simply applying heat to the paste.

As reference process for material dosing, FO-WLP has been chosen, materials selected for the investigations are glob top dam and fill material and liquid molding compound – using both rheological experiments as well as actual material dosing and processing. Apart from temperature, mechanical and ultrasonic stimulation of the material have been evaluated to achieve optimized dosing of high viscous pastes,

As a result, a first description of paste behavior during processing is given, being the basis for future work towards homogeneous precision dosing of high viscous pastes for microelectronic applications.
3D TSV-based Inductor Design for a Secure Internet of Things
Authors: Kim Bruce , Cho Sang-Bock
Published: November 2016

This paper describes the design and modeling of through-silicon via (TSV)-based high-density 3D inductors for Internet of Things (IoT) applications and presents some possible challenges for TSV-based inductors in IoT applications. For cybersecurity infrastructure, we designed IoT with hardware security in mind. We provide a secure design for Internet of Things based on secure 3D inductors and then show case studies of high-density RF packages with TSV-based inductors that require hardware security, such as military applications. We use ferromagnetic materials to achieve high inductance with good quality factor.
Simulation and Measurement of Power Distribution Networks (PDN)
Authors: (Alvin) Pin Jen Wang , Islam Sharmin , Barlow Fred , Elshabini Aicha
Published: November 2016

In this publication, signal integrity issues of Power Distribution Networks (PDNs) are addressed (to insure acceptable quality of signals within); Transmission line effects, Crosstalk, and Impedance mismatch. Power Integrity issues of PDNs are also addressed (to insure acceptable quality of power delivery within); Voltage drop, High impedance, Parasitic Via inductances, and Noise coupling. In this work, ANSYS™ HFSS 2013 FEM simulation techniques development, adaptive meshing, and convergence to S-parameters, Differential S-parameters, and Z-parameters to design and simulate PDNs under different conditions and the results are compared to measurements performed in our laboratories.
Spurious Turn-On inside a Power Module of Paralleled SiC MOSFETs
Authors: Miao Zichen , Ngo Khai D. T.
Published: November 2016

Silicon carbide (SiC) dice are often paralleled to realize power modules with high-current rating. Owing to the large network of interconnect (parasitic) impedances, terminal waveforms could appear benign while the dice experience detrimental fault currents generated by spurious cross-turn-on. This paper will quantify the non-uniform distribution of current stress and switching energy among the dice, as well as the penalty caused by cross-turn-on, versus layout symmetry, number of dice, gate resistance, input voltage, and load current.

Cross-turn-on currents inside a module increase the high-side switching energy and total switching energy by 44% and 20%, respectively, at 800 V / 300 A. Peak cross-turn-on current of the symmetrical module is only 16% of that of asymmetrical module at nominal condition. Symmetrical layout greatly decreases the cross-turn-on currents without increasing the total switching energy.

Four modules are constructed based on the asymmetrical layout to explore how number of dice influences cross-turn-on and switching energy. Peak cross-turn-on current and switching energy of the six-die module are 134% and 36% higher than those of the one-die module, respectively. Severity of cross-turn-on soars as number of dice increases.
Erratum - Osteophytes may be a rare cause of recurrent pleural effusions
Authors: Psathakis K. , Skouras V. , Chatzivasiloglou F. , Tsintiris K.
Published: November 2016

This corrects the article published on Monaldi Archives for Chest Disease 2013;79(2):87-89.
Corneal cross-linking methods and outcomes: A review
Authors: Nicholas Deanne Lee , Gillian Wayne D.H.
Published: November 2016

The prevalence of corneal ectasias such as keratoconus has been widely documented. Keratoconus may lead to detrimental changes in visual acuity, which can often be corrected in the early stages but requires more invasive treatment as the condition progresses. Corneal cross-linking has become a treatment method of choice in early keratoconic patients and is used to stabilise the condition and prevent further progression of the disease. The principle behind this procedure is the creation of additional bonds within the corneal structure in order to enhance its mechanical properties and thereafter halt the progression of the condition. There are disagreements within the literature as to how these procedures can be performed, and there are various alternative methods. It can be concluded that corneal cross-linking is an effective treatment method for keratoconus and has been shown to produce various beneficial effects in terms of ocular structure and function.
Employees' perceptions of the effectiveness and fairness of performance management in a South African public sector institution
Authors: Makhubela Mpho , Botha Petrus A. , Swanepoel Sonia
Published: November 2016

Orientation: The implementation of performance management systems (PMSs) and performance appraisals (PAs) by public managers remains a challenge and necessitates an investigation into employees’ perceptions of the effectiveness of the PMS and the fairness of PA.Research purpose: This study investigated the association between employee involvement, performance-oriented culture, management commitment and the effectiveness of a PMS. Six factors that determine and influence employees’ perceptions of PA fairness were also investigated.Motivation for the study: Employees’ experiences of the implementation and practice of PMSs and PAs by public managers may differ from what is intended. The motivation for this study was to quantify employee perceptions of the effectiveness of a PMS and the fairness of PA to establish if there is a discrepancy between what is intended and how they are implemented and practiced.Research approach, design and method: This cross-sectional study conducted a census on a total population of 140 employees in a public sector institution. A questionnaire comprising three sections was used to collect data: Section A contained biographical questions, Section B comprised questions on the contextual factors that measure the perceived effectiveness of the PMS while Section C comprised questions related to the perceived fairness of PA.Main findings: The results show that employees perceive their PMS to be ineffective and their PAs to be unfair. The mean perception scores for PA fairness for the Assets and Facilities Department were significantly lower than those of the Human Resources Department. This is indicative of some deficiencies in the appraisal process in the Assets and Facilities Department. Respondents occupying general positions returned significantly lower mean scores for PA fairness compared to those in managerial and professional positions, which indicates serious shortcomings in their appraisal process.Practical/managerial implications: The findings reveal that employees were not involved in the development of the PMS. Also, the results indicated a lack of employee participation in the PA process, that PAs were not conducted for development purposes, performance feedback sessions were not undertaken on a regular basis and employees were not involved in goal setting. A training programme should address these organisational and managerial deficiencies.Contribution: This research study contributes to the body of knowledge by quantifying the perceptions of employees regarding the organisational factors that influence the effectiveness of the PMS and the six factors, namely appraisers’ knowledge, employee participation, clear goal establishment, employee development, goal establishment, appraisal follow-up and goal discussion that influence PA fairness.