Source/Drain Epitaxy for Nanosheet-Based CFET Devices
Authors: Rosseel Erik , Porret Clement , Dursap Thomas , Loo Roger , Mertens Hans , Ganguly Jishnu , Sarkar Ritam , Cavalcante Camila , Richard Olivier , Geypen Jef , Marozas Brendan , Casey Daniel , Khazaka Rami , Demuynck Steven , P. B. Lima Lucas , Langer Robert , Biesemans Serge , Horiguchi Naoto 
Published: December 2024

The complementary field-effect transistor (CFET) is an attractive device architecture for beyond 1 nm CMOS technology nodes where n- and p-MOS nanosheet devices are placed on top of each other [1-3]. In the present paper, we discuss the progress in source/drain (SD) epitaxy development for nanosheet and monolithic CFET (mCFET) devices. A schematic cross-section of a mCFET stack is shown in Figure 1, in the case of a Metal-Diffusion-first (MD-first) integration scheme [3]. In this case, the p-MOS device is made first, leading to a bottom SiGe:B (B-SiGe:B) SD epi layer. The n-MOS device with top Si:P (T-Si:P) SD is placed on top of the p-MOS, which requires an isolation layer between the two devices.

Figure 2 shows cross-section transmission electron microscopy (X-TEM) examples for the integration of a co-flow SiGe:B layer [4] in nanosheet and CFET structures with 48 nm and 60 nm contacted poly pitch (CPP) respectively. In case of multiple sheets (Figure 2(a)), the SiGe:B growth happens from the different Si sheets and from the Si bulk. Twin defects can be observed due to the merging of neighboring and opposing sheets. For the bottom SD in CFET structures with single nanosheets (Figure 2(b)), the majority of the SiGe:B is grown from the Si bulk which then merges with the growth fronts from the single sheets. For the pre-cleaning of the nano-sheets before epi growth, we rely on a combination of wet and low-temperature in situ PreviumTM clean [5]. A pre-epi bake is omitted to avoid dummy gate crystallization. Figure 2(c) summarizes specific Ti/SiGe:B contact resistivity (rc) levels obtained using the circular transmission line method (CTLM) for stacks based on conventional co-flow and low-temperature (LT) SiGe:B processes [6-8]. Results are plotted as a function of the material resistivity (r). A lowest rc of ~ 2×10-9 Ω.cm2 is demonstrated with LT-Si0.5Ge0.5:B (active B concentration [B]act = 2.5×1021 cm-3), which is ~ 50% lower than values obtained with conventional Si0.4Ge0.6:B, for which lower [B]act are obtained. In the present paper we will further discuss the progress towards using LT-SiGe:B cyclic deposition etch (CDE) processes in nanosheet-based devices to reduce the access resistance.

X-TEM examples of the integration of T-Si:P SD in a CFET structure with 60 nm CPP are shown in Figure 3. A conventional high-temperature (HT)-Si:P [9] (Figure 3(a)) is compared with a LT-Si:P variant (Figure 3(b)). The LT-Si:P process used here is a CDE process running at 525ºC, which combines deposition with a higher order Si precursor and a HCl/GeH4 based etching steps to enable the selective epitaxial growth (SEG) of Si:P SD [10-13]. Figure 3(c) plots the specific resistivities obtained for Ti/Si:P contacts as a function of the active P-concentration ([P]act) as determined from micro-Hall measurements [6,7,13]. For the HT-Si:P process, the doping activation after epitaxy is relatively poor (10%-15%) and post epitaxy spike or laser anneals are typically used to increase the active concentration and decrease the contact resistivity. When moving to LT-Si:P processes with temperatures below 500ºC [14], [P]act can be increased up to ~ 1×1021 cm-3 and the contact resistivity reduced to ~ 2×10-9 Ω.cm2. In the present paper we will further discuss the progress of using LT-Si:P CDE processes in nanosheet-based devices and enable a benchmark of recently developed SD selective epitaxial growth options for the consistent fabrication of performant CFET devices.

Acknowledgements

This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 101007254. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Netherlands, Germany, France, Czech Republic, Austria, Spain, Belgium, Israel. The imec core CMOS program members, local authorities and the imec pilot line are acknowledged for their support.

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Figure 1