bluuebunny/crossref_metadata_2025 huggingface dataset:
Thin Film Packaging Reinforcement for Overmolded MEMS
Authors: Charlotte Gillot , Pornin Jean-Louis , Billard Christophe , Lagoute Emannuelle , Pellat Mihel , Parat Guy , Sillon Nicolas
Published: October 2015

Thin Film packaging (TFP) is now well known at CEA/LETI and mainly used as a protection for MEMS against degradation which can occur during back end processes: TFP is strong enough to endure the mechanical constraints due to grinding, handling and protects the device from water during the sawing step. Our TFP process is also compatible with under bump metallisation, balling and flip chip processes. The main advantages of our TFP is a very low lost of silicon area, a low cost process with 3 mask levels, and is performed on equipments commonly used in IC fab. In this paper we will speek about process improvement for a TFP overmolded.

The thermo-mechanical constraints due to the standard overmolding step (100 bars and 200°C) are much more challenging for TFP: the cavity is about 5 μm high, the cap layer 2μm thick and the polymer plugging layer 6μm thick. So TFP needs to be reinforced to withstand these high constraints.

Two processes using conventional IC manufacturing technologies have been developed at wafer level with two materials. 200μm and 500μm wide cavities with TFP were reinforced with these processes and first tested under pneumatically pressure at room temperature: in case of contact between the cap and the substrate, a short circuit is measured between one electrode on the substrate and another electrode behind the cap. Then, the same devices were overmolded at 75 bars and 100 bars at 185°C. In the same run, BAW resonators with TFP and one type of reinforcement were overmolded at 100 bars. The electrical performances of these resonators after overmolding fit very well to the modelling of the test card and are very good. This Compatibility between TFP and overmolding constraints could be a cost effective solution in MEMS packaging.
TLP Bonding Technologies for Micro Joining and 3D Packaging
Authors: Murayama Kei , Aizawa Mitsuhiro , Higashi Mitsutoshi
Published: October 2015

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance.

The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability.

The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered.

We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed.

In this paper, we report on various possible application of the TLP bonding.
Vacuum Packaged Silicon MEMS Gyroscope with Q-Factor Above 0.5 Million
Authors: Trusov Alexander A. , Schofield A. R. , Shkel A. M.
Published: October 2015

This paper reports a new dual mass vibratory MEMS z-axis rate gyroscope architecture that prioritizes the sense-mode quality factor and provides improved ordering of the mechanical vibrational modes. The proposed linearly coupled, dynamically balanced anti-phase sense-mode design minimizes substrate energy dissipation to maximize the quality factor. The levered drive-mode mechanism structurally forces the anti-phase drive-mode motion of the symmetrically decoupled tines eliminating the lower frequency spurious mode and providing true mechanical rejection of external shocks and accelerations. SOI prototypes were characterized in a vacuum chamber demonstrating drive-mode quality factor of 67,000 and ultra-high sense-mode quality factor of 125,000. A vacuum packaging technology was introduced and demonstrated a ceramic package-level sealed gyroscope with a quality factor on the order of 100,000. The high quality factor and mode ordering of the new design provide a path toward ultra-high scale factor without compromising the sensitivity to external accelerations.
A High-Sensitivity Resonant Sensor Realised Through the Exploitation of Nonlinear Dynamic Behaviour
Authors: Waugh William , Gallacher B. J. , Burdess J. S.
Published: October 2015

Existing MEMS viscometers and density meters typically measure vibrational characteristics such as resonant frequency, bandwidth and quality factor. In order to significantly improve sensitivity to changes in viscosity and/or density the proposed sensor will exploit nonlinear dynamic behaviour and measure the frequency separation between singular jump points in the frequency response function. By using a one-mode approximation when excited near resonance, the dynamics of a clamped-clamped slender beam in fluid is that of a standard Duffing oscillator. With harmonic forcing of sufficient magnitude, a bistable region, bounded by amplitude jump points, is seen to occur. The width of this bistable region is dependent on the damping ratio of the system, which is shown to be a function of the dynamic viscosity and density.

Experiments with clamped-clamped silicon beams in a range of gases demonstrate that the sensitivity of the proposed nonlinear sensor at low viscosity can be at least an order of magnitude better than that of conventional devices. Forcing magnitude and control is identified as being critical to the measured width of the bistable region. Beam dimensions can be chosen to optimise measurements for the desired application.
Underfill Design for Low-k Dielectrics and Lead Free Applications
Authors: Schmaltz Brian , Abe Yukinari , Kohara Kazuyuki
Published: October 2015

As technology nodes progress to 32/28nm and beyond underfill materials are presented with the significantly challenging task of maintaining bump protection while ensuring ultra low-K dielectric (ULK/ELK) integrity. This challenge is further complicated by the trend toward RoHS compliancy(lead-free) and a ever increasing die size. Through extensive research and testing, several specifically formulated underfill materials were determined acceptable solutions for these complex issues. As technology nodes progress to smaller process generations a high stress concentration is seen at the dielectric layer during thermal cycling. This stress is a typical result of a high glass transition temperature (Tg) / high strength material that often leads to a cracking failure mode of the thin dielectric layer. Too low of a Tg presents a high stress concentration on the bumps which once again constitutes failure, this time however the crack is typically seen at the bump location. This high stress concentration seen at the bumps is more significant when lead free bumps are considered due to their inherent fragile nature. Underfill materials must now be specifically formulated and optimized to solve these failure modes for a large variable of package types. This paper will discuss solutions to typical failure modes currently seen with reliability testing of present and future technologies.
Thermally Conductive (TC) Plastics in LED Lamps
Authors: Janssen Rob , Douven Ir. L. , van Dijk H. K.
Published: October 2015

In section 1, an assessment is made of the typical thermal conductivities attainable in a TC-plastic followed by an examination of the trade-off between increased thermal conductivity and decreased toughness caused by increasing filler load of such a TC-plastic.

Having established that currently there is a ceiling conductivity of around 25 W/mK for TC-plastics, i.e., well below the 100 W/mK TC level of metals, subsequently a basic analysis is provided on the suitability of materials with such moderate TC-levels in metal replacement. For this purpose, the ideal case of a unidirectional (1D) heat flow is considered in section 2, in section 3, a more complex case of a bidirectional heat flow is analyzed. Finally, section 4 considers the thermal performance of TC-plastics in a real 3D part, i.e., the heat sink housing of an LED lamp. More specifically, a comparison is made between the thermal performance of the housing molded in a heat conductive plastic and that of an all-aluminum housing. This comparison clearly demonstrates general validity and practical value of the conclusions drawn in sections 2 and 3 and highlights the outstanding suitability of TC-plastics for heat sinks in lighting applications. High performances STANYL TC in particular.
Improved Heat Dissipation and Optical Performance of High-power LED Packaging with Sintered Nanosilver Die-attach Material
Authors: Panaccione Paul , Wang Tao , Lu Guo-Quan , Chen Xu , Luo Susan
Published: October 2015

Heat removal in packaged high-power light-emitting diode (LED) chips is critical to device performance and reliability. Thermal performance of LEDs is important in that lowered junction temperatures extend the LED's lifetime at a given photometric flux (brightness). Optionally, lower thermal resistance can enable increased brightness operation without exceeding the maximum allowable Tj for a given lifetime. A significant portion of the junction-to-case thermal resistance comes from the joint between chip and substrate, or the die-attach layer. In this study, we evaluated three different types of leading die-attach materials; silver epoxy, lead-free solder, and an emerging nanosilver paste. Each of the three was processed via their respective physical and chemical mechanisms: epoxy curing by cross-linking of polymer molecules; intermetalic soldering by reflow and solidification; and nanosilver sintering by solid-state atomic diffusion. High-power LED chips with a chip area of 3.9 mm2 were attached by the three types of materials onto metalized aluminum nitride substrates, wire-bonded, and then tested in an electro-optical setup. The junction-to-heatsink thermal resistance of each LED assembly was determined by the wavelength shift methodology, described in detail in this paper. We found that the average thermal resistance in the chips attached by the nanosilver paste was the lowest, and it is the highest from the chips attached by the silver epoxy: the difference between the two was about 0.7°C/W, while the difference between the sintered and soldered was about 0.3°C/W. The lower thermal resistance in the sintered joints is expected to significantly improve the photometric flux from the device. Simple calculations, excluding high current efficiency droop, predict that the brightness improvement could be as high as 50% for the 3.9 mm2 chip. The samples will be functionally tested at high current, in both steady-state and pulsed operation, to determine brightness improvements, including the impact of droop. Nanosilver die-attach on a range of chip sizes up to 12 mm2 are also considered and discussed.
3D Modeling of Complex Combinations of Dies, Packages, Lead Frames, Sockets and Test Boards for Electrical, Thermal and Manufacturing Verification of Advanced Semiconductor Devices
Authors: Sovinsky John
Published: October 2015

The software process described permits putting unlimited layers of dies and substrates in the same CAD database where many advanced optimizations and tunings can be accomplished on the entire electronic system simultaneously. Gates and swappable memory and FPGA pins may be optimally selected to reduce wire length and the number of routing layers. Die placement may also be optimized across multiple subtrates for the same purpose.

Interposers between substrates or side routing can be implemented and I/O locations optimized for maximum performance. Native scripts may be used to generate composite electrical models in the major electrical analysis tools that define 3D geometries precisely without 2-1/2 D abbreviations. Exact ACIS and Step models define the complex stackups for Thermal analysis in major Thermal Modeling softwares. All these models are created with high speed which enables the multiple design cycle iterations necessary for the refinement of a quality product. All relevant material properties and ports are exported with the 3D graphical data. Where appropriate changes are initialised back into parametric models.

Customizations of the process by the users are routine.
High Flux Value Micro-Heat Pipe Arrays
Authors: Harris Daniel K. , Dean Robert , Palkar Ashish , Wonacott Gary
Published: October 2015

The concept of heat pipes was introduced by R.S.Gaugler in 1940s and Cotter first introduced the idea of “micro” heat pipes in 1984. Cotter in his paper, defined the micro heat pipe as being one in which the mean curvature of the vapor-liquid interface is comparable in magnitude to the reciprocal of the hydraulic radius of the total flow channel. The Micro Heat Pipes (MHPs) work efficiently through the use of two-phase heat transfer. Various working fluids have been tried in combination with various substrate materials. In this experimental work the main focus was to study the behavior of liquid metal filled MHPs made from silicon as the substrate material. Specially designed MHPs were assembled and charged with mercury as the working fluid. A special test setup was designed and built for the experimental work and the response of the MHPs to the controlled increment in the input power is presented. A number of experiments were carried out on the specimen MHPs to determine their effective thermal conductivity, the variation of the temperature along the axial length and the performance enhancement factor. Effective thermal conductivities as high as 900 W/m-K with a silicon equivalence of 6 were achieved with the liquid metal MHP. Based on the results from the various performance testing parameters, it was observed that the liquid metal charged MHPs performed substantially better than conventional MHPs filled with organic working fluids. The limitations and the possible methods of improving the performance of the MHPs are discussed.
Development of MEMS Power Sensor Package
Authors: Kim Bruce C. , Kasim Rahim
Published: October 2015

This paper presents a design and fabrication of advanced MEMS in high power applications. The developed MEMS is used as a high power sensor for high current applications. We designed and fabricated MxN array of low power MEMS switches to handle high power which are mass actuated by an external magnetic field. The array of MEMS devices has been packaged in a conventional package and testing was performed to validate its operation. The switching time was very compatible with the existing solid state switches with much higher order of power capability.
Design of a MEMS Force Sensor for Quantitative Measurement in the Nano- to Pico-Newton Range
Authors: Liew Li-Anne , Moreland John M. , Pratt Jonathan R.
Published: October 2015

We describe the design and fabrication of a MEMS nano- to pico-Newton force sensor with SI traceability.

There has been much recent interest in developing instrumentation for the quantitative measurement of forces in the nano- to pico-Newton range. Forces in this range are frequently encountered when investigating mechanical properties of nanomaterials, in nanobiotechnology, and in single-molecule biophysics.

Various methods of measuring forces at these levels include using AFM cantilevers, scanning probe microscopy, and nanoindentation. However, such measurements are relative, and in order to obtain precise quantitative measurements, it is necessary to be able to calibrate such sensors in a manner that is traceable to fundamental SI units. One such method of calibration is using an Electrostatic Force Balance (EFB) that has been established at NIST.

We thus describe the design and fabrication of a MEMS-based force sensor that may be directly calibrated with the EFB and thus has the potential to measure nano- to pico-Newtons of force with SI traceability. The sensor consists of a silicon rigid arm supported on silicon tethers and which are attached to capacitive electrodes. The bar, tethers and electrodes are made from the device layer of a double side SOI wafer. A glass wafer with patterned metal electrodes is anodically bonded on both the top and bottom of the wafer to form symmetrical capacitive electrodes. An external force moves the silicon arm and the resulting capacitive force gradient of the electrodes is measured with the EFB. The mechanical structure and electrodes are designed for force sensitivity in the nano- to pico-Newton ranges and for operation in UHV to reduce thermomechanical noise. We discuss the design, initial fabrication and testing of this force sensor as a step toward the ultimate goals of quantitative nanomechanical testing of materials, NEMS, and engineered surfaces at the nanoscale.
A Micromachined Robust Planar Triggered Sparkgap Switch for High Power Pulse Applications
Authors: Baginski Thomas A. , Dean Robert N. , Wild Ed J.
Published: October 2015

High voltage (HV) switches capable of operating at high speeds with high current levels are used in a variety of applications in commercial and government systems. Examples of HV switches include triggered sparkgap, dielectric breakdown, and mercury vapor switches. The triggered sparkgap switch is a three-element, gas-filled, ceramic-to-metal, hermetically sealed, pressurized switch that operates in an arc discharge mode. Triggered sparkgaps have been in use for many years, providing precision timing and activation of in-flight functions such as missile stage separation. These applications involve the activation of electro-explosive devices such as an exploding bridge-wire [EBW] or an exploding foil initiator [EFI]. This paper discusses the fabrication and characterization of a novel high voltage planar discharge switch using micromachining techniques. The switch provides a low cost alternative to conventional triggered sparkgaps. The switch is designed for direct integration into the strip-line geometries used in a conventional capacitive discharge unit (CDU). The geometry of the device was selected to minimize parasitic impedances associated with conventional firing circuits. The switch design is microfabricated on an alumina substrate utilizing a patterned electron-beam deposited metallic stack. A polyimide layer selectively deposited over the metal stack provides dielectric isolation and passivation for the switch electrodes. A similar methodology was utilized to fabricate sample EFIs for switch validation tests with insensitive secondary high explosive (HE) pellets. The discharging of the HV capacitor through the patterened bridgefoil of an EFI results in rapid vaporization of the metal stack. The high pressure gas formed by the vaporized metal accelerates the adjacent polyimide layer to high velocity. The polyimde layer then impacts the HE pellet, inducing a shock wave, which results in prompt detonation of the material. Thus, this device is a type of MEMS actuator with a very specialized use. Design, fabrication and test data are presented and discussed.
Advanced SiP Packaging Technologies of IPD for Mobile Applications
Authors: Kim Geun Sik , Liu Kai , Carson Flynn , Yoon Seung Wook , Padmanathan Meenakshi
Published: October 2015

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices.

Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors.

The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand.

In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important.

This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.
Flip Chip and Wafer Level Packaging - Past, Present and Future
Authors: Elenius Peter
Published: October 2015

Flip chip packaging was developed nearly 50 years ago by IBM for the purposes of improved reliability and automated semiconductor assembly. For the first 35 years the use of flip chip technology was limited to a few large IDMs and automotive companies. Beginning fifteen years ago, companies providing flip chip bumping services were established. The primary reason for adoption of flip chip in the 1990s was to enable higher I/O count chips and to improve the power and ground distribution through the use of area array interconnects. Beginning in the early 2000s high speed serial links and other I/O with fast edge rates required the use of flip chip interconnects to improve signal propagation. In the future a greater percentage of devices will utilize flip chip interconnects as these chip requirements continue to drive increased demand. Future challenges include the requirements for better power and ground distribution, finer pitch interconnects and higher I/O count devices while protecting the every more fragile inter layer dielectrics (ILDs) present on the device.

Wafer Level Package (WLP) technology was developed approximately fifteen years ago to address form factor requirements in mobile products. Today WLPs play an ever increasing role in both mobile and other applications. An understanding of the market drivers, technology limitations, and variety of WLP structures used will be reviewed from both a historical perspective and current implementation. The breadth of products that are currently packaged with WLPs will also be reviewed. The principal challenges for WLPs both today and historically has been to provide adequate thermal cycle reliability and drop test capability for ever increasing device sizes and ball counts. Future market requirements for WLP technology will likely require new structures that can be cost effectively produced.
3D TSV Products
Authors: Marcoux Phil
Published: October 2015

The development of an infrastructure for the 3D and 2.5D assembly infrastructure is progressing on many fronts. Several applications are being discussed but it's still unclear which ones will launch since there are many unanswered issues including cost, reliability, design and test tools, etc. This session summarizes a study of the different types of TSVs being developed and when interposers may be justified. It will conclude by suggesting the possible applications appropriate for the different TSV and interposer types.
PCBMEMS as a Flexible Path to Devices and Systems across Spatial Scales
Authors: Fries David , Hotaling Liesl , Barton Geran , Ivanov Stan , Janowiak Michelle , Smith Matt
Published: October 2015

PCB technology based on both rigid and flexible laminates is desirable for miniaturization of mobile devices and systems. The technology provides substantial flexibility in systems design. The ability to use flexible microsystems allows new sensing systems for mobile applications. Using this design, fabrication and construction approach allows lightweight, complex, and space efficient systems. Flex microsystems based on structurable, non-fiber filled laminates permits miniaturization to occur at two levels: at the micro scale with the embedding of microstructures in the substrate, and at the macro scale with the ability to flex the system across millimeter to centimeter lengths of real everyday objects. The macro scale systems further allows ultra large systems with high resolution features permitting novel sensor systems. Examples will be given where the technology has enabled devices, systems and packaging innovation across several spatial scales. Mobile (environmental, medical, portable, embedded) sensor systems all can be realized using this design and fabrication toolbox.
SUEX Laminates for Fan-In, Fan-Out and eWLB Development
Authors: Johnson Donald W. , Tsai Bin-Hong
Published: October 2015

The focus of this presentation is on the use of SUEX epoxy Thick Dry Film Sheets (TDFS) as a photoimagable dielectric layer in fan-in, fan-out and e-WLP applications. The sheets can be laminated over severe topography from under 2 μm to over 200 μm in height yielding void free coatings with 100% planarization over the entire substrate. The TDFS are available in a range of thicknesses and wafer or panel sizes.

This new material is prepared under a highly controlled solvent-less process, which provides uniform coatings between two throw-away layers of protective polyester film. SUEX sheets of 100 μm thickness have been vacuum laminated in an isothermal process at 60–80°C over 180 μm high, 2mm X 2mm device chips mounted onto a silicon carrier wafer. Process optimization studies were run to determine the desired chamber vacuum, chuck temperature, lamination pressure and lamination time for optimal performance. The entire lamination process has a cycle time of about 10min.

Using a vacuum laminator we have been able to obtain totally void-free coatings over 2 to 5 μm high bonding pads and buss lines at the silicon surface with a resist thickness of 205 μm over the trench and 25 μm thickness over the back of the chip with 100% planarization over the surface interface. Exposures on a contact aligner have yielded nominal 50 μm diameter via holes through the resist film to the contact pads at the bottom of the trench. Excellent adhesion to all surfaces on both the carrier wafer and the device chip has been obtained without any delamination or crack formation. Additional work to be presented will demonstrate the filling of the vias with electroplated copper to form interconnects the interconnects to for connection to bonding pads on the fan-out package surface.
Failure Analysis and Reliability of 3D Integrated Systems
Authors: Ramm Peter , Klumpp Armin , Franz German , Kwakman Laurens
Published: October 2015

Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines.

A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT.

The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from −55 C ° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering.

The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT's TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail.
Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages
Authors: Katkar Rajesh , Huynh Michael , Mirkarimi Laura
Published: October 2015

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance.

Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.
Electrolytic Solder Deposition for IC-Substrates: From Deposition Uniformity to Solder Ball Geometry
Authors: Roelfs Bernd , Matejat Kai
Published: October 2015

The current screen printing process for solder deposition on IC substrates is coming to a technology boundary due to the continuous down sizing of the solder structures. This will require soon new methods of solder transfer to the substrate. This paper describes an alternative process based on electrolytic deposition of Tin and Tin alloys for sub 100 μm solder balls. A suitable process sequence is evaluated and described in detail.

Uniformity of the electroplated deposits both in terms of solder thickness and chemical composition is of vital importance for the process. Thickness determines the solder ball diameter after reflow and elemental composition influences the reflow performance and solder joint reliability. We will present in this paper results from an investigation program to identify main parameters for the distribution of the plated solder. Main emphasis is here on difference between direct plated (DC) and reverse pulse plated (RPP)deposits. We want to clarify if reverse pulse plated layers exhibit a better distribution than dc plated deposits as known from other applications. As a 2nd very important parameter electrolyte flow is identified. We will show how variations in these parameters itself are translated first in variations of the plated layer and then – after reflow- into different solder ball geometries.

Understanding these influences will help introducing this technology into future production scenarios.
Novel Die-to-Wafer Interconnect Process for 3D-IC Utilizing a Thermo-Decomposable Adhesive and Cu-Cu Thermo-Compression Bonding
Authors: Pascual Daniel N.
Published: October 2015

Die-to-wafer interconnect offers key advantages for 3D-IC including heterogeneous die population using devices from different process lines, and higher yield by incorporating only known-good die. Attaching the dies to a wafer, however, typically involves serial processing whereby each die is aligned and bonded one at a time. This can be prohibitively time consuming particularly when using a slow, high-temperature process such as Cu-Cu thermo-compression for each die in succession. Also, the high temperatures applied locally can adversely affect neighboring sites by oxidizing the Cu bonding surface if not protected in an oxygen-free environment. We have developed a novel die-to-wafer interconnect process that circumvents these problems using a die-tacking and global-bonding approach.

Using a high-accuracy die placement tool, individual dies are aligned and tacked onto a wafer that is coated with a thermo-decomposable adhesive layer. The low-temperature tacking process avoids oxidation of the Cu bonding surfaces, minimizes thermal cycling, and increases throughput significantly. Once the wafer is fully populated, it is then processed in a closed-chamber wafer-bonding tool, which provides an oxygen-free environment. All of the dies are bonded in parallel using a high-temperature Cu-Cu bonding process to globally apply the required heat and force. Once the adhesive is heated past its critical decomposition temperature, it cleanly vaporizes away and allows the Cu-Cu bonding to proceed.

We have successfully demonstrated this process on a 300mm platform using custom-designed test dies and wafers containing through-silicon via (TSV) chains and Kelvin test structures providing 4-point resistance measurements. Experimental results including TSV chain yield, electrical resistance, alignment accuracy, and cross-sectional analysis will be presented. A discussion will also be given on the potential cost savings and future technical challenges of this approach.
Hetero-Structure Integration using an Atmospheric Plasma Treatment for Surface Preparation before its Interconnection
Authors: Charlet Barbara , Charlet B. , Di Cioccio L. , Rochat N. , Renault O. , Clavelier L. , Deguet C.
Published: October 2015

One of the open challenges, related to the heterogeneous devices stacking, is its surface preparation, in order to assure the optimal electrical connections, and finally achieve the high performance structures having the stacked chips and passive components.

Several techniques, using dry or wet process, allow the surface activation and preparation before the successive vertical interconnection achievement. We report the implementation of an environment friendly method, developed for chips and passive circuits surface preparation before its interconnection. This method is based on the use of atmospheric-pressure plasma source generating the radicals flux in the nitrogen or noble gases, mixed with a small volume of reactive gases, in order to stimulate the surface reactions. The surface properties of various treated materials were characterised by water drop contact angle, FTIR and TXRF method. The results of these behaviours allow defining a dedicated flow chart, in order to apply this surface treatment for the self-positioning of small silicon chips on the connection pads of printed passive circuits. Optimised process was applied to the silicon ICs chips assembly on the flexible polymeric substrates with passive devices; furthermore the treatment potentiality was also proved for other type of substrates and materials used for hetero structure integration. The application example given in this study concerns a novel approach of FRID tag assembly.
Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding
Authors: Lee Sang Hwui , Khbeis Michael
Published: October 2015

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.
Permanent Attachment of Silicon Structures via Joule Heat Induced Welding
Authors: Schofield Adam R. , Trusov Alexander A. , Shkel Andrei M.
Published: October 2015

We introduce a new method for the permanent attachment of assembled silicon microstructures using the precise application of current for localized welding. The attachment technique for planar SOI structures was demonstrated using an assembly mechanism that allows the post-release adjustment of micromachined gaps. The concept utilizes a mechanical assembly technique that takes advantage of the motion reduction experienced by the individual beams of a folded suspension ultimately allowing sub-micron position control of released structures. The proposed mechanism was incorporated into the sense mode of a symmetrically decoupled MEMS tuning fork gyroscope in order to demonstrate its potential for the realization of high performance inertial sensors. Two types of mechanisms were implemented resulting in 7.8 and 8.8 % motion reduction allowing capacitive gaps of 7.5 μm to be adjusted to 1.67 μm; the gaps can be further reduced by alternate suspension designs and implemented on arbitrarily thick layers. After assembly, the mobile electrode structure was rigidly attached to the anchor by locally melting the interface via a controlled current. The weld is achieved by applying 15 V with a current limit of 3 mA across the latching mechanism resulting in the permanent attachment of the two structures. Thus, when the desired gap is achieved, the previously released anchor can be fixed to eliminate any potential spurious motion of the electrodes. Our results demonstrate feasibility of the approach, which can be extended beyond planar devices to include out of plane and die-level 3-D assembled structures that typically rely on epoxy bonding or solder assembly to maintain their shape.
Packaging Strategies for Mitigation of Mechanical Noise in Sensor Systems
Authors: Reiner Philip , Long Calvin W.
Published: October 2015

Sensors are often required to operate within mechanical structures that present a variety of unwanted acoustic signals that can significantly deteriorate sensor performance. This problem is exacerbated when the sensor and associated electronics are reduced in size. MEMS devices by their very nature and size have mechanical resonances that are often in the hundreds of megahertz to gigahertz range. These ranges of frequencies are very difficult to measure and present unique problems for package design. In this paper we explore various techniques for mitigating these types of mechanical responses. We show how to properly characterize noise signatures and show how proper packaging design can be used to either block unwanted signals or reduce their amplitudes to acceptable levels.
Cu MEMS
Authors: Ellis Charles , Beal Aubrey , Dean Robert
Published: October 2015

Many types of MEMS devices have been fabricated through electro- or electroless-plating of metals, such as Ni. Typically, this is accomplished using LIGA or LIGA-like processes where the metal is plated into a mold fabricated through patterning a photoimageable polymeric layer. After plating, the polymeric mold is removed though chemical etching or ashing, leaving the freestanding metal structure. Through the advent of TSV technology, techniques have been developed for plating Cu into DRIE etched vias in Si wafers. This technology has matured to the point where arrays of defect free plated Cu vias can be realized across the surface of the Si wafer. TSVs generally require small diameter Cu posts extending through the depth of the Si wafer between a bond pad on each surface. However, this technology can be modified to filling other types of DRIE etched features with plated Cu to realize complex 3D Cu microstructures in and on the Si wafer. Furthermore, the Si die containing these Cu structures can be eutectically bonded to other surfaces, such as pads on printed circuit boards. Then the Cu structure can be released from the bulk Si though exposing it to XeF2 gas in a low vacuum. This gas chemically converts solid Si to gaseous SiF2, but is nonreactive with most other materials, including Cu, SiO2 and E-glass. After the bulk Si has been removed through this process, the free standing Cu microstructure remains, attached to the substrate to which it was eutectically bonded. A variety of MEMS devices can be realized with this technique, such as antennas, inductors, air gap capacitors, sensors and electrostatic actuators.
300mm Large Scale eWLB(embedded Wafer Level BGA) : Cost Effective Solution with Performance
Authors: Yoon Seung Wook , Lin Yaojian , Marimuthu Pandi C. , Lee Yeong J.
Published: October 2015

Demand for Wafer Level Package (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. The increasing demand for new and more advanced electronic products with smaller form factor, superior functionality and performance is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. 200mm eWLB is in HVM from industry last three years and there was need to move 300mm for scaling-up and low-cost solutions.

This paper will highlight some of the recent advancements in large scale 300mm eWLB development. Compared to 200mm case, 300mm has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100~150% more warpage with 300mm compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper presents study of process optimization for 300mm eWLB and mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps of scalability for higher throughput and manufacturability.