bluuebunny/crossref_metadata_2025 huggingface dataset:
Physiological analysis of the lymphatic system in the eastern painted turtle (Chrysemys picta picta)
Authors: Walker Mary E. , Wolfe Deanna C. , Toews Daniel P.
Published: April 2008

Examination into the anuran lymphatic system has led to a comprehensive understanding of lymphatics, including the importance of synchrony in fluid-balance maintenance. However, little research has been conducted on the lymphatics of turtles and other reptilian vertebrates. Using pressure-peak recordings created through cannulation of both lymph hearts of the eastern painted turtle, Chrysemys picta picta (Schneider, 1783), the lymph heart contraction rate was verified and the interbeat interval patterns were examined using Poincaré plots. The lymph heart beating rate was determined to be 38.2 beats·min–1with a mean pulse pressure of 2.40 ± 1.44 mm Hg (1 mm Hg at 0 °C = 133.3224 Pa). Poincaré plots are useful in displaying nonlinear sequential data and are often given descriptive names related to the overall pattern. The Poincaré plot resembled a garden hose nozzle spray, indicating a large variability in interbeat time intervals with periods of multiple-beat patterns. The degree of bilateral lymph heart synchrony was determined in the turtle using the mean time difference between right and left lymph heart systoles. Results show that chelonian lymph hearts do in fact beat in synchrony, with over 50% of contractions occurring within 100 ms of each other. This indicates shared neuronal control and may suggest an energetic advantage to fluid homeostasis.
FREE ENERGY DENSITY FOR MEAN FIELD PERTURBATION OF STATES OF A ONE-DIMENSIONAL SPIN CHAIN
Authors: HIAI FUMIO , MOSONYI MILÁN , OHNO HIROMICHI , PETZ DÉNES
Published: April 2008

Motivated by recent developments on large deviations in states of the spin chain, we reconsider the work of Petz, Raggio and Verbeure in 1989 on the variational expression of free energy density in the presence of a mean field type perturbation. We extend their results from the product state case to the Gibbs state case in the setting of translation-invariant interactions of finite range. In the special case of a locally faithful quantum Markov state, we clarify the relation between two different kinds of free energy densities (or pressure functions).
STUDIES ON NEON IRRADIATED AMORPHOUS CARBON USING X-RAY DIFFRACTION TECHNIQUE
Authors: SARKAR A. , DASGUPTA K. , BARAT P. , MUKHERJEE P. , SATHIYAMOORTHY D.
Published: April 2008

Two sets of amorphous carbon materials prepared at different routes are irradiated with swift (145 MeV) heavy ion ( Ne 6+). The structural parameters like the extent of local ordering along the c and a axis i.e., Lc and La, the average spacing of the crystallographic planes (002) i.e., d002 and the fraction of the amorphous phase of the unirradiated and the irradiated samples are estimated by X-ray diffraction technique. The fraction of the amorphous phase is generally found to increase with the irradiation dose for both sets of the samples. The estimated d002 values are found to be almost unaffected by irradiation but Lc and La are decreased slightly with irradiation. The estimated values of Lc and La corroborate with the increase of disorder in both sets of the samples with the increasing dose of irradiation.
Siam Makro Public Limited
Authors: Venkatesh Sundar , Puntsagdavaaa Ayurzana
Published: April 2008

The case provides background to the retail industry as well as excerpts from specialist reports forecasting the evolution of the retail industry in Thailand. The operating and financial data, covering a period of six years, of two companies in the retail industry in Thailand are also given. This case enables students to carry out computations and analyses to make comparisons of the financial performance of the two companies: Big C and Siam Makro Public Limited. Based on the comparisons of the financial performance of two companies within the same industry, students can draw conclustions with regard to the differences in the strategies of the two companies and how these differences affect their performances.
Six Sigma Implementation at Bharti Infotel
Authors: Shukla Archana , Srinivasan R.
Published: April 2008

Bharti Airtel Limited was a leading private sector provider of telecommunication services in India, with a customer base of 8.73 million as of July 2004. The company had two branch companies — Bharti Infotel (that dealt with fixed line, long distance, and enterprise services) and Bharti Cellular (that dealt with mobile telephone services). This case is about the six sigma implementation at Bharti Infotel.

The case briefly discusses the business imperatives in the fast changing Indian telecommunications industry. The industry was a monopoly for over half a century after independence and had recently been deregulated with the private players competing with the state-owned BSNL. The industry had exploded in the recent years with increasing number of players, falling tariffs, and improving technology. Stiff competition in the industry meant that any competitive action by a company was immediately imitated by others. Therefore the only sources of competitive advantage in the industry were “quality of service” and “speed”.

This case discusses the various steps in the implementation of six sigma quality management system in the company. The company had already implemented Business Process Management Systems (BPMS) and had begun monitoring their performance on the Non-Financial Parameters (NFPs). The six sigma initiative was expected to leverage on these initiatives. Following the six sigma initiative was the Knowledge Management (KM) initiative that was intended to help share the best practices and learning from the six sigma projects across the entire organization.

This case highlights the contribution of the six sigma quality management initiative to the company's business strategy, and helps students analyze the process of implementing and institutionalizing the six sigma initiative. The case enables the readers to appreciate the business benefits of six sigma implementation and how it fosters innovation.
LONG-RANGE DEPENDENCE IN EXCHANGE RATES: THE CASE OF THE EUROPEAN MONETARY SYSTEM
Authors: SOUZA SERGIO R. S. , TABAK BENJAMIN M. , CAJUEIRO DANIEL O.
Published: April 2008

In this work we measure the evolution of the long-range dependence phenomenon of returns and volatilities of nominal British exchange rates (British pound against US dollar) futures contracts negotiated on the Chicago Mercantile Exchange from 1986 to 2004. The measurement employs the R/S classic analysis, Detrended Fluctuation Analysis and Generalized Hurst exponents, upon a 1008-observation window, which moves along the data. We obtain as a result, the effects of the 1992 European financial crisis on the measurements of the long-range dependency phenomenon. After the crisis the returns of this futures contract showed no signs of the long-range memory, which existed before the crisis. The volatility presented moderate long-range memory the whole time. We also test for long-memory in European currencies inside the European Monetary System and find evidence of moderate long memory, which suggests that being inside the EMS increases predictability.
CONFLICT IDENTIFICATION AND RECONCILIATION IN A COLLABORATIVE MANUFACTURING SCHEDULING TASK
Authors: ABREU CLAUDIO F. , MAY JERROLD H. , SPANGLER WILLIAM E. , VARGAS LUIS G.
Published: April 2008

We studied the process of production scheduling in a large chemical plant. Scheduling in that environment is inherently a group process because multiple experts are needed to construct a schedule and to manage its execution. A mathematical formulation of the production scheduling problem yields a mixed-integer linear programming model too large to solve in a reasonable time with current technology. We therefore use an intelligent decision support system (DSS) to heuristically find a satisficing solution to the production scheduling problem. Our DSS is based on a model of the collaborative nature of the task, and it focuses on the communication, argumentation, and reconciliation strategies undertaken by individuals. Using actual production schedules, we show that our DSS can lead to measurable improvements over humanly-designed plans, where the quality of the schedule is measured using the objective function of the mathematical formulation of the problem.
A MIN–MAX GOAL PROGRAMMING APPROACH TO PRIORITY DERIVATION IN AHP WITH INTERVAL JUDGEMENTS
Authors: DESPOTIS DIMITRIS K. , DERPANIS DIMITRIS
Published: April 2008

We deal with the problem of priority elicitation in the analytic hierarchy process (AHP) on the basis of imprecise pair-wise comparison judgements on decision elements. We propose a min–max goal programming formulation to derive the AHP priorities in the case that the decision maker provides preference judgements in the form of interval numbers. By applying variable transformations, we formulate a linear programming model that is capable of estimating the priorities from both consistent and inconsistent interval judgements. The proposed method is illustrated by numerical examples.
Problems encountered by novice pair programmers
Authors: Hanks Brian
Published: April 2008

In a study of the types of problems encountered by students that led them to seek assistance, Robins et al. [2006] found that the most common problems were related to trivial mechanics. The students in this study worked by themselves on their programming exercises. This article discusses a replication of the Robins et al. study in which the subjects pair programmed. The types of problems encountered by the pairing students were similar to those of the solo students. The number of problems requiring assistance was much smaller for the pairing students, which suggests that they were able to resolve more problems on their own.
A study of the development of students' visualizations of program state during an elementary object-oriented programming course
Authors: Sajaniemi Jorma , Kuittinen Marja , Tikansalo Taina
Published: April 2008

Students' understanding of object-oriented (OO) program execution was studied by asking students to draw a picture of a program state at a specific moment. Students were given minimal instructions on what to include in their drawings in order to see what they considered to be central concepts and relationships in program execution. Three drawing tasks were given at different phases of an elementary OO programming course where two animation tools were used for program visualization. The drawings were analyzed for their overall approaches and their detailed contents.

There was a large variability in the overall approaches and the popularity of various approaches changed during the course. The results indicate that students' mental representations of OO concepts and program execution not only grow as new material is covered in teaching, but they also change. The first drawings treat methods as having primarily a static existence; later methods are seen as dynamic invocations that call each other. The role of classes in program execution fluctuates during learning, indicating problems in locating the notion of class with respect to, for example, objects. Two major sources of problems that manifested in many different forms were the relationship between object and method, and the role of the main method with respect to program state. Other problems were caused by overly simplistic understanding of object identification and improper use of application domain knowledge.
Uniform deterministic dictionaries
Authors: Ružić Milan
Published: April 2008

We present a new analysis of the well-known family of multiplicative hash functions, and improved deterministic algorithms for selecting “good” hash functions. The main motivation is realization of deterministic dictionaries with fast lookups and reasonably fast updates. The model of computation is the Word RAM, and it is assumed that the machine word-size matches the size of keys in bits. Many of the modern solutions to the dictionary problem are weakly nonuniform, that is, they require a number of constants to be computed at “compile time” for the stated time bounds to hold. The currently fastest deterministic dictionary uses constants not known to be computable in polynomial time. In contrast, our dictionaries do not require any special constants or instructions, and running times are independent of word (and key) length. Our family of dynamic dictionaries achieves a performance of the following type: lookups in time
O
(
t
) and updates in amortized time
O
(
n

1/
t

), for an appropriate parameter function
t
. Update procedures require division, whereas searching uses multiplication only.
Alternation and redundancy analysis of the intersection problem
Authors: Barbay Jérémy , Kenyon Claire
Published: April 2008

The
intersection of sorted arrays
problem has applications in search engines such as Google. Previous work has proposed and compared deterministic algorithms for this problem, in an adaptive analysis based on the encoding size of a certificate of the result (cost analysis). We define the
alternation analysis
, based on the nondeterministic complexity of an instance. In this analysis we prove that there is a deterministic algorithm asymptotically performing as well as any randomized algorithm in the comparison model. We define the
redundancy analysis
, based on a measure of the internal redundancy of the instance. In this analysis we prove that any algorithm optimal in the redundancy analysis is optimal in the alternation analysis, but that there is a randomized algorithm which performs strictly better than any deterministic algorithm in the comparison model. Finally, we describe how these results can be extended beyond the comparison model.
Finding a long directed cycle
Authors: Gabow Harold N. , Nie Shuxin
Published: April 2008

Consider a digraph with
n
vertices. For any fixed value
k
, we present linear- and almost-linear-time algorithms to find a cycle of length ≥
k
, if one exists. We also find a cycle that has length ≥ log
n
/log log
n
in polynomial time, if one exists. Under an appropriate complexity assumption it is known to be impossible to improve this guarantee by more than a log log
n
factor. Our approach is based on depth-first search.
Faster approximation schemes for fractional multicommodity flow problems
Authors: Karakostas George
Published: April 2008

We present fully polynomial approximation schemes for concurrent multicommodity flow problems that run in time of the minimum possible dependencies on the number of commodities
k
. We show that by modifying the algorithms by Garg and Könemann [1998] and Fleischer [2000], we can reduce their running time on a graph with
n
vertices and
m
edges from
Õ
(ε
−2
(
m
2
+
km
)) to
Õ
(ε
−2
m
2
) for an
implicit
representation of the output, or
Õ
(ε
−2
(
m
2
+
kn
for an
explicit
representation, where
Õ
(
f
) denotes a quantity that is
O
(
f
log

O
(1)

m
). The implicit representation consists of a set of trees rooted at sources (there can be more than one tree per source), and with sinks as their leaves, together with flow values for the flow directed from the source to the sinks in a particular tree. Given this implicit representation, the approximate value of the concurrent flow is known, but if we want the explicit flow per commodity per edge, we would have to combine all these trees together, and the cost of doing so may be prohibitive. In case we want to calculate explicitly the solution flow, we modify our schemes so that they run in time polylogarithmic in
nk
(
n
is the number of nodes in the network). This is within a polylogarithmic factor of the trivial lower bound of time Ω(
nk
) needed to explicitly write down a multicommodity flow of
k
commodities in a network of
n
nodes. Therefore our schemes are within a polylogarithmic factor of the minimum possible dependencies of the running time on the number of commodities
k
.
Getting to "we"
Authors: Denning Peter J. , Yaholkovsky Peter
Published: April 2008

Solidarity, not software, generates collaboration.
Solving Rubik's Cube
Authors: Kunkle Daniel , Cooperman Gene
Published: April 2008

Substituting disk for RAM, disk-based computation is a way to increase working memory and achieve results that are not otherwise economical.
Designing a learning management system to support instruction
Authors: Yueh Hsiu-Ping , Hsu Shihkuan
Published: April 2008

The goal of an LMS, devised by a growing number of universities, is to offer faculty instructional support. The actual use of these programs, however, suggests thatsupport is elusive. An experience at National Taiwan University illustrates how a university can increase faculty usage through better LMS design.
Agile dynamic provisioning of multi-tier Internet applications
Authors: Urgaonkar Bhuvan , Shenoy Prashant , Chandra Abhishek , Goyal Pawan , Wood Timothy
Published: April 2008

Dynamic capacity provisioning is a useful technique for handling the multi-time-scale variations seen in Internet workloads. In this article, we propose a novel dynamic provisioning technique for multi-tier Internet applications that employs (1) a flexible queuing model to determine how much of the resources to allocate to each tier of the application, and (2) a combination of predictive and reactive methods that determine when to provision these resources, both at large and small time scales. We propose a novel data center architecture based on virtual machine monitors to reduce provisioning overheads. Our experiments on a forty-machine Xen/Linux-based hosting platform demonstrate the responsiveness of our technique in handling dynamic workloads. In one scenario where a flash crowd caused the workload of a three-tier application to double, our technique was able to double the application capacity within five minutes, thus maintaining response-time targets. Our technique also reduced the overhead of switching servers across applications from several minutes to less than a second, while meeting the performance targets of residual sessions.
Social network?
Authors: Treese Win
Published: April 2008

There's an electronic mailing list I've been on for about 15 years. Most of the members have been on it at least that long. Every day for the past 15 years there is mail. Every member knows at least some of the other members from "real world" experience, although I'd guess that no one on the list has actually met everyone else in person.
Hey, providers, leave our bits alone!
Authors: Weiss Aaron
Published: April 2008

In the beginning, Internet service providers carried our bits from one place to another. Politicians called it the "information superhighway" and we laughed at their simplistic analogy (and also, because laughing at politicians is fun and easy). But if their beloved buzzword seemed simple at the time, maybe that's because they were kinda right. ISPs laid the roads. They weren't in the business of regulating what we did on them.
From Conference to Journal
Authors: McCartney Robert , Tenenberg Josh
Published: April 2008

Revising and extending conference articles for journal publication benefits both authors and readers. The new articles are more complete, and benefit from peer review, feedback from conference presentation, and greater editorial consistency. For those articles that are appropriate, we encourage authors to do this, and present two examples of such articles in this issue.
Teaching Design Patterns Through Computer Game Development
Authors: Gestwicki Paul , Sun Fu-Shing
Published: April 2008

We present an approach for teaching design patterns that emphasizes object-orientation and patterns integration. The context of computer game development is used to engage and motivate students, and it is additionally rich with design patterns. A case study is presented based on
EEClone
, an arcade-style computer game implemented in Java. Our students analyzed various design patterns within EEClone, and from this experience, learned how to apply design patterns in their own game software. The six principal patterns of EEClone are described in detail, followed by a description of our teaching methodology, assessment techniques, and results.
Interview with Wendy Hall
Authors: Atzenbeck Claus
Published: April 2008

Wendy Hall is Professor of Computer Science at the University of Southampton, UK, and was Head of the School of Electronics and Computer Science from 2002 to 2007. Her team invented the ground-breaking Microcosm hypermedia system, which pre-dated the Web, and for which a patent was granted.

Her research interests now include the development of web technologies (particularly the Semantic Web), hypermedia systems and link services, advanced knowledge technologies, digital libraries, decentralized information systems, and human computer interaction. She has published over 350 papers in areas such as hypermedia, multimedia, digital libraries, and distributed information systems.

She is founding director, along with Professor Sir Tim Berners-Lee, Professor Nigel Shadbolt, and Daniel J. Weitzner, of the Web Science Research Initiative, which was launched in 2006 as a long-term research collaboration between the University of Southampton and MIT.

She holds a number of prestigious leadership roles. She is currently senior Vice President of the Royal Academy of Engineering, and was President of the British Computer Society (2003-2004). She is a member of the Institute of Engineering and Technology (IET) Council and Publications Board and also Vice-President of the Association for Computing Machinery (ACM). She is a member of IW3C2 and was executive chair of the 15th International WWW conference in Edinburgh in May 2006. In April 2007 she joined the Board of the British Library.
WikiSym 2007
Authors: Désilets Alain
Published: April 2008

From October 21st to 23rd of 2007, I had the pleasure of chairing the 3
rd
International Symposium on Wikis (WikiSym 2007) in my native town of Montréal, Canada. Robert Biddle (Carleton University) was program chair and the theme we had chosen for the event was "
Wikis at Work in the World: Open, Organic and Participatory Media for the 21st Century
". We saw this as an invitation for all attendants to think about the various ways in which wiki technologies and paradigms are and will keep changing the world. I'm happy to report that they did!
Pattern-based segmentation of digital documents
Authors: Iorio Angelo Di
Published: April 2008

Angelo Di Iorio received a PhD in Computer Science from the University of Bologna, Italy. The title of his thesis is "Pattern-based Segmentation of Digital Documents: Model and Implementation". His research cover markup-languages, collaborative authoring, document versioning, content analysis and (re-)formatting, e-learning, and semantic web technologies. His interests have recently been extended towards layout languages and algorithms.
1st International Global Requirements Engineering Workshop --- GREW'07
Authors: Gorschek Tony , Fricker Samuel , Felt Robert , Wohlin Claes , Mattsson Michael
Published: April 2008

GREW'07 was held in conjunction with the International Conference on Global Software Engineering in Munich Germany. The aim was to bring researchers and industry practitioners together to discuss the area of global product development from a requirements engineering and product management perspective. The workshop aimed to analyze selected challenges put forward by accepted papers from both industry and academia. The session discussions then focused on identifying future needs for research, the relevance of which was assured by good industry presence at the workshop. The workshop resulted in a number of findings that can play an important role to further develop the field of global product management and requirements engineering.
Non homogenous poisson process based cumulative priority model for determining optimal software testing period
Authors: Srivastava Praveen R , Pareek Deepak , Sati Kailash , Pujari Dinesh C , Raghurama G
Published: April 2008

A software organization can obtain benefits from testing only when testing time is optimized and components of greater priorities are tested much rigorously. Critical errors, if remain undetected during testing can result in loss of revenues and goodwill for the organization. In this paper, we present a cumulative priority based model for determining the optimal testing period. Here we provide a Non Homogenous Poisson Process based model to help organizations achieve optimum software testing with minimal time and money loss.
Component behavior relativity analysis
Authors: Wei Wang , Tong Li
Published: April 2008

Component-Based Development, CBD for short, is becoming a main stream software development paradigm which reuses the off-the-shelf components and assembles them together to form a component-based application. CBD paradigm obviously has aroused a great attention among the engineering and academic domain and many new concepts, tools, and development methodologies have been coming out. However, CBD paradigms are usually questioned by its feasibility and performance. The inherent reason of this dilemma is lacking a methodology to guide researchers or engineers to clarify the behavior relativity among components. In this paper we proposed a new formalism, named component network, which is an extension of Petri net and its powerful capability to modeling distributed system is the guarantee of successful modeling component-based system. Further more, a series operation and theorems are presented, which are concerned to be the footstone of component behavior relativity analysis and software evolution research.
PICSEL
Authors: Mallik Arindam , Cosgrove Jack , Dick Robert P. , Memik Gokhan , Dinda Peter
Published: April 2008

The ultimate goal of a computer system is to satisfy its users. The success of architectural or system-level optimizations depends largely on having accurate metrics for user satisfaction. We propose to derive such metrics from information that is "close to flesh" and apparent to the user rather than from information that is "close to metal" and hidden from the user. We describe and evaluate PICSEL, a dynamic voltage and frequency scaling (DVFS) technique that uses measurements of variations in the rate of change of a computer's video output to estimate user-perceived performance. Our adaptive algorithms, one conservative and one aggressive, use these estimates to dramatically reduce operating frequencies and voltages for graphically-intensive applications while maintaining performance at a satisfactory level for the user. We evaluate PICSEL through user studies conducted on a Pentium M laptop running Windows XP. Experiments performed with 20 users executing three applications indicate that the measured laptop power can be reduced by up to 12.1%, averaged across all of our users and applications, compared to the default Windows XP DVFS policy. User studies revealed that the difference in overall user satisfaction between the more aggressive version of PICSEL and Windows DVFS were statistically insignificant, whereas the conservative version of PICSEL actually improved user satisfaction when compared to Windows DVFS.
Hardbound
Authors: Devietti Joe , Blundell Colin , Martin Milo M. K. , Zdancewic Steve
Published: April 2008

The C programming language is at least as well known for its absence of spatial memory safety guarantees (i.e., lack of bounds checking) as it is for its high performance. C's unchecked pointer arithmetic and array indexing allow simple programming mistakes to lead to erroneous executions, silent data corruption, and security vulnerabilities. Many prior proposals have tackled enforcing spatial safety in C programs by checking pointer and array accesses. However, existing software-only proposals have significant drawbacks that may prevent wide adoption, including: unacceptably high run-time overheads, lack of completeness, incompatible pointer representations, or need for non-trivial changes to existing C source code and compiler infrastructure.

Inspired by the promise of these software-only approaches, this paper proposes a hardware bounded pointer architectural primitive that supports cooperative hardware/software enforcement of spatial memory safety for C programs. This bounded pointer is a new hardware primitive datatype for pointers that leaves the standard C pointer representation intact, but augments it with bounds information maintained separately and invisibly by the hardware. The bounds are initialized by the software, and they are then propagated and enforced transparently by the hardware, which automatically checks a pointer's bounds before it is dereferenced. One mode of use requires instrumenting only malloc, which enables enforcement of perallocation spatial safety for heap-allocated objects for existing binaries. When combined with simple intraprocedural compiler instrumentation, hardware bounded pointers enable a low-overhead approach for enforcing complete spatial memory safety in unmodified C programs.
Predictor virtualization
Authors: Burcea Ioana , Somogyi Stephen , Moshovos Andreas , Falsafi Babak
Published: April 2008

Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology advances offer an increased amount of on-chip resources, these resources are allocated to increase the size of on-chip conventional cache hierarchies.

This work proposes
Predictor Virtualization
, a technique that uses the existing memory hierarchy to emulate large predictor tables. We demonstrate the benefits of this technique by virtualizing a state-of-the-art data prefetcher. Full-system, cycle-accurate simulations demonstrate that the virtualized prefetcher preserves the performance benefits of the original design, while reducing the on-chip storage dedicated to the predictor table from 60KB down to less than one kilobyte.
Tapping into the fountain of CPUs
Authors: Weinsberg Yaron , Dolev Danny , Anker Tal , Ben-Yehuda Muli , Wyckoff Pete
Published: April 2008

The constant race for faster and more powerful CPUs is drawing to a close. No longer is it feasible to significantly increase the speed of the CPU without paying a crushing penalty in power consumption and production costs. Instead of increasing single thread performance, the industry is turning to multiple CPU threads or cores (such as SMT and CMP) and heterogeneous CPU architectures (such as the Cell Broadband Engine). While this is a step in the right direction, in every modern PC there is a wealth of untapped compute resources. The NIC has a CPU; the disk controller is programmable; some high-end graphics adaptersare already more powerful than host CPUs. Some of these CPUs can perform some functions more efficiently than the host CPUs. Our operating systems and programming abstractions should be expanded to let applications tap into these computational resources and make the best use of them.

Therefore, we propose the H
YDRA
framework, which lets application developers use the combined power of every compute resource in a coherent way. H
YDRA
is a programming model and a runtime support layer which enables utilization of host processors as well as various programmable peripheral devices' processors. We present the frameworkand its application for a demonstrative use-case, as well as provide a thorough evaluation of its capabilities. Using H
YDRA
we were able to cut down the development cost of a system that uses multiple heterogenous compute resources significantly.
Communication optimizations for global multi-threaded instruction scheduling
Authors: Ottoni Guilherme , August David I.
Published: April 2008

The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several limit studies, most of the parallelization opportunities require looking for parallelism beyond local regions of code. To exploit these opportunities, especially for sequential applications, researchers have recently proposed global multi-threaded instruction scheduling techniques, including DSWP and GREMIO. These techniques simultaneously schedule instructions from large regions of code, such as arbitrary loop nests or whole procedures, and have been shown to be effective at extracting threads for many applications. A key enabler of these global instruction scheduling techniques is the Multi-Threaded Code Generation (MTCG) algorithm proposed in [16], which generates multi-threaded code for any partition of the instructions into threads. This algorithm inserts communication and synchronization instructions in order to satisfy all inter-thread dependences.

In this paper, we present a general compiler framework, COCO, to optimize the communication and synchronization instructions inserted by the MTCG algorithm. This framework, based on thread-aware data-flow analyses and graph min-cut algorithms, appropriately models andoptimizes all kinds of inter-thread dependences, including register, memory, and control dependences. Our experiments, using a fully automatic compiler implementation of these techniques, demonstrate significant reductions (about 30% on average) in the number of dynamic communication instructions in code parallelized with DSWP and GREMIO. This reduction in communication translates to performance gains of up to 40%.
Xoc, an extension-oriented compiler for systems programming
Authors: Cox Russ , Bergan Tom , Clements Austin T. , Kaashoek Frans , Kohler Eddie
Published: April 2008

Today's system programmers go to great lengths to extend the languages in which they program. For instance, system-specific compilers find errors in Linux and other systems, and add support for specialized control flow to Qt and event-based programs. These compilers are difficult to build and cannot always understand each other's language changes. However, they can greatly improve code understandability and correctness, advantages that should be accessible to all programmers.

We describe an extension-oriented compiler for C called xoc. An extension-oriented compiler, unlike a conventional extensible compiler, implements new features via many small extensions that are loaded together as needed. Xoc gives extension writers full control over program syntax and semantics while hiding many compiler internals. Xoc programmers concisely define powerful compiler extensions that, by construction, can be combined; even some parts of the base compiler, such as GNU C compatibility, are structured as extensions.

Xoc is based on two key interfaces. Syntax patterns allow extension writers to manipulate language fragments using concrete syntax. Lazy computation of attributes allows extension writers to use the results of analyses by other extensions or the core without needing to worry about pass scheduling.

Extensions built using xoc include xsparse, a 345-line extension that mimics Sparse, Linux's C front end, and xlambda, a 170-line extension that adds function expressions to C. An evaluation of xoc using these and 13 other extensions shows that xoc extensions are typically more concise than equivalent extensions written for conventional extensible compilers and that it is possible to compose extensions.
Understanding the propagation of hard errors to software and implications for resilient system design
Authors: Li Man-Lap , Ramachandran Pradeep , Sahoo Swarup Kumar , Adve Sarita V. , Adve Vikram S. , Zhou Yuanyuan
Published: April 2008

With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-the-field faults. To be broadly deployable, the hardware reliability solution must incur low overheads, precluding use of expensive redundancy. We explore a cooperative hardware-software solution that watches for anomalous software behavior to indicate the presence of hardware faults. Fundamental to such a solution is a characterization of how hardware faults indifferent microarchitectural structures of a modern processor propagate through the application and OS.

This paper aims to provide such a characterization, resulting in identifying low-cost detection methods and providing guidelines for implementation of the recovery and diagnosis components of such a reliability solution. We focus on hard faults because they are increasingly important and have different system implications than the much studied transients. We achieve our goals through fault injection experiments with a microarchitecture-level full system timing simulator. Our main results are: (1) we are able to detect 95% of the unmasked faults in 7 out of 8 studied microarchitectural structures with simple detectors that incur zero to little hardware overhead; (2) over 86% of these detections are within latencies that existing hardware checkpointing schemes can handle, while others require software checkpointing; and (3) a surprisingly large fraction of the detected faults corrupt OS state, but almost all of these are detected with latencies short enough to use hardware checkpointing, thereby enabling OS recovery in virtually all such cases.
Overshadow
Authors: Chen Xiaoxin , Garfinkel Tal , Lewis E. Christopher , Subrahmanyam Pratap , Waldspurger Carl A. , Boneh Dan , Dwoskin Jeffrey , Ports Dan R.K.
Published: April 2008

Commodity operating systems entrusted with securing sensitive data are remarkably large and complex, and consequently, frequently prone to compromise. To address this limitation, we introduce a virtual-machine-based system called Overshadow that protects the privacy and integrity of application data, even in the event of a total OScompromise. Overshadow presents an application with a normal view of its resources, but the OS with an encrypted view. This allows the operating system to carry out the complex task of managing an application's resources, without allowing it to read or modify them. Thus, Overshadow offers a last line of defense for application data.

Overshadow builds on multi-shadowing, a novel mechanism that presents different views of "physical" memory, depending on the context performing the access. This primitive offers an additional dimension of protection beyond the hierarchical protection domains implemented by traditional operating systems and processor architectures.

We present the design and implementation of Overshadow and show how its new protection semantics can be integrated with existing systems. Our design has been fully implemented and used to protect a wide range of unmodified legacy applications running on an unmodified Linux operating system. We evaluate the performance of our implementation, demonstrating that this approach is practical.
Accelerating two-dimensional page walks for virtualized systems
Authors: Bhargava Ravi , Serebrin Benjamin , Spadini Francesco , Manne Srilatha
Published: April 2008

Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. However, the extra dimension also increases the maximum number of architecturally-required page table references.

This paper presents an in-depth examination of the 2D page table walk overhead and options for decreasing it. These options include using the AMD Opteron processor's page walk cache to exploit the strong reuse of page entry references. For a mix of server and SPEC benchmarks, the presented results show a 15%-38% improvement in guest performance by extending the existing page walk cache to also store the nested dimension of the 2D page walk. Caching nested page table translations and skipping multiple page entry references produce an additional 3%-7% improvement.

Much of the remaining 2D page walk overhead is due to low-locality nested page entry references, which result in additional memory hierarchy misses. By using large pages, the hypervisor can eliminate many of these long-latency accesses and further improve the guest performance by 3%-22%.
Efficiency trends and limits from comprehensive microarchitectural adaptivity
Authors: Lee Benjamin C. , Brooks David
Published: April 2008

Increasing demand for power-efficient, high-performance computing requires tuning applications and/or the underlying hardware to improve the mapping between workload heterogeneity and computational resources. To assess the potential benefits of hardware tuning, we propose a framework that leverages synergistic interactions between recent advances in (a) sampling, (b) predictive modeling, and (c) optimization heuristics. This framework enables qualitatively new capabilities in analyzing the performance and power characteristics of adaptive microarchitectures. For the first time, we are able to simultaneously consider high temporal and comprehensive spatial adaptivity. In particular, we optimize efficiency for many, short adaptive intervals and identify the best configuration of 15 parameters, which define a space of 240B point.

With frequent sub-application reconfiguration and a fully reconfigurable hardware substrate, adaptive microarchitectures achieve

bips
3
/w

efficiency gains of up to 5.3x (median 2.4x) relative to their static counterparts already optimized for a given application. This 5.3x efficiency gain is derived from a 1.6x performance gain and 0.8x power reduction. Although several applications achieve a significant fraction of their potential efficiency with as few as three adaptive parameters, the three most significant parameters differ across applications. These differences motivate a hardware substrate capable of comprehensive adaptivity to meet these diverse application requirements.
No "power" struggles
Authors: Raghavendra Ramya , Ranganathan Parthasarathy , Talwar Vanish , Wang Zhikui , Zhu Xiaoyun
Published: April 2008

Power delivery, electricity consumption, and heat management are becoming key challenges in data center environments. Several past solutions have individually evaluated different techniques to address separate aspects of this problem, in hardware and software, and at local and global levels. Unfortunately, there has been no corresponding work on coordinating all these solutions. In the absence of such coordination, these solutions are likely to interfere with one another, in unpredictable (and potentially dangerous) ways. This paper seeks to address this problem. We make two key contributions. First, we propose and validate a power management solution that coordinates different individual approaches. Using simulations based on 180 server traces from nine different real-world enterprises, we demonstrate the correctness, stability, and efficiency advantages of our solution. Second, using our unified architecture as the base, we perform a detailed quantitative sensitivity analysis and draw conclusions about the impact of different architectures, implementations, workloads, and system design choices.
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Authors: Ballapuram Chinnakrishnan S. , Sharif Ahmad , Lee Hsien-Hsin S.
Published: April 2008

Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as the baseline to analyze problems in various domains. One of the main design issues facing CMP systems is the growing number of snoops required to maintain cache coherency and to support self/cross-modifying code that leads to power and performance limitations. In this paper, we analyze the internal and external snoop behavior in a CMP system and relax the snoopy cache coherence protocol based on the program semantics and properties of the shared variables for saving power. Based on the observations and analyses, we propose two novel techniques: Selective Snoop Probe (SSP) and Essential Snoop Probe (ESP) to reduce power without compromising performance. Our simulation results show that using the SSPtechnique, 5% to 65% data cache energy savings per core for different processor configurations can be achieved with 1% to 2% performance improvement. We also show that 5% to 82% of data cache energy per core is spent on the non-essential snoop probes that can be saved using the ESP technique.
Archipelago
Authors: Lvin Vitaliy B. , Novark Gene , Berger Emery D. , Zorn Benjamin G.
Published: April 2008

Memory errors are a notorious source of security vulnerabilities that can lead to service interruptions, information leakage and unauthorized access. Because such errors are also difficult to debug, the absence of timely patches can leave users vulnerable to attack for long periods of time. A variety of approaches have been introduced to combat these errors, but these often incur large runtime overheads and generally abort on errors, threatening availability.

This paper presents Archipelago, a runtime system that takes advantage of available address space to substantially reduce the likelihood that a memory error will affect program execution. Archipelago randomly allocates heap objects far apart in virtual address space, effectively isolating each object from buffer overflows. Archipelago also protects against dangling pointer errors by preserving the contents of freed objects after they are freed. Archipelago thus trades virtual address space---a plentiful resource on 64-bit systems---for significantly improved program reliability and security, while limiting physical memory consumption by tracking the working set of an application and compacting cold objects. We show that Archipelago allows applications to continue to run correctly in the face of thousands of memory errors. Across a suite of server applications, Archipelago's performance overhead is 6% on average (between -7% and 22%), making it especially suitable to protect servers that have known security vulnerabilities due to heap memory errors.
Accurate branch prediction for short threads
Authors: Choi Bumyong , Porter Leo , Tullsen Dean M.
Published: April 2008

Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to expose parallelism. Current branch predictors seek to incorporate large amounts of control flow history to maximize accuracy. However, when that history is absent the predictor fails to work as intended. Thus, modern predictors are almost useless for threads below a certain length.

Using a Speculative Multithreaded (SpMT) architecture as an example of a system which generates shorter threads, this work examines techniques to improve branch prediction accuracy when a new thread begins to execute on a different core. This paper proposes a minor change to the branch predictor that gives virtually the same performance on short threads as an idealized predictor that incorporates unknowable pre-history of a spawned speculative thread. At the same time, strong performance on long threads is preserved. The proposed technique sets the global history register of the spawned thread to the initial value of the program counter. This novel and simple design reduces branch mispredicts by 29% and provides as much as a 13% IPC improvement on selected SPEC2000 benchmarks.