bluuebunny/crossref_metadata_2025 huggingface dataset:
Social Impact Assessment in Europe: A Study of Social Impacts in Three Danish Cases
Authors: Larsen Sanne Vammen , Hansen Anne Merrild , Lyhne Ivar , Aaen Sara Bjørn , Ritter Eva , Nielsen Helle
Published: January 2016

Social impact assessment (SIA) is applied worldwide to assess social impacts of plans and projects. In Europe, directives on environmental assessment (EA) require attention to social impacts, however, there is a need to investigate the implementation in practise. To this end, we study three Danish cases, which are characterised by debates and conflicts on social issues. Analysis of the EA statements shows inclusion of a broad range of social impacts. However, the EAs do not fully match the concerns of the public, and social impacts are not always analysed in depth, mitigation measures are not suggested or are postponed and the geographical distribution of impacts assessed is biased towards including negative local impacts. We discuss the scope and handling of social impacts, and possible implications. Based on this, we conclude with the view that EA might do the job of handling social impacts in Europe, if practise is improved.
The characteristics of open fractures in carbonate reservoirs and their impact on fluid flow: a discussion
Authors: Wennberg Ole Petter , Casini Giulio , Jonoud Sima , Peacock David C.P.
Published: January 2016

Permeability in fractured carbonate reservoirs is very heterogeneous due to fracturing at different scales superimposed on inherent textures from deposition and diagenesis. Observations of fractures in core and outcrop indicate that flow in open fractures in carbonate rock tends to be channelled rather than through fissures. Most of the flow takes place along a few dominating channels in the fracture plane, whereas most of the fracture plane is not effective for fluid flow. The formation of flow channels is caused by a combination of mechanical and, in particular, diagenetic processes. Single extension fractures occur as partly open or vuggy fractures, and their hydraulic properties are controlled by dissolution and cementation. Single shear fractures are typically open at local steps in the fault plane controlled by shearing along irregular fracture surfaces. Fault damage zones tend to be concentrated at fault tips, intersections, pull-aparts and overlap zones that represent areas of dilation. These damage zones represent elongated features in three dimensions with a high fracture density that will result in channelled flow at reservoir scales. The effect of channelled flow should be taken into account during evaluation of fractured carbonate reservoirs and when building dynamic flow models.
Semantic locality and context-based prefetching using reinforcement learning
Authors: Peled Leeor , Mannor Shie , Weiser Uri , Etsion Yoav
Published: January 2016

Most modern memory prefetchers rely on spatio-temporal locality to predict the memory addresses likely to be accessed by a program in the near future. Emerging workloads, however, make increasing use of irregular data structures, and thus exhibit a lower degree of spatial locality. This makes them less amenable to spatio-temporal prefetchers.

In this paper, we introduce the concept of Semantic Locality, which uses inherent program semantics to characterize access relations. We show how, in principle, semantic locality can capture the relationship between data elements in a manner agnostic to the actual data layout, and we argue that semantic locality transcends spatio-temporal concerns.

We further introduce the context-based memory prefetcher, which approximates semantic locality using reinforcement learning. The prefetcher identifies access patterns by applying reinforcement learning methods over machine and code attributes, that provide hints on memory access semantics.

We test our prefetcher on a variety of benchmarks that employ both regular and irregular patterns. For the SPEC 2006 suite, it delivers speedups as high as 2.8X (20% on average) over a baseline with no prefetching, and outperforms leading spatio-temporal prefetchers. Finally, we show that the context-based prefetcher makes it possible for naive, pointer-based implementations of irregular algorithms to achieve performance comparable to that of spatially optimized code.
Heracles
Authors: Lo David , Cheng Liqun , Govindaraju Rama , Ranganathan Parthasarathy , Kozyrakis Christos
Published: January 2016

User-facing, latency-sensitive services, such as websearch, underutilize their computing resources during daily periods of low traffic. Reusing those resources for other tasks is rarely done in production services since the contention for shared resources can cause latency spikes that violate the service-level objectives of latency-sensitive tasks. The resulting under-utilization hurts both the affordability and energy-efficiency of large-scale datacenters. With technology scaling slowing down, it becomes important to address this opportunity.

We present Heracles, a feedback-based controller that enables the safe colocation of best-effort tasks alongside a latency-critical service. Heracles dynamically manages multiple hardware and software isolation mechanisms, such as CPU, memory, and network isolation, to ensure that the latency-sensitive job meets latency targets while maximizing the resources given to best-effort tasks. We evaluate Heracles using production latency-critical and batch workloads from Google and demonstrate average server utilizations of 90% without latency violations across all the load and colocation scenarios that we evaluated.
Rumba
Authors: Khudia Daya S. , Zamirai Babak , Samadi Mehrzad , Mahlke Scott
Published: January 2016

Approximate computing can be employed for an emerging class of applications from various domains such as multimedia, machine learning and computer vision. The approximated output of such applications, even though not 100% numerically correct, is often either useful or the difference is unnoticeable to the end user. This opens up a new design dimension to trade off application performance and energy consumption with output correctness. However, a largely unaddressed challenge is quality control: how to ensure the user experience meets a prescribed level of quality. Current approaches either do not monitor output quality or use sampling approaches to check a small subset of the output assuming that it is representative. While these approaches have been shown to produce average errors that are acceptable, they often miss large errors without any means to take corrective actions. To overcome this challenge, we propose
Rumba
for online detection and correction of large approximation errors in an approximate accelerator-based computing environment. Rumba employs continuous lightweight checks in the accelerator to detect large approximation errors and then fixes these errors by exact re-computation on the host processor. Rumba employs computationally inexpensive output error prediction models for efficient detection. Computing patterns amenable for approximation (e.g., map and stencil) are usually data parallel in nature and Rumba exploits this property for selective correction. Overall, Rumba is able to achieve 2.1x reduction in output error for an unchecked approximation accelerator while maintaining the accelerator performance gains at the cost of reducing the energy savings from 3.2x to 2.2x for a set of applications from different approximate computing domains.
MBus
Authors: Pannuto Pat , Lee Yoonmyung , Kuo Ye-Sheng , Foo ZhiYoong , Kempke Benjamin , Kim Gyouho , Dreslinski Ronald G. , Blaauw David , Dutta Prabal
Published: January 2016

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized---yet reusable---components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.

We present
MBus
, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts.

To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2mm
3
MBus system draws 8nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.
ArMOR
Authors: Lustig Daniel , Trippel Caroline , Pellauer Michael , Martonosi Margaret
Published: January 2016

Architectural heterogeneity is increasing: numerous products and studies have proven the benefits of combining cores and accelerators with varying ISAs into a single system. However, an underappreciated barrier to unlocking the full potential of heterogeneity is the need to specify and to reconcile differences in memory consistency models across layers of the hardware-software stack and among on-chip components.

This paper presents ArMOR, a framework for specifying, comparing, and translating between memory consistency models. ArMOR defines MOSTs, an architecture-independent and precise format for specifying the semantics of memory ordering requirements such as preserved program order or explicit fences. MOSTs allow any two consistency models to be directly and algorithmically compared, and they help avoid many of the pitfalls of traditional consistency model analysis. As a case study, we use ArMOR to automatically generate translation modules called shims that dynamically translate code compiled for one memory model to execute on hardware implementing a different model.
Exploring the potential of heterogeneous von neumann/dataflow execution models
Authors: Nowatzki Tony , Gangadhar Vinay , Sankaralingam Karthikeyan
Published: January 2016

General purpose processors (GPPs), from small inorder designs to many-issue out-of-order, incur large power overheads which must be addressed for future technology generations. Major sources of overhead include structures which dynamically extract the data-dependence graph or maintain precise state. Considering irregular workloads, current specialization approaches either heavily curtail performance, or provide simply too little benefit. Interestingly, well known
explicit-dataflow
architectures eliminate these overheads by directly executing the data-dependence graph and eschewing instruction-precise recoverability. However, even after decades of research, dataflow architectures have yet to come into prominence as a solution. We attribute this to a lack of effective control speculation and the latency overhead of explicit communication, which is crippling for certain codes.

This paper makes the observation that if both out-of-order and explicit-dataflow were available in one processor, many types of GPP cores can benefit from dynamically switching during certain phases of an application's lifetime. Analysis reveals that an ideal
explicit-dataflow
engine could be profitable for more than half of instructions, providing significant performance and energy improvements. The challenge is to achieve these benefits without introducing excess hardware complexity. To this end, we propose the Specialization Engine for Explicit-Dataflow (SEED). Integrated with an inorder core, we see 1.67× performance and 1.65× energy benefits, with an Out-Of-Order (OOO) dual-issue core we see 1.33× and 1.70×, and with a quad-issue OOO, 1.14× and 1.54×.
PIM-enabled instructions
Authors: Ahn Junwhan , Yoo Sungjoo , Mutlu Onur , Choi Kiyoung
Published: January 2016

Processing-in-memory (PIM) is rapidly rising as a viable solution for the memory wall crisis, rebounding from its unsuccessful attempts in 1990s due to practicality concerns, which are alleviated with recent advances in 3D stacking technologies. However, it is still challenging to integrate the PIM architectures with existing systems in a seamless manner due to two common characteristics: unconventional programming models for in-memory computation units and lack of ability to utilize large on-chip caches.

In this paper, we propose a new PIM architecture that (1) does not change the existing sequential programming models and (2) automatically decides whether to execute PIM operations in memory or processors depending on the locality of data. The key idea is to implement simple in-memory computation using compute-capable memory commands and use specialized instructions, which we call PIM-enabled instructions, to invoke in-memory computation. This allows PIM operations to be interoperable with existing programming models, cache coherence protocols, and virtual memory mechanisms with no modification. In addition, we introduce a simple hardware structure that monitors the locality of data accessed by a PIM-enabled instruction at runtime to adaptively execute the instruction at the host processor (instead of in memory) when the instruction can benefit from large on-chip caches. Consequently, our architecture provides the illusion that PIM operations are executed as if they were host processor instructions.

We provide a case study of how ten emerging data-intensive workloads can benefit from our new PIM abstraction and its hardware implementation. Evaluations show that our architecture significantly improves system performance and, more importantly, combines the best parts of conventional and PIM architectures by adapting to data locality of applications.
A scalable processing-in-memory accelerator for parallel graph processing
Authors: Ahn Junwhan , Hong Sungpack , Yoo Sungjoo , Mutlu Onur , Choi Kiyoung
Published: January 2016

The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations.

In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.
BEAR
Authors: Chou Chiachen , Jaleel Aamer , Qureshi Moinuddin K.
Published: January 2016

Die stacking memory technology can enable gigascale DRAM caches that can operate at 4x-8x higher bandwidth than commodity DRAM. Such caches can improve system performance by servicing data at a faster rate when the requested data is found in the cache, potentially increasing the memory bandwidth of the system by 4x-8x. Unfortunately, a DRAM cache uses the available memory bandwidth not only for data transfer on cache hits, but also for other secondary operations such as cache miss detection, fill on cache miss, and writeback lookup and content update on dirty evictions from the last-level on-chip cache. Ideally, we want the bandwidth consumed for such secondary operations to be negligible, and have almost all the bandwidth be available for transfer of useful data from the DRAM cache to the processor.

We evaluate a 1GB DRAM cache, architected as Alloy Cache, and show that even the most bandwidth-efficient proposal for DRAM cache consumes 3.8x bandwidth compared to an idealized DRAM cache that does not consume any bandwidth for secondary operations. We also show that redesigning the DRAM cache to minimize the bandwidth consumed by secondary operations can potentially improve system performance by 22%. To that end, this paper proposes
Bandwidth Efficient ARchitecture (BEAR)
for DRAM caches. BEAR integrates three components, one each for reducing the bandwidth consumed by miss detection, miss fill, and writeback probes. BEAR reduces the bandwidth consumption of DRAM cache by 32%, which reduces cache hit latency by 24% and increases overall system performance by 10%. BEAR, with negligible overhead, outperforms an idealized SRAM Tag-Store design that incurs an unacceptable overhead of 64 megabytes, as well as Sector Cache designs that incur an SRAM storage overhead of 6 megabytes.
Efficient execution of memory access phases using dataflow specialization
Authors: Ho Chen-Han , Kim Sung Jin , Sankaralingam Karthikeyan
Published: January 2016

This paper identifies a new opportunity for improving the efficiency of a processor core:
memory access phases of programs
. These are dynamic regions of programs where most of the instructions are devoted to memory access or address computation. These occur naturally in programs because of workload properties, or when employing an in-core accelerator, we get induced phases where the code execution on the core is access code. We observe such code requires an OOO core's dataflow and dynamism to run fast and does not execute well on an in-order processor. However, an OOO core consumes much power, effectively increasing energy consumption and reducing the energy efficiency of in-core accelerators.

We develop an execution model called memory access dataflow (MAD) that encodes dataflow computation, event-condition-action rules, and explicit actions. Using it we build a specialized engine that provides an OOO core's performance but at a fraction of the power. Such an engine can serve as a general way for any accelerator to execute its respective induced phase, thus providing a common interface and implementation for current and future accelerators. We have designed and implemented MAD in RTL, and we demonstrate its generality and flexibility by integration with four diverse accelerators (SSE, DySER, NPU, and C-Cores). Our quantitative results show, relative to in-order, 2-wide OOO, and 4-wide OOO, MAD provides 2.4×, 1.4× and equivalent performance respectively. It provides 0.8×, 0.6× and 0.4× lower energy.
Dynamic thread block launch
Authors: Wang Jin , Rubin Norm , Sidelnik Albert , Yalamanchili Sudhakar
Published: January 2016

GPUs have been proven effective for structured applications that map well to the rigid 1D-3D grid of threads in modern bulk synchronous parallel (BSP) programming languages. However, less success has been encountered in mapping data intensive irregular applications such as graph analytics, relational databases, and machine learning. Recently introduced nested device-side kernel launching functionality in the GPU is a step in the right direction, but still falls short of being able to effectively harness the GPUs performance potential.

We propose a new mechanism called
Dynamic Thread Block Launch (DTBL)
to extend the current bulk synchronous parallel model underlying the current GPU execution model by supporting dynamic spawning of lightweight thread blocks. This mechanism supports the nested launching of thread blocks rather than kernels to execute dynamically occurring parallel work elements. This paper describes the execution model of DTBL, device-runtime support, and microarchitecture extensions to track and execute dynamically spawned thread blocks. Experiments with a set of irregular data intensive CUDA applications executing on a cycle-level simulator show that DTBL achieves average 1.21x speedup over the original flat implementation and average 1.40x over the implementation with device-side kernel launches using CUDA Dynamic Parallelism.
FASE
Authors: Callan Robert , Zajić Alenka , Prvulovic Milos
Published: January 2016

While all computation generates electromagnetic (EM) side-channel signals, some of the strongest and farthest-propagating signals are created when an existing strong periodic signal (e.g. a clock signal) becomes stronger or weaker (amplitude-modulated) depending on processor or memory activity. However, modern systems create emanations at thousands of different frequencies, so it is a difficult, error-prone, and time-consuming task to find those few emanations that are AM-modulated by processor/memory activity.

This paper presents a methodology for rapidly finding such activity-modulated signals. This method creates recognizable spectral patterns generated by specially designed microbenchmarks and then processes the recorded spectra to identify signals that exhibit amplitude-modulation behavior. We apply this method to several computer systems and find several such modulated signals. To illustrate how our methodology can benefit side-channel security research and practice, we also identify the physical mechanisms behind those signals, and find that the strongest signals are created by voltage regulators, memory refreshes, and DRAM clocks. Our results indicate that each signal may carry unique information about system activity, potentially enhancing an attacker's capability to extract sensitive information. We also confirm that our methodology correctly separates emanated signals that are affected by specific processor or memory activities from those that are not.
A case for core-assisted bottleneck acceleration in GPUs
Authors: Vijaykumar Nandita , Pekhimenko Gennady , Jog Adwait , Bhowmick Abhishek , Ausavarungnirun Rachata , Das Chita , Kandemir Mahmut , Mowry Todd C. , Mutlu Onur
Published: January 2016

Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent execution of thousands of threads. Unfortunately, different bottlenecks during execution and heterogeneous application requirements create imbalances in utilization of resources in the cores. For example, when a GPU is bottlenecked by the available off-chip memory bandwidth, its computational resources are often overwhelmingly idle, waiting for data from memory to arrive.

This paper introduces the Core-Assisted Bottleneck Acceleration (CABA) framework that employs idle on-chip resources to alleviate different bottlenecks in GPU execution. CABA provides flexible mechanisms to automatically generate "assist warps" that execute on GPU cores to perform specific tasks that can improve GPU performance and efficiency.

CABA enables the use of idle computational units and pipelines to alleviate the memory bandwidth bottleneck, e.g., by using assist warps to perform data compression to transfer less data from memory. Conversely, the same framework can be employed to handle cases where the GPU is bottlenecked by the available computational units, in which case the memory pipelines are idle and can be used by CABA to speed up computation, e.g., by performing memoization using assist warps.

We provide a comprehensive design and evaluation of CABA to perform effective and flexible data compression in the GPU memory hierarchy to alleviate the memory bandwidth bottleneck. Our extensive evaluations show that CABA, when used to implement data compression, provides an average performance improvement of 41.7% (as high as 2.6X) across a variety of memory-bandwidth-sensitive GPGPU applications.
Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8
Authors: Nakaike Takuya , Odaira Rei , Gaudet Matthew , Michael Maged M. , Tomari Hisanobu
Published: January 2016

Transactional Memory (TM) is a new programming paradigm for both simple concurrent programming and high concurrent performance. Hardware Transactional Memory (HTM) is hardware support for TM-based programming. It has lower overhead than software transactional memory (STM), which is a software-based implementation of TM. There are now four commercial systems, IBM Blue Gene/Q, IBM zEnterprise EC12, Intel Core, and IBM POWER8, offering HTM. Our work is the first to compare the performance of these four HTM systems. We measured the STAMP benchmarks, the most widely used TM benchmarks. We also evaluated the specific features of each HTM system. Our experimental results show that: (1) there is no single HTM system that is more scalable than the others in all of the benchmarks, (2) there are measurable performance differences among the HTM systems in some benchmarks, and (3) each HTM system has its own implementation characteristics that limit its scalability.
Reducing world switches in virtualized environment with flexible cross-world calls
Authors: Li Wenhao , Xia Yubin , Chen Haibo , Zang Binyu , Guan Haibing
Published: January 2016

Modern computers are built with increasingly complex software stack crossing multiple layers (i.e., worlds), where cross-world call has been a necessity for various important purposes like security, reliability, and reduced complexity. Unfortunately, there is currently limited cross-world call support (e.g., syscall, vmcall), and thus other calls need to be emulated by detouring multiple times to the privileged software layer (i.e., OS kernel and hypervisor). This causes not only significant performance degradation, but also unnecessary implementation complexity.

This paper argues that it is time to rethink the design of traditional cross-world call mechanisms by reviewing existing systems built upon hypervisors. Following the design philosophy of separating authentication from authorization, this paper advocates decoupling of the authorization on whether a world call is permitted (by software) from unforgeable identification of calling peers (by hardware). This results in a flexible cross-world call scheme (namely CrossOver) that allows secure, efficient and flexible cross-world calls across multiple layers not only within the same address space, but also across multiple address spaces. We demonstrate that CrossOver can be approximated by using existing hardware mechanism (namely VMFUNC) and a trivial modification of the VMFUNC mechanism can provide a full support of CrossOver. To show its usefulness, we have conducted case studies by using several recent systems such as Proxos, Hyper-Shell, Tahoma and ShadowContext. Performance measurements using full-system emulation and a real processor with VMFUNC shows that CrossOver significantly boosts the performance of the mentioned systems.
A variable warp size architecture
Authors: Rogers Timothy G. , Johnson Daniel R. , O'Connor Mike , Keckler Stephen W.
Published: January 2016

This paper studies the effect of warp sizing and scheduling on performance and efficiency in GPUs. We propose Variable Warp Sizing (VWS) which improves the performance of divergent applications by using a small base warp size in the presence of control flow and memory divergence. When appropriate, our proposed technique groups sets of these smaller warps together by ganging their execution in the warp scheduler, improving performance and energy efficiency for regular applications. Warp ganging is necessary to prevent performance degradation on regular workloads due to memory convergence slip, which results from the inability of smaller warps to exploit the same intra-warp memory locality as larger warps. This paper explores the effect of warp sizing on control flow divergence, memory divergence, and locality. For an estimated 5% area cost, our ganged scheduling microarchitecture results in a simulated 35% performance improvement on divergent workloads by allowing smaller groups of threads to proceed independently, and eliminates the performance degradation due to memory convergence slip that is observed when convergent applications are executed with smaller warp sizes.
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Authors: Alvarez Lluc , Vilanova Lluís , Moreto Miquel , Casas Marc , Gonzàlez Marc , Martorell Xavier , Navarro Nacho , Ayguadé Eduard , Valero Mateo
Published: January 2016

The increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a hybrid memory system. Scratchpad memories are more power-efficient than caches and they do not generate coherence traffic, but they suffer from poor programmability. A good way to hide the programmability difficulties to the programmer is to give the compiler the responsibility of generating code to manage the scratchpad memories. Unfortunately, compilers do not succeed in generating this code in the presence of random memory accesses with unknown aliasing hazards.

This paper proposes a coherence protocol for the hybrid memory system that allows the compiler to always generate code to manage the scratchpad memories. In coordination with the compiler, memory accesses that may access stale copies of data are identified and diverted to the valid copy of the data. The proposal allows the architecture to be exposed to the programmer as a shared memory manycore, maintaining the programming simplicity of shared memory models and preserving backwards compatibility. In a 64-core manycore, the coherence protocol adds overheads of 4% in performance, 8% in network traffic and 9% in energy consumption to enable the usage of the hybrid memory system that, compared to a cache-based system, achieves a speedup of 1.14x and reduces on-chip network traffic and energy consumption by 29% and 17%, respectively.
DynaSpAM
Authors: Liu Feng , Ahn Heejin , Beard Stephen R. , Oh Taewook , August David I.
Published: January 2016

Spatial architectures are more efficient than traditional Out-of-Order (OOO) processors for computationally intensive programs. However, spatial architectures require mapping a program, either statically or dynamically, onto the spatial fabric. Static methods can generate efficient mappings, but they cannot adapt to changing workloads and are not compatible across hardware generations. Current dynamic methods are adaptive and compatible, but do not optimize as well due to their limited use of speculation and small mapping scopes. To overcome the limitations of existing dynamic mapping methods for spatial architectures, while minimizing the inefficiencies inherent in OOO superscalar processors, this paper presents DynaSpAM (Dynamic Spatial Architecture Mapping), a framework that tightly couples a spatial fabric with an OOO pipeline. DynaSpAM coaxes the OOO processor into producing an optimized mapping with a simple modification to the processor's scheduler. The insight behind DynaSpAM is that today's powerful OOO processors do for themselves most of the work necessary to produce a highly optimized mapping for a spatial architecture, including aggressively speculating control and memory dependences, and scheduling instructions using a large window. Evaluation of DynaSpAM shows a geomean speedup of
1.42x
for 11 benchmarks from the Rodinia benchmark suite with a geomean 23.9% reduction in energy consumption compared to an 8-issue OOO pipeline.
Manycore network interfaces for in-memory rack-scale computing
Authors: Daglis Alexandros , Novaković Stanko , Bugnion Edouard , Falsafi Babak , Grot Boris
Published: January 2016

Datacenter operators rely on low-cost, high-density technologies to maximize throughput for data-intensive services with tight tail latencies. In-memory rack-scale computing is emerging as a promising paradigm in scale-out datacenters capitalizing on commodity SoCs, low-latency and high-bandwidth communication fabrics and a remote memory access model to enable aggregation of a rack's memory for critical data-intensive applications such as graph processing or key-value stores. Low latency and high bandwidth not only dictate eliminating communication bottlenecks in the software protocols and off-chip fabrics but also a careful on-chip integration of network interfaces. The latter is a key challenge especially in architectures with RDMA-inspired one-sided operations that aim to achieve low latency and high bandwidth through on-chip Network Interface (NI) support. This paper proposes and evaluates network interface architectures for tiled manycore SoCs for in-memory rack-scale computing. Our results indicate that a careful splitting of NI functionality per chip tile and at the chip's edge along a NOC dimension enables a rack-scale architecture to optimize for both latency and bandwidth. Our best manycore NI architecture achieves latencies within 3% of an idealized hardware NUMA and efficiently uses the full bisection bandwidth of the NOC, without changing the on-chip coherence protocol or the core's microarchitecture.
Fusion
Authors: Kumar Snehasish , Shriraman Arrvindh , Vedula Naveen
Published: January 2016

Chip designers have shown increasing interest in integrating specialized fixed-function coprocessors into multicore designs to improve energy efficiency. Recent work in academia [11, 37] and industry [16] has sought to enable more fine-grain offloading at the granularity of functions and loops. The sequential program now needs to migrate across the chip utilizing the appropriate accelerator for each program region. As the execution migrates, it has become increasingly challenging to retain the temporal and spatial locality of the original program as well as manage the data sharing.

We show that with the increasing energy cost of wires and caches relative to compute operations, it is imperative to optimize data movement to retain the energy benefits of accelerators. We develop FUSION, a lightweight coherent cache hierarchy for accelerators and study the tradeoffs compared to a scratchpad based architecture. We find that coherency, both between the accelerators and with the CPU, can help minimize data movement and save energy. FUSION leverages temporal coherence [32] to optimize data movement within the accelerator tile. The accelerator tile includes small per-accelerator L0 caches to minimize hit energy and a per-tile shared cache to improve localized-sharing between accelerators and minimize data exchanges with the host LLC. We find that overall FUSION improves performance by 4.3× compared to an oracle DMA that pushes data into the scratchpad. In workloads with inter-accelerator sharing we save up to 10x the dynamic energy of the cache hierarchy by minimizing the host-accelerator data ping-ponging.
Enantioseparation of Citalopram by RP-HPLC, Using Sulfobutyl Ether-β-Cyclodextrin as a Chiral Mobile Phase Additive
Authors: Peng Yangfeng , He Quan Sophia , Cai Jiang
Published: January 2016

Enantiomeric separation of citalopram (CIT) was developed using a reversed phase HPLC (RP-HPLC) with sulfobutylether-β-cyclodextrin (SBE-β-CD) as a chiral mobile phase additive. The effects of the pH value of aqueous buffer, concentration of chiral additive, composition of mobile phase, and column temperature on the enantioseparation of CIT were investigated on the Hedera ODS-2 C18column (250 mm × 4.6 mm × 5.0 um). A satisfactory resolution was achieved at 25°C using a mobile phase consisting of a mixture of aqueous buffer (pH of 2.5, 5 mM sodium dihydrogen phosphate, and 12 mM SBE-β-CD), methanol, and acetonitrile with a volumetric ratio of 21 : 3 : 1 and flow rate of 1.0 mL/min. This analytical method was evaluated by examining the precision (lower than 3.0%), linearity (regression coefficients close to 1), limit of detection (0.070 µg/mL for (R)-CIT and 0.076 µg/mL for (S)-CIT), and limit of quantitation (0.235 µg/mL for (R)-CIT and 0.254 µg/mL for (S)-CIT).
Fuzzy Robust Design of Dynamic Vibration Absorbers
Authors: Silva A. D. G. , Cavalini Jr A. A. , Steffen Jr V.
Published: January 2016

This paper is dedicated to the development of robust optimization and decision making techniques taking into account the uncertain parameters of linear and nonlinear dynamic vibration absorbers. In this case, novel approaches are proposed regarding different fuzzy logic optimization strategies. The uncertain parameters of the considered mechanical systems are treated as fuzzy variables. Consequently, the associated optimization problem is described as a fuzzy function that maps the fuzzy inputs. The proposed techniques are applied to the design of dynamic vibration absorbers. This numerical study illustrates the versatility and convenience of the proposed fuzzy logic optimization strategies.
High Content Analysis of Human Pluripotent Stem Cell Derived Hepatocytes Reveals Drug Induced Steatosis and Phospholipidosis
Authors: Pradip Arvind , Steel Daniella , Jacobsson Susanna , Holmgren Gustav , Ingelman-Sundberg Magnus , Sartipy Peter , Björquist Petter , Johansson Inger , Edsbagge Josefina
Published: January 2016

Hepatotoxicity is one of the most cited reasons for withdrawal of approved drugs from the market. The use of nonclinically relevant in vitro and in vivo testing systems contributes to the high attrition rates. Recent advances in differentiating human induced pluripotent stem cells (hiPSCs) into pure cultures of hepatocyte‐like cells expressing functional drug metabolizing enzymes open up possibilities for novel, more relevant human cell based toxicity models. The present study aimed to investigate the use of hiPSC derived hepatocytes for conducting mechanistic toxicity testing by image based high content analysis (HCA). The hiPSC derived hepatocytes were exposed to drugs known to cause hepatotoxicity through steatosis and phospholipidosis, measuring several endpoints representing different mechanisms involved in drug induced hepatotoxicity. The hiPSC derived hepatocytes were benchmarked to the HepG2 cell line and generated robust HCA data with low imprecision between plates and batches. The different parameters measured were detected at subcytotoxic concentrations and the order of which the compounds were categorized (as severe, moderate, mild, or nontoxic) based on the degree of injury at isomolar concentration corresponded to previously published data. Taken together, the present study shows how hiPSC derived hepatocytes can be used as a platform for screening drug induced hepatotoxicity by HCA.
Software Reliability Growth Model with Partial Differential Equation for Various Debugging Processes
Authors: Xu Jiajun , Yao Shuzhen
Published: January 2016

Most Software Reliability Growth Models (SRGMs) based on the Nonhomogeneous Poisson Process (NHPP) generally assume perfect or imperfect debugging. However, environmental factors introduce great uncertainty for SRGMs in the development and testing phase. We propose a novel NHPP model based on partial differential equation (PDE), to quantify the uncertainties associated with perfect or imperfect debugging process. We represent the environmental uncertainties collectively as a noise of arbitrary correlation. Under the new stochastic framework, one could compute the full statistical information of the debugging process, for example, its probabilistic density function (PDF). Through a number of comparisons with historical data and existing methods, such as the classic NHPP model, the proposed model exhibits a closer fitting to observation. In addition to conventional focus on the mean value of fault detection, the newly derived full statistical information could further help software developers make decisions on system maintenance and risk assessment.
Induced Pluripotent Stem Cells and Outer Retinal Disease
Authors: Yang Jin , Cai Bingcui , Glencer Patrick , Li Zhiqing , Zhang Xiaomin , Li Xiaorong
Published: January 2016

The retina, which is composed of multiple layers of differing cell types, has been considered the first choice for gene therapy, disease modeling, and stem cell‐derived retinal cell transplant therapy. Because of its special characteristics, the retina, located in the posterior part of the eye, can be well observed directly after gene therapy or transplantation. The blood‐retinal barrier is part of a specialized ocular microenvironment that is immune privileged. This protects transplanted cells and tissue. Having two eyes makes perfect natural control possible after a single eye receives gene or stem cell therapy. For this reason, research about exploring retinal diseases’ underlying molecular mechanisms and potential therapeutic approach using stem cell technique has been developing rapidly. This review is to present an up‐to‐date summary of the iPSC’s sources, variations, differentiation methods, and the wide‐ranging application of iPSCs‐RPCS or iPSCs‐RPE on retinal disease modeling, diagnostics, and therapeutics.
The Motivating Function of Healthcare Professional in eHealth and mHealth Interventions for Type 2 Diabetes Patients and the Mediating Role of Patient Engagement
Authors: Graffigna Guendalina , Barello Serena , Bonanomi Andrea , Menichetti Julia
Published: January 2016

eHealth and mHealth interventions for type 2 diabetes are emerging as useful strategies to accomplish the goal of a high functioning integrated care system. However, mHealth and eHealth interventions in order to be successful need the clear endorsement from the healthcare professionals. This cross-sectional study included a sample of 93 Italian-speaking type 2 diabetes patients and demonstrated the role of the perceived ability of healthcare professionals to motivate patients’ initiative in improving the level of their engagement and activation in type 2 diabetes self-management. The level of type 2 diabetes patients’ activation resulted also in being a direct precursor of their attitude to the use of mHealth and eHealth. Furthermore, patient engagement has been demonstrated to be a mediator of the relationship between the perceived ability of healthcare professionals in motivating type 2 diabetes patients and patients’ activation. Finally, type 2 diabetes patients adherence did not result in being a direct consequence of the frequency of mHealth and eHealth use. Patient adherence appeared to be directly influenced by the level of perceived healthcare professionals ability of motivating patients’ autonomy. These results offer important insights into the psychosocial and organizational elements that impact on type 2 diabetes patients’ activation in self-management and on their willingness to use mHealth and eHealth devices.
Spectrum and theIn VitroAntifungal Susceptibility Pattern of Yeast Isolates in Ethiopian HIV Patients with Oropharyngeal Candidiasis
Authors: Moges Birhan , Bitew Adane , Shewaamare Aster
Published: January 2016

Background.In Ethiopia, little is known regarding the distribution and thein vitroantifungal susceptibility profile of yeasts.Objective.This study was undertaken to determine the spectrum and thein vitroantifungal susceptibility pattern of yeasts isolated from HIV infected patients with OPC.Method.Oral pharyngeal swabs taken from oral lesions of study subjects were inoculated onto Sabouraud Dextrose Agar. Yeasts were identified by employing conventional test procedures and the susceptibility of yeasts to antifungal agents was evaluated by disk diffusion assay method.Result.One hundred and fifty-five yeast isolates were recovered of which 91 isolates were from patients that were not under HAART and 64 were from patients that were under HAART.C. albicanswas the most frequently isolated species followed byC. glabrata, C. tropicalis, C. krusei, C. kefyr, Cryptococcus laurentii, and Rhodotorulaspecies. Irrespective of yeasts isolated and identified, 5.8%, 5.8%, 12.3%, 8.4%, 0.6%, and 1.3% of the isolates were resistant to amphotericin B, clotrimazole, fluconazole, ketoconazole, miconazole, and nystatin, respectively.Conclusion.Yeast colonization rate of 69.2% and 31% resistance to six antifungal agents was documented. These highlight the need for nationwide study on the epidemiology of OPC and resistance to antifungal drugs.
Improved Protective Effect of Umbilical Cord Stem Cell Transplantation on Cisplatin‐Induced Kidney Injury in Mice Pretreated with Antithymocyte Globulin
Authors: Večerić-Haler Željka , Erman Andreja , Cerar Anton , Motaln Helena , Kološa Katja , Lah Turnšek Tamara , Sodin Šemrl Snežna , Lakota Katja , Mrak-Poljšak Katjuša , Škrajnar Špela , Kranjc Simona , Arnol Miha , Perše Martina
Published: January 2016

Mesenchymal stem cells (MSCs) are recognised as a promising tool to improve renal recovery in experimental models of cisplatin‐induced acute kidney injury. However, these preclinical studies were performed on severely immunodeficient animals. Here, we investigated whether human umbilical cord derived MSC treatment could equally ameliorate acute kidney injury induced by cisplatin and prolong survival in mice with a normal immune system and those with a suppressed immune system by polyclonal antithymocyte globulin (ATG). We demonstrated that ATG pretreatment, when followed by MSC transplantation, significantly improved injured renal function parameters, as evidenced by decreased blood urea nitrogen and serum creatinine concentration, as well as improved renal morphology. This tissue restoration was also supported by increased survival of mice. The beneficial effects of ATG were associated with reduced level of inflammatory protein serum amyloid A3 and induced antioxidative expression of superoxide dismutase‐1 (SOD‐1), glutathione peroxidase (GPx), and hem oxygenase‐1 (HO‐1). Infused MSCs became localised predominantly in peritubular areas and acted to reduce renal cell death. In conclusion, these results show that ATG diminished in situ inflammation and oxidative stress associated with cisplatin‐induced acute kidney injury, the effects that may provide more favourable microenvironment for MSC action, with consequential synergistic improvements in renal injury and animal survival as compared to MSC treatment alone.