Via Bottom Profile Optimization in All-in-One Etch with Double Patterning Scheme
Authors: Yuan Ke-Fang , Zhou Jun-Qing , Hu Min-Da , He Qi-Yang , Zhang Hai-Yang 
Published: February 2020

Abstract—In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity and RC delay. Tapered via bottom profile means smaller contact area with lower metal which means larger via contact resistance and degradation of chip interconnect performance. The bottom profile of via may probably become tapered when it enters Etch Stop Layer (ESL) or when the plasma touches lower Cu layer. In this paper, we will explain the reason of tapered via bottom profile and several ways to solve this problem.

Keywords—AIO etch; Via bottom taper profile; ESL; Cu exposure; Metal capping layer;

Introduction—In current LELE double patterning scheme, the partial via (PV) is firstly formed in 1st mask. Then the second PV is formed in 2nd mask, following by one in-situ ash which will remove PR tri-layer film. Then AIO etch will form via bottom and hard mask defined trench pattern at one etch process synchronously. MHM pattern is also defined by LELE double patterning before PV etch. The process sequence is briefly depicted in Fig.1. In our process, via is self-aligned by MHM for photo lithography reaches its limit on via. After photography critical dimension (CD) is quite large, via CD is shrunk during tri-layer etch process. After shrinking, Via CD is still larger than line CD. Therefore, we use self-aligned via (SAV) to confine via in MHM open area to ensure final VBD and TDDB performance acceptable. In this scheme, we should ensure MHM selectivity during whole etch process to let it not be etched through. Porous ultra-low-k (ULK) is introduced to reduce interconnect RC delay [1]. The etch stop layer (ESL) is introduced to balance different patterns’ loading after PV and trench etch. Then we used a LRM step to open ESL and touch lower Cu layer. However, we found the via bottom profile inside ESL is usually tapered. The tapered via profile into ESL could result in decreased contact area to lower metal Cu which is critical to final RC value.

The plasma etch rate in ESL is always relatively slow to make sure the former PV and trench etch step can stop on it. For the practical ULK and ESL film thickness in advanced technology node, the selectivity ULK to ESL should be at least 5 to ensure 80-90% percentage of trench depth is etched by trench etch step, and the following ESL opening step just remove the little trench depth remaining [2]. In final Liner Remove (LRM) step, the etch rate cannot be so fast, meanwhile the etch rate (ER) will be slower after Cu exposure. In fluorocarbon plasma with oxygen, oxygen captures carbon to form C-O bond and control the polymer generation. Such ER change is induced by the reduction of oxygen ion after Cu exposure which will affect the total etch performance to form tapered via bottom profile. In this paper, tradition way to change plasma condition, the change of ESL and the introduction of lower metal capping layer will be used to solve via bottom tapered issue.