bluuebunny/crossref_metadata_2025 huggingface dataset:
Dynamic fine-grain leakage reduction using leakage-biased bitlines
Authors: Heo Seongmoo , Barr Kenneth , Hampton Mark , Asanović Krste
Published: July 2004

Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic deactivation techniques that include the effects of deactivation energy and startup latencies, as well as long-term leakage current. We present a new circuit-level technique for leakage current reduction, leakage-biased bitlines, that has low deactivation energy and fast wakeup times. We show how this technique can be applied at a fine grain within an active microprocessor, and how microarchitectural scheduling policies can improve its performance. Using leakage-biased bitlines to deactivate SRAM read paths within I-cache memories saves over 24% of leakage energy and 22% of total I-cache energy when using a 70nm process. In the register file, fine-grained read port deactivation saves nearly 50% of leakage energy and 22% of total energy. Independently, turning off idle register file subbanks saves over 67% of leakage energy (57% total register file energy) with no loss in performance.
Drowsy caches
Authors: Flautner Krisztián , Kim Nam Sung , Martin Steve , Blaauw David , Mudge Trevor
Published: July 2004

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. According to our projections, in a 0.07um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.
Power and performance evaluation of globally asynchronous locally synchronous processors
Authors: Iyer Anoop , Marculescu Diana
Published: July 2004

Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor die. Asynchronous processor designs do not suffer from this problem since they do not have a global clock. However, a paradigm shift from synchronous to asynchronous is unlikely to happen in the processor industry in the near future. Hence the study of Globally Asynchronous Locally Synchronous (or GALS) systems is relevant. In this paper we use a cycle-accurate simulation environment to study the impact of asynchrony in a superscalar processor architecture. Our results show that as expected, going from a synchronous to a GALS design causes a drop in performance, but elimination of the global clock does not lead to drastic power reductions. From a power perspective, GALS designs are inherently less efficient when compared to synchronous architectures. However, the flexibility offered by the independently controllable local clocks enables the effective use of other energy conservation techniques like dynamic voltage scaling. Our results show that for a 5-clock domain GALS processor, the drop in performance ranges between 5-15%, while power consumption is reduced by 10% on the average. Fine-grained voltage scaling reduces the gap between fully synchronous and GALS implementations, allowing for better power efficiency.
Using a user-level memory thread for correlation prefetching
Authors: Solihin Yan , Lee Jaejin , Torrellas Josep
Published: July 2004

This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: the correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide usability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.
Timekeeping in the memory system
Authors: Hu Zhigang , Kaxiras Stefanos , Martonosi Margaret
Published: July 2004

Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance gap between processors and main memory. This paper offers a fresh perspective on the problem of predicting and optimizing memory behavior. Namely, we show quantitatively the extent to which detailed timing characteristics of past memory reference events are strongly predictive of future program reference behavior. We propose a family of
time-keeping techniques
that optimize behavior based on observations about particular cache time durations, such as the cache access interval or the cache dead time. Timekeeping techniques can be used to build small simple, and high-accuracy (often 90% or more) predictors for identifying conflict misses, for predicting dead blocks, and even for estimating the time at which the next reference to a cache frame will occur and the address that will be accessed. Based on these predictors, we demonstrate two new and complementary time-based hardware structures: (1) a time-based victim cache that improves performance by only storing conflict miss lines with likely reuse, and (2) a time-based prefetching technique that hones in on the right address to prefetch, and the right time to schedule the prefetch. Our victim cache technique improves performance over previous proposals by better selections of what to place in the victim cache. Our prefetching technique outperforms similar prior hardware prefetching proposals, despite being orders of magnitude smaller. Overall, these techniques improve performance by more than 11% across the SPEC2000 benchmark suite.
Implementing optimizations at decode time
Authors: Kim Ilhyun , Lipasti Mikko H.
Published: July 2004

The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations, forcing the scheduler to allocate functional units and other execution resources several cycles before they are actually used. Unfortunately, several proposed microarchitectural optimizations become less desirable or even impossible in such an environment, since they require instantaneous or near-instantaneous changes in execution behavior and resource usage in response to dynamic events that occur during instruction execution. Since they are detected several cycles after scheduling decisions have already been made, such dynamic responses are infeasible. To overcome this limitation, we propose to implement optimizations by performing what we call
speculative decode.
Speculative decode alters the mapping between user-visible instructions and the implemented core instructions based on observed runtime characteristics and generates speculative instruction sequences. In these sequences, optimizations are pre-scheduled in a manner compatible with realistic pipelines with multicycle scheduling latency. We present case studies on memory reference combining and silent store squashing, and demonstrate that speculative decode performs comparably or even better than impractical in-core implementations that require zero-cycle scheduling latency.
A scalable instruction queue design using dependence chains
Authors: Raasch Steven E. , Binkert Nathan L. , Reinhardt Steven K.
Published: July 2004

Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, increasing a conventional IQ's physical size leads to larger latencies and slower clock speeds. We introduce a new IQ design that divides a large queue into small segments, which can be clocked at high frequencies. We use dynamic dependence-based scheduling to promote instructions from segment to segment until they reach a small issue buffer. Our segmented IQ is designed specifically to accommodate variable-latency instructions such as loads. Despite its roughly similar circuit complexity; simulation results indicate that our segmented instruction queue with 512 entries and 128 chains improves performance by up to 69% over a 32-entry conventional instruction queue for SpecINT 2000 benchmarks, and up to 398% for SpecFP 2000 benchmarks. The segmented IQ achieves from 55% to 98% of the performance of a monolithic 512-entry queue while providing the potential for much higher clock speeds.
Cache performance for selected SPEC CPU2000 benchmarks
Authors: Cantin Jason F. , Hill Mark D.
Published: July 2004

The SPEC CPU2000 benchmark suite (http://www.spec.org/osg/cpu2000) is a collection of 26 compute-intensive, non-trivial programs used to evaluate the performance of a computer's CPU, memory system, and compilers. The benchmarks in this suite were chosen to represent real-world applications, and thus exhibit a wide range of runtime behaviors. On this webpage, we present functional cache miss ratios and related statistics for selected benchmarks in the SPEC CPU2000 suite. In particular, split L1 cache sizes ranging from 4KB to 1MB with 64B blocks and associativities of 1, 2, 4, 8 and full. Most of this data was collected at the University of Wisconsin-Madison with the aid of the Simplescalar toolset (http://www.simplescalar.org).
Propagating constants past software to hardware peripherals in fixed-application embedded systems
Authors: Vahid Frank , Patel Rilesh , Stitt Greg
Published: July 2004

Many embedded systems include a microprocessor that executes a single program for the lifetime of the system. These programs often contain constants used to initialize control registers in peripheral hardware components. Now that peripherals are often purchased in intellectual property (core) form and synthesized along with the microprocessor onto a single chip, new optimization opportunities exist. We introduce one such optimization, which involves propagating the initialization constants past the microprocessor to the peripheral, such that synthesis can further propagate the constants inside the peripheral core. While constant propagation in synthesis tools is commonly done, this work illustrates the benefits of recognizing initialization constants from the software as really being constants for hardware. We describe results that demonstrate 23 times reductions in peripheral size, and 10.30% savings in power, on several common peripheral examples.
Performance characteristics of the SPEC OMP2001 benchmarks
Authors: Aslot Vishal , Eigenmann Rudolf
Published: July 2004

Parallel computing is becoming mainstream with the advent of general purpose cost effective Shared-memory Multiprocessor (SMP) systems. At the same time, new developments in parallel programming environments allow more rapid and efficient programming of these systems. To this end, OpenMP has emerged as a flexible and fairly comprehensive set of compiler directives, library routines, and environment variables to facilitate parallel programming of SMP systems in Fortran and C/C++. The Standard Performance Evaluation Corporation (SPEC) has created a benchmark suite of eleven applications, named SPEC OMP2001, to be used for the performance evaluation and comparison of moderate size SMP systems. Each of the benchmarks in SPEC OMP2001 is either automatically or manually parallelized using OpenMP directives. In this paper, we present basic static and runtime characteristics of these benchmarks. We present data gathered using high resolution timers and the hardware counters available on our SMP system. We explain some of the benchmark performance characteristics with measured data and with a quantitative model.
Exploiting memory affinity in OpenMP through schedule reuse
Authors: Nikolopoulos D. S. , Artiaga E. , Ayguadé E. , Labarta J.
Published: July 2004

In this paper we explore the idea of reusing loop schedules to improve the scalability of numerical codes in shared-memory architectures with non-uniform memory access. The main objective is to implicitly construct affinity links between threads and data accesses and reuse them as much as possible along the execution of the program. These links are created through the definition and reuse of iteration schedules which are either defined statically by the user or created dynamically at run time. The paper does not include a formal proposal of OpenMP extensions but includes some experiments showing the usefulness of constructing affinity links in both regular and irregular codes.
MediaBreeze
Authors: Talla Deependra , John Lizy K.
Published: July 2004

Decoupled architectures are fine-grain processors that partition the memory access and execute functions in a computer program and exploit the parallelism between the two functions. Although some concepts from the traditional decoupled access execute paradigm made its way into commercial processors, they encountered resistance in general-purpose applications because these applications are not very structured and regular. However, multimedia applications have recently become dominant workload on desktops and workstations. Media applications are very structured and regular and lend themselves well to the decoupling concept. In this paper, we present an architecture that decouples the useful/true computations from the overhead/supporting instructions in media applications. The proposed scheme is incorporated into an out-of-order general-purpose processor enhanced with SIMD extensions. Explicit hardware support is provided to exploit instruction level parallelism in the overhead component. Performance evaluation shows that such hardware can significantly improve performance over conventional SIMD enhanced general-purpose processors. Results on nine multimedia benchmarks show that the proposed MediaBreeze architecture provides a 1.05x to 16.7x performance improvement over a 2-way out-of-order SIMD machine. On introducing slip-based data prefetching, a performance improvement up to 28x is observed.
S
IDE
surfer
Authors: Touzet David , Menaud Jean-Marc , Weis Frédéric , Couderc Paul , Banâtre Michel
Published: July 2004

Development of wireless communications enables the rise of networking applications in mobile personal systems. Thus, Web access from wireless PDAs is now available. More recently, emergence of proximity and wireless communication technologies has allowed to envision new kinds of applications taking part from their physical neighbourhood. In the field of personal applications, physical neighbourhood awareness can contribute to manage direct interactions between people during opportunistic encounters. Such encounters can be exploited to perform spontaneous and direct information exchanges. In this context, the SIDE Surfer system proposes to enrich casual meetings with
proximate
and
spontaneous
Web interactions.
Internet nuggets
Authors: Thorson Mark
Published: July 2004

This column consists of selected traffic from the
comp.arch
newsgroup, a forum for discussion of computer architecture on Internet --- an international computer network.
An improved index function for (D)FCM predictors
Authors: Burtscher Martin
Published: July 2004

The most promising value predictors to date are the finite context method predictor and a recent improvement thereof, the differential finite context method predictor. Both predictors comprise two levels and the index into the second level is a function of the content of the first level. This index function is crucial for good performance. However, our research shows that the currently used select-fold-shift-xor function performs poorly on range-limited sequences of values. For example, it does not predict the results of byte loads well. The problem with the current function is that it often cannot reach the predictor's entire second-level table. We propose an improved index function that does not suffer from this shortcoming. On the 15 SPECcpu2000 C programs, our new index function improves the average load-value predictability by about 1% to 5% without increase in predictor size. On byte loads, the improvement is over 6% for 4096-entry predictors.
Architecture of a hardware data interpreter
Authors: Chu Yaohan
Published: July 2004

DATA INTERPRETATION REFERS TO THE EXECUTION OF THE DATA DECLARATIONS OF A HIGH-LEVEL PROGRAMMING LANGUAGE PROGRAM, WHICH DECLARE THE DATA TYPES AND THE DATA STRUCTURES IN THE PROGRAM. THIS PAPER PRESENTS A DATA INTERPRETER WITH A HIGH-LEVEL MEMORY STRUCTURE WHERE THE DATA IS STORED IN A RANDOM-ACCESS MEMORY, WHILE THE TYPE, STRUCTURAL, AND REFERENCING INFORMATION ABOUT THE DATA IS STORED IN AN ASSOCIATIVE MEMORY, WHEN THE HARDWARE DATA INTERPRETER SCANS THE DATA DECLARATION, IT MAKES ENTRIES INTO THE ASSOCIATIVE MEMORY. IT THEN INTERPRETS THE DATA WHEN THE DATA NAME IS REFERENCED. THE STORAGE STRUCTURES, CONTROL STRUCTURES, PROCESSORS AND DATA OPERATIONS OF THE HARDWARE DATA INTERPRETER ARE DESCRIBED. AN EXAMPLE OF INTERPRETING A STRUCTURE DATA DECLARATION IS USED TO ILLUSTRATE THE DATA INTERPRETER.
The design of some language constructs for horizontal microprogramming
Authors: Dasgupta Subrata
Published: July 2004

This paper considers the problem of representing horizontal microprograms. Three forms of micro-parallelism are discussed: (a) Where micro-operations are concurrently executable within a single control memory clock cycle; (b) Where micro-operations are executable in a single clock cycle but are not concurrently executable, as in polyphase systems; and (c) Where there are concurrently executable micro-operations whose time of execution span several clock cycles. Language constructs for each of these forms are proposed, and their features discussed.
The Honeywell Modular Microprogram Machine
Authors: Jensen E. Douglas , Kain Richard Y.
Published: July 2004

M
3
is intended for research into unconventional special purpose stored program elements of computer systems (for example, a distributed computer Bus Interface Unit). The principal requirements for such a machine are flexibility and modularity. M
3
consists of an application independent Kernel Machine to which application-dependent Functional Modules are attached. The Kernel Machine is vertically microprogrammed; it includes highly capable microinstruction sequencing logic which facilitates structured microprogramming. The Functional Modules contain the operand registers and the operators (e.g., adders, shifters, etc.) needed by the specific application. The operators may be invoked not only by the Kernel Machine but also by one another; control may be passed among operators in a sequential or hierarchical fashion; operators may execute concurrently with each other and with the Kernel Machine; operators may be re-entrant or recursive; operators may activate themselves, or cause microcode interrupt routines to be executed in the Kernel Machine.
A multi-microprocessor implementation of a general purpose pipelined CPU
Authors: Ramseyer Richard R. , Dam Andries van
Published: July 2004

This paper discusses and shows by example the potential of a network of microprogrammable microprocessors as a cost-effective alternative to traditional hardwired medium- and large-scale mainframes. While biased towards vector processing, this system is not intended to compete with multi-million dollar supercomputers such as the 360/195, CDC STAR, Illiac IV, CRAY-1, TI ASC, etc., which use special algorithms and the fastest circuitry available.

The architecture incorporates pipelining, multiprocessing and distributed processing techniques with bipolar microprocessor technology. The result should be a machine which will equal or outperform most traditional third- and fourth-generation mainframes at a fraction of the CPU cost. This should be the case even for scalar, general purpose computation.
Hierarchical multiprocessor organizations
Authors: Harris J. Archer , Smith David R.
Published: July 2004

The development of LSI components has induced a substantial research effort into the possibility of applying conglomerations of small processors on some computational problems previously limited to large processors. The primary advantages of “multi-microprocessor architectures” are their potential for improvements in cost, reliability, and possibly speed over conventional large computers. However, the realization of these advantages requires improvements in the techniques necessary to translate problems into parallel algorithms for multi-microprocessors, and in the architectures of the multi-microprocessors themselves. This paper describes an architecture currently being investigated at SUNY - Stony Brook. The first section discusses various strategies of design. The second section describes the structure of the proposed system. Finally, the third section discusses some classes of problems for which the architecture is suited.
Poly-Processor System analysis and design
Authors: Hurakami K. , Nishikawa S. , Sato M.
Published: July 2004

This paper discusses the structure and efficiency of a computer complex constructed of many small, tightly coupled, functionally dedicated processors called a Poly-Processor System (PPS). The objective of the PPS is to realize a computer system which has easier expandability, higher reliability and better cost-to-performance ratio than existing systems.

Firstly, presented are rules to assign functions among processors, memories and interconnection modules. Secondly, dynamic behavior of the system, such as the frequency of interprocesser communication and instruction occurance, is analyzed by computer simulation. Lastly, a pilot model (PPS for Research: PPS-R), developed to confirm the feasibility of the system and to acquire experience in establishing the architecture of the system, is described.
The microprogramming of pipelined processors
Authors: Kogge Peter M.
Published: July 2004

A pipelined processor is one whose computational capabilities are divided into several sequential stages, each of which may be working with an independent set of data at the same instant of time. Such processors are capable of handling large streams of data at very high rates. As with conventional CPUs, the microprogrammed control of such processors offers advantages not possible with hardwired controls. This paper discusses some unique tradeoffs that may be made in the design of microprogrammed pipelines. A sample pipeline demonstrates the characteristics of two extremes of microprogrammed control—one where the microinstruction specifies all activity in the pipeline at one instant of time (time-stationary) and one where the microinstruction “follows” the data through several clock periods (data-stationary). Several typical microprograms show the effects of these two variations on hardware costs, microprogrammability, and pipeline efficiency.
The effect of instruction fetch strategies upon the performance of pipelined instruction units
Authors: Rau Ramakrishna B. , Rossmann George E.
Published: July 2004

The interpretation of a machine instruction requires fetching the instruction, decoding the instruction, and then executing it. In addition, if the instruction requires one or more operands, their addresses must be generated and the operands fetched. A large number of processors have been designed to perform some or all of these functions simultaneously on successive instructions.

These pipelined processor architectures would appear to permit the decoding of a new instruction each machine cycle.
A Large Scale, Homogenous, Fully Distributed Parallel Machine, II
Authors: Sullivan Herbert , Bashkow Theodore R. , Klappholz David
Published: July 2004

The present paper complements the hardware proposal for a fully distributed parallel processor presented in “A Large Scale, Homogeneous, Fully Distributed Parallel Machine, I,” by describing a suitable software structure for its operating system management. It is shown that the most basic operating system functions can be performed on a purely local basis, i.e. in such a fashion that identical pieces of the operating systems are concurrently executed by each of the processing elements.
On virtual memories and micronetworks
Authors: Lipovski G. Jack
Published: July 2004

We propose to use the microcomputer in a network to share I/O resources such as printers and archival memories. A model of a network is developed where computers correspond to edges of a graph. This model reflects the desired characteristics of the microcomputer organization. The advantage of virtual memory in these microcomputers is discussed. Herein, pages in the virtual memory are packets in the network. Packets and requests for packets are generated by page faults and packets are stored and forwarded by hardware like that to manage virtual memory pages. The paper discusses the strategy for a micronetwork and suggests an implementation of the hardware of such a network.
Considerations for new tactical computer systems
Authors: Strauss Jon C. , Thurber Kenneth J.
Published: July 2004

The real-time command and control environments characteristic of tactical military systems and industrial process control systems place unique and conflicting design requirements on a support computer system. These requirements include fast context switching, selective protection of programs and their files, controlled sharing of program and files, high processing speed, flexible, yet fast priority structure for interrupts and program execution, flexible high-speed I/O and flexible intercommunication and control for interacting programs. This paper describes a new computer system now being prototyped to satisfy these requirements. The system design includes a number of unique features relating to the efficient implementation of a flexible virtual memory addressing system for the stringent real-time environment.
An advanced tactical computer concept
Authors: Thurber Kenneth J. , Patton Peter C. , Deward Robert C. , Strauss Jon C. , Petschauer Thomas W.
Published: July 2004

This paper discusses the design of a real-time computer. The computer's design requirements, design decisions, and architecture are summarized. The paper discusses how the design requirements influenced the computer architecture. The system's three upward compatible addressing options (real, base, virtual) are also discussed.
Microprocessor implementation of a parallel processor
Authors: Nutt Gary J.
Published: July 2004

A wide variety of uses have been proposed for the spectrum of currently available microprocessor systems. Included in this set of applications is the use of microprocessors for implementing larger systems; here, the possibility of employing bit slice microprocessors for various parts of a multiple control unit SIMD processor is discussed. A brief summary of bit slice microprocessor architecture is given, followed by an outline of individual applications to various components such as control units and arithmetic/logic units of the SIMD processor.
The design and implementation of a real-time sound generation system
Authors: Dworak Paul , Parker Alice C. , Blum Richard
Published: July 2004

This paper describes the design and partial implementation of a real-time sound generation system currently being built at Carnegie-Mellon University. The overall design process is followed, and design decisions are discussed in the light of design goals and overall system constraints. The resulting system consists of a keyboard which is light controlled and an array of microprocessors functioning in a pipeline fashion.
Hardware/software tradeoffs in a variable word width, variable queue length buffer memory
Authors: Parker A. C. , Nagle A. W.
Published: July 2004

This paper describes a buffer memory design which is integratable on a single 40 pin package. The memory consists of four variable word width, variable length queues, address logic, and logic for configuring the data widths and queue lengths. Simple program commands input on the data lines reconfigure the memories when the circuit is in program mode. In data mode, WRITE and READ requests to a particular buffer enable the memory to load and access itself, update its pointers, and check for full, empty, and bottom of queue conditions. This design is compared to software methods for queue maintenance. Speed of operation, in terms of memory cycles and register transfers is compared for the two methods, and the hardware complexity of both methods is discussed. A short discussion of hard and software tradeoffs is followed by conclusions.
Reduction of memory interference in multiprocessor systems
Authors: Hoogendoorn Cornelis H.
Published: July 2004

This paper reports results of a study to determine and compare the effectiveness of various techniques aimed at reducing memory interference in multiprocessor multi memory systems. A simulation model of a multiprocessor, driven by address traces, is used for evaluation purposes. Two approaches to interference reduction are considered, being the reduction of overlapping memory requirements through various memory allocation methods, and the use of local memory to reduce the request rate to shared memory. Both private and cache memory are considered for this purpose.
High-speed buffering for variable length operands
Authors: Tredennick H. L. , Welch T. A.
Published: July 2004

Variable word length processing is valuable for data base manipulations, editing functions in time-sharing systems, input-output data formatting, and vector operations, but current computer architectures seldom provide efficient means for manipulating variable length operands. A specialized computer architecture has been proposed to deal with the problems of variable length byte string processing. Operand buffering is a key part of the proposed architecture because the buffer: (1) replaces registers for variable length operands, (2) resolves address precision and operand boundary problems between the main memory and the ALU, and (3) can provide simultaneous access to several operands for faster execution. General observations are made about requirements which constrain memory buffer design and the merits of four memory buffering schemes are discussed. The most suitable of the buffering schemes is discussed in some detail. This scheme provides a separate cache for each of the operands. Hardware costs and timing considerations are given, and show that the multiple-buffer approach to variable word length buffering provides a reasonable cost-performance solution.
Computer structures
Authors: Bell Gordon , Strecker William D.
Published: July 2004

Over the PDP-11'S six year life about 20,000 specimens have been built based on 10 species (models). Although range was a design goal, it was unquantified; the actual range has exceeded expectations (500:1 in memory size and system price). The range has stressed the basic mini(mal) computer architecture along all dimensions. The main PMS structure, i.e. the UNIBUS, has been adopted as a de facto standard of interconnection for many micro and minicomputer systems. The architectural experience gained in the design and use of the PDP-11 will be described in terms of its environment (initial goals and constraints, technology, and the organization that designs, builds and distributes the machine).
A design tool for the multilevel description and simulation of systems of interconnected modules
Authors: Moalla M. , Saucier G. , Sifakis J. , Zachariades M.
Published: July 2004

We suggest a methodology and a language to permit the study of a system's behavior (functional validation, evaluation of global performances, critical situations). Every system is regarded as an interconnection of communicating modules functioning in a synchronous or asynchronous manner. The control section and the data section of each module are described separately in terms of respectively non-procedural and procedural sub-languages.
A course in computer structures
Authors: Allen Jonathan
Published: July 2004

In this subject, we treat computer structure as an element of a group of interacting structures including the technology, algorithm, data, and programming language. In the belief that the best designs result when these structural factors “match” in a complementary manner, the influence of each of these domains is carefully studied at both the conceptual and descriptive levels. Thus a modular treatment of current technology is provided, as well as a thorough analysis of algorithmic structure as reflected in computational schemata. Single-sequence machine design is discussed, including advanced topics such as multiple functional unit conflict resolution. Following a presentation of microprogramming and input/output, virtual ideas centered around the notion of process are introduced, leading to the design of multiprocessing and multiprocessor systems. These ideas are applied and extended in the presentation of the Burroughs B6700 as a higher-level language machine designed to execute ALGOL efficiently. Finally, the subject concludes with an introduction to general interpretive structures for high-level languages.
The IEEE Computer Society task force on computer architecture
Authors: Rossmann George E.
Published: July 2004

The subject of computer architecture as currently taught in most computer engineering and computer science programs is a mixture of architectural principles, organizational strategies, and implementation techniques. This blurring of the hierarchy of system levels that characterize the structure of a computer has made it very difficult for students (and often instructors as well) to determine what were the forces that led to the design decisions they have seen reflected in machines.

In view of these circumstances, a task force was established by the IEEE Computer Society to prepare a detailed specification for a course of study in computer architecture for students whose major interest is in computer engineering or computer science.
A model of interference in a shared resource multiprocessor
Authors: Jensen John E. , Baer Jean-Loup
Published: July 2004

This paper presents a generalized model of tightly-coupled multiprocessor systems which is then simplified to form a stochastic model for the study of interference. Analysis is performed on the resource contention which is characteristic of such systems in order to find a measure of system performance. After reviewing the problem of memory interference, the analysis is extended to contention in other individual resources, then combined to form a model for the interacting effects of contention in systems where processors contend for several shared resources.
A computer simulation facility for packet communication architecture
Authors: Leung Clement K.C. , Misunas David P. , Neczwid Andrij , Dennis Jack B.
Published: July 2004

Several proposals for computer data processing and memory systems that exploit the inherent parallelism in programs expressed in data flow form have been advanced recently. These systems have
packet communication architecture
—each system consists of many
units
that interact only through the transmission of information packets through
channels
that link pairs of units.

A simulation facility for evaluating the programmability and potential performance of these proposed data processing and memory systems has been designed. The facility uses microprocessor modules to emulate the behavior of system units or groups of units. By conducting a simulation in accurate scale time a precise extrapolation of performance of a proposed system may be obtained.

The user of the facility will specify the system to be simulated in an architecture description language. A host computer translates the system description modules into microprocessor programs and controls the loading and monitors the operation of the microprocessors. Application of the facility is illustrated by consideration of a simple data flow processor.
Cost, performance and size tradeoffs for different levels in a memory hierarchy
Authors: Rege S. L.
Published: July 2004

This paper evaluates the effect of cost and performance tradeoffs on memory system hierarchies achieved by varying the total amount of memory at any two adjacent levels. The hierarchy is analyzed in a multiprogramming mode by using a two server cyclic queuing model. As an example, a two level hierarchy of Bipolar, MOS and a three level hierarchy of Bipolar, MOS, and CCD for the primary memory are compared. A figure of merit that is a function of the number of instructions executed by a given processor is used to evaluate the different memory hierarchies. It is shown that up to 3:1 advantage in performance can be achieved by using a three level rather than the two level hierarchy at the same total cost. The effect on the performance of the memory hierarchy due to the change in the degree of multiprogramming, the speed and cost of CCD technology used, the speed of the CPU used and the amount of CCD and MOS memory used are then evaluated. The performance of two and three level hierarchies is also analyzed as a function of the primary memory requirements versus the CCD speed.
An input interface for a real-time digital sound generation system
Authors: Dworak Paul E. , Parker Alice C.
Published: July 2004

A man/computer input interface is described in this paper. This interface allows human control of the frequency, amplitude, spectral content and envelope of real-time sound production.

The interface consists of a two-dimensional array of keys for entering data, latches and comparators to signal changes in key depression, hardware for scanning the keyboard and address generation logic. Both the fundamental frequency represented by each key column and the harmonics of each frequency—represented by each element in the column—are programmable. Amplitude and envelope are software controlled.

Applications of the interface instrument range From music composition to clinical use in auditory testing. The interface is part of an electronic sound generation system presently being designed and constructed.
Multiprogramming for real-time applications
Authors: Gladney H. M. , Hochweller G.
Published: July 2004

A software system supporting multiple event-driven processes concurrently on a small process control computer is described. Each application can be programmed and tested independently. An implementation of the system, called LABS/7, has been productive for over three years.

The limits to which real-time multiprogramming may be pushed are explored.
Basil architecture - an hll minicomputer
Authors: Kehl Theodore H.
Published: July 2004

During the past several years a computer-aided design system (the Logic Machine) has been under development in our laboratory. Briefly, the Logic Machine consists of a microprogrammable control processor, one or more functional units, one or more bidirectional buses, and a microprogram all arranged to perform a specific digital algorithm. Our major goal has been to be able to construct
any
digital device with this system. We have been able to build a graphics display terminal (1), a floating point processor (2), string/array auxiliary processor (3), and a minicomputer (4). It has amazed us to see how simple and fruitful it has been to construct these devices. In this paper we describe the use of the Logic Machine design system to build still another digital device, a high-level language minicomputer.

The motivation for this effort is probably obvious to all hardware designers; software is the most expensive part of a computer system and a high-level language computer will significantly reduce software costs. Not so obvious is the task simplification at the systems programming level, enabling a programmer to quickly review his work, decide on additions or corrections, and expand a program or system. These benefits reduce the layers of logic and, we are convinced, will enable much more sophisticated software systems to be built.
Hardware support for inter-process communication and processor sharing
Authors: Ford W. S. , Hamacher V. C.
Published: July 2004

The abstraction of a computer system as a set of asynchronous communicating processes is an important system concept. This paper indicates how the concept could be supported at a low hardware level. A new inter-process communication mechanism called a mailbox is introduced. Examples of its use as a programming tool are given. This is followed by a description of hardware features that use this mechanism as the basis of communication between the components of a complete system. These features include processor-sharing hardware capable of handling process selection and switching with high efficiency. It is also indicated how these features can take the place of conventional input/output structures.
Traversing binary tree structures with shift register memories (Recent Results)
Authors: Kluge W. E.
Published: July 2004

The paper proposes a tree-structured shift register memory in which traversals of binary data tress in pre-or end-order are performed as sequences of two non-cyclic data permutations which move the data tree relative to a unique access port that is located in the root node of the memory tree. These two permutations, denoted A and B, emulate elementary traversal steps. Permutations A correspond to traversals between nodes of an even tree level and the next higher odd level, permutations B correspond to traversals between nodes of an odd tree level and the next higher even level. Traveling from a node to its left successor requires one permutation, traveling to its right successor requires two identical permutations in succession. Three identical permutations in succession perform a counter-clockwise cyclic traversal within a subtree which comprises a (root) node, its left successor node and its right successor node; i.e. subsequences AAA and BBB yield identity. Accordingly, if the conventional address assignment of trees applies, then the permutation (traversal) sequence that is effective on the memory corresponds to the address of the node that is actually being visited. Starting to the right of the most significant '1' bit in the address code and proceeding in the order from left to right, a '0' corresponds to one permutation and a '1' corresponds to two identical permutations; the permutation is A if the bit position is even, and B if the bit position is odd. Thus, the state of permutation may be identified by the address code. The permutation sequence that traverses the data tree is generated from single control bits, associated with every node of the data tree, which distinguish between branch nodes and leaf nodes. Whenever a branch node is being visited, then the permutation to be executed next changes with respect to the preceding permutation. Whenever a leaf node is being visited, the next permutation remains the same as the previous one.
System design of a grammar-programmable high-level language machine
Authors: Fournier Serge , Liu Ming T.
Published: July 2004

An architectural concept called Grammar-Programming is introduced which allows computers to be constructed that can directly execute a variety of high-level languages. Representing an intermediate level between the basic hardware/firmware functions of ordinary computers and the software operations of language translators, it is shown how grammar-programs can be constructed which specify the syntax and semantics of various programming languages. The Grammar-Programmable Machine (GPM) then uses these specifications to process directly the users' high-level language programs. In the Ph.D. dissertation* upon which this abstract is based, a model is first developed for representing the syntactic and semantic characteristics of context-free language generators, and an automaton called a Syntax Network (SN) is constructed. Next a simple, statement-directed language is introduced to express the states of the syntax network and to define the actual grammar-programming language. A simulator is then implemented which is used to test the grammar-programs written for ALGOL and SNOBOL. Finally, the architectural organization for the Grammar-Programmable Machine is described at the register-transfer level. By taking advantage of its intermediate position between software compilation and hardware interpretation of high-level languages, the Grammar-Programmable Machine is able to emphasize the best features of both techniques and to achieve a potential that neither can reach individually.
SMS 101 - A structuredmultimicroprocessor system with deadlock-free operation scheme
Authors: Kuznia Ch. , Kober R. , Kopp H.
Published: July 2004

The presented multimicroprocessor system has been designed to treat certain problem classes such as large systems of differential equations or online process control. It consists of a main processor and an arbitrary number of modules, each with a microprocessor, a private memory and a communication memory. The most characteristic features of the SMS 101 organization are:

- a phase structured interaction scheme (PSI-Scheme) which simplifies organizational problems

- a data communication concept, that replaces common memory by simultaneously storing data in distributed memories.

A first realization of the system comprises eight modules, but the organization allows an extension up to several hundreds of modules. Thus with present day technology a computing capacity can be achieved which is 2 or 3 magnitudes higher than that of conventional computers.
Selection schemes for dynamically microcoding fortran programs
Authors: Liu Philip S. , Mowle Frederic J.
Published: July 2004

The objective of the present study has been to investigate possible methods to reduce a program's execution time by detecting and converting automatically the more frequently executed program parts, mostly inner loops, into microcode. The methods proposed were static loading of inner loops, selective loading of inner loops, over-lay of inner loops, and user-aided scheme. Using Fortran programs as the test programs, a simulation program was written to measure the gain achieved by each method. A final gain between 1.587 and 4.76 was achieved by the proposed methods for memory speed ratios between 3 and 8. It was found that 90% of the final gain of the test programs could be obtained with writable control memory requirements that were less than 40% of the final requirement.