bluuebunny/crossref_metadata_2025 huggingface dataset:
Expression of a Governing Parameter for Electromigration Damage on Metal Line Ends
Authors: Hasegawa Masataka , Sasagawa Kazuhiko , Saka Masumi , Abe´ Hiroyuki
Published: May 2010

Recently, a governing parameter for electromigration damage, AFD*gen, was identified and, utilizing the parameter, a prediction method of electromigration failure was developed for the passivated polycrystalline line. The parameter AFD*gen was formulated considering the divergence of atomic flux due to electromigration in grain boundary network, and the boundary condition of metal line ends was not taken into account. So far, therefore, failure prediction was exclusively done for the metal line connected by electric-current input/output pads at both ends, not for the line connected by vias at both ends. It is known that there is threshold current density, jth, below which no electromigration damage appears, in the line connected by vias. In this study, first, a governing parameter for electromigration damage on the ends of passivated polycrystalline line is expressed considering the boundary condition of line ends concerning the atomic diffusion. Next, the way to estimate the threshold current density of the metal line with vias is shown based on the numerical simulation using the governing parameter.
Deformation Characteristics of Solder Joints
Authors: Bastawros Ashraf , Antoniou Antonia
Published: May 2010

A novel experimental configuration is devised to measure the evolution of the deformation field and the corresponding toughness in solder joints for microelectronic packaging. The material system utilized comprised ductile layer of Tin based solder, encapsulated within relatively hard copper shoulders. The experimental configuration provides pure shear state within the constrained solder layer. Different Pb/Sn compositions are tested with grain size approaching the film thickness. The in-plan strain distribution within the joint thickness is measured by a microscopic digital image correlation system. The toughness evolution within such highly gradient deformation field is monitored qualitatively through a 2D surface scan with a nano-indentor. The measurements showed a highly inhomogeneous deformation field within the film with discreet shear bands of concentrated strain. The localized shear bands showed long-range correlations of the order of 2–3 grain diameter. A size-dependent macroscopic response on the layer thickness is observed. However, the corresponding film thickness is approximately 100–1000 times larger than those predicted by non-local continuum theories and discreet dislocation.
Evaluation of Microstructural Evolution and Thermal Fatigue Crack Initiation in Sn-Ag-Cu Solder Joints
Authors: Sayama Toshihiko , Takayanagi Takeshi , Nagai Yoshiaki , Mori Takao , Yu Qiang
Published: May 2010

Thermal fatigue damage in solder joints is believed to be closely related to microstructural evolution. In this study, a microstructural approach will be taken to evaluate the lifetime of Sn-3.0Ag-0.5Cu lead-free solder joints before the initiation of thermal fatigue cracks. In order to clarify the relation between the microstructural change and the initiation of thermal fatigue cracks, a series of thermal cycle tests were performed using fabricated PCBs on which various chip resistors were mounted. The following results were obtained via SEM observations. First, both the β-Sn and the Ag3Sn phases grow as the number of cycles N increases. This phase growth is characterized by phase growth parameters Ss and SA in the β-Sn phase and the Ag3Sn phase, respectively, which are defined as the average phase size to the 4th power. The phase growth proceeds such that the parameters increase proportionally to N. Furthermore, simple relations exist between the average number of cycles leading to the initiation of thermal fatigue cracks Ni and the average increase in the parameters per cycle ΔSs or ΔSA. That is, power law relations ΔSs = C2Ni−β and ΔSA = C3Ni−γ are determined. These relationships will enable us to evaluate the lifetime of the solder joints before the initiation of thermal cracks based on observations of microstructural evolution.
Tackling the Drop Impact Reliability of Electronic Packaging
Authors: Wong E. H. , Lim C. T. , Field J. E. , Tan V. B. C. , Shim V. P. W. , Lim K. M. , Seah S. K. W.
Published: May 2010

A 3-year collaboration program between the Institute of Microelectronics, National University of Singapore, and the University of Cambridge has been established with the following two objectives: (i) to establish a mechanics and physics-of-failure based board-level test methodology; (ii) to establish design guidelines and, ultimately, failure criteria for board level interconnect during drop/impact test. The following accomplishments have been achieved in the first year of the program: (i) the mechanics and physics of failure in a typical board-level test have been established (ii) the drop impact characteristics of 6 commercial portable products have been comprehensively surveyed; (iii) a weakness has been identified in the drop impact strength of SnAgCu solder alloy (acknowledged as the leading Pb-free solder candidate).
Analysis of an Embedded Sensor in a Composite Laminate for Enabling Damage Detection
Authors: Sealing Scott , Seeley Charles , Ardebili Haleh
Published: May 2010

A study of the influence of embedding sensors to detect damage within a composite laminate is conducted. A variety of sensors are considered along with several encapsulation materials. Encapsulation is required to aid in interfacial adhesion and to provide an electrical isolation from the graphite fiber composite laminate. This study is conducted to down-select the options for the sensor and encapsulant. A parametric global and local finite element models are developed to perform multiple runs corresponding to a design of experiments (DOE). The parameters that are varied are the sensor thickness, sensor length, encapsulant thickness, sensor modulus and coefficient of thermal expansion (CTE), and encapsulant modulus and CTE. Each parameter is varied based on the initial selection of sensors and encapsulants and considered at three levels for a quadratic transfer function. The DOE selected is a face centered CCD resulting in a total of 143 runs. The required output from each run is the effective axial and bending stiffness and the normal and shear stresses at the material interfaces. For each of these outputs from all of the runs, a transfer function is developed to identify the major contributors to the results. The resulting transfer functions indicate that the influence of the sensor and encapsulant parameters do not significantly affect the effective composites stiffness. However, they do contribute significantly to the material interfacial stresses, with the modulus of the sensor and encapsulant contributing the most to the variation of these stresses.
Numerical Simulation of a Heat Pipe Embedded Cooling System for a Notebook PC
Authors: Jia Yi , Quinones Pablo D.
Published: May 2010

A finite element model using the ANSYS® software package was developed to simulate the thermal performance of a novel heat pipe embedded thermal hinge system in a notebook computer. Introducing heat pipes into a notebook PC cooling system on the back spreader plate assists in spreading heat rapidly throughout the entire plate. The effects of the heat pipe geometry and arrangement on the performance of the cooling system were numerically investigated using the model. Various arrangements of miniature heat pipes and a vapor chamber were studied to optimize the cooling system. The numerical simulation results showed that the new system creates an almost uniform temperature distribution in the entire spreader plate, and evenly dissipates the heat load throughout the display’s back plate. The analysis further confirms that incorporating a heat pipe into a spreader plate has the ability to further battle the ever increasing power dissipation demand, which can significantly benefit operation performance of notebook PCs.
Impact Reliability Study of BGA Solder Joints and Dropping Test Method
Authors: Yu Qiang , Kikuchi Hironobu , Watanabe Keiji , Siratori Masaki , Kakino Manabu , Fujiwara Noriyuki
Published: May 2010

The purpose of this study is to develop an assessment method for drop impact reliability of BGA solder joints. In this paper, the dynamic deformation behavior of PCB is examined to evaluate the dynamic fracture of solder joints, where a free fall drop-impact test was used, and explicit-based FEM code LSDYNA was used to study the basic behavior of the drop-impact test, and the effects of falling angle on the dynamic behavior of PCB were discussed. As a result, it was confirmed even if collision angle is very small, the dynamic deformation of PCB was drastically affected by the collision angle. In this study, the authors proposed that the dynamic behavior can dramatically be improved by attaching a hemisphere on the jig bottom to obtain stable dynamic deformation of the PCB. Furthermore, in case of that the PCB flexural rigidity was changed, the optimal test jig was designed so that the PCB and the jig for a drop test might not cause resonance vibration. Generally, the crack growing assessment and drop impact strength evaluation for solder joints were studied by a fine meshing FEM model, nevertheless it causes a rapid augmentation of calculation cost. In this study, the authors proposed a new method of transient response analysis by utilizing implicit based FEM analysis code to drop the calculation cost of impact study. It was shown that the present method can accurately simulate the dynamic behavior of BGA packaging including the time histories of the deformations and stresses, and it can drop the CPU time to about one tenth of that of explicit based analysis code.
Effect of Package and Board Pad Size on Optimum Flip Chip Ball Grid Array (FCBGA) Package Thermo-Mechanical Performance
Authors: Wong Chee Wai , Tay Cheng Siew , Tan Siew Sang , Vasudevan Vasu , Goh Eng Huat , Wong Shaw Fong
Published: May 2010

Flip Chip Ball Grid Array (FCBGA) has been a common package technology to achieve higher Input/Output (IO) count. In moving toward higher IO count without increasing the package size, FCBGA package with tighter pitch is required. Unfortunately, ball pitch reduction from 1.27mm to 1mm in FCBGA packages is not a transparent change. Instead, it provides an inside into the thermo-mechanical performance of FCBGA solder joint. Previous study indicated the importance of the package solder resist opening-to-board pad size ratio (AR) as the dominant factor in improving the thermo-mechanical performance of the solder joint at one solder system. An optimum range of AR had been defined as failure free zone with respect to the temperature cycling stress from −40degC to 85degC. This paper is a continued study, which focused on identifying the optimum range of AR for failure free zone. Key factors under the study are package solder resist opening (SRO), die size, population pattern, type of board pad, type of package design and thermal solution. This paper consolidates the modeling and empirical data on the relationship. The results of the study has brought towards an identification of process window for 1mm pitch FCBGA package and led to package and board design rules in terms of targeted SRO & board pad size, type of pad design and a tightening of SRO & board pad size specification. Besides, the learning has led towards a new look into the BGA package certification in which SRO and board pad size are key factors in the design consideration.
Isothermal Shear Fatigue Life of Sn-xAg-0.5Cu Flip Chip Interconnects
Authors: Kariya Yoshiharu , Hosoi Takuya , Terashima Shinichi , Tanaka Masamoto , Otsuka Masahisa
Published: May 2010

The mechanical shear fatigue test has been performed to look for the effect of silver content on the fatigue properties of Sn-xAg-0.5Cu (x = 1, 2, 3 and 4) flip chip interconnections. As the strength of the solder alloy increases with increasing silver content, the increase in silver content results in preventing a shear plastic deformation of solder bump. Therefore, the flip chip joints made using higher silver content solder such as 3 and 4Ag exhibit longer fatigue life, if the same levels of displacement is applied. The fatigue ductility of the solder decreases with increasing the silver content. Therefore, the fatigue endurance of the 1Ag solder itself is superior to other solders in high plastic strain regime, even though the strength of the solder is the lowest in the solders tested. Based on this study, the 3Ag solder might exhibit good fatigue performance for all condition, and the 1Ag solder is optimum for severe strain condition.
Arbitrarily Configurable Optical Interconnect Fabric for Intrachip Global Communication
Authors: Haney Michael W. , Iqbal Muzammil , McFadden Michael J.
Published: May 2010

Optical interconnections at the chip level may provide solutions to the limitations of metal interconnect technology, which is not keeping pace with the progress of device integration density. In this paper we undertake a quantitative analysis of on-chip metal interconnect performance as CMOS device technology scales into the nanometer regime. The results of this analysis motivates the use of optical interconnects as a replacement for global wires on the chip. We propose a new architecture, in which a 3-D optoelectronic Application Specific Interconnection Fabric (ASIF) is coupled to a conventional Silicon integrated circuit to alleviate the performance-limiting aspects of long metal interconnects. The overall goal of the ASIF concept is to overcome the limitations of conventional metal interconnects in a manner that can be seamlessly integrated according to current VLSI design constraints and practices.
Vapor Pressure Assisted Interface Delamination and Failure of Plastic IC Packages: A Micromechanics Approach
Authors: Chong C. W. , Guo T. F. , Cheng L.
Published: May 2010

Insights into delamination and popcorn cracking in plastic IC packages can be gained by studying the vapor pressure assisted void growth and coalescence at critical interfaces. The interface of interest for this paper is the die-pad/molding compound interface which is a site that is highly susceptible to delamination. A mechanism-based approach is adopted to simulate the initiation of debonding at the interface, and its subsequent growth. A layer of voided cells, governed by the extended Gurson constitutive law with vapor pressure incorporated as an internal variable, is embedded along the initially intact interface. Simulations are carried out under conditions similar to the specifications stated by the Moisture Sensitivity Test (MST). The extent of damage across the die-pad/molding compound interface is examined, and subsequent cracking is modeled. A full field analysis is carried out to investigate the moisture-induced damage in the entire molding compound as well.
Modeling the Laser Ablation Process Using Neural Networks
Authors: Setia Ronald , May Gary S.
Published: May 2010

Laser ablation has become an increasingly important process in the fabrication of microelectronic packaging substrates. In this research, laser ablation has been applied to drilling via holes during the sequential build-up process of a multilayer substrate. Since the quality of the process is influenced considerably by the process set points, studies that characterize the relationship between these conditions and the characteristics of the vias formed are necessary. This paper examines vias with diameters of 30, 40, and 50 μm ablated in DuPont Kapton® E polyimide using an Anvik HexScan™ 2150 SXE excimer laser. A statistical experiment using a 25−1 fractional factorial design was conducted to determine the significance of laser energy, shot frequency, number of pulses, and vertical and horizontal positions of the debris removal system in the laser tool affecting the top via diameter, via wall angle, and the ablated thickness of the dielectric. Several input factors and two-factor interactions were found to be statistically significant (p-value < 0.05). Following the collection of the experimental data, neural networks (NNs) were trained using the error back-propagation algorithm to model the average values of the responses. The prediction error for all the NN models was less than 5.5%.
Integrated Optics in a Standard MCM-D Motherboard Technology Demonstrated in O/E Measurement Probes
Authors: De Pauw H. , De Baets J. , Vanfleteren J. , Van Calster A.
Published: May 2010

An ongoing trend in packaging technology is the introduction of optical interconnections to cope with the problems of increased data transmission speed and the raised interconnection density. Hence, improving packaging and interconnection technologies is only viable if the aspects of optical interfaces and opto-electronic (O/E) components are considered. In this paper, we will demonstrate an MCM-D technology with O/E features. We achieved to integrate high-precision V-grooves for alignment and fixation of the optical fibers into a standard MCM-D technology. The V-groove shape of the fiber fixation structures is a result of the anisotropic etching of (100) silicon by means aqueous KOH. The technology aspects of this aggressive wet etching step are discussed as well as the optimisation results of a suitable KOH masking layer: a low refractive index PECVD nitride. The extension of an MCM-D technology with V-grooves generates the possibility to integrate side-emitting O/E components and fibers with the electronics on the same MCM-Si motherboard. This implies a more dense and compact motherboard with the potential of obtaining higher bandwidths due to the minimal distance between optics and electronics. Additionally, low coupling losses between O/E components and fibers are obtained by means of passive alignment as the accuracy of the V-grooves in silicon allow us to place the fibers with high precision. The feasibility of this optics-extended MCM-D technology will be shown in the example of O/E measurement probes. In the fabrication process of such O/E measurement probes, we will focus on the multilayer MCM-D motherboard extended with V-grooves, on the FC mounting of both RF-amplifier chip and laserdiode, and on the alignment of the fiber.
Source Synchronous Double Data Rate (DDR) Parallel Optical Interconnects
Authors: Gui Ping , Kiamilev Fouad , Wang Xiaoqing , McFadden Michael , Kuznia Charlie , Ekman Jeremy , Deroba Joseph , Haney Michael
Published: May 2010

Double data rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous, DDR optical signaling. On the transmit side, two 8-bit electrical inputs are multiplexed, encoded and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-bit electrical outputs. Our IC integrates analog Vertical Cavity Surface Emitting Lasers (VCSEL), drivers and optical receivers with digital DDR multiplexing, serialization, and deserializaton circuits. It was fabricated in a 0.5-micron Silicon-on-Sapphire (SOS) CMOS process. Linear arrays of quad VCSELs and photodetectors were attached to our transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mbps with a 250 MHz DDR clock, achieving a gigabit of aggregate bandwidth. While our DDR scheme is well suited for low-skew fiber-ribbon, free-space and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To our knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.
Spray Cooling Thermal Management of a Semiconductor Chip Undergoing Probing, Diagnostics, and Failure Analysis
Authors: Ansari S. , Cader T. , Stoddard N. , Tolman B. , Frank J. , Cotton D. , Wong T. , Pakdaman N.
Published: May 2010

With the proliferation of flip chip packaging and multiple metal layer technology in advanced semiconductor integrated circuits (IC’s), traditional front-side probing and failure analysis tools are no longer viable. Full transistor level access from the substrate side (i.e., backside) of the chip is now required to fully realize such investigative work. Silicon is transmissive in the near-IR above its bandgap (≅ 1,000nm to 1,100nm). As a result, transistor level access can be achieved by optical means. To enable such optical access, it is necessary to first remove all heat dissipating devices such as finned heat sinks and integrated heat spreaders placed in contact with the silicon substrate. For most applications, the silicon is then mechanically thinned down to approximately 100μm, and a microscope objective is used to “probe” the chip optically for diagnostics and failure analysis. During such diagnostics and failure analysis, the device under test (DUT) is electrically exercised typically “at speed”, which translates into high power dissipation levels. A thermal management system that can be physically and optomechanically integrated with state-of-the-art diagnostics and failure analysis systems, and can dissipate significant power levels is required to maintain the DUT’s temperature equilibrium and avoid thermal runaway, that could irreversibly damage the DUT. One possible and efficient solution is provided by spraying a dielectric coolant directly onto the chip. In the present study, a test chip was used in conjunction with an exact model of a novel microscope objective that is in full contact with the device. The test chip was powered in increments from 0 to 82W/cm2, and the device level temperature was measured by several temperature sensors embedded in the chip. A spray head was designed to deliver conditioned coolant to the test chip’s surface, while simultaneously accommodating the obstruction of the microscope objective and allowing full optical access to the entire chip surface. Thermal performance results for the cooling system are provided for uniform heat flux levels of 30, 52, and 82W/cm2, with the optical probe located in the worst-case center of the test chip. For all heat fluxes studied, the maximum device level temperature did not exceed 60°C, the across-chip temperature differential was approximately 31°C, and surface temperature fluctuations were seen to have a standard deviation of less than ±1°C. The results are discussed in-depth, and are put in perspective of industry needs.
Calibration Systems and Techniques for Automated Microassembly
Authors: Tsui K. , Geisberger A. , Ellis M. , Skidmore G.
Published: May 2010

A calibration technique is presented here that facilitates automated calibration of a robotic system used for open loop MEMS assembly. A micromechanical calibration device was fabricated in a 20 μm thick electro-plated nickel process as well as a 50 μm thick single crystal silicon, deep reactive ion etched (DRIE) process. This device uses a vision sensing system to detect end-effector position. Results obtained using the calibration device, are presented using a microgripper for pick and place assembly. The relative position of the microgripper and die-site was calibrated to an accuracy of ±1 μm using the described techniques. Microgripper geometry obtained using this technique is also ≤ 3.1 μm of the direct measurement. By utilizing these calibration techniques, the assembly system can be automated to yield a cost-effective microassembly solution.
Solution Space Analysis of High-Density Flex Substrates for 10 GE Optical Transceiver Applications
Authors: Fan Wei , Lu Albert Chee W. , Wai Lai L. , Ho Voon Yee , Gundel Douglas B.
Published: May 2010

This paper presents the application of a solution space methodology to coupled coplanar and microstrip interconnects on high-density flex substrates. Electromagnetic simulations, cross talk characterization and eye diagram measurements indicate good high-speed performance attributes.
Characterization of Time and Temperature Dependent Mechanical Behavior of Underfill Materials in Electronic Packaging Application
Authors: Kuo Chia-Tai , Yip Ming-Chuen , Chiang Kuo-Ning
Published: May 2010

The thermo-mechanical testing of HYSOL FP4549 polymer-filled underfill material was conducted under different strain rate and temperature environment. A new specimen preparation procedure and further test methodology are developed to characterize the underfill time-temperature mechanical behaviors. The stress-strain behavior of materials is simulated with constitutive framework, and the dependence of Young’s modulus on temperature and strain rate was evaluated. In addition, the specimens were tested with micro-tensile system to evaluate the underfill materials creep curve as a function of temperature and stress level. In view of the uncertainty of the Young’s modules determination, the specimens were tested with unloading-reloading technique to verify the test results and investigate its cyclic mechanical behaviors. On the other hand, the adhesion strength are tested between different adhesion surface by different deformation rate after some isothermal and hygro-thermal environments attack, which is to simulate the environment that the electronic components may be encountered. The results reveal that the rise of the temperature and moisture cause the apparent reduction of the surface adhesion strength, due to the material microstructure transition and the diffusion and concentration of moisture. For all conditions of the experiment after environmental preconditioning, the specimen fracture surfaces occur between solder mask and FR4 substrates, which means the measured strength is the adhesion strength between solder mask and FR4. Comparing different adhesion surface, the adhesion strength of underfill/FR4 is higher than solder mask/FR4. In addition, it has found that the fracture strain and the slope of the load-deformation diagram increases with the decreasing deformation rate. The interface of solder mask/FR4 is more sensitive to the temperature and moisture.
Characterisation of Anisotropic Conductive Adhesive Compression During the Assembly Process
Authors: Whalley David C. , Kristiansen Helge , Liu Johan
Published: May 2010

Models of the anisotropic conductive adhesive assembly process have previously been developed. Such models may be used to predict the time for adhesive resin flow out and whether this can be successfully achieved before resin cure. Modelling has also been used to provide significant insights into the effects of component and substrate bond pad geometry on the resin flow distribution and hence on the resulting conductive particle distribution. These models have however only been experimentally validated to a very limited extent. This paper will describe a new experimental technique, which has been developed to allow continuous monitoring of the adhesive thickness throughout the compression process. This technique applies a controlled assembly force through a linear “voice coil” type actuator and the resulting changes in capacitance of the adhesive material can be used to monitor its thickness. The data from tests using this technique show, for example, the effect of the conductor particle stiffness on the rate of adhesive compression during the later stages of the compression process. Such data will be used to further improve more sophisticated models of the ACA assembly process, which will both lead to a better understanding of the process and also facilitate establishment of design rules for different applications.
Packaging of Arrayed Waveguide Grating Demultiplexer and Subsequent Device Characterization
Authors: Grobnic Amelia G. , Callender Claire L. , James Robert , Noad Julian P.
Published: May 2010

This paper focuses on the optical alignment, packaging and subsequent characterization of a low-loss acrylate polymer arrayed waveguide grating (AWG) multiplexer/demultiplexer. Process, equipment and set-ups used for optical alignment and packaging of the AWG device are presented. The AWG itself was used as a vehicle for the package characterization. The variation of the output optical power versus wavelength for the packaged AWG channels is presented, analyzed and compared with theoretical calculation results. The variation of the packaged AWG center wavelength for each channel with temperature (peak wavelength thermal shift) over a range of temperatures between 18°C and 42°C is analyzed and the test results discussed. The thermal stability of the packaged AWG device, determined by the spectral response measurements over a similar range of temperatures is investigated. During the heating and cooling processes the packaged AWG is subjected to thermal stress. These phenomena are investigated and a thermal analysis (temperature distribution simulation) performed. Finally, conclusions and recommendations for future AWG packaging are presented.
Measurement of Hygroscopic Swelling in Mold Compounds and Its Effect on PEM Reliability
Authors: Stellrecht Eric , Han Bongtae , Pecht Michael
Published: May 2010

Hygroscopic stresses arise in a plastic encapsulated microcircuit (PEM) when the mold compound swells upon absorbing moisture and the lead frame, die paddle, and silicon die, do not experience swelling. Similar to the thermal stress produced by the mismatch of coefficients of thermal expansion between adjacent materials, the hygroscopic stress increases as the hygroscopic swelling coefficient of the mold compound increases. Accurate measurement of hygroscopic swelling is essential in assessing the effect of hygroscopic stresses on package reliability. In this paper, a whole-field experimental method to characterize the hygroscopic swelling of mold compounds is proposed. The method is implemented to determine the hygroscopic swelling and the corresponding coefficient of hygroscopic contraction of five commercial molding compounds. A comparison between the hygroscopic and thermally induced mismatch strains in PEMs is presented and its implication on PEMs reliability is discussed.
Parameter Optimization for a Temperature Estimation Model
Authors: Smith J. Cole , Ortega Alfonso , Gabel Colleen M. , Henderson Dale
Published: May 2010

We consider a problem arising in designing Compact Thermal Models (CTMs) for the purpose of simulating the thermal response of a package. CTMs are often preferred over more detailed models due to their minimal representation and the reduced computations required to obtain accurate nodal temperature predictions under hypothetical scenarios. The quality of CTM performance depends on the determination of an appropriate set of parameters that drive the model. The subject of this paper is a heuristic nonlinear optimization approach to computing the set of CTM parameters that best predicts the thermal response of a package. Our algorithm solves a series of one-dimensional nonconvex optimization problems to obtain these parameters, exploiting the special structure of the CTM in order to improve both the execution time of the algorithm and the quality of the CTM performance. We conclude the paper by providing a brief array of computational results as a proof of concept, along with several possible future research extensions.
A Chip-on-Beam Calibration Technique for Piezoresistive Stress Sensor Die
Authors: Jaeger Richard C. , Suhling Jeffrey C. , Chen Yonggang , Rahaman Shahan , Islam M. Nokibul
Published: May 2010

Wafer-level and four-point-bending (4PB) techniques are normally utilized for calibration of stress sensor test die. While excellent accuracy and repeatability have been demonstrated, the wafer-level technique requires access to a complete silicon wafer, whereas the 4PB method requires 5–10 cm strips of die. However, access to full wafers, or even strips of die, is typically limited to companies and universities with captive semiconductor fabrication facilities. In this paper, a chip-on-beam technique is demonstrated in which individual die are attached to silicon beams, and stress for calibration is applied to the beam using a precision 4PB fixture. Because of the resulting nonuniform stress distribution on the surface of the die, experimental measurements must be combined with finite element simulation results to extract the desired piezoresistive coefficients. These calibration results are compared to those obtained directly from strips of the same die, and it is shown that excellent agreement can be obtained between the two methods under proper experimental conditions. This work delineates the best location for calibration rosettes on the die as well as design of the beam geometry, relative to the chip dimensions, that will ensure the high accuracy calibration results. This technique permits measurement of the piezoresistive coefficients for a limited set of die such as those that may be obtained from typical MOSIS fabrication runs.
The Impact of Board Layout and Layup on PWB Warpage During Fabrication and Due to Reflow Solder Process: A Review of Literature
Authors: Ahn Wonkee , Agonafer Dereje , Novotny Shlomo
Published: May 2010

PWBA warpage is further compounded by the high densification of the PWBA, where heat dissipation occurs over a very small area during in-service operation. Automated component placement or insertion is difficult and sometimes impossible to achieve on a warped board. PWB assembly warpage will results in many problems including non co-planarity, chip/component surface crack, delamination, poor connectivity, floating, creep, failure and so on. Also PWBAs are sometimes subjected to mechanical loading as well as thermal loading during their lifetime, which will cause PWB deflection and stress/strain in the PWB assemblies. These mechanical loading will increase stress/strain level inside PWB and may have an effect on interconnect, PWB, or package reliability. In order to evaluate the reliability of PWBA, an optimal modeling is necessary. This paper reviews the literature with an understanding of layout and layup impact on PWB warpage for minimizing warpage of PWB architecture. This compilation of literature would help to enhance the quality and reliability of products by minimizing failures of device and component from PWB excessive warpage and to reduce production cost because of minimizing repair needs on the production line.
Compact Modeling of Unshrouded Plate Fin Heat Sinks
Authors: Narasimhan Sridhar , Bar-Cohen Avram
Published: May 2010

The present work considers the compact modeling of unshrouded parallel plate heat sinks in laminar forced convection. The computational domain includes three heat sinks in series, cooled by an intake fan. The two upstream heat sinks are represented as “porous blocks”, each with an effective thermal conductivity and a pressure loss coefficient, while the downstream heat sink, assumed to be the component requiring the most accurate characterization, is modeled in detail. A large parametric space covering three typical heat sink geometries, as well as a range of common inlet velocities, separation distances between the heat sinks, and bypass clearances is considered in the development and evaluation of the compact models. The current study uses a boundary layer-based methodology, accounting for both the viscous dissipation and form drag losses, to determine the pressure drop characteristics, and an effective conductivity methodology, using a flow bypass model and Nusselt number correlation, to determine the effective thermal conductivity, for the porous block representation of the heat sink. The results indicate that the introduction of compact heat sinks has little influence on the pressure drop of the critical heat sink. Good agreement in pressure drops, typically in the range of 5%, is also obtained between “detailed” heat sink models and their corresponding porous block representation. The introduction of the compact models is found to have little influence (typically less than 1°C) on the base temperature of the critical heat sinks. For the compact heat sinks, the agreement is again within a typical difference of 5% in thermal resistance. Dramatic improvements were observed in the mesh count (factor > 10X) and solution time (factor >20X) required to achieve a high-fidelity simulation of the velocity, pressure, and temperature fields.
MEMS Mirror Switch for Multi-Channel Spectrophotometer
Authors: Tuantranont Adisorn , Lomas Tanom , Bright V. M.
Published: May 2010

In this paper, the design, fabrication and performance of a MEMS-based micromirror switch used for routing a probing light signal in a multi-channel fiber optics spectrophotometer are presented. Our MEMS-based micromirror switch is a surface micromachined mirror fabricated through commercial available Multi-User MEMS Process (MUMPs) foundry service. The mirror is suspended by the double-gimbal structure, which consists of two pairs of torsion bars for X and Y axis scanning. Self-assembly by solders is used to elevate the torsion mirror 30 micron over the substrate to achieve large scan angle. The operating scan angle is in the range of 3.5 degrees with driving voltage of 0–100 V. The fastest switching time of 4 millisecond (1 ms rise time and 3 ms fall time) is measured corresponding to the maximum speed of the mirror of 0.25 kHz when the mirror is scanning at +/− 1.5 degree. The micromirror switch is packaged with a multi-mode fiber bundle using active alignment technique. Maximum insertion loss of 5 dB has been obtained.
Measurement of the Mode Mix Dependent Interfacial Fracture Toughness for a Ti/Si Interface Using a Modified Decohesion Test
Authors: Modi Mitul B. , Sitaraman Suresh K.
Published: May 2010

The Modified Decohesion Test (MDT), developed by the authors, eliminates shortcomings of current interfacial fracture toughness testing methods. In this approach, a highly stressed super layer is used to drive delamination and create any mode mix at the crack tip. MDT uses the change in crack surface area to vary the available energy per unit area for crack growth and thus to bound the interfacial fracture toughness. Therefore, this technique uses a single sample to measure the interfacial fracture toughness, as opposed to the decohesion test that uses several samples to be able to bound the interfacial fracture toughness. Since the deformations remain elastic, a mechanics-based solution can be used to correlate test parameters to the energy release rate. Common IC fabrication techniques are used to prepare the sample and execute the test, thereby making the test compatible with current microelectronic or MEMS facilities. In this paper, the mechanics based solution used in the MDT to correlate test parameters to the fracture metrics is discussed and compared against other analytical models. Interfacial fracture toughness results are provided for a Ti/Si interface at several mode mixes.
Failure and Reliability Analysis Influenced by Various Factors Using Accelerated Disturbed State Concept
Authors: Whitenack Russell D. , Desai Chandra S.
Published: May 2010

The disturbed state concept (DSC) presented herein represents a unified and powerful approach for constitutive modeling of materials and interfaces in electronic packaging. Together with the computer finite element procedure it provides an analysis tool for calculation of stresses, strains, disturbance and cycles to failure. The accelerated procedure allows economical approximation of cycles to failure and distribution of disturbance at different cycles for design and reliability.
Design and Reliability in Electronic Packaging Including Power Temperature Cycling and Vibration Effects
Authors: Nickerson Mark D. , Desai Chandrakant S.
Published: May 2010

Thermomechanical, power temperature cycling (PTC) and vibration analyses were performed on a 313 staggered pin PBGA package using plastic and viscoplastic disturbed-state damage models. An accelerated finite element failure analysis was performed using a newly developed procedure. Validations were performed using published PBGA test data. The disturbed state concept was used to model the disturbance (damage) accumulated in PBGA solder joints subjected to thermal cycling (PTC and TCT), vibration, and vibration coupled with three distinct temperatures. 2D FEA plastic and viscoplastic models were created based on a diagonal “slice” of the PBGA. This allowed the most critical solder balls (under the die and furthest DNP) to be analyzed in the same model. The thermal cycling results indicate that the solder balls under the die are the most likely to fail. The vibration results indicate the solder balls furthest from the package center are most likely to fail. The vibration results, coupled with distinct isothermal temperatures, indicate that as temperature increases, the cycles to failure decreases.
Creep and High-Temperature Isothermal Fatigue of Pb-Free Solders
Authors: Zhang Qian , Dasgupta Abhijit , Haswell Peter
Published: May 2010

The creep resistance of Sn3.9Ag0.6Cu Pb-free solder alloy is compared to that of the baseline eutectic Sn37Pb solder at comparable homologous temperatures. Sn3.9Ag0.6Cu is significantly more creep-resistant than Sn37Pb solder. The isothermal cyclic mechanical durability of Sn3.5Ag and Sn3.9Ag0.6Cu Pb-free solder alloys are presented and compared to that of the baseline eutectic Sn37Pb solder at comparable homologous temperature. Cyclic mechanical tests are performed at high temperature at various strain-rates and load levels, using a thermo-mechanical-microstructural (TMM) test system developed by the authors. The data is analyzed using standard power-law durability models based on 50% load drop, using cyclic work and cyclic inelastic strain range. The durability curve of Sn3.9Ag0.6Cu Pb-free solder is found to have the largest slope, followed by the Sn3.5Ag solder and finally the baseline Sn37Pb eutectic solder, under the test conditions investigated. At a homologous temperature of 0.75, Sn3.9Ag0.6Cu shows the best durability, while Sn3.5Ag and Sn37Pb have very similar durability performance according to damage relations based on either work or inelastic strain range. The damage propagation rate is also estimated for all three solders, based on the load drop rate, and plotted vs. cyclic work and cyclic inelastic strain range.
A Large Scale Ongoing R&D Project on Three-Dimensional Seismic Isolation for FBR in Japan
Authors: Kato A. , Umeki K. , Morishita M. , Fujita T. , Midorikawa S.
Published: May 2010

FBR is well known as a reactor that breeds the nuclear fuel. As Japan has little nuclear resources in its territory, the technologies those realize Fast Breeder Reactor (abbreviated FBR) have been developed for decades. The results of the development have been demonstrated through the construction and operation of the experimental fast reactor JOYO and the prototype FBR MONJU. In 1999, the R&D to realize the commercialized FBR has started as a national project. In the project, improving the economic competency of the commercialized FBR plant was set as one of the most important objectives as well as enhancing the safety.
Three Dimensional Seismic Isolation System Using Hydraulic Cylinder
Authors: Kajii Shinichiro , Sawa Naoki , Kunitake Nobuhiro , Umeki K.
Published: May 2010

A three-dimensional (3D) seismic isolation system for FBR building is under development. The proposed vertical isolation system consists form hydraulic cylinders with water-based liquid and accumulators to support large vertical static load and to realize low natural frequency in the vertical direction. For horizontal isolation, laminated rubber isolator or sliding type isolator will be combined. Because the major part of the feasibility of this isolation system depends on the sealing function and durability of the hydraulic cylinder, a series of feasibility tests of the hydraulic cylinder have been conducted to verify the reliability against seismic load and seismic motion. This paper describes the specification of the seismic isolations system, seismic response characteristics and the results of the feasibility tests of the seal. This study was performed as part of a government sponsored R&D project on 3D seismic isolation.
Development of Three Dimensional Seismic Isolation Device With Laminated Rubber Bearing and Rolling Seal Type Air Spring
Authors: Suhara Junji , Tamura Tadashi , Okada Yasuo , Umeki Katsuhiko
Published: May 2010

Three dimensional (3D) seismic isolation device has been developed to use for the base isolation system of the heavy building like a nuclear reactor building. The developed device is the 3D seismic isolation device that consists of the laminated rubber bearing as a horizontal isolation device and the rolling seal type air spring as the vertical isolation device in series. In this research, the 3D seismic isolation device reduction model whose scale is 1/10 is made and the workability of the device by the horizontal and vertical dynamic load is examined. Two experiment parameters are considered. One is the case that the structure of the part that the horizontal load and the vertical load contact is pin condition and the other is the case of the roller condition. As a result of the examination, the workability of the vertical direction is confirmed when the horizontal load acts. The pressure resistant ability test for the air spring is performed by the monotonic pressurization. As the result, it is confirmed that pressure resistant ability improved by restricting the side deformation of the air spring and that the material of the existing air spring can withstand high pressure use sufficiently. As the result, it is confirmed that the developed 3D seismic isolation device is applicable to the actual plant.
Cost-Effectiveness Evaluation of Seismically Isolated Pool Structures Considering Fluid-Structure Interaction
Authors: Koh Hyun-Moo , Park Kwan-Soon , Song Junho
Published: May 2010

A procedure for evaluating cost-effectiveness of seismically isolated pool structures is presented. The ground motion is modeled as the spectral density function matching the response spectrum, which is specified in codes in terms of acceleration and site coefficients. Interaction between flexible walls and contained fluid is considered in the form of added mass matrix. The thickness of wall and the stiffness of isolator are used as main design variables while the minimum cost for comparison is estimated. Transfer function vector of the system is derived and spectral analysis method based on random vibration theories is used for calculating probability of failure. Evaluation results of the examples show that the cost-effectiveness of seismically isolated pool structures is relatively high in regions of low to moderate seismicity.