Building III-V Devices onto Large Si Wafers
Authors: Bao Xin-Yu , Ye Zhiyuan , Carlson David , Sanchez Errol 
Published: February 2020

III-V semiconductor materials have been drawing extensive interests in the past decades due to their superior electronic and optical properties with great potential to improve the device performance. Compared to Si, III-V materials have mobility about 10 times higher and injection speed 2~3 times faster. CMOS devices can benefit from higher mobility and injection speed to improve operation frequency, current, power consumption, and reduce short channel effect, etc. With direct bandgap and sophisticated bandgap engineering, III-V materials also provide board range of optical applications such as optical transceivers, infrared and visible LEDs/photo detectors, photovoltaics, and lasers. It’s ideal and cost effective to integrate III-V with large Si substrate (e.g. 300mm) to take advantage of the main stream Si process flow in the semiconductor industry. The biggest challenges are lattice mismatch and anti-phase boundary (APB) caused by polar/nonpolar planes. In this paper, we reviewed the issues for growth on blanket wafers and selective growth on patterned wafers using the Applied Materials’ 300mm III-V metal-organic chemical vapor deposition tool (MOCVD).

On nominal non-offcut Si (100) blanket wafers prevalently used in industry, multiple layers are typically used as buffer stack to bridge the lattice mismatch between the Si substrate and final device layer. Ge buffer layer was first tested to achieve high quality GaAs film with APB free top surface on Si substrates with very small off-cut angles (≤0.5º) [1]. For growth directly on Si, it is critical to form proper double-step Si layers prior to the III-V layer deposition to reduce APB density. We found the oxygen and carbon residual contamination is directly correlated to the APB density for GaAs growth on Si (100). The APB density at the GaAs top surface increased significantly from 0.14 to 3.2μm-1 while the O and C dose at Si/GaAs interface increased from 7.3x1011 to 4.0x1012 atoms/cm2 and from 1.9x1014 to 1.7x1015 atoms/cm2, respectively. [2] By optimizing the process, the GaAs top surface can be virtually APB free with total thickness as thin as 150nm. The electrical and optical properties of GaAs film can be greatly improved when APB is eliminated. Hall Effect measurements revealed a mobility enhancement from 200 to 2000 cm2/V.s. The room temperature photoluminescence (PL) intensity increased almost 10 times. [3] Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (Lg) as small as 20 nm which showed high transconductance about 2000 μS/μm at VDS=0.5V and 142 mV/dec subthreshold swing (SS). The III-V buffer layers were grown on 300 mm Si substrates by MOCVD and the subsequent InAlAs bottom barriers and InAs channel were grown by MBE. [4]

Selective growth on patterned wafers can benefit from defect trapping in high aspect ratio structures. We successfully grew high quality GaAs, InGaAs and InAlAs layers in both narrow and wide trenches ranging from tens of nanometers to hundreds of nanometers. [5-7] It’s shown that the APB density is lower in higher aspect ratio trenches. InxGa1-xAs (x=0.1-0.4) quantum wells with stack GaAs/AlAs/InGaAs/AlAs/GaAs in 100nm wide trenches were demonstrated and room temperature μPL spectra were observed. We also explored the concept of III-V FinFET devices which uses InGaAs as channel layer.

Reference

[1] Y. Bogumilowicz, et al., Applied Physics Letters 107, 212105 (2015).

[2] C. Barrett, et al., Journal of Materials Science 51, 449-456 (2016).

[3] R. Alcotte, et al., APL Materials 4, 046101 (2016).

[4] C. Y. Huang, et. al., International Symposium VLSI Technology, Systems and Application (2015).

[5] W. Guo, et al., Applied Physics Letters 105, 062101 (2014).

[6] R. Cipro, et al., Applied Physics Letters 104, 262103 (2014).

[7] B. Wood, et al., International Symposium VLSI Technology, Systems and Application (2015).