bluuebunny/crossref_metadata_2025 huggingface dataset:
An Empirical Evaluation of Visuo-Haptic Feedback on Physical Reaching Behaviors During 3D Interaction in Real and Immersive Virtual Environments
Authors: Ebrahimi Elham , Babu Sabarish V. , Pagano Christopher C. , Jörg Sophie
Published: July 2016

In an initial study, we characterized the properties of human reach motion in the presence or absence of visuo-haptic feedback in real and Immersive Virtual Environments (IVEs) or virtual reality within a participant’s maximum arm reach. Our goal is to understand how physical reaching actions to the perceived location of targets in the presence or absence of visuo-haptic feedback are different between real and virtual viewing conditions. Typically, participants reach to the perceived location of objects in the three-dimensional (3D) environment to perform selection and manipulation actions during 3D interaction in applications such as virtual assembly or rehabilitation. In these tasks, participants typically have distorted perceptual information in the IVE as compared to the real world, in part due to technological limitations such as minimal visual field of view, resolution, latency, and jitter. In an empirical evaluation, we asked the following questions: (i) how do the perceptual differences between virtual and real world affect our ability to accurately reach to the locations of 3D objects, and (ii) how do the motor responses of participants differ between the presence or absence of visual and haptic feedback? We examined factors such as velocity and distance of physical reaching behavior between the real world and IVE, both in the presence or absence of visuo-haptic information. The results suggest that physical reach responses vary systematically between real and virtual environments, especially in situations involving the presence or absence of visuo-haptic feedback. The implications of our study provide a methodological framework for the analysis of reaching motions for selection and manipulation with novel 3D interaction metaphors and to successfully characterize visuo-haptic versus non-visuo-haptic physical reaches in virtual and real-world situations.
How to Build Static Checking Systems Using Orders of Magnitude Less Code
Authors: Brown Fraser , Nötzli Andres , Engler Dawson
Published: July 2016

Modern static bug finding tools are complex. They typically consist of hundreds of thousands of lines of code, and most of them are wedded to one language (or even one compiler). This complexity makes the systems hard to understand, hard to debug, and hard to retarget to new languages, thereby dramatically limiting their scope. This paper reduces checking system complexity by addressing a fundamental assumption, the assumption that checkers must depend on a full-blown language specification and compiler front end. Instead, our program checkers are based on drastically incomplete language grammars ("micro-grammars") that describe only portions of a language relevant to a checker. As a result, our implementation is tiny-roughly 2500 lines of code, about two orders of magnitude smaller than a typical system. We hope that this dramatic increase in simplicity will allow people to use more checkers on more systems in more languages.

We implement our approach in μchex, a language-agnostic framework for writing static bug checkers. We use it to build micro-grammar based checkers for six languages (C, the C preprocessor, C++, Java, JavaScript, and Dart) and find over 700 errors in real-world projects.
Baymax
Authors: Chen Quan , Yang Hailong , Mars Jason , Tang Lingjia
Published: July 2016

Modern warehouse-scale computers (WSCs) are being outfitted with accelerators to provide the significant compute required by emerging intelligent personal assistant (IPA) workloads such as voice recognition, image classification, and natural language processing. It is well known that the diurnal user access pattern of user-facing services provides a strong incentive to co-locate applications for better accelerator utilization and efficiency, and prior work has focused on enabling co-location on multicore processors. However, interference when co-locating applications on non-preemptive accelerators is fundamentally different than contention on multi-core CPUs and introduces a new set of challenges to reduce QoS violation. To address this open problem, we first identify the underlying causes for QoS violation in accelerator-outfitted servers. Our experiments show that queuing delay for the compute resources and PCI-e bandwidth contention for data transfer are the main two factors that contribute to the long tails of user-facing applications. We then present Baymax, a runtime system that orchestrates the execution of compute tasks from different applications and mitigates PCI-e bandwidth contention to deliver the required QoS for user-facing applications and increase the accelerator utilization. Using DjiNN, a deep neural network service, Sirius, an end-to-end IPA workload, and traditional applications on a Nvidia K40 GPU, our evaluation shows that Baymax improves the accelerator utilization by 91.3% while achieving the desired 99%-ile latency target for for user-facing applications. In fact, Baymax reduces the 99%-ile latency of user-facing applications by up to 195x over default execution.
CSR
Authors: Shalev Noam , Harpaz Eran , Porat Hagar , Keidar Idit , Weinsberg Yaron
Published: July 2016

One of the adverse effects of shrinking transistor sizes is that processors have become increasingly prone to hardware faults. At the same time, the number of cores per die rises. Consequently, core failures can no longer be ruled out, and future operating systems for many-core machines will have to incorporate fault tolerance mechanisms.

We present CSR, a strategy for recovery from unexpected permanent processor faults in commodity operating systems. Our approach overcomes surprise removal of faulty cores, and also tolerates cascading core failures. When a core fails in user mode, CSR terminates the process executing on that core and migrates the remaining processes in its run-queue to other cores. We further show how hardware transactional memory may be used to overcome failures in critical kernel code. Our solution is scalable, incurs low overhead, and is designed to integrate into modern operating systems. We have implemented it in the Linux kernel, using Haswell's Transactional Synchronization Extension, and tested it on a real system.
TPC
Authors: Jeon Myeongjae , He Yuxiong , Kim Hwanju , Elnikety Sameh , Rixner Scott , Cox Alan L.
Published: July 2016

In interactive services such as web search, recommendations, games and finance, reducing the tail latency is crucial to provide fast response to every user. Using web search as a driving example, we systematically characterize interactive workload to identify the opportunities and challenges for reducing tail latency. We find that the workload consists of mainly short requests that do not benefit from parallelism, and a few long requests which significantly impact the tail but exhibit high parallelism speedup. This motivates estimating request execution time, using a predictor, to identify long requests and to parallelize them. Prediction, however, is not perfect; a long request mispredicted as short is likely to contribute to the server tail latency, setting a ceiling on the achievable tail latency. We propose TPC, an approach that combines prediction information judiciously with dynamic correction for inaccurate prediction. Dynamic correction increases parallelism to accelerate a long request that is mispredicted as short. TPC carefully selects the appropriate target latencies based on system load and parallelism efficiency to reduce tail latency.

We implement TPC and several prior approaches to compare them experimentally on a single search server and on a cluster of 40 search servers. The experimental results show that TPC reduces the 99th- and 99.9th-percentile latency by up to 40% compared with the best prior work. Moreover, we evaluate TPC on a finance server, demonstrating its effectiveness on reducing tail latency of interactive services beyond web search.
M3
Authors: Asmussen Nils , Völp Marcus , Nöthen Benedikt , Härtig Hermann , Fettweis Gerhard
Published: July 2016

In the last decade, the number of available cores increased and heterogeneity grew. In this work, we ask the question whether the design of the current operating systems (OSes) is still appropriate if these trends continue and lead to abundantly available but heterogeneous cores, or whether it forces a fundamental rethinking of how systems are designed. We argue that: 1. hiding heterogeneity behind a common hardware interface unifies, to a large extent, the control and coordination of cores and accelerators in the OS, 2. isolating at the network-on-chip rather than with processor features (like privileged mode, memory management unit, ...), allows running untrusted code on arbitrary cores, and 3. providing OS services via protocols over the network-on-chip, instead of via system calls, makes them accessible to arbitrary types of cores as well.

In summary, this turns accelerators into first-class citizens and enables a single and convenient programming environment for all cores without the need to trust any application.

In this paper, we introduce network-on-chip-level isolation, present the design of our microkernel-based OS, M3, and the common hardware interface, and evaluate the performance of our prototype in comparison to Linux. A bit surprising, without using accelerators, M3 outperforms Linux in some application-level benchmarks by more than a factor of five.
Sego
Authors: Kwon Youngjin , Dunn Alan M. , Lee Michael Z. , Hofmann Owen S. , Xu Yuanzhong , Witchel Emmett
Published: July 2016

Sego is a hypervisor-based system that gives strong privacy and integrity guarantees to trusted applications, even when the guest operating system is compromised or hostile. Sego verifies operating system services, like the file system, instead of replacing them. By associating trusted metadata with user data across all system devices, Sego verifies system services more efficiently than previous systems, especially services that depend on data contents. We extensively evaluate Sego's performance on real workloads and implement a kernel fault injector to validate Sego's file system-agnostic crash consistency and recovery protocol.
DySel
Authors: Chang Li-Wen , Kim Hee-Seok , Hwu Wen-mei W.
Published: July 2016

The rising pressure for simultaneously improving performance and reducing power is driving more diversity into all aspects of computing devices. An algorithm that is well-matched to the target hardware can run multiple times faster and more energy efficiently than one that is not. The problem is complicated by the fact that a program's input also affects the appropriate choice of algorithm. As a result, software developers have been faced with the challenge of determining the appropriate algorithm for each potential combination of target device and data. This paper presents DySel, a novel runtime system for automating such determination for kernel-based data parallel programming models such as OpenCL, CUDA, OpenACC, and C++AMP. These programming models cover many applications that demand high performance in mobile, cloud and high-performance computing. DySel systematically deploys candidate kernels on a small portion of the actual data to determine which achieves the best performance for the hardware-data combination. The test-deployment, referred to as micro-profiling, contributes to the final execution result and incurs less than 8% of overhead in the worst observed case when compared to an oracle. We show four major use cases where DySel provides significantly more consistent performance without tedious effort from the developer.
TaxDC
Authors: Leesatapornwongsa Tanakorn , Lukman Jeffrey F. , Lu Shan , Gunawi Haryadi S.
Published: July 2016

We present TaxDC, the largest and most comprehensive taxonomy of non-deterministic concurrency bugs in distributed systems. We study 104 distributed concurrency (DC) bugs from four widely-deployed cloud-scale datacenter distributed systems, Cassandra, Hadoop MapReduce, HBase and ZooKeeper. We study DC-bug characteristics along several axes of analysis such as the triggering timing condition and input preconditions, error and failure symptoms, and fix strategies, collectively stored as 2,083 classification labels in TaxDC database. We discuss how our study can open up many new research directions in combating DC bugs.
AxGames
Authors: Park Jongse , Amaro Emmanuel , Mahajan Divya , Thwaites Bradley , Esmaeilzadeh Hadi
Published: July 2016

Approximate computing trades quality of application output for higher efficiency and performance. Approximation is useful only if its impact on application output quality is acceptable to the users. However, there is a lack of systematic solutions and studies that explore users' perspective on the effects of approximation. In this paper, we seek to provide one such solution for the developers to probe and discover the boundary of quality loss that most users will deem acceptable. We propose AxGames, a crowdsourced solution that enables developers to readily infer a statistical common ground from the general public through three entertaining games. The users engage in these games by betting on their opinion about the quality loss of the final output while the AxGames framework collects statistics about their perceptions. The framework then statistically analyzes the results to determine the acceptable levels of quality for a pair of (application, approximation technique). The three games are designed such that they effectively capture quality requirements with various tradeoffs and contexts. To evaluate AxGames, we examine seven diverse applications that produce user perceptible outputs and cover a wide range of domains, including image processing, optical character recognition, speech to text conversion, and audio processing. We recruit 700 participants/users through Amazon's Mechanical Turk to play the games that collect statistics about their perception on different levels of quality. Subsequently, the AxGames framework uses the Clopper-Pearson exact method, which computes a binomial proportion confidence interval, to analyze the collected statistics for each level of quality. Using this analysis, AxGames can statistically project the quality level that satisfies a given percentage of users. The developers can use these statistical projections to tune the level of approximation based on the user experience. We find that the level of acceptable quality loss significantly varies across applications. For instance, to satisfy 90% of users, the level of acceptable quality loss is 2% for one application (image processing) and 26% for another (audio processing). Moreover, the pattern with which the crowd responds to approximation takes significantly different shape and form depending on the class of applications. These results confirm the necessity of solutions that systematically explore the effect of approximation on the end user experience.
High-Performance Transactions for Persistent Memories
Authors: Kolli Aasheesh , Pelley Steven , Saidi Ali , Chen Peter M. , Wenisch Thomas F.
Published: July 2016

Emerging non-volatile memory (NVRAM) technologies offer the durability of disk with the byte-addressability of DRAM. These devices will allow software to access persistent data structures directly in NVRAM using processor loads and stores, however, ensuring consistency of persistent data across power failures and crashes is difficult. Atomic, durable transactions are a widely used abstraction to enforce such consistency. Implementing transactions on NVRAM requires the ability to constrain the order of NVRAM writes, for example, to ensure that a transaction's log record is complete before it is marked committed. Since NVRAM write latencies are expected to be high, minimizing these ordering constraints is critical for achieving high performance. Recent work has proposed programming interfaces to express NVRAM write ordering constraints to hardware so that NVRAM writes may be coalesced and reordered while preserving necessary constraints. Unfortunately, a straightforward implementation of transactions under these interfaces imposes unnecessary constraints. We show how to remove these dependencies through a variety of techniques, notably, deferring commit until after locks are released. We present a comprehensive analysis contrasting two transaction designs across three NVRAM programming interfaces, demonstrating up to 2.5x speedup.
ReBudget
Authors: Wang Xiaodong , Martínez José F.
Published: July 2016

Efficiently allocating shared resources in computer systems is critical to optimizing execution. Recently, a number of market-based solutions have been proposed to attack this problem. Some of them provide provable theoretical bounds to efficiency and/or fairness losses under market equilibrium. However, they are limited to markets with potentially important constraints, such as enforcing equal budget for all players, or curve-fitting players' utility into a specific function type. Moreover, they do not generally provide an intuitive "knob" to control efficiency vs. fairness. In this paper, we introduce two new metrics, Market Utility Range (MUR) and Market Budget Range (MBR), through which we provide for the first time theoretical bounds on efficiency and fairness of market equilibria under
arbitrary
budget assignments. We leverage this result and propose
ReBudget
, an iterative budget re-assignment algorithm that can be used to control efficiency vs. fairness at run-time. We apply our algorithm to a multi-resource allocation problem in multicore chips. Our evaluation using detailed execution-driven simulations shows that our budget re-assignment technique is intuitive, effective, and efficient.
TxRace
Authors: Zhang Tong , Lee Dongyoon , Jung Changhee
Published: July 2016

Detecting data races is important for debugging shared-memory multithreaded programs, but the high runtime overhead prevents the wide use of dynamic data race detectors. This paper presents TxRace, a new software data race detector that leverages commodity hardware transactional memory (HTM) to speed up data race detection. TxRace instruments a multithreaded program to transform synchronization-free regions into transactions, and exploits the conflict detection mechanism of HTM for lightweight data race detection at runtime. However, the limitations of the current best-effort commodity HTMs expose several challenges in using them for data race detection: (1) lack of ability to pinpoint racy instructions, (2) false positives caused by cache line granularity of conflict detection, and (3) transactional aborts for non-conflict reasons (e.g., capacity or unknown). To overcome these challenges, TxRace performs lightweight HTM-based data race detection at first, and occasionally switches to slow yet precise data race detection only for the small fraction of execution intervals in which potential races are reported by HTM. According to the experimental results, TxRace reduces the average runtime overhead of dynamic data race detection from 11.68x to 4.65x with only a small number of false negatives.
ProteusTM
Authors: Didona Diego , Diegues Nuno , Kermarrec Anne-Marie , Guerraoui Rachid , Neves Ricardo , Romano Paolo
Published: July 2016

The Transactional Memory (TM) paradigm promises to greatly simplify the development of concurrent applications. This led, over the years, to the creation of a plethora of TM implementations delivering wide ranges of performance across workloads. Yet, no universal implementation fits each and every workload. In fact, the best TM in a given workload can reveal to be disastrous for another one. This forces developers to face the complex task of tuning TM implementations, which significantly hampers their wide adoption. In this paper, we address the challenge of automatically identifying the best TM implementation for a given workload. Our proposed system, ProteusTM, hides behind the TM interface a large library of implementations. Underneath, it leverages a novel multi-dimensional online optimization scheme, combining two popular learning techniques: Collaborative Filtering and Bayesian Optimization.

We integrated ProteusTM in GCC and demonstrate its ability to switch between TMs and adapt several configuration parameters (e.g., number of threads). We extensively evaluated ProteusTM, obtaining average performance <3% from optimal, and gains up to 100x over static alternatives.
Scaling up Superoptimization
Authors: Phothilimthana Phitchaya Mangpo , Thakur Aditya , Bodik Rastislav , Dhurjati Dinakar
Published: July 2016

Developing a code optimizer is challenging, especially for new, idiosyncratic ISAs. Superoptimization can, in principle, discover machine-specific optimizations automatically by searching the space of all instruction sequences. If we can increase the size of code fragments a superoptimizer can optimize, we will be able to discover more optimizations. We develop LENS, a search algorithm that increases the size of code a superoptimizer can synthesize by rapidly pruning away invalid candidate programs. Pruning is achieved by selectively refining the abstraction under which candidates are considered equivalent, only in the promising part of the candidate space. LENS also uses a bidirectional search strategy to prune the candidate space from both forward and backward directions. These pruning strategies allow LENS to solve twice as many benchmarks as existing enumerative search algorithms, while LENS is about 11-times faster.

Additionally, we increase the effective size of the superoptimized fragments by relaxing the correctness condition using contexts (surrounding code). Finally, we combine LENS with complementary search techniques into a cooperative superoptimizer, which exploits the stochastic search to make random jumps in a large candidate space, and a symbolic (SAT-solver-based) search to synthesize arbitrary constants. While existing superoptimizers consistently solve 9--16 out of 32 benchmarks, the cooperative superoptimizer solves 29 benchmarks. It can synthesize code fragments that are up to 82% faster than code generated by gcc -O3 from WiBench and MiBench.
RID
Authors: Mao Junjie , Chen Yu , Xiao Qixue , Shi Yuanchun
Published: July 2016

Reference counts are widely used in OS kernels for resource management. However, reference counts are not trivial to be used correctly in large scale programs because it is left to developers to make sure that an increment to a reference count is always paired with a decrement. This paper proposes inconsistent path pair checking, a novel technique that can statically discover bugs related to reference counts without knowing how reference counts should be changed in a function. A prototype called RID is implemented and evaluations show that RID can discover more than 80 bugs which were confirmed by the developers in the latest Linux kernel. The results also show that RID tends to reveal bugs caused by developers' misunderstanding on API specifications or error conditions that are not handled properly.
Scalable Kernel TCP Design and Implementation for Short-Lived Connections
Authors: Lin Xiaofeng , Chen Yu , Li Xiaodong , Mao Junjie , He Jiaquan , Xu Wei , Shi Yuanchun
Published: July 2016

With the rapid growth of network bandwidth, increases in CPU cores on a single machine, and application API models demanding more short-lived connections, a scalable TCP stack is performance-critical. Although many clean-state designs have been proposed, production environments still call for a bottom-up parallel TCP stack design that is backward-compatible with existing applications.

We present Fastsocket, a BSD Socket-compatible and scalable kernel socket design, which achieves table-level connection partition in TCP stack and guarantees connection locality for both passive and active connections. Fastsocket architecture is a ground up partition design, from NIC interrupts all the way up to applications, which naturally eliminates various lock contentions in the entire stack. Moreover, Fastsocket maintains the full functionality of the kernel TCP stack and BSD-socket-compatible API, and thus applications need no modifications.

Our evaluations show that Fastsocket achieves a speedup of 20.4x on a 24-core machine under a workload of short-lived connections, outperforming the state-of-the-art Linux kernel TCP implementations. When scaling up to 24 CPU cores, Fastsocket increases the throughput of Nginx and HAProxy by 267% and 621% respectively compared with the base Linux kernel. We also demonstrate that Fastsocket can achieve scalability and preserve BSD socket API at the same time. Fastsocket is already deployed in the production environment of Sina WeiBo, serving 50 million daily active users and billions of requests per day.
NVWAL
Authors: Kim Wook-Hee , Kim Jinwoong , Baek Woongki , Nam Beomseok , Won Youjip
Published: July 2016

Emerging byte-addressable non-volatile memory is considered an alternative storage device for database logs that require persistency and high performance. In this work, we develop NVWAL (NVRAM Write-Ahead Logging) for SQLite. The contribution of NVWAL consists of three elements: (i) byte-granularity differential logging that effectively eliminates the excessive I/O overhead of filesystem-based logging or journaling, (ii) transaction-aware lazy synchronization that reduces cache synchronization overhead by two-thirds, and (iii) user-level heap management of the NVRAM persistent WAL structure, which reduces the overhead of managing persistent objects.

We implemented NVWAL in SQLite and measured the performance on a Nexus 5 smartphone and an NVRAM emulation board - Tuna. Our performance study shows the following: (i) the overhead of enforcing strict ordering of NVRAM writes can be reduced via NVRAM-aware transaction management. (ii) From the application performance point of view, the overhead of guaranteeing failure atomicity is negligible; the cache line flush overhead accounts for only 0.8~4.6% of transaction execution time. Therefore, application performance is much less sensitive to the NVRAM performance than we expected. Decreasing the NVRAM latency by one-fifth (from 1942 nsec to 437 nsec), SQLite achieves a mere 4% performance gain (from 2517 ins/sec to 2621 ins/sec). (iii) Overall, when the write latency of NVRAM is 2 usec, NVWAL increases SQLite performance by at least 10x compared to that of WAL on flash memory (from 541 ins/sec to 5812 ins/sec).
RAPID Programming of Pattern-Recognition Processors
Authors: Angstadt Kevin , Weimer Westley , Skadron Kevin
Published: July 2016

We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct execution of non-deterministic finite automata (NFAs), and has been demonstrated to provide substantial speedup for a variety of data-processing applications. RAPID is clear, maintainable, concise, and efficient both at compile and run time. Language features, such as code abstraction and parallel control structures, map well to pattern-matching problems, providing clarity and maintainability. For generation of efficient runtime code, we present algorithms to convert RAPID programs into finite automata. Further, we introduce a tessellation technique for configuring the AP, which significantly reduces compile time, increases programmer productivity, and improves maintainability. We evaluate five RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by the AP. We find that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact. In addition, our tessellation technique for configuring the AP has comparable device utilization to, and results in compilation that is up to four orders of magnitude faster than, current solutions.
COATCheck
Authors: Lustig Daniel , Sethi Geet , Martonosi Margaret , Bhattacharjee Abhishek
Published: July 2016

Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck, an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.
CASPAR
Authors: Gangwani Tanmay , Morrison Adam , Torrellas Josep
Published: July 2016

In multicores, performance-critical synchronization is increasingly performed in a
lock-free
manner using atomic instructions such as CAS or LL/SC. However, when many processors synchronize on the same variable, performance can still degrade significantly. Contending writes get serialized, creating a non-scalable condition. Past proposals that build hardware queues of synchronizing processors do not fundamentally solve this problem---at best, they help to
efficiently serialize
the contending writes.

This paper proposes a novel architecture that
breaks
the serialization of hardware queues and enables the queued processors to perform lock-free synchronization
in parallel
. The architecture, called
CASPAR
, is able to (1) execute the CASes in the queued-up processors in parallel through eager forwarding of expected values, and (2) validate the CASes in parallel and dequeue groups of processors at a time. The result is highly-scalable synchronization. We evaluate CASPAR with simulations of a 64-core chip. Compared to existing proposals with hardware queues, CASPAR improves the throughput of kernels by 32% on average, and reduces the execution time of the sections considered in lock-free versions of applications by 47% on average. This makes these sections 2.5x faster than in the original applications.
Proactive Control of Approximate Programs
Authors: Sui Xin , Lenharth Andrew , Fussell Donald S. , Pingali Keshav
Published: July 2016

Approximate computing trades off accuracy of results for resources such as energy or computing time. There is a large and rapidly growing literature on approximate computing that has focused mostly on showing the benefits of approximate computing. However, we know relatively little about how to control approximation in a disciplined way. In this paper, we address the problem of controlling approximation for non-streaming programs that have a set of "knobs" that can be dialed up or down to control the level of approximation of different components in the program. We formulate this control problem as a constrained optimization problem, and describe a system called Capri that uses machine learning to learn cost and error models for the program, and uses these models to determine, for a desired level of approximation, knob settings that optimize metrics such as running time or energy usage. Experimental results with complex benchmarks from different problem domains demonstrate the effectiveness of this approach.
Cogent
Authors: Amani Sidney , Hixon Alex , Chen Zilin , Rizkallah Christine , Chubb Peter , O'Connor Liam , Beeren Joel , Nagashima Yutaka , Lim Japheth , Sewell Thomas , Tuong Joseph , Keller Gabriele , Murray Toby , Klein Gerwin , Heiser Gernot
Published: July 2016

We present an approach to writing and formally verifying high-assurance file-system code in a restricted language called Cogent, supported by a certifying compiler that produces C code, high-level specification of Cogent, and translation correctness proofs. The language is strongly typed and guarantees absence of a number of common file system implementation errors. We show how verification effort is drastically reduced for proving higher-level properties of the file system implementation by reasoning about the generated formal specification rather than its low-level C code. We use the framework to write two Linux file systems, and compare their performance with their native C implementations.
Specifying and Checking File System Crash-Consistency Models
Authors: Bornholt James , Kaufmann Antoine , Li Jialin , Krishnamurthy Arvind , Torlak Emina , Wang Xi
Published: July 2016

Applications depend on persistent storage to recover state after system crashes. But the POSIX file system interfaces do not define the possible outcomes of a crash. As a result, it is difficult for application writers to correctly understand the ordering of and dependencies between file system operations, which can lead to corrupt application state and, in the worst case, catastrophic data loss. This paper presents crash-consistency models, analogous to memory consistency models, which describe the behavior of a file system across crashes. Crash-consistency models include both litmus tests, which demonstrate allowed and forbidden behaviors, and axiomatic and operational specifications. We present a formal framework for developing crash-consistency models, and a toolkit, called Ferrite, for validating those models against real file system implementations. We develop a crash-consistency model for ext4, and use Ferrite to demonstrate unintuitive crash behaviors of the ext4 implementation. To demonstrate the utility of crash-consistency models to application writers, we use our models to prototype proof-of-concept verification and synthesis tools, as well as new library interfaces for crash-safe applications.
Architecture-Adaptive Code Variant Tuning
Authors: Muralidharan Saurav , Roy Amit , Hall Mary , Garland Michael , Rai Piyush
Published: July 2016

Code variants represent alternative implementations of a computation, and are common in high-performance libraries and applications to facilitate selecting the most appropriate implementation for a specific execution context (target architecture and input dataset). Automating code variant selection typically relies on machine learning to construct a model during an offline learning phase that can be quickly queried at runtime once the execution context is known. In this paper, we define a new approach called architecture-adaptive code variant tuning, where the variant selection model is learned on a set of source architectures, and then used to predict variants on a new target architecture without having to repeat the training process. We pose this as a multi-task learning problem, where each source architecture corresponds to a task; we use device features in the construction of the variant selection model. This work explores the effectiveness of multi-task learning and the impact of different strategies for device feature selection. We evaluate our approach on a set of benchmarks and a collection of six NVIDIA GPU architectures from three distinct generations. We achieve performance results that are mostly comparable to the previous approach of tuning for a single GPU architecture without having to repeat the learning phase.
Generating Configurable Hardware from Parallel Patterns
Authors: Prabhakar Raghu , Koeplinger David , Brown Kevin J. , Lee HyoukJoong , De Sa Christopher , Kozyrakis Christos , Olukotun Kunle
Published: July 2016

In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and energy improvements over CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two important optimizations for using parallel patterns to generate efficient hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 39.4× on a set of benchmarks from the data analytics domain.
Identification of food-grade subtilisins as gluten-degrading enzymes to treat celiac disease
Authors: Wei Guoxian , Tian Na , Siezen Roland , Schuppan Detlef , Helmerhorst Eva J.
Published: July 2016

Gluten are proline- and glutamine-rich proteins present in wheat, barley, and rye and contain the immunogenic sequences that drive celiac disease (CD). Rothia mucilaginosa, an oral microbial colonizer, can cleave these gluten epitopes. The aim was to isolate and identify the enzymes and evaluate their potential as novel enzyme therapeutics for CD. The membrane-associated R. mucilaginosa proteins were extracted and separated by DEAE chromatography. Enzyme activities were monitored with paranitroanilide-derivatized and fluorescence resonance energy transfer (FRET) peptide substrates, and by gliadin zymography. Epitope elimination was determined in R5 and G12 ELISAs. The gliadin-degrading Rothia enzymes were identified by LC-ESI-MS/MS as hypothetical proteins ROTMU0001_0241 (C6R5V9_9MICC), ROTMU0001_0243 (C6R5W1_9MICC), and ROTMU0001_240 (C6R5V8_9MICC). A search with the Basic Local Alignment Search Tool revealed that these are subtilisin-like serine proteases belonging to the peptidase S8 family. Alignment of the major Rothia subtilisins indicated that all contain the catalytic triad with Asp (D), His (H), and Ser (S) in the D-H-S order. They cleaved succinyl-Ala-Ala-Pro-Phe-paranitroanilide, a substrate for subtilisin with Pro in the P2 position, as in Tyr-Pro-Gln and Leu-Pro-Tyr in gluten, which are also cleaved. Consistently, FRET substrates of gliadin immunogenic epitopes comprising Xaa-Pro-Xaa motives were rapidly hydrolyzed. The Rothia subtilisins and two subtilisins from Bacillus licheniformis, subtilisin A and the food-grade Nattokinase, efficiently degraded the immunogenic gliadin-derived 33-mer peptide and the immunodominant epitopes recognized by the R5 and G12 antibodies. This study identified Rothia and food-grade Bacillus subtilisins as promising new candidates for enzyme therapeutics in CD.
Opioidergic effects on enteric and sensory nerves in the lower GI tract: basic mechanisms and clinical implications
Authors: Hughes Patrick A. , Costello Samuel P. , Bryant Robert V. , Andrews Jane M.
Published: July 2016

Opioids are one of the most prescribed drug classes for treating acute pain. However, chronic use is often associated with tolerance as well as debilitating side effects, including nausea and dependence, which are mediated by the central nervous system, as well as constipation emerging from effects on the enteric nervous system. These gastrointestinal (GI) side effects limit the usefulness of opioids in treating pain in many patients. Understanding the mechanism(s) of action of opioids on the nervous system that shows clinical benefit as well as those that have unwanted effects is critical for the improvement of opioid drugs. The opioidergic system comprises three classical receptors (μ, δ, κ) and a nonclassical receptor (nociceptin), and each of these receptors is expressed to varying extents by the enteric and intestinal extrinsic sensory afferent nerves. The purpose of this review is to discuss the role that the opioidergic system has on enteric and extrinsic afferent nerves in the lower GI tract in health and diseases of the lower GI tract, particularly inflammatory bowel disease and irritable bowel syndrome, and the implications of opioid treatment on clinical outcomes. Consideration is also given to emerging developments in our understanding of the immune system as a novel source of endogenous opioids and the mechanisms underlying opioid tolerance, including the potential influence of opioid receptor splice variants and heteromeric complexes.
The role of Nrf2 in skeletal muscle contractile and mitochondrial function
Authors: Crilly Matthew J. , Tryon Liam D. , Erlich Avigail T. , Hood David A.
Published: July 2016

Nuclear factor erythroid 2-related factor 2 (Nrf2) is a transcription factor that confers cellular protection by upregulating antioxidant enzymes in response to oxidative stress. However, Nrf2 function within skeletal muscle remains to be further elucidated. We examined the role of Nrf2 in determining muscle phenotype using young (3 mo) and older (12 mo) Nrf2 wild-type (WT) and knockout (KO) mice. Basally, the absence of Nrf2 did not impact mitochondrial content. In intermyofibrillar mitochondria, lack of Nrf2 resulted in a 40% reduction in state 4 respiration, which coincided with a 68% increase in reactive oxygen species (ROS) emission. Nrf2 abrogation impaired in situ muscle performance, characterized by a 48% greater rate of fatigue and a 35% decrease in force within the first 5 min of stimulation. Acute treadmill exercise resulted in a 1.5-fold increase in Nrf2 activation via enhanced DNA binding in WT animals. In response to training, cytochrome- c oxidase activity increased by 20% in the WT animals; however, this response was attenuated in KO mice. Nrf2 protein was reduced 30% by training. Despite this, exercise training normalized respiration, ROS production, and muscle performance in KO mice. Our results suggest that Nrf2 transcriptional activity is increased by exercise and that Nrf2 is required for the maintenance of basal mitochondrial function as well as for the normal increase in specific mitochondrial proteins in response to training. Nonetheless, the decrements in mitochondrial function in Nrf2 KO muscle can be rescued by exercise training, suggesting that this restorative function operates via a pathway independent of Nrf2.
Intermittent hypoxia induces murine macrophage foam cell formation by IKK-β-dependent NF-κB pathway activation
Authors: Imamura Toshihiro , Poulsen Orit , Haddad Gabriel G.
Published: July 2016

Obstructive sleep apnea (OSA) is a common sleep disorder characterized by intermittent hypoxia (IH). Clinical studies have previously shown that OSA is an independent risk factor for atherosclerosis. Atherogenicity in OSA patients has been assumed to be associated with the NF-κB pathways. Although foam cells are considered to be a hallmark of atherosclerosis, how IH as in OSA affects their development has not been fully understood. Therefore, we hypothesized that IH induces macrophage foam cell formation through NF-κB pathway activation. To test this hypothesis, peritoneal macrophages collected from myeloid-restricted IKK-β-deleted mice were incubated with native LDL and exposed to either IH or normoxia. After exposure, NF-κB pathway activity and intracellular cholesterol were measured. In control macrophages, IH significantly increased NF-κB pathway activity by 93% compared with normoxia ( P < 0.05). However, such response to IH was diminished by IKK-β deletion (increased by +31% compared with normoxia; P = 0.64), suggesting that IKK-β is critical for IH-induced NF-κB pathway activation. Likewise, in control macrophages, total cholesterol was increased in IH compared with normoxia (65.7 ± 3.8 μg/mg cellular protein and 53.2 ± 1.2, respectively; P < 0.05). However, this IH-induced foam cell formation was disappeared when IKK-β was deleted (52.2 ± 1.2 μg/mg cellular protein for IH and 46.3 ± 1.7 for normoxia; P = 0.55). This IH-mediated effect still existed in macrophages without LDL receptor. Taken together, our findings show that IH activates the IKK-β-dependent NF-κB pathway and that this, in turn, induces foam cell formation in murine macrophages.
Membrane progesterone receptor-β, but not -α, in dorsal brain stem establishes sex-specific chemoreflex responses and reduces apnea frequency in adult mice
Authors: Boukari Ryma , Rossignol Orlane , Baldy Cécile , Marcouiller François , Bairam Aida , Joseph Vincent
Published: July 2016

We tested the hypothesis that membrane progesterone receptors (mPR) contribute to respiratory control in adult male and female mice. Mice were implanted with osmotic minipumps for continuous infusion of small interfering RNA (siRNA) directed against mPRα, mPRβ, or a control solution in the fourth ventricle (to target brain stem respiratory areas) for 14 days. We then performed respiratory and metabolic recordings by whole body plethysmography at rest and in response to hypoxia (12% O2) or hypercapnia (5% CO2, 5 min each). For each treatment, we have verified with immunohistochemistry that the staining intensity of mPRα or mPRβ in the brain stem is decreased. At rest, the siRNA against mPRα and mPRβ increased respiratory frequency in males only. The siRNA against mPRβ almost tripled the frequency of apneas in male and in female mice, while the siRNA against mPRα had no effect. Regarding respiratory chemoreflex, the siRNA against mPRβ suppressed the response to hypoxia in male and female mice and reduced by ∼50% the response to hypercapnia, while the siRNA against mPRα had more limited effects. Interestingly, control females had higher ventilatory response to hypoxia and hypercapnia than males, and these sex-specific effects were suppressed by the siRNA against mPRβ, whereas they were still present after treatment with the siRNA against mPRα. We conclude that mPRβ reduces apnea frequency in male and female mice and establishes sex-specific ventilatory chemoreflex.