Pinch Off Plasma Chemical Vapor Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation
Authors: Nguyen Son van , Haigh Thomas J , Cheng Kangguo , Penny C. , Park Chanro , Mehta Sanjay C , Yamashita Tenko , Jiang Liying , Canaperi Don 
Published: February 2020

EXTENDED ABSTRACT

Continued integrated circuit scaling deeper into the nanoscale regime has provided improved performance through shrinking of the Front-End-of-Line (FEOL) device and Back-End-of-Line (BEOL) interconnect. With scaling, resistance-capacitance (RC) delay is an increasing challenge, limiting overall product performance. Capacitance reduction is therefore vitally important for device performance in both the FEOL and BEOL device structure. Conventional capacitance reduction methods for FEOL and BEOL while maintaining yield and reliability have required significant material innovations such lower-k cap and bulk dielectrics with required mechanical, structural, electrical and other properties. To improve capacitance, other innovations in device structure and process integration such as Air Gap and Air Spacer are also needed (1-2). The air spacer (FEOL) and air gap (BEOL) structures require novel process technology approaches such as pinch off deposition to optimize the capacitance reduction while maintaining yield and reliability.

In this paper, we present an overview of material and process technology requirements for FEOL air spacer (1) and BEOL air gap (2) formation using a pinch off deposition approach. These approaches utilize established dielectric materials and processes such as Plasma CVD of SiN, SiCN, SiCOH, pSiCOH, in the formation of the air spacer/air gap. The selection of these dielectric materials and processes has a large impact in the void (gap) dimension and volume as typically show in figure 1. The void dimension and volume in airgap structures can be controlled with various dielectric deposition processes and materials as shown in Figure 1: (a) Long and wide voids for optimal capacitance reduction. (b) Short and wide voids for improved process fabrication and integration. (c) Short and narrow voids for better sidewall protection and device reliability but with a smaller capacitance reduction. The overall void dimension and type of dielectric material are strongly related to the total device capacitance reduction and reliability. Significant capacitance reduction with good reliability has been achieved through material, process and structural/architectural optimization with the pinch off deposition process approach on current 10 nm device structures as shown in figure 2 (FEOL Air spacer) and figure 3 (BEOL Air Gap).

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities

References

1) K. Cheng, S. Nguyen et al. International Electron Device Meeting, Proceeding Vol. 2016, paper 17.1, pp.444-447. San Francisco, USA

2) C. Penny, S. Gates, B. Peethala, J. Lee, D. Priyadarshini, S. Nguyen, P. McLaughlin, E. Liniger, C.-K. Hu, L. Clevenger, T. Hook, H. Shobha, P. Kerber, I. Seshadri, J. Chen, D. Edelstein, R. Quon, G. Bonilla, V. Paruchuri, and E. Huang, International Interconnect Technology Conference, Proceed. Volume, paper 2.2, May 16-18,2017, Taipei, Taiwan.

Figure 1