bluuebunny/crossref_metadata_2025 huggingface dataset:
DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C
Authors: Mehta Mohit R. , Neudeck Philip G. , Lawson John W.
Published: May 2022

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n−and extended n+) to reduce the SiC JFET channel length while maintaining the turn-off behavior needed to realize 500°C circuit operation. COMSOL Multiphysics was used to simulate the transfer characteristics and maximum potential below the gate of a 4H-SiC nJFET at 500°C, and a 1 μm gate length nJFET with turn-off performance comparable to the state-of-the-art is suggested.
Surface Potential Fluctuations of SiO2/SiC Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy
Authors: Yamasue Kohei , Cho Yasuo
Published: May 2022

We investigate surface potential fluctuations on SiO2/SiC interfaces by local capacitance-voltage profiling based on time-resolved scanning nonlinear dielectric microscopy. As experimental indicators of surface potential fluctuations, we measured the spatial fluctuations of local capacitance-voltage and its first derivative profiles through the detection of the voltages at the infection points of the profiles. We show that, even for a sample with a nitrided interface with low interface defect density, the fluctuations of the measured voltages are much higher than the thermal energy at room temperature. This indicates the existence of high potential fluctuations, which can give the significant impacts on the carrier transport at the SiO2/SiC interface of SiC metal-oxide-semiconductor field effect transistors.
SiC MOSFET C-V Characteristics with Positive Biased Drain
Authors: Matacena Ilaria , Maresca Luca , Riccio Michele , Irace Andrea , Breglio Giovanni , Daliento Santolo , Castellazzi Alberto
Published: May 2022

Even if SiC MOSFETs technology has undergone huge progress in last years, there are some issues still open, such as high traps density at the SiO2/SiC interface. This work focuses on the measurement of the Gate capacitance when a DC bias is applied between Drain and Source to characterize the SiO2/SiC interface. The experimental curves, performed on a commercial SiC power MOSFET, exhibit a peak when the Gate voltage approaches the threshold voltage. Such peak is analyzed through TCAD simulations and its origin is addressed. Numerical analysis shows that this peak is associated to the displacement current, with a strong dependence on the traps concentration at the SiO2/SiC interface.
AlGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications
Authors: Lesecq Marie , Frayssinet Eric , Portail Marc , Bah Micka , Defrance Nicolas , Ngo Thi Huong , Abou Daher Mahmoud , Zielinski Marcin , Alquier Daniel , De Jaeger Jean-Claude , Cordier Yvon
Published: May 2022

In this work, an AlGaN/GaN HEMT structure is grown on a 0.8 μm thick 3C-SiC layer on high resistivity Silicon substrate. The RF propagation losses are investigated and compared with the ones of epi-layers grown directly on Silicon and on 6H-SiC substrates. Short gate length transistors are fabricated using e-beam lithography. In spite of ohmic contact resistance of 0.6 Ω.mm, a saturated current density of 0.7 A/mm at a gate bias of +1V and a transconductance peak higher to 250 mS/mm for 75 nm T-shaped gate transistors are reached on structure with thick 3C-SiC template. Moreover, for the first time, transition frequencies fT/fmax of 60/98 GHz are reported on such 3C-SiC template.
Measurement of Dislocation Density in SiC Wafers Using Production XRT
Authors: Soukhojak Andrey , Stannard Tyler , Manning Ian , Lee Charles , Chung Gil , Gave Matthew , Sanchez Edward
Published: May 2022

X-ray topography (XRT) presents itself as an attractive non-destructive method to replace industry-standard destructive KOH etching used to measure dislocation density. However, a production-line-compatible XRT has to employ a low scan speed in order to work well with automated image analysis, which makes it impractical for a high-volume manufacturing to scan an entire wafer. We introduce the “radial band” approach to sampling the entire wafer’s area with a single-pass 16 mm tall scan band. Such a band spans the entire range of radii and thus captures the typically strong radial dependence of dislocation density over the entire range, while mostly ignoring the typically weak angular dependence of dislocation density and averaging the inevitable noise over the 16 mm band height. The XRT scan time savings for this approach are roughly 15-fold and 20-fold for 150mm and 200mm wafers respectively.
Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs
Authors: Torky Mohamed , Chow T. Paul
Published: May 2022

We evaluate and compare the static and dynamic performances of four different 4H-SiC power MOSFETs (Conventional DMOS and UMOS, Superjunction (SJ) DMOS and UMOS FETs) from 0.6 to 10kV. The static on-state performance is determined by analytically calculating the specific on-resistance (RON,sp), while the dynamic switching performance is determined by extracting the specific gate charge (QG,sp) and switching energy loss per cycle (Esw,cycle) using 2D device simulations. It has been found that the SJ UMOS FET exhibits at least a 31% (up to 53% at 0.6kV) reduction in the RON,sp · QG,sp Figure-of-Merit (FoM) compared to the SJ DMOS FET within the breakdown voltage rating range studied.
Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing
Authors: Chung Gil , Manning Ian , Soukhojak Andrey , Gave Matthew , Lee Charles
Published: May 2022

Post-growth thermal processing at higher temperature generates more BPDs (basal plane dislocations). It is observed that dislocation visibility in surface inspection tool images varies significantly even at comparable dislocation densities. Combination of dislocation decoration and light absorbance from SiC matrix by point defects or dopants has been proposed as a working hypothesis to explain dislocation visibility variations.
Temperature Dependence of On-State Inter-Terminal Capacitances (Cgd and Cgs) of SiC MOSFETs and Frequency Limitations of their Measurements
Authors: Tsibizov Alexander , Stark Roger , Grossner Ulrike
Published: May 2022

Inter-terminal capacitances (ITCs) have major influence on the dynamic performance of power SiC MOSFETs. Knowledge of the exact values for the ITCs is required in order to perform accurate and predictive compact model simulations of their dynamic performance. Since commercial SiC MOSFETs are capable of operating in a wide range of temperatures, it is important to know the values of ITCs in the whole temperature range of operation. Direct measurements of the ITCs with standard equipment is possible only at low current levels (i.e. in the off-state (Vgs < Vth) for Vds > 0 V), however their values in the on-state (Vgs>Vth) also influence the MOSFETs switching performance. In this work, ITCs of a planar SiC MOSFET in the on-state are studied by the means of a calibrated TCAD model, revealing substantial temperature dependence in the range of 300-450 K. In the first approximation, this temperature dependence of the ITCs can be explained by a weaker temperature dependence of the MOSFET channel resistance in comparison to its JFET and epitaxial layer resistances. In addition, it is shown that at high frequencies stray inductances of the TO-247-3 package result in a change of the extracted values of the on-state ITCs. This effect is already notable at 1 MHz.
Localized Lifetime Control of 10 kV 4H-SiC PiN Diodes by MeV Proton Implantation
Authors: Yuan Zimo , Jacobs Keijo , Bakowski Mietek , Ranstad Per , Schöner Adolf , Reshanov Sergey , Kaplan Wlodek , Nee Hans Peter , Hallén Anders
Published: May 2022

In this paper, proton implantation with different combinations of MeV energies and doses from 2×109 to 1×1011 cm-2 is used to create defects in the drift region of 10 kV 4H-SiC PiN diodes to obtain a localized drop in the SRH lifetime. On-state and reverse recovery behaviors are measured to observe how MeV proton implantation influences these devices and values of reverse recovery charge Qrr are extracted. These measurements are carried out under different temperatures, showing that the reverse recovery behavior is sensitive to temperature due to the activation of incompletely ionized p-type acceptors. The results also show that increasing proton implantation energies and fluencies can have a strong effect on diodes and cause lower Qrr and switching losses, but also higher on-state voltage drop and forward conduction losses. The trade-off between static and dynamic performance is evaluated using Qrr and forward voltage drop. Higher fluencies, or energies, help to improve the turn-off performance, but at a cost of the static performance.
Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide
Authors: Pinault-Thaury Marie Amandine , Jomard François
Published: May 2022

Diamond and Silicon Carbide (SiC) are promising wide band-gap semiconductors for power electronics, SiC being more mature especially in term of large wafer size (200 mm). Nitrogen impurities are often used in both materials for different purpose: increase the diamond growth rate or induce n-type conductivity in SiC. The determination of the nitrogen content by secondary ion mass spectrometry (SIMS) is a difficult task mainly because nitrogen is an atmospheric element for which direct monitoring of N± ions give no or a weak signal. With our standard diamond SIMS conditions, we investigate 12C14N- secondary ions under cesium primary ions by applying high mass resolution settings. Nitrogen depth-profiling of diamond and SiC (multi-) layers is then possible over several micrometer thick over reasonable time analysis duration. In a simple way and without notably modifying our usual analysis process, we found a nitrogen detection limit of 2x1017 at/cm3 in diamond and 5x1015 at/cm3 in SiC.
Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding
Authors: Kollmuss Manuel , Schöler Michael , Anzalone Ruggero , Mauceri Marco , La Via Francesco , Wellmann Peter J.
Published: May 2022

One setback that hinders the breakthrough of cubic silicon carbide is the lack of suitable seeding material for sublimation growth methods such as PVT. We present the growth of large area cubic silicon carbide material, up to a diameter of 100 mm, with a sublimation growth process called close spaced PVT (CS-PVT). Freestanding 3C‑SiC seeding layers were grown by a homoepitaxial CVD process. Subsequently CS-PVT was used to grow crystals up to a thickness of 1 mm. To prevent backside sublimation a carbon containing layer was applied as protection. Due to the presence of a wafer bow as well as a rough backside of the used seeds additional effort was necessary to apply the coating. After growth no visible curvature was present independent of the grown layer thickness and sample size. Raman spectroscopy was performed on the seeds and grown crystals, showing that the overall stress level of the material was reduced by CS‑PVT.
Neutron Detection Study through Simulations with Fluka
Authors: Muoio Annamaria , Meli Alessandro , Trotta Antonio , Parisi Miriam , Meda Laura , La Via Francesco
Published: May 2022

In this work the purpose of the simulations is to optimize a new large volume Silicon Carbide (SiC) detector for 14.1 MeV neutrons. The device has an active thickness obtained by epitaxial growth and an active area of 25 mm2. In the first step of the simulations we compare SiC detector performance to Diamond and Silicon detectors, with the same geometric features. In the second step of the simulations we have found the best solution to improve the response of the detector for a fixed epitaxial layer thickness using an overlayer of aniline (C6H7N).
Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress
Authors: Yamashiro Yusuke , Okada Masakazu , Baba Masakazu , Tanaka Takanori , Tomohisa Shingo , Watanabe Hiroshi , Kojima Kazutoshi , Harada Shinsuke , Yamaguchi Hiroshi
Published: May 2022

We evaluated stacking faults expanding by body diode current stress in the SiC Semi-SJ MOSFET for the first time. It was found that body diode degradation of the SJ MOSFETs tends to be smaller than that of conventional Non-SJ MOSFETs. Detailed crystal evaluations revealed that the stacking faults did not expand into the SJ structure. It is assumed that the expansion stops due to low carrier densities. The result suggests that the SJ device has a high potential as a device for suppressing the body diode degradation.
Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers
Authors: Grieseler Rolf , Gallino Isabella , Duboiskaya Natallia , Döll Joachim , Shekhawat Deepshikha , Reiprich Johannes , Guerra Jorge A. , Hopfeld Marcus , Honig Hauke L. , Schaaf Peter , Pezoldt Joerg
Published: May 2022

An alternative low thermal budget silicon carbide syntheses route is presented. The method is based on self-propagating high-temperature synthesis of binary silicon-carbon-based reactive mul­tilayers. With this technique, it is possible to obtain cubic polycrystalline silicon carbide at relatively low annealing temperatures by a solid state reaction. The reaction starts above 600 °C. The transformation process proceeds in a four-step process. The reaction enthalpy was determined to be (-70 ± 4) kJ/mol.
Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration
Authors: Jousseaume Yann , Cauwet François , Ferro Gabriel
Published: May 2022

In view of obtaining a step bunched morphology on large 4H-SiC surfaces, a sandwich configuration is investigated. A piece of silicon is melted between two 4H-SiC 4° off wafers, allowing a better spreading of the liquid than a Si drop approach. This successfully leads to highly step-bunched surfaces, though with irregular steps. The most regular step and terrace stuctures were found to be the result of epitaxial growth via a dissolution-precipitation process occuring from the edges to the center of the wafers. This is probably caused by radio-frequency induced electromagnetic convection within liquid Si. This process is quenched when using smaller liquid thickness.
Identification of High Resolution Transient Thermal Network Model for Power Module Packages
Authors: Fukunaga Shuhei , Funaki Tsuyoshi
Published: May 2022

A transient thermal network model is utilized to design and evaluate the transient thermal characteristics of power modules. Static test method identifies the transient thermal network model from the time response of the junction temperature, which is obtained by using the temperature dependency of I-V characteristics for power devices. This paper experimentally evaluates the effect of the sampling frequency and the resolution of the AD conversion on the accuracy of the obtained transient thermal network model. The high sampling frequency and the high resolution in the obtained time response of the junction temperature enable to clearly identify the transient thermal network model of the power module with the direct bonding copper substrate.
Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing
Authors: Calabretta Cristiano , Pecora Alessandro , Agati Marta , Privitera Stefania , Muoio Annamaria , Boninelli Simona , La Via Francesco
Published: May 2022

This paper discusses a novel annealing technique for 4H-SiC implants which involves the use of pulsed XeCl laser (l=308 nm). In particular, an absorbing graphitic coating is used to protect the sample from surface atoms desorption or phase separation. Both conventional furnace annealing and laser annealing on P and Al implants, commonly employed for source and body in metal-oxide-semiconductor field-effect transistors (MOSFETs), were examined through Transmission Electron Microscopy (TEM), u-Raman spectroscopy and Scanning Electron Microscopy (SEM). It is shown that the implant activated through traditional thermal annealing at 1650 °C for 30 min has a large network of dislocation loops, while they do not appear to be present in the laser annealed implant. Through Raman spectroscopy and SEM investigations both the crystalline quality of the laser annealed sample and the integrity of the surface were attested.
Evaluation of Line-Shape Defect in Epitaxial Wafer
Authors: Guo Ling , Shiomi Daisuke
Published: May 2022

In this study, we investigated the origin of line-shape defect in 4H-SiC epitaxial wafers. The inspection results revealed that such defects resulted from the substrate entirely and accompanied with dislocation lines during the epitaxial process. Although the defect surface condition with nanometer level of roughness seemed to do little harm to the initial electrical characteristics of power devices, dislocation lines possibly resulted in high leakage current when reverse voltage was applied. To reduce line-shape defects, it is essential to reduce defects and threading dislocations in substrates and to develop a nondestructive method for wafer screening.
Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low VF
Authors: Tian Xiao Li , Li Cheng Zhan , Yang Yu , Feng Wang , Lu Jiang , Zheng Chang Wei , Yang Cheng Yue , Bai Yun , Liu Xin Yu
Published: May 2022

The 10 kV silicon carbide p-channel insulated gate bipolar transistors (IGBTs) with low forward voltage drop (VF) have been fabricated and characterized successfully. The novel edge termination structure of Four-Region Multistep Field Limiting Rings (FRM-FLRs) and the optimum JFET region design proposed in our previous work is adopted to improve the blocking performance and the on-state characteristics. The fabricated device with a chip size of 6 mm × 6 mm and an active area of 0.16 cm2 exhibits a high blocking voltage of -10 kV with a small leakage current below -200 nA. Meanwhile, a low forward voltage drop of -8 V at the collector current of -10 A with a gate bias of -20 V is obtained at room temperature, corresponding to a current density of 62.5 A/cm2. Besides, a lower gate leakage current is measured less than 2 nA at the gate voltage of -30 V. Experimental results demonstrate that a better trade-off between the blocking voltage and the on-state characteristics is achieved for the fabricated device, which is desirable for the high power applications.
The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation
Authors: Frewin Christopher , Beygi Mohamad , Bernardin Evans , Feng Chen Yin , La Via Francesco , Dominguez-Viqueria William , Saddow Stephen E.
Published: May 2022

Silicon Carbide (SiC) has been demonstrated as both a bio- and neuro-compatible wide-band-gap semiconductor with a high thermal conductivity and magnetic susceptibility and may be potentially compatible with human brain tissue. Two single-crystal, solid-state forms of SiC have been used to create monolithic intracortical neural implants (INI) without using physiologically exposed metals or polymers, thus eliminating many known reliability challenges in-vivo through a single, homogenous material. Amorphous SiC (a-SiC) was used to insulate 16-channel functional INI and the electrochemical and MRI compatibility (7T) performance were measured. 4H-SiC interfaces were fabricated using homoepitaxy,alternating epitaxial films of n-type and p-type forming an isolating PN junction which prevents substrate leakage current between the 16 adjacent electrodes and traces fabricated which were formed using deep-reactive ion etching (DRIE). 3C-SiC interfaces were fabricated in a similar fashion, but the epitaial conductive layers were grown on on both bulk crystalline (100) silicon and SOI wafers. In both cases a conformal coating of a-SiC was used as the top-side insulator and windows opened using RIE to allow electrochemical interaction. Electrochemical charaterization achieved through electrochemcial impedance spectroscopy (EIS) and cyclic voltammetry (CV) indicates performance on par, or exceeding, that of Pt reference electrodes with the same form fit. While magnetic resonance imaging (MRI) is an essential, non-contact method used to investigate issues with the nervous system, the high field MRI (e.g., 3 T and higher) necessary for proper diagnosis can be a safety issue for patients with INI due to inductive coupling between the powerful electromagnetic fields and the implanted device. This results in having to use lower electromagnetic field power (less than 1.5T), and therefore lower resolution, which hinders diagnostic prognosis for these patients. In this work the MRI compliance of epitaxial, monolithic SiC INI was studied. The specific absorption rate (SAR), induced heating, and image artifacts caused by the portion of the implant within a brain tissue phantom located in a 7 T small animal MRI machine were estimated and measured via finite element method (FEM) and Fourier-based simulations. Both the simulation and experimental results revealed that free-standing 3C-SiC films had no observable image artifacts compared to silicon and platinum reference materials inside the MRI at 7 T while FEM simulations predicted an ~30% SAR reduction for 3C-SiC compared to Pt. These initial simulations and experiments indicate a SiC monolithic INI may effectively reduce MRI induced heating and image artifacts in high field MRI.
Automatic Image Analysis of Stackingfault
Authors: Muoio Annamaria , Calabretta Cristiano , Scuderi Viviana , Zimbone Massimo , La Via Francesco
Published: May 2022

3C silicon carbide is a semiconductor with remarkable properties, making it ideal for the development of long lasting devices, working in harsh environments and under high particle flows. The most significant obstacle to its wider diffusion is the presence of extended, bidimensional and linear defects in its crystal lattice. The purpose of this research is to automatically recognize defects from a TEM image by algorithm that calculates distances and angles.
Ohmic Contact Formation on 4H-SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation
Authors: Sundaramoorthy Vinoth , Wirths Stephan , Knoll Lars
Published: May 2022

In this manuscript Ohmic contact formation at low annealing temperatures is demonstrated using shallow implantation technique. Remarkably, Ni Ohmic contacts with a specific contact resistivity of 1.9x10-5 Ωcm2 have been achieved at as-deposited condition. Smooth interfaces along with reduced Schottky barrier at the metal/SiC interface contributed to improved Ohmic performance at as-deposited and 450°C anneal conditions.
Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiС on Silicon
Authors: Giannazzo Filippo , Fiorenza Patrick , Schiliro Emanuela , Di Franco Salvatore , Monnoye Sylvain , Mank Hugues , Zielinski Marcin , La Via Francesco , Roccaforte Fabrizio
Published: May 2022

This paper presents a macro-and nanoscale electrical investigation of Schottky and metal-oxide junctions with hetero-epitaxial 3C-SiC layers grown on Si. Statistical current-density-voltage (J-V) characterization of Pt/3C-SiC Schottky diodes showed an increase of the reverse leakage current with increasing the devices diameters. Furthermore, C-V and J-V analyses of SiO2/3C-SiC capacitors revealed non-idealities of the thermal oxide, such as a high trapped positive charge (3×1012 cm−2) and a reduced breakdown field (EBD=6.5 MV/cm) compared to ideal SiO2. Nanoscale electrical characterizations by conductive atomic force microscopy (CAFM) and scanning capacitance microscopy (SCM) allowed to shed light on the origin of non-ideal behavior of Schottky and thermal oxide junctions, by correlating the morphological features associated to 3C-SiC crystalline defects with local current transport and carrier density.
Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics
Authors: Lewke Dirk , Supplieth Frank , von Ringleben Maik , Ransom John
Published: May 2022

Within this paper, we will present the results of a study on the ohmic contact formation process with nanosecond (ns) pulsed UV lasers. For the study we compared two laser processes: The base line process with a 100-300 ns pulsed laser with Gaussian beam profile and the 3D-Micromac AG process with a 50-100 ns pulsed laser with top hat beam profile. The forward voltage characteristics at wafer level was analyzed and proves a clear benefit of the top hat laser process. Besides, the forward voltage characteristics of a second run was performed to analyze the influence of increasing energy density to the electrical characteristic of heat sensitive front side structures. Also with high energy density no negative influence could be detected.
Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices
Authors: Kodolitsch E. , Sodan V. , Krieger M. , Tsavdaris Nikolaos
Published: May 2022

In this work we report on the impact of various crystalline defects present in 4H-SiC epitaxial layers on the electrical blocking characteristics of SiC power devices. Dedicated test structures were fabricated and electrically characterized in reverse bias mode. SiC substrate and epitaxial crystal defects, as well defects due to front-end processing were detected and classified using commercial inspection tools. Devices with a single defect-type were studied which leads to a direct correlation of the leakage current spot position within the device and the obtained blocking characteristics. This gives a better understanding of each crystal defect impact on device ́s performance which leads to an improvement in the reliability and cost reduction of SiC power devices.
Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide
Authors: Arzig Matthias , Künecke Ulrike , Salamon Michael , Uhlmann Norman , Wellmann Peter J.
Published: May 2022

The growth conditions of 75 mm SiC crystals in the PVT process is varied by different methods while the temperature field is kept constant. The addition of graphite into the source material leads to the formation of an ordered step flow with step heights of 0.014 µm, while the addition of graphite into the source together with N2 doping changes the step kinetics on the main facet, leading to very large, bunched steps of 0.17 µm. When elemental Si was added into the source material large macro steps are formed on the whole crystal surface. While the doping induced step bunching is related to the incorporation kinetics, the large steps induced in Si-rich conditions are attributed the reduction of surface energy. With the variation of the inert gas pressure the morphology of the surface is altered, similarly. Under low pressure conditions (0.2 mbar) a fine step structure evolves, while at a high pressure (40mbar) large surface steps are formed on the whole growth interface. Large surface steps are strongly impeded in their lateral motion at defects permeating the growth interface. At these sites the formation of foreign polytypes is facilitated.
On the Short Circuit Electro-Thermal Failure of 1.2 kV 4H-SiC MOSFETs with 3D Cell Layouts
Authors: Donato Nazareno , Naydenov Kaloyan , Udrea Florin , Mihaila Andrei , Romano Gianpaolo , Wirths Stephan , Knoll Lars
Published: May 2022

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.
Sensitivity of Dit Extraction at the SiO2/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements
Authors: Belanche Guadas Manuel , Kumar Piyush , Woerle Judith , Stark Roger , Grossner Ulrike
Published: May 2022

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (Dit). We show that the extracted Dit strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the Dit extraction.
In Situ Monitoring of Unintentionally Released Nitrogen Gas in the Initial PVT Silicon Carbide Growth Process Using Mass Spectrometry
Authors: Ihle Jonas , Wellmann Peter J.
Published: May 2022

Different initial process steps during PVT crystal growth of SiC were monitored with a mass spectrometer. To measure the gas phase composition in the PVT growth machine during these steps the continuously pumped exhaust gas was analyzed by a quadrupole mass spectrometer (PrismaPro QMG 250). In order to reduce unintentionally doping of the crystal by contaminations in the growth setup the focus was on the release of nitrogen during the initial steps of the growth process. During the heat up of the growth setup in vacuum a substantial release of molecular nitrogen was observed at 800 °C. Further, the influence of pump and purge-steps on the amount of nitrogen in the gas phase was examined. After performing a pump and purge step, the intensity of the measurable nitrogen-related signal (m/z = 28) was approximately 20 % of the initial value. In-situ monitoring of the gas phase during the initial steps of crystal growth proved to be a versatile tool for the development of a process minimizing unintentionally doping through released nitrogen.
Self-Turn-On Phenomenon of SiC MOSFETs by Fast Switching Operation
Authors: Nakata Shuhei , Sato Yuta
Published: May 2022

The effect of the contact resistance between the p-well and the source electrode of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) on the self-turn-on phenomenon was investigated experimentally. It was found that the contact resistance significantly affects the self-turn-on in addition to the conventional self-turn-on owing to the parasitic capacitances. To simulate this phenomenon, a circuit model including the contact resistance, p-well sheet resistance, and p-well/n+ region diode was created, and the simulation results were compared with the measurement results. Consequently, by considering the contact resistance and the forward recovery effect in the diode characteristics, the gate-induced voltage was calculated, with the results close to those of the experiment. Thus, the influence of contact resistance and p-well/n+ diode effects are clearly very important when operating SiC MOSFETs at high switching speeds.
Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth
Authors: Baierhofer Daniel , Thomas Bernd , Staiger F. , Marchetti B. , Förster C. , Erlbacher Tobias
Published: May 2022

The yield of high power 4H-SiC Trench-MOSFET devices, especially for those with large chip area, is largely dependent on the quality of the underlying epitaxial layers and therefore low densities of critical defects are of utmost importance. Different growth conditions for the deposition of epitaxial layers were investigated to reduce the impact of defects on electrical device performance. For this investigation, 12 μm thick n-type epitaxial layers were grown varying growth rates for the buffer and the drift layer in a warm-wall chemical vapor deposition reactor. The defects in the epitaxial layers were characterized utilizing surface microscopy as well as ultraviolet photoluminescence techniques. A quantitative comparison of surface defects and crystallographic defects between the different growth conditions was conducted with these methods. The impact of the growth conditions on the formation of critical defects is discussed in detail. The reduction of critical defects, which resulted in an increase of the predicted die yield, as well as an outlook on future investigations, is discussed.
Ni/Heavily-Doped 4H-SiC Schottky Contacts
Authors: Vivona Marilena , Greco Giuseppe , Di Franco Salvatore , Fiorenza Patrick , Giannazzo Filippo , La Magna Antonino , Roccaforte Fabrizio
Published: May 2022

In this work, we focus on the electrical characterization of Ni Schottky contact on n-type heavily doped (ND>1019 cm−3) 4H-SiC layer, achieved by P-ion implantation. In particular, the forward current–voltage characterization of Schottky diodes showed a reduced turn-on voltage for the Ni/heavily-doped 4H-SiC if compared to a reference Ni/4H-SiC Schottky contact fabricated under similar conditions but without implant. Moreover, it was observed the predominance of a thermionic-field-emission (TFE) mechanism for the current transport through the interface. From a current-voltage-temperature (I-V-T) study, the temperature-dependence of the Schottky barrier and doping concentration were evaluated, obtaining a reduction of the barrier (from 1.77 to 1.66 eV), while the doping concentration maintains constant around 1.96×1019 cm-3. This study provides useful insights for a deeper comprehension of the electrical behavior of Ni contacts and can have possible applications in 4H-SiC Schottky diode technology.
SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth
Authors: Maloušek Roman , Chochol Jan , Das Hrishikesh , Sunkari Swapna , Justice Joshua , Gumaelius Krister , Franchi Jimmy , Domeij Martin , Allerstam Fredrik , Wada Ryota , Kuroi Takashi
Published: May 2022

This work details two approaches with multi-epitaxial growth to create a vertical superjunction structure made of alternating pillars. One approach is a chain of very high energy implants, the other uses a preferred implantation direction to achieve a channeled profile. The manufactured devices show a breakdown voltage of 1000 V for channeled, two-step epi with total 4.9 μm thickness. 800 V for regular high energy implants using three epi steps of total 3.7 μm thickness. The measured Rsp was 0.7 mOhm*cm2 for dies with size 0.018 cm2. UIS and temperature measurement show reliable performance. The channeled implant looks favorable to reduce the number of process steps needed to create an efficient superjunction structure.
Edge Terminations for 4H-SiC Power Devices: A Critical Issue
Authors: Godignon Philippe , Montserrat Josep , Rebollo José , Planson Dominique
Published: May 2022

Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific complementary characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.
Estimation of Activation and Compensation Ratios in Al+ Ion Implanted 4H-SiC: Comparison of Two Methodologies
Authors: Nipoti Roberta , Boldrini Virginia , Canino Maria , Tamarri Fabrizio , Vantaggio Salvatore , Parisini Antonella
Published: May 2022

Activation and compensation ratios feature the electrical doping efficiency of a semiconductor material by ion implantation. The estimation of these ratios requires a quantitative evaluation of the density of the implanted dopant in substitutional position and of the density of the compensator centers after the mandatory post implantation annealing treatment. In the case of Al+ ion implanted 4H-SiC, it is a common habit to determine acceptor density, compensator density and acceptor thermal ionization energy by fitting the curve of the drift holes temperature dependence with the charge neutrality equation. However, this strategy could lead to ambiguous results. In fact, this study shows several cases of Al+ ion implanted 4H-SiC of interest for electronic device fabrication, where at least two sets of such fitting outputs can reproduce the same experimental curve within the uncertainty of the data. Provided that a model for the carrier transport could be set-up, the contemporaneous fits of the temperature dependence of drift hole density and of drift hole mobility is proposed to alleviate the uncertainty of the estimated acceptor density, compensator density and acceptor thermal ionization energy.
Precise Control of Al Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride
Authors: Zielinski Marcin , Bussel Marc , Mank Hugues , Monnoye Sylvain , Portail Marc , Michon Adrien , Cordier Yvon
Published: May 2022

Experimental results presented in this contribution demonstrate that adding HCl to the SiC CVD process is not only an efficient way to suppress the Aluminum memory effect but may also be considered as a powerful tool for fine tuning of intentional Al incorporation in 3C-SiC and 4H-SiC thin films. The approach is easy to implement and seems more reliable than changing TMA bubbling/dilution parameters during the growth. An ad-hoc phenomenological model is proposed to explain the correlation between the HCl supply and Al incorporation.
Multiscale Simulations of Plasma Etching in Silicon Carbide Structures
Authors: Italia Markus , Deretzis Ioannis , Nastasi Alfio , Scalese Silvia , La Magna Antonino , Pirnaci Massimo , Pagano Daniele , Tenaglia Dario , Vasquez Patrizia
Published: May 2022

Manufacturing of Silicon Carbide (SiC) based devices will soon require the accuracy and control typical of the advanced Si based nanoelectronics. As a consequence, the processes development will surely benefit of technology computer aided design (TCAD) tools dedicated to the current and future SiC process technologies. Plasma etching is one of the most critical and difficult process for optimization procedures in the micro/nanofabrication area, since the resultant 2D (e.g. in trenches) or 3D (e.g in holes) profiling is the consequence of the complex interactions between plasma and materials in the device structures. In this contribution we present a simulation tool dedicated to the etching simulation of SiC structures based on the sequential combination of a plasma scale global model and feature scale Kinetic Monte Carlo simulations. As an example of the approach validation procedure the simulations are compared with the characterization analysis of particular real process results.
Pulsed Forward Bias Body Diode Stress of 1700 V SiC MOSFETs with Individual Mapping of Basal Plane Dislocations
Authors: Kochoska Sara , Domeij Martin , Sunkari Swapna , Justice Joshua , Das Hrishikesh , Pham Thanh Toan , Franchi Jimmy , Maslougkas Sotirios , Lee Ho Jung , Hu Xue Qing , Neyer Thomas
Published: May 2022

In this work, body diode stress has been carried out for 1700 V 25 mΩ planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of 250-400 A (about 1000-1600 A/cm2) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased RDSon was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.
Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models
Authors: Waltl Michael , Hernandez Yoanlys , Schleich Christian , Waschneck Katja , Stampfer Bernhard , Reisinger Hans , Grasser Tibor
Published: May 2022

For the analysis of the characteristics and behavior of circuits prior to fabrication and to improve circuit performance, simulations using Spice tools are typically performed. Such tools rely on static compact models describing the behavior of the individual circuit components such as transistors. In reality, the behavior of the transistors changes over time due to aging, for instance, as a consequence of bias temperature instabilities (BTI). BTI is typically referred to as a drift of the threshold voltage of a transistor due to charge trapping at oxide and interface defects. To explain BTI, power-law-like mathematical expressions are often employed. However, using these simple formulas, the experimental data can only be replicated with limited accuracy. To evaluate the performance of logic inverter circuits made from 4H-SiC CMOS transistors with high precision, we use a physics-based defect model to describe the change of the device behavior from a defect-centric perspective. Our results indicate the limitations of using power-law-like formulas as they lead to an overly pessimistic estimation for circuit parameters.
Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants
Authors: Hitchcock Collin , Ghandi Reza , Deeb Peter , Kennerly Stacey , Torky Mohamed , Chow T. Paul
Published: May 2022

MeV level aluminum implants into 4H-SiC were performed as part of superjunction diode fabrication. Measurement of resistance test structures produced resistivities well above expected values with large decreases at elevated temperatures. Capacitance-voltage measurements indicate a high activation rate of the implanted aluminum. Temperature dependent Hall measurements produce reasonable hole mobilities with acceptor ionization energies of approximately 330meV, well above the 200meV expected for low concentration aluminum doping in 4H-SiC.
Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography
Authors: Peng Hong Yu , Chen Ze Yu , Liu Yafei , Cheng Qian Yu , Hu Shanshan , Huang Xian Rong , Assoufid Lahsen , Raghothamachar Balaji , Dudley Michael
Published: May 2022

Synchrotron monochromatic beam X-ray topography has been widely applied to characterize structural defects in SiC crystals. Using ray tracing simulations, the dislocation contrast in X-ray topography under strong diffraction conditions (diffraction takes place at or near Bragg angle) has been intensively investigated. However, the contrast and the configurations of the dislocation images recorded under weak diffraction conditions have not been fully investigated. Recently, we demonstrated that the contrast of dislocations in synchrotron grazing incidence topography under weak diffraction conditions can also be analyzed and interpreted by applying ray tracing principles. In this study, we have extended the application of the ray tracing method to analyze the dislocation contrast in weak beam synchrotron back reflection and rocking curve topography. The ray tracing method is shown to successfully simulate and correlate the contrast of threading screw dislocations at various positions on the rocking curve and thus allow to determine the signs of Burgers vectors.
Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing
Authors: Badalà Paolo , Smecca Emanuele , Rascunà Simone , Bongiorno Corrado , Carria Egidio , Bassi Anna , Bellocchi Gabriele , Castorina Silvia , Tringali Cristina , La Magna Antonino , Alberti Alessandra
Published: May 2022

Laser annealing process for ohmic contact formation on 4H-SiC has attracted increasing attention in the last years, because it enables the fabrication of SiC power devices on very thin substrates. We have investigated the formation of Nickel-based ohmic contact on 4H-SiC by using a Yb:YAG laser in scanning mode, with a wavelength of 515 nm and a pulse duration of 1200 ns. A 100 nm thick Ni layer has been deposited on SiC and irradiated at different process conditions. The reaction process has been studied, as a function of fluence and scan number of laser annealing, by means of X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM) analyses. The electrical properties of the annealed layers have been evaluated on Schottky Barrier Diodes (SBDs) devices, confirming the ohmic behavior of the reacted contact and showing improved performances respect to RTA approach. The compatibility of thermal budget of the process in the front side has been verified by means process simulation. A strong relationship between structural properties of reacted layers and electrical behavior of SBDs devices has been revealed. Solid-state laser annealing process, with wavelength in green light region, can indeed represent a suitable solution for ohmic contact formation of 4H-SiC power devices, fabricated on thin substrates.
Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs
Authors: Murakami Eiichi , Takeshita Tatsuya , Oda Kazuhiro
Published: May 2022

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.
Investigation of SiC Thyristors with Varying Amplifying Gate Design
Authors: Scharnholz Sigo , Hassdorf Ralf , Bauersfeld Dirk , Vergne Bertrand , Phung Luong Viet , Planson Dominique
Published: May 2022

This paper presents experimental 1.2 kV, 10 A SiC thyristors with different amplifying gate design. In contrast to comparative devices (with simple gate) the amplifying gate thyristors show a characteristic snap-back and a higher gate current to trigger. Their gate-anode I-V characteristics comply with the underlying design constraint, regarding the resistances of pilot and main thyristor: (RP > RM). Moreover, the turn-on waveforms of well-designed amplifying gate thyristors reveal peak-shaped inversions in the gate current and voltage transients, providing clear evidence of the successive triggering of pilot and main thyristor.