bluuebunny/crossref_metadata_2025 huggingface dataset:
Direct-execution computer architecture
Authors: CHU YAOHAN
Published: July 2004

The Direct-Execution Architecture is a language-directed computer architecture. It can accept a highlevel-language program and directly executes it without compilation, assembly, linkage editing or loading. It offers a means to eliminate compilers, loaders etc. and attacks the problem of mounting software cost. In addition, the advent of microprocessors has demonstrated that highly complex digital hardware can be built reliably and inexpensively. Using this hardware to implement the Direct-Execution Architecture redistributes apportionment of costs between the hardware and software. The paper surveys the Direct-Execution Architecture, presents the relationship between language and architecture, and explains how a Direct-Execution system works. It also brings up the use of Direct-Execution for a highly interactive program writing, debugging, execution system. With this system, program writing could proceed like English composition. This paper then discusses the issue of a single high-level machine language, and the potential role of the interpreters. Finally, it attempts to fortell what could happen to the Direct-Execution Architecture in the next five to 10 years.
Introducing the notion of processes to hardware
Authors: van de Snepscheut Jan L. A. , Slavenburg Gert A.
Published: July 2004

A simple multiplexing technique is shown to lead to a starvation-free process-dispatching strategy without making any assumptions about the behaviour of a process. A strong implementation of semaphores is presented using associative hardware.
Technical overview of the Renaissance Octobus system
Authors: Gibson Randall , Anderson Paul
Published: July 2004

With the recent availability of inexpensive micro-computers, a technique for effectively sharing the still costly peripherals is needed. This paper summarizes the OCTOBUS, a multi-processor microcomputer architecture and system designed to meet this requirement. The current implementation is based on DEC's LSI-11 microcomputer.
Intelligent memory
Authors: Quick G. E.
Published: July 2004

This paper puts forward a design for a computer system based on an array of "Single chip" microcomputers. The design supports the requirements of Highly Reliable Software for execution of parallel programs.
Rivalling multiprocessor organization
Authors: Chroust G. , Mühlbacher J. R.
Published: July 2004

The availability of microprocessors in large quantities at amazingly low prices moves the break-even point for some traditional trade-offs between hardware and execution time into the direction of more hardware and towards systems with multiple microprocessors. The following scheme allows considerable execution-time speed-up at the cost of redundant hardware.
Extending the power of short-wordlength processors by means of context-dependent machine instructions
Authors: Yuen C K
Published: July 2004

It is shown that the concept of context-dependent machine instructions may be used in the architectural design of processors with short wordlengths, such as 8-bit microprocessors, in order to increase the capabilities of such machines above those of currently available models.
Protection at the micromachine level
Authors: McDowell Charlie
Published: July 2004

One possible reason that user writable control stores on microprogrammable computers are not used heavily, is the lack of a secure environment in which to run the WCS programs. This paper describes a simple method of adding hardware protection to the micromachine level of a computer.
Protected procedure call on the PRIME(TM) machines
Authors: Feustel Edward A.
Published: July 2004

The procedure call and argument transfer mechanism on the Model P400 and the 50 Series of PRIME machines is described. First, PRIME V-mode addressing is examined. Next, data structures interpreted by hardware and relevant to procedure call are explained. Finally, the process of procedure call, argument transfer, and return are described.The mechanism is evaluated on the basis of our experience. This mechanism has facilitated inter-language communications and has permitted the development of a shared operating system that is embedded within the user's address space. Its high speed has permitted a system environment consisting of many procedures. It has several novel features not available in other machines.Some extensions to the mechanism are suggested. These extensions would simplify the use of procedure call in languages which use call by value. They would facilitate procedure call in a general register environment.
Some remarks on direct execution computers
Authors: El-Halabi Hossam , Agrawal Dharma P.
Published: July 2004

As Direct-Execution Computers (D.E.C.s) are expected to reduce the semantic gap between the software and the hardware concepts to zero, they have been considered to be innovative in computer architecture. It is our objective to discuss this claim in the light of some major issues such as hardware technology, multilanguage environment, etc.
Peering through the RISC/CISC fog
Authors: Colwell Robert P. , Hitchcock Charles Y. , Jensen E. Douglas
Published: July 2004

We are defining a computer architecture to support a decentralized operating system that is under development. Since complex functions of this system could appear directly in the architecture's instruction set, we are immersed in the current RISC/CISC debate where we have found many questions and few answers. Hoping to shed light on aspects of this conflict, we have embarked on two studies. The first seeks to find an environment where complex instructions can enhance system performance. The second tries to decouple multiple register set performance from instruction set performance in general-purpose register machines.
Puzzling with microcode
Authors: Jones Jeremy
Published: July 2004

A Pascal version of the puzzle program was executed on a user-microprogrammable HLL machine and a "runtime profile" obtained. The code sections where most of the execution time was spent were found and replaced with microcode. A six fold increase in execution speed was achieved by writing 25 microinstructions.
Performance of various computers using standard linear equations software in a Fortran environment
Authors: Dongarra Jack J.
Published: July 2004

In this note we compare a number of different computer systems for solving dense systems of linear equations using the LINPACK software in a Fortran environment. There are about 50 computers compared, ranging from a Cray X-MP to the 68000 based systems such as the Apollo and SUN Workstations.
An algebraic memory model
Authors: Moskowitz J. P. , Jousselin C.
Published: July 2004

Memory in the von Neumann computer is usually viewed as a linear array. We prove that this view does not follow from the consecutive nature of this memory, but from the group structure of the law performed in the address arithmetic unit. By changing that law, we can get a memory with a non commutative access. As an example we describe the metacyclic memory.
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
Authors: Magklis Grigorios , Scott Michael L. , Semeraro Greg , Albonesi David H. , Dropsho Steven
Published: July 2004

A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and voltage to be reduced in domains that are not currently on the application's critical path. Given a reconfiguration mechanism capable of choosing appropriate times and values for voltage/frequency scaling, an MCD processor has the potential to achieve significant energy savings with low performance degradation.Early work on MCD processors evaluated the potential for energy savings by manually inserting reconfiguration instructions into applications, or by employing an oracle driven by off-line analysis of (identical) prior program runs. Subsequent work developed a hardware-based on-line mechanism that averages 75--85% of the energy-delay improvement achieved via off-line analysis.In this paper we consider the automatic insertion of reconfiguration instructions into applications, using profile-driven binary rewriting. Profile-based reconfiguration introduces the need for "training runs" prior to production use of a given application, but avoids the hardware complexity of on-line reconfiguration. It also has the potential to yield significantly greater energy savings. Experimental results (training on small data sets and then running on larger, alternative data sets) indicate that the profile-driven approach is more stable than hardware-based reconfiguration, and yields virtually all of the energy-delay improvement achieved via off-line analysis.
Pipeline damping
Authors: Powell Michael D. , Vijaykumar T. N.
Published: July 2004

Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause noise margins to decrease, while increasing current and frequency makes supply noise injection larger, especially noise caused by inductance in the supply lines. Creating power distribution systems is one of the key challenges in modern chip design. Decoupling capacitance helps reduce inductance effects, but there is often a peak in the supply impedance that occurs at a resonant frequency caused roughly by the package inductance and the chip decoupling capacitors. This frequency is on the order of 100MHz, which is much lower than the operating frequency of the processor. We propose pipeline damping, an architectural technique which controls instruction issue to guarantee bounds on current variation around the frequency of the supply resonance, thus reducing the resulting supply noise. Damping is a cheaper alternative to expensive, circuit-based noise-reduction techniques. We make the fundamental observation that limiting the current flow change (di) within resonant time period (dt) controls di/dt without large performance loss. Damping guarantees bounds on current variation while allowing processor current to increase or decrease to the magnitude required to maintain performance. Our results show that a damped processor guarantees a 33% reduction in the worst-case current variation with an average performance degradation of 7% and average energy delay of 1.09 compared to an undamped processor.
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
Authors: Xu Min , Bodik Rastislav , Hill Mark D.
Published: July 2004

Debuggers have been proven indispensable in improving software reliability. Unfortunately, on most real-life software, debuggers fail to deliver their most essential feature --- a faithful replay of the execution. The reason is non-determinism caused by multithreading and non-repeatable inputs. A common solution to faithful replay has been to record the non-deterministic execution. Existing recorders, however, either work only for datarace-free programs or have prohibitive overhead.As a step towards powerful debugging, we develop a practical low-overhead hardware recorder for cachecoherent multiprocessors, called
Flight Data Recorder (FDR)
. Like an aircraft flight data recorder, FDR continuously records the execution, even on deployed systems, logging the execution for post-mortem analysis.FDR is practical because it piggybacks on the cache coherence hardware and logs nearly the minimal threadordering information necessary to faithfully replay the multiprocessor execution. Our studies, based on simulating a four-processor server with commercial workloads, show that when allocated less than 7% of system's physical memory, our FDR design can capture the last one second of the execution at modest (less than 2%) slowdown.
A highly configurable cache architecture for embedded systems
Authors: Zhang Chuanjun , Vahid Frank , Najjar Walid
Published: July 2004

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.
DRPM
Authors: Gurumurthi Sudhanva , Sivasubramaniam Anand , Kandemir Mahmut , Franke Hubertus
Published: July 2004

A large portion of the power budget in server environments goes into the I/O subsystem - the disk array in particular. Traditional approaches to disk power management involve completely stopping the disk rotation, which can take a considerable amount of time, making them less useful in cases where idle times between disk requests may not be long enough to outweigh the overheads. This paper presents a new approach called DRPM to modulate disk speed (RPM) dynamically, and gives a practical implementation to exploit this mechanism. Extensive simulations with different workload and hardware parameters show that DRPM can provide significant energy savings without compromising much on performance. This paper also discusses practical issues when implementing DRPM on server disks.
Efficient use of memory bandwidth to improve network processor throughput
Authors: Hasan Jahangir , Chandra Satish , Vijaykumar T. N.
Published: July 2004

We consider the efficiency of packet buffers used in packet switches built using network processors (NPs). Packet buffers are typically implemented using DRAM, which provides plentiful buffering at a reasonable cost. The problem we address is that a typical NP workload may be unable to utilize the peak DRAM bandwidth. Since the bandwidth of the packet buffer is often the bottleneck in the performance of a shared-memory packet switch, inefficient use of available DRAM bandwidth further reduces the packet throughput. Specialized hardware-based schemes that alleviate the DRAM bandwith problem in high-end routers may be less applicable to NP-based systems, in which cost is an important consideration.In this paper, we propose cost-effective ways to enhance average-case DRAM bandwidth. In modern DRAMs, successive accesses falling within the same DRAM row are significantly faster than those falling across rows. If accesses to DRAM can be generated differently or reordered to take advantage of fast same-row accesses, peak DRAM bandwidth can be approached. The challenge is in exploiting this "row locality" despite the unpredictable nature of memory accesses in NPs. We propose a set of simple techniques to meet this challenge. These include locality-sensitive buffer allocation on packet input, reordering DRAM accesses to increase locality, and prefetching to reduce row miss penalty. We evaluate our techniques on cycle-accurate simulations of Intel's IXP 1200 network processor and find that they boost packet throughput on average by 42.7%, utilizing nearly the peak DRAM bandwidth, for a set of common NP applications processing a real trace.
Phase tracking and prediction
Authors: Sherwood Timothy , Sair Suleyman , Calder Brad
Published: July 2004

In a single second a modern processor can execute billions of instructions. Obtaining a bird's eye view of the behavior of a program at these speeds can be a difficult task when all that is available is cycle by cycle examination. In many programs, behavior is anything but steady state, and understanding the patterns of behavior, at run-time, can unlock a multitude of optimization opportunities.In this paper, we present a unified profiling architecture that can efficiently capture, classify, and predict phase-based program behavior on the largest of time scales. By examining the proportion of instructions that were executed from different sections of code, we can find generic phases that correspond to changes in behavior across many metrics. By classifying phases generically, we avoid the need to identify phases for each optimization, and enable a unified prediction scheme that can forecast future behavior. Our analysis shows that our design can capture phases that account for over 80% of execution using less that 500 bytes of on-chip memory.
Building quantum wires
Authors: Oskin Mark , Chong Frederic T. , Chuang Isaac L. , Kubiatowicz John
Published: July 2004

As quantum computing moves closer to reality the need for basic architectural studies becomes more pressing. Quantum wires, which transport quantum data, will be a fundamental component in all anticipated silicon quantum architectures. In this paper, we introduce a quantum wire architecture based upon quantum teleportation. We compare this teleportation channel with the traditional approach to transporting quantum data, which we refer to as the swapping channel. We characterize the latency and bandwidth of these two alternatives in a device-independent way and describe how the advanced architecture of the teleportation channel overcomes a basic limit to the maximum communication distance of the swapping channel. In addition, we discover a fundamental tension between the scale of quantum effects and the scale of the classical logic needed to control them. This "pitch-matching" problem imposes constraints on minimum wire lengths and wire intersections, which in turn imply a sparsely connected architecture of coarse-grained quantum computational elements. This is in direct contrast to the "sea of gates" architectures presently assumed by most quantum computing studies.
A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels
Authors: Suh Jinwoo , Kim Eun-Gyu , Crago Stephen P. , Srinivasan Lakshmi , French Matthew C.
Published: July 2004

Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM latency and bandwidth and diminishing returns of increasing superscalar ILP and cache sizes have led to the proposal of new microprocessor architectures that implement processor-in- memory, stream processing, and tiled processing. Each architecture is typically evaluated separately and compared to a baseline architecture. In this paper, we evaluate the performance of processors that implement these architectures on a common set of signal processing kernels.The implementation results are compared with the measured performance of a conventional system based on the PowerPC with Altivec. The results show that these new processors show significant improvements over conventional systems and that each architecture has its own strengths and weaknesses.
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
Authors: Sankaralingam Karthikeyan , Nagarajan Ramadass , Liu Haiming , Kim Changkyu , Huh Jaehyuk , Burger Doug , Keckler Stephen W. , Moore Charles R.
Published: July 2004

This paper describes the
polymorphous
TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism. To adapt to small and large-grain concurrency, the TRIPS architecture contains four out-of-order, 16-wide-issue Grid Processor cores, which can be partitioned when easily extractable fine-grained parallelism exists. This approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes--ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.
The Jrpm system for dynamically parallelizing Java programs
Authors: Chen Michael K. , Olukotun Kunle
Published: July 2004

We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with thread-level speculation (TLS) support. CMPs have low sharing and communication costs relative to traditional multiprocessors, and thread-level speculation (TLS) simplifies program parallelization by allowing us to parallelize optimistically without violating correct sequential program behavior. Using a Java virtual machine with dynamic compilation support coupled with a hardware profiler, speculative buffer requirements and inter-thread dependencies of prospective speculative thread loops (STLs) are analyzed in real-time to identify the best loops to parallelize. Once sufficient data has been collected to make a reasonable decision, selected loops are dynamically recompiled to run in parallel.Experimental results demonstrate that Jrpm can exploit thread-level parallelism with minimal effort from the programmer. On four processors, we achieved speedups of 3 to 4 for floating point applications, 2 to 3 on multimedia applications, and between 1.5 and 2.5 on integer applications. Performance was achieved by automatic selection of thread decompositions by the hardware profiler, intra-procedural optimizations on code compiled dynamically into speculative threads, and some minor programmer transformations for exposing parallelism that cannot be performed automatically.
A computer architecture with access control and cache option tags on individual instruction operands
Authors: Fong Anthony S.
Published: July 2004

The access control on data is usually on per memory page basis and is implemented in the Translation Lookaside Buffer (TLB) via page tables managed by memory management of operating systems. In addition, to optimize the memory reference performance, it is desirable to specify if a page should be encached or not, so that unnecessary and undesirable data encaching will be avoided. It is also desirable to be able to specify if maintaining data coherency in a multiprocessing system is required. Such maintenance demands a lot of checking, which creates performance bottlenecks and system complexity, but only a small percentage of data requires absolute data coherency. In all these cases, pages are not logical entities for such attributes or characteristic assignments. Better choices are the operands, which can map directly to the variables in a program.In this paper, we are proposing an architecture to support the access control, the maintenance requirement of data coherency and optional encaching on data as system attributes on individual operands.
Ocean warning
Authors: Heinrich Mark , Chaudhuri Mainak
Published: July 2004

Ocean is a popular program from the SPLASH-2 parallel benchmark suite. A complete application, as opposed to a computational kernel, Ocean is often used as a representative of a well-tuned parallel program in architectural studies. However, we find there is a danger in using Ocean to evaluate proposed enhancements that purport to either improve scalability or reduce synchronization overhead. The default Ocean code contains an ill-advised code segment that seriously handicaps its "base" performance in common architectural studies. We provide the one-line fix for the offending code that improves performance by as much as a factor of 2.3, and suggest that architecture researchers using Ocean to evaluate their new ideas---especially when discussing scalability or synchronization---change their code immediately.
A multiple floating point coprocessor architecture
Authors: Rauchwerger Lawrence , Farmwald Michael P.
Published: July 2004

General purpose microprocessor based computers usually speed their arithmetic processing performance by using a floating point co-processor. Because adding more co-processors represents neither a technological nor a cost problem we investigated a system based on a MIPS R2000 [2] and 4 floating point units. In this paper we show a block diagram of such an implementation and how two important scientific operations can be accelerated using a single unmodified data bus. A large percentage of the engineering applications are solved with the help of linear algebra methods like BLAS3 [4] algorithms; It is precisely for these primitives that the proposed architecture brings significant performance gains. The first operation described will be a matrix multiplication algorithm, its timing diagram and some results. Next a polynomial evaluation technique will be examined. Finally we show how to use the same ideas with various other microprocessors.
Cache performance of the integer SPEC benchmarks on a RISC
Authors: Pnevmatikatos Dionisios N. , Hill Mark D.
Published: July 2004

SPEC is a new set of benchmark programs designed to measure a computer system's performance. The performance measured by benchmarks is strongly affected by the existence and configuration of cache memory. In this paper we evaluate the cache miss ratio of the Integer SPEC benchmarks. We show that the cache miss ratio depends strongly on the program, and that large caches are not completely exercised by these benchmarks.
Coding guidelines for pipelined processors
Authors: Rymarczyk James W.
Published: July 2004

This paper is a tutorial for assembly language programmers of pipelined processors. It describes the general characteristics of pipelined processors and presents a collection of coding guidelines for them. These guidelines are particularly significant to compiler developers who determine object code patterns.
Fast procedure calls
Authors: Lampson Butler W.
Published: July 2004

A mechanism for control transfers should handle a variety of applications (e.g., procedure calls and returns, coroutine transfers, exceptions, process switches) in a uniform way. It should also allow an implementation in which the common cases of procedure call and return are extremely fast, preferably as fast as unconditional jumps in the normal case. This paper describes such a mechanism and methods for its efficient implementation.
An experiment to improve operand addressing
Authors: Cook Robert P. , Donde Nitin
Published: July 2004

MCODE is a high-level language, stack machine designed to support strongly-typed, Pascal-based languages with a variety of data types in a modular programming environment. The instruction set, constructed for efficiency and extensibility, is based on an analysis of 120,000 lines of Pascal programs. The design was compared for efficiency with the instruction sets of the Digital Equipment PDP-11 and VAX by examining the generated code from the same compiler for all three machines. In addition, the original design choices were tested by analyzing the generated code from 19,000 lines of StarMod programs. As a result of this iterative experiment, we have summarized our observations in an efficient reorganization of the VAX's addressing modes.
Empirical analysis of the mesa instruction set
Authors: Sweet Richard E. , Sandman James G.
Published: July 2004

This paper describes recent work to refine the instruction set of the Mesa processor. Mesa [8] is a high level systems implementation language developed at Xerox PARC during the middle 1970's. Typical systems written in Mesa are large collections of programs running on single-user machines. For this reason, a major design goal of the project has been to generate compact object programs.

The computers that execute Mesa programs are implementations of a stack architecture [5]. The instructions of an object program are organized into a stream of eight bit bytes. The exact complement into of instructions in the architecture has changed as the language and machine micro architecture have evolved.

In Sections 3 and 4, we give a short history of the Mesa instruction set and discuss the motivation for our most recent analysis of it. In Section 5, we discuss the tools and techniques used in this analysis. Section 6 shows the results of this analysis as applied to a large sample of approximately 2.5 million instruction bytes. Sections 7 and 8 give advice to others who might be contemplating similar analyses.
The data management machine, a classification
Authors: Rosenthal Robert S.
Published: July 2004

There has been much interest in the use of special purpose processors as the data base management component of data processing systems. The generic terms “backend” and “data management machine” have been applied to such devices. Examination of the literature reveals a broad cross section of host to backend functional distribution and interconnection methodology. This discussion represents an attempt to examine and classify several of these backend data base management machine configurations in terms of their operational parameters and application constraints. A formal taxonomy of such systems remains yet to be performed.

At least three distinct classes of data management machine (DMM) are evidenced in the literature; they are the large host backend, distributed network data node and smart peripheral. The intended classes of problem that the various authors envision amenable to solution by the DMM approach exhibit overlap while the performance envelope in which each DMM architecture would provide a technically acceptable, economically sound solution to a given user requirement set varies. Some of the papers used as source for this work contained no explicit mention of either the problem classes or performance constraints that the described configuration was to address; thus liberty has been taken in interpreting the implicit application goals of these authors.
Editing requirements for data base applications and their implementation on the INDY backend kernel
Authors: Otis Allen J. , Copeland George P.
Published: July 2004

An extrapolation of user and hardware cost trends indicate that future systems should provide more complete functionality, simplicity of use, and reliability by increasing the amount of hardware present in the system. For data base systems, this can be done by providing very high level data languages and by implementing them directly in hardware. These goals are realized with a simple hardware arrangement called INDY, which uses inexpensive memory technologies (such as charge coupled devices, magnetic bubbles, or discs). This paper first discusses the data definition and editing requirements of data languages. Then the implementation of these requirements on the INDY backend kernel is described. Finally, a comparison is made of the various memory technologies for suitability to INDY.
Semantic paging on intelligent discs
Authors: Lipovski G. Jack
Published: July 2004

In order to apply Artificial Intelligence techniques like inferencing to large (10
9
-10
12
bit) data bases, an intelligent secondary memory is proposed that is capable of extracting a subgraph from a graph stored in it for further processing in a conventional or special purpose computer. The "pointer transfer" technique developed for CASSM is used to efficiently mark and output a subgraph stored in one file, and a simple technique is proposed to link parts of the subgraph stored on different files. Besides proposing a useful secondary memory system for applying Artificial Intelligence techniques to large data bases, this paper attacks one of the most difficult problems in distributed data base systems, which is the generation of "homomorphic query fragments" that automatically carry the query from one file to other files needed to resolve the query.
A specialized computer architecture for text retrieval
Authors: Roberts David C.
Published: July 2004

This paper describes a specialized computer architecture for text retrieval that provides a wide range of query capabilities, without the use of indexes of the material retrieved. A distributed approach is employed, with direct search processors. Each search processor is closely associated with one or more disk drives that store the data to be searched and each consists of a comparator for matching query terms, logic elements to combine query terms, a disk controller and a control minicomputer.The key element of the architecture is the comparator, which can store over 64,000 characters of query terms and compare all of these terms simultaneously with data arriving from a disk continuously at more than one million bytes per second. Exact match, partical match, numeric comparison and context limitation are among the capabilities provided. The comparator is implemented as three similar universal finite-state automata, with special features to facilitate text retrieval and reduce hardware costs.A breadboard version of the system with one searcher is operational and has undergone detailed evaluation. A prototype system with two searchers is being implemented and will be placed into regularly scheduled use.
Functional parallelism in an operand state saving computer
Authors: Harvill J. B.
Published: July 2004

Multiple, high-level operators are assigned to a general operand. The operators are implemented with individual micro-processors and are "attached" dynamically to the memory location representing the "current" value of the operand. The operators then asynchronously use each new operand value as it is stored and perform their operations in parallel. The proposed architecture represents a true M I S D (Multiple Instruction Stream - Single Data Stream) computer. Its architecture can provide effective parallelism and reduced programming complexity for a large class of both numeric and non-numeric computer problems.
Madman machine
Authors: Hutchison J. S. , Roman W. G.
Published: July 2004

A back-end data base machine is discussed in which the back-end is closely coupled to the host system as an intelligent I/O device. The design of the hardware and software is such that the data base disks can be on either the host or back-end computers. The design is motivated by memory size considerations on mini-computer systems and also by cost considerations of large disks. The implementations of such a system on PDP-11s is discussed.
The use of a database machine for supporting relational databases
Authors: Banerjee Jayanta , Hsiao David K.
Published: July 2004

One of the goals in the design of database machines of the future is their generality. In addition to being capable of carrying out the common database management functions with high reliability and performance, some of these machines are intended to support more than one data model. A specific database machine, known as the DBC, is intended to support several existing data models. Although the DBC supports many data models, we single out the relational data model for this discussion. In particular, we have tried to concentrate mainly on the subject of database representation and query translation of System R-like database management systems. Some estimates of the storage requirements and performance gains are given in this paper. However, due to limited space, the detailed analysis is shown elsewhere in [22].
Role of incretin hormones in the regulation of insulin secretion in diabetic and nondiabetic humans
Authors: Holst Jens Juul , Gromada Jesper
Published: July 2004

The available evidence suggests that about two-thirds of the insulin response to an oral glucose load is due to the potentiating effect of gut-derived incretin hormones. The strongest candidates for the incretin effect are glucose-dependent insulinotropic polypeptide (GIP) and glucagon-like peptide 1 (GLP-1). In patients with type 2 diabetes, however, the incretin effect is lost or greatly impaired. It is hypothesized that this loss explains an important part of the impaired insulin secretion in patients. Further analysis of the incretin effects in patients has revealed that the secretion of GIP is near normal, whereas the secretion of GLP-1 is decreased. On the other hand, the insulintropic effect of GLP-1 is preserved, whereas the effect of GIP is greatly reduced, mainly because of a complete loss of the normal GIP-induced potentiation of second-phase insulin secretion. These two features, therefore, explain the incretin defect of type 2 diabetes. Strong support for the hypothesis that the defect plays an important role in the insulin deficiency of patients is provided by the finding that administration of excess GLP-1 to patients may completely restore the glucose-induced insulin secretion as well as the β-cells' sensitivity to glucose. Because of this, analogs of GLP-1 or GLP-1 receptor activations are currently being developed for diabetes treatment, so far with very promising results.
High- and low-affinity transport ofl-leucine andl-DOPA by the hetero amino acid exchangers LAT1 and LAT2 in LLC-PK1renal cells
Authors: Soares-da-Silva Patrício , Serrão Maria Paula
Published: July 2004

The present study examined the functional characteristics of the inward and outward l-[14C]DOPA and l-[14C]leucine transporters in LLC-PK1cells. Uptake was initiated by the addition of Hanks' medium with a given concentration of l-[14C]DOPA or l-[14C]leucine. Saturation experiments were performed in cells incubated for 6 min with 0.25 μM concentration of the substrates in the absence and the presence of increasing concentrations of the nonlabeled substrates. Fractional outflow of intracellular l-[14C]DOPA or l-[14C]leucine was evaluated in cells loaded with 2.5 μM l-[14C]DOPA or 1 μM l-[14C]leucine for 6 min and then the corresponding efflux was monitored over 24 min. The high-affinity ( Km= 5.1 μM) uptake of l-[14C]leucine and the low-affinity ( Km= 120.0 μM) uptake of l-[14C]DOPA were largely promoted through a Na+-independent transporter. The uptake of the substrates was insensitive to N-(methylamino)-isobutyric acid but competitively inhibited by 2-aminobicyclo( 2 , 2 , 1 )-heptane-2-carboxylic acid (BCH). l- And d-neutral amino acids, but not acidic and basic amino acids, markedly inhibited l-[14C]DOPA and l-[14C]leucine accumulation. The uptake of l-[14C]leucine was a pH-insensitive process, whereas that of l-[14C]DOPA was sensitive to pH. The efflux of l-[14C]DOPA and l-[14C]leucine was markedly increased ( P < 0.05) by l-cysteine, l-leucine, BCH, and l-DOPA but not by l-arginine. RT-PCR detected LAT1 and LAT2 transcripts in LLC-PK1cells. It is concluded that LLC-PK1cells express both LAT1 and LAT2 transcripts and transport l-[14C]leucine through the Na+-independent pH-insensitive and high-affinity LAT1 transporter, whereas l-[14C]DOPA is mainly transported through the Na+-independent pH-insensitive and low-affinity LAT2 transporter and a minor component through a Na+-dependent transporter.
Cold ischemic injury of transplanted kidneys: new insights from experimental studies
Authors: Salahudeen Abdulla K.
Published: July 2004

Kidney transplantation is the preferred and definitive treatment for end-stage renal disease (ESRD), and kidneys from deceased donors are a major source for it. These kidneys are routinely cold stored to prolong viability, which, however, when prolonged can cause injury, resulting in reduced graft function and survival. Recent experimental studies have identified the release of iron and free radicals, activation of calpain, and formation of F2-isoprostanes as important components of cold ischemic injury, as are the swelling of mitochondria and activation of mitochondrial apoptotic pathways. Moreover, studies have also suggested that fortifying the storage solution with deferoxamine or preconditioning the donor kidneys with hemeoxygenase-1 may prove viable clinical strategies to limit cold ischemic injury. This review will summarize these and other new experimental data that have implications for reducing cold ischemic transplant injury, a step necessary to improve deceased-donor allograft survival.
New insights into the pathophysiology of the dysnatremias: a quantitative analysis
Authors: Nguyen Minhtri K. , Kurtz Ira
Published: July 2004

Recent theoretical considerations have played an important role in advancing our understanding of the physiological mechanisms responsible for perturbing the plasma water sodium concentration ([Na+]pw) in health and disease. Central to these considerations is the original empirical relationship between the [Na+]pw and total exchangeable sodium (Nae), total exchangeable potassium (Ke), and total body water (TBW) initially discovered by Edelman and colleagues (Edelman IS, Leibman J, O'Meara MP, and Birkenfeld LW. J Clin Invest 37: 1236–1256, 1958). The non-zero values of the slope and y-intercept in the Edelman equation are a consequence of the effects of the osmotic coefficient of Na+ salts at physiological concentrations and Gibbs-Donnan and osmotic equilibrium. Moreover, in addition to Nae, Ke, and TBW, the physiological components of the y-intercept in this equation play a role in modulating the [Na+]pw and in the generation of the dysnatremias. In this review, the pathophysiological mechanisms underlying the generation and treatment of the dysnatremias are analyzed theoretically and quantitatively. Importantly, the non-zero values of both the slope and y-intercept in the Edelman equation result in several theoretical predictions that can be tested experimentally and have been mathematically incorporated into recently derived equations used to analyze both the generation and the optimal treatment of the dysnatremias. In addition, we review current concepts regarding 1) the role of Gibbs-Donnan and osmotic equilibrium in the determination of the [Na+]pw; 2) the modulating effect of osmotically inactive exchangeable Na+ and K+ on the [Na+]pw; 3) the effect of glucose on the [Na+]pw as reflected by changes in Nae, Ke, and TBW as well as changes in several components of the y-intercept resulting from the hyperglycemia; and 4) the complex role of K+ in modulating the [Na+]pw.
Homocysteine clearance and methylation flux rates in health and end-stage renal disease: association withS-adenosylhomocysteine
Authors: Stam Frank , van Guldener Coen , ter Wee Piet M. , Kulik Willem , Smith Desirée E. C. , Jakobs Cornelis , Stehouwer Coen D. A. , de Meer Kees
Published: July 2004

Hyperhomocysteinemia is a risk factor for cardiovascular disease and occurs frequently in end-stage renal disease (ESRD), but its pathogenesis is poorly understood. We aimed to evaluate one-carbon flux rates of methionine and homocysteine (Hcy) in ESRD patients and healthy controls. Transmethylation (TM), remethylation (RM), and transsulfuration (TS), as well as Hcy clearance by TS (i.e., TS/plasma total Hcy concentration) and by RM (i.e., RM/plasma total Hcy concentration) were evaluated in relation to body composition, vitamins, and S-adenosylhomocysteine (AdoHcy) and S-adenosylmethionine (AdoMet) levels. After a fixed protein diet for 3 days, primed-continuous infusion of [2H3-methyl-1-13C]methionine was performed in the postabsorptive state in 12 hemodialysis patients and 16 healthy volunteers. Hcy clearance by TS (−80%, P < 0.001) and by RM (−77%, P < 0.001) in ESRD patients was decreased compared with healthy controls. The absolute flux rates of TM (−27%, P < 0.01) and RM (−28%, P = 0.02) were lower in the ESRD patients. After adjustment for age, TS was not significantly reduced. Whole blood AdoHcy was significantly elevated in ESRD and was a significant determinant of TM (standardized β = −1.24, P = 0.01) and RM (standardized β = −1.43, P = 0.03). In conclusion, patients with ESRD have impaired Hcy clearance by TS and RM. Elevated whole blood AdoHcy levels are associated with impaired RM and TM flux rates in these patients, and AdoHcy may be a key regulatory compound in one-carbon flux.
Orexin (Hypocretin) Effects on Constitutively Active Inward Rectifier K+ Channels in Cultured Nucleus Basalis Neurons
Authors: Hoang Q. V. , Zhao P. , Nakajima S. , Nakajima Y.
Published: July 2004

Orexins are excitatory transmitters implicated in sleep disorders. Because orexins were discovered only recently, their ionic and signal transduction mechanisms have not been well clarified. We recently reported that orexin A (OXA) inhibits G protein–coupled inward rectifier K+ (GIRK) channels in cultured locus coeruleus and nucleus tuberomammillaris neurons. Other work in our laboratory revealed the existence of a novel inward rectifier K+ channel (KirNB), which is located in cholinergic neurons of the nucleus basalis (NB) and possesses unique single-channel characteristics. The mean open time is considerably shorter in KirNB than in Kir2.0 channels. Constitutive activity and a smaller unitary conductance set KirNB apart from cloned Kir3.0 channels. Previously, we found that substance P excites NB neurons by inhibiting KirNB channels. Here we show that orexins suppress KirNB channel activity, likely leading to neuronal excitation. Electrophysiological studies were performed on cultured NB neurons from the basal forebrain. OXA application decreased whole cell conductance through a pertussis toxin (PTX)-insensitive G protein. The OXA-suppressed current was inwardly rectifying with a reversal potential around EK. Single-channel recordings of NB neurons revealed that constitutively active KirNB channels were transiently inhibited by OXA. Okadaic acid pretreatment abolished the recovery. The results suggest that OXA inhibition of KirNB is mediated by a PTX-insensitive G protein (i.e., Gq/11), which eventually results in channel phosphorylation. Recovery from this inhibition is by dephosphorylation. These results, taken together with our previous study, suggest that orexin receptors can elicit neuronal excitation through at least two families of inward rectifier K+ channels: GIRK and KirNB channels.
Modeling the Heart
Authors: Noble Denis
Published: July 2004

Models of the heart have been developed since 1960, starting with the discovery and modeling of potassium channels. The first models of calcium balance were made in the 1980s and have now reached a high degree of physiological detail. During the 1990s, these cell models were incorporated into anatomically detailed tissue and organ models.