bluuebunny/crossref_metadata_2025 huggingface dataset:
(Invited) Vionx Energy: A Small Company Leveraging Large-Company Innovations
Authors: Perry Mike L. , Darling Robert M.
Published: February 2020

Vionx Energy is a start-up company that was created to launch and commercialize redox-flow-battery (RFB) systems for grid-scale energy-storage applications. Vionx has an exclusive license to innovative RFB technology that was originally developed and demonstrated by United Technologies Research Center (UTRC). The Vionx business model is different than most start-up companies and this innovative business model will be the primary focus of this presentation. Vionx Energy has brought together a number of partners with deep expertise in technology, energy, manufacturing, and financing to produce, market, and deploy groundbreaking energy-storage technology in an efficient and effective manner. The unique relationship brings together six global companies— United Technologies Corp. (UTC), Starwood Energy Group, Siemens, 3M, VantagePoint Capital Partners and Jabil. Some of the key advantages of this unique business model will be highlighted, with an emphasis on UTRC’s ongoing role as a source of electrochemical innovations that can enable Vionx to offer future products with increasingly improved performance and cost.

Acknowledgements

Thanks to the organizers of this Symposia for the invitation to present. The authors would also like to thank their collaborators at Vionx Energy and UTRC. Past funding from U.S. Department of Energy, Advanced Research Projects Agency - Energy (ARPA-E) under Award Number DEAR0000149 helped to accelerate UTRC’s initial work on flow batteries, and is also gratefully acknowledged.
Center Approach to Accelerate Technology Commercialization
Authors: Botte Gerardine G
Published: February 2020

Introduction

 

The Center for Electrochemical Engineering Research at Ohio University (CEER) is dedicated to electrochemical research and development, innovation, education, and economic growth [1]. The Center focuses on providing out of the box solutions to the problems encountered by chemical and electrochemical industries. The mission of the Center is to: (1) Develop solutions to global problems (sustainable food, energy, water, air) through an electrochemical approach; (2) Educate future generations of experts in electrochemistry and electrochemical technologies; (3) Be a resource to industry and government on policy issues where electrochemical technologies can provide solutions; (4) Disseminate scientific knowledge on electrochemistry and electrochemical technologies; and (5) Contribute to economic growth.

CEER has implemented a novel approach to accelerate technology commercialization from the University. The approach involves technology marketing and commercialization in parallel with its development through a combination of state programs and Industry/University partnerships. Through this approach, challenges in market acceptance get identified early during the technology development roadmap.

In this talk, the approach will be discussed under the context of the development of the electrolysis of coal for the production of high value products.

References [1] Ohio University Center for Electrochemical Engineering Research, https://www.ohio.edu/engineering/ceer/index.cfm, (accessed 04/18/2016).
(Invited) Defect Evolution during Silicon Smartcut™
Authors: Rieutord François , Tardif Samuel , Mazen Frédéric , Landru Didier , Kononchuk Oleg
Published: February 2020

We have studied the development of cracks in gas-implanted silicon, from nano-scale to wafer-scale which is at the heart of the SmartCut™ technology.

We will discuss the results of X-ray scattering experiments that allow the monitoring of growth of nanometer-size cavities (platelets) from implantation to their full development where they reach sizes of several tens of nanometers. The nucleation, growth and coarsening mechanisms of these nanometer size platelets are interpreted within the Ostwald ripening framework.

 At larger annealing times, some micron-size defects called microcracks appear, and experience again some competitive growth, dominated by coalescence. The growth of these micron-size objects depends on their interactions with smaller-size platelets. The modelling of this interaction can explain the dependance of split time with temperature. Microcrack development is a key step in the SmartCut™ process.

Finally the propagation of the fracture front will be discussed. We will discuss the velocity dependence of the crack front with temperature and present some new measurements of dynamic crack opening displacement.

Figure 1
High Electron and Hole Mobility by Localized Tensile & Compressive Strain Formation Using Ion Implantation and Advanced Annealing of Group IV Materials (Si+C, Si+Ge & Ge+Sn)
Authors: Borland John O
Published: February 2020

Since the 90nm node the industry has been using S/D-stressor for strain-channel formation and increased hole & electron mobility.  The S/D-stressor strain-Si method required optimizing the deep S/D junction with the shallow SDE implant junction.  PMOS used recess etch eSiGe for p+ S/D tensile strain with precise lateral gate overlap distance control to induce channel compressive strain for increased hole mobility in Si while NMOS n+ S/D compressive strain is formed by deep amorphous implant with carbon and stacking fault dislocation defects that induces channel tensile strain for increased electron mobility in Si.  With the switch in transistor design from 2-D planar to 3-D FinFET by the industry at the 22nm and 14/16nm nodes, increasing eSiGe Ge content above 55% has reached it’s limit in strain-Si S/D-stressor of -3GPa for hole mobility improvement therefore requiring higher mobility channel material at 10nm and beyond by using: 1) relaxed >70% SiGe to 100% Ge or 2) compressive strain >50% SiGe to 100% Ge for higher hole mobility.  Higher electron mobility requires: 1) relaxed >95% SiGe to 100% Ge, 2) tensile strain-Si on >25% relaxed-SiGe or 3) tensile strain >50% SiGe to 100% Ge.   Using CVD epitaxial growth of SiGe and Ge requires thick SRB (strain relaxed buffer) epilayers by blanket or selective epitaxial growth but this results in threading dislocation in the 106 to 109 /cm2 level results in high n+ and p+ junction leakage.  The reported targets for NMOS is 2% tensile channel strain of >1.5GPa while for PMOS, 2% compressive channel strain of >-1.5GPa at 7nm node [1].

This paper will review strain-Si and strain-Ge formation by ion implantation and advanced annealing to form tensile and compressive strain channel for improved electron and hole mobility in Group IV materials.  Carbon and Si implants was used to form surface tensile strained-channel SiC, GeC and GeSi material while Ge and Sn implants was used to form surface compressive strained-channel SiGe, SiGeSn and GeSn material.  Improved hole mobility (µh) by >4x and electron mobility (ue) by >2x have been reported by use of implantstrain formation [2,3].

References

1] R. Kim et al., IEDM-2015, paper 34.1.

2] J. Borland et al., IWJT-2013, paper S4-4, p.49.

3] J. Borland et al., IWJT-2015, paper S2-1, p.12.
(Invited) Significant Reduction of Leakage Currents in Reverse-Biased Ge n+/p Junctions by Taking Care of Peripheral Passivation Layer
Authors: Liu Chi , Ikegaya Hiroki , Nishimura Tomonori , Toriumi Akira
Published: February 2020

Drastic enhancement of electron mobility and deep understanding of carrier transport in Ge MOSFETs have been made thanks to a significant reduction of major extrinsic carrier scattering sources such as Dit
[1] and surface roughness [2]. Furthermore, EOT scaling in Ge gate stacks [3] in addition to the gate stack reliability [4] have also been demonstrated. One of the remaining big challenges in Ge MOSFETs is rather high leakage currents at n+/p junctions. We recently found that oxygen atoms in Ge substrate have an appreciable effect on reverse-biased n+/p junction leakage current. This result is good news for Ge technology [5].

In this presentation, we discuss the leakage current mechanism in Ge n+/p junctions. We prepared n+/p junctions with various areas, and investigated the dependence of the leakage currents both on area and perimeter length, by changing the peripheral passivation layer. We found a dramatic effect of the passivation layer on the reverse-biased junction leakage current. By taking care of the passivation layer, we demonstrate more than 106 magnitude difference in the on/off ratio at n+/p junctions biased at V=|1| V , which is, to our knowledge, the highest ratio in the conventional planar n+/p junctions.

It is true that the junction leakage is intrinsically poor in Ge due to a narrower energy band gap, but this paper strongly suggests that the poor quality of Ge n+/p junctions fabricated in the current technology is not intrinsic but quite process and materials dependent.

Thus, it is expected that Ge CMOS technology including junction leakage current will be further improved by detailed understanding of Ge properties.

[1] C. H. Lee et al., IEEE TED-58(2011) 1295.

[2] T. Nishimura et al., Appl. Phys. Exp. 5(2012) 121301.

[3] C. Lu et al., Dig. VLSI Tech. Symp. (2015) 2.4.

[4] C. Lu et al., Tech. Dig. IEDM (2015). 14.6.

[5] A. Toriumi et al., ECS-T, 69(5) 287 (2015).
High Purity Analysis of Low Melting Point Such As Gallium By Glow Discharge Mass Spectrometry
Authors: Yoon Jaesik
Published: February 2020

Recently, the market demand for high-purity metal is increased and purification method of the gallium high productivity is required. Gallium have low melting point (29.76 °C) and super cooling properties and that property was not applied to zone refining method of the ordinary. Therefore, we produced zone refining system for low melting metal by using Direct Cooling and Indirect heating. Purification of 4N gallium was carried out zone refining process. Depending on the refining process up to 5pass, the trace metal impurities such as B, Al, S, Cr, Fe, Ni and Si decrease 4N to 6N. We adopted GD90(MSI, UK) to the measurement of impurities in high purity Gallium metal for prevent gallium melt. GDMS, especially GD 90 is a powerful analytical method capable of analyzing solid samples without chemical decomposition step and analyzing a low-melting metal by adopting liquid nitrogen cooling and slow sputter method.
Electrical Characterization of Defects Introduced By Electron Beam Deposition in n-GaAs
Authors: Tunhuma Shandirai , Diale Mmantsae , Legodi Matshisa , Auret Danie
Published: February 2020

Metallization is an important processing step in the microelectronic and photovoltaic industry. Electron beam deposition is a popular method for depositing metals because of its ability to deposit metals at a more controllable rate. The disadvantage of electron beam deposition is that this technique introduces defects in n-GaAs. Recent research has pointed out to discrete breathers as the possible mechanism of defect formation during metallization. In this work, the fundamentals of energy transfer in GaAs, from electrons with sub-threshold energies were investigated. We have used deep level transient spectroscopy (DLTS) to characterize the defects introduced in n-GaAs during electron beam deposition (EBED) of tungsten Schottky barrier diodes. EBD induces the E0.43 and E0.49 defects. An analysis of the conditions under which the defects are formed was done to distill a number of possible defect formation mechanisms using the experimental evidence obtained.
Mechanical/Structural Properties of the Key Thin Film Materials Ag, Cu, & Ni for Electronics Applications
Authors: Mohammed Yousuf , Josell Daniel , Baumgart Helmut , Elmustafa A A
Published: February 2020

Thin metallic films and coatings of Ag, Cu, and Ni for interconnect and contact in next generation nanoelectronic are expected to have high conductivity, high temperature stability, good ohmic contacts to both p- and n- type semiconductors, and also superb mechanical properties. These metallic thin film are used in a variety of electronic applications due to their low cost of production, non-toxicity and excellent electrical conductivity. However, their applications in nanoelectronics are still limited due to diffusion into the commonly used silicon substrates and the tendency of developing oxides under atmospheric conditions. Thin oxide layers form immediately on metallic films surfaces’ upon contact with air even at room temperature. Thin metallic oxide films `tend to exhibit brittle behavior with a sharp jump in the mechanical properties such as hardness and modulus and results in high resistivity. Although the formation of oxides is still perceived as the primary impediment in using thin metallic films in nanoelectronics, thin metallic films exhibit promising applications in large-area electronics such as memories, MEMS, and microprocerssors.

Metallic films of Ag, Cu, and Ni each of 150, 300, 600 and 1000 nm thick were deposited on Si using E-beam evaporation and deposition technique. A shutter was used to successively cover increments of 1² of the wafer at a time, starting with the wafer fully uncovered. A thin titanium layer of 10 nm is first deposited over the entire Si wafers followed by 150, 300, 600, and 1000 nm of the 2² target. Vacuum conditions at the start were ~1x10-7 torr and reached as high as 2x10-6 torr during the copper deposition due to outgassing. Similar vacuum conditions were maintained for the other films.

The Ag, Cu, and Ni films thickness were verified using field emission scanning electron microscopy. A sample cross sectional FE-SEM of the 150 nm thick Ag film is shown in Figure1. Nanocrstalline grain structure formation is observed to dominate the crystal film growth. The nanomechanical properties were measured using nanoindentation to determine the modulus and hardness of the Ag, Cu, and Ni films. Indentations of 1/3 and 2/3 of the film thickness in addition to 2 µm deep indents were performed on each film to study the film properties irrespective of the Si substrate influence as well as the substrate influence on the mechanical properties. Figures 2 and 3 depict hardness versus normalized depth of indentation to film thickness for Ag and Cu. The hardness increases as the film thickness decreases and remains nearly flat (no size effects) for the same film with depth of indentation except for the very thin films as they suffer what is known as tapping effect [1].

References:

[1] David E. Stegal, Md. Abdullah Mamun, Bryan Crawford, and Abdelmageed Elmustafa, J. Mater. Res., Vol. 27, No. 12, Jun 28, 2012.

Figure 1
(Invited) Mechanism of Low Temperature ALD of Al2O3 on Graphene Terraces
Authors: Kwak Iljo , Park Jun Hong , Grissom Larry , Fruhberger Bernd , Kummel Andrew
Published: February 2020

2-D materials are single or trilayer networks of atoms, such as carbon, hBN, and MoS2. 2D materials are attractive for future electronic devices because they provide ballistic transport of charge carriers as well as carrier confinement. These novel devices require ultrathin and defect-free dielectric layers as gate or channel insulators. However 2D semiconductors such as graphene, boron nitride, and metal dichalcogenides (MDCs) are un-reactive; thus, the dielectric layer selectively nucleates on defect sites or step edges. In the conventional atomic layer deposition (ALD) process on graphene or other 2D semiconductors, such non-uniformly grown oxides can create large leakage currents. In the present report, polar metal phthalocyanine molecules have been employed as an ALD template for high nucleation density deposition of dielectric layers. By combining in-situ scanning tunneling microscopy (STM) and fabrication graphene devices, the insulating property and growth mechanism of the dielectric layer have been elucidated. Metal Ptholocyanines have been used to deposit gate oxides on graphene, MoS2, and WSe2. To deposit an ultrathin dielectric onto WSe2, monolayer titanyl phthalocyanine (TiOPc) is deposited by molecular beam epitaxy (MBE) as a seed layer for atomic layer deposition (ALD) of Al2O3 on WSe2. TiOPc molecules are arranged in a flat monolayer with four-fold symmetry as measured by scanning tunneling microscopy (STM). ALD pulses of trimethyl aluminum and H2O nucleate on the TiOPc, resulting in a uniform deposition of Al2O3, as confirmed by atomic force microscopy and cross-sectional transmission electron microscopy. The field-effect transistor (FETs) formed using this process have a leakage current of 0.046 pA/µm2 at 1 V gate bias with 3.0 nm EOT, which is lower leakage current than prior reports. The n-branch of the FET yielded a subthreshold swing of 80 mV/decade.
(Invited) Reliability Study on Layered 2D Insulator
Authors: Nagashio Kosuke
Published: February 2020

Hexagonal boron nitride (h-BN), an insulating layered material with a wide band gap, is widely utilized as the substrate and gate insulator to achieve high carrier mobility in layered channel materials, especially graphene. However little study has been conducted on the statistical analysis of the breakdown voltages and the breakdown mechanism. Generally the dielectric breakdown of SiO2, conventional three-dimensional (3D) amorphous oxides is simply explained by a percolation model. It has not been determined whether the dielectric breakdowns of 2D layered materials follow the general breakdown phenomena for 3D amorphous oxides. In this study, the anisotropic dielectric breakdown of h-BN is studied.

We have found that the dielectric breakdown in c axis direction using a conductive atomic force microscope proceeded in the layer-by-layer manner [1]. The obtained dielectric field strength was ~12 MV/cm, which is comparable to the conventional SiO2. On the other hand, to estimate the dielectric field strength in a direction perpendicular to c axis, voltage is applied to a relatively thick h-BN (5-60 nm) through Cr/Au electrodes fabricated on the h-BN by EB lithography. We realized that the absorbed water on h-BN significantly affect the IV characters and the breakdown voltage. After the adsorbed water was removed by the heating in vacuum, the dielectric field strength was determined to be ~ 3 MV/cm, which is the same order as that in c axis direction. This value could be increased to be ~5 MV/cm when we consider the effect of electric field concentration around the metal electrode. This difference in dielectric filed strength for two directions is due to the highly-anisotropic nature of dielectric constant[2].

Ref. [1] Y. Hattori, et al., ACS nano
2015, 9, 916. [2] Y. Hattori, et al., in preparation.
Self-Assembled Monolayer-Based Gate Dielectrics for MoS2 FETs
Authors: Kawanago Takamasa , Oda Shunri
Published: February 2020

In this study, self-assembled monolayer (SAM)-based gate dielectrics is applied to the fabrication of molybdenum disulfide (MoS2) field-effect transistors (FETs). A fabrication process of MoS2 FETs involves the selective formation of a SAM on aluminum oxides and the manual transfer of MoS2 flakes. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were attained with the ultrathin SAM-based gate dielectrics. These results indicate the superior interfacial properties of the MoS2/SAM structure. Cross-sectional transmission electron microscopy revealed a flat and abrupt interface of the MoS2/SAM structure. It is found that the SAM-based gate dielectrics is applicable to the fabrication of low-voltage MoS2 FETs. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.
Development of High Performance p-Type Bisbte Based Alloys By Powder Metallurgy
Authors: Madavali Babu , Lee Chul-Hee , Shin Dong-Won , Olu Emmanuel Femi , Hong Soon Jik
Published: February 2020

Due to the rapidly increasing global demands for alternative energy sources, thermoelectric materials are receiving great attention compare to other renewable energy sources due to the exhibiting excellent characteristic features such as no moving parts, silent, reliable, environment freely and minimum maintenance. TE devices are the semiconductor systems that can either directly convert thermal energy into electricity for power generation, or perform cooling or heating with electric power.

So far, single (unidirectional) crystal growth techniques such as zone melting and czochralski were used to produce TE material in which the maximum ZT of TE materials almost unity ( ZT= 1) was obtained. However, these crystals having cleavages along the basal plane and got easily fractured. Nevertheless, improving mechanical properties was elusive so far due to exhibiting coarse grain size and gets easily fractured during the manufacturing. Recent studied showed that the powder metallurgy methods (PM) have been attaining best TE properties as well as mechanical properties. TE alloys by gas atomization is one of the well adopted processes, can easily make powders in large scale.

In this research, we have fabricated thermoelectric alloys by gas atomization then subsequently consolidated by SPS. The phase analysis, and microstructure of powders and bulks were characterized by X-ray diffraction and scanning electron microscopy respectively. The temperature dependence of electrical resistivity and Seebeck coefficient were systematically investigated from room temperature to 500 K. The figure of merit, ZT is calculated from the measured Seebeck coefficient, electrical conductivity, and thermal conductivity values.
Plasma-Enhanced Atmospheric-Pressure Spatial ALD of Al2O3 and ZrO2
Authors: Creyghton Yves , Illiberi A. , Mione A. , van Boekel W. , Debernardi N. , Seitz M , van den Bruele Fieke , Poodt P. , Roozeboom Fred
Published: February 2020

Spatial Atomic Layer Deposition is emerging as an industrial thin-film manufacturing technology [1]. The technique is becoming so popular since it combines all advantages of conventional ALD (ultimate control of layer thickness and conformality over 3D-topologies, superior film material properties) with far higher deposition rates and processing at atmospheric pressure by means of spatial separation of the reactive gases. The integration of non-thermal plasma in spatial ALD reactors is expected to widen the thermal ALD process window towards lower operation temperatures and to enable to growth of specific materials requiring radicals (O, N, H, OH, NH, etc.). To this end, novel plasma sources with exceptional dimensional and chemical stability are required which provide the flow geometries optimized for efficient radical transport.

This paper reports on our preliminary efforts to provide and examine the required linear scalable plasma sources. The effectiveness of close-proximity direct and remote plasma sources [2] are demonstrated using the deposition of thin dielectric films of Al2O3 and ZrO2 at temperatures ranging from room temperature to 100 oC. Both direct and remote plasma sources of the so-called surface DBD-type (Dielectric Barrier Discharge) can be applied for spatial ALD using the usual metal precursors and O2/N2 plasma. The advantage of the remote plasma option is avoidance of electrical source-substrate interaction which is often the cause of layer or substrate damage as a result of filamentary plasma discharges impacting the substrate.

 

P. Poodt, et al., J. Vac. Sc. Technol. A, 30 010802-1 (2012).

Y. Creyghton et al., Patent publication WO2015199539, Dec. 30 (2015).
Refractory Solar Selective Coatings Synthesized By Atomic Layer Deposition
Authors: Mane Anil U. , Libera Joseph A. , Yanguas-Gil Angel , Avila Jason R , Elam Jeffrey W
Published: February 2020

One of the most economically viable methods for solar power uses an array of mirrors to concentrate sunlight onto a central receiver tower. The receiver surface heats up, and this heat is used to boil water and drive turbines that generate electricity. To improve the efficiency of these “power tower” facilities, the receiver must operate at higher temperatures and this requires developing high performance coatings. These coatings must be spectrally selective in order to absorb all of the visible light while emitting as little infrared radiation as possible (low emissivity). In addition, these coatings must be refractory to endure decades of high temperature operation under ambient conditions. We are pursuing a novel strategy to develop refractory solar selective coatings using ALD. Our strategy uses thin film nanocomposites composed of conducting metallic nanoparticles in a dielectric matrix. These films are prepared by combining the ALD processes for a metal (e.g. W using Si2H6/WF6) with that of an oxide (e.g. Al2O3 using TMA/H2O). The resulting nanocomposites are similar in structure to cermets, and consequently have tunable optical properties that can be adjusted to achieve a high solar selectivity. In addition, we use these ALD coatings to infiltrate inverse opal scaffolds which serve as photonic crystals to further enhance the spectral selectivity. In this presentation I will describe our ongoing work synthesizing and characterizing these refractory solar selective coatings, and also present results of testing their high temperature performance.

Figure 1
Tuning the Performance of Pt/HfO2/Ti/Pt ReRAM Devices Obtained from Plasma-Enhanced Atomic Layer Deposition for HfO2 Thin Films
Authors: Hardtdegen Alexander , Zhang Hehe , Hoffmann-Eifert Susanne
Published: February 2020

The market of portable electronics and Green IT solutions demands for non-volatile memory circuits with high speed data access, high reliability, and low power consumption. Resistive switching random access memories (ReRAM) based on the valence change mechanism (VCM) represent a promising concept. VCM-type memristive devices are generally based on transition metal oxide thin films sandwiched between metal electrodes that differ in respect of work function and oxidation enthalpy. ReRAM cells built from insulating metal oxides with a high band gap, like e.g. TiO2, HfO2, Al2O3, typically require an electroforming step to enable resistive switching. Decisive for a stable device operation are a homogeneous microstructure and a controlled defect density in the oxide films of a few nm in thickness. Atomic layer deposition (ALD) can fulfill these requirements by its unique surface-reaction controlled self-limiting growth enabling a control of the film defect structure even for thicknesses in the nm-regime and for low growth temperatures.

During the electroforming process, an electronically conducting filament is formed a significantly increased density of oxygen vacancies. The stable VCM-type resistive switching is related to drift/diffusion processes of oxygen vacancies (or oxygen ions, respectively) which depend on the oxidation/reduction enthalpies of the materials involved in the switching event.

In this presentation we are going to discuss possibilities to tune the resistive switching performance of nanostructured ReRAM devices by means of a variation of metal oxide bilayer structures with respect to the layer thickness and the stack sequence. This study was performed on various bilayers based on combinations of TiO2/Al2O3 [1] and TiO2/HfO2 [2] with a total thickness < 10 nm integrated into nano-crossbar structures with a size of 100 x 100 nm2. Addressing the ReRAM device performance we discuss effects on the electroforming voltage, necessary SET- and RESET-voltages, achievable resistance ratios, switching stability and variability. In addition, changes in the resistive switching polarity, i.e. from bipolar to complementary-type, which have been observed for certain stacks, are discussed.

This work was supported in part by the Deutsche Forschungsgemeinschaft (SFB917).

References:

[1] H. Zhang, N. Aslam, M. Reiners, R. Waser, S. Hoffmann-Eifert, “Atomic Layer Deposition of TiOx/Al2O3 Bilayer Structures for Resistive Switching Memory Applications”, Chemical Vapor Deposition, vol. 20, pp. 282-290, 2014.

[2] A. Hardtdegen, C. La Torre, H. Zhang, C. Funck, S. Menzel, R. Waser, S. Hoffmann-Eifert, “Internal Cell Resistance as the Origin of Abrupt Reset Behavior in HfO2-based Devices determined from Current Compliance Series”, Memory Workshop (IMW), 2016 8th IEEE International, accepted, 2016.
A High Mobility of p-Type Sno Thin Films Grown By Atomic Layer Deposition for Thin Film Transistors
Authors: Kim Soo Hyun , Pyeon Jung Joon , Kim Seong Keun
Published: February 2020

Oxide semiconductors have attracted great interest as channel materials for use in various emerging electronic applications including transparent and flexible displays, sensors, logic devices, and so on. Great progress has been made in n-type oxide semiconductors for thin film transistors (TFTs), which show superior properties such as high electron mobility and Ion/off ratio. Despite rapid development of n-type oxides, progress in the development of p-type oxides has been delayed. Only a few oxides including SnO, CuO, and NiO have been reported for p-type TFTs, and not yet sufficient for applications. Furthermore, most of the p-type oxides have been fabricated by a reactive sputtering technique, which is not applicable in industry.

In this study, we propose atomic layer deposition (ALD) of stable and high quality p-type SnO thin films for p-type TFTs. The SnO films were deposited with dimethylamino-2-methyl-2-propoxy-tin(II) and H2O as Sn and O sources, respectively. The growth of the SnO films was performed in a growth temperature range from 150 to 210 oC. From the XPS analysis, the ALD-grown SnO films are mainly composed of Sn2+ ions and O2- ions, and a peak from Sn4+ ions in the XPS spectra is not observed. As increasing the growth temperature, the Hall mobility increased from 1.26 to 3.8 cm2/Vs and Sn/O atomic ratio of the films approached the stoichiometric value from less unity (O-rich phase). We also fabricated TFTs with the ALD-grown SnO layer to characterize the properties of the p-channel layer in the TFTs. To exclude the influence of environment, we deposited a 15 nm-thick Al2O3 passivation layer on the TFTs by ALD. The field effect mobility increased with increasing the growth temperature, consistent with the change in the Hall mobility. A high field effect mobility of 1.5 cm2/Vs was achieved at a growth temperature of 210 oC. A high Ion/off ratio of ~ 106 was also achieved in the SnO film grown at 210 oC. This is attributed to the formation of dense and stoichiometric SnO films at 210 oC.
(Invited) Nano-Structure Controlled Very Low Resistivity Cu Wires By High Purity Plating and Realization of High Performance Lsis
Authors: Onuki Jin
Published: February 2020

Resistivity increase in nano-level Cu wires is becoming critical issue for high speed ULSIs. In order to lower resistivity of Cu wires, researchers investigated how to reduce the thickness of high-resistivity barrier metals surrounding Cu. However, area percentage of barrier metals to entire Cu wires is less than 20%. This means that thinning barrier metals is not so effective against resistivity increase. Hence, reduction of resistivity in Cu wires is much more important. We have established the new manufacturing process utilizing very high-purity 9N electrolyte and additives to control nano-structures of Cu wires, and realized Cu wires with resistivity 50% lower than those made with conventional process used for practical use. We also have ascertained the reason for getting very low resistivity Cu wires by STEM analyses and first-principle simulation.
Bottom-up Cu Filling of through-Silicon-Via(TSV) with Single Additive
Authors: Jin Sanghyun , Seo Sungho , Park Sangwoo , Yoo Bongyoung
Published: February 2020

Downscaling of the Cu interconnection was one of core technologies to enhance the performance of semiconductor devices. However, the shrinkage of Cu interconnection will face the limitation due to the physical limitation of Si based semiconductor device. In order to maintain the development in semiconductor device, the 3D interconnection is emerged, and the through-Si-via(TSV) interconnection is noticed. Large integration, high efficiency and high performance could be realized by composing the 3D integrated circuit with TSV. Furthermore, hetero interconnection between the logic and memory was possible by accepting the TSV technology.

The TSV filling process which plating the Cu in the TSV by electrodeposition was one of core process in TSV process due to high cost and difficulty. During the TSV filling process, bottom-up Cu filling which the Cu filled from the bottom of via to the top, should be occurred for avoiding the void formation and decreasing the processing time. In other to achieve the bottom-up filling, various additives were added in the electrolyte. The suppressor inhibited the deposition rate of Cu at the top surface and the sidewall of TSV. The accelerator promoted deposition rate of Cu at the undermost bottom of TSV.

Theoretically, the bottom-up filling of TSV was initiated by suppression breakdown at the bottom of TSV.1-3 Simultaneous detachment of suppressor by high potential due to ion depletion at TSV bottom leads focus of current at bottom of TSV. Therefore, bottom-up TSV filling could be achieved by only using the suppressor. Moreover, it was reported that accelerator substitute the suppressor at the sidewall and disturbed the bottom-up filling.3

In this research, the characteristics of suppressor were systematically investigated to achieve the bottom-up Cu filling of TSV with only using the suppressor. The influence of suppressor concentration on the Cu electrodeposition was investigated by observing the CV curves and morphology of Cu deposit. The influence of suppressor concentration and current density on the bottom-up TSV filling had also been observed. Interesting changes in bottom-up TSV filling by changing experimental conditions were delicately analyzed. Finally, the bottom-up TSV filling was achieved with only using the suppressor. This leaded the perfect and fast void free filling of 60 μm deep TSV within 1000 seconds.

References

1.T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012).

2.D. Josell, D. Wheeler, and T. P. Moffat, J. Electrochem. Soc., 159, D570 (2012).

3.L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013).
Damascene Copper Plating Recipe Engineering for Defectivity, Health of Line (HOL) and Reliability Improvement
Authors: Ahmed Shafaat , Huang Qiang , Cheng Tien Jen , Findeis Paul , Koli Dinesh R , Troung Connie Nga , Grunow Stephan
Published: February 2020

A typical damascene copper plating is a multi-step process, including wafer entry, Cu nucleation, trench filling and thick overburden plating. During these steps, the most important parameters are found to be the entry bias voltage (Evolv), nucleation pulse current (MWE) and the first plating step. It has been observed that a higher bias voltage helps to protect the seed dissolution and therefore improves the slit voids. In addition, an optimized MWE coupled with the first filling current was found to be beneficial to achieve embedded void free plating. This benefit is believed to relate to a thin but uniform Cu nucleation, which provides good conductivity but still leaves enough space in the narrow trenches for Cu to be filled during the first plating step. Fig.1a shows hollow metals signature at 12:00 and 3:00 O’clock position on the post CMP polished wafer surface which were acquired from a defined coordinate of a test macro. However, 1b shows the hollow metals at these locations significantly improved due to the graded plating fill current density in the first few fill steps followed by a potentiostatic entry. In this paper, we will describe how plating recipe could be engineered to minimize plating related defects and improve the overall HOL and reliability for BEOL interconnects.

Fig.1(a) API images from the post CMP wafer surface shows hollow metal signature at 12:00 and 3:00 O’clock position. 1(b) shows the hollow metals at these exact same locations significantly improved due to the graded fill current plating.

Figure 1
(Keynote) Reflections on the Evolution of Metal Oxide Cathodes for Li-Ion Batteries
Authors: Thackeray Michael M.
Published: February 2020

Since the introduction of lithium-ion battery products in 1991, the versatile and ever expanding market has been dominated by systems with carbon-based anodes and metal oxide cathodes. This presentation will highlight the structural evolution of metal oxide electrodes in advancing lithium-ion technology over the past twenty five years and the stumbling blocks that still remain. A prognosis for further advances will be given.
Bridging the Gap Between Supercapacitors and Batteries By a New Material Based on Renewable Resource
Authors: Fichtner Maximilian , Gao Ping , Chen Zhi , Zhao-Karger Zhirong , Ruben Mario
Published: February 2020

A new material is presented, which is based on a porphyrin material and which delivers good specific capacities in the order of 180 mAh/g at an average voltage of approx. 3 V. The material can be charged and discharged at rates around 50 C which is in the range of supercapacitors.

By a simple chemical modification of the material, the typical issue of organic batteries, the degradation upon cycling, was greatly improved and 80% of the capacity was retained after 6,000 cycles. The material can be used as cathode or anode, or both. Charge and discharge can be done based on Li or other ionic shuttles such as Mg.

Figure 1
Effect of Lithium Content on Spinel Phase Evolution in Lithium-Rich Layered Oxides LixNi0.25Co0.10Mn0.65O(3.4+x)/2 (0.8 ≤ x ≤ 1.6) for Li-Ion Batteries
Authors: Choi Byungjin , Park Kwangjin , Song Jayhyok , Yeon Dong-Hee , Kim Jung-Hwa , Park SeongYoung , Kim Hyoun-Ee , Park Jin-Hwan , Doo Seokgwang
Published: February 2020

Lithium-rich oxides LixNi0.25Co0.10Mn0.65O(3.4+x)/2 (x=1.6, 1.4, 1.2, 1.0, 0.8) were synthesized and characterized for their structural, morphological, and performance as cathode materials in Li-ion batteries. The baseline composition x=1.4 had been previously determined as having the best electrochemical performance due to its small primary particle size and homogeneous distribution of nano-domains consisting of (C2/m) and (R3¯m) phases. In this study, the Rietveld refinement results indicate the presence of two phases at high lithium levels (x=1.6 and 1.4): Li2MnO3 (C2/m) and Li
M
O2 (
M
= Ni, Co, Mn) (R3¯m); the latter contains Ni2+ and Ni3+. At low lithium levels (x=1.2, 1.0, and 0.8) an additional spinel phase Li
M

2O4 (Fd3¯m) emerges, which is known to affect the electrochemical performance of the oxide. Structural analysis reveals that the spinel phase contains mixed transition metals Ni, Co, and Mn as [Li+,Co2+][Ni2+,Co3+,Mn4+]2O4. A low lithium level is found to induce primary particle growth, as well as Co and Ni segregation within the secondary particles. These results are expected to contribute to material optimization and commercialization of lithium-rich oxide cathodes.
Morphological and Chemical Control of Oxide Cathode Materials Based on Mn
Authors: Hu Linhua , Cabana Jordi
Published: February 2020

Oxides based on Mn redox couples continue to attract wide attention in lithium battery due to consideration of cost and safety. To bypass issues of capacity and durability associated with John-Teller distortions, substituents such as Ni and Co are introduced in the Mn or Li sites. Ni-Co-Mn ternary materials, e.g. LiNixMnyCozO2, are usually synthesized through methods that involve steps at high temperature, whether to react binary oxides or precursors such as hydroxides made by co-precipitation and other low temperature methods. High temperature calcination results in complex morphologies that hard to control, especially if refined nanoscale features are desired. Further, they inherently under thermodynamic driving forces and, thus, may miss possible intermediate or metastable phases.

Here, we report a one-step hydrothermal process to synthesize well-defined nanocrystals of binary Ni-Mn and ternary Ni-Mn-Co cathode materials. TEM showed their morphology varies between rod and octahedron depending on conditions. XRD and EDX revealed that nanorods are composed of layered Li[NixLi(1/3-2x/3)Mn(2/3-3/x)]O2, whereas the octahedra correspond to spinel-type LiMnxNixCo(2-2x)O4.

Their electrochemical property showed high voltage range 2-4.9v and large capacity at 150~200mAh/g. The uniform morphology provide the further potential for their surface functionalization with alumina and the quest for faster Li diffusion channels in the near future.
A Predictive Model of Lithium-Ion Electrode Fabrication, Including Mixing, Coating, Drying, and Calendering
Authors: Forouzan M. Mehdi , Gillespie Anthony , Lewis Nicholas , Mazzeo Brian A , Wheeler Dean R
Published: February 2020

The microstructure of commercially made lithium-ion battery electrodes is not necessarily optimal for cell performance. In an attempt to optimize the performance, detailed understanding of the microstructure is necessary. Factors that influence electrode microstructure include high-level variables such as composition and porosity; as well as detailed fabrication conditions that are part of the film-making, drying, and calendering steps.

Here we report on continuing efforts to model the particle-level microstructure of porous electrodes and how this relates to fabrication conditions [1]. LAMMPS, a molecular simulation code, was adapted for these mesoscale particle simulations. In particular we simulate an NCM lithium-ion cathode using a superposition of spheres to imitate active particles, carbon, binder, and solvent. Equations of motion coupled to inter-particle forces are solved to simulate particle motion and subsequent immobilization during fabrication steps.

Our model is uniquely able to capture the essential physics in both the slurry and dried film. Model results are validated by comparing to experimental results for microstructure, tortuosity, and mechanical properties like viscosity and elasticity. Such simulations are a first step in allowing us to predict electrode microstructure and therefore battery performance from fundamental fabrication conditions. This contributes to the long-term goal of this work, namely to increase the performance of electrodes by improved control of the manufacturing process.

This work was supported by the U.S. Department of Energy through the BMR program.

References:

[1] M. Forouzan et al., J. Power Sources 312, 172-183 (2016).

Figure 1: 

Sequence of images (top to bottom) showing simulated electrode coating process with slurry film (green) moving relative to blade (gray) at shear rate 250 s-1.

Figure 1
Investigation of the Conductivity Effect on Silicon Anode Performance for Lithium Ion Batteries
Authors: Yuca Neslihan , Doğdu Murat Ferhat , Cetintasoglu Mehmet Emre , Taskin Omer Suat , Avci Ipek
Published: February 2020

The early development on rechargeable lithium battery began with lithium (Li) metal and Sony put into the market the first lithium ion batteries in 1991. Since that date the graphite has been used as commercial anode with the practiable capacity of 250 mAh/g and it has been yet reached the 290 mAh/g in 2015 [1]. In the development of high capacity anode materials for lithium ion batteries, silicon is apparently very promising as anode material due to its high theoretical capacity ~4200 mAh/g. However, the huge volume change (~300%) occurs during the cycling and it results breakdown of the conductive network of the composite electrode. This causes the electrical contact problem between conductive agent and the current collector, resulting low Coulombic efficiency and poor capacity retention for silicon-based lithium ion batteries (LIBs).

Polypyrene (Ppr) polymer has much concern recently not only the conductivity and other electrical properties but also thermal stability and mechanical properties. In this study, the aim is to enhance the conductivity of Si electrode which is crucial for charge-discharge rate of a battery. The high conductivity provides fast charge-discharge and that is very important for consumer electronics and electric vehicle applications. For this purpose, the conductive Ppr was synthesized through the free-radical polymerization of the acrylate backbone in the presence of an initiator. It was used as a conductive polymer for silicon anode in LIBs. The conductivity of anode was also studied with different carbonecous additives (carbon black, super p and carbon nanotube). The cells were fabricated as half and full cell. Li was used as the counter electrode for half-cell and NCA was used as the cathode for full cell.

Table 1. Experimental results for the conductivity study of Si anode

Experiment No
Composition Ratio
Active Material
Binder
Conductive additive

1
90:10
Si
Ppr
-

2
85:15
Si
Ppr
-

3
85:10:5
Si
Ppr
CB

4
85:10:5
Si
Ppr
SP

5
85:10:5
Si
Ppr
CNT

6
85:10:5
Si
PVDF
CB
Comparative Study of Si-Ti Thin Films and Alloys As Lithium Ion Anodes
Authors: Wang Yukun , Liu Hui , Zhu Min , Obrovac Mark N
Published: February 2020

Si based materials have been intensively studied due to the high theoretical capacity of Si (2194 Ah/L, 3579 mAh/g [1, 2]) and applicable lithiation voltage (around 0.4 V [3]). To address the issues brought by severe volume change during the charge-discharge process, the concept of active-inactive Si based alloys has been developed. Si can form intermetallic compounds with some inactive (towards Li) metals, such as Fe, Co, Mn and Ni [4]. These inactive Si1-xMx phases dilute the expansion of Si and thereby improve electrode cycling performance. Recent reports suggested that the voltage curves of Si1-xMxalloys can be shifted by hundreds of millivolts, presumably due to the stress induced by the volume expansion of active Si while being bonded to the inactive phase [5].

In this work, Si1-xTix (0 ≤ x ≤ 0.4, Δx = 0.05) alloys were prepared both by ball milling and magnetron sputtering. The structure evolution of these alloys and their electrochemical performance as negative electrodes for lithium ion batteries were compared. The capacity dependence of the Si-Ti alloys on Ti content suggests that these alloys comprise an active Si phase and an inactive Si phase. A voltage shift was observed during the lithiation process of Si1-xTix thin-films. Increasing the Ti content (x ≤ 0.3) was found to gradually lower the lithiation voltage by a shift of up to 600 millivolts, while the average voltage during delithiation process remains constant. (Figure 1). The voltage shift during discharge suppresses the formation of the Li15Si4phase at full lithiation, resulting in improved cycling performance.

This presentation will discuss the structural and electrochemical characteristics of sputtered and ball-milled Si-Ti alloys and their relation to alloy reversible capacity and cycle life.

Acknowledgements

The authors acknowledge funding from NSERC and 3M Canada, Co. under the auspices of the Industrial Research Chair and Discovery grant programs. We also acknowledge the support of the Canada Foundation for Innovation, the Atlantic Innovation Fund and other partners that fund the Facilities for Materials Characterization managed by the Institute for Research in Materials. Yukun Wang acknowledges the support from SCUT Doctoral Student Short-term Overseas Visiting Study Funding Project.

 References

[1] M.N. Obrovac and L. Christensen, Electrochem. Solid-State Lett., 7 (5) A93, (2004).

[2] M.N. Obrovac and L.J. Krause, J. Electrochem. Soc., 154(2) A103, (2007).

[3] L. Baggetto, R.A.H. Niessen, F. Roozeboom, and P.H.L. Notten, Adv. Funct. Mater., 18(7) 1057 (2008).

[4] Z. Du, T.D. Hatchard, R.A. Dunlap and M.N. Obrovac, J. Electrochem. Soc.,
162 (9) A1858, (2015).

[5] Z. Du, S.N. Ellis, R.A. Dunlap and M.N. Obrovac, J. Electrochem. Soc.,
163 (2) A13, (2016).

Figure 1