bluuebunny/crossref_metadata_2025 huggingface dataset:
Real-Time Observation of Initial Thermal Oxidation on Si(110)-16x2 Surface by Photoemission Spectroscopy
Authors: Suemitsu Maki , Kato Atsushi , Togashi Hideaki , Konno Atsushi , Yamamoto Yoshihisa , Teraoka Yuden , Yoshigoe Akitaka , Enta Yoshiharu , Narita Yuzuru
Published: November 2006

Kinetics of initial oxidation of Si(110)-16x2 surface has been investigated by using real-time photoemission spectroscopy. One of the most striking features of Si(110) oxidation, in comparison with that of Si(001) surface, is the occurence of an extremely rapid oxidation in its early stage. Only 15 s after introduction of ~10^-5-Pa oxygen molecules, the Si(110) surface at 540 deg-C is already covered with 0.3-monolayer oxide. This rapid initial oxidation can be related to oxidation at or around the adatom clusters which are reportedly the major constituent of the 16x2 reconstruction on this Si(110) surface.
High Mobility Channels for Ultimate CMOS
Authors: Sadana Devendra , Koester Steve , Sun Y , Kiewra E. W. , Bedell Stephen W. , Reznicek A , Ott John , Fogel Keith , Webb D J. , Fompeyrine J. , Locquet J.-P. , Sousa M , Germann R
Published: November 2006

Integration of Ge as the p-FET channel material for 22 nm and beyond technology nodes is receiving increasing attention. Furthermore, there is a growing consensus in the CMOS industry that III-Vs channels for n-FETs should be closely evaluated. This review examines choices for Ge integration with Si, and describes recent results from III-V channels with a high- k/metal gate stack.
Geometry Dependence of Poly-Si Oxidation and its Application to Self-Align, Maskless Process for Nano-scale Vertical CMOS Structures
Authors: Cho Hoon , Kapur Pawan , Kalavade Pranav , Saraswat Krishna
Published: November 2006

Geometry dependent thermal oxidation rates of silicon/polysilicon on concave and convex surfaces are complex and need a better understanding. The complexity is a result of several competing effects, namely, volume expansion stress, area effects, stress from etch damage, and crystal orientation. In this paper we present a systematic study to decouple these effects using both experimental test structures and simulations. Among other things, the result of this work directly impacts CMOS gate stack processing on vertical MOSFETs. In addition, we use the differential oxidation rate understanding to describe a novel technique for self-aligned maskless process. We apply this to create a process for vertical CMOS structure, which is capable of self-aligning and resolving very small features without photolithography.
III-V MOSFET's with Advanced High k Dielectrics
Authors: Hong Minghwei , Kwo J. Raynien , Chen C. P. , Chang Y. C. , Huang M. L. , Lin C. F.
Published: November 2006

Ga2O3(Gd2O3), the novel oxide, which was electron-beam evaporated from a gallium- gadolinium-garnet target in UHV, has unpinned the GaAs Fermi level. Systematic heat treatments under various gases and temperatures were studied to achieve low leakage currents of 10-8 - 10-9 A/cm2 and low Dit's in the range of 4-9 x 1010 cm-2V-1 for Ga2O3(Gd2O3) on InGaAs. By removing moisture from the oxide, thermodynamic stability of the Ga2O3(Gd2O3)/GaAs hetero-structures was achieved with high temperature annealing, which is needed for fabricating inversion-channel MOSFET's. The oxide remains amorphous and the interface remains intact with atomic smoothness and sharpness. The mechanism of Fermi-level unpinning and the band parameters in atomic layer deposition (ALD)-Al2O3 ex-situ deposited on InGaAs were studied and unveiled. The work of inversion- channel, depletion- mode, and power GaAs MOSFET's using Ga2O3 (Gd2O3) as the gate dielectric was briefly reviewed.
Conductive AFM Measurements on Carbon Nanotubes and Application for CNTFET Characterization
Authors: Rispal Lorraine , Ruland Tino , Stefanov Yordan , Wessely Frank , Schwalke Udo
Published: November 2006

In this work we report results of conductive atomic force microscopy (C-AFM) measurements performed on carbon nanotubes (CNTs) which are the inherent part of fully functional carbon nanotube field-effect transistors (CNTFET). The CNTs are grown in-situ, directly in their final position between source and drain, in order to avoid complicated postgrowth alignment techniques. Our goal is to characterize the CNTs after growth.
Electrical Characteristics of Ge-Nanocrystal Embedded MOS Capacitors for Non-Volatile-Memory Application
Authors: Choi Sam-Jong , Park Young-Soo , Cho Kyoo-Chul , Kang Taesoo , Kim Tae-Sung , Park Byoungjun , Cho Kyoungah , Kim Sangsig
Published: November 2006

Germanium nanocrystals (NCs)-embedded silicon dioxide (SiO2) layers on top of Si substrates were prepared using the implantation of 74Ge+ ions into the SiO2 layers and the annealing of the implanted oxide layers. The distribution of Ge NCs embedded inside the SiO2 layers was examined by high resolution transmission electron microscopy, and optical properties of the embedded NCs were characterized by photoluminescence and micro-Raman spectroscopy. Capacitance versus voltage (C-V) measurements of Ge NCs-embedded MOS capacitors with single Al2O3 capping layers were performed in order to study memory characteristics of these MOS capacitors. The C-V curves exhibit large threshold voltage shifts originating from charging effect of the Ge NCs, revealing the possibility that the MOS structure is applicable to Nano Floating Gate Memory (NFGM) devices.
Panel-Sized LCD Drivers Using SOG Technology
Authors: Hayama Hiroshi
Published: November 2006

Panel-sized drivers for medium- to large-sized LCDs has been proposed. They are TFT-LSIs fabricated on glass substrates whose length is nearly equal to the width or height of an LCD, and they have long narrow shapes and identical outputs for scan/column lines of the LCD. Scan- and column- driver prototypes have successfully been developed using System-on-glass technology for XGA amorphous silicon TFT-LCD panels.
Technology Trend of AMLCDs for Mobile Application
Authors: Yamamoto Yoshitaka , Voutsas Apostolos T.
Published: November 2006

Novel devices to serve the needs of ubiquitous network require powerful input-output terminals with exceptional characteristics. In response to these requirements, we have developed high performance TFTs and System LCD using CG Silicon® technology. In addition, we have demonstrated advanced system integration technology for mobile application such as sensors, the fusion of audio with visual and fine picture quality with good image control. And we have been developing Flexible Displays, and a new Reflective LCD technology for achieving super low power consumption.
Optical Feedback for AMOLED Pixel Circuits
Authors: Deane Steven , Fish David , Young Nigel , Steer Andrew , George David , Giraldo Andrea , Lifka Herbert , Oepts Wouter , Bramante Nicola
Published: November 2006

Optical feedback pixel circuits for a-Si:H and LTPS technologies will be presented. The circuits enable correction of threshold voltage drift of the drive TFT and degradation of the OLED. In the a-Si:H case this is achieved with a standard a- Si:H process and for LTPS an A-Si NIP photodiode is integrated. Operation, technology and measurements will be presented.
Electrical Hysteresis Behavior of Low Temperature Polycrystalline Silicon Thin Film Transistors
Authors: Nam Dae Hyun , Lee Hong-Koo , Jung Sang-Hoon , Ahn Tae-Joon , Kim Chang-Yeon , Kim Chang-Dong , Chung In Jae
Published: November 2006

Image sticking of AMOLED is caused by the property variation of driving transistors. In this paper, we investigated the hysteresis behavior of p-type p-Si thin film transistors as driving device for AMOLED. As the temperature increase, it was observed that hysteresis phenomenon was suppressed. This can be explained by that the trapping and de-trapping rate of carriers is much faster in high temperature than in room temperature.
Analysis of the Hump Characteristics in Poly-Si Thin Film Transistor
Authors: Kim Soopool , Oh Jae Young , Yang Joon Young , Yang Myoung Soo , Chung In Jae
Published: November 2006

To reduce the hump characteristic which is one of the critical issues in poly-Si TFT, we focus on crowding of gate fringing field at channel edge and suggest new modified structure of channel edge. Using dry etching process, poly-Si layer of channel edge is partially removed and the steep profile of channel edge is made into a step profile to decrease the number of carriers from active area. The edge step active (ESA) structure we proposed has a positive effect on removing the hump characteristics.
Analysis of Characteristics in Poly-Si Thin Film Transistor Crystallized by a New Alignment SLS Process
Authors: Kwang Sik Hwang , Yang Joon Young , Yang Myoung Soo , Kim Y. J. , Ahn Tae-Joon , Chung In Jae
Published: November 2006

In the conventional SLS crystallization method, we just perform a basic pre-align on the substrate stage and apply a whole substrate area scanning. Therefore, each TFT has different grain boundary(GB) location in channel region. The number of grain boundaries in channel also varies from one to two, which can cause non-uniform TFT characteristics and image quality deterioration of the panel. In this paper, we present work that has been carried out using the SLS process to control grain boundary(GB) location in TFT channel region and it is possible to locate the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics between a normal SLS method and the grain boundary location controlled SLS method.
Front and Back Channel Properties of Asymmetrical Double-Gate Polysilicon TFTs
Authors: Farmakis Filippos V. , Kouvatsos Dimitrios N. , Voutsas Apostolos T. , Moschou Despoina C. , Kontogiannopoulos Giannis P. , Papaioannou George J.
Published: November 2006

Polycrystalline silicon TFTs with different front- and back- gate lengths are investigated. In addition, the laser annealing process yields high quality directional grains that enable us to orient TFT channels parallel or perpendicular to the grain boundaries. It is demonstrated that double-gate TFTs are fully depleted and therefore back interface properties exert critical influence to the overall TFT electrical performance. More specifically, it is demonstrated that the back interface contains a large number of defects, resulting in a deterioration of carrier conductance.
Threshold-Voltage Instability of Single-Crystal Si Thin-Film Transistors Fabricated on Plastic Substrate
Authors: Yuan Hao-Chih , Ma Zhenqiang , Lagally Max G. , Celler George E.
Published: November 2006

Single-crystal Si thin films are transferred onto plastic host substrate after selectively removing the buried oxide (BOX) layer on the silicon-on-insulator (SOI) substrate. A layer of SU-8 epoxy is used as gate dielectric for the thin-film transistors (TFTs) fabricated on the transferred Si thin films. Here we report the first observation of threshold voltage (Vt) instability on these n-type, single-crystal Si TFTs on flexible plastic substrate. It is observed that Vt shifts to higher (lower) value under high positive (negative) gate-bias stressing. The logarithmic time-dependence of the Vt shift suggests that the instability is attributed to charge trapping in the gate dielectric layer.
The Role of Grain Boundaries on the Performance of Poly-Si TFTs
Authors: Michalas Loukas K. , Papaioannou George J. , Kouvatsos Dimitrios N. , Voutsas Apostolos T.
Published: November 2006

The role of grain boundaries on the performance of polycrystalline Si thin film transistors is investigated through the temperature analysis of the transfer characteristics. The investigation is performed on devices fabricated on films that consist of long grains, separated by parallel boundaries. The transport properties are studied by employing channel orientations parallel and vertical to the grain boundaries. Finally, the data analysis reveals that the major device parameters are thermally activated.
Hydrogen Passivation and Channel Capping for Threshold Voltage Shift and Off-Current Reduction in Nanocrystalline Silicon TFTs
Authors: Esmaeili Rad Mohammad Reza , Sazonov Andrei , Nathan Arokia
Published: November 2006

Bottom-gate thin-film transistors were fabricated using a nanocrystalline silicon channel with amorphous silicon cap layer along with hydrogen plasma treatment on silicon nitride gate dielectric to enhance the stability and reliability of TFTs. The hydrogen plasma reduces the rate of threshold voltage shift, while amorphous silicon cap layer plays the role to reduce the TFT off-current. The TFT exhibits mobility of ~0.8 cm2V-1s-1, threshold voltage of ~4V, on/off current ratio about 108 with off-current of 10-13A, and subthreshold slope of 0.8 V/dec. No threshold voltage shift was observed following application of 15V gate stress for 5 hours.
Room-Temperature Sputter-Deposited Gate SiO2 Films for High Quality Poly-Si TFTs
Authors: Serikawa Tadashi , Miyamoto Takamasa , Ueno Hitoshi , Sugawara Yuta , Uraoka Y. , Fuyuki Takashi
Published: November 2006

Gate SiO2 films in poly-Si TFTs were fabricated by sputtering at substrate temperature from 300°C down to room-temperature. It was found that poly-Si TFT characteristics of mobility, threshold voltage and subthreshold slope were greatly improved by decreasing substrate temperature. Mobility of the poly-Si TFT for room-temperature was 90 cm2/V.s, much higher than 50 cm2/V.s for 300°C. Moreover, sputtered gate SiO2 poly-Si TFTs showed high reliability against hot carrier effect even for room-temperature-deposition.
Novel Characterization Technique for Oxidation Processes
Authors: Sokolov Yuri V.
Published: November 2006

A new application of the commercially-available Surface Charge Profiler (SCP) tool to evaluate metal ionic contaminants that can be brought in during device fabrication processes, including oxidation, is discussed. The SCP measures the surface photovoltage (SPV) signal, and associated depletion width (Wd) and the minority-carrier recombination lifetime (τ). The technique allows not only detect a risky level of the contaminants but also to distinguish between different impurities such as Fe, Cu, and Na. A behavior of these metals in the vicinity of Si-SiO2 interface is discussed. A novel characterization technique should be a beneficial alternative metrology to the conventional capacitance versus voltage (CV), triangular voltage sweep (TVS), and SPV methods.
Deposition of Highly Crystallized Poly-Si Thin Films on Polymer Substrates Using Pulsed-Plasma CVD under Near-Atmospheric Pressure
Authors: Matsumoto Mitsutaka , Suemitsu Maki , Yara Takuya , Setsuo Nakajima , Tuyoshi Uehara , Yasutake Toyoshima , Syun Itou
Published: November 2006

Growth of highly crystalline poly-Si films on polyethylene terephthalate (PET) substrates at 150 {degree sign}C has been achieved with practical growth rates by using pulsed-plasma CVD under near-atmospheric pressure. The precursor is SiH4 diluted in H2, and no inert gases such as He were used. A short-pulse based power system has been employed to maintain a stable discharge in the near-atmospheric pressures. By using this technique we have succeeded in growth of poly-Si thin film on the glass substrate at 180 {degree sign}C with virtually no incubation layers. Good crystallinity of the poly-Si thin films were observed by Raman scattering spectroscopy and cross-sectional transmission electron microscopy.
The Geometry Effect of A Counter-Doped Lateral Body Terminal on Poly-Si TFTs
Authors: Han Sang-Myeon , Ji In-Hwan , Park Joon-Hyun , Choi Sung-Hwan , Yoo Juhn-Suk , Choi Byoung-Duk , Lee Ki-Yong , Han Min-Koo
Published: November 2006

We have designed and fabricated poly-Si TFTs employing various counter-doped lateral body terminals (LBT) which suppress a kink current and improve the reliability under the various electrical stresses. Our experimental results show that the TFT with a LBT structure connected near the drain region was more effective to suppress the kink current and to reduce the leakage current. The suppression of the kink effect employing LBT structure can be attributed to the decrease of E-field at the drain junction due to the potential redistribution in the channel of the TFT by the counter doped LBT and the collecting holes, which have been generated by impact ionization at the drain.
Excimer Laser Crystallization of Amorphous Silicon Film with Artificially Designed Spatial Intensity Profile Beam
Authors: Kim Eok Su , Kim Ki-Bum , Ryu Myung-Kwan , Kwon Hyuk Soon , Kim Cheon-Hong , Son Gon , Lee Jung Yeal
Published: November 2006

A new method to form polycrystalline silicon film with large grains at the controlled location by using a single irradiation of excimer laser beam is proposed for polycrystalline silicon thin film transistor. The excimer laser beam is modified to have a spatial intensity profile - periodic spatial variation of intensity maxima (I_Max) and minima (I_Min) - by the specially designed mask composed of the opaque and the transparent patterns where the opaque pattern size is less than the optical resolution of projection lens. Based on the melt depth of amorphous silicon at the location of I_Min, one can obtain three different regimes, namely, the partial melting, the near-complete melting, and the complete melting. Polycrystalline silicon grains grow vertically and laterally from the seeds at the location of I_Min to the complete molten region of I_Max. The evolution of polycrystalline silicon microstructure is investigated and elucidated in each regime.
Preferred <100> Surface and In-Plane Orientations in Self-Assembled Poly-Si by Multiple Excimer Laser Irradiation
Authors: He Ming , Ishihara Ryoichi , Metselaar Wim , Beenakker Kees
Published: November 2006

Clear preference of <100>- orientation in self-assembled poly- Si is observed for the first time not only in surface, but also in-plane orientations. This textured poly-Si can be used for TFT active channel, expecting a high performance with an excellent uniformity; or can be used as a seed layer for orientation controlling.
Crystallization of Double-Layered Silicon Thin Films by Solid Green Laser Annealing and Its Application to Low Temperature poly-Si Thin Film Transistors
Authors: Sugawara Yuta , Uraoka Y. , Yano Hiroshi , Hatayama Tomoaki , Fuyuki Takashi , Mimura Akio
Published: November 2006

In this study, we propose a novel laser-crystallization technique by employing a double-layered Si thin films substrate for solid green laser anneal (GLA) crystallization, named GLADLAX (Green Laser anneal Double Layer X'tallization). Simultaneous crystallization of both the upper and the lower a- Si films of the substrate in a single laser scan was successfully achieved, with the upper a-Si becoming poly-Si with fine crystallinity, and the lower one, μc-Si. In addition, it was found that approximately 30% of the laser energy was reduced to obtain nearly the same grain size of the upper poly-Si formed through the GLADLAX technique, compared with that of the conventional GLA crystallized single layer poly-Si. Furthermore, we fabricated thin-film transistors using the upper Si film of GLADLAX poly-Si as their active channels, and found they had excellent switching performance, with their mobility exceeding 350cm2/Vs.
Low-Temperature Crystallization of Amorphous Si Films Using Ferritin Protein with Ni Nanoparticles
Authors: Uraoka Y. , Kirimura Hiroya , Fuyuki Takashi , Okuda Mitsuhiro , Yamashita Ichiro
Published: November 2006

A poly-Si thin film with a high crystallinity was obtained using ferritin with a Ni core (7 nm), which enabled us to precisely control the density and position of the nucleus for crystal growth. The core density of ferritin adsorbed on the amorphous silicon surface was controlled in the range from 109 cm-2 to 1011 cm-2. Crystal growth was performed at 550°C in N2. Crystallinity or grain size strongly depended on Ni core density. Poly-Si film with the average grain size of 3 μm and a high crystallinity was obtained at a low Ni atom density of 1012 cm-2.
Molecular-Dynamics Simulations of Recrystallization Processes in Silicon: Nucleation and Crystal Growth in the Solid-Phase and Melt
Authors: Motooka Teruaki , Munetoh Shinji , Kishikawa Ryuzo , Kuranaga Takahide , Ogata Tomohiko , Mitani Takanori
Published: November 2006

It is of increasing importance to understand crystallization processes of silicon (Si) in atomic scale for developing high- speed thin film transistors. We have performed molecular- dynamics (MD) simulations of nucleation, crystallization and defect formation processes in amorphous Si (a-Si) as well as in liquid Si (l-Si). Based on the MD simulation results combined with high-resolution electron microscopy measurements, it is proposed that the crystallization and defect formation processes are controlled by the interface nanostructures between disordered and crystalline Si. It is also suggested that nucleation and crystal growth in a-Si films deposited on glass during excimer laser annealing occur in amorphous-solid and low-density liquid phases rather than in supercooled l-Si as has been generally accepted.
Ge Nuclei for Fabrication of Poly-Si Thin Films on Glass Substrates
Authors: Yasutake Kiyoshi , Watanabe Heiji , Ohmi Hiromasa , Kakiuchi Hiroaki
Published: November 2006

As nucleation sites for solid-phase crystallization (SPC) of a- Si thin films, crystalline Ge islands controlled in size and density were fabricated on glass and SiO2 substrates. Self- assembled crystalline Ge islands were formed by the SPC of a-Ge thin films on glass substrates. By annealing the samples under a reduced pressure of oxygen above 350{degree sign}C, Ge islands were etched to form volatile GeO species (oxygen etching). Single- crystalline Ge islands with good crystallinity and controlled in size and density were fabricated on glass substrates by a simple process combining SPC and oxygen etching. The crystallization times by SPC annealing of a-Si thin films deposited on SiO2 substrates with and without Ge nuclei were studied by Raman spectroscopy and transmission electron microscopy. Marked reductions of the crystallization time and temperature were observed in the SPC of a-Si:H thin films deposited by atmospheric pressure plasma CVD on SiO2 substrates with crystalline Ge islands.
The Road Towards Large-Area Electronics Without Vacuum Tools
Authors: Daniel Jurgen , Arias Ana Claudia , Krusor Brent , Lujan Rene , Street Robert
Published: November 2006

The fabrication of conventional electronic circuits relies on vacuum deposition and etching steps. However, for large-area and low-cost electronics other processes may be advantageous. We have explored the fabrication of electronic pixel circuits with a low-temperature all-additive process using jet-printing technology. These low-cost pixel backplanes are expected to find application in active-matrix addressed paper-like electronic displays
Mist Deposition for TFT Technology
Authors: Shanmugasundaram Karthikeyan , Price Steven , Chang Kyuhwan , Lee Dong-Oh , Ruzyllo Jerzy
Published: November 2006

In this work the process of mist deposition is explored as a method used to deposit organic semiconductors and gate dielectrics for TFTs. With an expanding use of TFTs in both electronic and photonic applications mist deposition offers advantages in terms of versatility, throughput and process cost. The method of mist deposition is first introduced and then example of results obtained with mist deposited dielectric and semiconductors thin films are discussed.
Hole Mobility in Structurally-Different Pentacene Field-Sffect Transistors
Authors: Kwok Harry
Published: November 2006

This work examined pentacene field-effect transistors (OFETs) made on polycrystalline, single-grain, and single-crystal active layers. Mobility data obtained in the literature were matched to equations developed from charge hopping and the Gaussian disorder model (GDM). Making use of a logical sequence of extraction steps, we were able to obtain materials parameters relevant to the charge transport (only one fitting parameter was needed). Our results indicated that there were major differences in the transport site distribution ranging from a very narrow rms width of the density of states (DOS) in the case of the single-crystal OFET to broader values in the single-grain and polycrystalline OFETs. Our model suggested an escape process dominated by correlated hopping at short distance and one limited by site energy distribution and re-organization energy as the active layer became more crystalline.
The Improvement of Electrical Characteristic of Solution Processed Triisopropylsilyl Pentacene Organic Thin-Film Transistors Employing Hexamethyldisilazane Treatment
Authors: Han Jeong-In , Lee Jae-Hoon , Han Min-Koo
Published: November 2006

The field-effect mobility of triisopropylsilyl (TIPS) pentacene organic thin-film transistors (OTFTs) is increased considerably by employing hexamethyldisilazane (HMDS) treatment on poly-4-vinylphenol (PVP) gate insulator. A simple spin coating of HMDS on PVP gate insulator of OTFTs suppressed the void formation significantly and improved structural morphology of pentacene film. The field-effect mobility of OTFT where the TIPS pentacene was spin coated was increased from 0.01 cm2V-1s-1 to 0.1 cm2V-1s-1 after HMDS treatment. The threshold voltage was decreased from -2.8V to -2.0V. We have also fabricated ink-jet printed OTFTs and investigated the effect of HMDS treatment on ink-jet printed OTFTs. The field- effect mobility of OTFT was not increased significantly by HMDS treatment while the threshold voltage of the device was reduced considerably. The threshold voltage of untreated OTFT was +11.1V while that of HMDS treated OTFT was -3.0V. Our experiment results suggest that the HMDS treatment improved the characteristics of OTFTs.
Suppression of OLED Current Error Caused by the Hysteresis of a-Si:H TFT For AMOLED display
Authors: Lee Jae-Hoon , Park Sang-Geun , Jeon Jae-Hong , Goh Joon-Chul , Choi Joonhoo , Chung Kyuha , Han Min-Koo
Published: November 2006

The new a-Si:H TFT pixel circuit, which successfully suppresses OLED current error caused by the hysteresis of a-Si:H TFT, is proposed and fabricated.When an identical VGS and VDS is applied to a-Si:H TFT device, the drain current of a-Si:H TFT is altered due to the hysteresis phenomenon, which changes the interface trapped charge between an a-Si active layer and SiNx gate insulator. When the data voltage of 8V is applied to the conventional a-Si:H TFT pixel, OLED current is changed from 117nA to 167nA due to the hysteresis phenomenon of a-Si:H TFT. In our proposed pixel circuit, OLED current error caused by the hysteresis is successfully suppressed by applying a reset voltage to the gate node of current-driving a-Si:H TFT before a data voltage is written, because a reset voltage can enable the starting gate voltage for a desired one not to be varied.
All-Solution-Processed Organic Thin Film Transistors Fabricated by Non-Piezoelectric Inkjet Printing
Authors: Takasu Isao , Sugi Keiji , Nomura Yuko , Nakao Hideyuki , Mori Kenichi , Amemiya Isao , Uchikoga S.
Published: November 2006

Non-piezoelectric inkjet printing methods, namely, ultrasonic inkjet printing and electrostatic inkjet printing have been used for fabricating an all-solution-processed organic thin- film transistor. Silver nanoparticle ink is patterned to form source/drain electrodes using the electrostatic inkjet method and high-viscosity poly(3,4-ethylenedioxythiophene) doped poly (styrene sulfonate) (PEDOT:PSS) was patterned as a gate electrode using ultrasonic inkjet printing. Polymer insulator and polymer semiconductor are spin-coated as a gate dielectric layer and a semiconductor layer, respectively. This is the first fabrication of all-solution-processed organic transistor using non-piezoelectric inkjet printing.
Nonvolatile Amorphous Silicon Thin Film Transistor Memories with the a-Si:H Embedded Gate Dielectric Structure
Authors: Kuo Yue , Nominanda Helinda
Published: November 2006

An a-Si:H TFT memory with an a-Si:H layer embedded in the gate dielectric structure has been studied. Fabrication steps for this floating gate structure include a simple one-pump down PECVD and a two--photo mask lithography process. Hysteresis of the transfer characteristic demonstrates the memory function. A steady difference between the threshold voltage of the write and erase state demonstrates the programmability of the memory. A charge retention time of more than 3600 secs has been shown. This new structure could expand the application of conventional a-Si:H TFTs.
Process Technology for High-Resolution AM-PLED Displays on Flexible Metal Foil Substrates
Authors: Chuang Ta-Ko , Troccoli Matias , Kuo Po-Chin , Jamshidi Roudbari Abbas , Hatalis Miltiadis , Spirko Jeffery , Klier Kamil , Biaggio Ivan , Voutsas Apostolos T. , Afentakis Themis , Hartzell John
Published: November 2006

The first successful integration of poly-Si thin-film- transistor (poly-Si TFT) backplane with polymer light-emitting diodes (PLEDs) onto a flexible stainless-steel foil is described, and a high-resolution (230 DPI) monochrome active- matrix polymer light-emitting diode (AM-PLED) display is demonstrated. The process technology required to implement this high-resolution AM-PLED display onto a flexible metal foil substrate is discussed. This technology primarily consists of the preparation of flexible metal foils, fabrication of the poly-Si TFT backplane, and integration with top-emitting PLEDs.
Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?
Authors: Orlowski Marius , Wild Andreas
Published: November 2006

Beyond 2007, when the channel length is projected to be 25 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 25 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge. Non-classical double-gate, ultrathin-body transistors offer to minimize short-channel effects and allow for more aggressive scaling. Several three- dimensional (3-D) multigate structures such as FinFET, Trigate, MIGFET, ITFET have been demonstrated with good electrical characteristics down to gate lengths of 10 nm. The manufacturing of 3D devices is entirely compatible with the integration processes employed for planar CMOS MOSFETs. Provided that fabrication, yield, design, and cost issues can be rendered tractable, 3D devices are poised to breathe new life into Moore's Law and close the gap between traditional CMOS planar MOSFETs and post-CMOS-era starting at gate lengths of 6 nm.
Fabrication Techniques for Thin-Film Silicon Layer Transfer
Authors: Holl Susan , Varasala Ravi , Jawanda Harshdeep , Colinge C. A. , Hobart K. D. , Kub Fritz J. , Song Scott
Published: November 2006

New, cost effective fabrication processes for bonding and thinning silicon wafers for improving device performance and creating 3-D structures were investigated. Wafer bonding and de-bonding are key fabrication steps for many applications such as 3-D devices. Double bond transfer and single bond processes to fabricate silicon thin films on permanent substrates were investigated. Polymer and direct bonding techniques were studied to create both permanent and temporary bonds. De-bonding methods utilizing wet chemistry and laser lift-off are discussed.
Sequential Activation Process of oxygen RIE and nitrogen Radical for LiTaO3 and Si Wafer Bonding
Authors: Zikuhara Yoshikaju , Higurashi Eiji , Tamura Noboru , Suga T.
Published: November 2006

Wafer level bonding (4 inch diameter) was examined for lithium tantalate (LiTaO3) and silicon (Si) with 1-um-thick SiO2 layer by using oxygen reactive ion etching (RIE) and sequential activation process. A sequential activation process is consisted of oxygen RIE and nitrogen radical activation. The bond strength under different bonding/annealing conditions was examined from a tensile pull test, a diesaw test and a razor blade method. The bond strength slightly decreased with increasing irradiation time of oxygen RIE, while the strength increased with increasing irradiation time of nitrogen radical. Post-bonding annealing at temperature below 180 {degree sign}C improved the bond strength and  increased the fracture energy without generating serious cracks. When the wafers were bonded at room temperature, followed by annealing at 160 {degree sign}C, the wafers were cut into 1 mm × 1 mm dies without interfacial debonding due to the applied stress during diesaw.
Strained Si via Plasma Enhanced dTCE Bonding
Authors: Sood Sumant , Belford Rona
Published: November 2006

We present various pre-bonding treatments in conjunction with co-implantation cleaving kinetics en route to producing strained silicon on quartz (SSOQ). This surface activation study presents the ground work for elevated temperature bonding required to obtain strained-Si via differential thermal coefficient of expansion (dTCE) wafer bonding. A novel pre-bonding remote plasma surface activation process is presented. Plasma parameters: exposure time, gas species, etc. are varied. Remote plasma effects are compared with standard RCA surface activation. Cleaving kinetics were investigated using co-implanted wafers of B2+, He+ and P2+ with H+.
Highly-Strained Silicon-On-Insulator Development
Authors: Akatsu Takeshi , Hartmann Jean-Michel , Aulnette Cécile , Le Vaillant Yves-Matthieu , Rouchon Denis , Abbadie Alexandra , Bogumilowicz Yann , Portigliatti Lionel , Colnat Cyrille , Boudou Nicolas , Lallement Fabrice , Triolet Fanny , Figuet Christophe , Martinez Muriel , Nguyen Phuong , Delattre Cécile , Tsyganenko Kira , Berne Cécile , Allibert Frédéric , Deguet Chrystel
Published: November 2006

Bi-axially highly-strained Silicon-On-Insulator (sSOI) substrates with a tensile stress up to 2.5 GPa have been obtained by Smart CutTM technology. Thin strained silicon (sSi) layers epitaxially grown on relaxed Si0.6Ge0.4 virtual substrates (VS) were used as starting materials. The threading dislocation density in those sSi layers was in the low 105 cm-2. Some stacking faults were also present in those highly strained Si films. The evolution of this linear defect density was characterized as a function of the sSi thickness by Secco etch. 2.5 GPa sSOI wafers have been demonstrated in 200 mm diameter. Stress uniformity σ equal to 1.14% and 2 nm thickness range has been obtained for 8 nm thick sSi layers.
Evolution of Lattice Strain in Hydrogen-Implanted Silicon Prior to Layer Splitting: An X-Ray Scattering Study
Authors: Capello Luciana , Rieutord Francois , Tauzin Aurelie , Mazen Frederic , Sousbie Nicolas , Letertre Fabrice
Published: November 2006

We have investigated the effects of hydrogen implantation in silicon wafers by x-ray scattering methods. Different crystalline orientations for the Si single crystals were studied, namely (100), (110) and (111) Si. Large strains normal to the surface were evidenced after implantation, which depends on the Si orientation and can be explained on the basis of the different alignment of the Si-Si bonds with respect to the crystal surface. A comparison with the results from infrared spectroscopy shows that strain is associated to specific H- related point defects, such as monohydride multivacancy and H2*. Finally the evolution of the stressed structure during annealing is discussed.
InAs on Insulator by Hydrogen Implantation and Exfoliation
Authors: Hayashi Sumiko L. , Noori Atif , Sandhu Rajinder , Cavus Abdullah , Gutierrez-Aitken Augusto , Goorsky Mark S.
Published: November 2006

InAs on insulator structures were successfully fabricated using wafer bonding and hydrogen implantation and exfoliation processes. Material was exfoliated from either a bulk InAs substrate or from a metamorphic InAs layer grown by MBE via a graded buffer layer on InP. The InAs from the bulk substrate exfoliates as a uniform planar layer with a large surface roughness, ~150 nm, which is similar to the estimated straggle. Under certain conditions, the InAs from the graded buffer layer, however, exfoliates non-uniformly, only transferring long wires of InAs that lie along a specific [110] direction. The size and spacing of these wires resemble the cross-hatch induced by the graded buffer layer growth indicating the exfoliation is influenced by dislocation strain fields. High resolution x-ray diffraction indicates that strain-free InAs is transferred in both cases, however, mosaic tilt is induced into the transferred layer by the hydrogen implantation step.
Low Temperature Void Free Hydrophilic or Hydrophobic Silicon Direct Bonding
Authors: Fournel Frank , Moriceau H. , Beneyton Rémi
Published: November 2006

For both hydrophilic and hydrophobic surface preparation, using the combination of advanced surface treatment and tuned annealing process, void free Si/Si direct bonding have been successfully obtained. The pre-bonding procedure involves only low temperature (<500{degree sign}C) treatment in order to be compatible with the low thermal budget requirement of some applications. The defectivity has been check using acoustic microscopy over all the interesting temperature range (RT-1100{degree sign}C) for 4' silicon wafers.
Plasma Activated Wafer Bonding of Silicon: In Situ and Ex Situ Processes
Authors: Dragoi Viorel , Lindner Paul
Published: November 2006

Plasma activated wafer bonding generated a high interest in last decade due to the important process temperature reduction. With the main advantage of bringing some applications at industrial degree of feasibility. An example of process which benefits from this new process is silicon fusion bonding: by using plasma activation the bond process temperature and time are reduced at values which make wafer bonding compatible with industrial manufacturing requirements. A newly developed process allowing bonding of two substrates in the plasma activation chamber is foreseen as a very interesting approach for numerous applications, especially in the field of engineered substrates fabrication.
Atmospheric Plasma Conditions Compatible with Wafer to Wafer Bonding Strategies
Authors: Farrens Shari N. , Gabriel Markus
Published: November 2006

Plasma activation is a surface preparation method that renders semiconductor substrates hydrophilic. The method has several advantages over wet chemical activation strategies because it is a completely dry process that does not alter the topography of the wafer surfaces. Thus fragile components are not damaged, geometry is not affected and micro-roughness remains unchanged. Plasma preparation of surfaces for wafer bonding is increasing in popularity and naturally there are several techniques available on the market. Plasma systems can be categorized broadly as systems working at atmosphere or in vacuum. An everyday example of the former is arc welding while the common fluorescent light bulb is a well known vacuum plasma application. With regard to semiconductors, vacuum based plasmas are extensively utilized for deposition, etching, cleaning, and surface activation. Bond activation using atmospheric plasma has recently been proved as an appropriate tool for rapid throughput and high bond strengths at low process temperatures for MEMS applications (1,2).
Plasma Activated Wafer Bonding as an Alternative to Standard Wafer Bonding Processes
Authors: Dragoi Viorel , Matthias Thorsten , Mittendorfer Gerald , Lindner Paul
Published: November 2006

Wafer bonding became a powerful industrial technology for various applications in the fields of Micro- Electro-Mechanical Systems (MEMS), wafers stacking for 3D interconnects, wafer level packaging and other areas where new materials combinations are facilitated by the use of different bonding processes. An important enlargement of wafer bonding applications field was brought by new developments in the area of low temperature wafer bonding processes (maximum temperature of 400{degree sign}C): with such processes wafer bonding can be applied for fully patterned wafers (e.g. CMOS), IC wafers (e.g. for 3D interconnects) or silicon direct bonding can now be performed in standard industrial wafer bonding equipment. Plasma activated wafer bonding is a process in which the two substrates are submitted to a plasma treatment prior to bringing them into contact. This surface treatment allows the control of surface chemistry and results in obtaining a high bond strength at low annealing temperatures and short thermal annealing times. This paper reports new results obtained for different applications using plasma activated wafer bonding.
Sequential Plasma Activated Process for Silicon Direct Bonding
Authors: Howlader Matiar R. , Itoh Hironori , Suga T. , Kim Moon
Published: November 2006

Sequential plasma activated bonding (SPAB) process consisting of oxygen reactive ion etching (RIE) and nitrogen microwave radical plasma was developed for silicon direct bonding at room temperature. A strong influence of plasma time and gas pressure on voids was found both in the SPAB and O2 RIE processes. Tensile strength and surface roughness are functions of oxygen RIE, nitrogen radical time and gas pressure. Improved tensile strength was achieved in the SPAB process. High resolution transmission electron microscope (HRTEM) observations showed a thicker silicon oxide interfacial layer from the SPAB process than that from the O2 RIE process. The increase in thickness of interfacial oxide layers in both processes after annealing at 600{degree sign}C for 2 h in air is attributed to the oxygen concentration of silicon bulk wafers. The SPAB process can be explained by the reaction between two metastable surfaces, which allows water removal from interface, resulting in covalent Si-O-Si bonding.
Rough Surface Adhesion Mechanisms for Wafer Bonding
Authors: Rieutord Francois , Moriceau H. , Beneyton Rémi , Capello Luciana , Morales Christophe , Charvet Anne-Marie
Published: November 2006

Wafer bonding can be viewed as an example of rough surface adhesion. We show that formalisms developed to describe rough surface adhesion can be rescaled to nanometer range and applied to silicon wafer bonding, with results that fit well with experimental observations.
Relation Between Electrical and Mechanical Characteristics of Low-Temperature Bonded Si/Si Interfaces
Authors: Raeissi Bahman , Sanz-Velasco Anke , Engström Olof
Published: November 2006

The bonding energy of low-temperature plasma bonded silicon- silicon interfaces is correlated with their electrical properties. From current versus voltage and capacitance versus voltage data, mobile ion charges are shown to play a considerable role for the bond force. By comparing the evolution of the bonding strength during the first 48 hours after bonding with that of ionic charge in the interlayer and interface electron state concentrations, we demonstrate a relation between these quantities for low temperature plasma bonded silicon surfaces. The results suggest that mobile ions in an interfacial layer change the charge distribution, resistance, capacitance, interface state density distributions and correlate with the bonding energy of the silicon-silicon junction.
Quantitative Model-Based Interpretation of Experimentally Measured Nanoscale Stress Sources at Wafer Bonded Interfaces
Authors: Horn Gavin , Johnson Harley , Mackin Thomas , Lesniak Jon
Published: November 2006

Nanoscale surface features at the interface of bonded silicon wafers are critical to achieving high yield wafer bonding processes. Interfacial features such as surface patterning, trapped particles and gasses, and wafer surface nanotopography can generate residual stresses that may affect subsequent device lifetimes, processing and performance. This paper presents a numerical model that captures a more complete description of bonding physics and mechanics than extensions of closed form thin-plate solutions. The model is verified by experimentally measuring residual stresses arising from patterned nanoscale surface features using an infrared grey- field polariscope. The proposed numerical model captures the functional form of the observed residual stress fields arising from interfacial defects and is in good agreement with experiments. These simulations indicate that high bond energies may produce debonds around small defects that are not possible to detect using infrared transmission inspection techniques, yet the associated residual stresses are increasingly large in magnitude.
Effect of Prebonding Surface Treatments on Si-Si Direct Bonding : Bonding Void Decrease
Authors: Beneyton Rémi , Fournel Frank , Rieutord Francois , Morales Christophe , Moriceau H.
Published: November 2006

Comparisons of various plasma assisted low temperature wafer bonding procedures have been conducted in order to carry out reliable void-free and high bonding strength. In this way, reactive ion etching (RIE), microwaves (MW) and inductive coupled plasma (ICP) modes have been investigated as surface cleaning and activation processes before Si-Si direct bonding. Moreover impacts of some additional prebonding surface treatments have been analyzed for such bonded structures. Using these additional treatments, focus has been specifically made on efficiencies to perform void-free and high bonding strength for Si-Si direct bonding thanks to prebonding 300{degree sign} heating and/or on under-vacuum bonding.
Controlled Silicon (001) Surface Periodic Nanopatterning by Direct Wafer Bonding
Authors: Bavard Alexis , Mézière Jérôme , Fournel Frank , Pascale Alina , Gentile Pascal , Eymery Joel
Published: November 2006

In order to control simultaneously the nanostructures size, density and positioning, nanopatterned substrates are elaborated using an original process based on the revelation by preferential chemical etching up to the surface of a buried square dislocation network obtained by direct twist wafer bonding. By including the dislocation network into a SOI substrate thin film the surface patterning evolution during the selective chemical etching for 20 and 50 nm periodicity samples is controlled and checked by Scanning Electron Microscopy (SEM). A dislocation network periodicity dependent surface grating is showed. Si mesas with efficient aspect ratios are obtained after a second selective chemical etching allowing the further Ge islands self-assembled growth. Germanium growth equivalent to 10 Aå layer is performed at 600{degree sign} C on 50 nm periodicity nanopatterned surfaces. For different cooling rate from deposition temperature to room temperature the dots size, shape and density are characterized by Scanning Tunneling Microscopy and SEM.
Review of Compound Materials Bonding and Layer Transfer for Optoelectronic Applications
Authors: Faure Bruce
Published: November 2006

Wafer bonding and layer transfer technologies open new ways for substrate and device structures in a wide field of application. This paper will review major achievements over the last ten years in building innovative structures in III-V materials by bonding and layer transfer by means of the Smart Cutä technology. Main published results about GaAs, InP, SiC and GaN layer transfer will be presented here.
Simple Technological Process for the Fabrication of Optical III-V Nanowires Integrated into a Benzocyclobutene Matrix
Authors: Carette Michèle , Lauvernier Denis , Vilcot Jean-Pierre , Bernard Dorothée , Decoster Didier
Published: November 2006

Our research interest is the fabrication of high index contrast waveguides in III-V material for nanophotonic applications at telecom wavelengths (1.3 or 1.55 µm). We propose to create this high index contrast by embedding a III-V nanowire in a low index polymer matrix (Benzocylobutene, BCB). We expose here the simple wafer bonding processing technique that leads to these III-V nanowires buried in BCB.
Moisture Resistant Nano Liter Packages Using Metallic Seal Wafer Bonding
Authors: Reinert Wolfgang H. , Merz Peter , Schwarzelbach Oliver
Published: November 2006

Vacuum wafer bonding technology provides a number of very effective techniques to produce low-cost, hermetic sealed nano liter packages for micromachined sensors and actuators. Beside the protection of the device from outside environmental stresses, the package must also provide an interior environment compatible with the device performance and reliability demands, see figure 1. The special challenges in passing autoclave testing are discussed. Moisture tolerant nano liter packages are an enabling factor for very cost effective 1st. level packaging in open cavity or molded packages for a large variety of applications, otherwise excluded due to cost reasons.