bluuebunny/crossref_metadata_2025 huggingface dataset:
Experimental Investigation of the Impact of Under Floor Blockages on Flow Distribution in a Data Center Cell
Authors: Bhopte Siddharth , Sammakia Bahgat , Iyengar Madhusudan K. , Schmidt Roger
Published: January 2010

Due to the increase in the rack power of computer equipment, in recent years, thermal management of data centers has become a challenging problem. Data center facilities with raised floor plenums are the most popular configuration from a ducting configuration perspective. The under floor plenum serves as a distribution chamber for the cooling air. Plenums are also used to route piping, conduits and cables that bring power, server network connections, and supply coolant to the air conditioning units. Computational modeling studies have shown that, these under floor blockages impede the flow of cold air from the air conditioning units and yield unpredictable air flow patterns. In this paper, the impact of under floor blockages on flow distribution in a data center is experimentally investigated. A data center experimental cell with one server rack and one air conditioning unit is examined. A number of perforated tiles and their resistances are altered to achieve variable flow patterns under the raised floor. Using previously established guidelines for the placement of under floor structures (piping, etc.) three different scenarios are studied, i.e. no blockages, blockages in critical flow path and blockages in safe flow path are considered. Experiments were carried out for two different tile designs, with free area ratios of 16% and 30%, respectively, and three tile configurations. A detailed comparison between the experimental and CFD model results are presented for several different cases, showing good agreement. Blockages if placed in critical path are shown to significantly reduce the supply tile flow rates which directly affects the thermal performance of the corresponding server. Blockages are shown to have minimal impact when they are placed in safe path. Based on CFD model and experimental results, guidelines on managing under floor blockages are verified. Emphasis has been given to the routing the blockages from safe paths and to keeping critical paths blockage free.
Mechanical Characterization of Sn-Ag-Cu Solder With Gold Addition Under Tensile Loading
Authors: Lakhkar Nikhil , Hossain Mohammad M. , Viswanadham Puligandla , Agonafer Dereje
Published: January 2010

Lead (Pb)-free implementation for electronic assembly has created a stir in electronic packaging industry during the last five years since Europe and eastern Asian countries decided to restrict the use of lead in electronic packages. Lead (Pb) content in solders is mandated to be less than 0.2 wt % (USA) and 0.1 wt % (EU). Sn-Ag-Cu (Tin, Silver, and Copper) solder is selected as one of the options to replace tin-lead solders. This solder is a preferred option as it comes closest to tin-lead solder in terms of parameters such as melting temperature (∼217°C), wettability, cost, availability, and reliability. Various agencies like NEMI, JEIDA and IDEALS recommend Tin-rich Lead (Pb) free solders as the possible alternatives to Pb-Sn solder [1]. Addition of elements like Au, Co, Fe, Ni, etc in small quantities can affect the properties of Sn-Ag-Cu solder. It has been reported that the addition of Au in small quantities improves the properties of lead-free solder. Au has very high reactivity with Sn and also improves the wettability of solder. Au forms a β-phase with Sn at the interface. This phase is considered beneficial in terms of improving fatigue life and fracture toughness as this β phase acts as a crack arrester thereby improving its strength Addition of Au also reduces the liquidus temperature to 204 °C. In this paper we tested and compared the strength of pure Sn-Ag-Cu solder and Sn-Ag-Cu solder with Au addition and it was concluded that the strength of material increases from 50 MPa to 70 MPa under tensile loading.
High Resolution Die Stress Mapping Using Arrays of CMOS Sensors
Authors: Chen Yonggang , Jaeger Richard C. , Suhling Jeffrey C.
Published: January 2010

This paper reports high resolution die stress measurements using a multiplexed array of 512 current mirror type CMOS piezoresistive FET stress sensor cells fabricated on an MOSIS tiny chip. Using 1.5 μm CMOS technology, a stress mapping resolution of 256 points/mm2 has been obtained, providing high spatial resolution mapping of the stress on the surface of the integrated circuit die. Driven by an on-chip counter, the sequentially scanned array efficiently maps the two-dimensional stress field. The sensor array is calibrated using a chip-on-beam calibration technique. These CMOS sensor arrays have been used to map stress on the die in the chip-on-beam configuration under four-point-bending load, in encapsulated chip-on-beam samples, and in DIP40 packages with cavities filled with underfill. The measured stress distribution agrees well with finite element simulation results, and permit smooth measurement of stress gradients on the surface of the integrated circuit die. The results give clear verification that the NMOS PiFET sensors are indeed responding to shear stresses.
Chip-on-Beam and Hydrostatic Calibration of the Piezoresistive Coefficients on (111) Silicon
Authors: Cho Chun-Hyung , Jaeger Richard C. , Suhling Jeffrey C. , Rahim M. Kaysar
Published: January 2010

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.
Computational Fluid Dynamics Investigation on FCBGA Die Bulk Penetrating Cracks After Thermal Shock Test
Authors: Tsai Kuo-Ying , Ku Shih-Chang
Published: January 2010

A crack with unusual failure mode after thermal shock test (TST) is observed on the die bulk of certain bare-die FCBGA, in which the crack penetrates longitudinally within silicon die region. The computational fluid dynamics (CFD) method is introduced to investigate this phenomenon. The transient analysis results indicate a significant temperature difference existing between top and bottom surfaces of the silicon die in the very beginning of the liquid-to-liquid temperature transition. This could be fatal to a brittle material like silicon. Some possible solutions are then surveyed to alleviate the thermal impact to the FCBGA. At least one of enhanced proposals is proved effective to eliminate die crack occurrence after TST.
Control of Instabilities in Two-Phase Microchannel Flow Using Artificial Nucleation Sites
Authors: Jones Rory J. , Pate Daniel T. , Bhavnani Sushil H.
Published: January 2010

Microchannel heat sinks offer the promise of an effective and compact technique for heat dissipation from high-powered microelectronics. When combined with phase-change mechanisms, it is possible to extend heat removal capabilities over several future technology nodes on electronics roadmaps. Many studies have documented instabilities in phase-change flows associated with uncontrolled transition from bubbly flows to slug flows at fairly low void fraction. The phase-change thermal transport reported here was carried out on microchannel heat sinks etched in silicon and cooled by the dielectric fluid FC72. Microchannels with a hydraulic diameter of 253 microns were studied. The base of each microchannel is augmented with 20-micron cavities to trigger controlled nucleation activity and help control large-scale instabilities reported in the literature. The cavities significantly impact the flow regime by promoting stable nucleate boiling. Temperature and pressure measurements show stable flow regimes under all combinations leading to saturated channel exit conditions and even for subcooled exit conditions at low-to-moderate heat fluxes. These measurements are confirmed by high-speed photography. Instabilities observed were confined to a sub-set of the subcooled exit flow regime. Within this region, an analysis of the data shows that the frequency of the flow instability is between 8–14 Hz. Instability maps demarcating regions of stable and unstable flow are presented as functions of mass flux (535–2140 kg/m2–s), and inlet subcooling (5–25°C).
Heat Conduction in Printed Circuit Boards: Part I — Overview and the Case of a JEDEC Test Board
Authors: Nakayama Wataru , Nakajima Tatsuya , Koike Hiroko , Matsuki Ryuichi
Published: January 2010

Addressed in the present study is the required accuracy in assuming equivalent thermal conductivities of printed circuit boards (PCBs) in the thermal analysis of electronic equipment. The required accuracy depends on the morphology of PCB and the thermal boundary condition. Out of various PCB morphologies two are considered as representatives in the extreme ends of PCB size and thermal conditions; one is a JEDEC test board having a large convection-cooled area, and the other is a small board in contact with a large solid thermal mass. The major focus of the present paper is on the case of a JEDEC test board measuring 11 cm × 11 cm and carrying a ball grid array package (4 cm square). Geometric complexity in the through-via zone under the package needs to be reduced by suitable modeling in order to simplify the analysis. In exploring modeling strategies the analyses were performed on three models. Level-one model includes the details of through-vias, and the computation is resource intensive. Level-two model is composed of two orthotropic media having pairs of different equivalent thermal conductivities, one corresponding to the via zone and the other to the rest. Level-three model is a thermal resistance network model derived from numerical/analytical composite analysis. Comparison of the results on the three models proves that the accuracy of temperature prediction is in general insensitive to the equivalent thermal conductivity values due to the dominant role of surface heat transfer on the temperature level of PCB.
Advanced Micro-Channel Vapor Chamber for Cooling High Power Processors
Authors: Mochizuki Masataka , Saito Yuji , Kiyooka Fumitoshi , Nguyen Thang , Nguyen Tien , Wuttijumnong Vijit
Published: January 2010

After the introduction of Pentium™ processor in 1993, the trend of the processor performance and power consumption have been increased significantly each year. Heat dissipation has been increased but in contrast the size of die on the processor has been reduced or remained the same size due to nano-size circuit technology and thus the heat flux is critically high. The heat flux was about 10–15 W/cm2 in the year 2000 and had reached 100 W/cm2 in 2006. The processor’s die surface where the heat is generated is usually small, approximately 1 cm2. For effective cooling should required least temperature gradient between the heat source and radiating components. The best known devices for effective heat transfer or heat spreading with lowest thermal resistance is heat pipe and vapor chamber. Basically, heat pipe and vapor chamber are an evacuated and sealed container which contains a small quantity of working fluid which is water. When one side of the container is heated, causing the liquid to vaporize and the vapor to move to the cold side and condensed. Since the latent heat of evaporation is large, considerable quantities of heat can be transported with a very small temperature difference from end to end. The 2-phase heat transfer device has excellent heat spreading and heat transfer characteristics, is the key element in thermal management challenge of ever power-increasing processors. In this paper, authors presented case designs using vapor chamber for cooling computer processors. Proposed ideas of using micro-channel vapor chamber for heat spreading to replace the traditional metal plate heat spreader. Also included in the paper are ideas and data that showed performance improvement of heat spreading devices.
Causes of Degradation of Thermal Performance of Ball Grid Arrays After Thermal Cycling
Authors: Knight Roy W. , Elkady Yasser , Suhling Jeffrey C. , Lall Pradeep
Published: January 2010

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.
Analytical Modeling of Fluid Flow and Heat Transfer in Micro/Nano-Channel Heat Sinks
Authors: Khan Waqar A. , Yovanovich Michael M.
Published: January 2010

Laminar forced convection in two-dimensional rectangular micro and nano-channels under hydrodynamically and thermally fully developed conditions is investigated analytically in the slip flow regime (0.001 < Kn < 0.1). Closed form solutions for fluid friction and Nusselt numbers are obtained by solving the continuum momentum and energy equations with the first-order velocity slip and temperature jump boundary conditions at the channel walls. Isoflux thermal boundary condition is applied on the heat sink base. Results of the present analysis are presented in terms of channel aspect ratio, hydraulic diameter, momentum and thermal accommodation coefficients, Knudsen number, slip velocity, Reynolds number and Prandtl number. It is found that fluid friction decreases and heat transfer increases, compared to no-slip flow conditions, depending on aspect ratios and Knudsen numbers that include effects of the channel size or rarefaction and the fluid/wall interaction.
Mechanical Reliability Evaluation of Stripped and Replated Component Termination Finishes
Authors: Subbarayan Guhan , Kinyanjui Robert , Tsai Pei Fang , Srihari Krishnaswami
Published: January 2010

The termination finish of Small Output Integrated Circuit (SOIC) and Small Output Transistor (SOT) chip components were converted from Pb-free to Sn-Pb (backward conversion) and vice versa (forward conversion). The motivation for these conversions is due to a combination of factors such as the supply chain constraints on component availability, European Union’s (EU) legislation on “Restriction of Hazardous Substances” (or RoHS), and the growth of tin whiskers on matte tin finish components. The conversions were performed using a “Robotic Stripping and Solder Dipping Process”, and the mechanical reliability of the converted components was evaluated through lead pull testing. In this experiment, a 100% (all finishes are given in weight percentage unless otherwise specified) matte tin finish was first stripped and re-plated with an eutectic Sn-Pb finish. Then, components with 100% matte tin and eutectic Sn-Pb termination finish were replaced with a Pb-free Sn-3.5%Ag-0.5%Cu (SAC305) finish. Three Printed Circuit Board (PCB) surface finishes namely Immersion Silver (ImAg), Organic Solderable Preservative (OSP), and Electroless Nickel/Immersion Gold (ENIG), were evaluated with Sn-Pb and Pb-free processes. All the assembled boards were subjected to an initial analysis, which includes visual inspection with an optical microscope and X-Ray analysis. Subsequently, a time zero analysis was performed which includes cross sectioning, Scanning Electron Microscope (SEM) analysis and lead pull testing. The pull testing was performed on a Chatillon TCM 201-SS equipment. All the leads were pulled orthogonal to the surface of the PCB. After isothermal aging at 150°C for a time period of 10 days (240 hours), cross sectioning and pull testing were performed to study its effect on Intermetallic Compound (or IMC) growth and reliability.
Server-Rack Air Flow and Heat Transfer Interactions in Data Centers
Authors: Tan S. P. , Toh K. C. , Wong Y. W.
Published: January 2010

The current study focuses on modeling the server-rack airflow and heat transfer interaction in a data center. In a typical computing facility, the computing requirements are often gradually built-up. For example, in this instance, two servers are placed in a rack designed for a six-server stack. Each server will be separately modeled to the required specifications, and also so that their numbers and placement can be changed. The mass flow rate through the server is determined by examining how pressure profiles develop at the inlet and outlet. This mass flow rate then becomes the input into the rack model. The air inflow temperatures at the front and rear grills were obtained from experiments. The pressure profile into and out of the servers were extracted from the rack model and substituted back into the server model. Iteration continues till an acceptable level of convergence is obtained. To validate the models, experiments were carried out using thermocouples arranged in a 3 × 3 grid on a vertical plane between the exit of the server and the rear cabinet wall of the rack. The results showed that the modeling had captured the essence of the flow and heat transfer interaction. The temperature and pressure profile at the rack inlet and outlet, although in a segmented form, have performed adequately to obtain a good approximation of the flow and temperature distribution within the server/rack. The methodology of passing parameters at the server-rack level using a segmented pressure profile has been established. A similar rack-room level interaction will subsequently be developed. In essence, the methodology is equivalent to replacing the server in the rack and the rack in the room with combined flow network - thermal models. But because of the coupled nature of these two different length scale systems, the models are obtained through an iterative process. The approach enables various combinations of servers and racks to be studied quickly for any undesirable effects of off-design data center operation or layout.
New Product Introduction of Fully Buffered DIMM: A Process Perspective
Authors: Chennagiri Gurudutt , Iyer Satyanarayan , Tsai Pei-Fang , Srihari Krishnaswami
Published: January 2010

The introduction of new products to the manufacturing environment is a challenging task. The extent of this challenge varies depending on the complexity of the product being introduced. Fully Buffered Dual In-line Memory Modules (FBDIMMs), which have been a recent introduction to the memory industry, pose several unique challenges that need to be addressed. The objective of this study was to first comprehend the distinguishing features of this product against a generic memory module from an assembly process perspective and address the associated issues. Failure Modes and Effects Analysis (FMEA) was conducted to highlight the areas of concern from a process and reliability stand point. Processes were developed to mitigate the occurrence and severity rate of the identified failure modes. The assembly of heat sinks on these modules is a unique aspect and required special tools and fixtures. Various issues that were critical to quality were encountered while assembling the heat sinks. Centering of heat sinks over the module after assembly was also observed to be critical. Misaligned heat sinks can obstruct the insertion of modules into test and application sockets. A special tool was designed to address this issue. Upon installation of the new tool, a capability study was performed to validate the process. Removal of the heat sink for component rework purposes was also a concern. This was mainly due to the adhesion of the Thermal Interface Material (TIM) material used on the heat sink with the components on the board. The adhesion led to component separation from the board during the removal process and required a special process to mitigate this issue. The methods used to address these issues are reported. The product reliability was validated using thermal cycling, shock and vibration tests. The results of these tests are also reported in the paper.
Effect of Heat Sink Assembly on Mechanical Reliability of a Wire Bonded Plastic Ball Grid Array Package
Authors: Trivedi Aalok , Kaisare Abhijit , Agonafer Dereje , Refai-Ahmed Gamal
Published: January 2010

Since the advent of the transistor and integrated circuit, the performance of electronic equipment has increased significantly while footprint of systems at all levels continues to decrease. Recently, the number of transistors on a high end microprocessor has exceeded a billion. All of the above has necessitated considerable improvement in cooling technology and associated reliability. Heat sinks play an important role in cooling technology by providing an increased surface area to dissipate heat. While there has been a great deal of work related to the thermal performance of heat sinks, there has not been a corresponding effort in studying the mechanical related reliability issues of the heat sinks. Previous work has been done to study the effect of adhesively bonded heat sink on the mechanical reliability of a two-layer wire bonded plastic ball grid array (WB-PBGA) package. Stresses induced in the package have been computed for a wide range of values of the adhesive mechanical properties and Young’s modulus. Variation of interfacial peel and shear stresses at the interface between the mold compound and the adhesive and between the adhesive and the heat sink have been qualitatively assessed for propensity of interfacial de-lamination along these two interfaces. In this paper a stress analysis of described package is carried out to study the effect of heat sink assembly on the mechanical reliability of the package. A three dimensional finite element model of WB-PBGA package and Printed wiring board (PWB) is solved numerically to predict the stresses induced and assess their impact on the mechanical integrity of the die and package due to the heat sink assembly. Die and C4 interconnect stresses are examined to evaluate package reliability. Stresses induced within the die and C4 interconnect are examined for different heat sink materials and variation of force developed by heat sink attachments such as clip and screw type has been examined. Finally recommendations will be made regarding choice of heat sink material and clipping force for overall heat sink assembly design. The modeling utilizes a solid model for geometry creation and a finite element commercial program for simulation.
Modeling Thermoelectric Device Enhancement of Heat Sink Performance
Authors: Roser Richard I. , Smythe Robert M. , Singh Malkiat
Published: January 2010

Increased power density is straining the ability of air-cooled heat sink technologies to provide adequate cooling for heat-generating components. Several technologies are under investigation as replacements for air-cooling. Under specific conditions, a well-selected thermoelectric device [TED] can act as an enhancement to a heat sink’s heat removal capacity or allow it to achieve lower temperatures. Such improvements to heat sink performance using a thermoelectric device are possible without increasing airflow or heat sink dimensions. Proper sizing of this kind of optimized thermoelectric system involves consideration of multiple conditions, including the amount of heat being generated, the temperatures involved (typically, target case temperature and expected ambient temperature), and available voltage and current. Although thermoelectric devices are often thought of as inefficient, with Coefficients of Performance [COP] of less than 1, a well-selected TED can have a COP of much greater than 10. Existing methods for thermoelectric optimization, for the sake of simplicity, often ignore the thermal resistance of the heat sink or ignore the effect of temperature dependence of the thermoelectric material parameters of resistivity, thermal conductivity, and thermopower. To correctly include these factors in the design of the TED, a methodology has been developed to determine an optimum device while simultaneously considering the input parameters of θCA (case to ambient thermal resistance), heat load, target cooling temperatures, and available DC power. The method is iterative, involving the use of given input conditions to yield an estimate for expected final temperature conditions, which are used to produce an initial estimate of the thermoelectric material parameters, which in turn are used to calculate the optimized device. The performance of this device is calculated to determine a new estimate for temperatures and material parameters. The process is repeated until convergence occurs for the device design. The methodology can also demonstrate the performance benefits of integrating a TED into an existing conventional fan/sink system, and also describes conditions that are unsuitable for the use of TED’s. Graphical representation of the information can be readily generated as an aid to design.
Effect of La Doping on SnAg Solder Microstructure Evolution
Authors: Pei Min , Qu Jianmin
Published: January 2010

In this paper, quantitative microstructure studies were performed on multiple length scales to investigate effect of La doping on SnAg lead free solder materials. Variables considered in this paper include doping amount, aging temperature and aging time. It was found that La doping refines the microstructure and reduces microstructure coarsening rate, but the inter-particle spacing remains unaffected. Therefore, higher La doping level leads to higher volume fraction of the eutectic phase due to the increased total number of Ag3Sn particles.
Phase Change Metallic Alloy TIM2 Performance and Reliability
Authors: Macris Chris G. , Ebel Robert G. , Leyerle Christopher B. , McCullough John C.
Published: January 2010

With processor power levels exceeding 200 Watts and nearly 25% of the overall processor junction-to-ambient thermal resistance budget consumed at the second-level thermal interface (TIM2), the use of an all-metal interfacial thermal path is highly desirable [1]. Phase Change Metallic Alloys (PCMAs) offer superior thermal performance due to their high thermal conductivities and low contact resistance resulting from their excellent surface wetting. Also, reworkability and ease of handling make PCMAs attractive in a high volume setting. The current work utilizes packaged Thermal Test Vehicles (TTVs) for thermal performance characterization and an In-situ Test Vehicle (ITV) platform for reliability testing. Comparative thermal performance between a PCMA and organic thermal interface products will be presented. Additionally, reliability data from PCMA samples subject to various environmental stress conditions will be discussed.
A Multiscale Modeling Method for the Creep Behavior of SnAg Solder Alloys
Authors: Pei Min , Qu Jianmin
Published: January 2010

In this paper, a microstructure-dependent creep model is developed that accounts for the hierarchal microstructure at multiple length scales. The model considers three distinguishable phases in the solder alloy at two different length scales: at the larger scale Sn dendrites of micrometer size are embedded in a homogeneous eutectic phase; at a much smaller length scale the eutectic phase consists of submicron size Ag3Sn particles embedded in a homogeneous Sn matrix. The model predictions agree well with creep test data of RE doped SnAg solders.
Thermal Performance Evaluation and Enhancement for an Automotive Wireless Application Incorporating Multiple Dynamic Heat Sources
Authors: Chiriac Victor , Lee Tien-Yu Tom
Published: January 2010

A detailed transient thermal study for a Remote Keyless Entry System with dynamic heat sources is performed using numerical simulations. The SmartMOS-type device is packaged in a 54 lead SOIC (small outline IC) package with an exposed copper slug. The package is attached to a 4-layer PCB with thermal vias embedded in the board. The challenge resides in the transient thermal interaction between several dynamic heat sources (channels), activated in a sequential fashion following different powering profiles and patterns. The main purpose of the device is to wirelessly provide a communication path between the remote and the receiver placed in the car, so the distance and the signal strength between the two are paramount for an optimal operation. The signal strength is directly associated with the voltage (and associated powering) levels. Several operating scenarios are evaluated by modifying the system design (thermal via pattern) and varying both power dissipation and duration levels. The study starts with just one channel dissipating power, followed by activating the entire dynamic system comprised of six channels dissipating each powers reaching up to 22W at different time intervals. The transient thermal behavior of each source is analyzed during the process. Results indicate that the system dissipating over 14V exceeds the thermal budget (150C) after only 3 powering cycles. Based on the analysis of the complex temperature fields for the multiple dynamic source system, the authors identify alternative power profiles to improve the thermal performance of the overall wireless system, by splitting the power in selective channels and by modifying the power sequence. Several additional cases are further investigated, and the optimized power profiles indicate that they satisfy the thermal budget under various operating conditions and several multiple cycles, while still maintaining the device voltage at 14V levels. A thorough study of the transient patterns and needed system improvements are included.
System Level Thermal Optimization of an Automotive Lightning Module Incorporating Several Power Devices
Authors: Chiriac Victor , Lee Tien-Yu Tom
Published: January 2010

The conjugate thermal performance of microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with multiple packaging and module-level thermal issues when reducing the size of components for a lightning system in a car, while managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance of the lightning system. The main concern is related to the possibility of exceeding the thermal budget for a large system incorporating several PQFN (Power Quad Flat No-Lead Package) packages with additional heat dissipation devices in an enclosure, at an external ambient temperature of 85°C. Due to the compactness of the device, there are only limited solutions to extract the heat from the high power dissipation system. The impact on the thermal balance of the trace dissipation, the location and size of the pins connecting the two boards (motherboard and daughter board) forming the system, the header heating and other passive components under various powered conditions are evaluated. A revised model includes additional pins (reduced diameter), modified motherboard and harness structures and their locations; the impact of additional heater traces on both top and bottom surfaces of the motherboard, and a modified daughter board design, is also evaluated. The resulting peak temperatures range from 118.3°C to 137.3°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.4°C/W to 8.8°C/W. Rja is defined as the temperature difference between the peak device and ambient divided by the total power dissipation of the PQFN packages. An optimized design is further evaluated, with lowered thermal resistance from the motherboard, the board-to-board pins, the junction box board, and the wiring harness. The thermal budget is satisfied, as the peak temperatures reached by the two designs are below the 150°C limit. Additional experimental results are used to benchmark the simulation results, within 1–6% accuracy.
Nano-Pattern Recognition and Correlation Technique for Nano-Scale Deformation Measurement
Authors: Bi Hongbo , Hartsough Chris , Han Bongtae
Published: January 2010

The foundation and technical procedure of Nano-Pattern Recognition and Correlation Technique (N-PRCT) is described. The proposed technique is an in-plane displacement measurement technique that is based on regularly oriented structures. Displacement is obtained by tracking the movement of each single pattern in the images taken before and after loading (deformation) through techniques of pattern recognition and correlation. The proposed technique is insensitive to the noise involved in the digital images which comes inherently from the SEM imaging process; this results in high measurement accuracy. The technique provides the spatial resolution of less than 5 nm/pixel and displacement measurement accuracy of approximately 0.1 nm, which will be suited ideally for thermal deformation measurements of Low-K layer.
An Investigation of the Effect of Nanoparticles on the Effectiveness of a Heat Exchanger
Authors: Upender Rao V. , Sajith V. , Hanas T. , Sobhan C. B.
Published: January 2010

Convective heat transfer can be improved by enhancing the thermal conductivity of the fluid. It has been established that fluids containing suspended solid particles of metallic origin in nanoscale dimensions, display enhanced thermal conductivity. Nanoparticle suspensions have superior qualities than suspensions of larger sized particles, such as more particle surface area, less possibilities of agglomeration and clogging and better stability. An experimental investigation on the effect of the inclusion of nanoparticles into the cooling fluid on the effectiveness of a heat exchanger is presented in this paper. An experimental double pipe heat exchanger with the hot fluid flowing through the inner tube was used in the study. Aluminum oxide and copper oxide nanoparticles with a size range of 20 to 30 nm suspended in water using ultrasonic agitation was used as the hot fluid, and water was used as the cold fluid passing through the annulus. The concentration of the suspended nanoparticles was varied to investigate its effect on the performance of the exchanger. The operating temperature is also used as a parameter in the study. Typically, an enhancement of 4.5 to 7 percent was observed in the effectiveness of the heat exchanger for 0.26% weight fraction of the nanoparticles in suspension, in an operating temperature range of 50–70°C. The effectiveness of the heat exchanger was found to increase with the concentration of nanoparticles for both materials used.
Vapor Chambers in Blade Server CPU Cooling Solutions
Authors: Connors Matt
Published: January 2010

Current blade processors need air cooling solutions that dissipate 100–300 watts with heat sinks that are less than 30 mm high. In order to cool these processors, the heat sink base has to grow in length and width to compensate for the lack of available height. As these dimensions grow, decreasing the base spreading of the heat sink becomes an important factor is decreasing the overall resistance of the heat sink. A vapor chamber used as a substitute to common copper or aluminum as the base of the heat sink can increase performance by 20–25%. A vapor chamber is a two phase heat transport system that significantly reduces the spreading resistance in applications where there is a high heat flux processor coupled with a large heat sink. In this paper, a CFD model will be constructed to predict the performance gains realized by using a vapor chamber base in lieu of a copper or aluminum base. These predictions will then be experimentally tested to confirm the modeling parameters and the actual measured thermal performance of the heat sink. By utilizing vapor chambers in heat sink design, thermal engineers will gain valuable heat sink performance within the constraints imposed by the blade system architecture.
Fast and Accurate Simulation of Heat Transfer in Microarchitectures Using Frequency Domain Techniques
Authors: Etessam-Yazdani Keivan , Hamann Hendrik F. , Asheghi Mehdi
Published: January 2010

In this paper, a numerical method for calculating chip temperature profile, based on spatial frequency domain analysis of heat transfer, is presented. This approach takes advantage of transforming three-dimensional space domain heat transfer problems to two-dimensional problems in frequency domain. The preliminary results indicate that the present approach yields significant improvement in terms of accuracy, required memory, and computation time (e.g., by three orders of magnitude), compared to conventional space domain methods such as the finite element method. Clearly, additional rigorous and stringent tests are required to explore the pros and cons of the present approach.
Optimizing the Cycle Time of a Multi-Spindle Pick-and-Place Machine
Authors: Thiagarajan Ashok , Damodaran Purushothaman , Srihari Krishnaswami
Published: January 2010

A typical Printed Circuit Board (PCB) assembly line comprises of three major process steps, namely solder paste printing, component placement, and soldering. A stencil printer is typically used to deposit adequate amount of solder paste at appropriate locations on the PCB. One or more component placement (pick-and-place type) machines are then used to populate the PCB. Finally, the entire assembly is passed through an oven for establishing the solder joint. It has been widely accepted that the component placement step is usually the bottleneck. Consequently, the cycle time of the placement machine has to be reduced in order to improve the throughput of the assembly line. Placement machines are expensive and hence their benefit-cost ratio can be improved by improving their cycle time. The objective of this research was to reduce the cycle time of a pick-and-place component placement machine with multiple spindles. The pick-and-place machine chosen for this study was the bottleneck in an assembly line at an electronics manufacturing facility. The primary functions of a placement machine are (1) to pick components from feeder slots, (2) check for any defects using the vision system, and (3) to place the components at appropriate locations. Two important decisions which affect the cycle time are (1) feeder assignment (component location along the feeder rack) and (2) the component placement sequence. A heuristic was proposed to determine the feeder assignments and the component placement sequence was determined by solving a multiple Traveling Salesman Problem (mTSP). The objective of the feeder assignment problem was to minimize the distance traveled by the head along the feeder rack (during the pick cycle). The objective of the component placement sequencing problem was to minimize the distance traveled by the head over the PCB (during the placement cycle). The individual placement tours are later sequenced such that the number of nozzle changes required is minimized. The time taken to populate a board (time to pick + place + nozzle changeover) using the proposed approach was compared to the software which was supplied by the vendor of the machine. Several ‘production boards’ were chosen for this experimental study. The proposed solution approaches outperformed the solutions suggested by the machine’s software for all the ‘production boards’ experimented with. The resulting improvements in cycle times demonstrate the effectiveness of the proposed approach.
Reliability of Power Electronic Modules
Authors: Lu H. , Loh W. S. , Tilford T. , Johnson M. , Bailey C.
Published: January 2010

The electric car, the all electric aircraft and requirements for renewable energy are examples of potential technologies needed to address the world problem of global warming/carbon emission etc. Power electronics and packaged modules are fundamental for the underpinning of these technologies and with the diverse requirements for electrical configurations and the range of environmental conditions, time to market is paramount for module manufacturers and systems designers alike. This paper details some of the results from a major UK project into the reliability of power electronic modules using physics of failure techniques. This paper presents a design methodology together with results that demonstrate enhanced product design with improved reliability, performance and value within acceptable time scales.
Mold Adhesion Force Measurement
Authors: Lee Huei-Huang , Hwang Sheng-Jye , Huang Durn-Yuan , Lin Yeong-Jyh
Published: January 2010

During the encapsulation process of IC packages, when epoxy molding compound (EMC) is filling the mold cavity and cured in the mold, adhesion effects occur in the interface between EMC and mold surface. Adhesion effects can cause many problems. For example, too large an adhesion force may damage an IC during ejection and cause the package to fail and thus lower the yield rate and reliability. To get rid of the mold adhesion problems, improving the mold design and applying suitable surface treatments such as mold surface coating are the common approaches. Applying suitable surface coating is a more popular and practical approach. How to evaluate the mold adhesion force and use the data to improve products yield rate are the main issues for packaging. This paper uses a semi-automatic EMC adhesion force test instrument that had been developed and fabricated to measure normal and shear adhesion forces between the mold surface and EMC. By measuring the adhesion force, one can judge how much does a specific type of surface treatment help in reducing the amount of mold adhesion force. Nine kinds of various mold surface coating were tested with this instrument to measure the magnitude of adhesion force between EMC to determine the effectiveness of mold coating. The measured data showed that with different coatings on mold surface, the mold adhesion force can be very different. This paper also discussed the issue of successive normal force test. Engineers would use the most effective mold coating material to execute the continuous normal adhesion experiment. The variation of normal force during successive molding test could be used to predict the time for mold cleaning. By counting the total number of shots when the normal force begins to rise, engineers can accurately predict the number of shots for a specific kind of mold surface coating to be cleaned. This paper also described the effects of defrosting period on mold adhesion force of EMC. Defrosting is a process to increase the frozen EMC temperature to room temperature and stay at room temperature for some time before molding. It was found by molding engineers that increased defrosting time period would increase the frequency of mold cleaning. But there had been no quantitative description on how much mold adhesion force increase during the defrosting process. A semi-automatic EMC adhesion force test instrument was used to evaluate the effects of defrosting period on mold adhesion force of EMC. It was found that increase the defrosting time will increase the amount of adhesion force between EMC and mold surface. The higher is the relative humidity during defrosting on the adhesion force, the higher is the increase of adhesion force.
Genetic Algorithm for Nanoscale Electro-Thermal Optimization
Authors: Skorek Adam W. , Gryko-Nikitin Anna , Nazarko Joanicjusz
Published: January 2010

In this paper, we are presenting a genetic algorithm adopted for electro-thermal optimization in nanoelectronics devices and systems. The model of nanoelectronic system is simplified. Each heat source will be approximated by a specific function. The presented optimization strategy is designated for any system containing a number N of nanoelectronic elements. Optimization for the overall structure of the system will be performed in conformity with the temperature minimization criteria in the chosen areas of the system. Regarding others non unexpected modifications of the optimization algorithm, we are using a modified complex objective function.
Thermal Investigation of Interconnect Technologies for GaAs RF Power Amplifier in Handheld Applications
Authors: Lee Tien-Yu Tom , Chiriac Victor A.
Published: January 2010

Thermal simulation and infrared characterization are conducted to evaluate and compare the thermal performance of three interconnect options: wire bond, direct die attach, and flip chip interconnect. The test vehicle is a dual band RF PA module with low and high-band GaAs devices. As only one band is operated at a time, the focus is on the low-band GSM GaAs die. For direct die attach interconnect, the wire bond device is reused with all RF in/outs being connected from the backside of the GaAs device through individual vias in the device. The effects of through via design, solder attach material and thickness, and the thermal via layout in the substrate are evaluated. For flip chip interconnect, the original wire bond device was redesigned to accommodate metallic bumps for RF in/out, control and grounding. The ground bumps placed directly above the heat source area provide the main heat transfer path to the substrate. The size of the ground bumps, its material and the thermal vias layout in the substrate are investigated. Infrared thermal characterizations were conducted on both wire bond and direct die attach options to validate the simulations, with good agreement.
Modeling of Thin-Film Multi-Phase Heat Transfer With Statistical Thermodynamics
Authors: Pautsch Adam G. , Shedd Timothy A.
Published: January 2010

The power densities on computer chips have continued to rise, and power maps are further complicated by the addition of multiple cores. This in turn has made it very hard to achieve uniform junction temperatures across a device. Liquid cooling solutions, such as spray cooling, have the capability to remove the heat from the chips and maintain uniform junction temperatures. For the best possible performance, the contribution of bubbles in the flow must be better understood. Near a heat transfer surface, a temperature gradient exists in the flow. At the surface of the bubble, the fluid will vaporize or condense, depending on the local vapor and liquid temperatures and energy states at a given location. This means that a bubble can act as a heat pipe in certain conditions and move a large amount of heat with no net vapor generation. A model was written using the Statistical Rate Theory and principles of irreversible thermodynamics to analyze the amount of heat that is removed by a bubble at or near the surface through both latent and heat pumping effects.