bluuebunny/crossref_metadata_2025 huggingface dataset:
A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis
Authors: Łuba Tadeusz , Selvaraj Henry
Published: September 2007

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this
paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation
of the function by a set of r‐partitions over the set of minterms. Two different decomposition strategies, namely serial and
parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely
or incompletely specified, single‐ or multiple‐output functions and is suitable for different types of FPGAs including
XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,
in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.
A New Design Methodology for Two‐DimensionalLogic Arrays
Authors: Song Ning , Perkowski Marek A. , Chrzanowska-Jeske Malgorzata , Sarabi Andisheh
Published: September 2007

This paper introduces a new design approach that combines stages of logic and physical design. The logic function is
synthesized and mapped to a two‐dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitra
cascades. Each cell can be programmed to a wire, an inverter, or a two‐input AND, OR or EXOR gate (with any subset of
inputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its result
back to them. This two‐dimensional geometrical model is well suited for both fine‐grain FPGA realization and sea‐of‐gates
custom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and
produces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, and
column folding, are discussed in more details to illustrate our general methodology.
New Methods for the Construction of TestCases for Partitioning Heuristics
Authors: Saab Youssef
Published: September 2007

Partitioning is an important problem in the design automation of integrated circuits. This problem in many of its
formulation is NP‐Hard, and several heuristic methods have been proposed for its solution. To evaluate the
effectiveness of the various partitioning heuristics, it is desirable to have test cases with known optimal solutions
that are as “random looking” as possible. In this paper, we describe several methods for the construction of such
test cases. All our methods except one use the theory of network flow. The remaining method uses a relationship
between a partitioning problem and the geometric clustering problem. The latter problem can be solved in
polynomial time in any fixed dimension.
A Novel Path Delay Fault Simulator Using Binary Logic
Authors: Majhi Ananta K. , Jacob James , Patnaik Lalit M.
Published: September 2007

A novel path delay fault simulator for combinational logic circuits which is capable of
detecting both robust and nonrobust paths is presented. Particular emphasis has been given
for the use of binary logic rather than the multiple‐valued logic as used in the existing
simulators which contributes to the reduction of the overall complexity of the algorithm. A
rule based approach has been developed which identifies all robust and nonrobust paths
tested by a two‐pattern test , while backtracing from the POs to PIs in a depth‐first
manner. Rules are also given to find probable glitches and to determine how they propagate
through the circuit, which enables the identification of nonrobust paths. Experimental results
on several ISCAS′85 benchmark circuits demonstrate the efficiency of the algorithm.
Time‐ and Cost‐Optimal Parallel Algorithms for the Dominance and Visibility Graphs
Authors: Bhagavathi D. , Gurla H. , Olariu S. , Schwing J. L. , Zhang J.
Published: September 2007

The compaction step of integrated circuit design motivates associating several kinds of graphs with a collection of non‐overlapping rectangles in the plane. These graphs are intended to capture various visibility relations amongst the rectangles in the collection. The contribution of this paper is to propose time‐ and cost‐optimal algorithms to construct two such graphs, namely, the dominance graph (DG, for short) and the visibility graph (VG, for short). Specifically, we show that with a collection of n non‐overlapping rectangles as input, both these structures can be constructed in θ(log n) time using n processors in the CREW model.
Minimum‐Cost Node‐Disjoint Steiner Trees in Series‐Parallel Networks
Authors: Chopra Sunil , Talluri Kalyan T.
Published: September 2007

The routing problem in VLSI‐layout can be modeled as a problem of packing node‐disjoint Steiner trees in a graph. The problem is as follows: Given an undirected network G = (V, E) and a net list Ψ {Ni,  i  =  1, …,  r}
, a family
is a node‐disjoint family of Steiner trees spanning Ψ if
, is a Steiner tree spanning Ni
for i = 1, …, r and = for i ≠ j. The edge‐disjoint version of this problem is known to be NP‐hard for t. series‐parallel graphs (see Rlchey and Parker [5]). In this paper we give a O(n5)
algorithm for finding a minimum‐cost node‐disjoint family of Steiner trees in series‐parallel networks. Our algorithm can be extended to k‐trees and is polynomial for fixed k.
Integration of SPICE with TEK LV500 ASIC Design Verification System
Authors: Srivastava A. , Palavali S. R.
Published: September 2007

The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500). The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.
A Timing‐Driven Partitioning System for Multiple FPGAs
Authors: Roy Kalapi , Sechen Carl
Published: September 2007

Field‐programmable systems with multiple FPGAs on a PCB or an MCM are being used by system designers when a single FPGA is not sufficient. We address the problem of partitioning a large technology mapped FPGA circuit onto multiple FPGA devices of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre‐designed interconnection patterns of each FPGA and the package. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a timing driven N‐way partitioning algorithm based on simulated annealing for technology‐mapped FPGA circuits. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. Furthermore, we have incorporated a new dynamic net‐weighting scheme to minimize the number of pin‐outs for each chip. Finally, we have developed a graph‐based global router for pin assignment which can handle the pre‐routed connections of our MFS structure. In order to reduce the time spent in the simulated annealing phase of the partitioner, clusters of circuit components are identified by a new linear‐time bottom‐up clustering algorithm. The annealing‐based N‐way partitioner executes four times faster using the clusters as opposed to a flat netlist with improved partitioning results. For several industrial circuits, our approach outperforms the recursive min‐cut bi‐partitioning algorithm by 35% in terms of nets cut. Our approach also outperforms an industrial FPGA partitioner by 73% on average in terms of unroutable nets. Using the performance optimization capabilities in our approach we have successfully partitioned the MCNC benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length.
Application of Dynamic Supply Current Monitoring to Testing Mixed‐Signal Circuits
Authors: Al-Qutayri Mahmoud A. , Shepherd Peter R.
Published: September 2007

This paper applies the time‐domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in
CMOS mixed‐signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement
achieves higher confidence in the detection. Catastrophic, soft and stuck‐at single fault conditions were introduced to the circuit‐under‐test (CUT). The time‐domain technique tests
a mixed‐signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.
IDDQ Detectable Bridges in Combinational CMOS Circuits
Authors: Isern E. , Figueras J.
Published: September 2007

Undetectable stuck‐at faults in combinational circuits are related to the existence of logic
redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging
faults to become undetectable by IDDQ testing. An efficient method for the identification and
removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits
is presented. OBDD graphs are used to identify the functional equivalence of candidate to
f‐redundancy nodes. An f‐redundancy removal algorithm based on circuit transformations to
improve bridging fault testability, is also proposed. The efficiency of the identification and
removal of f‐redundancy has been evaluated on a set of benchmark circuits.
Testability‐Driven Layout of Combinational Circuits
Authors: Ravikumar C. P. , Sharma Nikhil
Published: September 2007

The layout of a circuit can influence the probability of occurrence of faults. In this
paper, we develop algorithms that can take advantage of this fact to reduce the chances
of hard‐to‐detect (HTD) faults from occurring. We primarily focus on line bridge faults
in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern
generator fails to generate a test vector for f in a reasonable amount of CPU‐time. It is
common practice to drop such HTD faults from consideration during test generation.
The chip fault coverage achieved by a test set is poor if the fault set consists of many
HTD faults. We can combat this problem by avoiding altogether, or by reducing the
probability of, the occurrence of HTD faults. In this paper, we consider hard‐to‐detect
bridging faults and show how module placement rules can be derived to reduce the
probability of these faults. A genetic placement algorithm that optimizes area while
respecting these rules is presented. The placement algorithm has been implemented for
standard‐cell layout style on a SUN/SPARC and tested against several sample circuits.
Moving Adaptive Unstructured 3‐D Meshes inSemiconductor Process Modeling Applications
Authors: Kuprat Andrew , George Denise , Linnebur Eldon , Trease Harold , Smith R. Kent
Published: September 2007

The next generation of semiconductor process and device modeling codes will require 3‐D
mesh capabilities including moving volume and surface grids, adaptive mesh refinement and
adaptive mesh smoothing. To illustrate the value of these techniques, a time dependent process
simulation model was constructed using analytic functions to return time dependent
dopant concentration and time dependent SiO2 volume and surface velocities. Adaptive mesh
refinement and adaptive mesh smoothing techniques were used to resolve the moving boron
dopant diffusion front in the Si substrate. The adaptive mesh smoothing technique involves
minimizing the L2 norm of the gradient of the error between the true dopant concentration
and the piecewise linear approximation over the tetrahedral mesh thus assuring that the mesh
is optimal for representing evolving solution gradients. Also implemented is constrained
boundary smoothing, wherein the moving SiO2/Si interface is represented by moving nodes
that correctly track the interface motion, and which use their remaining degrees of freedom to
minimize the aforementioned error norm. Thus, optimal tetrahedral shape and alignment is
obtained even in the neighborhood of a moving boundary. If desired, a topological “reconnection”
step maintains a Delaunay mesh at all times. The combination of adaptive refinement,
adaptive smoothing, and mesh reconnection gives excellent front tracking, feature resolution,
and grid quality for finite volume/finite element computation.
A 3D Nonlinear Poisson Solver
Authors: Veszely Gyula
Published: September 2007

The Poisson equation is solved in a rectangular prism of semiconductor with the
boundary conditions commonly used in semiconductor device modeling. There is a
planar heterojunction inside the prism. The finite difference formulation leading to a
matrix of seven diagonals is used. The 3D version of the Stone′s method is applied for
the iterative solution of the matrix equation. The nonlinear dependence of the carrier
concentration on the electrostatic potential is taken into account. The heterojunction is
modeled by a potential jump. The advantages and limits of the method is presented.
Self‐Checking Combinational Circuits with UnidirectionallyIndependent Outputs
Authors: Morosow A. , Saposhnikov V. V. , Saposhnikov Vl. V. , Goessel M.
Published: September 2007

In this paper we propose a structure dependent method for the systematic design of a self‐checking
circuit which is well adapted to the fault model of single gate faults and which
can be used in test mode.

According to the fault model considered, maximal groups of independent and
unidirectionally independent outputs of an arbitrarily given combinational circuit are
determined. A parity bit is added to every group of independent outputs. A few
additional outputs are added to every group of unidirectionally independent outputs. In
the error free case, these groups of unidirectional independent outputs together with their
corresponding additional outputs are elements of a unidirectional error detecting code;
for example, a Berger code or an r‐out‐of‐s code.

It is demonstrated how the pairs of (unidirectionally) independent outputs of a given
circuit can be determined. A simple heuristic solution for this problem based on a
modified circuit graph is also given.

The maximal classes of (unidirectionally) independent outputs can be computed as
cliques of a dependency graph where the nodes of the graph are the outputs of the circuit.
The applicability of the proposed method is demonstrated for the MCNC benchmarks
circuits.
Monte Carlo Analysis of Anisotropy in the TransportRelaxation Times for the Hydrodynamic Model
Authors: Brunetti Rossella , Vecchi Maria Cristina , Rudan Massimo
Published: September 2007

This paper investigates the anisotropy properties of the relaxation times used in the hydrodynamic
model. To this purpose a calculation of the collision term of the Boltzmann Transport
Equation is performed by means of a Monte Carlo code accounting for the proper band structure
and scattering features. Numerical results for electrons in silicon are shown at 77 and 300
K for E ║ <100> and E ║ <111>.
The Combination of Equipment Scale and Feature ScaleModels for Chemical Vapor Deposition Via aHomogenization Technique
Authors: Gobbert Matthias K. , Cale Timothy S. , Ringhofer Christian A.
Published: September 2007

In the context of semiconductor manufacturing, chemical vapor deposition (CVD) denotes
the deposition of a solid from gaseous species via chemical reactions on the wafer surface. In
order to obtain a realistic process model, this paper proposes the introduction of an intermediate
scale model on the scale of a die. Its mathematical model is a reaction‐diffusion equation
with associated boundary conditions including a flux condition at the micro structured surface.
The surface is given in general parameterized form. A homoganization technique from
asymptotic analysis is used to replace this boundary condition by a condition on the flat surface
to make a numerical solution feasible. Results from a mathematical test problem are
included.
Modeling of Shot Noise in ResonantTunneling Structures
Authors: Iannaccone G. , Macucci M. , Pellegrini B.
Published: September 2007

In this paper, we present insights into the transport properties and the geometrical
structure of resonant tunneling devices that can be obtained by the study of their noise
properties. We stress the importance of including noise behavior among the objectives
of device simulations. The reason is twofold: on one hand, as the number of carriers
involved in device operation decreases, fluctuations become more relevant; on the other
hand, in devices whose functionality is based on quantum effects, noise properties
strongly depend on the details of device geometry.
Inclusion of Bandstructure and Many‐Body Effectsin a Quantum Well Laser Simulator
Authors: Oyafuso F. , von Allmen P. , Grupen M. , Hess K.
Published: September 2007

A self‐consistent eight band k.p calculation, which takes into account strain and
includes Hartree, exchange, and correlation terms (determined from a local density
approximation) is incorporated into a QW laser simulator (MINILASE‐II). The
computation is performed within the envelope function approximation for a superlattice,
in which all spatially varying terms of the k.p Hamiltonian, including the
exchange and correlation energies are expanded in plane waves. The k.p eigenvalue
equation, and Poisson′s equation are solved iteratively until self‐consistency is attained.
Results from the k.p calculation are exported to MINILASE‐II via a density of states
and an energy dependent optical matrix element factor, renormalized by a Coulomb
enhancement factor to account for electron‐hole attraction. Results are presented for
the gain spectrum and modulation response for a Ga0.8 In0.2 As/Al0.1 Ga0.9 As quantum
well laser with and without the inclusion of the Coulomb enhancement factor.
Hydrodynamic Device Simulationwith New State Variables Specially Chosen fora Block Gummel Iterative Approach
Authors: Liang Wenchao , Kerr Daniel C. , Goldsman Neil , Mayergoyz Isaak D.
Published: September 2007

A new numerical formulation for solving the hydrodynamic model of semiconductor devices
is presented. The method is based on using new variables to transform the conventional
hydrodynamic equations into forms which facilitate numerical evaluation with a block Gummel
approach. To demonstrate the new method, we apply it to model a 0.35 μm 2‐D LDD
MOSFET, where robust convergence properties are observed.
Statistical Enhancement of Terminal Current Estimation forMonte Carlo Device Simulation
Authors: Yoder P. D. , Krumbein U. , Gärtner K. , Sasaki N. , Fichtner W.
Published: September 2007

We present a new generalized Ramo‐Shockley theorem (GRST) to evaluate contact currents,
applicable to classical moment‐based simulation techniques, as well as semiclassical Monte
Carlo and quantum mechanical transport simulation, which remains valid for inhomogeneous
media, explicitly accounts for generation/recombination processes, and clearly distinguishes
between electron, hole, and displacement current contributions to contact current. We then
show how this formalism may be applied to Monte Carlo simulation to obtain equations for
minimum‐variance estimators of steady‐state contact current, making use of information
gathered from all particles within the device. Finally, by means of an example, we demonstrate
this technique’s performance in acceleration of convergence time.
Transient Phenomena in High Speed Bipolar Devices
Authors: Obrecht Michael S. , Heasell Edwin L. , Vlach J. , Elmasry Mohamed I.
Published: September 2007

A new numerical method is applied to the analysis of the charge partitioning in the
quasi‐neutral base of a BJT. The results show that the conventional, 1:2 collector/
emitter partitioning is not valid in general. High level injection increases the collector
fraction, whilst fast switching decreases it.
On Self‐Checking Design of CMOS Circuits for Multiple Faults
Authors: Busaba Fadi , Lala Parag K. , Walker Alvernon
Published: September 2007

A technique for designing totally self‐checking (TSC) FCMOS (Fully Complementary
MOS) designs for multiple faults is presented in this paper. The existing techniques for
self checking design consider only single faults, and suffer from high silicon area
overhead. The multiple faults considered in this paper are multiple breaks, multiple
transistors stuck‐offs and multiple transistors stuck‐ons. Starting from FCMOS design,
small modifications (addition of two‐weak transistors) make the original circuit totally
self‐checking. Experiemntal results show the overhead, delay and power consumption
for the proposed technique. This paper also presents a technique for designing
multistage TSC FCMOS circuits.
Cellular Automaton Study of Time‐Dynamicsof Avalanche Breakdown in IMPATT Diodes
Authors: Zandler G. , Oberhuber R. , Liebig D. , Vogl P. , Saraniti M. , Lugli P.
Published: September 2007

Employing a recently developed efficient cellular automaton technique for solving
Boltzmann’s transport equation for realistic devices, we present a detailed study of the
carrier dynamics in GaAs avalanche p-i-n (IMPATT) diodes. We find that the impact
ionization in reverse bias p-i-n diodes with ultrathin (less than 50 nm) intrinsic regions is
triggered by Zener tunneling rather than by thermal generation. The impact generation
of hot carriers occurs mainly in the low‐field junction regions rather than in the high
field intrinsic zone. The calculations predict significantly more minority carriers on the
n‐side than on the p‐side.
Monte Carlo Simulation of HEMT based on Self‐Consistent Method
Authors: Ueno H. , Yamakawa S. , Hamaguchi C. , Miyatsuji K.
Published: September 2007

Device simulation of HEMT (High Electron Mobility Transistor) has been carried out by
ensemble Monte Carlo simulation, where two‐dimensional motion of electrons confined in
GaAs region at GaAs/AIGaAs heterointerface is taken into account. In order to develop a
realistic device simulator of HEMT, we divide the channel region in meshes, and Schrödinger
and Poisson equations are solved self‐consistently to obtain electronic states of the twodimensional
electrons in a mesh. In addition the real space transfer from GaAs layer into
AIGaAs barrier layer is taken into account.
Comparison of Iteration Schemes for the Solution of theMultidimensional Schrödinger‐Poisson Equations
Authors: Trellakis A. , Galick A. T. , Pacelli A. , Ravaioli U.
Published: September 2007

We present a fast and robust iterative method for obtaining self‐consistent solutions to the
coupled system of Schrödinger′s and Poisson′s equations in quantum structures. A simple
expression describing the dependence of the quantum electron density on the electrostatic
potential is used to implement a predictor – corrector type iteration scheme for the solution
of the coupled system of differential equations. This approach simplifies the software
implementation of the nonlinear problem, and provides excellent convergence speed and
stability. We demonstrate the algorithm by presenting an example for the calculation ofthe
two‐dimensional bound electron states within the cross‐section of a GaAs‐AlGaAs based
quantum wire. For this example, six times fewer iterations are needed when our predictor – corrector
approach is applied, compared to a corresponding underrelaxation algorithm.
Quantum Transport and Thermoelectric Propertiesof InAs/GaSb Superlattices
Authors: Lin J.-F. , Ting D. Z.-Y.
Published: September 2007

In recent years, artificially layered microstructure have been considered as candidates
for better thermoelectrics. In this work we examine transport properties of the type‐II
broken‐gap InAs/GaSb superlattice. We use the effective bond orbital model for an
accurate description of the band structures. Theoretical results of thermoelectric
transport coefficients and the dimensionless figure of merit for an (8, 8)‐InAs/GaSb
type‐II superlattice are presented.
Calibration of a One Dimensional HydrodynamicSimulator with Monte Carlo Data
Authors: Muscato O. , Rinaudo S. , Falsaperla P.
Published: September 2007

In this paper we use the code Exemplar for matching a hydrodynamic 1D, time‐dependent
simulator and the transport coefficients obtained by the Monte Carlo
simulator Damocles. This code is based on the Least Square method and it does not
require any a priori knowledge about the simulator (analytical form of the equations
etc.). The stationary electron flow in a one dimensional n+ − n − n+ submicron silicon
diode is simulated.
Monte Carlo Simulation of Non‐Local Transport Effectsin Strained Si on Relaxed Si1 – xGex Heterostructures
Authors: Gámiz F. , Roldán J. B. , López-Villanueva J. A.
Published: September 2007

Electron transport properties of strained‐Si on relaxed Si1 – xGex channel MOSFETs have been studied using a Monte Carlo simulator. The steady‐ and non‐steady‐state
high‐longitudinal field transport regimes have been described in detail. Electronvelocity‐
overshoot effects are studied in deep‐submicron strained‐Si MOSFETs, where
they show an improvement over the performance of their normal silicon counterparts.
The impact of the Si layer strain on the performance enhancement are described in
depth in terms of microscopic magnitudes.
Exploiting Sleep Mode for Memory Partitioning and Other Applications
Authors: Farrahi Amir H. , Téllez Gustavo E. , Sarrafzadeh Majid
Published: September 2007

Sleep mode operation and exploiting it to minimize the average power consumption are
of great importance in modern VLSI circuits. In general, sleep mode refers to the mode
in which part(s) of the system are idle. In this paper, we study the problem of
partitioning a circuit according to the activity patterns of its elements such that circuit
elements with similar activity patterns are packed into the same partition. Then a
partition can be placed in sleep mode during the time intervals all elements contained in
that partition are idle. We formulate the partitioning problem to exploit sleep mode
operation and show that the problem is NP‐complete. We present polynomial time
algorithms for practical classes of the problem. Applications of the problem to memory
and module partitioning and clock gating are discussed. The experimental data confirm
that a careful partitioning allows upto 40% more sleep time which could be exploited to
minimize the average power consumption.
Two‐dimensional Carrier Transport in Si MOSFETs
Authors: Takagi Shin-Ichi
Published: September 2007

The importance of 2‐dimensional (2D) features of carriers in Si MOSFETs on the device
performance is re‐examined experimentally and theoretically from the viewpoint of low‐field
mobility, velocity in high tangential fields and the inversion‐layer capacitance. It is
confirmed that low‐field mobility and inversion‐layer capacitance can be understood
well in terms of the 2D subbands and the 2D carrier transport. In order to obtain fully‐quantitative
understanding of low‐field mobility, however, it is still necessary to more
accurately determine the amount of the scattering parameters in the inversion layer. On
the other hand, saturation velocity is considered to be less influenced by the 2D
quantization, while it is found experimentally that saturation velocity is slightly
dependent on surface carrier concentration.

According to the knowledge of 2‐dimensional carrier transport in Si inversion layer,
an effective way to have higher current drive is to increase the occupancy of the 2‐fold
valleys, which have lower conductivity mass, on a (100) surface. From this viewpoint,
two device structures, strained Si MOSFETs and SOI MOSFETs with ultra‐thin SOI
films, are introduced and the behavior of low‐field mobility is analyzed through the
calculations of the subband structures and phonon‐limited mobility.
Modeling of Poly‐Silicon Carrier Transport with ExplicitTreatment of Grains and Grain Boundaries
Authors: Kan Edwin C. , Dutton Robert W.
Published: September 2007

Explicit treatment of grains and grain boundaries is necessary to model the carrier
transport in poly‐silicon devices whose feature size is comparable to the grain size. The
grain boundaries were modeled by interface traps, and comparison was made between
thermionic and diffusion transport across the grain boundaries. It was found that the
numerical model for diffusion transport with total trap conservation in grain boundary
areas is not physically convergent and shows a strong grid sensitivity. Effects of the
critical doping level and the lattice temperature are demonstrated on poly‐silicon
resistors with 1‐D bamboo‐type and 2‐D realistic microstructures.
A Lattice Boltzmann Scheme for Semiconductor Dynamics
Authors: Succi S. , Vergari P.
Published: September 2007

We discuss an extension of the Lattice Boltzmann method which may prove useful for the
numerical study of electron transport in semiconductors.
Applicability of the High Field Model: A PreliminaryNumerical Study
Authors: Cercignani Carlo , Gamba Irene M. , Jerome Joseph W. , Shu Chi-Wang
Published: September 2007

In a companion presentation, we have discussed the theory of a mesoscopic/
macroscopic model, which can be viewed as an augmented drift‐diffusion model. Here,
we describe how that model is used. The device we consider for this presentation is the
one dimensional GaAs n+ − n − n+ structure of length 0.8μm. First, a full Hydro‐
Dynamic (HD) model, proven reliable when compared with Monte Carlo simulations, is
used to simulate the device via the ENO finite difference method. As applied to the full
device, the new model is not necessarily superior to traditional Drift‐Diffusion (DD).
Indeed, when we plot the quantity , where μ0 is the mobility constant
and E = −ϕ′ is the electric field, we verify that the high field assumption η › 1, required
for the high field model, is satisfied only in an interval given approximately by [0.2, 0.5].
When we run both the DD model and the new high field model in this restricted interval,
with boundary conditions of concentration n and potential ϕ provided by the HD
results, we demonstrate that the new model outperforms the DD model. This indicates
that the high field and DD models should be used only in parts of the device, connected
by a transition kinetic regime. This will be a domain decomposition issue involving
interface conditions and adequate numerical methods.
Inclusion of Quantum Confinement Effects in Self‐Consistent Monte Carlo Device Simulations
Authors: Kelsall R. W. , Lidsey A. J.
Published: September 2007

The design of Monte Carlo FET simulations is discussed, with specific attention to the methods used to describe quantum confinement effects. A new model is presented, which employs self‐consistent coupling of Schrodinger, Poisson and Monte Carlo algorithms, and explicit calculation of the scattering rates between confined and unconfined states. Comparisons between the new model and a standard semi‐classical Monte Carlo model are presented for a 0.1 μm gate‐length In0.52Al0.48As/In0.53 Ga0.47As/InP MODFET. Whilst the quantum model yields minor corrections in the predicted output characteristics, it is found that these results can be achieved without repeated iterations of the Schrodinger equation.
An Alternative Geometry for Quantum Cellular Automata
Authors: Krause Paul G. , Mueller Rachel M. , Tougaw P. Douglas , Weidner Janelle M.
Published: September 2007

We examine an alternative layout geometry for the quantum cellular automata (QCA)
architecture. In the traditional QCA geometry, all of the cells are placed in a single
plane, so that each cell interacts with a particular neighbor only along one of its edges.
By rotating the cells out of the plane, we make it possible for neighbors to interact along
all four edges at once. This increased interaction leads to a more bistable cell‐cell
response function and a 50% higher excitation energy. We also present a majority logic
gate designed using three‐dimensional cells.
Testing Hydrodynamical Models on the Characteristics of a One‐Dimensional Submicrometer Structure
Authors: Anile A. M. , Muscato O. , Rinaudo S. , Vergari P.
Published: September 2007

Recent advances in technology leads to increasing high speed performance of submicrometer
electron devices by the scaling of both process and geometry. In order to aid the design of
these devices it is necessary to utilize powerful numerical simulation tools. In an industrial
environment the simulation codes based on the Drift‐Diffusion models have been widely
used. However the shrinking dimension of the devices causes the Drift‐Diffusion based simulators
to become less accurate. Then it is necessary to utilize more refined models (including
higher order moments of the distribution function) in order to correctly predict the behaviour
of these devices. Several hydrodynamical models have been considered as viable simulation
tools. It is possible to discriminate among the several hydrodynamical models on the basis of
their results on the output characteristics of the electron device which are measurable (I‐V
curves). We have analyzed two classes of hydrodynamical models: i) HFIELDS hydrodynamical
models and HFIELDS drift‐diffusion model; ii) self‐consistent extended hydrodynamical
models with relaxation times determined from Monte Carlo simulations.
Resonances in Conductance Through Tunable Attractors
Authors: Joe Yong S. , Cosby Ronald M.
Published: September 2007

We present the effects of resonant tunneling through doubly‐coupled attractors in series
in a quantum nanosystem. It is found that multiple split‐tunneling peaks arise from
resonant tunneling through multiple nondegenerate quasi‐bound‐states of the coupled
attractors. We show that the tunability of coupling is achieved by modulating the
strength of the attractor for a fixed separation length between the attractors, and by
adjusting the geometrical separation length for a fixed intervening barrier strength.
Beating in the RHEED Intensity Oscillationsduring Surfactant Mediated GaAsMolecular Beam Epitaxy: Process Physicsand Modeling
Authors: Pamula Vamsee K. , Venkat R.
Published: September 2007

In a recent work, beating in the reflection high energy electron diffraction (RHEED) intensity
oscillations were observed during molecular beam epitaxial (MBE) growth of GaAs with Sn as a surfactant. The strength of beating is found to be dependent on the Sn submonolayer coverage with strong beating observed for 0.4 monolayer coverage. For a fixed temperature and
flux ratio (Ga to As), the period of oscillation decreases with increasing Sn coverage. In this
work, we have developed a rate equation model of growth to investigate this phenomenon. In
our model, the GaAs covered by the Sn is assumed to grow at a faster rate compared to the
GaAs not covered by Sn. Assuming that the electron beams reflected from the Sn covered surface
and the rest of the surface are incoherent, the results of the dependence of the RHEED
oscillations on Sn submonolayer coverages for various Sn coverages were obtained and compared
with experimental data and the agreement is good.
Computation of the Spectral Density of CurrentFluctuations in Bulk Silicon Based on the Solution of theBoltzmann Transport Equation
Authors: Piazza Alfredo J. , Korman Can E.
Published: September 2007

Numerical simulation results for the spectral density of noise due to current fluctuations are
presented. The mathematical framework is based on the interpretation of the equations
describing electron transport in the semiclassical transport model as stochastic differential
equations (SDE). Within this framework, it was previously shown that the autocovariance
function of current fluctuations can be obtained from the transient solution of the Boltzmann
transport equation (BTE) with special initial conditions. The key aspect which differentiates
this approach from other noise models is that this approach directly connects noise characteristics
with the physics of scattering in the semiclassical transport model and makes no additional
assumptions regarding the nature of noise. The solution of the BTE is based on the
Legendre polynomial method. A numerical algorithm is presented for the solution of the transient
BTE. Numerical results are in good agreement with Monte Carlo noise simulations for
the spectral density of current fluctuations in bulk silicon.
Power Distribution Synthesis for VLSI
Authors: Vittal Ashok , Marek-Sadowska Malgorzata
Published: September 2007

The synthesis of the power distribution network is an important problem in the layout
design of VLSI systems. In this paper we propose novel methods to solve the problem of
designing minimal area power distribution nets, while satisfying voltage drop and
electromigration constraints. We will see that our methods significantly improve upon
current techniques. We propose two novel greedy heuristics for power net design‐one
based on bottom‐up tree construction using greedy merging and the other based on top‐down
linearly separable partitioning. We test the efficacy of our techniques on
benchmark instances. The areas required by our methods on typical instances are
significantly smaller than those obtained using previous methods.
Self‐Consistent Scattering Calculation of Resonant Tunneling Diode Characteristics
Authors: Sun J. P. , Haddad G. I.
Published: September 2007

We perform a self‐consistent calculation of resonant tunneling diode (RTD) I‐V characteristics
including optical phonon scattering. The self‐consistency is obtained by solving the
Schrödinger equation and Poisson’s equation iteratively with the Thomas‐Fermi approximation
used for the device contact regions. For evaluation of phonon‐assisted current density,
the optical phonon scattering in the quantum well is modeled using the optical model potential.
Electron transverse momentum is also incorporated. The calculated current and electron
wavefunction illustrate the optical model and effects of the phonon scattering on the current
transport. The I‐V characteristics we obtain from the model calculation are in good agreement
with experimental results. This work manifests the importance of including self‐consistency,
optical phonon scattering, and electron transverse momentum in modeling realistic RTD
structures.
Theory and Modeling of Lasing Modes in Vertical Cavity Surface Emitting Lasers
Authors: Klein Benjamin , Register Leonard F. , Hess Karl , Deppe Dennis
Published: September 2007

The problem of obtaining the lasing modes and corresponding threshold conditions for vertical cavity surface emitting lasers (VCSELs) is formulated as a frequency-dependent eigenvalue problem in required gain amplitudes and corresponding fields. Both index and gain guiding are treated on an equal footing. The complex gain eigenvalues define necessary but not sufficient conditions for lasing. The actual lasing frequencies and
modes that the VCSEL can support are then determined by matching the gain necessary for the optical system in both magnitude and phase to the gain available from the laser′s electronic system. Examples are provided.
Single‐Electron Memories
Authors: Wasshuber Christoph , Kosina Hans , Selberherr Siegfried
Published: September 2007

One of the most promising applications of single‐electronics is a single‐electron memory
chip. Such a chip would have orders of magnitude lower power consumption compared
to state‐of‐the‐art dynamic memories, and would allow integration densities beyond the
tera bit chip.We studied various single‐electron memory designs. Additionally we are
proposing a new memory cell which we call the T‐memory cell. This cell can be
manufactured with state‐of‐the‐art lithography, it operates at room temperature and
shows a strong resistance against random background charge.
An Improved Ionized Impurity Scattering Model forMonte Carlo Calculations
Authors: Kaiblinger-Grujin G. , Kosina H.
Published: September 2007

The well known Brooks‐Herring (BH) formula for charged‐impurity (CI) scattering overestimates
the mobility of electrons in highly doped semiconductors. The BH approach relies on a
static, single‐site description of the carrier‐impurity interactions neglecting many‐particle
effects. We propose a physically based charged‐impurity scattering model including Fermi‐
Dirac statistics, dispersive screening, and two‐ion scattering. An approximation for the dielectric
function is made to avoid numerical integrations. The resulting scattering rate formulas
are analytical. Monte Carlo calculations were performed for majority electrons in bulk silicon
at 300 K with impurity concentrations from 1015 cm‐3 to 1021 cm‐3.
Gridding and Discretization For Divergence Form(Semiconductor‐Like) PDEs
Authors: Kao Ming Y. , Rose Donald J. , Shao Hai
Published: September 2007

We develop the box method for solving partial differential equations in the divergence (or
conservation law) form. We first use graphic theoretical approaches to generate grids, i.e. partition
the governing domain into boxes. Then we apply Green’s theorem box‐wisely and the constant-j assumption edge‐pair‐wisely to obtain the discretization system of equations,
which lead to the numerical solution to the problem. We show that the box method is inherently
more efficient than the traditional finite element method for linear (or convection-diffusion)
problems in and 2 dimensions. We also present some potential thoughts on
implementing the box method for problems in higher dimensions and with nonlinearity.
Additive Decomposition Applied to the SemiconductorDrift‐Diffusion Model
Authors: Brauer Elizabeth J. , Turowski Marek , McDonough James M.
Published: September 2007

A new numerical method for semiconductor device simulation is presented. The additive
decomposition method has been successfully applied to Burgers′ and Navier‐Stokes
equations governing turbulent fluid flow by decomposing the equations into large‐scale
and small‐scale parts without averaging. The additive decomposition (AD) technique is
well suited to problems with a large range of time and/or space scales, for example,
thermal‐electrical simulation of power semiconductor devices with large physical size.
Furthermore, AD adds a level of parallelization for improved computational efficiency.
The new numerical technique has been tested on the 1‐D drift‐diffusion model of a p-i-n
diode for reverse and forward biases. Distributions of φ, n and p have been calculated using the AD method on a coarse large‐scale grid and then in parallel small‐scale grid
sections. The AD results agreed well with the results obtained with a traditional one‐grid
approach, while potentially reducing memory requirements with the new method.
Routability Crossing Distribution and Floating Pin Assignment for T‐type Junction Region
Authors: Yan Jin-Tai
Published: September 2007

Based on non‐crossing relations, vertical constraint relations and net‐geometry relations
in one T‐type junction region, two kinds of routability crossing distributions are
proposed to improve routing performance in one T‐type junction region. For routability
crossing distribution in one T‐type junction region, a routability‐ordering graph is built
to decide a net ordering in O(n2) time. For routability quota crossing distribution in one
T‐type junction region, if the number of net crossings in base channel is more than a
given quota, this net ordering in routability crossing distribution will be further adjusted
to satisfy the quota requirement by using a net interchange operation in O(n) time. For
floating pin assignment in one T‐type junction region, global nets are assigned on the
boundary between top channel and base channel by interleaving vacant pins in O(n)
time according to a net ordering in routability crossing distribution.
Semi‐classical Limit in a Semiconductor Superlattice
Authors: Bechouche Philippe
Published: September 2007

In this paper, we perform a mathematical study of a semiconductor superlattice. Since the
thickness of the layers is very small, quantization plays an important role. The modelling
is therefore given by a Schrödinger equation with a periodic potential. The scaled lattice
thickness is denoted by a small parameter ℇ which is of the same order of magnitude as
the Planck constant. When this parameter tends to zero, i.e., the semi‐classical limit, we
obtain classical transport of the charge carriers described by a Vlasov equation.
A Wignerfunction Approach to Phonon Scattering
Authors: Frommlet Florian , Markowich Peter A. , Ringhofer Christian
Published: September 2007

We consider the motion of a single electron under phonon scattering caused by a crystal
lattice. Starting from the Fröhlich Hamiltonian in the second quantization formalism
we derive a kinetic transport model by using the Wigner transformation. Under the
assumption of small electron‐phonon interaction we derive asymptotically the operator
representing electron‐phonon scattering in the Wigner equation. We then consider some
scaling limits and finally we give the connection of our result to the well known Barker‐Ferry equation.
Semiclassical Analysis of Discretizationsof Schrödinger‐type Equations
Authors: Markowich Peter A. , Pietra Paola , Pohl Carsten
Published: September 2007

We apply Wigner‐transform techniques to the analysis of difference methods for
Schrödinger‐type equations in the case of a small Planck constant. In this way we are
able to obtain sharp conditions on the spatial‐temporal grid which guarantee convergence
for average values of observables as the Planck constant tends to zero. The
theory developed in this paper is not based on local and global error estimates and does
not depend on whether caustics develop or not.

Numerical examples are presented to help interpret the theory.
System‐level Time‐stationary Control Synthesis forPipelined Data Paths
Authors: Kim Jong Tae , Kurdahi Fadi J. , Park Noh Byung
Published: September 2007

We address the prblem of time‐stationary control synthesis for pipelined data paths.
Control synthesis system accepts scheduled control data flow graph with conditional
branches which are produced by high level synthesis tools such as Sehwa [1] as input
specification and generates a FSM controller. First a scheduled control/data flow graph
is analyzed and the various states are identified. Overlapped states are grouped together
to produce L groups where L is the pipeline latency. Next, state transitions are identified
and a state table is generated. Finally, a highly optimized FSM controller is
implemented by performing horizontal partitioning and the corresponding stae
encoding so as to minimize the total controller area. We compared our approach to
published work on FSM generation and optimization and the results indicate that our
method results in large savings in total controller area.