bluuebunny/crossref_metadata_2025 huggingface dataset:
Analysis and Design of Regular Structures for RobustDynamic Fault Testability
Authors: Bryan Michael J. , Devadas Srinivas , Keutzer Kurt
Published: September 2007

Recent methods of synthesizing logic that is fully and robustly testable for dynamic faults, namely path delay,
transistor stuck‐open and gate delay faults, rely almost exclusively on flattening given logic expressions into sum‐of‐products form, minimizing the cover to obtain a fully dynamic‐fault testable two‐level representation of the
functions, and performing structural transformations to resynthesize the circuit into a multilevel network, while
also maintaining full dynamic‐fault testability. While this technique will work well for random or control logic,
it is not practical for many regular structures.To deal with the synthesis of regular structures for dynamic‐fault testability, we present a method that involves
the development of a library of cells for these regular structures such that the cells are all fully path‐delay‐fault,
transistor stuck‐open fault or gate‐delay‐fault testable. These cells can then be utilized whenever one of these
standard functions is encountered.We analyze various regular structures such as adders, arithmetic logic units, comparators, multipliers, and parity
generators to determine if they are testable for dynamic faults, or how they can be modified to be testable for
dynamic faults while still maintaining good area and performance characteristics. In addition to minimizing the
area and delay, another key consideration is to get designs which can be scaled to an arbitrary number of bits
while still maintaining complete testability. In each case, the emphasis is on obtaining circuits which are fully
path‐delay‐fault testable. In the process of design modification to produce fully robustly testable structures, we
have derived a number of new composition rules that allow cascading individual modules while maintaining robust
testability under dynamic fault models.
An Optimum Channel Routing Algorithm in theKnock‐knee Diagonal Model
Authors: Song Xiaoyu
Published: September 2007

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In this
paper, we consider the two‐terminal channel routing problem in a new routing model, called knock‐knee diagonal
model, where the grid consists of right and left tracks displayed at +45° and –45°. An optimum algorithm is
presented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.
Resolution Enhancement in IDDQ Testingfor Large ICs
Authors: Malaiya Yashwant K. , Jayasumana Anura P. , Tong Carol Q. , Menon Sankaran M.
Published: September 2007

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is
normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many
faults present in such ICs cause the quiescent power‐supply current (IDDQ) to increase by several orders of
magnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected by
traditional IC test techniques.In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due to
normal parameter variations. A statistical characterization of the problem is presented. This can be used to
determine the optimal size of partitions. A new information compression scheme is presented which can significantly
enhance resolution.
Techniques for Self‐Checking Combinational LogicSynthesis
Authors: Busaba Fadi , Lala Parag K.
Published: September 2007

This paper presents techniques for designing arbitrary combinational circuits so that any single stuck‐at fault will
result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using
Berger code or m‐out‐of‐n code, then the proposed technique will enable on‐line detection of faults in the circuit.
An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is
presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either
produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault
which produces bidirectional error, no internal stuck‐at fault will result in such an error irrespective of the way
the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a
fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead
is estimated.
TOPS: A Target‐Oriented Partial Scan DesignPackage Based on Simulated Annealing
Authors: Ravikumar C. P. , Rasheed H.
Published: September 2007

In this paper, we describe algorithms based on Simulated Annealing for selecting a subset of flip‐flops to be
connected into a scan path. The objective for selection is to maximize the coverage of faults that are aborted by
a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm
based on Simulated Annealing. The SCOAP testability measure is employed to assess the selection of flip‐flops
during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which has
been designed as an enhancement to the OASIS standard‐cell design automation system available from MCNC.
We discuss the TOPS package and its performance on a number of ISCAS′89 benchmarks. We also present a
comparative evaluation of the benchmark results.
Register‐Transfer Synthesis of Pipelined Data Paths
Authors: Park Nohbyung , Kurdahi Fadi J.
Published: September 2007

We present a new approach to the problem of register‐transfer level design optimization of pipelined data paths.
The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps,
and a fixed set of hardware operators. In order to obtain a register‐transfer level design, we must assign operations
to specific operators, values to registers, and finish the interconnections. We first perform module assignment
with the goal of minimizing the interconnect requirements between RT‐level components as a preprocessing
procedure to the RT‐level design. This will result in a smaller netlist which makes the design more compact and
the design process more efficient. In addition to reducing the total number of interconnects, this approach will
also reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputs
of shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. We
developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30–50 times faster than other existing heuristics while still producing better results for our purposes. Using this
procedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical size
pipelined designs. This efficient approach will enable designers to explore a larger portion of the design space
and trade off various design parameters effectively.
Building Rectangular Floorplans–A GraphTheoretical Approach
Authors: Jabri Marwan A.
Published: September 2007

Rectangular dualisation is a technique used to generate rectangular topologies for use in top‐down floorplanning
of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity
graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient
algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph
that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the
global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting
floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also
introduces a novel technique to transform a tree of biconnected sub‐graphs into a block neighbourhood graph
that is a path.
Analysis and Characterization of State AssignmentTechniques for Sequential Machines
Authors: Makki R. Z. , Su S.
Published: September 2007

In this paper, we study the problem of state assignment as it relates to silicon area, propagation delay time and
testability of finite state machines. The results of a study involving various FSM benchmarks show that the simple
technique of one‐hot encoding often produces better results than those attained by complex state assignment
algorithms.
Geometric Design Rule Check of VLSI Layouts inDistributed Computing Environment
Authors: Nandy S. K.
Published: September 2007

In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting
either spatial independence or layer independence in layout data. We show that the former approach to DRC
can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance
for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC
tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.
Block‐Level Logic Extraction from CMOS VLSILayouts
Authors: Bhasin Inderpreet , Tront Joseph G.
Published: September 2007

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description
of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that
of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors,
resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used
to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the
circuit hierarchy. Basic gates such as inverters, transmission‐gates, nands, nors, etc. are identified first. Logic
blocks composed of these gates are then identified. More complex blocks which contain blocks already identified
are recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It can
provide a connectivity check for a circuit.
Channel Density Minimization by Pin Permutation
Authors: Cai Yang , Wong D. F. , Cong Jason
Published: September 2007

We present in this paper a linear time optimal algorithm for minimizing the density of a channel (with exits) by
permuting the terminals on the two sides of the channel. This compares favorably with the previously known
near‐optimal algorithm presented in [6] that runs in superlinear time. Our algorithm has important applications
in hierarchical layout design of intergrated circuits. We also show that the problem of minimizing wire length by
permuting terminals is NP‐hard in the strong sense.
High Throughput Error Control Using Parallel CRC
Authors: Sobski Andrzej , Albicki Alexander
Published: September 2007

Redesigning the LFSR (Linear Feedback Shift Register) so that syndrome calculations can be performed in one
sweep allows for fast error control in high speed computer networks. The resulting structure forms the basis of
the PEDDC (Parallel Encoder, Decoder, Detector, Corrector) which replaces the conventional Serial Encoder,
Decoder, Detector, Corrector for generation and utilization of cyclic codes. Since syndromes are calculated in
as little as one clock period, information from which the syndrome is calculated can be processed in a parallel
stream. In this paper a simple PEDDC is built, its operation is examined in detail, its performance is compared
with a serial counterpart, possible variations on the PEDDC structure is given, and further speed enhancement
techniques are considered.
A VHDL Based Expert System for HardwareSynthesis
Authors: Shiva Sajjan G. , Jones Judit U.
Published: September 2007

This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input to
the expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The
VHDL representation is first translated to a knowledge representation scheme known as a ‘hologram’ which is a
combination of rule, frame and semantic network representation schemes. The hologram representation of the
target system is then input to the inference engine, which matches the target system to the Knowledge Base
components and selects an appropriate set for implementation, and connects them creating a digital circuit. Some
design examples are described. The expert system approach results in designs very close to designs from a human
designer. In its present form, the system does not perform a design space exploration for alternate designs, but
expects the designer to alter the VHDL representation, after observing the results from previous design cycles.
Hydrodynamic Models of SemiconductorElectron Transport at High Fields
Authors: Ancona M. G.
Published: September 2007

Hydrodynamic or continuum descriptions of electron transport have long been used for modeling and simulating
semiconductor devices. In this paper, we use classical field theory ideas to discuss the physical foundations of such
descriptions as applied specifically to high‐field transport regimes. The classical field theory development of these
types of models is of interest because it differs significantly from and may be viewed as complementary to
conventional derivations based on the Boltzmann equation: After outlining the general field theoretic principles
upon which our development of fluid‐based high‐field transport descriptions is based, we study several specific
models both analytically and using numerical simulation. These models provide an overall framework for
understanding and extending various theories which have appeared in the literature. Most importantly, they
emphasize the importance of including memory or history effects and viscosity in describing high‐field transport.
In all of this our aim is a unified and synoptic view unencumbered with microscopic details. Obtaining quantitative
agreement with specific experiments and/or microscopic simulations is only of secondary importance. We share
the view that continuum approaches can provide succinct and computationally‐efficient models needed for current
and future semiconductor device analysis and engineering. At the same time, we believe that these models need
not be phenomenological but can be given solid physical foundation in macroscopic principles.
The Response of the Hydrodynamic Modelto Heat Conduction, Mobility,and Relaxation Expressions
Authors: Jerome Joseph W. , Shu Chi-Wang
Published: September 2007

We study simulations of then+‐n‐n+ diode, by means of higher moment models, derived from the Boltzmann
equation. We emply such realistic assumptions as energy dependent mobility functions, with doping dependent
low field mobility. It is known that a critical role is played in the hydrodynamic model by the heat conduction
term. When the standard choice of the Wiedemann‐Franz law is made for the conductivity, and constant low field
mobility values are used, spurious overshoot is observed. Agreement with Monte‐Carlo simulation in this regime
has in the past been achieved by empirical modification of this law. In this paper, we consider the effect of
representing the heat flux by the sum of two terms. It is found that the effect is negligible with respect to
overshoot in comparison to that achieved by employing a doping dependent low field mobility. We also compare
the hydrodynamic model to recently introduced energy transport models. Finally, in low temperature regimes, we
study the dependence of shock formation on the momentum relaxation time representations and on the heat
conduction term. The algorithms employed for both models are the essentially nonoscillatory (ENO) shock
capturing algorithms.
The STC104 Packet Routing Chip
Authors: Thompson Peter W. , Lewis Julian D.
Published: September 2007

High‐performance parallel systems demand a high‐performance interconnect so that their component parts can
exchange data and synchronise efficiently. The interconnect must be cheap, and must also scale well in both
performance and cost relative to the system size. In this paper we describe the rationale, architecture and operation
of the STC104, the first commercially available, general‐purpose interconnect chip. The serial protocols used by
the device are described, followed by an overview of the microarchitecture, The operation of the fundamental block
is outlined, including the response to error conditions. Chip‐wide design issues and design methodology are discussed,
and finally various aspects of performance are calculated.
Closed Form Aliasing Probability For Q‐ary Symmetric Errors
Authors: Edirisooriya Geetani
Published: September 2007

In Built‐In Self‐Test (BIST) techniques, test data reduction can be achieved using Linear Feedback Shift Registers (LFSRs). A faulty circuit may escape detection due to loss of information inherent to data compaction schemes. This is referred to as aliasing. The probability of aliasing in Multiple‐Input Shift‐Registers (MISRs) has been studied under various bit error models. By modeling the signature analyzer as a Markov process we show that the closed form expression derived for aliasing probability previously, for MISRs with primitive polynomials under q‐ary symmetric error model holds for all MISRs irrespective of their feedback polynomials and for group cellular automata signature analyzers as well. If the erroneous behaviour of a circuit can be modelled with q‐ary symmetric errors, then the test circuit complexity and propagation delay associated with the signature analyzer can be minimized by using a set of m single bit LFSRs without increasing the probability of aliasing.
Switch‐level Differential Fault Simulation of MOS VLSI Circuits
Authors: Vandris Evstratios , Sobelman Gerald
Published: September 2007

A new switch‐level fault simulation method for MOS circuits is presented that combines compiled switch‐level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck‐at‐0, stuck‐at‐1 faults and transistor stuck‐on, stuck‐open faults. Prior to simulation, the switch‐level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X‐state due to fighting pull‐up and pull‐down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate‐level circuits is adapted for use at the switch‐level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch‐level than at the gate‐level due to the dynamic memory properties of MOS circuits.
An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment
Authors: Yan Jin-Tai , Hsiao Pei-Yung
Published: September 2007

For a building block placement, the routing space can be further partitioned into channels and switchboxes. In general, the definition of switchboxes releases the cyclic channel precedence constraints and further yields a safe routing ordering process. However, switchbox routing is more difficult than channel routing. In this paper, an O(NlogN) region definition and ordering assignment (RDAOA) algorithm is proposed to minimize the number of switchboxes for the routing phase, where N is the number of vertices in a channel precedence graph. Several examples have been tested on the proposed algorithm, and the experimental results are listed and compared.
A Sea‐of‐Gates Style FPGA Placement Algorithm
Authors: Roy Kalapi , Guan Bingzhong (David) , Sechen Carl
Published: September 2007

Field Programmable Gate Arrays (FPGAs) have a pre‐defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool) developed specifically for this architecture.
Taking Thermal Considerations Into Account DuringHigh‐Level Synthesis
Authors: Weng Jen-Pin , Parker Alice C.
Published: September 2007

Submicron feature sizes result in designs in which power density is significantly increased.
High‐level synthesis strategies are proposed in this paper to relieve potential thermal problems.
Operators are placed as close as possible to their data predecessors in order to minimize
the interconnection cost while not violating the thermal constraints. Spreading overused
functional units away from the thermal problem area often results in performance degradation.
Introducing redundant operators is suggested to reduce the module utilization and hence
thermal problems among problem modules when system performance is important. Our
experimental results show that this technique produces quite satisfactory results for a powerdominated
example.
IDDQ Testing Experiments for Various CMOS LogicDesign Structures
Authors: Toukmaji A. , Helms R. , Makki R. , Mikhail W. , Toole R.
Published: September 2007

In this paper, we present two studies. The first study constitutes an assessment of the effectiveness
of IDDQ (quiescent power supply current) in detecting transistor‐level defects for
three CMOS logic design styles. This study was carded out by designing, simulating, fabricating,
and testing CMOS devices with built‐in defects. The second study involves an
assessment of IDDQ in a production‐type environment and the effect of bum‐in on IDDQ
levels. This study was carried out in a production facility. The results show that IDDQ testing
can detect some types of defects in precharge and pseudo‐NMOS circuits but may require
partitioning circuitry for the latter.
Operational and Test Performance in the Presence ofBuilt‐in Current Sensors
Authors: Menon Sankaran M. , Malaiya Yashwant K. , Jayasumana Anura P. , Tong Carol Q.
Published: September 2007

The effects of Built‐In Current Sensors (BICS) on IDDQ
measurements as well as on the
performance of the circuit under test are considered. Most of the Built‐In Current Sensor
designs transform the ground terminal of the circuit under test into a virtual ground. This
causes increases in both propagation delay and IDDQ
sampling time with the increase in the
number of gates, affecting both test as well as operational performance. The effects that
current sensors have on the operational and test performance of a circuit are considered.
Circuit partitioning may be used for overcoming the effects of BICS on IDDQ
measurements
as well as on the performance of the circuit under test.
Statistical Module Level Area and Delay Estimation
Authors: Tyagi Akhilesh
Published: September 2007

The increasing complexity of VLSI design process has led to an increasing use of layout
synthesis systems. For many components of a high‐level synthesis system such as module
generators and module generator development environments, an accurate model of area and
delay for the layouts generated by a layout synthesis system is extremely desirable. We have
experimented with a statistical model for area and delay of function modules. This model is
surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of
adder and shifter modules can be modeled to with in 5% accuracy while the error in delay
model is bounded by 4%. This model can be taken through another level of indirection
without significant loss in accuracy. The area of all the modules that fit a ripple‐template
(such as carry‐ripple adder) can be modeled with in 30% accuracy. The delay of these
modules has a better fit, 15%. The square‐template designs (such as array multiplier) have an
area model with 1.7% coeificient of variance. In these cases, the model is parametrized by
the area and delay of the leaf cells in the template.
Possible Wireless Single‐Electron Logic Biased by Electric Field
Authors: Korotkov Alexander N.
Published: September 2007

A new type of ultradense logic based on single‐electron tunneling is considered. The basic
element is a short chain of conducting islands which shows bistable polarization and affects
the polarization of neighboring chains. The power is supplied by alternating electric field.
Modeling Light‐Extraction Characteristics of Packaged Light‐Emitting Diodes
Authors: Ting D. Z.-Y. , Mcgill T. C.
Published: September 2007

We employ a Monte Carlo ray‐tracing technique to model light‐extraction characteristics of
light‐emitting diodes. By relaxing restrictive assumptions on photon traversal history, our
method improves upon available analytical models for estimating light‐extraction efficiencies
from bare LED chips, and enhances modeling capabilities by realistically treating the various
processes which photons can encounter in a packaged LED. Our method is not only capable
of calculating extraction efficiencies, but can also provide extensive statistical information on
photon extraction processes, and predict LED spatial emission characteristics.
Self‐Consistent Solution of the Multi Band Boltzmann,Poisson and Hole‐Continuity Equations
Authors: Singh Surinder P. , Goldsman Neil , Mayergoyz Isaak D.
Published: September 2007

The Boltzmann transport equation (BTE) for multiple bands is solved by the spherical harmonic
approach. The distribution function is obtained for energies greater than 3 eV. The BTE
is solved self consistently with the Poisson equation for a one dimensional npn bipolar junction
transistor (BJT). The novel features are: the use of boundary fitted curvilinear grid, and
Scharfetter Gummel type discretization of the BTE.
Analysis and Simulation of Extended HydrodynamicModels: The Multi‐Valley Gunn Oscillatorand MESFET Symmetries
Authors: Chen Gui-Qiang , Jerome Joseph W. , Shu Chi-Wang
Published: September 2007

We introduce a novel two carrier hydrodynamic model, which incorporates higher dimensional
geometric effects into a one dimensional model. We study (1) the GaAs device in the
notched oscillator circuit, and, (2) a MESFET channel, and its symmetries. We present new
mathematical results for a reduced model.
Monte Carlo Simulation of a Submicron MOSFETIncluding Inversion Layer Quantization
Authors: Roldan J. B. , Gamiz F. , Lopez-Villanueva J. A. , Carceller J. E.
Published: September 2007

A Monte Carlo simulator of the electron dynamics in the channel, coupled with a solution of
the two‐dimensional Poisson equation including inversion‐layer quantization and drift‐diffusion
equations has been developed. This simulator has been applied to the study of electron
transport in normal operation conditions for different submicron channel length devices.
Some interesting non‐local effects such as electron velocity overshoot can be observed.
SCOAP‐based Testability Analysis from Hierarchical Netlists
Authors: Ravikumar C. P. , Joshi H.
Published: September 2007

Circuits of VLSI complexity are designed using modules such as adders, multipliers,
register files, memories, multiplexers, and busses. During the high‐level design of such a
circuit, it is important to be able to consider several alternative designs and compare
them on counts of area, performance, and testability. While tools exist for area and
delay estimation of module‐level circuits, most of the testability analysis tools work on
gate‐level descriptions of the circuit. Thus an expensive operation of flattening the
circuit becomes necessary to carry out testability analysis. In this paper, we describe a
time and space‐efficient technique for evaluating the well known SCOAP testability
measure of a circuit from its hierarchical description with two or more levels of
hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional
modules, which can be precomputed and stored as part of the module data base. Our
hierarchical testability analysis program, HISCOAP, reads the SCOAP expression
diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a
systematic manner. The program has been implemented on a Sun/SPARC workstation,
and we present results on several benchmark circuits, both combinational and
sequential. We show that our algorithm also has a straightforward parallel realization.
Quantum Kinetic Transport under High Electric Fields
Authors: Sano Nobuyuki , Yoshii Akira
Published: September 2007

Quantum kinetic transport under high electric fields is investigated with emphasis on the
intracollisional field effect (ICFE) in low‐dimensional structures. It is shown that the ICFE in
GaAs one‐dimensional quantum wires is already significant under moderate electric field
strengths (≥ a few hundreds V/cm). This is a marked contrast to the cases in bulk, where the
ICFE is expected to be significant under extremely strong electric fields (≥ MV/cm). Employing
the Monte Carlo method including the ICFE, the electron drift velocity in quantum wires
is shown to be much smaller than that expected from earlier investigations.
Studies of Chaotic Transport of Electrons in Quantum Boxes
Authors: Ferry D. K. , Edwards G.
Published: September 2007

Recent studies of transport through ballistic quantum dot resonators have revealed a complex
array of behavior, including the existence of "universal" conductance fluctuations which are
presumed to arise from the chaotic behavior of the underlying classical dynamics. In this
paper, the results of studies on the classical ballistic transport of carriers, within a quasi‐two‐dimensional
electron gas, through a 1.0 micron square structure in a magnetic field are presented.
A Monte Carlo study ,of Electron Transport in StrainedSi/SiGe Heterostructures
Authors: Rashed Mahbub , Shih W.-K. , Jallepalli S. , Zaman R. , Kwan T. J. T. , Maziar C. M.
Published: September 2007

Electron transport in pseudomorphically‐grown silicon on relaxed (001) Si1-xGex is investigated
using a Monte Carlo (MC) simulation tool. The study includes both electron transport
in bulk materials and in nMOS structures. The bulk MC simulator is based on a multiband
analytical model, “fitted bands”, representing the features of a realistic energy bandstructure.
The investigation includes the study of low‐ and high‐field electron transport characteristics
at 77 K and 300 K. Single particle MC simulations are performed for a strained silicon nMOS
structure at room temperature. Both calculations show saturation of mobility enhancement in
strained silicon beyond germanium mole fraction of 0.2.
Timing‐Driven Circuit Implementation
Authors: Karayiannis Dimitrios , Tragoudas Spyros
Published: September 2007

We consider the problem of selecting the proper implementation of each circuit module
from a cell library to minimize the propagation delay along every path from any primary input to any primary output subject to an upper bound on the total area of the circuit.
Different module implementations may have different areas and delays on the paths. Wc
show that the latter problem is NP‐hard even for directed acyclic graphs with two
implementations per module and no restrictions on the overall area of the circuit. Wc
present a novel retiming based heuristic for determining the minimum clock period on
sequential circuits. Although our heuristics may handle a bound on the total area of the
circuit, emphasis is given on the timing issue.
Complexity of Scheduling in High Level Synthesis
Authors: Mandal C. A. , Chakrabarti P. P. , Ghose S.
Published: September 2007

This work examines the complexity of scheduling for high level synthesis. It has been
shown that the problem of finding the minimum time schedule for a set of chains of
operations of two types using two processors, one of each type, is NP‐complete.
However, for two chains only, a polynomial time algorithm can been obtained for
scheduling with two processors. The problem of scheduling a rooted binary tree of two
operation types on two processors, one of each type, has been shown to be NP‐complete.
It has also been proved that absolute approximations for schedule length
minimization or processor minimization are NP‐complete. A related resource
constrained scheduling problem has also been shown to be NP‐hard.
The Coupled Optoelectronic Problems of Quantum WellLaser Operation
Authors: Grupen Matt , Hess Karl
Published: September 2007

The treatment of several aspects of quantum well laser simulation are discussed in terms of
the Minilase‐II simulator. The discussion involves the optical problem and several components
of the electronic problem, including bulk transport, carrier scattering into and within the
quantum well, and the nonequilibrium LO phonon temperature within the well. Descriptions
of these problems are followed by simulation results which show the ways in which they each
affect the laser characteristics.
Surface Evolution During Semiconductor Processing
Authors: Rajagopalan Ganesh , Mahadev Vadali , Cale Timothy S.
Published: September 2007

We discuss our approach to using the Riemann problem to compute surface profile evolution
during the simulation of deposition, etch and reflow processes. Each pair of segments which
represents the surface is processed sequentially. For cases in which both segments are the
same material, the Riemann problem is solved. For cases in which the two segments are different
materials, two Riemann problems are solved. The material boundary is treated as the
right segment for the left material and as the left segment for the right material. The critical
equations for the analyses are the characteristics of the Riemann problem and the ‘jump conditions’
which represent continuity of the surface. Examples are presented to demonstrate
selected situations. One limitation of the approach is that the velocity of the surface is not
known as a function of the surface angle. Rather, it is known for the angles of the left and
right segments. The rate as a function of angle must be assumed for the explicit integration
procedure used. Numerical implementation is briefly discussed.
CLOTH MEASURE: A Software Tool for Estimating the Memory Requirements of Corner Stitching Data Structures
Authors: Mehta Dinesh P.
Published: September 2007

In a previous paper [1], we derived formulae for estimating the storage requirements of
the Rectangular and L‐shaped Corner Stitching data structures [2, 3] for a given layout.
These formulae require the computation of quantities called violations, which are
geometric properties of the layout. In this paper, we present optimal Θ(n log n)
algorithms for computing violations, where n is the number of rectangles in the layout.
These algorithms are incorporated into a software tool called CLOTH MEASURE.
Experiments conducted with CLOTH MEASURE show that it is a viable tool for
estimating the memory requirements of a layout without having to implement the
corner stitching data structures, which is a tedious and time‐consuming task.
Embedded Parity and Two‐Rail TSC Checkers withError‐Memorizing Capability
Authors: Tarnick Steffen
Published: September 2007

In self‐checking systems, checkers usually do not receive all code words during normal
operation. Missing code words may prevent a checker from achieving the totally self‐checking
property. The paper presents a novel approach to the design of embedded
parity and two‐rail checkers that allows a checker to receive all code words irrespective of
the set of code words that is provided by the functional circuit. A checker gets all code
words by an LFSR while at the same time it monitors the output of the functional circuit.
Additionally, the LFSR is able to capture the error patterns of noncode words. Captured
error patterns will be modified since they will cycle through the LFSR. Thus, noncode
words that are not detected due to undetected checker faults can be detected in later
instances of time. The proposed method can be extended to the design of checkers for
linear codes.
Transient Analysis of Silicon Devices Using the Hydrodynamic Model
Authors: Colalongo Luigi , Valdinoci Marina , Gnudi Antonio , Rudan Massimo
Published: September 2007

The analysis of the switching behaviour of submicron devices brings about the necessity of
extending the solution of the hydrodynamic model to the transient case. The implementation
of such model has been carried out and a few examples of simulation are presented here,
showing the velocity‐overshoot of a ballistic diode and the temperature spread in the drain
region of a realistic MOS device.
A Generalized Tunneling Formula for Quantum Device Modeling
Authors: Lake R. , Klimeck G. , Bowen R. C. , Jovanovic D. , Sotirelis P. , Frensley W. R.
Published: September 2007

The generalized tunneling formula with the simple model for the broadening in the contacts
gives surprisingly good results for the majority of RTD structures. It is just as fast as the
standard coherent tunneling simulators and much more versatile. It is easily generalized to
multi‐band and multidimensional models. The multi‐band generalization of the theory and the
effect of the optical potential are described.
High Performance, Point‐to‐Point, Transmission Line Signaling
Authors: Dehon André , Knight Thomas F.
Published: September 2007

Inter‐chip signaling latency and bandwidth can be key factors limiting the performance of large VLSI systems. We present a high performance, transmission line signaling scheme for point‐to‐point communications between VLSI components. In particular, we detail circuitry which allows a pad driver to sense the voltage level on the attached pad during signaling and adjust the drive impedance to match the external transmission line impedance. This allows clean, reflection‐free signaling despite the wide range of variations common in IC device processing and interconnect fabrication. Further, we show how similar techniques can be used to adjust the arrival time of signals to allow high signaling bandwidth despite variations in interconnect delays.

This scheme employed for high performance signaling is a specific embodiment of a more general technique. Conventional electronic systems must accommodate a range of system characteristics (e.g. delay, voltage, impedance). As a result, circuit designers traditionally build large operating margins into their circuits to guarantee proper operation across all possible ranges of these characteristics. These margins are generally
added at the expense of performance. The alternative scheme exemplified here is to sample these system characteristics in the device′s final operating environment and use this feedback to tune system operation around the observed characteristics. This tuning operation reduces the range of characteristics the system must accommodate, allowing increased performance. We briefly contrast this sampled, system‐level feedback with the
more conventional, fine‐grained feedback employed on ICs (e.g. PLLs).
Three‐Dimensional S‐Matrix Simulation ofSingle‐Electron Resonant Tunnelling Through RandomIonised Donor States
Authors: Mizuta Hiroshi
Published: September 2007

This paper presents a numerical study of single‐electron resonant tunnelling (RT) assisted by
a few ionised donors in a laterally‐confined resonant tunnelling diode (LCRTD). The 3D
multi‐mode S‐matrix simulation is performed newly introducing the scattering potential of
discrete impurities. With a few ionised donors being placed, the calculated energy‐dependence
of the total transmission rate shows new resonances which are donor‐configuration
dependent. Visualised electron probability density reveals that these resonances originate in
RT via single‐donor‐induced localised states. The I‐V characteristics show current steps of
order 0.1 nA per donor before the main current peak, which is quantitatively in good agreement
with the experimental results.
Simulation of Quantum‐Dot Structures in Si/SiO2
Authors: Chen Minhan , Porod Wolfgang
Published: September 2007

We present numerical simulations for the design of gated few‐electron quantum dot structures
in the Si/SiO2 material system. Because of the vicinity of the quantum dots to the exposed
surface, we take special care in treating the boundary conditions at the oxide/vacuum interfaces.
In our simulations, the confining potential is obtained from the Poisson equation with a
Thomas‐Fermi charge model. We find that the dot occupancy can be effectively controlled in
the few‐electron regime.
A Stochastic D/A Converter Based on a Cellular Automaton Architecture
Authors: Andreadis I. , Kokolakis I. , Gasteratos A. , Tsalides Ph.
Published: September 2007

The design and VLSI implementation of a new stochastic D/A converter using the
properties of Cellular Automata (CA) is presented in this paper. The converter is
implemented using a Double Layer Metal (DLM), 0.7 μm, N‐well, CMOS technology
process provided by the European Silicon Structures (ES2). Its maximum conversion
rate is 6 kHz and it is intended to be used in low‐cost applications. Additionally, the
proposed approach integrates into digital techniques more easily than other popular
building D/A techniques.
Influence of BJT Transit Frequency Limit Relationto MOSFET Parameters on the Switching Speedof BiCMOS Digital Circuits
Authors: Srivastava A.
Published: September 2007

The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFET
parameters (L, Vth) to design BiCMOS digital circuits. The fTL relation is used in
conjunction with the established BiCMOS gate delay models. It is shown that the
minimum delay BiCMOS circuits driving the large capacitive load, can be designed at
the transit frequency limit with the reduced BJT AREA factor. The time delay
calculations are presented for a typical BiCMOS circuit and comparison is made with
the results simulated using SPICE.
Theory and Simulation of the Smooth QuantumHydrodynamic Model
Authors: Gardner Carl L.
Published: September 2007

The “smooth” quantum hydrodynamic (QHD) model is derived specifically to handle
in a mathematically rigorous way the discontinuities in the classical potential energy
which occur at heterojunction barriers in quantum semiconductor devices. Smooth QHD
model simulations of the resonant tunneling diode are presented which exhibit enhanced
negative differential resistance when compared with simulations using the original O(ħ2)
QHD model. In addition, smooth QHD simulations of a classical electron shock wave are
presented which agree with classical hydrodynamic model simulations and which do not
exhibit the spurious dispersive oscillations of the O(ħ2) QHD model.
Reconfigurable Shift Switching Parallel Comparators
Authors: Lin R. , Olariu S.
Published: September 2007

We present novel asynchronous VLSI comparator schemes which are based on recently
proposed, reconfigurable shift switch logic and the traditional (precharged) CMOS
domino logic. The schemes always produce a semaphore as a by‐product of the process
to indicate the end of domino process, which requires no additional delay and a minimal
number of additional devices. For a large percentage of inputs the computations are
much faster than traditional synchronous comparators due to the full utilization of the
inherent speed of the circuits. Also the schemes are simple, area compact and stable.
Iterative Partitioning with Varying Node Weights
Authors: Caldwell Andrew E. , Kahng Andrew B. , Markov Igor L.
Published: September 2007

The balanced partitioning problem divides the nodes of a [hyper]graph into groups of
approximately equal weight (i.e., satisfying balance constraints) while minimizing the
number of [hyper]edges that are cut (i.e., adjacent to nodes in different groups). Classic
iterative algorithms use the pass paradigm [24] in performing single‐node moves [16, 13]
to improve the initial solution. To satisfy particular balance constraints, it is usual to
require that intermediate solutions satisfy the constraints. Hence, many possible moves
are rejected.

Hypergraph partitioning heuristics have been traditionally proposed for and
evaluated on hypergraphs with unit node weights only. Nevertheless, many real‐world
applications entail varying node weights, e.g., VLSI circuit partitioning where node
weight typically represents cell area. Even when multilevel partitioning [3] is performed
on unit‐node‐weight hypergraphs, intermediate clustered hypergraphs have varying
node weights. Nothing prevents the use of conventional move‐based heuristics when
node weights vary, but their performance deteriorates, as shown by our analysis of
partitioning results in [1].

We describe two effects that cause this deterioration and propose simple
modifications of well‐known algorithms to address them. Our baseline implementations
achieve dramatic improvements over previously reported results (by factors of up to 25);
explicitly addressing the described harmful effects provides further improvement.
Overall results are superior to those of the PROP‐REXest algorithm reported in [14],
which addresses similar problems.
Design of MOS‐translinear Multiplier/Dividers in Analog VLSI
Authors: Lopez-Martin Antonio J. , Carlosena Alfonso
Published: September 2007

A general framework for designing current‐mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric‐mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from
a generic second‐order MOS translinear loop. Various implementations are proposed,
featuring simplicity, favorable precision and wide dynamic range. They can be successfully
employed in a wide range of analog VLSI processing tasks. Experimental
results of two versions, based on stacked and folded MOS‐translinear loops and fabricated
in a 2.4‐μm CMOS process, are provided in order to verify the correctness of
the proposed approach.
Reconfigurable Architectures for System LevelApplications of Adaptive Computing
Authors: Schott Brian , Crago Stephen P. , Parker Robert H. , Chen Chen H. , Carter Lauretta C. , Czarnaski Joseph P. , French Matthew , Hom Ivan , Tho Tam , Valenti Terri
Published: September 2007

The System Level Applications of Adaptive Computing (SLAAC) project is defining an
open, distributed, scalable, adaptive computing systems architecture based on a highspeed
network cluster of heterogeneous, FPGA‐accelerated nodes. Two reference implementations
of this architecture are being created. The Research Reference Platform
(RRP) is a MyrinetTM cluster of PCs with PCI‐based FPGA accelerators (SLAAC‐1).
The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPCTM nodes
with VME‐based FPGA accelerators (SLAAC‐2) and a commercial 6U‐VME quad‐
PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed for
successful ACS technology insertions is source‐code compatibility between the RRP and
DRP platforms. This paper focuses on the development of the SLAAC‐1 and SLAAC‐2
accelerators and how the network‐centric SLAAC system‐level architecture has shaped
their designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic Target
Recognition (SAR/ATR) algorithm to SLAAC‐2 is also discussed.