bluuebunny/crossref_metadata_2025 huggingface dataset:
Damage Induced in Interconnect Structures Mimicking Stresses During Flip Chip Packaging
Authors: Ocana Ibon
Published: October 2015

Flip-chip packages are produced by an interconnection technique in which the active area of a chip is mounted by various interconnecting materials on a multilayer substrate. While flip-chip technologies have progressed rapidly and are now widely used, they present special reliability concerns. A large thermal expansion mismatch between the chip and the substrate increases the likelihood of fatigue failure in solder joints under cyclic thermal loading. In addition, the thermal mismatch often results in the delamination of interfaces between two materials, which eventually leads to mechanical and/or electrical failure. In this paper the use of piezo actuators to mimic stresses during packaging assembly and in operation is discussed. The test has been modeled using finite elements and the results show that the level of stresses reached during packaging can be attained. Electronic speckle-pattern interferometry (ESPI) was applied for noncontact, real-time evaluation of the deformation. Failure analysis has been performed using an FIB dual beam. Cracks extending from the bump edge through the structures under study have been observed.
Assembly Standardization for the Diverse Packaging Requirements of MEMS & Sensors
Authors: Shumway Russell
Published: October 2015

Abstract not provided. Outline of topics: MEMS Package Relative Growth; Commonalities between MEMS & IC Packaging; Differences between MEMS & IC Packaging; Explosive growth of MEMS Opportunities; MEMS Diversity of Assembly Materials; MEMS Packaging Complexity; Standardization in MEMS Fab, Assembly & Test; Amkor MEMS & Sensor Packaging Evolution; MEMS Package Selection
Fatigue testing of bulk materials using a microsystems based approach
Authors: Liew Li-Anne , Read David T. , Barbosa Nicholas
Published: October 2015

Fatigue, the degradation of a material's mechanical properties due to cyclic loading, is a critical issue limiting the reliability of structural materials[1]. Fatigue testing of materials is typically carried out in controlled laboratory conditions on specially prepared specimens, and the results are extrapolated to real world conditions. In the past two decades, conventional fatigue testing machines and specimens have undergone miniaturization for the purpose of evaluating the fatigue properties of miniaturized mechanical components such as sensors and biomedical implants, with the smallest test specimens having dimensions on the order of 1 mm length [2] or consisting of foils and wires [3]. Challenges with miniaturization include difficulty in specimen handling, gripping, and alignment. At the same time, MEMS technology has been used to fabricate the actuators and sensors for fatigue testing of thin films [4]. In this approach, the specimen is typically part of the MEMS actuator and is fabricated in-situ. While this eliminates the problems with specimen gripping and alignment, it limits the specimen materials to those from which MEMS actuators and sensors can be readily fabricated, is destructive to the MEMs device, and furthermore is typically limited to thin films. We seek to use the advantages of MEMS to study the fatigue properties of bulk materials rather than thin films, but at the micrometer scale. This allows for greater accuracy and spatial resolution, compared to the state of the art, of property measurements of structural materials such as aluminum and stainless steel alloys as well as other materials used in civil infrastructure, aerospace, transportation and energy industries. Our approach is to use MEMS as chip-scale re-useable test instruments into which small specimens cut from bulk materials can be inserted and tested [5]. We describe the design of the MEMS test instrument and the metal foil specimen, whose gage section was 135 um wide and 25 um thick. The test instrument was fabricated from silicon and glass wafers, and the specimens were etched from commercially available Al 1145 H19 foil. Our S-N curve agrees within expectation with published values for similar aluminum alloys tested using conventional methods at much larger specimen size scales, and the fracture surface shows distinct regions corresponding to slow and fast crack growth. We envision this test technique as a tool to further the study of the fatigue properties of structural materials.
Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield
Authors: Uhrmann Thomas , Burggraf Jürgen , Wiesbauer Harald , Bravin Julian , Matthias Thorsten , Wimplinger Markus , Lindner Paul , Meynen Herman , Civale Yann , John Ranjith , Wang Sheng , Fu Peng-Fei , Yeakle Craig , Aw Gary
Published: October 2015

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed.

The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO.

In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.
Applying system modeling to define 2.5 - d and 3 - d packaging roadmaps
Authors: Gupta Dev
Published: October 2015

Though work on 3-d and later 2.5-d packaging has been going on now for over 5 years, we do not yet see large applications in areas other than traditional heterogeneous integration e,g. in camera modules. Adoption of 2.5-d Si interposer technology in 2010-11 to build FPGA modules on a commercial scale had generated much enthusiasm and expectation that floodgates will open for wide use of this technology e,g. in every Smart Phone but that has not yet materialized, giving rise to a shift in attention in Blogs and Conferences from purely digital applications e,g. processor - memory modules to more performance driven and cost insensitive applications e,g. heterogeneous modules for electro - optic I/O in servers etc.

Roadmaps for emerging technologies like 3-d stacking or 2.5-d modules are developed taking process maturity into consideration but they must also anticipate major applications. Such applications using a new technology can succeed only if there are overwhelming advantages in performance and system cost that negate increases in module costs. When the author and his team developed electroplated solder bump flip chip technology and their high volume implementation at two of the leading IDMs over 2 decades ago, both performance ( electrical ) and cost modeling were used to short list applications most likely to succeed and limit process development only for those applications. Countless users & providers of flip chip technology since then have benefited from this original work on electroplated solder and pillar bumps as well as build up type organic substrate technologies.

A similar theoretical approach is sorely needed in the development of 2.5-d and 3-d technologies to define the most cost - effective configurations and focus development work on only those. In this work we will discuss the Bandwidth and Power consumption ( two of the key drivers for die stacking ) of various 2.5-d and 3-d package configurations and based on simulation results compare them.

Key takeaways : 3-d stacking of dice using TSVs may not necessarily produce improved performance compared to less complicated packaging. Expensive interposers with high interconnect density may not even be necessary for most volume applications. Most likely configurations for processor - memory 3-d modules to get good enough bandwidth at lowest cost.
Path Finding for Multiple Platforms
Authors: Park John
Published: October 2015

With the increasing complexity of today's SOCs and the growth in multi-die packaging, companies are recognizing the value of cross-domain collaboration between the IC, package substrate and PCB design groups. High pin count devices coupled with cost sensitivity drive engineers to reconsider how they plan, optimize and automate the I/O placement on their chips, while targeting multiple packaging variables, which have direct impact on how the PCB will be designed. In some instances, informal design flows based on multiple EDA design tools have been pieced together. This is a step in the right direction; however, without a central repository for the data or accurate device modeling and rule-based optimization, design intent is often misinterpreted or lost and redundancy is often introduced into the flow.

This presentation outlines a co-design methodology that allows design teams the ability to easily plan and optimize I/O and connectivity from a chip(s), through multiple packaging variables while targeting multiple different system platforms (PCBs).

Using this planning, optimization and design methodology, engineering teams for the IC, the Package and the PCB would drive rule-based I/O level optimization and perform ball-out studies from their respective domains, all while visualizing the impact across the complete system.

Key features and advantages of this methodology are:Multi-mode connectivity management for cross-domain pin/signal mapping/shortingUser definable rules for I/O and ball-out assignmentsRobust support for feasibility analysis and rapid prototypingFully automated library developmentDirect integration to multi-mode physical layout toolSeamless interface to 2D and 3D EM analysis enginesTight interface with CFD based thermal analysis solutionEDA vendor neutral flow

The result of implementing this methodology will be a chip(s) that is fully optimized for its package(s) and PCB(s). This solution drives down the cost of the package and PCB through layer reduction and tighter control of the design process without impacting the cost of the chip.
Thermal Aging of Optically Silicones
Authors: Velderrain Michelle , Poliskie Michelle
Published: October 2015

Silicone encapsulants are used for a variety of photonic and optoelectronic applications where they function as a photon guide to increase the device's functionality such as light output for an LED. The purposes range from light guides to increase signal strength, waveguides to increase viewing angles and to increasing the light output of an LED. Silicones are highly desired since they are transparent in the visible range as well as maintain their optical clarity and mechanical properties under harsh thermal conditions. Other polymeric materials, such as epoxies and urethanes, can degrade which negatively impacts the device's performance. The need to understand the thermo-optic stability of the encapsulant over time is very dependent on the conditions of the device itself. Variables that affect the material properties include but are not limited to; wavelength, temperature, exposure to air, and encapsulant thickness. Since it can be said that there are almost an infinite amount of possible combinations the material can be exposed to, the silicone supplier must use develop a method to uniformly expose the materials to heat and then measure response in order to give end users the most relative comparisons of how different materials perform. The work presented is the method developed for exposing materials to 150 ° C in air for 8,000 hrs and determine the change in transmission in the visible region of the UV-Vis spectrum. It was found that there are key variables that can affect the results and this will be discussed to help the end user interpret the data.
UV-C LEDs for Sterilization Applications
Authors: Grzyb Joe
Published: October 2015

HexaTech has developed a proprietary, patented process for manufacturing bulk aluminum nitride (AlN) crystals and semiconductor wafers. HexaTech is leveraging this unique capability to develop and commercialize high-performance, long-lifetime Ultra Violet Light Emitting Diodes (UV-C LEDs) for disinfection applications (particularly clean water) and high-voltage, high-efficiency power semiconductors for power conversion applications (particularly smart grid).

Deep-ultraviolet light with wavelength in the range of 250 to 280nm (UV-C) has been used to sterilize liquids, air and surfaces for over a century. UV-C light is absorbed by and damages the DNA of harmful bacteria, either outright killing the bacteria or preventing their ability to replicate. Traditionally, high voltage mercury tubes have been used to generate such UV light. While mercury tubes have enabled UV-C use bulk disinfection applications such as drinking water and waste water, they have proven impractical in point-of-use applications where small size, elimination of harmful mercury, and high reliability under intermittent use conditions are required. The solution is to generate UV-C light using LEDs.

In spite of numerous efforts, the power output and reliability of UV-C LEDs is still not sufficient for their adoption as practical and reliable UV-C light sources. Traditionally, AlGaN-based UV-C LEDs have been fabricated on sapphire substrates. Because of huge number of defects caused by the lattice mismatch between the AlGaN active layers and the sapphire substrate, these sapphire-based UV-C LEDs show performance and reliability of limited interest to sterilization system manufacturers.

HexaTech's AlN crystal growth and wafer processing technology results in single crystal wafers with extremely high quality. HexaTech and its development partners have fabricated UV-C LEDs that have shown performance dramatically superior to other devices in the market in terms of output power, power density and lifetime.

In this presentation, we will discuss the market requirements for UV-C LEDs, the challenges of UV-C device fabrication, package and test, and the solutions that are being pursued.
ARM Dual Core Product Demonstration with 2.5D Through-Silicon-Via (TSV)
Authors: Kelly Michael , Reed Rick
Published: October 2015

Through-silicon-via (TSV) package construction offers several silicon integration advantages that are being validated by leading technology providers. This paper will describe a System in Package (SiP) design utilizing two functional system-on-chip (SoC) ARM dual-core Cortex-A9 processors connected across a 2.5D silicon interposer. The test vehicle was designed to demonstrate high speed and high bandwidth communication between multiple chips. The two logic chips were designed by Open Silicon, Inc. and fabricated by GLOBALFOUNDRIES on their 28nm-SLP (Super Low Power) process technology. GLOBALFOUNDRIES also fabricated the 2.5D interposer using their 65nm manufacturing flow. Amkor Technology provided the final assembly utilizing advanced TSV packaging technologies such as copper pillar bumping and mass reflow bonding.

This is a pivotal demonstration of the heterogeneous die integration approach. A silicon process node or package interconnect density can either preserve or limit inter-chip communication when comparing SoC versus SiP approaches. Connecting two dual-core Cortex-A9 processors within a single package illustrated the expansion of function through multiple die. The test vehicle also implies that a large IC can be re-architected into smaller constituents to increase yield or design flexibility. By utilizing the best technology node for price and performance, 2.5D packaging can lower overall system cost of ownership or conversely, can expand overall performance through multiple high performance ICs.

Chip designers are facing increased complexity and higher costs in order to move to smaller IC geometries and the adoption of 2.5D TSV technology will increase the options of construction (one vs. multiple die/SoCs). Having the flexibility to design with one or multiple die while maintaining high performance levels can offset the real estate costs of advanced nodes, permit silicon die reuse, improve yield and decrease overall product risk. The designer must choose the most appropriate silicon and assembly processes that satisfy the needs of each of the major functions in the overall system.

Amkor's assembly process for this key product construction has been demonstrated on a range of products for the communications, graphics and the mobile markets. Process flexibility has been a key factor in addressing different markets and package complexity.
How to bring 3D IC to Maturity: Example of a pacemaker
Authors: DAL MOLIN Renzo
Published: October 2015

3D IC wafer level stacking raises the issue of yield and consequently cost.

If 4 levels of wafers are stacked and if the yield of each level is 95%, the global yield is expected to be 81%.

If 4 levels of wafers are stacked and if the yield of each level level is 90%, the global yield is expected to be 65%.

If 4 levels of wafers are stacked and if the yield of each level level is 85%, the global yield is expected to be 52%.

These numbers show that 3D IC stacking needs to increase the yield of each stacked level in order to get acceptable industrial yield.

One way to solve this issue is to use reconstructed wafers with known good dies.

We will give one example of a realized 4 level wafer stacking for an implantable pacemaker.

A second approach is to implement redundancies in each chip stacked in order to implement repair strategy. We will present this design strategy in some particular cases and mainly depending on the source of defects.

Another issue to solve when performing 3D IC stacking is the crosstalks specifically for analog circuits. We will present how we performed the capacitor extraction between interconnections in 3D for the pacemaker.

Finally we will compare the 2.5D with embedded PCB versus 3D IC on PCB stacking in terms of size and cost for a pacemaker.
Optimized TSV Module for High Performance 2.5D Device Packaging
Authors: Uzoh Cyprian , Wang Liang , Sun Zhuowen , Cao Andrew , Lee Bong-Sub , Gao Guilian , Shen Hong , Arkalgud Sitaram
Published: October 2015

3D-IC has been increasingly adopted by the industry owing to its promise of higher device speed and package bandwidth, improved power consumption, reduced form factor, and lower cost for important applications over a wide range of industrial segments including image sensors, logic-memory and logic-logic integration, MEMS, integrated optical interposers and LEDs.

This presentation is a systematic study of multiple experimental factors affecting the electrical performance, reliability and scalability of TSVs. Electrical modeling and simulation was used to determine the key factors influencing singal transmission and return losses in TSVs at high (>1 GHz) frequencies. A variety of process modules and steps for the fabrication of through silicon vias were then systematically optimized to ensure high performance. The modules evaluated include TSV etch, TSV fill, chemical mechanical polishing (CMP), pad finish, bonding schemes, wafer thinning, via reveal, passivation, wiring and bumping. One example is the improvement of TSV profile and sidewall roughness through the optimization of DRIE parameters and wet chemical methods to reduce silicon sidewall roughness from that of a typical Bosch etch to less than 10nm which is critical for adhesion of barrier/seed layer and the final reliability of 2.5D packaging. Scalability of void-free via fill process with respect to TSV diameter and depth was addressed by using highly conformal barrier layers. Adhesion of Cu to the barrier layer was also improved upon detailed analysis to prevent delamination and improve reliability. A bottom up plating chemistry with significantly low impurity content was utilized to mitigate voids, seams and excessive overburden in the TSV. Its impact on stress and delamination issues and subsequent reliability failures was studied in details. The annealing process following TSV formation is systematically studied with varying conditions and characterized with metrology and electrical tests to investigate its effect on microstructure and material properties. The process parameters were tuned for CMP of Cu, adhesion and barrier layer without causing corrosion or delamination between adjacent layers. Process requirements for these modules in TSV process are closely related. This presentation will review the process module development in the context of their effects on the integrated TSV parameters (performance, reliability and scalability). We will also provide an in-depth discussion on process module optimization, electrical and mechanical characterization and cost reduction methodologies.
Solderability Challenges in Emerging BGA Packages
Authors: Durham Maria , Liu Yan , Mackie Andy
Published: October 2015

The final step of reflowing solder spheres to solderable pads on the bottom of substrates in FCBGA, CSP, and WLCSP packages is often considered to be a trivial step. However, with the increasing complexity and number of assembly processes taken prior to this final soldering step, the formation of a reliable final joint is far from certain. In order to eliminate this problem, many OSATs and ODMs are adopting the non-value-added process of prefluxing, reflowing, cleaning, and drying substrates immediately prior to the final ball-attach process.

This paper details the sequence of processes seen in typical BGA assembly, and examines the effects of each set of prior processes on the solderability of the final pad. It also details investigations of the solderable surface and metallurgy of the substrate pad.

The introduction of a “one-step” pin-transfer ball-attach flux is shown to be a means of reducing both process cost and time, and also reducing the risk of significant warpage in the finished package.
Direct EP/EPAG - Ultrathin Surface Finish for Soldering and Wire Bonding
Authors: Oezkoek Mustafa , RamosArnd Gustavo , Wegricht KilianJens
Published: October 2015

New challenges in the industry, new technical requirements, as well as cost and environmental regulations, require a constant search for alternative manufacturing solutions for the electronic packaging industry. Finer lines and spaces, higher frequencies, improved solder joint reliability and new challenges in wire bonding – both with existing wire technology such as Al and Au or novel types such as Cu or Cu-Pd – are just a few examples of technological advancements for surface finishes in the packaging industry. Additionally, the reduction and elimination of toxic and hazardous materials, as well as the drive to further reduce the manufacturing costs, are important requirements which has to be addressed.

The new direct pure EP/EPAG surface finish is suggested as a solution to these challenges for the future. The direct EP/EPAG process allows the direct deposition of palladium on copper, without using any nickel. It is suitable for high frequency, for flexible applications, for gold, aluminum, gold, silver and copper wire bonding applications. The process proves superior solder joint strength for lead free and eutectic soldering and is compatible with many new base materials and soldermask types owing to its short deposit time and low temperature needs. Finally, the EP/EPAG process operates at a thickness of less than 300 nm, ideal for very fine lines and spaces. The EP/EPAG finish also features several environmental benefits, such as less water and energy consumption owing to reduced process steps and line lengths.

The suggested paper will provide new wire bond data with silver, gold and copper wire bonding results. A technical comparison to a thin ENEPIG finish will be provided to show the differences in terms of soldering and solder joint reliability.
High Throughput Thin Wafer Support Technology for 3DIC
Authors: Moore John , Pettit Jared , Young David , Law Alman
Published: October 2015

The 3DIC market has been investigated for several years. As many companies investigate this business, more is understood about the challenges and cost. All existing commercial technologies use a spin-on adhesive applied to the device wafer, is bonded to a carrier, and after processing, de-bonded by widely different practices. One of the leading technologies is WaferBond(TM), a rubber-based adhesive, supplied by Brewer-Science, Inc. (BSI). In 2005, this technology was developed by Daetec as one of their first technology transfers. Daetec has developed numerous temporary bonding systems, including a rosin and a silicone, sold under the trade name GenTak(TM) for General Chemical. [1] At this year's 2013 Semicon- West gathering, a panel of global experts from KMPG, IMEC, Sematech, CEA-Leti, and CNSE were asked to identify the semiconductor industry's greatest technical challenges. [2] Next to lithography, these experts believed the top challenge is to reduce the barriers to 3DIC. Such barriers include: high cost, poor yield, and poor throughput. When only a few companies can afford 3DIC, progress is slow and growth towards >2 integration levels is pushed to the future. Daetec has developed a new technology, DaeBond 3DTM, allowing carrier de-bond to occur in a batch process and while thinned wafers are affixed to film frames (Fig. 1). Many other benefits exist and will be presented at the show.
Next Generation Electrochemical Deposition TSV Fill
Authors: Kim Bioh , Golovato Stephen , Barbera Tyler , Fujita Keiichi , Tanaka Takashi
Published: October 2015

The first generation of through silicon via (TSV) designs for interposer and 3D die stacking has concentrated on TSV features with aspect ratio (AR) on the order of ten. Typical via sizes are 10 X 100 um for interposer and 5 X 50 um for 3D applications. Ionized physical vapor deposition (IPVD) has been successful in depositing barrier and seed layers in these AR=10 vias that allow efficient “bottom-up” filling by electrochemical deposition (ECD) using available chemistries. While these applications are currently moving to pilot lines and low scale production, research and development has already begun on the next generation of TSV structures for interposer and die stacking. These may be based on via middle or via last designs. They are expected to increase in aspect ratio for denser TSV arrays while maintaining similar wafer thickness. Structures with AR in the range of 15–20 are being designed and produced. For interposer, a typical structure might be 8 X 120 um and 2 X 40 um for 3D stacks. These structures will challenge all TSV formation processes, including etch, dielectric liner deposition, barrier-seed deposition and TSV fill.

This paper will focus on barrier-seed and TSV fill processes. IPVD barrier-seed deposition will be difficult for AR~15–20 and will require much longer deposition times for complete via coverage. Long IPVD times will produce thick overburden and pinch off the opening at the top of vias. Even if successful, IPVD may not be viable economically. More conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) and wet processes, like electro-less plating and conformal ECD, may be better alternatives to IPVD. A conformal process only needs to deposit the minimum required seed thickness in the via for successful ECD filling with the overburden being nearly the same thickness. The development of a successful conformal barrier-seed process may even challenge IPVD for AR=10. This paper presents ECD TSV fill results using several conformal barrier-seed processes, demonstrating the feasibility of this approach for structures with AR = 10–20.
Versatile Lead-Free Solder Electroplating Products for Advanced Bumping Technologies
Authors: Lee Inho , Cho Regina , Grippo Lou , Taylor Yen-Lin , Baldelli Wayne , Farrell Ryan , Woertink Julia , Qin Yi , Prange Jonathan , Lee Yil-Hak , Imanari Masaaki , Dong Jianwei , Calvert Jeff
Published: October 2015

Lead-free SnAg solder bumps deposited by electroplating are used extensively in high volume production lines for a number of new bumping technologies including C4 bumps, Cu pillars capped with SnAg solder and 3D microbumps. New bumping technologies present their challenging requirements such as tightly controlled thickness uniformity, alloy composition uniformity and avoidance of reflow voids to create high yields and low defects. To meet these requirements, SnAg plating chemistry must deliver strong performance over a wide range of applications.

Traditional device manufacturers, wafer foundry companies and Outsourced Assembly and Test (OSAT) companies are manufacturing a number of different types of bumped wafers in their production lines; a diverse range of die design and pattern densities, thin and thick resist film wafers, mushroom and in-via plating, and wide range of plating rate. The variety and complexity of bumping wafers have challenged SnAg plating chemistries to meet tight requirements in terms of running cost saving and high production yield. Hence, development of versatile and robust chemistries for electroplating is critical to overcome these challenges

In view of all these challenges and unmet needs in the market, Dow focused its efforts on developing a brand-new additive system for SnAg plating. On the one hand, we tapped into our know-how on solder plating to establish correlations between various types of end-user requirements and experiences to fundamental electrochemistry response. On the other hand, 300mm in-house plating and process tools are leveraged to speed up the feedback process and provide pilot run data. At the end, this highly iterative approach enabled us to optimize the performance of the chemistry without sacrifice on design space.

In this paper, we will discuss next generation of SnAg electroplating products capable of achieving versatile performance requirements over a wide range of applications. The bump height WID co-planarity% ((hmax-hmin)/2havg ×100) was achieved less than ±5% over the wide range of current density from 4 ASD to 12 ASD. Smooth surface morphology, narrow Ag alloy composition distribution less than ±0.2% across the 300mm wafers, and reflow void free were observed. An optimized formulation of the next generation SnAg products was successfully demonstrated plating capability on various bumping technologies such as C4 bumping, Cu pillars capped SnAg solders and micro bumps meeting plating requirements.
Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging
Authors: Tatsumi Koji , Mineo Kyouhei , Hatta Takeshi , Katase Takuma , Ishikawa Masayuki , Masuda Akihiro
Published: October 2015

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation.

We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary.

This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed.

With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming.

In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes.

We'd like to present our updates on controlling bump morphology for various applications.
Use of Darkfield Laser Technology in Monitoring Particles Generated by Process Tools in Cu Pillar Bumping & Wafer Edge Inspection
Authors: Asgari Reza
Published: October 2015

In recent years, the semiconductor industry has witnessed an increasingly fast adoption rate of Cu pillar bumps for a variety of devices including memory, logic, processors, and FPGA. Cu pillar bumps provide several advantages over their counterparts, among which are tighter pitch, large number of I/Os as well as better heat dissipation. Due to the constant drive for miniaturization, the size and pitch of these bumps are getting smaller and smaller. As the sizes shrink, the need to minimize size and number of particles generated by the process tools increases. Unwanted particles generated by tools such as sputtering or etch can create killer defects driving down yields.

The purpose of this paper is to examine how a darkfield laser technique can be used to monitor process tools for the amount of particles they generate. Determination of excessive particle density could trigger a chamber clean. After the chamber is cleaned, particle density needs to be re-characterized before releasing tool into production. Figure 1 shows the working principal of this sensor and figure two shows an example of maps generated by the inspection tool. Particle and haze data generated on a monitor wafer allows engineers to maintain process tools at optimal cleaning levels.
COMPARISON OF FOWLP VS QFN PACKAGE FROM THERMAL ASPECT
Authors: Wan Qun
Published: October 2015

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.
SiP Technology for Wireless Module Miniaturization
Authors: Kuo Benny
Published: October 2015

SiP (System in package) module provide a integrate functions, smaller and thinner package solution on electronic portable devices. For the wireless application, the advanced AoP (Antenna on package) and compartment shielding has been proposed and developed by Advanced Semiconductor Engineering (ASE), Inc. to be the next request for complex application and miniaturization solution. For AoP package, more focus on near field/wireless connection to have specific metal antenna design and attached on package surface to achieve SiP module miniaturization and perform required antenna efficiency on low frequency application. Advanced compartment shielding provide the simple method on function isolation area to prevent the electromagnetic noise interference (EMI) and high level of total radiated EMI from system product due to more complex package performance.

The major benefit of novel AoP package is transfer the antenna designed on PCB to directly attached on package to reduce the PCB X/Y dimension but still keep antenna efficiency performance. The fabrication of AoP consists of following factors: 1) special substrate design to have antenna connection pads; 2) specific 3D metal frame design for antenna; 3) antenna frame attachment and over mold for package. Following these processes, AoP provide a simple process on package assembly and smaller dimension of package.

For compartment shielding development in ASE, previously we design a metal can on module package to reduce EMI but induce a thickness increase. The novel compartment shielding more focus on shielding frame design inside the package to achieve simple process flow and good shielding performance, their fabrication consists the following factors: 1) specific tooth-type frame design to have shielding function for different zone in package and provide suitable slot width/pitch ratio for mold flow; 2) adhesion material for metal frame attached on substrate ; 3) over mold and laser trenching; 4) conductive material sputtering on package surface. This novel compartment shielding solution provides a simplified shielding and more reliable process on SiP module package.

Wireless module was designed RF/power/Switch/Bluetooth function inside the package, the high density of electrical function is usually designed in the portable devices with small/thinner size. Advanced AoP or compartment shielding technology provides more competitive solution on SiP module miniaturization. In the paper, we will present the design for AoP and compartment shielding, process characterization and measurement of antenna and shielding performance of module to present the advantage of SiP modules with this technology application.
Electroplating with Dielectric Bridges
Authors: Stout Gene , Scott Doug , Curtis Anthony , Burgess Guy , Tessier Theodore G.
Published: October 2015

The electroplating of underlying metal redistribution layers, under-bump metallization (UBM) layers, WLCSP, Cu pillar and other flip chip applications is well established in the semiconductor industry. The use of semi-additive plating can sometimes be adversely affected by the absence of plating occurring in all targeted locations or with plating non-uniformity as a result of front-end fab related structural anomalies.

Subsequent analysis has routinely determined that the previously deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant types of topographical issues causing discontinuity in the seed layer are related to adverse sidewall profiles of an underlying dielectric layer or an edge of die feature. Typically die streets are kept clear of certain dielectric layers to avoid complications from saw tool wear and residual defects. As such, these particular dielectric layers are usually terminated at or near each die edge on a semiconductor wafer during processing. Introducing dielectric bridges over the dicing streets provides additional assurances an alternative means to significantly improve the ability to uniformly plate on all targeted die by creating an electrically continuous seed layer pathway while still allowing for subsequent wafer dicing with minimal blade wear, die chipping or residual dielectric issues. FCI has developed and successfully uses this patent pending method to insure the uniform electroplating of metallization layers for a wide variety of applications.

This paper will highlight the advantages of this wafer level processing strategy in a high volume, high mix wafer bump fabrication facility including improvements in processing quality and consistency. The transparency on deploying this front-end process change on back-end assembly operations and device reliability will also be addressed.
Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding
Authors: Zoschke Kai , Lang Klaus-Dieter
Published: October 2015

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves.

Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general.

The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages.

However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways.

The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap.

The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail.

All processes were performed at 200mm wafer level.
Anaerobic adhesive jetting for micro-electronics packaging applications
Authors: Liang Hanzhuang , Suriawidjaja Floriana , Szuch Michael
Published: October 2015

Anaerobic fluid has been used as an industrial adhesive to seal or bond metal components for both large and small scales. Its use has recently extended to micro-electronics packaging. This novel application brings challenges to the dispensing process due to part handling at micro-scale dimensions and high production throughput. Most high-precision dispensers have fluid paths that are constructed of metal components to ensure product robustness and enable dimensional precision of micro-scale parts. This is incompatible with anaerobic adhesives which cure in the absence of oxygen and utilize metal ions as the catalyst. Furthermore curing accelerates with smaller gaps. A non-contact jetting solution has been developed and applied in production environment to dispense anaerobic adhesives with precise volume control, at high speed, and in continuous operation. Dispensing can be optimized to include a range of hardware dimensions, component surfaces, fluid handling, and process control.
A Kinetic Monte Carlo Approach to Study Transport in Amorphous Silicon
Authors: Muralidharan Pradyumna , Vasileska Dragica , Goodnick Stephen M.
Published: October 2015

The constant innovation of devices in the semiconductor industry to improve performance to meet very specific demands has led to the study and exploration of a host of new materials. The use of ternary and quaternary materials, organic materials, amorphous silicon are a few examples of promising alternatives to traditional crystalline silicon. However, the use of novel materials presents a unique challenge for a theoretical analysis using device simulation. Traditional device simulation methods are sometimes not enough to capture the nuances of transport. In this paper we study transport through amorphous silicon to evaluate it's role in a-Si/c-Si HIT Cell and it's potential for other device operations by the use of Kinetic Monte Carlo (KMC) method.

As an amorphous materials lack long range order, it is near impossible to create a bandstructure for it and conduct Ensemble Monte Carlo (EMC) simulations to study transport through the material. Also, the presence of many defects creates localized states below the conduction band which facilitates hopping transport. As hopping transport happens through a series of capture and emission processes, the time scales of these mechanisms render the use of a traditional EMC unfeasible. It is crucial to understand the nature of the defects/traps that are present in the amorphous material. Understanding defect assisted transport is the key to understanding how the amorphous silicon layer will affect overall device performance. Defect assisted transport (DAT) can be conducted in the amorphous material through various different mechanisms such as capture of carriers by a defect, tunneling emission, Pool-Frenkel emission, defect to defect transition etc.

Using the Kinetic Monte Carlo approach we will be able to simulate individual charge carriers that interact with point like defects over a period of time. However, the transient nature of the KMC is not limited to short time scales. Also, the suggested method can be used to study the effect of many transition mechanisms. This method facilitates the simulation of the many individual steps in a Markovian chain that mimics carriers moving through various defects. We study hopping transport through a triangular barrier with use of phonon assisted mechanisms to analyze current and carrier transit times. The distribution function is also analyzed before and after defect assisted transport. One of our primary objectives is to study the role played by the amorphous silicon layer in determining overall device performance of a-Si/c-Si HIT Cell.