Process and Design Challenges for Hybrid Bonding
Authors: Dubey Vikas , Wünsch Dirk , Gottfried Knut , Wiemer Maik , Fischer Tobias , Hanisch Anke , Schermer Sebastian , Helke Christian , Hasse Micha , Reuter Danny , Schulz Stefan E. , Ghosal Sanghamitra , Hofmann Lutz 
Published: February 2024

Hybrid bonding is one of the key technology to enable solutions for high bandwidth with increasing power and signal integrity. Hybrid bonding involves, face-to-face interconnect formation between wafers and it acts as an extension of fusion bonding technology. Wherein, dielectric materials such as silicon dioxide bond at room temperature and the copper vias embedded in the dielectric expand to form the electrical connections, enabling the interconnect formation between the top and bottom wafer.

Hybrid bonding provides advantages over traditional C4 flip-chip bonding involving solder-based micro-bumps, such as, interconnect pitch scaling to less than 10 µm thereby providing higher interconnect density and increased power and signal speed efficiency for memory and high-performance computing application along with better reliability. It is compatible with standard CMOS fabrication technology.

In this work, we would like to present the design and process challenges which may lead to improved bonding yield. To enable hybrid bonding with high yield it is necessary that the bonding surfaces are flat with low roughness. The optimized chemical mechanical polishing (CMP) process is one of the key process technology which enables surface topography to be less than 10 nm and surface roughness to be less than 0.8 nm. The surface topography is dependent on the metal via layout, interconnect density and the surrounding dielectrics and hence, these design parameters act as a guiding principle for the application-oriented definition of the design to accommodate different pitch sizes of interconnecting vias (from 1 µm to 10 µm). The mechanical properties of the materials play a key role as well as this will define the removal rate of dielectric and the metals during the CMP process which will affect the dishing and the surface topography. To achieve high bonding yield the surface topography is key as this will affect the bond front propagation and hence the bonded and non-bonded region between the dielectrics. To further improve the bonding yield we have applied a tailored annealing recipe which improves the bonding yield significantly. This paper would focus our work on topography improvement and overall bonding yield in detail and a comparison of bonding yield with and without dummy vias. Dummy vias in this context refer to the copper via structures that are not intended for interconnect formation but are there for CMP process optimization to achieve better process control. Hence, the dummy vias are not connected to the underlying routing metal layer.

Figure 1, shows an ideal surface that would result in W2W bonding with high yield. Figure 2 shows, the defects such as high copper dishing, copper protrusion, dielectric erosion and poor surface topography which will result in poor bonding yield. Figure 3 shows the bonding using SiON as the bonding dielectric with (a) without dummy copper vias (~98% bond yield) and (b) with dummy copper vias (~88% bond yield).

Figure 1