(Keynote) Group-IV Epitaxy and Process Solutions for Stacked Gate-All-Around Nanosheet Technology Performance Improvement
Authors: Mochizuki Shogo 
Published: December 2024

Stacked gate-all-around (GAA) nanosheet (NS) devices are attractive candidates to replace FinFETs at the 3nm technology node and beyond due to their excellent electrostatic properties and scalability. GAA NS technology has multiple advantages compared to FinFET technology. GAA NS device with stacked nanosheets offers increased drive current compared to FinFET technology due to significant improvement in the total effective width per active footprint GAA NS device also enables gate length scaling thanks to its outstanding electrostatics and short channel control. Unlike FinFET, the active footprint is not quantized on NS. Therefore, flexible power/performance tuning can be achieved with variable nanosheet width. The industry agrees that GAA NS structure is the architecture of choice for the next device structure after FinFET as scaling continues. In fact, mass manufacturing for stacked GAA Nanosheet technology started and is currently offered as first-generation product at the 3nm technology node.

Fabricating GAA NS structure can take advantage of many of the FinFET process integrations by adding elemental technology modules unique to the GAA NS structure. A specific SiGe/Si multi-layer epitaxy is employed for stacking Si NS channels. The SiGe layer is used as a sacrificial layer for forming inner spacer (IS) and defining the suspension thickness, the distance separating two consecutive stacked Si NS channels. The uniformity and crystallinity for the epitaxial SiGe/Si layers within wafer is critical since it will determine the Si NS channel thickness and performance. Abrupt Ge profile at the SiGe/Si interface is also required for achieving selective SiGe removal to form optimal IS profile and suppress Si NS channel surface roughness post channel release. IS is necessary to isolate the gate and S/D, playing an important role as a physical barrier to prevent S/D damage during channel release while providing device benefits. The IS profile and thickness are important for tuning device performance by modulation of capacitance and resistance. S/D epitaxial growth becomes more difficult as devices are scaled with a reduction of the opening of the S/D region For a GAA NS structure employing IS, all the focus will be on improving the integration and process to avoid negatively impacting the subsequent S/D epitaxial growth.

PFET device performance degradation is expected due to modulation of hole mobility. Transitioning the device structure from FinFET to GAA NS dramatically changes the transport properties as the channel surface orientation changes and is more dominated by the (110) surface compared to (001) plane for a FinFET. Therefore, exploring performance improvement techniques is required for next generation GAA CMOS technologies in order to improve the pFET device. Increasing channel carrier mobility is one way to improve device performance. Hole mobility can be increased by inducing compressive stress into the channel material. SiGe is one of the most promising materials for pFET channel as strained SiGe channel FinFET device shows intrinsic mobility gain compared to Si channel FinFET. Additional SiGe channel benefits include Vt tunability and superior NBTI performance. As such, applying SiGe channel into GAA NS device has great potential for further improving pFET device performance. SiGe cladded NS channel formation through selective SiGe epitaxial growth post Si channel release is an effective method for maintaining strain in the SiGe region. The lattice constant difference between the epitaxial SiGe layer and Si channel NS results in compressive strain in the SiGe cladded layer. This technique maintains the compressive strain since there is no patterning step in the downstream process. Altering the channel orientation is another technique for modulating carrier mobility independent of internal and external stressor elements. For instance, hole mobility is higher for (110) planes than for (001) planes. The same process integration can be utilized for both substrate types for fabricating GAA Si channel NS devices on (001) and (110) bulk substrates, although careful engineering is required for SiGe/Si epitaxy on (110) substrate.

In this talk, we will review the epitaxy processes and related technologies for GAA NS device fabrication. In addition, performance enhancement techniques such as, (1) strained SiGe channel and (2) channel surface orientation with high hole mobility, that can be applied for GAA NS pFET device are discussed.