Implementation Of Logic Fault Detection Techniques Using Fpga 1232 Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP) © Copyright: All rights reserved. Retrieval Number: F12110986S319/2019©BEIESP DOI:10.35940/ijeat.F1211.0986S319 Journal Website: www.ijeat.org Fig. 1. Block diagram of Simple Memory System III. LOGIC FAULT DETECTION TECHNIQUES A. Normal Majority Logic (ML) Decoder The fault present in the input can be corrected by ML decoder, a simple and efficient method. It works based on parity check equation, to correct multiple bit flip in the N code input bits stored in memory. ML decoder consists of four units namely, cyclic shift register, an XOR matrix, a majority gate and an XOR operation for correcting the codeword bit under decoding. The operation is explained below. Input N bits are initially stored in cyclic shift register and shifted to all the units. An N bit input will take N cycles to produce the output signal. If the input bit has flip in it, then after processing the decoder will calculate parity check equation which is connected to XOR matrix. In next step, it will compare to majority gates for checking the correctness. If the number of 1s produced is greater than number of 0s then current bit under decoding should be corrected. This procedure is repeated for each bit in N bit input. For correct bit, parity checksum should be zero. This method is useful only for simple bits, but will affect the system performance when applied for more number of bits. B. Normal ML Decoder with Syndrome Fault Detector To improve the performance of a normal ML Decoders, when operating with more number of bits, a new unit called Syndrome Fault Detector (SFD) is added. As most of the bits are error free in general, the performance will not be affected. Thus by adding this unit, average latency is reduced. Change in MLD and SFD will produce syndrome based parity check matrix. Faulty bit is detected by the syndrome equation. MLD will work normally until SFD activates the fault detection unit. As error free bit skips this step, error correction cycles are saved. The disadvantage in this method is the complexity in design. This
Authors:   Assistant Professor, Kumaraguru College of Technology, Coimbatore, Tamilnadu, India, Sundaram N. Mohana , Arunkumar S. ,   Assistant Professor, Kumaraguru College of Technology, Coimbatore, Tamilnadu, India, Mahalingam A. ,   Assistant Professor, Sri Shakthi Institute of Engineering and Technology, Coimbatore, Tamilnadu, India
Published: November 2019

The evolution of automation concept in industries and rising significance for digital mode of communication have in turn stresses the need for reliable, efficient and high performance digital system. One of the major problems faced in the digital transmission is the loss of data and hence an effective technique to detect and correct these faults is necessary. Conventionally, various techniques are used for this purpose. Among them, three of the techniques like Plain Majority Logic (ML) Decoder, Syndrome Fault Detector and Plain ML Detector Decoder (MLDD) are analyzed and compared in this paper. The purpose of this comparison is to identify the most suitable methodology based on its capability to track maximum number of faults in minimum number of cycles, with reduced memory read access time. All these logics are simulated using HDL code and analysis is done to implement it in FPGA. The results reveal that Plain MLDD is found to provide better solution for various digital circuits than other techniques.