bluuebunny/crossref_metadata_2025 huggingface dataset:
Low Voltage Driven CMOS Circuits Based on Silicon on Glass
Authors: Choi Min Hyuk , Choi Jae Won , Park Seung Hyun , Choi Won Jae , Mativenga Mallory , Jin Jang , Mruthyunjaya Ravi , J. Tredwell Timothy , Mozdy Eric , Kosik Williams Carlo
Published: October 2010

Low voltage driven inverter, ring oscillator and shift resistor using n- and p- channel TFTs based on Corning® silicon-on-glass substrates (SiOG) is studied. The field effect mobility of n- and p-channel TFTs based on SiOG are 226 cm2/V s and 165 cm2/V, respectively. TFTs exhibit the symmetric threshold voltage of ± 1.1 V and gate voltage swing of 0.21 ~ 0.23 V/dec. The total propagation delay time of the CMOS inverter is 2.54ns at the supply voltage of 7 V. In addition, the rise and fall times of the shift register are found to be 0.5 µs and 0.7 µs at VDD of 7 V, respectively. Therefore, high performance integrated circuits can be possible on SiOG using CMOS technologies.
The Application of Organic Electrochemical Transistors in Biosensors
Authors: Yan Feng , Lin Peng , Chan Helen
Published: October 2010

Ion-sensitive properties of organic electrochemical transistors (OECT) based on Poly(3,4-ethylenedioxythiophene): poly(styrene sulfonic acid) (PEDOT:PSS) are systematically studied for the first time. The transfer curve (IDS ~ VG) of an OECT shifts to lower gate voltage horizontally with the increase of the concentration of cations, including H+, K+, Na+, Ca2+, and Al3+, in the electrolyte. Nernstian relationships between the shift of the gate voltage and the concentrations of the cations have been obtained. Cell-based biosensors with cancer cells cultivated on top of the OECTs have been studied. The activities of the cells under the effect of trypsin have been monitored by characterizing the OECTs. It has been found that the performance of the device is sensitive to the surface charge and the morphology of the attached cells due to the electrostatic interaction between the adherent cells and the active layer of the OECT.
(Invited) Poly-Si TFT Based Technologies and Circuits for Multipurpose Sensors
Authors: Bonnaud Olivier , Mohammed-Brahim Tayeb
Published: October 2010

Many works were performed to develop CMOS like circuits with both types (NMOS and PMOS) thin film transistors (TFT), by improving the deposition techniques, the doping control and the crystallization of the deposited films to reach the highest performances and reliability. These results opened the spectrum of applications of large area electronics, on glass substrate. Among them, sensors are the most concerned. This paper presents several approaches involving TFT that lead to specific sensors. The first one concerned a dedicated TFT including two Hall contacts, a MAGFET. The second one consists to suppress the deposited gate oxide and to leave a free space that can store charges permanently or temporary. Thus, polysilicon TFTs with a suspended gate (SGTFT) were fabricated, the airgap under the gate bridge accepting charges in a very small volume. On the base of this generic structure, several sensors were developed more especially pH-meter, proteins and DNA sensors.
Crystalline Gadolinium Oxide: A Promising High-k Candidate for Future CMOS Generations
Authors: Endres Ralf , Gottlob Heiner , Schmidt Mathias , Schwendt Dominik , Osten H.-Jörg , Schwalke Udo
Published: October 2010

In this work, epitaxial grown gadolinium oxide (Gd2O3) has been investigated as promising high-k gate dielectric for future CMOS generations. Fully functional metal gate MOS capacitors and MOS field effect transistors (MOSFETs) on p- and n-type silicon substrates with titanium nitride (TiN) gate electrode have been fabricated in a gentle gate-last process and are electrically characterized in detail.
(Invited) Introducing Lanthanide Aluminates as Dielectrics for Nonvolatile Memory Applications: A Material Scientist's View
Authors: Adelmann Christoph , Swerts Johan , Richard Olivier , Conard Thierry , Popovici Mihaela , Afanas'ev Valeri V. , Breuil Laurent , Cacciato Antonio , Opsomer Karl , Brijs Bert , Tielens Hilde , Pourtois Geoffrey , Bender Hugo , Detavernier Christophe , Jurczak Malgorzata , Van Elshocht S. , Kittl Jorge A.
Published: October 2010

The lanthanide aluminates GdAlO3 and LuAlO3 have been examined for integration into advanced non-volatile memory devices. From a materials point of view, a number of physical properties of the material need to be understood prior to successful device integration, such as e.g. bandgap and band offsets, dielectric permittivity, or crystallization behavior. In addition to these material properties, the layers may have to withstand high thermal budgets during device processing such that thermal stability and interdiffusion in contact with surrounding materials become important.
(Invited) The Role of Oxygen in the Development of Hf-Base High-k/Metal Gate Stacks for CMOS Technologies
Authors: Cartier Eduard A.
Published: October 2010

The threshold voltage in HfO2/metal gated FETs is found to strongly dependent on the annealing conditions used for device fabrication. It is shown that this dependence arises in a large part from the formation of positively charged oxygen vacancy in the HfO2 layer during high temperature process steps. At low temperatures, oxygen stored in the metal gate or residual oxygen in the ambient of processing tools can diffuse back into the HfO2 layer, having a profound effect on the threshold voltage by modulating the concentration of charged defects. In absence of any oxygen sources, the threshold voltage is dictated by the temperature alone suggesting a thermal equilibrium between the vacancy concentration in the HfO2 layer and Si or metal oxidation. The extreme sensitivity of Vt to the external oxygen pressure can be used to tune the threshold voltage of pFET devices in advanced CMOS technologies.
Fermi-Level Unpinning of HfO2/In0.53Ga0.47As Gate Stack Using Hydrogen Anneals
Authors: Hwang Yoontae , Engel-Herbert Roman , Rudawski Nicholas , Stemmer Susanne
Published: October 2010

The electrical properties of Pt/HfO2/In0.53Ga0.47As metal oxide semiconductor capacitors were studied as a function of post-deposition annealing conditions and analyzed using the conductance and Terman methods. Forming gas annealed gate stack exhibit an unpinned Fermi level while nitrogen annealed stacks are effectively pinned at midgap.
Electrical Characterization of TbScO3/TiN Gate Stacks of MOS Capacitors and MOSFETs on Strained and Unstrained SOI
Authors: Durğun Özben Eylem , Nichau Alexander , Lopes J. Marcelo. J , Lenk Steffi , Besmehn Astrid , Bourdelle Konstantin K. , Zhao Qing-Tai , Schubert Jürgen , Mantl Siegfried
Published: October 2010

We investigated the electrical and structural properties of TbScO3 as an alternative gate dielectric. Rutherford backscattering spectrometry revealed a stoichiometric film while X-ray photo-electron spectroscopy indicated silicate formation at the interface. Capacitance-Voltage measurements resulted in well behaving C-V curves with no hysteresis and a low density of interface trap states in the range of 4x1011 (eVcm2)-1. Fully depleted (FD) SOI and sSOI MOSFETs fabricated with a full replacement gate process show a steep subthreshold slope down to 81 mV/dec and high Ion/Ioff ratios up to 108. Low field electron mobilities of 181 cm2/Vsec for SOI and 350 cm2/Vsec for sSOI, were extracted, which are comparable to MOSFETs with Hf based oxides. Gate induced drain leakage (GIDL) investigations indicate a trap assisted band to band tunneling.
(Invited) Synchrotron Radiation Photoelectron Spectroscopy of Metal Gate/HfSiO(N)/SiO(N)/Si Stack Structures
Authors: Oshima Masaharu , Toyoda Satoshi , Kamada H. , Tanimura T. , Nakamura Yoshiaki , Horiba K. , Kumigashira H.
Published: October 2010

In order to meet strong demands for precise analysis in metal gate/high-k dielectrics stack structures, we have developed high resolution photoelectron spectroscopy techniques using synchrotron radiation. We have succeeded in analyzing precise chemical-state-resolved in-depth profiles of gate electrode/dielectric multilayer/ Si structures from both front and back sides by angle-resolved photoelectron spectroscopy and maximum entropy method. Furthermore, pin-point nano-scale in-depth analysis using scanning photoelectron microscopy with sub 100 nm SR beam revealed the local formation of the intermixed region having silicide. Finally, non-destructive defect analysis using irradiation time-dependent photoelectron spectroscopy enabled us to analyze trapped charge and fixed charge.
(Invited) Multiparameter Admittance Spectroscopy
Authors: Engström Olof , Raeissi Bahman
Published: October 2010

Multiparameter admittance spectroscopy is described for investi-gating interface state properties of metal-oxide-semiconductor structures. In the conductance mode of this method, it allows for obtaining three-dimensional or contour plots of conductance data which reveal the mechanisms for capture of charge carriers into the interface states.
Stress-Induced Deterioration of Nanocrystalline ITO Embedded ZrHfO High-k Nonvolatile Memories
Authors: Yang Chia-Han , Kuo Y. , Lin Chen-Han , Kuo Way
Published: October 2010

The stress-induced deterioration phenomenon of the nc-ITO embedded Zr-doped HfO2 high-k gate dielectric film has been studied. The deterioration process is detectable from the decrease of the capacitance in the accumulation region and the shift of flatband voltage as well as the change of the amount of induced charges. In addition, the relaxation current and Coulomb blockage effect are influenced by the stress-induced process. Moreover, the nc-ITO embedded high-k capacitor shows the trap-assisted tunneling phenomenon and the Poole-Frenkel emission mechanism.
Metal-Organic Chemical Vapor Deposition of Ti-Doped NiO Layers for Application in Resistive Switching Memories
Authors: Meersschaut J. , Toeller M. , Schaekers Marc , Wang X.P. , Brijs Bert , Wouters Dirk J. , Jurczak Malgorzata , Altamime L. , Van Elshocht S. , Vancoille E.
Published: October 2010

We report on the metal-organic chemical vapor deposition of Ti-doped NiO thin films on 300 mm wafers for the application in resistive switching memories. We have used molecular oxygen as the oxidizer and Ni(dmamb)2 and TDMAT as precursors for the supply of Ni and Ti respectively. A well-behaved process is proposed for which the Ti-concentration is tunable between 0% and ~15%. We will demonstrate the functionality of resistive switching devices consisting of the stack Ni/Ti-doped NiO/TiN, and we will discuss the potential benefits of the titanium doping.
(Invited) Size-Dependent Switching and Reliability of NiO RRAMs
Authors: Ielmini Daniele
Published: October 2010

Resistive-switching memory (RRAM) based on the metal-insulator transition in some metal oxides are attracting interest as potential post-Flash nonvolatile memory devices. RRAM offers high capability for geometrical scaling, thanks to its two terminal structure and the ability for 3D stacking, However, the mechanisms of switching and reliability and their dependence on cell scaling are still under debate. This work reviews the state-of-the-art understanding of NiO RRAMs, discussing the dependence of switching and reliability on cell resistance linked to the size and nature of the localized conductive path in the cell.
Density and Grain Size of the IrOx Metal Nanocrystals in n-Si/SiO2/Al2O3/IrOx/Al2O3 Memory Capacitors
Authors: Li Wei-Chih , Banerjee Writam , Maikap Sidhu , Yang Jer-Ren
Published: October 2010

Excellent charge storage characteristics can be acquired in the novel IrOx metal nanocrystals memory devices with IrOx metal gates. The IrOx metal nanocrystals, which are small in size (diameter <4 nm) and high in density (1012/cm2), have a large memory window (>2V) at a low gate voltage of < 4V, can be used for future nanoscale NAND application.
Characteristics of ALD High-k HfAlOx Nanocrystals in Memory Capacitors Annealed at High Temperatures
Authors: Li Wei-Chih , Banerjee Writam , Maikap Sidhu , Yang Jer-Ren
Published: October 2010

Nanoscale (EOT=9.3 nm) nonvolatile memory capacitors by using atomic layer deposited high-k HfAlOx nanocrystals have been investigated. The high-k HfAlOx nanocrystals have been investigated by TEM, EDX and XPS. Due to the charge confinement in the high-k HfAlOx nanocrystals a memory window of 0.7V can be observed after 10 days of retention.
(Invited) Non-Planar Transistors with High-Mobility SiGe/Ge Channels for CMOS Applications
Authors: Tezuka Tsutomu , Kamata Yoshiki , Ikeda Keiji , Kamimuta Yuichi , Moriyama Yoshihiko , Koike Masahiro , Oda Minoru , Irisawa Toshifumi
Published: October 2010

Firstly, advantages and fabrication processes for strained SiGe fin- and wire-pMOSFETs are summarized. It is shown that strained SiGe-on-insulator channels formed by the Ge condensation process is effective to keep strain in the channel and hence to boost the current drivability of pMOSFETs. Secondly, our recent progress on a new gate-stack technology using SrGex interlayer and fabrication process of narrow Ge-fin structures using anisotropic wet etching were demonstrated for all-Ge CMOS applications. It is shown that these processes are beneficial for realizing non-planar Ge-CMOS devices in future technology nodes.
Maxwell-Wagner Instabilities and Defects Generation during CVS in REO-HfO2 Gate Stacks Grown on Germanium Based MOS Devices
Authors: Rahman Md. Shahinur , Evangelou Evangelos K. , Dimoulas Athanasios
Published: October 2010

The Current Instabilities and defects generation during constant voltage stress (CVS) in REO-HfO2 gate stacks grown on Ge (001) substrates by molecular beam deposition are extensively studied, and we report. Due to the different conductivities of the dielectrics in gate stacks charge accumulates at the interface of bilayer and results in current decay, and this behavior can be explained by the simultaneous effects of the Maxwell-Wagner instability and dielectric relaxation. However under CVS conditions new defects are created which is evident from 'Border traps' analysis.
Direct LaLuO3/Ge Gate Stack Formation by Interface Layer Scavenging and Subsequent Low Temperature O2 Annealing
Authors: Tabata Toshiyuki , Lee Choong Hyun , Kita Koji , Toriumi Akira
Published: October 2010

The scalable direct LaLuO3/Ge MIS gate stack was investigated by the IL scavenging with a subsequent low temperature O2 annealing (LOA). LOA dramatically improved the interface states degraded by the GeO volatilization from the interface, with no cost of the equivalent oxide thickness (EOT). The GeO desorption was also efficiently suppressed thanks to the upper LaLuO3 film, although a reaction between LaLuO3 and GeO2 might induce electrical defects in LaLuO3/Ge system. It is strongly suggested that the appropriate selection of high-k dielectrics (LaLuO3) and scavenging process followed by LOA enable us to achieve the scalable EOT for Ge-CMOS.
Leakage Current Improvement of Doped and Bilayer High-k for MIM Capacitor
Authors: Lim Han-Jin , Cho Kyuho , Yoo Cha Young , Nam Seok-Woo
Published: October 2010

High-k dielectrics like Ta2O5, TiO2 etc. should overcome high leakage current due to the low energy band-gap property for applying to the future DRAM device below 50nm design rule beyond. Various techniques including metal doping and bi-layer scheme were studied to improve the leakage current of I-V characteristics. The leakage current of Dy or Zr doped TiO2 could be improved depending on the doping concentration. Nb doping in Ta2O5 could increase the dielectric constant within the appropriate level of leakage current at the operation voltage. Bi-layer scheme of high-k dielectrics like HfO2-TiO2 or ZrO2-TiO2 also applied to reduce the leakage current with the high work function Ru electrode. Combination of high work function Ru as a top electrode with the bottom TiN electrode could reduce the leakage current by increasing band offset at the interface between the high-k and the electrode.
Evaluation of HfLaOx as Blocking Layer for Innovative Nonvolatile Memory Applications
Authors: Del Vitto Annalisa , Piagge Rossella , Ravizza Enrica , Spadoni Simona , Sebastiani Alessandro , Scozzari Claudia , Wiemer Claudia , Ghidini Gabriella , Alessandri Mauro , Fanciulli Marco , Maes Jan Willem , Verghese Mohith
Published: October 2010

In this paper, a study of a La-based high-k oxide to be employed as blocking oxide in future non-volatile scaled memory devices is presented. Hf1-xLaxOy deposited by atomic layer deposition is considered. In order to allow the integration of this material, its chemical interaction with an Al2O3 cap layer has been studied. Moreover, the electrical characteristics have been evaluated after integration in capacitor structures. The rare earth-based ternary oxide presents promising characteristics to be a good candidate as active dielectric for non volatile memory devices.
(Invited) Equivalent Oxide Thickness Correction in the High-k/In0.53Ga0.47As/InP System
Authors: Hurley Paul K. , Long Rathnait , O'Regan Terrance , O'Connor Eamon , Monaghan Scott , Djara Vladimir , Negara M. Adi , O'Mahony Aileen , Povey Ian , Blake Alan , Nagle Roger , O'Connell Dan , Pemble Martyn , Cherkaoui Karim
Published: October 2010

In this work we present the results of a combined experimental and theoretical investigation into the capacitance-voltage characteristics of the high-k/In0.53Ga0.47As/InP system. The emphasis of the work is placed on the maximum measured and theoretical capacitance for n and p doped In0.53Ga0.47As epitaxial layers. Theoretical calculations based on ideal systems indicate a highly asymmetric CV response, with an equivalent oxide thickness correction ~ 1.4nm (Γ valley only) and ~ 0.23nm for the high-k/n-In0.53Ga0.47As/InP and high-k/p-In0.53Ga0.47As/InP systems respectively. The theoretical calculations are compared to experimental results for Al2O3 /In0.53Ga0.47As/InP MOS structures, and discrepancies are discussed.
(Invited) Atomic-Layer-Deposited High-k Dielectric Integration on Epitaxial Graphene
Authors: Ye Peide , Neal A. T. , Shen T. , Gu J. J. , Bolen M. L. , Capano M. A.
Published: October 2010

The scaling of silicon-based MOSFET technology beyond the 22 nm node is challenging. Further progress requires new channel materials such as Ge, III-V semiconductors, carbon nanotubes (CNTs) and graphene. Perfect top-gate dielectric stacks are needed in order to sustain their potential device performance for carbon nanoelectronics. Due to the inert nature of carbon surfaces of CNTs and graphene, the challenges and current work on ALD high-k/CNTs and graphene integration are reviewed. The research work performed at Purdue University on ALD high-k integration on epitaxial graphene on SiC is summarized.
Oxygen Diffusion Barrier Applied To High-k Thin Films Deposition
Authors: Rauwel Erwan , Rauwel Protima , Ducroquet Frédérique , Matko Igor , Lourenço Armando
Published: October 2010

The effect of a thin metallic interlayer deposited on Si substrate prior the sputtering of HfO2 films was investigated. It was shown that the metallic interlayer acts as an oxygen barrier during the HfO2 deposition. After annealing, the metal diffuses in HfO2 films and prevents the formation of a low-k layer at the high-k/Si interface. However, in order to fully investigate the improvement in the interfacial and electrical properties, the thickness of the metallic interlayer needs to adapted to the thickness of the HfO2.
Competing Charge Relaxation Mechanisms in HfSiON Insulator Field Effect Transistors
Authors: Mee Jesse K. , Devine R. A. B. , Trombetta Len
Published: October 2010

We present negative bias temperature instability (NBTI) charge stress data, taken on 1 um HfSiON MOSFETs, which suggests the existence of an NBTI relaxation mechanism not previously reported in the literature. In particular, we observe significantly less NBTI damage in devices stressed in the MOSFET saturation region (large Vds) than in those stressed in the linear region (small Vds). We propose that this observation is explained by transport of trapped positive charge parallel to the channel, but inside the insulator, perhaps along a high defect density region in the HfSiON. This observation has interesting and important implications for high-k materials studies and NBTI measurement protocols.
Stress-Induced Leakage Current and Charge Trapping in Cerium Dioxide Thin Film
Authors: Chiu Fu-Chien , Chang S. H.
Published: October 2010

The reliability characteristics of Al/CeO2/p-Si devices were studied by the constant voltage stress (CVS) biased in accumulation mode. The charge trapping and stress-induced leakage current (SILC) of the MOS capacitors were found. The SILC was dominant at low field, which indicated that the trap generation rate (α) was increased with increasing voltage. Meanwhile, the charge trapping was dominant at high field, which indicated that the trapping time constant (τ) was decreased with increase voltage and the trap capture cross-section (σ) was determined to be around 1.24×10-22 cm2.
Simulation of the Breakdown Spots Spatial Distribution in High-K Dielectrics and Model Validation Using the Spatstat Package for R Language
Authors: Miranda Enrique , O'Connor Eamon , Hurley Paul K.
Published: October 2010

The application of successive high-voltage sweeps to the gate electrode of metal/MgO/InP capacitors generates multiple breakdown spots distributed over the metal gate that can be regarded, from the spatial statistics viewpoint, as a point pattern set. The spots are associated with filamentary paths running across the oxide layer and are the result of important thermal effects occurring during the current runaway phase of the breakdown event. In this work, we analyze the spatial distribution of the spots using a software package specifically developed to that aim. The package is called Spatstat and forms part of the R language library.
(Invited) Charge Trapping and the Negative Bias Temperature Instability
Authors: Goes Wolfgang , Schanovsky Franz , Hehenberger Philipp , Wagner Paul-Juergen , Grasser Tibor
Published: October 2010

During the last couple of years new measurement techniques have provided insight into the physics behind the negative bias temperature instability (NBTI) and indicate that the recoverable component of NBTI is due to some kind of charge trapping. As a consequence, charge trapping processes have been investigated and modeled in detail. We review the evolution of the latest charge trapping model by focussing on the correct temperature- and field dependence as well as on the quality of agreement with experimental stress/relaxation curves.
Field Dependent Electrical Conduction in TiN/HfO2/SiO2/P-Si (nMOS) Capacitor for Before and After Stressing
Authors: Sahoo Santosh K. , Misra Durga
Published: October 2010

The electrical conduction mechanism contributing to the leakage current at different field regions and different temperatures have been studied in this work. The current-voltage (I-V) measurement of TiN/HfO2/SiO2/P-Si nMOS capacitor, taken before and after constant voltage stress suggests that Poole-Frenkel mechanism is the dominant conduction mechanism. It was also observed that at low field region Ohmic conduction dominates. Trap energy level (φt) of 0.36 eV, obtained from Poole-Frenkel mechanism indicates that the defect is oxygen-related and is a good match with the reported value for V-/V-- in HfO2. Significant charge trapping at low level stress was observed whereas at high level and elevated temperature stressing suggests a variation of trap energy level indicating new defect formation.
Metal Surface Preparation for Wafer Bonding with Point of Use Wet Chemistries
Authors: Sood Sumant , Farrens Shari , Rardin Anthony , Kirk Simon , Pettit Dave
Published: October 2010

Diffusion and eutectic bonding are gaining broad acceptance in 3D integration and packaging. Many bonding schemes are based on copper because this material is used extensively in FEOL, has a well developed CMP history and high yield TSV's have been proven. One of the issues for low resistivity interconnects and high bonding yield is the surface cleaning methods used to remove copper oxidation. This paper will present the results of studies using DuPont EKC products for copper surface preparation prior to wafer bonding.
Metal Thermocompression Wafer Bonding for 3D Integration and MEMS Applications
Authors: Dragoi Viorel , Mittendorfer Gerald , Burggraf Jürgen , Wimplinger Markus
Published: October 2010

Metal bonding layers are used in various wafer bonding applications in MEMS and more recent in wafer-level 3D integration and optoelectronics. The bond process investigated in this paper is thermocompression. The most used metals for such applications are Cu, Au and Al, each of them with specific requirements for the wafer bonding process. While Au use doesn't face the problem of surface oxidation, both Cu and Al surfaces are covered by native oxides when exposed to ambient atmosphere: the oxidized surfaces impact on bonding process results, so their condition is crucial for successful process. The main process conditions for Cu-Cu and Al-Al bonding are reviewed and examples are presented.
Failure Diagnostics for 3D System Integration Technologies in Microelectronics
Authors: Altmann Frank , Schmidt Christian , Brand Sebastian , Czurratis Peter , Petzold Matthias
Published: October 2010

The reduced testability of 3D integrated microelectronic systems poses severe challenges to microstructure diagnostics, fault isolation and failure analysis techniques that are required to detect and analyze electrical opens, high resistive contacts and electrical shorts of the interconnects in the wafer-bonded interface. The potential of applying advanced Scanning Acoustic Microscopy and Lock in Thermography methods for defect localization as well as the application of combined laser and Focused Ion Beam techniques for target preparation and defect diagnostics is demonstrated.
(Invited) Room Temperature Bonding of Wafers with Thin Nanocrystalline Metal Films
Authors: Shimatsu Takehito , Uomoto Miyuki
Published: October 2010

Room temperature bonding between two flat wafers using thin metal films was studied. Thin nanocrystalline metal films (0.2-20 nm thick) were fabricated on two flat wafers' surfaces using sputter deposition. Bonding of the two metal films on the wafers was accomplished immediately after film deposition in vacuum. The wafers were bonded at room temperature over the entire bonded area using metal films of 16 kinds including W films. The two films' bonded structure was related closely to the self-diffusion coefficients of the metal films. The very high atomic diffusion coefficient at the grain boundaries and film surfaces is likely to have enabled bonding at room temperature. The wafers were bonded even with films of 0.2 nm thickness on each side. The potential of the bonding for applications to device fabrication is examined. Moreover, bonding in air using noble metal films is examined according to experimental results.
Cu-Sn Wafer Level Bonding for Vacuum Encapsulation of Microbolometer Focal Plane Arrays
Authors: Lapadatu Adriana , Simonsen Tor Ivar , Kittilsland Gjermund , Stark Birger , Hoivik Nils , Dalsrud Vegar , Salomonsen Guttorm
Published: October 2010

Wafer level vacuum encapsulation for wafers with integrated and released sensitive microelectromechanical structures has been achieved by making use of Cu-Sn solid liquid interdiffusion bonding. By using a Sn layer as oxidation barrier for the Cu underneath, the bonding surface does not require pre-cleaning or use of any flux agent prior to, or during bonding. With a tailored temperature and pressure bonding profile, the amount of Sn squeeze-out is reduced. Cross sections through the bonded frames were used to investigate the formation of Cu-Sn intermetallic compounds. The strength of the joints was measured using a shear test, which resulted in an average value of 35MPa. Further temperature cycling of bonded dies does not result in any reduction in bonding yield or shear strength. The concentric interference fringes revealed by IR pictures of the bonded wafer pairs demonstrate that the cap on each device is deflected towards the bottom wafer, confirming that the pressure in the bonded cavities is low.
Developing a Wafer Level Gold-Polysilicon Eutectic Bond Process to Protect Sensitive Electronic Devices
Authors: Saeidi Nooshin , Flynn Michael , Byun Ki Yeol , Yu Ran , Ferain Isabelle , Colinge C. , Demosthenous A. , Donaldson N.
Published: October 2010

Modern micro-systems can employ sensitive electronic circuits, micrometer sized mechanical devices and sensor elements. Common such systems available include accelerometers, switches, bio-medical implants and pressure sensors. The sensitive nature of these devices requires them to be physically sealed from harsh environment in which they operate. Additionally hermetic or vacuum packaging can at times be required for either operation of the device or peak operating efficiency. Hermetic sealing of such devices has been demonstrated using multiple wafer level bonding technologies, in this paper the various techniques employed and the development of a gold-polysilicon wafer bonding process is discussed.
Al-Ge Eutectic Wafer Bonding and Bond Characterization for CMOS Compatible Wafer Packaging
Authors: Sood Sumant , Farrens Shari , Pinker Ron , Xie James , Cataby Wilbur
Published: October 2010

Most current MEMS packaging applications either use glass frit and anodic bonding or metals such as gold that are not compatible with CMOS front end processing. There is a growing need for a wafer bonding process that is suitable for both MEMS and CMOS fabs. Al-Ge based eutectic bonding not only overcomes most of the drawbacks associated with glass-frit and anodic bonding; it also provides a practical solution for wafer level packaging for CMOS/MEMS applications as both Al and Ge are CMOS and MEMS Fab-friendly materials. In addition to providing a hermetic seal, AlGe bonding provides an electrically conductive path between two substrates. This paper describes a practical AlGe based bonding and post bond characterization process. In addition, a novel post bond hermeticity/ leakage testing process is also described in this paper.
(Invited) Wafer Bonding Technology in Nitride Semiconductors for Applications in Energy and Communications
Authors: Ryu Kevin K. , Chung Jinwook W. , Lu Bin , Palacios Tomas
Published: October 2010

Wafer bonding is an enabling technology for the fabrication of advanced electronic devices based on the integration of high-quality heterogeneous materials. This paper summarizes our work on wafer-level bonding of nitride semiconductors and its application to electronic devices. Our bonding technology uses a thin silicon dioxide (SiO2) or Benzocyclobutene (BCB) interlayer to enhance the bonding, and it has been applied to the fabrication of three different kinds of devices: hybrid chips where Si (100) MOSFETs are integrated with GaN transistors in close proximity; N-face GaN transistors on Ga-face grown material for high frequency applications; and high power GaN power switches with record breakdown characteristics.
New SOI Substrate with High Thermal Conductivity for High Performance Mixed-Signal Applications
Authors: Lee Taehun , Burzo Mihai , Raad Peter , Aliev Ali , Komarov Pavel , Kim Moon
Published: October 2010

Various materials, such as Si3N4, AlN, Al2O3, Diamond-like-carbon (DLC) and Diamond were employed as new buried oxide (BOX) candidates. Each candidate material has been fabricated by appropriate deposition methods and was extensively evaluated with respect to its thermal, physical and electrical properties. In order to understand thermal dissipation property, the measurement of thermal conductivity was performed by transient thermal-reflectance method and 3 omega method as a function of BOX thickness for a given material. The hydrogen implantation induced layer transfer technique was used for a silicon-on-insulator (SOI) fabrication.
Circular Geometry Transistors Fabricated on Germanium-on-Alumina Bonded Substrates
Authors: Baine Paul B. , Low Yee H. , Rainey Paul V. , Gamble Harold S. , Armstrong Mervyn , Mitchell Neil S. , McNeill David W.
Published: October 2010

Germanium (Ge) has been bonded to fine grain alumina (Al2O3) by means of a polished polycrystalline silicon interface layer. After room temperature bonding and subsequent bond strength annealing at 150 oC for 24 hrs, the germanium layer was ground and polished to 100µm. Low temperature Tungsten (W) gate circular geometry devices, W/L = 9, fabricated on this layer exhibited effective mobility values of 150 cm2/Vs. This is much lower than results obtained on equivalent devices on bulk Ge. Improvement in the germanium polish process resulted in transistors with an effective mobility of 415 cm2/Vs, comparable to that of the bulk Ge devices. Low temperature measurement, down to temperatures of 173 K, showed an improvement in device performance resulting in both an increase in effective mobility to 591 cm2/Vs and a decrease in sub threshold slope from 180 mV/dec to 60 mV/dec indicating a reduction in leakage current.
Structural and Electrical Properties of Low Temperature Direct Bonded Germanium to Silicon Wafer for Photodetector Applications
Authors: Yu Ran , Byun Ki Yeol , Gity Farzan , Hayes John , Ferain Isabelle , Colinge C. , Corbett Brian
Published: October 2010

A Ge/Si heterostructure with an ultra-thin transition layer was fabricated at low temperature by direct bonding. In-situ oxygen or nitrogen radical activation was performed after hydrophilic cleaning on both Germanium and Silicon surfaces. The interfacial structure was analyzed by Scanning Acoustic Microscopy (SAM) and High-Resolution Transmission Electron Microscopy (HR-TEM). The samples were diced into mesa structures and electrical properties at different locations were measured in order to characterize the quality of the bonded heterostructure.
200 mm Silicon on Porous Layer Substrates Made by the Smart Cut Technology for Double Layer Transfer Applications
Authors: Stragier Anne-Sophie , Signamarcheix Thomas , Salvetat Thierry , Nolot Emmanuel , Dechamp Jerôme , Mercier David , Gergaud Patrice , Tauzin Aurélie , Clavelier Laurent , Lemiti Mustapha
Published: October 2010

Silicon On Porous Layer (SOPL) substrate was elaborated by applying the Smart Cut{trade mark, serif} technology to silicon substrate having a superficial porous Si layer. Porous Si layer morphology was characterized after anodisation process. A single crystalline/porous Si bilayer was transferred onto a handling wafer to form SOI like structure. Subsequent bonding to a final wafer and separation induced in the fragile embedded porous Si layer led to the double-transfer of the single crystalline Si layer. Changes in mechanical properties and chemical composition of the embedded porous silicon layer as a function of the annealing temperature were also determined. Thickness homogeneity of the transferred thin Si layer was estimated after SOPL fabrication and after double-transfer achievement. The perfect crystallinity of the active Si layer was conserved during the whole process. SOI-like structure fabrication and subsequent separation of thin high quality Si film are reported in order to demonstrate adequacy of SOPL with post device post processing substrate removal.
Single Crystal Silicon Film Transfer onto Polymer
Authors: Argoud Maxime , Moriceau Hubert , Fretigny Christian , Rieutord François , Morales Christophe , Clavelier Laurent
Published: October 2010

The realization of SOP (Silicon On Polymer) structures, in other words a single crystal silicon film transferred onto polymer was investigated in this paper. SOP realization technique includes two major steps: polymer bonding and ion slicing. Polymer bonding is used and developed in our process, because it is a technique that allows some benefits (simplification of surface treatments and low temperature processing) in comparison of other bonding methods. Interface observations (infra-red transmission, scanning acoustic microscopy and X-ray reflectivity) and mechanical characterizations (blade insertion and four-points bending) have been developed to define a suitable polymer bonding process. Transferred Si layer quality of SOP structures and the compliance induced by the polymer layer are discussed.
LiNbO3 Single Crystal Layer Transfer Techniques for High Performances RF Filters
Authors: Deguet Chrystel , Pijolat Mathieu , Blanc Nicolas , Imbert Bruno , Loubriat Sebastien , Defay Emmanuel , Ricart Thibault , Clavelier Laurent , Moulet Jean Sebastien , Ghyselen Bruno , Letertre Fabrice , Ballandras Sylvain
Published: October 2010

In this paper we present the realization of engineered substrates based on thin single crystal piezoelectric layers. Their potential interest for next generation of ultra wide band RF filters has been demonstrated. For this purpose we propose two different methods to transfer a thin monocrystalline layer: the Smart Cut{trade mark, serif} technology and a "bond and etch back" technology. Lithium Niobate (LiNbO3) has been chosen for its high electromechanical coupling factor of about 45% for bulk acoustic waves but also for its availability as single crystal wafers diameters up to 6 inches. Engineered substrate process, material and electrical characterizations are presented. The first objective of this study is to demonstrate LiNbO3 piezoelectric property preservation after processes whatever the used technology. High overtone Bulk Acoustic Resonators have been used as test vehicles to characterize these layers so as to evaluate layer transfer achievement of sub micron single crystal LiNbO3.
Thermal Behavior of the Mechanical Properties of GaN throughout Hydrogen-Induced Thin Layer Transfer
Authors: Tapily Kandabara , Moutanabbir Oussama , Gu Diefeng , Baumgart Helmut , Elmustafa Abdelmageed
Published: October 2010

We report on the thermoevolution of the mechanical properties of H-implanted bulk GaN under the ion-cut process conditions. The mechanical properties were measured using a nanoindenter equipped with a continuous stiffness measurement attachment. The data were taken in depth control mode. Based on nanoindentation analysis, we obtained a modulus of 321{plus minus}7.3GPa and a hardness of 29.6{plus minus}1GPa for the as-implanted GaN samples. After implantation, the modulus and hardness values were found to be 321{plus minus}25GPa and 29.6{plus minus}3GPa, respectively. The influence of thermal treatment on the elasto-mechanical properties of H-implanted bulk GaN is investigated and its role in ultrathin layer splitting is discussed.
Lattice Strain and Strain Evolution in Hydrogen-Implanted Materials: The Roles of Mechanical Properties and Hydrogen Diffusion
Authors: Ventosa-Moulet Caroline , Hayashi Sumiko , Goorsky Mark S.
Published: October 2010

The strain introduced by the implantation of hydrogen into a material for subsequent exfoliation and layer transfer provides a useful monitor for the kinetics of the subsequent exfoliation process. We demonstrate that the level of strain induced by the implantation process, for a given dose, and at low temperatures, is determined by the energy loss per implanted ion by nuclear collisions, which, in turn, correlates strongly with the mechanical parameters such as the Young's modulus and bulk modulus. The magnitude of the dose linearly changes the maximum strain in the layer. At higher temperature implants, the maximum strain is reduced and is associated with the diffusion of point defects during implantation. These observations provide a means to predict the implant profile for any combination of implant dose, energy, and target material for parameters used for exfoliation processes at low temperatures. These results are also consistent with the literature that shows such a relationship for heavier ions at lower doses and for hydrogen implanted into semiconductors with different crystallographic orientation.
Hydrogen Ion-Induced AlN Thin Layer Transfer: An Elastomechanical Study
Authors: Tapily Kandabara , Moutanabbir Oussama , Abdullah Mamun , Gu Diefeng , Baumgart Helmut , Elmustafa Abdelmageed
Published: October 2010

The change in the micro-structural properties of epitaxially grown AlN as a function of different H-fluences and thermal evolution was elucidated by nanoindentation and by atomic force microscopy. In this study, we investigated 2 μm-thick AlN layers grown epitaxially on sapphire. The elasto-mechanical properties were measured using a Nanoindenter with continuous stiffness measurement attachment. The AlN samples were implanted with hydrogen ions at 50 keV with various fluences ranging from 0.5 × 1017cm-2 to 3 × 1017 cm-2. The modulus and hardness were carefully determined for each sample. The samples were then annealed in air at temperatures ranging from 300oC to 600oC for 5 min to study the influence of pre-layer splitting treatments on the mechanical properties.
The Role of the Nucleation Annealing Temperature Annealing on the Exfoliation of Hydrogen-Implanted GaN
Authors: Padilla Eric , Jackson Michael , Goorsky Mark S.
Published: October 2010

GaN exfoliation of ~ µm thick layers was achieved - thicker than has been reported elsewhere - due to an understanding of the introduction and evolution of strain-related defects produced during hydrogen implantation. Analysis and modeling of the strain via triple axis diffraction and SRIM calculations showed one strained region near the surface and the second at the projected range. After annealing at temperatures up to 450 °C (1-40 hours), the surface strain decreases, whereas the strain near the projected range decreased monotonically as the annealing temperatures increased to 300 °C but showed a reversal at higher temperatures. This led to a two step exfoliation process with a low temperature step performed for 20 hours followed by high temperature annealing (850 °C). For a 150 °C first step, the combination produced a series of small (< 1 µm) blisters whereas a 375 °C first step combination produced 5-10 µm-sized exfoliated sections.
MEMS Process by Film Transfer Using Fluorocarbon Anti-Adhesive Layer
Authors: Schelcher Guillaume , Brault Sebastien , Parrain Fabien , Lefeuvre Elie , Dufour-Gergam Elisabeth , Tatoulian Michael , Bouville David , Desgeorges Martial , Verjus Fabrice , Bosseboeuf Alain
Published: October 2010

A low cost and low temperature MEMS transfer process is presented. The process is based on adhesion control of molded electroplated Ni microstructures on donor wafer by using plasma deposited fluorocarbon film. Adhesive bonding of the microstructures on the target wafer using BCB sealing enables mechanical tearing out from the donor wafer. This proposed process has allowed us to realize from 7 µm down to 700 nm thick Ni patterns on Si, Pyrex glass wafers and Kapton foils. Multiple transfers lead to Ni stacked microstructures. Because this process is simple and only involves a low temperature (250°C) heating of the host wafer, it is highly versatile and suitable for various applications and brings new perspectives towards 3D integration of MEMS/NEMS.
Optimization of Silicon-Silicon Adhesive Wafer Bonding
Authors: Holl Susan L. , Korrapati Srinivasulu , Colinge C.
Published: October 2010

Optimization of bonding parameters to develop a low temperature adhesive wafer bonding process for silicon was studied. SU-8 was used as the adhesive. The Key Process Input Variables were soft bake temperature, UV exposure and bonding temperature. The soft bake temperatures were 70 oC, 90 oC and 95 oC. UV exposure energies were 50 mJ/cm2, 100 mJ/cm2 and 150 mJ/cm2 and bonding temperatures of 90 oC, 115 oC and 140 oC were studied to optimize the curing process. The quality of the bonds was determined by two Key Process Output Variables: the fraction of interfacial area in intimate contact, measured by void area, and the strength of the bond interaction, measured by tensile strength. A general linear statistical model was used to determine the impact of the KPIVs on the KPOVs. The optimum conditions are soft bake temperature: 90 oC, UV exposure: 100 mJ/cm2 and bonding temperature: 115 oC.
Reactive Bonding and Low Temperature Bonding of Heterogeneous Materials
Authors: Wiemer Maik D. , Braeuer Jörg , Wünsch Dirk , Gessner Thomas
Published: October 2010

This paper describes alternative low-temperature bonding procedures in Microsytems Technology. On the one hand reactive bonding is introduced, which is a relatively new joining technique for the mounting of microelectric components and the hermetic sealing of microelectronic packages. The usage of commercially available Ni/Al foils is demonstrated for room-temperature bonding an IR-emitter onto a covar socket. Furthermore integrated nano scale multilayer films of aluminum and titanium as well as titanium and amorphous silicon were magnetron sputter deposited and characterized. On the other hand surface activating procedures prior to bonding, like low- and atmospheric-pressure plasma, are presented. The wafer level bonding was examined for silicon to lithium tantalate (LiTaO3) and Foturan{copyright, serif} by using CMP-processes and plasma activation. The bond strength was characterized by micro chevron test to evaluate the different bonding, plasma and annealing conditions. The results showed that with the surface activation the bond strength can be dramatically enhanced.
Surface and Interface Characterization of Sequentially Plasma Activated Silicon, Silicon dioxide and Germanium Wafers for Low Temperature Bonding Applications
Authors: Zhang Fangfang , Kibria M.G. , Cormier Kyle , Howlader Matiar
Published: October 2010

This article reports the sequentially plasma activated bonding (SPAB) of n-Ge with p-Si and SiO2 at low temperature. Surface activation resulted in highest hydrophilicity of Ge compared with Si and SiO2 counterparts. The highest hydrophilicity of Si, Ge and SiO2 induced by O2 RIE plasma was combined with their highest reactivity induced by MW N2 radicals while maintaining smooth surface roughness. Weak bonding strength of Si/Ge and SiO2/Ge in the SPAB at room temperature was improved after heating at 200°C, but they were still lower than that of Si/Si in the SPAB at room temperature, which is due to the unique reactivity of Ge. The deviation of the reverse bias behavior from a typical p-n junction is due to the low doping concentration in Ge. The degradation of current in the sequential heating resulted mainly from the oxidized surfaces of Ge and Si as well as the bonded interface.
High Quality Thin Body III-V-On-Insulator Channel Layer Transfer on Si Wafer Using Direct Wafer Bonding
Authors: Yokoyama Masafumi , Yasuda Tetsuji , Takagi Hideki , Yamada Hisashi , Urabe Yuji , Fukuhara Noboru , Hata Masahiko , Sugiyama Masakazu , Nakano Yoshiaki , Takenaka Mitsuru , Takagi Shinichi
Published: October 2010

Integration of III-V semiconductor compounds into Si wafers has been paid match attention because of requirements of the high electron mobility and low effective mass channel materials instead of Si and requirements for monolithic integration of the electrical and optical integration. However, it has been still challenging due to several differences between III-V semiconductor compounds and Si in material properties: lattice constant, thermal tolerance, and material toughness. Therefore, for fabricating thin body III-V-on-insulator (III-V-OI) on Si wafers with retaining the high crystal quality, we have developed low damage and low temperature direct wafer bonding (DWB) processes using buried oxide protection layers. We have demonstrated high electron channel mobility thin body III-V-OI metal-oxide-semiconductor field-effect transistors (MOSFETs) on Si substrates. The transistor property has exceeded the Si MOSFETs and comparable to the bulk III-V MOSFETs, indicating that we can transfer the high crystal quality III-V-OI channel layers using these DWB processes.