Improvement of Germanium Channel Nmosfet By Using Fluorine Co-Implant Methods
Authors: Chi Ting- Han , Lin Yu-Hsien , Tsai Wan-Ting , Li Hui-Hsuan 
Published: February 2020

1.Background/ Objectives and Goal

Ge has been investigated as a high mobility (both hole and electron) channel material as a substitute for silicon channels in order to boost the device performances. In this paper, we successfully fabricated the Ge nMOSFETs by using fluorine co-implant method. The Ge nMOSFETs by using fluorine co-implant method has good performance with ION/IOFF ratio of ~8.6×103 at VDS = 1V and the subthreshold swing of 382 mV/dec.

2.Methods

Fig. 1 illustrates the process steps and structure of our Ge nMOSFETs by using F co-implant methods. We use (100)-oriented p-type Ge wafer with resistivity 0.1~0.6 Ω-cm as the starting material. Firstly, a 400 nm field oxide was deposited on p-type Ge substrates after diluted HF cyclic surface clean. The source/drain regions were defined by photolithography, and subsequently the oxide was etched by BOE. Then a implantation was used to create an n+ source/drain with P and F co-implant at different dose and energy. Following by 100nm SiO2 capping layer, dopant activation with different sequence were accomplished through rapid thermal annealing (RTA) at 600 °C in N2. The split table of dose/energy and RTA sequence was shown in table 1. After defining the active region, a GeO2 (~2 nm) was formed at 520°C for 30 s in pure O2 ambient (~1030 mBar) and then an Al2O3 (5 nm) was covered.

3.ExpectedResults/Conclusion/Contribution

Fig. 2 shows the I-V characteristics of co-implant n+-p Ge junction for different annealing sequence, we can observe that the reverse leakage currents of n-Ge contacts decreased. The sequence splits are the P implantation following by annealing at 1 minute and then F implantation following by annealing at 1minute / 2 minutes. It’s obvious that the F could passivate the defect through P implantation by sufficient thermal annealing in the P+F@RTA_1+2min co-implant sample with low reverse leakage current than the P+F@RTA_1+1minsample.

Fig. 3  shows the ID-VGS transfer characteristic of the control sample and the P+F@RTA_1+2min co-implant sample of nMOSFETs with W/L =100 μm /10 μm. The measurement voltage were in the linear region at VDS = 0.1 V and the saturation region at VDS = 1 V. We can observe that the co-implant nMOSFET have superior ION current, low IOFF current, ION/IOFF ratio and good subthreshold swing. The ION/IOFF ratio of the co-implant nMOSFET was of ~8.6×103 at VDS = 1V and the subthreshold swing was of 382 mV/dec. The white line cutting is the gate dielectric GeO2 (~2 nm) and Al2O3(5 nm) on top of the Ge substrate.

The Ge-nMOSFET and n+-p Ge junction device have been demonstrated by F co-implant methods on p-type Ge substrate. The F implantation can passivate the vacancies in Ge substrate and enhance the overall activated fraction of the dopant in Ge. The shallow junction, low off-state leakage current, and low series resistance could be achieved. Moreover, we also use the best condition to fabricate the Ge n-MOSFET, and superior IONcurrent, low IOFF current, ION/IOFF ratio, good subthreshold swing, and low RSD could be realized. The co-implant methods have great potential for leakage current improvement and shallow junction in the conventional Ge process.

REFERENCES

[1]M. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar,M. Metz, N. Zelick, and R. Chau, “High Mobility Si/SiGe Strained Channel MOS Transistors with HfO2/TiN Gate Stack,”IEEE International Electron DevicesMeeting,p.28, Dec. 2003

 [2]T. Krishnamohan, C. Jungemann, and K. C. Saraswat, “A Novel, Very High Performance, Sub-20 nm Depletion-Mode Double-Gate (DMDG) Si/Si,Ge(l.,jSi Channel PMOSFET,” in IEDM Tech. Dig., 2003, pp. 687-690.

Figure 1