bluuebunny/crossref_metadata_2025 huggingface dataset:
In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results
Authors: Segal Julie , Sagatelian Arman , Hodgkins Bob , Ho Tom , Chu Ben , Singh Tony , Berman Harvey
Published: December 2020

Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.
Failure Analysis from the Backside of a Die
Authors: Liebert Silke
Published: December 2020

A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using PEM are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an AFM tip for detection of interrupts within conductive interconnects are described.
Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring
Authors: Fliesler Michael , Morgan Ian H.
Published: December 2020

Continuous improvements over time to a CMOS Flash Memory technology resulted in significant improvement in Human Body Model (HBM) ESD immunity for “I/O’s” to Vcc power supply and Vss ground pins. Remaining low level failure modes in the die core included elevated standby current that in some cases could not be localized even with extensive chip de-processing. In addition an apparent functional failure upon post stress ATE test was isolated for certain part revisions. Routine separation of Vss/Vcc supply pin combinations from “all other pins” during HBM ESD test allowed identification of the several failures occurring in the die core. Failure analysis and corrective action is described. Additional diagnostic testing using separate polarity HBM pulses aided in tracing the conduction path causing the apparent functional failure and prompted investigation of HBM tester dynamic properties. It was determined that the magnitude of the “second” HBM pulse in certain testers was sufficient to cause a false powerup condition which results in apparent functional failure upon subsequent ATE test. In-situ monitoring of the Floating Power Bus response (in this case Vss) during application of HBM stress to the Input-pad to Vcc-pin combination revealed a transient caused by the “second” pulse that allowed such apparent failures to be invalidated. Further more, monitoring the in-situ floating Vss bus response to the HBM allowed conclusions to be drawn as to the utility of different power bus and Vss/Vcc supply clamp layouts, thereby allowing improvements to die layout to be implemented.
Transmission Line Pulse Testing of the ESD Protection Structures in ICs – A Failure Analyst’s Perspective
Authors: Henry Leo G. , Barth Jon , Richner John , Verhaege Koen
Published: December 2020

The IC industry continues to find ways to improve the ability to correlate the electrical failure signature of devices with the physical failure location using different techniques. The purpose of this work is to show that improved transmission line pulse (TLP) testing technique of ESD (ElectroStatic Discharge) protection structures can provide accurate identification of leakage current to better identify where ESD stress testing should stop and failure analysis should begin. Besides the traditional current and voltage measurements at the Device Under Test (DUT), this new TLP testing technique includes the ability to correct for the measurement system losses for improved accuracy. The pulse width of the TLP is chosen to provide the same current amplitude damage level (electrical) as is found in the Human Body Model (HBM) ESD stress testing. This allows a one to one correlation between the two methods and hence the means to correlate the electrical damage of the device and the physical location of the failure site. An SCR (Silicon Controlled Rectifier) device is used as an example.
Thermal Fatigue Induced Voiding in LDMOS Transistors Submitted to Multiple Energy Discharges
Authors: Percheron-Garcon I. , Bosc J.M. , Levade C. , Cabié M. , Vanderschaeve G.
Published: December 2020

The repetitive energy discharge test (power cycling) is an accelerated stress test (AST) that can be used to characterize the long-term behavior of power transistors taking into account stress on customer final application. This paper describes the application of this test to an LDMOS transistor in order to optimize both design and size while preserving final reliability of the product. We will detail this reliability characterization program, emphasizing the power cycling tests performed in extreme conditions in order to reach and study physical limit of LDMOS devices. Analysis of LDMOS devices under these extreme conditions indicated evidence of metal voiding: the conditions of formation of these thermal fatigue induced voids will be discussed. The effect of major parameters like power cycling energy, ambient temperature will also be discussed. Electrical characterization of stressed devices will be presented. Finally, the results of the Transmission Electron Microscopy characterization of the metal microstructure will be discussed.
Contrast Inversions in Scanning Acoustic Microscopy (C-SAM) of Glue Die-Attach
Authors: Plikat Boris
Published: December 2020

The quality of the die attach is crucial for almost all power devices, as in most cases thermal and electrical transport is vertical through the die and its backside. For glue inspection, C-SAM through the lead frame is widely used. Ordinarily, one of the three following states of delamination is found: (A) no delamination, (B) delamination at the die, or (C) delamination at the lead frame. A general rule for the assignment of the brightness in C-SAM amplitude images to these states of delamination cannot be given. This is evidenced by contrast inversions observed with frequency variation of the applied ultrasound or variation of the glue thickness. Contrast inversions at images through the lead frame occur between areas of states (A) and (B). The calculation of ultrasonic echoes for a three-layer model (copper, glue, silicon) shows that the contrast inversions are connected to the first resonance of the glue in state (B). Here complicated shapes of the echoes are found in experiments and calculations, which helps to correctly assign brightness levels to delamination states. Additionally a flow for reliable glue investigation with the use of through-transmission SAM inspection is proposed.
Focused Ion Beam Analysis of Low-K Dielectrics
Authors: Bender H. J. , Donaton R. A.
Published: December 2020

The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.
Temperature Distributions in III-V and SiC Micro-Wave Power Transistors Using Spatially Resolved Photoluminescence and Raman-Spectrometry Mapping Respectively
Authors: Martin P. , Bisaro R. , Dua C. , Noblanc O. , Delage S. L. , Floriot D. , Lemaire F. , Galtier P. , Landesman J. P. , Brylinski C.
Published: December 2020

This paper describes a new method for the mapping of local temperatures in the active region of highpower III-V semiconductor transistors for microwave applications. The measurement technique involves scanning a focused laser beam at the surface of a chip inside its package, while the photoluminescence (PL) or the Raman spectra produced are recorded sequentially for each position of the laser beam. The local temperature is deduced either from the corresponding wavelength shift of the PL (which represents changes in the band-gap due to heating) or from Raman Stokes peak shift or from the Stokes to anti-Stokes intensity ratio (which correspond to changes in optical phonon frequencies and population respectively due to heating). Results are shown both for SiC-based field effect transistors and for bipolar type transistors (heterojunction bipolar transistors – HBTs – in the GaAs/Ga1-xInxP system). A spatial resolution of 1 µm and an accuracy in the temperature determination of ± 3 °C are demonstrated, especially for the HBTs. Finally, procedures are proposed to implement the information on local operating temperatures provided by this method into thermal resistance calculations.
New Laser Ablation Method for Non-Destructive Backside Sample Preparation
Authors: Beaudoin F. , Perdu P. , Saviot F. , Lewis D. , Salin F.
Published: December 2020

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, on a TSOP plastic package with an oversized silicon die, on a DIL ceramic package and on a CCD device. Feasibility of silicon thinning using laser ablation is also discussed.
Intel® Component Diagnostic Technology: Tools and Education for Intel Component Defect Reduction
Authors: Doll Julie S.
Published: December 2020

To enable efficient, accurate debug of Intel architecture components to take place within contract manufacturing sites, and to provide alternatives for the removal of Intel components from, Intel is deploying a diagnostic capability and attendant educational collateral known as to achieve these objectives Intel® Component Diagnostic Technology. This paper will describe details of Intel® Component Diagnostic Technology, including the diagnostic fixture and user interface, diagnostic scripts and analytical coverage, data management and reporting, and on-site and Web-based educational offerings.
Identification and Characterization of Ultra-Thin (<100 nm) Flakes Using a Combination of Face-Lapping, High Energy (10 kV) SEM Imaging, and TEM
Authors: Mitro D. , Subramanian S. , Yeung S. (Wai Lung) , Chrastecky T. , Hagedorn B. , Widener E.
Published: December 2020

Ultra-thin (<100 nm) flakes shorting metal lines are difficult to detect and often cause the device to fail after reliability stress or at the customer site. In most cases, the common technique of inspecting the device in an optical microscope followed by conventional low energy (<3.0 kV) scanning electron microscopy (SEM) is often not able to detect this type of defect. In rare cases, where the defect is successfully exposed by the traditional procedure, it is very challenging to perform additional transmission electron microscopy (TEM) characterization of the defect without introducing arifacts during sample preparation of the exposed flake. A new procedure to identify these defects using a combination of face-lapping and high energy (>10 kV) SEM imaging is described in this paper. In this method, the failing device is carefully face-lapped and inspected frequently using a high energy (>10 kV) scanning electron beam. The high energy electron beam penetrates through the oxide layer and detects features embedded below the oxide. This technique greatly incresases the chances of detecting the flake, as the method is capable of detecting the defect at a larger range of oxide thickness as opposed to the traditional method. Additionally, TEM results were improved when the ultra-thin flakes were detected below the surface with the high energy SEM technique. Several examples of ultra-thin flakes found using the high energy SEM vs. low energy SEM will be presented.
Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps
Authors: Zanon T. , Maly W.
Published: December 2020

Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.
Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology
Authors: Wu Huixian , Cargo James , Wu Huixian , White Marvin
Published: December 2020

The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.
Via Electromigration Related Functional Failure—A Case Study
Authors: Chowdhury Vijay
Published: December 2020

Specialized structures have been developed to understand how interconnect and via would link together in a circuit to bring out the weakest link in the interconnect-via system. This article reports a phenomenon where electromigration occurred in an actual circuit with signal lines connected by individual vias. A prediction is made into the weak link in the via-Interconnect system based on real time product. In the interconnect-via system used, the TiW barrier blocked the material flow from M2 to Ml. W plugs would block the material flow as they do with the barrier layers and the failures would occur at the via to interconnect interface as noticed in this case. Depending on the electron flow through the via, the material will either accumulate at the via-interconnect interface, which will induce inter-metal dielectric cracks, or deplete, causing discontinuity (opens) of the interconnect lines.
Experiment Study on Crystal/Amorphous Structure of TEM Samples Prepared by FIB Milling
Authors: Gao Qiang , Zhang Mark , Niou Chorng , Li Ming , Chien W.T. Kary
Published: December 2020

It has been reported that a sample prepared by ion beam milling has a sandwich structure with amorphous on two sidewalls and crystal in the middle. In this paper, the sandwich structure of such a single crystal TEM sample was studied experimentally. A novel sample and its fabrication process were reported. The sandwich structure can be observed directly in TEM with this sample. When the crystal layer in monocrystal silicon TEM sample is less than 18 nanometers, or when the sample is thinner than 64 nanometers, the sample will be observed as fully amorphous. Removal of the amorphous layer on the sample sidewalls is crucial to get TEM pictures of better quality.
A Study of Flip-chip Open Solder Bump Failure Mechanism
Authors: Wang Zhaofeng , Choudhry Mahmood
Published: December 2020

The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation took place at Al – TiW interface. However, EDS analysis on the separated surface indicated the presence of Al metal at both sides of the separation, which raises a question of why the Al layer is cracked or separated instead of interface de-lamination. Research in literature and investigation at assembly line points an ultrasonic cleaning step in manufacturing process as a contributor to the open bump failure. Examining virgin dice after bump removal observed crack in nitride passivation around the bump neck, indicating high stress level during passivation film deposition and/or bump formation process. Hence it is concluded that ultrasonic cleaning in device assembly aggravates preexisting stress in weak bump(s), resulting in latent failure in field application.
Realization of an Integrated IT System Covering the Complete Failure Analysis Process
Authors: Grützner Markus
Published: December 2020

In the failure analysis (FA) process, a large amount and variety of data are involved: product information, images created by lab equipment, requester and accounting information, etc. Instead of using separate tools for image handling, sample tracking, report creation, and email, workflows can be improved by integrating all these functions in one single IT system. This paper describes the process and result of developing a dedicated FA software tool. The discussion provides details of the specification, main features, and architecture of the system. This system has been rolled out at 15 labs and is used by approx. 500 analysts and several thousands of company-internal FA customers. The flexible architecture made the adaptation to all the different business processes possible and provides a future-proof solution.
Studies of Silicon Dust Corrosion on Microchip Al Bondpads and Elimination of Silicon Dust During Wafer Sawing Process
Authors: Younan Hua , Siping Zhao , Zhiqiang Mo , Ying Cho Jie
Published: December 2020

After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.
Accelerated Corrosion of Printed Circuit Boards Due to High Levels of Reduced Sulfur Gasses in Industrial Environments
Authors: Mazurkiewicz Paul
Published: December 2020

Accelerated corrosion leading to system failure has been observed on printed circuit boards present in industrial environments that contain abnormal levels of reduced sulfur gasses, such as hydrogen sulfide (H2S) and elemental sulfur. The problem is compounded by the fact that elemental sulfur is regulated by OSHA as a nuisance dust, and is allowed in a human working environment at the parts per thousand levels. Anecdotal data shows clearly that elemental sulfur gas present at the parts per million level can cause computer systems to fail within 2 months of use. Newer technologies such as immersion silver plating are especially susceptible to this type of corrosion. With the rapid growth of organically coated copper (OCC) and immersion silver platings, the number of failures due to reduced sulfur gasses in the environment has risen substantially.
Ion Beam Imaging Methodology of Invisible Metal under Insulator Using High Energy Electron Beam Charging
Authors: Wang C.H. , Chang S.P. , Chang C.F. , Chiou J.Y.
Published: December 2020

Focused ion beam (FIB) is a popular tool for physical failure analysis (FA), especially for circuit repair. FIB is especially useful on advanced technology where the FIB is used to modify the circuit for new layout verification or electrical measurement. The samples are prepared till inter-metal dielectric (IMD), then a hole is dug or a metal is deposited or oxide is deposited by FIB. A common assumption is made that metal under oxide can not be seen by FIB. But a metal ion image is desired for further action. Dual beam, FIB and Scanning Electron Microscope (SEM), tools have a special advantage. When switching back and forth from SEM to FIB the observation has been made that the metal lines can be imaged. The details of this technique will be discussed below.
Cross-Sectional Sample Preparation Techniques for 2D Doping Profiling of Specific Site by SCM
Authors: Lee Tae-Kwon , Back Tae-Sun , Kim Jong-Hyeop , Park Yoon-Baek , Kim Ho-Joung , Lee Soun-Young
Published: December 2020

Scanning capacitance microscopy (SCM) is an SPM technique which measures capacitance variation between tip and sample generated by applied AC bias while the tip is scanning in contact mode. Focused ion beam (FIB) milling is the more precise method to perform cross-sectioning of a specific site. The surface amorphization and charge trap layers formed during FIB machining affect the SCM dC/dV signal. This article demonstrates that micro-cleaving and FIB milling are capable of preparing a cross-sectional sample for 2D doping profiling of a specific site for SCM observation. Using the Micro-cleaving technique, a cross-sectional sample can be prepared easily with higher accuracy and shorter time than using a polishing method. However, Micro-cleaving can't be used by itself in the case of cross-sectioning a pattern formed by front end processing of sub-micron patterns. The FIB technique can assist the Micro-cleaving technique in cleaving of front end patterns.
Combining the Nano-Probing Technique with Mathematics to Model and Identify Non-Visual Failures
Authors: Shen Cha-Ming , Chuang Tsan-Chen , Lin Shi-Chen , Wen Lian-Fon , Huang Chen-May
Published: December 2020

In this paper, we focus on how to identify non-visual failures by way of electrical analysis because some special failures cannot be observed by SEM (scanning electron microscopy) or TEM (transmission electron microscopy) even when they are precisely located by other analytical instrumentation or are symptomatic of an authentic or single suspect. The methodology described here was developed to expand the capabilities of nano-probing via C-AFM (conductive atomic forced microscopy), which can acquire detailed electrical data, and combining the technique with reasoned simulation using various mathematic models emulating all of the significant failure characteristics. Finally, a case study is presented to verify that such defect modes can be identified even when general PFA (physical failure analysis) cannot be implemented for investigating non-visual failure mechanisms.
Fault Isolation of Soft P-N Junction Break Down Due to Plasma Charging
Authors: Nguyen Dat , Dudar Taras
Published: December 2020

The P-N junctions are part of the construction of semiconductor devices. They are formed by the combination of P-type and N-type diffusions. This paper discusses a soft (small early conduction) P-N junction breakdown. The P-N junction in this work is a part of a differential amplifier, which is widely used in analog/mixed signal devices. The paper outlines the test techniques to detect the differential amplifier failure, the circuit analysis (design and simulation), the fault isolation, and the root cause analysis with data from the wafer fabrication process to support plasma charging on the emitter. The real physical defect was not observable. However, with the help of lab data, the failure can be explained as plasma charging.
From Static to Full Dynamic Laser Stimulation
Authors: Deyine A. , Sanchez K. , Perdu P. , Battistella F. , Deslandes H. , Lewis D.
Published: December 2020

Limitations of backside optical techniques for failure analysis of dynamically activated devices have underlined the need to extend the capabilities of Dynamic Laser Stimulation techniques (DLS). DLS techniques provide a precise localization of the dynamically failing area, but it lacks timing information as the fault is often related to a specific test vector. Optical probing techniques such as TRE and LVP [1, 2] are hardly applicable on cases with long test loop and for which no preliminary information is available on the time window of interest. Defect localization and electrical tests can be coupled in order to provide more accurate information about the failure, especially vector information in addition to x and y localization. We have developed a Full Dynamic Laser Stimulation (F-DLS) approach based on laser modulation by electro optic modulator to face this challenge. The purpose of this paper is to present DLS limitations, our motivations, comparisons with other DLS extensions, FDLS implementation on our system, application example and future F-DLS developments.
Global Die Ultra-Thin Silicon for Backside Diagnostics and Circuit Edit
Authors: Scott Dane , O’Donnell Erin , Malik Tahir , Jain Rajesh
Published: December 2020

For more than 10 years, silicon thinning techniques have been relegated to an art form of mere necessity to enable complex optical probing and circuit edit analysis. Silicon thinning is a fundamental aspect of diagnostic analysis and while it is well-understood that limitations in the area of silicon thinning can severely limit high-quality diagnostic results, poor thinning results have generally been accepted as standard environmental operating conditions with which optical probe and circuit edit engineers must cope. Presented here is a scientific approach to thinning silicon to enable predictable high-precision, high-quality results. Remaining silicon thickness (RST) has been debated throughout the years because it was uncertain how much thinning was excessive. Primary perceived limitations included mechanical constraints (package / die warping) and post-thinning thermal control. Adding to the complexity of the discussion has been the fact that RST has been largely uncertain because analysis usually involved determining how much silicon was removed rather than how much silicon remains. All of these challenges have been overcome. A novel process has been developed to ultra-thin bulk Si to as low as 10um remaining Si thickness, eliminating the need for the Laser Chemical Etcher for circuit edit and improving optical emission probing considerably. This sample preparation process has been used on Intel Core2 Duo products with a success rate of 98%. Post FIB unit testing is a critical step in this debug process. A technique was developed to calibrate the change in thermal resistivity of the ultra-thin unit such that it will remain within 100ps of its original FMax performance in 90% of tests.
In Situ Removal of Polyimide Layer Using Modified Decapsulator
Authors: Ramachandra C. , Sweety B.M. , Chandan U.G. , Jaypal D. , Dash Sarat Kumar , Ravindra M. , Khan A.M.
Published: December 2020

Removal of polyimide layer after decapsulation of IC package is essential for many of the failure analysis techniques. An alternative method for polyimide removal is described in this paper. The method suggests appropriate modification of dual acid decapsulation system for this purpose. Device integrity is verified after removal of polyimide layer. This method becomes promising for devices which are sensitive / vulnerable for exposure to plasma.
Studies on a Qualification Method (OSAT) of Microchip Al Bondpads in Wafer Fabrication
Authors: Younan Hua , Ramesh Rao Nistala , Adrian Ng , Tony Tsai
Published: December 2020

Non-stick on pad (NSOP) is a yield limiting factor that can occur due to various reasons such as particle contamination, galvanic corrosion, Fluorine-induced corrosion, process anomalies, etc. The problem of NSOP can be mitigated through a careful process characterization and optimization. In this paper, a bondpad qualification methodology (OSAT) will be discussed. It will be argued that by employing different physical analysis techniques in a failure analysis of wafer fabrication, it is possible to perform comprehensive characterization studies of the Aluminum bondpad so as to develop a robust far backend of line process. A good quality Al bondpad must meet the following four conditions-OSAT: (i) it should be no discoloration (using Optical inspection); (ii) should be defect free (using SEM inspection); (iii) should be with low contamination level (such as fluorine and carbon contamination should be within a control limit) (using Auger analysis) and (iv) should have a protective layer on bondpad surface so as to prevent bondpad corrosion (using TEM).
Degradation Analysis of Thick Film Chip Resistors
Authors: Sood Bhanu , Das Diganta , Azarian Michael H. , Pecht Michael
Published: December 2020

Negative resistance drift in thick film chip resistors in high temperature and high humidity application conditions was investigated. This paper reports on the investigation of possible causes including formation of current leakage paths on the printed circuit board, delamination between the resistor protective coating and laser trim, and the possibility of silver migration or copper dendrite formation. Analysis was performed on a set of circuit boards exhibiting failures due to this phenomenon. Electrical tests after mechanical and chemical modifications showed that the drift was most likely caused by moisture ingress that created a conductive path across the laser trim.
Copper to Aluminum Bonding: IMC Characterization through New Mechanical Sectioning Methods
Authors: Copeland Lucas , Saran Mukul
Published: December 2020

This paper presents a mechanical cross-sectioning approach that produces an image clarity not yet demonstrated in published literature. It demonstrates how a critical sequence of polishing, basic slurry optimization and staining, in conjunction with correct imaging parameters can be used to highlight the growth morphology of the intermetallic compound (IMCs). Utilizing this approach, the paper describes the results of a SEM imaging study of the intermetallic formation and growth at the Cu-Al bond interface during thermal ageing for up to 4000hrs at 150 deg C. The paper uses direct SEM imaging to catalog observations which are used to create an initial model for IMC and void growth at the wire bonded interface. It examines the effect of aluminum splash and concludes that growth of intermetallics at the Cu-Al interface is rapid into the bond-pad aluminum than into the Cu-ball, but the growth thickness uniformity is much higher into the Cu-ball.
Timing Characterization of a Tester Operated Integrated Circuit by Continuous and Pulsed Laser Stimulation
Authors: Kiyan Tuba , Brillert Christof , Boit Christian
Published: December 2020

The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.
Fault Isolation on High Resistance Failure of 45nm ET Via Chains Using Combined Technique of SEM PVC and Nanoprobing
Authors: Tan P.K. , Mai Z.H. , Goh Y.W. , Zhu L. , Toh S.L. , Deng Q. , He R. , Tan H. , Li H.L. , Wang Q.F. , Ma Y.Z. , Lee W.Y. , Low G.R. , Lam Jeffrey
Published: December 2020

Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.
Neon Ion Microscope Nanomachining Considerations
Authors: Tan Shida , Livengood Richard H. , Hallstein Roy , Shima Darryl , Greenzweig Yuval , Notte John , McVey Shawn
Published: December 2020

Nanomachining capability scaling both in the areas of machining precision and novel gas chemistries are required for focused ion beam technology to keep pace with process technology advancement. In this paper, we review the nanomachining potential for the Helium Ion Microscope (HIM) and the Neon Ion Microscope (NIM). The paper also includes an in depth analysis of NIM imaging resolution, subsurface material interaction, and nanomachining performance.
Characterization of MOS Transistors Using Dynamic Backside Reflectance Modulation Technique
Authors: Teo J.K.J. , Chua C.M. , Koh L.S. , Phang J.C.H.
Published: December 2020

The channel of metal-oxide-semiconductor (MOS) transistors at different modes of operation has been characterized using dynamic backside laser reflectance modulation technique for different NMOS and PMOS transistors with different channel lengths. The reflectance modulations contain a primary peak near the drain-end when the MOS transistor is in saturation mode. Comparison studies with a Pseudo-Two-Dimensional analytical model support the hypothesis that the observed peak corresponds to the pinch-off point.
Infrared Thermography Developments for III-V Transistors and MMICs
Authors: Carisetti Dominique , Bouya Mohsine , Bezencenet Odile , Servet Bernard , Clément Jean-Claude , Lambert Benoit , Caille Laurent , Malbert Nathalie , Labat Nathalie
Published: December 2020

This paper focuses on infrared (IR) thermography capabilities on III-V components for thermal measurements applications and failure analysis (FA). The first part discusses the thermal mapping on InGaAs/AlGaAs PHEMT structure and compares IR thermal measurement with the well-known techniques as Raman and SThM. The second part discusses IR thermography on challenging FA for hot spot detection on the most popular type of capacitor for III-V MMICs as the metal-insulator-metal capacitor. It shows how IR thermography can easily localize very small pinholes in SiN, where liquid crystal and OBIRCH techniques are not well adapted.
Near-Infrared Photon Emission Spectroscopy Trends in Scaled SOI Technologies
Authors: Kindereit Ulrike , Weger Alan J. , Stellari Franco , Song Peilin , Deslandes Hervé , Lundquist Ted , Sabbineni Prasad
Published: December 2020

In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements.
Improving the DLS Workflow
Authors: Bodoh Dan , Erington Kent
Published: December 2020

In this paper, we describe improved hardware to connect a semiconductor tester or applications board to a laser scanning microscope (LSM) for performing dynamic laser stimulation (DLS). The hardware, called DXGlue, simplifies the DLS workflow and enables new applications. We describe its precise monitoring of the fail rate and fail mode, its use for time resolved DLS and the enabling of long test loops with short laser dwell times.
Time Resolved Imaging Solving FPGA Logic Fault Localization by Pattern Matching Technique
Authors: Bascoul G. , Perdu P. , Di Battista J.
Published: December 2020

From a designer point of view, the analysis of a failure root cause can quickly become a nightmare if the number of hypothesis provided by a simulation tool is too high. To help solving this kind of problem the use of physical probing measurement can reduce drastically the number of assumptions made by the simulation by invalidating certain hypotheses. The purpose of this paper is to add to the simulation a new source of information based on light emission to solve this kind of problem. Virtual logic diagram computation is able to provide several hypotheses of fault for a given node and data coming from Time Resolved Imaging (TRI) measurement allows extraction of transition pattern for a given node where the assumption has been established. The cross-referencing of this information aims at eliminating wrong hypotheses and making the simulation more reliable.
A Novel Integrated Reliability Test System for BEOL TDDB Study
Authors: Chen Jifeng , Song Peilin , Shaw Thomas M. , Stellari Franco , Gignac Lynne , Breslin Chris , Pfeiffer Dirk , Bonila Griselda
Published: December 2020

In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.
Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal
Authors: Lagar Jason H. , Sia Rudolf A.
Published: December 2020

Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.
Delay Fault Model Evaluation Using Tester Response Data
Authors: Xue Cheng , Blanton R. D. (Shawn)
Published: December 2020

Most chip producers perform delay testing to detect chips that are affected by defects that adversely affect timing. Several delay fault models have been introduced to guide delay test generation. But similar to static (i.e., slow speed) testing, there is always the question of which fault models are best for ensuring quality. MEasuring Test Effectiveness Regionally (METER) is an approach for evaluating fault model effectiveness. Compared to the conventional test experiment, METER is extremely inexpensive and provides a more thorough evaluation of the quality achievable by a particular fault model. In this work, we describe an extension to METER (called DELAY-METER) that allows the effectiveness of delay fault models to be precisely evaluated. Application of DELAY-METER to the production fail data from an IBM ASIC demonstrates that new and existing delay fault models can be evaluated using conventional tester response data, i.e., data logs collected from production fails through the application of tests generated using conventional fault models.
TEM/FIB Technical Solutions to Electron Beam Induced Radiation Damage to Low K/Ultra Low K Dielectrics in Semiconductor Failure Analysis
Authors: Binghai Liu , Ye Chen , Zhiqiang Mo , Ping Zhao Si , Yuin Wang Chue , Jili Wang
Published: December 2020

Electron-beam induced radiation damage can give rise to large structural collapse and deformation of low k and ultra low k IMD in semiconductor devices, posing great challenges for failure analysis by electron microscopes. Such radiation damage has been frequently observed during both sample preparation by dual-beam FIB and TEM imaging. To minimize radiation damage, in this work we performed systematic studies on every possible failure analysis step that could introduce radiation damage, i.e., pre-FIB sample preparation, FIB milling, and TEM imaging. Based on these studies, we utilized comprehensive technical solutions to radiation damage by each failure analysis step, i.e., low-dose/low-kV FIB and low-dose TEM techniques. We propose and utilize the low-dose TEM imaging techniques on conventional TEM tools without using low-dose imaging control interface/software. With these new methodologies or techniques, the electron-beam induced radiation damage to ultra low k IMD has been successfully minimized, and the combination of single-beam FIB milling and low-dose TEM imaging techniques can reduce structure collapse and shrinkage to almost zero.
Two Step Fabrication of Tungsten Nanotips by AC Electrochemical Etching and Laser Irradiation for Nanoprobing on Advanced Technology Nodes
Authors: Dawood M. K. , Ng T. H. , Tan H. , Tan P. K. , Oh C. K. , Lam J. , Mai Z.H.
Published: December 2020

Rapid technology scaling results in ever shrinking device size. As such, sharper nanotips are required for application in nanoprobing systems. In this work, we present a two-step methodology of fabricating tungsten nanotips with radius of curvature down to 20 nm by using and optimized AC electrochemical etching of tungsten in KOH followed by laser irradiation in KOH. Finally we show the application of the fabricated nanotips with different radius of curvature (ROC) for nanoprobing.
Effective Defect Localization on Nanoscale Short Failures
Authors: Huang Jiang , Sweeney Ryan , Dumas Laurent , Johnston Mark , Chen Pei-Yi , Russell Jeremy
Published: December 2020

This paper presents two case studies, based on 32nm Silicon-On-Insulator (SOI) and 28nm bulk Si technology, on finding the root cause of nanometer scale short failures using Passive Voltage Contrast (PVC), Active Voltage Contrast (AVC) and Transmission Electron Microscopy (TEM). PVC/AVC is used as precision localization technique that is critical for a successful FA-TEM analysis. Combining planar TEM sample preparation and high sensitivity Energy Dispersive Spectroscopy (EDS) mapping, a small residual filament, which is not visible even at high resolution TEM, is found to short two metal lines. The effective usage of voltage contrast and TEM provides the need of high throughput, high precision, and high resolution in the advanced FA lab that serves leading-edge semiconductor manufacturing.
AFM-Based Chemical and Mechanical Property Characterization of Interconnects and Defects
Authors: Lo Michael , Dillon Eoghan , Hu Qichi , Kjoller Kevin , Shetty Roshan , Prater Craig , King Sean W.
Published: December 2020

Spectroscopic characterization of interconnects and circuits in semiconductor devices has become increasingly complicated as dimensions for breakthroughs and failure analysis are continuously shrinking. To achieve high spatial resolution infrared (IR) spectroscopic information, a pulsed infrared laser can be coupled to an atomic force microscope in the atomic force microscopy IR (AFM-IR) technique. The combination of AFM-IR and Lorentz contact resonance AFM (LCR-AFM) has great potential for providing high spatial resolution chemical and mechanical analysis. To demonstrate the feasibility of the AFM-based techniques, AFM-IR spectrum and images were obtained from the interlayer dielectrics of a test structure at a length scale shorter than the IR wavelength. Using the LCR-AFM technique, the relative mechanical properties of the components could be mapped distinctively by observing the contact resonance of the AFM probe. Finally, preliminary data suggest there may be AFM-IR spectral differences between contamination and the bulk material on a liquid crystal display.
Nanoprobing as an Essential and Fast Methodology in Identification of Failure’s Root Cause for Advanced Technology
Authors: Ma Yinzhe , Oh Chong Khiam , Nyi Ohnmar , Zhang Chuan , Nedeau Donald , Lim Seng Keat , King Ming Chu
Published: December 2020

This paper highlights the use of nanoprobing as a crucial and fast methodology for failure analysis (FA) in sub 20nm with an improved semi-auto nanoprobing system. Nanoprobing has the capability to localize as well as characterize the electrical behavior of the malfunctioning device for a better understanding of the failure mechanism. It provides a valuable guide to choose a proper physical FA technique to identify the root cause of the failure. This established methodology helps to accelerate the FA turnaround time and improve the success rate. Its application to a few of the front end of line and one back end of line issues is highlighted in the paper.
Memory Scramble Verification by Frontside and Backside FIB Modification
Authors: Tsai Chun Ming , Huang Yi Shiuan , Lu Ya Hui , Chang Jian
Published: December 2020

Backside FIB circuit edit is an effective way to modify circuit on flip chip or stacked chips. Directly damaging memory cell through bulk silicon by FIB can be used to locate bit address to verify that the scramble test program coordinates correspond to the physical cell location. This paper presents the application of FIB for chip editing, discusses the limitation of the FIB approach and reports the scramble test experiments about the front-side and backside FIB technique to correct scramble testing data.