bluuebunny/crossref_metadata_2025 huggingface dataset:
Smart in-line defectivity/metrology process control solution for advanced 3D integration
Authors: Sidhoum Amina , Devanciard Nicolas , Bana Franck , Garnier Arnaud , Bresson Nicolas , Bos Sandra , Rey Stéphane , Beitia Carlos , Alliata Dario , Hart Darcy , Thornell John , Miller Justin , Vera Gilles , Balak Scott
Published: November 2016

When combined with in-line local metrology, Automatic Visual Inspection/Classification is a powerful tool to characterize 3D interconnect processes, either at the R&D level or in volume manufacturing environments. A new methodology that uses visual inspection results to drive local smart metrology was used for the first time to control the fabrication process of micro-pillar/micro-bump vertical contacts. Quantification of the inspection time when the smart logic concept was used revealed a throughput increase of 23% on average, while consistency of the automatic morphological accuracy was preserved as confirmed by in-line mechanical profilometry. The morphology characterization is discussed with respect to the electrical performances at die level.
Characterizing and solving imaging challenges in thick resists for wafer and panel based lithography applications
Authors: Webb James E. , McCleary Roger
Published: November 2016

Increasing volume using larger substrates with decreasing process margins continues to create new challenges for advanced packaging applications. Key step and repeat camera technology continues evolving for the mass production of microstructures used for 2.5D and 3D technologies. Printing dense arrays of smaller features with high aspect ratios requires higher sidewall angles in thick photoresists and polyimides. To help solve these imaging challenges we have leveraged resist modeling software and guided the adjustment of optical parameters needed for better performance. Higher contrast films have also been evaluated to help achieve the improvements in performance needed. Resist models that can include the effects of flare have been critical to understand the requirement for printing in thick negative resists and has aided in printing features on varying topography and film thicknesses. Special chucks help improve the flatness of warped wafers and real-time auto-focusing provides good image fidelity. Printing microstructures over larger formats with higher throughput has been accomplished using large magnification adjustment for improving overlay and validated by characterizing image placement errors over large substrates. Examples of resist models that are created using resist parameters and optimized using SEM images of printed features are compared. Extrapolations of the resist models have shown that guide improvements can be achieved by varying optical parameters. SEM images confirm that the modeled result of the optimal solution was achieved. Reduction in large substrate overlay error was achieved after the stage corrections were applied. Examples show that topographical errors of warped wafers can be reduced and how real-time auto-focusing for each exposure minimizes focus errors.
Ultra thin, low ESL and high frequency performance of high density silicon capacitors
Authors: Bunel Catherine , Murray Franck
Published: November 2016

The very high capacitance platform (now up to 900 nF/mm2) of the 3D Silicon capacitor technology presents many advantages for signal integrity, performance improvement, and miniaturization. In this paper, we will illustrate these advantages for communication infrastructure and high speed processors. The intrinsic IPDiA Silicon capacitors construction and the simplified equivalent electrical models will be compared with the multilayer ceramic capacitor (MLCC) model. We will also demonstrate how the Silicon capacitors are better candidates for performance, miniaturization and integration thanks to their low profile. The thickness has been a limiting factor for ceramic capacitors and we believe that Silicon capacitors will help to address this profile challenge. On top of the competitive overview of performances specific to the Ultra Wide Broadband Capacitors - like signal integrity, frequency response, linearity, and dielectric absorption - the additional Silicon capacitor technology benefits will be detailed. Design recommendations will be given to those who want to optimize performance. Perspectives and roadmap for the future will be disclosed.
Washable Coatings for Packaging Processes
Authors: Brewer Alex , Laymon Alex , Moore John
Published: November 2016

Many packaging processes require the protection of components while another application is conducted. This may include a planarizing coat over large topography while a deposition, bonding, or curing step is completed. Washable coatings are materials that protect the substrate during thermal or mechanical activities and are simply washed away using readily available and green products, such as water or detergent. Washable products are not new, an example includes laser washable coatings that remove debris from the heat activation zone (HAZ) during scribe and break processes. In such cases, thermal resistance is desired as high as possible. The chemistry of washable products includes polyvinyl alcohol (PVA) and polyvinylpyrrolidone (PVP) [1]. While these are excellent choices for consumer packaging (e.g. laundry packets, vitamins), they are best used in electronics for room temperature processing due to their cross-linking upon exposure to heat and metals. Alternatively, thermal resistant and washable products (e.g. DaeCoat™ 515) are available that provide protection to ≥300°C without the aid of mechanical tooling [2]. Planarizing coatings over metals can be thick (>300μm) as in cases where solder bump encapsulation is needed during dielectric coating and cure or when another die is thermal compression bonded. This approach has been demonstrated with washable temporary bonding adhesives in protecting C4 bumps while bonding micro-bumped die onto FPGA interposers [3]. Washable adhesives have been created for thermal and vacuum driven processing as EMI/RFI shielding in a PVD tool. Such coatings are applied to porous substrates, affixing die, processing, and removal by water washing [4]. Success in these and related temporary applications depend upon matching the chemistry of the washable coating with the process. Our experience in creating solutions for these and other industry needs will be discussed as well as the criteria for using temporary washable coatings.
Reliability of SAC 105 and SAC1205N under Drop Tests
Authors: Lan Jia-Shen , Fan Stuwart , Huang Louie , Wu Mei-Ling
Published: November 2016

In this paper, the solder joint failure and the solder joint fatigue life in the Thin-profile Fine-pitch Ball Grid Array (TFBGA) Package was investigated by performing the drop test, and implementing a simulation model. Owing to the need to meet the increasing demands for functionality, microelectronic package reliability can be compromised and has become the key issue when executing drop tests. During impact in drop test, the deformation of PCB due to bending and mechanical shocks can cause solder joint crack. While this is a well-known issue, observing the solder joint responses during the test execution can be a challenge. Therefore, in this work, a simulation model approach has been developed to investigate the stress and strain of the solder joint during the drop test. In this research, the JEDEC Condition B drop test was simulated, characterized by 1500G peak acceleration and 0.5 ms duration. The drop test simulation model was successful in predicting the solder joint fatigue life with different solder joint materials, such as SAC105 and SAC1205N, while also facilitating result comparison to identify the most optimal structure.
Package Architecture and Component Design for an Implantable Peripheral Nerve Stimulation and Recording System for Advanced Prosthetics
Authors: Bjune Caroline K. , Lachapelle John R. , Czarnecki Andrew , Kindle Alexander L. , Burns John R. , Segura Carlos A. , Grainger Julianne E. , Nugent Brian D. , Sriram Tirunelveli S. , Parks Philip D. , Keefer Edward , Cheng Jonathan
Published: November 2016

One of the limitation of current prosthetics is the ability to provide sensory feedback to the human user. Due to this constraint, approximately 60–80 percent of amputees experience a phenomenon known as phantom limb pain, an ongoing painful sensations that to the individual, seems to be coming from the part of the limb that is no longer there. The lack of sensory feedback also limits the intuitive control of the user's hand movement, i.e. sense of grip or position. To address these limitations, we created am implantable system that could provide peripheral nerve stimulation, recording and motor control. The architecture of our Sensory-Stimulation Lead (SSL) system consist of multiple satellites connected to Draper's custom designed nerve electrodes. In this phase of the design, the implanted system is connected to a controller via percutaneous connections. The active electronics of the satellite is enclosed in a hermetic package approximately 14mm in diameter and less than 5mm thick. A custom ceramic feedthrough substrate provides the electrical connections of the internal electronics board to both the nerve electrodes and percutaneous leads. In this paper, we will describe the various packaging components of the system and the design, fabrication, and assembly considerations that drove our technology choices.
Unique Silicon Passive Component Technology for Medical implants combining highly flexible integration with outstanding performances.
Authors: Bunel Catherine , Murray Franck
Published: November 2016

Many implantable medical devices such as pacemakers, cochlear implants and neurostimulation devices have been developed and tremendously improved in electrical power consumption, battery lifetime, functionality, system delivery, and wireless communication but there is still a lot of room for improvement and these devices are still facing challenges with size shrinkage and reliability. Many efforts have been engaged to miniaturize and to facilitate the implantation of the device in order to reduce the impact of the surgery. IPDiA's technology is strongly contributing to this progress by providing passive components such as capacitor arrays or RC networks, with a high contribution to miniaturization, a very low profile, extremely low leakage and outstanding reliability. In this paper, the enablers such as design flexibility, co-integration, low leakage, extended life time will be presented and illustrated by several examples of solutions. Firstly, the recent progress in the capacitor technology development will be presented, secondly the impact of the component technology on the overall system size and performances through advanced packaging solutions will be highlighted together with other key differentiators and finally some of the applications where this technology is essential will be presented.
Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnects
Authors: Spinella Laura , Im Jang-Hi , Ho Paul S. , Jiang Tengfei
Published: November 2016

Through-silicon vias (TSVs) are a crucial technology for enabling full three dimensional integration, yet they pose unique reliability risks, including thermal stress buildup due to the mismatch in the coefficient of thermal expansion between the silicon and the copper and the via extrusion phenomena. These effects can degrade device performance and it has been proposed that smaller TSV dimensions will reduce these reliability risks. In this paper, the correlation of shrinking dimensions to TSV stress and reliability is investigated, focusing on the effect of the microstructure on the plasticity and extrusion for 10, 5, and 2 μm diameter copper vias. Synchrotron x-ray microdiffraction revealed local plasticity concentrated in the tops of the vias of all diameters, and showed that the TSV stress behavior seemed to depend on the variations in the grain structure. Electron backscatter diffraction quantified the microstructure to show a tight distribution of grain sizes after the post-plating anneal, but further annealing to 400°C causes considerable data scatter for vias of all diameters. This result is consistent with the observed via extrusion statistics, in which the absolute values and variations in the extrusion heights increased significantly with further annealing. The wafer curvature technique is also used to observe the TSV stress relaxation behavior. Overall, these results suggest that scaling down TSV dimensions may not improve the stress and reliability behavior, particularly after further annealing at 400°C. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.
High Aspect Ratio Bumping Process with Solder Bumps Included Sintered Pillars
Authors: Nakagawa S. , Yasoshima T. , Uno H. , Ishikawa M.
Published: November 2016

This study provides new method for fine pitch bumping described as sintered pillar (SP) bumping method, which enables the formation of high aspect ratio bumps for stable assembly process. The SP bumps include sintered pillars formed by the transient liquid phase sintering process, and both SP bumps and sintered pillars are used with conventional paste printing process and equipment. By optimizing the sintered pillar paste, we achieved approximately 25% increase in bump height compared to those formed by the conventional paste printing process. We propose that the SP bumping method is one of the solutions for fine pitch bumping.
Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor
Authors: Castillou Paul , Gaddi Roberto , van Kampen Rob , Lin Yaojian , Jamshidi Babak , Yoon Seung Wook
Published: November 2016

The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as wafer level chip scale packaging (WLCSP) or fan-out wafer level packaging (FO-WLP) solutions such as embedded Wafer Level Ball Grid Array (eWLB) to meet these needs.

One of the most promising solutions to enable the required RF performance levels in mobile and wearable devices is the use of RF MEMS Tuners. Mobile original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally.

With RF MEMS technology now maturing, the biggest challenge to address the fast growing opportunity was to find a suitable packaging technology that can deliver RF MEMS tuners in the smallest possible form factor, while maintaining the excellent performance characteristics of the RF MEMS technology. After careful analysis, an eWLB/FO-WLP package was adopted and released to volume production in 2015. The commercial eWLB/FO-WLP RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions, resulting in much higher data rates (up to 2×) and improved battery life (up to 40%). Redistribution layers (RDL) in eWLB are utilized for higher electrical performance and complex routing to meet electrical requirements. The ability to utilize embedded passives in a multi-layer eWLB structure provides a number of advantages including cost reduction, footprint reduction and increased reliability. Inductors in eWLB offer significantly better performance compared to inductors in standard on-chip technologies.

In this paper, we examine the WLCSP and eWLB packaging assembly flow, solutions to RF design challenges as well as characterization of RF performance. Further improvement of the quality factor of the integrated inductor and capacitors by using low-loss thin-film dielectrics and molding compound in eWLB will be reported as well. Package level reliability test results will also be presented in this paper.
Optimization of laser release layer, glass carrier, and organic build-up layer to enable RDL-first fan-out wafer-level packaging
Authors: Lee Alvin , Su Jay , Huang Baron , Trichur Ram , Bai Dongshun , Liu Xiao , Shen Wen-Wei , Lin Yu-Min , Chang Tao-Chih , Chang Hsiang-Hung , Chiang Chia-Wei , Fu Huan-Chun , Chen K. C. , Lu Yu-Lan , Chen Kuan-Neng
Published: November 2016

With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP.

In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE).

An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.
Increasing the Reliability of 3D Printing a Wi-Fi Sensor Device
Authors: Deffenbaugh Paul I. , Stramel Danielle M. , Church Kenneth H.
Published: November 2016

Printed electronics and 3D printing have proved their viability for manufacturing functional devices. The state of the art is now at a crossroads where yield, reliability, survivability, and longevity improvements will govern its continued success in manufacturing. Currently, 3D printed electronics demonstration parts are either grossly oversized or are meticulously fabricated and involve significant human interaction and repair and ultimately have low manufacturing yield.

Presented here are techniques for improving manufacturing yield. Coefficient of thermal expansion (CTE) mismatch problems frequently occur in devices with heterogeneous materials such as bulk metals, thermoplastics, thermosets, conductive pastes and inks, and pourable dielectrics. Controlling the interfaces between these materials in new and creative ways is key to solving these problems during manufacturing and lifecycle. Selecting materials with good properties such as adhesion, surface energy, flexibility, conductivity, and dielectric properties is the path forward to excellence in this field.

Certain improvements in the design of 3D printed electronic devices (demonstrated here) show improved ruggedness. A long-lasting 3D printed electronic device that has been operating 24/7 for 21,000 hours is shown, and the techniques of its design and fabrication are described in detail. Several testing procedures evaluate the performance of the devices. Microscope photos show key problem areas, solutions are implemented, and material selections are presented. Overall device function is monitored wirelessly before, during, and after temperature changes.
Additive Printing of Tight Tolerance Embedded Components via High Precision Shadow Masking and Their Integration with Traditional Circuit Board Manufacturing
Authors: Heydemann V.D. , Lauer S. , Decker W. , Slater J. , Mazurowski J.
Published: November 2016

Most embedded components manufactured today are made either by photolithography to pattern inner board layer materials or by placing discrete components on an inner board layer followed by planarization with a potting compound. These traditional methods produce devices with poor tolerance due to inherent variances in the photolithography and etch process, and parasitic capacitance of long traces. Discrete embedded components increase thickness and weight and suffer from reduced reliability caused by the planarization process. This paper introduces an alternative patterning method to integrate in-line embedded passive and active components without photolithography processing. This additive printing process uses high precision, high feature density shadow masks with micrometer-level registration. Devices are built layer by layer using off-the-shelf bulk materials instead of inks to produce tight tolerance passive and active components that can be integrated into traditional PCB and wafer-level processing. Examples of such additively manufactured devices for both DC and RF applications and preliminary test data are presented in this paper.
Investigation of the Defect Size and Density in Thin SiON Filmfor Organic Device Encapsulation
Authors: Chu Kunmo , Bae Ki Deok , Song Byong Gwon , Park Yong Young , Kim Jaekwan , Xianyu Wenxu , Lee Chang Seung
Published: November 2016

In this study, thin SiON was grown by plasma enhanced chemical vapor deposited (PECVD) method as a thin-film encapsulation (TFE) layer. For defect visualization, electroplating results in a Cu bump grown at each defect site in the SiON film where electrolytic solution establishes contact with the Ni substrate. It was inferred that the Cu bump density could be representative of the intrinsic defect densities for the SiON film. The defect density values were obtained by monitoring the Cu bumps grown at defect sites in the SiON films and then evaluating the number of densities of the Cu bumps for the corresponding defect densities.At the same time, by analyzing the cross section of the Cu bumps grown on SiON film, a linear relation between the Cu bump diameter and the defect size increase was obtained. We expect that this electroplating method allows for rapid visualization of defect distribution and quality evaluation of TFE layers.
Fabrication and characterization of advanced through glass via interconnects
Authors: Clingenpeel Timothy , Rahimi Arian , Hwangbo Seahee , Yoon Yong-Kyu , Shorey Aric
Published: November 2016

This work presents the fabrication process, electrical characteristics, and circuit model of through glass via (TGV) structures consisting of TGV holes with each diameter of 100 μm and different conductors including copper and composite in the frequency range of 300 kHz to 20 GHz. The Cu/NiFe superlattice metaconductors in combination with high-quality glass (Corning SGW3) are intended to reduce radio-frequency losses especially in 10 GHz and above for next generation communication applications such as 5G communications. The measured results of the copper structure are compared to simulated results. Superlattice metaconductor results will be presented. Based on the simulation and measurement results, a circuit model is demonstrated.
Glass Based Inductors, Capacitors and System-In-Package for RF Applications
Authors: Flemming Jeb H , Cook Roger , McWethy Kyle
Published: November 2016

Glassy materials offer a number of advantages over traditional packaging materials, such as laminates and ceramics including: (1) Better material properties, (2) decreased surface roughness to mitigate current crowding, (3) the ability to create small precise features with greater densities, and (4) the opportunity to integrate passive devices such as power inductors and High-Q inductors into an interposer substrate along with other active and passive devices. This paper will cover an overview of our efforts to create APEX® Glass based devices that form the building blocks for a variety of RF applications including power inductors, High-Q inductors, capacitors, filters and interposers. We also demonstrate the power of integrating these individual building blocks into more complex devices that offer compelling solutions for the increasingly complex RF market. Performance data is presented for power inductors and the in-glass inductors.
Ultra-High Density System-in-Package (SiP) for the Lowest Size Weight and Power (SWAP)
Authors: Barbara Bruce
Published: November 2016

Fan out wafer level packages have emerged across the market in an effort to reduce size and weight of electronics used in portable and wearable applications in the commercial, industrial, and the hi-reliability products space. If it is not a stationary platform, weight and volume reduction are imperative. For the stationary platforms, size and power are most critical. Integration of multiple complex heterogeneous IC components can only be done if there are a sufficient number of interconnect layers. Additionally, multiple interconnects are needed for transmission line creation and shielding. This paper provides an introduction to Aurora Semiconductor's high density packaging technology i.e. iUHD (integrated Ultra High Density) and compares it with other alternative technologies. The Aurora iUHD technology is a 2.5D/3D FOWLCSP including embedded components, TSV, multi-layer top and bottom interconnects.
Assembly Equipment Requirements for Next Generation Advanced Packaging
Authors: Chylak Bob , Clauberg Horst , Strothmann Tom
Published: November 2016

Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options.

Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.
Pre-applied inter chip fill material for 3D chip stack integration – How to improve bonding quality and reliability
Authors: Takeshita Kan , Ikemoto Makoto , Sugiyama Masaya , Yamamoto Hidehiro , Kiritani Hideki , Shen Jun-Wei , Yuge Tetsuharu , Kodama Hiroya , Kawase Yasuhiro
Published: November 2016

Pre-applied underfill, which is also called inter chip fill (ICF), was developed for 2D and 3D chip stack integration. We prepared many types of formulations that have a variety of chemical and mechanical properties. Using these ICFs and test vehicles, we have conducted bonding tests and following thermal cycle tests. Reliability of joined chips was largely dependent on properties of ICF, particularly on curing speed. We also found that lowering modulus moderate delamination in some cases. Thermal stress simulation was also done for stacking chips with ICF. These experimental and calculated results give us an insight into how to develop highly reliable ICF.
Effect of Vapor-Deposited Parylene Coating on Reliability of Sintered Silver Joints for Extreme Temperature Applications
Authors: Shen Zhenzhen , Reiderman Aleksey
Published: November 2016

Silver nano-particle (AgNP) sintering has been extensively shown to be an excellent bonding method for use in the assembly of high-temperature multi-chip modules (MCM) rated above 200° C. Among the proven advantages of using this material in the assembly are the high mechanical strength of the attachment joints, resilience to thermal cycles, low resistivity, and high thermal conductivity. One of the concerns related to the reliability of sintered silver joints is silver migration. Another concern is the change in the joint's microstructure under thermal stress. Vapor-deposited high-temperature fluorinated parylene coating (Paralyne HT) may have the potential to mitigate those concerns because of its superior conformal and crevice-penetration properties. In this work, impact of Parylene HT on sintered silver joints has been evaluated from the perspective of mechanical strength. Test vehicles were subjected to thermal cycling and high-temperature aging. To understand the sintered silver joint's failure mechanisms, shear test analysis of the cross sections and fracture surfaces was performed. In addition, the effectiveness of Parylene HT as a coating to inhibit silver migration at high humidity was evaluated. Coated and uncoated sintered silver test patterns were stressed with an electrical field inside a high-humidity chamber. The silver migration progression was monitored and compared between coated and uncoated samples during the test.

One of the findings was that the coating material penetrates the pores of the sintered silver joints, altering their mechanical performance under thermal stress. Analysis of the performance differences between coated and uncoated test vehicles is presented in the paper.
Computer-Aided Predictive Reliability Risk Analysis for High-Temperature Operation of Subsurface Electronics Development
Authors: Liew Josh , Fanini Otto
Published: November 2016

The engineering task to design a highly reliable printed circuit board assembly (PCBA) that can withstand high temperatures and vibration stress is a challenge faced by all downhole electronics designers in the oil and gas industry today. Discussion will focus a comprehensive Design for Reliability (DfR) process flow based on complementary use of computer-aided design (CAD) tools. The DfR can enable analysis of the PCBA electrical, vibration and thermal stresses, service life prediction, mean time between failure (MTBF) and identify potential design errors for iterative reliability improvement on the schematic-level, early in the design cycle.

Stress analysis using CAD tools includes reliability risk assessment based on historical failures (i.e., engineering practice), detects uncertain design errors, and provides MTBF predictions and life predictions for the PCBA. This approach could improve PCBA performance and reliability by and reducing the product design cost and development time including the design qualification test. The process could accelerate the product development's time-to-market, increase customer satisfaction, and save product development costs.

This paper discusses a case study used to evaluate this CAD-based DfR methodology. The paper also describes how the methodology can be used to support durability analysis at the early design stage.
Electrical Characterization of Low-Profile Copper Foil for Reduced Surface Roughness Loss
Authors: Su Qianfei , Engin A. Ege , Aguirre Jerry
Published: November 2016

Signal attenuation in transmission lines is a major issue for reliable transmission in high frequency range. Knowledge of the electrical parameters of printed circuit board (PCB), including dielectric constant and loss tangent, is critical. Moreover, surface roughness has a great effect on loss in high frequency. This paper demonstrates an effective simulation fitting method for electrical material characterization. Cavity resonator is chosen as the circuit for characterization. A methodology is presented to measure surface roughness from cross sections, and compared with values extracted from resonator measurements. Several materials and copper foils treatments, including low-profile, are analyzed in this paper.
Proceedings of the XXXVI National Meeting of the Italian Society for the Study of Connective Tissues (SISC)
Authors: Antonio Rossi President:
Published: November 2016

Proceedings of the XXXVI National Meeting of the Italian Society for the Study of Connective Tissues (SISC)
Strict stoichiometric homeostasis of Cryptomonas pyrenoidifera (Cryptophyceae) in relation to N:P supply ratios
Authors: Ramos Rodríguez Eloísa , Pérez-Martínez Carmen , Conde-Porcuna José María
Published: November 2016

A common freshwater cryptophyte, Cryptomonas pyrenoidifera, was cultivated in batch-cultures to analyze intraspecific variation in elemental stoichiometry along a broad gradient of pulsed phosphorus (P) enrichment during the early acclimation period and to determine the immediate homeostatic capacity of the nitrogen-to-phosphorus (N:P) ratio of this alga when nutrients are at saturating levels. Experimental results revealed that nitrogen (N) and P cell quotas significantly increased with increasing P concentration. However, despite the wide range of N:P ratios in the medium, Cryptomonas N:P ratios were highly stable at higher P-level treatments, indicating a highly conservative behavior and suggesting strict elemental homeostasis when nutrients are at saturating levels. The strictly homeostatic N:P ratio appears to be attributable to their high potential for a fast luxury consumption of both N and P after a brief and intense episode of increased resource availability and to physiological limits on their nutrient storage capacity. Most importantly, the N:P biomass ratio at nutrient saturating levels converged around 11:1, which was the observed ratio of maximum internal cell quotas for N and P (i.e. Qmax,N:Qmax,P) under the prevailing experimental conditions. This value is particularly informative for C. pyrenoidifera because it represents cell storage quotients and may be a taxon-specific evolutionary optimum, providing a reference point to infer the grade of nutrient-limitation. The experimental data give ranges of variation in C. pyrenoidifera elemental composition permitting, among others, proper parameterization of cryptophyte stoichiometry models.
Is Using a Latrine “A Strange Thing To Do”? A Mixed-Methods Study of Sanitation Preference and Behaviors in Rural Ethiopia
Authors: Aiemjoy Kristen , Stoller Nicole E. , Gebresillasie Sintayehu , Shiferaw Ayalew , Tadesse Zerihun , Sewent Tegene , Ayele Bezuayehu , Chanyalew Melsew , Aragie Solomon , Callahan Kelly , Stewart Aisha , Emerson Paul M. , Lietman Thomas M. , Keenan Jeremy D. , Oldenburg Catherine E.
Published: November 2016

Latrines are the most basic form of improved sanitation and are a common public health intervention. Understanding motivations for building and using latrines can help develop effective, sustainable latrine promotion programs. We conducted a mixed-methods study of latrine use in the Amhara region of Ethiopia. We held 15 focus group discussions and surveyed 278 households in five communities. We used the Integrated Behavioral Model for Water, Sanitation, and Hygiene interventions to guide our qualitative analysis. Seventy-one percent of households had a latrine, but coverage varied greatly across communities. Higher household income was not associated with latrine use (odds ratio [OR] = 1.9; 95% confidence interval [CI] = 0.5, 7.7); similarly, cost and availability of materials were not discussed as barriers to latrine use in the focus groups. Male-headed households were more likely to use latrines than households with female heads (OR = 3.5; 95% CI = 1.6, 7.7), and households with children in school were more likely to use latrines than households without children in school (OR = 2.3; 95% CI = 1.6, 3.3). These quantitative findings were confirmed in focus groups, where participants discussed how children relay health messages from school. Participants discussed how women prefer not to use latrines, often finding them strange or even scary. These findings are useful for public health implementation; they imply that community-level drivers are important predictors of household latrine use and that cost is not a significant barrier. These findings confirm that school-aged children may be effective conduits of health messages and suggest that latrines can be better marketed and designed for women.
From the archaeological record to archaeobim: the case study of the Etruscan temple of Uni in Marzabotto
Authors: Garagnani Simone , Gaucci Andrea , Gruška Bojana
Published: November 2016

The digital reconstruction of the recently discovered Tuscanic temple of Uni in Marzabotto gave the chance to test the application of the Building Information Modeling (BIM) process to the combined fields of Archaeology and Engineering. In addition to the traditional historic and archaeological analysis, a new methodology in Experimental Archaeology is proposed; it proved to be original and innovative in the examination of the buried building, taking advantage of technologies focused on the architectural reliability validated by inferred digital models. The peculiar aspect of the research involves the elements at the beginning of the process, which consist of foundations or negative archaeological evidences only, supported by the clues and the rules that can be found in the historic and scientific literature. To better define this distinctive working process, the expression ArchaeoBIM was proposed, which highlights the common BIM matrix used for the data management through one or more analytical models, applied to the peculiar aspects of the Archaeological discipline.
Development of a platform recommending 3D and spectral digitisation strategies
Authors: Wefers Stefanie , Karmacharya Ashish , Boochs Frank
Published: November 2016

Spatial and spectral recording of cultural heritage objects is a complex task including data acquisition, processing and analysis involving different technical disciplines. Additionally, the development of a suitable digitisation strategy satisfying the expectations of the humanities experts needs an interdisciplinary dialogue often suffering from misunderstanding and knowledge gaps on both the technical and humanities sides.

Through a concerted discussion experts from the cultural heritage and technical domains currently develop a so-called COSCHKR platform (Colour and Space in Cultural Heritage Knowledge Representation) which will give recommendations for spatial and spectral recording strategies adapted to the needs of the cultural heritage application. The platform will make use of an ontology through which the relevant parameters of the different domains involved in the recording, processing, analysis and dissemination of cultural heritage objects are hierarchically structured and are related through rule-based dependencies. Background and basis for this ontology is the fact that a deterministic relation exists between (1) the requirements of a cultural heritage application on spatial, spectral, as well as visual digital information of a cultural heritage object which itself has concrete physical characteristics and (2) the technical possibilities of the spectral and spatial recording devices. Through a case study which deals with the deformation analysis of wooden samples of cultural heritage artefacts this deterministic relationship is illustrated explaining the overall structure and development of the ontology.

The aim of the COSCHKR platform is to support cultural heritage experts finding the best suitable recording strategy for their often unique physical cultural heritage object and research question. The platform will support them and will make them aware of the relevant parameters and limitations of the recording strategy with respect to the characteristics of the cultural heritage object, external influences, application, recording devices, and data.
Algunos apuntes sobre la digitalización y la reconstrucción virtual del Castro de San Chuis (Allande, Asturias, España)
Authors: Molina Salido Juana , Jordá Pardo Jesús F.
Published: November 2016

With the firm conviction that current archaeology needs to use all the tools that computer science provides, we have developed a project for digitising and structuring all the information gathered from the different excavation campaigns carried out in San Chuis hillfort (Allande, Asturias, Spain).  In order to do it, we have developed the Spatial Data Infrastructure (SDI) of the hillfort, in order to proceed subsequently to its virtualization. To implement the SDI, we have reinstated the archaeological record in its original coordinates based on the information that we had. This restitution has allowed us to perform the spatial analysis of the elements of the record, to elaborate different plans of its distribution, not only campaigns but also types, and perform at the same time, a study of the densities.  Likewise, we have developed a general database of the hillfort, in which, aside of including the detailed table of the elements of the record and their coordinates, also contains the descriptive table of the stratigraphic units (SU) and the descriptive table of the wall stratigraphic units (WSU).  Finally, we have built an extensive planimetry and a web page in order to spread the information. With regard to the hillfort virtualization, we have developed two consistent models with two historical stages: the Iron Age and the Roman occupation. We have used Blender for its development.
Unveiling Damnatio Memoriae. The use of 3D digital technologies for the virtual reconstruction of archaeological finds and artefacts
Authors: Manferdini Anna Maria , Gasperoni Sofia , Guidi Federica , Marchesi Marinella
Published: November 2016

In ancient Rome, damnatio memoriae was a practice of erasing the memory of condemned persons from historical records after their death. This practice was usually addressed by the Senate to Roman elites and emperors who were declared enemies of the State, in order to preserve the honour of Rome. This condemnation usually included practices such as, for example, the erasure of names sculpted on inscriptions and the destruction or reworking of statues and of any other image of the person. Emperor Nero, for example, was condemned to this practice immediately after his death and a wide iconographic repertoire on him was therefore destroyed or deeply damaged.  This lack of information can actually be improved thanks to the possibilities of virtual restoration and reconstruction offered by 3D digital technologies.

The aim of this paper is to show how the possibility to acquire 3D reality-based data from archaeological finds allows to build 3D digital models that can be analysed and managed in a virtual environment and can be relocated, assembled or restored in order to suggest or graphically support archaeologists’ interpretations and reconstructions. The paper shows the methodology developed for the virtual restoration of the statue of Nero starting from the 3D digitization of the torso that was found 500 years ago by the Roman theatre of Bologna, Italy, the ancient Bononia.
3D visualization tools to explore ancient architectures in South America
Authors: Pierdicca Roberto , Malinverni Eva Savina , Frontoni Emanuele , Colosi Francesca , Orazi Roberto
Published: November 2016

Chan Chan is a wide archaeological site located in Peru. Its knowledge is limited to the visit of Palacio Tschudi, the only restored up to now, whilst the majority of the site remains unknown to the visitors. The reasons are manifold. The site is very large and difficult to visit. Some well-conserved architectures, such as Huaca Arco Iris, are very far from the core centre. Furthermore, there are heavy factors of decay, mainly caused by illegal excavations, by marine salt and by the devastating phenomenon of El Niño. For these reasons, the majority of the decorative elements are protected by new mud brick walls. Finally, the vastness of the buildings makes difficult to understand their real value, even through a direct visit of the site. In order to overcome the aforesaid problems, we designed, developed and realized the museum exhibition presented in this paper. We named Esquina Multimedia an installation where every corner is aimed to solve a specific problem, providing the tourists with interactive and enjoyable applications.  The virtual tour allows reaching also the unreachable areas. An Augmented Reality (AR) application has been developed in order to show ancient artefacts covered by the earth.  A web-browser has been specifically designed to show bas-reliefs, with HD visualization, anaglyph stereoscopic view and a 3D virtual model of both the structures and the bas-reliefs. At the same time, a wall-mounted panel representing a metric 3D reconstruction of the building helps the user to find the artefact position.  Descriptions of the hardware components and of the software details are presented, with particular focus regarding the implementation of the application, arguing how the digital approach could represent the only answer towards a full exploitation of archaeological sites. The paper also deals with the implementation of a web tool, specifically designed to display and browse 3D-Models.