Addressing the Defects within the Gate Oxide and at the Gate Oxide/Si Interface in Linear and Two-Dimensional Quantum Dot Arrays in Silicon
Authors: Karwal Saurabh , Michalak David J , Amitonov Sergey V , Tryputen Larysa , Sammak Amir , Meyer Marcel , Unseld Florian K , Déprez Corentin C , Meijer Ilja , Abswoude Timo R. van , Vandersypen Lieven M.K. , Scappucci Giordano , Veldhorst Menno , Hanfoug Rabah 
Published: December 2024

Some performance indicators of quantum computers can be traced back to the chip design and quality of materials comprising the quantum devices. Quantum states are fragile and may lose their state due to decoherence caused by a noisy environment [1,2,3]. Therefore, in addition to the growth of low-defect and low-disorder materials, reliable device fabrication with controlled densities of charge centers within the gate oxide and at the gate oxide/Si interface are also required.

In this work, we report on state-of-the-art fabrication methods of linear and two-dimensional quantum dot array devices that are defined in isotopically purified in-house grown 28Si/SiGe heterostructures. Specifically, the two-dimensional quantum dot array devices presents a promising way forward for scaling up spin qubits, as such a device architecture allows for tunnel coupling between two adjacent quantum dots in two-dimensions [4]. However, scalable quantum processor might require the use of shared plunger and barrier gates, as demonstrated in the Ge/SiGe material platform [5], which entails a very high level of device uniformity in terms of potential landscape and associated control voltages required per qubit. Here, we report on electrical tuning of plunger gates performed in linear quantum dot array devices in order to achieve higher degree of electrical uniformity, thereby significantly reducing variations in the turn-on voltages [6]. Furthermore, following a similar electrical tuning procedure for plunger gates in a 2×2 two-dimensional quantum dot array devices enabled the realization of (1,1,1,1) charge state when all the plunger gates are set to 1 V, which may relax the requirements on control electronics and operations for spin qubit devices, as previously mentioned [7].

In parallel to electrical tuning of the quantum dots, the electrical quality and defect densities of the gate dielectric and its interface with the semiconductor heterostructure are being studied for correlation with electrical tuning ability as well as device drift, jumps, and charge noise [8,9]. Specifically, we measure capacitance-voltage (CV), conductance-voltage (GV), and capacitance-time (C-t) data at room temperature on test structure devices in order to distinguish between mobile charge defects (Qm
), interface trap defects (Dit
), oxide fixed charge (Qf
) and dielectric non-linearities. As the next step, we are working to characterize the activities of these defects down to cryogenic temperatures and ultimately control their densities for optimal device performance.

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[3] Wuetz et al., arXiv: arXiv:2209.07242.

[4] Vandersypen et al., npj Quantum Inf 3, 34 (2017).

[5] Borsoi et al., Nature Nanotech 19, 21 (2024).

[6] Meyer et al., Nano Letters 23, 2522 (2023).

[7] Meyer et al., Nano Letters 23, 11593 (2024).

[8] Wuetz et al., Nat Comms 14, 1385 (2023).

[9] Esposti et al., npj Quantum Info 10, 32 (2024).