bluuebunny/crossref_metadata_2025 huggingface dataset:
Public Policies Impact on Third Sector Social Enterprises in UK Regions
Authors: Maher Chi
Published: November 2015

This chapter provides an important perspective on how public policies impact small third sector social enterprises in UK regions. There is limited research that has explored the how government policies are impacting on small regional drug and alcohol social enterprises. The research employed a multiple case study design (Stake, 2006; Yin, 2009).of eight small drug and alcohol third sector social enterprise organisations based in three UK regions (The East Midlands, The South East (including London) and Yorkshire and Humber). Semi-structured interviews were conducted Chief Executive Officers (CEOs) of these organisations to ascertain how government policy framework influences their service developments. The research finding contributes to the fairly limited empirical research investigating regional variations of third sector social enterprises. It advocates for changes in government regional funding polices help small third sector social enterprises to develop and sustain appropriate effective services where they are based – at the regional level.
Connecting Social Enterprise and Higher Education
Authors: Calvo Sara
Published: November 2015

Despite the increased attention paid to enterprise and entrepreneurship education in recent years, there exist limited bodies of research on the extent to which higher education institutions support and promote social enterprises. This chapter addresses this by drawing on previous research concerning enterprise and entrepreneurship education in universities and their role as drivers in bringing social change and improvement in individuals and the wider society. This chapter provides many examples of social enterprise curricular and co-curricular programmes in higher education institutions in the United Kingdom and concludes with a discussion of the opportunities and challenges of universities supporting social enterprise initiatives with a roadmap for future research directions.
An Innovation Ecosystem beyond the Triple Helix Model
Authors: Ferraris Alberto , Leucci Stefano , Bresciani Stefano , Giunchiglia Fausto
Published: November 2015

In the current global scenario, the relevance and the importance of social innovation becomes critical in order to face this situation of crisis. For its close link with the local area in which it takes place, social innovation is deeply rooted in the overall system, and thus involves the action of many different actors. The aim of this chapter is to highlight the presence of a new managerial model that is more suitable to promote social innovation within an ecosystem. This analysis has been developed focusing on a new and innovative framework, the Social Innovation Pyramid, and on the Trentino's ecosystem based in North-East of Italy.
The Drive towards Near Zero Energy Buildings through Professional Training in Southern Europe
Authors: Amorim Filipa , Gomes Ricardo , Dao Hang , Carvalho Miguel , Silva Carlos , Ferrão Paulo , Guedes Manuel Correia , Almeida Manuela
Published: November 2015

This chapter gives an overall summary of the challenges faced by European countries regarding the adoption of nZEBs, particularly focusing in the training needs in the Southern Mediterranean countries, and on the experience reached so far by the ongoing SouthZEB Project. Therefore, it first elaborates on the nZEB concept definition framework focusing on the relevance of the topic to local and regional development purposes. Secondly, the chapter gives an overview of the definitions that may be used to the adoption of nZEB across European countries. The perspective presented is first through a top-down approach, based on the policy implementation efforts developed by the European Commission and, after that, based on a bottom-up perspective, including an overview of existent voluntary standards that may be regarded as contributing to the adoption of near zero energy buildings. Thirdly, the chapter reflects on some of the barriers encountered that hamper nZEB adoption, specifically addressing the need for professional training in Southern European countries. Finally, the methodology used by the SouthZEB Project to define the training and certification needs, which is based on the participatory process, is presented along with an overview of the project major results achieved until now and the main difficulties identified so far.
Searching for Opportunities and Trust in International Markets
Authors: Carvalheira Alexandra Marisa Bastos , Moreira António
Published: November 2015

Internationalization has been adopted by many companies, regardless of size, to boost their growth. Although the Uppsala model and the network approach have been extensively used to analyze how small firms internationalize their operations, this chapter addresses how a small firm of the clean carpentry industry managed to overcome an economic slowdown of its domestic market and boosted its growth. This chapter uses a case study approach that is framed on a literature review covering internationalization of SMEs, entrepreneurship, the importance of the network approach, the search of opportunities and trust, and relationship orientation to show how a firm abandoned its passive behavior and its focus on the domestic market to proactively address the international market following an entrepreneurial perspective.
Entrepreneurship and Innovation
Authors: Gonçalves Maria Ortelinda Barros , Remoaldo Paula Cristina , da Cunha Paulo J. A. , Silva Nair
Published: November 2015

For countries like Portugal, with limited prospects in terms of employment, one of the solutions involves emigration and the desire of part of the Portuguese people to establish enterprises in other countries, England being one of the most favoured. Taking into account these premises, and in the scope of a broader research on the Portuguese Emigrant Entrepreneurship in Andorra, London, Nice and Monaco, we carried out a questionnaire to 51 Portuguese entrepreneurs living in London, within several economic sectors, between 2013 and 2014. Our main goals were to know the profile of Portuguese immigrant entrepreneurs in London, the reasons for their emigration, the need or opportunity for entrepreneurship, the types and areas of activity of their businesses, the obstacles they had to deal with and the possibility for them to return to Portugal. The novelty of our research lies in the study of the ethnic and economic emigration of Portuguese emigrants in London, a study that was under-researched and under-analysed to this date.
Networks Collaboration in Wine Sector SME
Authors: Lima Maria João Sousa , Carvalho Luísa Cagica
Published: November 2015

Collaboration between companies, especially for SMEs, can increase their ability to compete in new global markets. The emergence of new wine-producing countries over recent decades allows to evaluate its impact on the performance of a collaborative supply chain in countries with wine production tradition. This chapter describes the collaboration in the interface wine-grower/wine maker in a Portuguese wine region (Setúbal Peninsula). It reveal that intensification of collaboration between wine companies could increase their competitiveness in the domestic and the international markets, due the benefits it endorses. It also exposes some factors that stand out as conditioners to the operationalization of a deep collaboration, restricting it to just a few activities. The results of a case study performed suggested that the wine industry structure and the product characteristics are factors that negatively influence the intensity and the extension of collaboration. Trust is the intangible element that stands out as critical to the intensity of collaboration.
Best Practices in Social Media for Knowledge Management
Authors: Iyer M. K. Prasanna
Published: November 2015

The spirit of Social Media is in community building, and they have enriched the practice of Knowledge Management in very exciting ways. CoPs and Forums are ideal platforms to share experiences and lessons learnt. Communities are extremely valuable because of their informal, just-in-time, increasingly real-time advantage and cannot be replaced by structured KM platforms. It is this aspect of communities, that new Social Media enhances, in spirit as well as in tools support. Social Media provides multiple user-friendly tools to make it easy to share experiences and Lessons Learnt as they happen, as well as in a curated form. Best practices developed by this author and other practitioners are presented, so that other communities can benefit from them. Cases and anecdotes from organizations across industry sectors enliven the discussions. Emerging trends and innovative use of Social Media, are introduced as benchmarks.
Social Media as Elements of Shared Workspaces
Authors: Focardi Giulio , Salati Lorenza Victoria
Published: November 2015

Shared workplaces are becoming very common within Europe. Multifactories are shared working environment that combine traits of a Coworking Space, a Fab Lab and a Makerspace. One of the traits that characterize a Multifactory is how knowledge exchange brings to innovation. This chapter has its focus on a case study that shows how a traditional SME and a multifactory can work together in order to develop an innovative idea and how Social Media can be parts of an overall strategy set to product innovation.
Innovation Landscape Idea to Product Development
Authors: Goel Alok Kumar , Singhal Puja
Published: November 2015

This study seeks to address various phases, challenges and the principles influencing transforming an idea into a product innovation. This study is particularly relevant in light of the driving role given to small scale enterprises by the supporting policies and practices in the process of transforming India into an innovation-oriented nation and leading ‘Make in India' program. Based on a multi-disciplinary the framework discussed in this study highlights a number of internal processes and external network attributes, their interactions and moderating relationships as related to their impact on Indian small scale enterprises' product innovation capabilities. This study offers an overview of the factors that affect product innovation capabilities, with particular reference to entrepreneurial orientation of Indian Small and Medium Enterprises (SMEs). This study showcase provocative views that considers the concept of innovation ecosystem and new product development central to its philosophy and objectives.
Explaining Young Consumers' Online Purchase Behavior under Risky Conditions
Authors: Bulut Zeki Atıl , Karabulut Ali Naci , Uysal Tuğba Uçma , Uzun Ali Çağlar
Published: November 2015

As the internet becomes a new shopping channel, which threats traditional shopping, it also causes dramatic changes in consumer market. In the light of theories claiming that consumers act with limited rationality and make their preferences with the motive of avoiding loss, the main aim of this study is to measure the impact of loss variables on the consumers' decisions about online shopping in Turkey. The originality of this study is to categorise and analyse loss variables as ‘the ones that happen in the process of shopping' and ‘the ones that happen out of the process of shopping'. Following the literature stating that consumers tend to act irrationally, the study also concludes that consumers tend to be away from the economical rationality at a great extent under the loss conditions. The findings show that any type of loss either physically or mentally related to consumers' shopping has an effect on consumers' irrational behaviors. This study indicates that this effect is higher in the conditions of loss in the process of shopping than out of the process of shopping.
A TXV-less Packaging Platform for the Era of IoTs
Authors: Hu Dyi-Chung , Lin Yu-Min , Chang Hsiang Hung , Chang Tao-Chih , Lo Wei-Chung , Yang Chih-Kung , Yang Henry , Hung Yin-Po , Chen Yu-Hua , Tain Ra-Min
Published: November 2015

A new concept of packaging platform calls eHDF (embedded high density film), that without any TXVs is been proposed. The eHDF uses the technology from two categories; one utilize the semiconductor fine line technology infrastructure and the other takes the advantage of laminate organic large panel process infrastructure. Hence, the fine line, better electrical performance and low cost requirements can be addressed at the same time by the eHDF packaging platform.

In this paper, a test vehicle based on eHDF structure will be built and modules assembly with test chips on eHDF substrate will be performed.
Smart PCBs for Smart Appliances - Embedding as IoT Enabler
Authors: Renaud-Bezot Nick , Galler Christian , Vockenberger Christian
Published: November 2015

Be it the trillion-dollar economy dreamed up by Cisco Systems at one extreme, or the multitude of small crowdsourced projects at the other, there is no denying that IoT is capturing minds and making the news. Each company is vying for a piece of the pie, with semiconductor suppliers scrambling to call the latest releases “IoT-ready”.

Not wanting to feel left out, the PCB industry is of course finding ways to support this nascent economy. As main concerns are small sizes, low energy consumption and short cycle times, one solution is embedding. By placing active and passive components within the PCB itself, the system can:- be more integrated, as components disappear from the surface, making space for additional functionality, larger battery or simply fit in a smaller housing,- have lower losses, as stacking SMT components on top of the embedded allows for short connections, thus lowering resistance and inductance,- be created faster, to enable dimensional and functional integration without relying on complex and costly SoC design.

Starting with a backgrounder on common embedding technologies currently available from leading suppliers, the paper will present recent advances from AT&S's ECP® (Embedded-Component Packaging), including reliability data. Expanding from that field, the document will explore its future and extreme applications, such as high-power (multi-kW) and fine-pitch fields for industrial and automotive devices, showing the scalability of the technology and the evolutions supported by the EU-funded EmPower and UNSETH projects.
Quantitative Projections of the Cost Benefits of 3D Integration
Authors: Beece Adam , Milojevic Dragomir , van der Plas Geert , Augur Rod , Sureddin Michelle , Singh Jagar , Senapati Biswanath , Bouche Guillaume , Alapati Ramakanth , Stephens Jason , Lin Irene , Rashed Mahbub , Yuan Lu , Kye Jongwook , Woo Youngtag , Wehbi Ali , Hang Peter , Ton-That Van , Kanagala Vijay , Yu Donald , Gao Shan , Samavedam Srikant
Published: November 2015

The traditional drivers for the adoption of 3D integration technology are footprint, power, performance, and/or bandwidth gains at the expense of increased cost due to additional wafer processing, dies stacking and 3D test. However, for larger dies in cutting edge technology, total system cost can be reduced by leveraging heterogeneous 3D stacking, if it is done correctly. This paper presents a model which allows comparing the cost of moving a traditionally designed chip at given advanced node (in 2D) to an implementation in the next generation technology node using heterogeneous face-to-face 3D stacking. With this model we show that 3D integration scheme can be driven by cost savings. This is possible in a world where CMOS cost per transistor continues to improve because other components that are required in large SoCs, notably analog and I/O functionality, do not. The proposed model is used to evaluate the cost impact of iterating a 14nm SoC into a 10nm SoC (traditional scaling) compared to a 3D implementation that pulls the analog and I/O circuitry into a cheap 28nm top die. The cost impact of such a transition is evaluated for different starting SoC sizes (from 100 to 400mm2), differing area percentages of analog I/O (15–40% of the total 2D area), different increases in complexity (measured in implicit number of transistors). In the most realistic and representative cases studied, 28–10nm heterogeneous 3D stack reduced large-die package cost from 5% to 10%. Sensitivity analysis to various model parameters show that these savings are fairly robust, persisting through various scenarios unfavorable to this integration technique.
2.5D Interposers and Advanced Organic Substrates Landscape: Technology and Market Trends
Authors: Ivankovic A. , Buisson T. , Kumar S. , Pizzagalli A. , Azemar J. , Beica R.
Published: November 2015

This work focuses on the analysis of recent developments and future trends of organic substrates and 2.5D interposers. In the sub 10 μm line/width space, substrate manufacturers are pushing towards traditionally foundry level Si processing dimensions. Latest R&D shows organic substrates with L/S capability down to 2/2 μm. Organic substrates and 2.5D interposers can be in many cases separated in two different groups, however certain solutions propose a combination of the two, such as embedded interposers or fine extension layers of organic substrates acting as interposers. These substrate and interposer architectural solutions are analyzed. Furthermore, organic processing options and latest feature sizes are discussed. Dielectric build up material options with low dielectric constant (Dk) and low tangent loss (Df) are analyzed and their expected thermo-mechanical property trends presented, including the coefficient of thermal expansion (CTE), Young's modulus (E) and glass transition temperature (Tg). Coreless substrates and their advantages, disadvantages, industry readiness and future development are also addressed. Furthermore, 2.5D interposer options are analyzed by type of material: Si, glass and organic. A qualitative and quantitative comparison of their features and market status is done and their future development is extrapolated. Final conclusions are made on the sub 10 μm line/width advanced substrate application space and the market interaction of organic substrates and 2.5D interposers
Fan-in WLP: Technology and Market Trends
Authors: Ivankovic A. , Buisson T. , Kumar S. , Pizzagalli A. , Azemar J. , Beica R.
Published: November 2015

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile.

In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.
Evaluation about Solder-IMC Crack of Fine Pitch BGA Package
Authors: Kang Taeho , Lee Ara , Jeong Jaewoo , Kwak Dongok
Published: November 2015

FBGA is widely adopted as AP and memory package for mobile devices such as a smart phone and a smart watch. FBGA is attached to PCB assembly during SMT process. Double side SMT is preferred to increase the battery area for slim design and long life of mobile device. Solder-IMC crack is in-process reliability failure occurs during 2nd side SMT. The buried via is often used in double side SMT PCB is filled with filler material of CTE is highly mismatched to surrounding PCB laminates (FR-4). Tensile stress is applied to BGA pad by this CTE mismatch at high temperature and causes the solder-IMC crack. In this paper, we evaluate the factors of solder-IMC crack related to PCB and BGA. It is found that the length of buried via related to PCB thickness influences the solder-IMC crack. But if the location of buried via is not aligned to the location of BGA pad, solder-IMC crack does not occur. In the case of buried via and BGA pad are aligned each other, the failure rate of solder-IMC crack can be lowered by controlling O2 level that is less than 1000ppm and by applying solderball with high Ag content for SAC alloy. The temperature cracking solder-IMC interface is measured. The result shows that the solder-IMC crack occurs before solder joints are fully melted. The solder joint with low Ag content having broad melting temperature range is relatively weaker than high Ag having near eutectic point. It is recommended to design the PCB with buried via which avoids the location of the BGA pad and this is the good solution to reduce the failure rate of solder-IMC crack to near zero.
Mechanical testing and fracture analyses of miniaturized ZnO-based multilayer components
Authors: Macurova K. , Gruber M. , Pletz M. , Supancic P. , Danzer R. , Aldrian F. , Bermejo R.
Published: November 2015

Functional components are commonly fabricated combining a ceramic substrate with external and/or internal metallization (e.g. metal electrodes, vias, contact pads, etc.) using a tape casting process. Different layers are printed and/or fired (e.g. up to 800°C) onto the ceramic part to provide the component with a (certain) functionality. As a result of the combination of different materials (e.g. ceramic, glass, metal alloys) with different coefficients of thermal expansion, internal stresses may arise during the different fabrication steps. Although some of these tensile residual stresses may relax due to plastic deformation of metallic materials, stress concentrations generated in material junctions or terminations (imposed by geometrical constrains) may lead to cracks and/or reduce the component strength.

In this work different architectures combining metal and glass layers on the surface of ZnO substrates were investigated experimentally and numerically in order to identify weak points in commercial components. Mechanical testing using three-point-bending was performed on samples taken after different steps. A FE model was developed to (i) calculate residual stresses generated during the manufacturing process, and (ii) simulate the propagation of initial crack/defect during manufacturing. Experimental results were compared with numerical predictions. These results in combination with fractographic analyses were used to validate the finite element model in order to assess location of failure.
A New Package for High Speed and High Density eStorage Using the Frequency Boosting Chip
Authors: Kim Geukchan , Kim Hyejin , Chun Sunghoon
Published: November 2015

A die-stacking technology in a multi-chip package can effectively increase the capacity. However, long wire bonding for multi-chip stack, inter-symbol interference caused by large capacitive loading and I/O speed degradations due to simultaneous switching noise (SSN) and power consumption have become obstacles to optimize the internal NAND flash interface. In this paper, to overcome the inevitable challenge between larger storage capacity and higher I/O speed, we propose a new package structure with a frequency boosting interface chip (FBI-chip) for high speed and high density eStorage.
Bonding Technologies for 3D integration
Authors: Lohse Sascha , Wollanke Alexander
Published: November 2015

Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packaging. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands. Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging. In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 μm) and small bump diameter (down to 13 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.
A Case Study of Ultra-Leach Resistant Thick Film Conductors for Non-Magnetic Applications
Authors: Silvia John J. B.
Published: November 2015

Today, designers of SMT electronics are being asked to achieve more while designing around new technical constraints. Many times these constraints force designers to sacrifice commercial advantages of their designs in order to achieve performance goals or vice-versa. This is made worse when industries and regulations impose restrictions on materials such as lead free, high temperature processing, low-PIM or non-magnetic requirements. Often, the choice comes down to either using high performance components that are expensive and sensitive to processing or robust components that either offer reduced performance or are restricted for use due to material content. This is especially true of surface-mount technology components common to electronics manufacturing where solder processing requirements are found.

While typical Ag/Pt thick film conductors are a perfect choice for sensitive applications requiring robust processing, they cannot match processing parameters similar to very high leaching resistant materials like nickel barrier. Since nickel barrier is inherently ferro-resonant, some applications cannot be realized without a new material approach.

Components manufactured for use in these sensitive, yet demanding applications have now been produced using an Ultra Leach Resistant (ULR) processing of Ag/Pt thick film. The performance of components produced using this ULR material and process have been evaluated for survivability in solder environments to study the resistance to leaching compared to nickel barrier and traditional “leach resistant” materials available today. The results indicate that it is possible to achieve nickel-barrier-like results without ferro-resonant properties using a “ULR” material and process.
Enhanced Mpilog macromodels for Signal and Power Integrity Simulations
Authors: Signorini Gianni , Siviero Claudio , Stievano Igor Simone , Grivet-Talocia Stefano
Published: November 2015

Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.).

In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations.

This work summarizes the recent enhancements of “Mpilog”-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The static parts are extracted via nested DC sweeps simulations and reproduced by tensor representations obtained via high-order singular value decomposition (SVD) processes. The dynamic components are described by linear state-space models identified from device's transient responses to suitable stimuli. For transmitters, the weighting functions match the output-port transitions and the dynamic supply-current profiles, capturing also the dependency of switching delays upon supply-voltage fluctuations; this is a key feature that enables Mpilog macromodels to precisely reproduce simultaneous-switching-noise (SSN) effects in complex system-level SI&PI simulations. The macromodels can be readily synthesized as SPICE netlists (including resistors, capacitors and controlled-sources) or Verilog-A codes; this allows their use in any SPICE-type electrical solver.

Several examples of realistic SI&PI simulations for single-ended and differential interfaces are presented. Transistor-level simulations are compared with the corresponding ones based on Mpilog-macromodels: the resulting accuracy and the speed-up factors are extensively discussed. Comparisons with state-of-the-art legacy models (IBIS) are also discussed.
Line coding methods for high speed serial links
Authors: Goulahsen Abdelaziz , Saadé Julien , Pétrot Frédéric
Published: November 2015

A line coding for high speed serial transmission is defined by two major characteristics: the maximum guaranteed run length (RL) which is the number of consecutive identical bits, and the running disparity (RD or DC-Balance) which is the difference between the number of 'zeroes' and 'ones' in a frame. Both should be bounded to a certain limit, RL to ensure reliable clock recovery and RD to limit baseline wander. Another important parameter is the overhead predictability. This parameter may be critical for applications that need a regular synchronization but for other applications, especially if the variable transfer rate is handled by the upper layer protocol, a statistical value of this parameter is good enough. In this paper, we propose two programmable line codings which bound RL and RD with fixed or variable overhead. The resulting overhead for the line coding we propose is shown to be the lowest among the existing methods, as much as to 10 times lower than well-known encoding methods. The fixed overhead line coding is based on a generalization of the polarity bit approach and can be dynamically adapted to link quality and the environment. First we propose a line coding which bounds the RL, and then we propose another one which bounds the RD. We end up by combining both methods to build a DC-balanced and Run Length limited line coding.
Optimizing Diamond Heat Spreaders for Thermal Management of Hotspots for GaN Devices
Authors: Obeloer Thomas , Bolliger Bruce , Han Yong , Lau Boon Long , Tang Gongyue , Zhang Xiaowu
Published: November 2015

As devices become smaller while still requiring high reliability in the presence of extreme power densities, new thermal management solutions are needed. Nowhere is this more evident than with the use of Gallium Nitride (GaN) transistors, where engineers struggle with the thermal barriers limiting the ability to achieve the intrinsic performance potential of GaN semiconductor devices.

Emerging as a common solution to this GaN thermal management challenge are metallized diamond heat spreaders. In this paper, a diamond heat spreader has been applied with a hybrid Si micro-cooler for to cool GaN devices. Several different grades and thicknesses of microwave CVD diamond heat spreaders, as well as various bonding layers, are characterized for their thermal effects. The heat spreader is bonded through a TCB (thermal compression bonding) process to a Si thermal test chip designed to mimic the hotspots of 8 GaN units. The heat dissipation capabilities were compared through experimental tests and fluid-solid coupling simulations, both showing consistent results. In one configuration, using a diamond heat spreader 400μm thick with a thermal conductivity > 2000W/mK, to dissipate 70W heating power, the maximum chip temperature can be reduced by 40.4%, for test chips 100μm thick. And 10kW/cm2 hotspot heat flux can be dissipated while maintaining the maximum hotspot temperature under 160°C. The concentrated heat flux has been effectively reduced by the diamond heat spreader, and much better cooling capability of the Si micro-cooler has been achieved for high power GaN devices.
Pressure-less AgNP Sintering for High-power MCM Assembly for Extreme Environment Applications
Authors: Shen Zhenzhen , Reiderman Aleksey , Anude Casey
Published: November 2015

Silver nano-particle (AgNP) sintering has been a promising bonding material for high-temperature applications. There is an increasing demand for designs implemented as multi-chip module (MCM) in the high-temperature markets, like the oil and gas industry, primarily because of MCM's smaller size, higher-performance capability, and higher overall reliability when compared to traditional high Tg printed circuit boards.

In this work, pressure-less AgNP sintering paste was used in the assembly of multi-chip modules. The assemblies included die-mounted on aluminum nitride and alumina substrates that were metallized with various thin and thick films. Sintered silver nano-particle attachments were also attempted for surface-mounted technology (SMT) chip components. Different assembly parameters such as bonding line thickness and sintering profiles were evaluated to discover the optimal assembly process window that would yield acceptable reliability for 250°C and higher ambient temperature applications. The assemblies were subjected to various tests including thermal cycling, high-ramp rate thermal shocks, and high-temperature storage tests. Shear strength measurements and analysis of the cross sections and fracture surfaces were performed to understand failure mechanisms.

One of the findings was a certain and unique failure mode associated with bonding of thin-film gold metallized surfaces using pressure-less silver nano-particles sintering. That failure mode begins after a short exposure to temperatures of 200°C and higher. However, silver nano-particle sintering on substrates metallized with thin-film silver and some thick-film formulations yields dramatically better results.
High Thermal Stability of SiC Packaging with Sintered Ag Paste Die-attach combined with Imide-based Molding
Authors: Nagao Shijo , Sugioka Takuo , Ogawa Satoshi , Fujibayashi Teruhisa , Hao Zhang , Suganuma Katsuaki
Published: November 2015

We report that ultra-high thermal reliability can be achieved by combining Ag paste sintering die-attach and injection transfer molding with imide-based mold composite. Test specimens of SiC SBD in TO247 discrete-package are prepared; SiC dies bonded on Cu lead frame, Al ribbon wiring from electrode of SiC Schottky barrier diode (SBD) chip to the Cu leads, and injection transfer molding process. The hybrid nano+micro flake Ag paste realizes a low temperature bond process of 250°C in air, die-shear stress recorded 23 MPa without intensive pressure. The thermo-mechanical parameters like glass transition temperature, Young's modulus and CTE of the thermosetting composite are carefully tuned for both the manufacturing process targeting the device operating temperature of 250°C. The test pieces are tested by harsh thermal cycling between −50°C to 250°C, and compared with the other specimens made with usual Pb-5Sn soldering die-attach with the same molding composite. Interface failures are investigated by scanning acoustic tomography (SAT), and the electric properties of SBD are checked by I-V measurements. The sintered Ag die-attach survived over 500 cycles without any failures around the interfaces of SiC die, Cu lead-frame, and mold materials, and no obvious change is found in electronic properties. However, Pb-Sn die-attach joints are gradually damaged with increasing thermal cycles causing degraded I-V property. The SEM images indicate the microstucture of sintered Ag layer is unchanged after the thermal cycles, because of the impregnated imid-matrix into the porous Ag. Our results demonstrate that the combination of Ag sinter paste die-attach and imide-based thermosetting composite can be a massproduction-ready packaging technology to realize the high operation temperature of post-silicon power devices.
Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers
Authors: Sawyer Brett , Suzuki Yuya , Wu Zihan , Lu Hao , Sundaram Venky , Panayappan Kadappan , Tummala Rao
Published: November 2015

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.
Through Glass Via (TGV) Technology for RF Applications
Authors: Shorey A. B. , Kuramochi S. , Yun C. H.
Published: November 2015

Over the past several years there have been substantial advancements in through glass via (TGV) technology. There is an excellent opportunity to leverage TGV technology and the insulating properties of glass, to address next generation needs for RF components. Multi-bands multi-standards with carrier aggregation and WiFi and GPS coexistence make RF front end more and more complicated. In order to address the best-fit filtering solutions to RF front end, high-performance inductors and capacitors are required. For inductors, drastic performance improvement in terms of size and quality factor has been demonstrated by technology evolutions from 2D planar inductors to 3D solenoid using TGV. On top of the TGV inductors, we have successfully integrated Cu MIM (metal-insulator-metal) capacitors by using 15um thick Cu plates and a Si-N dielectric layer.
Understanding the Role of Ultrasonic Welding in Wire Bonding
Authors: Levine Lee
Published: November 2015

Wire bonding is the dominant chip interconnection method. Ultrasonic energy is the most important bonding parameter effecting the quality and the reliability of the intermetallic weld. Understanding the mechanism enabling weld formation is a key factor in maintaining the reliability and productivity that wire bonding provides.
Large Scale Photodesmear for Via Residue Cleaning in High Density Interconnect substrates
Authors: Habu Tomoyuki , Namai Masahito , Aiba Akira , Kikuiri Hajime , Maruyama Shun , Horibe Hiroki , Suzuki Hiroko , Endo Shinichi , Fujinami Toru , Yabu Shintaro , Jain Rahul , Darmawikarta Kristof , Obrien Michael
Published: November 2015

Smear residue from the build-up dielectric material is left at the bottom of the microvia after laser drill process which, if not cleaned, poses risk to the electrical functionality of the device. Thus, microvia cleanliness is the key to a reliable and electrically functional device. Currently, industry employs a wet process to clean the etch residue that results in significant chemical waste. Here, we evaluated an alternative, but effective Photodesmear method that provides a low cost of ownership and almost negligible environmental impact. We have demonstrated in IMAPS 2013 that this process can achieve residue- and silica filler free via bottoms by a two-step process: i) illuminating 172 nm vacuum ultraviolet light (VUV) on the panels, resulting in a photochemical ashing, and ii) a water clean. This process does not reduce the surface energy of the build-up material, thus not impacting the downstream processes.

The main technical challenge in developing Photodesmear technology will be panel level uniformity in cleaning all the microvias within the same process step. We have demonstrated that our process can achieve a highly uniform treatment over 510 mm wide panels. The process was optimized to clean microvias with a range of aspect ratios on insulating film (material N) drilled by CO2 laser. The microvia bottoms were also found to be clean when the vias were drilled by UV laser to test the desmear capability.

The quality of the Photodesmear was tested by measuring the peel strength between electrolytically plated Cu and dielectric surface, and by performing the quick via pull (QVP) to verify the failing interface. We found high peel strength of 0.7 kgf/cm when sputtered Cu seed layer was used. QVP experiments confirmed that the via residue is cleaned effectively since the interface between the plated Cu and the underlying Cu pad did not fail. This study shows that Photodesmear process is capable to produce clean vias along with acceptable peel strength. Future issues are to research the reliability, productivity, and cost of the Photodesmear process to compare with the existing process.
Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains
Authors: Gaudestad J. , Orozco A. , De Wolf I. , Wang T. , Webers T. , Kelley R. , Morrison T. , Madala S.
Published: November 2015

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).
Thermally Conductive Plastics for Enhanced Thermal Management
Authors: Raman Chandrashekar
Published: November 2015

Electronic devices continue to shrink while continuing to offer increasing functionality. This trend poses a significant challenge to design engineers who need to adequately address the increasing thermal management requirements of these devices on a shrinking footprint. Thermally conductive plastics have been gaining attention as an innovative new material option to address this challenge. While plastics are typically poor conductors of heat, it is possible to increase the thermal conductivity with the use of certain additives. Unique ceramic additives like boron nitride offer the added advantage of enabling thermally conductive plastic formulations that are also electrically insulating. The replacement of aluminum heat sinks in free (natural) convection environments with thermally conductive plastics is discussed in this paper. The results show it may indeed be possible to replace aluminum with thermally conductive plastic heat sinks in convection limited environments, and if judicious redesign of the plastic heat sink is incorporated, an improved thermal management solution can be realized. Additionally, the benefits of enhancing existing plastic housings to enable an improved thermal management solution are discussed. The results also show that modest enhancements to the thermal conductivity of existing plastic housings can yield significant improvements to the overall thermal management solution as well.
Thromboembolic and hemorrhagic risk stratification in patients with atrial fibrillation. Part II: hemorrhagic risk and guidelines recommendations
Authors: Abrignani Maurizio Giuseppe , Abrignani Vincenzo
Published: November 2015

Robust evidence exists on the efficacy of traditional anticoagulant oral therapy in the prevention of thrombo-embolic risk in patients with non valvular atrial fibrillation, but fears and concerns of hemorrhagic events for the physicians and logistic difficulties related to the periodic International Normalized Ratio evaluation for the patients are at the basis of a noticeable under-utilization of the therapy with vitamin K antagonists in the real world. Stratification of the hemorrhagic risk has, thus, particular importance; for this objective we may use now several score system, among whom the more suggested is the HASBLED, with the principal aim to select and trait modifiable risk factors for bleeding. These score systems have been evaluated in some recent clinical trials. During the last years, a number of national and international guidelines on the prevention of the thrombo-embolic risk in patients with non valvular atrial fibrillation have been updated. These guidelines, generally, recommend the use of the CHA2DS2VaSC score for the evaluation of the thrombo-embolick risk, and of the HAS-BLED score for the evaluation of the hemorrhagic one. The consequent risk stratification is fundamental as a clinical guide for the use of oral anticoagulant therapy.
Thrombus straddling a patent foramen ovale
Authors: Prota Costantina , Citro Rodolfo , Silverio Angelo , Ascoli Roberto , Naddeo Corrado , Vitale Giovanni , Piscione Federico
Published: November 2015

We present a case of a 67-year-old male with pulmonary embolism. Transesophageal echocardiography (TEE) showed the presence of a mobile thrombus straddling the patent foramen ovale (PFO) and prolapsing into both atria. Treatment with heparin was started. Five days after admission, repeat TEE revealed a reduction in thrombus dimensions, so anticoagulation therapy was continued. Eleven days after admission, TEE showed complete disappearance of the thrombus.