Investigation of the Low Temperature / High Temperature Approach to Produce Si0.5Ge0.5 and Pure Ge Strain Relaxed Buffers
Authors: Hartmann Jean-Michel , Aubin Joris , Bogumilowicz Yann , Delaye Vincent , Papon Anne-Marie 
Published: February 2020

Several microns thick, constant composition SiGe layers (with Ge contents typically in the 20% to 50% range) grown directly on Si(001), with sometimes thick Ge layers on top, are coming back in force as the core materials of mid and long infra-red waveguides. The impact of growth parameters and thickness on surface roughness, degree of strain relaxation and threading dislocations density (TDD) are not that well known, however. SiGe Virtual Substrates (VS), with several microns thick SiGe graded layers capped by constant composition layers or pure Ge grown directly on Si(001) are indeed preferentially used as templates for sSi layers, donors for GeOI fabrication or active media in near IR photo-detectors.

We have thus explored whether or not the Low Temperature / High Temperature (LT/HT) approach (+ Thermal Cycling) used for pure Ge growth on Si yielded high quality Si0.5Ge0.5 Strain-Relaxed Buffers (SRBs) that could serve afterwards as templates for thick Ge layers. To that end, we have grown various thickness Si0.48Ge0.52 layers at 550°C, 20 Torr and with a SiH4 + GeH4 chemistry, in order to have a satisfying Growth Rate (GR = 48 nm min.-1) at such a low temperature. As soon as those layers were relaxed (88% for 380 nm), the growth temperature was increased to 850°C and Si0.50Ge0.50 layers grown on top thanks to SiH2Cl2 + GeH4 (GR = 151 nm min.-1at 20 Torr). As soon as the 1.7 µm thick Si0.5Ge0.5 SRBs were completed, a 3 x (850°C, 10s / 975°C, 10s) TC was used to minimize defect density. Then, the growth temperature was reduced to 400°C and 130 nm of pure Ge grown at 100 Torr thanks to GeH4 (GR = 17 nm min.-1). The growth temperature was then ramped up to 750°C (and the growth pressure down to 20 Torr) and various thickness Ge layers grown on top (GR = 55 nm min.-1) until 1.3 µm was reached. Finally, another 3 x (750°C, 10s / 875°C, 10s) TC was used to minimize defect density and smoothen the surface.

20 µm x 20 µm Atomic Force Microscopy (AFM) images of the surfaces of our stacks at various stages of their completion can be found in Figure 1. Omega-2Theta scans around the (004) X-Ray Diffraction order for the same samples are provided in Figure 2, together with a (004) Reciprocal Space Map of a whole {1.7 µm thick Si0.5Ge0.5 SRB / 1.3 µm Ge} stack with the 2 aforementioned TCs. What is easily seen is that the surface of the Si0.48Ge0.52 layers is rough. The spatial wavelength of that roughness increases when the Si0.50Ge0.50 HT layer thickness increases and when a TC is used. The surface morphology definitely changes when Ge is added, first at LT then at HT. Large diameter hills are then formed and a cross-hatch appears when a TC is used. We have plotted in Figure 3 the surface root mean square roughness and the macroscopic degree of strain relaxation associated with our stacks as a function of the SiGe + Ge thickness, in order to see what is happening. We have, as soon as the Si0.48Ge0.52 layers plastically relax, a surface roughening which is not recovered by the HT growth of Si0.5Ge0.5 (rms roughness: 5 nm). Adding Ge @ LT roughens the surface even more. Thickening it with Ge @ HT and using a TC yields a slight surface roughness decrease, however (down to 3.5 nm). Those roughness values are in-between those associated with cross-hatched Si0.5Ge0.5 VS (12 nm) and pure Ge layers (1 nm). What is also noticeable is that the HT Si0.5Ge0.5and pure Ge layers are slightly tensily strained. This is due to thermal expansion coefficient differences between Si and SiGe (Ge) which come into play during the cooling-down to room temperature.

We have otherwise used the Ayers theory (J. Cryst. Growth 125 (1992) 329) in order to convert the full widths at half maximum of SiGe and Ge omega scans (from XRD RSMs) into actual TDDs. We would then have, for 60° misfit dislocations in our stacks, the following values: 6.0x108 cm-2 (3.5x108 cm-2) in as-grown (annealed) 1.7 µm thick Si0.5Ge0.5 SRBs and 2.8x108 cm-2 (1.6x108 cm-2) in as-grown (annealed) 1.3 µm thick Ge layers on top. Those values are definitely higher than those in 1.4 µm thick, cyclically annealed pure Ge layers grown directly on Si (3.8x107 cm-2) and in ~ 6 µm thick Si0.5Ge0.5 VS (2x105 cm-2). Plane view and cross-sectional Transmission Electron Microscopy is underway to confirm those TDDs.

Figure 1