bluuebunny/crossref_metadata_2025 huggingface dataset:
Selective Epitaxial Growth with Full Control of Pattern Dependency Behavior for pMOSFET Structures
Authors: Kolahdouz Mohammadreza , Hallstedt Julius , Ostling Mikael , Wise Rick , Radamson Henry H.
Published: October 2008

This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in pMOSFET structures. The pattern dependency behavior of the growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by gas depletion theory of the growth species in the stationary boundary layer over the wafer. The control of SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.
Evaluation of DiMethylAminoGermaniumTetraChloride as a novel Carbon-Dopant and Germanium Precursor for Germanium and Silicon Germanium Chemical Vapor Deposition
Authors: Leys Frederik E. , Liu Cong , Shi Xiaoping , Lamare Bruno , Takeuchi Shotaro , Schaekers Marc , Loo Roger , Woelk Egbert , Caymax Matty
Published: October 2008

DiMethylAminoGermaniumTriChloride (DiMAGeCl) is evaluated as a C-dopant source for selective SiGe and Ge epitaxy using Chemical Vapor Deposition. We determine the C-level as a function of temperature and pressure and we examine the applicability of DiMAGeCl for the growth of high quality Ge on Si.
Polarity Change of Threshold Voltage Shifts for n-channel Polycrystalline Silicon Thin-Film Transistors Stressed by Negative Gate Bias
Authors: Huang Ching-Fang , Yang Ying-Jhe , Peng Cheng-Yi , Sun Hung-Chang , Liu Chee Wee , Hsu Yuan-Chun , Shih Ching-Chien , Chen Jim-Shone
Published: October 2008

The negative bias instability on p-channel and n-channel polycrystalline silicon thin-film transistor is investigated. Negative threshold voltage shift is observed in p-channel TFTs and is attributed to the positively charged donor type interface traps. On the other hand, polarity change of threshold voltage shift is observed in n-channel TFTs, suggesting two competing mechanisms. Negatively charged acceptor type interface traps are the dominant factor for the positive threshold voltage shift. As the gate stress voltage increases, accumulated holes are trapped in the insulator via Fowler-Nordheim tunneling and are responsible for the negative threshold voltage shift. The stress-induced hump effect is attributed to higher electric filed at the edge transistors as compared to channel transistor along the channel width direction.
Hole Mobilities of Si0.6Ge0.4 Quantum Well Buried-Channel Field Effect Transistors on SOI
Authors: Fujinaga Kiyohisa
Published: October 2008

This report describes the ivestigation of the electronic properties for the single and multiple quantum well devices with the Ge composition of 20 % and 40 % fabricated on SOI. The single quantum well device with the 40 % Ge-composition showd that the highest hole mobility below the effctive electric field bellow -0.7 MV/cm. The mobilities of the multiple quantum well devices were inferior to those of the devices with the Ge composition of 20 %. This was due to that the increase of Ge composition caused three-dimensional growth in forming well layer, which resulted in the reduction of the well layers and interfaces quality.
Asymmetric Energy Distribution of Interface Traps in Germanium MOSFETs with HfO2 Gate Dielectric
Authors: Xie Ruilong , Wu Nan , Shen Chen , Zhu Chunxiang
Published: October 2008

In this work, a simple model, with a higher interface trap density in the upper half of Ge bandgap than that in the lower half, is proposed to explain the abnormal behaviors in Capacitance-Voltage characteristics of both p- and n-MOS capacitors on Ge substrate using different surface passivation. Variable rise/fall-time charging pumping measurement is used to study the energy distribution of interface trap density in HfO2 gated Ge MOSFETs. Our results reveal that Dit is higher in the upper half of the Ge bandgap than that in the lower half of the bandgap. These results are also consistent with the observation that n-channel mobility is more severely degraded compared to p-channel for Ge MOSFET.
Silicon Nanomembranes Incorporating Mixed Crystal Orientations
Authors: Scott Shelley A. , Paskiewicz Deborah M. , Savage Donald E. , Lagally Max G.
Published: October 2008

We present a method for fabricating hybrid-orientation surfaces composed of regions of single-crystal Si(001) and Si(110), with the potential for transfer to foreign surfaces, providing a material suitable for high-performance CMOS devices on a variety of host substrates.
Formation of SiGe Quasi-Single Crystal Grain on Insulator by Indentation-Induced Solid-Phase Crystallization
Authors: Sadoh Taizoh , Toko Kaoru , Miyao Masanobu
Published: October 2008

Formation of SiGe quasi-single crystal grains on insulator by the indentation-induced solid-phase crystallization has been investigated. The incubation time for nucleation was significantly reduced by the indentation. As a result, large (~2um) crystal grains were realized at controlled positions for samples with all Ge fractions. This method is expected to be useful for realization of the 3D-ULSIs and system-in-displays.
Reliability of Ti-based Gate Dielectrics on strained-Si0.91Ge0.09 and Ge under Dynamic and AC Stressing
Authors: Mahata C. , Bera Milan K. , Bose P.K. , Maiti C.K.
Published: October 2008

The trapped charge distributions in Al/TiO2/GeOxNy/p-Ge and Al/ TiO2/SiOxNy/strained-Si0.91Ge0.09 structures subjected dynamic stress of different amplitude and frequency in order to analyze the transient response and the degradation of the oxide as a function of different stress condition. The current transients and voltage transient observed in dynamic voltage (-4V to -9V) and current stresses (-2.5mA/cm2 to -12.5mA/cm2) have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar voltage stresses shows the degradation being much faster at low frequencies than at high frequencies.
Chemical Mechanical Polishing of Epitaxial Germanium on SiO2-patterned Si(001) Substrates
Authors: Hydrick Jennifer M. , Park Ji-soo , Bai Jie , Major Cheryl , Curtin Michael , Fiorenza James G. , Carroll Mark , Lochtefeld Anthony
Published: October 2008

Aspect Ratio Trapping is a promising technique for heterointegration of Ge onto Si substrates. By growing Ge in patterned SiO2 trenches, lattice-mismatch dislocations arising from the epitaxial interface can be effectively trapped. However, planarization of these samples is required to enable device fabrication. This paper describes the development and optimization of a chemical mechanical polishing process for these structures. Polishing using diluted Nalco 2360 slurry was investigated, with the addition of NaOCl, NH4OH, or H2O2, for Ge removal rate increase. A slurry mix consisting of Nalco 2360, H2O2, and DI water was shown to have low dishing and low surface metals contamination, and planarized the Ge Aspect Ratio Trapping samples very effectively.
Micro-Raman Studies on Nickel Germanides Formed on (110) Crystalline Ge
Authors: Peng Cheng-Yi , Huang Ching-Fang , Yang Ying-Jhe , Liu Chee Wee
Published: October 2008

Nickel germanides formed on crystalline n-Ge (110) substrate are investigated. By the XRD analysis, Ni5Ge3, NiGe, and Ni2Ge phases are formed sequentially with the increasing annealing temperatures from 300oC to 600oC on n-Ge (110) substrate. NiGe, however, is the only phase observed on (100) substrate at corresponded annealing temperatures. On the other hand, there shows a strong tensile stress in the underlying Ge (110) substrate. The tensile strain may be due to the lattice mismatch between nickel germanides and Ge substrate.
Nucleation Control for High Density Formation of Si-based Quantum Dots on Ultrathin SiO2
Authors: Makihara Katsunori , Kawanami Akira , Ikeda Mitsuhisa , Higashi Seiichiro , Miyazaki S.
Published: October 2008

We have demonstrated that the Si nucleation density can be controlled over ~1011cm-2 by changing the conditions of GeH4-exposure treatments just before Si2H6-LPCVD such as the GeH4 pressure, exposure time and the substrate temperature. This technique is quite effective to achieve a uniform size distribution of Si-QDs with an areal density of the order of 1013cm-2.
Generation of Acceptor Levels in Ge by the Uniaxial Strain - A Theoretical Approach
Authors: Takai Kentaro , Shiraishi Kenji , Oshiyama Atsushi
Published: October 2008

We have studied energetics and atomic and electronic structures of Ge mono-vacancies under biaxial and uniaxial strain. We have found that compressive strain drastically reduce the formation energy of Ge mono-vacancy, and strain induced Ge vacancy formation is expected. Further, our calculations show that energy levels of Ge mono-vacancies sensitively depend on the types of applied strain. In particular, direction of uniaxial strain greatly affects the position of Ge mono-vacancy levels. Our calculation indicates that acceptor levels are easily generated under [110] uniaxial compressive strain. Whereas, acceptor level generation is difficult under [100] uniaxial compressive strain.
Influence of in-situ Boron Doping on the Surface Roughening of SiGe:B Films
Authors: Tsuchida Ryutaro , Mori Shinji , Sato Tsutomu , Uchitomi Naotaka , Mizushima Ichiro
Published: October 2008

Selective epitaxial growth of B-doped SiGe (SiGe:B) films is one of the key techniques for the embedded SiGe (e-SiGe) structure for high-performance pMOSFETs. Both the high Ge composition and the high B-doping concentration are desirable for increasing the stress in the channel region and decreasing the series resistance in the source/drain region. However, increasing Ge composition and B concentration may lead to defects in the epitaxial SiGe:B layer and thus to the roughening of the surface of the films. In this work, influence of B doping on the surface roughness and the roughening process in SiGe:B epitaxial films are examined.
Low Temperature Epitaxial Growth of Full Heusler Alloy Fe2MnSi on Ge(111) Substrates for Spintronics Application
Authors: Ueda Koji , Ando Yuichiro , Yamamoto Kenji , Kumano Mamoru , Hamaya Kohei , Sadoh Taizoh , Narumi Kazumasa , Maeda Yoshihito , Miyao Masanobu
Published: October 2008

Low temperature epitaxial growth of the full Heusler alloy Fe2MnSi layers on Ge(111) substrates has been investigated. Good crystallinity of Fe2MnSi layers and a very sharp interface of Fe2MnSi/Ge structure were realized at 200oC.
Heteroepitaxial Integration of Single Crystalline Ge(111) layers on Si(111) via PrO2(111) Heterostructures
Authors: Giussani Alessandro , Seifarth Olaf , Rodenbach Peter , Zaumseil Peter , Weidner Guenter , Muessig Hans-Joachim , Storck Peter , Schroeder Thomas
Published: October 2008

Epitaxial Ge(111) layers were grown by Molecular Beam Epitaxy (MBE) on cubic PrO2(111) / Si(111) systems. The achieved Ge-on-Insulator heterostructures were widely characterized by a combination of in-situ and ex-situ techniques. It was shown that an interaction between the PrO2(111) layer and the growing semiconductor deposit occurs in the initial Ge evaporation stages, which results in a complete reduction of the buffer oxide to a cubic Pr2O3(111) film. On such a thermodynamically stable support Ge grows epitaxially in the Volmer-Weber mode, forming single crystalline, (111)-oriented islands. By suitably tuning the deposition parameters, these islands coalesce in a closed, atomically smooth, single crystalline Ge(111) layer with the same type-A orientation as the Si(111) substrate.
Effect of Ion Implantation and Anneals on Fully-strained SiC and SiC:P Films using Multiple Characterization Techniques
Authors: Madan Anita , Li Jinghong , Ren Zhibin , Yang B F. , Harley Eric C. , Adam Thomas N. , Loesing Rainer , Zhu Zhengmao , Pinto Teresa , Chakravarti Ashima , Dube Abhishek , Takalkar Rohit , Weijtmans J. W. , Black Linda R. , Schepis Dominic J.
Published: October 2008

In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films for various ion implant conditions and anneals that are typically used in traditional CMOS flows. Full characterization has helped identify process integration schemes which give significant drive current enhancements.
Uniaxially Strained SGOI and SSOI Channels for High Performance Multi-Gate CMOS
Authors: Irisawa Toshifumi , Numata Toshinori , Tezuka Tsutomu , Usuda Koji , Hirashita Norio , Moriyama Yoshihiko , Sugiyama Naoharu , Takagi S.
Published: October 2008

An appropriate merging of mobility enhancement technologies with multi-gate device structures has been strongly required for future high performance and low power CMOS. In this paper, we review our recent results concerning multi-gate CMOS with uniaxially strained SOI channels for nFETs and SGOI channels for pFETs. It is shown that those channels are quite effective to increase mobility. It is also suggested that the optimum multi-gate CMOS structures with enhanced mobilities of both electrons and holes can be realized on a conventional (001) substrate in the same <110> current flow direction for n and pFETs.
Elimination of Native Ge Dielectrics at Ge/High-k Dielectric Interfaces for Ge MOS Devices
Authors: Lucovsky Gerald , Long Joseph P. , Seo Hyungtak , Chung Kwun-Bum , Lee Sanghyun
Published: October 2008

This paper presents a spectroscopic study of interfacial bonding and substrate gate/dielectric reactions for crystalline Ge-high-K gate dielectric hetero-structures. A novel processing sequence has been developed for (i) depositing HfO2 and Hf Si oxynitrides (HfSiON) onto N-passivated Ge(111) and (100) substrates, designed to prevent subcutaneous oxidation of the Ge substrate during dielectric deposition, and then (ii) eliminating N from Ge-N interfacial bonds during 650-800oC rapid thermal annealing in Ar. This approach has been motivated by spectroscopic studies that have shown that the band-gaps of GeO2 and Ge3N4 are reduced with respect to their Si counterparts and cannot be used as interfacial layers (ILs) either: (i) on n-type Ge substrates, or (ii) in n-MOSFETs in which a p-type Ge substrate is inverted. Changes in interface bonding as a function of post-deposition annealing for G/HfO2 Ge/HfSiON, and Ge/HfSiON/HfO2 stacks have been studied by X-ray absorption and photoelectron spectroscopy revealing (i) conduction and valence band edge defects, as well as (ii) significant process induced changes in these defect densities.
Mobilty Modeling of Strained Germanium (s-Ge) Quantum Well (QW) Heterostructure pMOSFETs
Authors: Krishnamohan Tejas , Pham Anh-Tuan , Jungemann Christoph , Meinerzhagen Bernd , Saraswat Krishna
Published: October 2008

In this work, we have performed a thorough study of the mobility in 'Si / s-Ge / Si' QW heterostructure pMOSFETs. Through experiments and detailed simulations, the effects of the s-Ge quantum well (QW) thickness and quantum confinement effects on the hole mobility of both, single-gate (SG) and double-gate (DG) QW pMOSFETs have been explored.
The Versatile Use of SiGe for High-Performance Devices
Authors: Hijzen Erwin , Donkers Johan , Meunier-Beillard Philippe , Saarnilehto Eero , Sonsky Jan , Hurkx G. A. M. F. , Van Noort W.
Published: October 2008

Apart from the widely used bandgap engineering in the base of Hetero-junction Bipolar Transistors (HBTs) and strain engineering in CMOS SiGe has many other possible application in Si technology. This paper will discuss several examples, both within and outside (Bi)CMOS technology. For instance, SiGe bandgap engineering can be used in power diodes. Other possibilities make use of the fact that SiGe can be etched selectively towards Si. This allows, for example, creation of cavities in the silicon substrate. These can be used for, e.g., reduction of parasitic capacitance, device isolation, or electric field shaping.
HCl Selective Etching of Si1-xGex versus Si for Silicon On Nothing and Multi Gate Devices
Authors: Destefanis Vincent , Hartmann Jean-Michel , Hüe Florian , Bensahel Daniel
Published: October 2008

We have studied the low temperature (~ 650oC), high HCl partial pressure (180 Torr) selective etch of SiGe versus Si inside a RP-CVD reactor. The surface roughness strongly increases while vertically etching fullsheet Si1-xGex layers. We have also laterally etched (Si / SiGe) multilayers patterned along the <110> directions. The best selectivities and the highest SiGe etch rates have been obtained for the highest Ge content studied, i.e. 40%. <111> facets have been revealed at the end of tunnels. A strong increase (x 18) of the <110> lateral HCl etch rates has been evidenced when increasing the Si0.6Ge0.4 layer thickness from 5 up to 20 nm. Very good SiGe versus Si selectivities have been obtained with slightly higher etch rates than on bulk Si when HCl etching (Si / SiGe) multilayers grown on Si0.8Ge0.2 virtual substrates. Finally, a strong HCl etch in-plane anisotropy has always been evidenced. <100> oriented pattern corners are indeed far more etched than <110> oriented edges.
Comparison Between Three Si1-xGex versus Si Selective Etching Processes
Authors: Salvetat Thierry , Destefanis Vincent , Borel Stephan , Hartmann Jean-Michel , Kermarrec Olivier , Campidelli Yves
Published: October 2008

Three very different approaches to laterally etch SiGe layers selectively versus Si have been evaluated in terms of etch rate, selectivity and isotropy. The first one calls upon a CF4 plasma at low pressure and room temperature. The second one consists in the use of gaseous HCl at relatively high temperature and pressure in an epitaxy reactor. The third one is based on the use of appropriate chemistries in a wet bench. Germanium concentration impact on processes has been studied in the 20 - 40% range. To allow a strict comparison between so different processes, common test structures have been fabricated and etching targets have been jointly defined. Each technique entails its strengths and drawbacks, which will have to be carefully weighted when selecting one instead of another for a given sacrificial material configuration.
Low and High Temperature Boron and Phosphorous Doping of Si for Junctions and MEMS Purposes
Authors: Gonzatti Frederic , Hartmann Jean-Michel , Yckache Karim
Published: October 2008

Deals with the low temperature and high temperature boron and phosphorous doping of Si for raised sources and drains and MEMS purposes. Hydrogenated (NSEG) and chlorinated (SEG) chemistries have been probed.
Selective Polycrystalline Si and SiGe Deposition on Epitaxial Si Induced by B-Atomic Layer Doping
Authors: Yamamoto Yuji , Koepke Klaus , Fursenko Oksana , Weidner Guenter , Murota Junichi , Tillack B.
Published: October 2008

Selective polycrystalline growth is obtained by incorporation of high level of B concentration at the interface between the Si substrate and the deposited Si layer using atomic layer doping (ALD). The high doping concentration of B at the interface is covering the crystal information of the Si lattice resulting in polycrystalline growth. B diffusion into deposited Si layer is pronounced by the transition from epitaxial Si growth to polycrystalline growth. Effective activation energy of the selective polycrystalline Si growth on Si is not different from that on SiO2. The transition from epitaxial growth to polycrystalline growth is observed for B doses in the range of 2-4×1015 cm-2 as well for selective Si as for selective Si0.8Ge0.2 growth.
Electrical Activity of Dislocations and Defects in Strained Si and Ge Based Devices
Authors: Simoen Eddy R. , Eneman Geert , Verheyen Peter , Loo Roger , Bargallo Gonzalez Mireia , Claeys Cor
Published: October 2008

This paper reports on the Solid Phase Epitaxial Regrowth (SPER) of phosphorus implanted pre-amorphized p-type germanium at 350 oC using Rapid Thermal Annealing and focuses more specifically on the P concentration dependence of the regrowth velocity. This is studied by a combination of Rutherford Backscattering in the channeling mode (RBS-C) and Secondary Ion Mass Spectrometry (SIMS). As will be shown, different regimes can be distinguished whereby for chemical concentrations up to 4-5x1020 cm-3 an enhanced recrystallization occurs compared with undoped amorphized Ge. Above this metastable solid solubility limit, the regrowth is retarded, due to the redistribution and snow plow of the excess P across the amorphous/crystalline interface. It will also be demonstrated that during SPER at 350 oC, limited P-diffusion occurs even at the highest implantation dose studied.
Observation of Crystalline Imperfections in Supercritical Thickness Strained Silicon on Insulator Wafers by Synchrotron X-ray Topography
Authors: Shimura Takayoshi , Inoue Tomoyuki , Okamoto Yuki , Hosoi Takuji , Edo Hiroki , Iida Satoshi , Ogura Atsushi , Watanabe Heiji
Published: October 2008

A commercial supercritical thickness strained Si-on-insulator (SC-sSOI) wafer was characterized by large-area synchrotron x-ray topography at the glancing incident condition. Several kinds of contrast showing crystalline imperfections were observed all over the wafers, such as macule and crosshatch patterns. Similar crosshatch patterns were also observed in the x-ray topographs of a conventional strained Si-on-insulator (sSOI) wafer and a strained Si wafer that has the strained Si layer epitaxially grown on the relaxed SiGe layer on the insulator (SGOI) structure. This indicates that the crosshatch pattern of the SC-sSOI wafer originates from the lattice distortion in the original SiGe substrate of the strained Si layer.
Channel Strain Characterization in Embedded SiGe by Nano-beam Diffraction
Authors: Li Jinghong , Lamberti Angela , Domenicucci Anthony , Gignac L. , Utomo Henry , Luo Zhijiong , Rovedo Nivo , Fang Sunfei , Ng Hung , Holt Judson R. , Madan Anita , Lai Chung Woh , Ku Ja-Hum , Schepis Dominic J. , Han Jin-Ping , Lagus Mark
Published: October 2008

Nano-beam diffraction (NBD) has been successfully used in measuring channel strain in device of embedded SiGe (eSiGe). Strain measurements have been correlated to different processing conditions and microstructures of eSiGe and device performance. For intrinsic eSiGe without growth defect with 15-17%Ge, the average channel strain measured by NBD is ~ -0.55%, consistent with our previous measurement by convergent electron beam diffraction (CBED) and TCAD simulation. For graded eSiGe with average ~22%Ge, the average channel strain measured by NBD is ~ -0.90%, which is lower than the TCAD simulation. Differences between experimental results and simulation are also discussed.
The Effect of Silicide Processing on Stress Reduction in Silicon Device Structures with Strained SiGe Elements
Authors: Peidous Igor , Press Patrick
Published: October 2008

Intrinsic mechanical stresses in device structures with strained SiGe and Ni silicide have been studied. Stresses in blanket films were derived from wafer curvatures after different stages of device processing. The measurement suggested that the temperature coefficient of NiSi linear expansion equals 1.16⋅10-5 K-1. Experiments showed that silicide films on epitaxial layers of SiGe compensated SiGe stresses in a much greater degree compared to what would follow from the thermal contraction model. Electron microscopy revealed that NiSi(Ge) films formed on SiGe had rough surfaces reducing overall stresses in Si/SiGe/NiSi structures. Computer simulations of MOSFETs with embedded SiGe Source/Drain regions indicated that partial consumption of SiGe layers at silicidation, tensile stress developed in NiSi films due to the thermal contraction and silicide-SiGe interface roughness might reduce compressive stresses in MOSFET channels by 15 - 40%.
Performance of Ge/Si Receivers at 1310 nm
Authors: Morse Mike , Dosunmu Olufemi , Yin Tao , Kang Yimin , Liu H. D. , Sarid Gadi , Ginsburg Eyal , Cohen Rami , Litski S. , Zadka Moshe
Published: October 2008

We are studying three types of these detectors for use at 1310 nm; normal incident illuminated p-i-n detectors (NI-PD), waveguide p-i-n detectors (WG-PD), and avalanche photodetectors (APDs). NI-PDs have achieved -14.5 dBm sensitivity at 10 Gb/s and 850 nm, which is comparable to similarly packaged GaAs devices. Unlike GaAs detectors, however, the Ge detectors can also operate at 1310nm, with a ~0.5dB sensitivity improvement expected. WG-PDs have achieved bandwidths of approximately 30 GHz at 1550 nm with internal quantum efficiencies of 90%, and similar, or better, performance is also expected at 1310 nm. Normal incident APDs operating at 1310 nm have achieved a gain-bandwidth product of 153 GHz which exceeds that of a commercial InP-based APDs, These devices also have a primary responsivity of 0.54 A/W with a 3-dB bandwidth of 9GHz at a gain of 17.
High Performance Ge Devices for Electronic-Photonic Integrated Circuits
Authors: Liu Jifeng , Michel Jurgen
Published: October 2008

We present high performance, Ge-based photodetectors and electro-absorption (EA) modulators for electronic-photonic integrated circuits on Si platform. As a pseudo-direct band gap material, Ge offers excellent optoelectronic properties with CMOS compatibility. We demonstrate waveguide-integrated Ge photodetectors with a high responsivity of >1.0 A/W in a broad spectrum range of 1470-1570 nm and >7 GHz bandwidth at a low reverse bias of -0.1 V. We have also achieved a waveguide-integrated, ultra-low energy GeSi EA modulator with a small footprint of 30 µm2, a 10 dB extinction ratio at 1540 nm, an ultra-low energy consumption of 50 fJ/bit, and an operation spectrum that covers half of the C-band. These devices have been fabricated with standard CMOS technology and can be conveniently integrated with CMOS circuits for electronic-photonic integration.
Characteristics of Ge and SiGe pin Photodiodes without Post-growth Annealing
Authors: Park Sungbong , Takita Shinya , Ichikawa Ryuzo , Ishikawa Yasuhiko , Wada Kazumi
Published: October 2008

We demonstrate low dark currents Ge pin photodiodes on Si substrate fabricated by UHV-CVD without post-growth annealing and possibility of fabricating any composition SiGe diode between Si0.5Ge0.5 and Ge with as a high responsivity as theoretical calculation even at 0V. SiGe diodes showed diode characteristics like reference Si diodes but had much higher dark currents because of the surface leakage. The Ge diodes had low dark currents but some Ge diodes had high dark currents because of a structural difference. We discuss the difference of the current-voltage characteristics and responsivity between Ge and SiGe and between the Ge diodes with different structure. We also deal with a method to reduce a dark current without post-growth annealing using a Si cap. The photodiodes with low dark current without high temperature annealing is a key to photonics-electronics (P-E) convergence using standard Si processing.
Epitaxial Growth of Si:C by means of Gas Source MBE
Authors: Yamada Akira , Ishihara Hanae , Inoue Komaki
Published: October 2008

Si:C films have been successfully grown by the gas-source molecular beam epitaxy. The thermal stability of Si:C was comprehensively studied, and the formation of SiC and the diffusion of carbon atoms from the substitutional sites were observed when the film was annealed higher than 800 C. It was shown that the SOI substrate was very promising substrate in order to realize the strained Si/strain-relaxed Si:C structure, which is applicable to the vertical MOSFETs. Finally, the relaxation mechanism of Si:C was studied. It was shown that the Si:C was hard to form the misfit dislocations at the interface and that the stress was released by the cusp formation. The phenomenon is suitable for the application of Si:C to the source/drain stressor.
Massive Batch Selective Si and SiGe Epitaxial Deposition
Authors: Meyer Douglas J. , Suvar Erdal , Rohlfing Franziska , Grabolla Thomas
Published: October 2008

Selective and nonselective growth of Si and SiGe was performed in a large batch vertical LPCVD furnace on 200mm substrates. Excellent atomic crystal quality, as demonstrated by RHEED, and low defect epitaxy were observed using a wet HF-last process to remove native oxide followed by a H2 bake. Although an oxygen free interface, measured by SIMS, was achieved with a H2 bake temperature of 800C, a temperature of 900C was required in order to remove interfacial features detectable by laser surface scan. Selective Si deposition rates of 10nm/min., using SiH2Cl2/H2 chemistry have been demonstrated at a temperature of 850C and a pressure of 500Pa.
SiGe Quantum Rings by Ultra-high Vacuum Chemical Vapor Deposition
Authors: Lee Cheng-Han , Lin Cheng Min , Liu CheeWee , Chang Hung-Tai , Lee Sheng Wei , Shushpannikov Pavel , Gorodtsov V. A. , Goldstein Robert
Published: October 2008

SiGe quanrum rings (QRs) grown at 500oC and 600oC were observed on SiGe quantum dots (QDs) capped with Si. Average depth and diameter are 9 nm and 185 nm, respectively, for QRs at 500oC, while those are 0.9 nm and 84 nm for QRs at 600oC. Ge out-diffusion mechanism is proposed to be responsible for nanorings formation in 500oC, and Si surface diffusion toward strain-free edges is proposed to be responsible for nanorings formation in 600oC. Raman spectroscopy demonstrates that formation of QRs in 600oC is close correlated with a strain-driven process. QRs grown in 600oC are the metastable states and can be only observed in very limited conditions. Thick cap and high thermal budget can both destroy SiGe nanorings structures.
Fixed-Oxide-Charge Characterization by Photoreflec-tance Spectroscopy in HfO2 on Ge treated by Fluorine
Authors: Kanashima Takeshi , Lee Hyun , Mori Yuya , Imajo Hideto , Okuyama Masanori
Published: October 2008

The interface traps in HfO2/Ge is reduced by fluorine treatment, and photoreflectance spectroscopy (PRS) which has some merits such as nondestructive and contactless, is applied for characterization of fixed charges distribution to HfO2/Ge gate stack as a new type of measurement method. C-V characteristics show that the sample treated with fluorine before deposition by photo-assisted MOCVD has small hysteresis, and interface states are improved. PRS signal of HfO2/Ge gate stack can be detected, and these measurements show that fixed charges are mainly distributed at interface and reduced by fluorine treatment.
Enhanced Ge MOS Device Performance Through a Novel Post-gate CF4-plasma Treatment Process
Authors: Xie Ruilong , Thamarai Muruganandam , Sun Zhiqiang , Yu Mingbin , Lai Doreen M. , Chan Lap , Zhu Chunxiang
Published: October 2008

A post-gate CF4-plasma treatment process is proposed and demonstrated on Ge MOS devices and the effects of F incorporation have been extensively studied on both high-k/Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that: (1) F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k/Ge interface; (2) Electrical characteristics like Dit, gate leakage, C-V hysteresis and breakdown voltage are improved after F incorporation; (3) Post-gate CF4 treatment is also compatible with pre-gate surface passivation, and it can further enhance the device performance. By combining Si surface passivation and post-gate CF4 treatment, interface quality has been greatly improved for high-k/Ge gate stack and a high peak hole mobility of 376 cm2/V⋅s has been achieved for Ge pMOSFETs
Formation of Ge3N4/Ge Structures Using Nitrogen Radicals and Their Thermal Stability
Authors: Kondo Hiroki , Oda Shigehisa , Ogawa Masaki , Zaima Shigeaki
Published: October 2008

Formation of Ge3N4 on Ge(001) substrates by nitrogen radicals and their thermal stability were investigated in this study. A Ge3N4/Ge structure with a root-mean-square surface roughness of 0.18 nm is successfully formed by layer-by-layer manner at a substrate temperature of 300oC. In contrast, island growth and thermal decomposition of Ge3N4 occur during the nitridation at 600oC, and consequently island structures and locally-flat areas are formed. Ge3N4 thickness is saturated at a certain nitridation time and, not only saturation times but also saturation thicknesses are different depending on plasma condition. By a 2-step nitridation in which the nitridation at 300oC and 600oC for 900 sec were sequentially subjected to Ge surfaces, a Ge3N4 thickness much larger than that at the single-step nitridation can be obtained without surface roughening.
Nanowires to Replace Planar CMOS?
Authors: Thean Aaron
Published: October 2008

It is be hard to believe that nanowires will succeed planar CMOS completely, given some of the fundamental incompatibilities with the expected System-on-Chip needs. Nanowires may eventually replace planar devices for specific applications like memories. However, devices like FinFETs and Tri-gates would stand better chances for CMOS platform integration due to their compatibility with planar devices processing.
Gate-All-Around Silicon Nanowire Devices: Are These the Future of CMOS?
Authors: Lo Guo-Qiang P. , Singh Navab , Rustagi Subhash , Buddharaju K. D. , Balasubramanian N. , Kwong Dim-Lee
Published: October 2008

Though top-down approach, which leverages on conventional lithography, patterning for wire formation, has been considered as the closest to the manufacturing format, many technology issues or even barriers are still widely remained. These technology concerns will be presented in our discussion, in respect to both the horizontal and vertical wire platforms. With the analysis of the commonality and differences facing both platforms, the potential of the ultimate integration will be addressed
Opportunities for Group IV Nanowire Devices in Si CMOS Technology
Authors: Tutuc Emanuel , Banerjee Sanjay , Nah J. , Varahramyan Kamran , Jain N. , Ferrer D.
Published: October 2008

We discuss several group IV semiconductor nanowire devices, which are compatible and may outperform conventional CMOS devices. These include gate-all-around nanowire devices, Ge/Si core-shell structures, and tunneling field effect transistors.
III/V Nanowire FETs for CMOS?
Authors: Wernersson Lars-Erik
Published: October 2008

III/V MOS transistors are currently attracting considerable attention. The main driving force is that the advantageous transport properties in III/V materials are expected to increase the drive current in the MOS transistors. Major challenges for the III/V MOS technologies include the growth of high-quality III/V materials on Si substrates and the control of the MOS interface. Using the nanowire technology, we have recently demonstrated enhancement mode operation of 50 nm Lg InAs nanowire wrap-gate transistors in a vertical configuration. They demonstrate a transconductance of 0.5 S/mm, an inverse sub-threshold slope of about 80 mV/dec., and an Ion/Ioff ratio > 1000 for a drive voltage of Vd=0.5 V. These results show promise for the use of nanowires in CMOS applications.
Schottky Barrier Height Extraction in Ohmic Regime: Contacts on Fully-Processed 200mm GeOI Substrates
Authors: Hutin Louis , Le Royer Cyrille , Tabone Claude , Carron Véronique , Delaye Vincent , Nemouchi Fabrice , Aussenac François , Clavelier Laurent , Deleonibus Simon
Published: October 2008

The problematics of contacts optimization on Germanium MOSFETs suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals such as Ti on Ge were so far mostly investigated on weakly n-doped samples under pure Thermionic Emission (TE) regime. In this paper, we detail Schottky Barrier Height (SBH) extractions based on contact resistance (Rco) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully-processed GeOI samples with Ti-based contacts, yielding effective barriers of 0.32eV for electrons and 0.15eV for holes. The method provides a good physical understanding of the technological factors impacting their electrical properties, therefore enabling to define paths towards ohmic contact optimization in the context of device integration on GeOI.
Generation of Realistic Amorphous Al2O3 And ZrO2 Samples By Hybrid Classical and First-Principle Molecular Dynamics Simulations
Authors: Chagarov Evgueni , Kummel Andrew C.
Published: October 2008

Realistic amorphous samples of a-Al2O3 and a-ZrO2 were generated by a hybrid classical and density functional theory (DFT) "melt and quench" molecular dynamics approach. The generated samples demonstrated good correlation with reference experimental and simulated properties.
Nanosynthesis of Si-Ge-Sn Semiconductors and Devices via Purpose-built Hydride Compounds
Authors: Kouvetakis John , Tolle John , Roucka Radek , D'Costa Vijay R. , Fang Yan-yan , Chizmeshya Andrew V. , Menendez Jose
Published: October 2008

We describe new routes to the growth of Ge and Sn-containing semiconductors on Si(100). For modest Sn concentrations GeSn alloys are expected to be direct-gap materials and this property can be exploited to develop band-to-band devices. The ternary GeSiSn system eliminates one of the major limitations of SiGe/Si by decoupling strain and bandgap. This may lead to new families of devices including quantum cascade lasers and high-efficiency solar cells based on hybrid group IV/III-V designs. The latest advances in low-temperature CVD of SiGe/Si, Ge/Si, GeSn/Si, GeSiSn/GeSn/Si and GeSiSn/Ge/Si materials are described and key developments leading to practical device fabrication are emphasized. This includes selective growth via novel epitaxy and practical doping protocols via designer molecular sources to achieve carrier concentrations n, p > 1019 cm-3 for which alloy scattering to the electron and hole mobilities is very small. As an example of a GeSn/GeSiSn prototype device the fabrication of a simple photoconductor at 1.55 μm is presented.
Defect Reduction of Ge on Si by Selective Epitaxy and Hydrogen Annealing
Authors: Yu Hyun-Yong , Park Jin-Hong , Okyay Ali K. , Saraswat Krishna
Published: October 2008

We demonstrate a promising approach for the monolithic integration of Ge-based nanoelectronics and nanophotonics with Silicon: the selective deposition of Ge on Si by Multiple Hydrogen Annealing for Heteroepitaxy (MHAH). Very high quality Ge layers can be selectively integrated on Si CMOS platform with this technique. We confirm the reduction of dislocation density in Ge layers using AFM surface morphology study. In addition, in situ doping of Ge layers is achieved and MOS capacitor structures are studied.
Ge dots in Optical Microcavities--A Possible Direction for Silicon-based Light Emitting Devices
Authors: Xia Jinsong , Tominaga Ryuichiro , Iwamoto Satoshi , Usami Noritaka , Aragawa Yasuhiko , Shiraki Yasuhiro
Published: October 2008

Different silicon optical microcavities with Ge self-assembled quantum dots are fabricated and characterized. Room-temperature microphotoluminescence measurements show that strong resonant light emission from Ge dots in the cavities dominate the spectra and the photoluminescence intensity is significantly enhanced by the optical resonance in the cavity. Control of the wavelengths of resonant peaks is demonstrated by tuning the lattice constant of photonic crystal structures. A quality factor around 3000 of the resonant peak is achieved by microring resonators with Ge self-assembled dots.
Photocurrent of SiGe/Si Strained Multiple Quantum-Wells Grown by UHV-CVD
Authors: Kim Taek Sung , Choi Sang-Sik , Jeong Tae Soo , Kang Sukill , Shim Kyu-Hwan
Published: October 2008

The optical property was studied for the Si0.8Ge0.2/Si strained multiple quantum-well (MQW) structure grown by using ultra high vacuum chemical vapor deposition (UHV-CVD). The structural properties of the Si0.8Ge0.2/Si strained MQW were investigated using high-resolution X-ray diffraction (HR-XRD). The photocurrent spectrum of a Si0.8Ge0.2/Si strained MQW was measured at the room-temperature and the liquid-nitrogen temperature. For Si0.8Ge0.2/Si strained MQW, the transition peaks related to the MQW region observed in the photocurrent spectrum were preliminarily assigned to electron-heavy hole (e-hh) and electron-light hole (e-lh) fundamental excitionic transitions.
Optical Bleaching of Thin Film Ge on Si
Authors: Sun Xiaochen , Liu Jifeng , Kimerling Lionel , Michel Jurgen
Published: October 2008

Thin ﬁlm Ge on Si is a potential active material candidate for electrically pumped monolithically integrated Si-based light emitters. Theoretical analysis has shown that a combination of strain and n-type doping can modify the band structure of Ge so that it exhibits direct bandgap properties. Direct band-to- band optical transition is observed from the room temperature photoluminescence at around 1550nm. An optical bleaching ef- fect occurring in lock-in pump-probe measurements indicates a precursor to optical net gain.
Photoluminescence of Selectively Grown Epitaxial SiGe:C/Si layers
Authors: Bouvier Julien , Bremond Georges , Vandelle Benoit , Brossard Florence , Dutartre Didier
Published: October 2008

Photoluminescence of strained Si1-x-yGexCy alloy layer and Si1-x-yGexCy /Si1-xGex structures selectively grown by RT-CVD is investigated. Spectroscopic PL at low temperature (14K) and integrated PL at room temperature were performed. We report the effect of C atoms on SiGe photoluminescence spectra features, especially intensity ratio between the no-phonon (NP) and transverse-optical (TO) transitions. Using dedicated Si1-x-yGexCy /Si1-xGex structures, influence on SiGe PL spectra of C atoms supposed in non-substitutional positions is reported.
Formation of Si- and Ge-based Full-Heusler Alloy Thin Films using SOI and GOI Substrates for the Half-metallic Source and Drain of Spin Transistors
Authors: Takamura Yota , Nishijima Akira , Nagahama Yohei , Nakane Ryosho , Sugahara Satoshi
Published: October 2008

The paper presents a novel preparation technique for Si- and Ge-based half-metallic full-Heusler alloy thin films, utilizing silicon-on-insulator (SOI) and germanium-on-insulator (GOI) substrates, respectively. Full-Heusler Co2FeSi (Co2FeGe) alloy thin films were successfully formed by thermally activated silicidation (germanidation) reaction between an ultra-thin SOI (GOI) layer and Co/Fe layers deposited on it. This technique can easily produce fully ordered L21 structure that is necessary for the half-metallicity of full-Heusler alloys. The proposed technique is compatible with metal source/drain formation process in advanced CMOS technology and would be applicable to the fabrication of the half-metallic source/drain of MOSFET type of spin transistors.
Germanium-Based Ferromagnetic Semiconductor Ge1-xFex for Silicon Spintronics
Authors: Shuto Yusuke , Tanaka Masaaki , Sugahara Satoshi
Published: October 2008

Ferromagnetic semiconductor Ge1-xFex thin films were grown on Si(001) substrates by low-temperature molecular beam epitaxy. The crystal structure of the Ge1-xFex films was of diamond type for 0 {less than or equal to} x {less than or equal to} 17.5%. Magnetic circular dichroism (MCD) characterizations revealed that the origin of the ferromagnetic ordering in the Ge1-xFex films comes only from the diamond lattice phase with the cooperation of s,p-d exchange interactions. The Ge1-xFex films clearly exhibited the anomalous Hall effect at lower temperatures, and their ferromagnetic behavior was consistent with the results of the MCD observations. As the Fe content increased, the resistivity of the film monotonically decreased and simultaneously the Curie temperature monotonically increased. All the experimental results indicate that the Ge1-xFex films grown on Si(001) have the properties of intrinsic ferromagnetic semiconductor.
Electrodeposition of Nanoscale SixGe1-x from an Air- and Water Stable Ionic Liquid
Authors: Al Salman Rihab , Zein El Abedin Sherif , Endres Frank
Published: October 2008

We report for the first successful electrodeposition of highly pure SixGe1-x from the air- and water stable ionic liquid 1-butyl-1-methylpyrrolidinium bis(trifluoromethylsulfonyl)amide ([Py1,4]Tf2N) containing GeCl4 and SiCl4 as precursors. The electrodeposition is investigated by cyclic voltammetry and high resolution scanning electron microscopy. SixGe1-x can be deposited reproducibly and easily in this ionic liquid. Interestingly, the SixGe1-x deposit showed a strong colour change (from red to blue) at room temperature during electrodeposition. The observed colours are strong hints for band gaps between at least 1.5 and 3.2 eV, which are indicative of a quantum size effect. This proves the potential of ionic liquids in the electrodeposition of high quality SixGe1-x.
Phonon Transport and Thermoelectricity in Silicon Nanostructures
Authors: Ryu Hyuk Ju , Ritz Clark , Klein Levente , Hamann Hendrik , Lagally Max G. , Eriksson Mark
Published: October 2008

We present both experimental results and a compact model on nanoscale thermal transport in the vicinity of a hot spot in silicon. Effective-local-temperature measurements on the nanoscale are influenced by localized heating effect and a thermal interface resistance, as well as by the spreading resistance in silicon. Ballistic phonon transport is observed for nanoheaters where the interface thermal resistance contribution can be minimized. Thermoelectricity in silicon nanostructures is investigated as a possible route to convert thermal energy into electricity.
Enhanced Ferromagnetic Fe-rich Germanide Film Grown using Magnetron Sputtering Employing a Post-deposition Anneal
Authors: Wong Andrew S. , Ho Ghim Wei , Chi Dong Zhi
Published: October 2008

We describe the formation of a ferromagnetic Fe-rich germanide layer by a two-step process involving magnetron sputtering and anneal. A thin epitaxial iron (epi-Fe) film is deposited on Ge (001) substrate and then annealed at 275 oC in nitrogen inducing germanide formation. Surprisingly, we observe an enhancement in saturation magnetization in germanide films. Secondary ion mass spectroscopy and x-ray diffraction confirm the formation of a thin Fe-rich germanide layer whilst high resolution transmission suggest that it can be Fe3Ge.
SiGe:C BiCMOS Technologies for Automotive Radar Applications
Authors: Fischer Gerhard G. , Glisic Srdjan
Published: October 2008

The introduction of automotive radar sensors operating in the 76-81 GHz frequency range is a very promising application for SiGe:C HBT technologies. In this work, the performance of the critical mm-wave circuits has been benchmarked showing the suitability of SiGe:C HBT circuits as competitors to the III-V compound semiconductor circuits available in the first generation radar sensors. Additionally, because of the strong interest of the automotive industry on reliable sensor operation between -40oC and up to +85oC the temperature stability of the radar oscillator and the reliability of the SiGe:C HBTs will be discussed.
3D Integration Techniques Applied to SiGe Power Amplifiers
Authors: Malladi Ramana M. , Joseph Alvin , Lindgren Peter , Ni Wan , Wang Dawn , Ding Hanyi , Erturk Mete , Previti-Kelly Rosemary
Published: October 2008

We describe a 0.35 micron SiGe BiCMOS technology that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low inductance ground to the package by method of through-silicon-via (TSV), offering a competitive solution for future multi-band / multi-mode PA integration. The tungsten filled, multi-finger, bar shaped TSV delivers over 75% reduction in inductance compared to a traditional wire bond, enabling higher frequency applications with roughly 20% die area reduction, and without compromising the technology reliability for use conditions in a low-cost plastic QFN package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, and its usefulness in a demanding WiMAX PA application.