Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration
Authors: Loo Roger , Jourdain Anne , Rengo Gianluca , Porret Clement , Hikavyy Andriy Yakovitch , Liebens Maarten , Becker Lucas , Storck Peter , Beyer Gerald , Beyne Eric 
Published: December 2020

Three-dimensional System-On-Chip (3D-SoC) technology schemes require wafer-to-wafer bonding combined with good control of the Si thickness and the Si within wafer uniformity [1,2]. As a result, there is a renewed interest in epitaxial strained Si1-xGex as etch stop layer [3]. Epitaxial growth by means of Chemical Vapor Deposition (CVD) offers excellent control of layer thickness and material composition. If needed, the Si cap layer can be in-situ doped. The challenge is to develop low cost epitaxial growth processes without compromising the material quality. Indeed, relaxation of the Si1-xGex layer must be avoided as the presence of threading dislocations in the Si-cap has a detrimental effect on electrical properties and the yield of the devices fabricated afterwards. On the other hand, the Ge concentration in the Si1-xGex layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate [4]. The Si1-xGex layer also needs to be relatively thick as some material loss cannot be avoided. Etching of the Si-cap layer during wafer back-side thinning must be prevented.

In this contribution, we discuss the different challenges for the epitaxial growth of such Si-cap / Si1-xGex // Si-substrate layer stacks, with Si-cap layer thicknesses ranging from 20 to 500 nm and a targeted Ge content in the Si1-xGex layer of 25%. All epi-layers discussed in this work were grown in an ASM Intrepid RP-CVD cluster tool, aiming the highest possible process throughput. To control the epitaxial material quality, fast and reliable in-line metrology and inspection techniques are required. For instance, Wostyn et al. recently reported on inline light scattering measurements, commonly used to determine wafer quality and cleanliness, and have shown that the technique is also suitable to study the crystalline quality after hetero epitaxy [5].

Standard deviations in thickness below 1.5% as measured for both the Si0.74Ge0.26 and the Si-cap layers by means of Spectroscopic Ellipsometry illustrate the within wafer uniformity of the epitaxially grown layer stacks. The Si0.74Ge0.26 material quality is confirmed by the presence of well-defined Kiessig fringes on the (004) XRD spectrum. The lack of a surface crosshatch pattern in AFM and the very low haze values as obtained from light scattering measurements using the KLA Surfscan® SP3 indicate the absence of misfit dislocations in uncapped Si0.74Ge0.26 layers for thicknesses up to 100 nm. After Si capping, RSM measurements still indicate that the layer is fully strained (Fig. 1a). Moreover, no defects were detected by commercial in-line defect inspection systems such as the KLA Electron-Beam Wafer Defect Review (EDRT
M) System and the automated optical inspection system. However, depending on the process conditions, enhanced haze values might be measured. This enhanced surface roughness is due to the presence of misfit dislocations as evidenced by AFM (Fig. 1b). A careful process optimization enables the deposition of Si-cap / Si0.75Ge0.25 // Si-substrate bilayers with low haze values which are completely free of misfit dislocations, still allowing a Si-cap thickness of up to 500 nm and a relative high processing throughput (Fig. 1d). Still, it is striking that in case of 300 mm substrates, layer relaxation, if present, starts at the edge of the wafer (Fig. 1c) [6]. Therefore, special care needs to be taken to ensure that no relaxation is initiated at wafer edges. Extremely sensitive characterization methods are mandatory to detect the onset of relaxation and to ensure the fabrication of defect-free epi stacks. The developed epi process was successfully implemented in 3D device integration schemes to fabricate stacked Gate All Around devices and to demonstrate functional backside integration.

References:

A. Jourdain et al., 2016 IEEE Int. 3D Systems Integration Conf. (3DIC), DOI: 10.119/3DIC.2016.7970028

A. Jourdain et al., 2018 IEEE 68th Electronic Components and Technology Conf. (ECTC), p. 1529

D.J. Godbey et al., J. Electrochem. Soc. 137 (10), 3219 (1990)

K. Komori et al., Solid State Phenom. 282, 107 (2018)

K. Wostyn et al., ECS Trans. 64 (6), 989 (2014)

C. Porret et al., ECS J. of Solid State Sci. and Techn., 8 (8) P392 (2019)

Figure 1