bluuebunny/crossref_metadata_2025 huggingface dataset:
Study of Grid Connected Wind Energy System with Fuzzy Logic Based MPPT Controller
Authors: S Jayalakshmi N. , S Sachin
Published: April 2019

Renewable energy sources (RESs) are gaining more importance due to depleting fossil fuel sources in few decades. When compared to other RESs wind energy system is widely available and user friendly in nature. This paper presents modelling and simulation of grid connected PMSG based wind energy conversion system with P&O maximum power point tracking (MPPT) control technique.  The PQ controller is used for grid tied inverter to exchange real and reactive power with DC bus voltage regulation. The fuzzy logic controller (FLC) is used for MPPT implementation as it provides better performance as compared to the traditional PID controllers. The various case studies are considered for power management between wind system and the utility grid and the results are evaluated in MATLAB/ Simulink platform.
Effectual SVPWM Techniques and Implementation of FPGA Based Induction Motor Drive
Authors: M Saravanan , R Nandakumar , G Veerabalaji
Published: April 2019

This paper presents a field programmable gate array(FPGA)-based control integrated  circuits(IC) for controlling the pulsewidth modulation (PWM) inverter used in power conditioning system for ac-voltage regulation. Space vector pulsewidth modulation(SVPWM) algorithm offers great flexibility to optimise switching waveform. Among them,double edge triggering can be implemented, It consumes less power compare to other PWM techniques. The SVPWM pulses thus generated through Xilinx is given as switching pulses to voltage source inverter(VSI) circuit to trigger the motor. The delay time of PWM output is programmable and SVPWM control IC is reprogrammable.It shows the advantage of lower total harmonic distortion(THD) without increasing the switching losses. Results  are provided along with simulation analysis in terms of THD,output fundamental voltage and voltage transfer ratio to verify the feasibility of operation. The SVPWM switching pattern has been achieved with a fundamental frequency of  50HZ.
Real-time Optical-flow Computation for Motion Estimation under Varying Illumination Conditions
Authors: Sosa Julio C. , Rodríguez Roberto , García Ortega Víctor H. , Hernández Rubén
Published: April 2019

The optical flow approach has emerged as a major technique for estimating object motion in image sequences. However, the obtained results by most optical flow techniques are poor because they are strongly affected by large illumination changes and by motion discontinuities. On the other hand, there have been two thrusts in the development of optical flow algorithms. One has emphasized higher accuracy; the other faster implementation. These two thrusts have been independently pursed, without addressing the accuracy vs. efficiency trade-offs. The optical flow computation requires high computing resources and is highly affected by changes in the illumination conditions in most of the existing techniques. In this paper, a new strategy for image sequence processing is proposed. The data reduction achieved with this strategy allows a faster optical flow computation. In addition, the proposed architecture is a hardware custom implementation  in EP1S60F1020 FPGA showing the achieved performance.
CO Pollution Warning System for Indoor Parking Area Using FPGA
Authors: Purnamasari Prima Dewi , Sumbayak Evan G. , Kurniawan Vicky Dwi , Apriliyanti RR. Wulan
Published: April 2019

From some compounds used as parameters in air pollution-such as O3, Particulate Materials, CO, NO2, SO2 and Pb-CO is the most common cause of poisoning accidents. Indoor parking area is one sample of potential area for CO pollution. However, according to the scientific nature of CO-tasteless, colorless, and odorless-people exposed to CO are usually not aware that s/he exposed to dangerous levels of CO. This research aimed to make a prototype of an embedded system that can monitor air pollution, give an effective warning and it should be affordable. The prototype of CO air pollution alert system has been successfully built using FPGA Xilinx Spartan 3E as the major component. Sensor Hanwei MQ7 used in this prototype has been tested in a simulation box using cigarette smoke as CO pollutant and the reading result has met the characteristic curve in the datasheet. The system interface has met user satisfaction with MOS value 4.31 from 5 scales. Based on the response time testing, we conclude that FPGA is suitable to be used in a system that performs fast parallel processing based on logical actions from the input given.
FPGA Based Embedded System Development for Rolling Bearings Fault Detection of Induction Motor
Authors: SM Shashidhara , Raju Sangameswara P
Published: April 2019

Bearing fault diagnosis is crucial in condition monitoring of any rotating machine. Early fault detection in machines can save millions of dollars in maintenance cost. Different methods are used for fault analysis such as short time Fourier transforms (STFT), Wavelet analysis (WA), Model based analysis, cepstrum analysis etc. Recently, there have been outstanding technological developments related to digital systems, in both hardware and software. These innovations enable the development of new designing methodologies that aim to the ease the future modifications, upgrades and expansions of the system. This paper presents a study of rolling bearing fault diagnosis of induction motor  based on  reconfigurable logic. A case study using FPGA, its design, as well as its implementation and testing, are presented.
FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text
Authors: N Bharatesh , S Rohith
Published: April 2019

There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.
Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing
Authors: Sharma Anshuman , Syed Abdul Hafeez , M Midhun , Raghavendra M R
Published: April 2019

This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and were implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for a data rate from 1kbps to 8kbps was implemented.
Design of AES Algorithm for 128/192/256 Key Length in FPGA
Authors: V. Kinge Pravin , Honale S.J. , Bobade C.M.
Published: April 2019

The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used for  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).
FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System
Authors: A Manoj Kumar , Nadagouda R V , Jegan R
Published: April 2019

Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.
Wireless Sensor Network for Performance Monitoring of Electrical Machine
Authors: Ranaware Priyanka , Dhoot N.D.
Published: April 2019

This paper proposes a novel industrial wireless sensor network for industrial machine condition monitoring. To avoid unexpected equipment failures and obtain higher accuracy in diagnostic and prognostic for the health condition of a motor, efficient and comprehensive data collecting, monitoring, and control play an important role to improve the system more reliable and effective. A novel wireless data collection for health monitoring system of electric machine based on wireless sensor network is proposed and developed in this paper. The unique characteristics of ZigBee networks such as low power, low cost, and high flexibility make them ideal for this application. The proposed system consists of wireless sensor nodes which are organized into a monitoring network by ZigBee protocols. A base station and wireless nodes have been developed to form a prototype system. Various sensors have the capability to monitor physiological as well as environmental conditions. Therefore proposed system provides a flexible solution that makes our living spaces more intelligent.
Implementation of PI Controller for 3ф BLDCM Drive Using FPGA
Authors: Ramesh Balaji S.M. , Muniraj C.
Published: April 2019

Despite the need of a complex motor controller, the simple construction of BLDC motors offers several inherent advantages not provided with brushed DC motors in terms of low inertia, high torque and a very wide speed range. The BLDC motors include, Longer service life due to a lack of electrical and friction losses and also free maintenance due to a lack of brushes and mechanical commutators. The EMI and noise are reduced because of the elimination of ionizing spikes from brushes. The control system of BLDCM is highly complex drive due to nonlinear nature. In such a system for implementing control algorithm needs high speed processor. In this work the controller Xilinx Spartan-6 FPGA is a demonstration platform intended to become familiar with the new features and availability of the Spartan-6 FPGA. The various experimental tests are carried out in 3Ф BLDCM .The experimental results are reported in order to verify the steady state, transient and robustness performance of the controller.
An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control
Authors: Ramachandran Varatharajan
Published: April 2019

A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.
An Integrated Architectural Clock Implemented Memory Design for Embedded System
Authors: Khatwal Ravi , Jain Manoj Kumar
Published: April 2019

Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance for specific application. We have implemented clock based memory architecture design and analyzed internal clock efficiency for SRAM. Architectural clock implemented memory design that reduces access time and propagation delay time for embedded devices. Internal semiconductor material improvement increases simulation performance and these design implemented for application specific design architecture.
Design and Implementation of Multichannel Data Acquisition and Processing System Using LabVIEW
Authors: R. Rinku Dhruva , Srinath Gundu
Published: April 2019

The data acquisition and processing architecture covers the most demanding applications of continuousmonitoring in industrial field. The multichannel data acquisition is essential for acquiring and monitoring the various signals from industrial sensors. The problem is that the data storage and hardware size, so the multichannel data obtained is processed at runtime and stored in an external storage for future reference. The method of implementing the proposed design is by using the ARM Cortex M-3 Processor to reduce the hardware size. The Cortex M-3 attains high resolution. A Eight channel data acquisition processing (DAQP) and Controlling was designed, developed using the Lab VIEW graphical programming. The module was designed in order to provide high accuracy, storage and portability. The system designed is not specific for any sensor acquisition, so any sensor having signal conditioning circuit built can be connected to the DAQ (Data Acquisition System). ARM controller is used as heart of the DAQ.
A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique
Authors: Anitha M. , Joice J.Princy , Sheeba.I Rexlin
Published: April 2019

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.
An Efficient approach for Design and Testing of FPGA Programming using LabVIEW
Authors: Reddy Naresh Kumar , Suresh N.
Published: April 2019

Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.
Dynamic Partial Reconfiguration with FIR Filter Application
Authors: Astik Noopur
Published: April 2019

Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of Field Programmable Gate Array (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented
Design and Analysis of CMOS and Adiabatic 1:16 Multiplexer and 16:1 Demultiplexer
Authors: Anitha K. , Jayachira R.
Published: April 2019

Conventional CMOS is compared with two adiabatic logic styles namely Efficient Charge Recovery Logic (ECRL) and Improved Efficient Charge Recovery Logic (IECCRL). A 16:1 multiplexer and 1:16 demultiplexer using these design techniques are designed and results are compared based on their minimum/maximum power consumption and transistor count. The proposed schematics multiplexer and demultiplexer are simulated using Microwind2 and DSCH2 software.
Smart Safety Belt Design to Avoid Accidents in Hazardous Industrial Environment
Authors: Yaseen Muhammad , Khan Saad Qasim , Khurram Muhammad , N. Mubarak Rana
Published: April 2019

Warehouse is one of the most dangerous places to work because of many potential dangers. The accidents caused by heavy vehicles result in serious
injuries and even death. This paper proposes a solution to this problem. When a worker happens to be in any of such hazardous situations inside or outside workplace, he will press the emergency button (or pull a magnetic cord) placed in the smart safety belt which will not only stop the vehicles within 15 meters circle but also inform the workers within 250 meters circle through an indicator. In this technical paper, the outcome of first design phase has been reported. In the first design phase, we have successfully implemented a reliable and accurate ranging mechanism with ±0.3m maximum error. This ranging mechanism is based on wellknown RF Time-of-Flight (TOF) method. The maximum achievable transmit range of this solution is 300m.
FPGA Implementation of Automatic Irrigation and Pesticide Control System
Authors: Hanitha D. , Anusha B. , Prakash M. Durga
Published: April 2019

In many parts of the world rainfalls are inadequate to meet agricultural needs of farmers. It thus becomes imperative to use an irrigation system that meets the moisture needs of plants in order to increase food crop production. The system described here monitors the moisture and pesticide control needs of crops. Irrigation control is monitored through suitable moisture sensors and automatically pumps water when the need arises through FPGA control logic thus requiring minimal human interventions. We can also use this system for liquid pesticide supply through the selection. Thus, we achieve the efficient supply of water and pesticide as needed by plants and conserve quantity, energy and time. In this paper, the proposed system is designed using Verilog and implemented on FPGA. The system operation is also explained in DSCH (Digital Schematic) software. The system is very simple to operate and ideally suits the irrigation and pesticide need for green houses as well as farms.
FPGA Based Data Hiding Methods using DNA Cryptography Techniques
Authors: Krishna B. Murali , Surendra CH. , Varma K. Mani , Kanta K. Mani , Shabbeer S.K. , Madhumati G.L.
Published: April 2019

To convey the information safely DNA grouping mechanisms are used. There are many methods used by DNA sequences. The proposed method is of both encryption and information concealing utilizing a few properties of Deoxyribonucleic Acid (DNA) groupings. This technique is highlighted that DNA groupings have many more intriguing properties which are used for concealing the information. There are three strategies in this encryption strategy: the Insertion Technique, the Complimentary Pair Technique and the Substitution Strategy .For every single strategy, a specific reference DNA grouping P is chosen and then the taken sequence is changed over with the mystery message M and is consolidated, so that P0 is acquired. P0 is then sent to the collector and the beneficiary can recognize and separate the message M covered up in P. This technique is proposed to utilize INSERTION Strategy. Subsequently, the proposed plan comprises for the most part of two stages. In the principal stage, the mystery information is encoded utilizing a DNA Sequence. In the second stage the encoded information is steganographically covered up into some reference DNA grouping utilizing an insertion strategy. The effectiveness of this security algorithm is seen with many merits and limitations. A, C, G, and T are the 4 nucleotides which are taken for this project.
Design and Development of ARM based Electronic Test Evaluation System for RTO
Authors: Salokhe Shweta , Bombale U. L.
Published: April 2019

Electronic  test  evaluation  system  for  driving  license  is  very  useful  now  a  days,  as  there  is   increase  in  the  human  intervention  in  the  system.  This  system  make  the  driving  license  procedure  transparent  to  human  being. The  proposed  technological  solution  is advancement  towards    the  automation  of  system  and  improves  the  driving  test accuracy. As  a  contribution  to  society  this system  reduces  the  number  of  road  accidents occurs due to untrained drivers.
An FPGA Implementation of On Chip UART Testing with BIST Techniques
Authors: Gopal P Bala , Kishore K Hari
Published: April 2019

A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
Android Based Switch Controlling Technique for LED Bulbs Using Bluetooth/Wi-Fi Technology
Authors: Saikiran Munigoti , Nagaram Nagarajan Lalith , Bharath Malladi
Published: April 2019

This paper presents an efficient approach to switch on/off and control the intensity of an LED bulb from a remote place using Android Applications installed in a Smartphone. As LED household bulbs and lights are energy efficient, drop-in replacements for the incandescent lighting found in homes and offices. These lights produce a warm brightness while providing a significant cost savings over traditional lighting. Bluetooth & Wi-Fi modules are used simultaneously as an interface that make connection between Android Application and the LPC2148 controller by which the generated output can be viewed with the help of an LED bulb and control various other devices, based on the availability in particular areas.
NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm
Authors: Kalimuthu A. , Karthikeyan M.
Published: April 2019

A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique
Software and Hardware for managing Scratch Pad Memory
Authors: Hemdani Chabane , Aoudjit Rachida , Lalam Mustapha , Slimani Khaled
Published: April 2019

This paper proposes a low-cost architecture to improve the management SPM (Scratch Pad Memory) in dynamic and multitasking modes. In this context, our management strategy SPM based on Programmable Automaton implemented in Xilinx Vertex-5 FPGA is entirely different from prior research works. SPM is generally managed by software (by a strong programming logic or by compilation). But our Programmable Automaton facilitates access to SPM in order to move code or data and liberates space in SPM. After this step, software takes over content management of SPM (what part of code or data should be placed in SPM, locates spaces of Heap and Stack). So the performance of the programs is actually improved thanks to minimization of the access latency at the DRAM (Dynamic Random Access Memory or Main Memory).
CMOS Active Inductor Based Voltage Controlled Oscillator
Authors: P Patel Dhara , Oza Shruti , A Thakker Rajesh
Published: April 2019

A Tunable Active Inductor (TAI) based Voltage Controlled Oscillator (VCO) for Radio Frequency (RF) applications ranging from 670 MHz - 1.53 GHz is presented. A design of low phase noise and compact VCO is proposed. In order to lower the phase noise of VCO, its RF output power has been improved. The use of low voltage active in-ductor circuit reduces the power dissipation of VCO. The single ended CMOS active inductors with minimum number of transistors are used to consume less die area of VCO circuit. The low power dissipation of the circuit have high efficiency to generate output RF power. A supply independent variable current source tunes the VCO. The post layout design is simulated in Cadence spectreRF using TSMC 180 nm process libraries. The VCO circuit shows the phase noise variation from -124 to  - 126 dBc/Hz and an active area of 0.0049 mm2. The VCO core circuit, excluding output buffers, consumes 10 mW at 1.8 V supply voltage.
ARM Controller and EEG based Drowsiness Tracking and Controlling during Driving
Authors: Naresh B. , Rambabu S. , Khalandar Basha D.
Published: April 2019

This paper discussed about EEG-Based Drowsiness Tracking during Distracted Driving based on Brain computer interfaces (BCI). BCIs are systems that can bypass conventional channels of communication (i.e., muscles and thoughts) to provide direct communication and control between the human brain and physical devices by translating different patterns of brain activity commands through controller device in real time. With these signals from brain in mat lab signals spectrum analyzed and estimates driver concentration and meditation conditions. If there is any nearest vehicles to this vehicle a voice alert given to driver for alert. And driver going to sleep gives voice alert for driver using voice chip. And give the information about traffic signal indication using RFID. The patterns of interaction between these neurons are represented as thoughts and emotional states. According to the human feelings, this pattern will be changing which in turn produce different electrical waves. A muscle contraction will also generate a unique electrical signal. All these electrical waves will be sensed by the brain wave sensor and it will convert the data into packets and transmit through Bluetooth medium. Level analyzer unit (LAU) is used to receive the raw data from brain wave sensor and it is used to extract and process the signal using Mat lab platform. The nearest vehicles information is information is taken through ultrasonic sensors and gives voice alert. And traffic signals condition is detected through RF technology.
FPGA Implementation of High Speed Hardware Efficient Carry Select Adder
Authors: Saravanakumar Saravanakumar , Vijeyakumar Vijeyakumar , Sakthisudhan Sakthisudhan
Published: April 2019

This paper presents a novel architecture for high speed and hardware efficient carry select  addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.
Notice of Retraction Designing of Vedic Based Modulo Multiplication in Residue Number System
Authors: Akhter Shamim , Bareja Divya , Kumar Satyendra
Published: April 2019

Notice of Retraction

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After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles.

We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.

The presenting author of this paper has the option to appeal this decision by contacting ijres@iaesjournal.com.

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Residue Number System (RNS) is a very old number system which was proposed in 1500 AD. Parallel nature for mathematical operations in RNS results in faster computation. This paper deals with designing of modulo multiplication in RNS. Direct computation of |AB|m, requires multiplier to get A.B first and then Mod-m calculator to get the final result. We have used Vedic technique along with RNS to improve the computation time for modulo multiplication. This paper is aimed at designing and analysis of modulo multiplier for special moduli set like 3, 5 and 7. Comparative analysis in terms of area and delay is performed for input data size (N=8, 16 and 32-bit) between proposed technique and direct computation using Xilinx ISE 14.1. Design is also been compared using Synopsys Design Compiler with 32 nm Std_Cell Library. It is found that proposed technique is more efficient in terms of speed when input data size increases.
Impacts of Embedded Generation on Distribution Network Behavior
Authors: Sudhakar Puladasu , Malaji Sushama , Sarvesh B.
Published: April 2019

This paper explores the impacts of multiple embedded generators penetration on distribution system behavior. For this rationale, a IEEE-13 bus distribution feeder was modeled and investigates by assimilating different types of embedded generation (EG) sources. Different scenarios were implemented in which WIND, SOFC FUEL CELL, SOLAR and MICRO TURBINE plants were modeled with high variability of load and generation to observe their impacts on system’s protection, unsymmetrical faults also consider observing impacts effectively. To eradicate the impacts on distribution system with presence of EG’s and distribution system undergone in the event of faults, in this paper primarily reverse power due to EG integration is estimated and sensed with reverse power relay, Further two types of Superconducting Fault Current Limiters Passive resonance CB (PRCB) SFCL and Inverse current injection CB (I-CB are proposed and results are compared for amended solution in mitigating fault current magnitude and over voltages, Finally penetrations levels are computed mathematically and All the modeling and simulations were carried out using MATLAB SIMULINK tool.
Design and Implementation of LCG-Trivium Key Stream Generator into FPGA
Authors: Tchendjeu A. E Tchahou , Robert Tchitnga , Hilaire B Fotsin
Published: April 2019

This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 264 clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2144 bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.
Design of active inductor-based butterworth and chebyshev microwave bandpass filters in standard 0.18µm-CMOS technology
Authors: Mariem Jarjar , Nabih Pr. EL Quazzani
Published: April 2019

In this paper we propose a synthesis of microwave active filters having Butterworth and Chebyshev responses in the frequency range 1GHz-2GHz. The filter fundamental block, used to build an active inductor, consists of CMOS-based Operational Transconductance Amplifier (OTA) circuits. These amplifiers are made out of simple current mirror using MOS transistors. The simulation procedure has been carried out through PSPICE software showing good performances regarding scattering parameters in terms insertion losses, of out-of-band rejection and phase.
Design and software characterization of finFET based full adders
Authors: Hajare Raju , Lakshminarayana C.
Published: April 2019

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various  technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.
Entre el cine y la serigrafía: para una biografía sociológica de Andy Warhol
Authors: Rauschenberg Nicholas
Published: April 2019

Procuramos neste artigo reconstruir uma breve biografia sociológica de Andy Warhol, ícone da pop art. Nosso objetivo é identificar em sua trajetória uma dimensão performativa da objetivação como sujeito do campo do artista norte-americano. Warhol transformou um procedimento original – a serigrafia – em obra de arte. Se, por um lado, Andy encontrou um modo específico de estilizar fotografias, por outro, encontrou um modo de legitimar a reprodutibilidade das obras de arte para fins de mercado, isto é, transformou suas obras de arte em mercadorias produzidas em série. No entanto, Warhol, em seus trabalhos cinematográficos, desenvolveu uma perspectiva de gênero com base em sua estética cinematográfica que nos interessa ressaltar.
Revisitando la elección de Allende en 1970: lo que revelan encuestas aplicadas en la época
Authors: Mac-Clure Oscar , Garretón Manuel Antonio
Published: April 2019

A eleição de Allende como presidente do Chile em 1970, cujo governo foi derrubado três anos depois por um golpe militar, é o tema deste artigo. O período anterior à eleição de Allende é estudado, enfatizando a perspectiva das pessoas comuns, examinando, por um lado, a legitimidade do sistema político e, por outro, as percepções sobre a justiça social. São analisados os bancos de dados de pesquisas de opinião feitas no período eleitoral por um dos fundadores da sociologia no Chile. A análise desses dados permite uma abordagem sem precedentes das aspirações das pessoas ante os problemas do país nos meses que antecederam a eleição presidencial. Ao comparar o nível micro ou individual a partir de pesquisas com o discurso político ao nível macrossocial, o estudo contribui a reexaminar o período.
Urban Phenomena in São Paulo’s Nineteenth and Twentieth Centuries: Appropriating Local Spatio-Temporalities
Authors: Dorsch Sebastian
Published: April 2019

The article seeks to investigate urban phenomena in São Paulo’s 19th and 20th centuries by utilizing Henri Lefebvre’s concept of appropriation. Thus I focus on the relations between urban space(s) and its inhabitants, and the analysis of the city – usually perceived as space – becomes a spatio-temporal and relational analysis regarding dynamic practices, conflicts, etc. understood as urban phenomena. How did the inhabitants appropriate São Paulo? May we state special forms by comparing it to other Latin American cities of former times? How did the migrants arriving at the end of 19th century change old forms of living in the city? I conclude with remarks and critics on the potential of using the concept of appropriation in urban studies.
Brasília classificada: novos espaços de classe média na capital federal
Authors: Moura Cristina Patriota de , Januzzi Vinicius Prado
Published: April 2019

Este artigo tem como proposta pensar aspectos do “fazer-cidade” (Agier, 2015) a partir do estabelecimento de áreas residenciais destinadas a membros das camadas médias em Brasília. Iniciamos com uma discussão acerca da história de proposição e ocupação residencial do Plano Piloto para em seguida pensar com base em duas experiências de trabalho de campo antropológico vividas em anos recentes, notadamente nos condomínios horizontais estabelecidos no início do presente século e no recém-inaugurado Setor Noroeste, cuja construção foi possibilitada pelo Plano Diretor de Ordenamento Territorial aprovado em 2009. O argumento central é que, em seu processo de consolidação e expansão, a “nova capital” brasileira vem se caracterizando, cada vez mais, pela condição de classe de seus moradores, em processo que denominamos de classificação do espaço.
Descompassos de uma etnografia : sobre os passados presentes de um bairro
Authors: Cordeiro Graça Índias
Published: April 2019

Com o objetivo de discutir a relação entre etnografia, história e memória, especificamente no que se refere ao modo como o ‘passado’ é percecionado, representado e usado no presente, projetando-se no futuro, o artigo reflete criticamente sobre uma pesquisa realizada nos anos 1990 sobre um bairro histórico e “popular” de Lisboa. O modo como diferentes tipos de temporalidades e de memórias são estrategicamente evocadas sob a forma de “mito de origem” ou de “marcha popular”, contribuindo para a definição de um pequeno território “tradicional” urbano, e o papel ativo que o processo etnográfico desempenha neste processo são alguns dos pontos analisados.
A New Species of the Genus Eulophias (Zoarcoidei: Stichaeidae) from Korea
Authors: KWUN HYUCK JOON , KIM JIN KOO
Published: April 2019

A new species, Eulophias koreanus, belonging to the family Stichaeidae, suborder Zoarcoidei, is described on the basisof five specimens (70.7–160.7 mm in standard length) collected from the southern sea of Korea. The new species differsfrom the only two known congeneric species, Eulophias tanneri and Eulophias owashii, which are endemic to Japan. Eu-lophias koreanus is readily distinguished from E. tanneri by the numbers of anal-fin rays (102–103 vs. 75 in E. tanneri)and caudal-fin rays (9–10 vs. 7). Eulophias koreanus is more similar to E. owashii than to E. tanneri, but differs from theformer in the number of vertebrae (141–143 vs. 133 in E. owashii) and pectoral-fin length (36.1–39.5% of HL vs. 27.8%).Regarding the caudal skeletons in E. koreanus, the last dorsal pterygiophore is inserted between the last 1st and 2nd or the2nd and 3rd neural spines, and a small spine is absent on the ventral portion of the parhypural, whereas in E. owashii, thelast dorsal pterygiophore is inserted between the last 3rd and 4th neural spines, and a small spine is present on the ventralportion of the parhypural. Analyses of 500-bp sequences of mitochondrial DNA cytochrome oxidase subunit I providestrong evidence that the five new specimens belong to the same species, even though they show some variation in head shape.
Two new species of the genus Celyphoma Emeljanov, 1971 (Hemiptera: Fulgoromorpha: Issidae) from China
Authors: MENG RUI , WANG YINGLUN
Published: April 2019

Two new species of the genus Celyphoma Emeljanov, 1971 in the tribe Issini, C. quadrupla sp. nov. and C. bifurca sp. nov., are described and illustrated. In addition, the male and female reproductive systems of C. quadrupla sp. nov. are described. A key to all 26 species in the genus is provided.
First record of the genus Kimulodes Tjeder & Hansson in West Africa with description of a new species (Neuroptera, Ascalaphidae)
Authors: MICHEL BRUNO
Published: April 2019

The genus Kimulodes was described by Tjeder and Hansson (1992) to accommodate two species, Kimulodes sinuatus originally described as Helicomitus sinuatus by Kimmins (1949) and a new species they named K. angulicornis. Within the tribe Ascalaphini, this genus is characterized by the hairless genae, the absence of a tuft of hairs at the base of the forewing in males, in contrast to the African species of Ascalaphus, and the antennae of males being sinuate or sharply arched with stout tufts of hairs on the basal flagellomeres. The genus Kimulodes was known from Central and East Africa, but remained unrecorded from West Africa. The material collected by a colleague, Jean-Michel Maldès (CIRAD), during a prospecting mission in Togo in 1990 included a male of an undescribed species of Kimulodes, which is described below. Furthermore, examination of the collection of the Museum National d’Histoire Naturelle in Paris, yielded a male and a female of K. angulicornis from an unrecorded locality in the Central African Republic.
Tanaidacea (Crustacea) from Macaronesia III. The shallow-water Tanaidomorpha from the Cape Verde archipelago
Authors: LARSEN KIM , NAGAOKA RYOKO , FROUFE ELSA
Published: April 2019

Three new species of Tanaidacea are described from the Cape Verde archipelago in the Mid-Atlantic, collected during thesampling program of the Laboratory of Marine Community Ecology and Evolution (LMCEE) to Macaronesia and formerPortuguese colonies. The new species belong to the tanaidomorphan families Leptocheliidae (Leptochelia parasavignyi), Paratanaidae (Paratanais vicentetis), and Pseudotanaidae (Pseudotanais Akanthinotanais breviaquas).
A new species of Polypedates Tschudi (Amphibia, Anura, Rhacophoridae) from Sri Lanka
Authors: WICKRAMASINGHE L. J. MENDIS , MUNINDRADASA D. A. I. , FERNANDO PRITHIVIRAJ
Published: April 2019

A new species of frog tentatively assigned to the genus Polypedates is described from the Gilimale forest reserve of theSabaragamuwa province of Sri Lanka. This tree frog is characterized by unique osteological characteristics in the skullwhich distinguish it from all other congeners, such as the presence of a series of maxillary teeth progressively changingorientation from horizontal to vertical from posterior end to anterior; a laterally-curved spine in the quadratojugal bone;and bony co-ossification on the skull resulting in four dorsal spines which are externally seen as protrusions in the parietalarea. Bioacoustic observations of Polypedates ranwellai sp. nov. revealed three distinct call types. High rates of deforestation and anthropogenic activities at the type locality threaten the survival of the species.
Phylogenetic Relationships of Species of Hypselobarbus (Cypriniformes: Cyprinidae): An Enigmatic Clade Endemic to Aquatic Systems of India
Authors: ARUNACHALAM M. , RAJA M. , MURALIDHARAN M. , MAYDEN RICHARD L.
Published: April 2019

Very little is known about the diversity and systematics of the genus cypriniform genus Hypselobarbus. Currently, the genusincludes at least eleven species, all endemic to freshwater systems of Peninsular India. While these species are commonlyknown in India and are frequently used as a food source, little is known about the morphological diversity within and betweenspecies and nothing is known regarding intraspecific genetic diversity or species relationships. Herein, we examine the geneticdiversity in the genus for 11 mitochondrial genes for eleven populations representing nine of the known 11 species.Hypselobarbus is resolved as monophyletic, with the inclusion of P. carnaticus, and species relatioships are very stronglysupported. Because of the unambiguous relationships strongly supported B. carnaticus is allocated to Hypselobarbus. Thisresearch and ongoing morphological and molecular work with the genus supports the existence of additional new species inpeninsular India in need of further molecular and morphological study. Genetic diversity in the genus is high; for the twospecies wherein more than one sample, and the two of each are suspected to represent undescribed taxa, these populationsexhibited greater genetic divergence than that observed between any two of the other currently recognized species,corroborating our hypothesis based on morphological evidence. Clearly the genus warrants more thorough geographicsampling and examination of morphological and molecular data/analyses to reveal the natural lineages existing in this endemic and enigmatic genus.
A new species of Catapagurus A. Milne-Edwards (Crustacea: Decapoda: Anomura: Paguridae) from Brazil, with a key to the western Atlantic species
Authors: NUCCI PAULO RICARDO , DE MELO GUSTAVO AUGUSTO SCHMIDT
Published: April 2019

We describe herein a new species of Catapagurus, the twenty-second species of the genus. This is the third species ofCatapagurus recorded from the western Atlantic and the second from Brazil; the remaining 19 species occur in the IndoPacific region.
First record of Kamimuria (Plecoptera: Perlidae) from Hainan Island of China, with description of K. hainana n. sp.
Authors: LI WEIHAI , WANG LIUHAO , YU HAO
Published: April 2019

The genus Kamimuria is reported from Hainan Island, China for the first time with K. hainana sp. nov. described as new to science. The taxonomic relationship with similar species is discussed.