bluuebunny/crossref_metadata_2025 huggingface dataset:
Oxygen Reduction and Evolution Examined Using Quartz Crystal Microbalance and Electrochemical Methods in Non-Aqueous Li-O2 Batteries
Authors: Lindberg Jonas , Wickman Björn , Lindbergh Göran , Behm Mårten
Published: February 2020

The Lithium-Oxygen battery is one of the most promising battery technologies being researched, it is also one of the more challenging ones due to the various problems associated with the battery. One of these problems is the poor understanding of the reaction occurring during oxygen reduction and evolution. It is known that the intermediates of the reaction are highly reactive and take part in unwanted side reactions. It is also known that the oxygen reduction products are poorly soluble in the electrolyte.

This study sets out to further examine these effects. Qualitatively these aspects are somewhat known but quantitatively the answer is less straight forward. By combining a Quartz Crystal Microbalance with electrochemical techniques the mass, current and voltage can be measured simultaneously to help shed further light on the species solubility and occurrence of side reactions. Obtaining this information about the chemical nature of the species formed will serve as a well needed compliment to the more frequently used surface characterization methods used when trying to determine the reactions occurring at the oxygen electrode.
New Metal Phosphide with Topotatic Reaction As an Anode Material for Lithium Ion Rechargeable Battery
Authors: Lee Sang-Min , Sim Sungju , Kim Jeom-Soo , Park Gumjae
Published: February 2020

The current level of performances of Lithium Ion Batteries (LIBs) is not enough to meet commercial demands for new applications(xEV, ESS), in particular, with respective to energy density. Graphite and hard carbons are commonly used as a negative electrode material for LIBs, but higher-capacity alternatives are being consistently sought due to their limited capacity as an anode material of next generation LIBs for large-scale power applications. Recently, various Si, and Sn based compound including transition metal oxide, multiphase alloy, and intermetallic compounds have been extensively studied as alternatives to the existing carbon based anode material. These materials show much higher capacities than those of carbonaceous material. However, they are suffering from huge lattice volume change (4.4Li+Si ® Li4.4Si, ΔV>300%) through conversion reaction mechanism during Li insertion, which results in poor cycle life of LIBs.

In this respect, metal phosphides have been alternatively suggested as a promising anode material for their reversibility, and large amount of lithium uptake at relatively low potential. It is not clarified yet until now, but the electrochemical reaction in metal phosphides with lithium might be classified into two reaction mechanisms, depending on electronegativity difference between metal and phosphorous atoms. Obviously, the large difference in electronegativity between constituting elements inevitably brings about decomposition of host composition (structure) with lithium intercalation, which can be readily understood by considering the Gibbs formation free energy. Even if being composed of elements with the very small difference in electronegativity, however, the reaction mechanisms are different with chemical stoichiometry of metal phosphides (MPx). In case of SnPx (Electronegativity : Sn=1.96, P=2.19) intermetallic compounds, the SnP0.75 equilibrium phase shows typical conversion reaction mechanism, on the other hand, SnP0.94metastable phase has been observed to be on intercalation reaction mechanism during lithiation process [1,2].

In this work, we have investigated the reaction mechanism of MoPx(Electronegativity : Mo=2.16, P=2.19) with various stoichiometry, relating with electrochemical properties. We finally propose newly designed metal phosphide with ternary composition showing topotatic reation.

References

[1] Young-Ugk Kim, Churl Kyung Lee, Hun-Joon Sohn, and Tak Kang, Journal of The Electrochemical Society, 151 (2004) A933-A937

[2] Youngsik Kim, Haesuk Hwang, Chong S. Yoon, Min G. Kim, and Jaephil Cho, Adv. Mater.19 (2007) 92–96
Electrochemical Performance of Dual Doped Li4Ti5O10 for Use at Anodes of Lithium Ion Batteries
Authors: Cetin Deniz , Hua Keping , Gopalan Srikanth
Published: February 2020

Formation of solid electrolyte interphase (SEI) increases the cell internal impedance and reduces the charge rates in lithium ion batteries (LIB) and causes significant cell performance limitations.  Lithium titanate, Li4Ti5O10 , (LTO) is a promising lithium storage material for anodes that does not form SEI, but it suffers from poor charge and discharge rates which arise from low lithium ion and electron conductivity at operation temperatures.

In order to improve the performance of the LIB anode, ionic and electronic conductivities should be enhanced. We present a  novel approach in this work to simultaneously increase the ionic and electronic conductivities by dual doping of LTO.  Doped materials are synthesized at temperatures higher than 800°C and analyzed using electrochemical impedance spectroscopy.
SnOx/Carbon Core Shell Structure: An Efficient Anode for Rechargeable Sodium Ion Batteries
Authors: Kalubarme Ramchandra S. , Park Ga-Eun , Park Chan-Jin
Published: February 2020

Lithium-ion batteries have been widely used as energy storage media in portable electronic devices, electrical vehicles, hybrid electrical vehicles, etc. In particular, they have become indispensable energy storage devices for intermittent energy conversion applications such as solar cells and wind power. However, the low abundance and uneven distribution of lithium resources show the potential difficulties of the long-term and large-scale applications of lithium-ion batteries in aspects of their availability and cost. Accordingly, the development of new types of batteries, such as sodium-ion and magnesium-ion batteries, is necessary. Among them, sodium (Na)-ion batteries (NIBs) possess electrochemical working principles that are similar to LIBs. In addition, sodium is inexpensive and abundant. Therefore, NIBs could substitute LIBs in applications such as smart grids and large-scale energy storage for renewable solar power and wind power.

The major obstacle in realizing NIBs has been the absence of suitable anodes. Most of all, graphite which has been a commercially well-known anode material for LIBs cannot be used as an insertion host for Na ions due to their large ionic size. Moreover, only few noticeable studies on negative electrode materials, e.g., lead and hard carbon have been reported thus far. Metal oxides are considered to be important electrode materials, as they follow a conversion reaction mechanism. However, metal oxides suffer from several problems when used as anode materials which limit their use, such as swelling and shrinking of active material particles upon the insertion and extraction of Li+ or Na+ ions, which can induce poor contact between the active materials and the electron conducting agents, leading to low electric and ionic conductivity.

In this study, we report the electrochemical activity of carbon coated SnOx nanostructures for NIBs. The nanostructured SnOx were synthesized by a hydrothermal method and their surfaces were coated by carbon to improve the electric conductivity. The effect of solvent used for hydrothermal process and annealing temperature on the structure, morphology and Na storage capacity was investigated. The single phase SnO2 was obtained using ethanol solvent, while the blend of SnO and SnO2 was obtained using DI water and ethylene glycol solvents. The transmission electron microscopic images conform the presence of carbon coating on the SnOx nanoparticles. Further, the anodes made of carbon coated SnOx prepared in ethanol solvent exhibited stable cycling performance and attained the capacity of about 443 mAh/g in the first charge. With the help of the conductive carbon, the carbon coated SnO2 delivered more capacity at high rates; 257 mAh/g at the 1 C-rate, 156 mAh/g at the 5 C-rate and 70 mAh/g at the 10 C-rate. The excellent cyclability and high-rate capability are attributed to the formation of a mixed conducting network and the uniform carbon coating formed on the SnO2 nanoparticles.
3D Nanoarchitecture of Ge/C Core-Shell for Ultra-High Rate Anode for Lithium Ion Batteries
Authors: Ngo Duc Tung , Lee Jae-Young , Park Chan-Jin
Published: February 2020

The mobile world depends on lithium ion batteries (LIBs), which provide portable power for variety of applications, ranging from personal electronic devices such as laptops, mobile phones and digital cameras to electric vehicles due to their high energy density, low self-discharge and long cycle life.

Currently, the anode material in commercially available LIBs is made of graphite, which has the specific capacity of 372 mAh/g, but it cannot meet the world’s growing demand for batteries with higher energy density, power density and rate capability. For further increasing the energy and power density of LIBs, the replacing graphite carbon anode by new advanced materials with higher reversible capacity and rate capability as well as long-term cyclability is considered an attractive route. In this context, the lithium alloys based material emerged as a promising alternative candidate to replace graphite as an anode material for LIBs due to their high specific capacity.

Here, we propose a facile method to prepare 3D nanoarchitecture of carbon coated Ge (3D-Ge/C) using simple method. The 3D-Ge/C constructed from secondary particles of Ge/C composite with diameter of about 100 nm that composed of nanometer-size (~10 nm) primary particles of Ge coated with carbon. Through carbon coating on the nanosized Ge, the aggregation of Ge particles in nano scale is completely prevented. As a result, outstanding capacity and rate capability can be achieved with this structure, 3D-Ge/C exhibited a high reversible capacity of 1604 mAh/g at the rate of C/10 after 100 cycles and excellent rate capability. In particular, at high rate of 100C (160 A/g) the average capacity of 1122 mAh/g was observed and at ultrahigh rate of 400C (640 A/g) the average capacity of 429 mAh/g was recorded.
New Flame-Retardant Composite Separators Based on Metal Hydroxides for Lithium-Ion Batteries
Authors: Daeyong Yeon , Lee Yunju , Cho Insung , Song Seonghyun , Ryou Myung-Hyun , Lee Yong Min
Published: February 2020

In order to enhance the thermal stability of conventional polyolefin separators, we propose a novel composite separator based on metal hydroxides. In particular, metal hydroxides not only function as a thermally stable mechanical matrix like alumina (Al2O3) or silica (SiO2) but also flame retardant due to their ability to release absorbed water molecules under some accidental conditions (e.g. higher than 200 oC).

 The flame-retardant composite separators are prepared by coating both sides of a microporous polyethylene (PE) membrane with nano-sized metal hydroxide (Al(OH)3 and Mg(OH)2) ceramic powders and poly(vinylidene fluoride-co-hexafluoropropylene) PVdF-HFP binder. Their physical properties are evaluated via scanning electronic microscopy (SEM) for surface morphology, the densometer to measure Gurley number (permeability), electrochemical impedance spectroscopy for ionic conductivity, and uptake amount of liquid electrolyte for wettability. In addition, the flame retardancy of composite separator is investigated by measuring the extinction time. Furthermore, the electrochemical properties of composite separators are evaluated with lithium-ion cells composed of a graphite anode and a LiCoO2 cathode. Comparing to bare separators, the composite separators show improved flame retardancy and rate performances due to water release property and better electrolyte wettability, respectively.

Acknowledgement

This research was financially supported by the Ministry of Education, Science and Technology (MEST) and National Research foundation (NRF) of Korea through the Human Resource Training Project for Regional Innovation (2014066977) and This research was ﬁnancially supported by Chungcheong Leading Industry Promotion Project of the Korean Ministry of Trade(R0001485).
MoO2/Mo2C hybrid Nanowires As Anode Materials for High Performance Lithium Ion Batteries
Authors: Yang Lichun , Sun Wei , Zhong Zhiwei , Wang Yukun , Gao Qingsheng , Zhu Min
Published: February 2020

Molybdenum oxides, mainly including MoO3 and MoO2, are attractive materials with potential applications in catalysis, sensors and energy storage. Owing to the good electronic conductivity, high stability and density, MoO2 was proposed as a host material for lithium ions. However, the application of MoO2 as anode material for lithium ion batteries was limited in the early research, due to the low capacity and poor cycling stability resulting from the bulky dimensions, the consequential slow kinetics and huge volume changes during the charge/discharge process. To improve the performance of MoO2, a most promising way is to design and construct nanostructured composites[1-3].

   Here we report on a facile synthesis of MoO2/Mo2C hybrid nanowires through simple calcination using MoOx/amine nanowires as a precursor. The small diameters of the nanowires ensure fast lithium ion insertion and extraction, while the long dimensions benefit good electron transport between wires. Besides, The electrochemical inactive Mo2C with a high specific conductance distinctly increases the structural stability and electronic conductivity of the hybrid nanowires. As a result, the cycling and rate performance of the hybrid nanowires is remarkably enhanced. At a current density of 1000 mA/g, a discharge capacity of ~ 700 mAh/g is still retained after 300 cycles, which indicates the MoO2/Mo2C hybrid nanowires a promising anode material for high performance lithium ion batteries.

Acknowledgements

This work was financially supported by the National Natural Science Foundation of China (Nos. 51402110, and 51231003), and the Fundamental Research Funds for the Central Universities (2013ZM0002).

References

[1] Q.S. Gao, L. C. Yang, X. C. Lu, J. J. Mao, Y. H. Zhang, Y. P. Wu, Y. Tang, J. Mater. Chem., 2010, 20, 2807.

[2] L.C. Yang, L. L. Liu, Y. S. Zhu, X. J. Wang, Y. P. Wu, J. Mater. Chem., 2012, 22, 13148.

[3] H. J. Zhang, K. X. Wang, X. Y. Wu, Y. M. Jiang, Y. B. Zhai, C. Wang, X. Wei, J. S. Chen, Adv. Funct. Mater., 2014, 24, 3399.
Bottom-up Synthesis of Copper Fluoride Nanocomposites and Their Application to Rechargeable Li Batteries
Authors: Chun Jinyoung , Kim Youngsik , Lee Jinwoo
Published: February 2020

Copper fluoride (CuF2) is one of the attractive cathode candidates for rechargeable Li batteries that have high theoretical operation potential (3.55 V vs. Li/Li+) and large specific capacity (528 mAh/g). However, synthesizing nanostructured CuF2, as well as harnessing its potential rechargeability, has been a challenge because of it inherent chemical and electrochemical properties. Only top-down approaches have been reported for down-sizing CuF2, and there are no reports on reversible electrochemical performance of CuF2 even at the first several cycles. Herein, we report a facile and versatile synthetic method for CuF2/mesoporous carbon nanocomposites and their application to the cathodes of rechargeable Li batteries. Through heat treatment with NH4F in a solventless system, CuF2 was easily synthesized from various copper precursors. CuF2 nanoparticles confined in mesoporous carbon exhibited not only superior specific capacity and rate capability at the first discharge in the normal coin-type cell, but also promising cycle performance in the solid-electrolyte-incorporated cell. To the best of our knowledge, this is the first report in which nanostructured CuF2 is synthesized using a bottom-up approach and successfully applied to rechargeable Li batteries.
Advanced Electron Microscopy of Layered-Oxide Cathode Materials
Authors: Phillips Patrick J , Kim Chunjoong , Bareno Javier , Yi Tanghon , Cabana Jordi , Abraham Daniel P , Klie Robert F
Published: February 2020

The role of aberration-corrected scanning transmission electron microscopy (STEM) in materials characterization is examined with respect to layered-oxide cathode materials for battery applications. STEM-based methods are quickly becoming the most promising characterization tools for these materials, owed largely to the wide-range of techniques available on advanced STEM instruments, including the direct imaging of both heavy and light elements, and both energy-dispersive X-ray (EDX) and electron energy loss (EEL) spectroscopies. The current talk will focus on multiple materials, including Li- and beyond Li-ion oxides, characterized via STEM methods, in pristine, cycled, and in-situ irradiated states. The latter allows for single particle tracking of the dynamic processes occuring upon Li and O loss from the material. Various imaging modes, including high/low angle annular dark field (H/LAADF) and annular bright field (ABF), in conjunction with EELS/EDX, will be used extensively for this analysis, while parameters such as Mn valence, O presence, and light element occupation and intercalation will be discussed.
Investigation of Graphite/Tin Phosphide Composites As the Potential Anode in Li-Ion Batteries
Authors: Li Zhe-Fei , Xie Jian
Published: February 2020

Driven by the rapidly-growing of hybrid and electric vehicles, there is an increasing demand on lithium ion batteries (LIBs) with high energy density, long cycle life, and low cost. One of the most widely used anode materials in LIBs, graphite, only possesses a theoretical specific capacity of about 370 mAh/g, limiting the specific energy of LIBs.1 Recently, conversion-type of electrode materials, i.e. metal oxide and metal sulfide, has been regarded as one of the most promising anode materials for high performance LIBs, due to the low cost and exceptionally high specific capacity (>1000 mAh/g).2 However, these conversion-type electrode materials suffers from several issues, i.e. relatively low conductivity and rapid capacity fade due to irreversible phase change and particle pulverization during cycling. For example, the poor performance of tin oxide is mainly caused by its low intrinsic conductivity, formation of irreversible insulating Li2O phase during discharging, and large volume change.3 To overcome these disadvantages, various methods have been developed, like carbon/tin oxide composites, tin phosphide (Sn4P3). Tin phosphide has a layered structure and can be prepared by a mechanochemical or hydrothermal method. It has shown promising electrochemical performance as the anode in Li-ion batteries.4,5 As the lithium was inserted, Sn4P3 was first converted into lithium phosphides and Sn, followed by lithium-tin alloy formation. The advantage of Sn4P3 is its high capacity and Li+ conductivity of the Li3P. However, it suffers from similar drawbacks as tin oxide, i.e. large volume change and irreversible Li3P phase formation.

In this work, we prepared Sn4P3 nanowires by hydrothermal reaction of red phosphorus and tin in ethylenediamine at 200 °C for 40 h. Then, graphite/Sn4P3 composites were prepared by high-energy ball milling for 2 h under Ar atmosphere. Graphite and Sn4P3 were uniformly distributed in the composites, shown in Figure 1a. When tested as the anode materials, the composites showed superior performance compared to Sn4P3 alone. The capacity of Sn4P3 rapidly decreased to around 200 mAh/g after 15 cycles. In comparison, graphite/Sn4P3 composites showed an initial specific capacity of about 1014 mAh/g and maintained a capacity of 782 mAh/g after 50 cycles. In addition, the coulombic efficiency was also much higher in the graphite/Sn4P3 composites, indicating a reversible Li insertion/deinsertion behavior and more stable SEI layer.  The rate performance of graphite/Sn4P3 composites was also much better than pure Sn4P3. In conclusion, we report a facile preparation of graphite/Sn4P3 composites with excellent electrochemical performance as anode material in Li-ion batteries.

Figure 1
About the Thermodynamics of LixCoO2 in the Metal-Insulator Two-Phase Region Derived from DFT Calculations
Authors: Dang Siaufung Oliver , Markus Isaac Manny , Asta Mark , Singheiser Lorenz
Published: February 2020

Although LixCoO2 has been in use as cathode material in Lithium-ion batteries for quite some time the mechanisms responsible for its cycling behavior are not completely understood. In practice only about 50 % of its theoretical capacity is accessible without rapid deterioration of cathode performance due to changes in the crystal structure. Moreover, its performance as a cathode material is known to be significantly influenced by the metal-insulator transition within a compositional range of x in [0.75; 0.94]. This concentration range marks the 2-phase region within which the cathode potential exhibits a plateau in agreement with the Gibbs’ phase rule.

Up to now this transition has never been modeled by ab initio calculations due to the lack of feasible straight-forward methods for strongly correlated materials to account for the interactions of the open-shell d-electrons as they exist in LixCoO2. In this work the ambition is to capture the 2-phase region by running a number of calculation series on various compositions within the 2-phase-region by using the GGA+U approach. The space of magnetic configurations is sampled and results are analyzed with respect to metallic and semiconducting properties. Convex hulls are drawn through the acquired data points in a total energy versus Lithium-concentration plot for the metallic and semiconducting states. The common tangent of both convex hulls will pinpoint the borders of the two-phase region.

The successful DFT-modeling of the metal-insulator transition is of particular interest since effects of dopants on this region could be studied. Especially the effect on the potential and the compositional range of the region would be leading aspects to look at since a higher potential and a broader two-phase region are beneficial for the cathode’s overall performance.
(Invited) Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs
Authors: Schenk Andreas , Sant Saurabh , Moselund Kirsten , Riel Heike
Published: February 2020

The Tunnel Field Effect Transistor (TFET) which utilizes the band-to-band-tunneling (BTBT) generation current of a gated diode is regarded as promising candidate for ultra-low power circuits. TFETs with different geometries and operation modes have been proposed. In this work, we study different hetero-structure systems - InAs/Si and all-III-V (In0.53Ga0.47As/InP, InAs/GaSb) - and compare their performance in TFET applications. First, we evaluate the TCAD model by simulating realistic structures as the one shown in Fig. 1 and compare the results with measured current-voltage (IV) characteristics. Then we focus on 2D double-gate TFETs with gate-overlapped-source geometry (Fig. 2) which capture the essential physics.

The TEM image of an InAs/Si nanowire p-TFET fabricated at IBM Research-Zurich is shown in Fig. 1. The n-doped InAs source (ND=2e18cm-3) is overlapped with the gate to increase “line” (under-the-gate) tunneling. Geometry and doping profile of a p-TFET used for the simulations are displayed in Fig. 2(a). The source donor concentration is at its optimum for minimum sub-threshold swing (SS), the corresponding value for the In0.53Ga0.47As/InP  p-TFET being ND=1e19cm-3. The distributions of the electron and hole BTBT generation rates in the sub-threshold regime are shown in Fig. 2(b) and Fig. 2(c) for both material systems. One observes that BTBT takes place along the line tunnel path in the In0.53Ga0.47As/InP TFET while it occurs primarily along a “point” tunnel path (in-junction, inter-material) in the InAs/Si TFET. This is a result of the opposite signs of the valence band offset in the two hetero-systems. The different dominant tunnel paths result in different transfer characteristics as shown in Fig. 3. In bulk-like devices, the point tunneling rate is expected to change less rapidly than the line tunneling rate. Hence, the SS (averaged over 3 decades above 1e-9A/µm) of the InGaAs/InP TFET is slightly smaller than that of the InAs/Si TFET (47.3 vs 48.5). The difference is more pronounced in n-channel TFETs formed with the same set of hetero-systems. Also the current I60 (ID@ SS=60mV/dec) is comparable (6e-9A/µm vs 2e-9A/µm). In the simulations, the effect of the diffusion barrier of the InGaAs/InP hetero-system has been minimized by a proper composition gradient.

In addition to the above effects, the quality of the interfaces will affect the IV characteristics. The lattice-matched In0.53Ga0.47As/InP interface is expected to exhibit a lower trap density than the highly mismatched InAs/Si interface. We will demonstrate the effect of trap-assisted tunneling on the TFET performance.

Figure 1
Direct Characterization of Impact Ionization Current in Silicon-on-Insulator Body-Contacted MOSFETs
Authors: Marquez Carlos , Rodriguez Noel , Montes Jose Manuel , Ruiz Rafael , Gamiz Francisco , Sampedro Carlos , Ohata Akiko
Published: February 2020

Impact Ionization (I.I.) is an inherent phenomenon of very scaled MOSFET devices operated at a high lateral electric field regime (VD=VDD
). From the Silicon-On-Insulator prospective, it leads, not only to possible reliability issues arisen from the hot carrier generation, but also to the accumulation of charge in the body of the transistor [1]. This particularity yields a set of effects that depending on the application may be desirable or not; among them: kink effect, body-to-source junction forward biasing or bipolar triggering [3].

The use of body-contacted devices has allowed us the direct monitoring of the Impact Ionization phenomenon in two sets Silicon-On-Insulator transistors: Devices with silicon film thickness TSi=7nm and Buried Oxide Thickness of TBOX=145nm, and devices with TSi=26nm and TBOX=10nm. Both of them fabricated in a 22nm process at CEA-LETI facilities.

Two types of measurements have been conducted by applying different contour conditions to the body-contacted device:

i) Zero-current measurements, have led to determine directly the evolution of the potential of the body (Figure 1), disclosing the conditions were the accumulation of positive charge rises the body potential up the point where the body-to-source junction is triggered.

ii) Zero-potential measurements, draining the impact ionization hole current through the body-contact. This has allowed a precise reconsideration of the commonly accepted models to describe the phenomenon (Figure 2).

From our study, an updated set of constants have been extracted for the calibration of the models [3]. The updated models (Selberherr and Crowell-Sze impact ionization [4]) have been validated comparing experimental data with commercial ATLAS-Silvaco simulations (Figure 3) for devices with different channels lengths and bias conditions.

The outcome of this work provides further insight on the I.I. in thin and ultrathin SOI devices, developing a new protocol for its electrical characterization. The updated models will be essential for the proper description of the phenomenon in TCAD tools.

[1] B. Vandana, International Journal of Modern Engineering Research, (IJMER), 2013.

[2] S. Cristoloveanu, S. Li, Kluwer Academic Publishers, 1999.

[3] S. Krishnan and J.G. Fossum, Solid-State Electronics, 39, 5, 1996.

[4] Atlas users manual, Silvaco International 2010.

Figure 1
(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics
Authors: Zhao Qing-Tai , Richter Simon , Knoll Lars , Luong Gia Vinh , Blaeser Sebastian , Schulte-Braucks Christian , Schäfer Anna , Trellenkamp Stefan , Buca Dan , Mantl Siegfried
Published: February 2020

Band-to-band tunnel-FETs (TFETs), which can break the 60mV/dec limit for MOSFETs are very attractive for low power applications.   It is expected that TFET circuits will outperform subthreshold electronics at voltages around 0.2 V. However, the fabrication of well and equivalently performing n- and p-type TFETs is still a great challenge. The lack of steep junctions and occurrence of trap assisted tunneling (TAT) are the major obstacles to achieve steep slopes.

In this paper, we will present Si nanowire TFETs. Emphasis will be placed on strained silicon n- and p-type nanowire TFETs, TFET inverters and NAND logic. We developed a simple process using ion implantation into silicide and dopant segregation (DS) to make steep tunneling junctions. TFETs with a minimum inverse subthreshold slope of 30mV/dec have been realized with trigate configuration, as shown in Fig.1. Gate all around (GAA) TFETs with nanowire diameter down to 10nm were also fabricated (Fig.2). High on-currents of ~64µA/µm at VDS=VOV=-1.0V were achieved for p-TFETs [2]. We could show that scaled NW devices with multi-gates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path.

Inverters with complementary TFETs (C-TFET) are also presented in this paper. The C-TFET inverters show a sharp transition at a very low Vdd=0.2V (Fig.3). The experimental results of GAA p-TFET inverters and NAND demonstrate a potential of TFET for low power applications with Vdd<0.2V (Fig.4).

Finally TFETs for analog applications and perspectives of Si-Ge-Sn TFETs will be presented.

Acknowledgement: The research leading to these results has received funding from the European Community’s Seventh Framework Programme under grant agreement No. 619509 (project E2SWITCH) and the German BMBF project “UltraLowPower” (16ES0060K).

References

[1]  L. Knoll, Q.T. Zhao, A. Nichau, S. Trellenkamp, S. Richter, A. Schäfer, D. Esseni, L. Selmi, K. K. Bourdelle, and S. Mantl, Electron Device Letters, IEEE, vol. 34, no. 6, pp. 813–815, 2013.

[2] L. Knoll, Q.T. Zhao, A. Nichau, S. Richter, G. Luong, S. Trellenkamp, A. Schäfer, L. Selmi, K. Bourdelle, and S. Mantl,  IEDM Tech. Dig., p4-4, 2013.

Figure 1
(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs
Authors: Lee Rinus T.P. , Loh Wei Yip , Tieckelmann Robert , Orzali Tommaso , Huffman Craig , Vert Alexey , Huang Gensheng , Kelman Maxim , Karim Zia , Hobbs Chris , Hill Richard J.W. , Papa Rao S.S.
Published: February 2020

III-V semiconductors have emerged as a leading candidate to replace Si as channel material in future low power logic applications. To realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (REXT) be minimized. Among the different components of REXT, contact resistance (RC) between metal and source/drain (S/D) junctions has become a critical area of focus to lower REXT. Historically, multi-layered Au-based metal contacts (e.g. Au/Ge/III-V) were used in III-V processing. However, the renewed interest in III-V semiconductors for CMOS has attracted an increasing interest by many to develop Au-free contacts to III-V with low RC. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it is a self-aligned process and it offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Si/Ge/III-V). In this paper, we will review these technology options for RC reduction and present some of our recent results on contact/junction engineering to lower RC in III-V transistors.
Oxide Structure-Dependent Interfacial Layer Defects of HfAlO/SiO2/Si Stack Analyzed by Conductance Method
Authors: Ding YI Ming , Misra Durga
Published: February 2020

Aggressive downscaling of effective oxide thickness (EOT) requires improvement in gate leakage current and interfacial characteristics. Recently other materials like Al, Zr, and La are introduced into HfO2 to further reduce the EOT and improve the reliability. Since the structure of the HfO2-based dielectric changes with addition such materials it is required that the impact of structural change on the interface needs to be investigated. In addition, the effect series resistance（R
s）associated with the substrate and contact needs to be excluded. In this work we have used metal oxide semiconductor capacitor (MOS-C) devices of 3nm HfAlO/ 0.5nm SiO2/Si gate stack by different preparation methods (different Al doping, post annealing temperatures, deposition stacks) to characterize the quality of interface. Interface defect densities were evaluated by conductance method (1) while excluding any series resistance effect.

13 samples were prepared with 5 angstrom of interfacial layer SiOx, intentionally deposited on the Si substrate by vapor ozone treatment prior to depositing the high-k layer by atomic layer deposition (ALD) in a 300 mm TEL Trias™ cleanroom tool at TEL Technology Center. The metal gate was prepared by 5nm ALD TiN followed by 50nm physical vapor deposition (PVD) TiN. The substrate was of p-type Si (001) orientation with a.doping concentration of approximately 1015cm-3. Small signal capacitance and conductance measurements were investigated by HP4284 LCR analyzer. It is known that depending on the post-deposition annealing (PDA) temperatures Al doped HfO2 changes its structure from amorphous to tetragonal reducing its EOT (2).

It was observed that D
it is dependent on the EOT of hafnium aluminum oxide. The amorphous structure has the lowest D
it (2.76) whereas tetragonal HfO2 (t-HfO2) has the highest D
it (1.27). The Dit
values of other EOT are within the range of observed highest and lowest values as EOT, as shown in Fig.1. It is expected that D
it value are affected both by the oxide phase structure and interfacial layer thickness since Aluminum doping could impede the growth of the interfacial layer. The decrease in interfacial layer will significantly impact the interface defects as they are closer to interface, this was observed when annealing temperature was 800°C (3). However, in the low annealing temperature with addition of Al the dielectric constant of oxide decreases insignificantly to changed EOT without reducing Dit
.

 

E. H. Nicollian and A. Goetzberger, Bell Syst. Tech. J. 46, 1055 (1967).

K. Tapily, S. Consiglio, R. Clark, R. Vasic, C. Wajda, J. Jordan-Sweet, G. Leusink, and A.C Diebold, ECS Trans., 64 (9), 123 (2014).

Y.Sugimotoa, H.Adachia, K.Yamamotoa, D.Wangb,H. Nakashimaa, H. Nakashima, Material Sci. in Semicon. Process.,9, 1031 (2006).

Figure 1
Room Temperature Photoluminescence Characterization of Interface Quality of SiN/SiO2/Si Prepared under Various Deposition Techniques and Conditions
Authors: Yoo Woo Sik , Kim Byoung Gyu , Jin Seung Woo , Ishigaki Toshikazu , Kang Kitaek
Published: February 2020

Various types of stacked dielectric films are used in complimentary metal-oxide-semiconductor (CMOS) devices in gates, capacitors and device isolation structures. They are also used as insulating materials between conductors, as inter-metal dielectrics (IMD) and inter-layer dielectrics (ILD). The preparation technique, structure and properties of dielectrics strongly influence the quality of the dielectrics/Si interface. Nominally, similar dielectrics/Si structures, even prepared by the same technique, often show different electrical properties depending on subtle differences in process conditions (hidden variables). Monitoring of physical dimensions and chemical compositions of dielectrics often miss unexpected variations in electrical properties. Non-contact electrical property characterization techniques lack lateral resolution and often results in impairment of the dielectrics/Si interface due to strong external electric fields from the measurement process. Alternative dielectrics/Si interface characterization techniques, which can provide insights into electrical properties without external electric field, would be very useful as a complimentary process and material quality monitoring technique.

In this study, we have investigated the effect of SiN film deposition techniques on the interface quality of the resulting SiN/SiO2/Si using spectroscopic room temperature photoluminescence (RTPL) under multiwavelength excitation. The sample preparation procedures are as follows. First, ultra thin (~2.2 nm thick), gate oxide quality, thermal oxide films were grown on 300 mm Si(100) wafers. Nominally 5.0 nm thick SiN films were grown on ~2.0 nm thick SiO2/Si wafers using conventional low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) under various nitrogen source flow conditions. The film thickness was measured (after SiO2 film deposition) before and after SiN deposition using ellipsometry.  Figure 1 (a) and (b) show RTPL spectra measured at the center of seven different SiN/SiO2/Si wafers under 650 nm excitation and showing maximum RTPL intensity under 650 nm and 827 nm excitation. Significantly large RTPL intensity variations were measured among the seven SiN/SiO2/Si wafers. The SiN film deposition conditions have modified the underlying SiO2/Si interface characteristics. Non-contact RTPL measurements are very sensitive to the thin film deposition techniques and conditions. It is effective as a complimentary dielectrics/Si process and interface characterization and monitoring technique.

Figure 1
Process Optimization of CoSi2 Formation on P-Doped Poly-Si by Hot Wall-Based Rapid Thermal Annealing
Authors: Lee Jin Yul , Kim Hun Joo , Kim Eun Jeong , Song Han Sang , Yeom Seung Jin , Ishigaki Toshikazu , Kang Kitaek , Yoo Woo Sik
Published: February 2020

Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices with advanced device modes. Significant effort has been expended to develop low resistivity junctions, industry wide. However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node. Once the candidate silicide material is chosen for the device node, relatively small improvement in resistivity has been made in recent years, despite silicidation process optimization which include modifications of process steps and integration schemes.  

In this study, we have investigated the effect of annealing temperature and time on the resulting resistivity of Co2Si contacts with P-doped poly-Si using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower Rs, down to 19.6 ohm/sq. from equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window (RTA temperature and time). Secondary ion mass spectroscopy (SIMS) dopant (P) depth profiling results revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The same Rs value can be realized by different P profiles resulting from different RTA conditions. To enable contact resistance reduction, P pile-up near the CoSi2/P-doped poly-Si interface for and to suppress P depletion from P-doped poly-Si layer for resistivity reduction, lower temperature RTA for longer times in the hot wall RTA system was found to be beneficial. 

Wafers with almost identical P depth profiles after CoSi2 formation RTA in the cold wall RTA and the hot wall RTA systems, still showed an Rs difference of ~20%. The wafers annealed in the hot wall RTA system always showed lower Rs values indicating higher P dopant activation in the P-doped poly-Si layer. The difference in wafer heating mechanisms between the cold wall (lamp-based) RTA and the hot wall (furnace-based) RTA may have played an important role in the dopant activation and Rs differences. Hot wall RTA is very promising for realizing the low resistivity contacts required in advanced high performance devices. The simple change of annealing technique may extend the life cycle of CoSi2/P-doped poly-Si contacts. 

The Rs response surface (as a function of RTA temperature and time) and SIMS depth profiles of P atoms will be presented at the meeting.

Figure 1
Non-Volatile Resistive Memory Switching in Pulsed Laser Deposited Rare-Earth Gallate-GdGaO3 Thin Films
Authors: Sharma Yogesh , Pavunny Shojan P. , Scott James F. , Katiyar Ram S.
Published: February 2020

Resistive random access memories (ReRAMs) have emerged as a potential memory candidate that has the capability of fulfilling the future high density requirements due to their simple design, excellent scalability, high speed storage capacity, low power consumption, and CMOS process-flow compatibility. With this motivation pulsed laser-deposited amorphous GdGaO3 (GGO) thin films sandwiched between two Pt-electrodes were investigated to explore their resistive switching (RS) behaviour. Pt/GGO/Pt memory cells showed a stable resistance ratio of ~104 between low resistance state (LRS) and high resistance state (HRS) and non-overlapping switching voltages (set voltage VON ~1.2˗1.4 V and reset voltage VOFF ~0.5˗0.7 V) with a small variation of 5˗10%. To confirm the reliability of the Pt/GGO/Pt memory cells, cyclic endurance up to 60 set/reset cycles and data retention up to 103 seconds were measured. Only a unipolar RS mechanism in Pt/GGO/Pt memory cells was observed due to a conductive filamentary (thermo-chemical) mechanism in which, the change in resistance state (LRS↔HRS) of the cell was found to occur from rupture of conductive filaments consisting of metallic Gd atoms and oxygen vacancies. The charge transport mechanisms of the cell in LRS and HRS states were found to be dominated by Ohmic conduction and trap controlled space–charge limited current, respectively. This work reveals the potential of rare-earth gallates for non-volatile memory device applications.
(Electronics and Photonics Division Award) Dielectrics for III-V Materials
Authors: Abernathy Dean Cammy R.
Published: February 2020

Successful electronic device technologies require the ability to passivate semiconductor surfaces and to retain that passivation during subsequent processing and device operation.  In silicon this passivation is obtained through the use of silicon dioxide.  A similar approach in III-V semiconductors has not been as successful due to the relative instability of the native oxides in this system.  This has led to the investigation of a range of dielectrics with varying degrees of success.  In addition to the difficulty in obtaining a dielectric suitable in terms of stability and band alignment, III-V surfaces have proven to be difficult to sufficiently clean and thus often suffer from severe interfacial leakage.  Finally deposition methods compatible with IC fabrication processes must also be developed once the dielectric material itself has been chosen and optimized.  In spite of these challenges substantial progress has been made in the development of dielectrics for III-V device technology.  This talk will review the development of dielectrics on III-V surfaces with a particular focus on dielectrics for widebandgap materials.
Annealing Effects on the Electrical Activation of Si Dopants in InGaAs
Authors: Lind Aaron Gregg , Aldridge Henry Lee , Bomberger Cory Carl , Hatem Chris , Zide Joshua M. O. , Jones Kevin Scott
Published: February 2020

There is a renewed interest in integrating high mobility III-V channel materials into sub 10 nm nMOS devices but the continued scaling of devices has resulted in the need to create contacts and source/drains with ultra low contact resistivities in order to reduce current losses. This study investigates thermal stability of Si dopants incorporated via MBE growth and ion implantation as potential methods to create heavily-doped, low resistance source/drain regions in III-V channel devices. For this study, the electrical activation and diffusion of Si active layers in In0.53Ga0.47As formed by a 10 keV, 5×1014 cm-2 Si implant and MBE growth doping with a peak Si concentration of 7×1019 cm-3 were investigated as a function of post growth and post-implant isochronal annealing.  While most previous studies conclude that MBE doping can achieve higher active Si concentrations than ion implantation, the results of this study show conclusively that electrically active Si concentrations above 1.4×1019 cm-3 formed by MBE doping are prone to deactivation upon thermal treatment after growth whereas ion-implantation shows no metastable activation behavior.  Significant Si deactivation in MBE doped substrates is shown to occur before the onset of Si diffusion whereas saturated activation in ion implanted substrates does not occur until diffusion is observed.  Upon annealing at sufficiently high temperatures to cause Si diffusion, the electrical activation of Si in MBE doped substrates and ion implanted Si are shown to converge to a stable activation limit of 1.4×1019 cm-3. The common activation limit upon Si profile motion for both Ion implanted and growth doped Si active layers after thermal annealing at 750°C suggests that the maximum stable electrical activation of Si is an intrinsic property of In0.53Ga0.47As. Si diffusivity has also been calculated from SIMS results in both ion-implanted substrates and growth-doped substrate and Si diffusion in MBE doped substrates was observed to be nearly three times as fast as ion implanted substrates presumably due to the observed concentration dependent diffusion effects. The mechanism of Si diffusion and its relation to the observed concentration dependent diffusion and electrical activation behavior in both materials are also discussed.

Figure 1