(Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits
Authors: Weber Walter M. , Heinzig André , Trommer Jens , Baldauf Tim , Raitza Michael , Grube Matthias , Pregl Sebastian , Jeon D.-Y. , Park S.-J. , Sessi Violetta , Mikolajick Thomas 
Published: February 2020

Semiconductor nanowire transistors are considered potential successors of finFETs providing the ultimate miniaturization capabilities of MOS transistors and thus targeting ultimate circuit complexity and performance. A promising perspective for further advancement beyond classical CMOS scaling is to exploit functionality enhancement of nanowire transistors. Several nanowire based multi-gated device concepts known as reconfigurable field effect transistors (RFETs) or polarity control FETs that combine multi-functionality with the inherent advantages of silicon nanowires are being currently evaluated [1-4]. These multi-terminal devices merge unipolar n- and p- FET switching characteristics from the same device as selected simply by an electric signal and without the need for doping enabling complementary CMOS operation with a single kind of transistor. RFETs make use of two sharp metal-NiSi2 / intrinsic-silicon interfaces with individual gates for the selective injection of electrons and holes into the channel region [5]. Additional independent steering gates can be integrated to further enhance functionality without comprising on-conductance [6]. In order to allow complementary circuit operation symmetry in the p- and n-type I-Vcharacteristics is mandatory. To this end, we show both experimentally [7] and by device simulations [8] that the application of radial compressive strain to <110> oriented silicon nanowires is able to align the injection efficiency of electrons and holes for diverse nanowire geometries. Full swing complementary operating circuits such as inverters [7] and compact six transistor cells yielding NAND, NOR and minority functions as demonstrated with symmetric RFETs and 3XOR gates with only 8 transistors vs. 24 with CMOS [6,7,10,11]. These gates build the basis for arithmetic building blocks such as one-bit adders with substantially lower transistor count reducing critical pathes, delay and power consumption as compared to conventional CMOS [6]. The RFET concept has been recently successfully transferred to a parallel nanowire technology [12,13] principally enabling to build low operation power circuits and sensors on plastic substrates. Finally, we show that germanium based RFETs improve the individual device performance and to reduce dynamic power consumption without comprising static power consumption.

Figure caption:

a) Schematic of reconfigurable nanowire FET (RFET) encompassing intrinsic Si nanowire channel and two independently gated Si / NiSi2 junctions. b) Oxide induced compressive stress in Si nanowire core required to adjust electron and hole currents: TEM cross section of nanowire channel with overlay of computed mechanical strain distribution. c) SEM image of abrupt Si / NiSi2 junction. d) SEM of symmetrically operating RFET with electrical device symbol. e) Symmetric p- and n-program I-V transfer characteristics of device depicted in d). f) SEM of inverter built of two RFETs within a single nanowire. g) Measured inverter transfer characteristic with supply voltage of Vdd = 2V showing low operation power complementary behavior and full swing output. Propagation delay for scaled structure and for different fanouts. Output of reconfigrable NAND/NOR/Minority 6-transistor cell, shows reconfiguration at runtime (mixed -mode computations). h) High-yield printed silicon nanowire FETs encompassing ~ 1xE3 parallel nanowires with meander source/ drain / gate structure. Technology is compatible with flexible plastic substrates.

References:

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[2] W. M. Weber et al. IEEE Proc. Nanotechnology Conf. pp 580-581 (2008)

[3] F. Wessely et al. Sol. Stat. Elec.
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[4] M. De Marchi, et al. IEDM 2012 Tech Digest pp. 183-186 (2012)

[5] D. Martin, et al. Physical Review Letters  107, 216807 (2011)

[6] J. Trommer et al. DATE 2016 Conf. Proceedings (2016)

[7] A. Heinzig, et al. Nano Letters
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[8] T. Baldauf et al.  IEEE Electron Device Letters
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[10] J. Trommer et al. IEEE Electron Device Letters. 35, 141 (2014)

[11] J. Trommer et al. IEEE Transactions Nanotechnology
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[12] S. Pregl et al. IEEE Transactions Nanotechnology DOI:10.1109/TNANO.2016.2542525

[13] D.-Y. Jeon et al. Nano Letters 15, pp. 4578-4584 (2015)

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