bluuebunny/crossref_metadata_2025 huggingface dataset:
Molecular Architecture and Assembly of the Eukaryotic Proteasome
Authors: Tomko Robert J. , Hochstrasser Mark
Published: March 2013

The eukaryotic ubiquitin-proteasome system is responsible for most aspects of regulatory and quality-control protein degradation in cells. Its substrates, which are usually modified by polymers of ubiquitin, are ultimately degraded by the 26S proteasome. This 2.6-MDa protein complex is separated into a barrel-shaped proteolytic 20S core particle (CP) of 28 subunits capped on one or both ends by a 19S regulatory particle (RP) comprising at least 19 subunits. The RP coordinates substrate recognition, removal of substrate polyubiquitin chains, and substrate unfolding and translocation into the CP for degradation. Although many atomic structures of the CP have been determined, the RP has resisted high-resolution analysis. Recently, however, a combination of cryo-electron microscopy, biochemical analysis, and crystal structure determination of several RP subunits has yielded a near-atomic-resolution view of much of the complex. Major new insights into chaperone-assisted proteasome assembly have also recently emerged. Here we review these novel findings.
A Novel Deep–Oxide Trench SOI–LIGBT with a P–Pillar Layer
Authors: Fu Qiang , Zhang Bo , Li Zhaoji
Published: March 2013

In this paper we propose a novel deep-oxide trench SOI-LIGBT (DTPL SOI-LIGBT) with a deep P-Pillar layer in the drift region. The device can not only shorten the device cell pitch but also improve the breakdown voltage simultaneously. Particularly, it offers a fast extraction path for the hole current during turn-off, and in result shows significant improvement in the on-state and switching trade-off.
Ti/HfO2 Based RRAM Operation Voltage Scaling for Embedded Memory
Authors: Tsai C.H. , Chen F. T. , Lee H.Y. , Chen Y.S. , Tsai K.H. , Wu T.Y. , Rahaman S.Z. , Gu P.Y. , Chen W. S. , Chen P.S. , Lin Z.H. , Tseng P.L. , Lin W.P. , Lin C.H. , Sheu S.S. , Tsai M. J. , Ku T.K.
Published: March 2013

Consumer gadgets make up the fastest growing market for electronic devices today. These products will rely more and more on embedded storage-type memory, which can store system and processing data without impacting standby power consumption. For embedded memory applications, including microcontrollers, automotive, and mobile code storage applications, NOR flash is a popular choice for its non-volatility and fast read time on the order of nanoseconds. However, its operation voltage is larger than 10V, and the write speed exceeds 10 microseconds. Although increasing density is not a key requirement for process scaling of embedded memory down to advanced nodes, the operation voltage needs to be reduced to continually lower power consumption and to match foundry offerings in the logic and mixed-signal sectors, both in the core voltages and the I/O voltages. Resistive random-access memory (RRAM) is proposed to be such a scalable embedded memory technology. RRAM offers the advantages of CMOS process compatibility, high speed, high endurance, low-voltage operation, and high cell density. In this article, we demonstrate that the operation voltage can be reduced to under 1V in the Ti/HfOx RRAM system with a multi-level RESET operation strategy, while keeping the write speed to less than 2 microseconds, opening up opportunities for RRAM in embedded memory applications.
Simulations of Bulk FinFETs with Body Gate Controlling Punch through Leakage
Authors: Xu Miao , Zhu Huilong , Wu Hao , Liang Qingqing , Yin Haizhou , Cheng Dapeng , Ye Tianchun
Published: March 2013

An optimized structure of bulk FinFETs with low punch through leakage is studied by 3D-TCAD simulation. We use an additional gate, called body gate, to control the punch through leakage to achieve low junction leakage. Different body gate bias can be used to control FinFETs punch through leakage without additional dopant in the channel, leading to less random dopant fluctuation. A new process flow to make the bulk FinFET structure with body gate is also proposed.
Low-Frequency Noise in High-K and SiO2 UTBOX SOI nMOSFETS
Authors: dos Santos S. D. , Martino J. A. , Strobel Vincent , Cretu Bogdan , Routoure Jean-Marc , Carin Regis , Simoen E. , Aoulaiche M. , Jurczak M. , Claeys Cor
Published: March 2013

The impact of different gate dielectrics on the low-frequency (LF) noise behavior is investigated in UTBOX SOI nMOSFETs. Hafnium silicate (HfSiO) devices are compared to silicon dioxide (SiO2) ones in terms of low-frequency noise apart from the analysis of both front and back-channels. Despite the improvement of process steps for obtaining good dielectric layers, high-k devices have shown elevated current noise spectral density due to the higher number of traps which also degrades the front-channel mobility. Although the buried oxide (BOX) of both wafers is formed by thermal SiO2, the strong electrostatic coupling between front and back-channels has resulted in a worse noise performance for high-k devices even at the back interface.
Ultra Low Power 6T SRAM Cell Designed on 65nm Low Power Technology Platform Suitable for High Temperature Applications
Authors: Jinhua Liu , Zhou June , Zhou Allan , Chen JinMing , Huang Stella , Ning Jay , Yu ShaoFeng
Published: March 2013

Cell leakage (Istby) reduction of ultra low power (ULP) SRAM with conventional 6T configuration on 65nm low power (LP) technology platform is studied in the paper. Istby components are analyzed and optimized for the leakage reduction by adopting no sleep transistor or other leakage suppression schemes. Gate oxide of cell transistor is grown thicker compared to 65nm LP process to fully suppress the gate oxide leakage contribution. Sub-threshold leakage of the cell transistors are much decreased to lower down both the total Istby and its temperature sensitivity. The 16M ULP SRAM featuring a 0.525um2 bit cell size with the proposed technique shows Istby as low as 1.2pA/bit at 1.2V under room temperature and 3.1pA/bit at 85℃. The voltage data retention (VDR) of the ULP SRAM is shown to be 0.7V indicating the feasibility of Istby further reduction by applying low Vdd under stand by mode. Moreover, the ULP process is fully compatible with logic process flow, by adopting several more masks, the above mentioned SRAM can be embedded into standard CMOS flow easily.
High Density Low Leakage SRAM Standby Current Reduction with a Channel Stop Implant in p-Type Well in 40nm CMOS Development
Authors: Li Yong , Tao Jiajia , Huang S.K. , Lin David , Zhang Shuai , Ju Jianhua , Jin Da , Yu Shaofeng
Published: March 2013

In this paper, 32M 0.242 um2 SRAM cell array leakage was reduced significantly by ~ one order of magnitude without affecting the N+/PW junction capacitance after introducing a channel stop implant (CSI) in P-type well. The space for N+ in PW to NW is generally much smaller for SRAM than for logic device, therefore SRAM is normally the weakest point for N+ in PW to NW well isolation. After checking the N+ in PW to NW leakage, we found that its leakage is the dominant factor for the high SRAM standby current. Furthermore, NMOS performance was also improved with this channel stop implant. The N+/PW diode, N+/PW/DNW and P+/NW/PW bipolar were confirmed to be comparable with the baseline without the channel stop implant. P-type well proximity effect (WPE) and NMOS body effect performance were also analyzed.
(Invited) Advanced Modeling for Full-Chip Low-k1 Lithography Simulations
Authors: Liu Peng
Published: March 2013

Full-chip computational lithography is an important technology that enables low-k1 patterning. Examples of its applications include optical proximity correction (OPC), source-mask optimization (SMO) and verifications. In these applications, lithography models are required to predict the printed patterns on the wafer. Therefore the model accuracy has a direct impact to the quality of the final result. Rigorous physical models are accurate but computationally expensive. Therefore simple approximate models are generally used in full-chip applications. As the k1-factor continues to shrink, the errors produced by these simple models become unacceptable. Advanced models with improved accuracy and reasonable speed are required for low-k1 applications. In this work we will discuss the issues with the existing full-chip models and the development of advanced models.
Substrate Induced Overlay Non-Uniformity Study
Authors: Wang Lei , Meng Honglin , Liu Yao , Guo Xiaobo , Sun Qin , Xiao Shen’an
Published: March 2013

According to ITRS roadmap, the overlay control becomes more and more critical with the layout design shrinkage. In order to meet the tight overlay requirement lots of new techniques had been proposed from exposure system, metrology equipment and APC algorithm. Although current overlay techniques can obviously improve overlay control capability, they still cannot include all factors which will impact overlay into the model. To describe the impact from those factors which are not involved in model, the model fitting error is introduced. Normally it is not so important in generic logical process. But it will become very serious and lead to terrible yield loss in some special case. In all kinds of factors which impact to overlay, the wafer substrate and thermal process are seldom reported, but actually both of them are critical or fatal factors of overlay fail in high voltage and high power devices which have lots of high temperature thermal process. In this paper, we will demonstrate the overlay non-uniformity study with different substrates, film stacks, thermal processes and EPI processes. Seriously random occurrence of overlay non-uniformity is found and the model fitting error is very large. It cannot be resolved by typical overlay improvement method such as overlay mark design, alignment detecting, overlay metrology method and APC algorithm refine. Splits on wafer substrate, thermal and EPI process are proposed. Finally the non-uniformity is reduced by over 90% and model fitting error is also largely reduced.
Evolution of Dual-Layer Patterning Film for Lithography Applications
Authors: Chai Qinglin , Liang Xudong , Chen Yingjie , Li Xianyuan , Zhao Ganming
Published: March 2013

As the IC industry progresses through each technology node on the ITRS roadmap to continually produce increasingly high performance devices, new processes are required to realize the high yields necessary for success. We present and review the evolution of patterning film applications, and recent developments in the anti-reflective coating (ARC) and advanced patterning film (APF) processes. Characteristics of dual-layer patterning film combination to achieve high etch selectivity and good process integration are also discussed.
Process Optimization Using OPE-Master and CDU Master
Authors: Shao Chun , Takehito Kudo , Fujiwara Tomoharu , Matsuyama Tomoyuki
Published: March 2013

OPE matching and CD-Uniformity control have become inevitable steps for most of high volume manufacturing(HVM) of a state-of-the-art devices. OPE matching is a step to match CDs of various patterns from different scanners or steppers. CD-Uniformity control is to stabilize CDs across exposure fields, across wafers and across lots, for HVMs. At a current OPE matching, one usually collects tool properties from each matching tool and import them into simulation software they are using to improve its prediction accuracy. However, generally speaking, this is a time and human resource consuming process, because data acquisition from scanners usually take a lot of time of both human and machine. Furthermore, what makes it more difficult is that an OPE matching, in most cases, requires several iterations. In this paper, we will introduce our latest software named OPE-Master. By employing the software, we can expect following merits. Firstly, with the help of the software, one can be able to automatically import machine properties. This means we can expedite the iterations without sacrifice of the accuracy. Secondly, one can also be able to get better solutions, because it uses all possible adjustment knobs, some of which are ones that unable to be accessed by a third party softwares, with the help of newly developed optimization algorithm that uses a hybrid method of nonlinear optimization and rigorous simulation. Finally, intuitive interface of the software makes it possible for an engineer without much optical simulation experiences to do an OPE matching simulation. In this paper, we will also introduce one of our latest software, called CDU-Master, which will be used to control CD uniformities for a HVM. CDU-Master can analys CDs from various metrology tools, such as, CD-SEMs, OCDs or a macro inspection tools(AMI, for example). CDU-Master can decompose CD errors into focus and dose errors and then derives parameters to correct CDs. One can expect extremely high accuracy of the decomposition, because, CD-SEM as an example, it uses all possible information such as CDs and pattern 3D structure information. The correction parameters, which may include very high order coefficients to be able to deal with very high spatial frequency distribution of errors across a field or across a wafer, will be converted into a format that can be recognized by scanners and then can be exported to scanners automatically, by the software.
The Focus Margin Gain and Limitation Realized by Focus Drilling in 28 nm Hole-Like Design Rules
Authors: Li Tianhui , Deng Guogui , Hao Jingan , Li Gaorong , Wu Qiang
Published: March 2013

Since the device integration and relating lithography process progressively increasing in complexity, more integrated approach to process control has been very necessary. There is more function in scanners that can be used to improve process window, CDU and OVL etc. When semiconductor technology node achieves to 28 nm, some function of scanner comes out contribution on process window increase. Focus drilling is the scanner implementation to increase the depth of focus (DoF) for contact-hole or via fabrication processes [1-7]. The basic principle is to smear out the maximum image contrast at best focus (BF) over a specific defocus range. This function applies a wafer stage Rx-tilt (X-axis tilt) when scanning along the Y-direction (scanning direction). This allows the wafer stage to scan along a plane parallel to its tilt. This paper relies on Focus drilling to improve DoF of 28nm Via process, meanwhile also to analyze its negative impact on EL and CDU etc. And then try to find a balance focus range (Rx tilt) for 28 nm product. But the experiment result showed focus marginal gain is about 15nm, meanwhile it is hard to increase DoF through Rx tilt expanded.
(Invited) Development of Mask 3D Virtual Aberration Model to Predict Pattern Best Focus Deviation
Authors: Fujii K. , Imai M. , Qunying Lin
Published: March 2013

Mask 3D effect induces non-negligible inter-pattern best focus deviation in lithography process. In this paper, mask 3D effects are studied fundamentally and a new novel virtual aberration model is proposed to predict pattern best focus deviation caused by mask 3D effect. Furthermore, resist thickness effect on the phase error is studied and a vitual aberation model is suggested to reflect resist thickness effect. Experimental data shows that the proposed models are effective and accurate to predict total best focus deviation caused by mask 3D and resist thickness effects.
Limitation of Layout Correction on Improvement of OPC Model Calibration
Authors: Wang Kobe , Shen Xuan , Xing Jay , Liu Qingwei , Shi Xuelong , Wu Ken , Gu Yiming , Zhang Recoo , Zhu Yu , Shao Feng , Du Chunshan
Published: March 2013

OPC models are fundamental for accurate OPC. With critical dimension shrinking from generation to generation, the accuracy requirement imposed on OPC model is getting more stringent. From a regression point of view, in order to acheive a good model, uncertainty in calibration data should be minimized throuhg averaging, while errors in control variables should be corrected as much as possible. In OPC model calibration, the deviation of mask CD from design CD constitutes the errors in control variables. It is perceived that OPC model quality might be improved by eliminating this error source in OPC model calibration. Based on this line of reasoning, we have carried out experiments, setting up two OPC models; one model with desgin GDS as control variables, and the other with measured mask CD as control variables. The model accuracies from these two OPC models are compared. It is found that the model accuracies form these two models are statistically insignificant. This unexpected result was analyzed, and the causes are mainly ascribed to (1) small mask CD errors, (2) nearly symmetrical mask CD error distribution around zero and (3) uncertainties in measurements, (4) models form's capability to absorb small mask CD errors.
(Invited) Applications Of A Low Te Plasma To finFET FEOL Etch Challenges
Authors: Yang Qingyun , Chen Lee
Published: March 2013

A new type of plasma source (RLSATM) is described to generate low temperature plasma in the wafer region. The low Te characteristic arises from decoupling of wafer region palsma from that of power deposition region. The plasma source has been demonstrated to show improved performance in etching high aspect ratio structures with reduced micro-loading and ARDE and can help mitigate challenges in advanced finFET FEOL etch applications.
Improving MTBC for Al Etch Using an In Situ Chamber Clean
Authors: Chen Feng , Huang Y. , Ge Q. , Ng H.
Published: March 2013

An in-situ chamber clean process was optimized to extend the aluminum etch chamber manufacturing time between cleans (MTBC) without damaging the chamber interior while also maintaining reasonable throughput. Chlorine/oxygen removes carbon-based polymer most efficiently, while boron trichloride/chlorine is best for removing aluminum byproducts. The greatest improvement in lid/sidewall cleaning uniformity was achieved by raising pressure. After implementing the optimized cleaning process, MTBC improved fourfold.
Formation of Porous Low-K Dielectric Interconnect Structure on Advanced Dielectric-Reactive Ion Etcher
Authors: Zhang Cheng-Long , Hu Min-Da , Zhou Jun-Qing , Wang Dong-Jiang , Wang Xin-Peng , Lee Kwok-Fung , Zhang Hai-Yang
Published: March 2013

Porous low-k dielectrics have been extensively integrated into back-end-of-line (BEOL) for its significant improvement of chip resistance-capacitance (RC) delay performance. However, Metal hard-mask (MHM) has to be introduced to reduce the low-k damage from radicals and photons during plasma strip. We investigated the formation of porous low-k dielectric interconnect structure on advanced dielectric reactor ion etcher (AD-RIE) of AMEC (Advanced Micro-fabrication Equipment Company) from the point of view of etch profile, wafer acceptance test (WAT), RC delay performance and reliability (RE). Scanning electron microscope (SEM) results exhibit the desired etch profiles for both trench and via. The WAT electrical results, RC delay and RE performances can be well improved by etch profile control. In brief, all of these demonstrate AD-RIE is capable of delivering the qualified porous low-k dielectric structure as main-stream etchers did.
A Study of Sigma-Shaped Silicon Trench Formation
Authors: Sui Yun-Qi , Han Qiu-Hua , Zhang Haiyang , Lee Kwok-Fung
Published: March 2013

The strict shape control of sigma-shaped silicon trench has to leverage the dry etch process coupled with the appropriate post-etch treatment (PET). Here we addressed the strong link between the shape of dry etch based silicon recess and its effect on the definition of final sigma-shaped trench. Experiment results indicate the critical physical parameters of final sigma-shape silicon trench could be predicted by means of geometry analysis and monitoring dry etching related recess in bulk silicon. Besides, we also noticed the effect of pattern-dependent depth loading at dense areas. Organic polymer generated during etch process tends to introduce the trench depth variation. Polymer lean etch process has been proven as one of effective knobs to overcome such loading to some extent. In addition, the oxidation capacity of post-etch treatment can not be ignored. The ultra-thin silicon oxide film on silicon trench sidewall must be completely removed by dilute hydrofluoric acid before PET to avoid the possible trench depth loading.
Fabrication of TiN Blade Bottom Electrical Contact for PC-RAM
Authors: Wang Dongjiang , Zhou Junqing , Fu Yali , Hu Minda , Zhang Chenglong , Wang Xinpeng , Zhang Haiyang
Published: March 2013

Two patterning schemes and etch approaches were exploited to study the formation of TiN blade BEC (bottom electrical contact) from the reactive ion etch point of view. Patterning scheme I features the benefit of cost-saving but less scalability due to the limitation from lithography process, while patterning scheme II is better on scaling but challenging for RIE to remove TiN side-wall and control profile. Results showed that the etch approach I, adopting isotropic etch, is capable of clean the side-wall TiN without too much oxide loss. However, it suffers CD loss and worse TiN profile issue particularly when applied in patterning scheme II. On the other hand, the etch approach II, adopting anisotropic etch, is better on TiN CD and profile control. After the optimization of etch process, bottom oxide loss can also be well controlled. All of these merits make it possible for the integration of TiN blade BEC with further dimension shrink by means of patterning scheme II coupled with etch approach II.
Fabrication of Silicon Nanopore Arrays with Three-Step Wet Etching
Authors: Chen Jian , Deng Tao , Wu Cinan N. , Liu Zewen W.
Published: March 2013

Solid-state nanopore arrays are realized with a well-controlled, three-step, anisotropic wet etching process with different KOH bath temperatures. The influence of etchant concentration and temperature on the etching rate is investigated. Nanopore arrays with an average size of 100 nm and single pores with a feature size of 30 nm in a silicon membrane are successfully fabricated at low cost using this method. This study paves the way towards the controllable, large-scale production of arrays of nanopores with desired size.
Advanced PVD TiN for Metal Gate Application
Authors: He Weiye , Kang Jian , Luo Jeff , Wu Grant , Zhang Lei
Published: March 2013

High-κ metal gate is widely used for 32nm and beyond to enable scaling down of MOSFET geometry while improving device speed and gate leakage. This structure requires a good work function metal to tune Vt as well as a stable metal barrier to control inter-diffusion and interaction between the multiple metal gate layers. To meet the integration requirements of metal gate, it is very important to choose the proper metal thin film process. Its stability and excellent integration performance make TiN a good option for metal gate application, but the traditional PVD (physical vapor deposition) TiN process still faces issues, such as plasma damage and poor gap-fill capability. RFPVD (radio frequency physical vapor deposition) TiN has been developed for metal gate application. This paper presents studies of the film texture, density, and inter-diffusion base on different metal gate layers. MOSCAP (metal oxide silicon capacitor) tests showed that RF PVD TiN exhibits low Dit and device leakage. To meet the strict gap-fill requirement of the gate-last scheme, physical gap-fill performance of the high-pressure RF TiN process was checked. It achieved more than 60% bottom coverage and minimal sidewall coverage, allowing the electrode gap-fill window to be effectively enlarged.
Integration Challenges and Options of Replacement High-κ/Metal Gate Technology for (Sub-)22nm Technology Nodes
Authors: Veloso Anabela , Ragnarsson Lars-Åke , Schram Tom , Chew Soon Aik , Boccardi Guillaume , Thean Aaron , Horiguchi Naoto
Published: March 2013

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), focusing on the scalability challenges faced by: 1) effective work function (EWF) engineering targeting logic high-performance and low-power applications; 2) low-resistance fill-gate metallization for extremely scaled gates with high aspect-ratios; and 3) ultra-thin EOT gate dielectrics with controlled JG, reliability and variability. Also addressed is the need for, and exploration of options compatible with 3D-architecture devices (FinFETs). Key results include controlled TiN/TiAl-alloying and conformal ALD-TiN/TaSiAl for low-threshold voltage (VT) scaled NMOS, W vs. Co-Al alloy evaluation as fill-metal, and cubic-phase HfO2 with higher k-value (k=30) showing improved performance and reliability when normalized to JG. Reduction of the bulk high-k dielectric defects, by implementation of an optimized post high-k deposition anneal (PDA), is shown to play a key and dominant role to enable substantial NBTI lifetime improvement in the (sub-)1nm EOT regime.
(Invited) PMD and STI Gap-Fill Challenges for Advanced Technology of Logic and eNVM
Authors: Liu Huang , Srivathanakul Sonny , Liu Hung-Wei , Gaan Sandeep , Cai Xiuyu , Rao Xuesong , Shu Jeff , Kim Sung
Published: March 2013

With a gap-fill friendly "V'" profile, HARP can address the stringent gap fill requirements from 20nm STI and 32nm/28nm PMD with gate first HKMG with not much limitation to spacing CD. The weakest line in the STI trench can be addressed by adding steam into deposition steps or post-dep steam annealing. Dep-etch-dep approach would help to extend the gap fill application of HARP process. But in FinFET STI or PMD with RMG integration where "V" shape profile is difficult to be realized due to their unique integration flows, a FCVD process is needed to fulfill the gap-fill requirement. Excellent FCVD gap-fill has been demonstrated in high AR ratio FinFET STI and PMD even with straight vertical or reentrant profile. Some integration challenges like poor wet resistance and FCVD induced structured bending are addressed.
Process Optimization of Dielectric CVD Film for Patterning Related Defect Reduction at 28nm Technology
Authors: Deng Hao , Zhang Bin , Xiang Yang Hui , Guo ShiBi , Tong Hao , Yan Yan , Zhang Beichao
Published: March 2013

As semiconductor device scales down towards 28nm technology and below, patterning technique becomes more critical and challenging to achieve circuit image with more stringent features, especilly for critical layers, such as AA, Gate, CT and M1 etc. Good patterning performance is not only related to lithograph/etch process window, but also process variation of various patterning related films, such as surface roughness, defect density and size, etc. In this paper, a few patterning related dielectric films, including APF (Advanced Patterning Film), NF-DARC (Nitrogen Free Dielectric Anti-Reflective Coating) and hardmask oxide/nitride, were discussed on defect reduction in a 28nm logic chip. Four types of patterning related defects at AA, CT and Gate layer, were addressed, which are Si cone, CT missing/distortion, poly bridging and tiny abnormal poly pattern. An in-depth study of defect source and mechanism of defect formation and transformation were dicussed. Potential solutions involving improved DCVD film deposition processes were also presented.
High Density Copper Nucleation on Ruthenium and Its Application to Direct Plating of Advanced Interconnects
Authors: Shi Ping , Wu Jun
Published: March 2013

Electrochemical nucleation of Cu on Ru in commercial chemistries was studied. The results show that Cu nucleation behavior is highly dependent on the suppressor species and concentrations, the acidity of the electrolyte, and the state of Ru surface. With an excellent suppressor and intermediate acid electrolyte, the Cu nucleation density as high as 1 ×1013 cm-2 can be achieved without the need of a pretreatment of the Ru surface. Direct plating of Cu on Ru with both damascene and through-silicon via structures using this highly suppressive chemistry is demonstrated.
Effective Approach for TSV Cu Plating Gap Fill Improvement
Authors: Lin Paul-Chang , Li Guang-Ning , Jiang Jian-Yong , He Peng , Sun Ri-hui , Yang Yi , Liu Xuan-Jie , Chen Xiao-Jun
Published: March 2013

TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu plating is the key step in TSV flow. But we suffered TSV void issue in TSV ECD (Electro Chemical Deposition ) process for TSV seed layer poor condition impact .It is important to understand how to improve TSV Cu plating gap fill capability in order to develop TSV technology. In this paper, the barrier and seed layer performance improvement in TSV Cu plating is introduced, and then an effective approach to improve the TSV plating gap fill capability is demonstrated.
Optical Emission Spectroscopy Studies in ECR Plasma Used for the Deposition of Silicon Oxide Film
Authors: Hsieh Yu-Lin , Chang Shan-Yuan , Li Tomi T , Hu Li-Cheng , Lee C.C , Chang J.Y. , Chen I.C. , Chu Y.H. , Lee J.Y. , Wang S.H.
Published: March 2013

The Optical Emission Spectroscopy (OES) is used as a diagnostic tool for analyzing the plasma spectrum of Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) in solar silicon oxide thin film process. In this study, the correlation between spectrum variation trend and a-SiOx film properties will be discussed. The results reveal when the total flow rate and working pressure are fixed, the silicon oxide deposition rate can be interpreted by SiH* spectroscopy. On the premise that the bond energy of reaction species is lower than the bond energy of Si-O bond, the O* spectroscopy intensity tends to to be a positive correlation with oxygen content of thin film. Based on the above results, we can develop and use the database from plasma spectra corresponding to film properties, and the processing time required for optimization of silicon oxide process can be reduced significantly. In addition to the film properties, it is noted that a different and opposite finding compared with PECVD is that the photo-conductivity of a-SiOx film increases and dark-conductivity decreases when microwave power augments. Finally, in 800W power, 200°C process temperaure and 5mTorr working pessure, it is found that the hydrogenated amorphous silicon oxide will transform to the crystalline phase when CO2/SiH4 ratio was less than 0.2 and H2/SiH4 ratio greater than 10.
(Invited) GST CMP Challenges and Solutions for 45nm PCRAM
Authors: Jiang Li , Chen Feng , Zhu Pulei , Li Mingqi , Liu Hongtao , Wu Guanping , Zhong Ming , He AoDong
Published: March 2013

We report on GST(Ge2Sb2Te5) CMP process challenges and solutions in this paper. GST stain issue is solved through proper polish pad selection, process scheme and cleaning step optimization. The key factors to achieve minimum oxide loss are slurry dilution ratio & H2O2 concentration optimization and over polish control. Pico-second laser acoustics type measurement tool proves suitable for GST CMP process inline and offline monitor
The Preparation of Nanometer Non Spherical Colloidal Silica and Its Polishing Character
Authors: Weiwei Li , Jianxin Diao
Published: March 2013

Using mixed alkali which is mixed by inorganic base and organic base and potassium carbonate can prepare non-spherical colloidal silica and the two types of colloidal silica are well used in chemical mechanical polishing of silicon substrate surface. A lot of chemical mechanical polishing tests about the non-spherical colloidal silica have proved that non spherical colloidal silica which the particle size is about 50 nm can be used in chemical mechanical polishing whose removal rate is faster than 130nm spherical colloidal silica around 10%.
CMP Platen 1 Endpoint System Innovation for Post Profile Control
Authors: Gao Fang , Xu Ying , Zhang Weifeng , Zhao Runtao , Zhao Ganming
Published: March 2013

Continuously shrinking dimensions in VLSI manufacturing introduces new challenges in copper CMP. One of the critical challenges is the requirement for surface flatness after bulk copper removal on Platen 1. A new metrology has been deployed for the Platen 1 process control system. The new capability allows the system to implement multiple trace channels to monitor remaining copper thickness while also monitoring the profile of remaining copper.
High K Metal Gate CMP Process Development for 32nm and Beyond Gate Last Approach
Authors: Shao Qun , Chen Feng , Jiang Li , Li Mingqi , Wang Qingling , Zhu Pulei , Cheng Ji , Xiong Shiwei , Liu Hongtao
Published: March 2013

ILD0 CMP and Al CMP plays important roles to form high k metal gate in the gate last approach for 32nm technology and beyond. It requires very tight control for the gate height and the surface topography. The gate height uniformity improvement, the dishing/erosion reduction and defect reduction are the key aspects for ILD0 CMP and Al CMP process development. Firstly, the polishing strategies and slurry selection are the most critical part. Several types of SiN slurries for ILD0 CMP process are evaluated. The impacts of SiN slurry's selectivity on dishing and poly thickness control are studied. The pros and cons of different CMP techniques, such as fixed abrasive CMP and slurry CMP for ILD0 CMP will be elaborated as well. Secondly, the pattern design and the design rules have significant impact on gate CMP process performance. The gate height and topography performance for different feature sizes and pattern densities are described and the dummy rule setup strategies are explored in this paper. Next, defect (Al pitts, scratches, particles, residues and as such) is another major challenge to a successful gate CMP process. The mechanism for the formation of the various types of defects is discussed and approaches for defect reduction are explored. In addition, the interation among the STI CMP, ILD0 CMP and Al CMP processes is discussed. Lastly, various process control and gate height monitor methods are compared and discussed in this paper.
Low Cost and High Performance CMP Solution for Si Polishing in Backside Illumination (BSI) Application
Authors: Yang Yifan , Huang Simen , Chan James , Wang Xucheng , Sang Sand , Zhao Colin , Du Simon , Wang Yuchun
Published: March 2013

Backside illumination (BSI) is an uprising technology to achieve high performance of CMOS (Complementary Metal-Oxide Semiconductor) imaging. Si CMP (Chemical-Mechanical Polishing) process is required in BSI application to remove grinding masks and dislocations from bonded wafer with typical 1.0~3.0um removal amount. BSI CMP appears easy compared to traditional IC CMP in that there is much less integration requirements from pre/post CMP steps. The challenges lie in CMP profile control to compensate incoming thickness variation from grinding for low TTV (total thickness variation), low surface roughness and supreme surface quality for optical path, and low cost for mass production. There is a need to develop slurries/process to conquer all the challenges. Reported in this paper is our recent effort to address such challenges in Si CMP process for BSI application by combining CMP slurry selection and process optimization together. The performances of these approaches were tested on laboratory-scale instruments and further optimized on 8” and 12” CMP tools. Polishing results from both blanket Si (EPI) wafers and SOI wafers are discussed to set up the final process conditions.
(Invited) Material Removal Mechanism of Single and Polycrystalline Silicon in Alkaline Slurry
Authors: Park Jin-Goo , Venkatesh R. Prasanna , Kwon Tae-Young
Published: March 2013

The material removal characteristics of single and polycrystalline silicon in an alkaline regime under the same polishing conditions were investigated. The static and dynamic etch rates, and removal rates were measured as a function of slurry pH. The single silicon showed a higher static etch rate than the polycrystalline silicon. The friction force between pad and substrate and pad temperature was also measured as a function of pH during polishing in order to get more understanding of polishing process. At all the pH values being investigated, poly showed lower dynamic and removal rates, higher friction force and higher temperature. The results clearly show that the material removal mechanism of poly is different from that of single. This might be due to the presence of grain boundaries in poly which strongly interferes in the removal mechanism.
The Synthesis of Novel Polystyrene-SiO2 Composite Abrasive for CMP Slurry
Authors: Qin Hongyi , Kim Mingu , Jang Sunjae , Xu Yang , Kim Taesung
Published: March 2013

We developed a novel method to synthesize the polystyrene-SiO2 composite abrasive with raspberry structure. The SiO2 nanoparticles were embedded by the polystyrene microsphere. This raspberry-like composite abrasive had lots of advantages for CMP abrasive, for example, the hardness of composite abrasive could easily be controlled by the proportion of SiO2 and the cushioning effect of soft polystyrene core could decrease the excessive mechanical damage caused by hard silica abrasive. Moreover, this structure made sure the stability of composite abrasive in the polishing process. The shape of composite particles was sphere and monodisperse. The size of polystyrene-SiO2 could be controlled in the range from 50 ~ 300 nm by adjusting the amount of styrene monomer. The removal rate in polishing test depended on the proportion of SiO2 and hardness of composite abrasive.
Effects of Polishing Parameters on the Evolution of 3-D Wafer Patterns During CMP
Authors: Wu Lixiao , Yan Changfeng
Published: March 2013

Chemical mechanical polishing (CMP) has been widely used in IC industry. To specify the proper polishing parameters for CMP is a very important and difficult task. In this paper, the effects of polishing parameters including polishing time, polishing heights and down force and elastic modulus of pad on the evolution of 3-D wafer patterns during CMP are discussed. The 3-D wafer patterns contain square-wave features with different pitches and an almost constant nominal density of 50%. Based on the linear model, the magnitude spectra of CMP system are given and the contact pressure distribution is calculated under different polishing circumstances. The evolutions of the 3-D wafer patterns under different polishing parameters are simulated. The effects of polishing parameters on polishing processes are discussed.
Aggressive Diamond Characterization and Wear Analysis During Chemical Mechanical Planarization
Authors: Philipossian Ara , Wu Changhong , Zhuang Yun , Liao Xiaoyan , Jiao Yubo , Sampurno Yasa , Theng Siannie , Sun Fred , Naman Ananth
Published: March 2013

In this study, a 3M A3700 diamond disc was used to condition a Cabot Microelectronics Corporation D100 pad for 30 hours, and wear on its aggressive diamonds was analyzed. The top 20 aggressive diamonds for two perpendicular disc orientations were identified before wafer polishing, as well as after 15-hour and 30-hour polishing. Results showed that the original top 20 aggressive diamonds identified before polishing were subjected to wear after the first 15-hour polishing as the furrow surface area that they generated decreased dramatically by 47%. As these original aggressive diamonds were worn, seven new aggressive diamonds were “born” and joined the new top 20 list for both disc orientations. After the second 15-hour wafer polishing, the furrow surface area of these new top 20 aggressive diamonds did not change significantly. The furrow surface area created by all the active diamonds exhibited the same trend as the top 20 aggressive diamonds, confirming that most pad conditioning work was performed by these aggressive diamonds and that the disc lost its aggressiveness in the first 15 hours of polishing and then maintained its aggressiveness during the second 15 hours.
(Keynote) In Situ AFM Imaging and Stress Measurements during Interruption of Electrochemical Deposition of Copper Nanofilms
Authors: Buckley D. Noel , O'Grady Michael , Lenihan Catherine
Published: March 2013

In-situ stress measurements and in-situ AFM imaging were employed to study time evolution of stress during interruption of the room-temperature electrodeposition of copper nanofilms. Generally, when deposition was interrupted, tensile stress decreased as predicted by Chason's model for low mobility deposits. At all potentials, upon resuming deposition stress recovered to its pre-interrupted state. The relative reduction in stress during interruption increased with increasing overpotential.
Contact Process Optimization for 40nm CMOS Yield Improvement
Authors: Lin Yihui , Wang Xin-Peng , Chen Larry , Yang Cheng Jui
Published: March 2013

The contact process optimization of 40nm node has been achieved through co-optimization of contact etch process, contact wet clean process and glue layer film stack. In this study, it is found that the optimized contact etch process can improve the queue time window from contact etch to contact wet clean and prevent the polymer buildup inside the contact for yield loss. The wafer clean process improvement of contact strip can reduce contact protrusion at the interface of ILD oxide and CESL SiN, one of the root causes for potential reliability issue due to poly to contact shorting. And the increase of the thickness of glue layer will reduce square contact resistance, but lead to high resistance for shared contact on poly. The process co-optimization has been achieved by contact etch new process, contact wet clean new process, and the optimized contact barrier process.
Improvement of Electronic Characteristic for Vertical CNT via Interconnection by Focused Ion Beam
Authors: Kuibo Lan , Li Tian , Kailiang Zhang , Fang Wang , Jun Ren , Yuhang Liu , Yuling Feng
Published: March 2013

Carbon nanotubes (CNTs) have emerged as a promising candidate for next generation interconnect material because of its ballistic transport characteristics, high thermal conductivity, high current carrying capacity and high aspect-ratio. Despite of those advantages, catalysts often cover the top of CNTs based on the top growth model. As a result, CNT-metal contact area and contact resistance were influenced. In this paper, the holes in the dielectric layer were fabricated and the CNTs interconnection structure could be realized by Focused Ion Beam (FIB). The CNTs was grown by Plasma Enhanced Chemical Vapor Deposition (PECVD). Then the top catalysts at the end of CNTs were cut by FIB. The I-V results showed the lowest resistance is 18.15Ωfor the interconnect structure of Pt protection cutting, comparing without any treatment CNTs (39.75Ω), because of increasing contact area and open CNTs end.
Integration Issue of Tensile SiN Liner for Dual Stress Liner(DSL) in Gate-Last High-k/Metal Gate(HKMG) Process Flow
Authors: Qin Changliang , Yin Haizhou , Yin Huaxiang , Wang Guilei , Hong Peizhen , Yang Tao , Lu Yihong , Xu Qiang , Zhao Zhiguo , Cui Huishan , Zhao Chao
Published: March 2013

In this paper, a process challenge of integrating Dual Stress Liner (DSL) (1)-(2) into gate-last High-k/Metal Gate (HKMG) flow is explained and a solution is presented. DSL is an effective method to enhance carriers’ mobility for short channel devices. But when it is applied to gate-last HKMG flow, the dummy gate oxide removal step (wet etch by DHF solution) would result in significant etch of tensile SiN liner. Because tensile SiN liner is formed on gate spacers and is exposed after Poly-Open-Polish (POP) CMP, recesses at the sides of the gate stacks would be formed during dummy gate oxide etch. In order to solve this problem, tensile SiN liner is treated in N2 plasma to reduce it’s etch rate in DHF solution. As a result, no recess appears at the side of gate stacks in our devices during the dummy gate oxide removal step.
On The Resistivity Increase of Heavily Doped n-Type Si by Rapid Thermal Processing
Authors: Zhang Xinpeng , Ma Xiangyang , Gao Chao , Xu Tao , Zhao Jian , Dong Peng , Yang Deren , Vanhellemont Jan
Published: March 2013

The resistivity change of heavily doped n-type Si by rapid thermal annealing is studied. The observed resistivity increase can be explained by dopant deactivation due to vacancy trapping by dopant atoms. The stability of the vacancy-dopant clusters and the recovery of resistivity is studied by low temperature anneals.
Effect of Germanium Doping on Thermal Evolution of Neutron Irradiation Induced Defects in Czochralski Si
Authors: Dong Biyun , Gao Chao , Ma Xiangyang , Yang Deren
Published: March 2013

In this paper, the impact of germanium (Ge) doping on thermal evolution of neutron-induced defects in Czochralski (CZ) silicon has been investigated. It is found that more vacancy-oxygen (VO) defects are generated in Ge-doped Czochralski (GCZ) silicon after fast neutron irradiation. This is ascribed to the promoted vacancy production and retarded vacancy annihilation caused by the large-sized Ge atoms, which lead to an increased equilibrium vacancy concentration and VO complex generation. FTIR measurements found the IR bands of vacancy-oxygen-related complexes in GCZ silicon almost copy their counterparts in CZ silicon, which implies that Ge-doping has little influence on the final states of the evolution of VO complexes. This is also verified by the variations of interstitial oxygen concentrations in CZ and GCZ silicon after isothermal annealing at 800 °C for up to 144 h. However, the evolution process may be somewhat retarded in GCZ silicon, which is caused by the continuous vacancy trapping and releasing.
The Challenges of IC Substrate Materials for Advanced Node Silicon
Authors: Hu Dyi-Chung
Published: March 2013

The design rules of advanced node semiconductor enable more transistors per unit area and demand finer interconnections to the outside world. The material in advanced node silicon is moving from low k to ultra-low k, which makes the devices more vulnerable to stress. In order to meet the requirements of advanced node silicon, the substrate materials are moving to the directions of low CTE that closed to that of silicon, and high Young’s modulus with fine line capabilities. In this paper, the current substrate materials development status from different suppliers is reviewed. Industry also has a revolutionary approach to substrate materials by using so called 2.5D silicon interposers. However, the major shortcoming is its inherent high cost. In this paper, alternative materials such as glass, ceramic and organic substrate materials are been considered and their pro or cons are compared.
Development of Alkaline Solvent Stripper for Wafer Level Package
Authors: Liu Bing , Peng Libbert , Sun Justin , Yan Evan , Xu Rock
Published: March 2013

In this paper, the advantage and limitation of different alkali photoresist stripper is reviewed. Different from traditional dry film stripper, tetramethyl ammonium hydroxide is adopted to replace potassium hydoxide as an etchant to prevent precipitation. In details, the substrate protection, such as Al, Cu, Ag and Sn, is studied, and angstrom level etch rate is received with the carefully-designed inhibitor system; Secondly, the effective photoresist removal performance is acheived with the components balance; In the end, the cleaning mechanism and capability of this novel photoresist removal stripper are disclosed.