A Steep Subthreshold Swing Technique for Gate-All-Around SOI MOSFETs
Authors: Chen Chun-Yu , Lin Jyi-Tsong , Chiang Meng-Hsueh , Hsu Wei-Chou 
Published: February 2020

A device design technique for nanowire FETs for low power capability beyond 10 nm technology node is proposed using 3D numerical simulation and physical analysis. The subthreshold kink effect enables the use of low supply bias without compromising performance. The proposed technique overcomes the fundamental and thermal voltage-limited subthreshold swing (SS).

 

As end of technology roadmap is being approached, many solutions to extend Moore’s Law have been proposed. As the leakage current, mainly coming from the short-channel effects (SCEs), is becoming a limiting factor, the supply bias, i.e. VDD, has to decrease as the channel dimension continues to shrink. However, in order to provide a good CMOS logic, on-off current ratio, which is linked to SS, has to maintain at least three orders. Such limitation has prevented the supply bias from further scaling down. It would be a great deal if we can reduce SS.

 

In SOI-based MOSFETs, floating body effects (FBEs) have addressed a concern for design, especially for a partially depleted body. Fully depleted SOI (Fig. 1) is considered a simpler device as FBEs are minimized. Among FBEs, the kink effect in subthreshold regime and in strong inversion due to impact ionization was once a big issue for the concern of raised off leakage current (Ioff). Nontheless, such concern has long gone since fully depleted SOI emerged. For the kink mechanism, the quasi neutral body in which the injected holes are stored is needed (Fig. 2), but it does not exist in fully depleted devices.

 

Among nonplaner emerging transistors, gate-all-around (GAA) nanowire MOSFET shows superior SCE control due to excellent electrostatics. The GAA channel is usually design with a small diameter to meet the scale length requirement. FBEs are never of concern in the strongly depleted body. We found that using a proper scheme of channel doping, the subthreshold kink is observed. Furthermore, if the kink is away from VGS = 0 V, Ioff is not influenced. Using such technique, we were able to lower SS to less than 60 mV/dec. Fig. 3 shows the GAA n-MOSFET for simulation with gate length (L) of 5 nm, gate oxide thickness of 0.4 nm, channel doping of 1e19 cm^-3 and source/drain doping of 1e20 cm^-3 following ITRS. The high channel doping is intended to create a quasi neutral body for FBEs to effect. Such doping level is now a viable option as in-situ doping has become widely accepted. Fig. 4 shows IDS versus VGS characteristics, where the subthreshold kink at high drain bias is observed. Fig. 5 shows IDS versus VGS characteristics for different channel doping levels, indicating high doping is needed. Figs. 6 and 7 show hole density at different biases, respectively. As can be seen, holes are being accumulated when VGS is set to the condition for the kink to occur.

 

A kink-assisted steep SS scheme was proposed for GAA MOSFETs using in-situ doping technique. Though additional channel doping induces impurity scattering and hence degrades drive current, the benefit from steep SS could overwhelm such drawback if designed properly when seeking for lower supply bias.

Figure 1