Vertical Nanowire TFET Diameter Influence on Intrinsic Voltage Gain for Different Inversion Conditions
Authors: Sivieri Victor De Bodt , Bordallo Caio Cesar Mendes , Agopian Paula Ghedini Der , Martino Joao Antonio , Rooyackers Rita , Vandooren Anne , Simoen Eddy , Thean Aaron , Claeys Cor 
Published: February 2020

TFETs arise as promising devices for low power and low voltage applications, since they don’t present a subthreshold slope limit of 60 mV/dec like in MOSFETs (1-3) and also show higher intrinsic voltage gain (AV) than the conventional MOS transistors (4). Furthermore, in order to improve the performance and the scaling, the nanowire structure for this technology has been studied (5).

From simulations, it was observed that the predominant conduction mechanism and the interactions between the diagonally opposite surfaces of the nanowire TFETs are changed when the transistor diameter is reduced. When the transistor is biased in “strong inversion”, the predominant conduction mechanism near the silicon/oxide interface is the band-to-band tunneling (BTBT). However it is known that there is a gradual transition of mechanisms along the source/channel junction. As a consequence, coming closer to the center of the nanowire, the trap-assisted tunneling (TAT) influence becomes higher. In the center and nearby regions, where the energy bands of source and channel at the interface are far from being overlapped and therefore there is no tunneling occurrence, the conduction occurs through SRH mechanism. This work focuses on the impact of the nanowire diameter reduction on the main analog performance parameters. This analysis will be performed both experimentally and by simulations.

The studied devices were fabricated at IMEC, Belgium.  The gate stack consists of 3nm of HfO2 on 1nm, 10nm TiN and 30nm amorphous silicon. The measured devices contain 400 nanowires in parallel. The difference between the abrupt and the non-abrupt TFETs process resides in the source doping process. In the first and in the latter, a boron in-situ doping and a boron ion implantation were performed, respectively (5).

The main difference between MOSFETs and TFETs is the conduction mechanism, since TFETs operate through tunneling mechanisms while MOSFETs are based on drift/diffusion (fig.1). Considering that the devices with a large diameter are biased in “strong inversion” condition, the TFETs present a higher intrinsic voltage gain (AV­) than the MOSFETs (fig.2). Although the transconductance (gm) of the MOSFETs is higher, TFETs are less affected by the electric field from the drain and thus have a good output characteristic (lower gd values).

For devices with smaller diameters in the “strong inversion” condition, in which an interaction between the potential of the opposite surfaces appears and the symmetrical BTBT regions becomes closer to each other, Av is degraded due to the stronger dependence of BTBT on the drain voltage, causing a higher gD(fig.3). Due to this interaction, the BTBT predominance begins to occur at a lower gate voltage for nanowires with smaller diameter (fig.4).

Since TFETs have been studied for low voltage applications, the analog analysis is also performed in “weak inversion”. When a TFET is biased in this condition, the efficiency (gm/ID) is higher for smaller diameter devices (fig.5). This happens owing to the higher percentage of the junction, in which the predominant occurring mechanism is BTBT, if compared with larger devices. Consequently, the value of gm is higher for smaller nanowires. AVwas calculated using equation [1] and the results are presented in table 1.

Considering the “weak inversion condition”, there is a point of maximum AV for a specific diameter and a degradation for smaller and larger nanowire diameters because of a competition between both effects, the increase of gm/ID and the decrease of the Early voltage (VEA) with the reduction of the diameter. The VEA decrease is caused by the higher dependence of the current conduction on the drain voltage, since for the smaller devices, BTBT predominates along the entire source/channel junction. From a large to a narrow nanowire, the BTBT regions from opposite surfaces become even closer. The diameter for which these regions start to overlap, is the one associated with maximum AV. Therefore, it is possible to conclude that the decrease of the intrinsic voltage gain for larger diameters is more dependent on the transistor efficiency, and for narrower diameters it is more dependent on the Early voltage.

Besides the larger diameter nanowire TFETs, which show better analog behavior than MOSFETs in “strong inversion” (this result was also found for FinFET structures (4)), the smaller diameter devices show potentialities for low power and low voltage applications, since their AV is better for low gate voltages than for the larger diameter NW-TFETs.

(1) W.M.Reddick et al.,Appl.Phys.Lett.,67, 494-496,(1995).

(2) T.Krishnamohan et al.,Techn,Dig.IEDM,947-950,(2008).

(3) A.S.Verhulst et al.,J.Appl.Phys.,104(6),(2008).

(4) P.G.Agopian et al.,TED,60,2493-2497,(2013).

(5) A.Vandooren et al., Solid State Electronics, Vol.72, 82-87,(2012).

Figure 1