bluuebunny/crossref_metadata_2025 huggingface dataset:
Control of Material Interactions in Advanced High-k Metal Gate Stacks
Authors: Wajda Cory , Leusink Gert , Akiyama Koji , Ashigaki Shigeo , Aoyama Shintaro , Shimomura Kouji , Aruga Miki , Takahashi Tsuyoshi , Yamazaki Kazuyoshi , Yamasaki Hideaki
Published: November 2006

Material interactions in advanced high-κ / metal gate stacks can have a significant effect of the performance of completed devices. The effect of these interactions was investigated using planar MOS capacitor stacks that might be used for the gate of a MOS transistor. Gate electrode materials included TaN, TaSiN, and W, and HfSiO and HfSiON were used as the gate dielectric materials with an ultra-thin SiO2 interface between the silicon substrate and the dielectric. Deposition methods included CVD and ALD.
Thermal Stability of HfN Compounds on HfO2/SiO2 Gate Stacks
Authors: Callegari Alessandro , Gribelyuk Michael , Kellock Andrew
Published: November 2006

The thermal stability of HfN compounds on HfO2/SiO2 gate stack has been investigated. Before annealing HfN and HfSiN were found to have a work function of a band-edge N metal. Films have very good thermal stability as measured by Rutherford backscattering. Gate stack high temperature instabilities were observed to occur at the SiO2/Si interface because of the high oxygen solubility of HfN and HfSiN which tends to reduce the underlying SiO2 layer. Attempts to improve the high temperature gate stack stability by incorporating oxygen into the Hf compounds to reduce its oxygen solubility produced some SiO2 interfacial layer re-growth and a work function shift toward mid gap.
On the Growth of Native Oxides on Hydrogen-Terminated Silicon Surfaces in Dark and Under Illumination with Light
Authors: Kovalgin Alexey Y. , Zinine Andrei , Bankras Radko , Wormeester Herbert , Poelsema Bene , Schmitz Jurriaan
Published: November 2006

We investigated the thickness evolution of silicon dioxide grown on a silicon surface terminated by H-Si groups, at room temperature and an elevated temperature of 250{degree sign}C. At room temperature, we observed a noticeable difference in the oxidation rate between light-illuminated samples and the samples kept in the dark. No measurable difference between the oxidation of p-type Si and n-type Si was observed. To describe the low-temperature oxidation, we made further steps towards the extension of our oxidation model earlier developed for thin oxides grown in the temperature range 750-950{degree sign}C.
Impact of Grain Size Distribution of Gate Poly-Si on PMOSFET Performance
Authors: Saki Kazuo , Mizushima Ichiro , Shimizu Takashi
Published: November 2006

We studied the impact of grain size distribution of poly-Si gate on PMOSFET performance. It was found from voltage capacitance characteristic that the smaller grain size causes boron concentration to be depleted at gate dielectric film interface. Moreover, grain size affects the ultra thin gate dielectric film too. Boron is more penetrated to ultra thin gate dielectric film as initial grain size gets larger. The penetrated boron degrades hole mobility at channel region in PMOSFET. It was found for the first time that highest PMOSFET performance can be obtained by optimizing the grain size of gate poly-Si, which strongly impacts on the hole mobility as well as the depletion of boron concentration at gate dielectric film interface.
Ni, Pt and Yb Based Fully Silicided (FUSI) Gates for Scaled CMOS Technologies
Authors: Kittl Jorge A. , Lauwers Anne , van Dal Mark , Yu Hongyu , Veloso Anabela , Hoffmann Tom , Pawlak Malgorzata , Demeurisse Caroline , Kubicek Stefan , Niwa Masaaki , Vrancken Christa , Absil Philip , Biesemans Serge
Published: November 2006

An overview of FUSI gates, emphasizing on Ni-based materials for applications into sub-45 nm CMOS is presented. The work function of FUSI gates was investigated, finding lower values (suitable for NMOS) for 1) gate stacks containing lanthanides (such as Yb) for SiON or HfSiON, 2) NiSi with dopants (Sb, As and P) on SiO2 or SiON and 3) Si-richer silicides (e.g. monosilicides) for HfSiON. Higher WF values (adequate for PMOS) were found for 1) Pt containing silicides on SiO2 or SiON, 2) Ni or Pt metal-rich silicides on HfSiON and 3) B doped NiSi or Al doped Ni-rich silicides on SiO2 or SiON. Several of these FUSI gates were implemented in transistors demonstrating |Vt| values down to ~0.25-0.3 V. The scalability and integration issues are discussed, demonstrating good device characteristics down to ~50 nm gatelengths for optimized process conditions. Finally, a dual WF Ni FUSI CMOS integration flow is demonstrated.
Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem
Authors: Guha Supratik , Narayanan Vijay , Paruchuri Vamsi , Linder Barry , Copel Matthew , Bojarczuk Nestor , Kim Young-Hee , Chudzik Michael , Wang Yun , Ronsheim Paul
Published: November 2006

The requirements for a high-k metal gate n-mosfet solution are that one has a device that exhibits a low Tinv (<1.5 nm), high mobility (~200 @ 1MV/cm) and a threshold voltage in the range of 0-0.2V. While these properties have been independently demonstrated, the key challenge has been to deliver these properties simultaneously and in a gate first , high temperature process flow. We show, that by introducing a new, ultrathin lanthanum oxide dielectric layer in the gate stack, whose function is to provide an electrostatic shift to the onset of threshold these requirements can be acceptably met. This is carried out without compromising gate capacitance and with minimal degradation to the mobility. The underlying physics behind the threshold shift will also be discussed.
NBTI Study on PMOS Devices with TiN/HfO2 Gate Stack and Process Induced Strain
Authors: Shickova Adelina K. , Verheyen Peter , Eneman Geert , San Andres Enrique , Absil Philip , Kaczer Ben , Groeseneken Guido
Published: November 2006

We investigate the effect of process induced strain on Negative Bias Temperature Instability (NBTI) for devices with TiN/HfO2 gate stacks. Devices with compressive Contact Etch Stop Layer (CESL), SiGe Source/Drain, and devices with a combination of both SiGe and CESL were studied and compared to reference devices. We decouple the effect of processing conditions in order to assure correct interpretation of the results. Our study demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with process induced strain. In addition, we performed an Arrhenius study showing that Si-H bonds under strain exhibit similar activation energies as Si-H bonds without strain, indicating that no favorable conditions for interface states generation are created by the strain.
Challenges in Dual Workfunction Metal Gate CMOS Integration
Authors: Lee Byoung Hun , Song Seungchul , Jammy Raj , Hussain Muhammad
Published: November 2006

Technical challenges for various integration schemes including gate first dual metal process, fully silicided gate and replacement gate are discussed. Implementation of dual workfunction metal gate CMOS integration is feasible, but needs more systematic reliability assessment.
Low Pressure Chemical Vapor Deposition of Tantalum-Based Material
Authors: Yanagita Kazutaka , Dussarrat Christian , Beyssac Laurent
Published: November 2006

Tantalum-based materials are attractive as metal electrode as well as for barrier layers. In order to comply with manufacturing requirements, we have developed new processes to deposit various types of tantalum-based films from a novel, volatile liquid precursor called TaPeDiS. The new tantalum source exhibits an excellent versatility as a Ta source with a wide applicability with suitable co-reactants. Tantalum metal, tantalum carbides, tantalum silicon nitride, tantalum silicide and tantalum nitride have all been successfully deposited using TaPeDiS as the Ta precursor. All the deposited films contain low concentration of impurities. The film composition could be adjusted by controlling the respective source amounts. Such tunability can be used in order to set to the desired values for the key electrical properties such as the work function or the conductivity.
Fully Depleted Silicon-on-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channels
Authors: Ducroquet Frédérique , Hartmann Jean-Michel , Tabone Claude , Lafond Dominique , Vizioz Christian , Ernst Thomas P. , Deleonibus Simon
Published: November 2006

High carbon content Si1-yCy layers, with substitutional C concentration as high as 2% and almost no interstitial C atoms (<0.1%) have been grown by Reduced Pressure Chemical Vapour Deposition. The electrical Si1-yCy /Si/SiO2 interface properties have been investigated. It was demonstrated that low oxidation temperature has a beneficial effect on the interface state density as well as on the oxide quality. These high quality Si1-yCy layers have been used as the channel of n-type TiN metal gate FDSOI devices. The threshold voltage adjustment induced by the conduction band offset of Si1-yCy channel is clearly demonstrated.
Dual Substrate Orientation Integration for High Performance (110) PMOS
Authors: Karve Gauri , Ted White , Eades Debby , Sadaka Mariam , Spencer Greg , Hackenberg John , Norbert John , Kropewnicki Tom , Zollner Stefan , Beckage Pete , Grant Jack , Garcia Ricardo , Nguyen Bich-Yen , Cave Nigel , Hall Mark , Cheek Jon , Venkatesan Suresh , Lin C.T. , Wu I-Lu
Published: November 2006

Hole mobility is significantly higher for silicon MOSFETs with channels along a <110> direction on the (110) plane than the usual (100) plane. Formation of (110) PMOS and (100) NMOS transistors is possible through use of Dual Substrate Orientation (DSO) integration. This paper describes a CMOS integration scheme to achieve bulk (110) PMOS and SOI (100) NMOS devices on the same substrate. Transistor results indicate a 130% improvement in PMOS Id,lin and 90% enhancement in Id,sat for long channel devices. Hole mobility and drive current anisotropy along the <110> and <100> channels on (110) plane was observed. There was no gate leakage or sub-threshold slope degradation indicating that the DSO integration results in high quality Si/SiON dielectric interfaces. PMOS enhancement from compressive channel stress is additive to that of orientation and compatible with the DSO integration.
Investigating Electronic and Chemical Properties of Ge/GeOxNy/HfO2 Gate Stacks : High-Resolution Photoelectron Spectroscopy Using Synchrotron Radiation
Authors: Renault Olivier J. , Martinez Eugénie , Fourdrinier Lionel , Clavelier Laurent , Barrett Nick , Le Royer Cyrille , Crotti Corrado
Published: November 2006

We implemented high-resolution photoelectron spectroscopy using synchrotron radiation (160 eV photon energy) to investigate the electronics and chemistry at the interfaces of HfO2 (1 nm)/GeOxNy (0.6 nm)/Ge gate stacks. Ge3d core-level spectra show the formation of Hf-germanate at the bottom Ge oxide-high κ interface. Valence-band spectra highlight the presence of electronic N2p states in the Ge oxide band gap. The GeON/Ge valence band offset is determined as 1 eV{plus minus}0.2 eV.
High Reliability and Performance Poly-Si TFTs for System in Displays
Authors: Hatano Mutsuko , Matsumura Mieko , Toyota Yoshiaki , Tai Mitsuharu , Hamamura Hirotaka , Miyazawa Toshio , Ohkura Makoto
Published: November 2006

Narrow frame size IPS-mode LCD with high resolution system-in- display have been developed utilizing hybrid laser crystallization technology: SELAX are applied to low-power, high-speed circuits, and conventional ELC are used for the high- voltage circuits. The TFT degradation phenomena under dynamic stress are clarified, and the high-immunity TFT structure and high-quality gate insulator are proposed.
Design of Ultra-High Performance Si TFTs
Authors: Kawachi Genshiro
Published: November 2006

Design considerations for making use of ultra-high performance Si TFTs for future display systems are presented. Careful choice of the thickness and impurity concentration of the TFT channel is important to maximize the breakdown voltage. In the sub-micron regime, a lightly-doped-drain (LDD) structure is needed to suppress drain-induced phenomena. Layout design considerations based on the knowledge on the channel location dependence of device parameters and alignment method of TFT channels to the grain pattern are important to achieve high performance, while avoiding the undesirable effects of grain-boundary defects.
Development of ALD/PECVD Reactor for High Quality LTPS-TFTs Insulator
Authors: Murata Kazutoshi , Miyatake Naomasa , Mori Yasunari , Tachibana Hiroyuki , Uraoka Y. , Fuyuki Takashi
Published: November 2006

A high quality gate insulator is one of the key technologies for improving the performance of Low Temperature Poly Silicon TFTs. We propose an all-new stacked gate insulator, which is prepared with ALD technology for an interfacial layer, and a monopole antenna Plasma Enhanced Chemical Vapor Deposition (PECVD) technology for a secondary layer. The ALD/PECVD reactor, which handles glass substrates of 370 mm×470 mm in size was developed, and its performance was evaluated. Silicon dioxide films were deposited at 400°C with the reactor. Thickness variations of the ALD film and the PECVD film were confirmed to be less than {plus minus}5% and {plus minus}10%, respectively. The stacked insulator, which was composed of the 2nm-ALD film and the 100nm-PECVD film, had an excellent Si/SiO2 interface of 1×1011 cm-2eV-1 and breakdown electrical field of 7.5 MVcm-1.
Nanosecond Monitoring of Lateral Crystallization Dynamics Induced by ELA
Authors: Takami Yoshio , Warabisako Terunori , Matsumura M.
Published: November 2006

In this paper we report the direct observations of the lateral crystallizing process induced by single-pulse excimer laser annealing (ELA) for the first time. In order to modulate a beam profile on amorphous-silicon thin films intentionally, a mask projection type ELA system was used. Incorporating an optical microscope, a high speed gated image intensifier and a streak camera imaging system, a novel measuring system successfully revealed the dynamic lateral motion of liquid-solid Si interface with micrometer spatial resolution and nanosecond time domain. Furthermore, it was confirmed that the obtained streak images were well consistent with the simulated beam profiles to induce lateral growth crystallization, and the lateral solidifying velocity of 13m/sec was directly measured when 4μm-long grain had grown by phase-modulated excimer laser annealing (PMELA) method.
Poly-Si TFT Technology: Advances in Material, Process and Device Technology
Authors: Voutsas Apostolos T.
Published: November 2006

In this paper we present advances in poly-Si TFT technology driven by the demands of the next SOP generations. Improved Si crystallization technology enables significant reductions of the variability in TFT characteristics, due to improved defect control. Advanced gate insulator technology allows thickness scaling of the gate dielectric film (concomitant to device scaling) without loss of performance or reliability. New plasma deposition technology developed and optimized by our group provides for such improvements due to virtual elimination of inadvertent plasma damage in the dielectric film. Research on novel device architectures enables the integration of such process improvements with device structures that complement and customize device performance according to function. SLA's research and development will be the main thrust behind the next generation of novel display products and applications.
Poly-Si Thin Fim Transistor with Multiple Nanowire Channels Prepared by Excimer Laser Annealing
Authors: Lee Si-Chen , Meng Chao-Yu , Tsai Ming-Wei , Yang Po-Chuan
Published: November 2006

Low temperature (<500oC) polysilicon thin-film transistors (LTPS TFTs) prepared by KrF excimer laser annealing with multiple nanowire channels have been fabricated successfully. Grain boundary defects of poly-Si can be reduced effectively by multichannel structure. The ten 40 nm split channels TFT passivated by oxygen and NH3 plasma exhibits good electrical performance, i.e., high ON/OFF current ratio (>106), better subthreshold swing and suppressed kink effect.
Green Laser Crystallization of a-Si Films Using Preformed a-Si Lines
Authors: Brunets Ihor , Holleman Jisk , Kovalgin Alexey Y. , Aarnink Tom , Boogaard Arjen , Oesterlin Peter , Schmitz Jurriaan
Published: November 2006

In this work, amorphous silicon films with preformed a-Si lines were crystallized using a diode pumped solid state green laser irradiating at 532 nm. The possibility of controllable formation of grain boundaries was investigated. The crystallization processes in the rapidly melted silicon films were discussed. The influence of the crystallization parameters (i.e., energy density, scan velocity, etc.) and structure type (i.e., with and without preformed lines) on properties of the crystallized films was studied. The laser treatment with an energy density of 1.00 J/cm2 at a laser pulse overlapping of 90% provided the optimal crystallization process with predefined grain boundary location. X-ray diffraction (XRD), SEM and AFM microscopy have been used to characterize the crystallized silicon films.
A Simple Method for Gettering of Nickel within the NILC Polycrystalline Silicon Film Using a Gettering Substrate
Authors: Wu Yewchung S. , Hou Chih-Yuan , Lin Chi-Ching , Hu Chen-Ming
Published: November 2006

Ni-metal-induced lateral crystallization (NILC) of amorphous silicon (α-Si) has been employed to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). However, the current crystallization technology often leads to trapped Ni and NiSi2 precipitates, thus degrading the device performance. We proposed using α-Si- coated wafers as gettering substrates. By bonding the gettering substrate and NILC poly-Si film together, the Ni- metal impurity within the NILC poly-Si film was greatly reduced.
Overlay Alignment in a-Si:H TFTs Fabricated on Foil Substrates
Authors: Gleskova Helena , Cheng I-Chun , Kattamis Alexis Z. , Wagner Sigurd , Suo Zhigang
Published: November 2006

Thermo-mechanical theory of a device film-on-foil structure reveals that the layer-to-layer alignment accuracy and the radius of curvature of the structure are both controlled by the mismatch strain between the deposited films and the substrate. Amorphous silicon thin-film transistors fabricated on thin foils of steel or plastic must be grown with tensile built-in stress to make the structure as flat as possible, and for accurate layer-to-layer alignment.
Design, Fabrication and Characterization of Parylene-Packaged Thin-Film Transistors
Authors: Lo Hsi-Wen , Tai Yu-Chong
Published: November 2006

A micro-fabricated parylene-packaged flexible pentacene thin film transistor is presented. Different from preceding devices that have been reported, this thin film transistor employs parylene as the substrate, the gate insulator and also the encapsulation layer. Also, this thin film transistor uses pentacene, an organic semiconductor with high mobility, as the active material. The transistor consists of Au/Cr gates and Au source and drain electrodes and takes a bottom-contact configuration. The freshly made thin film transistor shows a hole mobility of 0.084809 cm2/V-s with an on-off ratio of 104.
Integrated Circuits Based on Amorphous Indium-Gallium-Zinc-Oxide-Channel Thin-Film Transistors
Authors: Ofuji Masato , Abe Katsumi , Kaji Nobuyuki , Hayashi Ryo , Sano Masafumi , Kumomi Hideya , Nomura Kenji , Kamiya Toshio , Hosono Hideo
Published: November 2006

Five-stage ring oscillators (ROs) composed of amorphous In-Ga- Zn-O (a-IGZO) channel TFTs were fabricated at room temperature with no post-deposition annealing. We observed oscillation of ROs with a variety of channel lengths and channel widths. A RO with channel lengths of 10 um operated at 21.5 kHz (propagation delay of 4.7 us / stage), when the external voltage of +18 V was supplied. A circuit simulation reproduced the measured output characteristics of ROs qualitatively, and also the simulated propagation delays agreed with the measured ones approximately.
The Abnormal Degradation Behavior of ZnO TFT Under Gate Bias Stress
Authors: Hwang Chi-Sun , Ko Park Sang Hee , Chung Sung Mook , Lee Jeong-Ik , Yang Yong Suk , Do Lee-Mi , Chu Hye Yong
Published: November 2006

ZnO TFT was fabricated using ALD deposited materials. The temperature dependence of transfer characteristics and the degradation behavior under gate bias stress was observed. The shift of Vth under gate bias stress was explained through electron trapping and H movement.
Thin-Film Transistors in Disordered Semiconductors for High Performance Macroelectronic Circuits.
Authors: Balon Frantisek , Shannon John M. M.
Published: November 2006

In general the performance of circuits in macroelectronic systems depends on the quality of semiconductor material used to make the devices. In this paper it is suggested that by using a different device structure based on the source-gated concept we can overcome intrinsic material problems and achieve much better device speed and stability in all disordered and poor quality semiconductors. Experimental and modeling results, on the most commonly used disordered material, amorphous silicon, show that high performance thin- film devices and circuits based on the SGT concept are a real possibility.
Artificial Retina using Thin-Film Photodiode and Thin-Film Transistor
Authors: Kimura Mutsumi , Shima Takehiro , Yamashita Takehiko
Published: November 2006

An artificial retina using thin-film photodiodes (TFPDs) and thin-film transistors (TFTs) is proposed, which is an improvement of system-on-panel (SOP) concepts where in-pixel and pixel-to-pixel operations are executed using the TFTs. Device characteristics of the TFPD and TFTs are measured, and they are modeled into circuit simulation. Circuit configurations of a retina pixel and retina array are invented with some improvements, and they are designed. It is confirmed that the artificial retina can operate and achieve edge enhancement. Behavior tolerance against characteristic deviations of the TFTs and photo-sensitivity control of the edge enhancement are evaluated.
New Heterostructures and 3D Devices Obtained at CEA/LETI by the Bonding and Thinning Method
Authors: Di Cioccio Léa
Published: November 2006

Direct wafer bonding and thinning technologies are now extensively used in combination to produce SOI wafers. Emerging demands of new functionalities at the material or device level for 3D integration have allowed to increase the level of maturity of these technologies. This paper deals with the innovative 3D substrates and devices we have obtained in the frame of fruitful collaborations.
Automotive Semiconductor Devices Using Bonded SOI Wafers
Authors: Fujino Seiji , Himi Hiroaki
Published: November 2006

The SOI structure is excellent for electric isolation between devices and it can markedly improve noise-immunity and thermo- tolerance, which are demanded for automotive semiconductor devices. It makes possible to integrate various functions and also it makes possible to integrate the multi-voltage devices, which operate under the different common-voltage conditions. Moreover, in the field of MEMS, unique sensors can be realized by using the SOI features such as stop-etching. In this paper, several devices are introduced, that we have developed using unique features of SOI.
Thin Film Transfer for the Fabrication of Multiple Gate MOS Transistors
Authors: Olbrechts Benoit , Södervall Ulf , Bengtsson S. , Raskin Jean-Pierre
Published: November 2006

A new approach in double gate devices processing based on the wafer bonding of a thin SOI film on pre-etched cavities is presented. In this context, wafer bonding parameters are analyzed. The effects of surface activation and annealing conditions are qualified, quantified and a viable solution is proposed.
Si-Based Resonant Tunneling Devices Using UHV Wafer Bonding
Authors: Kim Moon , Lee Taehun , Kim Jiyoung , Wallace Robert M. , Gnade Bruce
Published: November 2006

While resonant tunneling-based quantum devices have been studied extensively in compound semiconductors, there has been limited work on silicon-based resonant tunneling diode (RTD) devices, especially with processes that are compatible with scaled silicon CMOS processing. The indirect band gap of Si (and Ge) results in significant challenges for these structures. In the case of RTDs, the biggest problem has been the ability to fabricate high quality dielectric - semiconductor interfaces, and high quality crystalline silicon quantum wells, at the dimensions required for resonant tunneling devices. To date, most approaches used to demonstrate siliconbased RTDs have been based on using single crystal, epitaxial dielectrics, with lattice constants similar to those of silicon, in order to allow for the growth of high quality, single crystal silicon for the quantum well. Past attempts to produce silicon-based resonant tunneling devices based on CaF2 barriers have been hampered by poor quality interfaces and the inability to grow high quality silicon on single crystal CaF2.
Cu-Cu Room Temperature Bonding - Current Status of Surface Activated Bonding(SAB) -
Authors: Suga T.
Published: November 2006

Low temperature process has long been a technological goal of interconnect and boding of solid materials. Especially it is inevitable for interconnections or joints on a small area between dissimilar materials, because a small amount of reaction products at the bonded interface may degrade the bond reliability and the thermal expansion mismatch between dissimilar materials may reduce the bond strength of the interface. Such problems can be solved only by decreasing the bonding temperature. The surface activated boding (SAB) is a highly potential method providing a low temperature bonding process.
Low Temperature Bonding of PECVD Silicon Dioxide Layers
Authors: Baine Paul T. , Bain Michael , McNeill D. W. , Gamble Harold S , Armstrong Mervyn
Published: November 2006

The bonding of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide layers, deposited at 300oC, to thermal silicon dioxide layers is described. The PECVD oxide requires pre-bond annealing and CMP for void free bonding. Post bond annealing for bond strengthening must be performed at a lower temperature than the pre-bond annealing step. Bond strengths of 1J/m2 have been achieved after bond annealing at 400oC. This bonding method can be used in layer/circuit transfer and has been demonstrated with the transfer of a 2µm SOI layer from one substrate to another.
Plasma Assisted Low-Temperature Hydrophobic Wafer Bonding
Authors: Breninford Michael P. , Bailey David , Ikram Hamid , Colinge C. A. , Holl Susan
Published: November 2006

The effect of argon plasma treatment prior to hydrophobic bonding of silicon wafers was investigated. Bonded wafers were annealed at 400{degree sign}C for up to 96-hours and bond-strength analysis was performed. Experimental results revealed that plasma exposure of electrically isolated (floating) wafers for a period of 7- seconds followed by HF treatment, room temperature bonding, and 400{degree sign}C anneal resulted in bonded wafers with bond strength equivalent to that of silicon's fracture surface energy.
Non-Destructive Strength Characterization of Full-Wafer Bonds: A Modified Blister Test Method Enables a Controlled Crack Formation at the Bond Interface
Authors: Rabold Martin , Doll Alexander , Goldschmidtboeing Frank , Woias Peter
Published: November 2006

This article presents a novel test method for a non- destructive strength characterization of bonded wafer pairs. The test is based on a modification of the common, destructive blister test. Thereby, special geometries enable a controlled crack generation at the bond interface. Based on the theory of energy conservation, a theoretical model was built up and a novel crack propagation parameter was introduced. Three test strategies were established - an analog strategy, that can be used for a very accurate measurement, a digital strategy, that enables a redundant test analysis and finally a binary strategy, that can be used as bond gauge to guarantee a certain bond strength. Due to the complexity of the test structures, analytical models in combination with numerical simulations were used for the geometric design. Bonded wafers including these test structures were fabricated and the bond strength was measured to verify the theoretical model in practice.
Comparison of the Mechanical Properties of Low Temperature Bonded Test Samples
Authors: Bagdahn Joerg , Bernasch Michael , Fischer Carola , Wiemer Maik
Published: November 2006

The fabrication of silicon microelectromechanical components (MEMS) involves joining of two or even more wafers. During the last years special focus was given on low temperature wafer- bonding. In this paper an universal test wafer is proposed that can be applied for bond strength quality monitoring. The investigated wafers in this study were activated, wafer- bonded, annealed at 200 {degree sign}C or 400 {degree sign}C and subsequently tested with respect to dicing yield, tensile strength, fracture toughness, and surface energy. The wafer bonding was performed by seven different partners. It was shown that the bonding quality varied significantly for the different activation technologies even for the same annealing conditions. In general the special treated samples exceed the values of a RCA pre-treated reference sample annealed at 200 {degree sign}C. Some of the activation technologies were able to create bonds that reached the value of RCA pre-treated reference samples, which were annealed at 900 {degree sign}C.
Dislocation-Induced Light Emission
Authors: Reiche Manfred , Kittler Martin , Wilhelm Thomas , Arguirov T. , Seifert Winfried , Yu X. , Mchedlidze T
Published: November 2006

Hydrophobic wafer bonding causes the formation of dislocation networks in the bonded interface. The structure of the dislocation network depends on the misorientation between both wafers during the bonding. The characterization of the dislocation networks proved that the luminescence depends only on the structure of the dislocation network. Different degrees of misorientation cause that different lines in the PL- and CL- spectra appear. This makes it possible to construct monochromatic light sources.
Adhesive Bonding of III-V Dies to Processed SOI Using BCB for Photonic Applications
Authors: Roelkens Gunther , Batalliou Benoit , Brouckaert Joost , Van Laere Frederik , Van Thourhout Dries , Baets Roel
Published: November 2006

The bonding process of InP/InGaAsP dies to processed SOI using DVS-bis-BenzoCycloButene was developed. Surface preparation and the degree of planarization of bonding layers thinner than 300nm were optimized. Bonding strength and bonding quality was assessed, which shows to be sufficient for post-bonding processing. The heterogeneous integration of active photonic devices fabricated in this bonding layer on top of the SOI photonic layer is described.
Wafer Bonding of CdZnTe / Si Structures
Authors: Goorsky Mark S. , Miclaus C.
Published: November 2006

In this work, we demonstrate the transfer of Cd0.96Zn0.04Te layers to Si substrates by both bond and etch back and by ion exfoliation techniques. The (211)A face was employed for the bonding face to expose the pre-ferred (211)B face for subsequent HgCdTe growth. SiN intermediate lay-ers were used to facilitate the bond process. For the bond-and-etch proc-ess, 10 mm CdZnTe layers were transferred to silicon substrates. For ion-exfoliated layers, layers of 0.3 - 1 μm were transferred. The low level of implant-induced strain in the rpe-exfoliated layer is consistent with results from other materials. After transfer, these structures exhibited no strain and exhibited high crystal quality (as determined by double crystal x-ray topography and triple axis x-ray diffraction).
Low Temperature Plasma-Assisted-Wafer-Bonding for MEMS
Authors: Sanz-Velasco Anke , Bring Martin , Rödjegaård Henrik , Andersson Gert I. , Enoksson Peter
Published: November 2006

Bonding is one of the most important tools for the fabrication of Silicon On Insulator (SOI) material and building of MicroElectroMechanical Systems (MEMS). Nevertheless, the most significant limitation in prevalent bonding processes pertains to the high temperature required, limiting choices of materials and components. As a result of this problem, researchers have turned to bond at low temperature (LT). Unfortunately, the lack of fundamental knowledge on LT bonding procedures and their resulting bond interfaces, limits their application. Here electrical and mechanical properties of LT plasma-assisted-wafer bonding are addressed.
Chemical Nanotechnology: From Molecules to Applications
Authors: Mathur Sanjay , Shen Hao , Donia Nicole
Published: November 2006

The article reviews the potential of bottom-up chemical methodologies in synthesizing nanoscopic materials, and evaluates the influence of chemistry involved in materials processing on functional and structural properties of ceramics. Application of molecular sources in preparation of nanomaterials allows an intrinsic chemical encodingl in the initial stages of molecule-to-material transformation which plays an important role in tuning the properties of nanomaterials. Salient examples describing the precursor- structure-property-application relationship have been discussed to support the above arguments.
Transformation of Amorphous TiO2 Into Crystalline Materials
Authors: Reyes Coronado David , Oskam G. , Peet Poot Felipe
Published: November 2006

TiO2 is used in a variety of photochemical applications including catalysis, antibacterial coatings and dye-sensitized solar cells. The transformation of amorphous TiO2 into the three most common phases, anatase, rutile and brookite has been achieved under the appropriate experimental conditions. The amorphous TiO2 was obtained by adding titanium isopropoxide to isopropanol with a low concentration of water. A paste of amorphous titania was then mixed with different reactants and hydrothermally treated at elevated temperature in order to obtain a crystalline phase. Anatase nanoparticles were obtained by using acetic acid, while rutile nanoparticles were obtained using HCl. Titanates were formed with LiOH and KOH as reactants, while the use of NaOH results in brookite particles (>200 nm) after the formation of titanates as intermediate. The materials were characterized with X-ray diffraction and SEM.
Pulsed Laser Deposition of High-Quality Manganite Thin Films at Low Background Pressures with in-situ Reflection High Energy Electron Diffraction
Authors: Tebano Antonello , Aruta Carmela , Medaglia Pier Gianni , Balestrino Giuseppe , Boggio Norberto G. , Tozzi Feancesco , Davidson Bruce A.
Published: November 2006

We have developed a methodological approach which allows the deposition of high quality fully oxidized manganite thin films at low oxygen background pressure (10-4 - 10-3 mbar) by PLD. In such oxygen conditions the thickness of the deposited layer can be controlled at the level of a single unit cell by the use in situ of a conventional Reflection High Energy Electron Diffraction diagnostic. We show that by decreasing the laser fluence it is possible to improve the oxidation process in thin films under low background oxygen pressure. Films deposited at low laser fluence (about 0.2 J/cm2) show a two-dimensional growth mode and possess very good transport properties without the necessity of any further post-growth annealing treatment. A physical model, based on the plume-background interaction as a primary mechanism of film oxidation during growth, is proposed to explain the experimental findings.
Electrodeposition of Cu/Alumina and Ni/Alumina Nanocomposites
Authors: Bund Andreas , Thiemig Denny
Published: November 2006

This paper discusses recent results from the authors' lab on the electrocodeposition of Cu/alumina and Ni/alumina nanocomposites. A variety of electrolytes was investigated covering the pH range from 2 to 10. The particle content, the micro hardness (Vickers), and the electric conductivity of the layers were characterized and their dependence on the deposition parameters (current density, pH, etc.) is discussed. The pH of the bath directly affects the surface charge of the particles. This has been verified by zeta potential measurements in diluted electrolytes. One interesting result was that negatively charged particles are more easily codeposited compared to positively charged ones. At the first glance this result seems a little bit counterintuitive: why should a negative surface charge be favorable in a cathodic deposition process? A simple electrostatic model will be presented which can explain this finding.
A Scalable Method for the Synthesis of Metal Oxide Nanowires
Authors: Sunkara Mahendra K. , Thangala Jyothish , Vaddiraju Sreeram , Bogale Rahel , Thurman Ryan , Deb Biswapriya , Powers Trevor
Published: November 2006

We report a novel, scaleable and versatile method for large scale synthesis of tungsten trioxide nanowires and their arrays on a variety of substrates including amorphous quartz, fluorinated tin oxide, etc. The synthesis concept uses the chemical vapor transport of metal oxide vapor phase species onto substrates using air or oxygen flow over hot-filament sources. The hot-filaments were designed to provide uniform heating and gas phase composition over large substrate areas. The results show that the nucleation densities could be varied from 106/cm2 to 1010/cm2 with decreasing substrate temperature. A thermodynamic model for determining the nucleation density and nanowire diameter is presented. The analysis indicates that the nucleation for nanowires occurs through condensation of sub-oxide, WO2 species. This is in contrast to WO3 species condensation into WO3 solid phase for nanoparticle formation. The dispersion behavior of as- synthesized nanowires in aqueous and organic solvents is also studied.
Effects of Calcination Temperature and Zinc Source Concentration on Chemical-Solution Synthesized ZnO Nanorod
Authors: Cheong Kuan Y. , Hussin Hartini , Ismail Khairul
Published: November 2006

In this paper, ZnO nanoparticles, in particular nanorods, were prepared by a time-saving and a cost effective chemical- solution process. Zinc acetate dehydrates, 2-propanol and diethanolamine were used as the source to produce a well controlled precursor. The effects of calcination temperature (200 to 1000oC) and mole ratio of zinc source to 2-propanol on ZnO particle size and shape were systematically investigated. Results indicated that a single phase and orientated at [0001] direction ZnO has been obtained at calcinations temperature higher than 200oC. In addition, hexagonal-shaped nanorod, with diameter and length ranging from 20 to 150 nm and 100 to 250 nm, respectively, were observed at samples calcinated at 400 and 600{degree sign}C. As the temperature increased beyond 800 {degree sign}C, the sizes of nanoparticles became larger with irregular shape. In contrast, by varying the investigated mole ratio, no significant effect on the shape and size of the nanoparticles were observed.
Proton Conducting Composite Membranes from Polyether Ether Ketone and Hydrated Metal Oxides
Authors: D'Epifanio Alessandra , Mecheri Barbara , Traversa E. , Miyayama Masaru , Licoccia Silvia
Published: November 2006

Composite membranes based on sulfonated polyether ether ketone (SPEEK) and hydrated tin oxide (SnO2·nH2O) were prepared and characterized. The formation of the composite substantially modified the properties of SPEEK in terms of water uptake and solubility. The structural and electrochemical performance of the samples were investigated by simultaneous thermogravimetric and differential thermal analyses (TG-DTA), X-ray diffraction and electrochemical impedance spectroscopy (EIS). Proton conductivity measurements were carried out on the composite systems as a function of temperature and relative humidity in the 20-100 % RH range. The polymer electrolyte membranes doped with SnO2·n(H2O) showed an increase in electrical performance that can be attributed to the formation of a coordinative interaction between the water molecule of the metal oxide and -SO3H groups of SPEEK. Conductivity values of the composite SPEEK/SnO2·n(H2O) demonstrated that it possesses good proton transport characteristics and it is then suitable for application as electrolyte in Polymer Electrolyte Fuel Cells
Dense Intra-Cavity Interconnection Technology for Hermetically Packaged MMICs
Authors: Chang-Chien Patty , Tornquist Kelly , Zeng Xianglin , Luo Ke , Yang J , Kho Keang , Uyeda Jansen , Lai Richard , Oki Aaron
Published: November 2006

Northrop Grumman Space Technology has recently developed a technology that is capable of creating dense intra- cavity interconnections (ICICs) for hermetically packaged MMICs. These interconnections provide signal routing between circuits residing on the facing surfaces within the sealed wafer level package. They are fabricated by batch processes and are fully compatible with NGST's MMIC production processes. Greater than 90% interconnection yield is consistently obtained from different substrate material combinations. RF ICIC transitions with insertion loss of less than 0.1dB at 15GHz have been demonstrated. These ICICs are also proven to be mechanically and thermally robust. NGST's dense ICIC technology enables heterogeneous integration of multi-functional MMICs and MMIC modules.
Visible Light Active Carbon Modified (CM)-n-TiO2 Nanotubes for Efficient Photoelectrochemical Splitting of Water
Authors: Khan Shahed U. , Xu Chengkun , Shaban Yasser A. , Ingler William B.
Published: November 2006

Carbon modified (CM)-n-TiO2 nanotube arrays were successfully synthesized by anodization of Ti metal sheet in fluoride solution and subsequent annealing in air and natural gas flame oxidation. Both nanotube structure and carbon doping contributed to the enhancement of photoresponse of n-TiO2. About two fold increase in photocurrent density was observed at n-TiO2 nanotube compared to its thin film photoanode. Also, about two fold increase in photocurrent density was observed at carbon modified (CM)-n-TiO2 nanotube compared to its thin film photoanode. The sample prepared by anodization at 20 V cell voltage for 20 h followed by annealing in air at 500 0C for 1 h and natural gas flame oxidation at 820 0C for 18 min produced highest photocurrent density. It was found that the bandgap of n-TiO2 was reduced to 2.84 eV and an additional intragap band was introduced in the gap at 1.30 eV above the valence band. The bandgap reduction and the new intragap band formation in CM-n-TiO2 extended its utilization of solar energy up to the visible to infrared region.
Current Status of Field Aided Lateral Crystallization
Authors: Choi Duck-Kyun , Kim Hyun-Chul , Han Tae-Seok , Kim Young-Bae
Published: November 2006

As a low temperature crystallization process, the field-aided lateral crystallization (FALC) technique possesses outstanding advantages such as directional crystallization, high crystallization rate and inherent gettering effect owing to the effect of electric field and can lead on to high performance transistors. It turned out that the FALC behaviors resulted from the competition between electromigration effect and the magnitude of potential gradient. In order to demonstrate the feasibility of FALC process, an array of FALC processed poly-Si TFT was fabricated. The transistor characteristics were evaluated and compared to those fabricated without an electric field.
Improved GaN Homo-Junction, Ultraviolet, Light-Emitting Diodes Grown on Step-Free 4H-SiC Mesas
Authors: Caldwell Joshua D. , Mastro Michael , Hobart K. D. , Glembocki Orest , Eddy Charles R. , Bassim Nabil , Tadjer Marko , Holm Ronald , Henry Richard , Twigg Mark , Neudeck Phillip , Trunek Andrew , Powell J. Anthony , Kub Fritz J.
Published: November 2006

We report improvements in ultraviolet (380 nm) electroluminescence (EL) output of GaN pn homojunctions grown on 4H-SiC mesas with step-free surfaces of 49% on average in comparison to their stepped counterparts. The GaN on step-free 4H-SiC growth process has been previously reported to lead to 100-fold reductions in threading dislocation densities in III-N heterofilms. Despite the intense EL from the GaN on step-free SiC devices, significant current leakage was observed through the periphery of the device, possibly due to the lack of GaN junction isolation processing.
Ammonia Impurities Critical To The Performance Of Nitride Semiconductor Devices
Authors: Torres Robert , Chyi Jen Inn , Chen G T , Wyse Carrie , Vininski Joseph
Published: November 2006

AlGaN/GaN HEMT devices were grown under specific experimental conditions designed to elucidate the effects of purification of the ammonia gas. Two different, commercially available, purifiers were tested under identical growth conditions along with three different grades of ammonia. After growth of the AlGaN/GaN layers, the wafers were subjected to Hall measurements where the sheet concentration, and mobility, were determined. The results clearly showed significantly enhanced performance for the inorganic based purifier compared to the resin based organometallic purifier for all experimental parameters tested. Additionally, the nitride devices were subjected to SIMS analysis with depth profiling in an attempt to identify the elemental nature of the impurities that caused the discrepancy in performance results between the various samples. Results from the Hall measurements and the SIMS analysis are presented and correlated to the conditions controlled during the growth of the nitride devices.
Recent Achievement in the GaN Epitaxy on Silicon and Engineering Substrates
Authors: Thuret Julien , Bove Philippe , Lahreche Hacene , Wilk A. , Lijadi M , Langer R
Published: November 2006

Since the middle of the 90's, many techniques of growing GaN epitaxy have been developed, using either MOCVD or MBE growth methods. Historically, Sapphire and Silicon Carbide have been primarily the substrates used to gorw the GaN Epilayers. The reason was the low mismatch between GaN and these Compounds semiconductors. However each of them has its drawbacks. Poor thermal conductivity for the Sapphire matters as far as the power density going through the device increases. About the SiC, the perfect material after Diamond to dissipate the heat, face significant challenges to increase substrates diameter greater than 3 inches. By going in these directions, the industrialization of the GaN Epitaxy won't be able to increase its capacity to large volume and large diameter and will remain as a technology for a niche market. Picogiga has worked on the development of alternative approach which assures the capability to increase production easily. Obviously because its maturity, its availability, Silicon substrates must be our best choice material. Secondly thank to the Smart-CutTM process developed by Soitec, Picogiga has transferred this new technique to the Compound Semiconductor. This technique has opened new ways to optimize the GaN technology, to improve performances, to remain cost competitive.