bluuebunny/crossref_metadata_2025 huggingface dataset:
On interprocess interaction in distributed architectures
Authors: Marovac Nenad
Published: July 2004

Computational concurrency has been with us for some time and is here to stay, particularly in the domain of distributed systems and fault-tolerant computers. Processes executing concurrently in such systems communicate in order to exchange information and to synchronize the activities they perform. Classical interprocess synchronization mechanisms, based on shared variables and semaphores, are neither efficient nor methodically sound; nor do they produce correct solutions when dealing with autonomous processes running on different processors.The purpose of this paper is to define the problem, submit the arguments against using shared variables and semaphores for interprocess synchronization in distributed systems, and to present a mechanism for handling interprocess interaction in such systems.
Addressing operations for automatic data structure accessing
Authors: Fenwick P. M.
Published: July 2004

Although present computers often provide excellent operations for data manipulation, data accessing is generally performed by manipulation of addresses with little recognition of the actual data structure of programs. In an attempt to overcome this deficiency, a technique is presented whereby all of the data-accessing algorithms are separated out into separate code streams which run as coroutines in a special address processor. The operations of this address processor are appropriate to the accessing of arrays and data structures. The resultant system is able to handle, in hardware, most of the data structures which are found in present programming languages.
Some applications of the implicit register reference
Authors: Yuen C. K.
Published: July 2004

It is suggested that instructions with implicit register references may be readily added to current computer processors in order to facilitate a number of common operations.
B - HIVE
Authors: Agrawal Dharma P. , Alexander Winser E.
Published: July 2004

A 24 node multiprocessor computer system is currently under development at the N. C. State University. A diameter oriented ALPHA structure is used for interconnecting the computers which will operate in a MIMD mode. A communications processor is added to each node to satisfy data communications requirements in an efficient manner in a packet switched environment. A host computer will be used for program development and compilation. The software complexity will be reduced by the use of a static mapping of the partitioned computational flow diagram representing the algorithm to be executed. The long range goal of this research project is to develop a hierarchical structure with each node being replaced by a cluster of simple processors which are custom designed to implement computational primitives associated with digital signal and image processing applications.
The performance enhancement of descriptor-based virtual memory systems through the use of associative registers
Authors: Brundage R. E. , Batson A. P.
Published: July 2004

Contemporary paged virtual memory systems often use associative registers to reduce access time to frequently-referenced pages. Here we examine the analogous use of associative registers in descriptorbased, symbolically-segmented virtual memory systems, where each segment contains an entire data structure as defined in a high-level language. Symbolic trace data from production Algol 60 programs were used to determine performance improvement as a function of the number of associative registers in the system. Our results indicate that, even for reasonably large programs, a hit ratio of 0.9 is achieved with only 4 associative registers. Increasing the number of associative registers to 8 gives a hit ratio of 0.98, which with current technology gives a performance improvement of at least 80% in addressing speed over a similar system without associative registers.
SPEAC
Authors: Marvel Orin E.
Published: July 2004

In the high data rate systems (> MHz) associated with signal processing, a standard stored program computer is not fast enough. At the present time, parallel (1, 2) and pipeline (3) architectures are being used to solve these computational problems.This paper describes a preprocessor which is optimized to perform sum-of-product operations with a "pipeline ripple through" architecture. A breadboard built to perform the "absolute difference" and "product" correlation functions using this architecture is described.
Hardware-software interactions in SYMBOL-2R's operating system
Authors: Richards H. , Oldehoeft A. E.
Published: July 2004

This paper describes the chief attributes of the Virtual Processor placed at the disposal of each user of the SYMBOL-2R time-shared multiprocessor system, and the mechanisms by which SYMBOL's hardwired operating system manages processing-mode transitions for individual Virtual Processors and allocates hardware resources -- processors and memory space -- among competing Virtual Processors. It describes the provisions by which the unusually high-level capabilities of the hardware are augmented by software, and contrasts the structure of the software component of the operating system with that of the hardware component. Finally, it describes the hardware/software partition of resource-allocation functions, in which allocation policies are controlled by software and executed by hardware.
A preliminary architecture for a basic data-flow processor
Authors: Dennis Jack B. , Misunas David P.
Published: July 2004

A processor is described which can achieve highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor is a step toward a practical data-flow processor for a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnecion that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.
On relating small computer performance to design parameters
Authors: Rannem S. , Hamacher V. C. , Zaky S. G. , Connolly P.
Published: July 2004

This paper presents a method for correlating performance measures of small computers to design parameters. An experiment is described in which execution times and memory space requirements are gathered for three small benchmark kernels when run on fifteen small computers. The benchmarks are drawn from three different application areas. All of them exercise only the CPU ↔ memory area of the machines, and I/0 operations are not involved.Using standard regression analysis techniques, this data is then used to calculate coefficients in empirical equations which relate the performance measures, time and space, to easily quantifiable design parameters of the machines.
SOCRATES
Authors: Foster Caxton C.
Published: July 2004

SOCRATES is a "Stack-Oriented Computer for Research and Teaching--an Exploratory System." It is designed around push down stacks as its main store. The structure of the machine is specified and several aspects of programming it are investigated.
A design-oriented computer engineering program
Authors: Sloan M. E.
Published: July 2004

Two national committees issued definitive computer curricula in the 1960s, Since then digital technology has changed, high school graduates have different preparation, computer science and computer engineering curricula have proliferated, and design has become more important. This paper proposes a computer engineering program that will respond to these changes. The program is a spiral one, based on an introductory computer engineering program, and emphasizing design through each of a number of streams that can reflect local interests and resources. This paper discusses the main courses of a stream and the basic introductory course.
An educational laboratory in contemporary digital design
Authors: Baron Janis Beitch , Atkins D. E.
Published: July 2004

Formal education in computer architecture rests upon the integration of numerous specialized courses. One such course, a new laboratory concerning contemporary, register-transfer level digital design, is described. Design in the course proceeds at the level of interconnection of memories, arithmetic logic units, I/O interfaces, and buses, rather than at the individual gate level associated with traditional combinational and sequential logic design. The principle items of hardware used in the laboratory are DEC Register Transfer Modules, the DEC PDP/16M, and the INTEL SIM8-01 Microcomputer. Numerous software packages have been developed to support activities within the lab including an RTM simulator, a graphical simulation of an RTM control sequencer, a PDP/16M assembler, a microcode generator, and SIM8-01 utility routine, assembler, and simulator. During one fourteen-week term, students are expected to complete six assigned lab projects and one special project. Examples of projects are described. A critique based upon the students' reactions and the technician's experience with the equipment is given together with proposals for future additions to the course.
A unified decimal floating-point architecture for the support of high-level languages
Authors: Ris Frederic N.
Published: July 2004

This paper summarizes a proposal for a decimal floating-point arithmetic interface for the support of high-level languages, consisting both of the arithmetic operations observed by application programs and facilities to produce subroutine libraries accessible from these programs. What is not included here are the detailed motivations, examinations of alternatives, and implementation considerations which will appear in the full work.
Application of the military computer family architecture selection criteria to the PR1ME P400
Authors: Mountain John B. , Enslow Philip H.
Published: July 2004

The evluation criteria and procedures developed by the Army-Navy Comittee on military computer family architecture selection and utilized by that committee in the evaluation of nine candidate architectures were applied to the PR1ME 400 computer system. The result of this project provided a better understanding of the PR1ME 400 architecture, while at the same time, highlighted some of the problems in interpreting the committees' evaluation criteria and the problems in applying in such an evaluation procedure.
Multiprocessor architectures for concurrent programs
Authors: Hansen Per Brinch
Published: July 2004

This paper proposes a hierarchical multiprocessor architecture for real-time programs written in a concurrent programming language. The use of processes and monitors leads to a multiprocessor system in which each processor has a local store dedicated to a single process. The processors share a common store that contains the monitors. To avoid congestion in the common store the processes and monitors are partitioned into subsystems that share a hierarchy of common stores. The main goal is to develop a synthesis of an abstract language and a computer architecture that match in an obvious way.
On processes and interrupts
Authors: Gerrity G. W.
Published: July 2004

The key concept of a process in a multi-program, multi-processor operating system is examined in detail to highlight areas where appropriate hardware support can yield benefits. A sketch of one architecture providing appropriate support is given in sufficient detail to illustrate its flexibility and its low time and space overhead.
Modelling and performance evaluation of multiprocessors, organizations with multi-memory units
Authors: Naderi M.
Published: July 2004

In a multiprocessors configuration, a memory conflict occurs whenever two or more processors or I/O, s attempt to access the same memory unit simultaneously. The overall effect of these conflicts are lose of the system efficiency. A multiprocessor activity during execution of a program has been considered as a stochostic process which moves through a countable set of states. The process decides where to go next by a random mechanism which depends only on the current state and not on the previous history or even on the time. This kind of process is called Markov process. The transition from any state is possible only to the neighbouring states due to these conditions that the arrivale of request rate from processors and the memory communication rate follow a poisson distribution. Under these assumations a multi-server waiting line model has been developed for a multi-processors organisation. The basic motivation for this investigation will be the search to find a set of system parameters to measure the multiprocessors. performance with multi-memory nuits.The Makrovian waiting line model has been emplayed and obtained a general solution to estimate the effect of memory conflict on the average number of waiting units in the system, idle and busy periods for memory unit, system efficiency, the stretching factor of program on bases of "First Com, First Served" descipline.The simulation programs written by Basic to implement the developed waiting line model are general enough so that a system configuration of any size can be studied.
Architecture and compiler tradeoffs for a long instruction wordprocessor
Authors: Cohn Robert , Gross Thomas , Lam Monica
Published: July 2004

A very long instruction word (VLIW) processor exploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compiler tradeoffs in the design of iWarp, a VLIW single-chip microprocessor developed in a joint project with Intel Corp. The iWarp processor is capable of specifying up to nine operations in an instruction word and has a peak performance of 20 million floating-point operations and 20 million integer operations per second. An optimizing compiler has been constructed and used as a tool to evaluate the different architectural proposals in the development of iWarp. We present here the analysis and compiler optimizations for those architectural features that address two key issues in the design of a VLIW microprocessor: code density and a streamlined execution cycle. We support the results of our analysis with performance data for the Livermore Loops and a selection of programs from the LINPACK library.
Using registers to optimize cross-domain call performance
Authors: Karger Paul A.
Published: July 2004

This paper describes a new technique to improve the performance of cross-domain calls and returns in a capability-based computer system. Using register optimization information obtained from the compiler, a trusted linker can minimize the number of registers that must be saved, restored, or cleared when changing from one protection domain to another. The size of the performance gain depends on the level of trust between the calling and called protection domains. The paper presents alternate implementations for an extended VAX architecture and for a RISC architecture and reports performance measurements done on a re-microprogrammed VAX-11/730 processor.
A message driven OR-parallel machine
Authors: Delgado-Rannauro S. A. , Reynolds T. J.
Published: July 2004

A message driven architecture for the execution of OR-parallel logic languages is proposed. The computational model is based on well known compilation techniques for Logic Languages. We present first the multiple binding mechanism for the OR-parallel Prolog architecture and the corresponding OR-parallel abstract machine is described. A scheduling algorithm which does not rely upon the availability of global data structures to direct the search for work is discussed. The message driven processor, the processing node of the parallel machine, is designed to interact with a shared global address space and to efficiently process messages from other processing nodes. We discuss some of the results obtained from a high level functional simulator of the message driven machine.
Beyond striping: the bridge multiprocessor file system
Authors: Dibble P. C. , Scott M. L.
Published: July 2004

High-performance parallel computers require high-performance file systems. Exotic I/O hardware will be of little use if file system software runs on a single processor of a many-processor machine. We believe that cost-effective I/O for large multiprocessors can best be obtained by spreading both data and file system computation over a large number of processors and disks. To assess the effectiveness of this approach, we have implemented a prototype system called Bridge, and have studied its performance on several data intensive applications, among them external sorting. A detailed analysis of our sorting algorithm indicates that Bridge can profitably be used on configurations in excess of one hundred processors with disks. Empirical results on a 32-processor implementation agree with the analysis, providing us with a high degree of confidence in this prediction. Based on our experience, we argue that file systems such as Bridge will satisfy the I/O needs of a wide range of parallel architectures and applications.
Disk array performance in a random IO environment
Authors: Oslon T. M.
Published: July 2004

Large arrays of disks have been proposed as a way to meet the need for increasing IO bandwidth. This paper examines disk array performance in a random IO environment. It also presents the results of performance testing using the Prime IOBENCH™ benchmark on a combination of disk striping, RAID 1, and RAID 5 disk arrays. It concludes, that for a given number of disk drives, that both RAID 1 and RAID 5 have acceptable performance in a read environment, while RAID 5 degrades significantly in an update intensive environment.
An analysis of server-based locking
Authors: Wolman B. L.
Published: July 2004

This paper discusses the performance implications of using server-based locking instead of shared memory locking in an input/output (IO) intensive benchmark. Uniprocessor and multiprocessor systems were investigated. Server-based locking was not a problem in uniprocessor runs or in multiprocessor runs that were processor limited. Server-based locking resulted in a significant degradation in throughput of IO limited multiprocessor runs.
A multiprocessor configuration in accordance with the aspects of physical and systems design
Authors: Oyang Y.-J.
Published: July 2004

A new multiprocessor configuration that exploits process-level parallelism is proposed. The objective is to define a configuration for next generation multiprocessor systems. The new configuration is a direct result of careful examination of the aspects of physical and system design and the development of integrated circuit technology. The new configuration eliminates the major problems that limit the expansion capability of the conventional configurations and thus paves the path toward higher performance systems.
Evaluating the performance of four snooping cache coherency protocols
Authors: Eggers S. J. , Katz R. H.
Published: July 2004

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large cache sizes will hurt write-broadcast. Read-broadcast and competitive snooping extensions to the protocols have been proposed to solve each problem.

Our results indicate that the benefits of the extensions are limited. Read-broadcast reduces the number of invalidation misses, but at a high cost in processor lockout from the cache. The net effect can be an increase in total execution cycles. Competitive snooping benefits only those programs with high per-processor locality of reference to shared data. For programs characterized by inter-processor contention for shared addresses, competitive snooping can degrade performance by causing a slight increase in bus utilization and total execution time.
Architectural mechanisms to support sparse vector processing
Authors: Ibbett R. N. , Hopkins T. M. , McKinnon K. I. M.
Published: July 2004

We discuss the algorithmic steps involved in common sparse matrix problems, with particular emphasis on linear programming by the revised simplex method. We then propose new architectural mechanisms which are being built into an experimental machine, the Edinburgh Sparse Processor, and which enable vector instructions to operate efficiently on sparse vectors stored in compressed form. Finally, we review the use of these new mechanisms on the linear programming problem.
2-D SIMD algorithms in the perfect shuffle networks
Authors: Ben-Asher Y. , Egozi D. , Schuster A.
Published: July 2004

This paper studies a set of basic algorithms for SIMD Perfect Shuffle networks. These algorithms where studied in several papers, but for the 1-D case, where the size of the problem
N
is the same as the number of processors
P
. For the 2-D case of
N = L * P
, studied by [GK-80] and [Kr-81], we improve several algorithms, achieving run time Ο(
L
+ log
P
) rather than Ο(
L
* log
P
), as
N
exceeds
P
. We give non-trivial algorithms for the following 2-D operations: Row-Reduction, Parallel-Prefix, Transpose, Smoothing and Cartesian-Product.
Systematic hardware adaptation of systolic algorithms
Authors: Valero-Garcia M. , Navarro J. J. , Llaberia J. M. , Valero M.
Published: July 2004

In this paper we propose a methodology to adapt Systolic Algorithms to the hardware selected for their implementation. Systolic Algorithms obtained can be efficiently implemented using Pipelined Functional Units. The methodology is based on two transformation rules. These rules are applied to an initial Systolic Algorithm, possibly obtained through one of the design methodologies proposed by other authors. Parameters for these transformations are obtained from the specification of the hardware to be used. The methodology has been particularized in the case of one-dimensional Systolic Algorithms with data contraflow.
Supporting reference and dirty bits in SPUR's virtual address cache
Authors: Wood D. A. , Katz R. H.
Published: July 2004

Virtual address caches can provide faster access times than physical address caches, because translation is only required on cache misses. However, because we don't check the translation information on each cache access, maintaining reference and dirty bits is more difficult. In this paper we examine the trade-offs in supporting reference and dirty bits in a virtual address cache. We use measurements from a uniprocessor SPUR prototype to evaluate different alternatives. The prototype's built-in performance counters make it easy to determine the frequency of important events and to calculate performance metrics.

Our results indicate that dirty bits can be efficiently emulated with protection, and thus require no special hardware support. Although this can lead to
excess faults
when previously cached blocks are written, these account for only 19% of the total faults, on average. For reference bits, a
miss bit approximation
, which checks the references bits only on cache misses, leads to more page faults at smaller memory sizes. However, the additional overhead required to maintain true reference bits far exceeds the benefits of a lower fault rate.
Constructing replicated systems using processors with point-to-point communication links
Authors: Ezhilchelvan P. D. , Shrivastava S. K. , Tully A.
Published: July 2004

Replicated processing with majority voting is a well known method of achieving fault tolerance. We consider the problem of constructing a distributed system composed of an arbitrarily large number of N-modular redundant (NMR) nodes, where each node itself is composed of N, N = 2m + 1 and m ≥ 1, processing and voting elements. Advanced microprocessors, such as Inmos Transputers, provide fast serial communication links for inter-processor communication, making it possible to construct large networks of processors. We describe how replicated processing with majority voting can be achieved for such processor networks. This paper will present the overall systems architecture, including voting and NMR synchronization algorithms specially developed to exploit fast point to point communication facilities.
A type driven hardware engine for Prolog clause retrieval over a large knowledge base
Authors: Wong K.-F. , Williams M. H.
Published: July 2004

Whereas existing Prolog systems are very effective at handling small knowledge bases, they are not very efficient at and often incapable of handling large sets of clauses. Large knowledge bases which may comprise millions of clauses and are shared by a number of users, may need to reside in secondary memory. In such cases exhaustive search is inordinately slow. Various approaches have been put forward for handling the problem, most of which involve
coupled
systems (loosely or tightly coupled). A Prolog data/knowledge based system which provides an
integrated
solution to the problem is being developed. An essential element in this system is the CLAuse Retrieval Engine, CLARE, which is a special purpose hardware engine designed to perform selective retrieval of data from disk in order to identify all potential clauses which will be required for full unification during a query. The engine consists of two separate hardware components, which together form a two-stage filtering configuration. This paper concentrates on the second stage filter which is concerned with partial test unification.
Improving performance of small on-chip instruction caches
Authors: Farrens M. K. , Pleszkun a. R.
Published: July 2004

Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this instruction cache will cause an external memory reference which must compete with data references for access to the external memory, thus affecting the overall performance of the processor. One common way to reduce the number of off-chip instruction requests is to increase the size of the on-chip cache. An alternative approach is presented in this paper, in which a combination of an instruction cache, instruction queue and instruction queue buffer is used to achieve the same effect with a much smaller instruction cache size. Such an approach is significant for emerging technologies where high circuit densities are initially difficult to achieve yet a high level of performance is desired, or for more mature technologies where chip area can be used to provide more functionality. The viability of this approach is demonstrated by its implementation in an existing single-chip processor.
Can dataflow subsume von Neumann computing?
Authors: Nikhil R. S.
Published: July 2004

We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?” Starting with a simple, “RISC-like” instruction set, we show how to change the underlying processor organization to make it multithreaded. Then, we extend it with three instructions that give it a fine-grained, dataflow capability. We call the result P-RISC, for “Parallel RISC.” Finally, we discuss memory support for such multiprocessors. We compare our approach to existing MIMD machines and to other dataflow machines.
Multiple vs. wide shared bus multiprocessors
Authors: Hopper A. , Jones A. , Lioupis D.
Published: July 2004

In this paper we compare the simulated performance of a family of multiprocessor architectures based on a global shared memory. The processors are connected to the memory through caches that snoop one or more shared buses in crossbar arrangement.

We have simulated a number of configurations in order to assess the relative performance of multiple versus wide bus machines, with varying amounts of prefetch. Four programs, with widely differing characteristics, were run on each configuration. The configurations that gave the best all-round results were multiple narrow buses with 4 words of prefetch.
Analysis of computation-communication issues in dynamic dataflow architectures
Authors: Ghosal D.S. , Tripathi S. K. , Bhuyan L. N. , Jiang H.
Published: July 2004

This paper presents analytical results of computation-communication issues in dynamic dataflow architectures. The study is based on a generalized architecture which encompasses all the features of the proposed dynamic dataflow architectures. Based on the idea of characterizing dataflow graphs by their average parallelism, a queueing network model of the architecture is developed. Since the queueing network violates properties required for product from solution, a few approximations have been used. These approximations yield a multi-chain closed queueing network in which the population of each chain is related to the average parallelism of the dataflow graph executed in the architecture. Based on the model, we are able to study the effect on the performance of the system due to factors such as scalability, coarse grain vs. fine grain parallelism, degree of decentralized scheduling of dataflow instructions, and locality.
Logic simulation on massively parallel architectures
Authors: Kravitz S. , Bryant R. E. , Rutenbar R.
Published: July 2004

This work examines the mapping of logic simulation onto massively parallel computer architectures. We discuss alternative communication primitives for a massively parallel instruction set architecture and the impact of the choice of communication primitives on logic simulation. We have developed compilation tools to automatically map the simulation of an MOS transistor circuit onto a massively parallel computer. We analyze the efficiency of this mapping as a function of the available communication primitives. The compilation process is illustrated by describing our pilot implementation on a 32k processor Connection Machine.
An architecture framework for application-specific and scalable architectures
Authors: Mulder J. M. , Portier R. J. , Srivastava A. , in't Velt R.
Published: July 2004

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture.

The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;

This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.
An aperiodic storage scheme to reduce memory conflicts in vector processors
Authors: Weiss S.
Published: July 2004

One of the most noticeable differences between the CRAY-2 and its predecessors, the CRAY-1 and the CRAY X-MP, is a significantly longer memory path. This is a consequence of increasing the size of the memory at the expense of the bank access time. With a longer memory path, the impact of bank conflicts becomes more apparent. In this paper we study a storage strategy for vector processors that has the following properties: (1) it is aperiodic, (2) it tends to distribute references more uniformly over the memory banks, (3) the implementation of the addressing hardware is straightforward, and (4) the delay added to the memory path is minimal. The first two properties help in reducing the frequency of bank conflicts.
An efficient implementation of Boolean functions nd finite state machine as self-timed circuit
Authors: David Llana , Ginosar Ran , Yoeli Michael
Published: July 2004

Self-timed logic provides a method for designing logic circuits such that their correct behavior depends neither on the speed of their components nor on the delay along the communication wires. General synthesis methods for
efficiently
implementing self-timed combinational logic (CL) and finite state machines (FSM) are presented. The resulting CL is shown to require less gates than other proposed methods. The FSM is implemented by interconnecting a CL module with aself-timed master-slave register. The FSM synthesis method is also compared with other approaches. A formal system of behavioral sequential constraints is presented for each of the systems, and their behavior is proven correct. Thus, the synthesized CLs and FSMs can serve as "correct-by-construction" building blocks for self-timed silicon system compilation.
A hardware mechanism for priority queue
Authors: Hsu Tsong-Chih , Kung Ling-Yang
Published: July 2004

In this paper a hardware mechanism for supporting priority queues is described that provides the primitive operations on a priority queue. The principle mechanism for attaining this goal are a fast fully parallel Content Associative Memory (CAM), a high speed priority memory, and a good multiple--response resolver.
Fresh Breeze
Authors: Dennis Jack B.
Published: July 2004

It is well-known that multiprocessor systems are vastly more difficult to program than systems that support sequential programming models. In a 1998 paper[11] this author argued that six important principles for supporting modular software construction are often violated by the architectures proposed for multiprocessor computer systems. The Fresh Breeze project concerns the architecture and design of a multiprocessor chip that can achieve superior performance while honoring these six principles.The envisioned multiprocessor chip will incorporate three ideas that are significant departures from mainstream thinking about multiprocessor architecture: (1) Simultaneous multithreading has been shown to have performance advantages relative to contemporary superscalar designs. This advantage can be exploited through use of a programming model that exposes parallelism in the form of multiple threads of computation. (2) The value of a shared address space is widely appreciated. Through the use of 64-bit pointers, the conventional distinction between "memory" and the file system can be abolished. This can provide a superior execution environment in support of program modularity and software reuse, as well as supporting multi-user data protection and security that is consistent with modular software structure. (3) No memory update; cycle-free heap. Data items are created, used, and released, but never modified once created. The allocation, release, and garbage collection of fixed-size chunks of memory will be implemented by efficient hardware mechanisms. A major benefit of this choice is that the multiprocessor cache coherence problem vanishes: any object retrieved from the memory system is immutable. In addition, it is easy to prevent the formation of pointer cycles, simplifying the design of memory management support.
On cache memory hierarchy for Chip-Multiprocessor
Authors: Zahran Mohamed M.
Published: July 2004

Advances in integrated circuit technology have led the microprocessor design to more challenging areas by providing a high budget of transistors. The one billion microprocessor is not that far from now. This leads microarchitects to look for efficient ways to make use of this feature. Chip-Multiprocessor (CMP) is one of the strong candidates in this area. Memory system for any multiprocessor is a pivotal part and can boost the performance or decrease it dramatically. The purpose of this study is to investigate the most appropriate cache memory hierarchy for CMP. We provide comparisons between several candidates and present a conclusion that can lead to better performance for CMP as well as the configurations that must be avoided.
Indirect VLIW memory allocation for the ManArray multiprocessor DSP
Authors: Pitsianis Nikos P. , Pechanek Gerald G.
Published: July 2004

The indirect very long instruction word (iVLIW) architecture and its implementation on the BOPS ManArray family of multiprocessor digital signal processors (DSP) provides a scalable alternative to the wide instruction busses usually required in a multiprocessor VLIW DSP. The ManArray processors indirectly access VLIWs from small caches of VLIWs localized in each processing element. With this work, we present an algorithm to perform 1) iVLIW instruction memory allocation on multiple processing elements to minimize instruction memory requirements and 2) scheduling of the iVLIW setup instructions to minimize execution overhead. We present preliminary experimental results that demonstrate the effectiveness of our approach.
A transparent Linux super page kernel for Alpha, Sparc64 and IA32
Authors: Shimizu Naohiko , Takatori Ken
Published: July 2004

Modern processors have various features for latency tolerance such as Hit-under-miss, Out-of-order execution, or Multi-threading. However, many processors must make a precise trap for a TLB miss, because they maintain the TLB with software and cannot distinguish the TLB scarcity from the page fault. It is very important for the application and/or the operating system to avoid the TLB misses as much as possible. Many processors have some super page features that extend the coverage of the TLB significantly, but few operating systems support it. In this paper, we present our implementation of Super Page Kernel for the Linux operating system along with its performance. We implemented Super Page for Alpha, Sparc64 and IA32. With super page kernel, a matrix transpose program runs at least 4 times faster on Alpha, at least 2 times faster on Sparc64, and generates interesting results on IA32 compared to the normal Linux kernel. In addition, we got SPEC CPU numbers that were about 10% higher than normal kernel on Alpha.
The pringle parallel computer
Authors: Kapauan Alejandro , Field J. Timothy , Gannon Dennis B. , Snyder Lawrence
Published: July 2004

The Pringle is a 64 processor MIMD computer with a 64 M (8 bit) instructions per second execution rate. (Copies are running at Purdue and Washington.) The Pringle runs programs written for the Configurable, Highly Parallel (CHiP) Computer. That is, the Pringle executes the 64 separate instruction streams as well as the interconnection (phase) stream that configures the lattice of a 64 processor CHiP computer. But the Pringle is not a CHiP. It gives the illusion of the CHiP machine's conflict-free, point-to-point communication using a 64 Mbit internal polled bus. In addition to describing the design goals and the Pringle architecture, this paper identifies two problems common to novel architecture implementation projects, the “wisdom of experience” problem and the “single instance” problem, and expalins how they were addressed for the Pringle.
The architecture of replica
Authors: Ma Y. W. , Krishnamurti R.
Published: July 2004

REPLICA is a special-purpose computer architecture to support active multi-sensory perception of 3-D objects. The system is partitionable, reconfigurable, and highly parallel. In this paper, we present the design of a set of interconnection networks which form the core of the REPLICA architecture. This set of interconnection networks consists of a capability-enhanced cross-bar switch and multiple fast shift-register rings. The capability-enhanced cross-bar switch supports rapid set-up of partitions, point-to-point communication and broadcasting communication between the controller and processors in a partition. The multiple rings support high bandwidth communications among the processors and also provide the partitionability and reconfigurability required by the system. The cost of these interconnection networks can also be kept low. The communication delay in the ring network is analyzed by deriving an upper bound on the maximum communication delay in a partition. A set of performance attributes for evaluating the performance of reconfigurable, partitionable, and highly parallel computer systems is proposed. Based on this set of attributes, the design of the REPLICA architecture is evaluated and compared with the other reconfigurable, partitionable, and highly parallel computer architectures in the literature.
A generalized object display processor architecture
Authors: Goldwasser Samuel M.
Published: July 2004

A multiprocessor architecture has been developed which addresses the problem of the display and manipulation of multiple shaded three dimensional objects derived from emperical data on a raster scan CRT. Fully general control of such parameters as position, size, orientation, rotation, tone scale, and shading are accomplished at video rates permitting real-time interaction with the display presentation.

The GODPA architecture is based on a large number of relatively simple processing elements which access their own memory modules without input conflict. Reconstruction algorithms are used which do not require any complex arithmetic or logical high speed operations. This hardware organization is highly modular and expandible and is ideally suited for implementation with VLSI technology.
The design and implementation of a VLSI chess move generator
Authors: Ebeling Carl , Palay Andrew
Published: July 2004

Communication is a basic problem when using VLSI technology to implement large parallel circuits. Valuable chip area must be used to run wires connecting components on a chip and current packaging technology restricts the amount of communication that can cross chip boundaries. This paper presents a large parallel architecture for generating moves in chess and shows how it can be restructured to reduce communication and permit a straightforward VLSI implementation without any performance loss. The result is a move generator comprising 64 identical custom chips performing at a rate of 500,000 moves per second, performance that is comparable to the best existing move generator.

The success of the architecture of a component module like a chess move generator depends not only on its performance but on how well it meshes with the rest of the system. We discuss the requirements of a chess move generator in the context of a chess-playing system and describe how each of these are met by our design. Details of the chip design are presented along with a description of how the move generator is built using identical chips.
Dictionary machines with a small number of processors
Authors: Fisher Allan L.
Published: July 2004

A number of tree-structured multiprocessor designs have been proposed for performing a group of dictionary operations (INSERT, DELETE, EXTRACTMIN, NEAR, etc.) on a set of keys. These designs typically use one processor for each key stored and operate with constant throughput, assuming unit time to communicate and compare keys. This assumption breaks down in applications with long keys. This paper describes a machine which uses a number of processors proportional to the maximum length of a key to achieve constant throughput, regardless of key length. This design has important practical advantages over the family of tree-structured machines, and demonstrates that processor-intensive VLSI structures are not always the best route to a high-performance system.
Experimental evaluation of on-chip microprocessor cache memories
Authors: Hill Mark D. , Smith Alan Jay
Published: July 2004

Advances in integrated circuit density are permitting the implementation on a single chip of functions and performance enhancements beyond those of a basic processors. One performance enhancement of proven value is a cache memory; placing a cache on the processor chip can reduce both mean memory access time and bus traffic. In this paper we use trace driven simulation to study design tradeoffs for small (on-chip) caches. Miss ratio and traffic ratio (bus traffic) are the metrics for cache performance. Particular attention is paid to sub-block caches (also known as sector caches), in which address tags are associated with blocks, each of which contains multiple sub-blocks; sub-blocks are the transfer unit. Using traces from two 16-bit architectures (Z8000, PDP-11) and two 32-bit architectures (VAX-11, System/370), we find that general purpose caches of 64 bytes (net size) are marginally useful in some cases, while 1024-byte caches perform fairly well; typical miss and traffic ratios for a 1024 byte (net size) cache, 4-way set associative with 8 byte blocks are: PDP-11: .039, .156, Z8000: .015, .060, VAX 11: .080, .160, Sys/370: .244, .489. (These figures are based on traces of user programs and the performance obtained in practice is likely to be less good.) The use of sub-blocks allows tradeoffs between miss ratio and traffic ratio for a given cache size. Load forward is quite useful. Extensive simulation results are presented.
The design of an object oriented architecture
Authors: Ishikawa Yutaka , TOKORO Mario
Published: July 2004

This paper proposes a new object model, called the
distributed object model,
wherein the model is unified as a protection unit, as a method of data abstraction, and as a computational unit, so as to realize reliable, maintainable, and secure systems. An object oriented architecture called
ZOOM
is designed based on this object model. A software simulator and cross assembler for this architecture have been implemented. The feasibility and performance of the architecture are discussed according to program sizes and estimated hardware size and execution speed.
Design of instruction set architectures for support of high-level languages
Authors: Bose Pradip , Davidson Edward S.
Published: July 2004

Conventional instruction sets or directly interpretable languages (DILs) have not been designed with high-level languages (HLLs) in mind. The modern design problem is to derive a space-time efficient DIL for a HLL processing system. In this paper, we present our approach to the problem of designing well-matched, space-time efficient DILs. A systematic, syntax- and semantics-directed DIL design methodology is presented. It calls for an incremental transformation of the source HLL, until a suitable target DIL is obtained. At the heart of the methodology is a canonic set of language transformations. An experimental study, involving several systematically derived DILs is carried out in order to characterize the relative merits and disadvantages of various sequences of transformations. Various space, time and interpretability trade-offs implied by the transformations are studied.
On the performance of loosely coupled multiprocessors
Authors: Bhuyan Laxmi N.
Published: July 2004

A Processing Element (PE) essentially consists of a processor and a memory module. A loosely coupled multiprocessor is comprised of a set of such PEs interconnected through an Interconnection Network (IN). The design of the IN is crucial to an efficient communication beween the PEs. This paper presents approximate evaluations of two loosely coupled architectures, each having three types of INs, namely: shared bus, crossbar and a class of Multistage Interconnection Networks (MINS) called Omega network. Probability of Acceptance (PA) of a message is considered as a measure of the performance. For a high rate of internal requests, it is shown that an Omega network performs close to a crossbar while reducing the the cost of interconnection to a large extent.