bluuebunny/crossref_metadata_2025 huggingface dataset:
Double Gate 180V-128mA/mm SiC-MESFET for Power Switch Applications
Authors: Tournier Dominique , Vellvehi Miquel , Godignon Philippe , Jordá Xavier , Millan José
Published: March 2009

The potential of SiC MESFETs has been demonstrated for high frequency
applications on several circuits in the 1-5 GHz frequency range. Although MESFET structures
are conventionally used for RF applications, in this paper we report a low voltage (180V)
power switch and its current limiting application based on a double gate MESFET structure,
showing enhanced forward and blocking capabilities. The reported devices utilize a thin
highly doped p-type layer implanted at high energy as buffer layer. Various layouts have been
fabricated, varying the gate length; with either a single gate (p-buried layer connected to
source) or double gate (one Schottky, and the second on the P-buried layer). Gate RESURF
field-plate variation has been also included at the gate electrode. The I(V) electrical
characterization validates the double gate configuration benefits. This double gate structure
shows a higher gate transconductance than the single gate one. High voltage measurements in
conducting mode (180V, 160mA/mm, 30W/mm) confirm the operation of the MESFET as a
current limiting device, with excellent gate control capabilities at temperature up to 190°C.
4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal
Authors: Fedison Jeffery B. , Cowen Chris S. , Garrett Jerome L. , Downey E.T. , Kretchmer James W. , Klinger R.L. , Peters H.C. , Tucker Jesse B. , Matocha Kevin , Rowland L.B. , Arthur Steve
Published: March 2009

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell
regions are reported. The implanted regions are activated by way of a high temperature anneal
(1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force
microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs
when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal
process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking
voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel
mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature
increases (2.8 cm2/V×s at 200°C).
Fabrication and Performance of 1.2 kV, 12.9 mΩcm2 4H-SiC Epilayer Channel MOSFET
Authors: Tarui Yoichiro , Watanabe Tomokatsu , Fujihira Keiko , Miura Naruhisa , Nakao Yukiyasu , Imaizumi Masayuki , Sumitani Hiroaki , Takami Tetsuya , Ozeki Tatsuo , Oomori Tatsuo
Published: March 2009

4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer
channel which improves the surface where the MOS channel is formed. By the optimization of the
epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 mcm2 is obtained at
VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is
obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage
increase slightly with an increase in temperature. This behavior is favorable for high power
operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of
the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length
and it corresponds to an effective channel mobility of about 20 cm2/Vs.
Measurements of Breakdown Field and Forward Current Stability in 3C-SiC pn Junction Diodes Grown on Step-Free 4H-SiC
Authors: Neudeck Philip G. , Spry David J. , Trunek Andrew J.
Published: March 2009

This paper reports on initial fabrication and electrical characterization of 3C-SiC p+n
junction diodes grown on step-free 4H-SiC mesas. Diodes with n-blocking-layer doping ranging
from ~ 2 x 1016 cm-3 to ~ 5 x 1017 cm-3 were fabricated and tested. No optimization of junction edge
termination or ohmic contacts was employed. Room temperature reverse characteristics of the best
devices show excellent low-leakage behavior, below previous 3C-SiC devices produced by other
growth techniques, until the onset of a sharp breakdown knee. The resulting estimated breakdown
field of 3C-SiC is at least twice the breakdown field of silicon, but is only around half the
breakdown field of <0001> 4H-SiC for the doping range studied. Initial high current stressing of 3C
diodes at 100 A/cm2 for more than 20 hours resulted in less than 50 mV change in ~ 3 V forward
voltage.
About the Nature of Recombination Current in 4H-SiC pn Structures
Authors: Strel'chuk Anatoly M. , Mashichev A.V. , Lebedev Alexander A. , Volkova A.N. , Zekentes Konstantinos
Published: March 2009

The forward current was investigated in 4H-SiC p+n structures grown by sublimation
epitaxy. The doping level, Nd-Na, of the n-layer was about (3-4)x1016 cm-3 and the diode area was in
the range from 1x10-5 to 2x10-4 cm2. The observed current can be considered as current due to bulk
recombination in the space charge region of the pn junction via deep level center or due to surface
recombination. The criterion which was performed in this study to differentiate such currents was
the investigation of recombination current versus perimeter/area ratio dependence. It was found that
no pronounced difference in the recombination current parameters for diodes with different
perimeter/area ratio was observed, i.e. current due to surface recombination was not observed for
the 4H-SiC pn structures investigated.
Influence of Basal Plane Dislocation Induced Stacking Faults on the Current Gain in SiC BJTs
Authors: Agarwal Anant K. , Krishnaswami Sumi , Richmond Jim , Capell Craig , Ryu Sei Hyung , Palmour John W. , Geil Bruce , Katsis Dimos , Scozzie Charles , Stahlbush Robert E.
Published: March 2009

SiC BJTs show instability in the I-V characteristics after as little as 15 minutes of
operation. The current gain reduces, the on-resistance in saturation increases, and the slope of the
output characteristics in the active region increases. This degradation in the I-V characteristics
continues with many hours of operation. It is speculated that this phenomenon is caused by the
growth of stacking faults from certain basal plane dislocations within the base layer of the SiC BJT.
Stacking fault growth within the base layer is observed by light emission imaging. The energy for
this expansion of the stacking fault comes from the electron-hole recombination in the forward
biased base-emitter junction. This results in reduction of the effective minority carrier lifetime,
increasing the electron-hole recombination in the base in the immediate vicinity of the stacking
fault, leading to a reduction in the current gain. It should be noted that this explanation is only a
suggestion with no conclusive proof at this stage.
Performance Assessment of 4H-SiC Bipolar Junction Transistors and Insulated Gate Bipolar Transistors
Authors: Balachandran S. , Chow T. Paul , Agarwal Anant K.
Published: March 2009

The performance prospects for 4H-SiC Bipolar Junction Transistors (BJTs) and Insulated
Gate Bipolar Transistors (IGBTs) are theoretically evaluated. The total power dissipated (Ptotal) for
both devices is calculated as a function of lifetime in the drift region and blocking voltage and used
as a figure of merit to compare and contrast the effectiveness of different semiconductor materials
for bipolar device applications. Assuming a maximum of 300W/cm2 for the total permissible power
dissipation due to heat sink constraints we estimate an upper limit of 5kV for SiC BJT operation.
400 Watt Boost Converter Utilizing Silicon Carbide Power Devices and Operating at 200°C Baseplate Temperature
Authors: Richmond Jim , Ryu Sei Hyung , Krishnaswami Sumi , Agarwal Anant K. , Palmour John W. , Geil Bruce , Katsis Dimos , Scozzie Charles
Published: March 2009

This paper reports on a 400 watt boost converter using a SiC BJT and a SiC MOSFET as
the switch and a 6 Amp and a 50 Amp SiC Schottky diode as the output rectifier. The converter was
operated at 100 kHz with an input voltage of 200 volts DC and an output voltage of 400 volts DC.
The efficiency was tested with an output loaded from 50 watts to 400 watts at baseplate
temperatures of 25°C, 100°C, 150°C and 200°C. The results show the converter in all cases capable
of operating at temperatures beyond the range possible with silicon power devices. While the
converter efficiency was excellent in all cases, the SiC MOSFET and 6 Amp Schottky diode had
the highest efficiency. Since the losses in a boost converter are dominated by the switching losses
and the switching losses of the SiC devices are unaffected by temperature, the efficiency of the
converter was effectively unchanged as a function of temperature.
Reduction of Defects in GaN Epitaxial Films Grown Heteroepitaxially on SiC
Authors: Eddy Charles R. , Bassim N.D. , Mastro Michael E. , Henry R.L. , Twigg Mark E. , Holm Ronald T. , Culbertson James C. , Neudeck Philip G. , Powell J. Anthony , Trunek Andrew J.
Published: March 2009

Silicon carbide (SiC) has become the substrate of choice for III-N epilayers applied to
electronic devices due to the lack of a native III-N substrate. This is particularly true for high
power applications, since the thermal conductivity of the substrate enhances device performance.
Although the GaN lattice match is slightly better for SiC than for sapphire, the dislocation densities
that result are still very high (generally in the high 108 cm-2 range) and often deleterious to device
performance. Screw-component dislocations are especially critical since they serve as leakage
paths in vertically conducting III-N devices.
In this paper efforts to reduce the extended defect density in III-N films grown on SiC will be
reviewed. Details on recent efforts to use step-free SiC mesa surfaces arrayed on commercial 4HSiC
substrates will then be highlighted showing dramatic reductions in extended defect densities
and the virtual elimination of critical defects for vertically conducting devices. In these
experiments, SiC surfaces that are homoepitaxially grown step-free or of very low step density have
been used as growth templates for thin (<3 μm) GaN films deposited on a novel 1000 Å AlN
nucleation layer characterized by a total dislocation density two orders of magnitude lower than the
previous state-of-the-art, and with no evidence of screw-component dislocations.
Electron Microscopy Investigation of the Role of Surface Steps in the Generation of Dislocations during MOCVD Growth of GaN on 4H-SiC
Authors: Bassim N.D. , Twigg Mark E. , Mastro Michael E. , Neudeck Philip G. , Eddy Charles R. , Henry R.L. , Holm R.N. , Powell J. Anthony , Trunek Andrew J.
Published: March 2009

Through the use of specially-prepared on-axis SiC substrates with patterned mesa tops
completely free of atomic-scale surface steps, we have previously reported the growth of highquality
GaN heteroepitaxial films with greatly reduced threading dislocation densities on the order
of 107/cm2. In these films, we reported a defect substructure in which lateral a-type dislocations are
present in the nucleation layer but do not bow into threading dislocations during the subsequent
GaN growth. This study focuses further on the role of SiC substrate surface steps in the generation
of misfit, a-type, and threading dislocations at the heteroepitaxial interface. By using weak-beam
imaging (both to eliminate Moiré effects and to observe narrow dislocation images) from plan-view
transmission electron microscopy (TEM), we identify dislocations generated on stepped and
unstepped mesas and compare their geometries. We observe that misfit dislocations nucleated on an
unstepped SiC mesa are confined to one set of a-type Burgers vectors of the form g=1/3 [2110]
_ _
,
straight and well-ordered so that they are less likely to interact with each other. On the other hand,
misfit dislocation structures on a stepped SiC mesa surface are not nearly as well-ordered, having
bowed structure with threading dislocations that appear to nucleate at SiC surface steps.
Strain Relaxation in GaN/AlN Films Grown on Vicinal and On-Axis SiC Substrates
Authors: Bai J. , Huang X. , Raghothamachar Balaji , Dudley Michael , Wagner B. , Davis Robert F. , Wu L. , Zhu Yi Mei
Published: March 2009

Strain relaxation in the GaN/AlN/6H-SiC epitaxial system grown by vicinal surface
epitaxy (VSE) is investigated and compared with that in on-axis epitaxy. High resolution x-ray
diffraction (HRXRD) measurements show that GaN films grown by VSE have improved crystalline
quality. High resolution transmission electron microscope (HRTEM) studies reveal that there are
two types of misfit dislocations (MDs) at AlN/6H-SiC interfaces: 60˚ complete dislocations along
<1120 > directions with Burgers vector 1/3<1120 > and 60˚ Shockley partials along <10 10 >
directions with Burgers vector 1/3<10 10 >. The latter are usually geometrical partial misfit
dislocations (GPMDs) that are dominant in VSE to accommodate the lattice mismatch and stacking
sequence mismatch simultaneously. In VSE, it is the high-density GPMDs formed at the vicinal
surface steps that facilitate rapid strain relaxation at the initial stage of deposition and hence lead to
superior crystalline quality of the subsequently grown GaN films.
4H-SiC Epitaxial Growth on Carbon-Face Substrates with Reduced Surface Roughness
Authors: Aigo Takashi , Sawamura M. , Fujimoto Tatsuo , Katsuno Masakazu , Yashiro Hirokatsu , Tsuge Hiroshi , Nakabayashi Masashi , Hoshino Taizo , Ohtani Noboru
Published: March 2009

4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a
low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared
by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl
etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates
made it possible to decrease the substrate temperature and specular surface morphologies were
realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of
1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were
obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of
1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at
1500°C and it was verified that a high quality metal-semiconductor interface was formed on the
epitaxial layer.
Quantitative Mobility Spectrum Analysis of AlGaN/GaN Heterostructures Using Variable-Field Hall Measurements
Authors: Biyikli N. , Litton Cole W. , Xie J. , Moon Y.T. , Yun F. , Stefanita C.G. , Bandyopadhyay S. , Meyer J.R. , Morkoç Hadis
Published: March 2009

Carrier transport properties of AlGaN/GaN heterostructures have been analyzed with the
quantitative mobility spectrum analysis (QMSA) technique. The nominally-undoped
Al0.15Ga0.85N/GaN sample was grown by metal-organic vapor phase epitaxy. Variable-magneticfield
Hall measurements were carried out in the temperature range of 4-160 K and magnetic field
range of 0-6.6 T. QMSA was applied to the experimental variable-field data to extract the
concentrations and mobilities associated with the high-mobility 2DEG and the relatively lowmobility
bulk electrons for the temperature range investigated. For temperatures below 100 K the
calculated mobility and carrier density values were close to the experimental results. No bulk
conduction was observed in this temperature range. At 160 K, QMSA results show that parallel
conduction in 3 mm thick GaN layer started to affect the average electron mobility.
Direct Electrical Characteristics of GaN Nanowire Field Effect Transistor (FET) without Assistance of E-Beam Lithography (EBL)
Authors: Lee Sang Kwon , Seong Han Kyu , Choi Ki Chul , Cho Nam Kyu , Choi Heon Jin , Suh Eun Kyung , Nahm Kee Suk
Published: March 2009

We report on simple techniques for extracting the electrical properties of 1-dimensional
semiconductor nanowires using standard ultraviolet (UV) photo-lithography instead of e-beam
lithography (EBL), which is a commonly used technique for the fabrication of nanoscale electrical
devices. For electrical transport measurement the gallium nitride nanowires (GaN NWs) were
prepared by a horizontal hot-wall chemical vapor deposition (CVD) with metallic Ga and NH3 gas for
Ga and N sources, and GaN nanowire field effect transistor (FET) structures on a 8×8 mm2 silicon
wafer were fabricated by ordinary 2-mask photo-lithography processes. The estimated carrier
mobility from the gate-modulation characteristics is on the order of 60 ∼ 70 cm2/V⋅s. We found that
our approach is a powerful and simple technique to extract the electrical properties of semiconductor
nanowires. The material characteristics of GaN nanowires are also discussed.
First Principles Modelling of Scroll-to-Nanotube Defect: Screw-Type Dislocation
Authors: Suarez-Martinez I. , Savini G. , Heggie M.I.
Published: March 2009

Carbon nanotubes present interesting potential applications especially in nanoelectronics.
Their electrical properties are known to be a function of their chirality. It happens that 1/3 of CNs
are metallic and 2/3 are semiconductors. Narrow nanotubes are expected to be wide-band gap
semiconductors. Several experimental results have shown that the thickness of a multi-wall
nanotube along the axis can change, while the interlayer spacing remains fairly constant. These
observations suggest the coexistence in the same tube of a scroll structure and a multi-wall nested
tube. We explain this defect as a screw dislocation which by gliding transforms between these two
forms. In this paper, we present a density functional theory study of the structure and energetics of
screw dislocations in AA and ABC graphite, and we discuss their role in the scroll-to-nanotube
transformation in multi-wall nanotubes.
Investigation of the Mechanism and Growth Kinetics of Homoepitaxial 4H-SiC Growth Using CH3Cl Carbon Precursor
Authors: Lin Huang De , Wyatt Jeffery L. , Koshka Yaroslav
Published: March 2009

In this work, the mechanism of the epitaxial growth of 4H SiC using CH3Cl as the carbon
source gas was investigated. The experiments were conducted with a H2 carrier gas flow rate
reduced in comparison to the standard conditions used for device-quality, full-wafer C3H8 growth.
Low-H2 conditions have been found favorable for investigating the differences between the two gas
systems. A non-linear trend of the growth rate dependence on CH3Cl flow was observed. This
dependence was quantitatively different for C3H8 growth, which serves as an indication of different
kinetics of CH3Cl and C3H8 precursor decomposition, as well as differences in Si droplet formation
and dissociation. The maximum growth rate that we were able to achieve was by a factor of two
higher for the CH3Cl precursor than for the C3H8 precursor at the same temperature and flow
conditions. The growth on lower off-axis angle substrates produced surface morphology degradation
similar for both CH3Cl and C3H8 precursor systems.
Homoepitaxial Growth and Characterization of 4H-SiC Epilayers by Low-Pressure Hot-Wall Chemical Vapor Deposition
Authors: Sun Guo Sheng , Ning Jin , Gong Quan Cheng , Gao Xin , Wang Lei , Liu Xing Fang , Zeng Yi Ping , Li Jin Min
Published: March 2009

Horizontal air-cooled low-pressure hot-wall CVD (LP-HWCVD) system is developed to
get high quality 4H-SiC epilayers. Homoepitaxial growth of 4H-SiC on off-oriented Si-face (0001)
4H-SiC substrates purchased from Cree is performed at a typical temperature of 1500°C with a
pressure of 40 Torr by using SiH4+C2H4+H2 gas system. The surface morphologies and structural
and optical properties of 4H-SiC epilayers are characterized with Nomarski optical microscope,
atomic force microscopy (AFM), x-ray diffraction, Raman scattering, and low temperature
photoluminescence (LTPL). The background doping of 32 μm-thick sample has been reduced to
2-5×1015 cm-3. The FWHM of the rocking curve is 9-16 arcsec. Intentional N-doped and B-doped
4H-SiC epilayers are obtained by in-situ doping of NH3 and B2H6, respectively. Schottky barrier
diodes with reverse blocking voltage of over 1000 V are achieved preliminarily.
Optimisation of Epitaxial Layer Growth by Schottky Diodes Electrical Characterization
Authors: La Via Francesco , Galvagno G. , Firrincieli A. , Roccaforte Fabrizio , Di Franco Salvatore , Ruggiero Alfonso , Calcagno Lucia , Foti Gaetano , Mauceri Marco , Leone Stefano , Pistone Giuseppe , Abbondanza Giuseppe , Portuese F. , Abagnale Giovanni , Valente Gian Luca , Crippa Danilo
Published: March 2009

The influence of the epitaxial layer growth parameters on the electrical characteristics of
Schottky diodes has been studied in detail. Several diodes were manufactured on different epitaxial
layers grown with different Si/H2 ratio and hence with different growth rates. From the electrical
characterization a maximum silicon dilution ratio can be fixed at 0.04 %. This limit fixes also a
maximum growth rate that can be obtained in the epitaxial growth, with this process, at about 8
μm/h. Several epitaxial layers have been grown, using this dilution ratio, with different
temperatures (1550÷1650 °C). At 1600 °C the best compromise between the direct and the reverse
characteristics has been found. With this process the yield decreases from 90% for a Schottky diode
area of 0.25 mm2 to 61% for the 2 mm2 diodes. Optimizing the deposition process to reduce the
defects introduced by the epitaxial process, yield of the order of 80% can be reached on 1 mm2
diodes.
Growth of Low Basal Plane Dislocation Density SiC Epitaxial Layers
Authors: Zhang Ze Hong , Sudarshan Tangali S.
Published: March 2009

A method was developed in our laboratory to grow low basal plane dislocation (BPD)
density and BPD-free SiC epilayers. The key approach is to subject the SiC substrates to defect
preferential etching, followed by conventional epitaxial growth. It was found that the creation of BPD
etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations
(TEDs) during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained. The
reason why BPD etch pits can promote the above conversion is discussed. The SiC epilayer growth by
this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.
Epitaxial Growth of 4H-SiC (0001) by Sublimation Method Using Horizontal Furnace
Authors: Park Chi Kwon , An Joon Ho , Lee Won Jae , Shin Byoung Chul , Nishino Shigehiro
Published: March 2009

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was
adopted to produce thick SiC epitaxial layers for power device applications. We aimed to
systematically investigate the dependence of SiC epilayer quality and growth rate during the
sublimation growth using the CST method on various process parameters such as the growth
temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth
rate (30 μm/h) exhibited a low etch pit density (EPD) of ~2000 /cm2 and a low micropipe density
(MPD) of 2 /cm2. The etched surface of a SiC epitaxial layer grown with a high growth rate (above
100 μm/h) contained a high EPD of ~3500 /cm2 and a high MPD of ~500 /cm2, which indicates that
high growth rate aids the formation of dislocations and micropipes in the epitaxial layer.
Structures of Comets in a Homoepitaxially Grown 4H-SiC Film Studied by DUV Micro-Raman Spectroscopy
Authors: Tomita Takuro , Matsuo Shigeki , Okada Tatsuya , Kimoto Tsunenobu , Mitani Takeshi , Nakashima Shinichi
Published: March 2009

Deep-ultraviolet (DUV) micro-Raman spectroscopy was applied to study the micro
structures of surface defects in a 4H-SiC homoepitaxially grown film. From DUV Raman spectrum,
inclusions of 3C-SiC was found in comet defects. The shape of 3C-structure in comets was
investigated and it was found that 3C inclusions in comets can be classified into two types. In addition,
spectrum broadening due to the coupling of nonfolded longitudinal optical phonon mode and the
photo-excited carriers was also found. The formation mechanisms of 3C inclusion in comets were
discussed.
Observation of Shrinking and Reformation of Shockley Stacking Faults by PL Mapping
Authors: Miyanagi Toshiyuki , Tsuchida Hidekazu , Kamata Isaho , Nakamura Tomonori , Ishii R. , Nakayama Koji , Sugawara Yoshitaka
Published: March 2009

We provide evidence of shrinking of Shockley-type stacking faults (SSFs) in the SiC
epitaxial layer by high temperature annealing. Photoluminescence (PL) mapping in combination with
high-power laser irradiation makes it possible to investigate the formation of SSFs, which lie between
a pair of partial dislocations formed by dissociation of a basal plane dislocation (BPD), without
fabrication of pin diodes. Using this technique, we investigated the annealing effect on SSFs.
Comparing before and after annealing at 600°C for 10 min, it became obvious that high-temperature
annealing results in shrinking of the faulted area of the SSFs. The SSFs form into the same features as
those before annealing when high-power laser irradiation is performed again on the same area. This
result shows that the faulted area of SSFs shrinks by 600°C annealing but the nuclei of SSFs (BPDs)
do not disappear.
Investigation of Mechanical Stress-Induced Double Stacking Faults in (11-20) Highly N-Doped 4H-SiC Combining Optical Microscopy, TEM, Contrast Simulation and Dislocation Core Reconstruction
Authors: Lancin Maryse , Regula G. , Douin Joël , Idrissi Hosni , Ottaviani Laurent , Pichaud Bernard
Published: March 2009

Defects are introduced into (11-20) highly N-doped 4H-SiC by one surface scratch
followed by annealing at 550°C or 700°C with or without an additional compressive stress.
The defects are planar and always consist of double stacking faults dragged by a pair of
partial dislocations. In a pair, the partial dislocations have the same line direction, Burgers
vector and core composition. All the identified gliding dislocations have a silicon core. An
analysis of their expansion during annealing proves that C(g) partial segments can be created
but that C(g) partial dislocations are immobile.
Overlapping Shockley/Frank Faults in 4H-SiC PiN Diodes
Authors: Twigg Mark E. , Stahlbush Robert E. , Losee Peter A. , Li Can Hua , Bhat I. , Chow T. Paul
Published: March 2009

Using light emission imaging (LEI), we have determined that not all planar defects in
4H-SiC PiN diodes expand in response to bias. Accordingly, plan-view transmission electron
microscopy (TEM) observations of these diodes indicate that these static planar defects are different
in structure from the mobile stacking faults (SFs) that have been previously observed in 4H-SiC
PiN diodes. Bright and dark field TEM observations reveal that such planar defects are bounded by
partial dislocations, and that the SFs associated with these partials display both Frank and Shockley
character. That is, the Burgers vector of such partial dislocations is 1/12<4-403>. For sessile Frank
partial dislocations, glide is severely constrained by the need to inject either atoms or vacancies into
the expanding faulted layer. Furthermore, these overlapping SFs are seen to be fundamentally
different from other planar defects found in 4H-SiC.
Growth of Micropipe-Free Single Crystal Silicon Carbide (SiC) Ingots Via Physical Vapor Transport (PVT)
Authors: Basceri C. , Khlebnikov I. , Khlebnikov Y. , Muzykov P. , Sharma M. , Stratiy G. , Silan M. , Balkas Cengiz M.
Published: March 2009

The move towards commercialization of SiC based devices places increasing demands on the
quality of the substrate material. While the industry has steadily decreased the micropipe (MP) levels in
commercial SiC substrates over the past years, the achievement of wafers that are entirely free of MPs
marks an important milestone in commercialization of SiC based devices. We present the results of a
study for controlling the nucleation and propagation of MP defects in SiC ingots grown via PVT. Our
studies confirm that during bulk growth of SiC, foreign polytype nucleation such as 3C-polytype occurs
at the initial stages of growth (nucleation period) and/or during subsequent growth in the presence of
facets. Results in this investigation suggest that polytype instability during crystal growth adversely
impacts the MP density. Based on this key concept, growth conditions for nucleation and growth stages
were optimized. These conditions were subsequently implemented in an innovative PVT growth
environment to achieve a growth technique with highly effective polytype control. Under continuously
modulated growth conditions, MPs induced by seed material and/or formed during the growth were
eliminated. 2-inch and 3-inch diameter MP-free (zero MP density) conducting 4H-SiC ingots were
obtained.
Development of Non-Destructive In-House Observation Techniques for Dislocations and Stacking Faults in SiC Epilayers
Authors: Kamata Isaho , Tsuchida Hidekazu , Miyanagi Toshiyuki , Nakamura Tomonori
Published: March 2009

We have developed non-destructive in-house observation techniques for dislocations and
stacking faults (SFs) in 4H-SiC epilayers. Low temperature photoluminescence (PL) mapping was
carried out at 100K using He-Cd laser (325 nm) as an exciation source. PL mapping at ~420 nm was
used to investigate basal plane dislocations (BPDs), Shockley stacking faults (SSFs) and boundary,
while PL mapping at ~470 nm and 100K obtained in-grown SF images. In addition, using a
high-resolution laboratory X-ray topography system with a four-crystal collimator, we succeeded in
recording BPDs propagating along [11-20]. From the measurement results, new evaluation
techniques for dislocations and SFs other than KOH etching and Synchotron radiation topography
were demonstrated on Si- and C-face 4H-SiC epilayers.
Identification of Polytypes in Sublimation Grown 4H-SiC Crystals by High Resolution X-Ray Diffractometry
Authors: Dong Jie , Wang Li , Hu Xiao Bo , Li Xian Xiang , Li Juan , Jiang Shou Zhen , Chen Xiu Fang , Xu Xian Gang , Jiang Min Hua
Published: March 2009

4H-SiC single crystal with a diameter of 1.5’’ has been grown by the seed sublimation
method. Regions of mixed polytypes are assessed by high resolution X-ray diffractometry with the
asymmetrical diffraction geometry. Multiple reflections are observed from the rocking curve
measurements of a longitudinal cut 4H-SiC slice. Those reflections are indexed to be 2131 and
2131 of 4H-SiC, 2130 , 2131 , 2131 , 2132 and 2132 of 6H-SiC, 2131 , 2132 , 2134 , 2135 and
2137 of 15R-SiC respectively based on the lattice constants of different polytypes in SiC crystal. It
is believed that the polytypes can be identified by high resolution X-ray diffractometry.
Optical Studies of Deep Centers in Semi-Insulating SiC
Authors: Magnusson Björn , Aavikko Reino , Saarinen Kimmo , Son Nguyen Tien , Janzén Erik
Published: March 2009

Semi-insulating SiC grown by the HTCVD technique are studied by luminescence and
absorption measurements and the results are compared to PAS and SIMS results. We have found
that metal impurities are present but only in very small concentrations. The semi-insulating
properties are instead determined by the intrinsic defects, mostly the silicon vacancy in hydrocarbon
rich grown material and the carbon vacancy in the hydrocarbon poor grown material. The
hydrocarbon poor material is stable upon annealing both from a vacancy concentration point of view
and from a resistivity point of view. The hydrocarbon rich grown material does not stand the
annealing at 1600 °C and the resistivity is decreased; from the absorption and PAS measurements
we have observed that the decrease in silicon vacancy concentration fits the growth of the vacancy
clusters.
Investigation of the Electronic Structure of the UD-4 Defect in 4H-SiC by Optical Techniques
Authors: Thuaire Aurelie , Henry Anne , Magnusson Björn , Bergman Peder , Chen W.M. , Janzén Erik , Mermoux Michel , Bano Edwige
Published: March 2009

A detailed investigation of the optical and electronic properties of the deep-level defect
UD-4 is reported. This defect has recently been observed in 4H semi-insulating silicon carbide, but
has hardly been studied yet. Both low temperature and temperature-dependent photoluminescence
were collected from the defect. Zeeman spectroscopy measurements were performed as well as
time-resolved photoluminescence.
Investigation of the Displacement Threshold of Si in 4H SiC
Authors: Sullivan W. , Steeds John W.
Published: March 2009

Samples of 4H SiC, both n- and p-doped, have been irradiated with low-energy electrons
in a transmission electron microscope. The dependence of the silicon vacancy-related V1 ZPL
doublet (~860nm) on electron energy and electron dose has been investigated by low temperature
photoluminescence spectroscopy. Furthermore, this luminescence centre has been studied across a
broad range of samples of various doping levels. Some annealing characteristics of this centre are
reported.
Long Distance Point Defect Migration in Irradiated SiC Observed by Deep Level Transient Spectroscopy
Authors: Alfieri Giovanni , Grossner Ulrike , Monakhov Edouard V. , Svensson Bengt Gunnar , Steeds John W. , Sullivan W.
Published: March 2009

The migration of carbon interstitials in n-type 4H-SiC has been revealed with optical and
electrical measurements. Furthermore, clear evidence is found that carbon interstitials are involved
in the formation of the Z- and S-centers detected by DLTS within the electronic band gap of n-type
4H-SiC.
Deep Traps and Charge Carrier Lifetimes in 4H-SiC Epilayers
Authors: Huh Sung Wook , Sumakeris Joseph J. , Polyakov A.Y. , Skowronski Marek , Klein Paul B. , Shanabrook B.V. , O'Loughlin Michael  J.
Published: March 2009

Carrier lifetimes and the dominant electron and hole traps were investigated in a set of
thick (9-104mm) undoped 4H-SiC epitaxial layers grown by CVD homoepitaxy. Deep trap spectra
were measured by deep level transient spectroscopy (DLTS) with electrical or optical injection,
while lifetimes were measured by room temperature time-resolved photoluminescence (PL). The
main electron traps detected in all samples were due to Ti, Z1/Z2 centers, and EH6/EH7 centers. Two
boron-related hole traps were observed with activation energies of 0.3 eV (boron acceptors) and 0.6
eV (boron-related D centers). The concentration of electron traps decreased with increasing layer
thickness and increased toward the edge of the wafers. PL lifetimes were in the 400 ns-1800 ns
range with varying injection and generally correlated with changes in the density of Z1/Z2 and to a
lesser extent the EH6/EH7 electron traps. However, the results of DLTS measurements on p-i-n
diode structures suggest that the capture of injected holes is much more efficient for the Z1/Z2 traps
compared to the EH6/EH7 centers making the Z1/Z2 more probable candidates for the role of
lifetime killers. A good fit of the thickness dependence of the measured lifetimes to the usual
analytical form was obtained assuming that Z1/Z2 is the dominant hole recombination center and
that the surface recombination velocity was 2500 cm/sec.
Deep Traps in High-Purity Semi-Insulating 6H-SiC Substrates: Thermally Stimulated Current Spectroscopy
Authors: Fang Z.Q. , Claflin B. , Look David C. , Polenta L. , Chen J. , Anderson Thomas , Mitchel W.C.
Published: March 2009

Thermally stimulated current spectroscopy (TSC) has been applied to characterize deep
traps in high-purity semi-insulating 6H-SiC substrates. By using above bandgap to sub-bandgap
light for illumination at 83 K and different applied biases, at least nine TSC traps in the temperature
range of 80 to 400 K can be consistently observed. It is found that TSC peaks for T < 130 K are
significantly affected by light and some peaks are strongly enhanced by the applied bias. Measured
trap activation energies range from 0.15 eV to 0.76 eV. Theoretical fittings of selected traps give
more accurate trap parameters. Based on literature results connected with deep traps in conductive
6H-SiC, the origin of these TSC traps is discussed.
Electron Paramagnetic Resonance Study of the HEI4/SI5 Center in 4H-SiC
Authors: Umeda T. , Son Nguyen Tien , Isoya Junichi , Morishita Norio , Ohshima Takeshi , Itoh Hisayoshi , Janzén Erik
Published: March 2009

We present new electron-paramagnetic-resonance (EPR) data on the HEI4/SI5 center in
4H-SiC. So far, the SI5 (SI-5) center has been observed only in as-grown SiC substrates; however, we
found that it can be created by electron irradiation to commercial n-type 4H-SiC. The artificially
created SI5 center, which we had preliminary called HEI4, was found to be identical with the SI5
center in as-grown SiC. A high-intensity HEI4/SI5 spectrum of irradiated SiC revealed clear
hyperfine structures of 29Si and 13C, which enabled us to identify the origin of this center as a carbon
antisite-vacancy pair in the negative charge state (CSi-VC
–). We assessed its electronic levels using
photo-EPR.
A Theoretical Study on Doping of Phosphorus in Chemical Vapor Deposited SiC Layers
Authors: Hornos T. , Gali Adam , Devaty Robert P. , Choyke Wolfgang J.
Published: March 2009

Ab initio supercell calculations have been carried out to investigate the doping of
phosphorus in chemical vapor deposited (CVD) SiC layers. CVD conditions have been simulated
by using the appropriate chemical potentials for hydrogen and phosphorus (P). We found that
the most abundant defect is P at Si-site followed by P at C-site. The calculated concentrations
of the P-donors and free carriers in CVD grown SiC agree with the experimental results.
In Situ Observation of Mass Transfer in the CF-PVT Growth Process by X-Ray Imaging
Authors: Chaussende Didier , Wellmann Peter J. , Ucar M. , Pons Michel , Madar Roland
Published: March 2009

The development of the Continuous Feed Physical Vapour Transport (CF-PVT) process
requires a perfect control of each phenomenon in the growth cell. Along this line, the present paper
gives some inputs on the CF-PVT mass transfer regimes with respect to the process parameters,
both from qualitative and quantitative viewpoints. For example, two boundary cases have been
evidenced depending on the temperature. At low temperature, the growth is limited by the
sublimation step between the source and the seed. In this case, the CF-PVT process can be roughly
assimilated to the classical seeded sublimation technique. At high temperature, the process is
limited by the feeding step, i.e. the CVD deposition and infiltration on the lower part of the source.
Measurements are correlated to in-situ X-ray imaging. The ability of the X-ray imaging to in-situ
qualify and quantify the mass transfer is discussed.
Results of SIMS, LTPL and Temperature-Dependent Hall Effect Measurements Performed on Al-Doped α-SiC Substrates Grown by the M-PVT Method
Authors: Contreras Sylvie , Zielinski Marcin , Konczewicz Leszek , Blanc Caroline , Juillaguet Sandrine , Müller Ralf , Künecke Ulrike , Wellmann Peter J. , Camassel Jean
Published: March 2009

We report on investigation of p-type doped, SiC wafers grown by the Modified- Physical
Vapor Transport (M-PVT) method. SIMS measurements give Al concentrations in the range 1018 to
1020 cm-3, with weak Ti concentration but large N compensation. To measure the wafers’ resistivity,
carrier concentration and mobility, temperature-dependant Hall effect measurements have been
made in the range 100-850 K using the Van der Pauw method. The temperature dependence of the
mobility suggests higher Al concentration, and higher compensation, than estimated from SIMS.
Additional LTPL measurements show no evidence of additional impurities in the range of
investigation, but suggest that the additional compensation may come from an increased
concentration of non-radiative centers.
Luminescence and EPR Characterization of Vanadium Doped Semi-Insulating 4H SiC
Authors: Kalabukhova Ekaterina N. , Savchenko D.V. , Greulich-Weber Siegmund , Bulanyi M.F. , Omelchenko S.A. , Khmelenko O.V. , Gorban A.A. , Mokhov E.N.
Published: March 2009

In this paper, we report on a photoluminescence (PL) and EPR study of several semiinsulating
(SI) 4H SiC samples showing the different compensation regimes due to the presence of
V4+ and V3+of different concentration. The samples which contain only V3+ indicates the
compensation regime NV≅ND-NA>0 with the Fermi level located in the upper half of the band gap.
The presence of V4+ along with V3+ in the other two set of samples indicates the SI behavior of the
samples with compensation regime NV>NA-ND>0. Considering that the samples revealed EPR
spectrum of vanadium V3+, position of the Fermi level should be also in the upper half of the band
gap and mixed conductivity could be expected. UD-3 PL spectrum was observed in vanadium
doped SI 4H SiC presented in the samples in V3+/V4+ and V4+/V5+ charge states with compensation
regime NV>NA-ND>0. The data obtained prove that the PL and EPR are suitable techniques in
determination SI yield in SiC crystal.
Thermal Lens Technique for the Determination of SiC Thermo-Optical Properties
Authors: Anjos V. , Bell M.J.V. , Vasconcelos Elder A. de , Silva Jr. E.F. da , Andrade A.A. , Franco R.W.A. , Castro M.P.P. , Esquef I.A. , Faria Jr. Roberto da Trindade
Published: March 2009

In this paper we combine the use of photo-thermal techniques, Thermal lens (TL)
spectrometry, Photoacoustic and heat capacity measurements to determine the optical path
dependence with temperature (ds/dT) of a polycrystalline 3C-SiC sample. Results obtained for the
polycrystalline sample with the TL technique show that ds/dT is negative at room temperature. This
means that the thermal lens formed in 3C-SiC acts as a divergent lens when light impinges the
sample. Our measurements, demonstrate that photo-thermal techniques can be used to obtain
thermal parameters in circumstances where other techniques cannot be used, for example, in harsh
environments.
Wannier-Stark Ladder and Negative Differential Conductance in 4H-SiC
Authors: Sankin Vladimir Ilich , Yakimova Rositza
Published: March 2009

The work deals with the highly important problem of the qualitative temperature
dependence of avalanche breakdown voltage in p-n junctions based on 4H-SiC. As it has been
shown before, the temperature coefficient of avalanche breakdown voltage (TCABV) is negative in
seven SiC polytypes, including 4Н-SiC. This effect has been explained by the Wannier-Stark
localization (WSL). It is worth noting that the plane of the investigated p-n junctions coincided with
the basal plane (0001). However the current SiC device technology prefers 4H-SiC p-n junction
formation on a plane that has 8о disorientation from (0001). This may result in a weakening of the
WSL and, correspondingly, in a positive TCABV. This problem has been elucidated in the present
paper. The photocurrent of 4H-SiC p-n junctions in a strong electric field has been scrutinized, that
has allowed to discover a negative differential conductivity region and it has testified to the WSL
process and negative TCABV.
Processing of Poly-SiC Substrates with Large Grains for Wafer-Bonding
Authors: Chichignoud Guy , Auvray Laurent , Blanquet Elisabeth , Anikin Mikhail , Pernot Etienne , Bluet Jean Marie , Chaudouët Patrick , Mermoux Michel , Moisson Catherine , Letertre Fabrice , Pons Michel , Madar Roland
Published: March 2009

The transfer by wafer-bonding of single-crystalline SiC thin films to a
polycrystalline SiC support to obtain a “quasi-wafer” is an attractive way for lowering the
cost of silicon carbide wafers. Such a process needs high quality polycrystalline substrates,
with controlled and high-level bulk properties (thermal conductivity, electrical resistivity) and
with very low surface roughness and surface bowing. Currently, polycrystalline SiC wafers
which are available are siliconized SiC or CVD processed SiC wafers. Siliconized ceramic
wafers are very heterogeneous (mixture of 3C, 6H, 15R and silicon), while CVD ones are of
better quality (homogeneous and textured 3C). However neither the siliconized SiC nor the
CVD SiC can be CMP polished with low roughness over large dimension. In this paper,
wafers with large and textured grains (> 1cm) are processed and characterized. The polishing
of such structures is studied and optimized to obtain low surface roughness. To meet these
requirements high temperature processes used for single crystal growth were selected.
Structural investigations performed on the grown ingots showed an important influence of the
used seed since no preferential crystallographic orientation was observed during the growth.
The final polishing quality was of high level but step heights were observed between grains.
Correlation between Room Temperature Photoluminescence and Resistivity in Semiinsulating Silicon Carbide
Authors: Chanda Sashi Kumar , Koshka Yaroslav , Yoganathan Murugesu
Published: March 2009

A room temperature PL mapping technique was applied to establish the origin of
resistivity variation in PVT-grown 6H SiC substrates. A direct correlation between the native
defect-related PL and resistivity was found in undoped (V-free) samples. In vanadium-doped
samples with low vanadium content, the resistivity showed a good correlation with the total PL
signal consisting of contributions from both vanadium and native point defects. Well-known UD1
and UD3 levels were revealed by low-temperature PL spectroscopy. Some correlation was observed
between these low-temperature PL signatures and the resistivity distribution.
Microwave Dielectric Loss Characterization of Silicon Carbide Wafers
Authors: Bogart Timothy , Everson W.J. , Gamble Rick D. , Oslosky Ed , Snyder David , Furman Eugene , Perini Steve , Lanagan M.
Published: March 2009

Semi-insulating silicon carbide (SiC) wafers are important as substrates for high
frequency devices such as AlGaN-GaN HEMT’s. A nondestructive characterization technique has
been developed to measure the dielectric properties of SiC wafers in the GHz frequency range
where the devices will operate in order to validate wafers for high yield working devices. The
dielectric loss is measured at approximately 16 GHz in a split microwave cavity. Initial results
show a correlation where the dielectric loss decreases as the resistivity increases, where the
resistivity was measured using a Contactless Resistivity Mapping system (COREMA). The
uniformity of dielectric loss across SiC wafers was evaluated using a split post dielectric resonator
cavity fixed at 5.5GHz to measure the dielectric loss at five points on a wafer. Dielectric loss as a
function of temperature from room temperature to 400°C was also studied.
Brillouin Spectra of Porous p-Type 6H-SiC
Authors: Andrews G.T. , Young C.K. , Polomska A. , Clouter Maynard J. , Ke Yue , Devaty Robert P. , Choyke Wolfgang J.
Published: March 2009

Brillouin spectra have been recorded for a series of supported films of p-type
porous 6H-SiC with a branched morphology and porosities in the range from 30% to 58%.
Complex spectra comprising up to 7 identifiable components were observed in some cases.
An effective medium model is being developed as an aid in interpreting the spectra, and
preliminary results are presented.
A Simple Method to Synthesize Nano-Sized 3C-SiC Powder Using Hexamethyldisilane in a CVD Reactor
Authors: Gupta Aparna , Jacob Chacko
Published: March 2009

In this paper, we report a novel route to synthesize nano-sized cubic silicon carbide (3CSiC)
powder by a chemical vapor deposition (CVD) technique in a resistance-heated furnace. The
nanoparticles were deposited on the relatively cold region of a hot-wall quartz reactor.
Hexamethyldisilane (HMDS) was used as the source material for both silicon and carbon. The
presence of crystalline 3C-SiC was identified using powder x-ray diffraction (XRD) technique.
From the XRD data, the crystallite size was also estimated to be in the range of nanometers (nm). A
clear evidence of the particle size (~ 10 - 30 nm) was obtained by transmission electron microscopy
(TEM). Selected area electron diffraction (SAED) was carried out on the nanoparticle assembly.
The ring shaped pattern is a clear indication of polycrystalline particle formation. High resolution
TEM (HRTEM) of nanoparticles was performed to study the crystal structure in detail. The
nanoparticles were also characterized by Raman spectroscopy at room temperature. Finally, the
influence of the growth parameters is also reported in the present study.