bluuebunny/crossref_metadata_2025 huggingface dataset:
(Invited) Chemisorption Reaction Mechanisms for Atomic Layer Deposition of High-k Oxides on High Mobility Channels
Authors: Delabie A. , Sioncke Sonja , Van Elshocht S. , Caymax Matty , Pourtois Geoffrey , Pierloot Kristine
Published: October 2010

For next generation CMOS technology nodes, new channel materials, such as Ge and III/V semiconductors, are investigated because of their higher intrinsic carrier mobility as compared to Si. In this work, we have studied the chemisorption reaction mechanisms for Atomic Layer Deposition (ALD) of the high-k dielectric Al2O3 on S-passivated Ge by means of ab initio calculations. The calculations provide insight into the specific interactions occurring during gate stack formation and the character of the bonds at the Ge interface.
Plasma Enhanced Atomic Layer Deposition of SiN:H Using N2 and Silane
Authors: King Sean
Published: October 2010

As the nano-electronics industry looks to transition to both three dimensional transistor and interconnect technologies at the < 22 nm node, highly conformal dielectric coatings with precise thickness control are increasingly being demanded. Plasma Enhanced Chemical Vapor Deposition (PECVD) currently fills this role for most applications requiring low temperature processing, but does not always meet step coverage and thickness precision requirements. We present results for a hybrid technique, Plasma Enhanced Atomic Layer Deposition (PEALD), that utilizes typical PECVD process gases and tooling while delivering improved topography coverage and thickness control. Specifically, we show that alternating SiH4 gas / N2 plasma exposures applied in an atomic layer deposition sequence can be used to deposit SiN films in a self limiting fashion.
(Invited) DC Biased Remote Plasma Atomic Layer Deposition and Its Applications
Authors: Kim Hyungchul , Jeon Hyeongtag
Published: October 2010

To enhance thin film quality by increasing the plasma density and minimizing plasma-induced damage, we introduced a new direct current (DC) biased remote plasma atomic layer deposition (RPALD) method as one of the variants of RPALD. With this new deposition method, HfO2 dielectric films were deposited and characterized to examine the effect of DC-bias on grown films. The plasma properties were investigated by using the optical emission spectroscopy (OES) and floating harmonic method. When DC biased was applied to the RF plasma, the amount of free radicals and ions were increased by the collisions between electrons and metastable atoms or molecules. The electrical properties of high-k materials, such as the effective oxide thickness (EOT) and the breakdown voltage, were improved by the DC biased RPALD when compared to those of RPALD.
(Invited) Large Format Atomic Layer Deposition
Authors: Sundaram Ganesh M. , Bertuch Adam , Bhatia Ritwik , Coutu R. , Dalberth Mark J. , Deguns Eric , Liu Guo , Sowa Mark J. , Becker Jill S.
Published: October 2010

The demonstrated benefits provided by Atomic Layer Deposition (ALD) in producing films of exceptional uniformity, and conformality, has set the stage for its use in large area, and batch processing applications. Two key elements which drive the adoption of ALD for these applications are the ability to scale the film processes from small to large size substrates, and for the effective throughput to be increased in a manner consistent with volume production needs. In this paper we discuss the results of scaling processes from small format substrates to large format substrates, along with a presentation of the parameters which influence throughput. Additionally we describe the basic underpinnings of batch and roll-to-roll ALD systems, and the design factors which must be considered when used in a high volume setting.
(Invited) High Throughput ALD of Al2O3 Layers for Surface Passivation of Silicon Solar Cells
Authors: Kuznetsov Vladimir , Granneman Ernst , Vermont Pascal , Vanormelingen Koen
Published: October 2010

A high-throughput ALD system based on wafer transport in an atmospheric gas bearing was developed. Line-shaped TMA and H2O precursor zones are present in the direction perpendicular to transport takes place. Thin Al2O3 films of 4-24 nm were deposited at wafer speed of 160-230 mm/s (corresponding to a throughput of 2400 - 3600 wph). After annealing and firing the films show good passivation. Effective minority carrier lifetimes measured on 2.3 ohm cm p-type c-Si wafers at excess carrier density of 1E15 cm-3 reach values of 0.3-2.5 ms depending on surface preparation, annealing steps and film thickness. No degradation of films during firing was observed and the lifetime values remain stable in time. The Levitrack system presented in this paper is expected to meet the requirements of the PV industry.
High Throughput ALD Production Systems for Cadmium Free CIGS and Enhanced Efficiency c-Si Solar Cells
Authors: Skarp Jarmo I.
Published: October 2010

Photovoltaic (PV) industry is growing rapidly. It has very demanding requirements for throughput of production equipment. ALD films have shown excellent results for improving the efficiency of both CIGS and c-Si solar cells in research level. We will discuss on the criteria for high throughput ALD system and introduce new high throughput systems for large area substrates and crystalline solar cells.
Surface Immobilizations of AlGaN/GaN High Electron Mobility Transistor Based Sensors
Authors: Chu Byung Hwan , Chang C. Y. , Wang Y. L. , Pearton S. J. , Ren Fan
Published: October 2010

Recent progress in AlGaN/GaN HEMT sensors is reviewed in this paper. These devices can take advantage of the advantages of microelectronics, including high sensitivity, possibility of high-density integration, and mass manufacturability. HEMT sensors show promising results for protein, DNA, prostate cancer, kidney injury molecules, pH values of solutions, mercury ions as well glucose in the exhaled breath condensate. The method relies on an amplification of small changes in antibody-structure due to binding to antigens. The characteristics of these sensors include fast response (liquid phase-5 to 10 seconds and gas phase- milli-second), digital output signal, small device size (less than 100 x 100 μm2) and chemical and thermal stability.
Growth and Characterization of AlN and AlGaN Epitaxial Films on AlN Single Crystal Substrates
Authors: Dalmau Rafael , Moody Baxter , Schlesser Raoul , Mita Seiji , Xie Jinqiao , Feneberg Martin , Neuschl Benjamin , Thonke Klaus , Collazo Ramón , Rice Anthony , Tweedie James , Sitar Zlatko
Published: October 2010

AlN and AlGaN epitaxial films were deposited by metal organic chemical vapor deposition on single crystal AlN substrates processed from AlN boules grown by physical vapor transport. Structural, chemical, and optical characterization demonstrated the high crystalline quality of the films and interfaces.
A Review of Materials Issues and Degradation of III-V Compound Semiconductors and Optical Devices
Authors: Ueda Osamu
Published: October 2010

Materials issues in III-V alloy semiconductors and our current understanding of degradation mechanism in III-V compound semiconductors and optical devices are systematically reviewed. Generation of defects and thermal instability are among these issues for these systems. In each phenomenon, generation mechanism of defects and structure are clarified. Three major degradation modes of optical devices, rapid degradation, gradual degradation, and catastrophic failure are briefly summarized, and the rapid and the gradual degradation modes are discussed in more detail.
High Mobility Compound Semiconductor Permeable Base Transistors with Suppressed Base Current
Authors: Shih Kun-Huan , Chui Chi On
Published: October 2010

Two novel Permeable Base Transistor (PBT) structures for base leakage suppression with lattice-matched In0.53Ga0.47As channel have been proposed. The operations of these novel devices have been analyzed, and their DC and RF performance have been evaluated against the conventional PBT.
"Graphene-Like" Exfoliation of Atomically-Thin Films of Bi2Te3 and Related Materials: Applications in Thermoelectrics and Topological Insulators
Authors: Teweldebrhan Desalegne , Balandin Alexander A.
Published: October 2010

In this paper we overview our results on "graphene-inspired" exfoliation of crystalline bismuth telluride films with a thickness of just a few atoms. The atomically thin films were suspended across trenches in Si/SiO2 substrates, and subjected to detail material characterization. The presence of the van der Waals gaps allowed us to disassemble Bi2Te3 crystal into its quintuple building blocks - five mono-atomic sheets - consisting of Te(1)-Bi-Te(2)-Bi-Te(1). By altering the thickness and sequence of atomic planes we were able to create "designer" quasi-2D crystalline films, change their composition, the type of charge carriers as well as other properties. The exfoliated quintuples and ultra-thin films have low thermal conductivity, relatively high electrical conductivity and enhanced thermoelectric properties. The obtained results pave the way for producing stacks of crystalline bismuth telluride quantum wells with nearly infinite potential barriers, strong spatial confinement of charge carriers and acoustic phonons, beneficial for thermoelectric devices.
Dependence of Thermal Decomposition of Metal Organic Gases on Metal Surface for Gas Distribution System
Authors: Yamashita Satoru , Watanuki Kohei , Ishii Hidekazu , Shiba Yoshinobu , Kitano Masafumi , Shirai Yasuyuki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: October 2010

The performance of semiconductor films is influenced by the purity of the metal-organic (MO) gas that is used, so it is important to investigate the decomposition behavior of MO gases. The decomposition of dimethylzinc, trimethylgallium and trimethylaluminum is found to depend on the metal surface in the reactor tube. A reactor tube with an Al2O3 surface exhibits the highest temperature as which decomposition of the MO gases started, and the highest activation energy. These results indicate that the Al2O3 surface has the lowest catalytic activity for the decomposition of these MO gases. However, decomposition of dimethylzinc occurs at room temperature when it is trapped in a reactor tube. This decomposition ceases past a certain trapped time, so the catalytic activity for the decomposition of MO gases by surfaces stabilizes. Therefore, Al2O3 surfaces are useful for application in MO gas distribution systems.
High-Temperature Dielectric Behavior of Nanocrystalline and Microcrystalline Diamond Thin Films
Authors: Govindaraju Nirmal , Das Dibakar , Kosel Peter , Singh Raj
Published: October 2010

This paper presents high-temperature electrical properties of polycrystalline, microcrystalline and nanocrystalline diamond films synthesized with varying proportions of nitrogen and argon in the gas phase. Resistivity data, activation energies, barrier heights, dielectric constants and quality factors are reported for these films up to 823 K. Results indicate that high N2 (0.5 %) and Ar (85 %) levels in the gas phase degrade the electrical quality of the diamond films. This degradation is attributed to a combined effect of decreasing grain size and higher sp2 carbon content in the films. A gas ratio of 60:39:1 of Ar:H2:CH4 was found to produce improved dielectric quality with resistivities comparable to those of typical microcrystalline diamond films. A proprietary seeding technique which produced a dense diamond nucleation layer is also presented. This research resulted in the development of process conditions for diamond deposition on device substrates that incurred no observable damage to device metallization.
Flip-Chip Packaging of In0.6Ga0.4As MHEMT Device on Low-Cost Organic Substrate for W-Band Applications
Authors: Lim Wee-Chin , Wang Chin-Te , Kuo Chien-I , Hsu Li-Han , Tsai Szu-Ping , Chang Edward Yi
Published: October 2010

A discrete low noise In0.6Ga0.4As MHEMT with 150 nm gate length was flip-chip assembled on the low-cost RO3210 organic substrate for wireless communication applications. The measured DC characteristics were very similar before and after flip-chip assembly. The flip-chip packaged MHEMT showed a high drain current density of 516 mA/mm and a maximum transconductance of 576 mS/mm at a VDS of 0.8 V. The insertion gain of the flip-chip packaged device was decayed less than 2 dB up to 100 GHz as compared to the data of bare die. Moreover, the measured minimum noise figure was less than 2 dB as measured at VDS of 0.7 V and VGS of -0.7 V in the frequency range from 20 to 64 GHz for the device after flip-chip assembly. The excellent performance of the flip-chip packaged MHEMT demonstrates the feasibility of using low cost organic substrate for high frequency applications up to W band.
The Control of Optical and Structural Properties of ZnO:Mg Films Deposited by the Electrochemical Techniques
Authors: Ishizaki Hiroki , Ito Seishiro
Published: October 2010

ZnO films doping magnesium atoms were electrochemically grown on the NESA conductive glass substrate from the magnesium nitrate aqueous solution with zinc sulfate, kept at 323K and the cathodic potential of -0.9V vs. Ag/AgCl. The Mg/(Mg+Zn) atomic ratio of ZnO:Mg films increased with the decrease in the zinc sulfate concentration. For the optical band gap energy of these ZnO:Mg films, the adding zinc sulfate into magnesium nitrate aqueous solution, gave the decrease in these optical band gap energy. Thus, the optical band gap energy of ZnO:Mg films would depend on the zinc sulfate concentration.
Large-Scale Automated Identification and Quality Control of Exfoliated and CVD Graphene via Image Processing Technique
Authors: Nolen Craig M. , Teweldebrhan Desalegne , Denina Giovanni , Bhanu Bir , Balandin Alexander A.
Published: October 2010

Graphene, a monolayer of carbon atoms, is a high-interest material in the research community and semiconductor industry due to its extraordinary electronic, thermal, and mechanical properties. Graphene layer identification is very important since its intrinsic properties change drastically between each 0.34-nm thick layer. Current methods of identification rely on restrictive small-area microscopy techniques, the most robust being micro-Raman spectroscopy. Here we present a new method for a large-area graphene layer identification characterized by low cost, high accuracy, high throughput, complete automation, and scalability. Our metrology tool is based on a fast image processing algorithm, which analyzes optical contrasts between single-layer, bi-layer, and few-layer graphene used for exfoliated, transferred, or grown graphene flakes on large wafers verified by micro-Raman spectroscopy.
Properties of Quasi-Two-Dimensional Crystals of Titanium Ditelluride
Authors: Khan Javed M. , Nolen Craig M. , Teweldebrhan Desalegne , Balandin Alexander A.
Published: October 2010

We report a method for obtaining atomically thin layers of titanium ditelluride (TiTe2) and describe the electronic and phonon properties of the resulting quasi-2D crystals. TiTe2 belongs to the class of transition-metal dichalcogenides, which have a layered crystalline structure. This material can be separated out into atomically thin tri-layers of Te - Ti - Te. Due to the nature of the extremely small thickness of these atomically thin quasi-2D crystals, ~0.271 nm in height, one can achieve strong spatial confinement of charge carriers and phonons. Our approach allows one to tune the electron and phonon transport properties of this atomically thin material to enhance their electrical, ferromagnetic and thermoelectric properties.
(Invited) Nano Characterization of Materials
Authors: Schroder Dieter K.
Published: October 2010

Material and device characterization is challenged by continuously decreasing device dimensions placing significant demands on cha-racterization instruments and measurement interpretation. The trend in many techniques is clearly toward characterization of smaller di-mensions. Among the myriad of characterization techniques in use today, I discuss recent advances in probe microscopy, interferometric microscopy, transmission electron microscopy, electron holography and tomography, nano secondary ion mass spectrometry, atom probe ion field ion microscopy and X-ray tomography. All of these have made significant advances and have produced very impressive results. For example, TEM is now able to generate images with 0.05 nm lateral resolution, allowing display of individual atoms. Probes in conjunction with magnetic fields have demonstrated vertical resolu-tion of 0.0015 nm. Progress in developing further advances in nm dimensional characterization will, no doubt, continue to satisfy the demand for such measurements.
(Invited) Practical Method and Physics of Evaluation for Vacancy Concentration of Silicon Crystals by Measuring Low-Temperature Elastic Softening
Authors: Yamada-Kaneta Hiroshi , Baba Shotaro , Nagai Yuta , Akatsu Mitsuhiro , Mitsumoto Keisuke , Yanase Takashi , Okabe Kazuki , Ono Yasushi , Nemoto Yuichi , Goto Terutaka
Published: October 2010

The paper reports the recent progress of our research on the vacancies in boron-doped (B-doped) as-grown silicon crystals of commercial-base quality achieved by means of the low-temperature ultrasonic measurements. The paper also demonstrates how our research-base technique for the vacancy observation is established as the practical tool of evaluating the vacancy concentration of the commercial silicon crystals and wafers. An emphasis is made on the confirmation of the following findings obtained in our previous experiment for the elastic softening by the vacancies in boron-doped silicon crystals: (1) the steep softening that suddenly starts at 2-4 K in the cooling process, and (2) the complete disappearance of the softening by a weak magnetic field of 4 T applied along [111] direction. We further investigate in detail how the low-temperature softening at a fixed temperature responds to the applied magnetic field, to find the following characteristic anisotropy: The manner of disappearance of the softening strongly depends on the direction of the magnetic field. For the magnetic field imposed along [1-10] direction, nearly 60 % of the full softening still remains even at a strong magnetic field of 8 T, in contrast to the case of magnetic field applied along [111] direction.
(Invited) Nano-Beam Diffraction: Crystal Structure and Strain Analysis at the Nanoscale
Authors: Favia Paola , Popovici Mihaela , Eneman G. , Wang Gang , Bargallo-Gonzalez Mireia , Simoen Eddy , Menou Nicolas , Bender Hugo
Published: October 2010

Two different applications of the nano beam diffraction technique are reviewed: the determination of crystallographic orientation and the evaluation of strain at the nanoscale. Both applications benefit of the small parallel electron probe to obtain information that cannot be achieved with conventional electron diffraction or other analysis methods.
Recent Insights In Solid Phase Epitaxy of Silicon and Germanium
Authors: Johnson Brett C. , Stavrias Nikolas , Kandasamy Sasikaran , Pyke Daniel , Holland Anthony , McCallum Jeffrey
Published: October 2010

The crystallization of amorphous layers via solid phase epitaxy (SPE) is commonly used in semiconductor device fabrication to activate dopants. The kinetics of SPE depend on temperature, dopant and impurity concentration, hydrostatic pressure and crystallographic orientation. The effect of H on SPE in both Si and Ge is discussed. Numerical simulations are performed to model the H diffusion, the moving amorphous/crystalline interfaces and the refinement of the H profile at these interfaces. Despite the high H concentration involved, a simple Fickian diffusion model results in good agreement with the SIMS data. A significant fraction of the H escapes from the a-Si layer during SPE and becomes trapped at end of range defects. The light-emitting properties of these defects are investigated. Finally, the formation of germanides via SPE is discussed.
(Invited) Strain Scaling and Modeling for FETs
Authors: Moroz Victor , Choi Munkang
Published: October 2010

Stress engineering overview is given including the reasons behind its ongoing evolution. Some aspects of the stress-induced defect formation are discussed. Guidelines for avoiding such defects are proposed based on stress evolution in and around transistors during the process flow. Stress-induced performance is addressed with the focus on conversion of stress-enhanced mobility into stress-enhanced on-state current. FinFET-specific stress engineering is analyzed as well as the stress vs capacitance trade-offs. Usage of simulation tools for optimization of various stress-related design trade-offs is demonstrated. It is concluded that it is a pursuit of beneficial stress patterns that improve transistor performance without creating defects and increasing variability that defines evolution of stress engineering techniques.
(Invited) Strain Mapping of Layers and Devices Using Electron Holography
Authors: Claverie Alain , Cherkashin N. , Hüe F. , Reboh S. , Houdellier F. , Snoeck E. , Hyütch M.
Published: October 2010

We present the HoloDark technique which has recently been invented and allows one to map strain in two dimensions in layers and devices with nanometer resolution, high precision and large field of view. The technique is based on electron holography and is applicable to all standard focused-ion beam FIB prepared crystalline samples. We show a panorama of typical results obtained in SiGe stacks, ion implanted silicon, strained silicon channel nMOS and pMOS type transistors and in the challenging case of strained silicon FinFETs, In such materials and structures, the HoloDark technique, although still perfectible, appears as the only technique able to provide reliable and extended data against which simulations can be calibrated.
(Invited) Applications of Epitaxy for Semiconductor Technology
Authors: Sadana Devendra K. , Bedell Stephen , Adam Thomas N. , Reznicek Alexander , He Hong
Published: October 2010

The role of epi in CMOS as one of the key performance enhancing element for both bulk-Si and SOI technologies is well established. This review discusses e-SiGe, e-Si:C, and raised source drain epi research for 15 nm and beyond nodes. Impact of proposed device design change from "doped body" to "undoped body" will be examined. Finally, growth options for strained SiGe (> 50%) on Si without a graded buffer layer have been studied to fabricate short channel pFETs. Challenges and opportunities for epi in the context of future generation CMOS are discussed.
Low-Temperature Epitaxial Si, SiGe, and SiC in a 300mm UHV/CVD Reactor
Authors: Adam Thomas N. , Bedell Stephen , Reznicek Alexander , Sadana Devendra K. , Murphy Richard J. , Venkateshan Aarthi , Tsunoda Takaaki , Seino Takuya , Nakatsuru Junko , Shinde Sanjay
Published: October 2010

Low-temperature epitaxial Si, SiGe, and SiC films were grown in a 300mm cold-wall UHV/CVD reactor on (100) silicon wafers (bulk and SOI) at temperatures ranging from 300 to 800 °C using disilane, germane and methylsilane. Four key advantages of UHV/CVD over RPCVD are demonstrated: (i) higher structural quality of epitaxial Si using disilane as a precursor, (ii) highly controlled growth of ultra-thin Si down to ~ 6 Aå, (iii) planar growth of SiGe at ultra low temperature (< 375 ºC), and (iv) planar growth of germanium at temperatures of less than 350 ºC.
Monochlorosilane for Low Temperature Silicon Epitaxy
Authors: Tomasini Pierre , Weeks Keith D.
Published: October 2010

Silane (SiH4) and dichlorosilane (DCS) are currently the precursors of choice for the vapor phase epitaxy of silicon at low temperatures (T < 1000 C). Device innovation is pushing down process thermal budgets to the extent that it becomes apparent that in the near future SiH4 and DCS will face challenges in maintaining high growth rates and achieving selectivity at low temperatures. New precursors that produce high growth rates at low deposition temperatures (< 650 C) are needed for advanced epitaxial applications such as recessed source/drain stressors, p-Metal Oxide Semiconductor channel and elevated source/drain structures. In this work, monochlorosilane (MCS) is investigated for the deposition of Si thin films such as blanket Si:P, selective epitaxial Si and Si1-xCx:P. MCS brings a substantial improvement in selective epitaxial silicon growth rate and HCl consumption as compared to DCS.
Formation of Pseudo-Expitaxial Ge Films on Si(100) by Droplet of Ge Microliquid
Authors: Matsumoto Tatsuya , Higashi Seiichiro , Makihara Katsunori , Akazawa Muneki , Miyazaki Seiichi
Published: October 2010

A small droplet of liquid Ge was formed by ejecting molten Ge from a 300 μmφ nozzle of a carbon cylinder heated at 1850 K. When a liquid Ge was dropped onto hydrogen-terminated c-Si and quartz surface under N2 ambient without any external heating, the width and height of solidified Ge crystals can be controlled in the range of 3.5 to 6.0 mm and of 20 to 900 μm, respectively, by adjusting the amount of molten Ge and injecting N2 pressure. From the Raman scattering spectra of solidified Ge films show peak position of Ge-Ge TO phonon band and FWHM for the Raman scattering spectra were almost the same as those of single crystalline Ge(100). In addition, preferential growth of Ge droplet, reflecting the orientation of the Si(100),(110),and (111) substrates, were also confirmed by X-ray diffraction measurements.
Investigation of Process Parameters on the Properties of Selective Epitaxial Growth SiGe Structure
Authors: Kim Sun-Wook , Yoo J.-H. , Koo Sang-Mo , Ko Dae-Hong
Published: October 2010

This work presents the effect of process parameters such as substrate condition, flow rate of precursors and dopant on selective epitaxial growth (SEG) of Si1-XGeX layer in recessed source and drain (S/D) regions of pMOSFET structure. It was observed that the growth rate of SEG Si1-XGeX on patterned wafer was slightly less than that of Si1-XGeX on bare wafer as GeH4 flow rate increased. And an in-situ boron-doped SiGe layer exhibits lower growth rate and Ge content than intrinsic SiGe layer due to a decrease of GeH4 partial pressure. Nano beam electron diffraction (NBD), which is an efficient method to measure induced compressive strain in Si channel, is applied on both intrinsic and in-situ boron doped Si1-XGeX layers with a different Ge content. NBD patterns confirmed that higher Ge concentration introduces more strain in the channel region and in-situ boron doping of Si1-XGeX does not affect the channel strain.
Design, Manufacture and Performance of Germanium Bipolar Transistors
Authors: Li Kezheng , Gamble Harold S. , Armstrong Mervyn , McNeill David W. , Armstrong Alastair
Published: October 2010

Germanium NPN bipolar transistors have been manufactured using phosphorus and boron ion implantation processes. Implantation and subsequent activation processes have been investigated for both dopants. Full activation of phosphorus implants has been achieved with RTA schedules at 535C without significant junction diffusion. However, boron implant activation was limited and diffusion from a polysilicon source was not practical for base contact formation. Transistors with good output characteristics were achieved with an Early voltage of 55V and common emitter current gain of 30. Both Silvaco process and device simulation tools have been successfully adapted to model the Ge BJT(bipolar junction transistor) performance.
Control of Strain Relaxation Behavior of Ge1-xSnx Layers for Tensile Strained Ge Layers
Authors: Shimura Yosuke , Takeuchi Shotaro , Nakatsuka Osamu , Zaima S.
Published: October 2010

We have investigated the dependence of strain relaxation behavior of Ge1-xSnx layers on the misfit strain at the interface between Ge1-xSnx layers and substrates. When the large misfit strain was induced, surface roughening and degradation of the crystallinity occurred during the Ge1-xSnx growth. We found that the universal dependency of the strain relaxation behavior, which is independent on kinds of substrates. As a result, the Ge1-xSnx layer having a Sn content of 12.3% was achieved, which has a potential to induce a tensile strain of 1.28% in a Ge layer.
Optical Property of Si0.8Ge0.2/Si Multilayer Grown by Using RPCVD
Authors: Kim Taek Sung , Kil Yeon-Ho , Shin Mi Im , Jeong Tae Soo , Kang Sukil , Choi Chel-Jong , Shim Kyu-Hwan
Published: October 2010

We have investigated the characterization of Si0.8Ge0.2/Si multi-layer grown directly onto Si (001) substrates using reduced pressure chemical vapor deposition (RPCVD). The structural properties of the Si0.8Ge0.2/Si multi-layer were investigated using X-ray diffraction (XRD) and TEM. Three peaks are observed in Raman spectrum, which are located at about 514,404, and 303 cm-1, corresponding to the vibration of Si-Si, Si-Ge, and Ge-Ge phonons, respectively. The PL spectrum originates from the radiative recombinations both from the Si substrate and the Si0.8Ge0.2/Si multi-layer. For Si0.8Ge0.2/Si multi-layer, the transition peaks related to the QW region observed in the photocurrent spectrum were preliminarily assigned to electron-heavy hole (e-hh) and electron-light hole (e-lh) fundamental excitonic transitions.
Stable Position of B12 Cluster Near Si(001) Surface and Its STM Images
Authors: Maruizumi Takuya , Ito Shunsuke
Published: October 2010

We report first-principles examinations and STM images of the most stable position of B12 clusters in both icosahedral and cubo-octahedral forms near the Si (001) surface. The icosahedral form is found to be more stable than the cubo-octahedral form, and a cluster is found to be most stable when its center is 4 layers below the surface and is directly under a Si dimer. STM simulations revealed that at low sample bias voltages the Si dimers above the B12 cluster are distinguishable from other dimers. B 1s XPS chemical shifts for the stable B12 cluster were calculated in order to clarify the chemical bonding configuration of B atoms in heavily doped Si samples made by plasma doping.
A Physics-Based Trap-Assisted Tunneling Current Model for Cryogenic Temperature Compact Modeling of SiGe HBTs
Authors: Xu Ziyan , Niu Guofu , Luo Lan , Cressler John
Published: October 2010

The work presents a new physics-based compact model of trap-assisted tunneling (TAT) current in forward biased base-emitter junction. Such TAT current is negligible at room temperature, but becomes significant at cryogenic temperatures. Inclusion of TAT current and its separation from the total base current is not only important for lower VBE base current, but also affects extraction of the ideal base current. The model is successfully applied to a first-generation SiGe HBT technology from 43 to 110 K.
fMAX Increase to 500 GHz of SiGe HBTs at Low Temperature
Authors: Zerounian Nicolas , Diallo Mariam , Aniel Frédéric , Chevalier Pascal , Chantre Alain
Published: October 2010

SiGe HBTs exhibiting fmax of 400 GHz at room temperature have shown fmax value of 500 GHz at low temperature (30 K). It helps highlighting which are the limiting factors to reach 0.5 THz fmax target of the DotFive European project at room temperature.
Influence of the Selectively Implanted Collector Integration on +400 GHz fMAX Si/SiGe:C HBTs
Authors: Lacave Thomas , Chevalier Pascal , Campidelli Yves , Depoyan Linda , Berthier Ludovic , André Frederic , Buczko Michel , Avenier Gregory , Gaquière Christophe , Chantre Alain
Published: October 2010

Optimization of SiGe HBT performances towards very high cut-off frequencies fT and fMAX requires high collector doping level together with low collector/base junction capacitance CBC. This compromise is usually achieved by localizing a dedicated collector implant (so-called SIC implant) under the intrinsic emitter/base region of the device. In this paper, we present the influence of the integration choice of the Selectively Implanted Collector (SIC) on the performance of +400 GHz fMAX Si/SiGe:C HBTs featuring a selective epitaxy of the base [1]. We describe in the first part of this paper the different process flows investigated for the SIC integration. Second part is dedicated to the analysis of the electrical results obtained for the different SIC modules and to the understanding of these results. We conclude on the perspectives to further improve hf performances.
Room-Temperature Resonant Tunneling Diode with High-Ge-Fraction Strained Si1-xGex and Nanometer-Order Ultrathin Si
Authors: Sakuraba Masao , Takahashi Kuniaki , Murota Junichi
Published: October 2010

For the purpose of heterointegration of Si-based group IV semiconductor quantum effect devices into Si large-scale integrated circuit, formation of atomically flat heterointerfaces in quantum heterostructure by lowering Si barrier growth temperature was investigated in order to improve negative differential conductance (NDC) characteristics of high-Ge-fraction strained Si1-xGex/Si hole resonant tunneling diode. It was found that roughness generation at heterointerfaces is drastically suppressed by utilizing, Si barriers with nanometer order thickness deposited using Si2H6 reaction at a lower temperature of 400oC instead of SiH4 reaction at 500oC after the Si0.42Ge0.58 growth. NDC characteristics show that difference between peak and valley currents is effectively enhanced at 11-295K by using Si2H6 at 400oC, compared with that using SiH4 at 500oC. Thermionic-emission dominant characteristics at higher temperatures above 100 K indicates a possibility that introduction of larger barrier height (i.e., larger band discontinuity) enhances the NDC at room temperature by suppression of thermionic-emission current.
Formation of High Aspect-Ratio Ge-Fin Structures with {110} Facets by Anisotropic Wet Etching
Authors: Moriyama Yoshihiko , Ikeda Keiji , Kamimuta Yuichi , Tezuka Tsutomu
Published: October 2010

As a template for scaled Ge-FinFETs, anisotropic wet etching was applied to obtain narrow Ge-fins with smooth sidewalls. It was found that Ge (110) facets were formed with a higher pH APM etchant. 100nm-width Ge-fin structures were slimmed to approximately 30nm by the APM etching. Moreover, LWF (Line Width Fluctuation) values of the Ge-fin were reduced by the emergence of (110) facets due to the lower etching rate on {110} surfaces. These results suggest that the wet etching process is applicable to future high-performance Ge-FinFETs.
Germanium on Nothing for Nanowire Devices
Authors: Thomas Paul M. , Pawlik David , Freeman Eugene , Romanczyk Brian , Rommel Sean
Published: October 2010

The authors present a fabrication process by which Germanium-on-nothing (GON) can achieve ordered arrays of locally thinned Ge nanowires for integration into CMOS or sensor applications. GON involves epitaxial Ge grown in oxide trenches on a Si substrate and then a series of wet and dry etching define the suspended wire structures. Arrays of GON nanowires, as small as 147 nm long and 48 nm wide, have been attained through this method. GON has the potential to monolithically integrate Ge NWs for transistor and NEMS applications on a Si substrate.
Critical Factors for Enhancement of Compressive Strain in SGOI Layers Fabricated by Ge Condensation Technique
Authors: Takagi Shinichi , Tomiyama Kentaro , Dissanayake Sanjeewa , Takenaka Mitsuru
Published: October 2010

SGOI layers with high compressive strain and high Ge content are promising channel materials for high current drive pMOSFETs under future technology nodes. In order to clarify the way of maximizing strain in SiGe-On-Insulator (SGOI) structures with high Ge fraction fabricated by th Ge condensation technique, we have examined the strain relaxation behaviors of the SGOI layers during the condensation process. The relationship among compressive strain in SGOI, the oxidation recipe and the substrate structures before oxidation has been quantitatively evaluated. With increasing the Ge fraction, the compressive strain in the SGOI layers linearly increases in lower Ge contents and rapidly decreases after it reaches peak values. It is found that the higher oxidation temperature and the Ge content in the SiGe epitaxial layers before oxidation are influential factors in mitigating the strain relaxation, in addition to the use of the strained Si-On-Insulator (sSOI) substrates As a result of optimizing these structural parameters, we have successfully obtained SGOI with 2.5% compressive strain under the Ge content of 0.86.
(Invited) Band-Engineered Ge-On-Si Lasers for Integrated Photonics
Authors: Liu Jifeng , Sun Xiaochen , Camacho-Aguilera Rodolfo , Kimerling Lionel C. , Michel Jurgen
Published: October 2010

Electronic-photonic synergy has become an increasingly clear solution to enhance the bandwidth and improve the energy efficiency of information systems. Monolithic lasers on silicon are ideal for large scale electronic-photonic integration. Germanium is a particularly interesting candidate for this application due to its pseudo-direct gap behavior in the near infrared regime for optical communications and compatibility with advanced silicon complementary metal oxide semiconductor (CMOS) technology. In this paper, we review theoretical modeling and experimental studies on optical gain and lasing from monolithic epitaxial Ge-on-Si devices band-engineered by tensile strain and n-type doping to compensate the energy difference between the direct and indirect conduction valleys. Demonstrations of optical gain and lasing at room temperature indicate that the Ge-on-Si laser is a promising candidate for monolithic electronic-photonic integrated circuits.
(Invited) Optoelectronic Monolithic Integration of Waveguided Metal-Germanium-Metal Photodetector and Ge CMOSFETs on SOI Wafer
Authors: Zang H. , Wang J. , Lo G.Q. , Lee Sungjoo
Published: October 2010

We demonstrate monolithic integration of waveguided Metal- Germanium -Metal photodetector (WG-MGM-PD) and Ge CMOS with high-k dielectric and metal gate on SOI wafer using novel epi-growth technique. WG-MGM-PD achieves a responsivity of 0.6A/W and speed (f3dB) of 17.4GHz. Ge CMOS with ultra-thin EOT (1.4nm) was demonstrated with 2 times hole mobility improvement over the Si universal mobility and very low gate leakage current (10-5~10-4A/cm2).
300mm Cold-Wall UHV/CVD Reactor for Low-Temperature Epitaxial (100) Silicon
Authors: Adam Thomas N. , Bedell Stephen , Reznicek Alexander , Sadana Devendra K. , Venkateshan Aarthi , Tsunoda Takaaki , Seino Takuya , Nakatsuru Junko , Shinde Sanjay
Published: October 2010

A 300mm cold-wall UHV/CVD reactor was used to grow epitaxial silicon layers on (100) SOI wafers at 500 to 800 °C using disilane, silane, and mixtures thereof. Spectroscopic ellipsometry was utilized to measure the deposition rates and wafer uniformities after growth, and high-resolution atomic force microscopy was employed to extract surface roughness and assess step flow growth. In the massflow controlled deposition region, both disilane and silane resulted in a linear dependence of growth rate on gas flow where disilane dominated over silane. In the reaction-limited regime, both precursors exhibited a perfect rate limitation with activation energies of ≈ 2 eV. Unlike in RPCVD, the deposition rate of disilane was found to approach twice that of silane at lowest temperatures. Step-flow growth was maintained even after 1μm of silicon was deposited under high-rate conditions. Additionally, continuous epitaxial films with thickness as low as 4 Aå were also obtained.
(Invited) Si-Ge-Sn Technologies: From Molecules to Materials to Prototype Devices
Authors: Kouvetakis John , Tolle J. , Mathews J. , Roucka Radek , Menéndéz Jose
Published: October 2010

We report new approaches based on rational design and preparation of chemical vapor deposition precursors involving novel main-group hydrides to fabricate new families of Si-based semiconductors and prototype devices that display compositional and structural inheritance, from the parent molecule to the solid end-product. This methodology enables materials synthesis at extraordinarily low temperatures that are compatible with CMOS processing/selective growth, and provides the means for obtaining highly metastable strain states in prototype structures that cannot be obtained by conventional protocols. Some of the materials and devices under development, involving alloys in the Si-Ge-Sn system, open up exciting opportunities in photodetectors and photovoltaics because they grow directly on cheap Si substrates and cover an extended range of the near-infrared spectrum that is not accessible to current photovoltaic and optoelectronic group IV semiconductors.
(Invited) Toward Si/SiGe Quantum Dot Spin Qubits: Gated Si/SiGe Single and Double Quantum Dots
Authors: Simmons Christie , Prance J. R. , Thalakulam Madhu , Rosemeyer B. M. , Van Bael B. J. , Savage Donald E. , Lagally Max G. , Joynt R. , Friesen Mark , Coppersmith S. N. , Eriksson M. A.
Published: October 2010

Quantum dots in Si have attracted recent interest due to the possibility of long spin relaxation and spin dephasing times in this material. Si/SiGe heterostructures are a particularly promising host for Si quantum dots, because the epitaxial interfaces that define the quantum well are believed to have very low defect density. Here we discuss recent results demonstrating that gate- tunable quantum dots containing individual electrons can be reproducibly produced in the Si/SiGe materials system. We discuss the tunability of the tunnel rates to the leads, the role of such tunnel rates in the determination of the absolute number of electrons in the quantum dots, and the role of the interdot tunnel rate in double quantum dots.
Advanced Strained-Silicon and Core-Shell Si/Si1-xGex Nanowires for CMOS Transport Enhancement
Authors: Hashemi Pouya , Poweleit Christian , Canonico Michael , Hoyt Judy
Published: October 2010

Top-down fabrication and characterization of vertically-stacked suspended strained-silicon nanowires (s-SiNWs) and Ge-shell/Si-core NWs are demonstrated. Epitaxially-grown strained-Si/relaxed-Si0.7Ge0.3 superlattice structures with up to 5 periods were patterned into arrays of nanoscale wires, and s-SiNWs were suspended by selective etching of the inter-level Si0.7Ge0.3 layers. Micro-Raman measurements reveal that 2.3GPa of tensile stress (mainly uniaxial) is present at the midpoint of 30 nm-wide s-SiNWs, and this amount of stress is maintained in 5-level-stacked nanowires. In addition, p-MOSFETs with Si-core/Ge-shell nanowire channels formed by selective epitaxial growth of Ge on the Si-nanowires were realized and integrated with a high-K/metal gate process to investigate hole transport in these non-planar nano-heterostructures. It is observed that defects in the Ge originate from the Si corners. In addition, Ge {111} facets are seen. Hole mobility increase, as high as 40%, has been observed as the NW width is decreased down to 20 nm.
Ge/Si Core/Shell Nanowire Structures for Tunneling Devices
Authors: Smith Joshua T. , Zhao Yanjie , Razavieh Ali , Yang Chen , Appenzeller Joerg
Published: October 2010

In this work, the concept of band-to-band tunneling (BTBT) devices is explored and the benefits of Ge/Si core/shell nanowire heterostructures (NWHs) as a material/geometry-related choice are discussed, namely increased performance accessible by 1D material systems that operate in the quantum capacitance limit (QCL), higher tunneling currents than available to Si-based tunneling structures, and compatibility of Ge/Si platforms with current manufacturing processes. The realization of such devices requires a degenerately doped source with an atomically abrupt source/channel interface. Toward this end, we present the electrical characterization of n+-Si shells around Ge cores that are close to the range suitable for the fabrication of optimized tunneling field effect transistors (TFETs). Specifically, we show that tuning the shell growth temperature from 470 to 600 °C has a significant impact on the morphology and transport properties of the grown Ge/Si core/shell nanowires.
(Invited) High Power Waveguide Ge/Si Photodiodes
Authors: Bowers John E. , Piels Molly , Ramaswamy Anand , Yin Tao
Published: October 2010

High-performance analog optical links require photodiodes that can handle large amounts of optical power. The power-handling capability of a photodiode is typically limited by 1) space-charge effects and 2) thermal effects. Space-charge effects can be overcome by using a uni-traveling carrier (UTC) design with the appropriate doping profile and bias voltage. Ge and Si have much higher thermal conductivities than the InGaAs absorbing layers and InGaAsP waveguide layers usually used for high power waveguide photodetectors at 1.3 and 1.5 um. Consequently, we have measured dramatically higher power handling in these devices. We have used a thermoreflectance imaging technique to measure the surface temperature of a waveguide photodiode under high-power operation. The results from this measurement closely agree with a finite element model of the device. Additionally, it has been shown that the heat generation in the depletion region of a waveguide photodetector closely follows the absorption profile.
(Invited) Integration of Germanium Avalanche Photodetectors on Silicon for On-Chip Optical Interconnects
Authors: Assefa Solomon , Xia Fengnian , Vlasov Yurii
Published: October 2010

A waveguide-integrated Germanium avalanche photodetector with gain-bandwidth-product of 350GHz, sensitivity improvement of 6dB, and excess noise with keff ~ 0.2 was demonstrated while operating with 12dB gain at around 3V bias voltage. The photodetector has capacitance of 10+2fF and operates at 40Gbps. Monolithic integration of thin single-crystalline Ge into front end CMOS stack was achieved by rapid melt growth during sourcedrain implant activation anneal.
(Invited) Ge/Si Waveguide Avalanche Photodiodes on SOI Substrates for High Speed Communication
Authors: Kang Yimin , Saado Yuval , Morse Mike , Paniccia Mario , Campbell Joe , Bowers John E. , Pauchard Alexandre
Published: October 2010

In this paper, we report the development and performances of two high-bandwidth Ge/Si waveguide avalanche photodiodes (APDs). They are either evanescent-coupled or directly butt-coupled with a multi-mode silicon-on-insulator waveguide. Both APDs demonstrate low dark current, high internal responsivity at long wavelength. The measured bandwidths are 23 GHz and 28.5 GHz at unity gain for evanescent- and butt-coupled APDs, respectively. Importantly, the corresponding receiver sensitivity is measured as -30.4 dBm at 10 Gb/s. This is already better than the current commercial available III-V based APD receivers.
(Invited) SiGe MEMS Technology: A Platform Technology Enabling Different Demonstrators
Authors: Witvrouw Ann , Van Hoof Rita , Bryce George , Du Bois Bert , Verbist Agnes , Severi Simone , Haspeslagh Luc , Osman Haris , De Coster Jeroen , Wen Lianggong , Puers Robert , Beernaert Roel , De Smet Herbert , Rudra Sukumar , Van Thourhout Dries
Published: October 2010

In imec's 200mm fab a dedicated poly-SiGe above-IC MEMS (Micro Electro-Mechanical Systems) platform has been set up to integrate MEMS and its readout and driving electronics on one chip. In the Flemish project Gemini the possibilities of this platform have been further explored together with the project partners. Three different demonstrators were realized: mirrors for display applications, grating light valves (GLV) and accelerometers. Whereas the mirrors and GLVs are made with a ~300 nm thick SiGe structural layer plus optical coating, the SiGe structural layer thickness for the accelerometers is 4µm in order to improve the capacitive readout of in-plane devices. The processing and measurement results of these functional demonstrators are shown in this paper. These new demonstrators reconfirm the generic nature of the SiGe MEMS platform.
Functionalized Back-End Devices for (Bi)CMOS Circuits
Authors: Wenger Christian , Walczyk Christian , Walczyk Damian , Lukosius Mindaugas , Fraschke Mirko , Wolansky Dirk , Santos Paulo V.
Published: October 2010

The integration of various functionality to (Bi)CMOS circuits is in the focus of the "More than Moore" approach. Here, we demonstrate the incorporation of surface acoustic wave (SAW) devices as well as of nonvolatile memories (NVM) into the Back end of line (BEOL) of Bi(CMOS) circuits. The added functionalities open new technological possibilities for high value microelectronics systems.