(Invited) Probability of Low Off Angled 4H-SiC Epitaxial Wafers on Power Device Applications
Authors: Kojima Kazutoshi , Masumoto Keiko , Asamizu Hirokuni , Harada Shinsuke , Okumura Hajime 
Published: February 2020

Nowadays, the size of 4H-SiC bulk wafer in R & D stage have already reached at 8-inch. In this situation, wafer off angle is considered to be a big issues on reducing wafer cost due to existence of large material loss when slicing wafers from a SiC ingot. Epitaxial growth technique for low off angle 4H-SiC substrate lower than 4 degree is one of solutions for above issue. However, large step bunching is easily generated on low off angled epitaxial wafer surface and affects the device performance like long time reliability. So, it is very difficult to apply such wafers to power device applications. In this study, we investigated the probability of low off angled 4H-SiC epitaxial wafers on power device applications. To do this purpose, we focused on improvement of surface quality on low off angled epitaxial wafer. In addition, we fabricated Schottky barrier diodes, MOS capacitors, and Trench gate MOSFETs on grown epitaxial wafer and investigated theses characteristics. . In this study, we used horizontal hot wall type CVD with SiH4-C3H8-H2 gas system for epitaxial growth. On substrates, we used 2 degree and 0.8 degree off 4H-SiC Si-face 3 inch substrates that can be conventionally purchased. As the result, we found the balance of growth temperature and C/Si ratio is significantly important to control the generation of step bunching. In our case, when the growth temperature is low about 1500ºoC, the generation of large step bunching can be well suppressed. However, generation of in-grown stacking fault or triangular defects is enhanced. On the other hand, higher growth temperature close to 1700ºoC easily generates such step bunching nevertheless the generation of above defects is well suppressed. This tendency becomes strong with reducing wafer off angle. We could well take a balance between growth temperature and C/Si ratio and suppress the generation of large step bunching on 2 degree off 4H-SiC Si-face epitaxial wafer. By the AFM measurement, we could observe step terrace structure dependence on wafer off angle. The Ra and the step height were 0.48 nm and less than 1 nm at 10 mm square, respectively. It means surface quality of 2 degree off epitaxial wafer is almost the same as that of 4 degree one. We fabricated SBDs and MOS capacitors on as grown surface. For I-V characteristics of SBDs, except for 2 SBDs into 52 points shows good I-V characteristics. For forward characteristics, an average n value of all points is 1.03 and deviation is 1.4%. On the reverse ones, all points showed blocking voltage higher than 600V and an average leakage current density of all points at 600V was 1.70 x 10-7 A/cm2. Concerning MOS capacitors, we carried out the TDDB measurement in whole 3-inch wafer. The number of measurement MOS capacitors is 2099 in whole wafer. The charge-to-breakdown (Qbd) of MOS capacitors fabricated on 2 degree off epitaxial wafer shows the same value with that on 4 degree one. For the epitaxial layer grown on 0.8 degree off 4H-SiC Si-face, we have applied the same way with 2 degree off epitaxial wafer. This way is well effective to suppress the generation of the large step bunching. However, in the view point of triangular defect, this way is not enough to suppress the generation of such defects. To solve this issue, we applied long time hydrogen etching before epitaxial growth. As the results, we could well suppress the generation of triangular defects. On the other hand, step bunching is still remained on the surface of 0.8 degree off Si-face epitaxial layer. We also fabricated trench gate MOSFETs on this wafer. The measured device characteristics are the same as that fabricated on 4 degree off epitaxial wafer. These results mean low off angle epitaxial wafer is possible to use for power device applications. This work was supported by “Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society” (2010-2015) organized by Ministry of Economy, Trade, and Industry (METI) and New Energy and Industrial Technology Development Organization (NEDO).