bluuebunny/crossref_metadata_2025 huggingface dataset:
Radiation Mechanisms and Electromagnetic Interference in Ceramic Electronic Packages
Authors: Aguirre Jerry , Vargas Marcos , Garland Paul
Published: October 2015

A full-wave electromagnetic analysis for characterizing typical electromagnetic shielding practices in ceramic electronic packages is presented. Typically in printed circuit board emissions, the power plane emissions, and exposed surface nets are considered, however, the signal interconnect from the PCB to an electronic package can also be a significant source of radiation and hence an electromagnetic interference (EMI) issue. In this paper we describe electromagnetic radiation mechanisms resulting from high-frequency and high-speed applications in ceramic multilayer electronic packages and review the typical practice of implementing via fences to mitigate and reduce the EMI risk within a package substrate and also for the case when the package is part of a package/board configuration.
Copper Wire Bonding: R&D to High Volume Manufacturing
Authors: Chylak Bob , Clauberg Horst , Foley John , Qin Ivy
Published: October 2015

During the past two years copper wire bonding has entered high volume manufacturing at a number of leading edge OSATs and IDMs. Usage of copper wire has achieved 20% market share and is expected to exceed 50% within three years. Products spanning the range from low pin count devices with relatively large wire diameter to FPGA's with nearly one thousand wires at 20 μm or even 18 μm wire are now using copper wire.

This paper will discuss the requirements for developing a robust copper wire bonding process and then moving it to high volume manufacturing. Process optimization begins with the selection of the appropriate wire diameter, ball diameter, bonding tool and bonding process type. These are functions not only of the bond pad opening, but also of the pad aluminum thickness and relative sensitivity of the pad to damage. Proper optimization depends on the availability of new and modified bond quality metrologies, such as extensive reliance on cross-sectioning and intermetallic coverage measurements. The bonding window of a copper wire bonding process is defined in substantially new terms compared to optimization in gold wire bonding.

Once an optimized process has been developed in the lab on a single bonder, it needs to be verified. Copper wire bond processes are much less forgiving with respect to the acceptable variability on the manufacturing floor. To ensure that the process is stable, a low volume pre-manufacturing test is highly recommended. This not only makes sure that the process is stable across multiple bonders, but also ensures the adequacies of manufacturing controls, incoming materials quality and sufficient equipment calibration and maintenance procedures.
Response of Long Sculpted Wire Bonds to Vibrational Excitation
Authors: Marinis Thomas F. , Soucy Joseph W.
Published: October 2015

The pitch of wire bond connections is decreasing to meet the need for higher interconnect densities, while at the same time, the ratio of wire length to diameter is increasing, which lowers the mechanical resonant frequency of the wire. In many applications in which MEMS sensors are coupled with ASIC front end electronics, the bonded wires can be subjected to a wide frequency spectrum of mechanical vibrations. One potential consequence is that the parasitic capacitances of the sensor could vary dynamically at a magnitude comparable to that of the sensor signal. In extreme cases, intermittent shorts or fatigue failures of the wire bonds could occur. A recent paper by Barber et. al, showed that wire bonds carrying alternating currents in a strong magnetic field could suffer fatigue failure.[1] Their analysis and experiments focused on simple loop geometries. In many applications, more complex wire bond geometries are used to minimize loop height and obtain dense wiring in stacked chip configurations. These geometries give rise to many more vibration modes with unique resonant frequencies and displaced shapes. We have used simple analytical beam models in conjunction with finite element models (FEM) to study various wire bond configurations subject to mechanical vibratory excitation. We focused on the effects of overall wire length and geometric shape on resonant modes. The finite element models were also used to calculate the capacitance between adjacent wires subject to mechanical excitation at one or more of their resonant frequencies. We show that there is an apparent shift in the time averaged capacitive coupling that increases with increasing vibration amplitude.
Method to measure wafer stiffness in Fan-Out Wafer Level Package
Authors: Teixeira Jorge , Ribeiro Mário
Published: October 2015

Wafer level packaging is an important development trend for IC package design. One of the emerging variants is the fan-out wafer level package (FO-WLP), namely Embedded Wafer Level Ball Array (eWLB) [1].

In the eWLB process, singulated known good dies are placed into a “reconstituted wafer” with enough space around each chip to accommodate second-level connections. Space between dies is filled with molding compound, this construction results in a plurality of microelectronic elements triggering a particular mechanical behavior.[1].

Two of the main characteristics associated to the handling and process capabilities of wafers are warpage (or bow) and stiffness. These two properties are directly related to the success of the wafer handling and processing. However, all equipment and processes running FO-WLP were designed to process silicon wafers, which have high and homogenous rigidity and whose behavior approaches that of a true elastic material, in opposition to the “reconstituted wafer”. This fact poses several manufacturing and process challenges when dealing with “reconstituted wafers”.

Currently, different warpage methods and measurement systems are available, but wafer stiffness assessment is not yet explored and to our knowledge there is no commercially available instrument to perform this task.

In our research, it's presented an original experimental method to measure wafer stiffness. The method is based on an apparatus specifically designed to quickly record the force-displacement curve of wafer stiffness. Results are demonstrated by varying different characteristics of reconstituted wafers: Si/mold compound ratio, wafer thickness, mold compound, humidity absorption and process steps. The correlation between wafer stiffness and warpage was also investigated.

This method has been successfully used in the field and showed to be a valuable process instrument for both product development and process monitoring.
Formulation of percolating thermal underfills using hierarchical self-assembly of micro- and nanoparticles by centrifugal forces and capillary bridging
Authors: Brunschwiler Thomas , Schlottig Gerd , Ni Songbo , Liu Yu , Goicochea Javier V. , Zürcher Jonas , Wolf Heiko
Published: October 2015

Thermal underfills are crucial to support integration density scaling of future integrated circuit packages. Therefore, a sequential process using hierarchical self-assembly of micro- and nanoparticles is proposed to achieve percolating thermal underfills with enhanced particle contacts. The three main process steps hereby are assembly of filler particles by centrifugation, formation of nanoparticle necks by capillary bridging, and the backfilling of the porous structure with an unfilled capillary adhesive.

Numerical simulations predicting trajectories and distributions of micron-sized particles dispensed into a rotating disk are presented. The trajectories exhibit a strong dependence on the particle size; thus in the case of polydisperse filler particles nonuniform particle beds may result. An efficient centrifugal disk design with spiral-like guiding structures is experimentally validated. Defect-free, percolating particle beds in confined space with fill fractions of 46 vol-% to 66 vol-%, i.e., close to the theoretical limit, are also presented.

The self-assembly of nanoparticles, forming enhanced thermal contacts between the percolating filler particles, is discussed. Two consecutive evaporation patterns during the capillary bridging process were identified: 1) dendritic network growth and 2) collapse of capillary bridges. The concave neck topology could only be achieved at temperatures below the boiling point. An optimal evaporation temperature of 60°C with respect to in-plane uniformity and neck shape was identified. Existing thermal gradients normal to the cavity surface resulted in strongly asymmetric neck formation in the cavity. Hence, uniform heating in an oven is the preferred method to initiate evaporation. Two types of bimodal dielectric necks are demonstrated. Polystyrene acts as the adhesive between thermally conductive alumina particles to form mechanically stable dielectric necks after an annealing step at 140°C. Interstitial and core-shell necks are presented.

Finally, a benchmark study was performed to compare the effective thermal conductivity of the percolating thermal underfill with and without necks with state-of-the-art capillary underfills. A close to fivefold improvement could be obtained for diamond filler particles with silver necks (3.8 W/m-K).
Characterization of Interconnects and RF Components on Glass Interposers
Authors: Ndip Ivan , Töpper Michael , Löbbicke Kai , Öz Abdurrahman , Guttowski Stephan , Reichl Herbert , Lang Klaus-Dieter
Published: October 2015

As a result of their myriad of advantages over silicon and other conventional substrate technologies, glass substrates have received significant attention from the electronic packaging and system integration community worldwide. So far, most of the research effort on glass has concentrated on developing methods for fabricating cylindrical through glass vias (TGVs). However, to fully evaluate the potential of glass as an interposer material for microelectronic systems with computing and communication functions, an extensive characterization of interconnects and RF components on these substrates must be carried out.

In this contribution, we go beyond state-of-the-art research and present an in-depth characterization of TGVs, coplanar lines and 60 GHz coplanar excited patch antennas on two glass substrates. One of these substrates has a low alkaline content (Borofloat33®) and the other is alkaline-free (AF32®). The effects of these glass materials on the RF performance of TGVs, coplanar lines and 60 GHz antennas are extensively studied, and recommendations for performance optimization are proposed. For experimental verification, test samples are fabricated and measured. Very good correlation is obtained between the measurement and simulation results from 100 MHz to 100 GHz.
Formation of Through-Glass-Via (TGV) by Photo-Chemical Etching with High Selectivity
Authors: Pei Zingway , Sun Jui-Po , Lai Hsin-Chen , Tzeng Pei-Jer , Lin Cha-Hsin , Ku Tzu-Kun , Kao Ming-Jer
Published: October 2015

In this work, we utilize a photo-chemical etching (PCE) method to form through-glass-via (TGV). The PCE is a low cost, damage-free and potentially large-area method for TGV formation. An ultra-violet (355 nm) pulse laser was used to illuminate the glass surface. The illuminated region will crystallize after thermal annealing in a furnace. The crystallized glass shows much faster etching rate than the amorphous region in HF solution. For a relatively thick (600 nm) glass, a via-hole with diameter of around 60 μm was demonstrated in laser energy of 11 J/cm2. No laser damages were observed. In comparison, at least 10 times higher energy was required to drill a glass directly. Micro-cracks were form around the glass-via. In addition, a 40 selectivity was achieved to the crystallized and amorphous region. This simple and useful method paves a straight road for 3-D integration.
A Wafer-level System Integration Technology Incorporates Heterogeneous Devices
Authors: Yamada Hiroshi , Onozuka Yutaka , Iida Atsuko , Itaya Kazuhiko , Funaki Hideyuki
Published: October 2015

A pseudo-SoC technology incorporating heterogeneous devices has been developed by applying a wafer-level system integration technology. The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and redistribution layer, respectively. The individual heterogeneous devices are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper describes the heterogeneous devices integration technologies and focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications.
Isothermal Aging Effects on the Thermal reliability Performance of Lead-Free Solder Joints
Authors: Zhang Jiawei , Hai Zhou , Thirugnanasambandam Sivasubramanian , Evans John L. , Bozack M. J.
Published: October 2015

Electronics assemblies containing solder joints are often exposed to elevated temperatures for prolonged periods of time. The time-at-temperature stress impacts the overall package reliability of the assembled circuitry due to evolving materials, microstructural, and mechanical properties. It is especially important to understand the impact of isothermal aging on the long term behavior of lead (Pb)-free solder joints which operate in harsh environments. In this study, we have explored the effects of elevated temperature isothermal aging on the reliability of Sn-Ag-Cu (SAC) assemblies on board level packages. As the isothermal aging temperature increases, the Weybull characteristic lifetime for SAC 105 and 305 solder joints is drastically reduced compared to Sn-37Pb.In parallel mechanical studies on bulk solder specimens, the creep rate for SAC105, 305 rapidly increases with aging. A full test matrix with varying aging temperatures and solder alloys was considered. Package sizes ranged from 19mm, 0.8mm pitch ball grid arrays (BGAs) to 5mm, 0.4mm pitch μBGAs. The test structures were built on three different board finishes (ImSn, ImAg and SnPb). Storage condition temperatures were 25°C, 55°C, 85°C and 125°C with aging over time periods of 0, 6, and 12 months. Subsequently, the specimens were thermally cycled from −40°C to 125°C with 15 min dwell times at the high temperature. It was found that the thermal performance of lead-free fine-pitch packages significantly degrades up to 55–60% after aging at elevated temperature. The dominant failure mode can be associated with the growth of Cu6Sn5 intermetallic compounds (IMC) during the aging, particularly on the pad side.
Package Reliability Monitored Drop Shock and Temperature Cycling Testing Progression and Advantages
Authors: Ferrara Michael
Published: October 2015

The increase in sophistication of reliability testing over the past several years is in part driven by the increase in complexity of package architecture it is meant to evaluate. Movement from a pass/ fail centric suite of testing toward a trend of increased design for reliability and potential problem analysis driven testing criteria is evident. A facet of this is the increased emphasis on test to failure approaches for certain package related tests such as drop shock testing. Additionally, there is an increased importance for extracting more meaningful data from standard fixed duration tests such as temperature cycling. In-situ monitored reliability testing for both drop shock and temperature cycling is an effective method for evaluating package technologies from a test to failure and immediate failure feedback perspective.
Solution for HVM TSV Etch Process
Authors: Roy Rajiv , Wilson Matt
Published: October 2015

As the industry is getting their hands around processes critical to cost-effective and reliable TSV manufacturing a key enabler is process control through inspection and metrology. In working with the industry, Rudolph has developed a suite of solutions that incorporate inspection, metrology and software enabling rapid yield ramp. The solution set apply all the way from via etch to CMP, RLD, micro-bumping and all the way to Chip on Wafer mount and post-saw. Within the TSV process a challenging inspection is that of detecting defects after CMP and nail reveal. The bonded wafers are warped, there are no alignment fiducials and the resolution requirement is high. Rudolph has developed a specific solution designed to address the nail reveal defectivity issue.
Accurate Prediction of Thermal Resistance of FET by Detailed Modeling of Heat Generation and Backend Stackup
Authors: Wan Qun , Willis Don , Jin Daniel
Published: October 2015

In typical thermal modeling of a FET (field effect transistor) structure, the power could be modeled as the heat generation, which is averaged under the entire gate length (gate averaged). However, it is found from the electrical potential field within the channel that the heat generation is actually distributed all the way from source to drain with a heavy concentration around the gate edge at the drain side. In a typical case, the peak of the heat distribution is almost four times of the gate averaged. Therefore, accurate modeling of the heat generation averaging over a much smaller region near the gate edge (edge averaged) makes a significant difference. This paper focuses on the comparison of the edge averaged versus the gate averaged modeling development. Furthermore, the detailed topology of the backend stackup layers and their relative impacts on heat dissipation paths are evaluated and the practical simplification is proposed in the modeling development. The result shows that, for a single gate FET die, the thermal resistance is found to be 26% more than that of the gate averaged approach. For a multiple gate FET die, both methods give the same surface temperature on the top surface layer. However, the temperature difference (ΔTjs) between the junction and the top surface is different between the two heat averaging approaches and the edge averaged approach prediction doubles that of the gate averaged approach. It is also found that ΔTjs is independent of number of gates and only depends on the backend stackup details between source and drain.
Thermal Power of Mobile Application Processor
Authors: Kwon Heung Kyu , Hwang Jugnwook , Chung Hyunkwon , Kang Munsik , Cho Hyun Duk , Kim Young Min
Published: October 2015

Until recently, heat dissipation performance of the conventional mobile AP (Application Processor) and mobile phone hasen't been a critical issue because the level of heat generated from a low-frequency, single core AP was insignificant. However, as the mobile AP consumes more power by adopting high frequency multi-core CPU (Central Processing Unit) and GPU (Graphic Processing Unit), the heat dissipation performance of its application set, such as smart phone and tablet PC (Personal Computer) became a critical issue. The conventional stand alone type applications sets such as desktop PCs and servers could afford additional thermal management tools such as heat sink, heat pipe and cooling fan to improve thermal performances. On the contrary, the limited inside space of mobile set doesn't allow the use of conventional cooling methods so that the feasible thermal solutions for the mobile AP and mobile sets are limited. In addition, since mobile set is normally in contact with human skin during its operation, the criterion, Tcsmax (Maximum Case Skin Temperature) which determines the thermal power per-formance of the mobile set is different from the conventional criterion, Tjmax (Maximum Junction Temperature) of CPU. Therefore, the thermal performance of mobile AP and its mobile set should be carefully determined to satisfy the Tcsmax by considering AP operation power and heat dissipating performance of the its application set. This paper shows how to define the thermal power performance of mobile AP and its mobile application set and which technologies are important for future mobile AP and its application sets.
Influence of thermal ageing on void content and shear strength for selected lead free solder die-attach
Authors: Otiaba K. C. , Raju N. , Bhatti R. S. , Mallik S. , Bernasko P.K.
Published: October 2015

In flip-chip packaging technology, thermal performance can be improved by attaching heat spreader to the backside of the heat generating silicon die via thermal interface material. Solder thermal interface materials (STIMs) are preferred to their polymer-based counterparts because they relatively offer higher thermal conductivities. Unlike lead-based solders which have had a longer application history, lead-free solders are relatively new; thus, the reliability of these lead-free solders are subject of research interest. In this study, lead-free solder preforms with compositions of 96.5Sn3Ag0.5Cu, 99.99In, 97In3Ag and 58Bi42Sn were used for silicon die attachment on copper heat spreader. The void content and shear strength of the soldered joints after thermal ageing at 125°C for 50 hours, 100 hours, 200 hours and 300 hours were evaluated. Generally, the four studied solder joints show decrease in voids with thermal ageing though 96.5Sn3Ag0.5Cu and 58Bi42Sn comparatively manifested more reduction in voids. The shear strengths of 96.5Sn3Ag0.5Cu alloy and 99.99In are shown to be relatively more stable throughout the ageing time. The results also indicate that samples with lower void content comparatively result in higher shear strength and vice versa. These results are especially important for high temperature application environments of Pb-free STIMs like in automotive systems.
The Distribution and Transport of Alpha Activity in Tin
Authors: Clark Brett M.
Published: October 2015

The presence of alpha emitters in packaging materials pose an increased risk to device reliability as device size decreases and flip chip and 3-D packaging technology becomes more widespread. Particularly troubling is the observation that alpha emission increases over time in some reported instances. Several experiments were conducted to examine alpha flux behavior in tin materials and determine the cause for the temporal alpha emissivity increase. The experiments determined the distribution of the alpha emitters within the material volume, and a mechanism based on microsegregation is presented to explain the non uniform distribution. Data describing differential isotope distribution within tin are also presented, providing confirmation of 210Po transport within a solid tin matrix. The effects of microsegregation and 210Po migration on alpha emissivity over time will be discussed. Potential impacts from these mechanisms on alpha emissivity in packaging applications will also be presented.
Development of Silver Nanoparticle Ink for Printed Electronics
Authors: Wu Yiliang , Liu Ping , Wigglesworth Tony
Published: October 2015

Printable conductors with high conductivity would be critical for low-cost printed electronics. In view of printability, conductivity, and electrical stability, metal such as gold or silver derived from solution-deposited precursor compositions would be an ideal candidate. Xerox has been exploring the use of silver nanoparticles as conductor precursor composition for printed electronics. This paper reviews our research in the development of alkylamine-stabilized silver nanoparticles that can be sintered at low temperature (∼ 120 °C) for high conductivity (>10000 S/cm). Silver nanoparticle ink formulations based on these silver nanoparticles exhibit surface-energy independent printability which enables the fabrication of high-performance top-contact transistor devices, and self-assembly characteristic when printed on hydrophilic substrates which allows for large-area, defect-free source drain arrays to be printed with a narrow and uniform channel length.
High Yield Embedding of 30μm Thin Chips in a Flexible PCB using a Photopatternable Polyimide based Ultra-Thin Chip Package (UTCP)
Authors: Sterken T. , Op de Beeck M. , Vermeiren F. , Torfs T. , Wang L. , Priyabadini S. , Dhaenens K. , Cuypers D. , Vanfleteren J.
Published: October 2015

A thin chip package for off-the-shelf ICs is developed which enables the embedding of these chips into a flexible circuit board. The package consists of a copper fan-out on a polyimide substrate, in which the thinned IC (30μm) is embedded. These packages are subsequently integrated in a standard flexible circuit board (FCB). A microcontroller and a proprietary DSP processor are embedded using this technology. The yield of the Ultra-Thin Chip package (UTCP) was measured before embedding in the circuit board, and reaches up to 87% for the packaged microcontrollers (MSP430 family, known-good dies). The yield on the DSP processor was measured to be 62%. After embedding in the FCB, 95% of the functional UTCP-packaged dies are still functional.
Handling technology for 0.075-square mm powder IC chip
Authors: Noda Hideyuki
Published: October 2015

We have developed a packaging technology for powder IC chip of 0.075-square mm × 5 μm thickness. The chip, which can be embedded into papers, is expected to be a key device in pioneering new markets, where it can cheaply and easily manage a number of articles and identify papers such as securities. Manipulating a fine chip in a dry environment has been difficult due to adhesion of the other chips and scattering from the influence of electrostatic phenomena. However, using the micro-bead and cell trapping technology, it is possible to put the chips on a substrate one by one. The technique uses a double-surface-electrode chip, and a novel water-based chip handling technique composed of a micropipette manipulation and a self-aligned positioning. The double-surface-electrode structure that has two individual surface electrodes is advantageous in that when mounting the powder chip on a substrate, the chips are placed on the substrate without the need for highly accurate positioning, including the chip orientation control (upside-down, rotation). As for the micropipette manipulation, the chips are kept dispersed by stirring liquid with addition of a 0.5% surfactant to prevent chips from sticking together, and a flat-end glass micropipette successfully manipulated a single chip with high chip-capturing ratio. The self-aligned positioning of the chip uses micro liquid droplet shrinkage during evaporation process. The chip was able to move together with the droplet edge, and was positioned in the predefined hydrophilic domain. The liquid cushioning pick-up and placing action enables stress-free handling.
Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects
Authors: Miyairi Ken , Sunohara Masahiro , Charbonnier Jean , Assous Myriam , Bally Jean-Philippe , Cuchet Robert , Feldis Helene , Murayama Kei , Aizawa Mitsuhiro , Simon Gilles , Higashi Mitsutoshi
Published: October 2015

Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates.

A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analyzed and they will be discussed in this paper. The first half of this paper will focus on integration including several technical challenges such as: 10:1 Aspect Ratio dense TSV of 10μm diameter, damascene metal layers 100,000 25μm diameter micro-bumps per die, and a specific backside redistribution layer, and the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good uniformity among wafers.

The later half of this paper will focus on assembly process and reliability test. Conventional mass reflow was performed for each level assembly. As assembly was successfully processed, reliability test which were TC 1000 cycles to check electrical connection on daisy chain and C4 bump, HTS for 1000 hours to observe resistance change on C4 bump and HAST 1000hours to check underfill delamination was performed. All samples passed each reliability test. The results in detail will be discussed in this paper.
New Build-up Insulation Material Based on Cyclo-Olefin Polymer for High-Performance IC Packages
Authors: Tateishi Yohei , Fujimura Makoto , Iga Takashi , Jimbo Toshihiko
Published: October 2015

A variety of mobile devices such as smart phones, ultra thin laptops, and tablet PCs have been introduced to the world wide market, and the demands are gaining momentum. In technological perspectives, the trend is going to increased amount of data transfer and further miniaturization of the devices for more comfortable browsing and convenience. With this trend, a build-up insulation film material that plays an important role in interposer substrates for semiconductor packaging, is required to have higher performance to cover 1) low transmission loss, 2) extremely small line and space (L/S) with an ultra-smooth copper surface, and 3) low coefficient of thermal expansion (CTE). It has been very challenging to develop build-up film materials to meet all requirements. We have developed a new build-up insulation film material based on a unique polymer, cyclo-olefin polymer (COP), which has much lower moisture absorption, Dk, and Df than standard epoxy-based materials. The COP-based build-up insulation material has shown outstanding performance; low tangent loss (0.0045 at 5 GHz), 4 um/4 um in L/S with ultra smooth surface for copper plating (Ra < 100 nm), copper peel strength (7 N/cm), and low CTE (17 ppm/deg.C). It has also been found that the COP-based material demonstrates a wide process window for semi-additive process (SAP) that could help ensure easy manufacturing of interposer substrates besides the outstanding performance. For instance, as the material has strong chemical resistance against desmear solution, it does not significantly alter/damage surface roughness, plated copper peel strength, and via morphology. The newly developed build-up insulation material can be promising not only for bearing high electric performance to more sophisticated mobile devices, but also for contributing to high yield manufacturing thanks to easy processability, based on the new polymer, COP.
Integrated Ψ-Type Photonic Polarization Diversity Receivers for Wireless Radio-over-Fiber Communication Links
Authors: Rymanov V. , Dülme S. , Wachholz M. , Palandöken M. , Tekin T. , Stöhr A.
Published: October 2015

In this work, we present novel integrated Ψ-type photonic polarization diversity receivers (PPDRs), comprising two high-frequency 1.55 μm photodiodes (PDs) applicable in wireless radio-over-fiber (RoF) communication links. Therefore, geometries in the overall optical beam splitter (OBS) output section, e.g. optical mode-guiding stripe height, gap between the optical waveguides (WGs), WG widths and coupling length, are considered to obtain high polarization diversity for the developed PPDRs. Moreover, we demonstrate first experimental achievements based on the coupling length variation. In comparison to a conventional 3-dB Y-coupler-integrated device, the experimental results show a polarization-dependent behavior of the PPDR with a maximum polarization dependent loss (PDL) of >3 dB (e.g. measured at the WG-PDs) due to the integrated Ψ-type OBS output section. Taking further geometry parameters of the PPDR into consideration, an increased PDL is expected for the monolithically integrated WG-PDs.
Ag wire and Ag alloy wire reliability and molding compounds
Authors: Mizushima Aya , Kato Shinichiro , Abe Hidenori , Sadayori Naoki , Endo Yoshinori , Yasuhara Kazuhiko , Chiba Jun , Iwasaki Tomio
Published: October 2015

Ag wire and Ag alloy wire reliability experiments were conducted on both 28-lead SOP and 96-pin PBGA packages. Biased HAST (b-HAST) of Ag-wired packages with higher ion content molding compouds generated obvious defects promoted by ion accumulation mechanism. Intermetallic compounds (IMCs) at the corroded interface are identified using cross-sectional TEM/EDX. Ion selective affinity of intermetallic compound is rationalized using ab initio molecular dynamics simulation.
LORD SolderBrace™ Wafer Applied Coating for Improved Reliability and Throughput in WLCSP
Authors: Sears George , Tian Guoyun , Le Duy , Bradley Heather
Published: October 2015

As more manufacturers look to increase the size of Wafer Level Chip Scale Package (WLCSP) dies and also look to decrease the ball pitch, the susceptibility of the die to fail during thermal cycling and drop shock testing increases. The stress conditions introduced during thermal cycling from the mismatches in Coefficients of Thermal Expansion (CTE) lead to solder fatigue. The failure of WLCSPs during drop shock is found at the solder/pad interface. The general solution to address solder fatigue during thermal cycling and solder joint stress at the copper pad interface has been capillary underfilling the chips after chip attachment.

To address these issues, a new material from LORD Corporation – SolderBrace™ wafer applied coating, can be used to partially underfill the WLCSP die at the wafer level. This type of technology can be applied using existing equipment and processing techniques making these materials a more cost effective solution. This new material technology has enabled thermal cycling reliability improvements by replacing the final passivation layer with a new low CTE material as the partial underfill.

This wafer applied partial underfill material technology has been successfully used to provide increased thermal cycling and drop shock reliability in WLCSPs using a number of different methods that have been previously described. The method to be discussed in this paper is a production process using a screen printed, photo defined polymer system that does not require any in-process post cure.
Influence of the organic vehicle and inorganic additives on the properties of thick film pastes for AlN
Authors: Schmidt Richard , Wenzel Marco , Reinhardt Kathrin , Partsch Uwe , Rebenklau Lars , Eberstein Markus
Published: October 2015

New conductor pastes for AlN as substrate material with fired films of a sheet resistance below 25 mOhm/sq were investigated. The pastes consist of AgPd as conductive phase for leach resistance. Other paste ingredients are glasses of matched composition for adhesion and densification properties, little amounts of inorganic additives and organic vehicles for film deposition. The latter has a significant influence on the paste deposition and the resulting film properties as well. In order to shine light into these relationship systematic rheological studies of the organic vehicle and the manufactured pastes were performed. The rheological investigations include measurements in rheological steady-state as well as dynamic experiments. In addition, the solder properties of the fired film were studied. FESEM analyses were performed on the surface of the fired films.
A Non-Through Silicon Via 1000+ IO Package On Package Solution For Wide IO Applications
Authors: Mirkarimi Laura , Katkar Rajesh , Zhang Ron , Co Rey , Zhao Zhijun
Published: October 2015

We are developing a new solution for wide I/O package on package applications, which is Bond Via Array (BVA) technology. The prototype vehicle built in this study has 1020 I/O's at a pitch of 0.24 mm with a high aspect ratio of approximately 10:1 and is ≤1.4 mm tall. PoP applications require large bandwidth and thinner packages challenging package developers to address warpage control for high yield processes. The design optimization of this package was established through rigorous finite element analysis of materials selection and structural modifications. The simulation methodology was validated by measuring the warpage as a function of temperature for the experimental prototypes. The details for the simulation and verification processes for the wide I/O process will be discussed. The variation between finite element analysis predictions and the experimental builds was ~10%, which allowed us to complete package design optimization with our simulation tools. The prototype build includes a standard and a low CTE substrate.
Evaluation of Epoxy Flux for Use in Hearing Aid SMD Assemblies
Authors: Johansson Susie , Dzarnoski John
Published: October 2015

Miniaturization of everyday products has been driving sales for some time and continues to fuel the consumer market. Everyone expects size reduction with each new product generation [1], [2]. Almost everything has electronics inside that must get smaller. There is no market demanding smaller devices that are faster, more capable, more feature-rich than that of the hearing aid industry. While radios, Bluetooth wireless systems and other accessories are added to hearing instruments feature lists, the consumer nonetheless continues to wish for them to be even smaller. Advancements in circuit fabrication, component shrinkage and die consolidation have aided the industry in satisfying this need. However, as this demand continues and even intensifies, current surface mount device assembly materials are becoming inadequate and the limiting factor for overall circuit size reduction; specifically, the die attachment, protection and reinforcement process is limiting how small hearing aid circuits can be. For hearing aids, the addition of more features and connection to more accessories each require a number of integrated circuits and associated passives attached to a flexible circuit. These circuits are invariably bent and twisted during assembly, up to 180°, requiring the integrated circuit solder joints to be reinforced by underfilling to prevent detachment. Unfortunately, the underfilling process is time-consuming and the capillary action necessary for its success is finicky. Even more unfavorably, a designated “keep out” area for other components must surround the die to be underfilled to allow for the dispensing equipment to access the die, reducing the useable board space and limiting the overall possibility of circuit size reduction. Additionally, the underfill material must stay away from circuit board edges and areas to be bent during final assembly. In an attempt to increase useable circuit board space, decrease overall circuit board size, and reduce assembly steps, the application of two epoxy flux materials for die attach fluxing and underfilling of hearing aids was evaluated. Epoxy flux is a relatively new material, which combines the functionality of flux and underfill into a single step. Epoxy flux's application, while eliminating steps, would more significantly eliminate the necessary “keep out” areas around die and allow for more densely placed surface mount components. The epoxy flux materials were applied by both printing and dipping, and then evaluated using x-ray imaging, scanning acoustic microscope imaging, die peel testing, multiple reflow integrity testing and die shear testing.
Anti-Counterfeit, Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices
Authors: Das Rabindra N. , Egitto Frank D. , Lin How
Published: October 2015

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. This paper discusses the development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for miniaturized electronic devices. In particular, recent developments in high density interconnect (HDI) substrate technology are highlighted. System-in-Package (SiP), embedded passives, stacked packages, and flex substrates are utilized to achieve significant reduction in size, weight, and power (SWaP) consumption in electronic devices. The paper also describes a novel approach for the fabrication of silicone-coated flexible substrates to provide biocompatibility for implantable devices. In particular, we highlight recent developments on silicone coatings on high density, miniaturized polyimide-based flexible electronics. A variety of high density circuits ranging from 11 microns lines/space to 25 microns lines/spaces were processed on polyimide flex substrates and subsequently coated with biocompatible silicone coatings. The electrical performance of silicone coated batteries was characterized by voltage measurements. The final structure enhances the stretching capability. Fabrication of advanced medical substrates incorporating technologies for parts authentication (anticounterfeit measures) such as embedded signature circuits and use of nano or micro materials as signatures are discussed. In some instances, these measures do not add cost to package fabrication.
Non-Hermetic Micropackage for Chronic Implantable Systems
Authors: Wang P. , Lachhman S.B. , Sun D. , Majerus S.J.A. , Damaser M.S. , Zorman C.A. , Feng P.X.-L. , Ko W.H.
Published: October 2015

We report on the development of a non-hermetic micropackage technology that employs multiple layers of polydimethylsiloxane (PDMS), epoxy, and parylene-C thin films for conformal coating of chronic biomedical implantable systems with laboratory testing results in saline bath at 85°C, achieving very long micropackaging lifetime (up to ~2–5 years). By combining experiments of material characterization and qualitative analysis of the observations, we explain the measured long lifetimes of the micropackages (projected equivalent of ~2–5 years) using these non-hermetic coating materials and composites.
Ultrasonically Enabled Low Temperature Electroless Plating for Advanced Electronic Manufacture
Authors: Cobley A J , Graves J E , Kassim A , Mkhlef B , Abbas B
Published: October 2015

Electroless plating is an important process for the metallization of non-conductive substrates and is therefore widely utilized throughout the electronics and packaging industry. Electronic manufacture now requires processes and materials that can meet the demands for miniaturization and reliability since holes and via diameters in both printed circuit boards (PCBs) and microelectronics are being reduced whilst aspect ratios are getting higher. It is critical for the future development of electronics that manufacturing processes become adapted to meet these requirements. In terms of electroless plating, miniaturization means that ensuring full coverage in vias and holes is extremely challenging whilst the electroless deposit structure is important to ensure high reliability, high conductivity etc. In addition the plating process must be able to meet the need for high production volumes (i.e. high deposition rates) whilst enabling more sustainable, low energy manufacturing. Performing electroless plating in an ultrasonic field has great potential to enhance the deposit properties and meet these advanced manufacturing requirements. This paper will discuss the results from the IeMRC funded ULTIEMet (Ultrasonically enabled Low Temperature Immersion and Electroless Metallization) research project which has utilized a methodology incorporating a mixture of electrochemical and laboratory plating tests. It has been found that by optimizing how ultrasound is introduced to the electroless process benefits such as reduced temperature plating, enhanced coverage and a finer grain structure deposit can be realized.
An Overview of Isotropic Conductive Adhesives Filled with Metal-coated Polymer Spheres
Authors: Nguyen Hoang-Vu , Aasmundtveit Knut E. , Kristiansen Helge , Helland Tore
Published: October 2015

Novel isotropic conductive adhesives (ICAs) filled with metal-coated polymer spheres (MPS) have been introduced in order to improve the mechanical performance, and hence the reliability, compared to conventional ICAs filled with solid silver (Ag) particles. This paper summarizes a number of characterization studies on the electrical, the mechanical and the rheological properties, as well as a study on the reliability, of MPS-based ICAs. The feasibility of the ICAs filled with MPS has been demonstrated in terms of potential processing capabilities, improved mechanical performance and competitive electrical properties (compared to conventional ICAs with Ag flakes). Therefore, the MPS-based ICAs have a good potential for demanding environment applications, in which electronic products (e.g., hand held devices) are subjected to thermal shock and thermal cycling, mechanical vibration and mechanical shock.
Lithography Process Optimization for 3D and 2.5D Applications
Authors: Shelton Doug , Kume Tomii
Published: October 2015

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.
A Novel Epoxy Flux On Solder Paste For Assembling Thermally Warped POP
Authors: Hu Ming , Kresge Lee , Lee Ning-Cheng
Published: October 2015

A novel epoxy flux EF-A was developed with good compatibility with no-clean solder pastes, and imparts high reliability for BGA assembly at a low cost. This compatibility with solder pastes is achieved by a well-engineered miscibility between epoxy and no-clean solder paste flux systems, and is further assured with the introduction of a venting channel. The compatibility enables a single bonding step for BGAs or CSPs, which exhibit high thermal warpage, to form a high-reliability assembly. Requirements in drop test, thermal cycling test (TCT), and SIR are all met by this epoxy flux, EF-A. The high viscosity stability at ambient temperature is another critical element in building a robust and user-friendly epoxy flux system. EF-A can be deposited with dipping, dispensing, and jetting. Its 75°C Tg facilitates good reworkability and minimizes the adverse impact of unfilled underfill material on TCT of BGA assemblies.
Production Proven, High Precision Temporary Bond/De-bond Process
Authors: Dronen Blake , Shorey Aric , Wang B.K. , Tsai Leon
Published: October 2015

Wafer thinning represents a critical step in 2.5D and 3D-IC integration. Achieving low total thickness variation (TTV) of a bonded stack is essential since it directly impacts the TTV of the thinned device wafer. It is essential to understand and utilize appropriate processes and materials that provide precision bonded stacks prior to thinning operations in order to achieve high process yields. The 3M™ Wafer Support System and Corning's precision glass carrier wafers were used to produce bonded stacks. Leveraging metrology tools like the Flatmaster MSP-300 and low coherence interferometric probes allow for characterization of the TTV of each layer of a bonded stack and better understanding of the stack-up as well as how to minimize stack TTV. The ability to deliver stack TTV of < 2 um in a repeatable manner has been demonstrated.