bluuebunny/crossref_metadata_2025 huggingface dataset:
Passivation Damage and Residue-Induced Package Failure Analysis for a 16 Lead SOIC GaAs RF/IF Package
Authors: Cavasin Daniel
Published: December 2020

Recently, Motorola was notified that certain of their RFIC devices had failed electrically during Accelerated Life Testing (ALT) at their customer’s board-mounting facility. These devices were assembled in both 8 and 16 lead narrow-body SOIC packages, and had been previously qualified ‘by comparison’ as JEDEC Moisture Sensitivity Level (MSL) 1, indicating that the packages could be shipped without dry packing and left indefinitely at factory-level temperature and humidity, without the need for pre-baking before surface mount reflow. The returned parts exhibited delamination of the mold compound from the die surface, in some cases resulting in wire bond lifting. Since the parts had been shipped as MSL1 for several years in some cases, it was not deemed necessary to investigate whether the customers, Motorola N.S.S. in Fort Worth, TX, and Swindon, U.K., had implemented any changes in their handling procedures which may have impacted the MSL performance of the packages. At the beginning of February, 2000, because of the fact that the SOIC packages were assembled at an external subcontract facility, the issue was brought to the attention of the Motorola External Manufacturing Quality (EMQ) and External Final Manufacturing (eFM) organizations. A containment action was immediately implemented at the assembly site, which consisted of large-scale Scanning Acoustic Microscope (SAM) inspection of the assembled devices, to identify delamination after post mold cure (PMC). A separate series of more in-depth engineering analyses were also initiated, centering on three main areas: 1, Possible die surface contamination; 2, Possible mold compound material issues, and 3, Possible molding process variation. All such activities were conducted with the support and assistance of the IC packaging subcontractor. Results gathered from these activities are summarized below.
A Broadband Model for Ultrasonic Pulses in the Presence of Thin Layers in Microelectronics
Authors: Canumalla Sridhar
Published: December 2020

A broadband model is proposed to describe the nature of ultrasonic pulses in multilayered systems with a sub-wavelength thickness layer. This model, which is targeted towards acoustic microscopy of microelectronic devices, can incorporate measured ultrasonic properties of electronic materials and predict the complete ultrasonic pulse-train for all the interfaces in an electronic device. The model is robust, and incorporates material and geometric variables commonly encountered in microelectronics applications. Results are presented to illustrate how delaminations and cracks with foreign material or moisture ingress can appear to be well-bonded and why acoustic images of interfaces with thin layers can sometimes give erroneous indications of the bond state.
High Resolution Backside Thermography Using a Numerical Aperture Increasing Lens
Authors: Thorne S. , Ippolito S. , Eraslan M. , Goldberg B. , Ünlü M.S. , Leblebici Y.
Published: December 2020

As the feature size in integrated circuits (ICs) become smaller, the techniques we use to localize defects must also progress to the level that they can resolve potential errors. Additionally, because most errors cannot be identified by visual inspection alone, it is necessary to develop techniques, such as thermography, with the capability of localizing failures to the specific component or defect at fault. This paper will review the theory and application of an advanced subsurface (through the substrate) analytical technique for IC failure analysis – solid immersion lens thermal emission microscopy.
New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM)
Authors: Falk R. Aaron , Bauersfeld Neil , LaPierre Mark , Elliott Shawn
Published: December 2020

Thermal laser signal injection microscopy (T-LSIM) (aka TIVA and OBIRCH) has shown considerable promise in stateof- the-art digital integrated circuits. The technique has been utilized to locate shorts, leakage currents, problem vias, and timing issues in these devices. However, little has been published on the utility of this technique for analog and mixed signal devices. In this paper we demonstrate the application of T-LSIM on two different analog devices with defects that conventional FA technology and fault isolation techniques were unable to locate. Analog devices produce several unique challenges to the basic T-LSIM technique as typically utilized in the digital regime. Extensions of the basic T-LSIM technique were utilized to locate the failures, which produced unexpected results. The T-LSIM technique has proved essential in the quick identification and localization of failure sites. The T-LSIM technique provides the failure analyst with the analytical power not previously available on conventional fault isolation tools such as emission microscopy and liquid crystal.
Solder Bump Defects in Ceramic Flip Chip Packages and Their Acoustic Signatures
Authors: Ramanujachar Kartik , Rusli Darwin , Agarwal Reena , Widaski James
Published: December 2020

Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump defects. In this article we present experimental results that document the nature of interface defects in multi-layered solder bumps as well as their acoustic signatures. The acoustic signatures obtained from defective bumps are contrasted with the signals obtained from pristine bumps and the sensitive nature of these signatures to defects is highlighted.
Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis
Authors: Prejean Seth J. , Shannon Joseph
Published: December 2020

This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.
A Novel Approach to Front-Side Deprocessing for Thinned Die after Backside Failure Isolation
Authors: Nguyen Dat , Phan Cuong , Conner Jeff , Smith Martin , Drummond John
Published: December 2020

This paper describes a novel approach for safe handling of the thinned die from the front; a technique that can also be successfully applied to preserve cracked die. The discussion provides details on the characteristics and processes involved in backside reconstruction, thinned die reconstruction, and front-side deprocessing of thinned die. The finished backside reconstruction sample was cross-sectioned for examination using a diamond saw. After 6 hours of bake, no cracking of the thinned die was observed. Front-side deprocessing was then applied to the backside reconstructed sample. The sample remains intact. The technique has proven to be easily applied and highly reliable, and provides a solution for front-side deprocessing for both high pin count ball grid arrays and flip chips.
A Method for Exact Determination of DRAM Deep Trench Surface Area
Authors: Russell Jeremy D. , Tseng Yuan-Wei
Published: December 2020

A technique is described which allows the precise measurement of the surface area of the dielectric layer of a DRAM deep trench (DT) capacitor. It uses precision FIB sectioning, and allows determination with arbitrary accuracy. It can be used for measuring random DTs in a region of interest for process monitoring, and can also be used for a single target trench in the case of failure analysis.
A Review of TEM Observations of Failures of the Memory Cell in a Deep Trench Capacitor DRAM
Authors: Lue Jen-Lang , Lee Jack , Chen Esther , Luo Jian-Shing
Published: December 2020

Application of the high resolution of Transmission Electron Microscopy (HRTEM) plays a very important role in structural analysis and materials characterization for process evaluation and failure analysis in the Integrated Circuit (IC) industry. We summarize TEM observation experience of the common memory failures of a BEST deep trench cell with an N-MOS gate used in CMOS DRAM technology. Memory cell failures are categorized into three areas for discussion – the deep trench (DT) capacitor, the transfer gate (GC), and the borderless bit-line contact (CB) between a transistor and a bit line. Typical examples that occurred in these three areas are presented and provide a basic understanding of normal DRAM cell failures.
The Effect of TEM Specimen Preparation Method on Ultra-Thin Gate Dielectric Analysis
Authors: Du A. Y. , Tung C. H. , Freitag B. H. , Zhang W. Y. , Lim S. , Ang E. H. , Ng Danny
Published: December 2020

The three typical TEM specimen preparation methods are investigated for two different ultra-thin gate dielectric materials analysis. The results show that the mechanical polishing with short time, low angle ion milling is best specimen preparation method for both samples. FIB finial thinning can be used for SiON gate dielectric specimen analysis, but is not suitable for HfO2 gate dielectric analysis. After FIB thinning, severe Ga and Pt contamination on the specimen surface is found when using HR-STEM/HAADF imaging.
Forward Scattered Scanning Electron Microscopy for Semiconductor Metrology and Failure Analysis
Authors: Vanderlinde William E.
Published: December 2020

Continuing decreases in electron device feature size have strained the resolution limits of scanning electron microscopy (SEM). In this paper a simple method is demonstrated for producing significantly improved resolution in SEM imaging without making any special sample preparation or modifications to the SEM. This method images with the lowloss forward scattered electron signal by using a modified sample holder. The method was found to be particularly useful for observing low atomic number materials such as photoresist and molecular semiconductors in their natural state, i.e. without sputter coating.
Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results
Authors: Ferrier Steve , Martin Kevin D. , Schulte Donald
Published: December 2020

Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.
Novel Application of Transmission Electron Microscopy and Scanning Capacitance Microscopy for Defect Root Cause Identification and Yield Enhancement
Authors: Tangyunyong P. , Hill T. A. , Nakakura C. Y. , Soden J. M. , Cole E. I. , Flores R. S. , Shaneyfelt M. R. , Dockerty R. C. , Headley T. J. , Rye M. J.
Published: December 2020

Transmission electron microscopy (TEM) [1] and scanning capacitance microscopy (SCM) [2] have become common failure analysis tools at Sandia for new product development, process validation, and yield enhancement. These two techniques provide information that cannot be obtained with other analytical techniques. The information provided by these two techniques has been instrumental in identifying the root causes of several yield-limiting defects in CMOS IC technologies at Sandia. This paper describes an example of how TEM and SCM have been used to identify the root causes of SOI device failures. The corrective actions taken to reduce defects and improve yield are also described.
Contact Failure Due to Particulate Defect in a 0.13 µm CMOS Process
Authors: Bagchi Sandeep , Arunachalam Valli , Saenz Javier , Beck James , Duncan Lupe , Conner Jim
Published: December 2020

Random single bit failures were encountered in cache areas of Motorola’s 0.13 µm CMOS products under development. Extensive in-line probe data and end-of-line probe data in conjunction with failure analysis indicated the presence of particles at the upper surface of tungsten contacts. This paper describes how TEM based techniques were used to analyze the origin of the defect which in turn enabled process optimization and yield improvement.
ESD: Correlation between Electrical Signature and Failure Modes
Authors: Korchnoy V. , Lisenker B. , Posimeinik I.
Published: December 2020

The correlation between electrical characteristics and failure modes in some common cases of ESD protection circuitry is described. The investigation is based on experimental results obtained during the qualification of highly integrated CPUs and chipsets manufactured by 0.18 µm CMOS technology. The implementation of these data during qualification of 0.13 µm CMOS products allowed the decrease of qualification throughput time (TPT), and, in some cases, reduction of FA efforts. Some process related and designs related ESD concerns are discussed herein.
Recent Developments in Automated Sample Preparation for FESEM
Authors: Cerchiara R. R. , Fischione P. E. , Gronksy J. J. , Hein W. F. , Martin D. D. , Matesa J. M. , Robins A. C. , Smith D. W.
Published: December 2020

Standard analytical practice in the semiconductor industry depends on fast, efficient and reliable sample preparation prior to FESEM. “In lens” imaging technology and orientation mapping (EBSD) demand sample surfaces free of physical damage and residual contamination. An integrated preparation tool has been developed that incorporates the functionality necessary for argon – oxygen plasma cleaning, ion beam etching (IBE), reactive ion beam etching (RIBE), reactive ion etching (RIE), and ion beam sputter coating (IBSC). Control, monitoring and sequential automation of the processes is accomplished through a novel combination of software and hardware. FESEM results for Al and Cu based microelectronic materials will be discussed, as well as EBSD results for bulk metals. Improvements in throughput and subsequent materials characterization will be demonstrated.
Improvements of Secondary Electron Imaging and Endpoint Detection in Focused Ion Beam Circuit Modification
Authors: Ray Valery , Antoniou Nicholas , Krechmer Alex , Saxonis Andrew
Published: December 2020

Secondary electron signal is widely used in Focused Ion Beam (FIB) systems for imaging and endpointing. In the application of integrated circuit modification, technology has progressed towards smaller dimensions and higher aspect ratios. Therefore, FIB based circuit modification processes require the use of primary ion beam currents below 10 pA and Gas Assisted Etching (GAE). At low beam currents, short pixel dwell times and high aspect ratios, the level of available secondary electrons for detection has declined significantly. FIB GAE and deposition requires delivery and release of a gaseous agent near the beam scanning area, and involves insertion of a gas delivery nozzle made of conductive material and grounded for charge prevention purposes. The proximity of a grounded gas delivery nozzle to the area being milled and/or imaged creates a “shielding” effect, further lowering secondary electron signal level. The application of a small positive bias to the gas delivery nozzle provides an effective way of reducing the “shielding” effect. Depending on the geometrical arrangement of the gas delivery system and other conductive objects in the chamber, an optimized nozzle bias potential can create conditions favorable for enhanced extraction and collection of secondary electrons. The level of the secondary electron image signal, collected in an FEI Vectra 986+ system, from a grounded copper sample with the nozzle extended and biased can be enhanced as much as six times as compared to the grounded nozzle. Secondary electron intensity endpoint is improved on backside samples, however shielding of the nozzle field by the bulk silicon substrate limits the electron extraction effect from within a via. For front side edits the improvement of endpoint signal level can be dramatic. Lateral image offset induced by the electrostatic field of a biased nozzle, can be removed by software position compensation.
Fault Localization of a Scan Shift Problem on Integrated Logic Designs
Authors: Burmer C. , Egger P. , Huber A. , Cerva H. , Petit D. , Grellner F.
Published: December 2020

Effort and complexity for failure analysis are increasing on state of the art logic designs. As chips become more and more complex, functional tests are not possible anymore [1] and are replaced with automatic test pattern generation (ATPG) using a full scan design approach. Analysis of failing devices, however, becomes more complex as scan chains contain a large number of flip flops and localization of the failing net is a prerequisite for subsequent physical failure analysis (PFA). This becomes especially true for flip chip products, since access to the chip front side is not easily possible any more. This report describes the necessary failure analysis steps in order to identify the root cause of scan shift problems associated with two products fabricated in deep sub-micron technology
Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy
Authors: Lee Jon C. , Chuang J. H.
Published: December 2020

As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.
Magnetic Emission Mapping for Passive Integrated Components Characterisation
Authors: Crépel O. , Bouttement Y. , Descamps P. , Goupil C. , Perdu P. , Desplats R. , Beaudoin F. , Guirardel M.
Published: December 2020

We developed a system and a method to characterize the magnetic field induced by circuit board and electronic component, especially integrated inductor, with magnetic sensors. The different magnetic sensors are presented and several applications using this method are discussed. Particularly, in several semiconductor applications (e.g. Mobile phone), active dies are integrated with passive components. To minimize magnetic disturbance, arbitrary margin distances are used. We present a system to characterize precisely the magnetic emission to insure that the margin is sufficient and to reduce the size of the printed circuit board.
Sample Preparation Techniques for Analysis and Debug of Circuits with Cu Inductors and Thick Organic Dielectric
Authors: Sutton Mauri , Kiefer Scott , Wilson Syd , Nair Manoj , Sanders Paul , Steele John , Paulson Wayne
Published: December 2020

This paper describes techniques to prepare integrated circuit (IC) samples, containing a Thick Organic Dielectric (TOD) over Cu inductors, for Scanning Electron Microscopy (SEM) or Focused Ion Beam (FIB) editing. Our technique utilizes mechanical polishing and UV laser ablation in lieu of chemical decapsulation and deprocessing.
Laser Interferometer Specimen Preparation of PCB Assembled Components at Second Level Interconnect for In-plane Shear Strain Measurements
Authors: Cunningham William J.
Published: December 2020

Preparing Laser Interferometer (Moiré) samples involves several steps that can be time consuming and labor intensive. This process requires diligence and discipline in order to create a successful sample. Previous Moiré sample preparation methods have yielded <30% for component characterization. The sample preparation presented in this document has increased yield to approximately 90%. Improvements are the result of optimized tooling and a novel epoxy application technique. Prepared laser interferometer samples are used to subsequently reveal inplane strain and residual stresses present at the component of interest. Two applications that benefit from Moiré are as follows: 1) inelastic strains due to deflection or thermal cycling, and 2) elastic coefficient of thermal expansion effects resulting from high temperature cure to ambient temperature. In the first case, the inelastic strain is typical due to permanent residual deformation. In the second case, the thermal expansion effects are the result of growing and bending and then coming back to normal position. In this presentation both the ambient (inelastic) and the high temperature (elastic) sample preparation techniques will be covered in detail, thus providing the end user great success in capturing strain data.
A Novel Fault Isolation Technique for Identifying Deep Sub-Micron Defects
Authors: Bundhoo Fayik M. , Kasivisvanatha Soundaranathan
Published: December 2020

A novel failure analysis approach has been developed to isolate and characterize deep sub micron defects in P<100>- silicon lattice. This technique utilizes unique wet chemical deprocessing and side wall cleaning in conjunction with focused ion beam milling to isolate a single vertical failing DMOS source contact from a parallel array of 462K contacts covered with oxide dielectric and top metal layers. The two methods of analysis and root cause of crystalline lattice dislocation in a vertical DMOS transistor are discussed. TEM examination of implanted dopant interface was carried out in order to determine the nature and origin of lattice dislocations. A study1 indicates that lattice dislocations are generated by deep boron and arsenic implants that are not adequately annealed. In our analysis, these dislocations were observed as loop pairs causing low-level leakage that did not initially allow the part to fail. However, these silicon lattice dislocations do pose reliability issues.
Failure Analysis Case Study in 0.18μm Flash Memory Devices and Root Cause Identification
Authors: Chen Wen-Rong , Wu Mao-Sheng , Chu Chi-Ling
Published: December 2020

This report summarizes the analysis of 0.18µm Flash ROM technology qualification failure cases at Macronix. The cases include single cell read failures, erase/program function failures, and high temperature storage test failures. Electrical analysis, EMMI and physical check by chemical de-processing, parallel lapping, FIB, SEM, PVC and TEM techniques were employed to identify the failure mechanisms, root causes, and solutions. From this study, improvements were achieved in process defect density, test fault coverage and product reliability of the 0.18µm Flash ROM technology.
Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel In-Situ Methodology
Authors: Hartfield C.D. , Broz J.J. , Moore T.M.
Published: December 2020

The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reaching the best compromise of good contact resistance (CRES) performance with a minimum amount of probe damage, low-K materials present an increased risk of compromising the dielectric or barrier layers beneath bond pads. For a better understanding of the dynamic contact phenomenon of probing and its effect on the integrated circuit (IC) metal stack, a specialized in-situ nanomanipulator tool was developed for simultaneous visualization of probing events with data recording of electrical and load measurements. This paper describes initial research with this new tool.
A Multi-Stage Approach to Fault Identification Using Fault Tuples
Authors: Desineni R. , Vogels T. J. , Dwarakanath K. N. , Zanon T. , Blanton R. D. , Maly W.
Published: December 2020

We present a generalized method to attack fault diagnosis at the logic level that aims at localizing and differentiating fault types. In particular, we present an application of this method that aids in distinguishing opens and two-line shorts. While past work has addressed distinction between shorts and opens, we present an algorithm to generate more test patterns to narrow down the diagnosis callout based on type or location. In general, we are not limited to a few fault models as our description of the logic misbehavior is built on fault tuples. This becomes important in the area of fault and defect characterization. Results based on logic validation and SPICE simulations of extracted netlists indicate the usefulness and efficiency of our approach.
The Microstructure Evolution of Corrosion Phenomenon on Aluminum Bond Pads
Authors: Luo Jian-Shing , Lo Hui-Min , Russell Jeremy D.
Published: December 2020

X-ray photoelectron spectroscopy (XPS) is a very popular tool for identification of the chemical state of fluorine contamination on aluminum (Al) bond pads. To date, as far as the authors are aware the detailed microstructures of fluorine corrosion on bond pads have not been reported. This paper reports the microstructure evolution of fluorine corrosion on bond pads in a plastic box under specific environment conditions by using transmission electron microscopy (TEM), optical microscopy, focused ion beam and scanning electron microscopy (SEM). The elemental distributions and chemical bonding were performed by using Gatan Image Filter/TEM, energy dispersive X-ray/Scanning TEM (STEM), Auger electron spectroscopy and XPS, respectively. On Al pads with 35 atomic %, fluorine residual, corrosion was observed after around 10 days of storage and became more severe with time. The corrosion layers consist of nano-crystalline and amorphous for both single and double-layer structures.
Studies on a Failure Analysis Flow of Surface Contamination, Corrosion, and Underetch on Microchip Al Bondpads in Wafer Fabrication
Authors: Younan Hua
Published: December 2020

A failure analysis flow is developed for surface contamination, corrosion and underetch on microchip Al bondpads and it is applied in wafer fabrication. SEM, EDX, Auger, FTIR, XPS and TOF-SIMS are used to identify the root causes. The results from carbon related contamination, galvanic corrosion, fluorine-induced corrosion, passivation underetch and Auger bondpad monitoring will be presented. The failure analysis flow will definitely help us to select suitable methods and tools for failure analysis of Al bondpad-related issues, identify rapidly possible root causes of the failures and find the eliminating solutions at both wafer fabrication and assembly houses.
Scanning Capacitance Microscopy Application for Bipolar and CMOS Doping Issues in Semiconductor Failure Analysis
Authors: Lin Coswin , Ou Homy , Chao Chia-Hsing , Lu Shey-Shi
Published: December 2020

Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.
Analog Circuit Failure Analysis Using Time-Resolved Emission
Authors: Cain B.J. , Woods G.L. , Syed A. , Herlein R. , Nomura Toshihiro
Published: December 2020

Time-Resolved Emission (TRE) is a popular technique for non-invasive acquisition of time-domain waveforms from active nodes through the backside of an integrated circuit. [1] State-of-the art TRE systems offer high bandwidths (> 5 GHz), excellent spatial resolution (0.25um), and complete visibility of all nodes on the chip. TRE waveforms are typically used for detecting incorrect signal levels, race conditions, and/or timing faults with resolution of a few ps. However, extracting the exact voltage behavior from a TRE waveform is usually difficult because dynamic photon emission is a highly nonlinear process. This has limited the perceived utility of TRE in diagnosing analog circuits. In this paper, we demonstrate extraction of voltage waveforms in passing and failing conditions from a small-swing, differential logic circuit. The voltage waveforms obtained were crucial in corroborating a theory for some failures inside an 0.18um ASIC.
A New Non Destructive Method to Screen for Corona/Breakdown of a Transformer Core
Authors: Molle Gary M
Published: December 2020

There is a problem with testing torroidal or encapsulated transformers for their DWV characteristics in that the core is normally inaccessible. For high voltage transformers, knowing whether or not the core is sufficiently insulated to prevent breakdown is crucial to the component reliability. If there is a lack of dielectric material between any winding set and the core, it is impossible to determine potential failure susceptibility by the normal DWV testing means. Using MILT- 27’s “Corona discharge” test circuits for this determination requires special equipment, “corona free” capacitors, and has other issues. I have developed a screening method using a Fluorescent Lamp Supply “drive box” with a sinusoidal output from 2 to 7KVpp at or above 25 KHz that will expose corona in transformers when directly back driven into the secondary windings. Transformers that do not have sufficient insulation between winding sets and windings to core can develop corona discharge which can be seen on an oscilloscope via a commercially available isolated current probe as high frequency spikes modulating the original sine wave, heard on an AM radio the same as lightning or static discharge, or cause complete collapse of the voltage at test voltages within seconds when tested up to the rated voltage of the particular winding set. A sample set of 80 transformers was tested, and a 30 percent failure rate was discovered.
Hot Electron Induced Fiber Optic Transistor Beta Degradation, Recovery, and Dynamics of Hydrogen Atoms at the Si-SiO2 Interface Layer
Authors: Seo Kuhn , Monarch Jim , Dunlap Brett
Published: December 2020

Hot electron induced beta degradation has been observed from fiber optic transistors after multiple parametric testing. Beta degradation originated from increasing base leakage current due to the multiple testing. Base leakage current increases were directly related to the hot electron phenomenon at Si-SiO2 interface layer. The hot electron effect broke down the trivalent silicon and its hydrogen compounds (SisH) at the interface layer, which created mobile interstitial hydrogen atoms (Hi) and trivalent silicon atoms Si* (interface trap charges) at the same time. Typically, the SisH forms during the post metallization anneal. This paper will outline the following topics: 1.) The generation of mobile hydrogen atoms and trap charges at the Si-SiO2 interface due to the hot electron phenomenon and its relationship to transistor beta degradation. 2.) A quantitative analysis of hydrogen atoms measured by Secondary Ion Mass Spectrometry (SIMS), and a direct relationship model between beta degradation and hydrogen profiles at the interface layer. 3.) Experimental result showing transistor beta recovery as well as the repopulation of the hydrogen atoms at the interface layer after low temperature annealing (150 °C to 200 °C bake).
Focused Ion Beam (FIB) Method for Reconditioning Worn Tungsten Atomic Force Probe (AFP) Tips
Authors: Mulder Randal E. , Subramanian Sam , Chrastecky Tony
Published: December 2020

Atomic force probing (AFP) uses very sharp tungsten tips (100nm in radius) which wear out rather quickly, even with the greater durability of tungsten as compared to silicon. This paper demonstrates how worn tips that no longer image and probe properly can be reconditioned using the focus ion beam (FIB) tool. The method works best for tips that are under approx. 750nm in diameter and are not bent. It works well for freshly manufactured tips that do not work properly due to mishandling or improper storage which allowed particulates/oxide to build up on the tip. The method also works well for fresh tips that have been worn down (or slightly bent) after several hours of scanning and probing. This method is straightforward and requires a minimal amount of time. Typically, four probe tips can be reconditioned in about 30 minutes on the FIB.
An Alternative to High-Temperature and Acid/Solvent-Based Methods for Removing Integrated Circuits from Ceramic or Other Problem Substrates
Authors: Nail Carl M.
Published: December 2020

Dice must often be removed from their packages and reassembled into more suitable packages for them to be tested in automated test equipment (ATE). Removing bare dice from their substrates using conventional methods poses risks for chemical, thermal, and/or mechanical damage. A new removal method is offered using metallography-based and parallel polishing-based techniques to remove the substrate while exposing the die to minimized risk for damage. This method has been tested and found to have a high success rate once the techniques are learned.
FINANCIAL LITERACY OF UNIVERSITY STUDENTS MEASURED BY P-FIN INDEX
Authors:   College of Regional Development and Banking Institute – AMBIS, Department of Economics and Management, Lindnerova 575/1, 180 00 Praha 8, Czech Republic, Polák Josef , Kozubíková Zuzana ,   University of Žilina, Faculty of Managements and Informatics, Dpt. of Macro and Microeconomics, Univerzitná 8215/1, 010 26 Žilina, Slovakia, Kozubík Aleš ,   University of Žilina, Faculty of Managements and Informatics, Dpt. of Mathematical Methods and Operations Research, Univerzitná 8215/1, 010 26 Žilina, Slovakia
Published: December 2020

Financial literacy belongs to the most important competences of all members of the modern 21-st century society. The authors present results of the research based on the personal finance index that is recently developed an innovative measure of knowledge. The questionnaire research that has been conducted among the students of two universities in the Czech and Slovak republic. It focused on full-time and part-time students with the aim to verify the suggestion that practical experience of distance learning students has a significant impact on the level of their financial literacy. Statistical analysis of the data shows, that part-time students have achieved better results in all functional areas of the personal finance index. Based on these findings authors also drew some conclusions for improving education in this field.
THE DIFFERENT APPROACHES FOR THE MARKET SEGMENT B2G (B2A) COMPARED TO B2B AND B2C, BASED ON A CASE STUDY FOR INFRASTRUCTURE IN THE PHILIPPINES
Authors:   Faculty of Management, Comenius University, Bratislava, Krah Bernhard Alexander
Published: December 2020

In today´s highly competitive marketing methods, the market segments B2B (Business-to-Business) and B2C (Business-to-Consumer) are very well established and applied. The worldwide largest market segment, the B2A/B2G (Business-to-Administration/Business-to-Government) however, has until now received little or no attention in the literature. In the theoretical part of this paper, a focus has been placed on the measurements, how a company is able to find the right approach to operate its business successfully in this very specific business segment, where the players have completely different motivations. The aim of this paper is to gain insight into the basic concepts what rules must be followed to avoid delays, errors and losses, especially considering suppliers, who want to work internationally. This paper is complemented by a case study of an infrastructure product (sewage pipe system), that was manufactured and successfully launched and installed in the Philippines. This research shows the strategy for an infrastructure product market penetration for a new player in the market, with a „non-existent “product.
LINEAR ECONOMY AND CIRCULAR ECONOMY - CURRENT STATE ASSESSMENT AND FUTURE VISION
Authors: Gubeladze David , Solomon Pavliashvili
Published: December 2020

Economic Research of Agricultural Activities in Georgia, based on the experience of developed countries, it has become apparent that the key to comprehensive management of economic efficiency is the transition to a circular economy, which implies the creation of an alternative model to the traditional linear economy. In the proposed model, agricultural products will have maximum use in terms of yield, and the remaining agricultural products, given the value of each production cycle, are given the opportunity for new consumption after processing. The purpose of this paper is to present a new model of effective economic management of agricultural production based on the principles of circular economy.
Relevant Local Fatwā on The Issues of Using Human Tissues in Articular Cartilage Tissue Engineering Experimentation
Authors: AR Muhammad Aa’zamuddin , MA Nur Syamimi , AH Abdurezak , A Azhim , S Munirah
Published: December 2020

In articular cartilage tissue engineering (ACTE) experimentation, the researchers have utilised cells and tissues sampled from the human donor for research purposes. The cells and tissues may be harvested from the living donor’s discarded tissues through a medical procedure, e.g. the total knee replacement surgery. The small pieces of a tissue sample taken from the human donor are essential to study the articular cartilage regeneration for treating joint disease, i.e. osteoarthritis. However, the procedure has raised some ethical and fiqh (Islamic jurisprudence) concerns. The study was done by utilising the secondary analysis of local Muslim jurists’ opinions (fatwā) related to the sampling of human biological samples. This paper explores the scenarios of using cell sources taken from the living human donor through the existing fatwā of local Muslim jurists (fuqahā`). The scenarios include: (1) taking samples from the living donor, and (2) discarding human tissue, as practised in ACTE experimentation. The current fatwā has shown that honouring every part of a human body is considered essential in Islam. ACTE researchers may utilise the biological samples from living donors as alternatives in studying articular cartilage regeneration. The donation of human biological samples for research purposes in ACTE experimentation, obtained from a medical procedure, may be permissible, should the stipulated terms and conditions were observed, and the procedure does not cause any additional harm to the donor.
In Vitro and in Vivo Cytotoxic Effects of Chlorella Against Various types of Cancer
Authors: R Ahmad Raus , NS Adzahar , DF Basri , ES Latif , NJ Sallehudin
Published: December 2020

Chlorella is one of the microalgae that had been studied intensively owing to its rapid growth and easily cultured at a large scale compared to other microalgae and valuable nutrient compositions. Numerous studies have observed that Chlorella possess various health benefit including antioxidant, anti-cholesterol, anti-inflammatory, and antiproliferative effect against many types of cancer. In this review paper, the effects of various Chlorella species against cancer cells and animal induced cancer are discussed and an overview on Chlorella is briefed. The Chlorella deleterious effect on cancer through various mechanisms such as enhancement of immune system and apoptosis; improving lipid peroxidation; synthesis and expression of the protein-degrading matrix; and preventing the formation of new blood vessels are elaborated as well. Based on the findings of many studies reported in this article, it can be suggested that Chlorella has the potential in supporting cancer therapy and may develop to become an anti-cancer agent.
A Systematic Review of Immersive Social Media Activities and Risk Factors for Sexual Boundary Violations among Adolescents
Authors: FS Arsad , MIA Abdul Khani , F Daud
Published: December 2020

Social media is appealing to the general public, especially the teenagers. This has brought about changes as the role of social media has penetrated our daily activities which directly affects the adolescence. This review looked at the usage of social media amongst adolescents and its impact on their sexual behaviour. Four databases were used in the literature search ie Web of Science, PubMed, EBSCOhost, and Ovid Medline. The search terms used revolved around social media, adolescent and social behaviour. Only English literature published from 2015 to 2020 were included. A total of 244 potentially relevant articles were identified in the initial search. 16 were excluded due to duplicates. A further 199 articles were excluded due to irrelevant population, intervention or outcome. Only 29 articles were suitable for narrative synthesis. The selected articles were analysed for risk factors and impact on the usage of social media on sexual behaviour. Sexual abuse, same-sex sexual activity, pornography, multiple online sexual partner, and sexual dissatisfaction were found to be negative impact. Positive impact included understanding of sexual role and consequences, safe sex practices and improved psychological well-being. This systematic review proved social media usage amongst adolescents have great impact on their sexual behaviour. Sexting was the main social media online sexual activity amongst adolescents which brings about negative sexual behaviours. This must be curb from earlier on which demands parental supervision in monitoring adolescence online activities.
Fusobacterium Nucleatum : An Atypical Cause of Pyogenic Liver Abscess in an Apparently Immunocompetent Patient
Authors: AR Yusoff , NA Abd Razak , S Samsuddin , S Mokhtar
Published: December 2020

Pyogenic liver abscess is an uncommon but potentially lethal infection if left untreated. Enteric bacteria and anaerobes are the most common causative organisms of pyogenic liver abscess. Although most infections are of a polymicrobial nature, monomicrobial infections are possible. An immunocompromised status and the presence of periodontal disease are the risk factors for liver abscess caused by these rare, monomicrobial anaerobic infections. Here, we report on a successful non-operative management of a case of multiloculated pyogenic liver abscess caused by Fusobacterium nucleatum in a young, healthy, immunocompetent male patient. The diagnosis was established by radiological imaging and was based on a positive aspirate culture, whereas the mainstay of treatment comprised percutaneous drainage and a prolonged course of antibiotics. Thus, the patient was successfully treated with a 2-week course of intravenous imipenem/cilastatin while he was on percutaneous drainage, and he is now doing well.