CMOS Compatible Atomic-Precision Donor Devices
Authors: Ward Daniel R , Campbell DeAnna M , England Troy , Mincy John , Carr Stephen , Anderson Evan M , Schmucker Scott , Ivie Jeffrey , Scrymgeour David , Gao Xujiao , Lepkowski William , Lu Tzu-Ming , Tracy Lisa , Misra Shashank 
Published: May 2020

Atomic precision advanced manufacturing (APAM) is a technique for placing dopant atoms with single atomic-lattice site precision on silicon surfaces. APAM devices are created by patterning the placement of dopants into a two-dimensional sheet of phosphorus atoms on the silicon surface, incorporating the dopants into the lattice, and then capping the device in silicon. The dopant atoms are incorporated into the silicon lattice through a surface-activated chemical reaction, as opposed to a thermally activated bulk process, which allows for electrically active doping above the solubility limit for phosphorus in silicon. The two-order of magnitude higher doping levels and two-dimensional nature of the dopant sheet enable new device physics and the potential for new device types with superior performance under specific tasks.

Atomic precision fabrication requires atomically clean surfaces. Historically the APAM technique has required temperatures in excess of 1200 °C to prepare device surfaces, which has severely limited the ability to combine APAM with other manufacturing techniques such as CMOS. Recent work by our group and others has shown that the surface preparation process can be achieved at temperatures near 800 °C, greatly improving integration possibilities with CMOS [1,2]. Once fabricated, APAM devices have low thermal budgets to minimize vertical diffusion of the phosphorus dopants out of the non-equilibrium two-dimensional sheet. Temperatures on the order of 450 °C have been shown to be permissible for long periods of time.

In this talk we report on the initial development of a CMOS process flow that incorporates APAM device fabrication. Based on the thermal budget and processing constraints, our basic process flow involves building the APAM device between CMOS Front-end-of-line (FEOL) and the CMOS Back-end-of-line (BEOL) steps. This is a natural insertion point based upon both thermal budget limitations and the need to directly access the device silicon to build the APAM device. Borrowing from CMOS nomenclature, we introduce the concept of “APAM select” and “APAM active” to indicate where the window for APAM device patterning will be opened and the actual APAM device area, respectively. These are the only additional mask layers needed to introduce APAM into a CMOS layout cell. An APAM cell was created that has the appropriate source/drain placement and targeting reticle in poly-Si to enable alignment of the APAM lithography tool to the wafer.

Two classes of challenges exist in developing a CMOS-APAM process flow. The first is related to the APAM process itself and limitations of current fabrication tools. The APAM surface preparation, patterning, dopant incorporation, and silicon capping all occur in a scanning tunneling microscope (STM). Devices must be processed at the die level to fit into the STM sample holders. Die level processing puts restrictions on the BEOL processing including minimum feature size and available processes, such as a lack of chemical-mechanical polish (CMP) to planarize metal layers. The second class of challenges is related to the impacts of the APAM process, such as surface preparation, on CMOS devices, which has not been previously explored. We discuss our strategy for integration with CMOS, by including test structures to mimic the APAM device, and sequential implementation and testing of the APAM fabrication steps with CMOS chips.

We conclude with a discussion of future integration challenges such as wafer level processing of APAM devices in a CMOS foundry flow. Direct integration of APAM components into CMOS circuits opens the door for devices with enhanced functionality.

ACKNOWLEDGMENT

This work is supported by Sandia’s Lab Directed Research and Development Program, and was performed in part at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

References

[1] T. Skeren, et al., “CMOS platform for atomic-scale device fabrication,” Nanotechnology, vol. 29, pp. 435302, 2018.

[2] D. R. Ward, et al., “All-optical lithography process for contacting nanometer precision donor devices,” Appl. Phys. Lett., vol. 111, pp. 193101 (2017).