bluuebunny/crossref_metadata_2025 huggingface dataset:
How Trace Analytical Techniques Contribute to the Research and Development of Ge and III/V Semiconductor Devices
Authors: Hellin David , Rip Jens , Bonzom Renaud , Nelis Daniel , Sioncke Sonja , Brammertz Guy , Caymax Matty R. , Meuris Marc M. , De Gendt S. , Vinckier Chris
Published: November 2006

Ge and III/V semiconductor substrates are recently being investigated as a candidate material for the replacement of Si substrates in advanced micro-electronic devices. The reintroduction of this material requires engineering of the standard IC processing steps. In this paper, we present how the trace analytical techniques of total reflection X-ray fluorescence spectrometry (TXRF) and atomic absorption spectrometry (AAS) contribute to the realization of suitable processes to realize a high quality gate stack on Ge and GaAs substrates. A conventional application for these techniques lays in contamination control on incoming wafers. Besides this, we demonstrate some more advanced applications such as the determination of dopant concentrations (As in Ge), the study of passivation processes (S on Ge) and the characterization of nanometer thin layers (Si on Ge, HfO2 on Si).
Ge Selective Epitaxial Growth with Ultra Thin SiGe Buffer Layer
Authors: Nakatsuru Junko , Date Hiroki , Mashiro Supika , Ikemoto Manabu
Published: November 2006

In this study, we introduced another very thin SiGe layer that was selectively grown on the Si buffer layer prior to the ultra- thin Si0.5Ge0.5 buffer growth. As a result, selective epitaxial growth of Ge film with good crystalline quality was realized without increasing intermediate layer thickness or thermal budget significantly. This technique is expected to be applicable for the Ge channel formation and other application that require selective Ge film formation with low thermal budget. The mechanism of selectivity enhancement by the first SiGe layer as well as its influence on crystalline quality of the Si0.5Ge0.5 buffer layer and Ge epitaxial layer above will be discussed in the presentation.
Influence of Temperature on Boron Concentration in SiGe-B Epitaxy
Authors: Zhou Yiyang , Reindhardt James A. , Martin Glen E. , Dominguez Selene D. , Carey Raymond D.
Published: November 2006

SiGe-B source/drain (S/D) epitaxy is successfully used in mass production of high performance CMOS device (1-2). Due to the difference in free energy across the SiGe-B/substrate interface, there is boron segregation at the interface (3-4). In addition, low level of contamination also contributes to the pile-up of boron at the interface (5). In PMOS device manufacturing, the excessive boron will diffuse into the channel region in the high temperature processes after EPI S/D, which adversely affects device performance (5). In this paper, influence of temperature on boron concentration in the bulk and at the interface is reported.
Very High Temperature Growth of SiGe Virtual Substrates (15% < [Ge] < 45%)
Authors: Hartmann Jean-Michel , Baud L. , Rolland Guy , Fabbri J. M. , Billon Thierry
Published: November 2006

We have studied at 20 Torr the very high temperature (i.e.850ºC to 1100ºC) growth kinetics of SiGe in Reduced Pressure-Chemical Vapour Deposition. The growth chemistry adopted was heavily chlorinated, i.e. SiH2Cl2 + GeH4 + HCl, in order to avoid any significant chamber quartz wall coating (and thus flaking) during the deposition of thick layers. We are mostly in a high temperature, supply limited regime, with a small increase of the SiGe growth rate as the GeH4 mass flow and/or the growth temperature increases. By contrast, the Ge concentration decreases for given precursor mass flows as the growth temperature increases. Its dependence on the F(GeH4)/F(SiH2Cl2)+F (GeH4) mass flow ratio, almost linear at 850ºC and 900ºC, gets parabolic for higher growth temperatures. We have used those datapoints to grow linearly graded (~9%Ge/m) SiGe Virtual Substrates(VS) with final Ge concentrations in the 15% to 45% range.
Precise Analysis of Si/Graded-Si1-xGex/Si1-xGex Heterostructure Films Grown by Reduced Pressure Chemical Vapor Deposition Using Spectroscopic Ellipsometry
Authors: Shim Kyu-Hwan , Seo J.J. , Choi S.S. , Yang H.D , Kim J.Y. , Yang J.W. , Han T.H. , Cho D.H.
Published: November 2006

Si/graded-Si1-xGex/Si1-xGexheterostructures were grown by reduced pressure chemical vapor deposition on Si (100)&(111) substrates at different temperatures, and their structural properties were investigated using spectroscopic ellipsmetry and secondary ion mass spectroscopy. The variation of growth temperature was observed to alter each part of Si/graded-Si1- xGex/Si1-xGexheterostructure growth, and the changes could be clearly addressed according to the evolutions of ellipsometry spectra. As an in line monitoring tool, the spectroscopic ellipsometry presented excellent capability of accuracy ranging ± 1.2ºC in substrate temperature and correspondingly <5% in current gain for heterojunction bipolar transistor with the Si/graded-Si1-xGex/Si1-xGex base epi layers.
Unique Temperature Dependence on the Morphological Evolution of Ge on Si(100)
Authors: Alguno Arnold C. , Usami Noritaka , Nose Yoshitaro , Nakajima Kazuo
Published: November 2006

The Ge/Si system has been receiving much attention for both fundamental studies and device applications. It is a good model for understanding the basic physics for heteroepitaxy of lattice-mismatched semiconductors since Ge has a lattice constant of about 4.2% larger than that of Si. The presence of Ge in the Si lattice introduces stress, which has dramatic effects on the film growth. During the deposition of Ge on Si, small change in growth temperature will have big impact on the surface morphology and subsequently affect the optical properties of the system. The mechanism of this surface morphology evolution with respect to growth temperature is not well understood. In this study, we try to explain the surface morphology evolution of Ge on Si by intentionally introduce interdiffusion into the system by changing the growth temperatures in order to modify the total free energy that controls the energetics of surface morphology.
Development of Textured High-Quality Si and SiGe Multicrystal Ingots with Same Grain Orientation and Large Grain Sizes by the New Dendritic Casting Method
Authors: Nakajima Kazuo , Fujiwara Kozo , Tokairin Masatoshi , Pan Wugen , Nose Yoshitaro , Usami Noritaka
Published: November 2006

We have developed the dendrite casting method based on our new concept to control the grain orientation and grain size. The Si and SiGe multicrystal ingots grown by this method have same grain orientation and quite large grain sizes (≥3cm), and have the longer lifetime more than 35μs without hydrogen passivation. The conversion efficiency of the solar cell prepared by the Si multicrystal with same orientation was found to be improved compared with that based on the conventional Si multicrystal. Therefore, this dendritic casting method is very promising in the field of the Si and SiGe multicrystal solar cells.
Characteristic Influence of DC Bias on SiGe HBT Linearity and Power Gain under Different Operation Configurations
Authors: Qin Guoxuan , Wang Guogong , Ma Zhenqiang
Published: November 2006

The characteristic bias dependence of SiGe HBT linearity and power gain under both common-emitter and common-base configurations is experimentally studied and verified with simulations. Higher power-gain and better linearity can be obtained from the CB than CE configuration.
Modeling of Lossy MOS Capacitors on Ge-Rich Si0.15Ge0.85 Substrates
Authors: Bera Milan K. , Das Ratan , Chakraborty Sandipan , Saha Satyajit , Maiti Chinmay K.
Published: November 2006

A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) characteristics in lossy gate dielectrics formed by rapid thermal oxidation of Ge-rich Si0.15Ge0.85 in dry O2 ambient is presented. An equivalent circuit model approach to MOS capacitance modeling is proposed.
Suppression of Structural Imperfection in Strained Si Thin Film by Utilizing SiGe Bulk Substrate
Authors: Usami Noritaka , Nose Yoshitaro , Fujiwara Kozo , Nakajima Kazuo
Published: November 2006

We demonstrate suppression of structural imperfection in strained Si by utilizing homemade SiGe bulk crystal as a substrate. X-ray reciprocal space mapping clarified that the growth of a Si thin film on a SiGe bulk substrate leads to reduction in the orientation fluctuation compared with that on a SiGe virtual substrate. Furthermore, analysis of Raman spectra revealed dramatic decrease of the strain fluctuation in the strained Si film on the SiGe bulk substrate. These results suggest that the SiGe bulk crystal can be utilized as a substrate for various strain-controlled heterostructures for fundamental studies as well as improvement of device performance.
Comparison of SiGe Virtual Substrates for the Fabrication of Strained Silicon-on-Insulator (sSOI) Using Wafer Bonding and Layer Transfer
Authors: Reiche Manfred , Radu Ionut , Himcinschi Cameliu , Singh Rajendra , Christiansen Silke , Goesele Ulrich
Published: November 2006

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 - 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers proved that strained silicon layers are completely transferred if designed PE-CVD oxide layers were used. For both types of virtual substrates the oxide layers are deposited on top of the strained silicon and bonded to non-oxidized (blank) silicon wafers. A perfect layers transfer is obtained for virtual substrates having thick SiGe buffer layers (type A) even at 350ºC, while annealing at 450ºC is required for substrates with thin SiGe buffer layers (type B). The lower annealing temperature for substrates of type A is caused by the lower activation energy for blistering. The hydrogen implantation is here into the SiGe. For type B substrates the hydrogen implantation is into the underlying Si requiring a higher temperature for layer splitting (higher activation energy for Si).
Defect and Strain Characterization of Selective-Area-Growth Ge Mesa Structures on Si Substrate
Authors: Lu Jinggang , Rozgonyi George , Liu Jifeng , Kimerling Lionel, K , Michel Jurgen
Published: November 2006

Ge Mesas ranging from 30x30 to 2.5x2.5 µm were prepared by ultrahigh vacuum CVD and characterized by preferential defect etching, HR-TEM, XRD, and convergent beam electron diffraction (CBED). It was found that the threading dislocation density decreased from higher than 1 x 108 cm-2 for the as-grown Ge mesas to ~3 x 107 cm-2 for the annealed ones. Misfit dislocations at the Ge/Si interface are found to be predominantly 600 perfect dislocations. XRD showed that Ge mesas are tensile strained. It was found that the strain level decreases with decreasing mesa sizes, suggesting elastic strain accommodation by mesa sidewalls. Spatial resolved CBED measurements confirmed that the strain variation across the mesa depth was below 0.0005, which is consistent with the HRTEM observation that most of misfit dislocations are confined at the Ge/Si interface.
Self-Aligned SiGe HBT Based on Combined Dry and Wet Etching
Authors: Liu Daoguang , Xu Shiliu , Hao Yue , Xu Jun , Qian P , Liu Z , Hu G , Zhang J , Zhang Z. , Liu R , Liu L , Li R , He K , Liu Y , Chen G , König U , Kibbel H , Gruhle A , Seiler U , Li K
Published: November 2006

In this paper, a self-aligned SiGe/Si HBT has been fabricated based on dry/wet etching, where Si and SiGe materials were etched by KOH (potassium hydroxide) solution and SF6(sulfur hexafluoride). It is a key technology to control the etch of ultra-thin Si and SiGe film. When N+/N silicon in emitter region is etched, the length of etch time is critical. Despite a small lateral etch, dry etching doesn't benefit the realization of self-alignment process, nor benefit improvement of yield and fmax. In this paper, based on the chemical properties of silicon and germanium, dry and wet etches were properly combined to etch silicon and silicon germanium. First, N+/N Si outside emitter was etched with intentional lateral etch using KOH solution. Then, SiGe was etched by SF6. Finally, SiGe HBT with self-alignment of emitter to base has been developed. The measured results are: cutoff frequency fT=103GHz, maximum oscillation frequency fmax=124GHz.
Manufacturing Control and Optimization of SiGe(C) HBT Epitaxial Growth
Authors: Zhang Nancy , Tan Poh Cheng , Rodriquez Angel , Prando Greg , Nguyen Chinh , Sinn Craig , Fung Min Su , Safran Laura , Lehman Gerold (Jerry) , Gausepohl Steve , Mase Jerry , Bell Nancy
Published: November 2006

Reduced pressure (RP) epitaxial (EPI) growth is the core of state-of-the-art Silicon-Germanium-Carbon (SiGe:C) heterojunction bipolar transistors (HBT) construction. In- line control of large volume production is a continuing task for wafer Fabs. A special technique of monitoring product wafers has been developed for use in both process and tool control. The cost of additional operations and wafers can therefore be minimized. The NPN collector current was used as the device variability measurement during this SiGe:C EPI process optimization study.
2D-TCAD Process Calibration for a High Speed QSA SiGe:C HBT Verified with SSRM
Authors: Sibaja-Hernandez Arturo , Eyben Pierre , Van Huylenbroeck Stefaan , Vanhaeren Danielle , Vandervorst Wilfried , Decoutere Stefaan , Maes Herman
Published: November 2006

In this work, a 2D-TCAD process simulation platform for high speed bipolar HBT devices with ƒT/ƒmax values exceeding 200GHz is presented. The process simulations implement a consistent model describing the diffusion behavior of boron and carbon in silicon and silicon germanium. In particular, the model successfully accounts for coupled diffusion of carbon and silicon point defects under several RTA conditions. The Kick-Out and Frank-Turnbull reactions model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations. It is shown that 2D-TCAD process simulations, calibrated with SIMS and TEM pictures, can be successfully complemented with the use of SSRM measurements, which provide emitter-base and collector- base junction delineation and two-dimensional carrier distributions. An excellent agreement in vertical and lateral electrical junction depths between SSRM measurements and the 2D-TCAD simulations validates the 2D process calibration.
Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement
Authors: Cayrefourcq Ian , Boussagol Alice , Celler G.
Published: November 2006

In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with process-induced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm.
Strain Degradation in Strained-Si Layers Far Thicker than the Critical Thickness Grown on Relaxed Si0.65Ge0.35 Layers
Authors: Kang Suk June , Yuk Hyung-Sang , Kim In-Kyum , Lee Jea-Chun , Lee Sang-Hyun , Shim Jung-Jin , Lee Bo-Young , Fiorenza J. G. , Curtin M. , Lochtefeld Anthony
Published: November 2006

We have investigated for the first time the thickness effect of strained-Si layers grown on relaxed Si0.65Ge0.35 layers for power MOSFET applications. It was found that 98% of the strain compared to theoretical value was still maintained up to 100nm but the value was decreased to 70% at 150nm and 44% at 300nm. We have also presented the mechanism of dislocation generation caused by an increase in the strained-Si layer thickness and how it degrades the strain, surface roughness, and wafer curvature.
Selective Epitaxy of Si/SiGe to Improve pMOS Devices by Recessed Source/Drain and/or Buried SiGe Channels
Authors: Loo Roger , Verheyen Peter , Rooyackers Rita , Walczyk Christian , Leys Frederik , Shamiryan Denis , Absil Philip , Delande Tinne , Moussa Alain , Weijtmans Hans , Wise Rick , Machkaoutsan Vladimir , Arena Chantal , McCormack John , Passefort Sophie , Sorada Haruyuki , Inoue Akira , Lee Byeong Chan , Hyun Sangjin , Jakschik Stefan , Caymax Matty R. , Eneman Geert , Bender Hugo , Drijbooms Chris , Geenen Luc , Tomasini Pierre , Godny Stephane
Published: November 2006

Selective Epitaxial Growth of SiGe and/or Si-cap/SiGe heterostructures offer an elegant way to improve pMOS device performance. This paper discusses some important challenges and characteristics of the corresponding epi process. Loading effects are strongly reduced by choosing the growth conditions away from the mass transport regime, i.e. by reducing the growth pressure and/or increasing the gas velocity. Anomalous SiGe thickening at convex corners of recessed areas and the impact of the underlying SiGe on the growth behavior during Si- capping are discussed as well. The limits of the chemical and thermal budgets during pre-epi treatments as defined by the device concepts require some process optimization but are not a show stopper.
Ge and III/V as Enabling Materials for Future CMOS Technologies
Authors: Heyns Marc M. , Meuris Marc M. , Caymax Matty R.
Published: November 2006

Future CMOS technologies will require the use of substrate materials with a very high mobility in order to fulfill the performance requirements. It was show that Ge is an enabling material to introduce these new channel materials in a Si- compatible format. The first steps towards demonstrating the feasibility of an ultra high performance CMOS technology with Ge pMOS and III/V nMOS devices were shown. Good device performance was obtained on short channel Ge pMOS devices fabricated in a Si-like flow. The selective growth of GaAs on Ge was demonstrated. This work also opens the path into introducing added functionality to CMOS circuits by incorporating more advanced III/V material stacks that can be used for optical components or other applications, making this into a daring approach to further performance enhancements in future generation technologies.
Low Temperature Surface Nitridation Processes for Dielectric-Ge Interfaces
Authors: Wadsworth Haydn J. , Bhattacharya Sekhar , Ruddell Fred , McNeill D. W. , Mitchell Neil , Armstrong Mervyn , Gamble Harold S , Denvir Donal
Published: November 2006

Germanium MOS capacitors have been fabricated with a high-κ HfO2 dielectric using ALD. An in-situ low temperature (250ºC) nitrogen plasma treatment on the germanium surface prior to the deposition of HfO2 was found to be beneficial to the electrical properties of the devices. Germanium MOS capacitors have also been fabricated with a SiO2 dielectric deposited by an atmospheric pressure CVD 'silox' process. The same low temperature plasma nitridation was found to degrade the electrical properties of the silox devices. The effect of a post-metal anneal in H2 and N2 on both types of capacitor structure was also found to degrade device electrical properties.
Effects of Interfacial Layers Formed by Plasma Oxidation and Nitridation on HfO2/Ge-MIS Properties
Authors: Maeda Tatsuro , Morita Yukinori , Nisizawa Masayasu , Takagi Shin-Ichi
Published: November 2006

We report successful fabrication of oxide and nitride interfacial layers on Ge substrates by means of low-temperature plasma processing on Ge substrate. A transmission electron microscope observation revealed that the obtained interfacial layers are atomically smooth. The interface trap density (Dit) was measured for Au/HfO2/Ge metal/insulator/ semiconductor (MIS) structures with oxide and nitride interfacial layers by the ac conductance method. It is found that a minimum Dit value of 1.0×1011 cm-2•eV-1 is obtained for the oxide samples after forming gas annealing (FGA) at 400ºC. Significant improvements by FGA on the electrical properties of the samples with nitride interfacial layers, including the reduction of Dit from 1.8×1012 to 1.5×1011cm-2•eV-1, are also demonstrated.
Epitaxial Growth of Heterovalent GaAs/Ge and Applications in III-V Monolithic Integration on Si Substrates
Authors: Fitzgerald Eugene , Dohrman Carl L. , Chilukuri Kamesh , Mori Michael J.
Published: November 2006

We review past and present work regarding epitaxial growth of GaAs on Ge surfaces. Early work in molecular beam epitaxy showed that substrate off-cut was a critical factor, although later work with gas-source molecular beam epitaxy and chemical vapor deposition revealed that interface initiation equally controlled GaAs epitaxial layer quality. Using SiGe buffer layers to produce Ge on Si, and GaAs/Ge interfaces with optimal epitaxial control, various minority carrier devices have been fabricated over the past 5 years. To allow the co- habitation of such devices with silicon CMOS in a true monolithic technology, a new substrate platform has been created to allow for the integration of these III-V devices within a Si CMOS fabrication environment.
Some Insights into the Relaxation Mechanisms of Germanium Growing on (001) Si by Ultrahigh Vacuum Chemical Vapor Deposition
Authors: Bouchier Daniel , Yam Vy , Halbwax Mathieu , Nguyen Lam , Debarre Dominique , Fossard Frédéric
Published: November 2006

Recent developments in the control by UHVCVD of relaxation mechanisms are reported and discussed. Considering the elastic domain, it is shown that the nucleation of Ge QDs can be accurately driven in order to form isolated single dots or regular arrays of dots, as a consequence of an additional relaxation effect at Si mesas edges. The plastic relaxation can be drastically favored at low deposition temperature : it was found to proceed during the deposition of the first two monolayers at 330ºC. The morphology of the corresponding Ge films becomes stable above a critical thickness value lying just below 27 nm. A further re-growth at 600ºC leads to a low disorder level and a low roughness, while the misfit dislocations are located at the very Ge-Si interface. At last, the growth of Ge on oxidized Si is shown as a promising alternative for growing Ge films free of misfit dislocations.
Selective Epitaxial Growth of GaAs on Ge Substrates with a SiO2 Pattern
Authors: Brammertz Guy , Caymax Matty R. , Mols Yves , Degroote Stefan , Leys Maarten , Van Steenbergen Jan , Winderickx Gillis , Borghs Gustaaf , Meuris Marc M.
Published: November 2006

We have selectively grown thin epitaxial GaAs films on Ge substrates with the aid of a 200 nm thin SiO2 mask layer. The selectively grown structures have lateral sizes ranging from 1 μm width up to large areas of 1 by 1 mm2. The growth is fully selective, thanks to an optimized growth procedure, consisting of a 13 nm thin nucleation layer grown at high pressure, followed by low pressure growth of GaAs. This growth procedure inhibits the nucleation of GaAs on the mask area and is a good compromise between reduction of loading effects and inhibition of anti phase domain growth in the GaAs. Nevertheless, both microscopic and macroscopic loading effects can still be observed on x-section SEM images and profilometer measurements. X-ray diffraction and low temperature photoluminescence measurements demonstrate the good microscopic characteristics of the selectively grown GaAs.
Diode Analysis of Electrically Active Defects in Recessed SiGe Source/Drain Diodes
Authors: Simoen Eddy R. , Bargallo Gonzalez Mireia , Eneman Geert , Verheyen Peter , Claeys C. L. , Benedetti Antonio , Bender Hugo , De Meyer Krtistien , Schreutelkamp Robert , Washington Lori , Nouri Faran
Published: November 2006

In this paper, the impact of several processing parameters, like the etch depth and elevation of the epitaxial Si0.8Ge0.2 layer on the current-voltage (I-V) characteristics of recessed Source/Drain p+-n junctions is studied. It is shown that the area leakage current density is a strong function of the position of the junction with respect to the SiGe/Si interface. The highest area leakage current density is found for the heterojunctions, which can be explained by the presence of extended defects, generating excess carriers in the depletion region in the silicon substrate. The corresponding perimeter leakage current density is also highest for the highest etch depths. In addition, for some splits an empirical exponential dependence on the total epi layer thickness has been observed.
High Mobility Strained Ge / SiGe PMOSFETs for High Performance CMOS
Authors: Shang Huiling , Chu Jack O. , Bedell Stephen W. , Ott John
Published: November 2006

Dramatic hole mobility enhancement of 4-25X has been demonstrated in compressively strained Ge p-channel MOSFETs - the highest mobility enhancement for hole carriers among all available options. This paper reviews the material properties of strained Ge/SiGe and the integration challenges of strained Ge MOSFETs. A compatible process to incorporate high performance strained Ge PMOSFETs into standard CMOS technology is presented.
High Performance, Ultra-thin, Strained-Ge, Heterostructure FETs With High Mobility And Low Leakage
Authors: Krishnamohan Tejas , Kim Donghyun , Nishi Yoshio , Saraswat Krishna , Jungemann Christoph
Published: November 2006

High mobility channel materials are very promising for enhanced transport in future nanoscale MOSFETs. However, because of their reduced bandgap, large Band-To-Band Tunneling (BTBT) leakage currents can ultimately limit the scalability of FETs incorporating high mobility (small bandgap) channels. For the first time, the tradeoffs between drive current (ION), intrinsic delay (τ), band-to-band tunneling (BTBT) leakage and short channel effects (SCE) have been systematically compared in futuristic high mobility materials, like strained-Si, strained-SiGe and relaxed-Ge. The optimal channel materials and device structures for nanoscale p-MOSFETs are discussed through detailed BTBT (including band structure and quantum effects), Full-Band Monte-Carlo, 1-D Poisson-Schrodinger simulations. We present a novel, Heterostructure FET, which can significantly reduce the off-state leakage currents, while retaining its high mobility, making it suitable for scaling into the sub-20nm regime. Through detailed experiments, we examine the enhanced transport and low leakage in ultra-thin, strained-Ge, heterostructure MOSFETs on bulk-Si and UT-SOI.
The Combination of Embedded Si1-xGex S/D and Metal Gate Options for High Performance pMOS Transistors
Authors: Verheyen Peter , Severi Simone , Eneman Geert , Loo Roger , Shamiryan Denis , Rooyackers Rita , Demand Marc , Veloso Anabela , Lauwers Anne , De Meyer Krtistien , Absil Philip , Jurczak Malgorzata , Biesemans Serge
Published: November 2006

Using strain to boost transistor performance and the use of metal gate electrodes are both considered to be key enablers for further improvements in device performance. This paper discusses the combination of Si1-xGex S/D, used as a pMOS stressor, with two metal gate options: inserted metal gates and FUSI
Sidewall Dislocations in Embedded SiGe Source/Drain Areas of MOSFETs and Their Impact on the Device Performance
Authors: Kammler Thorsten , Peidous Igor , Wei Andy , Reichel Carsten , Heinemann Stefan , Romero Karla , Engelmann Hans-Juergen
Published: November 2006

Strain-engineered PMOS devices have been characterized by physical and electrical analysis, and computer modeling. Characteristic defects at the sidewall of embedded SiGe were found to degrade transistor performance. This could be attributed to carrier scattering rather than stress relaxation.
Effectiveness of Embedded-SiGe in Strained-SOI Substrates and Implications on Embedded-SiGe Stress Transfer Mechanics
Authors: Wei Andy , Kammler Thorsten , Cayrefourcq Ian , Höntschel J. , Mowry A. , Bierstedt H. , Hellmich A. , Hempel K. , Rinderknecht J. , Trui B. , Otterbach R. , Horstmann M. , Metral F. , Kennard Mark , Guiot Eric
Published: November 2006

Embedded-SiGe is shown to be fully compatible with strained-SOI substrates. Despite a lack of lateral lattice mismatch between the SiGe and strained-SOI, the resulting drive current improvement from embedded-SiGe is identical for strained-SOI and standard SOI control (where a lateral lattice mismatch is present). This result isolates the vertical lattice mismatch as the source of stress generation from embedded-SiGe. The concept of a critical length of SiGe beyond the vertical Si-SiGe interface is introduced to explain the observed experimental results, and is confirmed by various SiGe epitaxial fill-height and stress relaxation experiments.
Germanium Photodetectors for Photonics on CMOS
Authors: Fedeli Jean-Marc , Damlencourt Jean-François , El Melhaoui Loubna , Le Cunff Yves , Mazzochi Vincent , Vivien Laurent , Marris Morini Delphine , Rouvière Mathieu , Pascal Daniel , Le Roux Xavier , Cassan Eric , Laval Suzanne , Grosse P. , Poncet S.
Published: November 2006

Different technologies for the fabrication of Germanium photodetectors were developed. Germanium was grown by RPCVD in a silicon cavity in order to provide a direct coupling with a rib silicon waveguide. With direct deposition of Ti/TiN/AlCu on Ge, Metal-Schotkky-Metal (MSM) diodes were formed. PIN photodiode were fabricated either with in-situ doping during RP- CVD epitaxy of Ge, either by ion implantation. For vertical PIN photodiode, the germanium was successfully etched either in mesa either anisotropically with Cl2 gazes. Small footprint Ge photodiodes can lead to high speed operation on CMOS
Prospects and Critical Issues on Ge MOS Technologies
Authors: Takagi Shin-Ichi , Taoka Noriyuki , Nakaharai Shu , Ikeda Keiji , Tezuka Tsutomu , Yamashita Yoshimi , Moriyama Yoshihiko , Maeda Tatsuro , Sugiyama Naoharu
Published: November 2006

Ge channel MOSFETs have recently stirred a strong interest as a promising candidate for high speed MOSFETs beyond strained- Si channels. It has been well recognized, however, that there exist a variety of issues to be solved for realizing Ge MOS technologies. Major critical issues include (1) Gate insulator formation with high quality MIS interfaces (2) High quality GOI or Ge substrate formation (3) Formation of low resistivity S/D junctions (4) CMOS structures and integration. In this paper, these technological problems are addressed and possible solutions for these technological challenges are presented on a basis of our recent research progress.
Advanced Applications of Semiconductor Epitaxy for Cutting Edge Integrated Circuit Technolgy
Authors: Sadana Devendra , Yang Min , Bedell Stephen W. , Reznicek A , de Souza Joel P. , Hovel Harold J.
Published: November 2006

Advanced applications of epitaxy in enabling future CMOS scaling are discussed. Novel processes to create substrates for hybrid oriented technology (HOT), superHOT and single wafer sSOI are described.
Development of High-Throughput Batch-Type Epitaxial Reactor
Authors: Kunii Yasuo , Inokuchi Yasuhiro , Wang Jie , Yamamoto Katsuhiko , Moriya Atsushi Moriya , Hashiba Yoshiaki , Kurokawa Harushige Kurokawa , Murota J.
Published: November 2006

Si/SiGe selective epitaxial growth is becoming a critical process step for ULSI fabrication on 65nm and beyond technologies with need for elevated source-drain or strained Si channel to enhance device performance. This paper reviews recent efforts to improve batch-type epitaxial reactors for high-volume device fabrication and shows recent progress in low-temperature Si/SiGe selective epi process.
A Study on B Atomic Layer Formation for B-Doped Si1-xGex(100) Epitaxial Growth Using Ultraclean LPCVD System
Authors: Ishibashi Kiyohisa , Sakuraba Masao , Murota J. , Inokuchi Yasuhiro , Kunii Yasuo , Kurokawa Harushige Kurokawa
Published: November 2006

B atomic layer formation on Si1-xGex(100) (x=0, 0.3, 1) using BCl3 gas has been investigated by ultraclean low-pressure chemical vapor deposition. At 450ºC, in the case using BCl3-He-H2 gas mixture, B amount tends to increase beyond one atomic layer (6.8x1014 cm-2) with increasing BCl3 exposure time on Si0.7Ge0.3(100) and Ge(100). On the other hand, in the case using BCl3-He-Ar mixture gas, 1/3-1/2 atomic layer (2.3x1014 cm-2) formation is achieved self-limitedly with high Cl coverage on the surface. The Cl atoms on the B adsorbed Si1-xGex(100) are effectively removed by H2 introduction at 450ºC after BCl3exposure. In this way, atomically-controlled B atomic layer formation on Si1-xGex/Si(100) was demonstrated by using the self-limited surface reaction of BCl3 at 450ºC.
Issues and Opportunities for Complementary SiGe HBT Technology
Authors: Cressler J. D.
Published: November 2006

This paper reviews the prospects of using complementary SiGe HBTs (npn + pnp transistors) to enhance the capabilities of current npn-only SiGe technology platforms. After an introduction, we discuss device design approaches and optimization, point out device and fabrication challenges, introduce technology solutions presently in existence, and project forward to potential applications of complementary SiGe technology.
A 20 GSample/s, 40 mW SiGe HBT Comparator for Ultra-High-Speed ADC
Authors: Borokhovych Yevgen , Gustat Hans
Published: November 2006

This paper presents a high-speed master-slave comparator in an ECL configuration. Implemented in 190 GHz SiGe HBT technology, the comparator occupies 0.7 x 0.7 mm2, including bondpads. The comparator can operate at a speed up to 20 GSample/s with a resolution of 7.2 bits per 1.2 Vp-p input. The low power consumption of the comparator itself (40 mW) and its small core area of 190 x 35 um2 make it suitable for medium resolution full-flash A/D converters and other low-power comparator applications.
Influence of Strained Si1-yGey Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0
Authors: Ni Chleirigh Cait , Olubuyide Oluwamuyiwa , Hoyt Judy L.
Published: November 2006

Hole mobility enhancements of 5 to 8X are demonstrated in heterostructure p-MOSFETs for strained Si1-yGey fractions, y ranging from 0.8 to 1. The influence of SiGe film thickness on hole mobility for strained Si0.3Ge0.7-channel p-MOSFETs is also investigated. Mobility is found to decrease significantly for channel thicknesses below 7 nm. Off-state leakage increases exponentially with increasing Ge concentration in the channel. Temperature dependent measurements of the leakage are consistent with trap-assisted tunneling at low drain-to-gate bias, and with band-to-band tunneling at higher biases. A reduction in leakage is observed for SiGe channel layer thicknesses below 7 nm. The results presented in this work are relevant to modeling and optimization of the performance of high mobility, high Ge concentration strained heterostructure p-MOSFETS.
RF Modeling of Large Gate-Width Multi-Finger Si/SiGe Power MODFETs
Authors: Yuan Hao-Chih , Jiang Ningyue , Croke Edward , Ma Zhenqiang
Published: November 2006

N-type large gate-width modulation-doped field-effect transistors (MODFETs) are fabricated on Si/SiGe modulation-doped heterostructure with fT and fmax of around 8 GHz and 20 GHz, respectively. These power devices demonstrate 15 to 16 dB power gain at 2 GHz, which make them suitable for low- and medium-power amplifiers for RF applications. We report here the RF modeling using small-signal equivalent circuit of these power devices. The extracted parameters are compared with prior work having similar gate length and the differences between this work and the previous one are discussed.
Parasitic Electrostatic Capacitances in Si/SiGe n-HFET
Authors: Enciso-Aguilar Mauro , Zerounian Nicolas , Hackbarth Thomas , Herzog Hans , Aniel Frederic
Published: November 2006

The influence of parasitic capacitance on high frequency performances of SiGe n-HFET is reported. These capacitances due to fringe effect and electrostatic contribution of the gate are extracted from HF measurement and estimated with a 2D hydrodynamic modeling of the device and with a 2D electrostatic modeling of the HFET. These capacitances lower the intrinsic transit frequency in between 30-38% for the samples reported here.
Analysis of Gate Leakage in Strained Si MOSFETs
Authors: Yan Liang , Olsen Sarah H. , Kanoun Mehdi , Al-Araimi Mohammed , Agaiby Rimoon , Dalapati Goutam , O'Neill Anthony
Published: November 2006

This work investigates gate leakage mechanisms in advanced strained Si/SiGe MOSFET devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure and device processing on gate oxide leakage characteristics are analysed in detail. We show that at high oxide electric fields where gate leakage is dominated by F-N tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. However for device operating regimes at lower oxide electric fields Poole-Frenkel (P-F) emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Consequently advanced strained Si/SiGe devices are inadvertently subject to a potential trade-off between power consumption (gate leakage current) and device reliability (gate oxide interface quality).
The Challenges of Ge-Condensation Technique
Authors: Terzieva Valentina , Caymax Matty R. , Souriau Laurent , Meuris Marc M. , Clemente Francesca , Benedetti Alessandro
Published: November 2006

Ultra-thin SiGe films on insulator with high Ge fraction were fabricated through Ge condensation. To achieve that strained Si0.75Ge0.25 layers were grown epitaxially on SOI wafers and oxidized in O2 at 1150ºC for various times. Raman measurements and X-TEM revealed the importance of purity of oxidation ambient for the oxidation process. Traces of moisture in the oxygen flux accelerate the process causing a switch from dry to wet oxidation mechanism, leading to complete oxidation of the starting layer in only 1 hour. The crystal quality and overall uniformity of such layers however is poor. The use of 100% dry oxygen provides the necessary control over the oxidation process. This allowed relaxed SiGe layers with concentration of Ge up to 45% and higher to be obtained. X-TEM indicated good crystalline quality and uniform layers with no threading dislocations or other defects introduced during oxidation.
Oxidation Saturation of SiGe Alloy on Silicon-on-Insulator Wafers
Authors: Shimura Takayoshi , Shimizu Michihiro , Horiuchi Shinichirou , Watanabe Heiji , Yasutake Kiyoshi
Published: November 2006

Oxidation saturation of SiGe alloy on silicon-on-insulator wafers was investigated. Oxidation saturates after a few hours for the Si1-xGex (x=0.068-0.156) layers. For higher initial Ge concentrations of the SiGe layer, the oxidation saturated in a shorter oxidation time. We propose a model for oxidation saturation, in which the oxidation saturation is governed by an interfacial melting layer that has high Ge concentration.
Nucleation and Movement of Dislocations during Relaxation of He Implanted SixGe1-x/Six Heterostructures
Authors: Luysberg Martina , Hueging Norbert , Buca Dan , Trinkaus Helmut , Mantl Siegfried
Published: November 2006

The fabrication of strain relaxed SixGe1-xbuffer layers is technologically of great importance, because biaxial, tensile strain can be achieved within a thin Si layer grown onto these SixGe1-x virtual substrates. Strain relaxation of the SixGe1-x layer can be accomplished by He implantation and subsequent annealing. In this paper we address the nucleation and movement of dislocations in He implanted SixGe1-x/Si heterostructures. By in-situ transmission electron microscopy we find clear evidence, that He precipitates formed during annealing act as internal dislocation sources and therefore promote the relaxation. This can be understood in view of the results of quantitative evaluation of the shear stress around He filled precipitates. Clearly, for some of the precipitates, the critical resolved shear stress for dislocation formation is exceeded at the edge of the platelets.
Dopant Diffusion in SiGeC Alloys
Authors: Rucker Holger , Heinemann Bernd , Kurps Rainer , Yamamoto Yuji
Published: November 2006

In this paper, we discuss the impact of germanium and carbon on the diffusion of common dopants in Si-based alloys. We review results of various diffusion experiments and discuss the basic physical mechanisms of the observed changes of diffusion coefficients as a function of alloy composition. Results of boron and phosphorus marker layer diffusion experiments are presented for binary Si1-xGex and Si1-yCy and ternary Si1-x-yGexCy alloys.
Thin Germanium-Carbon Layers on Silicon for MOS Applications
Authors: Kelly David Q. , Wiedmann Isaac , Garcia-Gutierrez Domingo I. , Jose-Yacaman Miguel , Banerjee Sanjay K.
Published: November 2006

We report the growth and materials characterization of thin (<35 nm) germanium-carbon alloy (GeC) layers grown directly on Si by ultra-high-vacuum chemical vapor deposition. We show that the presence of C atoms is limited to a thin interfacial region at the Si substrate, and interpret this result as a mechanism for strain relief. We also show that the GeC films exhibit remarkably low threading dislocation densities despite significant relaxation.
Study of Poly-SiGe Structural Properties for Modularly Integrated MEMS
Authors: Low Carrie W. , King Liu Tsu-Jae , Howe Roger T.
Published: November 2006

Approaches to improve the strain gradient of low-temperature- deposited LPCVD poly-SiGe for MEMS inertial sensor applications are investigated. Correlation between the strain gradient and film microstructure is found, and the effects of film deposition conditions on film microstructure are studied. Boron-doped poly-SiGe films generally have vertically oriented grains, either conical or columnar in shape. Films with small strain gradient usually have columnar grain structure with low defect density. The best strain gradient achieved is 1.1×10-6 µm-1 for a 3.5 µm thick film deposited at 410ºC, with a worst- case variation across a 150 mm-diameter wafer of 1.6×10-5 µm- 1. The uniformity of films deposited in a batch LPCVD reactor can be improved by increasing the deposited film thickness, using a proper seeding layer, and/or depositing the film in muliple layers. Post-deposition annealing and argon implantation can be used to tune the strain gradient so that lower strain gradient can be achieved with proper deposition and annealing/implantation combinations.
Silicon-Carbon Source/Drain: Selective Epitaxy, Process Integration, and Transistor Strain Engineering
Authors: Yeo Yee-Chia
Published: November 2006

We examine the technology options for the enhancement of electron mobility in n-channel metal-oxide-semiconductor field-effect transistors, focusing on channel strain engineering using lattice-mismatched source/drain (S/D) materials. Silicon-carbon (Si1-yCy) S/D induces lateral tensile strain in the Si channel for electron mobility and drive current improvement. This has been demonstrated on bulk planar transistors, silicon-on-insulator transistors, and multiple-gate transistors. Further performance enhancement is achieved by the combination of multiple-stressors, e.g. Si1-yCy S/D and silicon nitride liner stressor. Process integration issues and strain enhancement approaches are discussed.
Power Output Improvement of Silicon-Germanium Thermoelectric Generators
Authors: Wagner Martin , Span Gerhard , Holzer Stefan , Triebl Oliver , Grasser Tibor , Palankovski Vassil
Published: November 2006

We present a technology for thermoelectric generators using large area pn-junctions. Thermally generated carriers are separated by the gradient of the built-in potential caused by the pn-junction. The use of these structures for waste heat recovery implies an externally applied temperature gradient in-plane with the pn-junction which causes a current of both electrons and holes from the heated to the cooled side, where electrical contacts are mounted. The device behavior is strongly influenced by the magnitude and the spatial distribution of the generation rate as well as the local transport properties. We present the influence of the alloy composition on the material properties and possibilities to increase the power output by modification of the local material composition. Furthermore, the influence of intentionally implanted gold atoms as additional generation centers is assessed. We present simulation results obtained by the device simulator Minimos-NT working in conjunction with the optimization framework Siesta.
SiGe and Ge Cryogenic Power Transistors
Authors: Ward Rufus R. , Dawson William , Zhu Lijun , Kirschman Randall , Niu Guofu , Nelms Mark , Mueller Otward , Hennessy Michael , Mueller Eduard , Patterson Richard , Dickman John , Hammoud Ahmad
Published: November 2006

We have undertaken development of power semiconductor devices based on SiGe and Ge, intended for operation over a wide temperature range, from room temperature down to deep cryogenic temperatures, ~30 K (~ -240{degree sign}C). We summarize results for Ge diodes (~10 A/400 V), Ge junction field-effect transistors (Ge JFETs, ~0.5 A/30 V), Ge metal-insulator field-effect transistors (Ge MIS-FETs ~1 A/20 V) and SiGe heterojunction bipolar transistors (SiGe HBTs, ~10 A/50 V). As a practical demonstration, we have used SiGe HBTs and SiGe diodes as the active devices in 100-W power-conversion circuits, operating from room temperature down to ~30 K (~ -240{degree sign}C) with increased efficiency as temperature de-creases. Our developments demonstrate the potential of alternative semiconductor materials to provide excellent performance for power applications down to deep cryogenic temperatures.
Catalyst Development Needs and Pathways for Automotive PEM Fuel Cells
Authors: Wagner Frederick T. , Gasteiger H. A. , Makharia Rohit , Neyerlin Kenneth C. , Thompson Eric L. , Yan Susan G.
Published: November 2006

Mass production of cost-competitive fuel cell vehicles will require oxygen reduction catalysts with 4 times the mass activity of current state-of-the-art platinum/carbon materials. The catalysts must maintain this high activity through the aggressive automotive duty cycle. Pt-alloy catalysts have to date given at least half the required activity gain, and the activity advantages of alloys vs. pure Pt are maintained in PEMFCs even under low-humidification conditions. Alloys show durability advantages, but sometimes- seen losses of specific activity must be understood. Consideration of the mechanisms whereby alloys enhance oxygen reduction activity has led to literature reports of several promising pathways to 4x Pt activity, primarily through control of catalyst particle surface structure and subsurface layer composition. A critical topic for upcoming research will be to determine whether activities enhanced by such structural control can be made durable against realistic drive cycles.
Preparation of Self-Standing Composite Electrolyte Membrane by Use of Three-Dimensionally Ordered Macroporous Silica Matrix
Authors: Sasajima Keiji , Munakata Hirokazu , Kanamura K.
Published: November 2006

Three kinds of sulfonated polymer electrolytes (PAMPS, SPEES, and SPI) have been synthesized and evaluated as filling polymers for a three-dimensionally ordered macroporous (3DOM) silica membrane. The 3DOM composite membrane exhibited excellently high dimensional stability regardless of the kind of filling polymers due to a suppression of polymer expansion by the hard silica matrix. Accordingly, a low methanol cross- over could be attained in the composite membrane with high proton conductivity.