bluuebunny/crossref_metadata_2025 huggingface dataset:
Printed Wiring Board Inner Layer Contamination Study
Authors: Chan A.S.L. , Shankoff T.A. , Culver D.
Published: February 2008

Electrical leakage beyond control levels did not occur in high temperature and humidity stressing of surface insulation resistance patterns when the relatively high contamination levels of 5 and 10 µg LiBr/cm were laminated into a simple test multilayer board structure. When sputtered layers of LiF, LiBr and NaCl were covered by a thin 0·002 in. lamination layer, generally similar results were obtained at 35°C/90% relative humidity and even at 85°C/85% relative humidity. Biasing of some samples at 85°C/85% relative humidity out to 400 hours did cause leakages which vary from one to three decades above the controls, but drifting with time beyond 96 hours towards a shorting condition, or to the level of unlaminated samples, on a leakage per square basis was not observed. Because the surface insulation resistance per square concept did not hold in these experiments, the surface leakage mechanism is apparently overridden by bulk leakages which occur in parallel in the laminations.
Propylene Glycol Ethers—An Alternative to CFC 113 for the Cleaning of Printed Circuit Boards
Authors: van Gerven J. , van Horssen L. , van Veen N.
Published: February 2008

The threat posed to the environment by CFC cleaning processes for printed circuit boards has led to an investigation of possible alternatives. In a preselection procedure, surprising results were obtained using propylene glycol ethers (PGE), solvents for the paint industry. In this study these ethers are compared with five other groups of cleaners, which can be divided into four water‐based classes: weak acid, neutral, weak and strong alkaline, and water miscible organic solvent cleaners which are non halogen‐containing and biodegradable. The cleaning power of PGE and other cleaners is tested on fluxes for wave and reflow soldering. Comparative results for the different groups are given, combined with surface insulation resistance measurements. Good results can be obtained using alkaline or solvent cleaners. However, it appears that the cleaning results depend heavily on the type of flux used and the choice of a matching cleaning process.
Practical Experimental Designs Applied to Haloing (Measling) on Teflon® Circuit Boards
Authors: McQuarrie W.G. , Voss F.
Published: February 2008

In the fast paced PCB industry of today windows of opportunity are short. One needs to be able to find quickly the key variables to a new process or an existing process so that the capability requirement can be met. Guesswork and traditional experimental design approaches will not work. Control charts by themselves will not work. Very large experimental studies will not work. What will work are simple, well defined, statistically designed experiments. This paper is an example of how simple, statistically based experiments were used to reduce haloing on Teflon® circuit boards. The drilling and plating processes using different laminate materials were investigated using Box‐Wilson and Plackett‐Burman experimental designs. Different data analysis techniques such as confidence intervals, scree plots, analysis of variance tables and analysis of means charts were used to determine the true significant (key) variables and the insignificant (non key) variables. An effective experimental study must have a capable measurement system. A method of determining the measurement system capability and improving it for haloing using isoplots is presented. In the end, two economically feasible paths to reduce the haloing problem were found.
Integration and Application of Vision Systems in SMD Automatic Placement Machines
Authors: Neger V. , Pawlischek H.
Published: February 2008

The mechanical design of the automatic placement machine and the integrated application of different tools dictate the result of the placement process. The placement accuracy of the system is a decisive factor for the quality and cost of the printed circuit board. Vision systems have become indispensable in today's SMD placement technology.
Waste Treatment Process for Electroless Copper
Authors: Holly J.D.
Published: February 2008

The spent electroless copper bath is deactivated at the overflow by the automatic addition of hydrogen peroxide (H2O2) to prevent copper from plating out in the drain lines, causing the lines to become blocked. Caustic (NaOH) and formaldehyde (HCHO) are then added to the deactivated electroless copper solution in a batch treatment process. Powdered aluminium or aluminium fines are added to precipitate out the copper as metallic copper. The copper concentration (<1 ppm) can be made stable for several days if necessary. The metallic copper is filtered out and salvaged. The mother liquor is neutralised (pH 6·5–9·0) and discharged. United States patent applied for, 07–345865.
Non‐ionic Water Soluble Flux Residue Detection by XPS
Authors: Hirt A. , Artaki I.
Published: February 2008

For many years the analysis of contaminant residues on PWB surfaces has been of major importance to the industry. While the identification of residues left on metallic surfaces has proven to be relatively straightforward, the analysis of organic contamination of similar composition to that of the underlying board surface has not been as successful. Through the use of modern XPS instrumentation, the non‐ionic component of water soluble flux has been identified and differentiated from the chemically similar FR‐4 and soldermask substrates. This paper presents the XPS results for a series of experiments aimed at determining the location and relative concentration of water soluble flux residues on standard surface insulation resistance (SIR) comb patterns. The data show that the water soluble flux residue is not present as a uniform coating on the board surface but appears in localised sites in high concentrations while being absent in other locations. Through more aggressive cleaning procedures the sites of high residue concentration can be significantly reduced.
Design Guidelines for Polymer Thick‐film Technology
Authors: Halbo L. , Nielsen C.W. , Nørlyng S.
Published: February 2008

The paper gives design guidelines for polymer thick‐film technology (PTF). After an introduction reviewing the main PTF properties, materials and processes, detailed PTF design rules are presented. They are conservative, to achieve high production yield. The design rules are based on the considerable experience in the companies of the authors and of the persons mentioned in the acknowledgements, as well as on information from the open literature and from materials suppliers. The design guidelines are intended primarily for designers, but they are also important for production personnel, to facilitate a close coupling between design and production, and thus provide optimum use of PTF and obtain high production yield.
Liquid Photoresist Techniques for Fine Pattern Flexible Printed Circuits
Authors: Kiyota S. , Koizumi T. , Kobayashi S.
Published: February 2008

This paper presents a new roll‐to‐roll (R‐R) production system modified for fine line patterning of flexible printed circuits (FPCs) using the subtractive method. The R‐R system is especially suited to production of FPCs because the material used—copper‐clad laminate (CCU—can be handled as it is rolled. Consideration has been given to methods and materials in designing the machines. They are now operating successfully and are used in single‐sided flexible circuit manufacture. A liquid photosensitive etch resist and a collimated light source are recommended for the system and several factors necessary for achieving R‐R working conditions are discussed. Judging from the experimental results of these systems, using narrower width materials with chemical surface preparation is an effective technique for improving the yield rate. The selection of a liquid photoresist is not so common in the case of rigid printed circuit boards because of the difficulty of the coating process. On the other hand, in the case of flexible PCBs, it is successful not only in terms of resolution characteristics but also of productivity under several different types of coating conditions. It should be noted that use of the conventional subtractive method in the printed circuit field is still advantageous as some semiconductor technologies are applicable.
Bow and Twist in the Printed Circuit Manufacturing Industry
Authors: Heywood D.
Published: February 2008

‘Bow and Twist’ is a phrase that is commonly used to cover all forms of non‐flat distortion in the PCB industry. The shape that distortions can assume are analysed and quantified; the size and shape of distortion are compared with the physical properties of the material that give rise to them. The special care needed in the manufacture of multilayer circuits is highlighted. The effects of more advanced material and of heatsinks are considered.
Influence of Direct Current Ripple on Metal Deposition
Authors: Pešić S.
Published: February 2008

This paper focuses on the quality of output current rectification—an important feature which should be taken into account alongside voltage and current. It is the author's intention to provide other authors and equipment manufacturers with the incentive to elaborate on this theme.
Special Report
Authors: Ellis B.N.
Published: February 2008

Pleasantly sited on the Inner Harbour, the Hyatt Regency Hotel was the venue for this year's conference. Baltimore was essentially an industrial city until some twenty or thirty years ago. The Inner Harbour area housed warehouses, power stations and such like and could have been described as all that was unpleasant that this description could evoke. By a bootlace‐pulling‐up‐exercise, the city fathers decided that they would rehabilitate this district, and they have succeeded in the way that only the Americans know how to. The most remarkable addition to the skyline is a fantastic combination of art and functional architecture, the National Aquarium of Baltimore. To borrow the expression from the Michelin Guide, it is ‘worth a detour’, and a long one at that.
The Thermal and Electrical Characterisation of PWB Test Vehicles Built with Low Dielectric Constant Materials
Authors: Blackshaw M.F. , Lee L.H. , Burt R.
Published: February 2008

The trend towards high speed digital processing has stimulated the need for new substrate materials with superior electrical properties for multilayer printed wiring board (PWB) applications. Two important electrical substrate parameters are dielectric constant and dissipation factor. This study examines the effect of combining different resin and fibre systems for altering or possibly improving electrical performance. Resin systems studied include FR‐4, cyanate ester and polytetrafluoroethylene. Materials used for reinforcement include E‐glass, S‐glass and polytetrafluoroethylene based fibres. Results of the electrical and thermal characterisation work on the test vehicles built based on the mixed resin and fibre systems are reported.
Investigation of Copper Deposition on Printed Circuit Boards Using Taguchi Methods
Authors: Halužan I. , Reichenbach D.
Published: February 2008

This study describes how the copper deposition rate and the degree of copper coverage in the holes on printed circuit boards were investigated. The composition of the chemical copper solution was varied, and consequently the deposition parameters were changed. By using Taguchi methods, the level of significance of the process parameters was determined.
Product Costing—An Essential Element for Success in Bare Board Manufacture
Authors: Robinson C.G.
Published: February 2008

In the fiercely competitive environment of printed circuit manufacturing, price undercutting has become the normal marketing tool. While selling prices are being influenced by the competition, much is still within the control of the supplier as long as a sound policy of product costing is adopted. A company that knows its product costs can concentrate on the most profitable product mix and avoid loss‐making activities.
Circuit Board Thermal Design or How to Succeed at the Impossible
Authors: Dean D.J.
Published: February 2008

This paper explains why the data with which thermal designers have to work is uncertain and incomplete. It then describes how accepting this uncertainty unlocks the shackles of accurate temperature prediction and gives the designer the freedom to tackle the different aspects of thermal design at an appropriate and simple level. The latter part of the paper concentrates on the thermal design of circuit boards, first for steady state and then for transient operation.
Polymer Thick Film Technology in Telecommunication Applications
Authors: Cavero J. , Rodriguez A.
Published: February 2008

This paper concisely describes polymer thick film technology used with printed circuit boards as an interesting means of achieving time and cost reduction. Telephone keypads and edge connectors manufactured with this technology and using two different processes are subjected to environmental and life tests in order to compare them with the traditional gold‐plated keypads and edge connectors used in the same applications.
Vertical Electrostatic Spraying of Photosensitive Resists
Authors: Hall A. , Hemming M.
Published: February 2008

With the growing demand for more complex PCBs with tighter tolerances, there is a need to improve the production capability of solder masks, together with etch and plating resists.
Fine Line Conductor Formation
Authors: Nakahara H.
Published: February 2008

Driven by the demand for higher density in electronic packaging, each signal plane of printed wiring board must accommodate more conductors. As a result, conductor width is becoming narrower each year. This chapter reviews some of the important steps of forming finer line conductors in printed wiring boards, such as surface preparation, plating/etching, photo‐exposure, automatic optical inspection, etc.
Productronica
Authors: Ellis Brian
Published: February 2008

Productronica, the 9th International Trade Fair for Electronics Production held in Munich from 12–16 November 1991, more than fulfilled the high expectations placed in this worldwide leading fair. Some 75,000 trade visitors from 61 countries spent an average of 1·7 days at the fair examining the clearly organised range of products and processes of 1,636 exhibitors and 268 additionally represented companies. Despite unfavourable economic conditions as well as increasingly tough competition from suppliers in North America and the Far East, the industry still conveyed an extremely optimistic atmosphere.
Inert IR Reflow: The Significance of Oxygen Concentration in the Atmosphere
Authors: Lea C.
Published: February 2008

The benefits of controlling the atmosphere in an infra‐red reflow oven are evident in improved soldering yields and easier post‐soldering cleaning of the assembly. The main benefits arise from reducing the oxygen partial pressure in the atmosphere at the time when the solder is molten. The most common inerting atmosphere used is nitrogen, and to reduce the oxygen concentration to 100 ppm is relatively straightforward, but below this level the equipment and the running costs increase with decreasing oxygen requirement. This paper gives data on the effects of reducing the oxygen level on a number of parameters relevant to high quality manufacture and product reliability. The aim is to identify which aspects of the soldering process are crucially sensitive to the oxygen concentration and which are not, in order to establish a good working compromise between oxygen level and the cost of its attainment.
Thermal Strain Response of Plated Holes
Authors: Gross T.S. , Watt D.W. , Raber R.S. , Perault J.A. , Zhang Y.
Published: February 2008

The failure of copper‐plated holes in dielectric laminates during thermal cycling is a serious problem for the electronics industry. The large difference in out‐of‐plane thermal expansion between the dielectric laminate and the copper plating can cause the copper plating to deform and fail as the board is thermally cycled. The purpose of this study was to demonstrate the feasibility of using electro‐optic holographic interferometry (EOHI) to measure deformation around plated holes and to evaluate methods for estimating the stress in the barrel plating. It was demonstrated that EOHI was more than adequate to resolve the out‐of‐plane thermally induced displacement field around an array of plated‐through holes. The displacement sensitivity was better than ±10 nm with high spatial resolution (92 ?m horizontally and 75 ?m vertically).The expansion was reasonably linear from 30°C to 120°C. The deformation around the individual holes was not axisymmetric. It is suggested that the method for estimating barrel stresses may be too sensitive to thickness and architecture variations in the pad for reliable stress estimates. An alternative scheme for estimation of barrel stresses based on thermal strain energy evaluation is described.
Performance Characterisation of VAX 9000 MCU Flexible Circuit Interconnect
Authors: Palmieri L.
Published: February 2008

A contact featured flexible circuit connector was designed to meet the high speed signal performance needs of the VAX 9000 Multi Chip Unit. With contact densities of 200 I/O over approximately 2 square inches, this connector has the highest contact density of any high performance signal connector in any DEC system. This paper discusses the use of a specially designed tester to characterise and measure connector performance against its design goals.
Modelling of Power and Ground Planes
Authors: Pedersen O. , Flaten B.‐E. , Gleditsch T.
Published: February 2008

A new model for the power system, covering resistance, self‐inductance, mutual inductance, and capacitive coupling between planes is presented. The model parameters are calculated from the geometry of the actual board. No measurements are necessary to set up a model for a new board. The model has been verified against detailed computer simulations and measured data.
PWB Interconnect Strategy Using a Full Build Electroless Copper Plating System:
Authors: Cisson J. , Seigo J. , Minten K.
Published: February 2008

This paper constitutes a follow‐up to earlier work published in Circuit World, Vol. 17, No. 4. The first paper studied the metallographic structures of two commercially available full build electroless copper foils. Part 2 reports the investigations carried out into the etching characteristics of these copper foils, chemically deposited from full build electroless copper baths designated high elongation (HE) and high strength (HS). It is shown that, although attention should be given to the choice of etchant for these copper foils, they do not exhibit an uncontrollable etch rate, as is often feared.
A User's Experience with a New Composite Solder Mask System
Authors: Penot J.M. , Tatsos P.
Published: February 2008

Alcatel's production plant at Coutances, on the coast of Normandy, is dedicated to the manufacture of printed circuit boards (PCBs) and has been producing printed circuits for more than 15 years. The factory has been extended twice, to meet increased demand, and now covers an area of more than 13,000 square metres.
PCIF News
Authors: Ross Bill , Morris Bob
Published: February 2008

The most important news at this moment is that the PCIF Annual Conference and Dinner will take place on 16–17 September 1992, at the Anugraha Conference Centre, Engelfield Green, Egham, Surrey. The Conference will open with a keynote address by John Budgen, Site Director, IBM Havant. We are very pleased to say that the President of the Board of Trade and Secretary of State for Trade and Industry, the Right Honourable Michael Heseltine, MP, will address the Federation members at the Annual Conference dinner.
Reliability of Surface Mount Electronics Assemblies Cleaned Using CFC‐113‐free Techniques
Authors: Ellis B.N.
Published: February 2008

This paper summarises briefly all the substitutive techniques for CFC‐113 and 1,1,1 ‐trichloroethane blend cleaning, including the use of ‘no‐clean’ and controlled atmosphere soldering, with emphasis on high‐reliability applications. Each technique is discussed with regard to its influence on the final reliability of the assembly under normal and abnormal storage and working conditions. Reliability is determined by numerous other parameters which are frequently ignored, such as the component layout for best cleaning quality. The requirements of conformal coating are also frequently given scant attention. In practical terms, this paper may help those selecting a substitutive soldering/cleaning process to choose one which will meet their quality requirements at minimum cost.
High Performance Materials for PCBs
Authors: Cygon M.
Published: February 2008

High demands are placed on base materials for present‐day printed circuits. The requirements for multilayer materials are examined including satisfying criteria regarding low dielectric constant, high glass transition temperature and dimensional stability. Comparisons are made involving different resin systems and reinforcement materials. Improvements in material characteristics are often accompanied by disadvantages in terms of processability, copper peel strength and price. The properties of a number of paper‐based laminates and their requirements are discussed. It is concluded that no ‘ideal’ base material is available which simultaneously fulfills all demands including price.
Immersion, Non‐electrolytic Tin/lead Plating Process
Authors: Couble E.C. , Dutkewych O.B. , Florio S.M. , Marsh M.V. , Staniunas R.F.
Published: February 2008

The technological development and characteristics of an innovative process and composition for immersion plating and fusing of a solderable tin/lead deposit over copper are discussed. The process offers a viable alternative to hot air solder levelling, electrodeposition/selective stripping, or inhibitor coatings for maintaining solderability of printed wiring boards. A flat, uniform solderable tin/lead coating on all feature surfaces and edges is achieved. A number of important benefits are derived. The ability to coat any copper surface uniformly, including fine pitch features, is substantially enhanced. Solderability is improved because of a thick, flat, co‐planar and uniform tin/lead deposit on all copper surfaces. Typical thickness and composition of the fused alloy are 150 to 300 microinches (4 to 8 microns) and 65 to 75% tin.
PWB Interconnect Strategy Using a Full Build Electroless Copper Plating System
Authors: Minten K. , Cisson J.
Published: February 2008

This, the third in a series of papers, reports an investigation of the semi‐additive process strategies of PWB manufacture. It will show that, although the adoption of a ‘naked’ palladium catalyst is the optimal production strategy in terms of cost, caution must be exercised in its implementation, particularly with regard to material process flow and solder mask type employed. It will be demonstrated that the use of a thin, sacrificial ‘flash’ of electroless copper prior to circuitisation and full build deposition will be required for the liquid photoimageable soldermask (LPISM) approach.
Teknek Electronics Ltd, Quarriers Village, Bridge of Weir, Scotland
Authors: Cullen Lorna
Published: February 2008

FRIDAY, December 11, 1992 — While hordes of headline‐seeking journalists at Holyrood Palace competed for the latest scoop on the Edinburgh Summit, it was pleasant to travel west to the calmer setting of Quarriers Village in Renfrewshire. Success was claimed as the outcome of the Summit. Another success story is reflected in the growth and performance of the still fairly young but thriving company Teknek Electronics Ltd. Success in a period of inescapable gloom for the electronics industry is all the more newsworthy. It should also offer a glimmer of optimism to an industry where hope and enthusiasm appear dampened, if not extinguished, by successive recession‐related blows.
Alternative Solders for Electronics Assemblies
Authors: Vincent J.H. , Richards B.P. , Wallis D.R. , Gunter I.A. , Warwick M. , Steen H.A.H. , Harris P.G. , Whitmore M.A. , Billington S.R. , Harman A.C. , Knight E.
Published: February 2008

This is the second of two papers reporting work carried out under a programme sponsored by the Department of Trade and Industry (DTI), involving collaboration between the above companies and research centres. The objectives of the programme are to identify/develop lead‐free alternatives to Sn‐40Pb solder, progress towards the development of which is described in this paper. A number of promising alloys have been selected for trial in a further round of experimentation.
Corrosion Protection of Copper Using Organic Solderability Preservatives
Authors: Artaki I. , Ray U. , Gordon H.M. , Opila R.L.
Published: February 2008

The emergence of new interconnection technologies involving double‐sided surface mounted components has put stronger restrictions on the method of preserving the solderable finish on printed circuit (PC) boards. The popular Sn/Pb coatings have come under strong scrutiny due to environmental hazards of lead and also because they do not provide flat, planar surfaces for SM assembly. Organic solderability preservative coatings (OSP) are emerging as strong contenders for replacing Sn/Pb surface finishes. Benzotriazole based organic coatings have been successfully used in the past by several electronics manufacturers. However, assembly technologies involving multiple thermal operations have necessitated a fundamental understanding of the thermal stabilities and the mechanism of corrosion protection provided by the OSPs. This paper reports the results of an investigation of the thermal stabilities of two organic corrosion protection coatings. Although both are organic azole based, they operate in two distinct regimes: one forming thin films (∼100 Å) and the other forming thick films (∼5000 Å). The mechanism of surface protection has been studied using direct surface analytical techniques such as X‐ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), scanning transmission electron microscopy (SEM/TEM) and Fourier transform infrared spectroscopy (FT‐IR). The solderability of the copper was measured by wetting balance techniques and correlated to the amount of copper oxidation. The results indicate that, although the thin films provide excellent protection for storage and handling operations, they decompose under heat, thereby causing oxidation of the copper. The thick films appear to withstand multiple thermal cycling. However, the underlying copper substrate can still be oxidised by oxygen diffusion through pores or cracks, or the film may undergo chemical changes that render the copper unsolderable.
The Cooling Efficiency Concept — A Tool for Fast Thermal Analysis of PCBs
Authors: Mälhammar Å.
Published: February 2008

Thermal analyses of printed circuit boards (PCBs) based on the finite element or finite difference methods are frequently used in the electronics industry, the major reason for this being the geometrical complexity of the thermal problems. Correctly used and with access to all relevant data, these methods are very accurate. In the early stages of the PCB design process, it is often necessary to make temperature estimations based on data which are very uncertain and sometimes mere guesswork. Any temperature prediction based on such assumptions will, regardless of the method used, always be of a preliminary nature. A fast and approximate method can then offer advantages over a complex but accurate method. The cooling efficiency for a PCB is defined as the heat dissipation for the PCB over the heat dissipation for a flat smooth isothermal plate of the same size and with a temperature which equals the maximum temperature of the PCB. This definition makes it possible to derive the maximum temperature on a PCB from the well‐defined isothermal case. The cooling efficiency for a particular PCB can be calculated or measured. The experience of the author is that the values for most multilayer PCBs are in the range 50–85%. For PCBs which have a few concentrated heat sources, the cooling efficiency could be considerably lower. For PCBs with any form of surface extension, the cooling efficiency could be higher. The cooling efficiency concept is particularly useful as a fast front‐end thermal analysis tool. The concept can also be used in conjunction with thermal specifications of PCBs and at the PCB enclosure level.
Integration of Thin Film Polyimide with PCB Technology
Authors: Kersten P. , Reichl H.
Published: February 2008

The development of high density packaging technologies offers cost reduction, smaller system volumes and better performance. High performance PCBs with fine line technology reach conductor widths of <0.1 mm and pitches of <0.2 mm. The limiting factors for higher densities of PCBs are the mechanically drilled through‐holes. In particular, the assembly of modern ICs with a pitch of less than 0.2 mm requires fine line technology and a simultaneous reduction of via diameters to minimise fan‐out areas. To meet these requirements, an interconnection system with photosensitive polyimide as an interdielectric thin film layer on top of a PCB is investigated. To demonstrate process feasibility, a test module including a test structure for measurement of contact resistance has been fabricated.
Reducing Plated‐through Hole Copper Loss during Pin‐in‐hole Rework — Polymer Barrier Film Process
Authors: Davis C.R.
Published: February 2008

In an electronic manufacturing environment, rework of pin‐in‐hole components on printed circuit boards is an essential process. Rework enhances product yield and through‐put efficiency by allowing device repair to occur quickly and at significantly reduced costs in comparison with complete board reconstruction. However, current rework techniques are not without their shortcomings, most notably enhanced dissolution of copper in plated‐through holes. This paper discusses a new methodology using polymer films as barrier layers, resulting in negligible plated‐through‐hole copper dissolution when conventional rework technologies are practised.
Printed Circuit World Convention VI
Authors: Christie I.R.
Published: February 2008

The Printed Circuit World Convention 1993 was held at the Fairmont Hotel, San Francisco, from 11–14 May 1993. The Convention was the sixth in the series held at three‐year intervals and represents the major conference on all matters relating to processing, development, management and future predictions within the industry. Over 60 papers in three concurrent sessions were held over the conference period.
Wire‐bonding on Printed Circuit Boards
Authors: Falk J. , Hauke J. , Kyska G.
Published: February 2008

Although wire‐bonding is an established and well‐known technique for micro‐joining on leadframes, direct die‐attach without housing on printed circuit boards has some new requirements for the surface of the bond pads and the PCB itself. The best choice of material for the bond pads is a pure gold metallisation. The quality of the surface can be tested during wire‐bonding using the ultrasonic‐power process window. It will be shown that the surface and the PCB itself have a considerable influence on the ultrasonic and thermosonic bonding process.
Electromagnetic Interference in Portable Electronic Products: Emerging Challenges and Opportunities
Authors: Nyholm P. , Rao S. , Duffy H.
Published: February 2008

This paper reviews technologies used for the prevention of electromagnetic interference in current portable electronic products. It studies the need for future advanced products and some of the technologies likely to be available. The focus is on housing technologies and the products available for giving greatest electromagnetic compatibility with the latest European and other emission and susceptibility standards. It is concluded that new or improved approaches which are better able to ensure long‐term reliability will be essential for the 100 MHz clock speed equipment likely to be in production within the coming five years.
No‐clean Flux Appraisal — The Total Process Approach
Authors: Mason B.J.
Published: February 2008

No‐clean flux printed board appraisal tests were conducted with all materials used in the production process. Metallic growths during environmental testing revealed that there was incompatibility between some materials used. Initial tests with two solder resists and several fluxes showed that one non solder resisted board, soldered using a synthetically activated (SA) flux, had surface insulation resistance (SIR) two decades higher than those using low solids flux (LSF) or other SAs. For boards with solder resist, the SIR of those soldered using LSFs was higher, however, than those using SA fluxes. SIR dependence on temperature and humidity was investigated. Results demonstrated that the dominant factor to determine the SIR of a no‐clean board was the characteristics of the board substrate finish. SIR changes with condensation were logged and found to be significant for solder resist finishes. Tests proved that reducing the contamination levels under and on top of the solder resist, by using hot de‐ionised water rinsing, enabled the calculated minimum SIR level to be achieved for spray fluxed boards and minimised the possibility of metallic growth. Visual examination proved to be at least as important as SIR testing. No‐clean processes were appraised using sequential environmental conditions with differing SIR pass levels. As a result of this appraisal a maximum ionic contamination level of 0·5 μg/cm2 NaCl equivalent and Dl water rinses, before and after solder resist added, will be introduced. Ionic contamination tests indicated that contamination levels reduced with elapsed time, probably due to ionic molecules locking more firmly into the board surface structure. A novel method for SIR measurements at any voltage, developed by the author, is described. It is hoped that this paper will further the understanding of no‐clean flux issues and highlight potential solutions and pitfalls.
No Clean Mass Reflow of Large Plastic Ball Grid Array Packages
Authors: Lau J. , Miremadi J. , Gleason J. , Haven R. , Ottoboni S. , Mimura S.
Published: February 2008

A no‐clean mass reflow process for 396‐pin, 324‐pin and 225‐pin over moulded plastic pad array carriers (OMPACs) or plastic ball grid array (BGA) is presented. Emphasis is placed on the OMPAC assembly parameters such as the design, material and process of the packages and printed circuit board (PCB), solder paste, stencil design, printing technology, pick and place, mass re‐flow and inspection. Furthermore, cross‐sections and the ‘popcorn’ effect of the OMPAC assembly are provided and discussed.
Solderability Preservative Coatings: Electroless Tin vs Organic Azoles
Authors: Artaki I. , Ray U. , Jackson A.M. , Gordon H.M. , Vianco P.T.
Published: February 2008

Substitution of lead‐free solders in electronic assemblies requires changes in the conventional Sn:Pb finishes on substrates and component leads to prevent contamination of the candidate solder. Options for solderability preservative coatings on the printed wiring board include organic (azole or rosin/resin based) films and tin‐based plated metallic coatings. This paper compares the solderability performance of electroless tin coatings versus organic azole films after exposure to a series of humidity and thermal cycling conditions. It is shown that the solderability of immersion tin is directly related to the tin oxide growth on the surface and is not affected by the formation of Sn‐Cu intermetallic phases as long as the intermetallic phase is protected by a surface Sn layer. For a nominal tin thickness of 60 ?inches, the typical thermal excursions associated with assembly were not sufficient to cause the intermetallic phase to consume the entire tin layer. Exposure to elevated temperatures, in the presence of humidity, promoted heavy tin oxide formation which led to solderability loss. In contrast, thin azole films were shown to be more robust to humidity exposure; however, upon heating in the presence of oxygen, they decomposed and led to severe solderability degradation. Evaluations of lead‐free solder pastes for surface mount assembly applications indicated that immersion tin significantly improved the spreading of Sn:Ag and Sn:Bi alloys compared with azole surface finishes.
PCB Investment Strategy into the 1990s
Authors: Tyler R.L.
Published: February 2008

This paper will debate the issues affecting the OEM's future use of PCBs during the years leading up to 2000. It will explore the primary driving forces that will influence the PCB's future as an interconnect platform and forecast the changes in usage patterns and user demands likely to occur in the next 5–7 years. Trends in system design will be tracked and the implications for board manufacturers identified in terms of the board volume and market mix that will be demanded by the electronic system houses. The paper will also look into the board industry and give a view on the internal effects of all this change. It will look at the technology responses needed by the board shops and the impact on investment strategy and financial viability that may be engendered by these changes. The paper should give a concentrated overview of the impacts — market, technology, structural and financial — that the inexorable move towards (and past) a $1 billion world electronics industry will have on the world's board makers.
PCB Fabrication Technologies for Improved Performance and Cost
Authors: Britton P.L.
Published: February 2008

Lower manufacturing costs and improved performance are required by the printed circuit board industry. This paper focuses on manufacturing technologies that will permit both technical and cost criteria to be achieved. Existing and emerging fabrication techniques (worldwide) are discussed and a path forward is suggested for cost‐effective manufacture of high‐performance PCBs.
Lead‐free Solders for Electronic Packaging and Assembly
Authors: Hwang J.S. , Guo Z.
Published: February 2008

In terms of science, technologies and end‐use applications, ‘lead‐free solders’ are a very broad subject. This paper is intended to highlight the key issues of this broad subject for its applications in electronic packaging and assembly. The areas covered include the main thrusts behind the research and development effort, the scientific approaches, economic and practical considerations, and regulatory and legislative perspectives of lead. In addition, this paper will present the new findings as a result of research and development effort on lead‐free solders. Technologically, in view of the current and future needs in interconnecting materials, the first objective of this work is to demonstrate the ability to provide lead‐free solders in lieu of conventional lead‐bearing solders without mandating significant changes in manufacturing processes and/or equipment which have been established and proven in the industry. The second objective is to design the lead‐free solders which are able to offer superior performance to their Sn/Pb counterparts, thus providing solder interconnections with higher reliability and endurance during service life. The fulfilment of these two objectives will concurrently address the two critical technological areas in the field of solders, namely the inherent vulnerability of conventional solders to temperature and stress, and the concerns of toxicity and health hazard of lead. Based on materials principles, ternary and quaternary lead‐free systems are at present being designed. The work conducted thus far demonstrates that two of the designed solder compositions show great promise. In comparison with 63Sn/37Pb eutectic solder, the new lead‐free compositions exhibit superior performance in shear strength, creep resistance and thermomechanical fatigue resistance. This paper will also cover the data in mechanical testings, the summary of microstructure evaluation (with detailed elucidation omitted), and low‐cycle fatigue fractoqraphy examination of the designed lead‐free compositions.
The Determination of Flux Residue Safety: The State of the Art
Authors: Ellis B.N.
Published: February 2008

The need to use cleaning methods other than traditional CFC‐113 solvent for hi‐rel electronics imposes more rigid cleanliness testing. In the past, this was mainly limited to ionic contamination control, but this is probably insufficient by itself when using other methods. This paper discusses the various methods for which instrumentation is available, from the practical standpoint. This should satisfy all the requirements of both procurement agencies and manufacturers. Particular emphasis is placed on the fact that most existing standards are out‐of‐date and should be urgently revised. It is suggested that the standards be based on statistically valid test results rather than the simpler, but risky, go/no‐go methods. These probability limit levels should be modulated according to the use to which the circuitry will be put and the technology used in its manufacture. Above all, emphasis is placed on testing methods that are more scientifically based with less empirical guesswork.
International Institute News
Authors: Galbraith Trevor
Published: February 2008

During the first half of this year the Association has continued to expand its exhibition programme by increasing its presence at overseas shows. Two DTI sponsored joint venture groups have been formed, one to Nepcon West, the other to Nepcon Beijing. Anaheim saw the biggest UK group for over 10 years, with CEMA taking three separate blocks in different sectors of the show. There is no doubt from the reception we received that CEMA is now firmly established at Nepcon West. We enjoyed tremendous support from both the British Consulate and the British‐American Chamber of Commerce with their President making several visits to the CEMA booth.
Confronting the Challenges of Change
Authors: Damrich Thomas J
Published: February 2008

“The only constant in today's world is change”. We've heard this many times over the past several years. It has become a cliche. Fact is, not only is it true, but change is coming at us at a faster and faster rate with each passing year.
Current Situation with regard to PCB Production in the Western Part of the Former USSR
Authors: Evzhenko V.M. , Chebotarevsky A.G.
Published: February 2008

An analysis is given of the present situation regarding PCB production in six independent states of the former USSR. The distinctive characteristics of the PCB industry under the command‐administrative system which existed until 1991 are outlined. Production capacities of PCB manufacturers and production volumes for 1989–1993 are analysed. An important feature of the market is PCB complexity. The fact that the majority of companies are equipped with domestically produced machinery creates drawbacks. The paper concludes with some proposals for action to increase the efficiency and competitiveness of printed circuit board production in the western part of the former USSR.
Innovations in Organics Circuit Packaging Technology
Authors: Brauer J.M. , Chen W.T.
Published: February 2008

This paper describes some recent innovations in design, process and materials in printed circuit laminate technology, which can lead to significant paradigm shifts in the design and application of electronic products. The traditional roles for printed circuit cards and boards have been to provide wiring interconnection capacity, and a robust mechanical structure for the more delicate and costly chips and modules. The advent of surface mount technology eliminated the need for plated‐through holes as anchors for pinned components. The proliferation of light, high performance, multifunction electronic products will lead to light weight, small, low profile printed circuit assemblies. Adding a redistribution layer to the traditional card surface allows flip‐chip‐on‐board and MCM‐L packages as a low‐cost alternative to traditional high density MCM packages, particularly in applications where size, shape and weight are as important as density and performance. Concurrent with the deliberate evolution of traditional printed circuit technology, some important new materials and process innovations have brought about a new generation of laminate capabilities that are particularly important for the future high I/O requirements predicted for the second part of this decade.
European Joint Conference IV Held in St Petersburg, Russia
Authors: Dammrich Thomas J.
Published: February 2008

The European Joint Conference was held in St Petersburg, Russia. Approximately 120 people attended the conference, many bringing along spouses who enjoyed visiting this beautiful, culture rich city. The site was selected to give attendees from Western Europe, North America and Southeast Asia (although there were few, if any, attendees from Southeast Asia) an opportunity to look into the former Soviet Union and learn more about its printed circuit industry.
PCIF News
Authors: Macariou Matthew
Published: February 2008

The latest industry statistics recently published by the PCIF indicate that the UK printed circuit fabrication industry has emerged from the recession leaner and fitter. Over‐capacity has been slashed, with 60% fewer companies producing 10% more product than three years ago. Productivity is up 58%.
Plastic Encapsulated MCM Technology for High Volume, Low Cost Electronics
Authors: Fillion R. , Wojnarowski R. , Gorcyzca T. , Wildi E. , Cole H.
Published: February 2008

An innovative embedded chip MCM technology is being developed to address the packaging needs of the high volume, non‐military electronics industries. This development has evolved out of the GE High Density Interconnect (HDI) embedded chip MCM technology that was aimed at very high performance electronics in harsh military environments. In the HDI process, multiple bare chips are placed into cavities formed in a ceramic substrate and interconnected using an overlay polymer film, thin film metallisation and laser formed vias. Multiple levels of fine line (20 to 40 microns) interconnections and reference planes are used to form the circuit. In this new process, a plastic encapsulated substrate is formed by moulding a polymer resin around the bare die after placement on to a flat polymer film pre‐coated with an adhesive layer. After curing of the resin, the circuit is formed by patterning via holes through the polymer film to the components, metallising the polymer film and patterning the metal into the desired interconnect pattern. Feature sizes are readily scaled to the complexity needed by the circuit, permitting the use of lower cost and higher yield board photopatterning processes and equipment. This paper will cover the development of this low cost technology and will describe the process. It will also describe the thermal, mechanical and electrical features of this process and show actual working prototype modules.
An Alternative to Feed and Bleed for Saving Chemicals and Rinse Water
Authors: Choo T.Y.
Published: February 2008

The feed and bleed method of controlling process chemicals commonly used in the printed circuit industry, though convenient, is inefficient. In a typical feed and bleed application, a portion of the fresh chemistry is always being bled out with the spent solution. A technology introduced by the author's company can achieve the chemical efficiency of a batch method and process convenience of the feed and bleed process. This article describes the technology, application method, theory and mathematical calculation showing the saving. Examples of some of the application areas are: photoresist developing, stripping; ammoniacal etch; electroless copper; rinse water in plating and cleaning.
PCIF News
Authors: Galbraith Trevor
Published: February 2008

The following is a summary of the reports sent to those members participating in the various statistical surveys running at present.
Industry News
Authors: Franke Jörg
Published: February 2008

Dr Wallace Rubin, international consultant on soldering technology, was recently honoured with the 1994 Environmental Protection Agency (EPA) Stratospheric Ozone Protection Award for his work in helping to bring about the elimination of chlorofluorocarbon (CFC) solvents in the world's electronics industry. He is the only individual UK recipient of the 1994 award and one of just fifty individual and corporate recipients worldwide.