bluuebunny/crossref_metadata_2025 huggingface dataset:
Glass Interposer Substrates: Fabrication, Characterization and Modeling
Authors: Shorey Aric , Chaparala Satish , Pollard Scott , Piech Garrett , Keech John
Published: October 2015

There is growing interest in applying glass as a substrate for 2.5D/3D applications. Glass has many material properties that make it well suited for interposer substrates. Glass based solutions provide significant opportunities for cost reduction by leveraging economies of scale as well as forming substrates at design thickness. A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, an interposer made with glass should have better electrical performance than one made with silicon. Electrical characterization and electrical models confirm this advantage, and its positive impact on functional performance. Further advantages are anticipated in reliability, driven by the ability to tailor thermal properties such as coefficient of thermal expansion (CTE) of glass. Modeling results will be presented that show how the proper choice of CTE can significantly lower stack warpage. Additionally, significant progress has been made in the demonstration of glass interposer fabrication. Fully patterned wafers and panels with through holes and blind holes are being fabricated today. It is equally important to be able to demonstrate the ability to leverage existing downstream processes for metallization of these substrates. The ability to apply existing downstream processes to make functional glass interposers using both through and blind via technology will be presented.
An Analysis of Evolving Package Reliability Test Methodologies for Wireless Applications
Authors: Ferrara Michael
Published: October 2015

Increased demands on time to market and new technology introductions create challenges for package reliability testing to be as efficient and comprehensive as possible within a limited time frame. Further, new package technologies and their interactions pose additional reliability risk with the need to be carefully evaluated. This paper will analyze this trend and identify solutions in the form of better and more efficient upfront methodologies such as potential problem analysis, delta analysis, detailed statistical analysis, and daisy chain/ test to failure methodologies. Future trends will also be evaluated.
Microfluidic Device Packaging
Authors: Spangler Leland “Chip”
Published: October 2015

Microfluidic devices are used in a very diverse set of applications including medical and laboratory diagnostics, environmental monitors, ink jet print heads, chromatography and fuel cells to name just a few. These wide ranging applications, the highly diverse set of fluid types that are used in them, and the fact that many of these devices are used in relatively uncontrolled environments, places significant demands on the package and the materials the package is made from. These challenges can be offset by the fact that many microfluidic package technologies provide opportunities for the designer to incorporate valuable features into the package with little additional complexity or cost. A set of case studies is presented to illustrate the concepts presented in the paper.
Mechanical Stress Analyses of Packaged Pressure Sensors for Very High Temperatures
Authors: Zeiser Roderich , Ayub Suleman , Hempel Jochen , Berndt Michael , Wilde Juergen
Published: October 2015

Methods for investigations of stresses specialized for devices operating up to 500 °C are presented in this study. Resistive pressure sensors and test-chips with micro strain gauges are processed in thin film technology. The sensor structure was a wheatstone-bridge on a silicon membrane with platinum resistors. The μ-strain gauges were characterized with tensile tests in combination with optical strain measurements. A gauge factor of 3.6 was measured at room temperature. After characterization as bare dies, the chips were mounted with a borosilicate glass-solder on two ceramic substrates, AlN and Si3N4. We generated a FE-model of the sensor assemblies including temperature dependent materials properties. The distribution of mechanical strains and stresses in the sensor was analyzed. The chip warpage dependent on temperature up to 500 °C was obtained from FE-simulations and compared to high precision 3D-deformation measurements. Deformation results from digital image correlation (DIC) verified the utilized FE-model. The correlation of experimental results for the chip warpage exhibited a good agreement with the numerical results obtained from FEM. The chip deflection from center to the edges in out-of-plane direction on AlN was 4.5 μm; on Si3N4 a concave warpage of 3 μm at 25 °C was found. Temperature induced deformations of the sensor chip in the range of micrometers were recorded up to 500 °C. The output signal of the pressure sensors is strongly affected by superimposed strains due to the sensor assembly. The bridge voltage increased by 40 % after the glass solder process on AlN and by 34 % for devices on Si3N4. The analysis of the μ-strain gauges showed a compressive strain in the sensor membrane of −1.39 % for assemblies on AlN and of −0.168 % for glass soldered chips on Si3N4. The FEM simulations revealed an average in-plane stress in the sensor membrane of −45 MPa for chips on AlN and – 20 MPa for Si3N4 substrates. A higher strain and stress gradient in the membrane of devices on AlN was found with FEM, which is assumed to lead to the higher offset drift of the sensor signal after the assembly.
Conceptual Development Using 3D Printing Technologies for 8kV SiC Power Module Package
Authors: Ke Haotao , Xu Yang , Hopkins Douglas C
Published: October 2015

Post-silicon power devices, SiC or GaN for example, have many advantages over traditional silicon devices, particularly for smaller size and higher thermal densities. Although these devices are in the early stage of development, many applications have been identified, such as hybrid vehicles and the smart grid. For power packaging, there is now a greater challenge of much higher voltage, faster switching speed and much smaller package size (higher density). All of these issues call for newer approaches in power packaging.

The microelectronics area has been developing stacked 3D technology along with printed 3D circuit technologies. Of been interested are the 3D printing technologies that can implement complicated structures, such as multilevel interconnects and selective dielectric field enhancements, besides introducing rapid prototyping in the early power stage design cycle. The 3D printing technology, introduced in the late 1980's, is now becoming prevalent. Commercial printers can create high-resolution structures in ceramic, metals (e.g. titanium, copper and aluminum) and polymers. The conceptual design proposed in this paper will incorporate a hybrid approach of traditional structures over-printed with polymers, or more advanced structures over-printed with metal and ceramic.

The design focuses on packaging 1 cm × 1 cm SiC Schottky diode, which has a blocking capability of 8kV with a final target at 15kV. Early use of the package, in keeping with rapid prototyping, is to provide a test vehicle for the device, and prove the application of 3D printed material to high voltage power modules. This paper will present the necessity for packaging new SiC devices, review device characteristics, introduce the use of extruded 3D printing materials for a hybrid structure, and use of jetted/extruded layer-by-layer buildup for total, direct structure creation. Characterization of some available dielectric and metal printable materials, and a test methodology for electrical, thermal and mechanical performance will be discussed. An early-stage example will be shown and extrapolated to higher-level conceptual designs.
TSV Etching Process For High Capacitor And TSV Reliable Integration.
Authors: Murayama Takahide , Sakuishi Toshiyuki , Morikawa Yasuhiro , Tani Noriaki , Saitou Kazuya
Published: October 2015

TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. We have developed Si etching technology for high aspect ratio (>20) ultra low leak high- capacitor by using TSV production technology. As anisotropic deep silicon etching method, cycle etching and non-cycle etching method have been offered. Cycle etching is a general anisotropic Si etching method by cyclic etching of deposit (fluorocarbon polymer) and etching. In cycle etching, sidewall is protected by fluorocarbon polymer, periodic roughness appears on etched sidewall called 'scallops'. On the other hand, non-cycle etching is without using fluorocarbon. In non-cycle etching, sidewall is protected by thin SiOX, non-cyclic etching process achieves smooth etched 'scallops-free' sidewall. It is considered that the quality of etched sidewall influences capacitor reliability in process integration, it is necessary to investigate sidewall condition about both cycle etching and non-cycle/scallops-free etching because of differences of each etching process property; process gas, sidewall protection mechanism, scallops/ scallops-free, and so on. Therefore we conducted XPS analysis etched trench sidewall; depth of 10 um, 25 um, 40 um. XPS Analysis showed that in cycle etching there are more residual F and C on etched sidewall due to fluorocarbon polymer than non-cycle without using fluorocarbon. It is considered that more residual F and C on etched sidewall might influence capacitor and TSV reliability.
Cost Analysis of TSV Process and Scaling Options
Authors: Vartanian Victor , Smith Larry , Hummler Klaus , Olson Steve , Sapp Brian , Barbera Tyler , Golovato Steve , Yu Kai-Hung , Hasegawa Toshio , Hu Shan , Leusink Gert , Maekawa Kaoru , Enloe Jack , Gracias Alison , Pattanaik Gyanaranjan , Wafula Fred
Published: October 2015

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm.

These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable.

We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions.

The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.
Manufacturing Readiness of BVA™ Technology for Fine-Pitch Package-on-Package
Authors: Katkar Rajesh , Co Rey , Zohni Wael
Published: October 2015

Ever increasing performance demands in a rapidly evolving smart phone market have led to a need for higher density interconnections linking memory components with logic devices in a standard package on package (PoP) configuration. While existing solutions present a technological roadblock at 350–400μm PoP pitch, new Bond Via Array (BVA™) technology provides a cost effective and scalable alternative that can achieve 240μm and below pitch values while utilizing conventional wirebond package assembly processes and tools. BVA is a high density, ultra-fine pitch package-on-package (PoP) interconnect solution that enables more than 1000 high aspect ratio connections between memory and processor components in a standard outline PoP. This increase significantly improves PoP capability and correspondingly provides increased bandwidth for the next generation of mobile devices. Here we discuss the 1020 IO BVA demonstration test vehicle, associated manufacturing process details, reliability performance and bi-level socket hardware developed to test these wire bond based novel interconnects. Furthermore the overall high volume manufacturing (HVM) readiness state of this technology for PoP applications will be described. The 1020 IO BVA prototype features 5 rows of vertical interconnects at 0.24mm pitch within an industry standard 14 x14mm package footprint. Although BVA interconnects were primarily developed for PoP packages, they offer many benefits over traditional vertical interconnects and can be implemented in a variety of other applications.
Methodology for Predicting BGA Warpage by Incorporating Metal Layer Design
Authors: Shantaram Sandeep , Hauck Torsten
Published: October 2015

This paper presents a methodology to predict warpage of ball grid array packages (BGAs) that takes into account details of metal designs in the multi layered substrate. Composite theory along with local homogenization methods are used to resolve the distribution of material properties in each layer of the substrate that enables an efficient simulation model with moderate computational size. Associated procedures have been implemented and tested for finite element simulation tool. Verification examples were prepared to demonstrate the warpage predictions on BGA packages. Key substrate parameters including package mold compound shrinkage during post mold cure and the resultant impact on deformation behavior and mechanical reliability of BGA assemblies. A comparison of simplified homogenization methods and representative unit cell models of multi layered composite structures are discussed and show the significance of incorporating detailed metal layer design in simulation model for accurate warpage prediction.
Parametric Studies of Effects of Solder Bump Pitch, Package Size, and Molding Compound and Substrate Thicknesses on Warpage of PBGA Packages
Authors: Kang Sungbum , Ume I. Charles
Published: October 2015

Plastic ball grid array (PBGA) is one of the most widely used types of chip packages in various electronic devices such as network servers, microcontrollers, and memory devices. As the demand for higher performance electronic devices grows, the I/O densities of PBGA packages are increasing while requiring superior reliability. Warpage induced during the reflow assembly process is one of the crucial factors affecting the thermo-mechanical reliability of PBGA packages; therefore, accurate warpage prediction is an important task for package design processes. In this study, the effects of four geometric factors (the solder bump pitch, package size, and molding compound and substrate thicknesses) of the PBGA package on its warpage are assessed by using parametric finite element analysis. The correlation between PBGA warpage and the four factors is studied using the regression method. These results are expected to provide design guidelines for in-house PBGA designers.
Solder Joint Reliability Assessment for a High Performance RF Ceramic Package
Authors: Charbonneau Paul , Ohman Hans , Fortin Marc
Published: October 2015

The prediction of long term solder joint reliability, (SJR), of microelectronic devices and packaging solutions continues to challenge the microelectronic packaging industry, particularly with the introduction of lead-free materials, the push for higher performance (frequency/speed/thermal) and lower unit cost. High performance packages are generally custom designed and therefore have minimal industry data on configuration specific reliability performance. In this application, the package substrate coefficient of thermal expansion, (CTE), was closely matched to the die resulting in a relatively large CTE mismatch between the package and organic PCB. In addition, the package RF and thermal performance requirements required this particular solution to be configured as a “cavity down” perimeter ball array with a large central ground pad to electrically couple the package to the PCB. Given the package's unique design requirements and CTE mismatch, even modest daily temperature swings of 20°C usually found in a controlled or “Central Office” environment could have an adverse impact on the interconnect reliability.

This study provides an overview of the solder joint reliability assessment methodologies performed for a custom design lead-free, high performance RF package as part of the requirements to demonstrate compliance to product specifications. SJR life predictions were made for varying package BGA configurations using a multi-tiered approach using constitutive material models, thermo-mechanical finite element simulations, and material specific fatigue models. Empirical accelerated life testing was performed and a life prediction obtained through modeling was validated. Finally, statistical failure distributions were fit to empirical data and discussed in the context of absolute solder life predictions of small fractions unit failures, (100ppm).
High Resolution Patterning Technology to enable Panel Based Advanced Packaging
Authors: Ruhmer Klaus , Cochet Philippe , McCleary Roger , Chen Nelson
Published: October 2015

As the semiconductor industry is maturing, the reign of Moore's law has come to an end. New approaches beyond scaling down transistors have taken over the burden of continued and rapid performance growth. These new approaches are essentially related to integration of components. Decrease of form-factors and increase of functionality and performance is accomplished by sophisticated integration schemes. In other words, back-end Advanced Packaging technologies continue to grow ever more important to not only meet performance and size goals but also to drive down cost.

Although front-end manufacturing is naturally tied to round semiconductor wafers, some of the most recent back-end technologies are no longer required to be performed on round substrates. Embedded die, fan-out and interposer based packages can be manufactured on larger and more convenient substrates such as square and rectangular glass, molded or organic panels thus enabling economy of scale efficiency gains and cost savings.

This work focuses specifically on the challenges surrounding the lithographic patterning of these “non-round” substrates using a high-resolution 2x reduction stepper lithography system. The paper provides an overview of the various panel-based advanced packaging applications including Panel Fan-Out (P-FO), 2.5D glass interposers and high-density organic substrate interposers. The specific lithography requirements and challenges are highlighted and analyzed. These include patterning resolution down to 2μm and beyond, layer to layer overlay accuracy of better than 1μm, depth of focus of 15μm and more, resist sidewall angles of above 80 degrees, ability to deal with topographic variations, ability to handle and process panels with severe warpage, ability to prevent system contamination due to outgassing of photoresists or polyimides, ability to process devices without so-called field stitching only to name a few.

Last but not least, cost implications of the lithography process are analyzed and discussed.

Ultimately, the work attempts to assess the readiness of the industry for panel based Advanced Packaging specifically from a lithography perspective. The potential cost advantages but also the hurdles and challenges related to panel-based advanced packaging patterning technologies are highlighted.
Automated Metrology Improves Productivity and Yields for Wafer Level Packaging in High Volume Manufacturing
Authors: Zao Jin You , Yen Bong Yin , Kuan Lim Beng , Thornell John , Hart Darcy , Marx David
Published: October 2015

Wafer Bumping In-line Process control of Wafer-Level Chip Scale Package (WLCSP) requires accurate measurement of bump features during processing. These bump features include critical dimension of Redistribution Layer (RDL), Under Bump Metal (UBM) and transparent polyimide thickness. For a 4-Mask Layer Cu plated WLCSP, accurate feature thickness measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor.

This paper reports the development of an automated Critical Dimension (CD) measurement solution capable of measuring features at pre-defined locations on different topology both under sampling and full inspection mode on wafer. The solution is fully scalable to meet the requirement of high product-mix HVM environment, by highly adaptive to different features on different products for which measurement needs to be automated for effective process control.
Adhesive Enhancement Technology for Directly Metal Plating on EMC
Authors: Mukai Kenichiroh , Kim Kwonil , Eastep Brian , Gaherty Lee , Kashyap Anirudh
Published: October 2015

Plating on molding compound is a relatively new field with many possible applications. One major application is magnetic or electrical EMI shielding of active components. This is currently done by metallic cans. However, this technique also increases the space requirements. A second major application, is the formation of build-up circuits on encased components, such as for Fan-out Wafer Level Packaging (FO WLP).

An established method to provide a metallic seed layer is sputtering. However, with respect to cost effectiveness and mass production capability, classical electroless metallization along with an adhesion promoters would a desirable alternative. In this paper we will present a new approach, where components encased by molding compound are directly coated with an electroless copper or nickel layer. By this method spatial requirements are minimized. Also, this process fits into the existing infrastructure within the PCB industry.

Due to the presence of fillers with an extremely high ratio (70–90%wt.) and irregular size (from few μm to tens of μm), classical Desmear followed by electroless seeding can get at best an adhesion of only 2–3N/cm . This is typically insuffient to prevent delamination during further processing. In contrast, with chemically bonding adhesion promoters, as presented in this paper, we are able to get up to 5N/cm of peel strength without any blistering. The plated layer stands up well to reflow shock (260C) and HAST without significant loss of adhesion.

These adhesion enhancement technology is applicable to various kinds of molding compound. Extending this technology to FO WLP (i.e. FO SiP, FO PoP) can be another far reaching application.
Silver Paste with Nano-sized Glass Frits for Silicon Solar Cells
Authors: Shih Yu-Chou , Shao Yue , Lin Yeong-Her , Shi Frank G.
Published: October 2015

Scientists are looking for alternatives to fossil fuels as energy source in order to reduce the environmental issues. Solar energy is one of the candidates that have attracted our attention. Monocrystalline and polycrystalline silicon materials are the most common ones for solar cell panels, and one of the key properties of silicon solar cells is the interfacial resistivity between the front silver electrodes and the n-type silicon emitters. The interfacial resistivity is hugely affected by the interfacial structure between silver electrodes and n-type silicon emitters, which plays a very substantial role for the electrical and mechanical properties of the fabricated silicon solar cells. Previous studies show that the residual glass frits layers at the Ag/Si interfaces after the firing process will dramatically increase the contact resistance and this phenomenon subsequently leads to degradation in the overall efficiency of the silicon solar cells. In this study, nano-sized glass frits were employed to improve the interfacial conductivity. Transfer length method (TLM) was applied to evaluate the electrical performance of samples made by different glass frits. Because of the excellent etching ability of nano-sized glass frits, the total amount of isolating compositions can be reduced and therefore there is less residual ceramic at the interfaces. For samples made with nano-sized glass frits, the specific contact resistivity was found to be only 40% of that of samples made with micro-sized glass frits after otherwise identical processing. Our results show that nano-sized glass frits can provide better energy efficiency, less processing time and lower manufacturing cost.
A New Package Structure for High Speed eStorages
Authors: Kim Hyejin , Chun Sunghoon , Hwang Jaeyeon , Kang Ilmok
Published: October 2015

Mobile storage density per chip (NAND, DRAM, etc) has increased as well with ever growing usage of high speed mobile systems. For these requirements, various eStoarge solutions (eMMC, eMCP, etc) have been developed. To optimize high speed and high density requirements in a tighter limited packaging space, we propose a new package structure using RDL(Re-Distribution Layer) on chips for optimal design with a high interface speed, smaller and cheaper package in this paper.
Hashing Processors: A New Challenge for Power Package Design
Authors: Tarter T. S. , Carrasco A. , Do N. , Felten G. , Nunn W. , Church J.
Published: October 2015

A new class of processors has emerged for high speed hashing of crypto-currency numerical constructs. The paper examines package design for processors with multiple cores running at full speed continuously and requiring high current supply at low voltages. The work described in this paper is focused on package design for high-current, high-power devices with emphasis on PDN structures and package development using state-of-the-art design, modeling and simulation toolsets.
Pre-applied Inter Chip Fill for 3D-IC Joining
Authors: Kawase Y. , Ikemoto M. , Sugiyama M. , Kiritani H. , Mizutani F. , Matsumoto K. , Mori H. , Orii Y.
Published: October 2015

For the conventional two dimensional (2D) packaging of integrated circuit (IC), reflow and capillary under fill have been used for more than a decade. But for the purpose of low power and high performance of IC, three dimensional IC (3D-IC) have been proposed in recent years. In case of 3D-IC, both bump pitches and gaps between stacked thin chips should be fine and narrow, so that pre-applied inter chip fill (ICF) which is applied in thermal compression bonding have been proposed. In this process, not only low viscosity but also thermal conductivity is simultaneously required.

In this study, some of selected epoxy based matrix and filler were simulated and evaluated for pre-applied ICF, we confirmed its process applicability to pre-applied chip bonding. Physical characteristics of cured ICF and void-less joining were also discussed.
Performance Assessment of a Low Temperature Polymer Conductor for Lead-Free Soldering Processes
Authors: Grabey Steven , Shahbazi Samson , Groman Sarah , Munoz Catherine
Published: October 2015

An increased interest in low temperature polymer thick film products has become apparent due to the rise of the printed electronics market. The specifications for these products are becoming more demanding with expectations that the low temperature products should perform at a level that is typically reserved for their high temperature counterparts; including solderability with lead free solders, high reliability and strong adhesion.

Traditionally, it has only been possible to use leaded solders for soldering to polymer based thick film conductors. Over the last 15 years environmental concerns and legislation have pushed the industry towards a lead free approach. The shift to lead free solders, while beneficial, provides new challenges during processing. The high temperatures required for a lead-free soldering process yield a naturally harsher environment for polymer thick film pastes. In the past these conditions have proven too harsh for the pastes to survive.

The polymer thick film discussed in this document aims to address some of these concerns for a highly reliable and easy to process polymer thick film paste. Due to the poor leaching characteristics of polymer thick films, at elevated temperatures, the predecessors of this paste typically soldered at low temperatures with leaded solders. The goal of this paper is to present a low temperature paste that is compatible with a variety of substrates and readily accepts lead-free solder.

This paper will discuss a newly formulated low temperature curing (150°C – 200°C) RoHS and REACH compliant paste that shows excellent solderability with SAC305 solder. The paste was evaluated using a dip soldering method at 235°C–250°C on a variety of substrates. The data presented includes solder acceptance, adhesion data, thermal analysis and SEM analysis.
Reliability potential of silicone molding compounds for LED application
Authors: Shao Yue , Shih Yu-chou , Shi Frank G.
Published: October 2015

As the development of light emitting devices (LEDs), integrate circuits (ICs) and concentration photovoltaic (CPV) modules towards higher density, packaging materials are facing the challenges of withstand with heat generation and high energy. Epoxy molding compound (EMC) is the latest technology for LED and solar cell package to replace PPA and PCT. However, it is well known that the thermal and radiation resistance of epoxy is limited. Recently, silicone based composites are attracting attention as ideal materials because they are insensible to high energy density and good resistance to UV light and heat. Epoxy and silicone both have reliability issues during long-term service at high temperature and high energy. Thermal and radiation degradation of reflector materials will largely affect their reflectance and their contribution to a higher light output and energy efficiency. Therefore, it is very essential to evaluate reliability performance of SMC and EMC based reflecting materials. Aging under multiple environmental conditions has generated considerable interest for evaluating the life and behavior of materials in a real environment. Radiation and thermal aging are two quite different types of aging. The combination of these two situations will cause the aging process to accelerate further. The objective of this study is to investigate the synergetic influence of thermal and radiation aging on optical performance of SMC and EMC based packaging materials. It is concluded that SMC is the preferred choice for packaging LEDs, ICs and solar cells for its superior thermal and radiation resistance.
Embedded Capacitive Filter Units in LTCC for the Protection of Active Implantable Medical Devices
Authors: Ordonez Juan S. , Singh Vivek , Kohler Fabian , Pfau Jennifer , Stieglitz Thomas , Schuettler Martin
Published: October 2015

We investigate the compact integration of passive capacitive filter units embedded in low-temperature cofired ceramics for active implantable medical devices. The goal lies in avoiding volume consumption by large passive components and to achieve a miniaturized integration of filters for the reduction of induced radio frequency currents and voltages during magnetic resonance imaging. Embedding such filter units inside the substrates carrying the electronics can be a promising solution for implants to allow higher channel densities with only a marginal increase in implant's size. By combining laser ablation and screen printing manufacturing technologies, we investigated a fabrication process for multilevel ceramic capacitors (MLCCs) in low temperature co-fired ceramic (LTCC) substrates resulting in mean capacitances of 220 pF, (10 × 0.4 × 0.62 mm3) with a dissipation factor of 0.42% and a breakdown voltage of 500 V. Dissolution of the material during accelerated aging tests however raises concerns over its biostability and biocompatibility during chronic implantation and needs further testing.
High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer
Authors: Sundaram Venky , Tong Jialing , Demir Kaya , Huang Timothy , Shorey Aric , Pollard Scott , Tummala Rao
Published: October 2015

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.
Advanced Build-up Materials and Processes for Packages with Fine Line and Space
Authors: Nishimura Yoshio , Narahashi Hirohisa , Nakamura Shigeo , Yokota Tadahiko
Published: October 2015

Printed circuit boards manufactured by a semi-additive process are widely used for packaging substrates. Along with increasing demands of downsizing electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to be miniaturized with high density of circuit wirings. We report our insulation build-up materials and processes for advanced packages with fine line/space and high reliability. The insulation materials we developed show low coefficient of thermal expansion (CTE), low dielectric loss tangent and good thinner insulation reliability. They can produce fine line and space (FLS) under 10μm pitch by a semi-additive process.
A Resealable Hermetic Packaging Technique for Silicon Microfluidic Devices
Authors: Smith Lilla Safford , Hoople Gordon D. , Cheng Jim C. , Pisano Albert P.
Published: October 2015

Recent efforts have lead to the development of a silicon microfluidic cooling device known as the micro-Columnated Loop Heat Pipe (μCLHP) [1] [2] [3] . The μCLHP, like a traditional heat pipe, utilizes phase change of a liquid to rapidly draw heat away from a concentrated hot spot. Proper hermetic packaging of this device is critical for the reliable testing of the recirculating fluid. This work presents a novel approach to filling and hermetically sealing the μCLHP. A miniature valve (Beswick M3SV-N) is bonded to the silicon fill ports of the μCLHP. The use of a resealable valve, as opposed to a permanent sealing method, allows the device to be filled, sealed, and then evacuated for testing with different fluids and at multiple pressures. Building on work by Murphy [4], the fill ports on the μCLHP were metalized with a 10nm Cr - 200 nm Ni - 10 nm Au stack. Then a lead based solder was used to bond the stainless steel adapter to the metalized layers. Hermeticity testing of devices sealed using these miniature valves demonstrated average hourly percent weight losses between 0.170 % – 0.821 %. While this bonding method has been developed specifically for the μCLHP, it is broadly applicable to most ceramic microfluidic devices, especially those fabricated from silicon and glass. Due to the time intensive manufacturing process of microfluidic devices made from these hard materials, a novel, robust, resealing method that allows reuse of a single silicon microfluidic device for multiple test conditions is highly desirable.
Reliability of LTCC using Electroless Nickel Immersion Gold (ENIG) Plating Technology
Authors: Graddy Patricia , Beikmohamadi Allan , Nair Deepukumar , Thrasher Brad , Parisi James
Published: October 2015

In an effort to address the impact of rising gold costs on the fabrication expense for high frequency circuits, and maintain circuit quality and reliability, the DuPont™ GreenTape™ 9K7 low temperature co-fired ceramic materials (LTCC) with top silver conductors have been evaluated using electroless nickel immersion gold (ENIG) plating. Results comparable to the quality of efficiency and reliability of traditional gold conductor systems were achieved at reduced costs.

LTCC coupons produced using the ENIG process were tested and compared to standard specifications for coupons with gold printed conductors. The test methods used include wire bond and adhesion pull tests on eight layer coupons, and MIL-STD-883 [1] temperature cycle testing on a layered high frequency test pattern. The reliability of the high frequency characteristics including insertion loss and return loss measurements were evaluated periodically throughout 1090 temperature cycles. Adequate results for most applications were obtained using the ENIG plated system compared to gold printed coupons.

In an attempt to better understand the boundaries of the ENIG process on 9K7 LTCC and its use as an alternative for gold conductor systems; future testing will explore the effects of additional environmental testing. The added tests will include thermal shock, and temperature and humidity cycling on 9K7 LTCC test coupons. The testing will be conducted in accordance with MIL-STD-883 as a benchmark, and also evaluate wire bond and adhesion properties. This paper will report the reliability test results on plated GreenTape™ 9K7 LTCC systems after exposure to the stated environmental conditions.
Zero Meta-material Ferroelectric Phase Shifter Embedded inside LTCC
Authors: Tork Hossam , Elshabini Aicha , Barlow Fred
Published: October 2015

This paper describes the design and processing of a zero meta-material phase shifter (ZMPS) embedded within a low temperature co-fired ceramics (LTCC) structure. The designed ZMPS is based on a composite right/left handed meta-material (CRLH MTM) transmission line approach. L-C networks were used to achieve zero phase shift at a specified frequency. The proposed design combines the advantages of an accurate zero phase shift using meta-material concepts and the advantages of passive components (capacitors and inductors) embedded inside LTCC to reduce device size, weight, and cost. The designed phase shifter provides an accurate 0o phase shift at 0.73 GHz with −16.7 dB return-loss and −0.31 dB insertion-loss at the center frequency. The paper also provides a comparison between BST and BZT as dielectric materials embedded inside LTCC with respect to the preparation process and shrinking effects.
A Novel Thin Wafer Handling Technology to Enable Cost-Effective Fabrication of Through-Glass Via Interposers
Authors: Lee Alvin , Su Jay , Arnold Kim , Bai Dongshun , Wang Bor Kai , Tsai Leon , Shorey Aric , Shen Wen-Wei , Chien Chun-Hsien , Chang Hsiang-Hung , Wang Jen-Chun
Published: October 2015

Thin wafer handling technologies to fabricate silicon interposers have been widely discussed at conferences. Despite tremendous efforts to overcome several technical hurdles such as wafer chipping, cracking, and warpage, high manufacturing costs resulting from the complexity of the processes used to make silicon interposers remains a major concern.

Fabricating a through-glass via (TGV) interposer using novel thin wafer handling (TWH) technology will be presented here as an example of a simple and cost-effective solution for realizing 2.5-D IC integration. Utilizing a simplified TWH technology, a TGV interposer with 30-μm-diameter vias to eliminate the isolation layer is combined with polymer-based polybenzoxazole (PBO) as passivation to build one to two redistribution layers (RDLs) with 20-μm line width on both sides after thinning to 100 μm. The simplified TWH requires only a release layer on the glass carrier and another layer of bonding material on the TGV wafer to enable fabrication of a TGV interposer.

A process flow for fabricating a TGV interposer utilizing a simplified TWH technology will be presented in detail, including carrier treatment, bonding material, bonding, titanium/copper seed layer deposition, copper plating, RDL deposition, under-bump material (UBM) formation, debonding, and silicon chip stacking on a TGV interposer. The combination of TGV interposer and novel TWH technology will pave the way for cost-effective fabrication in 2.5-D IC.
Osteolysis Affecting the Jaws in Systemic Sclerosis: Clinical and Osseous Changes Based on a Case Presentation
Authors: Delantoni A. , Matziari E.
Published: October 2015

Objectives

The aim of the current paper is to present a case of systemic sclerosis of the jaws with all the characteristics and some extensive findings.

Methods

Systemic sclerosis is a connective tissue condition characterized by chronic inflammatory changes, presenting with a number of symptoms. The paper aims to present a case of systemic sclerosis that had some of the characteristics of the condition unilaterally. The features were prominent and well demarcated on the panoramic radiograph.

Results

The panoramic radiograph of the patient showed extensive condylar head resorption almost to the level of complete flattening.

Discussion

The rarity of the condition and the awareness the oral radiologist must have upon presentation of similar images is the main reason for the presentation of the case. The features the case presents are both characteristic and well demarcated. Finally, the authors try to alert the clinician, who should be mindful of the fact that sclerodermatous involvement of organ systems is so pleotropic, that it may include the oral cavity, which is not always thoroughly observed, and is often left unattended by medical practitioners.
Impact of the Stem Extract of Thevetia neriifolia on the Feeding Potential and Histological Architecture of the Midgut Epithelial Tissue of Early Fourth Instars of Helicoverpa armigera HÜbner
Authors: Mishra Monika , Gupta Kamal Kumar , Kumar Sarita
Published: October 2015

Helicoverpa armigera HÜbner is one of the most important agricultural crop pests in the world causing heavy crop yield losses. The continued and indiscriminate use of synthetic insecticides in agriculture for their control has received wide public apprehension because of multifarious problems, including insecticide resistance, resurgence of pest species, environmental pollution, and toxic hazards to humans and nontarget organisms. These problems have necessitated the need to explore and develop alternative strategies using eco-friendly and biodegradable plant products. In view of this, the efficacy of Thevetia neriifolia methanol stem extract was evaluated against the early fourth instars of H. armigera as an antifeedant and stomach poison agent. Feeding of larvae with the diet containing 0.005%–5.0% extract resulted in 2.06%–37.35% antifeedant index; the diet with 5.0% extract caused 54.3% reduced consumption. The negative impact of extract on larval feeding resulted in 37.5%–77.7% starvation, causing adverse effects on the larval weight. Choice between control and experimental diet resulted in feeding preference of larvae for the control diet, leading to 7.3%–42.9% reduced consumption of extract-containing diet. The only exception was the diet with 0.005% extract, which could not cause any deterrence. The midgut histological architecture of H. armigera larvae fed with 0.005%–0.05% extract-containing diet with negligible antifeedant potential showed significant damage, shrinkage, and distortion and vacuolization of gut tissues and peritrophic membrane, causing the disintegration of epithelial, goblet, and regenerative cells; the damage increased with the increase in concentration. These changes in the gut caused negative impact on the digestion and absorption of food and thus nutritional deficiency in the larvae, which could probably affect their growth and development. This study reveal the appreciable stomach poison potential of T. neriifolia stem methanol extract against H. armigera larvae, which can be explored as an eco-friendly pest control strategy.
تقديم
Authors: Yousuf Al-Mannai Aisha
Published: October 2015

تسعى مجلة أديان للتطبيق أسس الديموقراطية من خلال "حرية العقيدة وحرية الفكر والتعبير الآمن المطمئن". وتهدف المجلة لخلق بيئة تسمح "لقبول الآخر والتحاور معه" بهدف التعارف والتفاهم والتحاور بين الأديان.
الافتتاحية
Authors: Laude Patrick
Published: October 2015

يعرب رئيس التحرير عن ضرورة الحوار والتواصل بين الأديان من أجل التعارف والتفاهم و"بقصد تحقيق تعايش سلمي"، وذلك بسبب تزايد سوء التفاهم ما بين الأديان مما أدى إلى "عدم الثقة….والعنف بلا معنى".
لقاء مع السيد حسين نصر
Authors: SHN SHN
Published: October 2015

من خلال المقابلة يتطرق حسين نصر إلى وضع الدين ومفهوم الأديان في عصرنا الحالي الذي يدور حول "عالماً قائماً على نسيان الله". وبالرغم من ذلك فإن السيد نصر متفائل بأن هناك فرص تسمح للأديان أن تُسمع صوتها للعالم من دون أن تعد التعددية الدينية خطراً. حيث أن السيد نصر يقوم بالتطرق إلى التعددية الدينية من منطلق تاريخي، ويوضح الدوافع التي أظهرت الدين بشكل نسبي، بالإضافة إلى مناقشة أهمية معرفة القواسم بين الأديان. ومن خلال المقابلة يقوم السيد نصر بشرح ومناقشة الوقائع التي تمر بها المفاهيم عن الدين والأديان، بالإضافة إلى ذلك يتطرق السيد نصر للحديث عن دور الإسلام والمسلمين في حوار الأديان من منطلق إجتماعي وديني، ويناقش بعض من العوائق التي تحد من حوار الأديان في العالم الإسلامي.
أمة الله الواحدة
Authors: George Khodr Bishop
Published: October 2015

يناقش الكاتب مفاهيم جوهرية في الإسلام والمسيحية ألا وهي التوحيد، ويستشهد الكاتب بالآيات والأحداث التاريخية. مما يسمح للكاتب أن يقارن بين أوجه التشابه والإختلاف بين الإسلام والمسيحية من عدة مفاهيم مثل: الله والتوحيد والرحمة. ويقوم الكاتب بذلك من أجل حث القارئ أن "ما ييسر اللقاء الفكري هو [أن] تفهم الإسلام من مصادره والمسيحية من مصادرها". بالإضافة إلى ذلك يتطرق الكاتب للفكر اللاهوتي من خلال أوجه التشابه بين أسماء الله. ومن ثم ينتقل ليناقش الكاتب علاقة الله والناس في الإسلام والمسيحية. بالإضافة إلى ذلك يتطرق الكاتب إلى التفاعلات بين المجتمعات المسلمة والمسيحية في الدول العربية.
صورة الإله في الإسلام: التقاء وافتراق مع الأديان السماوية
Authors: Yousuf Al-Mannai Aisha
Published: October 2015

تتطرق الكاتبة إلى مناقشة مفهوم الإله في الأديان السماوية الثلاثة - اليهودية والمسيحية والإسلام - وبالأخص في الإسلام، وتلجأ إلى إيجاد أوجه الإلتقاء والتشابه في صورة الإله من خلال الديانات السماوية بالإضافة إلى التطرق إلى الإختلافات فيما بينهم. وتتناول الكاتبة مفهوم "الحقيقة الإلهية الواحدة" المشتركة بين الأديان السماوية ولكن في نفس الوقت تتطرق إلى أن صورة الإله تختلف في الأديان السماوية وليست متحدة في جميع المفاهيم والعبادات. ومن ثم تنتقل الكاتبة إلى الاستدلال ومناقشة وصايا سيدنا موسى وسيدنا عيسى والرسول محمد، بالإضافة إلى التطرق لفكرة أن رسالة الإسلام "مكملة للرسالتين السابقتين، وأن الأنبياء كلهم أخوة ودعوتهم واحدة".