Lithiation of Oxidised Silicon
Authors: Schnabel Manuel , Arca Elisabetta , Teeter Glenn , Ban Chunmei , Stradins Pauls 
Published: February 2020

The electrochemical energy storage market is growing rapidly, and is currently dominated by lithium ion batteries. Replacing the standard graphite anode with silicon, whose theoretical gravimetric capacity is roughly ten times higher, promises a step-change improvement in capacity. Unfortunately, the use of silicon in lithium ion battery anodes frequently leads to poor cycle life, related at least in part to the challenges in creating a stable solid-electrolyte interphase (SEI). This issue is made more complex by the fact that the silicon used in composite anodes is typically nanostructured, with a poorly defined and often oxidized surface, especially when the silicon was prepared at elevated temperature. SiOx has been proposed as an alternative anode material to Si, whereas SiO2 is an electronic insulator. It is therefore valuable to understand the effect of surface oxides in more detail.

In this work, we take a fundamental approach to understanding how an oxide on a silicon surface affects SEI formation and lithiation. Silicon wafers with precisely controlled thermal SiO2 thicknesses were prepared by thinning thicker oxides down to 1-30nm SiO2 using buffered hydrofluoric acid solution. These wafers were then cycled against a Li counter and reference electrode in Gen2 electrolyte (1.2M LiPF6 in EC:EMC (3:7 by wt.)) using custom three-electrode cells, which use an O-ring seal on the silicon to prevent contact between the electrolyte and the edges or rear of the wafers.

Galvanostatic cycling at 20µAcm-2 indicates that while Si with 1nm SiO2 will lithiate above 0V vs Li, Si with 3nm SiO2 will only lithiate after a potential spike to -0.4V vs Li. Thereafter, it actually cycles with higher Coulombic efficiency (CE) than Si with 1nm SiO2. However, Si with 5-30nm SiO2 initially requires voltages below -1.0V vs Li to sustain 20µAcm-2, resulting in localized Li plating at pinholes in the SiO2 rather than lithiation. The voltages required to induce this pinhole plating will be compared to the dielectric breakdown strength of the SiO2 layers.

To understand these phenomena in more detail, cyclic voltammetry (CV) was performed on Si with 1-5nm SiO2 (1mV/s, see abstract figure). Lithiation only occurred in the 1.0nm sample in the first cycle, but by the fourth cycle, lithiation occurred in samples with up to 2.9nm SiO2. Samples with 3.9nm and 4.8nm SiO2 on the other hand exhibit no lithiation or reversible electrochemistry during ten CV cycles. Two distinct delithiation peaks are observed for 1.0 and 1.4nm SiO2, but only the higher-voltage peak is observed for the 2.9nm SiO2, suggesting a unique delithiation chemistry that may be correlated to the high CE during galvanostatic cycling, and which will be studied by XPS. The peak currents (0.05V for lithiation, 0.5V for delithiation) decrease exponentially with SiO2 thickness, indicating that tunneling electron transfer across the SiO2 may play a key role in the reaction kinetics.

Overall, we find that dense thermal oxides of 5nm or more severely impede lithiation, whereas 1nm SiO2 allows lithiation to proceed unimpeded. Intermediate thicknesses of ~3nm alter the delithiation chemistry while yielding improved CE during galvanostatic cycling. These effects will be discussed in relation to the bonding of the SiO2 network in thermal oxides, as compared to native or sputtered oxides.

Figure 1