(Invited) Temperature Influence on Current Leakage and Hysteresis of Nc-CdSe Embedded Zr-Doped HfO2 High-k Dielectric Nonvolatile Memory
Authors: Zhang Shumao , Kuo Yue 
Published: February 2020

The nanocrystals embedded high high-k gate dielectric structure can replace the poly-Si floating-gate dielectric structure in nonvolatile memories (NVMs) for advantages of the low leakage current and improved reliability [1]. The Zr-doped HfO2 (ZrHfO) high-k film has better bulk and interface properties than those of the undoped film with respect to the crystallization temperature and interface density of states [2]. The nanocrystalline cadmium selenide (nc-CdSe) embedded ZrHfO NVM has exhibited excellent charge storage and retaining capacitiess [3]. Most studies on this kind of device were done at room temperature [4]. Since the temperature of the high density integrated circuit on a board can be much higher than the room temperature [5], it is imperative to understand the temperature influence on charge transferring mechanisms. In this paper, authors studied the temperature effect on the leakage current characteristics of the nc-CdSe embedded ZrHfO MOS capacitor.

                The ZrHfO/nc-CdSe/ZrHfO tri-layer stack was sputter deposited on the dilute HF cleaned p-type Si (100) wafer in a one pumpdown process without breaking the vacuum. The post deposition annealing was done at 800°C for 3 min under the N2 condition. The ITO film was deposited and wet etched into the gate electrodes. The final annealing was done at 400°C for 5 min under the H2/N2 atmosphere. The control sample contained the 12-min sputter deposited ZrHfO prepared under the same process condition. The detailed device fabrication process can be found in ref. 3.

                Figure 1 shows J-V hysteresis curves of the (a) control and (b) nc-CdSe embedded samples with the gate voltage (Vg
) swept from -4 V to +4 V to -4 V at 20°C, 70°C, and 120°C, separately. In the small Vg
 range of -2 to +2 V, the control sample has a larger leakage current than those of the nc-CdSe embedded sample. The is because the nc-CdSe embedded sample can trap charges in the nc-CdSe bulk or at the nc-CdSe/ZrHfO interface. The bulk ZrHfO film traps negligible amount of charges. In the control sample, charges can be easily transferred through the ZrHfO bulk, which shows as a large leakage current. In the nc-CdSe embedded sample, they are trapped at shallow or deep trapping sites, leading to a smaller leakage current. At the raised temperature, charges gain higher thermal energy and are easily transferred through the bulk ZrHfO film, which enlarges the leakage current. However, in the nc-CdSe embedded sample, the energy is still not high enough to overcome the energy barrier between nc-CdSe and ZrHfO at a small electric field. Therefore, the nc-CdSe embedded sample has a slightly larger leakage current at the high temperature. In the C-V hysteresis study, it was found that when the temperature was increased, the interface state density (Dit
) of the nc-CdSe embedded sample increased but that of the control sample did not change much. At the raised temperature, the Si/high-k interface is damaged by the charge transfer process but the bulk film was little damaged.

                Figure 2 shows that in the negative Vg
range, holes are transferred through the nc-CdSe embedded sample following (a) the Schottky emission mechanism in the low electric field range and (b) the Poole-Frenkel (P-F) mechanism in the large electric field from 20°C to 120°C. This is in agreement of the literature report that the Schottky emission happens under the low electric field but the F-P emission needs the high electric field condition [6].

                Figure 3(a) shows that in the positive Vg
range, for the nc-CdSe embedded sample, electrons are transferred through the nc-CdSe embedded sample following the Schottky emission mechanism in the low electric field range over the temperature range of 20°C to 120°C. However, it changes to the Fowler-Nordheim (F-N) tunneling mechanism at the high electric field. The transition occurs faster with the increase of the temperature. For example, it is around E1/2 ~ 1700 (V/cm)1/2 at 120oC, while the Schottky emission still dominates around the same region at 20oC and 70oC.

[1] C.-H. Lin and Y. Kuo, J
AP,
110, 024101 (2011).

[2] J. Lu and Y. Kuo, APL, 87,232906 (2005).

[3] C.-C. Lin and Y. Kuo, JAP, 115, 084113 (2014).

[4] C. H. Yang and Y. Kuo, MRS Symp. Proc., 1071-F02-09 (2008).

[5] T. Y. T. Lee et al, IEEE Trans. Comp. Packag. Manufact. Technol.,
17, 564 (1994).

[6] C.-L. Cheng, et al, APL, 86, 212902 (2005).

Figure 1