bluuebunny/crossref_metadata_2025 huggingface dataset:
Enabling Packaging Houses to Achieve 3D Integration without Interposers
Authors: Leal Jeff , Robinson Marc , Pangrle Suzette
Published: October 2015

The growth of small portable consumer electronics has increased the requirements of creating densely stacked packages with ever decreasing footprints while still increasing storage capacities as well as accessible memory. Traditional approaches to create these packages have included wire-bonding and Package on Package (PoP) as well as through Silicon Via (TSV). All of these methods present a solution to current system requirements, each with its own drawback.

This paper will discuss a novel method in which a vertical 3D die stack can be created of similar an in some cases dissimilar die. The final 3D structure of stacked die will present no XY offset between any level of the die stack achieving the smallest possible form factor. This method also eliminates the requirements of creating an interposer for the electrical connection between layers.

The final result is a completely vertical die stack with electrical connections drawn on the outside edges of the die stack which adds <400um total in either the X or Y axis of the package. We will discuss required equipment, the best known methods and the optimal materials required to achieve the final product as well as JEDEC reliability data proving package robustness, such as Temperature Cycle, biased-HAST and High Temperature Storage.
Advanced Substrate Applied Fluxing Underfill for Bonding of Fine Pitch Solder Capped Cu Pillars to Oxidized Cu Substrates
Authors: Stapleton Russell , Greig Jim
Published: October 2015

Underfill solutions for fine pitch flip chip assemblies is an active area of development. Non-conductive films (NCF) and pastes (NCP) have shown great potential in bridging the gap between no-flow and capillary underfills for improving the reliability of fine pitched devices. But NCFs and NCPs require costly passivated pad finishes (e.g. Au, Sn, Ni, OSP) or careful substrate handling for proper solder joint formation. In this paper, we will describe a new class of underfill material that benefits from the growing trend of using thermal compression bonding as a cost effective alternative to mass reflow based underfilling processes (e.g. capillary and no-flow). This material is a fluxing NCP that is useful for a wide variety of fine pitch substrates, including low cost Cu. The material we will demonstrate contains many advanced features: high filler loading, strong flux activity, long work life, off-tool pre-dispense, low stress, high Tg, high modulus and rapid cure. The all-in-one underfill demonstrated in this paper is applied by using a screen printing process, where the material is applied to all of the chip sites in one step achieving excellent application efficiency and wetting/conformity to the substrate. The substrate is glass, containing a 4x4 array of die sites. Each of the die sites are 5x5mm in size with a full area array of 2501 Cu pads (50um pads on 100um pitch) that are pre-oxidized for 1h at 175C in air prior to printing (to simulate a dehydration bake). This transparent substrate was chosen to show the robust nature of the underfill for fluxing, stability and void-free placement/cure. Images of the substrate, before and after chip bonding will be given, along with cross sections. Details of the material properties will also be discussed.
Development of Lead Free Plating Chemical for Various Applications
Authors: Hatta Takeshi , Ishikawa Atsushi , Katase Takuma , Masuda Akihiro
Published: October 2015

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging.

Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world.

In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production.

In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability.

We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.
Super Fine Lead-Free Solder Powder for Fine Pitch Bump Applications
Authors: Uesugi Ryuji , Uno Hironori , Ishikawa Masayuki , Masuda Akihiro , Muraoka Hiroki , Kawamura Yousuke , Nakagawa Sho , Kuba Kanji
Published: October 2015

We have successfully developed super fine lead-free and low alpha solder powder, which contains more than two elements by the method of wet chemical reduction. The size (D50) of super fine powder is around 2–3 micrometer to meet finer pitch assembly in the near future. This new method made it available to synthesize various compositions of solder powder like Sn-Ag, Sn-Cu, Sn-Ag-Cu, etc. Also, this method achieves very high yield compared to a gas atomization method.

A solder paste for printing method composed of the fine solder powder has a superior printing ability because of the unique powder shape. The powder shows anisotropic shape, and it can make printed figure excellent after printing without bridge and coplanarity issues for finer pitch applications. With our super fine solder paste, we will be ready for <100um pitch of solder bumps which will come in a few years.

Furthermore, the super fine powder is applied to the Cu pad pre-coat. The solder paste for pre-coat composed of the super fine powder shows an excellent coverage and solders flatness on the outer pad after reflow.
Passive Flexible-Substrate Blast Sensor Array
Authors: Phillips Stephen M. , Allee David R. , Lakamraju Narendra
Published: October 2015

We have developed a design for a wearable passive blast sensor array to detect the peak shock experienced by personnel exposed to high energy events. The sensor is fabricated on a flexible substrate using a MEMS process. The design includes an array of sensors, each element of which is triggered at a different pressure level and which records the peak pressure by means of a permanently deformed diaphragm. The elements can be integrated with a flexible electrophoretic display or can be interrogated externally with an electronic reader.

A key application is in predicting the exent of traumatic brain injury for military peronnel exposed to explosions in a battlefield environment. Peak blast information can assist in prioritizing and determining the appropriate battlefield treatment. The flexible substrate allows integration into personal armor or clothing and the passive nature of the sensor ensures a very long shelf life and reduces cost and maintenance.

Details of the sensor designs and process flows for their fabrication are described. Prototype sensors have been fabricated and the fabrication characterized. Also included are simulation results for the preforamnce of the arrays. Finally, preliminary pressure blast test data for indivdual sensor elements are presented.
Rigid and Flex PCB Based Microsystems for Mobility, Systems Development and Harsh Environments
Authors: Fries David , Barton Geran , Hendricks Gary , Gregson Brian , Hotaling Liesl
Published: October 2015

The exploration of PCBMEMS as a path towards systems development continues. PCBMEMS technology based on rigid-flexible laminates is desirable for miniaturization and integration of systems for mobility and harsh environment deployments. The technology provides substantial flexibility in systems design and integration of multiple functions into limited spaces. Using this design and construction approach allows lightweight, complex, and space efficient systems. Flex microsystems based on structurable, non-fiber filled laminates permits miniaturization to occur at two levels: at the micro scale with the embedding of microstructures in the substrate, and at the macro scale with the ability to flex the system across millimeter to centimeter lengths of real everyday systems. Examples will be given where the technology is being applied toward several different systems including mobile chemical analyzers, heat and mass transfer devices, portable therapeutics, augmented mobile phone systems, and high density microfluidics-based robotics.
Testing of Flexible Metamaterial RF Filters Implemented through Micromachining LCP Substrates
Authors: Dean Robert , Richard Jonathan
Published: October 2015

Metamaterials have a wide range of potential uses in areas such as optics, transmission lines, and RF design. The simplest metamaterial structures are Split-Ring Resonators (SRR) and Complementary Split-Ring Resonators (CSSR). Through the combination of various forms of these structures, different applications in the areas previously stated can be achieved. Under this investigation, a metamaterials transmission line was realized through micromachining a Liquid Crystal Polymer (LCP) substrate. Not only does LCP possess useful RF properties, it is flexible and micromachinable. This transmission line consisted of several CSSRs in series, which performed as a high-order, high-frequency filter. This structure was unique to most metamaterial structures because LCP is a flexible substrate. Prototype filters were fabricated and evaluated. One test involved flexing the devices over various radii of PVC pipe sections to evaluate the effects of flexing the substrate on the filter's performance. The filter properties were shown to maintain approximately the same frequency and roll-off while being bent over the various radii of curvature. Therefore, arrays of these filters could be fabricated with planar processes and attached to non-planar surfaces, such as airfoils, for uses such as radar cloaking.
Polymer-Based Hermetic Packaging for Flexible Micro Devices
Authors: Liew Li-Anne , Lin Ching-Yi , Lee Y. C.
Published: October 2015

In recent years, polymers have been widely adopted as a low-cost, light-weight and high-flexibility alternative to traditional silicon materials for MEMS. However, the majority of polymers do not provide hermetic protection because of their high moisture- and gas permeation rates. Yet, hermetic packaging is critical for many applications such as medical devices [1], RF MEMS [2] and micro heat pipes [3]. In particular, our group has been developing flexible thermal ground planes based on heat pipe technology [3] for advanced electronics cooling applications. Heat pipes require hermetic sealing, while flexibility requires the structural material to be polymer-based. Hermetic packaging methods for MEMS typically include welding, soldering [4], and various epoxies and polymers [1, 2, 5] to bond the parts in a package together. The bond interface is a major potential source of gas and moisture leakage. Although welds and solder joints offer effective hermetic seals, the bond interface is mechanically rigid. On the other hand, flexible bond materials like epoxies typically possess high moisture absorption rate and bonding strength degradation at high temperature [6] while polymers such as BCB [2] or LCP [7] either provide only semi-hermetic sealing or degrade at high temperature. We report a polymer-based hermetic packaging approach using fluorinated ethylene propylene (FEP), which possesses flexibility, high operating temperature compatibility (204°C), chemical resistance, and low water absorption rate. We report results of hermeticity tests in which FEP, solder, and epoxy were used to bond a copper-clad kapton “lid” onto a water-containing copper vessel which is then kept in an oven at 100 °C. The only path for water loss is through the bond interface. We show that the FEP-bonded test vehicles result in negligible water loss comparable to the solder-bonded containers, and far outperforming the epoxy-bonded containers. References: [1] G. Jiang and D. D. Zhou (Ed.), Implantable Neural Prostheses 2, (2010). [2] A Jourdain, P De Moor, K Baert, I DeWolf and H A C Tilmans, J. Micromech. Microeng.,15 (2005) S89–S96. [3] C.J. Oshman, B. Shi, C. Li, R. Yang, Y.C. Lee, G.P. Peterson, and V.M. Bright, J. Microelectromechanical Systems, 20, 2 (2011), 410–417. [4] T. Rude, J. Subramanian, J. Levin, D. Van Heerden, O. Knio, Proc. IMAPS 2005. [5] G. B. Tepolt, M. J. Meschera, J. J. LeBlanca, R. Lutwakb, M. Varghesec, Proc. of SPIE, Vol. 7592, 2010, 759207. [6] E. M. Petrie, Handbook of Adhesives and Sealants, 1st Ed. (McGraw-Hill, 1999), p. 707. [7] C.-D. Ghiu, S. Dalmia, J. Vickers, L. Carastro, W. Czakon, V. Sundaram, G. White, Proc. 1st European Microwave Integrated Circuits Conference, 2006, pp.545–547.
Ultra High 3D Capacitors Values with High Volume Efficiency and Outstanding Stability
Authors: Bunel Catherine , Murray Franck
Published: October 2015

IPDIA's primary effort is to develop innovative 3D technologies to integrate Passive Devices .One of their key technology drivers is the trench high-density capacitor.

After introducing the 250nF/mm2 in mass production, it's now the turn to launch outstanding performances with a new worldwide record of 550nF/mm2.

With the advanced packaging solutions using very thin dies stacking ,combining a high level of capacitance integration and high volumetric efficiency, this achievement will enable to extend the range of high reliability Silicon Capacitor values up to 10 μF in a package size 3.4mm*2.4mm*1.4mm and even smaller .

This paper will provide the details to prove that the former ambitious target of 2 μF/mm3 is now close to reality.
Micromachined High Density Embedded Capacitor Technologies for Silicon Interposers
Authors: Beal Aubrey , Baginski T. , Dean R. , Hamilton M.
Published: October 2015

We describe our work on micromachined, large surface area, thin and high-density capacitor technologies targeted at the growing interest and applications for embedded passive devices in thin silicon interposers. As integrated circuit I/O number, speed and density increase, chip current requirements grow and margins shrink leading to the requirement of large, distributed decoupling capacitance as close to the load as possible. The simple fabrication methods used to form our embedded capacitors can be used to alleviate the increasing demand for low impedance power distribution networks in high-density integrated electronic systems while maintaining required signal integrity through the interposer.

We have investigated silicon dioxide-based capacitors of varying oxide thickness, with and without integrated parallel metal Schottky barrier capacitors or pn junction capacitors. These device structures have been fabricated using standard MEMS processing techniques such as DRIE and thermal oxidation to enhance the available surface area and increase capacitance per chip foot-print.

We have characterized the performance of the various capacitor structures using both time and frequency response measurements. Time response measurements are performed using a capacitive charge and discharge ringdown test. High frequency (> 1GHz) performance characterization and modeling of these devices has also been performed. In general, measurement results correlate with simulation. We will describe the challenges associated with fabricating, testing and integrating these passive devices.

On-going measurement and simulation work that will be reported includes modification of device structures to evaluate the range of achievable capacitance density, minimize leakage current, minimize effective series inductance / resistance, and achieve thinned capacitor structures integrated into our Si interposer technology that incorporates electroplated through-Si vias (TSVs) of varying sizes and densities. The results of these efforts will be presented.
Active and Passive Devices Embedded in Laminate-Based Multilayer Board
Authors: Okude Satoshi , Itoi Kazushisa , Okamoto Masahiro , Ueta Nobuki , Nakao Osamu
Published: October 2015

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging.

Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.
3D Integration of RF Package
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Kim Gwang , Ahn Billy
Published: October 2015

As form-factor has been one of the key drivers for mobile devices, 3D integrations that make the use of vertical dimension have been widely explored. Conventional side-by-side approaches, for implementing memory devices, controlling circuits, baseband devices, application processors, RF devices, etc., have been replaced by package-on-package (PoP) or other 3D approaches. One key issue for 3D approaches is to maintain signal integrity, which is typically not the bottle-neck for side-by-side solutions. For an RF stack-die package, where at least one of the chips in the configuration is RF chip, having either active or passive function, the interference or cross-talk between the chips in a package may severely deteriorate the signal integrity, and may make the package malfunction. In this paper, we will describe a RF stack-die package where a RF transceiver chip and an IPD chip are implemented. Chip-to-chip interference directly by individual components (e.g., between inductor coils in different chips), and through the power feeding lines (or power distribution networks) in the IPD chip and in the laminate substrate, is investigated. Based on this analysis, proper arrangement of the off-set between the two chips is applied in the final package design, and is approved to be able to overcome a receiver sensitivity issue occurred in the previous version of the package.
Thermal Challenges in 3D Stacks
Authors: Narasimhan Susheela , Chu Herman , Ahmad Mudasir , Li Li
Published: October 2015

Thermal Management of high performance 3D SiP Modules is gaining momentum in telecommunication and networking applications. With increasing need for bandwidth and reduced real estate on boards, there is an acute need for 3D SiP modules. At the same time, the stacked modules come with a host of new challenges in terms of thermal management, packaging, thermo-mechanical stresses etc. This study looks at one such module with stacked dies for memories along with another high performance silicon all under a single lid. The study focuses on the effect of underfill materials on thermal performance, effect of through silicon vias, effect of non-uniform heat source on hot spots on the die etc. It will also focus on thermal management of a single module as well as a series of modules in a networking application. The effect of thermo-mechanical stresses will also be investigated and conclusions drawn on the effect of each of these parameters.
A Methodology for Chip - Package Interaction (CPI) Modeling in 3D IC Structures
Authors: Dhandapani Karthikeyan , Syed Ahmer , Lin Wei , Nakamoto Mark , Zhao Wei , Radojcic Riko
Published: October 2015

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require an ability to model and evaluate the interactions and risks.

In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Examples of these effects are ball cracking, ILD/ELK cracking or delamination and shifts in the behavior of sensitive devices such as transistors in analog circuits.

Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates a seamless interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. This package level simulator uses a nested sub-modeling approach for detailed extraction of stresses at different locations within BEOL layers of die, u-bumps, and C4 bumps from package level simulations. Additionally, it allows complete flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online.

The capabilities of this modeling approach are demonstrated by studying the impact of design and material parameters on stresses at various interconnect structures constituting a typical 3D IC stack package. An example of active silicon layer stress correlation from package level model and die-level model will be presented, thus validating this overall modeling flow.
Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking
Authors: Choubey Anupam , Anzures E. , Dhoble A. , Fleming D. , Gallagher M. , Lee I. , Oliver M. , Qin Y. , Truong C. , Wang Z. , Woertink J.
Published: October 2015

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance.

Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.
ChipletT, A Cost-Effective, High Reliability, Embedded Die Fan-Out Package Based on Multilayer Flex Laminate with Enhanced Thermal Performance
Authors: Sivaswamy Senthil , Tessier Theodore (Ted) G. , Curtis Tony , Clark David , Itoi Kazuhisa , Okamoto Masahiro , Sano Yoshinori , Ueta Nobuyuki , Okude Satoshi , Nakao Osamu
Published: October 2015

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed.

ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning.

Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.
High Density Attachment of HB-LED Die to Heat Sink Surfaces Using Aerosol Jet Printing
Authors: Christenson Kurt K. , Renn Michael J. , Paulsen Jason A. , Bourassa Justin J. , McDonald Kelley M.
Published: October 2015

High LED junction temperature leads to reduced LED output and color shift, and are a factor in most LED failure mechanisms. Every interface and layer of packaging between the junction and the heat sink increases the device operating temperature necessitating more aggressive heat sink design. Packaging also increases the footprint of the device, limiting packing density. The ideal design would have the bare LED die attached directly to the heat sink with a micron-scale bond of thermally conductive adhesive. This paper discusses the use of an Aerosol Jet ® system to create micron-scale bonds of adhesives for both top and bottom-side (flip-chip style) connections. The system is also used to write topside connections, replacing wire bonding.

In order to limit the temperatures of LED junctions with power densities of 250 W/cm2 to below 100 °C, it is necessary to limit the thermal resistance of a direct die-heat sink bond for a 0.4 W, 0.16 mm2 die to approximately 100 C/W. Assuming 50% coverage, this implies a thickness of approximately 1.5 um for an unfilled adhesive (K=0.2) or 40 um for a filled adhesive (K=5). For a 0.16 mm2 die this requires an adhesive volume of 65 pl and 1600 pl respectively, far below the 17,000 pl in the 8 mil hemisphere from a syringe dispense. Aerosol Jet systems are able to produce patterned deposits with total volumes in the 100 pl range. This paper will describe the results of work with top and bottom-side attachment of 450 nm InGaN LED die to thermally conductive substrates.
Hybrid Bonding Methods Using Ultra Precision Cutting for 3D-SIC
Authors: Sakai Taiji , Imaizumi Nobuhiro , Mizukoshi Masataka , Kawase Masayuki , Tanimoto Ryoji , Mori Takashi , Takeda Kohei , Enami Toshio
Published: October 2015

We have developed Cu-Cu/adhesives hybrid bonding technique by using collective cutting of Cu bumps and adhesives in order to achieve high density 3D-SIC. It is considered that progression of fine pitch interconnection leads to lower height of bonding electrodes, resulting in narrow gap between 3D-SICs. Therefore, it is difficult to fill in adhesive to such a narrow gap 3D-SICs after bonding, so we consider that hybrid bonding of pre-applied adhesives and Cu-Cu thermocompression bonding must be advantageous, in terms of void less bonding and minimizing bonding stress by adhesives and also low electricity by Cu-Cu solid diffusion bonding.

In the present study, we adapted the following process; at first adhesives were spin coated on the wafer with Cu post and then pre-baked. After that, pre-applied adhesives and Cu bumps were successfully cut by single crystal diamond bite. Typical adhesives may cause bite damage with continuous cutting, but in this research, we selected low damage adhesive against continuous cutting, which is important properties to commercial uses. Then, chips with adhesives were attached to substrates and Cu oxidation layer was removed by exposing formic acid atmosphere. Finally permanent bonding was done at 225 degree C for 30 minutes. We concluded that solid diffusion between bonded Cu bumps could be achieved and no adhesive residue could be seen between bonded interfaces by TEM/EDX analysis.
Room Temperature Debonding - An Enabling Technology for TSV and 3D Integration
Authors: Matthias Thorsten , Pabo Eric , Burggraf Juergen , Burgstaller Daniel , Wimplinger Markus , Lindner Paul
Published: October 2015

Thin wafer processing is a critical technology for TSV manufacturing and 3D integration. Thin wafer processing allows to reduce the aspect ratio of the vias, thereby reducing the total processing cost and enables ultra-thin packages for handheld applications. Temporary bonding to a rigid support carrier and debonding after backside processing have been used for thin wafer handling/processing for many years. However, so far all the debonding methods imposed severe limitations on the manufacturability. For light induced debonding the carrier had to be transparent and for solvent based debonding the carrier had to be perforated. For thermally induced debonding, “slide-off debonding” the debonding temperature had to be below the reflow temperature of the solder bumps, which limited the maximal process temperature of the adhesive.

In this paper we describe a new debonding method at room temperature. This new technology decouples the debonding process from the adhesive properties, which creates a de facto material independent debonding standard. As the debonding process does not rely on the adhesive properties a major boundary for adhesive engineering has been removed. The debonding method is compatible with bumps or pillars in the bond interface as well as on the backside of the wafer stack. No force is applied on the bumps during debonding which results in very high yields.
Laddered-UBM Structure: Bump Reliability Improvement through Distribution of Load Concentration Points
Authors: Topacio Roden
Published: October 2015

Flip-chip mounting schemes have been used for decades to mount semiconductor chips to substrates. In flip-chip process, a solder bump is metallurgically bonded to the under-bump-metallurgy, also known as UBM, on a given pad of the semiconductor chip and a pre-solder is metallurgically bonded to a corresponding pad of the substrate. Thereafter the solder bump and the pre-solder are brought into proximity and metallurgically bonded using reflow.

Flip-chip solder joints are subjected to mechanical stresses from a variety of sources, such as coefficient of thermal expansion mismatches, ductility differences and circuit board warping. Such stresses can subject the conventional UBM structure to bending moments specially during the flip-chip reflow solder solidification stage where the bump is still unprotected by the underfill. The effect is somewhat directional in that the stresses tend to be greatest nearer the die edges and corners and fall off with increasing proximity to the die center. The bending moments associated with this so-called edge effect can impose stresses on the dielectric film beneath the UBM structure that, if large enough, can produce fracture.

This paper will discuss the load distribution on a conventional UBM structure due to the bending moments and how the Laddered-UBM structure attempts to overcome or reduce the effects of these bending moments. Contrary to conventional methods where stress concentration points are eliminated, the Laddered-UBM is designed to strategically increase the number of load concentration points along the UBM structure. With the increased number of load concentration points, the stress along the UBM is distributed more evenly which effectively reduces the stress at any given point thus preventing a single large enough stress to cause dielectric fracture. Theoretical analysis and experimental data including reliability results on both the conventional UBM structure and the Laddered-UBM structure will be presented and discussed in this paper.
Through Glass Via (TGV) Solutions for Wafer and Chip level Interposers and RF Integration Methods for High Frequency Applications
Authors: Mobley Tim , Stygar Vern
Published: October 2015

This presentation will discuss TGV market trends and a low cost solution using new glass and synthetic fused quartz materials, TCE matched Cu metalizations, and designs for high density interconnect. The glass substrate or wafer combined with the low cost Cu metalization offers the market a solution that it has not yet seen. Applications are MEMS devices, Signal processing devices, memory storage devices, where hermeticity and high reliability are required, but the real challenge is how to achieve this at low cost. TGV technology offers significant advantages over Through Silicon Via (TSV) techniques, in that the glass can be assembled with the Si wafer or as a die with several highly reliable bonding techniques, which will be discussed. Technology continues to evolve requiring form factors that are smaller and smaller while still maintaining high frequency performance and long battery life; which are driving more interconnects from single IC's. Glass Interposers offer a high aspect ratio of wafer/substrate thickness to via diameter, and this paper will demonstrate 25–50micron vias in 10–15mil thick glass or synthetic fused quartz using low cost methods of production. While this method may be disruption to the current TSV supply chain to IC Device manufacturers, it will offer them a low cost, highly reliable solution they seek. The solution is enabled by an AGC manufactured Synthetic Quartz using a patented process that facilitates low impurities levels which results in an insertion loss previously unavailable at in both polymeric substrates and ceramic substrates.
Post-Packaged Measurement of MEMS Gap, Displacement, Force, Stiffness, Mass, Damping, and Quality Factor
Authors: Clark Jason Vaughn
Published: October 2015

What is presented: We present a practical MEMS metrology technology that can be used to extract system stiffness, mass, damping, and excitation force after a MEMS is packaged. Presently the technology applies to planar MEMS with comb drives. Our method is quick, accurate, and precise.

Why important: Our technology will likely be important for manufacture, accuracy, and controllability. During manufacture, MEMS metrology can be 30% to 40% of the cost. This high cost is due to factory testing tools that are impractical and not optimized for batch fabrication. The tools often apply an external disturbance that the MEMS are electronically tuned to. Accuracy is a critical problem area in MEMS. Often MEMS are more sensitive and precise than the tools used to calibrate them. And there are no ASTM standards in MEMS for measuring stiffness, mass, damping, and force. Since there is a lack of standards, high cost in metrology, and low return on measurement due to large uncertainties, it has been difficult for manufacturers and their customers to agree on calibration technologies. Moreover, calibration in controlled laboratory conditions may not be consistent with conduction due to harsh environmental changes or long-term dormancy. Conventional calibration methods often treat MEMS as a black box, where numerous parameters remain uncharacterized. Without complete characterization, a complete understanding of what is being sensed is unlikely. However, by measuring the stiffness, mass, damping, and excitation forces on-chip, MEMS can become self-calibrating and offer more complete analysis of what is being sensed.

What is different: Our method consists of using on-chip or off-the-shelf electronics to measure changes in capacitance to measure geometry, displacement, stiffness, and comb drive force. Upon measuring stiffness, mass is determined by velocity resonant frequency. The benefit of using changes in capacitance is that our technology is independent of meter accuracy; that is, it is the precision of the meter that matters. E.g. Zeptofarad precision has been realized by a few groups. Such an independence from absolute measurements allows our technology to be repeatable between different laboratories, where parasitics will likely differ.

Results: We validate our electro-metrology technology for geometry, displacement, stiffness, and force. Our results of geometry compares favorably against geometry measured by a scanning electron microscope by 2 orders of magnitude. We validate displacement by measuring the distance traveled between a pair fabricated displacement stops. Stiffness and force are simi-validated by applying an identical (but unknown) AFM-cantilever force to two different MEMS which are each calibrated using our method. Although such a method does not directly provide a traceable measurement of force, it does imply the possibility of developing a standard of measure because the same value of force is obtained across different devices.
Simulating Atomic-Scale Defects with Atomic Methods and Extended Finite Elements
Authors: Oswald Jay
Published: October 2015

A finite element method is developed for dislocations in arbitrary, three-dimensional bodies, including micro-/nano-devices, and layered materials, such as thin films. The method is also compatible with anisotropic materials, and can readily be applied to nonlinear media. In this method, dislocations are modeled by adding discontinuities to extend the conventional finite element basis. Two approaches for adding discontinuities to the conventional finite element basis are proposed. In the first, a simple discontinuous enrichment imposes a constant jump in displacement across dislocation glide planes. In the second approach, the enrichments more accurately approximate the dislocations by capture the singular asymptotic behavior near the dislocation core. A basis of singular enrichments is formed from analytical solutions of straight dislocation lines, which are shown to be applicable for more general, curved dislocation configurations. Methods for computing the configurational forces on dislocation lines within the XFEM framework have also been developed. For jump enrichments, an approach based on an energy release rate or J-integral is proposed. When singular enrichments are available, it is shown that the Peach-Koehler equation can be used to compute forces directly. This new approach differs from many existing methods for studying dislocations because it does not rely on superposition of solutions derived analytically or through Green's functions. This extended finite element approach is suitable to study dislocations in micro- and nano-devices, and in specific material micro-structures, where complicated boundaries and material interfaces are pervasive.
Modeling and Simulation of 3D MEMS Integrated RF Circuits
Authors: Kim Bruce , Kannan Sukeshwar , Gupta Anurag , Evana Naga Sai
Published: October 2015

Today's integrated packaging consists of analog, mixed-signal and RF circuits. These integrated packages are now available in 3-D which makes it extremely difficult to test for defects and their circuit functionalities. This paper provides 3D MEMS integrated packaging which provides self testing and calibrations to overcome process defects and out of spec circuits inside the package making the package self heal itself in case of faults and defects. We have worked on TSV based 3D packaging with MEMS switches to perform self calibrations. We developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated on an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. We used arrays of MEMS switches to perform self testing. We have considered a low noise amplifier as the reference RF circuit which operates between 4 GHz and 6 GHz. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. The paper presents defects in TSV due to mechanical stress and thermal changes.
Semeiconductor Packaging Trends and Materials Challenges
Authors: Iyer Mahadevan “Devan”
Published: October 2015

Semiconductor advancements continue to enable many new applications to enable the Internet of Things and transform areas such as coud computing, health care, safety and security, and consumer electronics. As exciting new capabilities emerge, customers are demanding smaller, thinner, faster and more power efficient solutions. In his keynote presentation Dr. Mahadevan “Devan” Iyer will discuss these trends, and how packaging technology is playing an increasingly important role in delivering these benefits in IC products. Dr. Iyer will outline the materials requirements and challenges for increased electrical, thermal and reliability performance.
Cost Drivers for 2.5D and 3D Applications
Authors: Palesko Chet , Vardaman E. Jan , Palesko Alan
Published: October 2015

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as a packaging alternative. Miniaturization and high performance product requirements are driving this move – even though in many cases the cost of both 2.5D and 3D is still high.

The primary applications for 2.5D interposers with TSVs are GPUs/CPUs, high-end ASICs, and FPGAs. Adoption for FPGAs has already started. The key to the performance gains in recently introduced FPGAs is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer or what Xilinx calls its Stacked Silicon Interconnect technology. Applications for interposers include tablets, gaming, and high-end computing and network systems. The drivers are mainly partitioning large die, integrating single chips into a module, reducing die size where substrate density is the constraint, and using the interposer to minimize the stress on large die that are fabricated with extra-low-k (ELK) dielectrics.

The primary applications for 3D solutions are stacked memory cubes and memory plus logic. The true 3D nature of stacking all active silicon allows better miniaturization, but yield issues can quickly drive the cost unacceptably high.

This analysis examines the cost drivers for 2.5D and 3D applications. Activity based cost models will be used to analyze the complete cost of fabricating and assembling active die on a silicon interposer and active die stacking on other active die. Total product cost impact - not just the cost of a specific activity - is the focus of this analysis. Since yields play a major role in cost, a sensitivity analysis of the different yields including die yield before wafer probe, die yield after wafer probe, TSV yield, interposer yield, assembly yield, substrate yield, etc. will be presented. The critical yield points in the manufacturing flow and dominant activity cost drivers (equipment, material, and /or labor) will be presented as well as suggested minimum thresholds for 2.5D and 3D technology to be a cost effective technology.
Lithography Process Challenges for 3D and 2.5D Applications
Authors: Shelton Doug , Kume Tomii
Published: October 2015

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.