bluuebunny/crossref_metadata_2025 huggingface dataset:
The Synthesis of Hydrocarbons for Fuel and Lubricants via Ceramic Membrane Reactor
Authors: Mosby James M , McGuire Patrick , Taggart Daniel , Staley Jacob , Elangovan S
Published: May 2015

The development of alternative feed stocks for fuels and chemicals has received growing interest as a means to reduce greenhouse gas (GHG) emissions. Biomass has been proposed and used as one alternative that is converted to fuels and chemicals using high energy reactions that require catalyst and/or hydrogen. To have a significant market penetration and corresponding reduction in GHG, biomass fuels and chemicals need to compete economically with petroleum feed stocks. Thus, Ceramatec is developing a novel technology that uses a ceramic membrane reactor to reduce the cost of converting biomass derived free fatty acids (FFAs) to infrastructure compatible hydrocarbons. This work has centered on improving the selectivity and efficiency of the electrolysis by using a NaSICON membrane to customize the anolyte specifically for the oxidation reaction.
(Invited) Electrochemical CO2 Reduction to Formic Acid on Crystalline SnO2 Nanosphere Catalyst
Authors: Fu Yishu , Liu Yuyu , Li Yanan , Qiao Jinli , Zhou Xiao-Dong
Published: May 2015

In this work, the morphology controlled SnO2 nanosphere catalyst has been successfully synthesized and applied to electrochemical CO2 reduction to formic acid in 0.5 M KHCO3. The catalysts were synthesized by a simple hydrothermal method under controlling the different proportions of ethanol to distilled water as mixed solvent. The obtained catalysts were then coated on gas diffusion electrode (SnO2/GDE) as working electrode. It was found that the catalyst prepared from 50% content of ethanol gives the best catalytic activity towards CO2 reduction, where the onset potential was found to be 300 mV more anodic than that of hydrogen evolution. Meanwhile, the SnO2/GDE-50 showed the most stable property for CO2 reduction. The current density and faradaic efficiency increased as the potential increased, reaching a maximum at -1.7 V vs. SHE. At this stage, the maximum faradaic efficiency of 68% with a current density of 6 mA cm-2 was obtained. Moreover, the production rate of format exhibits a maximum value of 518.2 mg L-1 at the cathode potential of -1.9 V vs. SHE.
CO2 Electrocatalytic Reduction at Gold and Copper Electrodes: Role of Particle Size and Surface Chemistry
Authors: Andrews Evan Michael , Flake John , Fang Yuxin
Published: May 2015

This work details the investigation into the effects of surface chemistry modifying agents on the electrochemical reduction of CO2 with the intent of controlling product selectivity and yield. Results for the reaction on gold and copper electrodes, both on the nano and macro scales are discussed.
Kinetics and Electrocatalytic Activity of Co(Aminopyrine)-Derived Nitrogen-Doped Porous Nanocomposite for Oxygen Reduction Reaction in Alkaline Electrolyte
Authors: Tang Sheng , Zhu Taishan , Fu Yishu , Qiao Jinli , Zhou Xiao-Dong
Published: May 2015

The presented paper reports the preparation and electrocatalytic activity of nanostructured Co-Aminopyrine catalyst for oxygen reduction reaction (ORR) in alkaline media. The catalysts were prepared through a nano-SiO2 hard template method along with the high-temperature pyrolysis process. Results of electrochemical characterization, which was performed using cyclic voltammetry (CV) and linear sweep voltammetry (LSV) employing a rotating disk electrode (RDE), with emphasis on the activity of the catalyst are presented. The electrochemical property was found to depend strongly on the pyrolysis times. The Co-Aminopyrine pyrolyzed twice (Co-Apr-2), with onset potential at 0.15V and half-wave potential at 0.05V, showed much better catalytic activity than Co-Aminopyrine pyrolyzed just once (Co-Apr-1).
Nitrogen-Doped Hierarchical Mesoporous/Macroporous Carbon (H-C) Prepared from the Combined Silica Templates with Different Size for Oxygen Reduction
Authors: Wu Mingjie , Shi Jingjing , Wang Qiang , Qiao Jinli , Liu Yuyu
Published: May 2015

In this work, by combining a simple two-step graphitization of the impregnated carbon, we have synthesized novel nitrogen-doped hierarchical mesoporous/macroporous carbon (H-C) with high efficient catalytic activity for ORR by mixing two or more kinds of particle size controlled silica template agent. Results of electrochemical characterization, which was performed using cyclic voltammetry (CV) and linear sweep voltammetry (LSV) employing a rotating disk electrode (RDE), with emphasis on the activity of the catalyst are presented. The catalytic activity was found to depend strongly on the porous structure. The resulting H-C obtained from the binary nanosilica template (15nm/500nm = 9:1 in mass) exhibits the highest catalytic performance in terms of ORR among the catalysts studied, where the onset potential at 0.2V, half-wave potential at 0.03V and average transferred electron number at 3.50, were achieved in alkaline media.
The Performance of Doped Mesoporous Carbon Electrodes as Electrochemical Capacitors in Optimized Alkaline Electrolyte
Authors: Chen Wenzhao , Li Jiadong , Xu Nengneng , Wang Qiang , Liu Yuyu , Qiao Jinli
Published: May 2015

Nitrogen and sulfur dual-doped mesoporous carbons were prepared through a facile template-mediated pyrolyzing method using poly(ethyleneimine) (PEI) as sources of nitrogen (N) and carbon (C), ferrous sulfate (FeSO4 7H2O) as both precursor of sulfur (S) and activation reagent along with nanoscaled silica as sacrificial supports. The as-prepared doped mesoporous carbons show perfect supercapacitive performances, which have been demonstrated by cyclic voltammetry and constant-current charge/discharge cycling techniques. The specific capacitance (SC) of the as-prepared electrode can reach 279 F/g at a current density of 1 A/g. Even at a high rate capability of 100 A/g, the electrode still shows the SC value as high as 240 F/g, retaining 86% of that at 1 A/g. Regarding the effect of electrolyte concentrations (1-6M KOH), 3 M KOH gives the best performance. The above results indicate that the doped mesoporous carbon electrodes developed in this work are promising for use in energy storage devices.
Electrode Kinetics of the Ni Porous Electrode for Hydrogen Production in the Molten Carbonate Electrolysis Cell (MCEC)
Authors: Hu Lan , Lindbergh Göran , Lagergren Carina
Published: May 2015

The hydrogen evolution reaction in molten carbonate salts is an important process in the development of the molten carbonate electrolysis cell (MCEC). In the present study the kinetics of hydrogen production in the Ni porous electrode in a MCEC is investigated. The general procedure is to determine the reaction orders of hydrogen, carbon dioxide and water. For this purpose steady-state polarization data were recorded under different gas compositions and temperatures. The exchange current densities were calculated from the slopes of the polarization curves at low overpotential. On the basis of that, the partial pressure dependencies of hydrogen, carbon dioxide and water could be determined in the electrolysis operation.
Cross-linked Anion Exchange Membranes Composed of Imidazolium Salt for Alkaline Fuel Cell
Authors: Song Feifei , Chen Shuli , Gao Ying , Liu Yuyu , Qiao Jinli
Published: May 2015

Two novel cross-linked anion exchange membranes (AEMs) composed of PVA or Chitosan by incorporation of PMViC-Co-VP as ion conductors for alkaline fuel cells (AFCs) were prepared by a simple solution-casting method. The anion conductivity (OH-) and water uptake of the as-prepared membranes were investigated. It is found that the OH- conductivities could reach 0.0086S cm-1 for both PVA/PMViC-Co-VP/GA and Chitosan/PMViC-Co-VP/GA membranes, and gradually increased with increasing temperature up to 80oC. Meamnwhile, the water uptake (WU) of these two kinds membranes are aslo less than 100% after immerion in different concentrations of KOH (1-8M) solution. In addition, both PVA (Chitosan)/PMViC-Co-VP/GA membranes posses good mechanical property, where the PVA/PMViC-Co-VP/GA (1:0.5:0.1 by mass) membrane shows the tensile strength of 31.11 MPa with elongation at break of 10.45%.
H2/O2 Alkaline Membrane Fuel Cell Performances Using Carbon-Supported Metal Phthalocyanine (MPc/C,M = Co, Cu, Zn, Ni) as Cathode Catalysts
Authors: Zhu Taishan , Qing Xin , Xu Pan , Song Yanxi , Qiao Jinli
Published: May 2015

This work is focused on the fabrication of membrane electrode assembly (MEA) and power performances by applying carbon supported metal phthalocyanine (MPc/C, M = Co, Cu, Zn, Ni) as cathode catalysts for alkaline anion exchange membrane fuel cells. The MPc/C catalysts are synthesized via a combined solvent-impregnation along with the different temperature treatment. The catalytic activity of MPc/C catalysts toward ORR are screened by linear sweep voltammetry (LSV) employing a rotating disk electrode (RDE) technique. The MEA fabricated with MPc/C catalysts and the Tukuyama membrane gave the initial power densities of 12.6, 6.8, 6.1 and 6.0 mW cm-2 for CoPc/C, CuPc/C, NiPc/C and ZnPc/C, respectively, at room temperature using H2 and O2 gas. At this stage, the power densities of MPc/C catalysts with Cu, Ni and Zn as centre metals are still low in comparison with that of CoPc/C, however, these initial results are promising for the application both in alkaline membrane fuel cells and metal-air batteries by further optimization of MEA preparation and cell test conditions.
Synthesis and Conductive Property of Alkaline Anion-Exchange Membranes Based on Poly(vinyl alcohol)/Bis(2-chloroethyl) Ether-1,3-bis[3-(dimethylamino)propyl] Urea Copolymer Composite
Authors: Chen Shuli , Song Yanxi , Song Feifei , Zhao Xiaoxiang , Qiao Jinli , Zhou Xiao-Dong
Published: May 2015

This study reports a new type of alkaline anion-exchange membranes consisting of poly (vinyl alcohol) (PVA) and poly Bis(2-chloroethyl) ether-1,3-bis [3-(dimethylamino)propyl] urea copolymer (PUB). The membranes were prepared by a combined chemical cross-linking method with different concentration solution consisting of glutaraldehyde as a cross-linker. The OH- conductivity of the membranes was found to be increased with increasing mass ratio of PUB, and reached high up to 6.78 × 10-3S cm-1 at room temperature.. It is found that the conductivity reached 7.60×10-3S cm-1 under ambient conditions when the membrane were immersed into the cross-linking reaction solution consisting of 15 wt.% GA. Moreover, The OH- conductivities were all gradually increased with increasing temperature, where the maximum OH- conductivity of 9.28×10-3 S cm-1 was obtained at 80oC.
Manganese Doped Lanthanum-Strontium Chromite Fuel Electrode for Solid Oxide Fuel Cell and Oxygen Transport Membrane Systems
Authors: Gupta Sapna , Singh Prabhakar
Published: May 2015

(La0.75Sr0.25)0.95Cr0.7Mn0.3O3 (LSCM) mixed with 8YSZ has promising attributes to function as fuel electrode and electrolyte membrane in high temperature electrochemical devices including solid oxide fuel cell as well as oxygen transport membrane systems. In this study, role of temperature (850-950°C) and bias (0-0.8V) is investigated on the electrochemical performance of symmetrical cells of configuration LSCM/8YSZ//8YSZ//LSCM/8YSZ in oxidizing (air) and reducing atmosphere (Ar-3%H2-3%H2O) under the simulating device operating condition. Higher performance is obtained in oxidizing atmosphere when compared to reducing atmosphere. Bulk, surface and the electrode/electrolyte interfaces are examined during post-test characterization of the tested cells. No electrode delamination as well as no interface layer or compound formation is identified in the bulk and/or interface in both oxidizing and reducing atmosphere.
(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges
Authors: Hashemi Pouya , Balakrishnan Karthik , Ott John A. , Leobandung Effendi , Mo Renee T. , Park Dae-Gyu
Published: May 2015

Strained Silicon-Germanium (s-Si1-xGex) FinFET is a promising pMOS candidate for sub-10nm technology generations due to its superior hole transport properties over Si FinFETs, which is a result of built-in uniaxial compression. In this paper, we discuss process integration challenges and opportunities as well as electrical characterization of s-Si1-xGex–on-Insulator (SiGeOI or SGOI) FinFETs with aggressively scaled gate and fin dimensions and Ge content up to x~0.5, using an improved Si-cap-free surface passivation process. The device electrostatics, hole transport, impact of surface passivation, and drain leakage characteristics of SiGeOI pMOS FinFETs are comprehensively studied. The results indicate that SiGeOI FinFETs with moderate Ge content of x~0.3 can offer superior pMOS characteristics and are promising candidate for high-performance (HP) and some low-power applications (LP). On the other hand, while SiGeOI FinFETs with higher Ge content (x~0.5) can offer extremely high mobility and high current drive which is applicable to high-performance CMOS, their off-state leakage could be a concern for low-power applications.
High Mobility Materials on Insulator for Advanced Technology Nodes
Authors: Schwarzenbach Walter , Figuet Christophe , Delprat Daniel , Veytizou Christelle , Huyet Isabelle , Tempesta Catherine , Ecarnot Ludovic , Widiez Julie , Loup Virginie , Hartmann Jean-Michel , Besson Pascal , Deguet Chrystel , Mazen Frédéric , Nguyen Bich-Yen , Maleville Christophe
Published: May 2015

sSOI & SiGeOI substrates have already demonstrated their potential to support digital advanced technology performance roadmap, and are consequently considered in Soitec product roadmap for 10nm technology nodes and beyond. Smart-Cut® process has already demonstrated its benefit to transfer high quality strain silicon and/or SiGe layer from a donor. This paper will show for the first time the results achieved on a 300mm SiGeOI material with high germanium content. Beyond current crystal quality & active layer uniformity, next development will focus on dislocation and surface defect densities improvement.
Evaluation of Anisotropic Biaxial Stress in Si1-X
Ge
x
/Ge Mesa-Structure by Oil-Immersion Raman Spectroscopy
Authors: Yamamoto Shotaro , Takeuchi Kazuma , Yokogawa Ryo , Tomita Motohiro , Kosemura Daisuke , Usuda Koji , Ogura Atsushi
Published: May 2015

Si1-x
Ge
x
is one of the prospective materials for the next-generation transistors due to its high carrier mobility, especially for high Ge concentration Si1-x
Ge
x
. Inducing strain in the Si1-x
Ge
x
leads to transistor performance improvement, however it is difficult to evaluate strain induced in the channel region because the strained Si1-x
Ge
x
channel may be scaled down to nanosize and relaxed complicatedly. We adopted oil-immersion Raman spectroscopy to evaluate the stress in the Si1-x
Ge
x
nanostructure. In this technique, the anisotropic biaxial stress state in the Si1-x
Ge
x
nanostructure can be evaluated. As a result, the nanostructure size dependence of the biaxial stress states in the Si1-x
Ge
x
mesa structure on the Ge substrates was obtained, which was confirmed for the Si1-x
Ge
x
with 76, 85, 92% Ge concentrations.
A New Method to Induce Tensile Stress in Silicon on Insulator Substrate: From Material Analysis to Device Demonstration
Authors: Maitrejean Sylvain , Loubet Nicolas , Augendre Emmanuel , Morin Pierre Francois , Reboh Shay , Bernier Nicolas , Wacquez Romain , Lherron Benoit , Bonnevialle Aurore , Liu Qing , Hartmann Jean-Michel , He Hong , Halimaoui Aomar , Li Juntao , Pilorget Sonia , Kanyandekwe Joel , Grenouillet Laurent , Chafik Fadoua , Morand Yves , Le Royer Cyrille , Faynot Oliver , Celik Muhsin , Doris Bruce , de Salvo Barbara
Published: May 2015

Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGex on SOI substrate, the partial amorphization and crystallization of the Si / Si1-xGex bilayers and the selective removal of the top Si1-xGex film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted- SOI (CMOS FD-SOI) devices at 14 nm node design rules were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.
Mechanical Analyses of Extended and Localized UTBB Stressors Formed with Ge Enrichment Techniques
Authors: Morin Pierre Francois , Grenouillet Laurent , Loubet Nicolas , Pofelski Alexandre , Lu Darsen , Liu Qing , Augendre Emmanuel , Maitrejean Sylvain , Fiori Vincent , de Salvo Barbara , Doris Bruce , Kleemeier Walter
Published: May 2015

Germanium enrichment process also known as condensation can be used for the integration of stressors in the fully depleted silicon on insulator technology. Using multi-physics modeling combined with advanced TEM characterization we studied the formation of stressors with condensation. We first observed in blanket 1D structures that the diffusion rate is substantially reduced during Ge condensation compared to the typical diffusion in neutral atmosphere. We postulate this is due to the injection of interstitial at the oxide/SiGe interface and to a reduced stress effect on the kinetics. We then studied self-aligned in plane stressors (SAIPS) formed in the source/drain region using localized Ge condensation. It is shown that the SAIPS methodology almost doubles the channel stress generated by the source drain stressor. Combining Si0.65Ge0.35 and SAIPS source/drain stressors with in-situ Si0.79Ge0.21 strained channel allows achieving a stress of -2 GPa in the p-type channel with gate first architecture.
The Impact of the Ge Concentration in the Source for Vertical Tunnel-FETs
Authors: Martino Joao Antonio , Agopian Paula Ghedini Der , Neves Felipe Souza , Vandooren Anne , Rooyackers Rita , Simoen Eddy , Thean Aaron , Claeys Cor
Published: May 2015

The goal of this work is to study the influence of the germanium concentration in the source region of vertical TFETs for different temperatures. Vertical TFETs with the source region composed by Si(100%), Si0.73Ge0.27, Si0.56Ge0.44 and Ge(100%) were studied in the temperature range from room temperature to 150oC. The main analog parameters like transconductance, output conductance and intrinsic voltage gain were analyzed. With increasing Ge concentration the drive current, the subthreshold swing, the transconductance and the intrinsic voltage gain improves while the output conductance and 1/f noise degrades. The temperature increase impacts negatively the output conductance and the intrinsic voltage gain, in spite of improving the transconductance due to the higher band-to-band tunneling caused by the source bandgap lowering.
(Invited) Monolithic Integration of III-V Semiconductors by Selective Area Growth on Si(001) Substrate: Epitaxy Challenges & Applications
Authors: Merckling Clement , Jiang Sijia , Liu Ziyang , Waldron Niamh , Boccardi G , Rooyackers R , Wang Zhechao , Tian Bin , Pantouvaki Marianna , Collaert Nadine , Van Campenhout Joris , Heyns Marc , Van Thourhout Dries , Vandervorst Wilfried , Thean Aaron
Published: May 2015

This study relates to the selective area growth (SAG) of III-V semiconductors on Silicon substrates. Both approaches, growth in trenches and NWs bottom-up growth, are considered and discussed. We demonstrated in a first part a high control of the two-step InP buffer growth in STI trench width below 20 nm. First GaAs NWs from production MOVPE tool are also shown in a second part. Finally we conclude with the different applications using III-V semiconductors successfully integrated on Silicon substrates.
(Invited) Dopant Activation and Deactivation in InGaAs during Sub-Millisecond Thermal Annealing
Authors: Sorg Victoria , Zhang Suki Naifang , Hill Megan , Clancy Paulette , Thompson Michael O.
Published: May 2015

Dopant activation of Si implanted In0.53Ga0.47As (InGaAs) following laser spike annealing (LSA) was studied at temperatures up to 1000oC with dwells from 250 μs to 2000 μs. Temperatures of the InGaAs under LSA were directly measured using Pt thermistors and calibrated to the known decomposition temperature of a simple polymer. Using spatially resolved probes with single laser stripe scans, the temperature dependent activation and damage behaviors were determined. Compared to furnace annealing, LSA was found to increase active carrier concentration and extend the temperature limit before damage. CAPRES 4-point measurements were used to determine carrier activation while Raman analysis of the LO phonon peak and LO phonon-plasmon coupling mode (LOPCM) peak was used to monitor crystal quality and carrier concentrations. For a 1014 cm-2 Si implant at 20keV, a minimum sheet resistance of 135 Ω/sq was obtained for a 1000 μs dwell at 845oC, with a peak carrier concentration near 8x1018 cm-3.
(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs
Authors: Lee Rinus T.P. , Loh Wei Yip , Tieckelmann Robert , Orzali Tommaso , Huffman Craig , Vert Alexey , Huang Gensheng , Kelman Maxim , Karim Zia , Hobbs Chris , Hill Richard J.W. , Papa Rao S.S.
Published: May 2015

III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (Rext) be minimized. Among the different components of Rext, contact resistance (RC
), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower RC
. However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low RC
. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-V). In this paper, we will review these RC
reduction options and present some of our recent results on contact/junction engineering to lower RC
in III-V MOSFETs.
(Invited) Record-Performance In(Ga)As MOSFETS Targeting ITRS High-Performance and Low-Power Logic
Authors: Rodwell Mark J , Huang Cheng-Ying , Lee Sanghoon , Chobpattana Varistha , Thibeault Brian , Mitchell William , Stemmer Susanne , Gossard Arthur
Published: May 2015

We review development of In(Ga)As-channel MOSFETs. InAs and InGaAs channels, combined with thin gate dielectrics, provide high transconductance, but off-state leakage can be high due to band-band tunneling currents. This leakage is reduced through thin 2.5-3nm channels, and through InGaAs or InP vertical field spacers in the raised source and drain. Devices with 2.7nm InAs channels and lightly-doped InGaAs source/drain spacers, at 25nm Lg
, provide a record 0.5mA/µm Ion
at 100nA/µm Ioff
and 500mV VDD
. 1 µm Lg
FETs show 61mV/decade subthreshold swing at VDD
=0.1 V. Targeting the LP specification, we have developed InGaAs-channel MOSFETs with lightly-doped InP wide-bandgap source/drain spacer layers. At 30nm gate length, these show a minimum 60 pA/µm Ioff
, approximately 100:1 smaller than a similar device using InGaAs source/drain spacers. A FET using InP spacers, with 45 nm gate length, shows 0.15 mA/µm Ion
at 1nA/µm Ioff
and 500mV VDD
.
Effect of Hydrogen on Silicon Nitrides Formation by Microwave Excited Plasma Enhanced Chemical Vapor Deposition
Authors: Teramoto Akinobu , Nakao Yukihisa , Suwa Tomoyuki , Hashimoto Keiichi , Motoya Tsukasa , Hirayama Masaki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: May 2015

The gas composition is one of the most important parameters for reducing process temperature of the plasma enhanced chemical vapor deposition. We investigate the effect of the gas flow rate of SiH4, H2, and N2 on the quality and the deposition rate of the silicon nitride films (SiNx) formed by the microwave excited PECVD. The SiH4 flow rate is most important parameter for controlling the deposition rate and the film quality in the PECVD using N2, H2, SiH4 gasses. The deposition rate strongly depends on the SiH4 flow rate; however the film quality was degraded with the increase of the flow rate. The hydrogen has an optimum flow rate for the high deposition rate and high quality film formation. The hydrogen effectively dissociates the SiH4 gas and makes the nitridation species (NHx), as the result, the optimal hydrogen improves the reaction efficiency of SiH4 and NHx.
Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates
Authors: Engelhardt Manfred , Baumgartl Johannes , Denifl Guenter , Ehrentraut Georg , Kuenle Matthias , Stadtmueller Michael , Werner Sebastian , Crippa Danilo , Kraft Martin
Published: May 2015

The customized substrates for manufacturing 300mm power semiconductors had to be prepared by deposition processes and epitaxial growth on standard substrates since they were not yet available from suppliers in both sufficient quality and quantity. Polysilicon films were deposited on wafer backsides and optimized regarding impurity gettering. Severe modifications of existing epitaxy reactors, the facilitation, and the infrastructure were prerequisite to develop extremely high doped, thick silicon layers with both supreme uniformity of layer thickness and dopant distribution to take full advantage of the productivity advantage of large diameter wafer processing. Simulation supporting these activities was also key to enable furnace processes with extremely tight temperature ranges. For the development of very thick, high resistivity silicon layers a 5-wafer 200mm batch tool was used to exploit the tool and process learning for the design and manufacturing of a similar 300mm batch tool. For pattern transfer the same advanced plasma etch equipment was mandatory to achieve similarly uniformities regarding etch rate, profile shape, and CD as in CD-driven advanced DRAMs and MPUs.
Influence of Annealing Condition on TSV Pumping and Microstructure Evolution
Authors: Jing Xiangmeng , Lee Ui-Hyoung , Xu Cheng , Niu Zhongcai , Song Chongshen , Zhang Wenqi , Bae Jong-yong , Won Jaihyung
Published: May 2015

Through silicon vias (TSVs) are regarded as one of the key enabling components to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we report on the thermal mechanical assessment of Cu “pumping” (i.e. protrusion) treated at different annealing conditions. Moreover, the impact of different integration approaches on the TSV pumping behavior is also investigated. The thermo-mechanical behavior under different annealing temperatures of TSVs having a diameter of 10 µm and a depth of 100 µm has been evaluated by white light optical profiler inspection and by high-resolution micro-Raman microscopy. The protrusion can be controlled when the test temperature is lower than the annealing temperature. Higher processing temperature than annealing temperature is not recommended according to pumping and stress measurement results.
(Invited) Temperature Influence on Current Leakage and Hysteresis of Nc-CdSe Embedded Zr-Doped HfO2 High-k Dielectric Nonvolatile Memory
Authors: Zhang Shumao , Kuo Yue
Published: May 2015

Current leakage and hysteresis characteristics of a MOS capacitor containing nanocrystalline CdSe embedded ZrHfO high-k gate dielectric at different temperatures have been investigated. Variation of the temperature changes the supply and energy state of charges from the Si wafer, the charge trapping and retaining properties of the embedded nanocrystal, and the conductivity of the high-k stack. They are responsible for the magnitude and hysteresis of the leakage current. Depending on the polarity and magnitude of the applied voltage and the substrate temperature, charges are transferred following the Schottky emission, Poole-Frenkel, or Fowler-Nordheim mechanism. The leakage current hysteresis of the nanocrystalline CdSe embedded sample is smaller than that of the control sample, and the difference increases as the temperature rises. These phenomena are related to the defect density, the physical thickness, and the charge trapping mechanism.
Ge Nanostructures Embedded in ZrO2 Dielectric Films for Nonvolatile Memory Applications
Authors: Lehninger D. , Khomenkova L. , Röder C. , Gärtner G. , Abendroth B. , Beyer J. , Schneider F. , Meyer D.C. , Heitmann J.
Published: May 2015

Thin films of pure Ge and ZrO2, composite Ge-ZrO2 layers and [Ge-ZrO2/ZrO2]40 multilayers were fabricated by confocal radio frequency magnetron sputtering. The structural and optical properties of these samples were studied by spectroscopic ellipsometry, Raman scattering and Fourier transform infrared spectroscopy in dependence of the chemical composition and the annealing treatment. It could be shown that rapid thermal annealing stimulates a phase separation process within the Ge-ZrO2 composite films leading to a formation of Ge nanocrystals and tetragonal ZrO2. The starting point of this process depends significantly on the Ge content: the higher the Ge content, the lower is the crystallization temperature. Compared to the monoclinic phase, the tetragonal ZrO2 phase offers an enhanced permittivity.
(Invited) Phosphor-Free III-Nitride Nanowire White Light Emitting Diodes: Challenges and Prospects
Authors: Nguyen Hieu Pham Trung , Evo Yaset
Published: May 2015

Tremendous progress has been made in GaN-based nanowire light-emitting diodes (LEDs), which can exhibit drastically reduced dislocation densities and polarization fields, compared to the conventional quantum well devices. However, the performance of nanowire LEDs is limited due to the poor hole transport, the electron overflow, and the large surface nonradiative recombination. In this context, we have investigated the molecular beam epitaxial growth, fabrication and characterization of full-color InGaN/(Al)GaN dot-in-a-wire LEDs on Si substrates, wherein the emission characteristics are controlled by the dot properties in a single epitaxial step. With the use of p-type modulation doping, electron blocking layer (EBL), and core-shell heterostructures, we have further demonstrated superior performance phosphor-free white LEDs that can exhibit record high output power of ~ 5.2 mW and unprecedentedly high color rendering index (CRI) of > 95.
(Invited) Fabrication of High-Quality TiO2 Nanotubes on Conductive Glasses
Authors: Li Shibin , Yang Xiaohui , Wei Xiongbang , Xuan Yaoyu , Chen Zhi David , Jiang Yadong
Published: May 2015

High quality self-ordered TiO2 nanotubes (TNTs) were grown on a conductive fluorine-doped tin oxide (FTO) glass by anodization of titanium thin film. The result showed that high density Ti film with good adhesion was obtained by direct current (DC) magenetron sputtering at 200 ˚C. The dependence of morphology of TiO2 nanotube on anodization time was investigated by scanning electron microscope (SEM). The TiO2 nanotubes were annealed at 500 ˚C for 180 min, which led to the transformation of the crystal structure from amorphous to anatase. The influences of anodization time on the crystallization of nanotubes also were discussed. The proposed low cost method for fabricating TiO2 nanotubes provides an approach to enhance the efficiency of dye-sensitized solar cells (DSSC).
On the Origin of the Gate Oxide Failure Evaluated by Raman Spectroscopy
Authors: Yokogawa Ryo , Tomita Motohiro , Mizukoshi Toshikazu , Hirano Takehiro , Kusano Kenichiro , Sasaki Katsuhiro , Ogura Atsushi
Published: May 2015

The metal-oxide-semiconductor-field-effect-transistor (MOSFET) has been miniaturized for the high performance large-scale integrated-circuit (LSI). However, in the ultimately miniaturized MOSFET, the gate oxide failure with high leakage current is inevitable. In this study, we evaluated the origin of the gate oxide failure by Raman spectroscopy in conjunction with optical beam induced resistance change (OBIRCH) analysis. MOS capacitors were used as the samples. The 2.8 nm thick gate oxinitrid insulator film and the poly-Si gate electrode layer were formed on a P type Si substrate. The cobalt (Co) silicide film was formed on the poly-Si electrode. The SiH4 flow rate was 150 sccm or 350 sccm. The gate oxide integrity was evaluated by the test element group (TEG) measurements. As a result, Raman intensity increased at the failure position compared with the other positions in the sample deposited with 150 sccm of SiH4 flow rate. We consider that higher Raman intensity at the gate oxide failure positions reflects the irregular structure of poly-Si. Furthermore, the Raman peaks at failure positions shifted toward the lower wavenumber while the FWHMs are approximately constant with other positions. Thus, we found that there is no difference in the crystallinity of the poly-Si. The origin of the gate oxide failure was high tensile strain in the gate poly-Si electrode. In conclusion, we have successfully evaluated the gate oxide failure by Raman spectroscopy with a quasi-line excitation source.
Oxide Structure-Dependent Interfacial Layer Defects of HfAlO/SiO2/Si Stack Analyzed by Conductance Method
Authors: Ding YI Ming , Misra Durga
Published: May 2015

This work investigates the interface properties in a metal oxide semiconductor capacitor (MOS-C) device with a 3 nm HfAlO/0.5 nm SiO2/Si stacks prepared by various processing conditions. The impact of different Al doping, different post annealing temperatures and different deposition steps and stacks was studied. Equivalent oxide thickness (EOT) and flat band voltage (V
FB) were obtained from capacitance-voltage measurements. A simple approach was used to address the error introduced by the series resistance（R
s）associated with the substrate and contact while carefully monitoring the impact of the tunneling current. The interface state density (D
it) was calculated by the conductance method. The observed D
it seems to be dependent on the structure of hafnium aluminum oxide film. The amorphous structure has the lowest D
it tetragonal HfO2 (t-HfO2) has the highest D
it and the D
it values of other structures are within the highest and lowest values.
Room Temperature Photoluminescence Characterization of Interface Quality of SiN/SiO2/Si Prepared under Various Deposition Techniques and Conditions
Authors: Yoo Woo Sik , Kim Byoung Gyu , Jin Seung Woo , Ishigaki Toshikazu , Kang Kitaek
Published: May 2015

Room temperature photoluminescence (RTPL) spectroscopy was examined as an in-line monitoring technique for characterizing the interface of ultra-thin (~7.2 nm) stacked dielectric films (SiN/SiO2) on 300 mm Si wafers. To investigate the effect of the stacked dielectric films on electronic properties at the interface, RTPL signals were measured under various excitation wavelengths with different probing depths. Changes of interface quality of the stacked dielectric films and the Si wafer were investigated using various specimens prepared by different deposition techniques and conditions. The overall interface quality of the SiN/SiO2/Si specimens was found to be very dependent on the SiN deposition technique and process conditions. N-rich SiN films resulted in very intense RTPL signals. As the stoichiometry of SiN films change from N-rich to Si-rich conditions, the RTPL signal becomes weaker, indicating the change of electronic properties at the SiN/SiO2/Si interface. Within-wafer and wafer-to-wafer variations of the SiN/SiO2/Si interface quality were successfully characterized by RTPL spectroscopy under various excitation wavelengths.
Pulse Width Modulation for Reducing Pulsed MOS Capacitor Measurement Time
Authors: Safarnezhad Hendijani Mohamad , Zahedi Sayedehgolnaz
Published: May 2015

Semiconductor manufacturing economics necessitate the development of novel approaches to reduce the measurement time for commonly established lifetime measurement techniques. Although accurate and easy to implement, the pulsed MOS-Capacitor technique takes a long time to accomplish. This becomes problematic when the goal is to map the whole wafer area. We show that by using a dynamic pulse train and with manipulating the accumulation pulse width, the pulsed MOS-C technique can be implemented in much faster time frames while its accuracy is being kept constant.
Non-Volatile Resistive Memory Switching in Pulsed Laser Deposited Rare-Earth Gallate-GdGaO3 Thin Films
Authors: Sharma Yogesh , Pavunny Shojan P. , Scott James F. , Katiyar Ram S.
Published: May 2015

Pulsed laser deposited amorphous GdGaO3 (GGO) thin films were investigated to explore their resistive switching (RS) behaviour. Pt/GGO/Pt memory cells showed a stable resistance ratio of ~104 between low resistance state (LRS) and high resistance state (HRS) and non-overlapping switching voltages (set voltage, VON ~1.2˗1.4 V and reset voltage, VOFF ~0.6˗0.8 V) with a small variation of about ± 5˗10% in each. To confirm the reliability of the memory cell, cyclic endurance tests up to 80 set/reset cycles and data retention checks up to 103 seconds were performed. Unipolar RS mechanism in Pt/GGO/Pt memory cell was explained by a conductive filament (thermo-chemical) model, where the change in resistance state (LRS↔HRS) was found to occur due to the formation/rupture of conductive filaments consisting of metallic Gd-atoms and oxygen vacancies. The charge transport mechanisms in LRS and HRS were found to be compatible with Ohmic conduction and space–charge limited current, respectively.
Effect of Process Temperature of Al2O3 Atomic Layer Deposition Using Accurate Process Gasses Supply System
Authors: Sugita Hisaya , Koda Yasumasa , Suwa Tomoyuki , Kuroda Rihito , Goto Tetsuya , Ishii Hidekazu , Yamashita Satoru , Teramoto Akinobu , Sugawa Shigetoshi , Ohmi Tadahiro
Published: May 2015

Al2O3 is one of the most expectancy high-k materials for high density on-chip metal-insulator-metal (MIM) capacitors as well as gate insulator for composed semiconductor power devices. In this paper, using the developed atomic layer deposition (ALD) process equipment with multiple oxidation methods and accurate process gas supply system adapted to high temperature usage, the impact of the process temperature on the electrical characteristics of Al2O3 films was investigated. It was found that the substrate material must not be oxidized at the trimethylaluminum (TMA) - oxidation step of ALD. An excessive high temperature may cause decomposition of TMA, so the process temperature should be controlled sufficiently low in order to obtain one layer TMA adsorbing on the wafer. However, this tends to cause lowering oxidation ability, so it is necessary to remove carbon in the Al2O3 films after the ALD. Post ALD process, such as post deposition anneal (PDA) is required.
(Plenary) Physical Insights on the Design of UTB Devices, Including FinFETs
Authors: Fossum Jerry G.
Published: May 2015

Based on our recently published textbook on ultra-thin-body (UTB) CMOS devices, unique physics of the two prime candidates for revolutionary nanoscale CMOS (i.e., the quasi-planar FinFET and the planar fully depleted (FD) SOI MOSFET) is overviewed, offering insights on device designs, scalabilities, and performance potentials. Emphasis is placed on features of these UTB devices that are not yet recognized or fully appreciated, and implied simplifications of device design and processing are noted.
(Plenary) Substrate Innovation for Extending Moore and More than Moore Law
Authors: Maleville Christophe
Published: May 2015

Within last 10 years, end markets drastically changed towards mobile connected users. With 8B smartphones to be shipped next 4 years, typical performance/cost KPIs have been evolved towards more demanding PPAC metrics adding power consumption (battery life) and area (from factors) constraints. In this effort to bring more performance, less power or more functionality, innovation or evolution starting from substrates has demonstrated significant successes, such as FDSOI for extension of Moore’s law beyond 28nm node. In the field of front end modules (FEM) for smartphones, switch, previously built on AsGa substrates, are now built on RFSOI substrates. Compared to 150mm AsGa wafers, 200mm RFSOI wafers are silicon family wafers and FEM switch are now built in large volume in most foundries, offering very significant die cost advantage. This example can be reproduced for many other application fields or device options where substrate innovation is supporting major improvements.
(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS
Authors: Weber Olivier , Josse Emmanuel , Haond Michel
Published: May 2015

This work presents a 14nm technology designed for high speed and energy efficient applications using FDSOI transistors. The specific process integration features of this technology are highlighted in this paper. The transistors have been strain-engineered to provide high drive current and optimally designed to achieve low parasitic capacitance. As a result, this 14nm FDSOI technology provides 0.55x area scaling and delivers +50% speed with -100mV Vdd supply voltage operation compared to the 28nm FDSOI technology.
(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era
Authors: Yamamoto Yoshiki , Makiyama Hideki , Yamashita Tomohiro , Oda Hidekazu , Kamohara Shiro , Sugii Nobuyuki , Yamaguchi Yasuo , Mizutani Tomoko , Kobayashi Masaharu , Hiramoto Toshiro
Published: May 2015

We demonstrated ultralow voltage (<0.4V) operation of Silicon-on-Thin-Buried-oxide (SOTB) CMOS. Thanks to the small variability of SOTB Vmin of SRAM was lowered down to <0.4 V. Both fast access time and small standby leakage were achieved by adaptive back biasing (ABB). 32-bit RISC CPU operated at ultralow energy consumption of 13.4 pJ.
N-Junctionless Transistor Prototype: Manufacturing Using a Focused Ion Beam System
Authors: Lima Lucas Petersen Barbosa , dos Santos Marcos Vinícius Puydinger , Keiler Marco Aurélio , Dekkers Harold F. W. , De Gendt Stefan , Diniz José Alexandre
Published: May 2015

Junctionless (JL) devices were fabricated using focused ion beam (FIB) system for Si milling (to define the Si nanowire (SiNW)) and for gate dielectric (SiO2), gate, drain and source electrode (Pt) deposition. Energy dispersive spectroscopy (EDS) measurements confirmed the presence of Ga+ into SiNW. The influence of Ga+ incorporation into SiNW, due to Si milling, was studied in this work. Electrical measurements results indicate that the Ga+ incorporation can affect the SiNW properties (doping concentration), and consequently, the JL performance (distortions on electrical characteristics). In addition, the simulated JL transistors (considering the Ga+ incorporation) results are in good agreement with the electrical characteristics extracted from the fabricated JL devices. Therefore, the experimental results indicate that our fabrication method using FIB system can be used to obtain prototypes of JL devices.
Germanium Junctionless MOSFET with Steep Subthreshold Swing
Authors: Gupta Manish , Kranti Abhinav
Published: May 2015

In this work, we analyze the occurrence of steep subthreshold swing (S-swing) in Double Gate (DG) Germanium (Ge) Junctionless (JL) nMOS transistors. The performance of Ge JL transistor is compared with that of Si based JL MOSFETs. Our results show that it is possible to achieve steep S-swing < 1 mV/decade along with a steep current transition of nearly 3.5 orders at drain bias of 1.3 V in Ge JL MOSFETs. The work explores the feasibility of the occurrence of steep S-swing, and establishes an understanding of the advantages and challenges associated with Ge JL MOSFETs.
Direct Characterization of Impact Ionization Current in Silicon-on-Insulator Body-Contacted MOSFETs
Authors: Marquez Carlos , Rodriguez Noel , Montes Jose Manuel , Ruiz Rafael , Gamiz Francisco , Sampedro Carlos , Ohata Akiko
Published: May 2015

This work faces the study of impact ionization in Silicon-On-Insulator transistors from the direct characterization of the body current and electrostatic potential. Body contacted devices have been fabricated for that purpose, and biased at zero-potential and zero-current conditions. The combination of both types of measurements has allowed the extraction of an updated set of parameters for the accurate calibration of the conventional stablished models used in TCAD simulations.
Study of Total Quantum Efficiency of Lateral SOI PIN Photodiodes with Back-Gate Bias, Intrinsic Length and Temperature Variation
Authors: Novo Carla , Baptista João , Guazzeli da Silveira Marcilei , Giacomini Renato , Afzalian Aryan , Flandre Denis
Published: May 2015

This paper addresses, for the first time, an analysis of the total quantum efficiency of lateral SOI PIN photodiodes with different intrinsic lengths in the 300 to 500 K range simultaneously considering back-gate bias and temperature influences. Experimental results showed that the mode of operation changes the behavior of the devices concerning dark and photocurrents, while the temperature variation produces different trades in quantum efficiency related to the absorption length and the diffusion length variation.
Improved Charge-Trapping Performance of Hf-Doped SrTiO3 for Nonvolatile Memory Applications
Authors: Huang X.D. , Lai P.T.
Published: May 2015

The charge-trapping characteristics of Hf doped SrTiO3 have been studied based on Al/Al2O3/Hf-doped SrTiO3/SiO2/Si capacitors. The thermodynamic stability of the SrTiO3 film is significantly improved by Hf incorporation, thus resulting in negligible formation of an interlayer at the Hf-doped SrTiO3/SiO2 interface, as confirmed by X-ray photoelectron spectroscopy and transmission electron microscopy. The memory device with Hf-doped SrTiO3 as charge-trapping layer displays high speed at low operating voltage (a VFB shift of 1.9 V at +6 V, 100 ms) and good data retention (charge loss of 12.7% after 104 s). Therefore, the Hf-doped SrTiO3 film is a promising material as charge-trapping layer for high-performance nonvolatile memory applications.
(Invited) A Sub-1G MEMS Sensor
Authors: Yamane Daisuke , Konishi Toshifumi , Toshiyoshi Hiroshi , Masu Kazuya , Machida Katsuyuki
Published: May 2015

This paper presents our recent research progress of highly-sensitive micro-electro-mechanical systems (MEMS) capacitive accelerometers for monitoring micro motion and vibration at the acceleration scale of lower than 1 G (G = 9.8 m/s2 : gravitational acceleration). To reduce the Brownian noise (BN
) on the sensors, we have employed high-density metal for proof mass, and implemented the MEMS structures. Proof-of-concept inertial sensors have been developed by gold electroplating, and we have estimated the BN
to be below 10 μG/Hz1/2, which is nearly one order of magnitude smaller than those of the conventional MEMS accelerometers with the same proof mass size. The experimental results indicate that the proposed sensor concept would be a promising way to further improve the sensitivity and miniaturization of micro-scale motion sensors, which could advance the emergence of new MEMS applications.
(Gordon E. Moore Medal for Outstanding Achievement in Solid State Science and Technology) Research on Nano and Giga Electronics – Breakthroughs Along the Path
Authors: Kuo Yue
Published: May 2015

MOSFETs and TFTs are key semiconductor devices in the two largest semiconductor industries nowadays. The development of the former follows the Moore’s Law in shrinking of the size to the nano scale. The advancement of the latter is toward the high density, large area array. They are operated based on the same principle and facing common challenges. The success is dependent on the thorough understanding of material properties, fabrication processes, and device physics. The author reviews two sets of critical works developed in his laboratory, i.e., plasma thin film technology and high-k thin films for electronics and optoelectronics.