High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing
Authors: Kurz Florian , Plach Thomas , Süss Jürgen , Wagenleitner Thomas , Zinner Dominik , Rebhan Bernhard , Dragoi Viorel 
Published: February 2020

The increased microelectronic devices complexity is raising a strong demand for high wafer-to-wafer (w2w) alignment accuracy allowing for high levels of integration by wafers stacking. One of the major aspects for the alignment is the overlay alignment accuracy as this is strongly impacting on the final yield: the future generation devices will require w2w overlay alignment accuracies in the range of 100 nm or lower. The overlay alignment accuracy can be split into following errors: translation, rotation, run-out and distortion of the patterns on the wafers. In order to meet the increasing demand of overlay alignment accuracy, all those components have to be considered for optimization in the alignment technology development.

This work presents different newly developed concepts for high precision aligned w2w bonding processes which are applicable for any low temperature fusion bonding or Cu/dielectric hybrid bonding processes. The new technologies enable sub-100 nm w2w overlay alignment accuracy. The components of w2w overlay accuracy and the latest developments for their optimization are introduced and different approaches of run-out compensation with and without temperature compensation are introduced. Finally, a feedback loop between SmartView®NT2 w2w alignment system with integrated run-out compensation and in-situ post bond alignment verification module (AVM) will be shown. Additionally to the w2w alignment process and the feedback-loop which is monitoring and controlling the overlay accuracy, a new technique will be presented, which allows a fully automated in-situ recycling method of bonded wafers, which are out of alignment-specification.

The process development was performed using a Gemini®FB-XT fully automated wafer bonding system, equipped with a plasma activation chamber enabling low temperature bonding processes, a SmartView®NT2 optical aligner using a face-to-face alignment principle, a pre-bonding station used for bringing the substrates in contact after alignment, an alignment verification module (AVM) as well as a debonding module which allows for re-working of the wafer pairs failing the alignment criteria.

For optimization of the overlay accuracy on bonded wafers, the optimization steps have to address the individual components of the overlay. A significant contributor to the overlay accuracy is the scaling or run-out error, so the main focus of this evaluation is the run-out compensation process in SmartView®NT2. A well-known run-out compensation method in lithography is a thermal compensation of the scaling, which can also be applied for bonding.Deeper investigations showed that the thermal run-out compensation has major disadvantages in terms of wafer-stress and pattern distortion, which are significant problems for BSI CIS, so this type of compensation would not be an acceptable general solution for such stress- and overlay alignment-sensitive applications.

Multiple new methods for run-out compensation without using thermal compensation were successfully developed, enabling w2w overlay accuracy better than 100 nm on every point measured on the wafers stack and overlay accuracy values better than 100 nm could already be shown successfully.