bluuebunny/crossref_metadata_2025 huggingface dataset:
High-Speed Damage-Free Contact Hole Etching Using Dual Shower Head Microwave-Excited High-Density-Plasma Equipment
Authors: Goto Tetsuya , Yamauchi Hiroshi , Kato Takeyoshi , Terasaki Masato , Teramoto Akinobu , Hirayama Masaki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: February 2005

Dual shower head microwave-excited plasma etching equipment for separating the plasma-excited region from the etching process region has been developed. With the aim of realization of damage-free etching, the carrier activation of boron-doped p+-Si is investigated after plasma irradiation. The damage-free-etching mode in which holes do not deactivate was found. Contact holes are successfully etched using a surface damage-free etching process consisting of high-speed etching mode and surface damage-free etching mode. The damage-free-etching mode consists of low-self-bias condition and a low etching gas flow rate as compared with the high-speed mode. For both modes, the etcher can maintain the process uniformity because the etcher can control self-bias voltages without changing other process parameters.
Effect of Film Composition of Nitrogen Incorporated Hafnium Aluminate (HfAlON) Gate Dielectric on Structural Transformation and Electrical Properties through High-Temperature Annealing
Authors: Koyama Masato , Kamimuta Yuuichi , Koike Mitsuo , Suzuki Masamichi , Nishiyama Akira
Published: February 2005

We investigated the effect of nitrogen on the structural and electrical properties of nitrogen incorporated hafnium aluminate (HfAlON) gate dielectrics through high-temperature annealing. It was found that 30 at.% nitrogen substantially suppresses HfO2 segregation after the annealing. An amorphous HfAlON film with a k-value of 17 after 1000°C appeared at the composition of Hf ratio = 35% and N = 32 at.%, accompanied by improved boron blocking from the p+poly-Si gate. At an Hf ratio higher than 47%, however, cubic-HfN crystals emerged from HfAlON after the annealing. The cubic-HfN significantly increased gate leakage current through the film. We conclude that the applicability of HfAlON gate dielectric to the further scaling down of LSIs is inherently limited by metallic HfN formation at high process temperatures.
Enhancement of Dielectric Constant due to Expansion of Lattice Spacing in CeO2 Directly Grown on Si(111)
Authors: Matsushita Daisuke , Nishikawa Yukie , Satou Nobutaka , Yoshiki Masahiko , Schimizu Tatsuo , Yamaguchi Takeshi , Satake Hideki , Fukushima Noburu
Published: February 2005

We have investigated the reason behind the enhancement of dielectric constant (ε), which occurred in CeO2 directly grown on Si(111). ε of directly grown CeO2 is enhanced to 52, which is twice as large as the reported value. From in-plane X-ray diffraction measurements and electron diffraction pattern observations using a transmission electron microscope, it has been found that the lattice spacings in CeO2 were isotopically expanded by 0.6%, as compared with the reported values in bulk CeO2. In addition, from X-ray photoelectron spectroscopy measurements, the existence of oxygen defects in CeO2 was confirmed. The oxygen defects in CeO2 may cause the decrease in coulomb interaction in the ionic crystal, resulting in the expansion of lattice spacings. The enhancement of ion movability, due to the expansion of lattice spacings is considered as the reason behind the enhancement of ε.
Optimum TiSi2 Ohmic Contact Process for Sub-100 nm Devices
Authors: Park Hee Sook , Lee Jong Myeong , Lee Sang Woo , Park Jea Hwa , Moon Kwang Jin , Kang Sang Bom , Choi Gil Heyun , Chung U In , Moon Joo Tae
Published: February 2005

A defect which occurs at the corner of the metal/n+ contact bottom in direct contact (DC) of dynamic random access memories (DRAMs) with 100 nm technology and below is reported for the first time. The defect consists of Si stacking faults with a Si [011] zone axis and contains diffused titanium. The DC defect was responsible for high n+/p leakage current which increased with decreasing contact size. The defect can be completely removed by applying 700–900°C rapid thermal process (RTP) immediately after chemical vapor deposition (CVD)-Ti/TiN deposition, which transforms the deposited titanium to C54 titanium silicide. It is suggested that the generation of the DC defects is related to the incomplete phase transformation of titanium silicide.
A Novel Photosensitive Porous Low-k Interlayer Dielectric Film
Authors: Kuroki Shin-Ichiro , Sakamoto Susumu , Kikkawa Takamaro
Published: February 2005

The characteristics of photosensitive porous low-k methylsilsesquioxane (MSQ) were investigated by electron-beam lithography. Photosensitive low-k MSQ makes it possible to realize via and trench patterns for Cu damascene technology without dry etching processes in the ultra large-scale integrated (ULSI) circuit multilevel interconnect integration.
Impact of In Situ NH3 Preannealing on Sub-100 nm Tungsten Polymetal Gate Electrode during the Sealing Nitride Formation
Authors: Lim Kwan-Yong , Lee Jung-Ho , Cho Heung-Jae , Oh Jae-Geun , Hong Byung-Seop , Jang Se-Aug , Kim Yong Soo , Yang Hong-Seon , Sohn Hyun-Chul
Published: February 2005

We investigated the effects of in situ NH3 preannealing immediately before sealing nitride deposition on the wordline sheet resistance (R
s) of a tungsten polymetal gate electrode (W/WN
x
/poly-Si). While in situ NH3 preannealing is very effective for the suppression of W-O whisker formation, it was found that excessively long-time NH3 preannealing could cause an unexpectedly abnormal increase in the wordline R
s of short gate length electrodes, typically <100 nm. Since X-ray diffraction (XRD) and secondary ion mass spectroscopy (SIMS) analyses reveal that long-time NH3 preannealing results in the nitridation of tungsten sidewall surfaces, the wordline R
s increase in a small-gate-length sample subjected to long-time NH3 preannealing is mainly due to tungsten sidewall nitridation, which is localized at the surface region of the tungsten sidewall. In addition, at a long-time NH3-preannealed gate electrode, an abnormal inflation of the tungsten sidewall occurred due to a slight increment in lattice spacing by tungsten nitridation.
Effect of Boron and Fluorine Incorporation in SiON Gate Insulator with Optimized Nitrogen Profile
Authors: Sasaki Takaoki , Ootsuka Fumio , Ozaki Hiroji , Hoshi Takeshi , Tomikawa Mitsuhiro , Yasuhira Mitsuo , Arikado Tsunetoshi
Published: February 2005

In this paper, the effects of boron and fluorine in the SiO2/Si interface region with the optimized nitrogen profile are described. Fluorine in the interface region has been found to terminate the interface states and improve negative bias temperature instability (NBTI). However, fluorine enhances the boron penetration. The ideal nitrogen profile has been achieved in order to suppress NBTI characteristics by applying the SiN/SiO2 stack structure.
Enhanced Metal-Induced Lateral Crystallization in Amorphous Ge/Si/SiO2 Layered Structure
Authors: Kanno Hiroshi , Kenjo Atsushi , Sadoh Taizoh , Miyao Masanobu
Published: February 2005

Metal-induced lateral crystallization (MILC) in a-Ge/a-Si/SiO2 layered structure has been investigated. Crystal nucleation was initiated in the a-Ge layer, which stimulated the bond rearrangement in a-Si. The MILC velocity of a-Si was successfully increased becoming threefold higher than that of a-Si/SiO2 single structure. As a result, poly-Si films with large areas were obtained after 550°C annealing, i.e., ∼10 µm for 5 h and ∼30 µm for 15 h. This will be a powerful tool for realizing large poly-Si areas on insulating films for system-in-displays and three-dimensional ultra-large scale integrated circuits.
Selective Dry Etching of HfO2 in CF4 and Cl2/HBr-Based Chemistries
Authors: Maeda Takeshi , Ito Hiroyuki , Mitsuhashi Riichiro , Horiuchi Atsushi , Kawahara Takaaki , Muto Akiyoshi , Sasaki Takaoki , Torii Kazuyoshi , Kitajima Hiroshi
Published: February 2005

We investigated HfO2 etching characteristics in conventional Si gate etching chemistries, namely, CF4 and Cl2/HBr/O2-based chemistries. We obtained an adequate etch rate of 2.0 nm/min for both chemistries and a selectivity of 1.9 over SiO2 for Cl2/HBr/O2-based chemistry. We examined the etch rate dependence on source power, bias power, O2 flow rate, and Cl2 flow rate in the Cl2/HBr/O2 chemistry. It was clarified that a physical component is dominant in HfO2 etching in this chemistry. The possibilities of achieving a higher HfO2/SiO2 selectivity and of controlling the anisotropic/isotropic component in HfO2 patterning were also discussed. Moreover, it was clarified that the surface portion of the damaged layer created by the dry-etching step can be removed by a subsequent wet etching. Based on these results, the sub-100 nm patterning of poly-Si/HfO2 gate stacks was successfully demonstrated.
Formation of β-FeSi2-xGex by Ge-Segregation-Controlled Solid-Phase Growth of [a-Si/a-FeSiGe]n Multilayered Structure
Authors: Sadoh Taizoh , Owatari Masakazu , Murakami Yuji , Kenjo Atsushi , Yoshitake Tsuyoshi , Itakura Masaru , Miyao Masanobu
Published: February 2005

The solid-phase growth of [a-Si/a-Fe0.4Si0.5Ge0.1]
n
(n=1, 2, 4; total thickness: 500 nm) multilayered structures has been investigated. After annealing at 700°C, [a-SiGe/polycrystalline β-FeSi2-x
Ge
x
]
n
(x=0.5, 0.4, 0.2 for n=1, 2, 4, respectively) multilayered structures were formed. From the analysis of X-ray diffraction spectra, it was found that the lattice constants of β-FeSi1.5Ge0.5 changed from those of relaxed β-FeSi2 by 0.4–0.5%. The change decreased with increasing n, which was due to the segregation of Ge atoms from the a-Fe0.4Si0.5Ge0.1 layers to the a-Si layers becoming larger with increasing n. After annealing at 800°C, Ge atoms were completely swept out from the β-FeSi2-x
Ge
x
lattice. In addition, the agglomeration of β-FeSi2 occurred, and nanocrystals of relaxed β-FeSi2 and c-Si0.7Ge0.3 were formed. This technique for the formation of β-FeSi2-x
Ge
x
is expected to be useful for energy gap modulation for advanced optoelectrical devices.
Characterization and Comparison of Strained Si1-yCy Metal Oxide Semiconductor Field-Effect Transistor Grown by Gas-Source Molecular Beam Epitaxy and Hot Wire Cell Method
Authors: Watahiki Tatsuro , Ishihara Hanae , Abe Katsuya , Yamada Akira , Konagai Makoto
Published: February 2005

Strained Si1-y
C
y
metal oxide semiconductor field-effect transistors (MOSFETs) were fabricated by gas-source molecular beam epitaxy (GS-MBE) and the Hot Wire (HW) Cell method, and their electrical characteristics were compared. The strained Si1-y
C
y
films were grown by GS-MBE at 600°C and by the HW-Cell method at 200°C. The electron mobility of the MOSFET fabricated by GS-MBE showed a large decrease while that fabricated by the HW-Cell method showed a slight decrease. It was considered that this difference was due to the difference in non-substitutional carbon content. We found that the increase in growth temperature caused the decrease in substitutional carbon content and increase in non-substitutional carbon content. These results indicated that lowering the growth temperature decreases the non-substitutional carbon content and improves the electrical characteristics of Si1-y
C
y
films.
Effects of Thermal Stress on the Performance of Benzocyclobutene-Passivated In0.52Al0.48As/In0.53Ga0.47As High Electron Mobility Transistors
Authors: Yoon Myounghoon , Kim Taeho , Kim Daehee , Yang Kyounghoon
Published: February 2005

The effects of thermal stress on benzocyclobutene (BCB)-passivated In0.52Al0.48As/In0.53Ga0.47As high electron mobility transistors (HEMTs) were investigated and compared with those on silicon nitride and polyimide-passivated devices by DC, RF and microwave power characterization for the first time. In order to investigate the thermal stress effects on the devices passivated by different layers, DC and small-signal S-parameters were measured and characterized. Moreover, the variation of parameters, which are related to the RF performance of the devices, was analyzed based on small-signal parameters extracted during thermal stress. Compared to the polyimide-passivated devices, the BCB-passivated HEMTs exhibited more stable DC-g
m and access resistance (R
d+R
s) as functions of thermal stress time. The BCB-passivated HEMTs also showed a device performance comparable to that of the silicon nitride-passivated HEMTs that were stabilized by stabilization bake. In addition, the BCB-passivated HEMTs demonstrated better microwave power characteristics before and after 100 h thermal stress, indicating that BCB is an attractive passivation layer for In0.52Al0.48As/In0.53Ga0.47As HEMTs.
Reduction in Turn-on Voltage in GaInNAs and InGaAs-Based Double-Heterojunction Bipolar Transistors
Authors: Wu Cheng-Hsien , Su Yan-Kuin , Wei Shang-Chin , Chang Shoou-Jinn , Sio Chi-Cheong , Chen Wei-Chang
Published: February 2005

A new quaternary material of GaInNAs has been proposed as base material for GaAs-based double-heterojunction bipolar transistors (DHBTs). The used InGaAs as base material results in the lower band gap energy of the base layer in heterojunction bipolar transistors (HBTs) followed by a smaller turn-on voltage. However, the compressive strain induced by the InGaAs grown on GaAs diminishes the influence of indium-addition induced band gap energy reduction, and thus abate turn-on voltage reduction. By incorporating suitable amounts of indium (In) and nitrogen (N) into GaAs, a smaller band gap material of GaInNAs lattice-matched to GaAs substrate can be obtained. In this study, N-p-n InGaP/Ga0.985In0.015N0.005As0.995/GaAs DHBTs have been demonstrated. A turn-on voltage reduction of 215 mV compared to that of the conventional HBT with a GaAs base layer was obtained. The device has a peak current gain of 85 and shows good high-frequency characteristics of f
T and f
MAX, which are both higher than 40 GHz
Improvement of DC and RF Characteristics of AlGaN/GaN High Electron Mobility Transistors by Thermally Annealed Ni/Pt/Au Schottky Gate
Authors: Nanjo Takuma , Miura Naruhisa , Oishi Toshiyuki , Suita Muneyoshi , Abe Yuji , Ozeki Tatsuo , Nakatsuka Shigenori , Inoue Akira , Ishikawa Takahide , Matsuda Yoshio , Ishikawa Hiroyasu , Egawa Takashi
Published: February 2005

A thermally annealed Ni/Pt/Au metal structure was employed as the gate contacts of AlGaN/GaN high electron mobility transistors (HEMTs), and their DC and RF performances were investigated. This gate structure markedly improved the Schottky characteristics such as the Schottky barrier height and leakage current. Regarding the DC characteristics, the maximum drain current and off-state breakdown voltage were increased from 0.78 A/mm (Vg=1 V) to 0.90 A/mm (Vg=3 V) due to the improved applicability of the gate voltage and from 108 V to 178 V, respectively, by annealing the gate metals. In addition, a reduction of the transconductance was not observed. Furthermore, even after the deposition of SiNxpassivation film, the off-state breakdown voltage remained at a relatively high value of 120 V. Regarding the RF characteristics, the cut-off frequency and maximum oscillation frequency were also improved from 10.3 GHz to 13.5 GHz and from 27.5 GHz to 35.1 GHz, respectively, by annealing the gate metals whose gate length was 1 µm.
Low-Frequency Noise Caused by Substrate Current in AlGaAs/InGaAs HEMTs
Authors: Wada Masanori , Nakamoto Takayuki , Higuchi Katsuhiko
Published: February 2005

The surplus low-frequency noise (LFN) caused by substrate current is investigated for high electron mobility transistors (HEMTs). The substrate current increases with decreasing the substrate thickness, which causes the surplus LFN. It is found that the surplus LFN is proportional to the square of the substrate current, and becomes dominant in the case of a thinner substrate. We also discuss the restriction on the substrate thickness from the viewpoint of LFN.
Electrostatic Discharge Effects on AlGaN/GaN High Electron Mobility Transistors on Sapphire Substrates
Authors: Lee Seung-Chul , Her Jin-Cherl , Han Sang-Myeon , Seo Kwang-Seok , Han Min-Koo
Published: February 2005

The effects of electrostatic discharge (ESD) on the variation of electrical characteristics of AlGaN/GaN high electron mobility transistors (HEMTs), such as on-current, leakage current of gate and transconductance (g
m), have been investigated. The failure phenomena of HEMTs due to the ESD stress have also been studied. We have applied the ESD stress by transmission line pulsing (TLP) method, which is widely used in ESD stress experiments, and measured the electrical characteristics before and after applying ESD stress. The on-current after applying ESD stress was increased because the space between the drain and the gate was narrowed due to the migration of the metal caused by the high electric field and temperature under the ESD stress. The leakage current was decreased and g
m was changed slightly. The failure points were located mainly in the middle and on each side of the gate. AlGaN/GaN HEMTs, in contrast with GaAs HEMTs, have been shown to easily fail due to the poor thermal characteristics of the sapphire substrate.
High-Power 200 mW 660 nm AlGaInP Laser Diodes with Low Operating Current
Authors: Hiroyama Ryoji , Inoue Daijiro , Kameyama Shingo , Tajiri Atsushi , Shono Masayuki , Sawada Minoru , Ibaraki Akira
Published: February 2005

We have newly introduced a two-step-growth structure and a ridge stripe with steep sidewalls formed with a dry-etching process in the fabrication of a buried ridge stripe structure of a high-power 660 nm laser diode instead of a conventional three-step-growth structure and a ridge stripe with gentle sidewalls formed with a conventional wet-etching process in order to reduce the operating current. We have found that the two-step-growth structure provides better heat dissipation and the dry-etched ridge stripe structure offers higher characteristic temperature. The operating current under pulsed 200 mW at 70°C of the fabricated laser diode is 270 mA. This is the lowest value ever reported so far, to our knowledge. These laser diodes exhibit a kink level and a maximum light output power of 220 mW and higher than 300 mW, respectively. These laser diodes have also operated stably for 1500 h at 70°C with a light output power of 200 mW under the pulsed condition.
Very High Frequency Self-Pulsation and Stable Optical Injection Locking for Well-Defined Multi-Electrode Distributed Feedback Lasers
Authors: Nishikawa Satoshi , Gotoda Mitsunobu , Nishimura Tetsuya , Tokuda Yasunori , Matsumoto Keisuke
Published: February 2005

Self-pulsating multi-electrode distributed feed back (DFB) lasers with two active DFB regions and a passive phase tuning region between them were fabricated by introducing well-designed index-coupled gratings and phase shift. Free running self-pulsation and optical injection locking at 40 GHz were demonstrated for a device with detuned uniform gratings. Self-pulsation at a very high repetition of 275 GHz was experimentally confirmed for a device with a λ/4 phase shift in the DFB region. Dual mode laser oscillation occurred for both cases and the pulsating frequencies were determined by the wavelength separation of the two lasing modes. Numerical calculation of temporal behavior by solving traveling wave equations explained the observed optical spectra of the laser. Furthermore, based on the comparison between the calculated reflectivity spectra of individual DFB regions and the optical spectra of the laser, the origins of the lasing modes were determined.
Coupled Waveguide Devices Based on Autocloned Photonic Crystals
Authors: Shirane Masayuki , Gomyo Akiko , Miura Kenta , Ohtera Yasuo , Yamada Hirohito , Kawakami Shojiro
Published: February 2005

We proposed and demonstrated the operation of coupled waveguide devices based on photonic crystal (PC) structures fabricated by autocloning technology. Fundamental operations as optical directional couplers with PC waveguide structures were achieved at a 1550-nm wavelength. Furthermore, we demonstrated optical add/drop multiplexers with a 7-nm dropping bandwidth by adding Bragg reflectors with three-dimensional PC structures to the directional couplers.
Enhancement of Cavity-Q in a Quasi-Three-Dimensional Photonic Crystal
Authors: Ito Masamichi , Iwamoto Satoshi , Arakawa Yasuhiko
Published: February 2005

We propose and design a novel microcavity structure constructed in a quasi-three-dimensional (quasi-3D) photonic crystal (PhC), which is composed of a 2D PhC and a 1D distributed Bragg reflector (DBR). The quality factor (Q-factor) in the vertical direction of more than 30,000 and the Purcell factor up to 1,740 are numerically demonstrated. This Purcell factor is 250 times larger than that in the conventional air-bridged PhC slab cavity. Momentum space analysis indicates that this enhancement results from the strong optical confinement by DBRs in the vertical direction. It is expected that in a quasi-3D PhC a defect mode can be designed to extract light toward the vertical direction with a simple radiation pattern while maintaining a high Q-factor and a small mode volume. Therefore, the proposed structure is promising for high-efficiency surface-emitting light sources including single-photon emitters.
Novel Ring Waveguide Device in a 2D Photonic Crystal Slab –Transmittance Simulated by Finit-Difference Time-Domain Analysis–
Authors: Furuya Katsumi , Yamamoto Noritsugu , Watanabe Yoshinori , Komori Kazuhiro
Published: February 2005

We propose a novel ring waveguide device in a two-dimensional (2D) photonic crystal (PhC) slab with a hexagonal lattice of air holes in a semiconductor (Si/GaAs). The device consists of a single line-defect ring waveguide and other parts. We simulated the propagation of a 1 ps pulse in the device. We analyzed the device using the 2D finite-difference time-domain (FDTD) method. The 1 ps pulse is transmitted well through sharp 60 degree bends in the ring waveguide. We designed and examined four-port directional couplers (DC) as input/output (I/O) components for the ring device. Coupling between the I/O waveguides and the ring waveguide in the device can be achieved by the four-port DC. We adopted a defect pattern formed with a straight waveguide and a waveguide with bends as the DC structure. This pattern realizes the coupling length based on the coupled mode theory. Our DC with the new multistep-like waveguides improved both the directivity and coupling factor across most of the frequency band where there are practical guided-wave modes in the photonic band gap (PBG). The propagation loss of a 1 ps pulse in the ring waveguide is low, so the transmission property of the ring device depends mainly on the I/O parts. In this study, we confirmed that the ring device would be sufficient for such applications as delay lines.
InGaN/GaN Light Emitting Diodes with a Lateral Current Blocking Structure
Authors: Wang Hsin-Chuan , Su Yan-Kuin , Lin Chun-Liang , Chen Wen-Bin , Chen Shi-Ming
Published: February 2005

The light output of InGaN/GaN light-emitting diodes (LEDs) was improved by introducing a current blocking hole between the n-type and p-type bonding pads. The injected current was forced to spread out instead of directly passing along the nearest path between the p-type and n-type bonding pads. The light output of the LED with a current blocking hole at 20 mA was 7.2% higher than that of the conventional LED. The forward voltage of the LED with the blocking hole was 3.29 V at 20 mA, which is slightly higher than that of the conventional LED (3.26 V). LEDs with different current blocking hole sizes were also studied.
Ultrafast Coherent Control of Inhomogeneously Broadened System by an Area-Regulated Pulse Sequence
Authors: Tsurumachi Noriaki , Komori Kazuhiro , Hattori Toshiaki
Published: February 2005

We have proposed a new coherent control method that is available even for inhomogeneously broadened systems, which uses an area-regulated laser pulse sequence. It is expected to be applied to ultrafast optical devices without restriction of energy relaxation time.
Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
Authors: Kim Kyung Rok , Song Ki-Whan , Kim Dae Hwan , Baek Gwanghyeon , Kim Hyun Ho , Huh Jung Im , Lee Jong Duk , Park Byung-Gook
Published: February 2005

Novel metal-oxide-semiconductor (MOS)-based single-electron transistors (MOSETs) using band-to-band tunneling mechanism have been fabricated by the conventional silicon-on-insulator (SOI) MOSFET technologies. The fabricated SETs have tunnel barriers and quantum-dot formed by an extremely small channel between two p+-n+ tunnel junctions in the degenerately doped SOI MOSFET. Coulomb oscillation was observed in the subthreshold region at liquid nitrogen temperature and total capacitance of quantum-dot is 2.25 aF which is well matched to the device geometry. In order to validate the operation principle of our device, we have implemented an analytical device model in the simulation program with integrated circuit emphasis (SPICE). SPICE simulation of our model with a unique distribution function has reproduced the experimental results with good agreement for wide gate and drain bias range.
Analysis of Back-Gate Voltage Dependence of Threshold Voltage of Thin Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor and Its Application to Si Single-Electron Transistor
Authors: Horiguchi Seiji , Fujiwara Akira , Inokawa Hiroshi , Takahashi Yasuo
Published: February 2005

The back-gate voltage (V
BG) dependence of threshold voltage (V
th) is analyzed for n- and p-channel thin silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a self-consistent solution of the coupled Poisson and Schrödinger equations with a variational method. It is found that the slope (dV
th/dV
BG) is modulated not only by the gate-oxide and buried-oxide thickness but also by the distribution of the wave functions of carriers in the SOI layer and that the slope can be well described by an approximate equation derived assuming that a δ-function-like charge sheet exists at the average position of carriers in the SOI layer. From these findings, SOI-layer thickness and gate-oxide thickness or average position of carriers are shown to be determined precisely. Moreover, from the back-gate voltage dependence of peak voltage (defined as the gate voltage giving a drain current peak) of a single-electron transistor (SET), the average position of electrons in a Si island is shown to change, particularly in the few-electron regime, probably due to electron-electron interaction.
Electron Transport in Molecular Enamel Wires
Authors: Belosludov Rodion V. , Farajian Amir A. , Mizuseki Hiroshi , Ichinoseki Kyoko , Kawazoe Yoshiyuki
Published: February 2005

The electronic transport through a single molecular enamel wire such as an inclusion complex between polythiophene (PT) and β-cyclodextrin (β-CD) molecules has been investigated by the nonequilibrium Green's function formalism of quantum transport and density functional theory (DFT) of electronic structures using local orbital basis sets. Major conducting channels in all structures correspond to the states extended along the entire length of the system. Encapsulating PT in β-CDs might be a good method for obtaining an isolated single molecular wire, practicularly if accompanied by doping in order to enhance the conductance.
Transition Energy Control via Strain in Single Quantum Dots Embedded in Micromachined Air-Bridge
Authors: Nakaoka Toshihiro , Kakitsuka Takaaki , Saito Toshio , Arakawa Yasuhiko
Published: February 2005

We have fabricated a micromachined air-bridge in which InGaAs self-assembled quantum dots are embedded. Electrostatic voltage applied between the air-bridge and the substrate pulls the air-bridge down. The deformation of the bridge produces additional strain on the matrix and the dots modifying the electronic states. The modification has been detected through a photoluminescence peak shift of a single dot. The effect of the deformation on the electronic states is evaluated with the aid of theoretical calculation using a finite element method. The good agreement between calculated and experimental energy shifts demonstrates that the energy shift is due to the strain induced by the bridge deformation. Based on the result, we discuss the capability of this micromachined device with quantum dots to control the zero-dimensional electronic system and to measure small deformation and strain.
A Solid-State Multicolor Light-Emitting Device Based on Ballistic Electron Excitation
Authors: Nakajima Yoshiki , Uchida Tetsuya , Toyama Hajime , Kojima Akira , Gelloz Bernard , Koshida Nobuyoshi
Published: February 2005

It is demonstrated that a solid-state luminescent device based on ballistic electron excitation can be fabricated using blue- or red-light-emitting materials as a fluorescent film. This device is composed of an n-type Si substrate, a nanocrystalline porous polysilicon (nc-PPS) layer, an organic fluorescent film, and a semitransparent thin Au film. When a positive bias voltage higher than approximately 10 V is applied to the Au top contact, the device uniformly emits blue or red light. The light intensity sharply increases with increasing bias voltage. The measured luminescence band almost coincides with the original photoluminescence spectrum of the deposited fluorescent material. The results indicate that light emission is due to the luminescence excited by ballistic electrons generated in the nc-PPS layer under a high electric field. This device is useful for applications to multicolor ballistic lighting.
Au/GaAs Magnetoresistive-Switch-Effect Devices Fabricated by Wet Etching
Authors: Sun Zhi-gang , Mizuguchi Masaki , Akinaga Hiroyuki
Published: February 2005

Au/GaAs magnetoresistive-switch-effect (MRS effect) devices were successfully fabricated by the wet etching method. A large MRS effect was observed. In the current-voltage curves, the current jumped steeply at a threshold voltage of 32.0 V. The threshold voltages shifted to higher values and became less steep with increasing magnetic field. Above 2,000 Oe, no current jump driven by the applied voltage could be observed. The magnetoresistance (MR) ratio reached 1,000,000% at 15,000 Oe when the devices were operated above the threshold voltage. Also magnetic field sensitivity was greatly improved. To achieve a 1000% MR ratio, only 300 Oe was required at 32.2 V.
Electron Transition Energy for Vertically Coupled InAs/GaAs Semiconductor Quantum Dots and Rings
Authors: Li Yiming , Lu Hsiao-Mei
Published: February 2005

We investigate the transition energy of vertically coupled quantum dots and rings (VCQDs and VCQRs) with a three-dimensional (3D) model under an applied magnetic field. The model formulation includes (1) the position-dependent effective mass Hamiltonian in the nonparabolic approximation for electrons, (2) the position-dependent effective mass Hamiltonian in the parabolic approximation for holes, (3) the finite hard-wall confinement potential, and (4) the Ben Daniel-Duke boundary conditions. We explore small VCQDs and VCQRs with disk (DI) and conical (CO) shapes. For small VCQDs and VCQRs, the electron-hole transition energy is dominated by the interdistance d which plays a crucial role in the tunable states of structures. Under zero magnetic field, there is about 25% variation in the electron ground state energy for both InAs/GaAs DI-shaped VCQDs and VCQRs with d varying from 0.4 nm to 4.8 nm. The energy spectra of the CO-shaped VCQDs are the most stable against the structure interdistance deviations (among dots and rings of the same volume). For a fixed d, VCQDs show diamagnetic shift; contrarily, VCQRs imply a nonperiodical transition among the lowest electron energy states. The energy band gap of VCQRs oscillates nonperiodically between the lowest electron and holes states as a function of external magnetic fields. Our investigation is constructive for studying the magneto-optical phenomena of the nanoscale semiconductor artificial molecules.
Fully Depleted SOI Complementary MOS Device with Raised Source/Drain for 90 nm Embedded Static RAM Technology
Authors: Park Chang Hyun , Oh Myung Hwan , Kang Hee Sung , Oh Chang Bong , Jung Mu Kyeng , Kim Young Wug
Published: February 2005

Fully depleted silicon-on-insulator (FD SOI) devices with 70 nm gate lengths for embedded static random access memory (SRAM) technology were investigated for different SOI film thickness. Transistor performances of 700 µA/µm and 320 µA/µm were obtained for n-type and p-type metal-oxide semiconductor field effect transistor (NMOSFET and PMOSFET) devices, respectively at 1.0 V operation voltage and I
off=75 nA/µm. Si selective epitaxial growth (SEG) process was well optimized. Both the single raised (SR) and double raised (DR) source/drain process were studied to reduce parasitic series resistance. For the DR process, both NMOSFET and PMOSFET performance are improved by 9 and 13% respectively, compared to the SR process. Drain induced barrier lowering (DIBL) was improved from 100 mV to 13 mV as the SOI film thickness was scaled down from 50 nm to 17 nm. Due to the self-heating effect, the AC current is 15% higher than the DC current for the case of 40 nm SOI thickness. The static noise margin (SNM) for a 1.1 µm2 6T-SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.
A High-Aspect-Ratio Silicon Gate Formation Technique for Beam-Channel MOS Transistor with Impurity-Enhanced Oxidation
Authors: Katakami Akira , Kobayashi Kei , Sunami Hideo
Published: February 2005

In this study, a three-dimensional (3D) transistor with 1-µm-high beam is proposed. This is named beam-channel transistor (BCT) after its “beam structure of channels”. One of the key processes for fabricating the BCT is the gate-formation process because BCT has a very high aspect-ratio of the beam on which the gate should be formed by an anisotropic dry etching process such as reactive ion etching (RIE). To cope with the problem, isotropic dry etching and impurity-enhanced oxidation (IEO) are used. As a result, the selectively oxidized polysilicon gate is expected to form relatively shorter gate and sidewall spacers facilitating the formation of lightly-doped drain (LDD) or self-aligned silicided source and drain. By utilizing this gate formation process, it is speculated that BCT with a 1-µm-high beam and 0.2-µm channel length might successfully be fabricated using adequate channel doping design. Thus, the BCT can provide strongly area-efficient performance.
P-Channel Vertical Double-Gate MOSFET Fabricated by Utilizing Ion-Bombardment-Retarded Etching Processs
Authors: Masahara Meishoku , Hosokawa Shinichi , Matsukawa Takashi , Ishii Kenichi , Liu Yongxun , Tanoue Hisao , Sakamoto Kunihiro , Yamauchi Hiromi , Kanemaru Seigo , Suzuki Eiichi
Published: February 2005

It is experimentally demonstrated that the novel ion-bombardment-retarded etching (IBRE) process can be applied to fabricate p-channel (p-ch) vertical double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) on bulk Si substrates. By utilizing the IBRE process, p-ch vertical DG MOSFETs with 12- to 42-nm-thick Si vertical channels have been successfully fabricated for the first time. The fabricated vertical DG MOSFETs clearly exhibit the unique nature of the DG structure, i.e., the short-channel-effect (SCE) immunity by decreasing the channel thickness. It is shown that a very low S-slope and relatively high current drive are successfully achieved for the p-ch vertical DG MOSFET with the thinnest channel thickness.
SOI SRAM/DRAM Cells for 0.5 V Operation
Authors: Terauchi Mamoru
Published: February 2005

A four transistor static random access memory (4T SRAM) cell and a silicon-on-insulator dynamic random access memory (SOI DRAM) gain cell, both operating at low supply voltage, are proposed. Both cells actively exploit the body region of partially depleted SOI metal-oxide-semiconductor field-effect transistors (MOSFETs). The body region of an SOI MOSFET with an `H-shaped' gate electrode is used as a resistor in the inverter pair of the proposed SRAM cell. Its resistance is controlled independently from the threshold voltage of the main MOSFET. Simulation shows the stable operation of the proposed SRAM cell under a supply voltage of 0.5 V. The SOI DRAM gain cell consists of a p-channel junction field-effect transistor (JFET) and an n-channel MOSFET, where the source diffusion of the MOSFET functions as the gate diffusion of the JFET as well. Signal charge is stored in the gate diffusion capacitance of the JFET, leading to modulation in its source-drain conductance. Simulation also reveals that the proposed SOI DRAM gain cell operates properly under a supply voltage of 0.5 V.
Complete Surface-Potential-Based Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistor Model for Circuit Simulation
Authors: Kitamaru Daisuke , Uetsuji Yasuhito , Sadachika Norio , Miura-Mattausch Mitiko
Published: February 2005

The circuit simulation model Hiroshima-university STARC IGFET Model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI metal-oxide-semiconductor field-effect-transistor (MOSFET) is developed based on the surafce-potential description. To include all device features of the SOI-MOSFET explicitly, the surface potential values not only at the SOI surface but also the back side, as well as the bulk back-gate are solved iteratively. The total iteration for the potential calculation requires only about twice as much calculation time as the bulk-MOSFET case, solving ony at the surface. The model reproduces measured I–V characteristics within numerical accuracy, and is proved stable circuit convergence.
A Workable Use of the Floating-Body Silicon-On-Sapphire MOSFET as a Transconductance Mixer
Authors: Lam Sang , Lee Wai-Kit , Chan Alain C.-K. , Mok Philip K. T. , Ko Ping K. , Chan Mansun
Published: February 2005

The operation, biasing, and measured performances of the floating-body silicon-on-sapphire (SOS) MOSFET as a single-gate FET upconversion mixer are presented. Despite the floating-body effects of the SOS MOSFET, the upconversion RF mixer operation is feasible by utilizing the approximate square-law transfer characteristics of the SOS MOSFETs. With a drawn gate length L
min=0.8 µm, the single-gate SOS MOSFET mixer gives an approximately 1.5-dB power conversion gain, an input-referred third-order intercept point (IP3) of 5 dBm while requiring a local oscillator (LO) power of 5.5 dBm with an RF bandwidth of 2 GHz and an IF bandwidth of 400 MHz. The current consumption is about 8 mA with a 3 V voltage supply. The realization of a high output bandwidth and high IF RF mixer is demonstrated to be possible with the floating-body SOS MOSFET.
Low-Frequency Noise in Partially Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures
Authors: Chen Kun-Ming , Hu Hsin-Hui , Huang Guo-Wei , Yeh Wen-Kuan , Chang Chun-Yen
Published: February 2005

The low-frequency noise characteristics of partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator technology at various temperatures were investigated. For floating-body devices, a Lorentzian-like noise overshoot is observed due to the floating-body effect. The noise overshoot is dependent on temperature and bias, and can be reduced using a source-to-body-connected structure. At high temperature or high drain bias, the 1/f noise will be observed, and it is temperature-independent due to the trap-induced mobility fluctuation in the channel.
Proposal for a New Ferroelectric Gate Field Effect Transistor Memory Based on Ferroelectric-Insulator Interface Conduction
Authors: Hirooka Gen , Noda Minoru , Okuyama Masanori
Published: February 2005

A new type of ferroelectric gate field effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and needs no semiconductor. The FET has been fabricated by forming drain and source electrodes on a SiON/Si substrate, depositing SrBi2Ta2O9 (SBT) film, and then forming the gate electrode. Drain current versus gate voltage characteristics show counterclockwise hysteresis loop similarly to the conventional metal-ferroelectric-insulator-semiconductor-FET (MFIS-FET), and the loop is due to polarization hysteresis of the SBT film. The FET shows that 1) the On/Off ratio of the conduction current is 3.8 at 0 bias voltage and 2) the relationship of the conduction current to channel width and length coincides well with the predicted characteristics.
Proposal of New Nonvolatile Memory with Magnetic Nano-Dots
Authors: Sakaguchi Takeshi , Hong Youn-Gi , Kobayashi Motoki , Takata Masaaki , Choi Hoon , Shim Jeoung-Chill , Kurino Hiroyuki , Koyanagi Mitsumasa
Published: February 2005

In this study, a new nonvolatile memory with magnetic nano-dots (MNDs) was proposed. A relatively large anisotropic change of gate current–voltage characteristics by the magnetization in magnetic non-volatile memory with Co nano floating gate and Ni-Fe control gate was obtained. A Co magnetic nano-dot film with very high dot density of 2×1013 cm-2 was successfully formed by sputtering with optimized target composition. A small anisotropic change of gate current–voltage characteristics by the magnetization in MND memory with Co MNDs and Ni-Fe control gate was observed.
70 nm Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices Using Fowler-Nordheim Programming and Hot Hole Erase Method
Authors: Chae Soodoo , Lee Changju , Kim Juhyung , Sung Sukkang , Sim Jaeseong , Kim Moonkyung , Yoon Sewook , Jeong Younseok , Ryu Wonil , Kim Taehun , Park Byung-Gook , Lee Jo-won , Kim Chungwoo
Published: February 2005

70 nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with an ultra-thin oxide-nitride-oxide (ONO) film on an silicon-on-insulator (SOI) wafer are fabricated. If we consider the program/erase threshold voltage window as 2 V, the program time is approximately 1 ms at an 8 V program voltage and the erase time is about 200 us at a -6 V erase voltage using FN write and the 2-sided hot hole injection method. It is observed that the 2-sided hot hole injection can completely erase the electrons in the ONO thin film on a 70 nm channel. The memory window is almost constant after 100,000 cycles, and the retention characteristics show that the threshold voltage after 106 s is predicted as 0.75 V by extrapolation.
A Novel Sensing Circuit for High Speed Synchronous Magneto-Resistive RAM
Authors: Kim Hyejin , Lee Seungyeon , Lee Seungjun , Shin Hyungsoon , Kim Daejung
Published: February 2005

A novel sensing scheme for a magneto-resistive random access memory (MRAM) with a twin cell structure is presented. New sensing circuit has very simple structure while providing stable operation. Voltage-controlled transistor switch limits the voltage across the magnetic tunnel junction (MTJ) under 400 mV while reading. The circuit layout is small enough to fit into 4-cell pitches that high speed synchronous operation is made possible in MRAMs as in DRAMs or SRAMs. We have fully integrated a 256 bit synchronous MRAM operating at 100 MHz with 0.35 µm complementary metal oxide semiconductor (CMOS) technology.
Evaluation of Aluminum Oxide Thin Film in Magnetic Tunneling Junction Utilizing Scanning Probe Microscopy
Authors: Ham Ho Chan , Lee Kye Won , Park S. J. , Kim T. W. , Chung Ilsub
Published: February 2005

We attempted to evaluate the role of tunneling oxide in a magnetic tunneling junction (MTJ) cell using scanning probe microscopy (SPM). In particular, we focused on the variation in the thickness uniformity of aluminum oxide thin film, thereby correlating the topology with its current image. The local I-V measurement revealed that a preferred current conduction through thinner aluminum oxide exists. The cross-sectional image confirmed that the variation in the thickness of aluminum oxide creates weak points for current conduction. Finally, we could obtain a tenfold the MR value in the MTJ cell by improving the thickness uniformity of the aluminum oxide thin film.
Design and Demonstration of High Breakdown Voltage GaN High Electron Mobility Transistor (HEMT) Using Field Plate Structure for Power Electronics Applications
Authors: Saito Wataru , Takada Yoshiharu , Kuraguchi Masahiko , Tsuda Kunio , Omura Ichiro , Ogura Tsuneo
Published: February 2005

AlGaN/GaN power high electron mobility transistors (HEMTs) with a breakdown voltage of 600 V are fabricated and demonstrated as switching power devices for motor drive and power supply applications. A high breakdown voltage was realized in the fabricated power-HEMT by the field plate technique and an ultra low on-state resistance of 3.3 mΩ·cm2, which is 20 times lower than the silicon limit, due to the high critical field of the GaN material and the high mobility in a two-dimensional electron gas channel. A device with the double-field plate structure was also designed using two-dimensional device simulation to increase the breakdown voltage without any increase of the GaN layer thickness.
Base Current Control in Low-VBE-Operated SiGeC Heterojunction Bipolar Transistors Using SiGe-Cap Structure and High-Carbon-Content Base
Authors: Saitoh Tohru , Kawashima Takahiro , Kanzawa Yoshihiko , Sato-Iwanaga Junko , Idota Ken , Takagi Takeshi , Ohnishi Teruhito , Yuki Koichiro , Sano Tsuneichiro , Sawada Shigeki
Published: February 2005

We have demonstrated the low-V
BE operation of SiGeC heterojunction bipolar transistors by introducing a novel device design concept using the SiGe cap structure and high Ge- (up to 25%) and C- (up to 0.8%) content base. We successfully controlled the base current by designing the SiGe cap structure and C content, which enabled us to obtain suitable values of h
FE and B
V
CEO, while maintaining a high collector current and high-frequency performance. We clarified that the recombination around the emitter-base junction is enhanced by introducing the SiGe cap structure and high C content, which contribute to the increase of the base current.
Micro Cu Bump Interconnection on 3D Chip Stacking Technology
Authors: Tanida Kazumasa , Umemoto Mitsuo , Tanaka Naotaka , Tomita Yoshihiro , Takahashi Kenji
Published: February 2005

The three-dimensional (3D) chip stacking LSI technology under development at the Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology to realize high-density and high-speed transmission, and superfine flip-chip bonding technologies in 20-µm-pitch microbumps on Cu through-via (TV) are substantial technologies. As for advanced bonding technology, Cu bump bonding (CBB) utilizing Sn alloy is a simple process to connect Cu TVs directly without the formation of bumps on the device back surface, and the influence of the intermetallic compound (IMC) on the minute interconnection focusing on the bondability and reliability was verified, and the following results were obtained. The IMC state formed at the bonding interface depended on bonding temperature, and was confirmed as multilayered Cu6Sn5 and Cu3Sn at 240°C, and single-layered Cu3Sn at 350°C. The IMC state is the governing factor of bondabilities of Cu bump interconnection in a 20-µm-pitch. The electroresistance value of the Cu bump interconnection was approximately 0.45 Ω, and no significant difference was confirmed under each condition. Young's modulus values of IMC (Cu6Sn5:112.6 GPa and Cu3Sn:132.7 GPa) were obtained by the nano-indentation test. The Sn-Ag layer as bonding material should be reduced to Cu-Sn IMC, and a low-rigid resin was preferable in terms of interconnection reliability based on the results of finite element method (FEM) analysis. Finally, the vertical interconnections utilizing CBB were formed, and the increase in electrical resistance by stacking one TV chip was approximately 0.03 Ω. Therefore, sufficient electrical vertical interconnection of Cu TV in a 20-µm-pitch was performed.