Role of Proportion of Surrounding Gate on the Improved Transient Behavior of MIS Tunnel Diode with Ultra-Thin Metal Surrounded Gate (UTMSG)
Authors: Huang Sung-Wei , Hwu Jenn-Gwo 
Published: September 2023

Metal-Insulator-Semiconductor tunnel diodes (MISTD) are widely used in modern integrated circuits, and have shown the potential in dynamic memory [1], [2]. To recognize the memory states more easily, efforts should be made to enhance the transient behavior. Recently, MISTD with ultra-thin metal surrounded gate (UTMSG) had been proposed in [3] and [4], presenting improved transient current and transient capacitance. In this work, we further modulated the proportion of surrounding gate, S, and found increased transient behavior for larger S.

Fig. 1(a) and (b) illustrate the structure of UTMSG and planar MISTD, respectively. For UTMSG, the total gate is composed of a thick metal center gate and a resistive thin metal surrounding gate. Fig. 2 shows the process flow and the anodic oxidation system. For UTMSG, after defining the center gate by photolithography, dilute nitric acid was used to form a very thin aluminum oxide layer on the edge. 10 nm Al was then evaporated as the resistive surrounding gate. Table 1 lists the detailed parameters and the proportion of surrounding gate, S. Fig. 3(a) shows the transient read currents for UTMSG and planar, with inset illustrated the voltage program. Fig. 3(b) shows the read currents extracted at 40 ms under different read voltages after a 2 V write pulse. All UTMSG show larger transient current than planar. Besides, UTMSG with larger S would have better performance. The reason could be explained by Fig. 3(c). The insulating aluminum oxide interlayer and the resistive thin metal surrounding gate together result in a distributed resistance, leading to an RC time delay during voltage switching. During read, the electrons stored under the surrounding gate would take longer to response. Therefore, larger current could be read out, due to the edge late response. Consequently, more electrons would be delayed for larger S, and larger transient current would be expected.

Fig. 4(a) and (b) show the AC signal model and the reverse-bell shape capacitance-voltage (C-V) characteristics of UTMSG, which were discussed in detail in previous work [5]. When Rsi, determined by the electron density under gate, is small enough such that the cut-off frequency 1/2πRsiCs,o is larger than the AC frequency, Cs,o could be read out. Fig. 5 shows the frequency dispersion of C-V curves. For lower frequencies, lower VG is needed for the AC signal to pass through.

Fig. 6(a) shows the 10kHz C-V curves, on which ± 0.5 V voltage pulse were performed to read out two capacitance states. Fig. 6(b) shows the transient capacitance read at 0 V. When switching from + 0.5 V to 0 V, excess electron would be stored under gate initially. To balance the gate voltage, depletion region would shrink and high capacitance state would be measured, which would be more significant for UTMSG due to more delay of electron. For UTMSG at – 0.5 V and 0 V, depletion capacitance under center gate Cs,i and under total gate Cs,i + Cs,o would be read out, respectively. This means after applying a - 0.5 V pulse and then read at 0 V, UTMSG devices would experience a larger change of capacitance. Moreover, since the capacitance at - 0.5 V is lower for UTMSG with larger S, the change of capacitance would be larger. The two state capacitance windows measured at 30 ms are shown in Fig. 6(c), where larger capacitance window could be observed for UTMSG with larger S. Finally, the capacitances when sweeping voltage forwardly and backwardly and the separation between them were shown in Fig. 7(a) and (b) for UTMSG and planar devices. All UTMSG show larger separations, which further confirms the improved transient capacitance window observed in Fig. 6.

In conclusion, transient behavior could be further improved by increasing the proportion of surrounding gate in UTMSG MISTD, and 17x read current and 14x capacitance window could be measured. The discovery in this work might be beneficial for the future dynamic memory design.

Acknowledgement: This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-192-MY3 and NSTC 111-2622-8-002-001

[1] M. A. Green, F.D. King and J. Shewchun, Solid-State Electronics, 17, 6, pp. 551-561, (1974).

[2] S.-W. Huang and J.-G. Hwu, IEEE Trans. on Electron Dev., 68, 12, pp. 6580-6585 (2022).

[3] K.-H. Tseng, C -S. Liao and J. -G. Hwu, IEEE Trans. on Nanotech., 16, 6, pp. 1011-1015, (2017).

[4] C.-D. Lin and J.-G. Hwu, ECS Trans.,
85, 51, (2018).

[5] S.-W. Huang and J.-G. Hwu, IEEE J. of the Electron Devices Soc., 9, pp. 1041-1048, (2021).

Figure 1