Favorable Combination of Schottky Barrier and Junctionless Properties in Field-Effect Transistors for High Temperature Applications
Authors: Krauss Tillmann Adrian , Wessely Frank , Schwalke Udo 
Published: February 2020

High-temperature transistors are of great interest for industrial applications, for instance, oil&gas and geothermal exploration, avionic, space, automotive and energy conversion. Especially, energy conversion electronics using wide-bandgap power transistors, i.e. SiCFET, in combination with high-temperature silicon gate-driver circuits can significantly increase system efficiency and reduce costs [1]. Our improved planar virtually dopant-free silicon-based double gate SOI FET with Ni and WTiN front-gate electrodes demonstrates ultra-low drain leakage currents at high-temperatures opening a path to record operating temperatures for silicon-based FET devices.

Device Structure

The long-channel device fabrication relies on a standard CMOS-compatible prototyping process using SOITEC Smart-Cut™ SOI-substrates with the lowest commercially available boron background doping of 1E15cm-3 enabling high carrier mobilities. Mid-gap Schottky barrier (SB) contacts are fabricated via nickel silicidation. The metal front-gate (FG) electrode consist of reactively sputtered WTiN for NMOS or Nickel for PMOS operation on a 8nm thick SiO2 gate dielectric. Channel height (CH) is approximated to 15nm. The back-gate (BG) formed by the silicon handle wafer is insulated by 145nm buried SiO2 (BOX) (Fig.1).

Device Operation

The device is modeled as a combination of two interacting FETs, one fully ambipolar Schottky barrier backside FET and a second unipolar junctionless (JL) topside FET [2,3].

The BG influences the whole body layer including the S/D Schottky barriers forming an ambipolar enhancement mode SBFET. Therefore, the dominant charge carrier type, i.e. electrons (VBG»0V) or holes (VBG«0V) in the channel region is defined by the BG polarity. In this configuration, the channel is located close to the body silicon to BOX interface (Fig.3). The charge carriers originate from the mid-gap NiSi SB contacts and enter the body layer at room temperature mainly by thermionic field emission (TFE) and at elevated temperatures by thermionic emission (TE) (Fig.2). In contrast, the depletion mode JLFET formed by the FG electrode only locally affects the charge carrier density in the middle of the channel and controls the current flow between source and drain with excellent electrostatic control as illustrated by the carrier density simulation in Fig.3. The combination of the enhancement and depletion mode operation in one device can appositely be summarized as enhancement suppression or dehancement mode operation (DeFET).

Results & Discussion

P- and NMOS transistor behavior is realized by applying the appropriate BG polarity to the very same device enabling transistor level reconfigurability (Fig.4). Maximum on-state current and threshold voltage are proportional to the magnitude of VBG (Fig.4). The work function difference between Ni and WTiN metal front-gate devices as well as process variations result in a significant threshold shift (Fig.4). The channel height (Fig.1) is a crucial parameter in device fabrication as it directly affects the off-state leakage current and threshold voltage [7].

Regarding high-temperature performance, the use of the SOI substrate eliminates bulk drain leakage while the introduction of SB contacts minimizes the band-to-band tunneling effect in comparison to classic steep S/D pn-junctions. For rising operating temperatures up to 470K, the on-state current increases from 8 to 46µA as TFE and TE increase allowing an overcompensation of the temperature dependent carrier mobility degradation effect (Fig.5,right). At the same time the drain leakage current is only increasing from <100fA to 2nA from 300 to 470K due to the high potential barrier induced by the FG (Fig.5,left). Gate leakage currents are <6pA during all measurements. Furthermore, PMOS behavior with nickel metal front-gate follows the same trends.

Device simulations predict that reducing the channel height and introducing mid-κ gate dielectrics, i.e. Al2O3, renders record operating temperatures possible even for scaled devices limited only by reliability. Comparing the here presented DeFET generation with previous generations and other long-channel Si-based high-temperature FET structures illustrates the clear advantage of our device concept in suppressing drain leakage currents at high temperatures (Fig.6) [4-7].

Conclusion

In this contribution, we demonstrate by means of experimental measurement data and device simulations the significantly improved drain leakage suppression at high operating temperatures of the planar dehancement mode FET CMOS technology in comparison to our previously published results in [7]. The combination of SB and JLFET properties opens a possible path for silicon based FET operation up to temperatures of 700K for various industrial applications.

References

[1] Blalock et al., IEEE Trans. on Power Electronics, 30(3), 2015.

[2] Walter et al., Phys. Status Solidi C, 11(11), 2014.

[3] Larson and Snyder, IEEE Trans. on Electron Devices, 53(5), 2006.

[4] Colinge et al., IEEE Electron Device Letters, 14(1), 1993.

[5] Colinge et al., IEEE Trans. on Electron Devices, 57(3), 2010.

[6] Cristoloveanu et al., Microelectronics Reliability, 47(12), 2007.

[7] Krauss et al., ECS Journal of Solid State Science and Technology, 4(5), 2015.

Figure 1