High Quality (001)-Oriented Nanolayers of Goi Fabricated through 3D Condensation for Augmented MOSFETs Based Devices
Authors: Takala Adonis Steve , Gourhant Olivier , Verdier Stephane , Levert Theo , Madaci Ismail , Duluard Christophe , Mallet Anne-Flore , Arette-Hourquet Adam , Bollani Monica , Salvalaglio Marco , Favre Luc , Berbezier Isabelle 
Published: December 2024

The fabrication of Ge strained (and/or relaxed) layers or nanolayers embedded in an oxide layer has attracted a great deal of attention for various applications such as photodetectors, resonant tunneling devices, transistors, etc. In this work, the integration of fully relaxed Ge-on-insulator (GOI) nanolayers with silicon was demonstrated by using a combination of epitaxy / patterning and condensation. Arrays of nanoscales patterns featuring ultra-thin (3-4 nm) GOI with high crystalline quality, in various shapes such as rectangular strips and mesa structures with rounded and thicker end edges are fabricated for augmented Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) based devices. A 20 nm Si1-xGex layer (with x=0,17) is epitaxially grown on a 300 mm (001) Silicon-on-insulator (SOI) wafer with 8 nm thick top silicon layer and 25 nm buried oxide (BOX) layer (Figure 1.a), using an industrial-standard Reduced Pressure Chemical Vapor Deposition system (RP-CVD). The epitaxy process parameters were optimised to insure a pseudomorphic growth of the SiGe layer with a thickness non-uniformity variation of 1 nm along the entire 300 mm diameter as shown in Figure 2a-b. After growth, (Figure 1.b), arrays of submicron-wide stripes with various rectangular shapes are patterned on the SOI/SiGe using either conventional UV photolithography and reactive ion etching processes (Figure 1.c) or e-beam lithography (Figure 3). Subsequently, the patterned wafer is then introduced into an industrial dry oxidation furnace to perform the condensation which consists of the selective oxidation of Si1–3 associated to the repulsion of Ge atoms at the bottom of the layer (Figure 1.d). During this selective oxidation, the top surface and the sidewalls of the patterns are simultaneously oxidized but with different kinetics4, resulting in 3D condensation. This process is engineered to consume all the Si atoms contained in the SOI/SiGe layers to generate high crystal quality GOI nanolayers with thicknesses about 3-4 nm.

The resulting GOI nanolayers have great potential for augmented MOSFET based devices, since Ge mobility far exceeds Si mobility5,6. In addition, when the GOI becomes thinner, there is a noticeable increase of the mobility due to the quantum confinement (modulation of the GOI band7).

The uniformity in thickness and the oxidation kinetics are assessed by spectroscopic ellipsometry. The chemical composition of the layer is determined by XPS, and EDS. The topography of surface and interface and the morphological evolution of the GOI nanolayers are analysed by AFM, FIB-SEM and HR-TEM. as the variation in the oxidation kinetics between the top surface and the sidewalls affects the shape of the resulting GOI nano patterns. As it is well known that the mechanical stress which increases with enrichment, can lead to the formation of crystalline defects1 , the crystal quality and the strain are thoroughly examined using HR-TEM-GPA and µRaman spectroscopy.

Furthermore in this study, it is shown that a sliding behaviour of the GOI/BOX interface, due to weak bonds between the two layers8 can relieve mechanical stress in the Ge-rich layer. Such behaviour enables the creation of fully relaxed and defect-free pure Ge nanolayers (Figure 4). In addition, the process allows the fabrication of well organised arrays of Ge nanodots embedded in the oxide layers. These nano-objects are well suited for resonant devices.

1 S. Nakaharai, T. Tezuka, N. Hirashita, E. Toyoda, Y. Moriyama, N. Sugiyama and S. Takagi, Semiconductor Science and Technology, 2006, 22, S103.

2 D. Valenducq, O. Gourhant, E. Blanquet, F. Deprat, F. Abbate, V. Guyader, and D. Rouchon, in 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2019, pp. 1–4.

3 S. Nakaharai, T. Tezuka, N. Hirashita, E. Toyoda, Y. Moriyama, N. Sugiyama and S. Takagi, Journal of Applied Physics, 2009, 105, 024515.

4 E. A. Irene, H. Z. Massoud and E. Tierney, Journal of The Electrochemical Society, 1986, 133, 1253.

5 K. J. Kuhn, ECS Transactions.

6 K. J. Kuhn, IEEE Transactions on Electron Devices, 2012, 59, 1813–1828.

7 K. . -. W. Jo, C. . -. M. Lim, W. . -. K. Kim, K. Toprasertpong, M. Takenaka, and S. Takagi, in 2019 IEEE International Electron Devices Meeting (IEDM), 2019, p. 29.1.1-29.1.1.

8 M. Houssa, G. Pourtois, M. Caymax, M. Meuris, M. M. Heyns, V. V. Afanas’ev and A. Stesmans, Applied Physics Letters, 2008, 93, 161909.

Figure 1