Impact of Gate Stack Dielectric on Intrinsic Voltage Gain and Low Frequency Noise in Ge pMOSFETs
Authors: Oliveira Alberto Vinícius de , Agopian Paula Ghedini Der , Martino Joao Antonio , Fang Wen , Arimura Hiroaki , Mitard Jerome , Mertens Hans , Simoen Eddy , Mocuta Anda , Collaert Nadine , Thean Aaron , Claeys Cor 
Published: February 2020

Concerning future high-performance applications, materials such as germanium (Ge) and III/V, have been extensively studied as alternative for the channel region instead of silicon. The high mobility makes Ge a promising channel material for both low power and high performance applications of advanced devices [1]. On the other hand, gate stack engineering is challenging in Ge devices, in view of the higher density of interface states typically observed [2]. 

This work analyses the influence of gate stack layers (GSL) on intrinsic voltage gain and low frequency noise in planar Ge pMOSFET devices. The GSL is composed of germanium oxide (GeOx), aluminum oxide (Al2O3) and hafnium oxide (HfO2), where both Al2O3 and HfO2film thicknesses were varied. There are also two different plasma powers under evaluation. Furthermore, the analog parameters were analyzed at high temperature, ranging from 25 to 150 °C.

The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are four wafers with different dielectric composition as shown in table 1. The planar device dimensions are channel width (W) of 10 µm and channel length (L) of 130, 250, 1 and 10 µm. 

The low frequency noise (LFN) was measured in linear operation showing no clear impact of the gate stack processing. From the normalized noise power spectral density versus drain current it is derived that the predominant flicker noise is due to trapping by border traps in the gate stack and more specifically in the GeOx layer. Representing the square root of the input-referred voltage noise spectral density (SVG
0.5) versus Id/gmyields the flat-band value (intercept) and the mobility scattering coefficient is obtained from the slope of a linear fit in Fig. 1. 

Among the studied wafers (figure 2), D20 (which has the thinnest Al2O3 thickness) presents the lowest value of the intrinsic voltage gain (AV) for the channel length range studied due to the degradation of the Early voltage (VEA). Furthermore, for the other wafers no significant AV variation betweem the wafers was observed. It suggests that neither the HfO2 thickness nor the plasma power presented a relevant influence on the AVvalue. 

Considering that the AV for all studied wafers, except D20, present the same trend at room temperature (figure 2), wafer D18 was chosen to investigate the analog basic parameter performances from 25 to 150 °C. In figure 3 is can be seen that the transconductance (gm) is strongly degraded as the temperature increases due to mobility degradation. On the other hand, the output conductance (gD) presented almost no difference with the temperature rise. Figure 4 focuses on the AV as a function of temperature. It can be seen that AVdecreases 5 dB as the temperature increases from 25 to 150 °C, due to the influence of the gm reduction.

[1] J.-H. Han et al., Microelectronic Engineering, v.109, p. 266–269, 2013.

[2] V.P.-H Hu et al.,TED, v.60, I. 10, p. 3596 – 3600, October, 2013.

[3] S. Takagi et al., Microelectronic Engineering, v.109, p. 389–395, 2013.

Figure 1