bluuebunny/crossref_metadata_2025 huggingface dataset:
Information flow inference for ML
Authors: Pottier François , Simonet Vincent
Published: November 2005

This paper presents a type-based information flow analysis for a call-by-value λ-calculus equipped with references, exceptions and let-polymorphism, which we refer to as Core ML. The type system is constraint-based and has decidable type inference. Its non-interference proof is reasonably lightweight, thanks to the use of a number of orthogonal techniques. First, a syntactic segregation between
values
and
expressions
allows a lighter formulation of the type system. Second, non-interference is reduced to
subject reduction
for a non-standard language extension. Lastly, a
semi-syntactic
approach to type soundness allows dealing with constraint-based polymorphism separately.
Fractional rate dataflow model and efficient code synthesis for multimedia applications
Authors: Oh Hyunok , Ha Soonhoi
Published: November 2005

Automatic code synthesis from dataflow program graphs is a promising high-level design methodology for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has been an active research subject to reduce the gap in terms of memory requirements between the synthesized code and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia applications.
Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation
Authors: Mohanty S. , Prasanna V. K. , Neema S. , Davis J.
Published: November 2005

In addition to integrating different Intellectual Property cores, heterogeneous embedded systems provide several architecture knobs such as voltage, operating frequency, configuration, etc. that can be varied to optimize performance. Such flexibilities results in a large design space making system optimization a very challenging task. Moreover, such systems operate in mobile and other power constrained environments. Therefore, in addition to rapid exploration of a large design space a designer has to optimize both time and energy performance. To address these issues, we propose a hierarchical design space exploration methodology. Our methodology initially uses symbolic constraint satisfaction to rapidly prune the design space. This pruning process is followed by a system wide performance estimation to further reduce the number of candidate designs. Finally, detailed simulation using low-level simulators are performed to select an appropriate design. Our methodology is implemented by integrating two tools, DESERT and HiPerE, into the
M
model based
I
ntegrated simu
LA
tio
N
(MILAN) framework. DESERT uses Ordered Binary Decision Diagrams based symbolic search to rapidly explore a large design space and identifies candidate designs that meet the user specified performance constraints. HiPerE provides rapid estimation of system wide energy and latency based on component level simulations and also facilitates energy optimization. MILAN provides the required modeling support for these tools and also facilitates component specific multi-granular simulations through seamless integration of various simulators.
Footprint and feature management using aspect-oriented programming techniques
Authors: Hunleth Frank , Cytron Ron K.
Published: November 2005

Applications accrue features in response to the needs of
all
users, yet the associated code bloating and performance loss often render an application unsuitable for some users, particularly those interested in using the application in an embedded system. As a result, developers are often faced with either reinventing pieces of an application, custom tailored to their needs, or they are faced with the daunting task of refactoring an existing application to obtain an appropriate subset of that application's functionality. In either case, subsequent development, maintenance and testing of the application becomes more complex, due to the effects of future revisions on all of the derived subsets.In this paper, we report on our experience in obtaining subsets of an application's functionality, using a relatively new programming-language paradigm and tool to achieve the subsets compositionally. Instead of refactoring a large, feature-rich application, a feature can be added by including that feature's
aspect
in the set provided to an aspect compiler. In particular, a minimal, base implementation was developed in Java and features were added by supplying the appropriate advice to an AspectJ compiler. We describe our approach and present footprint and performance results for automatically derived subsets of an
event channel
.
Standardization approach of ITRON debugging interface specification and evaluation of its adaptability
Authors: Wakabayashi Takayuki , Takada Hiroaki
Published: November 2005

Debugging environments for embedded systems unavoidably depend on the internal structure of the operating system (OS) in order to implement OS support functions. Since the ITRON specification standardizes only the API, the internal structure of operating systems conforming to the ITRON Specification are different, resulting in difficulties in supporting ITRON-Specification operating systems for debugging environments. To solve this problem, we design the ITRON Debugging Interface Specification which is defined as a standard interface for debugging environments supporting ITRON-Specification operating systems. In designing the ITRON debugging interface, we adopt the approach where a module hiding the difference of the internal structure of OS is embedded to the host side. With this method, we are able to achieve the adaptability to a variety of target systems. This paper describes the standardization approach adopted to the ITRON debugging interface. This paper also evaluates the approach's adaptability.
On systematic design of globally consistent executable assertions in embedded software
Authors: Jhumka Arshad , Hiller Martin , Claesson Vilgot , Suri Neeraj
Published: November 2005

Over the design of software (SW) used in provisioning of dependable services, Executable Assertions (EAs) are seeing increasing usage in aiding detection of data errors. Given the requirements for provision of service despite faults, early detection of system states that can potentially lead to system failure is valuable. We address the issue of ascertaining whether
localized
EAs in individual modules add up complementarily to implement a
global
EA/property. We first show that detection of globally compliant EAs is NP-complete. Thus, we develop a two-pass approach for our objective. In the first pass, we introduce the
consistency
property of EAs and use it to ascertain global conformity across all EAs. The second pass, analogous to predicate transformers, generates globally consistent EAs when any inconsistency is flagged in the first pass. We show the applicability of our approach on a real embedded system. Initial results obtained show that our framework is able to detect inherent vulnerabilities (due to placement of mismatched EAs) that were previously undetected. Our intent is automation of this approach, which can be incorporated in a compiler.
DSPs
Authors: Fettweis Gerhard
Published: November 2005

DSPs today are still programmed mainly in assembly code - which somehow seems like a "stone age" approach for the compiler dominated microprocessor world. Now that compilers are moving into the DSP world, does this mean that we see the long-awaited merger of DSPs & micros? Or will DSPs disappear? To understand this we must have a look at

what are DSPs good at, and what not

is there future potential in DSP architecture development

how could future DSPs look like

how do these DSPs address compiler issues, and vice versa

.DSPs have a distinct reason for their existence and will not go away in foreseeable future. Why? This is exactly what the talk is about.
Energy aware compilation for DSPs with SIMD instructions
Authors: Lorenz Markus , Wehmeyer Lars , Dräger Thorsten
Published: November 2005

The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. In this paper we present compiler optimizations with the aim of minimizing energy consumption of embedded applications: This comprises loop optimizations for exploitation of SIMD instructions and zero overhead hardware loops in order to increase performance and decrease the energy consumption. In addition, we use a phase coupled code generator based on a genetic algorithm (GCG) which is capable of performing energy aware instruction selection and scheduling. Energy aware compilation is done with respect to an instruction level energy cost model which is integrated into our code generator and simulator. Experimental results for several benchmarks show the effectiveness of our approach.
Compiling with code-size constraints
Authors: Naik Mayur , Palsberg Jens
Published: November 2005

Most compilers ignore the problems of limited code space in embedded systems. Designers of embedded software often have no better alternative than to manually reduce the size of the source code or even the compiled code. Besides being tedious and error-prone, such optimization results in obfuscated code which is difficult to maintain and reuse. In this paper, we present a code-size-directed compiler. We phrase register allocation and code generation as an integer linear programming problem where the upper bound on the code size can simply be expressed as an additional constraint. Our experiments show that our compiler, when applied to two commercial microcontroller programs, generates code as compact as carefully crafted code.
Register allocation for irregular architectures
Authors: Scholz Bernhard , Eckstein Erik
Published: November 2005

For irregular architectures global register allocation is still a challenging problem that has not been successfully solved so far. The graph-coloring analogy of traditional approaches does not match the needs of register allocation for such architectures which feature non-orthogonal instruction sets and small register files. This work proposes a fundamentally new approach to global register allocation for irregular architectures. Our approach formulates global allocation as a
partitioned boolean quadratic optimization problem
(PBQP) that allows generic modeling of processors peculiarities. Because PBQP is NP-complete we present a heuristic that exhibits a nearly linear run-time complexity.We integrated our register allocator with the Infineon Carmel C Compiler which is based on the Open Compiler Environment from Atair Software. A DSP benchmark suite was used to compare the performance of our register allocator with a graph-coloring approach and with an optimal allocation. The experiments show that our new approach performs better than a traditional graph coloring approach for irregular architectures.
Quick piping
Authors: Milner Christopher W. , Davidson Jack W.
Published: November 2005

Responding to marketplace needs, today's embedded processors must feature a flexible core that allows easy modification with fast time to market. In this environment, embedded processors are increasingly reliant on flexible support tools. This paper presents one such tool, called
Quick Piping
, a new, high-level formalism for modeling processor pipelines.
Quick Piping
consists of three primary components that together provide an easy-to-build, reusable processor description:

Pipeline graphs-a new high-level formalism for modeling processor pipelines,

pipe--
a companion domain-specific language for specifying a pipeline graph,

pipe miner--
a compiler specification generator for
pipe
descriptions.
pipe miner
processes a
pipe
description and produces a compiler specification that is used to build a compiler that reads the corresponding machine's instruction set and automatically generates resource vectors

.Despite their ubiquity and importance in achieving high performance in modern processors, pipelines--and improving the mechanisms for specifying their operation--have received little attention. Until now,
handwritten
resource vectors have served to specify information about a processor's pipeline and encode relevant information about each instruction's resource usage. Describing the complete set of resource vectors for a machine can be quite tedious and error prone, since it commonly must be developed by hand on an instruction-by-instruction basis.With its use of pipeline graphs, the pipe language, and the
pipe miner
compiler specification generator,
Quick Piping
gives the embedded processor architect and compiler writer an intuitive high-level abstraction of pipelines, a language for specifying a pipeline, and a tool for automatically producing pipeline resource vectors. The resulting specifications are quick to develop, easy to understand, simple to modify and maintain, and can be automatically processed to produce the low-level information required by processor control units and instruction schedulers.
Application specific compiler/architecture codesign
Authors: Wahlen Oliver , Glökler Tilman , Nohl Achim , Hoffmann Andreas , Leupers Rainer , Meyr Heinrich
Published: November 2005

This paper proposes an architecture exploration methodology for application specific instruction set processors (ASIPs) including a C compiler and a VHDL model in the exploration loop. For a given application the target architecture is an instance of the scalable ALICE VLIW architecture which will be presented in this paper. In a case study it will be explained how the LISA processor design platform in conjunction with the CoSy compiler environment significantly reduces the time for exploration cycles. Using a typical telecommunications application, the quality of the resulting architecture and its performance are compared to the ICORE2 processor - a manually designed ASIP for efficient processing of computation intensive kernels.
When to use a compilation service?
Authors: Palm Jeffrey , Lee Han , Diwan Amer , Moss J. Eliot B.
Published: November 2005

Modern handheld computers are certainly capable of running general purpose applications, such as Java virtual machines. However, short battery life rather than computational capability often limits the usefulness of handheld computers. This paper considers how to reduce the energy consumption of Java applications.Broadly speaking, there are three interleaved steps in running Java programs in a compiled environment: downloading the bytecodes, compiling and possibly optimizing the bytecodes, and running the compiled code. Optimized code typically runs faster than non-optimized code but the optimization process itself may consume significant energy. We consider the possibility of moving compilation (optimizing or non-optimizing) to a tethered server. We demonstrate that there is a significant benefit to moving compilation to a server (up to 67% reduction in energy for a realistic handheld configuration). We also demonstrate that there is no single best compilation strategy for all methods.
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Authors: Dudani Ajay , Mueller Frank , Zhu Yifan
Published: November 2005

Embedded systems have limited energy resources. Hence, they should conserve these resources to extend their period of operation. Recently, dynamic frequency scaling (DFS) and dynamic voltage scaling (DVS) have been added to a various embedded processors as a means to increase battery life. A number of scheduling techniques have been developed to exploit DFS and DVS for real-time systems to reduce energy consumption. These techniques exploit idle and slack time of a schedule. Idle time can be consumed by lowering the processor frequency of selected tasks while slack time allows later tasks to execute at lower frequencies with reduced voltage demands.Our work delivers energy savings beyond the level of prior work. We enhance the earliest-deadline first (EDF) scheduling to exploit slack time generated by the invocation of the task at multiple frequency levels
within the same invocation
. The technique relies strictly on operating system support within the scheduler to implement the approach. Early scaling at a low frequency, determined by a feedback mechanism and facilitated by a slack-passing scheme, capitalizes on high probabilities of a task to finish its execution without utilizing its worst-case execution budget. If a task does not complete at a certain point in time within its low frequency range, the remainder of it continues to execute at a higher frequency. Our experiments demonstrate that the resulting energy savings exceed those of previously published work by up to 33%. In addition, our method only adds a constant complexity at each scheduling point, which has not been achieved by prior work, to the best of our knowledge.
Pointer and escape analysis for multithreaded programs
Authors: Salcianu Alexandru , Rinard Martin
Published: November 2005

This paper presents a new combined pointer and escape analysis for multithreaded programs. The algorithm uses a new abstraction called
parallel interaction graphs
to analyze the interactions between threads and extract precise points-to, escape, and action ordering information for objects accessed by multiple threads. The analysis is compositional, analyzing each method or thread once to extract a parameterized analysis result that can be specialized for use in any context. It is also capable of analyzing programs that use the unstructured form of multithreading present in languages such as Java and standard threads packages such as POSIX threads.

We have implemented the analysis in the MIT Flex compiler for Java and used the extracted information to 1) verify that programs correctly use region-based allocation constructs, 2) eliminate dynamic checks associated with the use of regions, and 3) eliminate unnecessary synchronization. Our experimental results show that analyzing the interactions between threads significantly increases the effectiveness of the region analysis and region check elimination, but has little effect for synchronization elimination.
Dynamic adaptation to available resources for parallel computing in an autonomous network of workstations
Authors: Rencuzogullari Umit , Dwardadas Sandhya
Published: November 2005

Networks of workstations (NOWs), which are generally composed of autonomous compute elements networked together, are an attractive parallel computing platform since they offer high performance at low cost. The autonomous nature of the environment, however, often results in inefficient utilization due to load imbalances caused by three primary factors: 1) unequal load (compute or communication) assignment to equally-powerful compute nodes, 2) unequal resources at compute nodes, and 3) multiprogramming. These load imbalances result in idle waiting time on cooperating processes that need to synchronize or communicate data. Additional waiting time may result due to local scheduling decisions in a multiprogrammed environment. In this paper, we present a combined approach of compile-time analysis, run-time load distribution, and operating system scheduler cooperation for improved utilization of available resources in an autonomous NOW. The techniques we propose allow efficient resource utilization by taking into consideration all three causes of load imbalance in addition to locality of access in the process of load distribution. The resulting adaptive load distribution and cooperative scheduling system allows applications to take advantage of parallel resources when available by providing better performance than when the loaded resources are not used at all.
Statistical scalability analysis of communication operations in distributed applications
Authors: Vetter Jeffrey S. , McCracken Michael O.
Published: November 2005

Current trends in high performance computing suggest that users will soon have widespread access to clusters of multiprocessors with hundreds, if not thousands, of processors. This unprecedented degree of parallelism will undoubtedly expose scalability limitations in existing applications, where scalability is the ability of a parallel algorithm on a parallel architecture to effectively utilize an increasing number of processors. Users will need precise and automated techniques for detecting the cause of limited scalability. This paper addresses this dilemma. First, we argue that users face numerous challenges in understanding application scalability: managing substantial amounts of experiment data, extracting useful trends from this data, and reconciling performance information with their applications design. Second, we propose a solution to automate this data analysis problem by applying fundamental statistical techniques to scalability experiment data. Finally, we evaluate our operational prototype on several applications, and show that statistical techniques offer an effective strategy for assessing application scalability. In particular, we find that non-parametric correlation of the number of tasks to the ratio of the time for communication operations to overall communication time provides a reliable measure for identifying communication operations that scale poorly.
Weaving aspects in a persistent environment
Authors: Rashid Awais
Published: November 2005

This paper discusses two mechanisms for weaving aspects in persistent environments founded on object-oriented databases. The first mechanism is based on exploiting existing aspect languages and their associated weavers while the second mechanism is based on building weaving functionality into the database management system (DBMS). The first mechanism has been used to integrate AspectJ and its associated weaver with the Jasmine ODBMS. The second approach has been used to implement a weaver within the SADES object database evolution system.
A scripting language to help the blind to program visually
Authors: Siegfried Robert M.
Published: November 2005

Computer programming, a career path that has been accessible to the blind, has changed in recent years as more systems use graphical user interfaces. These changes make it more difficult for the blind to work productively as programmers. Visual Basic, a RAD programming language that stores forms in text format, requires a great deal of information to be specified. A scripting language is introduced which simplifies the task and allows blind programmers to specify forms in a much simpler fashion. An example and a formal grammar are included.
Yet another meta-language for programming language processing
Authors: Chen Haiming , Dong Yunmei
Published: November 2005

The formal specification language LFC was designed to support formal specification acquisition. However, it is yet suited to be used as a meta-language for specifying programming language processing. This paper introduces LFC as a meta-language, and compares it with ASF+SDF, an algebraic specification formalism that can also be used to programming languages.
The role of opaque types to build abstractions
Authors: Corradi A. , Leonardi L.
Published: November 2005

This note examines the MODULA-2 approach to build data abstractions and abstract data types. MODULA-2 provides a byreference semantics by providing opaque types via pointers. The paper compares this mechanism with the one furnished by ADA (*). A comparison with object-oriented systems brings out the issue of assignment, copy and compare operations. That leads to a constructive methodology for abstract data types in MODULA-2. Any abstraction must furnish copy operations with two different semantics, respectively shallow and deep, and related equality and inequality operations.
Improvements of an incremental evaluation algorithm for ordered attribute grammars
Authors: Yeh D. , Kastens U.
Published: November 2005

Three improvements are suggested upon an incremental attribute evaluation algorithm proposed by the first author. The resulting algorithm allows multiple subtree replacement and cancels three auxiliary tables required by the previous version.
Time space tradeoffs in vector algorithms for APL functions
Authors: Budd T.
Published: November 2005

When considering algorithms which will run on processors in which large vectors of values can be manipulated in time which is independent of the length of the vector, many issues of time versus space arise which are not important, or of less importance, on more conventional machines. This paper explores various alternative techniques which might be used in an implementation of APL on such a machine, and considers some of these time/space tradeoffs.
Bootstrapping one-sided flexible arrays
Authors: Hinze Ralf
Published: November 2005

The abstract data type
one-sided flexible array
, also called random-access list, supports look-up and update of elements and can grow and shrink at one end. We describe a purely functional implementation based on weight-balanced multiway trees that is both simple and versatile. A novel feature of the representation is that the running time of the operations can be tailored to one's needs---even dynamically at array-creation time. In particular, one can trade the running time of look-up operations for the running time of update operations. For instance, if the multiway trees have a fixed degree, the operations take θ(log
n
) time, where
n
is the size of the flexible array. If the degree doubles levelwise, look-up speeds up to θ(sqrtlog
n
) while update slows down to θ(2

sqrt log
n

). We show that different tree shapes can be conveniently modelled after mixed-radix number systems.
A theory of overloading
Authors: Stuckey Peter J. , Sulzmann Martin
Published: November 2005

We present a minimal extension of the Hindley/Milner system to allow for overloading of identifiers. Our approach relies on a combination of the HM(X) type system framework with Constraint Handling Rules (CHRs). CHRs are a declarative language for writing incremental constraint solvers. CHRs allow us to precisely describe the relationships among overloaded identifiers. Under some sufficient conditions on the CHRs we achieve decidable type inference and the semantic meaning of programs is unambiguous. Our approach allows us to combine open and closed world overloading. We also show how to deal with overlapping definitions.
Type classes with more higher-order polymorphism
Authors: Neubauer Matthias , Thiemann Peter
Published: November 2005

We propose an extension of Haskell's type class system with lambda abstractions in the type language. Type inference for our extension relies on a novel constrained unification procedure called guided higher-order unification. This unification procedure is more general than Haskell's kind-preserving unification but less powerful than full higher-order unification.The main technical result is the soundness and completeness of the unification rules for the fragment of lambda calculus that we admit on the type level.
A compiled implementation of strong reduction
Authors: Grégoire Benjamin , Leroy Xavier
Published: November 2005

Motivated by applications to proof assistants based on dependent types, we develop and prove correct a strong reducer and ß-equivalence checker for the λ-calculus with products, sums, and guarded fixpoints. Our approach is based on compilation to the bytecode of an abstract machine performing weak reductions on non-closed terms, derived with minimal modifications from the ZAM machine used in the Objective Caml bytecode interpreter, and complemented by a recursive "read back" procedure. An implementation in the Coq proof assistant demonstrates important speed-ups compared with the original interpreter-based implementation of strong reduction in Coq.
Reconsidering custom memory allocation
Authors: Berger Emery D. , Zorn Benjamin G. , McKinley Kathryn S.
Published: November 2005

Programmers hoping to achieve performance improvements often use custom memory allocators. This in-depth study examines eight applications that use custom allocators. Surprisingly, for six of these applications, a state-of-the-art general-purpose allocator (the Lea allocator) performs as well as or better than the custom allocators. The two exceptions use regions, which deliver higher performance (improvements of up to 44%). Regions also reduce programmer burden and eliminate a source of memory leaks. However, we show that the inability of programmers to free individual objects within regions can lead to a substantial increase in memory consumption. Worse, this limitation precludes the use of regions for common programming idioms, reducing their usefulness.We present a generalization of general-purpose and region-based allocators that we call
reaps
. Reaps are a combination of regions and heaps, providing a full range of region semantics with the addition of individual object deletion. We show that our implementation of reaps provides high performance, outperforming other allocators with region-like semantics. We then use a case study to demonstrate the space advantages and software engineering benefits of reaps in practice. Our results indicate that programmers needing fast regions should use reaps, and that most programmers considering custom allocators should instead use the Lea allocator.
Multiple instances and symbolic variables in executable sequence charts
Authors: Marelly Rami , Harel David , Kugler Hillel
Published: November 2005

We extend live sequence charts (LSCs), a highly expressive variant of sequence diagrams, and provide the extension with an executable semantics. The extension involves support for instances that can bind to multiple objects and symbolic variables that can bind to arbitrary values. The result is a powerful executable language for expressing behavioral requirements on the level of inter-object interaction. The extension is implemented in full in our
play-engine
tool, with which one can execute the requirements directly without the need to build or synthesize an intra-object system model. It seems that in addition to many advantages in testing and requirements engineering, for some kinds of systems this could lead to the requirements actually serving as the final implementation.
Implementing distribution and persistence aspects with aspectJ
Authors: Soares Sergio , Laureano Eduardo , Borba Paulo
Published: November 2005

This paper reports our experience using AspectJ, a general-purpose aspect-oriented extension to Java, to implement distribution and persistence aspects in a web-based information system. This system was originally implemented in Java and restructured with AspectJ. Our main contribution is to show that AspectJ is useful for implementing several persistence and distribution concerns in the application considered, and other similar applications. We have also identified a few drawbacks in the language and suggest some minor modifications that could significantly improve similar implementations. Despite the drawbacks, we argue that the AspectJ implementation is superior to the pure Java implementation. Some of the aspects implemented in our experiment are abstract and constitute a simple aspect framework. The other aspects are application specific but we suggest that different implementations might follow the same aspect pattern. The framework and the pattern allow us to propose architecture-specific guidelines that provide practical advice for both restructuring and implementing certain kinds of persistent and distributed applications with AspectJ.
Performance and scalability of EJB applications
Authors: Cecchet Emmanuel , Marguerite Julie , Zwaenepoel Willy
Published: November 2005

We investigate the combined effect of application implementation method, container design, and efficiency of communication layers on the performance scalability of J2EE application servers by detailed measurement and profiling of an auction site server.We have implemented five versions of the auction site. The first version uses stateless session beans, making only minimal use of the services provided by the Enterprise JavaBeans (EJB) container. Two versions use entity beans, one with container-managed persistence and the other with bean-managed persistence. The fourth version applies the session fasade pattern, using session beans as a fasade to access entity beans. The last version uses EJB 2.0 local interfaces with the session fasade pattern. We evaluate these different implementations on two popular open-source EJB containers with orthogonal designs. JBoss uses dynamic proxies to generate the container classes at run time, making an extensive use of reflection. JOnAS pre-compiles classes during deployment, minimizing the use of reflection at run time. We also evaluate the communication optimizations provided by each of these EJB containers.The most important factor in determining performance is the application implementation method. EJB applications with session beans perform as well as a Java servlets-only implementation and an order-of-magnitude better than most of the implementations based on entity beans. The fine-granularity access exposed by the entity beans limits scalability. Use of session fasade beans improves performance for entity beans, but
only
if local communication is very efficient or EJB 2.0 local interfaces are used. Otherwise, session fasade beans degrade performance.For the implementation using session beans, communication cost forms the major component of the execution time on the EJB server. The design of the container has little effect on performance. With entity beans, the design of the container becomes important. In particular, the cost of reflection affects performance. For implementations using session fasade beans, local communication cost is critically important. EJB 2.0 local interfaces improve the performance by avoiding the communication layers for local communications.
TACO
Authors: Nolte Jörg , Ishikawa Yutaka , Sato Mitsuhisa
Published: November 2005

Taco(Topologies and Collections) is a template based object platform for cluster architectures, that provides the flavour of distributed data-parallel programming based on distributed object groups. This paper introducesTaco's basic concepts and discusses template based programming techniques to control the behaviour of (collective) method invocations. In particular, the problem of polymorphism and concurrency control in the context of distributed, parallel computing is addressed.
Naked objects
Authors: Pawson Richard , Matthews Robert
Published: November 2005

Naked objects is an approach to systems design in which core business objects show directly through to the user interface, and in which all interaction consists of invoking methods on those objects in the noun-verb style. One advantage of this approach is that it results in systems that are more expressive from the viewpoint of the user: they treat the user like a problem solver, not as merely a process-follower. Another advantage is that the 1:1 mapping between the user's representation and the underlying model means that it is possible to auto-generate the former from the latter, which yields benefits to the development process. The authors have designed a Java-based, open source toolkit called Naked Objects which facilitates this style of development. This paper describes the design and operation of the toolkit and its application to the prototyping of a core business system. Some initial feedback from the project is provided, together with a list of future research directions both for the toolkit and for a methodology to apply the naked objects approach.
AspectCOOL
Authors: Avdičauševič Enis , Lenič Mitja , Mernik Marjan , Zumer Viljem
Published: November 2005

Aspect-oriented programming (AOP) is a promising technique helping programmers to easily reason about, develop and maintain programs. AOP improves reusability since components with a clearly defined functionality, which is not tangled with different aspects, are much easier to reuse. In order to explore different AOP concepts a general-purpose aspect-oriented language AspectCOOL has been designed and implemented. Among the different concepts, which we explored, the most important is the separate compilation of aspect and component code. Using this concept aspects can be applied on already compiled components, which improves their reusability.
Embedding built-in tests in hot spots of an object-oriented framework
Authors: Jeon Taewoong , Seung Hyon Woo , Lee Sungyoung
Published: November 2005

This paper describes a scheme of encapsulating test support code as built-in test (BIT) components and embedding them into the hot spots of an object-oriented framework so that defects caused by the modification and extension of the framework can be detected effectively and efficiently through testing. The test components embedded into a framework in this way increase the testability of the framework by making it easy to control and observe the process of framework testing. The proposed technique is illustrated using the facilities of C++. Our testing scheme, however, is equally applicable to other object-oriented languages. Using our scheme, test components can be designed and embedded into the hot spots of a framework without incurring changes or intervention to the framework code, and also can be attached and detached dynamically to/from the framework as needed at run-time.
Implementing a real computational-environment jump in order to develop a runtime-adaptable reflective platform
Authors: Ortín Francisco , Cueva Juan Manuel
Published: November 2005

Different techniques are emerging in order to build adaptable computing systems and software engineering methods. Two examples in the software engineering field are aspect-oriented programming and multi-dimensional separation of concerns. They distinguish functional code from reusable crosscutting aspects, creating the final application by
weaving
the program and its specific aspects. They lack runtime adaptability, simply offering design-time adaptation.Dynamic adaptability is offered by MOP-based reflective systems. However, meta-object protocols (MOPs) restrict the amount of features an application may customize, and the way they can express this customization. Furthermore, this kind of systems uses a fixed programming language.What we present in this paper is a non-restrictive reflective system that achieves a real computational jump, making every application and language feature adaptable at runtime-without any previous restriction. Moreover, the reflection mechanism is independent of the language selected by the programmer.
Speculative synchronization
Authors: Martínez José F. , Torrellas Josep
Published: November 2005

Barriers, locks, and flags are synchronizing operations widely used programmers and parallelizing compilers to produce race-free parallel programs. Often times, these operations are placed suboptimally, either because of conservative assumptions about the program, or merely for code simplicity.We propose
Speculative Synchronization,
which applies the philosophy behind Thread-Level Speculation (TLS) to explicitly parallel applications. Speculative threads execute past active barriers, busy locks, and unset flags instead of waiting. The proposed hardware checks for conflicting accesses and, if a violation is detected, offending speculative thread is rolled back to the synchronization point and restarted on the fly. TLS's principle of always keeping a
safe thread
is key to our proposal: in any speculative barrier, lock, or flag, the existence of one or more safe threads at all times guarantees forward progress, even in the presence of access conflicts or speculative buffer overflow. Our proposal requires simple hardware and no programming effort. Furthermore, it can coexist with conventional synchronization at run time.We use simulations to evaluate 5 compiler- and hand-parallelized applications. Our results show a reduction in the time lost to synchronization of 34% on average, and a reduction in overall program execution time of 7.4% on average.
Automatically characterizing large scale program behavior
Authors: Sherwood Timothy , Perelman Erez , Hamerly Greg , Calder Brad
Published: November 2005

Understanding program behavior is at the foundation of computer architecture and program optimization. Many programs have wildly different behavior on even the very largest of scales (over the complete execution of the program). This realization has ramifications for many architectural and compiler techniques, from thread scheduling, to feedback directed optimizations, to the way programs are simulated. However, in order to take advantage of time-varying behavior, we must first develop the analytical tools necessary to automatically and efficiently analyze program behavior over large sections of execution.Our goal is to develop automatic techniques that are capable of finding and exploiting theLarge Scale Behaviorof programs (behavior seen over billions of instructions). The first step towards this goal is the development of a hardware independent metric that can concisely summarize the behavior of an arbitrary section of execution in a program. To this end we examine the use ofBasic Block Vectors.We quantify the effectiveness of Basic Block Vectors in capturing program behavior across several different architectural metrics, explore the large scale behavior of several programs, and develop a set of algorithms based on clustering capable of analyzing this behavior. We then demonstrate an application of this technology to automatically determine where to simulate for a program to help guide computer architecture research.
Energy-efficient computing for wildlife tracking
Authors: Juang Philo , Oki Hidekazu , Wang Yong , Martonosi Margaret , Peh Li Shiuan , Rubenstein Daniel
Published: November 2005

Over the past decade, mobile computing and wireless communication have become increasingly important drivers of many new computing applications. The field of wireless sensor networks particularly focuses on applications involving autonomous use of compute, sensing, and wireless communication devices for both scientific and commercial purposes. This paper examines the research decisions and design tradeoffs that arise when applying wireless peer-to-peer networking techniques in a mobile sensor network designed to support wildlife tracking for biology research.The ZebraNet system includes custom tracking collars (nodes) carried by animals under study across a large, wild area; the collars operate as a peer-to-peer network to deliver logged data back to researchers. The collars include global positioning system (GPS), Flash memory, wireless transceivers, and a small CPU; essentially each node is a small, wireless computing device. Since there is no cellular service or broadcast communication covering the region where animals are studied, ad hoc, peer-to-peer routing is needed. Although numerous ad hoc protocols exist, additional challenges arise because the researchers themselves are mobile and thus there is no fixed base station towards which to aim data. Overall, our goal is to use the least energy, storage, and other resources necessary to maintain a reliable system with a very high `data homing' success rate. We plan to deploy a 30-node ZebraNet system at the Mpala Research Centre in central Kenya. More broadly, we believe that the domain-centric protocols and energy tradeoffs presented here for ZebraNet will have general applicability in other wireless and sensor applications.
Dynamic dead-instruction detection and elimination
Authors: Butts J. Adam , Sohi Guri
Published: November 2005

We observe a non-negligible fraction--3 to 16% in our benchmarks--of
dynamically dead instructions,
dynamic instruction instances that generate unused results. The majority of these instructions arise from static instructions that also produce useful results. We find that compiler optimization (specifically instruction scheduling) creates a significant portion of these
partially dead
static instructions. We show that most of the dynamically instructions arise from a small set of static instructions that produce dead values most of the time.We leverage this locality by proposing a dead instruction predictor and presenting a scheme to avoid the execution of predicted-dead instructions. Our predictor achieves an accuracy of 93% while identifying over 91% of the dead instructions using less than 5 KB of state. We achieve such high accuracies by leveraging future control flow information (i.e., branch predictions) to distinguish between useless and useful instances of the same static instruction.We then present a mechanism to avoid the register allocation, instruction scheduling, and execution of predicted dead instructions. We measure reductions in resource utilization averaging over 5% and sometimes exceeding 10%, covering physical register management (allocation and freeing), register file read and write traffic, and data cache accesses. Performance improves by an average of 3.6% on an architecture exhibiting resource contention. Additionally, our scheme frees future compilers from the need to consider the costs of dead instructions, enabling more aggressive code motion and optimization. Simultaneously, it mitigates the need for good path profiling information in making inter-block code motion decisions.
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Authors: Kim Changkyu , Burger Doug , Keckler Stephen W.
Published: November 2005

Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the hit time of large on-chip caches a function of a line's physical location within the cache. Consequently, cache access times will become a continuum of latencies rather than a single discrete latency. This non-uniformity can be exploited to provide faster access to cache lines in the portions of the cache that reside closer to the processor. In this paper, we evaluate a series of cache designs that provides fast hits to multi-megabyte cache memories. We first propose physical designs for these Non-Uniform Cache Architectures (NUCAs). We extend these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache. We show that, for multi-megabyte level-two caches, an adaptive, dynamic NUCA design achieves 1.5 times the IPC of a Uniform Cache Architecture of any size, outperforms the best static NUCA scheme by 11%, outperforms the best three-level hierarchy--while using less silicon area--by 13%, and comes within 13% of an ideal minimal hit latency solution.