bluuebunny/crossref_metadata_2025 huggingface dataset:
GaN Film Grown on Si Substrate for Monolithic Optical MEMS
Authors: Hu F.-R. , Ochi K. , Choi B.-S. , Kanamori Y. , Hane K.
Published: April 2009

GaN is a new and powerful material for photonic devices such as light emitting and laser diodes. On the other hand, optical MEMS technology is attractive for miniaturizing several optical systems. We are studying GaN film grown on Si substrate for the optical MEMS application in order to fabricate monolithic structure. In this paper, the characteristics of GaN film grown on Si substrate by MBE are reported. The growth conditions of GaN layer on Si substrate are studied. The surface morphology of the grown GaN film is measured by electron microscopy and atomic force microscopy. Furthermore, a preliminary grating structure is fabricated for a MEMS application.
Thermal Radiative Properties of Photonic Crystals
Authors: Miyazaki Koji , Kihara Masahiro , Tsukamoto Hiroshi
Published: April 2009

We investigate the spectral directional reflectivity of photonic crystals assembled with 2μm silica particles. The propagation of electromagnetic wave can be controlled by photonic crystals. Therefore photonic crystals are anticipated for advanced control of thermal radiation beyond solid state properties. Samples are prepared by Catalysts & Chemicals Industries Co., Ltd. The close-packed photonic crystals are fabricated on a Si wafer by using self-assembly of the colloidal particles under the specific condition. We measure reflectivities of the samples by using a FT-IR (Fourier Transform – Infrared Spectroscopy). The spectral reflectivity is enhanced at specific wavenumber. The peaks of spectral reflectivity shift to larger wavenumber as a function of an increased incident angle. The angular dependency of reflectivity can be roughly explained by using the modified Bragg’s equation taking into account Snell’s law. We show that the reflectivity in IR range is well enhanced by using a photonic crystal.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
Adhesion Strength at High Temperatures Affected by Moisture for Die-Attach Materials of Integrated Circuit Packages
Authors: Tanaka Hiroyuki , Numata Takashi
Published: April 2009

This paper presents a method of finite element analysis for calculating moisture concentration in non-isothermal and non-steady states of moisture for integrated circuit packages composed of dissimilar moisture-permeable materials. The method can address non-Fickian behavior of materials in moisture diffusivity. Specimens were put on a hot plate after pre-conditioning in a moist environment. Distribution of moisture concentration in the specimen used in adhesion strength measurement was calculated in the temperature-change process. Comparatively large change in moisture concentration occurs in the neighborhood of the dissimilar material interface during that process, demonstrating that adhesion strength between die-attach material and printed circuit board at high temperatures might have greater moisture-sensitivity than at low temperatures.
Fabrication of the Tip of GaAs Microwave Probe by Wet Etching
Authors: Ju Yang , Sato Hiroyuki , Soyama Hitoshi
Published: April 2009

In order to develop a new structure microwave probe, the fabrication of micro tip on the GaAs wafer surface was studied. The effects of the shape, direction, and size of etching mask to the fabricated tip were discussed in details. By finding the most suitable etching conditions, a tip having 7 μm high, 1.4 aspect ratio, and 50 nm curvature radius was formed. The experimental result indicates that the tip having the similar capability to sense the surface topography of materials as that of commercial atom force microscope (AFM) probe.
Creep Properties and Microstructure of the Sn-Ag-Cu-Ni-Ge Lead-Free Solder Alloy
Authors: Hidaka Noboru , Nagano Megumi , Shimoda Masayoshi , Watanabe Hirohiko , Ono Masahiro
Published: April 2009

A new lead-free solder alloy, Sn-Ag-Cu base adding a small amount of Ni, Ge, has been developed to improve their mechanical properties and prevent oxidation in solder alloys. In this paper, creep properties of two lead-free solder alloys, Sn-3.5Ag-0.5Cu-0.07Ni-0.01Ge (abbr. Sn-3.5Ag-0.5Cu-Ni-Ge) solder and Sn-3.0Ag-0.5Cu solder, were investigated at three temperatures ranging from 313K-398K. It was found that the creep strength of the Sn-3.5Ag-0.5Cu-Ni-Ge solder is higher than that of the Sn-3.0Ag-0.5Cu solder. Especially in the low stress region at 398K, the creep rupture time of the Sn-3.5Ag0.5Cu-Ni-Ge solder is about three times as long as that of the Sn-3.0Ag-0.5Cu solder. The microstructure of these solder alloys show that the addition of Ni was found to refine the effective grain size and provide a fine and uniform distribution of Ag3Sn in the solidified microstructure. The microstructure of the Sn-3.5Ag-0.5Cu-Ni-Ge solder is more stable than that of the Sn-3.0Ag-0.5Cu solder alloy after aging treatment at 398K, 1000 h. TEM observation was also performed, showing that precipitations of (Cu, Ni)6 Sn5, the diameter of which are about 0.5 μm, are distributed in the Ag3Sn/β-Sn phase eutectic area of the Sn-3.5Ag-0.5Cu-Ni-Ge solder after creep test at 398K, 5MPa. It is thought that the precipitations of (Cu, Ni)6 Sn5 contribute to creep strength in the Sn-3.5Ag-0.5Cu-Ni-Ge solder alloy.
Predicting Technique of Delamination at Adhesively Bonding Joints in a Flip Chip Package During Solder Reflow Process
Authors: Ikeda Toru , Kim Won-Keun , Miyazaki Noriyuki
Published: April 2009

Recently, adhesively bonding techniques such as the anisotropic conductive film (ACF) or the non-conductive adhesive resin are often used for connections in the chip size packages instead of conventional solder joints due to their reasonable cost and the ease of miniaturization. Adhesively bonding techniques expected to be a key technology for the chip size packaging and the system in package. However, the level of reliability for adhesively bonding techniques is still less than that for solder joints. The quantitative evaluation techniques for the reliability of adhesively bonding techniques are desired. This paper focused on the reliability of adhesively bonding joints in a flip chip package during the solder reflow process for other solder jointed devices. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. The delamination toughnesses between components in a flip chip based on the stress intensity factors were measured by fracture tests in conjunction with the numerical analysis developed in our previous study. Moisture concentration after moisture absorption was expected by the diffusion analysis using the finite element method. Then, vapor pressure in a flip chip during the solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. The delaminations in an actual flip chip package during moisture/reflow sensitivity tests have successfully predicted by the present methodology.
Micro-Via Reliability Study of High-Density Substrate
Authors: Wu Youhong
Published: April 2009

The micro-via dimension of substrate decreased rapidly as the I/O density of substrate dramatically increased to meet the high market needs. However, the strength of micro-via becomes weak, and will be easily broken during the manufacturing process or reliability test. The purpose of this study is to understand the key effective factors of the micro-via reliability with the 3D non-linear thermal stress analysis using the Multi-scaling modeling (submodeling) technique.
Circuit-Thermal Collaboration Design Method for Outline Design Stage of Mobile Terminal
Authors: Iwata Yoshiharu , Hayashi Shintaro , Satoh Ryohei , Fujimoto Kozo
Published: April 2009

The device layout design on the circuit board has a common method of performing a thermal design after the circuit design that is the main performance. But, there is no remaining budget of thermal design of the high performance mobile terminal. Then, a large feedback loop of the design from thermal detail design to outline design is occurred on high performance mobile terminal design. For this purpose, we build upon the high-speed module-based thermal analysis. But the design time is very long with using the general optimization method, i.e., GA, SA. Then, we need more high-speed design method. For this purpose, we have proposed the modularized high-speed layered thermal design method based on the boundary conditions between modules. In this report, we constructed the high-speed circuit-thermal collaboration design method at the outline design stage. This design method is collaborated at decision of boundary conditions between both circuit-thermal design methods. Furthermore, this design method, which computes the Pareto solutions set by changing the weight of each design performance index, was constructed. Moreover, we performed a layout design of a board with four devices mounted on top of the circuit board as a case study. The collaboration design solution between thermal layout design (total temperature rise of device =>min.) and circuit layout design (total circuit line length => min.) was computed in about 250sec, and the Pareto solutions set were computed in about 5000sec.
Evaluation of Damage Process Near Interfaces During Nanoscratch Test
Authors: Shibutani Tadahiro , Yu Qiang , Shiratori Masaki , Akai Takeshi
Published: April 2009

In multi-layered films on a silicon substrate for an advanced electronics devices, interfacial fracture often takes place and its strength (thin film adhesion) is very important in reliability. This study aims that the mechanism of damage initiation during nanoscratch test is examined for Si3N4/Cu/TaN films on a silicon substrate. In the case that the interfacial strength is weak, the interfacial damage initiates before surface film failure. In the case of edge-forward scratching, there are little effects of the rates of normal stress and scratching on the critical load. Contact analysis without friction for the system consisting of the tip, films and substrate reveals that the peak of shear stress appears on the track near the tip. Face-forward scratching shows the same behavior of damage as edge-forward scratching. Stress states acting on the interface in scratch tests suggest that the damage initiates when shear stress reaches the critical value.
Prediction of Equilibrium and Stability of Molten Solder Geometries by Finite Element Analysis
Authors: Nagata Takahiro , Kobayashi Takaya
Published: April 2009

Improving the reliability on solder joints is one of the major tasks to achieve downsizing of electronics products. Taking the molten solder profile as an object of study, a new procedure to model solder liquid with a structural FEM has been developed, which enables us to solve an issue of predefining the geometrical profile of solder liquid drops in a state of static equilibrium taking the surface tension into account, and also a problem concerning dynamic stability of the liquid drops. Molten solder liquid is treated as viscous fluid. Deformation of the material due to its viscosity can be represented by the structural analysis using rheological approach. Two types of the constitutive laws, creep model or viscoelasticity model, can be applied. Such a simple case as the Newtonian fluid, either constitutive law may be employed. Using these types of the constitutive laws in the analysis with time incremental steps, it becomes possible not only to obtain the stabilized shape of liquid drops, but also to analyze problems involved with transient (including dynamic effect) stability. As the size of a liquid drop is microscopic in a range of 100 to 1000 μm, the effect of the surface tension must become so predominant in the loading conditions. In most of the conventional theoretical researches, it is found that the surface tension is treated as the pressure difference varying according to the surface curvature. However, this method is not only so complicated, but also may lead to numerical instability particularly in the transient analysis subjected to large deformations. In this study, an effective method has been developed in which the surface tension can be represented with good accuracy through simplified input data with allocating the shell element generating a constant membrane force over the surface of a liquid drop.
Low Cycle Fatigue Properties of Solder Alloys Evaluated by Micro Bulk Specimen
Authors: Kariya Yoshiharu , Niimi Tomokazu , Suga Tadatomo , Otsuka Masahisa
Published: April 2009

Micro-bulk fatigue testing was developed to investigate the fatigue lives and damage mechanisms of Sn-3.0Ag-0.5Cu and Sn-37Pb solder alloys. The fatigue lives of micro-bulk solder obeyed Manson-Coffin’s empirical law, and the fatigue ductility exponents were about 0.55 for both Sn-Ag-Cu and Sn-Pb alloys. The fatigue life of Sn-3.0Ag-0.5Cu alloy was 10 times longer than that of Sn-37Pb alloy under symmetrical wave profile, although fatigue resistance of Sn-3.0Ag-0.5Cu alloy was not so superior under asymmetrical wave condition. The fatigue crack was developed from extrusion and intrusion of slip band in Sn-3.0Ag-0.5Cu alloy, while the crack was observed at colony boundary in Sn-37Pb alloy. The difference in damage mechanism may affect the sensitivity of fatigue life to reversibility of loading profile.
Effects of Interfacial Microstructure on Strength of Solder Joint Using Sn-Ag-Bi-In Solder
Authors: Hirose Akio , Hojo Takashi , Sogo Yosuke , Miwa Ryoko , Kobayashi Kojiro F. , Yamaguchi Atsushi , Furusawa Akio , Nishida Kazuto
Published: April 2009

In the present research a BGA (Ball Grid Array) type Sn-3Ag-0.5Cu solder ball was reflowed on Cu/Ni/Au pad using a Sn-3.5Ag-0.5Bi-8In solder or a Sn-8Zn-3Bi solder with varying reflow peak temperature and the interfacial microstructure and joint strength were evaluated. The strength of the Sn-3.5Ag-0.5Bi-8In solder joints reached the maximum value at reflow peak temperature of 483K to 493K and then decreased with increasing reflow temperature, whereas the Sn-8Zn-3Bi solder joints had high strength at the higher reflow peak temperature of 503K. In the Sn-3.5Ag-0.5Bi-8In solder joints, at a reflow peak temperature of 493K or less, a thin Ni-Sn type intermetallic layer formed at the interface between the solder and the pad. However at the higher reflow peak temperatures a clumpy (Cu, Ni)6Sn5 phase locally formed on the Ni-Sn interfacial reaction layer. This is caused by Cu from melted Sn-Ag-Cu ball reacting to Ni and Sn in the interfacial region. The (Cu, Ni)6Sn5 clumps increased with reflow peak temperature. Some void-like defects existed at the interface between the Ni-Sn layer and (Cu, Ni)6Sn5 clumps. These defects can act as crack initiation sites and thereby cause the degradation of the joint strength. It is concluded from the results that when the Sn-3.5Ag-0.5Bi-8In solder is applied to reflow soldering of the packages having Sn-Ag-Cu solder bump on the Cu/Ni/Au pad, the reflow peak temperature should be controlled ranging from 483K to 493K. When the reflow peak temperature was over 493K, a holding of 20s at the peak temperature, which resulted in diminish the void-like defects at the interface between the Ni-Sn layer and the (Cu, Ni)6Sn5 clumps, improved the joint strength.
Stress Concentration and Surface Roughness Effect on Strength of Polycrystalline Silicon Structure
Authors: Hamada Shigeru , Tani Shuichi , Katagiri Daisuke , Tsugai Masahiro , Horikawa Makio , Otani Hiroshi
Published: April 2009

In order to clarify the stress concentration and surface roughness effect on strength of the polycrystalline silicon (poly-Si) structure, bending tests of poly-Si microcantilever beam specimen and surface roughness measurement is performed. The bending test results are analyzed by means of maximum stress at the notch root calculated by FEM models, and it is found that this approach cannot describe the test results. Therefore, modified approach is taken into account by use of two parameters that are the maximum stress and area where stress is larger than 50% of the maximum stress, which indicates stress extension around the position of maximum stress representatively. By this two parameters approach, the test results are explained quantitatively and a strength design chart for stress concentration area of the poly-Si structure is obtained. On the other hand, relationship between strength and surface roughness are confirmed and useful information for the process quality control are obtained.
Reliability Improvement of Solder Joints Between Ceramic Chip Resistors and Insulated Metal Substrates With Thick Copper Pads
Authors: Monden Kenji
Published: April 2009

An insulated metal substrate (IMS) is a circuit board comprised of an insulating layer on a metal base plate. The insulating layer is made from epoxy resin incorporating dense inorganic fillers with high thermal conductivity. Because the substrates have high thermal conductivity, they have been used in electrical products that generate intense heat, such as inverters, amplifiers, motor drivers and so on. For using a high power semiconductor, thick copper pads are used on IMSs. In many times, aluminum plates are used for metal base plates in IMSs. The substrates are repeated heating and cooling in ordinary usage. So cracks of solder joints between ceramic chip resistors and IMSs often occur because of coefficient of thermal expansion (CTE) mismatch between ceramic and aluminum. Moreover, SnAgCu solder used to replace eutectic Sn/Pb solder as the joint has become major trend from a viewpoint of earth environmental protection. Finite element analysis was used for development of a high reliable IMS to meet these demand for the IMSs. The accelerated temperature cycling test on IMS was simulated by finite element method. The influence of the CTE of metal base plate and the influence of the modulus of insulating layer were studied. The reliability of solder was predicted to increase with CTE reduction of metal base plate. The modulus of insulating layer must be reduced sharply for a high reliable IMS. However, the insulating layer is difficult to be realized by using the epoxy resin. So the effect by fixing the chip resistor on a IMS using resin was calculated. When the space between the bottom of a chip resistor and the copper pads were filled up with resin such as underfill resin in ball grid array (BGA) mounting, it was predicted that the stress of solder decreased. The effect was confirmed by experiment. Solder joint fracture life of accelerated temperature cycling test on IMS was improved more than three times longer by using the underfill resin.
Orthotropic Thermal Conductivity Effect on Cylindrical Pin Fin Heat Transfer
Authors: Bahadur Raj , Bar-Cohen Avram
Published: April 2009

There is growing interest in the use of polymer composites with enhanced thermal conductivity for high performance fin arrays and heat sinks. However, the thermal conductivity of these materials is relatively low compared to conventional fin metals, and strongly orthotropic. Therefore, the design and optimization of such polymer pin fins requires extension of the one dimensional classical fin analysis to include two-dimensional orthotropic heat conduction effects. An analytical equation for heat transfer from a cylindrical pin fin with orthotropic thermal conductivity is derived and validated using detailed finite-element results. The thermal performance of such fins was found to be dominated by the axial thermal conductivity, but to depart from the classical fin solution with increasing values of a radius- and radial conductivity-based Biot number. Using these relations, it is determined that fin orthotropy does not materially affect the behavior of typical air-cooled fins. Alternatively, for heat transfer coefficients achievable with water cooling and conductivity ratios below 0.1, the fin heat transfer rate can fall more than 25% below the “classical” heat transfer rates. Detailed orthotropic fin temperature distributions are used to explain this discrepancy. Simplified orthotropic pin fin heat transfer equations are derived and validated over a wide range of orthotropic conditions.
Effect of Continuous and Discontinuous Fabrication and Reflow Processes on PWB Warpage
Authors: Karajgikar Saket , Ahn Wonkee , Agonafer Dereje
Published: April 2009

PWB also known as Printed Circuit Board (PCB) provides the physical structure for mounting and holding the electronic components and electrically connecting it. They are foundation of virtually all of the electronic devices. Typically they are multilayer structures consisting of organic/composites (e.g. FR4) and circuit layers, laminated together. Such multi-layered structures exhibit ‘board warpage’ during manufacturing process. It is a result of residual thermo-mechanical stresses along with any asymmetries (if present) during the curing process. This effect further increases when the board undergoes thermal cycling during component mounting and reflow process. Effect of different parameters such as board size, board thickness, and pressure (at the time of developing) on PWB warpage is studied.
Mathematical Optimization of Electronic Enclosures
Authors: De Kock D. J. , Nagulapally M. , Visser J. A. , Nair R. , Nigen J.
Published: April 2009

The thermal design of electronic enclosures is becoming more important as the demand for smaller, lighter systems with better performance increases. The limiting factor on the lifetime of these systems is the maximum temperature of the electronic components. Nowadays in some systems, the thermal design is the limiting factor for performance increases. A simple yet effective design method that yields optimum designs is therefore required to design these systems. Traditionally, experimental methods were used in the design of electronic enclosures. More recently Computational Fluid Dynamics (CFD) has established itself as a viable alternative to reduce the number of experimentation required, resulting in a reduction in the time scales and cost of the design process. The CFD process is usually applied on a trial and error basis and relies heavily on the insight and experience of the designer to improve designs. Even an experienced designer will only be able to improve the design and does not necessarily guarantee optimum results. A more efficient design method is to combine a mathematical optimizer with CFD. In this study the mathematical optimization method, DYNAMIC-Q, is linked with the commercial CFD package, Icepak to optimize different electronic enclosures. The method is applied to the following design situations commonly found in electronics enclosures. The first case is that of the optimization outlet grille of a telecommunications rack to reduce the electromagnetic interference without exceeding a specified temperature in the rack. The second case involves the optimum placement of electronic components on a printed circuit board to minimize the maximum temperatures of the components. The third case deals with flow through an electronic enclosure cooled by fans placed on the wall of the enclosures. The geometrical arrangement of boards and components on the boards in these enclosures might result in unequal flow distribution between the boards. For this purpose air flow filters of varying free-area ratios are used to make the flow rates between the boards more uniform. The free-area ratios of three filters are determined in order to maximize the total flow rate through system with the added constraint that the flow rates through each of the three filters are within 5% of each other. The last case deals with flow through a simplified notebook where the CPU temperature is minimized by changing the position of two exhaust fans. The study shows that mathematical optimization is a powerful tool that can be combined with CFD to yield optimum designs.
Thermal Characterization of Pulse-Activated Microelectronic Devices by Thermoreflectance-Based Surface Temperature Scanning
Authors: Komarov Pavel L. , Burzo Mihai G. , Raad Peter E.
Published: April 2009

This work reports on a system that can determine the thermal behavior of an activated complex microelectronic device by measuring its surface temperature field with a thermoreflectance-based system. The article describes the features of the experimental setup, provides details of the calibration process used to map the changes in the measured surface reflectivity to absolute temperature values, and explains the data acquisition procedure used to measure the transient temperature over a given active region. The measurement methodology requires two steps. First, the coefficient of thermal reflectance is determined for each of the surface materials to be scanned. Second, the changes in the surface reflectivity as a function of changes in temperature are measured at each point of interest with submicron spatial resolution and better than microsecond temporal resolution. The resulting reflectivity waveforms are combined to obtain a transient temperature field over the scanned area. The method is applied to determine the thermal behavior of actual MOSFET devices. First, the method is used to measured an activated MOSFET device and show that by scanning first and then switching the source and drain contacts, the two resulting steady state temperature scans are symmetrical. The method is then used to differentiate between the transient thermal behavior of identically activated devices that have been made on two different epitaxial layers, one with natural and the other with isotopically-pure silicon. The results show non-negligible differences in the resulting transient temperature signatures due to the use of different materials in the construction of the otherwise identical devices, with the isotopically-pure silicon device running cooler than the corresponding device made with natural silicon. This measured behavior provides confirmation of the authors’ previous measurement of a higher thermal conductivity for isotopically-pure silicon. The results are shown as quasi-steady temperature contour plots and snapshots of the temporal evolution of the surface temperature fields for both types of MOSFET devices.
Superlattice Thermoelectrics for Thermal Management of Electronics and Optoelectronics
Authors: Venkatasubramanian R. , O’Quinn B. , Alley R. , Siivola E. , Reddy A. , Soto M. , Addepalli P.
Published: April 2009

Solid-state cooling technologies using advanced superlattice thermoelectric materials are likely to provide not only near-term solutions for the hot-spots but also scalable refrigeration solutions for the entire chip. We discuss our development efforts with the superlattice thermoelectric technology for advanced microprocessor thermal management. We also discuss the development of similar technologies for application in the thermal management of optoelectronic components. The performance of small footprint thermoelectric modules fabricated using the thin film superlattice materials are discussed. We have begun early reliability studies on the superlattice materials, devices, and modules and the early results are positive. Advanced reliability studies using full Mil-spec and Telecordia-like power cycling are being undertaken for full commercial implementation of such advanced thermoelectric components.
Numerical Analysis of Electro-Thermal Phenomena in Metal by Boltzmann Transport Equation for Electron
Authors: Ito Kohei , Muramoto Ryohei , Shiozawa Isamu , Kakimoto Yasushi , Masuoka Takashi
Published: April 2009

By the development of micro-fabrication technology, much smaller-size electronic devices will be soon available. In such a smaller device, a non-equilibrium state might appear in metal and/or semiconductor. In this case, it is difficult to estimate the device performance by the macroscopic transport equations that assume quasi-equilibrium distribution. We are developing a numerical simulation based on Boltzmann transport equation (BTE), which can analyze thermal and electric phenomena even when the state is far from equilibrium. In this study, we show a new formulation of BTE for free electron in metal and its calculation result: the thermoelectric power obtained agreed with that of experimental value: the heat flux derived by the non-equilibrium distribution was two-orders small than that estimated by thermal conductivity.
Simplified Network Based Modeling of Cold Plate in a CFD Environment
Authors: Pal Debabrata , Severson Mark
Published: April 2009

Thermal management of high power electronics for aerospace applications frequently utilizes liquid or air-cooled cold plates with embedded fin cores. These commonly used cold plates use fin assemblies with small flow passages and large area enhancements to achieve high levels of heat transfer performance. The design of this type of cold plate is well documented in the literature, with the most common methodology utilizing “f” and “j” test data as a function of Reynolds Number. This paper presents a technique termed “network modeling” that simplifies the modeling of cold plate features within a CFD model. This technique greatly reduces model size and CPU time needed for solutions. In addition, it is inherently accurate because it allows test data to be incorporated into the model. Simplification of the performance of coldplate features within a system level CFD thermal model is a great advantage, as modeling these small coldplate features is a tedious task and often unnecessary. The methodology presented uses a convective resistance network with mass flow links and convective links to describe the overall thermal behavior of the coldplate. This simplified network model can be used within a detailed thermal model of the electronics assembly to provide an accurate simplification of the coldplate performance for temperature and heat flow prediction. Since the network technique simplifies the flow boundary conditions, the detailed thermal model can contain as much internal details of an electronics assembly as desired, while still keeping the overall model size manageable and CPU times minimal. This network-based method of modeling coldplate should be very accurate because it is based upon established test data of “f” and “j” as the basis of the model. This network method has significant advantages over the other methods of heat exchanger simplification such as coarse mesh, effective thermal conductivity, source-sink, etc. This paper describes the creation of such a network, integration in an ICEPAK thermal model, discussion of the advantages, and results.
Impingement Air Cooling With Synthetic Jets Over Small and Large Heated Surfaces
Authors: Garg Jivtesh , Arik Mehmet , Weaver Stanton
Published: April 2009

Increasing heat loads and the need for improving natural convection heat transfer has brought micro fluidic technology into the thermal management of electronics. A maximum air velocity of 90 m/s from an 800 μm hydraulic diameter orifice was achieved through specially designed synthetic jets. The resonance frequency for a particular jet was determined through the effect of exit velocity magnitude, as well as power consumption. During the experiments, the operating frequency for the jet was varied between 3000 and 5000 Hz. Heat transfer augmentation experiments were performed on two heaters with different sizes to understand the size effect. A microscopic infrared thermal imaging technique was used to acquire fine scale temperature measurements. While an earlier study focused on a heater with a surface area of 160 mm2, the current study used a heater with a surface area of 1450 mm2, which is approximately 9 times larger. The effect of jet-location, driving-voltage, frequency and heater-power were studied during the experiments. A heat transfer coefficient enhancement over natural convection of 10 times, with the smaller heater, and 5 times, with the larger heater was measured.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
Modeling of Electron Transport in Thin Films With Quantum and Scattering Effects
Authors: Bulusu A. , Walker D. G.
Published: April 2009

With device dimensions shrinking to nanoscales, quantum effects such as confinement and tunneling become significant in electron transport. In addition, thermal transport in devices is directly coupled to charge transport even in highly scaled devices. While electron-phonon scattering usually helps restore thermodynamic equilibrium, shrinking device dimensions may not ensure enough scattering to restore equilibrium. The simultaneous consideration of scattering effects, which is usually described as particle behavior, and quantum effects, which are wave in nature, is extremely difficult and computationally intensive. Most device transport simulation models are not mature enough to couple quantum effects with strong scattering effects. In this paper, we couple quantum effects and scattering influences on electron transport using the non-equilibrium Green’s function formalism. Results indicate a 45 to 70 percent decrease in channel current for the case of near-elastic, phase-breaking, electron-phonon scattering. The single phonon energies ranged from 2meV to 20meV. The results illustrate the importance of including scattering effects with quantum transport. In addition, the NEGF model is used to assess the effect of temperature on device characteristics of thin film superlattices whose applications include thermoelectric cooling of electronic and optoelectronic systems. Results show the predicted Seebeck coefficient to be in good agreement with the measured values.
Future of Thermal Management of High End Video Cards in ATX and BTX
Authors: Refai-Ahmed Gamal , Tantoush Mohammed , Novak Colin
Published: April 2009

The present study aims to examine the future of the thermal management of video cards in PC systems. The primary focus of this investigation is on high end video card applications in both the ATX and BTX platforms. In this article, the thermo-mechanical architecture of these platforms will be revealed along with a discussion of the power density road map of both the graphics processing unit (GPU) and video processor unit (VPU) expected to be in use until the year 2010. Recommendations of how to extend the air cooling limit for video cards in either the ATX or BTX platforms will be part of the conclusions of this study.
Multidirectional Force and Torque Sensor for Insect Flight Research
Authors: Nasir Mansoor , Dickinson Michael , Liepmann Dorian
Published: April 2009

This paper focuses on the development of a microsensor system that can simultaneously measure multidirectional forces generated by a tethered fly. The proposed sensor combines the well-understood concepts of piezoresistive force sensing with a very unique design that not only allows the measurement forces with more than one degree of freedom (DOF) but will simultaneously support the fly inside a virtual reality arena. The sensor is fabricated on a wafer-level using standard MicroElectro-Mechanical System or MEMS technology. By a directly measuring the thrust, lift, yaw and side slip generated by the fly, complex aerodynamics mechanisms due to rapidly rotating and flapping wings can be better understood.
The Effect of Die Attach Voiding on the Thermal Resistance of Chip Level Packages
Authors: Fleischer Amy S. , Johnson Barry C. , Chang Li-Hsin
Published: April 2009

During semiconductor manufacturing, voids are easily formed in the die attach bond layer and are found to form, grow and coalesce with thermal cycling. The presence of such voids is known to adversely affect the package thermal resistance, but to this point, not enough data exists to precisely analyze the effects of void size, configuration and depth. Using an innovative experimental method the present study investigates these effects with a carefully controlled void geometry. The results show that the thermal resistance increases linearly with void percentage for random voids, but increases exponentially for contiguous voids.
Thermal Analyses of Composite Copper/ Porous Graphite Spreaders for Immersion Cooling Applications
Authors: El-Genk Mohamed S. , Saber Hamed H. , Parker Jack
Published: April 2009

The performance of composite spreaders cooled by nucleate boiling of FC-72 liquid and made of top porous graphite layer (≥ 0.4 mm or ΔPG ≥ 0.2), for enhancing nucleate boiling, and copper substrate (≤ 1.6 mm), for efficient spreading of the thermal power dissipated by underlying chips is investigated. The spreaders are of the same thickness (2.0 mm) and have square surface areas that are sized depending on the composition and cooling condition of the spreaders. The 10 × 10 mm and 15 × 15 mm chips considered in the analysis are assumed to uniformly dissipate the thermal power. With composite spreaders (ΔPG = 0.2) cooled by 30 K subcooled nucleate boiling the removed total dissipation thermal powers of 160.3 W and 98.4 W from the 10 × 10 mm and 15 × 15 mm chips, respectively, are attainable at total thermal resistances of 0.29 and 0.48 °C/W, respectively. When these spreaders are cooled by saturation nucleate boiling, however, the removed dissipation thermal powers (85.6 W and 53.4 W, respectively) and the total thermal resistances (0.12 and 0.20 °C/W, respectively) are much lower. For same cooling conditions, the removed dissipation thermal powers by the porous graphite spreaders (ΔPG = 1.0) are much lower and the thermal resistances are much higher than those with composite spreaders, because of the relatively low and anisotropic thermal conductivity of porous graphite. Results also showed that the surface temperatures of the chips are not uniform. The maximum chip temperatures at the highest removed dissipation powers by composite spreaders are < 71 °C and the temperature differentials across the chips are < 8 °C. Results demonstrated that composite spreaders are an attractive option for cooling high power computer chips at relatively low chip temperature.
Experiments on the Flow and Heat Transfer in Fine Pitch Parallel Plate Heat Sinks With Side Inlet Side Exit Flow
Authors: Ortega Gutierrez Felipe E. , Ortega Alfonso , Xu Guoping
Published: April 2009

Detailed static pressure and temperature measurements were made in fine pitch parallel plate copper heat sinks with and without top bypass flow. A set of heat sinks with differing fin pitch and with and without anodized finish were tested in a 3rd generation cross-flow wind tunnel that provides zero to one top clearance ratio. Static pressure measurements were made in the vicinity of the heat sink in order to study the influence of the top bypass for approach velocities from 1 to 10 m/s. A comparison was made with existing ad hoc models that model the core flow with laminar theory and the inlet and exit losses with empirical correlations from the compact heat exchanger literature. In general, excellent agreement was found in the laminar regime. However, significant deviation was found for approach velocities exceeding 5 m/s, probably because the flow transitions to turbulent beyond this approach Reynolds number. In the case of flow bypass a non-iterative two-leg bypass model yielded excellent agreement for pressure drop, indicating that an ad-hoc approach such as this has value. Precise temperature measurements were taken at different stream-wise locations at the centerline of the heat sinks, under conditions where the heat sink base was heated uniformly and when the base area was heated with a smaller heat source with a 1-to-11 heater-to-base area ratio. The combined data allow the direct evaluation of base heat spreading effects. The experimental results were compared to well-known models that solve the conduction problem by assuming either an isothermal boundary condition on the top of the base of the heat sink or a specified uniform effective heat transfer coefficient. Excellent agreement was found with the latter model.
Microstructure and Magnetic Properties of NdFeB Based Nanocomposites to Shock Compression
Authors: Lin Jin-Chein , Nien M. H. , Chang L. C.
Published: April 2009

Three typical Nd-Fe-B permanent magnetic alloys of Nd13Fe75B6Al6, Nd13Fe79B6Si2 and Nd13Fe80B6Zr1 have been presented to study the effect of annealing and shock compression on the microstructure, magnetic and mechanical properties. The response of NdFeB based nanocomposites mixed with medium particle morphologies of Al, Si and Zr, respectively were conducted under high shock pressure. The starting materials were prepared by rapidly quenching and melt-spinning of NdFeB based powders under vacuum at different temperatures. The magnetic properties on Br, Hci and (BH)max tend to increase with rising annealing temperature, and reach their highest value at either 700° or 750°C. The addition of Zr and Si enhance the chemical short range reaction and stablize the residual amorphous matrix. For recovery shock-consolidate compression, Br and Hci reach to a peak value at about 5.5 GPa which can be closely associated with the retention of nanostructure and strong exchange coupling between hard and soft magnetic phases. Secondly, the main work is to experimentally investigate the mechanics of the deformation processes leading to shock-induced chemical reaction. The results showed that the fracture mechanism on three specific magnetic alloys reveal that the Nd13Fe79B6Si2 sample, and the addition of Zr in NdFeB will lead to embrittlement of the ductile morphology.
Comparative Analysis of Different Data Center Airflow Management Configurations
Authors: Shrivastava Saurabh , Sammakia Bahgat , Schmidt Roger , Iyengar Madhusudan
Published: April 2009

Increase in computing power resulting from high performance microprocessors, packages, and modules and the deployment of high heat load computer rack units in high density configurations, has escalated the thermal challenges in today’s data center systems. One of the key issues is the location of hot recirculation regions in the room and the mixing of hot rack exhaust air with the cold supply air. Along with many factors such as the rack heat load and the cooling capacity of the supply air, the data center thermal management architecture plays an important role in determining the reliability of the electronic equipment and the general thermal performance of the data center. There are several candidate configurations available for the air ducting designs for data centers. The overall energy efficiency of the system is highly dependant upon the selection of the specific configuration. This paper will summarize the results of a broad numerical study carried out to assess the effectiveness of different data center configurations. The numerical modeling is performed using a commercial computational fluid dynamics (CFD) code based on finite volume approach. The configurations studied include different combinations of raised floor and ceiling supply and return vent location subject to specific constraints. The performance of the data center has been characterized on the basis of average and maximum mean region rack inlet air temperature. Among the seven different configurations compared, the raised floor/ceiling return type configuration is found to be the most effective configuration for the given set of constraints and assumptions.
Constitutive Relationship Development, Modeling and Measurement of Heat Stressing of Micro-SMD Assembly With Sn3.9Ag0.6Cu SAC Alloy
Authors: Xiao Qiang , Armstrong William D. , Pitarresi James M. , Chaparala Satish C. , Rogeman Brian D. , Sammakia Bahgat G. , Nguyen Luu
Published: April 2009

The Creep and microstructural changes during creep behaviors of bulk and thin cast forms of Sn3.9Ag0.6Cu were compared. The processing parameters of the thin cast material was selected to result in a very fine microstructure analogous to what occurs in very small size solder electronic interconnections. We found that the thin cast material was less creep-resistant than the bulk material. A comparison of Ag element maps between as crept bulk and thin cast material showed that the relevant climb process occurs in a very different environment in the bulk material as compared to the thin cast material. In the bulk material the relevant climb process occurs within a finely dispersed IMC eutectic which covers broad areas within the material. In the thin cast material the relevant climb process occurs primarily in the beta-Sn grains which continuously surround isolated, coarse IMC particles. This resulted in the activation energy of the bulk material being larger than that for the thin cast material. Finally, it is important to note that the strength deficiency of the thin cast material was persistent, once the material is cast in thin cast form it will remain weak in comparison to the bulk material. Therefore, using data obtained from bulk material samples for the construction of thermo-mechanical models of very small scale solder interconnections is likely to result in significant, intrinsic errors. Second, the thermal-mechanical response of electronic packages was simulated using the commercial finite element code ANSYS coupled with the Garofalo model to represent the solder constitutive creep response. The measured properties for bulk and thin-cast Sn3.9Ag0.6Cu SAC alloy were used in the FE modeling. A 36 I/O micro-surface mount device (SMD) package was used as a test vehicle in this work. Moire´ Interferometry was used to measure the horizontal displacements in the solder joints as a result of cooling the package from 100°C to room temperature. Modeling results were found to have good agreement with moire´ measurements on the actual SAC packages. The bulk properties produced a better correlation with the measurement of the horizontal displacement in the solder joints than the thin-cast properties. However, the assemblies that were tested used the Sn3.8Ag0.6Cu alloy rather than the Sn3.9Ag0.6Cu alloy. It is not known if this difference is significant to the thermo-mechanical response.
Thermal Devices Integrated With Thermoelectric Modules With Applications to CPU Cooling
Authors: Sauciuc Ioan , Erturk Hakan , Chrysler Gregory , Bala Vikram , Mahajan Ravi
Published: April 2009

Over the past few years, the air cooling technology improvements present diminishing returns for microprocessors cooling applications. Presently most of the proposed future cooling technologies (i.e. pumped liquid cooling or vapor compressor refrigeration) may need some fluid moving device and a large remote heat exchanger which requires additional volume. Due to the complexity, reliability issues and space requirements it is preferred to extend the air cooling within the current form factors and using passive devices. This paper will show that optimized thermoelectric modules combined with two-phase (liquid/vapor) passive devices can further improve the cooling capability compared to conventional air cooling technologies at reasonable thermoelectric cooler (TEC) power consumption. Current computational fluid dynamics programs are not yet well equipped to find out the most optimized TEC geometry (for a given COP and given thermal requirements) in a reasonable amount of computation time. Therefore, two modeling steps are proposed: find out the preliminary TEC geometry using an ID analytical program (based on uniform heat flux and a given COP) and use it as an input to CFD programs (i.e. Icepak®) for detailed predictions. Using this model, we confirmed that the conventional TEC technology must use some spreading device to dissipate the CPU heat to the TEC cold side. Different spreading devices are considered: solid metal, heat pipe, vapor chambers and single/two phase pumped cooling. Their individual performance integrated with TEC will be presented. In addition, we propose that the TEC performance to be controlled as a function of instantaneous CPU power consumption, ambient temperature and other parameters. This controller offers extra flexibility which can be used for either noise reduction or TEC power reduction. However, such power cycling of the TEC may affect the TEC reliability. Power cycling accelerated test data (>500,000 accelerated cycles) have been performed together with the life predictions will be presented in the paper.