(Invited) Transistor Applications Using Vertical III-V Nanowires on Si Platform
Authors: Tomioka Katsuhiro , Fukui Takashi 
Published: February 2020

III-V compound semiconductor nanowires (NWs) have stimulated interest in recent years because of their unique properties and potential applications as building blocks for nanoscale electronic and photonic devices. For future electronics, inherent issue for low-power LSI is lowering supply voltage of transistor while avoiding physical limit of subthreshold slope (SS = 2.3 k
BT/q = 60 mV/dec). Otherwise, this limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented. In this talk we report on new tunnel junction based on III-V/Si interface [1,2] which is formed by selective-area growth of III-V nanowires (NWs) on Si [3-5], and demonstrated vertical TFETs with steeper SS[6,7]. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials.

For integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [6]. Sn was used for n-type dopant, and Zn-pulse doping technique [7] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-long in this case).

Next, we demonstrate electronic devices using III-V NWs on a Si substrate. Fabricated vertical transistors contained In0.7Ga0.3As NWs with modulation doped layer. We observed n-type FET behavior in ID-VDS and ID-VG characteristics. The performances are threshold voltage ~ 0.25 V, Gm,max = 1.45 µS/µm at VDS = 0.50 V, Ion / Ioff > 106, subthreshold slope, SS = 78 mV/decade.

Besides the III-V NW-based vertical FETs, the heterointerface between the III-V NWs and Si can be used as tunnel FETs (TFETs). In this case, we use band discontinuity between III-V NWs and Si substrate for TFETs. The device fabricated by InAs NW on Si substrate showed switching behavior with an average subthreshold slope (SS) of 30 mV/dec, which is much lower than the physical limitation of metal-oxide-semiconductor field-effect transistors (MOSFETs, SS ~ 60 mV/dec.) [8,9]. Reducing the opening diameter of the masked substrate decreased the numbers of misfit dislocations. The TFETs made by using III-V NW/Si heterojunctions demonstrated steep-SS properties at room temperature. One of the key issues in the vertical TFETs is the formation of intrinsic channels inside the tiny NW-body and another is the reduction of NW-diameter. We also discuss several current-boosting technologies for the TFETs. The current-boosted TFET exhibits steep SS and high Ion, and the transconductance efficiency (Gm/ID), which is important parameter for low-power analog circuits, is a thousand times higher than that of conventional MOSFETs [10].

 

References

1) K. Tomioka and T. Fukui, Appl. Phys. Lett., 98, 083114-1 – 3 (2011).

2) K. Tomioka and T. Fukui, Appl. Phys. Lett., 104, 073507-1 – 4 (2014).

3) K. Tomioka et al., Nano Lett., 8, 3475 – 3480 (2008).

4) K. Tomioka et al., Nanotechnology, 20, 145302 – 145309 (2009)

5) K. Tomioka et al., Nature, 488, 189 – 192 (2012).

6) K. Tomioka et al., Nano Lett., 13, 5822 – 5826 (2013)

7) E. Nakai et al., Jpn. J. Appl. Phys., 54, 015201-1 – 3 (2015).

8) K. Tomioka et al., IEEE IEDM Tech. Dig. 88 – 91 (2013).

9) K. Tomioka et al., IEEE ESSDERC Tech. Dig. 397 – 402 (2016).

10) K. Tomioka et al., paper submitted