bluuebunny/crossref_metadata_2025 huggingface dataset:
Use of Polyalkylene Carbonate Binders for Improved Performance in Multilayer Ceramic Capacitors
Authors: Ferraro Peter , Hanggodo Sugianto , Burn Ian , Baker Amanda , Qu Weiguo
Published: October 2015

Past work by Polotai and co-workers produced convincing evidence that a Ni-Ba-Ti alloy layer forms at the electrode/dielectric interface of multilayer ceramic capacitors (MLCC’s) made with Ni electrodes and a barium titanate based dielectric. It has been shown that this alloy layer can lead to discontinuous electrodes, resulting in reduced capacitance and lower reliability. The most likely explanation is that the alloy layer results from residual carbon remaining after the binders used to make the tape and paste are decomposed. Polypropylene carbonate binder is known for its extremely clean burnout properties so a multilayer structure was prepared from QPAC® polypropylene carbonate binder in both the dielectric tape and nickel electrode paste. This was compared against a multilayer structure prepared using PVB binder for the dielectric tape and a nickel paste based on ethyl cellulose. Examination of the fired parts by TEM clearly showed the elimination of the interfacial layer when using the polypropylene carbonate binder system. Good electrode continuity was also obtained.
Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump
Authors: Orii Yasumitsu , Toriyama Kazushige , Kohara Sayuri , Noma Hirokazu , Okamoto Keishi , Toyoshima Daisuke , Uenishi Keisuke
Published: October 2015

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.
Hardware Design for Multiple Gas Detection System Using Zeolite Coated with Nile Red
Authors: Nguyen Son , Delalic Z. Joan , Kargbo David M. , Sheffield Joel B. , Hasan Zameer
Published: October 2015

The goal of this research is to develop a nanosensor that integrates a zeolite/dye sensing unit with an optoelectronic detector, fully integrated into a portable gas sensor. The device will detect and measure more than one target gas at the same time. Since nanoporous structures of zeolites are manipulated, the device is expected to be more accurate, more sensitive, is able to better differentiate and detect any one target in a mixture of different gases. This is achieved by incorporating fluorescent dyes into the zeolites’ cavities, measuring gas absorption, desorption and photo-chromic interaction of dye and gases, interfacing the zeolite/dye sensor arrays with light source and electronic detectors. The electronic part of the device is fully customized VLSI chip. The final device will be packaged into a portable unit. The designed and packaged prototype will be presented.
BGA Solder Life Prediction under Combined Power and Temperature Cycling Condition
Authors: Chai Fei , Osterman Michael , Pecht Michael
Published: October 2015

Solder interconnect failure is a known life limiting failure mechanism that is induced by cyclic temperature excursions. Thermal fatigue reliability of solder interconnects is conventionally assessed by simple temperature cycling test, which applies a constant temperature range, fixed dwell times and ramp rates during the test. However, due to the user controlled power cycles, non-constant workloads, and changes in the surrounding environment, electronics in the field often experience a complex combination of temperature and power cycling.

In this study, the effect of power cycling superposed on a simple temperature cycling is experimentally examined. Furthermore, a scheme for modeling the solder interconnect fatigue life of Plastic Ball Grid Array (PBGA) parts under the concurrent power and temperature cycling. Damage, defined as the number of applied cycles over the number of survivable cycles, from the simple temperature cycle and the power cycle are linearly added using Miner's rule, and compared with the concurrent temperature and power cycling test. Cycles to failure of each condition is derived by life testing conducted on Plastic Ball Grid Array (PBGA) assembled with eutectic and SAC305 solder.
Evaluating the Impact of Dwell Time on Solder Interconnect Durability under Bending Loads
Authors: Menon Sandeep , Osterman Michael , Pecht Michael
Published: October 2015

With increased portability and miniaturization of modern day electronics, the mechanical robustness of these systems has become more of a concern. Existing standards for conducting mechanical durability tests of electronic assemblies include bend, shock/drop, vibration and torsion. Though these standards provide insights into both cyclic fatigue and overstress damage incurred in the solder interconnects (widely regarded as the primary mode of failure in electronic assemblies), they fail to address the impact of time dependent (creep) behavior due to sustained mechanical loads on the solder interconnect durability. It has been seen that the solder durability under thermal cycling loads is inversely proportional to the dwell time or hold time at either temperature extreme of the imposed temperature cycle. Fatigue life models, which include dwell time, have been developed for solder interconnects subject to temperature cycling. However the fatigue life models that have been developed in literature for solder interconnects under mechanical loads fail to address the impact the duration of loading. In this study, solder interconnect test vehicles were subject to cyclic mechanical bending with varying dwell times in order to understand the impact of duration of mechanical loads on the solder interconnect durability. The solder interconnects examined in this study were formed with 2512 resistor packages using varying solder compositions (SnPb and SAC305). In order to evaluate the impact of dwell time, the boards were tested with a 60 second and a 300 second dwell time on both extremes of the loading profile. It was observed that an increase in dwell time of the loading profile resulted in a decrease in the characteristic life of the solder interconnects.
Understanding and Controlling Cu Protrusions in 3D TSV Processing
Authors: Kruger Seth , Hummler Klaus , Geer Robert , Dunn Kathleen , McDonough Colin , Cordes Aaron , Enloe Jack , Sapp Brian , Ali Iqbal , Pieper Stefan , Arkalgud Sitaram , Murray Thomas
Published: October 2015

Cu-filled through-silicon vias (TSVs) are an essential building block of 3D and 2.5D integrated chips. In the TSV-mid processing flow, which has emerged as an industry mainstream, one or more on-chip wiring levels are formed after the TSV Cu fill is completed, which exposes the fill to peak temperatures of up to 400 °C. Due to the higher coefficient of thermal expansion (CTE) of Cu than the surrounding silicon and dielectrics, the TSV fill protrudes above the level previously defined by the TSV chemical mechanical polishing (CMP) step. Even after returning to room temperature, the top of the TSV will not occupy the same space due to plastic deformation during the thermal treatment. This phenomenon is known as Cu protrusions, pumping, or popping. Excessive amounts of Cu protrusion present a risk to yields and reliability because the expansion can damage dielectrics and wiring above or adjacent to the TSVs.

In this study, we report the underlying mechanisms as well as process remedies for Cu protrusions. The SEMATECH 5 um × 50 um TSV process and learning vehicle is used to conduct process split experiments comparing various plating chemistries, plating recipes, and post-plating anneal conditions. Stresses in the surrounding silicon are studied by micro-Raman, and a distinct signature distinguishing good from bad Cu protrusion behavior is identified. Cu material properties such as contamination, grain size, grain orientation, and strain may also influence the protrusion behavior; these factors are studied by micro-secondary ion mass spectroscopy (SIMS) and electron backscatter spectroscopy (EBSD). Our results shows that the choice of plating chemistry and subsequent optimized post-plating anneal are the main factors in suppressing Cu protrusions. Our best known method is able to reduce Cu protrusions to about 15 nm after typical thermal loads.
An Overview - Temporary Wafer Bonding / Debonding for 2.5D and 3D Technologies
Authors: Chanchani Rajen
Published: October 2015

In recent years, material suppliers in collaboration with equipment suppliers have developed many new materials/process options for temporary bonding and debonding to be used in 2.5D and 3D technologies. . These options are still being evaluated and at best they are in prototype stage. As a result, the cost is still perceived to be high, there are no reliability data available and many new users in the market are confused about which option and corresponding equipment set should they invest in. I will present the requirements for ideal temporary bonding debonding solution, describe the available technology options for temporary bonding and debonding and their status.

The primary technologies for temporary bonding are adhesive-based. These adhesives are tailored so the adhesive bonds can be broken either by laser ablation, thermal-slide, ZoneBond process, solvent release or mechanical peel-off. It appears that a single solution will not be applicable to all different 2.5D/3D technologies that are being developed and thus, multiple options will be the forerunners.
Getters and Design to Reliability: A Tool For Lifetime Assurance
Authors: Kullberg Richard C. , Phillip Bradley L.
Published: October 2015

The key to reaching multi-decade package lifetimes and device reliability is to not just take a snap shot with a RGA and declaring a part passed per MIL-STD-883. It requires a deep understanding of the sources of unwanted gases in a package, characterizing their true flow rates within, without and through the package system, and carefully choosing processes and materials, including getters, to manage the unwanted gases. This is true whether the package is hermetic or non-hermetic.

A multi-step process is discussed to include identifying the gas sources, the species present and their quantities, modeling the true quantities of gas generated over the lifetime of the package, and removing it, either through process or materials. When package service lifetimes reach decades, traditional understandings start to fall apart and careful quantitative analysis is rewarded.

Getters play a key role in attaining multi-decade lifetimes. Getter selection and sizing is discussed. Included in the discussion will be a brief synopsis of the current state of the art of gettering technology.
Advanced Manufacturing Methods for Brazing High-Reliability Electronic Packages
Authors: Labadie Iris
Published: October 2015

Brazing is a critical process for producing reliable adhesion between package metallization and metal components such as heat sinks, seal rings, and connectors. Package performance for signal integrity, mechanical reliability, and thermal management not only relies on improved materials but also on manufacturing methods designed to leverage those improvements. High-reliability packaging for applications in medical, harsh environment or aerospace applications requires a thorough understanding of which fabrication processes to select, as well as fixturing and material preparation to meet increasing demands for low electrical losses at higher frequencies and higher thermal conductivity for high-power GaN and SiC device operation. In the present work, utilization of manufacturing design tools and methods for optimal brazing will be discussed.
Reliability analysis of low-Ag BGA solder joints using four failure criteria
Authors: Kimura Erin , Pan Jianbiao
Published: October 2015

The appropriate selection of failure criterion for solder joint studies is necessary to correctly estimate reliability life. The objective of this study is to compare the effect of different failure criteria on the reliability life estimation. The four failure criteria in this study are a 20% resistance increase defined in the IPC-9701A standard, a resistance beyond 500Ω, an infinite resistance (hard open), and a failure criterion based on X̄ and R control charts. Accelerated thermal cycling conditions of a low-silver BGA study included 0°C to 100 °C with ten minute dwell times and −40°C to 125°C with ten minute dwell times. The results show that the life estimation based on X̄ and R failure criterion is very similar to the life estimation when a 20% resistance increase defined in the IPC-9701A failure criterion is used. The results also show that the reliability life would be overestimated if the failure criterion of a resistance threshold of 500Ω or an infinite resistance (hard open) is used.
Mixed Attachment Technology Studies in RF & Optoelectronic Packages Requiring High Accuracy Placement
Authors: Evans Daniel D. , Bok Zeger
Published: October 2015

RF & Optoelectronic packages continue to shrink in size with less space for die. Power densities are increasing as well. Packaging engineers are exploring a switch from conductive adhesive to eutectic solder attachments on high power components. Lower power components still allow adhesive attachment but have their own challenges due to tight spacing. This paper explores a range of case studies that demonstrate both eutectic and adhesive assembly and the results for closely spaced components.

An overview of the technology and the placement accuracy and attachment method is presented for eutectic and adhesive based attachment for components ranging from 0.18mm [7.1mil] × 0.18mm [7.1mil] × 0.20mm [7.9mil] Si die to 1.7mm [67mil] × 1.4mm [55mil] × 0.16mm [6.3mil] GaAs die. Component spacing of 60μm or less create challenges in keeping epoxy or solder from squeezing between die.

A review of tools, guidelines, and actual results will be shared in this paper.
Smart and Quick Dk, Df Extraction Flow of Halogen-free and Lead-free Materials under Different Temperatures
Authors: Liu Chang-Chih , Tsai Cheng-Hua , Chen Wei-Ting , Cheng Chang-Sheng , Chang Li-Chi
Published: October 2015

Halogen-free and lead-free materials are eco-friendly and the main trend in the long run. Recently, a lot of electronic gadgets including not only mobile phones but relevant accessories have been gradually made of this kind of material in place of traditional formulas to comply with the compliance by European Union. However, there are many drawbacks about halogen-free and lead-free materials such as mechanical reliability and thermal issues which will cause the failure in use. Besides, electrical property is another inevitably critical problem. Not a few of electronic devices are needed to operate under different environmental temperatures stemming from different locations or the heat generated itself. Different ambient temperatures can affect the normality of each material used within the device and further influence the whole function. Therefore, correct and quick extraction of electrical parameters of the material is desirable in the development of high speed application easily influenced by the variation of temperature to conform to the requirement of higher precision of parameters and lower-cost expectation. Based on this reason, the main purpose of this paper is to set up a procedure which can provide an easy and reliable calibration and measurement of vector network analyzer (VNA) accompanies with thermal cycle oven to satisfy the users who want to get these electrical parameters in short time. Dielectric constant (Dk) and dissipation factor (Df), the most two important electrical parameters, have been quickly analyzed in planar-circuit methods and processed by the programs designed by ourselves under ambient temperatures ranging from −40 to 85 degree Celsius. The results of measurement reveal that Dk and Df of the halogen-free and lead-free material among these interest temperatures are 4.5–4.85 and 0.01–0.035, respectively.
Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging
Authors: Malachowski Karl , Qian Karen , de Beeck Maaike Op , Verbeeck Rita , Bryce George , Dekkers Harold , Tezcan Deniz S.
Published: October 2015

Material selection is the key issue when developing a biocompatible packaging process for implantable electronic systems. To secure a reliable performance of the chip in such a package, its encapsulation has to be considered up-front in the wafer-level integration scheme. A differentiation of two main material types can be made:1) Insulating or passive materials functioning as a bi-directional diffusion barrier preventing body fluids leaking into the package causing systems malfunction due to possible materials corrosion and also avoiding a leakage of built-in materials to the in-vivo environment and2) Conductive or active materials as diffusion barriers, e.g. against copper diffusion or as direct external contacts responsible for electrical performance of the system.

This study investigates the properties of two widely used insulating materials in the semiconductor industry, the nitride and the oxide. Both material types are deposited in a PECVD system using different temperatures; 400 ° C for CMOS compatibility and 200 ° C for wafer back side process integration when a temporary carrier system is used. The biocompatibility investigations of these materials (evaluated using cell lines and primary cells) show promising results. However, for the long term application, the stability results for the oxide layers show hydration effects resulting in material degradation where the nitride layers clearly show corrosion and are even etched when elevated temperatures are applied. This fact is surprising since nitride layers are widely used as a humidity barrier for various chip types but obviously not suitable for a direct contact with liquids. Various analysis methods using e.g. Fourier Transformed IR Spectroscopy or mass measurements substantiate this thesis.
Assembly and Packaging of a Wireless, Chronically-Implantable Neural Prosthetic Device
Authors: Shah Kedar G. , Tooker A. , Tolosa V. , DeLima T. , Benett W. , Felix S. , Sheth H. , Pannu S.
Published: October 2015

We present a chronically implantable, 121-channel, wireless neural prosthetic device assembled using a combination of novel and standard microelectronics packaging techniques. The exposed components are made of long-term biocompatible materials and are assembled into a three-dimensional package to minimize implant size. This device will be implanted into the spinal cord of an animal and is capable of electrically stimulating neural tissue. The objective of this work is to develop a clinical treatment for patients who lack micturition or bladder control due to paralysis or neurological-impairment.
Epidermal electronics for health and fitness monitoring
Authors: Rafferty Conor , Dalal Mitul , Davis Dan , Elolampi Brian , Hsu Yung-Yu , Lee Stephen , Klinker Lauren , Morey Briana
Published: October 2015

Medical deployment of electronics is frequently hampered by boxy, rigid packaging. Biological tissues are soft and curved, while electronic components are hard and angular. The mechanical mismatch can be alleviated by re-packaging electronics in radical new form factors. MC10 has developed a technology platform using ultra-thin components linked with stretchable interconnects and embedded in low modulus polymers which provide an excellent match to biological tissues.

The MC10 platform is based on packaging today's high-performance active components in new mechanical form factors. The platform has three key elements: thin silicon embedded in film for flexibility, silicon transfer from foundry CMOS wafers to polymer-coated carriers and flexible metallic interconnect on polymer.

On-body and in-body applications are both well suited to the technology platform. Skin-mounted systems resemble electronic tattoos, and can be worn for extended periods without discomfort while providing continuous monitoring. Inside the body, instrumented catheters provide a practitioner with unprecedented electrical information about the interior of the heart.
Laminate Materials for Microfluidic PCBs
Authors: Babikian Sarkis , Soriano Brian , Li G.P. , Bachman Mark
Published: October 2015

The printed circuit board (PCB) is a very attractive platform to produce highly integrated highly functional microfluidic devices. We have investigated laminate materials and developed novel fabrication processes to realize low cost and scalable to manufacturing integrated microfluidics on PCBs. In this paper we describe our vision to integrate functional components with microfluidic channels. We also report on the use of Ethylene Vinyl Acetate (EVA) as a laminate for microfluidics. The material was characterized for microfluidic applications and compared with our previously reported laminates: 1002F and Polyurethane.
Process integration solution for damage-free bevel for deep Si etch applications
Authors: Majeed Bivragh , Tutunjyan Nina , Fiorini Paolo , Tezcan Deniz. S.
Published: October 2015

This paper reports on the process integration solutions to protect wafer bevel during deep Silicon etching (DSiE) process. In DSiE systems with no physical protection of the wafer bevel, the etching species attack the exposed bevel of the wafer. The damage to the bevel leads to yield loss and numerous processing issues. The damaged bevel wafers are very fragile and very susceptible to breakage. In this paper we present two generic approaches that can be applied to integration flow requiring deep Si etch up to 200 to 230 μm deep. We demonstrate these two approaches for silicon lab-on chip (LoC) fabrication. Silicon fabrication technologies allow very accurate, repeatable and reliable system development in bio-medical applications.
Biocompatible encapsulation and interconnection technology for implantable electronic devices
Authors: de Beeck Maaike Op , O'Callaghan John , Qian Karen , Morcos Bishoy M. , Radisic Aleksandar , Malachowski Karl , Amira M. F. , Van Hoof Chris
Published: October 2015

A biocompatible packaging process for implantable electronic systems is under development at imec, combining biocompatibility, hermeticity, extreme miniaturization and cost aspects.

In a first phase of this packaging sequence, hermetic chip sealing is performed by encapsulating all chips to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, biostability, diffusion barrier properties and sensitivity to corrosion. Material selection and integration aspects are modified until good properties are obtained.

In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme. We selected the use of Pt due to its excellent biocompatibility and corrosion resistance. Since Pt is very expensive, a cost effective Pt-selective plating process is developed.

During the third packaging step, all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all components are finally embedded using a medical grade elastomer such as PDMS or Poly-urethane.
Electromigration Performance of Fine-Pitch Copper Pillar Interconnections
Authors: Syed Ahmer , Berry Christopher J. , Dhandapani Karthikeyan , Thompson Patrick , Chae Seung-Hyun
Published: October 2015

The miniaturization trend in electronic packaging continues to drive smaller and smaller chip-to-substrate interconnections with no reduction in IC operating temperature or device power in sight. These two factors (current density and temperature) make the electromigration lifetime of chip-to-package interconnections a critical consideration in package design. Of particular interest these days are the “fine pitch copper pillar” structures due to their very small size (30um dia or less). This paper presents interconnection lifetime and metallurgical data on the same which demonstrates the extreme robustness of these joints due largely to their reaching a fully reacted state in which no free solder exists in the conduction path thus providing electromigration performance like that of the base copper and intermetallic compounds. Joint resistance trends observed during stress testing are also discussed.
Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's
Authors: Nakamoto Mark , Dhandapani Karthikeyan , Zhao Wei , Syed Ahmer , Lin Wei , Radojcic Riko
Published: October 2015

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance.

Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates an interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC's) to act as a hand-off between the two simulation tools. A package level modeling approach is developed incorporating package assembly processes to predict residual stresses at the end of package assembly process. It allows flexibility in selecting boundaries at chip-package interface and then the extraction of BC's necessary for die and transistor level simulations. These boundaries for Chip-Package Interaction are selected by the device manufacturer and the output from this simulation is fed into device level simulations. To provide flexibility for the user and to attain quick turnaround time, a web hosted interface is enabled to run package simulations online.

Examples are presented to demonstrate the influence and impacts of materials, process recipes and chip/package design; including an example of the flow from package level through silicon electrical level modeling to silicon hardware measurements.
Influence of Different Packaging and Footprint Technique for Microwave Absorptive Bessel Filter's Performance
Authors: Rahman Akhlaq , Norman Jim
Published: October 2015

In present day's ultra high speed data transmission environment, passive filters play a very important and critical function to achieve high-end system performance, especially in Microwave frequency ranges of 10 GHz or higher. Excellent electrical specification such as accurate −3dB cutoff frequency bandwidth, stable group delay, along with VSWR characteristics are very important parameters for system performance. Filters mechanical specification is similarly important, if not more. Products need not only be in certain size to fit in the board but also needs to be complement with other components. As available space in PCB become miniature for each component, filters footprint as well as via position need to be in certain ways to optimize board space and performance. Packaging material and packaging techniques play significant role to be ease of mass production as well. While some manufacturers like “Wirebonding” packaging, some like “Through Via”, and “Ball Grid Array” is the packaging choice of some manufacturers. Component vendors need to have capability to change component design space, as the system designers' demand for their choice of footprint and packaging environment. Moreover, these stringent mechanical specifications cannot compromise the electrical specification. To realize the effect of different packaging technique, we extensively studied several packaging techniques for Bessel filters with −3dB cutoff frequencies of 7 GHz to 10 GHz. We explored “stud bump ball grid array”, “wirebonding”, and “land grid array” footprint packaging. We modeled different packaging technique and incorporated that into simulation to design the filter. We successfully manufacture surface mount filters with three different footprint packaging. We explored the influence of each packaging technique for electrical performance. We studied the hidden parasitic introduction from each packaging style and the detrimental effect of these to electrical performance, especially for frequency of 7 GHz to 10 GHz. We showed the advantages and disadvantages of all three kind of packaging technology in respect of electrical as well as mechanical specification.
Qualification of Polyimide Based Coverlays for 900 MHz and 2.40 GHz Microstrip Antenna Applications
Authors: Nair Deepukumar , Oliver Glenn , Parisi Jim
Published: October 2015

Organic coverlays are required to protect microstrip circuits in most applications. The presence of coverlay can potentially influence the performance of microstrip antennas. This paper describes the qualification of polyimide based coverlays for microstrip antennas both in 900 MHz and 2.50 GHz frequency bands. An Inverted F-shaped antenna fabricated on FR-4 dielectric is used as the test vehicle and two different coverlay materials are tested with respect to key parameters like resonant frequency, S11 bandwidth, antenna gain, frequency detuning, and radiation pattern. The data presented in this paper clearly indicates polyimide materials are well suited to cover microstrip antenna circuits with minimal impact on performance.
Characterization of Over Pad Metallization (OPM) for High Temperature Reliability
Authors: Mathew Varughese , Tran Tu Anh
Published: October 2015

Temperature is a key accelerating factor for failures in semiconductor devices which brings reliability challenges for electronic packaging process because of the thermo-mechanical, metallurgical and chemical properties of the materials used in packaging. Failures at high temperatures (≥ 175 °C) often originate from aluminum – gold wirebonding systems because of the formation of Au-Al intermetallic phases and associated Kirkendall voiding which degrade the interface. A stack of Nickel/Palladium /Gold (Over Pad Metallization or OPM) formed on aluminum or copper bond pads are reported to be reliable pad finishing for high temperature applications. In this study OPM stack is formed by electroless plating on aluminum bond pads separated by 10 μm or more and the process is optimized to achieve high process yields. Al bond pad contamination is shown to be an important factor for achieving good plating quality and yield. Various plating defects which can lead to electrical failures are characterized. It is shown that defective rough plating can lead to wirebonding failures such as non-stick on pads (NSOP). Interface of gold ball bond and OPM after thermal aging at 225 °C for 168 hours is characterized by High Resolution Transmission Electron Microscopy (TEM) and Focused ion beam (FIB) cross-section analysis. Excellent thermal reliability with no degradation of ball shear or wire pull strengths achieved with non-defective OPM pads. High temperature (175 °C) package reliability with OPM is demonstrated for gold and copper wires.
High Temperature Packaging for SiC Power Transistors
Authors: Brinkfeldt K. , Åklint T. , Sandberg C. , Johander P. , Andersson D.
Published: October 2015

Power transistors based on silicon carbide (SiC) are now commercially available. They have a higher efficiency and higher voltage blocking capabilities than conventional silicon devices. The wide-band gap and chemical inertness of SiC makes it suitable to high temperature operation. However, there is a need for new packaging for power transistors that can operate in higher temperatures. We have developed a package based on ceramics and silver for high temperature operation of SiC power transistors. Three types of SiC devices from different manufacturers are packaged and tested in room temperature. Though the devices were still functional after the packaging process, their performance seem to have degraded. This could be a result of the high temperature packaging process and the measurement setup. FEM simulations are also performed to investigate the thermo-mechanical behavior of the package. The target operating temperature of the package is 400 °C. Modeling show stress concentrations at the corners of the device chip and suggests that this stress is decreased if the substrate metallization is changed from copper to silver.
Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)
Authors: Mohammed Ilyas
Published: October 2015

For low power processors, stacking memory on top offers many advantages such as high performance due to memory-processor interface within package, small footprint and standard assembly. Package-on-package (PoP) is preferred method of stacking as it offers two discrete packages that are tested separately and can be sourced independently. However, current PoP interconnect technologies do not efficiently scale to meet the memory bandwidth requirements for new generations of multi-core applications processors. The current interconnect technologies such as stacking with smaller sized solder balls, using solder filled laser drilled vias in the mold cap, or using organic interposers are not practically achieving the high IO requirements, since the aspect ratios of these interconnects are limited. To address the gap in PoP interconnect density, a wire bond based package stacking interconnect technology called Bond Via Array (BVA™) is presented that enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. The main technological challenges are identified and the research results explained. The three main challenges were forming free standing wire-bonds, molding the package while exposing the tips of the wire-bonds, and package stacking. The assembly results showed that the wire tips were within the desired positional accuracy and height, and the packages were stacked without any loss of yield. These results indicate that the BVA interconnect technology is promising for the very high density and fine pitch required for upcoming mobile computing systems.
Thin Substrates Bursting into the Market
Authors: Appelt Bernd K , Su Bruce , Lee Dora , Lee Kidd , Yen Uno
Published: October 2015

The continued drive for miniaturization by mobile applications demands its toll also from packaging. Innovative packages are required to shrink volume and weight of packages. This has led to the development of single layer, coreless and embedded component substrates. The thinnest prepreg based substrate and concomitant package is a single layer substrate termed a-S3 ™ and can be as thin as 90 μ and 400 μ, respectively, with the appropriate mold cap. The manufacturing concept for a-S3 has inspired a new manufacturing concept for thin prepreg based coreless substrates with any number of layers. Layers two through seven have been demonstrated successfully. The practical layer count is limited only by yield and cycle time. The same concept has been extended also to embedding active die as well as passives, a-EASI™. The total package height here is governed by the thickness of the embedded elements. The simplest embedded substrate is a two layer substrate with a MOSFET die. The advantage is a very low profile power package with excellent electrical and thermal performance. The interconnections to the die/passives are formed by plated laser vias as is a common practice. Process flows and concepts will be introduced here. Thin substrates do pose many challenges during substrate manufacturing as well as during assembly. Some of the handling concepts will be elucidated. Sample pictures will be shown to demonstrate successful builds and some reliability data will be presented as well.
ACES characterization of damping in micro-beam resonators
Authors: Parker Jason , Chen Xiuping , Nguyen Vu , Pryputniewicz Ryszard J.
Published: October 2015

This study develops a preliminary model of Q-factor of MEMS resonators by using Analytical, Computational, and Experimental Solutions (ACES) methodology to investigate the effects of various damping mechanisms on the Q-factor of microelectromechanical resonators. Focus was made on the contributions of air damping, thermoelastic damping (TED), and surface damping to the Q-factor. Laser Doppler Vibrometry (LDV) and Michelson Interferometry were used to characterize the damping of tipless atomic force microscopy (AFM) probes through ring down tests. Tests were performed at various levels of vacuum with different beam geometries and coatings. COMSOL was used to model the TED as well as resonance characteristics of the beams and the computational results were compared to analytical and experimental results. It was found that as surface area to volume ratio increases beyond approximately 1 μm−1, surface damping becomes the dominant damping mechanism. Additionally air damping was significant at a vacuum level greater than approximately 0.1 μbar. It was also found that surface damping was much greater with Au-Pd and Al coatings applied. Finally, the dissipation term in the analytical approximation of surface damping was calculated for the above coatings.
High Frequency Signal Propagation in Through Silicon Vias
Authors: Narasimhan Srinidhi Raghavan , Engin A. Ege
Published: October 2015

The 3D IC integration technology and silicon interposers rely on through silicon vias (TSVs) for vertical interconnections. Hence, the medium carrying high frequency signals is lossy silicon (Si). Fundamental understanding of wave propagation through TSVs is essential for successful implementation of 3D IC integration technology as well as for the development of Si interposers at RF/microwave frequencies. The focus of this paper is characterization and modelling of TSVs and Si to explore high speed signal propagation through the lossy Si medium. To understand better the physical significance of the TSV, we will establish a framework for wave propagation through TSVs based on dielectric quasi-TEM, skin effect, and slow-wave modes similar to MIS micro-strip lines. For validation of the existence of these modes, full wave simulation results will be compared with simpler two dimensional transmission line simulators.
Through Silicon Via (TSV) Technology Creates Electro-Optical Interfaces
Authors: Marcoux Phil
Published: October 2015

Silicon is a most versatile material, it is readily etched into a multitude of shapes and it has very highly desirable electrical properties .Through Silicon Via (TSV) technology is emerging as an essential method for allowing circuits on one side of an IC to be accessible from the other. This ability is not only essential for devices requiring covers, such as image sensors and MEMs but for stacking ICs as well. Much has been reported about the interconnecting and stacking of devices, such as, memory-on-memory and memory-on-logic devices.

TSV fabrication is a micro-machining process for silicon. The micro-machining properties of silicon can also be utilized to etch and form features other than vias, such as the ability to etch precise channels which can be used to align and secure the fiber cables in an interposer. The interposer is one of the main elements in short length multimode (MMF) electro-optical transceivers capable of data rates exceeding 10 Gb/sec.
Quality and Reliability of 3D High-Performance Heterogeneous Integration through Die Stacking
Authors: Banijamali Bahareh , Madden Liam , Ramalingam Suresh , Wu Ephrem
Published: October 2015

This paper studies package reliability for the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration) delivering up to 2.78 Tb/s transceiver bandwidth. Each device is packaged on a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. 3D thermal-mechanical simulations are built to analyze package warpage, low-k stresses, microbumps and C4 bumps fatigue as well as BGA ball reliability. Different substrate sizes and designs, lid designs, lid materials and C4 bump underfill materials are investigated in order to optimize package reliability. LTCC ceramic package reduces fatigue in C4 bumps when increasing the risk for BGA balls to fail in thermal stressing. Hence, lid design and C4 bump underfill material are optimized to increase fatigue life for BGA balls. Simulation results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.
Enabling the 2.5D Integration
Authors: Xie John Y. , Shi Hong , Li Yuan , Li Zhe , Rahman Arif , Chandrasekar Karthik , Ratakonda Deepa , Deo Manish , Chanda Kaushik , Hool Vincent , Lee MJ , Vodrahalli Nagesh , Ibbotson Dale , Verma Tarun
Published: October 2015

3D IC is the viable revolutionary technology that will enable system-level integration, miniaturization, optimal power management, increased data bandwidth, and eventually reduced system cost. Like any breakthrough technologies, it faces many challenges. Design methodology, integration technology, manufacturing process and new industrial ecosystem are the areas of focus. This paper will discuss these challenges and Altera's 3D integration development effort.

2.5D is an intermediate path to true 3D IC using silicon interposer and TSV (Through-Si-Via) stacking. The 2.5D stacking configuration offers different form factor, interconnect path, and thermal management options than monolithic packages, which could help to reduce system level power and thermal management pressure. It offers silicon level interconnect density, low inductive path and wide IO application. However, it's power delivery system (PDN) could be the bottleneck for the system to perform at the intended bandwidth and speed. Thus, the whole system, IC-Interposer-Package-PCB, must be considered holistically, and trade off study and compensation mechanism development are needed in such complex system level integration.

There are many different 2.5D integration manufacturing flows currently under development. They can be categorized into two major flow options: Attaching interposer to substrate first, which can be called CoCoS (Chip on Chip on Substrate); or attaching device silicon to interposer first, which is also called CoWoS (Chip on Wafer on Substrate). The major challenges are in the areas of manufacturing process window and yield, thin wafer handling, testability and overall cost of the integration process. ,).

This paper will discuss design consideration, manufacturability analysis, Logic/memory devices and silicon interposer interaction, and thermal management to enable the 2.5D integration. System level characterization and correlation with simulations are performed. The challenge of new supply-customer model and industrial ecosystem development associated with 2.5D integration will also be discussed.
DESIGN AND PROCESS OPTIMIZATION OF THROUGH SILICON VIA INTERPOSER FOR 3D-IC INTEGRATION
Authors: Monajemi Pejman , Newman Michael , Uzoh Cyprian , Woychik Charles , Caskey Terrence
Published: October 2015

The 3D-IC stacking technology provides improved performance, and reduced form factor for applications such as logic-memory integration, image sensors, MEMS, and LED. We present design and fabrication methods to implement Through Silicon Via (TSV) interposer. Cylindrical copper TSV's of 20 μm diameter and 100 μm depth are fabricated in silicon. We present a method for design and process optimization, by recursive enhancement of parameters. Our approach includes selection of materials, proper thicknesses, tolerances, and geometries to achieve the specifications. A discussion on process module optimization and correlation among the whole will be given. We also present an analysis of the relative contribution to cost of each of the modules and identify areas for improvement.
Process challenges in 0-level packaging using 100μm-thin chip capping with TSV
Authors: Pham Nga P. , Cherman Vladimir , Tutunjyan Nina , Teugels Lieve , Tezcan Deniz S. , Tilmans Harrie A.C.
Published: October 2015

This paper presents the process challenges for the fabrication of 0-level packages using chip capping with through silicon via's (TSV) in the capping chip/wafer. The key processing challenges addressed include the fabrication of TSVs on capping wafers that are thinned down to 100μm and further, the Cu/Sn/Cu diffusion soldering to make an intermetallic bond for the chip capping. Integration of the TSVs on the cap wafer enables the vertical interconnection, thus making the package with a small form factor and readiness for 3D integration. The Cu/Sn/Cu bond and seal process provides a hermetic package and at the same time provide electrical connection between the cap and the device wafer. Adequate processing conditions are proposed.