bluuebunny/crossref_metadata_2025 huggingface dataset:
Demystifying statistics in surgical research: Navigating the path to effective treatment evaluation
Authors: Chulasiri M. P. P. U. , Atapattu A. H. A. K. S.
Published: January 2025

Many surgeons often find statistics to be unfamiliar and challenging. In the context of contemporary medicine, understanding statistical concepts is crucial for professional development. This article provides a basic overview of statistics and terminology commonly used in Orthopaedics and Trauma research. Orthopaedic surgery research often involves comparing two groups: one that has undergone a specific procedure and another that hasn't or has had a different procedure. The central question is whether the differences in outcomes are due to the surgical intervention or random chance. For instance, in a study assessing a new knee replacement surgery, there's a need to balance Type 1 and Type 2 errors, which relate to incorrectly concluding effectiveness. A larger sample size increases statistical power but also comes with practical and cost constraints. Choosing the appropriate study design depends on research questions, ethical considerations, resources, and the nature of the intervention. Common designs include Randomized Controlled Trials (RCTs), Prospective Cohort Studies, Retrospective Cohort Studies, Case-Control Studies, Cross-Sectional Studies, Systematic reviews and Meta-Analyses. Understanding the nature of data (qualitative and quantitative) and data distribution, especially Gaussian distribution, is essential in orthopaedic or any type of research. Different types of data require distinct statistical approaches, ensuring the selection of the most suitable analytical techniques. Proper selection of a statistical test starts with formulating a null hypothesis. The p-value is crucial in assessing the strength of evidence against the null hypothesis. A low p-value (typically < 0.05) indicates a significant difference, while a high p-value suggests results could be due to random chance. Various statistical tests, like Chi-Square, Student's T Test, ANOVA, and regression analysis, can be used depending on the research question and data type. Each test is applied to analyze specific aspects of the data, such as relationships between categorical variables, differences in means, or the influence of various factors. In summary, understanding statistics is fundamental in assessing the efficacy of orthopaedic treatments. Researchers must manage errors, choose the right study design, understand the nature of data, and select appropriate statistical tests. This statistical literacy is essential for evidence-based decision-making in orthopaedic practice.
Cauda equina syndrome caused by an acute spinal epidural haematoma following low molecular weight heparin therapy : A case report
Authors: Marage P. M. N. C. , Sathik M. M. M. , Rathnayake R. M. U. C. , Mendis D. C. D. , Wijerathne M. , Perera A. S. B.
Published: January 2025

No abstract available
Abstracts from the SLOA : 14th Annual sessions 2022
Authors: Amarasekara Sumedha S.
Published: January 2025

NA
Package Assembly Design Kits - What are They and How Can They Benefit the Packaging Community — Chiplets and 3D Stacking. An EDA perspective of Heterogenous Integration
Authors: Park John
Published: January 2025

An IC designer wouldn’t dream of starting a new die design without a process design kit (PDK). PDK’s take much of the “can-this-be-built” guess work-out a designing a new die by providing data on materials, libraries and design rules all directly from the semiconductor fab who is going to build the wafer. Over the past few years as packaging technologies evolve, and in many cases start to look more like IC design technologies, the package design community has started talking about the need for package assembly design kits (PADK/ADK). However, there is not a one-to-one mapping of an IC PDK to a package ADK. This presentation outlines and describes what the contents of PADK could and should provide to streamline the design of today’s complex multi-chip(let) packages.
Innovative Package on Package Solution: M-Series Fan-Out (mPoP)
Authors: Kim Byung Cheol
Published: January 2025

Maximizing the advantages of M-Series which are superior reliability and high electrical performance with cost-effective and productive, the stackable package on package (mPoP) structure has been developed for a competitive integration solution of large application processor (AP) with high density routing and memory device based on M-Series technology. Introduced mPoP demonstrates an exceptionally thin profile of less than 0.45mm with a minimum 0.15mm height of the Cu post structure enabling 3D interconnection. mPoP aims to provide Low-band (DRAM stacks on the top of the AP) to high-band (DRAM stacks on the bottom of the AP) structures with a double-sided 3D platform. Furthermore, The mPoP structure is to be realized in the 600mm Panel Level Package(PLP) platform using the same process integration on the Cu stud & Post, panelization, and build-up processes. 600mm PLP will achieve around 5.0 times of package quantity compared with 300mm round. mPoP with Adaptive Patterning technology enables multi-layer RDL with fine line and space together with wider tolerance of die placement variations and allows the industry’s best design rules for scaling. With these, the heterogeneous integrated designs with M-Series will be also explored.

This paper will show how M-Series(TM) fan-out wafer level packaging technology enables a stackable package on package structure extending to 600mm PLP together with heterogeneous multi-chip solutions. We will also present major design considerations and process integration opportunities for future development.
Flexibility of System Technology Co-Optimization (STCO) Demands a Shift-Left Process and Methodology
Authors: Viklund Per
Published: January 2025

The huge costs and lack of flexibility in traditional SoC design have led to the STCO concept (System Technology Co-Optimization) where an SoC type system is fractioned into smaller modules that can be asynchronously designed by dispersed teams and be combined together into a larger highly flexible system using chiplet based package design and/or 3D Packaging.

With the larger flexibility offered, comes several additional challenges in the form of Power integrity, Signal Integrity, Thermal performance, Warp and Mechanical stress. Finding and having to fix such issues late in the design cycle becomes exorbitantly expensive. A ‘left shift’ approach is suggested where very early but due to a preliminary design state, approximate analysis, can be performed and its results drive design decisions as well as corrections to mitigate the risk of failing later verification.

We will examine how such early analysis in complex High-Density Advanced Packaging enables designers to spot potential issues early to avoid building in constructs that later will cause failures and require major re-design.

While verification type analysis of a completed design can offer very accurate results, it’s way too late in the process to provide value. The Shift Left approach means applying multi-physics analysis very early in the design process: already at the prototyping and design planning stage where very little is known about the design. We will show how a minimum of input still provides enough detail to drive a left shift process. This paper focuses on Power and Signal integrity prototyping in STCO High-Density Advanced Packaging (HDAP) but the approach applies equally to thermal, warp and mechanical stress.
Advanced Packaging Dielectric for 5G
Authors: Miskiewicz Pawel , Larbig Greg , Satake Noboru , Pradella Jens , Meyer Frank , Koch Matthias
Published: January 2025

The packaging requirements for high frequency applications and heterogeneous integration have brought well established dielectric materials to their limits. While there is a demand for increased technical performance, mainly low dielectric constant and low dielectric loss, trade-offs in processing conditions and yield are hardly acceptable.

In order to address the technical challenges, Merck KGaA has developed a novel type of dielectric material, looking beyond existing classic polymers like polyimide or polybenzoxazole.

The framework of the development was established around the key requirements from the industry, both on the process and material itself. With 5G applications in mind, low dielectric constant and loss are required. From the process side, compatibility with existing photolithography, low film shrinkage during curing processes and in general reduction of the stress, seen e.g. as warpage, are considered critical.

Our materials demonstrated dielectrics properties which fit very well into 5G devices, with Dk ~ 2.5 and Df <0.005 for the frequency up to 75Ghz. In combination with low water uptake, that ensures compatibility with designed for 5G technology.

When approaching the processing aspects, we looked at broad picture of what can cause the issues, beyond purely numerical specification: Our materials are designed to be primarily curable with UV light at room temperature, with shrinkage during curing <5%, as that process ensures low build-up stress. Photosensitivity also enabled compatibility with photolithography, showing L/S feature below 5µm and still fully reworkable with standard, non-NMP, organic solvents.

Warpage issue has been addressed not only by UV cure at room temperature but also by distinctive behavior of CTE across the temperature range, where CTE values are similar at temperatures below and above Tg. That special feature, in combination with Young Modulus <2GPa and elongation >20% enables significant stress reduction during processing and subsequent use of the packaged device.

Our new materials offer a combination of advanced performance and processing advantages leading to increased throughput and yield. Thus, offering a competitive advantage for tomorrow’s packaging designs.
Emerging Process and Assembly Challenges in Electronics Manufacturing
Authors: Farris Glenn
Published: January 2025

Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions.

These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement.

This presentation will look at the challenges and potential approaches for efficient and cost effective solutions.
Power Packaging Trends in Emerging 48V Ecosystem
Authors: Sattu Ajay
Published: January 2025

Recently, the semiconductor industry has seen significant technology and product development in application areas such as automotive, datacom, telecom and automation. System demands such as higher power density, higher switching efficiency and smaller form factors are becoming more important to reduce effective carbon footprint. Consequently, a new 48V system design has gained lot of attention. For example, the applicability of the 48V design/architecture was seen primarily in automotive mild hybrid cars and data center power delivery. In the world of automotive, degree of electrification, comfort features and advanced driver assistance systems (ADAS) in a car, result in need for higher total power budget. However, existing vehicle power tree is powered directly from a 12V lead acid battery to the mechanical auxiliary loads (typically <5-7 kW) such as water and oil pumps, climate compressor, active roll control, headlights and taillights. This, along with stricter emission norms from Corporate Average Fuel Economy (CAFE) standards and power hungry ADAS systems make it challenging to improve efficiency.

Data centers offer services such as data storage, processing, networking and distribution. To manage these services, operators need power in the order of several 100’s of MW. As much as 40% of the operating costs of the data center comes from the energy needed to power and cool racks of servers. Amid the growing service demand, increasing efficiency and power density has become a priority for data center operators. On average, approximately 30-35% of power is wasted in the conversion from the AC grid to the microprocessors of an individual server. However, to realize system benefits, packaging technologies must not limit achievable electrical and thermal benefits. Historically, power device packaging has evolved from through hole packages such as TO247 and TO220 with long leads to surface mount components with shorter leads such as D2PAK, DPAK and SO8. Further, leaded packages have been replaced with lead-less surface mount options such as TOLL and PQFN, offering higher levels of integration. Package innovation has always been driven to improve parasitic resistances, inductances, thermal resistances and reliability.

This presentation will explore some of the recent trends and new ideas in packaging technologies and their potential for addressing system performance requirements.
MAXQFP: NXP New Package Platform for Automotive Application
Authors: Lee Chu-Chung Stephen , Pang XS , Yao JZ , Tran Tu-Anh , Mawer Andrew
Published: January 2025

MAXQFP, a newly developed package platform by NXP semiconductor Inc, has been certified meeting AEC (Automotive Electronic Council) Grade 1 application and targeted on HVM (high volume manufacturing) by 2023. MAXQFP has combined both gull-wing and J- leads in an over-mold package body similar to QFP/LQFP. NXP has offered both 172-lead (16x16 mm body size) and 100-lead (10x10 mm body size) MAXQFP’s for automotive industry. For high power application, MAXQFP_EP (exposed pad) is also available by creating heat pipe through PCB board with exposed die flag which is similar to LQFP_EP packages. As compare to JEDEC compliance LQFP/QFP packages, MAXQFP has offered higher pin counts at the similar body size. For example, 172 MAXQFP is in 16x16 mm body size while 176 LQFP is in 24x24 mm body size. The 56% body size decrease offered by 172 MAXQFP over 176 LQFP can result in significant PCB board area reduction for NXP automotive end customers. Due to the higher density of lead per mm of body size, MAXQFP indeed has slightly better thermal performance over LQFP (i.e. Theda JA and JB). However, the smaller distance between adjacent leads of MAXQFP as compare to LQFP has raised reliability concerns and assembly production challenges. This paper is going to show NXP’s innovative methods and data to resolve these challenges. For example, Sn whisker and Sn migration both are concerns to MAXQFP because of smaller distance between adjacent leads. The board-level solder joint reliability (SJR) is collected to prove it is AEC G1 compliant. Visual inspection concern on J-leads of MAXQFP will be addressed. Standard AEC G1 component level reliability stresses defined at AEC Q100 which are TC (temperature cycling), HTSL (high temperature storage life), HAST (humidity accelerated stress test)/ THB (temperature humidity biased), and uHAST (un-biased HAST) tests are conducted on MAXQFP using functional die made of 7-metal-layer-C40 nm wafer nodes with ultra-low k dielectrics as BEOL (backend of line) structures and will be shown in the paper. Since Cu wires were used, AEC Q006 data are also collected. Assembly challenges will be briefly described, for example, trim & form processes and molding process concerns. MAXQFP has been patented by NXP semiconductor Inc and been released at USPTO (US patent trad-mark office). The future works and potential MAXQFP application will also be disclosed in the paper.
SiP in Advanced Automotive Packaging
Authors: Islam Nokibul
Published: January 2025

The automotive market for the IC (integrated circuit) packaging industry has grown significantly over the last 8 to 10 years due to its increasing need for automation, higher performance, and the more stringent reliability requirements in the vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent at a reasonable cost. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced and more reliable packages for next generation automotive market requirements.

Automotive IC’s have traditionally been assembled in mature wirebond type packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards very high performance flip chip, fan out wafer level and very recently system in package (SiP) solutions for automotive ADAS, infotainment, GPS, camera, radar, driverless car and many more applications. SiP packages or modules are getting more momentum for complex functionality for high computing automotive such as L3 or L4 automotive. In this study a comprehensive view of the changing packaging landscape from standard flip chip interconnect to highly complex SiP or module packages and the corresponding reliability grade level requirements (G2, G1) will be discussed. Special design, process and BOM (bill of materials) are the most important parameters to consider for high reliability, complex SiPs for automotive applications. In this study, detailed design parameters, step-by-step package development, along with the optimal BOM are evaluated. Both package and board level data were analyzed to qualify automotive SiP for G2 and G1 conditions. Relative packaging cost vs performance for traditional packages to advanced SiPs are evaluated in the study.
2-High Stacked Heterogeneous System-in-Package (HSIP) Modules Using Solder Assembly
Authors: Woychik Charles , Mundella Robert , Black Larry , Borski Justin , Nead Robert
Published: January 2025

A stitched module with embedded semiconductor die has been fabricated using a Heterogeneous System-in-Package (HSIP) technology in order to create a highly dense integrated Multi-Chip Module (MCM) package solution for reliability testing. This technology is based on Fan-out Wafer-level Packaging (FOWLP) technology which consists of a molded core wafer having embedded devices and Through Mold Vias (TMVs), along with buildup circuitry layers on both sides of the molded core wafer. On both sides of the outer layers are Ball Grid Array (BGA) pads which allow these modules to be stacked using conventional solder attach methods. After the buildup layers are produced on the molded wafer, the individual modules are diced out of the wafer. The completed individual HSIP modules are relatively thin packages, which average about 350um. In this work, solder balls are used to stack the HSIP modules. A clam shell test socket has been built to test the initial stack to ensure all the stitched nets are connected and read their calculated initial resistance values. This 2-High stacked HSIP technology can produce a robust 3D package design that can meet aggressive JEDEC testing requirements for military, aerospace and commercial applications, in order to achieve the lowest power consumption, weight and size. A discussion of our 2-High stacked HSIP technology will be presented along with supporting reliability data.
Effect of Silicon BEOL Presence on Solder Fatigue Life During Board-Level Thermal Cycling of WLCSP
Authors: Hadizadeh Rameen , Pang Yaoyu , Patel Anuj
Published: January 2025

Traditional electronics packaging qualification includes a board-level reliability (BLR) component, which is intended to simulate the customer system-level environment and characterize package-to-PCB interconnect integrity. BLR is a particularly critical stage of qualification for wafer-level chip-scale packaging (WLCSP) due to the sensitivity of interconnect performance to package size, and the limitations of ubiquitous materials used in WLCSP manufacturing. In the context of mobile electronics, perhaps the most challenging BLR stress to accommodate is thermal cycling (TC) during which the large mismatch in thermal expansion between the package and PCB causes an accumulation of plastic deformation within the interconnects (in most cases a lead-free solder alloy) over an extended period of time, ultimately resulting in electromechanical failure due to fatigue.

Regardless of package type, a customized daisy chain test vehicle is often fabricated to perform in-situ monitoring of the package-to-PCB interconnects during BLR-TC. The complexity of this daisy chain structure for WLCSP is often debated since it is not clear whether the redistribution layer (RDL) design or silicon back-end-of-line (BEOL) metal layers have any appreciable effect on the characterization of solder fatigue life. It is possible to electrically integrate the Si BEOL into the daisy chain path, albeit not without a substantial increase in foundry mask and wafer cost, and a much more involved design effort to achieve connectivity through all metal levels. Were it possible to simplify the daisy chain structure to only the packaging layers - polymer re-passivation (PM1), RDL, second polymer re-passivation (PM2), under-bump metal (UBM) and solder ball - this would reduce design complexity and the cost associated with recurring product qualifications.

This study aims to compare BLR-TC solder fatigue life between three daisy chain structures: packaging layers on full Si BEOL, packaging layers on partial Si BEOL, and packaging layers on dummy Si. The 5.022mm x 5.022mm x 0.5mm package size and 0.4mm ball grid array (BGA) pitch is consistent among all daisy chain types. Packaging layer stackup is also kept consistent at 9um PM1, 5um Cu RDL, 9um PM2, 8.5um Cu UBM and pre-formed SAC405 solder spheres. The influence of RDL layout is also captured within this comparison. In addition to physical characterization of these daisy chain structures, a well-correlated finite element model (FEM) was used to predict the solder fatigue life for each of the three cases to determine if an analytical approach is suitable for this type of structural comparison. Finally, cross-sectional failure analysis was completed to ensure that the only mode of failure for these daisy chain structures was bulk solder fatigue, contributing to higher confidence in the conclusion of this work.
Cost Analysis of Lithography Options for Panel-Level Fan-Out Packaging
Authors: Lujan Amy P.
Published: January 2025

Panel-based fan-out packaging is a continuing topic of interest. The cost reduction associated with processing more die at one time by using a large panel instead of a smaller wafer is attractive, despite the challenges associated with the switch to panels. Those challenges include a lack of alignment within the industry on which panel size to pursue, new material and equipment requirements to support panels, and the fact that a panel may produce so many chips per panel that true high volume and high utilization may never be achieved.

Once these challenges are addressed, there are still questions to be answered about the process itself. There are a number of options to consider for the lithographic portion of the panel fan-out process. This paper will explore the following four options for the formation of the redistribution layer (RDL) on a panel: stepper, aligner, laser direct imaging, and laser ablation.

The paper will introduce the basic process flows for each technology, and the focus of the comparison will be on the costs associated with each lithographic option. Equipment cost, processing throughput, yield, and material costs (dielectric, photoresist, masks, etc.) will be considered. Multiple panel and package sizes will be analyzed. Key variables will be tested to evaluate the sensitivity of each assumption.

Activity based cost modeling will be used for this analysis. This is a bottom-up, detailed approach to cost that accounts for the many cost components associated with every step of the process flow, such as material, labor, and capital depreciation. The goal of this analysis is not to highlight one lithographic option as the best or worst choice, but to understand the cost drivers associated with all four potential choices.
Enabling the Transition to Heterogeneous Integration
Authors: Black Bryan
Published: January 2025

Enabling the Transition to Heterogeneous Integration.

• integrate many disparate dies from many different vendors into a single substrate • new packaging technologies and on-die IP innovations are required • endless configurations mean endless complexity but needs to be straight forward for the design house
The Future is Heterogeneous Integration IMAPS Global Business Council
Authors: Chen William
Published: January 2025

Agenda:

• news of the semiconductor world • times are changing • digital transformation • heterogeneous integration roadmap • innovations are bubbling up everywhere • future is heterogeneous integration
Increasing Role of Glass in the Semiconductor Applications: Market, Technology Trends, Supply Chain Evolution and Challenges
Authors: Kumar Santosh
Published: January 2025

Agenda:

• glass substrates for semiconductor devices • application segmentation • material supplier and manufacturing supply chain • focus on TGV interposer • glass as package substrate material
Challenges for High Frequency Measurement of Low Loss Dielectric Material
Authors: Ray Urmi
Published: January 2025

The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors.

The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging.

This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.
Recent Developments of Resonator Measurements for Emerging Materials and Technologies
Authors: Olszewska-Placha M. , Celuch M.
Published: January 2025

Resonator methods for material characterization:

• What are resonant methods and why we use them • What resonant methods we know • How these resonant methods work • Resonant methods for broadband material characterization
High Frequency Measurements Using Wafer Level Techniques
Authors: Orloff Nate
Published: January 2025

AI and Automation will change the economy.

Low latency, high data communications are key.

mmWaves aren’t the only new thing in 5G.
Ag-Diamond Heatspreader for Power Devices
Authors: Okubo Takara
Published: January 2025

As electric devices are developed for high-powered, high-speed and high capacity at a rapid pace, their thermal design are considered more important. With thermal conductivity (TC) of about 400 W / mK coupled with low-cost, Cu is widely used as a packaging material for electronic devices. However, its coefficient of thermal expansion (CTE) is 17 ppm / K, which is much different from that of Si, GaAs, and SiC devices, pose a risk of lowered reliability of packaged devices, such as cracks at solder joints or damage to semiconductor devices. Therefore, a packaging material for a high-performance device requires not only high TC but also a CTE close to that of the semiconductor chip and the packaging materials. To achieve this goal, we have developed a Ag-Diamond composite material. This new material has TC of 600 W / mK or more, and CTE 9.0 ppm / K (R.T. to 400 deg.C). It can also stand 1000 heat-cycles at -65 to 150 C, and maintain TC over 600 W / mK with minimal TC degradation of 4%. Also, the material is found to maintain TC over 600 W / mK after two cycles of thermal stresses at 800 deg.C, a temperature for brazing process for ceramic packages. Lastly, our simulation using Ag-Diamond composite as a heatspreader for a GaN (RF power) device has demonstrated that the material yields less thermal stress, >=-8 Mpa, compared with a GaN device directly bonded on copper base plate, and also lower Tj on GaN device, > -26 C, vs. GaN device directly bonded on Cu-Mo composite.
Thiol-based, Thermally-Conductive Adhesives for High Power Electronics
Authors: Lund Benjamin , Barrios Carlos , Hosseini Mahmoud , Han Xun , Aliev Ali , Baughman Ray , Voit Walter
Published: January 2025

High power electronics, such as those enabling the next generation of so-called ‘5G’ devices, evolve significant amounts of heat and require improved mechanisms to dissipate that heat. As an alternative to sintered copper-based nanomaterial composites, recent work in silver nanoparticle pastes has shown great promise to provide high thermal conductivities (278.5 W/mK)[1] approaching that of neat silver (429 W/mK); however, pastes, in general, are not functional as adhesives for chip attachment under repeated thermal cycling without requisite mechanical reinforcement and interfacial stress mitigation. Work at UT Dallas, and Adaptive3D, on thermally conductive systems explores thiol-based resins composites as adhesives with excellent adhesion to metal substrates, interfaces and fillers, with tunable electrical and thermal conductivities. Voit, Lund, et al. have demonstrated thiol-ene polymer systems for flexible electronics and semiconductor packaging with excellent adhesion to metal substrates (due to the thiol-metal interaction) and excellent survivability to thermal cycling despite significant interfacial coefficient of thermal expansion (CTE) mismatch. This advantage is due to the thermoset nature of the polymer matrix, the ability to accommodate strains at the interface between CTE-mismatched materials and the lack of stress concentrators that evolve during polymerization due to the thiol-mediated chain transfer mechanisms during curing [2]. We demonstrate the ability to deposit plasma-enhanced chemical vapor deposited Silicon Nitride (CTE <3) on thiol-based polymers (CTE ~70) and survive thermal cycling to 270°C without interfacial delamination. The same polymerization phenomena that enable this behavior are conducive for loading organic and inorganic filler into thiol-based systems to optimize electrical and thermal conductivity in die attach adhesives, molding compounds and unique semiconductor packaging materials. Aliev, Baughman, et al. have previously utilized multiwalled carbon nanotubes and graphene-based structures to tune thermal conductivities and properties of organic-inorganic composites [3]. Herein we will present a multi-materials approach to enhance both thermal and electrical conductivity through control of phononic resonances in semiconductor packaging adhesives and discuss the impacts of modifying metallic (silver) and carbonaceous (nanotube and graphene) fillers imbedded within a thiol-based polymer matrix. We present early work on the effects of thiol-mediated chain transfer mechanisms during polymerization on the percolation threshold of fillers and resulting electrical and thermal conductivity.
Modernization of Metrology for Metallization Solutions with ICP - A Quality Control Requirement
Authors: Okagbare Paul , MacEwan Michael , Shalyt Eugene
Published: January 2025

The semiconductor industry is highly dynamic and innovative. New semiconductor devices are introduced every year with improved performance and a smaller footprint. Efficient process control is essential for high yield operation. The fast dynamics of the semiconductor industry has to be matched with the innovation of metrology. Old methods do not meet today’s challenges.

This talk describes the benefits of inductively coupled plasma (ICP) online analysis for process solutions for advanced packaging, and its ability to detect metal impurity concentrations. Ten years ago, ICP technology was very expensive, bulky, and unreliable. Over the years, it has matured and has become a common analytical tool in the lab. The next step is to bring this solution to point of use in the cleanroom for an automatic unattended operation.

A unique feature of the ICP method is its ability to measure multiple elements at the same time. It also does not use an open flame which enables safe operation in compliance with semiconductor standards. The table below summarizes some of the typical applications:

Chemistry Component Analyzable by ICP

Acid Copper Electrodeposition Copper, Acid, Chloride, TOC, Trace Metals (Ni, Sn, Au), Accelerator Turnover

Nickel Electrodeposition Nickel, Boric, Chloride/Bromide, TOC, Trace metals (Cu, Sn, Au)

Sn, SnAg Electrodeposition Sn/Sn(IV), Ag/Bound Ag; Trace metals (Cu, Ni, Au)

Sulfite Au Electrodeposition Au, Tl/As, SO4, Trace metals (Cu, Sn, Ni)

Electroless Solutions Main components, stabilizers, Pd catalyst,

Boron/Phosphorous reducers

The presentation will describe challenges and solutions to enable effective online monitoring of different chemistry types with a single analyzer. Case studies will be used to demonstrate the effectiveness of metals removal and breakdown products with ICP metrology to achieve higher process control.
Investigation of Low Temperature Bonding Process based on Cu/Ni/In Solid Liquid Interdiffusion
Authors: Shehzad Adil , Bickel Steffen , Panchenko Iuliana , Wolf Jürgen M. , Steller Wolfram , Wolfram Benedikt , Myndyk Maksym
Published: January 2025

Solid-Liquid-Interdiffusion (SLID) bonding is an approach for the interconnect formation which offers the joint possibility for different metal systems at low temperatures. In this study Cu/Ni/In system was utilized which includes Indium as one of the promising candidate for low temperature applications. In exhibits lower melting point (156 °C) in comparison to commonly used Sn and SnAg solders which are being used in 2.5/3D integration for fine pitch interconnects. Cu/In microbumps were investigated for the low temperature assembly of sensible devices. However, the processing of Cu/In microbumps features a challenge due to the very fast formation of the CuIn2 room temperature intermetallic phase (IMC). The thin layers of In can be completely trans-formed into this IMC after one or two weeks of room temperature storage. This is critical for the following assembly process which requires at least thin layer of pure In for good bonding quality.

Hence to overcome this challenge, we propose the introduction of a Ni layer between Cu and In in order to slow down the IMC formation at the interface between Cu and In. In this work we investigated die to die bonding using Fineplacer Matrix bonding tool with top dies containing the Cu/Ni/In bumps (Ø 25µm) and bottom dies with Cu bumps (Ø 35µm). Bonding time, bonding pressure and bonding temperature were varied basically to investigate the influence of the bonding process on interconnect quality. Bonding time was varied between 10 sec to 2 min. The bonding temperature was varied between ~170°C to ~162°C.

The samples were investigated through shear tests in order to identify the shear strength and shear mode. Afterwards the cross-sections and scanning electron microscopy (SEM) were carried out for the investigation of the bonding interface. The results have demonstrated that longer bonding cycles in terms of bonding time and constant applied temperature and pressure are more prone to structural defects and additional voiding, especially at Ni/In interface. Almost in all of the assembled dies, shear mode was detected at Ni/In interface. We assume that very fast formation of the Cu11In9 IMC from the bottom side and very slow formation of the NiIn IMC from the top side cause voiding at the interface. In order to reduce the number of voids and improve the bonding quality we propose different approaches in this study.
2D Materials for BEOL Applications
Authors: Chen Zhihong
Published: January 2025

Abstract not provided for 2D Materials for BEOL Applications
A New Dual-Band Resonator in Measuring Dielectric Constant at 5G Frequency Band and Yagi Antenna Implemented
Authors: Lai Chia-Chu , Lin Ho-Chuan , Shih Teny , Lai David , Wang Yu-Po
Published: January 2025

Dielectric constant (Dk) is an important factor for engineers to design circuits previously by simulation tool. In this paper, we design a dual-band resonator to extract the dielectric constant of material at 5G frequency band – 28GHz and 39GHz, which provide designer more precise factor and simulation result with measurement. The resonator is designed in 6mm x 3.5mm x 0.15mm (L x W x H) and the result shows -1.7% frequency shifted at 28GHz and -3.1% at 39GHz between measurement and design. Then it can get the realistic Dk by matching the resonator frequency of measurement with actual size and Dk adjustment. Finally, we design a 1x4 Yagi-antenna array at 28GHz frequency band with the same Dk enactment. It shows a good correlation and the result achieves a bandwidth of 10.2GHz for -10 dB return loss and gain of 13.3 dBi.
Integration Technologies Transforming the World
Authors: Chang Yin , Rice Rich
Published: January 2025

Emergence of Die Partitioning and Chiplets

•

Drivers and benefits:

•

Moore’s law benefits are slowing at SOC level

•

Traditional SOC cost barriers-NPI costs inflating

•

SOC scaling limitations for integration of analog, logic and memory circuits

•

Economic leverage of trailing nodes for analog and mature devices

•

Mix & match systems –time to market, system flexibility

•

Performance and cost optimization for individual chips

•

Near Monolithic & More Than Monolithic Integration better performance than SoC

•

Key Integration Technologies

•

MCM, 2.5D, 3D, Fan-out, Bridge
Samsung Foundry’s 3D Package Solution based on Cadence Design Flow
Authors: Min Max , Moon Sungwook
Published: January 2025

Samsung Foundry provides a package solution for 3D stacked IC, that is configured with a single logic die and multiple SRAM dies to support large bandwidth and low latency for HPC/AI applications. Entire design flow for a 3D stacked IC from RTL to GDS/PKG was implemented by using seamless Cadence tool line-up such as OrbitIO, Innovus, Voltus, Sigrity/Clarity, and SiP. The established 3D IC design flow will be further enhanced by incorporating the design flexibility of 3D stack structure in low-profile HPC/AI products considering thermal and mechanical stress.
Heterogeneous System-in-Package (HSIP) Using Fan-Out Wafer-Level Packaging (FOWLP)
Authors: Woychik Charles , Borski Justin , Nead Robert
Published: January 2025

An interposer with embedded semiconductor die and passive devices has been fabricated using a Heterogeneous System-in-Package (HSIP) technology in order to create a highly dense integrated multi-chip module (MCM) package solution. This technology is based on Fan-out Wafer-level Packaging (FOWLP) technology which consists of a molded core wafer having embedded devices, through mold vias (TMVs), and passive devices, along with buildup circuitry layers on both sides of the molded core wafer. This HSIP technology is capable of integrating multiple die and passives to achieve maximum device packing, which are molded using an epoxy based silica filled molding compound to create a reconstituted wafer. In order to maintain a flat module, it is necessary to balance the amount of Cu in both the front and back layers to achieve a neutrality of the module bow during thermal excursions. To create the buildup layers, a first dielectric material is deposited over the reconstituted wafer, vias are created and then the Cu circuitry is formed. This sequential process is repeated until the required number of layers is formed. This same process is repeated on the backside of the wafer. After the buildup layers are produced on the molded wafer, the individual modules are diced out of the wafer. On both sides of the outer layers are ball grid array (BGA) pads which allow these modules to be stacked using conventional solder attach methods. The completed individual HSIP modules are relatively thin packages, which average about 350um. This HSIP technology can produce a robust package design that can meet aggressive JEDEC testing requirements for military, aerospace and commercial applications, in order to achieve the lowest power consumption, weight and size. A discussion of our HSIP technology will be presented along with supporting reliability data.
PCB Embedding of Magnetic Material for Inductor-Based Applications
Authors: Weis Gerald
Published: January 2025

As PCB embedding is an emerging

technology, this can be used to place

pre-cutted inlays of various materials

into a PCB build-up. A combination of

the inlay and a well-designed copper

structure forms an inductor, a transformer or a current sensing

device.

Embedding of the magnetic material is

achieved by a standard embedding

process. The process starts with the

cavity-forming in the PCB core. After

that, a pick and place process assemble

the pre-cutted inlays into the openings. To hold them in place, a

soft-lamination cycle fills up the cavity with resign material. Subsequent processes are standard for PCB

manufacturing.

The end application of the PCB or module is copper design dependent. As

mentioned, an inductor would only need one spiral winding around the magnetic material core. To achieve a stable characteristic of the inductance over current, it could be necessary to add

“air”-gaps into a closed magnetic core.

Depending on the application and the

complexity, a couple of core openings

is possible. As alternative, a material

with a distributed air-gap can help to

further optimize the PCB based inductor.

Such kind of process could also help to

form a PCB-based transformer to supply

galvanically isolated circuit parts.

For such applications, two independent

windings need to be formed on the core.

Depending on the maximum isolation

voltage, a dedicated distance is required.

The advantage of PCB embedding is the

cost-effective process of the combination of different materials and electrically conductive structure. In the extended abstract we will show how an inductor and a transformer can be

formed. Additionally, we show a cost

calculation example to evaluate such

process for future applications.
Embedded Trace and RDL Copper Plating Process for Panel Level Packaging Applications
Authors: Feng Kesheng , Kim Leslie , Lee Johnny , Dharmarathna Saminda , Bowerman William , Watkowski Jim
Published: January 2025

Advanced packaging suppliers are faced

with two primary challenges in

introducing Fan-out Panel Level Packaging (FOPLP) to mainstream use.

These challenges are manufacturing

process cost reduction and performance

improvement of the chemical processes

utilized in creating the fine line

dimensions needed for FOPLP. As

package cost reductions from FOPLP are still difficult to obtain comparing to

incumbent processes, penetration of

FOPLP into widespread market adoption is still low in 2019. On the

performance improvement front, a key problem to be solved is to obtain both high resolution and height uniformity

within the fine line and RDL copper

plating processes. This is especially

true when the design includes ground

planes, fine lines, and microvias all to be plated simultaneously with what is called 2-in-1 RDL plating. Plating uniformity and trace/via top shape and

coplanarity are critical to quality. A

non-planar surface could result in

signal transmission loss and induce

stress points to the wafer connection.

Therefore, copper plating solutions

providing uniform, planar profile

without any special post treatment are

highly desirable features of fine line

and RDL plating processes. There are

currently three main technologies used

in fine line formation for panel level

packaging applications: Embedded Trace

Processing, Semi Additive Processing

(SAP) and modified Semi Additive

Processing (mSAP). Two plating

processes, embedded trace plating for

the M1 layer and 2-in-1 RDL pattern

plating by mSAP methodology for the M2 and M3 layers are discussed in this

paper. Embedded trace plating involves

photo imaging the pattern on a copper

carrier, and then plating with an acid

copper electrolyte to finish the first

layer. The second layer and third

layer are then formed by mSAP, utilizing 2-in-1 RDL plating to

simultaneously fill vias and plate

fine lines. Utilizing a vertical continuous plating tool, the

electrolyte for embedded trace plating can achieve a resolution of 5/5 µm L/S with excellent uniformity between fine line and large pad areas, and great

uniformity across the panel. When this

electrolyte was adjusted with VMS

(virgin make-up solution) by varying

copper and acid concentration, the

solution could also be used for the 2-

in-1 RDL process. For 2-in-1 RDL designs with larger size vias, another electrolyte is discussed which filled

these vias with shallow dimple. This

electrolyte can also fill laser drilled through vias with excellent

fine line trace profile. The physical

properties from these two deposits were evaluated. Both deposits offered

elongation above 18% and tensile strength above 36,000 PSI which are the required IPC Class III criteria for electroplated copper. The plated copper also had low internal stress.

FIB and XRD studies indicated the

deposits had equiaxial grain structure

with preferred [111] planes.
Improving WID & WIW Non-Uniformity in ECD Applications
Authors: Sharbono Charles , Hsieh I -Wen
Published: January 2025

As chip packaging technology advances,

chip layout is posing increasingly challenging structures and pattern

density to be metallized uniformly. In the field of electrodeposition, a

mask or a photoresist is often used to

define the pattern of metal lines or contacts. But the extremely varying

pattern density between sparsely

patterned regions and densely patterned regions causes

correspondingly varying local current

density and concentration differences, which affect deposition thickness uniformity within a die (WID) or

coplanarity and WIW (within in wafer).

In order to improve thickness uniformity (WID and WIW), common approaches are to either reduce the applied current density or deposition

rate (also reduces tool throughput) or

select a plating bath with high throwing power. This presentation

describes a different approach by using deplating or reverse plating to achieve increased thickness uniformity for both WID and WIW.

The approach follows the electroplating process with a

deplating process in a bath with low

throwing power in a separate processing chamber. The low throwing power exaggerates the local current density in the sparse regions versus

that in the dense regions. Throwing

power can be defined as the ability of a plating bath to produce deposits of

uniform thickness on cathodes having

macroscopic irregularities. The higher the throwing power, the more uniform the resulting deposit. While in the

case of electroplating, low throwing power is highly undesirable, it would be desirable in the case of deplating.

In the case of deplating, the low

throwing power enables preferential

thickness removal (removal selectivity) in the sparse region

(high feature height) vs the dense region (low feature height), leading to an overall reduction to height

delta between sparse and dense regions. This process can be

applicable to all applications from Cu

pillar, microbumping to RDL and pads.

Depending on pattern and layout, WID

uniformity can be improved by as much

as 80% and WIW uniformity up to 30%.

As a result, not only it can dramatically remedy one customer’s most pressing concerns, it can also potentially enable higher plating

rates. Worse WID and WIW uniformity

used to be coupled with higher plating

rate. This approach allows WID and WIW uniformity to be corrected in a more independent and effective method.