(Invited) Combining SiGe BiCMOS and InP Processing in an on-top of Chip Integration Approach
Authors: Lisker Marco , Trusch Andreas , Krüger Andreas , Fraschke Mirko , Kulse Philipp , Marschmeyer Steffen , Schmidt Jens , Meliani Chafik , Tillack Bernd , Weimann Nils , Kraemer Tomas , Ostermay Ina , Krüger Olaf , Jensen Thomas , Al-Sawaf Thualfiqar , Krozer Viktor , Heinrich Wolfgang 
Published: February 2020

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs.

Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b).

To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2).

Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes.

References

[1] T. Kraemer, M. Rudolph, F.J. Schmueckle, J. Wuerfl, and G. Traenkle, IEEE Transactions on Electron Devices, 56 (9), (2009), pp. 1897 – 1903

[2] H. Rücker, B. Heinemann, and A. Fox, Proc. Silicon Monolithic Integrated Circuits on RF Systems (SiRF 2012), 133 (2012)

[3] T. Jensen, T. Al-Sawaf, M. Lisker, S. Glisic, M. Elkhouly, T. Kraemer, I. Ostermay, C. Meliani, B. Tillack, V. Krozer, and W. Heinrich, EuMIC (2013), pp. 244-247