Single-Wafer Chemical Mechanical Planarization (CMP) on 150mm Silicon Carbide Substrate with Superior Surface Finish and Removal Efficiency
Authors: Yu Dongshan 
Published: July 2021

Silicon carbide (SiC) has excellent performances such as superior thermal conductivity, good carrier mobility and high chemical stability in comparison with those of silicon (Si). SiC has a great potential in the area of the next generation power controlling devices, high performance communication, and LED lighting. Chemical mechanical polishing (CMP) techniques combine mechanical polishing with a chemical etching action and can achieve truly defect-free surface with wafer flatness control capability, which is important for obtaining good epitaxial layer. However, Silicon carbide (SiC) presents many challenges for wafer surface treatment because of its high hardness and remarkable chemical inertness. Currently, low material removal rate (MRR) of CMP technique is a fundamental limit, it extends the CMP process time and effects the yield in mass production of substrate.

In this study, we proposed an ultra-high MRR CMP process on 150mm n-doped, 4° off-axis, single crystal, 4H-SiC wafers. The process was developed at Applied Materials Mirra Durum® CMP configured with the membrane polishing head using an acidic slurry with strong potassium permanganate oxidant and thermoplastic polyurethane (TPU) pad. The effect of polishing process parameters (speed of the head and platen rotating, head sweeping distance and applied pressure) on MRR are analyzed in JMP® (SAS institute) while a design of experiments (DOE) is employed. The chemical composition of slurry, which is also critical to MRR, has also been evaluated via DOE. Potassium permanganate with certain concentration has been selected as oxidant and aluminum oxide micron particle has been used as abrasive. We have also conduct studies on the SiC wafer flatness control, which is proven to depend on structural design of polishing head. The head has been optimized to offer a flexible zone pressure control, therefore the impact on wafer flatness during the CMP process has also been minimized. In addition, accepted industry measurements of surface roughness, surface defect and wafer deformation are also taken into consideration.

The successful development of CMP process provided an optimized MRR result, the reported MRR is 22.5 um/hr from C face and 6.4um/hr from Si face. The MRR have achieved highest level within literature and industry. The MRR results are analyzed by least–square modelling, which reveals that Prob >|t| is less than 0.05 for platen rotation speed and membrane pressure. Prediction profile demonstrates that MRR typically follows Preston’s law, which is a linear function of the platen speed and the pneumatic pressure applied to substrate. MRR is highly stable throughout a 2000-wafer repeat run with wafer-to-wafer uniformity of 2.4-3.7%.

Scratch-free wafer surfaces are observed for the ultra-smooth wafers via atomic force microscopy (AFM) and defect inspection (Candela) tool. Roughness on Si face has been reduced from 2.0-2.5nm to less than 0.15nm with acceptable repeatability. Surface defects including scratches, pits have been greatly reduced. Total scratch length of 10mm has been achieved. Total thickness variation (TTV) is measured to characterize wafer flatness by Tropel tool, which indicates that the total amount of removed thickness on faces has a profound influence on TTV. With focused process control, post-CMP TTV can be improved by 0.6 ~2.1 um from pre-CMP TTV.