bluuebunny/crossref_metadata_2025 huggingface dataset:
ФОРМИРОВАНИЕ ПРОБЛЕМЫ СТАРЕНИЯ НАСЕЛЕНИЯ в республике Дагестан
Authors: Гимбатов Шамиль Магомедович
Published: December 2020

Целью исследования является определения закономерности социально-демографической динамики и изменений структуры населения в Северо-Кавказском федеральном округе (СКФО) России. Методы исследования. Представленное исследование дает возможность оценить развитие социально-демографической ситуации в Северо-Кавказском федеральном округе России более чем десятилетний период. В контексте темы данной статьи изменения в демографической структуре анализируются с помощью коэффициента пенсионной нагрузки. Результаты. В регионе намечается новый тренд на сокращение доли молодежи в регионе. Данный процесс не так явно выражен, как и в целом по стране, но темпы изменения структуры населения свидетельствуют сдвигах в структуре в пользу увеличения доли пожилого населения. Процесс старения населения, который наблюдается практических во всех регионах страны, вполне может стать объективной реальностью и в кавказском регионе.
ЦИФРОВЫЕ ИНСТРУМЕНТЫ ОПОВЕЩЕНИЯ ОБ ОПАСНОЙ ПРОДУКЦИИ НА РЫНКАХ ЕАЭС И ЕС
Authors: Зайченко Елена Анатольевна , Петренко Елена Валерьевна
Published: December 2020

Цель работы. В статье рассматривается отечественная и зарубежная практика использования цифровых ресурсов для оповещения об опасной продукции. Методы проведения работы. Проанализированы системы оповещения о опасной продукции на рынках ЕАЭС и ЕС, выявлены их преимущества и недостатки. Ресурс Федеральной службы по надзору в сфере защиты прав потребителей и благополучию человека недостаточно информативен, невозможно идентифицировать продукцию и типы нарушений. Система оповещения о опасных товарах Rapex более информативна. На информационном портале приводится подробная информация о выявленных нарушениях: о наименовании, производителе и торговой марке, демонстрируется фотография товара, приводится характеристика типа риска, а также указываются предпринятые меры в отношении опасного товара. Данная информация является открытой, и с ней могут ознакомиться все участники рынка. Область применения результатов. Рассмотрена возможность использования опыта ЕС в отношении цифровых ресурсов для оповещения об опасной продукции контрольно-надзорными органами и потребителями, предотвращения попадания ее на рынок. Выводы. Формирование единой информационной системы на рынках ЕАЭС о продукции, не соответствующей требованиям технических регламентов, позволит субъектам рынка получать информацию не только об опасной продукции, но и мерах в отношении нее, принятых надзорными органами.
Expresar en palabras el pensamiento animal
Authors: Crelier Andrés
Published: December 2020

El artículo defiende la tesis de que es posible en principio formular en palabras el contenido del pensamiento animal. En primer lugar, se propone una interpretación de la investigación en etología cognitiva en el sentido de un progreso que presupone, en algunos casos, la posibilidad de formular en palabras los pensamientos de los animales. En segundo lugar, se intentan debilitar dos objeciones filosóficas, la de que los pensamientos animales tendrían un contenido extraño e inconmensurable, y la de que serían de naturaleza no conceptual. En tercer lugar, se utiliza la distinción entre expresar y describir el pensamiento (Dennett) para proponer un modo en el que formular en palabras el pensamiento de los animales sin lenguaje.
Banalización de la violencia
Authors: Caldera Ortiz Pablo
Published: December 2020

Reseña de: J.L. Nancy, Banalidad de Heidegger, Madrid: Trotta, 2019, 93 pp.
GOD’S MAIDSERVANTS: A PENTECOSTAL WOMEN (COUNTER)NARRATIVE
Authors: Coral Gómez L. Valentina
Published: December 2020

Basándose en la doctrina de que tanto las mujeres como los hombres pueden sentir el llamado de Dios y, de consecuencia, servirle de la misma manera, algunas iglesias pentecostales y neo-pentecostales parecen favorecer el empoderamiento de las mujeres. Un análisis de la IDMJI, una iglesia neo-pentecostal fundada en Colombia, y de su correspondiente partido político, MIRA, permite apreciar cómo opera este empoderamiento, evidenciando al mismo tiempo cómo estos grupos religiosos mantienen intactos estereotipos de género que pueden perjudicar tanto a sus propios feligreses como a la sociedad en general. La IDMJI es liderada por una mujer y sostiene que tanto hombres como mujeres pueden predicar. Su partido político ha realizado acciones en favor de las mujeres y otras minorías, por ejemplo, exigiendo la paridad en el servicio público y protestando en contra de la violencia de género. No obstante, el valor que le dan a las mujeres sigue estando altamente relacionado con su papel de esposas y madres. Además, no contemplan la posibilidad de relaciones afectivas o sexuales que no se ajusten al modelo heteronormativo. De esta manera, refuerzan el modelo social patriarcal y ponen en riesgo tanto la autodeterminación de las mujeres como los derechos de la comunidad LGBTQ+.
Magia, sacralidad y realeza. Un balance sobre un hito historiográfico:Les rois thaumaturgues de Marc Bloch
Authors: LLinares-García Mar
Published: December 2020

Algunos historiadores consideran que un libro es un hito que abre nuevas vías a la escritura de la historia, mientras que otros lo ven simplemente como el símbolo de identificación de una escuela académica. Este fue el caso de Les Rois thaumaturgues de Marc Bloch (1924), libro que algunos historiadores franceses consideran el inicio de la histoire des mentalités. El libro es un estudio de caso del toque real, un ritual medieval de curación de la enfermedad llamada scrofulae mediante la imposición de las manos de los reyes de Francia e Inglaterra. Este artículo analiza la obra de Bloch en su relación con las teorías de la llamada “realeza sagrada”, especialmente la propuesta por J.G. Frazer y con el nacimiento y desarrollo de la histoire des mentalités.
CONSTRUCTION OF ATTACK DETECTION SYSTEMS IN INFORMATION NETWORKS ON NEURAL NETWORK STRUCTURES
Authors: Tolіupa Serhii , Pliushch Oleksandr , Parkhomenko Ivan
Published: December 2020

Systems for detecting network intrusions and detecting signs of attacks on information systems have long been used as one of the necessary lines of defense of information systems. Today, intrusion and attack detection systems are usually software or hardware-software solutions that automate the process of monitoring events occurring in an information system or network, as well as independently analyze these events in search of signs of security problems. As the number of different types and ways of organizing unauthorized intrusions into foreign networks has increased significantly in recent years, attack detection systems (ATS) have become a necessary component of the security infrastructure of most organizations. The article proposes a software prototype of a network attack detection system based on selected methods of data mining and neural network structures. The conducted experimental researches confirm efficiency of the created model of detection for protection of an information network. Experiments with a software prototype showed high quality detection of network attacks based on neural network structures and methods of intelligent data distribution. The state of protection of information systems to counter cyber attacks is analyzed, which made it possible to draw conclusions that to ensure the security of cyberspace it is necessary to implement a set of systems and protection mechanisms, namely systems: delimitation of user access; firewall; cryptographic protection of information; virtual private networks; anti-virus protection of ITS elements; detection and prevention of intrusions; authentication, authorization and audit; data loss prevention; security and event management; security management.
METHOD FOR PROTECTION TRAFFIC FROM INTERVENTION OF DPI SYSTEMS
Authors: Ilyenko Anna , Ilyenko Sergii , Vertypolokh Oleksandr
Published: December 2020

This article discusses further ways to protect traffic from DPI systems. The possibilities of using network protocols and application of DPI systems are investigated in the article. The analysis of the problem made it possible to identify vulnerabilities in the DNS protocol, which is based on the UDP protocol. These vulnerabilities include spoofing, interception, and traffic tethering. Also on the basis of the analysis of methods of protection of DNS traffic from interference, the authors substantiate and define the following: 1) all DNS queries are transmitted in the open; 2) existing approaches to traffic protection do not use encryption and, consequently, do not ensure the confidentiality of information; 3) there is only confirmation of the authenticity of the records. The authors have created a summary table, which identifies reliable methods of protecting DNS traffic. The authors propose the development of a full-fledged local proxy server to provide DNS traffic that can access trusted public DNS resolvers using doh and dot protocols. To understand the principles of protocol interaction, we developed our own local implementation of the main components of the network, which are most often dealt with by network users, namely: 1) web server; 2) DNS server; 3) server providing cryptographic protection and hiding open requests. The practical value of the obtained results lies in the software implementation of methods to protect traffic from DPI systems in Visual Studio Code by using the Python 3.8 programming language, which allows to provide cryptographic protection of traffic. The proposed solution of the local proxying server can be improved in the future by introducing local caching with the addition of the ability to create rules for certain domains and their subdomains. The implemented test doh server can be deployed on a trusted dedicated server outside of possible filter equipment installation points. This implementation will allow you to fully control your own traffic for resolving domain names. The authors further plan a number of scientific and technical solutions to develop and implement effective methods, tools to meet the requirements, principles and approaches to cyber security and traffic protection from interference by DPI systems in experimental computer systems and networks.
6 Şubat 2017, Mw=5.4 Ayvacık Depremi Öncesi ve Sonrası Temel Deprem Tehlike Parametrelerinin Analizi
Authors: Gezer Ayşe , Bekler Tolga
Published: December 2020

Kuzeybatı Ege bölgesinin en karmaşık tektonik unsurlarını barındıran Biga Yarımadası oldukça yoğun bir dep-remsellik gösterir. Bu yarımada ve yakın çevresi için farklı dönemlerde meydana gelen orta ve büyük depremlerin deprem tehlikesi analizi, çalışmanın temelini oluşturmaktadır. Temel deprem parametreleri olarak da bilinen a ve b-değerleri bu çalışmanın veri tabanı olan aletsel dönem deprem kataloğundaki M>2 için belirlenmiş ve değerlendi-rilmiştir. Bu çalışmada, ÇOMÜ) ve KRDAE tarafından işletilen deprem istasyonları ve buna bağlı yüksek kaliteli faz okumaları sonucuna dayalı ortak bir deprem kataloğu kullanılmıştır. Ayvacık başta olmak üzere ve yakın çevresinde 6 Şubat 2017’de meydana gelen Mw=5.4 büyüklüğündeki deprem ile başlayan ve süreklilik gösteren deprem sonrası aktivitenin Tuzla deformasyon zonu çevresinde yaklaşık 25x10 km’lik bir alanda kümelendiği gözlenmiştir. Bu deprem öncesi ve sonrası yerel tektonik yapılar ve gerilme durumları ile ilişkilendirilebilecek başta b-değeri olmak üzere olasılıksal parametreler de değerlendirilmiştir. Kısa ve uzun dönemde bu parametrelerin ana deprem öncesi ve sonrası azalım ve artış eğilimleri yerel ve bölgesel hâkim gerilmelerin yanında üst kabuktaki heterojenite ve jeotermal kaynaklar da göz önünde bulundurularak sismisite ve sismotektonik yapıya katkısı ve ilişkisi uzaysal ve zamansal olarak incelenmiştir. Saroz-Ayvacık-Edremit doğrultusunda alansal olarak deprem verisi yoğunluğu dikkate alındığında b-değerlerinin gerilmelerle ters orantılı olarak deprem öncesi artışı ve akabin-de de bu davranış azalımı 2014 ve 2017 depremleri ile kendisini göstermiştir.
Silencing Speech: New American Free Speech Debates
Authors: Dybska Aneta
Published: December 2020

This article investigates the discursive production of “the silent majority” as a collective subject of Right-wing politics in the context of free speech controversies on U.S. college campuses. The discussion that follows examines the way the populist rhetoric, reified in the speech/silence dichotomy, focalizes partisan dissent and resentment and seeks to restore the nation’s past glory that was allegedly lost to political correctness and identity politics.
Use of Non-Traditional Types of Flour in the Flour Culinary Production (Pancakes)
Authors: Tiunov Vladislav , Chugunova Olga , Arisov Aleksandr
Published: December 2020

Currently, Strategy for Improving the Food Products Quality in the Russian Federation until 2030 identifies the need to develop new food products as one of the important state tasks; the quality improvement of raw materials used, the nutritional and biological value of finished products and expanding its range are an urgent area of scientific research. Flour culinary products are no exception. These products made from traditional wheat flour of the highest grade have low nutritional value, high calorie, lack of vitamins and minerals. In order to increase the biological value of flour culinary products, a man adds food additives and biologically active substances; uses non-traditional raw materials for the production. The article considers the possibility of using non-traditional flour types mixtures instead of wheat flour of the highest grade in the production of flour culinary products (pancakes). The researchers developed the optimal dosage for adding mixtures of rice and corn, rice and amaranth, rice and soya flour to the product formulations. They studied comprehensively the regulated indicators of product quality and safety: organoleptic, physical and chemical, microbiological; run the comparative analysis of samples from non-traditional types of flour with a control sample. The authors developed the pancakes technology in the form of baking it in a convection steamer with a complete replacement of wheat flour with a mixture of rice and corn, rice and amaranth, rice and soya flour. They compiled technological maps and formulated a technical document package on the products range.
Mushroom Powder Application of Oyster Mushroom for Activation of Pressed Baking Yeast
Authors: Maslov Alexander , Mingaleeva Zamira , Reshetnik Olga
Published: December 2020

The article concerns the study of pressed baking yeast activation with mushroom powder obtained by drying oyster mushrooms (grain size – 100 microns; humidity – 5.0–6.0 %). A man carried out the work according to the methods used in baking to determine the yeast fermentation activity. To optimize yeast activation parameters the researchers used a second order Box–Hunter rotatable plan for two factors. The optimal ratio of yeast and oyster mushroom powder in the nutrient medium for yeast activation is 1:2.45; the activation time is 31 minutes. The compressed yeast activation in a nutrient medium containing oyster mushroom powder contributes to an increase in the zymase and maltase activity of yeast, which increase on average by 52.1 and 62.7 %, respectively, compared to the control. The results obtained indicate that the oyster mushroom powder use is promising for compressed yeast pre-activation. The use of this additive in bakeries will potentially reduce the fermentation time of test semi-finished products by increasing the fermentation activity of yeast. In addition, it is possible to improve the quality characteristics of finished products due to the enrichment of biologically active substances contained in oyster mushrooms. Further research should determine the effect of yeast activation using oyster mushroom powder on the physical, chemical and organoleptic quality indicators of finished bakery products.
Estraga-prazeres feministas (e outras sujeitas voluntariosas)
Authors: Ahmed Sara
Published: December 2020

Questionando da figura da “estraga-prazeres feminista”, este ensaio explora sua negatividade, bem como sua promessa de agência. Ao enquadrar o pensamento feminista como uma crítica da felicidade, sugere que a sujeita feminista deve ser entendida como uma “figura voluntariosa”. A obstinação feminista é, assim, entendida como o terreno incerto para uma política coletiva de tradução de emoções individuais, dor ou raiva diante das injustiças. Além disso, a figura feminista voluntariosa pode ajudar a compreender as formas pelas quais, nos espaços feministas, as mulheres negras foram reduzidas à sua raiva e designadas como causadoras das divisões produzidas pelo racismo. A posição de obstinação é, portanto, tanto um lugar de tensões políticas quanto um lugar de reivindicações.
Entrevista com Heloísa Buarque de Hollanda - Feminismos em pleno voo: multiplicidade, protagonismo e transformação social
Authors: Sovik Liv , Lana Lígia , Bogado Maria
Published: December 2020

Entrevista inédita com a escritora Heloísa Buarque de Hollanda.
The President and the viper
Authors: Berberović Sanja , Delibegović Džanić Nihada
Published: December 2020

Applying
conceptual blending theory, the paper analyses the construction of the meaning
of a satirical text ridiculing the language employed by politicians to frame
the debate on current political and social issues. In particular, it focuses
on the language used by Donald Trump in explaining his anti-immigration
stances through a poem based on the fable about the farmer and the viper, and a satirical text providing a new
version of the poem, which criticizes Trump’s immigration policy. The paper
examines the creation of the humorous meaning of the text in conceptual
blending. The humorous meaning is created in the blended space due to the unusual combination of related
structures, which results in incongruity (Coulson 2002; Marín-Arrese 2003). Furthermore, as blending can be used as a rhetorical tool
influencing the audience to change the reality and even act upon it (Coulson
2006; Coulson & Oakley 2006; Coulson & Pascual 2006; Oakley &
Coulson 2008), the analysis of the construction of the meaning of the
satirical text as a product of conceptual blending can reveal rhetorical and
argumentative goals in political discourse.
Can
political rhetoric ever be “too persuasive”?
Authors: Musolff Andreas
Published: December 2020

Can the use of linguistic devices to achieve
persuasion, such as metaphor, irony and hyperbole, ever be “too persuasive”,
i.e., overshoot its rhetorical aim? More specifically, can the combination of
such devices be “too much of a good thing” in that it commits speakers (and
approving hearers) to actions that they were not part of their persuasion
intentions? This paper investigates the semantic and pragmatic development of
the Brexit-related applications of the metaphorical proverb, You cannot have your cake and eat it,
during 2016–2019 in British public discourse. At the start of that period,
the proverb’s reversal into the assertion “We can have our cake and eat it!”
by the then Foreign Secretary Boris Johnson and other “Brexiteers” became a
highly prominent endorsement of Brexit and its supposed benefits for the UK;
it even temporarily set the agenda for the public perception of UK–EU
negotiations. Over time it became an object of hyperbolic praise as well as
derision and recently seems to have lost much of its persuasive force. The
paper argues that the proverb’s new reversed application by Johnson was
initially successful in reviving its metaphorical meaning and framing it in a
hyperbolic rhetorical context but that it also pushed Brexit proponents to an
“all-or-nothing” outcome of the conflict narrative, both vis-à-vis the EU and
within the British political debate. Thus, rhetorical success can lead to
argumentative (and political) commitments that may have been not foreseen by
the speaker and may run counter to their persuasive interests.
Mitigating MOSFET Radiation Effects by Using the Wave Layout in Analog ICs Applications
Authors: De Souza Rafael Navarenho , Guazzelli Marcilei A. , Gimenez Salvador P.
Published: December 2020

This paper presents an experimental comparative study of the Total Ionizing Dose (TID) effects between the Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET) manufactured with the Wave (S gate geometry) and the standard layout (CnM). Because of the special geometric characteristic of the gate, drain and source regions of the Wave MOSFET (WnM), this innovative layout proposal for transistors is able to mitigate the TID effects in order to implement in analog integrated circuits (IC) for space and medical applications without causing any additional cost to the Complementary MOS (CMOS) manufacturing process.
MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design
Authors: Toledo Pedro , Klimach Hamilton , Cordova David , Bampi Sergio , Fabris Eric
Published: December 2020

In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.
A Synthesizable BCH Decoder For DVB-S2 Satellite Communications
Authors: Chaves Cesar G. , De Lima Eduardo R. , Mertes Jacqueline G.
Published: December 2020

This paper presents the design of a BCH Decoder for digital satellite TV Communications. It includes an architecture design specification, as well as the results of FPGA prototyping and of the logical and physical synthesis in 65nm CMOS. Moreover, it can be used as a basis for BCH Decoder designs for other kind of communications or even storage error correction.
A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC
Authors: Jung Inseok , Kim Kyung Ki , Kim Yong-Bin
Published: December 2020

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.
A Defects Simulator for Robustness Analysis of QCA Circuits
Authors: Reis Dayane Alfenas , Torres Frank Sill
Published: December 2020

Although QCA (Quantum-dot Cellular Automata) is a promising nanotechnology to replace CMOS (Complementary Metal-Oxide-Semiconductor), it has several known reliability problems. Consequently, the design of robust QCA structures is a mandatory step towards the consolidation of this new technology. This paper presents a novel methodology for error analysis of QCA structures based on deterministic and random insertion of possible defects to either the cells and to the phase shifts of the clocking circuit. Further features presented are an evaluation of structures robustness and identification of the design elements most susceptible to the defects. Simulation results obtained from the implemented QCA Defects Simulator indicate the feasibility of the proposed error exploration methodology, also revealing starting-points for robustness improvements of known QCA structures.
Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs
Authors: Assalti Rafael , Doria Rodrigo T. , Flandre Denis , De Souza Michelly
Published: December 2020

In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.
Focal-Plane Compression Imager with Increased Quantization Bit Rate and DPCM Error Modeling
Authors: De Oliveira Fernanda Duarte Vilela Reis , Lopes Tiago Monnerat de Faria , Gomes José Gabriel Rodríguez Carneiro , Barúqui Fernado Antônio Pinto , Petraglia Antonio
Published: December 2020

Focal-plane processing is the target of many studies due to its potential for enhancing the speed of the vision system flow. With focal-plane processing it is possible to perform parallel processing throughout the entire matrix. In order to alleviate A/D conversion and transmission constraints, analog image compression is implemented at the focal plane, thereby reducing the amount of data to be transmitted and the bandwidth requirements. The ADC is performed at the focal plane as well, after the compression operation whose realization is based on differential pulse-code modulation (DPCM), linear transform and vector quantization (VQ) applied on every 4 × 4 pixel block using current-mode circuits. This paper presents experimental results obtained from a second-generation version of the image sensor. Among these results we can point out the presentation of different captured images and the modeling of errors that were identified during the experimental tests. Since the source of these errors is the DPCM stage, the modeling concerns the bits that refer to the mean block luminance results. The error modeling procedure was developed considering the relationship between the pixel integration period and the DPCM quantizer threshold values. The main contributions of the second-generation chip in comparison to the previous realization are: increase of the vector quantizer complexity, number of bits per pixel, pixel matrix size, and the use of cascode current mirrors in the linear transform matrix. The image sensor advanced in this paper was fabricated in a standard 180 nm CMOS process.
Compact CMOS Analog Multiplier Free of Voltage Reference Generators
Authors: De Sousa Antonio José Sobrinho , De Andrade Fabian Souza , Bomfim Matheus Artur Macedo , Silva Alípio Souza , Dos Santos Hildeloi Cunha , De Lima Robson Nunes , Santana Edson Pinto , Cunha Ana Isabela Araújo
Published: December 2020

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.
Improving Ultrasonic Imaging of Aluminum Plates using Phase Modulation
Authors: Tischer Rafael Mateus , Higuti Ricardo Tokio , Kitano Claudio , Prado Vander Teixeira
Published: December 2020

Ultrasonic imaging using arrays is a widespread technique used in medical imaging, with increasing use in industry. Conventional techniques use amplitude information from the ultrasonic signals to produce the images. These amplitude images can be produced with high quality, but can also present limitations regarding dead zone, artifacts and detection of far reflectors. Coherence images based on the signal phase have been explored in some works, and produce an image that indicates the presence of a defect. In this work we explore he effect of phase modulation of the ultrasonic signal and its effect on the corresponding coherence image. Simulations and experimental tests in an aluminum plate using Lamb waves and a linear piezoelectric array show that the phase modulation hasadvantages over coherence images without phase modulation for defect indication.
Memory-aware Workload Balancing Technique based on Decision Trees for Parallel HEVC Video Coding
Authors: Storch Iago , Zatt Bruno , Agostini Luciano , Correa Guilherme , Palomino Daniel
Published: December 2020

Video coding applications demand high computational effort to achieve high compression rates at a low perceptual quality expense. In order to reach acceptable encoding time for such applications, modern video coding standards have been em-ploying parallelism approaches to exploit multiprocessing plat-forms, such as the tiling tool from HEVC standard. When employing Tiles, each frame is divided into rectangular-shaped regions which can be encoded independently. However, alt-hough it is possible to distribute the data equally among the processing units when using Tiles, balancing the workload among processing units poses great challenges. Therefore, this paper proposes a workload balancing technique aiming to speed up the HEVC parallel encoding using Tiles. Different from other literature works, the proposed solution uses a novel approach employing static uniform tiling to avoid memory management difficulties that may emerge when dynamic tiling solutions are employed. The proposed technique relies on workload distribution history of previous frames to predict the workload distribution of the current frame. Then, the pro-posed technique balances the workload among Tiles by em-ploying a workload reduction scheme based on decision trees in the coding process. Experimental tests show that the pro-posed solution outperforms the standard uniform tiling and it is competitive with related works in terms of speedup. Moreo-ver, the solution optimizes resources usage in multiprocessing platforms, presents a negligible coding efficiency loss and avoids increasing memory bandwidth usage by 9.8%, on aver-age, when compared to dynamic tiling solutions, which can impact significantly the performance in memory-constrained platforms.
Table of contents and Foreword
Authors: Reis Ricardo , Moraes Fernando , Fouillat Pascal
Published: December 2020

The Editorial Board has the satisfaction to launch the first edition of the Journal of Integrated Circuits and Systems - JICS. This journal will present state-of-art papers on Integrated Circuits and Systems areas. It is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering the following microelectronic domains: Process and Materials, Device and Characterization, Design, Test and CAD of Integrated Circuits and Systems.This first edition includes a regular paper in the field of asynchronous circuits, a paper in the area of mixed-signal circuits which first version was selected as one of the best papers in SBCCI2001, as well five others papers that were selected as best papers from SBCCI2002. We would like to thank Luigi Carro, José Huertas and Ney Calazans that worked as editors of the papers originated from SBCCI.We ask the researches all around the world to submit good papers to consolidate the journal as an international publication composed by a set of attractive and outstanding papers.The Editors
Table of contents and Foreword
Authors: Reis Ricardo , Moraes Fernando , Fouillat Pascal
Published: December 2020

The Editorial Board has the satisfaction to launch the second edition of the Journal of Integrated Circuits and Systems - JICS. This journal will present state-of-art papers on Integrated Circuits and Systems areas. It is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering the following microelectronic domains: Process and Materials, Device and Characterization, Design, Test and CAD of Integrated Circuits and Systems. This second edition includes a selection of papers from SBMicro symposium. We would like to thanks João Antonio Martino that worked as editor of the papers originated from SBMicro and included in this edition. We ask the researches all around the world to submit good papers to consolidate the journal as an international publication composed by a set of attractive and outstanding papers.The editors
Hardware support in a middleware for distributed and real-time embedded applications
Authors: Silva Jr Elias T. , Wagner Flávio R. , Freitas Edison P. , Kunz Leonardo , Pereira Carlos E.
Published: December 2020

One of the main challenges in the development of tools and methodologies for a multiprocessor realtime embedded system is to reuse already developed software, but at the same time obtaining low memory footprint, low energy consumption, and minimal area, obviously addressing the real-time constraints. This work aims to face these problems at the middleware level.We show that adaptations in the platform architecture, for instance exploring hardware implementations of middleware services, such as task scheduling and communication, can drive better gains in application requirements like energy and performance, which are essential for embedded applications. This approach is coupled with a high flexibility in choosing either a hardware or a software implementation, because services are encapsulated into objects and the application development and the design space exploration at middleware level can be performed independently from each other, in a fully transparent way. Furthermore, the use of the object-oriented approach reduces time-to-market and development costs.
Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration
Authors: Do Nascimento Paulo Sérgio Brandão , Da Silva Stelita M. , Seixas Jordana L. , Sant’Anna Remy E. , De Lima Manoel E.
Published: December 2020

High parallelism degree is fundamental for high speed massive data processing systems. Modern FPGA devices can provide such parallelism plus flexibility. However, these devices are still limited by their logic block size, memory size, memory bandwidth and configuration time. Temporal partitioning techniques can be a solution for such problems when FPGAs are used to implement large systems. In this case, the system is split into partitions (called contexts), multiplexed in a FPGA, by using reconfiguration techniques. This approach can increase the effective area for system implementation, allowing increase of parallelism in each task that composes the application. However, the necessary reconfiguration time between contexts can cause performance decrease. A possible solution for this is an intensive parallelism exploration of massive data application to compensate for this overhead and improve global performance. This is true for modern FPGA with relatively high reconfiguration speed. In this work, A reconfigurable computer platform and design space exploration techniques are proposed for mapping of such massive data applications, as image processing, in FPGA devices, depending on the application task scheduling. A library with different hardware implementation for a different parallelism degree is used for better adjustment of space/time for each task. Experiments demonstrate the efficiency of this approach when compared to the optimal mapping reached by exhaustive timing search in the complete design space exploration. A design flow is shown based on library components that implements typical tasks used in the domain of applications.
Parameters Extraction from C-V Curves in Triple-Gate FinFET
Authors: Rodrigues Michele , Sonnenberg Victor , Martino João Antonio
Published: December 2020

Methods to determine the effective oxide thickness (EOT), fin height (Hfin) and fin doping concentration (Nfin) through gate to drain/source capacitance as a function of the front and the back gate voltage curves in triple-gate nMOS FinFET are presented. The proposed methods were validated through three-dimensional numerical simulations and experimental measurements showing that these methods can be also applied in triple-gate nMOS FinFET devices as a powerful tool for experimental validation.
Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses
Authors: Lomné V. , Dehbaoui A. , Ordas T. , Maurine P. , Torres L. , Robert M. , Soares R. , Calazans N. , Moraes F.
Published: December 2020

Side channel attacks (SCA) are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind STTL are valid in general and particularly for FPGAs. Also, the paper shows that this new logic may provide interesting design guidelines to get circuits that are resistant to differential power analysis (DPA) attacks which and also more robust against differential electromagnetic attacks (DEMA).
Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs
Authors: Camillo Luciano Mendes , Martino João Antonio , Simoen Eddy , Claeys Cor
Published: December 2020

This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.
A Fast-Response Charge-Pump Gate Driver Applied to Linear Regulation
Authors: Mansano André L. R. , De Lima Jader A. , Swart Jacobus W.
Published: December 2020

This paper presents a compact charge-pump gate driver (CPGD) that dynamically adjusts the driving voltage VGS_SW of power switches, following stringent load transients in amplitude and duration. Owing to its simple topology, the CPGD responsively sustains regulation of the charge-pump (CP) output voltage VOUT within the range [2.4V, 3.0V] during transient load, while consuming only tens of μA. Contrary to driving techniques that depend on the settling of VOUT before adjusting VGS_SW, the CPGD instantaneously compares VOUT to a reference VREF and optimally sets VGS_SW. The circuit shows low sensitivity with switching frequency fsw across a broad range [50KHz fsw 1MHz]. Simulations with PSPICE and Bsim3v3 models attest the CPGD performance at extreme scenarios of a light and heavy load current ILOAD. For a 20μs-step of ILOAD from 0 to 20mA, the CPGD takes only 20μs to raise VGS_SW from 1.0V to 4.75V. The entire CP regulator was prototyped on a standard 0.35μm CMOS fabrication process, with the CPGD occupying an area of 0.014μm2. Experimental results match closely both DC and transient the expectations for CPGD. The driver features consumption below 475μW and complies with a low-voltage supply, such as1.5V-batteries.
Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator
Authors: Majek Cedric , De Peslouan Pierre-Olivier Lucas , Mariano André , Lapuyade Hervé , Deval Yann , Bégueret Jean-Baptiste
Published: December 2020

This paper presents the design and the measurement results of a novel Voltage Controlled DelayLine (VCDL) dedicated to an original architecture of Delay Locked Loop (DLL): the Factorial DelayLocked Loop (F-DLL). Based on the multiphase ring oscillator technique, the proposed VCDL offers,among others, two outputs in phase quadrature. These last ones allow the F-DLL to be zero-IF compliantand becomes a good candidate for multi-standard local oscillator. The proposed circuit hasbeen fabricated in a 130nm CMOS-SOI technology from STMicroelectronics. Measurement resultsconfirm the low quadrature phase error of the topology (inferior to 5°) and the ability of the F-DLL tosynthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications, while offering veryinteresting performances in term of phase noise and settling time.
Design Validation of Multithreaded Processors Using Threads Evolution
Authors: Ravotto D. , Sanchez E. , Sonza Reorda M. , Squillero G.
Published: December 2020

Within the design arena of modern devices based on cutting-edge processor cores, the availability of effective verification, validation and test methodologies able to work on high-level descriptions of processor cores represents an interesting advantage, since it can dramatically reduce the overall time for design and manufacturing, while improving yield and quality. In this paper we propose a semi-automatic test program generation technique able to target modules in modern computer architectures that implement the multithreading paradigm. The methodology starts from high level descriptions of processor cores and using an incremental multi-run approach produces, with very limited manual intervention, a test set able to maximize verification metrics. Experimental results gathered on a couple of real complex designs (the OpenSPARC™ T1 and T2) show the effectiveness of the proposed methodology.
Motion Estimation Architecture Using Efficient Adder-Compressors for HDTV Video Coding
Authors: Porto Marcelo , Silva André , Almeida Sergo , Da Costa Eduardo , Bampi Sergio
Published: December 2020

This paper presents real time HDTV (High Definition Television) architecture for Motion Estimation (ME) using efficient adder compressors. The architecture is based on the Quarter Sub-sampled Diamond Search algorithm (QSDS) with Dynamic Iteration Control (DIC) algorithm. The main characteristic of the proposed architecture is the large amount of Processing Units (PUs) that are used to calculate the SAD (Sum of Absolute Difference) metric. The internal structures of the PUs are composed by a large number of addition operations to calculate the SADs. In this paper, efficient 4-2 and 8-2 adder compressors are used in the PUs architecture to achieve the performance to work with HDTV (High Definition Television) videos in real time at 30 frames per second. These adder compressors enable the simultaneous addition of 4 and 8 operands respectively. The PUs, using adder compressors, were applied to the ME architecture. The implemented architecture was described in VHDL and synthesized to FPGA and, with Leonardo Spectrum tool, to the TSMC 0.18μm CMOS standard cell technology. Synthesis results indicate that the new QSDS-DIC architecture reach the best performance result and enable gains of 12% in terms of processing rate. The architecture can reach real time for full HDTV (1920x1080 pixels) in the worst case processing 65 frames per second, and it can process 269 HDTV frames per second in the average case.
Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors
Authors: Contreras E. , Cerdeira A. , Alvarado J. , Pavanello M. A.
Published: December 2020

The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.
PDMS (Polydimethylsiloxane) Microfluidic Chip Molding for Love Wave Biosensor
Authors: Tarbague H. , Lachaud J.-L. , Destor S. , Vellutini L. , Pillot J.-P. , Bennetau B. , Pascal E. , Moynet D. , Mossalayi D. , Rebière D. , Dejous C.
Published: December 2020

We present the development of new Polydimethylsiloxane (PDMS) chips, which are coupled with Love acoustic wave sensors to realize a detection cell of bio-organisms in liquid media. Three generations of biocompatible PDMS chips have been developed. Built-in thermistors allow a thermal control (±0.05°C). Unlike the usual assemblies, this chip is maintained by pressure on the sensor and not sticked on its surface. This technique makes it entirely removable and cleanable. Therefore, the surface of the sensor can be functionalized or regenerated. The realization of these chips is quick and inexpensive.We here outline the development of these different cells and present characteristics of the resulting microsensors, depending on the chip configuration. Real-time responses during antibodies immobilization are presented and analyzed. Antibodies at typical concentration of 45μg/ml are successfully fast detected, with response times from 350s for static down to 90s for dynamic detection setup, with similar sensitivity. Discussions on the mechanical fluid behaviour at the near sensor surface allow to better understand these results and to investigate further developments aiming at improving the quality of the fluid stream in order to even increase future sensor characteristics.
Thin-Film Lateral SOI PIN Diodes for Thermal Sensing Reaching the Cryogenic Regime
Authors: De Souza Michelly , Rue Bertrand , Flandre Denis , Pavanello Marcelo Antonio
Published: December 2020

This paper presents the performance of lateral SOI PIN diodes for temperature sensing in the range of 100 K to 400 K. Experimental results indicate that PIN diodes can be used to implement temperature sensors with high accuracy in cryogenic regime, provided that a suitable temperature range is chosen for calibration. Numerical simulations using Atlas two-dimensional simulator were performed in order to confirm this hypothesis and extend the analysis, verifying the accuracy of the existing model.