bluuebunny/crossref_metadata_2025 huggingface dataset:
Investigation of Coated Lithium Powder for Lithium Metal Batteries By Using Couette-Taylor Flow
Authors: Lee Changbum , Kim Jiwoong , Yoon Woo Young
Published: February 2020

Because of high theoretical specific energy density (3860mAhg-1) lithium metal is used for anode materials for rechargeable batteries. However, safety issues caused by the lithium inside a battery represent one of the main reasons for the lack of commercial availability of secondary lithium-metal batteries. Lithium metal powder and coated powder were suggested as an anode material and the droplet emulsion technique (DET) is one of the way to produce powder. DET method has a limitation for continuous producing and in-situ coating. This study present new method for lithium powder producing and in-situ coating using Coquette-Taylor (CTF) flow. The CTF flow contactor is characterized by high mass transfer parameters and represents an attractive tool for the multiphase systems. The results showed significant influence of the rotational flow in the CTF contactor on stability and characteristics of multiple emulsions. An electron probe x-ray micro-analyzer (EPMA) and a scanning electron microscope (SEM) were used to determine the size of powder and identify the coating layer.
Morphology-Tuned NiCo2O4-Coated 3D Graphene Rrchitectures As Binder-Free Electrode for Lithium Ion Battery
Authors: Zhang Chunfei , Yu Jong-Sung
Published: February 2020

In recent decades, lithium ion batteries (LIBs) have been considered as the most effective and practical technology products for portable electronic devices because of their flexibility, high energy density and long lifespan. Nanostructured transition metal oxides have been intensively studied as one of the most promising candidates for LIBs because of their high theoretical capacities (500-1000 mAh g-1), good reversible conversion, and low cost. However, in general, poor cycling performance and low electrical conductivity have hindered their practical application. Recently, 3D graphene synthesized by chemical vapor deposition (CVD) method has been studied extensively and used as a binder-free electrode in energy storage devices because of its excellent electron conductivity as current collector and high stability in electrolyte, but the application of 3D graphene as free-standing electrode is still limited due to its weak mechanical strength.

In this work, nanostructured NiCo2O4 is directly grown on the surface of three-dimensional graphene-coated nickel foam (3D-GNF) by a facile electrodeposition technique and subsequent annealing. The resulting NiCo2O4 possesses a distinct flower or sheet morphology tuned by potential or current variation electrodeposition, which is used as a binder-free lithium ion battery anode for the first time. Both samples exhibit high lithium storage capacity profiting from unique binder-free electrode structures. The flower-type NiCo2O4 demonstrates high reversible discharge capacity (1459 mAh g–1 at 200 mA g–1) and excellent cyclability with around 71% retention of the reversible capacity after 60 cycles, which are superior to sheet-type NiCo2O4. Such superb performance can be attributed to high volume utilization efficiency with unique morphological character, a well-preserved connection of active materials to the current collector, a short lithium ion diffusion path, and fast electrolyte transfer in binder-free NiCo2O4-coated 3D graphene structure. The simple preparation process and easily controllable morphology make binder-free NiCo2O4/3D-GNF hybrid a potential material for commercial application.
Initial Coulombic Efficiency Improvement of the Li-Rich Layered Oxide Cathodes Via Tellurium Doping
Authors: Meng Junxia , Wang Zicheng , Xu Lishuang , Xu Huaizhe
Published: February 2020

Li-rich layered oxide cathodes have the advantages of higher capacity and lower cost. However, they suffer from low initial Coulombic efficiency, which impose a great obstacle for their practical applications. In this work, a series of cathode matrials Li1.2Mn0.48-xTexNi0.16Co0.16O2(x=0, 0.02, 0.05 and 0.1) were synthesized via a co-precipitation. Structural characterizations revealed that the Te6+ doping samples with a suitable amount show low cation mixing, indicating an enhanced ordered layer structure. The electrochemical experiments show that the initial Coulombic efficiencies of the Li1.2Mn0.48-xTexNi0.16Co0.16O2 Li-rich material is largely improved by the tellurium substitution for manganese, and the highest value is about 88% with 272 mAh g-1 initial discharge capacity at room temperature when the content of doping tellurium is 0.05. These results prove that tellurium doping can effectively improve the initial Coulombic efficiency of these cathode materials during the first cycle process via enhancing the electrical conductivity and increasing structural stability of these Li-rich layered materials with a tellurium element introduction.

Figure 1
Gradient Surface Modification of Li-Excess Layered Oxide Cathodes Using Polyanions
Authors: Wei Weifeng , Liu Jiatu , Zhao Ying , Ivey Douglas G
Published: February 2020

Li-excess layered oxides (LLOs) of the general formula xLi2MnO3·(1-x)LiTMO2 (TM = Mn, Ni, Co, etc.) exhibit reversible capacities of up to 250 mAh g-1 and are more cost-effective. The Li2MnO3 component plays crucial roles in the electrochemistry of the LLOs, which not only improves the structural stability of LiTMO2 at high potentials, but also serves as an electrochemically active phase for Li extraction when charged above 4.5 V vs. Li/Li+. However, LLO cathode materials still suffer from limited cycle life and sluggish kinetics (e.g., poor rate capability), which origins from complex transition metal arrangements associated with the activation of Li2MnO3 (release of Li2O) upon charging at high potential and the inevitable layered-to-spinel structural transformation during electrochemical cycling.

Herein, a gradient polyanion-doping strategy, on the basis of borate, phosphate and silicate polyanions, is developed to integrate the advantages of both bulk doping and surface modification as the oxygen close-packed structure of LLOs is stabilized by polyanion doping, and the LLO cathodes are protected from steady corrosion induced by electrolytes. We comprehensively investigate the electrochemical performance of polyanion-doped LLOs with various local structures, which were prepared by manipulating doping content and annealing temperature. With the assistance of aberration-corrected scanning transmission electron microscopy (STEM), we present direct evident that the incorporation of polyanions induces a complex crystallization process of layered structure, and propose some new insights into the electrochemical improvement resulted from polyanion doping.
Improved Electrochemical Performance of Li1.2Ni0.2Mn0.6O2 By AlF3 Coating
Authors: Abdel-Ghany Ashraf , El-Tawil Rasha S , Hashem Ahmed M , Mauger Alain , Zaghib Karim , Julien Christian M
Published: February 2020

Li-rich layered Li1.2Ni0.2Mn0.6O2 (LLNM) was synthesized by sol–gel method using citric acid as chelating agent and further coated with AlF3 by chemical deposition method. The synthesized Li-rich oxides and AlF3 coated oxides were confirmed to be layered-layered integrated blends form by the hexagonal (R-3m S.G.) and the monoclinic (C2/m S.G.) phase. AlF3 layer with a thickness of about 2–5 nm is formed on the surface of Li-rich particles. Improvement in discharge capacity (253 mAh g-1) after lithium enrichment and coating process for Li-rich oxides was observed from galvanostatic measurements and compared with features of LiNi0.5Mn0.5O2. From analysis of electrochemical impedance spectra (EIS), the enhancement of the electrochemical performance is mainly attributed to the pre-activation of the Li-rich layered oxide induced by the AlF3 coating.
Ca-doped Li4Ti5O12 Nanosphere as a Superior Anode Material for Lithium-ion Batteries
Authors: Zhang Qianyu
Published: February 2020

Li4Ti5O12(LTO) has been regarded as a promising anode material for lithium-ion batteries(LIBs). Unfortunately, the implementation of LTO is hampered by its low electric conductivity and relatively poor lithium diffusion rate. Herein, we report a controllable route to synthesize Ca-doped LTO nanosphere to overcome such problems. Density functional theory calculations reveal that Ca2+ substituting on the Li site enables an electron to easily move to an energy level higher than the Fermi level, indicating that Ca-doped LTO is an electrical conductor. Furthermore, detailed characterizations demonstrate that the spherical nanostructuring reduces the diffusion distance for both the Li ions and electrons within the LTO bulk. When tested as the anode in LIBs, it shows superior electrochemical performances with an ultrafast charging time and ultrahigh specific capacity at high charge/discharge rates. Therefore, this strategy provides a new insight on how to significantly enhance LTO’s rate performance for targeted applications via doping and nanostructuring.
Structurally Defined Nanographene Assemblies for Highly Efficient Lithium Storage
Authors: Yen Hung-Ju , Tsai Hsinhan , Zhou Ming , Chen Aiping , Holby Edward F. , Choudhury Samrat , Wang Xianliang , Zhu Linxiang , Lin Haiqing , Dai Liming , Adamska Lyudmyla , Tretiak Sergei , Wu Gang , Wang Hsing-Lin
Published: February 2020

Tradition graphene anodes in lithium ion batteries (LIBs) suffer significant performance loss due to the restacking of graphene layers. In this work, we have demonstrated a facile synthesis of preparing a series of graphene-derived nanomaterials. Among other potential application, these nanomaterials achieved an excellent cyclic durability with much enhanced capacity as novel anode materials in LIBs. These exceptional metrics observed within the novel assemblies is primarily due to the robust structure along with the optimal d-spacing allowing for facilitated Li adsorption/desorption and diffusion. Furthermore, the significantly enhanced rate performance was achieved after optimizing the structure of the self-assemblies. Development of nanomaterials anode suggests that the optimal design of graphene materials with robust structures is very important for next generation LIBs with high-energy storage efficiencies.
Power-Dependent Transient Gain Study on Direct Gap GeSn Crystallized on Amorphous Layers
Authors: Wang Xiaoxin , Li Haofeng , Liu Jifeng
Published: February 2020

Group IV semiconductors attract intensive interests for potential monolithically integrated photonics on the Si platform. The realization of Group IV-based light emitters is challenging yet highly desirable. Ge-on-Si lasing from the direct gap transition has been demonstrated at room temperature by employing n-type doping and tensile strain to reduce the energy difference between direct bandgap and indirect bandgap[1-2]. An alternative method is incorporating Sn into Ge, which shrinks the direct bandgap much faster than the indirect bandgap, thereby leading to direct bandgap GeSn alloys. We found that the incorporation of Sn into Ge can also enhance the crystallization of GeSn on amorphous substrate, which is beneficial for 3D photonic integration on Si by moving all the photonic components to the metal/dielectric interconnect level well above the CMOS layer using back-end-of-line (BEOL) processing. In our previous work, high crystallinity GeSn substitutional alloy thin films with up to 9 at.% Sn are directly grown on amorphous SiO2 layers at low crystallization temperatures of 370~470 °C, eliminating the thick buffer layer commonly used in epitaxial GeSn on Si.[3]

Recently, epitaxial GeSn-based lasing is reported in the near mid-infrared wavelength range, but only observed at low temperatures [4]. A detailed understanding of the ultrafast carrier dynamics is necessary to design and optimize high-performance GeSn lasers operating at room temperature. In this study, we investigate the power-dependent femtosecond transient gain of direct-gap GeSn with 9% Sn thin films crystallized on amorphous SiO2 layers in the wavelength range of 1950~2350 nm. It is found at carrier injection density Δn<1×1017 cm-3 , the transmission of GeSn is same as that measured by Fourier Transfer Infrared spectroscopy (FTIR), i.e. no optical bleaching. When the injection density is increased to Δn~8×1018 cm-3 , the GeSn film becomes transparent at λ~2000 nm. At higher injection of Δn~2×1019 cm-3 , net transient gain is observed at λ=1900-2150 nm, with a peak gain of 6300 cm-1 at λ=2000 nm . Further increasing the carrier injection to Δn~1×1020 cm-3, the peak of transient gain red-shifted to 2100 nm due to the bandgap renormalization, and the peak gain further increases to ~8000 cm-1. The transient gain of GeSn with 9% Sn is similar to III-V direct bandgap semiconductors at similar injection levels. These results confirm that the GeSn thin film crystalized on amorphous SiO2 is a good optical gain medium. Further studies will reveal more detailed carrier dynamics between direct and indirect conduction valleys.

[1] R. E. Camacho-Aguilera, Y. Cai, N. Patel, J. T. Bessette, M. Romagnoli, L. C. Kimerling, and J. Michel, Opt. Express. 20, 11316 (2012).

[2] R. Koerner, M. Oehme, M. Gollhofer, et al, Opt. express, 23, 14815 (2015).

[3] H. Li, J. Brouillet, A. Salas, X. Wang and J. Liu, Opt. Mater. Express 3, 1385 (2013).

[4] S.Wirths, R. Geiger, N.von den Diresch, et al, Nature Photonics, 9, 88 (2015).
(Invited) Strain Engineered Crack-Free GaN on Si for Integrated Vertical High Power GaN Devices with Si CMOS
Authors: Dayeh Shadi , Tanaka Atsunori , Choi Woojin , Chen Renjie
Published: February 2020

We demonstrated beyond 10 µm thick crack-free GaN growth on Si substrate using selective area growth technique. Systematic characterization by scanning electron and optical microscopy on the grown samples revealed that cracks nucleate and propagate on {1-1
00} planes in <1-2
10> directions. By developing {1
-101} facet planes in selective area growth, thermal mismatch strain relief at facet surfaces eliminate cracking and enable growth over 10 µm thick crack-free GaN on Si. These grown structures exhibited high crystalline quality throughout the thickness of the structure as validated by selective area diffraction in high resolution transmission electron microscopy, with a dislocation density of 2-3 x 108 cm-2 at the GaN surface. On the same Si substrate, we were able to fabricate enhancement mode CMOS devices. The overall progress reported here paves the way for monolithically integrated GaN technologies for RF and high power applications on Si CMOS devices.
(Invited) Low Resistance Contacts to Nanoscale Semiconductor Devices
Authors: Saraswat Krishna C. , Shine Gautam
Published: February 2020

The scaling of silicon CMOS faces several obstacles necessitating the need to introduce materials such as germanium, III-Vs and 2D materials together with novel structures such as FinFET. As device scaling continues, parasitic source resistance largely dominated by contact resistance, is beginning to limit the device performance. Specific contact resistivity, ρc, of a metal-semiconductor (M/S) contact is dependent on the Schottky barrier height, ΦB, and the electrically active dopant density N at that interface. In M/S contacts the metal Fermi level is pinned at the charge neutrality level, ECNL, resulting in fixed electron and hole Schottky barrier heights ΦBN and ΦBP. High ΦB and low N results in high ρc, eclipsing the promise of intrinsic performance of scaled devices. To obtain low ρc it is essential to reduce ΦB and increase N.

Fermi level pinning occurs because wave functions of electrons in the metal tail can decay into the semiconductor in the band gap, creating metal-induced gap states (MIGS). Charging of these states by the metal wavefunction creates a dipole charge causing the Fermi level to align to minimize the dipole charge towards zero, effectively pulling the EF at the interface towards ECNL.

Historically the method to reduce ρc is by increasing N to > 1E20/cm3 thereby thinning the barrier, thus allowing more tunneling current. This method works well for n-Si and p-Ge which can be doped heavily. However, it is not very practical for n-Ge, p-Si, many III-Vs and 2D materials because of inability to dope them heavily. Second method is to create an additional dipole at the M-S interface to modulate ΦB by incorporating a dopant or a chalcogen close to the interface to modulate the dipole. Fluorine, sulfur and selenium have been shown to reduce ΦB in many semiconductors. Third method is by inserting a thin interlayer between the metal and semiconductor to depin the Fermi level and reduce ΦB. The metal electron wavefunction now decays in the interlayer resulting in fewer MIGS thus depinning the Fermi level, which now pins on the interlayer. Hence metal workfunction ΦM can now be used to tune the effective barrier height. For n-type ohmic contacts, metals with a low ΦM and interlayer with ~0 conduction band offset (ZnO, TiO2, SnO2) with semiconductor should result in a near zero ΦBN. For p-type ohmic contacts, metals with a high ΦM and insulator with ~0 valence band offset (NiO, CuAlO2) with semiconductor would be desirable. This method has been used to obtain low ΦB and thus low ρc in Si, Ge and III-V semiconductors and should prove to be very useful for 2D materials. Alternatively the interlayer can be chosen such that the metal pins near the band edge to get ~0 ΦB and it can be doped heavily to get thin barrier facilitating increased tunneling. SiGe source/drain in Si PMOS is a good example of this technique.

Results of theoretical modeling and experimental work will be presented in this talk.
Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs
Authors: Wang Guilei , Luo Jun , Qin Changliang , Cui Hushan , Liu Jinbiao , Jia Kunpeng , Li Junjie , Yang Tao , Li Junfeng , Yin Huaxiang , Zhao Chao , Ye Tianchun , Yang Ping , Jayakumar Ganesh , Radamson Henry H
Published: February 2020

As CMOS technology is downscaled into 22nm a transition from 2D to 3D transistors occurred and a revolutionary FinFET design was introduced. During this R&D, different strain engineering methods including selectively grown SiGe on source/drain as stressor material was used to boost the channel mobility. Another way to deal with channel mobility issue is to integrate Ge material which has high mobility for both p and n channel instead having Si fin in the transistor structure.

In this study, the Si Fin is processed and subsequently removed to create the trench between the STI SiO2 and a SiGe/Ge bilayer is selectively grown to fill the trench that is used as the MOS channel. In principle, there are two methods to remove the Si Fins as shown Fig.1 Primarily using WET etch while the second method is using the HCl etch during the epitaxy process. Since SiGe/Ge epitaxy process is sensitive to surface quality of the Si Fin, a meticulous in-situ cleaning is essential to remove all undesired residuals from the Si surface.

At first, selective Ge growth was applied to fill out the Si removed areas. The Ge layer is difficult to fill the small trenches (Fig.2a), therefore a SiGe layer is deposited as the strain relaxed buffer (SRB) layer in the trench prior to the Ge layer (Fig.2b). A Chemical Mechanical Polish (CMP) is necessary to planarize the surface (Fig.2c).

The Ge content and the strain amount in the SiGe layers was directly measured using high-resolution x-ray diffraction (HRXRD) rocking curves (RC). RCs were done at (113) reflection where the incident beam is as low as 2.6° and a large area of sample containing an enormous of number of transistors could be covered by x-ray beam. These RCs were simulated by the Takagi-Taupin equations and compared to the experimental curves in order to obtain high precision data for analysis. Cross-section images where provided by high-resolution scanning electron microscopy (HRSEM) and transmission electron microscopy (HRTEM) to measure the layer thickness, epi-quality, and integrity of the whole transistor structures. In the latter analysis, energy dispersive spectroscopy (EDS) technique was also employed to reconfirm the Ge profile in the channel regions of the FinFETs.

Reference
s

[1] Wang G, Abedin A, Moeen M, et al. Integration of highly-strained SiGe materials in 14nm and beyond nodes FinFET technology[J]. Solid-State Electronics, 2015, 103: 222-228.

Figure 1
(Invited) Silicon Nano-Tip Pattern Approach for Surface and Interface Engineering of Fully Coherent, High Ge Content Nanostructure Arrays for High Performance Photodetection
Authors: Niu Gang , Capellini Giovanni , Lupina Grzegorz , Niermann Tore , Salvalaglio Marco , Marzegalli Anna , Schubert Markus Andreas , Zaumseil Peter , Krause Hans-Michael , Skibitzki Oliver , Lehmann Michael , Montalenti Francesco , Xie Ya-Hong , Schroeder Thomas
Published: February 2020

Defects in form of dislocations at the interface and threading arms in the film as well as SiGe intermixing are the main mechanisms to release the crystallographic misfit strain in Germanium (Ge) heterostructures grown on the mature Silicon (Si) wafer platform, severely deteriorating thereby the superior optoelectronic properties of Ge for device applications. We demonstrate here a novel technique, enabling fully coherent, high Ge content islands on nano-tip patterned Si (001) substrates by the suppression of plastic relaxation as well as SiGe intermixing. The Si-tip patterned substrate, fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology, features ~50 nm wide Si tips emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy (MBE) growths result in Ge nano-islands with high selectivity and having homogeneous shape and size. The ~850°C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 at.% Ge). Nano-tip patterned wafers result in geometric, kinetic diffusion barrier intermixing hindrance (in particular surface diffusion suppression) confining the major intermixing to the pedestal region of Ge islands where kinetic diffusion barriers are however high. Theoretical calculations suggest that the self-assembled thin SiGe layer at the interface plays nevertheless a significant role in realizing fully coherent Ge nano-islands free from extended defects especially dislocations. Finally, single layer graphene (SLG)/Ge/Si-tip Schottky junctions were fabricated and thanks to the absence of extended defects and SiGe intermixing in the Ge islands, high performance photodetection characteristics with responsivity and Ion/Ioff ratio of ~45 mA/W and ~103, respectively, are demonstrated.
Rectification Properties of Boron Nitride/Silicon Heterostructure Diodes
Authors: Teii Kungen , Ito Hiroyuki , Katayama Naoki , Matsumoto Seiichiro
Published: February 2020

Boron nitride is formed in three main crystalline forms: cubic, wurtzite, and hexagonal. Cubic boron nitride (cBN) is potentially expected as the semiconductor for high temperature condition due to the large band gap, high breakdown field, and high resistance to oxidation. Vapor deposition of cBN films on a foreign substrate is generally followed by an sp2-bonded BN (sp2BN) interlayer. The resistivity of sp2BN phase is usually higher than cBN phase by more than two orders of magnitude. However, the role of the sp2BN interlayer in rectification of cBN-based heterostructure diodes has not been clarified yet. In this study, rectification properties of p-type cBN/sp2BN/n-type Si heterostructure diodes fabricated under low-energy ion impact by plasma-enhanced chemical vapor deposition are studied in terms of the sp2BN interlayer [1].

A two-step biasing technique is developed to control the fraction of cBN phase and, hence, the thickness of the sp2BN interlayer in the films. We show that the rectification ratio at room temperature is increased up to the order of 104 at ±10 V of biasing with increasing the sp2BN thickness up to around 130 nm due to suppression of the reverse leakage current. The variation of the ideality factor in the low bias region is related to the interface disorders and defects, not to the sp2BN thickness. The forward current follows the Frenkel-Poole emission model in the sp2BN interlayer at relatively high fields when the anomalous effect is assumed. The thermionic emission model is not well applied to both the forward and reverse currents. We conclude that the transport of the minority carriers for reverse current is strongly limited by the high bulk resistance of the thick sp2BN interlayer, while that of the major carriers for forward current is much less affected. [1] K. Teii, H. Ito, N. Katayama, S. Matsumoto, J. Appl. Phys. 117 (2015) 055710.
(Invited) Advanced Photonic Circuits Using III-V Semiconductors
Authors: Tauke-Pedretti Anna , Vawter G. Allen , Skogen Erik , Peake Gregory , Overberg M. E. , Alford Charles , Cajas Florante
Published: February 2020

Advances in photonic integrated circuits (PICs) have enabled increased system performance and new photonic system capabilities. Integration leads to reductions in SWaP (size, weight and power) and packaging costs, while increasing reliability and mechanical robustness when compared to discrete components. The unique characteristics of compound semiconductors enable monolithically integrated PICs with efficient integrated light sources, amplifiers and high performance modulators and detectors. Additionally, specialized discrete devices can be heterogeneously integrated with other photonic circuits to form more complex circuits.

Sandia has developed a fundamental capability in InP-based PICs that enables the monolithic integration of a diverse set of lasers, modulators (both phase-based and absorption-based), photodetectors, amplifiers (both high-gain and high-saturation power varieties) and routing waveguides, in addition to electrical passive components such as resistors, capacitors, and transmission lines.The foundation of the capability is quantum-well-intermixing which enables the realization of multiple bandedges to be formed across the wafer with very low optical reflections (<1 dB) at the interfaces [1], coupled with simple blanket MOCVD regrowths

This InP-based PIC platform allows for high performance components including >40 Gbps EAMs (electroabsorption modulators) and photodetectors [2], <1 GHz passband optical filters and wavelength-tunable lasers with >40 dB side mode suppression ratio on a single monolithic chip.This variety of devices enables the creation of unique, highly-functional PICs for a variety of applications. In addition, this PIC technology can also be combined with photonic technologies, including Si photonics, using heterogeneous integration to reduce costs and expand the application space.

Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

References

[1] E.J. Skogen, J.S. Barton, S.P. DenBaars, and L.A. Coldren, “A Quantum-Well-Intermixing Process for Wavelength-Agile Photonic Integrated Circuits,” IEEE Journal of Sel. Topics in Quantum Electronics, Vol. 8, No. 4, 863-869 (2002).

[2] E.J. Skogen, G.A. Vawter, A. Tauke-Pedretti, C.R. Alford, M.E. Overberg, and C.T. Sullivan, “Integrated Guided-Wave Photodiode Using Through-Absorber Quantum-Well-Intermixing”, IEEE Photonics Technology Letters, 25, (17), pp.1684-1686 (September 1, 2013).
(Invited) Surface Activated Wafer Bonding; Principle and Current Status
Authors: Takagi Hideki , Kurashima Yuichi , Suga Tadatomo
Published: February 2020

The surface activated bonding method originally uses cleaning of material surfaces by sputter etching using high energy ion/atom beam of inert gases, typically Ar. [1] The cleaning process removes adsorbed atoms and compound layers, typically oxides, which stabilize the surface. Therefore, after the cleaning process the surfaces become unstable “active” states. Mating two such activated surfaces in vacuum enables strong bond formation even at room temperature. This process is quite suitable for the wafer direct bonding. Because intimate contact is automatically achieved at the bonding interface by attractive force between two atomically smooth surfaces of polished wafers, the process requires not only heating process but also pressure application. [2,3]

This method has been successfully applied to various semiconductor wafers such as Si, GaAs, SiC, etc. [4,5] Most of the metals can be also bonded by the method in case of atomically smooth surfaces of, for example, metal layers finished by CMP and/or thin metal films deposited on well-polished wafers. [6,7] On the other hand, materials such as SiO2 and polymers cannot be directly bonded by the method. To bond such materials, deposition of very thin intermediate layers of metals or Si has been proposed. [8] The deposited metal atoms firmly adhere to the surface of SiO2 and/or polymers and simultaneously form active metal surface. The thin film deposition is regarded as a new process for the surface activation. This means that the concept of the surface activated bonding has been extended in order to apply the method to wide range of materials.

Various applications of the surface activated bonding have been developed in the field of wafer-level packaging and engineered substrates. In wafer-level packaging field, various MEMS devices have been already commercialized and 3D-integration of heterogeneous devices are under investigation. In engineered substrate application, RF filters have been already commercialized and still succeeding developments continue. Engineered substrates for micro-electronics, power-electronics, solar cells, etc. are now extensively developed by the method. We believe the surface activated bonding will be used in wide range of technological fields in the near future.

[1] T. Suga, et al., Acta Metall. Mater. 40 (1992) S113.

[2] H. Takagi, et al., Appl. Phys. Lett. 68(1996) 2222.

[3] H. Takagi, et al., Sens. Actuat. A 105 (2003) 98.

[4] M. M. R. Howlader, et al., J. Vac. Sci. Technol. B 19(2001) 2114.

[5] J. Suda, et al., Proc ICSCRM 2013, Miyazaki, Japan, (2013) 358.

[6] A. Shigetou, et al., J. Mater. Sci. 40 (2005) 3149

[7] T. Shimatsu, et al., J. Vac. Sci. Technol. B 28(2010) 706.

[8] R. Kondou, et al., Scripta Materialia 65(2011) 320.
A Study of Void Formation in Fluorine Containing Plasma Activated Wafer Bonding
Authors: Wang Chenxi , Liu Yannan , Suga Tadatomo
Published: February 2020

Plasma activated bonding is one of promising candidates in wafer bonding field. In the past decade, much progress in terms of plasma generation, plasma treatment parameters, and annealing conditions has been achieved to allow high strength bonding at low temperatures with minimal defects. Since wafer bonding is often used as a middle process during device manufacturing, subsequent heated (or annealing) processes are inevitable for bonded wafers. However, void generation in annealing process (known as “annealing void”) is a serious problem in plasma activated bonding, especially for Si/Si wafer pairs. In particular, voids more frequently occur and are significantly severer as the wafer sizes further increase. Recently, our group has developed a fluorine activated bonding process enabling strong bonding of Si/Si bonded pairs (~2.2 J/m2 in surface energy) even at room temperature (~25ºC) without requiring annealing by introducing a small amount of carbon tetrafluoride (CF4) into oxygen plasma treatments. It seems that the fluorinated oxide allows water and hydrogen to diffuse out more easily from the interface at room temperature. But we have no idea how voids would be generated in elevated temperatures during subsequent annealing process. In this work, we demonstrate a quantitative evaluation of the void formation. As a comparison, void generation in the samples prepared by O2 plasma activated bonding is also systemically investigated. The void formation model is proposed to gain insight the mechanism of the fluorine containing plasma activated bonding.

8-inch silicon wafers (i.e. 200-mm diameters) were used in the experiments. To inspect void formation, a couple of bonded wafer pairs were prepared with different plasma treatment conditions. All the bonded wafer pairs were heated at 200, 300, 400, 500, 600, 700, and 800ºC for 8 h in ambient air. The heating steps do not aim to improve the bonding strength, but to investigate void formation at high temperatures. The IR imaging system was mainly used to characterize the voids in bonded pairs. To track the void emergence and growth, the digital image processing was employed to calculate void densities over the entire bonded wafer pairs. Water contact angle and x-ray photoelectron spectroscopy (XPS) measurements were made to investigate the plasma effects prior to bonding.

In conclusion, we found adding fluorine to oxygen plasma could effectively mitigate void formation in subsequent annealing process. Moreover, the plasma treatment time is a vital parameter to optimize the bonding strength as well as the void generation. Long plasma treatment may produce more porous surfaces and introduce undetected microdefects. Consequently, a short fluorine containing plasma treatment (e.g. ~10 s) is suitable to remove organic contaminants, it is thus nearly void-free at the bonding interfaces during heating from 200 to 800ºC. In practice, an optimum treatment time depends on the application requirements.

Figure 1
Direct Bonding of Multiple Curved, Wedged and Structured Silicon Wafers as X-Ray Mirrors
Authors: Landgraf Boris , Gunther Ramses , Vacanti Giuseppe , Barriere Nicolas , Vervest Mark , Girou David , Yanson Alex , Collon Max
Published: February 2020

In this paper we present the technological basis for assembling multiple structured silicon plates using direct wafer bonding. Each individual plate is prebend and bonded on the growing stack, up to 35 plates, that forms a stiff self supporting structure. Throughout the production of the structured plates and the assembly of the curved monolithic silicon structures our focus lies on maintaining pristinely clean and ultra flat surfaces as this is a prerequisite for direct wafer bonding. The application relies on void free bonds imposing stringent requirements for cleanliness that we address with a carefull cleaning process and an automated stacking process in a particle free environment. Several metrology tools have been developed that operate in line to ensure plate to plate alignment, cleanliness and figure accuracy. The process is adaptable to work with plates of various dimensions, have metal coatings, with an intregral wedge and bend radii.
(Invited) A New Materials Concept for High Performance Organic Thin Film Transistors
Authors: Iino Hiroaki , Kunii Masafumi , Hanna Jun-ichi
Published: February 2020

Various organic semiconductor materials for field effect transistors have been developed in these decades, since comparable FET mobility to that of amorphous silicon FETs was demonstrated in Pentacene FETs fabricated with its crystalline thin films. These includes small molecules and polymer materials for solution processes, some of which exhibit high mobility of over 10cm2/Vs. [1], [2] However, the small molecules have remained the problems to be solved such as quality and thermal durability of films, while the polymers need easy control of molecular orientation in a practical way, in addition to reliablities on material preparation from lot to lot and material purification.

We have established a new approach to solve the problems e in the small molecules, that is, utilization of highly-ordered smectic liquid crystals exhibiting self-organization and solid-like nature. 2-Phenyl-7-decyl-benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-10) is a typical example in this approach and exhibits SmE phase at the temperature range from 142oC to 200oC, which allows high thermal durability at that range for thermal processes in device fabrication and high mobility of over 10cm2/Vs in solution processed polycrystalline FETs in bottom-gate and bottom-contact configuration [3]. In addition, we have succeeded in operating the FETs at low voltage lower than 5V with low-dielectric gate materials [4].

In this talk, we will discuss how the liquid crystallinity can solve the problems in small molecules for FET applications, and report the newest results on the FETs fabricated with this new material.

References

[1] K．H．Minemawari，T．Yamada，H．Matsui，J.Y．Tsutsumi，S．Haas，R．Chiba，R．Kumai，T．Hasegawa，Nature，475，pp．364–367 (2011).

[2] H-R Tseng，H．Phan ，C．Luo ，M．Wang ，L．A．Perez ，S．N．Patel，L．Ying ，E．J．Kramer ，T-Q Nguyen，G．C．Bazan ，and A．J．Heeger， Adv．Mater．DOI: 10.1002/adma.201305084 (2014).

[3] H. Iino, T. Usui, and J. Hanna, Nature Commn., 6:6828 | DOI: 10.1038/ncomms7828 (2015).

[4] M. Kunii, H. Iino, and J. Hanna, IEEE Electron Dev. Lett., 37, 486 (2016).

Figure 1
(Invited) Ambipolar Organic-Inorganic Hybrid Perovskite Tfts
Authors: Li Juan , Wu Yuxiang , Xu Jian , Zhang Jianjun
Published: February 2020

Abstract: Organic-inorganic hybrid perovskites have attracted substantial attention because of their excellent physical properties, which enable them to serve as the active material in emerging hybrid solid-state solar cells. Here, we proposed a new type of thin-film field-effect transistor (TFT) with an organic-inorganic hybrid perovskite channel layer. The organic-inorganic hybrid perovskite material has advantages of a high mobility like that of an inorganic semiconductor and the easy process like an organic layer. A TFT using CH3NH3PbI3 as the semiconducting channel was demonstrated. The organic-inorganic hybrid perovskite thin fim with a grain size of 1µm and a smooth surface has been achieved as shown in fig.1. A clear electrical-field induced effect can be observed in the C-V measurements. This type of TFT shows an ambipolar performance in its transfer characteristics (as shown in fig.2 ) and the V shape of the transfer curves is similar to those of other types of ambipolar transistors. The hole and electron field effect mobilities (µFE) are derived as 5.1 cm2/Vs and 5.2cm2/Vs, respectively. The on/off current ratio is nearly 106. This Organic-inorganic hybrid perovskite TFT can be processed by cheap, low-temperature techniques, which suggest that it may be suitable for applications that require low cost, a large area, and the flexibility. Molecular engineering of the organic and inorganic components of the hybrids perovskite is expected to further improve device performance for high speed application.

Figure 1
Highly Stable Zinc Oxynitride Thin-Film Transistors with Field-Effect Mobility Exceeding 100 cm2/Vs
Authors: Kim Yang Soo , Kim Hyun-Suk
Published: February 2020

Ultra definition, large-area displays with three-dimensional visual effects represent the megatrend in the current and future display industry. On the hardware level, such a “dream” display requires faster pixel switching and higher current driving, which in turn necessitate thin-film transistors (TFTs) with high field-effect mobility values. Amorphous oxide semiconductors (AOSs) such as In-Ga-Zn-O have recently emerged as candidate materials that may satisfy the above requirements, but the trade-off between device performance (i.e., field-effect mobility) and stability (i.e., threshold voltage shift) under illumination critically limits their usability. Here we report on amorphous-like Zn-O-N (ZnON) TFTs that are Indium-free but still exhibit high field-effect mobility exceeding 100 cm2V-1s-1. Such devices have a superior stability over conventional AOS devices with respect to light radiation, which can be understood by studying the fundamental electronic band structure of ZnON. It is anticipated that high-mobility and high-stability ZnON TFTs will be extensively applied to next-generation flat-panel displays.
NMOS Logic Inverters Based on Threshold Voltage-Tunable IGZO Transistors
Authors: Liang Lingyan , Yu Jingjing , Wang Mei , Cao Hongtao
Published: February 2020

Enhancement/Depletion (E/D) inverter, as one kind of NMOS inverters, is a promising supplementary technology for complementary logic circuits. Two n-channel bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) TFTs with different threshold voltage (Vth) were utilized to construct the E/D inverter. Tunable Vth was achieved by introducing an ultrathin SnOx capping layer onto the uncovered IGZO back channel surface. According to the composition evolution of the SnOx capping layers, it was believed that loosely bound oxygen in the IGZO can be consumed by the SnOx capping layer, resulting in the Vth negative-shift and enhanced field-effect mobility. The SnOx capping layer also had some effect on the prevention from moisture or oxygen in the air, hence leading to a good stability of the capped TFT when exposed to the air. In addition, the device bias stability was further improved after passivation with SU-8 photo-resist. Finally, an optimized inverter with a voltage gain up to 45.9 was realized. The proposed inverters demonstrated a great potential in the high-voltage-gain, low-cost, and easy-fabrication logic circuits.

Figure 1
Inkjet-Printed Oxide TFTs with Solution-Processed Dual Semiconductors
Authors: Lee Seung-Hyun , Kwack Young-Jin , Lee Jun Seok , Choi Woon-Seop
Published: February 2020

The solution process is a simple and low-cost thin film deposition method that enables a large area coating and high throughput because it can circumvent the need for photolithography and vacuum deposition. Direct patterning can be processed with screen printing, imprinting, ink-jet printing, and electrohydrodynamic-jet printing. Among them, inkjet printing is an attractive technique in device fabrication for the direct pattern writing and precise materials delivery. Recently, spin-coated double-active layer oxide TFTs, in which heterostructured channels, were reported to obtain improved electrical properties at relatively low processing temperatures. However, inkjet printing can provide a patterned active layer structure and give better properties compared to a simple spin-coated one.

To achieve the optimized electrical properties of an inkjet-printed double-active layer, the ZTO TFTs with various compositions of In2O3 solutions were examined. By controlling the annealing temperature and indium content, heterostructured In2O3/ZTO TFTs with improved mobility, threshold voltage and bias stability were obtained. The best electrical properties of the inkjet-printed double-active layer ZTO TFTs were obtained with 0.01 M of In2O3: a mobility of 8.6 cm2/ V s, a threshold voltage of 2.76 V, a subthreshold slope of 0.52 V/dec, and an on-to-off current ratio of 106 . The electrical properties of the inkjet-printed double-active layer oxide TFTs were superior to those of the single-active layered TFTs.
Low Temperature Processed Organic Tfts with Solution-Processable Al2O3 Gate Insulator Using Hydrogen Peroxide
Authors: Park Eung-Kyu , Wang Sihan , Cho Hyeong Jun , Lee So Young , Lee Dong-Hoon , Kim Yong-Sang
Published: February 2020

Organic semiconductors are considered as a replacement for amorphous silicon in thin-film transistor (TFT) applications, since they have shown comparable electrical properties and potential advantages for their compatibility with plastic substrates. However, the high operating voltages of these TFTs still need to be reduced for any practical application. Among dielectric materials, aluminum oxide (Al2O3) appears to be promising due to its high dielectric constant, its robustness and its possibility to be prepared on different type of substrates under easy process. However, high quality and high dielectric constant films generally require annealing temperature above 400 oC, which is not suitable for high-throughput and flexible electronic devices.

In this study, we fabricated the bottom-gate and top-contact organic TFTs on glass substrate. Al gate electrode was deposited by thermal evaporation while Al2O3 thin films, used as gate insulators, were grown by spin coating. Employing hydrogen peroxide (H2O2) in the solution process helps reduce defects at the interface between channel and G/I through strong oxidation and minimize organic chemical-induced defects, such as pores, pin holes, and organic residues, through decomposing organic chemicals at low temperature. The growth of the Al2O3 thin films with H2O2 was studied with various annealing temperatures from 100 ~ 300 oC and solution concentration of 0.1 ~ 1 M. Pentacene was evaporated through shadow mask at a rate of 0.3 Å/s to form a 70 nm thick active layer. Gold source/drain (S/D) electrodes (100 nm) were patterned using shadow mask on the pentacene layer. The performance of the solution processed Al2O3 based TFT was validated using capacitance-voltage and current-voltage analysis.
Design of Bi-Directional Transmission Gate Driver in Amorphous Silicon Technology for TFT-LCD Application
Authors: Zheng Guang-Ting , Liu Po-Tsun , Wu Meng-Chyi , Lu i-Hsiang
Published: February 2020

A novel bi-directional transmission gate driver circuit integrated by amorphous silicon thin film transistors (a-Si:H TFTs) has been proposed. In the proposed design, the noise suppression structure of the gate driver utilized the AC drive inverter to reduce the degradation of the pull down TFTs. The clock frequency of AC signal is 30 Hz, which could reduce dynamic power consumption of the circuit. In addition, the synchronous controlled method in this research could reduce the amount of device in gate driver.The simulated result shows the good output performance of the gate driver and match the circuit design. 

Figure 1
(invited) Metal-Catalyzed Etching of Graphene Layers
Authors: Cheng Guangjun , Calizo Irene , Hight Walker Angela R.
Published: February 2020

We present a comparative investigation on the etching of graphene layers catalyzed by Fe and Cu and demonstrate that their strikingly different etching behaviors are governed by their distinct interactions with carbon. Metal thin films are deposited by sputtering onto mechanically exfoliated graphene, few-layer graphene (FLG), and graphite flakes on a Si/SiO2 substrate. When the sample is rapidly annealed in forming gas or nitrogen, particles are produced due to the dewetting of the metal thin film. The evidence from the low-voltage scanning electron microscopy and Raman spectroscopy reveals that, at 950 oC in forming gas, the particles catalytically etch channels in graphite. No etching is observed on graphite for the Fe thin film annealed in nitrogen, indicating that this graphite etching process is catalyzed by Fe particles through the carbon hydrogenation reaction. Due to the strong Fe-C interactions, graphene and FLG are severely damaged through not only catalytic carbon hydrogenation but also carbon dissolution into Fe alone. By comparing with the etched monolayer and FLG in nitrogen, we identify that, in forming gas, the catalytic etching of monolayer and FLG is through carbon hydrogenation. During carbon hydrogenation, Fe particles are catalytically active in the dissociation of hydrogen into hydrogen atoms and in the production of hydrogenated amorphous carbon through hydrogen spillover. For the Cu case, while no etching takes place for Cu particles on graphite in either gas environment at 1050 oC, Cu particles catalyze the carbon hydrogenation reaction on graphene and FLG. The weak interaction between Cu and graphene, along with the low solubility of carbon in Cu, makes the Cu particles ideal for tracking their etching paths on graphene layers. Further temperature-dependent study shows that no catalytic etching occurs at 850 oC. Both etching from the graphene step edge and on the graphene basal plane are observed for Cu particles at 950 oC and vertical etching takes place in graphite at 1150 oC, resulting in the formation of hexagon pits with all zigzag edges.