Gate Electrode Material Effect on Characteristics of Zirconium-Doped Hafnium Oxide High-k MOS Capacitors
Authors: Lin Wen-Shan , Liu Lingguang , Kuo Yue 
Published: May 2020

The hafnium oxide based high-k dielectric material has been used to replace SiO2 in advanced MOSFETs to lower down the leakage current based on the same equivalent oxide thickness (EOT) of SiO2 [1,2]. The Zr-doped HfO2 (ZrHfO) thin film has many advantages over the undoped HfO2 thin film with respect to the higher permittivity, higher crystallization temperature, lower interface thickness, and lower interface density of states [3-6]. MOS capacitors with EOT less than 1 nm has been successfully prepared using the sputter deposited ZrHfO [5]. The metal electrode material is crucial to the device performance because it could diffuse into the structure to introduce dipoles or new charge trapping sites [7,8]. In this paper, electrical properties of MOS capacitors made of two different gate electrode materials, i.e., copper (Cu) and molybdenum (Mo), were investigated.

MOS capacitors were fabricated on p-type Si (100) 1015 cm-3 wafers. The ZrHfO film was sputtered deposited from a Zr/Hf (12/88 wt. %) target under Ar/O2 (1:1 sccm) at 10 mTorr and 80 W for 12 min. The sample was subsequently annealed at 800°C in N2 for 5 min. Then, a 200 nm thick Cu or Mo electrode film was sputter deposited at 10 mTorr and 80 W, i.e., 20 min for the former and 120 min for the latter. They were etched into round gate electrodes of 200 µm, 300 µm and 400 µm diameters. The Mo electrode was wet etched with a H3PO4/HNO3/CH3COOH/H2O (80:5:5:10) solution. The Cu electrode was etched with a plasma-based etch process of which the detailed process condition can be found in refs [9]. Then, the sample was treated with a post metal annealing (PMA) step at 250°C in N2 for 10 min. Samples without the PMA treatment, i.e., controlled samples, were also prepared and measured for comparison. Electrical properties, e.g., EOT, VFB
, Dit
, and Qot
, of the sample were extracted from the C-V curve using the method described in ref 10.

Figure 1 shows the C-V hysteresis curves of Mo gated capacitors (a) before and (b) after PMA. The samples were measured with the gate voltage (Vg
) swept from -3 V to 3 V (forward) and then back to -3 V (backward). The control sample shows a large flat-band voltage shift ( ) of 1.4881 V while the annealed sample shows a much smaller ’s of 0.083 V. Also, the Qot
is decreased from 9.611011 to 1.091011 cm-2 for the control and annealed samples [10]. The long Mo sputtering time may induce hole-trapping defects in the high-k film or at the high-k/Si interface. In addition, it was reported that the Mo gate could react with high-k film to form new bonds that reduced the work function [11]. The 250˚C annealing step can effectively reduce defects in various parts of the capacitor.

Figure 2 shows the C-V hysteresis curves of Cu gated capacitors (a) before and (b) after PMA. Before PMA, the C-V curve is similar to that of a good capacitor with a low of 0.012 V, which corresponds to a low charge trapping density [10]. However, after PMA, the C-V curve distorted. It shows the strong inversion phenomenon, which indicates the possible high electron concentration at the interface exceeding the dopant concentration near the wafer interface [12]. Since Cu can easily diffuse through a dielectric film [13], it is possible that Cu diffuses through the high-k gate dielectric during the PMA step. Cu in the high-k film may exist in the CuOx form, which changed the charge trapping states and locations. More discussions on the above mechanism will be presented.

Lingguang Liu acknowledges the financial support of National Natural Science Foundation of China (Grant Number:61771382), China Scholarship Council (No. 201806280283) and the Shaanxi International Science and Technology Cooperation and Exchange Program (2018KW-034).

1. Kang, et al., IEEE EDL, 21, 181 (2000).

2. I. Hegde, et al., JAP, 101, 074113 (2007).

3. Kuo, ECST, 3, 253 (2006).

4. Kuo, et al., ECST, 1, 447 (2006).

5. Yanet al., ECS SSL, 10, H199 (2007).

6. Luo, et al., APL, 89,072901 (2006).

7. Ravindran, et al., APL, 89, 263511 (2006).

8. C. Vezzoli, et al., Ceram. Int., 23, 105 (1997).

9. Kuo and S. Lee,APL, 78, 1002 (2001).

10. H. Nicollian and J. R. Brews, MOS Physics and Technology, p424, Wiley, New York (1982).

11. Ha, et al., JJAP, 42, 1979-1982 (2003).

12. Ytterdal, et al., Device Modeling for Analog and RF CMOS Circuit Design, p4, Wiley (2003).

13. D. McBrayer, et al.,JES, 133, 6,1242 (1986).

Figure 1