(Invited) Smartphones: Driving Technology to More than Moore 3-D Stacked Devices/Chips and More Moore FinFET 3-D Doping with High Mobility Channel Materials from 20/22nm Production to 5/7nm Exploratory Research
Authors: Borland John O 
Published: February 2020

Today smartphone ICs are driving technology to More Moore 3-D device scaling and More Than Moore 3-D stacked devices with >1.24B smartphones sold in 2014 accounting for >27% of all ICs.  The expected increase in smartphone application processor (AP) demand in 2015 (Samsung Exynos 7 for Galaxy S6 and Apple A9 for iPhone 6s/7) is driving the rapid ramp to 14/16nm technology node 3-D FinFET devices at foundries, 3-D memory devices such as 128Gb NAND Flash memory devices with 32-layers and 3-D stacked chips for form factor with >40% package area saving.  Intel was first to production with 3-D bulk-FinFET devices at the 22nm technology node in 2011 and reported their SOC version for Chinese low-end smartphone market.  Intel’s 2nd generation bulk-FinFET devices at 14nm node was introduced in Aug 2014 with their SOC version to follow.  In Sept 2012 iPhone 5 was first to incorporate Sony’s 8M pixel 3-D stacked backside CMOS image sensor for rear-facing camera.  In April 2015 Samsung Galaxy S6 incorporated 14nm technology node 3-D FinFET devices in the Exynos 7 Octa application processor and first 3-D ePOP (embedded package on package) which stacks AP+DRAM (3Gb LPDDR3)+Flash(128/64/32Gb)+eMMC (embedded multi-media card)+controller saving 40% area and use Sony’s 16M pixel 3-D stacked back-side CMOS image sensor for rear-facing camera and 5M pixel RWB image sensor for front-facing camera.  Apple will introduce the iPhone 6s/7 in Sept 2015 with A9 application processor using 3-D FinFET devices with Samsung/Foundry 14nm technology node and TSMC 16FF+.  10nm technology node is expected in 2016 with higher mobility SiGe or Ge channel material then 7nm node in 2018 and gate-all-around nano-wire by 5nm node in 2020.  

                           To understand 3-D FinFET doping and high mobility channel material this paper will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.  3-D 8o tapered FinFET S/D extension conformal doping was achieved with high tilt ion implantation at >45 degree.  Highest retained dose and improved Fin sidewall line-edge-roughness (LER) on the atomic level can be realized with Hydrogen annealing surface passivation.  High dopant activation is also achieved with advanced annealing SPE techniques of amorphous implanted junctions.  Other 3-D dopant methods such as plasma implantation, knock-in dopant and deposition doping with diffusion including monolayer doping were not successful due to poor dopant activation and severe surface dopant loss.  FinFET channel mobility enhancement at 22nm node used (511) plane taper Fin with 55% eSiGe S/D compressive strain for PMOS and amorphous implant SPE residual stacking fault defect S/D tensile stressor for NMOS.  For 14nm node taller vertical Fins without the (511) taper and still 55% eSiGe S/D for PMOS and now eS/D for NMOS which is full of stacking fault defects.  At the 10nm or 7nm node direct higher mobility Fin/channel material (SiGe, Ge or III-V) is expected to be introduced followed by exploratory research of gate-all-around nanowire for 5nm technology node.  25% SiGe to 100% Ge high mobility Fin-channel material on Si wafers will be realized by traditional gas/vapor phase epitaxial growth techniques by chemical vapor deposition (CVD) in blanket, selective growth including aspect ratio trapping, Ge condensation or an alternative liquid phase epitaxial (LPE) regrowth of an amorphous material layer by melt solidification.  At 5nm node Si, SiGe or Ge nano-wire gate-all-around devices.  Finally a discussion on dopant activation in high mobility Ge and SiGe material with low junction leakage.