bluuebunny/crossref_metadata_2025 huggingface dataset:
Backside Imaging and AFM Profiling of Tunnel Oxide, Poly 1, ONO and Poly 2 Layers on Flash Devices
Authors: Upadhyaya Kaushal , Blacker Patrice W.
Published: December 2020

With increasing density of metal interconnects and shrinking device sizes with each process generation, there has been a growing interest in the Flash failure analysis (FA) community to approach the devices from the backside. Looking at the process layers like Tunnel Oxide, Poly 1 (floating gate), Oxide Nitride Oxide (ONO) and Poly 2 (control gate) from the backside provides useful information about failure location, failure type and failure mechanism which may be obscure from the front side. This work describes a novel combination of mechanical polishes and chemical etches to delayer Intel’s Flash memory devices from the backside to enable viewing of the bottom of the previously mentioned process layers. In addition to Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) has been attempted to gather more information about the surface details. This technique has been used successfully on Intel’s latest 90 nm flash process and has been verified on earlier process generations.
Diffractive Lenses for High Resolution Laser Based Failure Analysis
Authors: Zachariasse Frank , Goossens Martijn J.
Published: December 2020

In this paper we present a new method to increase the lateral resolution available in laser scanning failure analysis tools. By fabricating a diffractive lens on the back side of the die, the area of the circuit of interest, directly underneath the lens, may be studied with a lateral resolution up to 3.5 times better than without the lens. This method is easily implemented with standard equipment already present in most failure analysis laboratories, and overcomes some significant problems encountered with alternative resolution enhancing schemes.
Scanning Optical Microscopy Application in Micron® Memory Devices
Authors: Yuan Wong Yaw , Poh T.L. Edmund , Lam David
Published: December 2020

The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.
Advanced Electrical Characterization of 90 nm Soft Bit Failure by Nano Probing Technique
Authors: Giret Christelle , Faure Damien
Published: December 2020

The Soft Bit failure (Single Bit Failure sensitive to voltage) of a 90nm SRAM cell presented a difficult challenge for the Failure Analysis (FA) group. Physical analysis of these Soft SRAM failures did not show any visual defects; therefore the FA required an accurate electrical characterization. The transistor characteristics of the failing SRAM transistors are needed in order to speculate on the possible failure mechanism. The Nano-Probing technique performed at Nice Device Failure Analysis of Laboratory (NDAL) allowed us to identify anomalies of I/V characteristics like Vt imbalance, low Gain, asymmetrical Vt, ID (Drive current) and Ron. Case studies of an asymmetry phenomenon reported here lead to a correlation between the failure mode and the electrical measurements. This paper demonstrates a suitable electrical methodology and characterization by Nano-Probing in order to successfully manage a FA approach on this type of failure.
Guideline for Interpreting IR Laser Stimulation Signal on Semiconductors for Materials and for Improving Failure Analysis Flow
Authors: Firiti A. , Haller G. , Beaudoin F. , Perdu P. , Lewis D. , Fouillat P.
Published: December 2020

Infra-red Thermal Laser Stimulation (TLS) signatures obtained on semiconductor materials can be difficult to interpret and to distinguish from signatures from metallic materials. Investigations presented here consist in the study of TLS signals on unsilicided/silicided polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection and to determine the ideal silicon thickness for sample preparation. This study also completes our methodology based on the TCR parameter which aims at improving defect localization in the depth (Z) of circuitry. As it will be shown through failure analysis case studies, this methodology increases the physical analysis success rate and reduces the turnaround time.
Lock-In Assisted Soft Defect Localization (LIA-SDL) and Its Application in Scan Shift Problems
Authors: Qian Zhongling , Brillert Christof , Burmer Christian , Grützner Markus
Published: December 2020

A new localization method called LIA-SDL is introduced and applied to scan shift problems. The method combines local thermal stimulation technique with lock-in technique applied to periodical test pattern. The localization capability on soft defects is shown in comparison with SDL. Same localization results are obtained. LIA-SDL technique requires no special LSM (Laser Scan Microscope) facilities and is quite easy to handle. Limits and prospects of this new methodology are shown at several analysis examples.
Unique Failure Modes from use of Sn-Pb and Lead-Free (mixed metallurgies) in PCB Assembly: Case Study
Authors: Toth Frank , Shade Gary F.
Published: December 2020

Printed Circuit Board (PCB) assemblies are moving toward lead-free (LF) alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures.
Stacked Die Analysis Using C-mode Scanning Acoustic Microscope
Authors: Na Li , Khan Jawed , Adams Lonnie
Published: December 2020

For stacked die package delamination inspection using C-mode acoustic microscope, traditional interface and thorough scan techniques cannot give enough of information when the delamination occurs in multi-interfaces, and echoes from adjacent interfaces are not sufficiently separated from each other. A thinner thickness in the stacked-die package could complicate C-mode scanning acoustic microscopy (CSAM) analysis and sometimes may lead to false interpretations. The first objective of this paper is to briefly explain the CSAM mechanism. Based on that, some of the drawbacks of current settings in detecting the delamination for stacked-die packages are presented. The last objective is to introduce quantitative B-scan analysis mode (Q-BAM) and Zip-Slice technologies in order to better understand and improve the reliability of detecting the delamination in stacked-die packages. Therefore, a large portion of this paper focuses on the Q-BAM and Zip-Slice data acquisition and image interpretation.
Method of Detecting Trace Metal Contamination in Thick-Film SOI Device
Authors: Goto Yasunori , Eguchi Hiroomi , Iida Masaru
Published: December 2020

In the automotive IC using thick-film silicon on insulator (SOI) semiconductor device, if the gettering capability of a SOI wafer is inadequate, electrical characteristics degradation by metal contamination arises and the yield falls. At this time, an automotive IC was made experimentally for evaluation of the gettering capability as one of the purposes. In this IC, one of the output characteristics varied from the standard, therefore failure analysis was performed, which found trace metal elements as one of the causes. By making full use of 3D perspective, it is possible to fabricate a site-specific sample into 0.1 micrometre in thickness without missing a failure point that has very minute quantities of contaminant in a semiconductor device. Using energy dispersive X-ray, it is possible to detect trace metal contamination at levels 1E12 atoms per sq cm. that are conventionally detected only by trace element analysis.
The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits
Authors: Kimball Mark
Published: December 2020

This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.
Dynamic Electroluminescence Imaging (DEI) as an “Optical Oscilloscope” Probe
Authors: Hulse John , Sarault Keith , Simard-Normandin Martine
Published: December 2020

Dynamic Electroluminescence Imaging (DEI) is a technique used to observe semiconductor devices as they operate. Much like a traditional oscilloscope, the technique delivers waveform information that is useful for assessing the operation of the circuits that comprise a device. It can be thought of as a non-contact “optical oscilloscope probe”. The technique has two major advantages over traditional electrical oscilloscope probing. The technique is noninvasive and has a theoretical bandwidth approaching 100 GHz. This means that very fast signals can be observed without unduly loading or otherwise interfering with the circuitry under test. Moreover, the characterization of signals at individual nodes along a signal path allows problems that arise from intervening interconnects and transmission lines to be identified. This paper will show several examples of the radio frequency (RF) measurement capabilities of this technique that have been demonstrated in our laboratory.
Root Cause Analyses of Metal Bridging for Copper Damascene Process
Authors: Song Z. G. , Neo S. P. , Loh S. K. , Oh C. K.
Published: December 2020

New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.
Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors
Authors: Anderson M.L. , Tangyunyong P. , Hill T.A. , Nakakura C.Y. , Headley T.J. , Rye M.J.
Published: December 2020

By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.
Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs
Authors: Burmer Christian , Erb Hans-Peter , LemMger Andreas , Gruetzner Markus , Schwemboeck Thomas , Trost Stefan
Published: December 2020

During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.
Deprocessing of Integrated Sealing Structures from MEMS Devices for Failure Analysis
Authors: Barbieri Thomas J. , Vandemeer Jan
Published: December 2020

Freescale Semiconductor is employing a new, multi-layer integrated seal (IS) on its next generation accelerometers. The IS, which encloses the moveable sensing element, consists of alternating layers of poly-Si and PSG. A technique needed to be developed to remove the integrated seal in order to permit failure analysis. Mechanical methods were attempted first, but these resulted in severe damage to the sensing element. Chemical deprocessing was considered, but eventually abandoned because there seemed to be no way to protect the sensing elements from the wet etchants that would be used on the IS. Eventually, Reactive Ion Etching (RIE) with an Inductively Coupled Plasma (ICP) source proved to be a successful means for removing the IS without impacting the sensing element. As the design of the integrated seal underwent multiple redesigns, the removal process was successfully modified multiple times to comply with these changes. By using the right gases in the correct order, a high level of selectivity was maintained, allowing for removal of successive layers of different materials (poly-Si, PSG) without harming the sensing element. After removal of some IS designs, a wispy residue was observed on the sensing element and remaining IS support pillars. Chemical analysis identified this material as a by-product of the RIE process, and methods were devised to eliminate it.
Recent Developments in TEM Applications for the IC Industry
Authors: Fu L. F. , Wang Y. C. , Jiang B. , Shen F. , Strauss M. , Van Leer B. , Senowitz C. , Buxbaum A.
Published: January 2021

Recent developments in aberration-corrected transmission electron microscopy have drawn much attention from the semiconductor characterization community. Two new developments in transmission electron microscopy, image aberration correctors and probe aberration correctors, are discussed in term of their applications in characterizing gate oxide dielectrics for the IC industry.
Automated Serial-Section Polishing Tomography
Authors: Hunt J.A. , Prasad P. , Raz E.
Published: January 2021

Tomographic reconstruction of a wide range of materials can be accomplished via mechanical polishing serial-sectioning – alternately polishing away material and imaging the remaining polished surface with optical (or electron) microscopy. Under computer control it is possible to acquire 2-D images of hundreds of sections without user intervention and assemble them for 3-D visualization and measurements. In general, the resulting 3-D images permit significantly better understanding of the structure of complex systems than would be possible with a few strategically acquired 2-D images at various depths. Herein we report what we believe is the first general implementation of automated Serial-Section Polishing Tomography (SSPT) and reconstruction using light microscopy.
New Developments in High-Resolution X-ray Computed Tomography for Non-Destructive Defect Detection in Next Generation Package Technologies
Authors: Pacheco Mario , Goyal Deepak
Published: January 2021

The development of a next generation high-resolution x-ray Computed Tomography (CT) tool and its applications are reported in this paper. Some of the key features are region of interest capability, improved time-to-data, improved usability, and data collection automation capability. We also discuss the key technical challenges that are faced by x-ray CT technology. Critical cases that are hard or not possible to isolate by alternative methods are also discussed. Examples include Controlled Collapse Chip Connection (C4) bump cracking and “invisible” non-wetting analysis, ball grid array (BGA) solder joint cracking, and wirebond microcracking and wirebond shorting, as well as demonstration of progressive testing capability.
Flip-Chip Bump Interface Failure Mechanisms In Plastic BGA Packages and Failure Analysis Process Flow
Authors: Wang Zhaofeng
Published: January 2021

The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.
PCB Pad Cratering – Characterization Techniques and Challenges
Authors: Parupalli Satish , Newman Keith , Ahmad Mudasir
Published: January 2021

Some standard characterization techniques (solder ball pull, solder ball shear, etc.) exist for the assessment of solder ball mechanical fracture strength; however, it is not clear if these test methods would also provide characterization of printed circuit board (PCB) pad cratering susceptibility. This paper provides an overview of test methods being investigated by a PCB pad crater industry working group. The scope of this industry working group is two-fold: standardization of PCB pad crater crack characterization and measurement methods and development of a quantitative quality metric for PCB pad cratering. Though the test methods were successful in creating pad craters; there was not enough distinction between the various laminate material types based on the output parameters. Based on the readings from Phase 1 study and available literature, the team is in the process of completing the Phase 2 study which will be reported at a later stage.
Stitch-Bond-Shearing in Optoelectronic Devices, Caused by Lead-Free-Wave-Soldering – Do We Need Improved Wire-Bonding Methods?
Authors: Jacob Peter , Rütsch Michael
Published: January 2021

This case study shows a typical example of a manufacturing-chain-induced reliability problem. All participants of the chain do their work within specifications, but, looking at the system level, severe reliability problems have been observed. In order to get back into the system-level process window, several corrective actions are possible. In this case, the most promising approach is an improvement of the stitch bond robustness, combined with a clear user specification.
Lead-Free Solder/Gold Metallization Interdiffusion in Electronic Interconnects – Challenges and their Control
Authors: Asrar Nausha
Published: January 2021

While considerable amount of researches and investigations have been made on lead-free solder joint reliability, limited number of literatures are available on the effect of gold content on lead-free solder joint performance. The challenges of lead-free solder/gold metallization interdiffusion during high temperature application/test are: gold embrittlement, intermetallics growth, void formation, and tin-whisker formation. Tin whiskers causing system failures in earth and space-based applications have been reported. This paper illustrates a few case histories of such challenges. The results confirmed that the synergistic effects of void formation, intermetallic compounds formation due to the thick gold plating, and coefficient of thermal expansion mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components.
A Logical Problem Solving Process for High Via Resistance Root Cause Analysis
Authors: Li K. , Liu P. , Teong J. , Lee M. , Yap H. L.
Published: January 2021

This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.
Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques
Authors: Song Z. G. , Ippolito S. B. , McGinnis P. J. , Shore A. , Paulucci B. , Kane T. , Tenney M. P. , Trudeau F. G. , Kozaczka A. W.
Published: January 2021

It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.
Fast Root Cause Analysis Based on Electrical Defect Localization
Authors: Schmidt Michael , Dworkin Larry , Hess Christopher , Squcciarini Michele , Yu Shia , Burrows Jonathan
Published: January 2021

The ability to rapidly perform root cause analysis (RCA) on yield limiting defects is critical to a fab’s ramp. Here we present two methodologies for RCA using specially designed high density test structure arrays and a FIB/SEM DualBeam. These methodologies have been proven to identify the root cause of both hard and soft electrical failures. Correlation between electrical test results and the yield-impacting defects are presented.
Failure Analysis for Gate Oxide Breakdown
Authors: Chen Xianfeng , Li Ming , Guo Qiang , Chien Kary , Gao YanBo
Published: January 2021

Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.
Techniques for Identification of Silver Migration in Plastic Encapsulated Devices Assembled with Molding Compound Containing Red Phosphorus Flame Retardant Material
Authors: Hylton Ronald R.
Published: January 2021

This paper describes the electrical signatures and failure analysis techniques used to identify plastic encapsulated devices that have failed due to silver migration. This migration, which produces resistive leakages between adjacent pins, has been associated with molding compounds that utilize red phosphorous as a flame retardant material. A description of the failure mechanism is also presented.
An Analysis of Tungsten FIB-Fabricated Via Resistance
Authors: Niles David W. , Meyer Jay , Kee Ronald W. , DiBattista Michael
Published: January 2021

We present an analysis of tungsten vias fabricated by a focused ion beam with regard to the understanding of circuit editing strategies. The growth rate of W is ~10 times faster in high aspect ratio vias than on flat surfaces, and W in vias has 4 at. % more C but only one-tenth the Ga of surface-deposited W. We propose that vias act like small Faraday cups, trapping the energy of the Ga+ ions and the reaction byproducts to enhance the growth rate of W and to increase the C to W ratio in vias compared to flat surfaces. The resistivity of W in the vias determined by a least squares fit to resistance data is 250μΩ-cm, unchanged from the resistivity of W deposited on a flat surface. The resistances of the vias fabricated in a SiO2 layer to contact an underlying Al sheet layer fit well to either of two models: 1) an effective area model that invokes resistive via sidewalls that do not participate in conduction, and 2) an contact resistance model that invokes tapered vias with a constricted W/Al contact area.
Insulator Deposition for Through Conductor Editing
Authors: Richardson Chris , Martin Mark , Malik Tahir , Barone Jerrold P.
Published: January 2021

Circuit Edit (CE) through a conductor requires an insulator to isolate the connection transiting the conductor. We investigate several recipes to determine not just the optimum recipe but also the latitude to provide a means of throughput optimization for a given edit requirement. The results show that trade-offs in deposition rate, robustness and isolation quality can be made to enable this throughput optimization.
Photon Emission Spectral Signatures of AlGaN/GaN HEMT for Functional and Reliability Analysis
Authors: Glowacki Arkadiusz , Boit Christian , Lossy Richard , Würfl Joachim
Published: January 2021

Non-degraded and degraded AlGaN/GaN HEMT devices have been characterized electrically and investigated in various operating modes using integral and spectrally resolved photon emission (PE). In degraded devices the PE dependence on the gate voltage differs from the non-degraded devices. Various types of dependencies on the gate voltage have been identified when investigating local degradation sites. PE spectroscopy was performed at various bias conditions. For both devices broad spectra have been obtained in a wavelength regime from visible to near-infrared, including local performance variations. Signatures of the degradation have been determined in the electrical characterization, in integral PE distribution and in the PE spectrum.
A Novel OBIRCH Fault Isolation Method to Locate the Leakage Failure Point
Authors: Huang Chi-Lin , Shu Yu Hsiang
Published: January 2021

Conventional isolation techniques, such as Optical Beam Induced Resistance Change (OBIRCH) or photoemission microscopy (PEM) frequently fail to locate failure points when only applied to power pin of the semiconductor device. In this paper, a novel OBIRCH failure isolation technique is utilized to detect leakage failures. Different test conditions are presented to identify the differences in current when all input pins are pulled high in an OBIRCH system. In order to verify a failure point, it is necessary to perform electrical analysis of the suspected failure point in the failing sample. In general, Conductive Atomic Force Microscope (C-AFM) and a Nano-Prober is sufficient to provide the electrical data required for failure analysis. Experiment results, however, prove that this novel OBIRCH failure isolation technique is effective in locating the failure point, especially for leakage failures. The failure mechanism is illustrated using cross-sectional TEM.
Dynamic Laser Stimulation Technique for Device Qualification Process
Authors: Deyine-Barth A. , Perdu P. , Benetti G. , Sanchez K. , Battistella F. , Lewis D.
Published: January 2021

A key point to guarantee electronic device quality is device qualification. This part of the process is a significant contributor to the time and cost of the development and production of any electronic device. A device is required to perform a task and its operational lifetime is a key issue for the end user. The more sensitive the qualification technique is, the faster marginalities in the device parameters could be observed. Dynamic Laser Stimulation techniques fill this requirement and could be used in conjunction with traditional qualification procedures.
Lead Frame Metal Migration in an Encapsulated IC Package
Authors: Eslinger William
Published: January 2021

This case study details a latent integrated circuit (IC) failure mechanism caused by the migration of silver (Ag) inside the encapsulated package of a CMOS (complementary metal-oxide-silicon) device. The plating of the lead frame was the source of the migrated silver, which was redeposited along the interface between the die attach epoxy and the plastic encapsulate. The resulting metallic ‘stringers’ bridged adjacent lead frame legs over distances greater than 150 μm and created relatively low-resistance paths capable of carrying 100’s of micro-amps.
Reliability for Pure CMOS One-Time Programmable Memory Using Gate-Oxide Anti-Fuse (eFuse)
Authors: Wakai Nobuyuki
Published: January 2021

The reliability of a pure CMOS One-time Programmable (PCOP) Memory was investigated. The memory is programmed with and anti-fuse formed by the breakdown of the thin gate oxide. The results of reliability stress tests show that the PCOP memory is stable and reliable for normal using environmental conditions.
Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering
Authors: Moor Tony , Malyanker Eli , Raz-Moyal Efrat
Published: January 2021

The idea behind Destructive Semiconductor Reverse Engineering (DSRE) is to investigate a device in part or as a whole using many of the techniques employed in the physical failure analysis (PFA) field. The device is usually examined for intellectual property/patent protection or competitive analysis purposes. This paper presents a technique for the full layer-by-layer deprocessing of a single semiconductor device using purely mechanical polishing for DSRE or FA. It describes a step-by-step method developed by Raw Science/Datel Design and Development and Gatan for the reliable, purely mechanical deprocessing of individual dice. The paper presents the two modifications made to the process to virtually eliminate the edge effects. A computer controlled mechanical polishing system coupled with a unique customized process allows for the investigation of those one of a kind samples as a whole with 100% success rate.
Characterization and Failure Analysis of Wafer Bonded Devices and Unfilled Through-Silicon-Vias (TSVs)
Authors: Cassidy C. , Kraft J. , Koppitsch G. , Brandlhofer E. , Steiner M. , Schrank F. , Erwin D. , Raz-Moyal E.
Published: January 2021

This paper is concerned with characterization and failure analysis challenges posed by 3D integration of semiconductor devices, with a particular focus on wafer bonded components and Through Silicon Vias (TSV). Requirements for sample preparation are discussed, along with advantages and limitations exhibited by various different techniques. Analysis examples with real devices are presented, along with successful sample preparation solutions enabled by a precision polishing toolset.
Timing Failure Debug Using Debug-Friendly Scan Patterns and TRE
Authors: Burmer Christian , Guo Ruifeng , Cheng Wu-Tung , Lin Xijiang , Benware Brady
Published: January 2021

In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.
Deterministic Localization and Analysis of Scan Hold-Time Faults
Authors: Hwang Jaecheol , Kim Daegyu , Seo Namsik , Lee Euncheol , Choi Wooseong , Jeong Yeongtaek , Orbon J. , Cannon S.
Published: January 2021

This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper also presents a method to detect multiple hold-time faults in the chain using auto generated pattern, real-time on the tester. The approach includes validation of the hold-time fault model, characterization of the failure behavior in terms of Vdd and data dependencies and finally localization to a cone of logic including the data paths and the clock trees. This method of hold-time localization is organized into three steps. First, the chain integrity test is run at the safe voltage. Second, a set of new patterns is created and run at the failing voltage. Finally, the data is shifted out and compared with the simulation result. The data provides the locations of all of the hold-time faults for the selected failing voltage. Combined with silicon voltage probing, the technique allows the analysis to localize the faults and to measure timing slack on sub-nets in the failing circuitry. This allows very close correlation between timing models and silicon performance leading to more robust design/process matching.
Combining Refractive Solid Immersion Lens and Pulsed Laser Induced Techniques for Effective Defect Localization on Microprocessors
Authors: Quah A.C.T. , Goh S.H. , Ravikumar V.K. , Phoa S.L. , Narang V. , Chin J.M. , Chua C.M. , Phang J.C.H.
Published: January 2021

The spatial resolution and sensitivity of laser induced techniques are significantly enhanced by combining refractive solid immersion lens technology and laser pulsing with lock-in detection algorithm. Laser pulsing and lock-in detection enhances the detection sensitivity and removes the ‘tail’ artifacts due to amplifier ac-coupling response. Three case studies on microprocessor devices with different failure modes are presented to show that the enhancements made a difference between successful and unsuccessful defect localization.
Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique
Authors: Kim Suk Min , Lee Jung Ho , Lee Jong Hak , Kim Hyung Ki , Chang Myung Sick , Lee Jung Hoon , Hong Sung Joo
Published: January 2021

We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.
Low Voltage, Low Current AFP Characterization of Non-Visible Soft Transistor Defects
Authors: Mulder Randal , Subramanian Sam , Chrastecky Tony
Published: January 2021

This paper presents case studies that examine low voltage, low current electrical characterization and analysis of data that could help identify root cause failure mechanisms for soft transistor failures, providing a review of Vt shifts and blocked LDD implants review. The case studies demonstrate the importance of getting the most information possible out of all aspects of the nanoprobe electrical characterization results for failing transistors. Technology computer aided design (TCAD) modeling of transistor defects will be a useful tool for the nanoprobe analyst to identify the subtle defects that can only be identified through careful electrical characterization in conjunction with process analysis and experiments by the manufacturing facility. However, modeling at the transistor level has its difficulties. The key will be to build a library of electrical signatures with corresponding defects as they are discovered.
Investigation on Focused Ion Beam Induced Damage on Nanoscale SRAM by Nanoprobing
Authors: Hendarto E. , Toh S.L. , Tan P.K. , Goh Y.W. , Cai J.L. , Ma Y.Z. , Mai Z.H. , Lam J. , Sudijono J.
Published: January 2021

As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the electrical parameters of the pull-up (PU), pull-down (PD) and pass-gate (PG) transistors of 6-Transistor Static Random Access Memory (6T SRAM) cells.
A Study of Pad Contamination Defect and Removal
Authors: Mohammad K.A. , Liu L.J. , Liew S.F. , Chong S.F. , Lee D.G. , Lee S.F. , Lee B.C.
Published: January 2021

The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.
Transient Latch-Up Analysis of Power Control Device with Combined Light Emission and Backside Transient Interferometric Mapping Methods
Authors: Heer M. , Pogany D. , Street M. , Smith I. , Riedlberger F. , Bonfert D. , Gieser H. A.
Published: January 2021

A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.
Dopant Analysis on Advanced CMOS Technologies
Authors: Siegelin Frank , Dübotzky Anja , Danzfuss Bodo , Schömann Stephan
Published: January 2021

This paper gives an overview of methods for imaging the distributions of dopant in semiconductor devices. Top view imaging by means of NanoSIMS and chemical etching will be discussed as well as cross section imaging on etched transmission electron microscopy (TEM) lamellas and Scanning Spreading Resistance Microscopy (SSRM).
3-D Image Reconstruction in the Scanning Electron Microscope
Authors: Vanderlinde William E.
Published: January 2021

This paper demonstrates that an SEM stereo-pair can be accurately translated into a Digital Elevation Model (DEM) using commercial software running on a desktop computer. The DEM is easy to view without any special equipment and can provide accurate measurements of the sample in all three dimensions. Vertical height measurements with high accuracy can be obtained from the elevation model when the sample has sufficient surface texture and a uniform baseline.
NATIONAL FINANCIAL SYSTEM ANALYSIS IN TERMS OF THE COMPLEX SYSTEMS THEORY
Authors: Lopotenco Viorica
Published: December 2020

The recession caused by the pandemic and the vulnerabilities faced by the entire international monetary system and the national financial systems requires a particular approach to analyzing the current situation and the design of new developments. Based on these arguments, we set out to investigate national financial systems from the perspective of complex systems theory.Following the research, we concluded that understanding the nature and characteristics of the manifestation of synergistic effects allows organizing the financial system's management at a new quality level, based on the concepts of discretion and stability of development trajectories of the world economy.
Teaching Arabic for Professional Purpose: Develop a Pilot Course for Humanitarian Volunteers in Malaysia (Mengajar Bahasa Arab untuk Tujuan Profesional: Mengembangkan kursus perintis untuk sukarelawan kemanusiaan di Malaysia)
Authors: Ali Asem Shehadeh
Published: January 2021

Presently there are very few Malaysian Volunteers. The former Prime Minister of Malaysia, Dato 'Sri Najib Abdul Razzaq, had encouraged volunteerism as a multi-ethnic Malaysian social lifestyle, to make Malaysia a center and volunteer model. Showing statistics released by UNHCR in Malaysia in October 2018, there are about 8645 registered refugees in Malaysia coming from Arab countries including Yemen, Syria, Iraq and Palestine. The refugees are increasing every day, and this situation paves the way for Malaysians to participate in voluntary work. This study aims to achieve the following objectives; Statement of language requirements in the field of humanitarian work, to demonstrate skills to focus on humanitarian volunteers and to design the standard statement of Arabic language for professional purposes in the field of humanitarian work.
Keywords: Arabic for special purposes, Arabic for Professional Purposes, humanitarian volunteers, Curriculum.
Abstrak
Pada masa ini terdapat sangat sedikit Sukarelawan Malaysia. Mantan Perdana Menteri Malaysia, Dato 'Sri Najib Abdul Razzaq, telah mendorong kesukarelaan sebagai gaya hidup sosial pelbagai etnik Malaysia, untuk menjadikan Malaysia sebagai pusat dan model sukarelawan. Menunjukkan statistik yang dikeluarkan oleh UNHCR di Malaysia pada Oktober 2018, terdapat sekitar 8645 pelarian berdaftar di Malaysia yang berasal dari negara-negara Arab termasuk Yaman, Syria, Iraq dan Palestin. Pelarian semakin meningkat setiap hari, dan keadaan ini membuka jalan bagi rakyat Malaysia untuk mengambil bahagian dalam pekerjaan sukarela. Kajian ini bertujuan untuk mencapai objektif berikut; Pernyataan keperluan bahasa dalam bidang pekerjaan kemanusiaan, untuk menunjukkan kemahiran untuk menumpukan perhatian kepada sukarelawan kemanusiaan dan merancang pernyataan standard bahasa Arab untuk tujuan profesional dalam bidang pekerjaan kemanusiaan.
Kata Kunci: Bahasa Arab untuk tujuan khas, Bahasa Arab untuk Tujuan Profesional, sukarelawan kemanusiaan, Kurikulum.
الأبعاد المقاصدية في منهجية مكافحة الجريمة في النظام الإسلامي
Authors: الغرابلي رزق , هنداوي حسن
Published: January 2021

يسلط هذا البحث الضوء على الأبعاد المقاصدية في منهجية مكافحة الجريمة في النظام الإسلامي، فالإسلام تفرّد بمنهج ربّاني في الوقاية من الجريمة وعلاجها على أسسٍ أخلاقية، فاستبقت الشريعة إمكانية وقوع الجريمة بجملة من التشريعات الأخلاقية الكفيلة بمنع وقوعها، كما عالجت آثارها بأسس أخلاقية أخرى كفيلة بإصلاح الجاني وجبر نفس المجني عليه، وغيرها، بما يتوافق مع مقاصد الشارع الحكيم في تحقيق مصالح العباد في العاجل والآجل.

ويردّ هذا البحث على من يتهم الإسلام بالقوة والعنف والقسوة في التعامل مع المجرمين إجمالا، ويبرز منهجًا يعد الأرقى على مستوى المناهج التي تعاملت مع أنواع الإجرام كافة، يتحقق معه مقصود الشارع في جلب مصالح العباد ودرء المفاسد عنهم. ومن أجل تحقيق أهدف البحث اتبعت المنهج الاستقرائي لطائفة من الشواهد المتعلقة بالموضوع سيما من القرآن والسنة، ثم المنهج الاستنباطي لاستخراج القيم الأخلاقية والأبعاد المقاصدية المتضمنة في المنهج الإسلامي في مكافحة الجريمة، مستعينًا بالمنهج التحليلي في المواضع التي احتاجت إلى ذلك.
Curriculum Integration based on the Story of Prophet Musa and the Righteous Man in Chapter al-Kahf (Integrasi Kurikulum Berdasarkan kisah Nabi Musa A.S dan Seorang Pemuda Soleh (al-Khidr) di dalam Chapter Al-Kahf)
Authors: Abdulmaelk Yahya Al-Hidabi Dawood
Published: January 2021

Curriculum integration at all levels of education is common practice and well-researched area. However, there is no consensus among scholars and educationists about the definition of curriculum integration. Different factors influence the definitions and models of curriculum integration. Philosophical, Ideological, cultural and historical perspectives lead to different definitions, types and models. The integration of curriculum, particularly in the west, passed through different phases since the early 1900s and produced different emphasis, types, processes and models. This paper attempts to present a new definition and model based on one case in the Qur’an. This case reflects the story of Prophet Musa and the righteous man (al-Kẖidr) in chapter al-Kahf. The new model has some similarities with specific elements in the western literature but has its unique characteristics which reflect the uniqueness of the revealed knowledge in this story. Different models of curriculum integration could be adopted for different topics/issues/problems and contexts. Further, research is needed in this area, particularly in Muslim societies and contexts.
Keywords: Integrated curriculum, Islamic perspective, the story of Prophet Musa and the righteous man (al-Khidr). 
Abstrak
Integrasi kurikulum adalah perkara yang sering dikaji dan diamalkan didalam setiap tahap pendidikan. Namun begitu, tidak ada kata sepakat dikalangan para ilmuwan dan pendidik dalam menetapkan definasi integrasi kurikulum. Terdapat beberapa faktor yang mempengaruhi definasi dan model integrasi kurikulum. Dari sudut falsafah, ideologi, budaya, dan sejarah, ia membawa kepada maksud, jenis dan model yang berbeza. Integrasi kurikulum khususnya di barat telah melalui pelbagai fasa sejak awal tahun 1900 dan telah malahirkan kepelbagaian dari sudut penekanan, jenis, proses, dan model. Artikel ini bertujuan untuk mengemukakan definasi dan model baru berdasarkan satu kisah di dalam al-Quran. Kisah ini menggambarkan tentang kisah Nabi Musa A.S dan seorang pemuda soleh (al-Khidr) di dalam Chapter al-Kahf. Model baru tersebut mempunyai beberapa persamaan dengan unsur-unsur di dalam sastera barat akan tetapi ianya juga mempunyai ciri-ciri unik yang mencerminkan keunikan di dalam kisah yang telah diwahyukan. Model integrasi kurikulum yang berbeza dapat diadaptasikan untuk pelbagai topik, masalah, isu, dan konteks. Penyelidikan yang lebih terperinci diperlukan di dalam bidang ini, terutamanya dalam konteks masyarakat Islam.
Kata Kunci: Integrasi kurikulum, perspektif Islam, kisah Nabi Musa A.S. dan seorang pemuda soleh (al-Khidr).