(Invited) Impact of Some Processing Steps onto the Strain Distributions in FD-SOI CMOS Planar Devices: A Contribution of Dark-Field Electron Holography
Authors: Boureau Victor , Benoit Daniel , Claverie Alain 
Published: February 2020

For long time considered as detrimental, stress is now an integral feature of modern electronic devices. Indeed, correctly oriented, the resulting strains may significantly increase carrier mobility and thus boost device performance. In this context, Dark-Field Electron Holography (DFEH) was used to study the impact of some key steps of the manufacturing process of 22 nm fully depleted planar transistors (FDSOI).

DFEH is an interferometry technique based on Transmission Electron Microscopy recently invented and still being developed at CEMES-CNRS, which allows us to map crystalline strains with nanometer resolution and an accuracy of 10-4 over micrometer fields of view. The comparison of these experimental maps with simulation results obtained from Finite Element Modelling (FEM) allows one to explore, then possibly identify, the mechanical phenomena involved during the processing steps of FDSOI transistors.

In general, samples are fabricated using a Focused Ion Beam equipment and thinned down to 80-110 nm. Thus they suffer some elastic relaxation at, and close to, the two free surfaces. FEM is used to reproduce the observed strain in the same thin “measured sample”, taking into account the influence of thickness on the electron wave amplitudes and resulting phase contributions to the final hologram, then to retrieve the strain which was originally present in the bulk sample. Based on our (long) experience, these physically sound refinements never alter the measurements by more than 15%, most often by a mere 5%, for the planar devices we observe. In other words, the mappings directly obtained by DFEH reproduce very well the actual strain fields which reside in the transistor before thinning.

Following the different steps leading to the co-integration of n and p-MOS, from the “Ge condensation technique” to locally form a thin highly compressively strained SiGe layer to the opening of trenches, we have evidenced abnormal large strain relaxations of these layers at the trench edges, extending well beyond elasticity predictions. Numerical approaches suggest some “weakened interface” exist between the SiGe layer and the BOX. It can be simulated introducing weak elastic spring forces to bind the interface, instead of the foreseen rigid connection. Later confirmed by Raman and electrical studies and despite various hypothesis have been investigated (H, Ge-O bonds…), this phenomenon remains unexplained.

The figure shown above is a composite image of the strain along the channel of the foreseen n-MOS after the fabrication of the gate stack on the Si thin top layer. The stack was deposited “full sheet” and involves several different materials and energetic thermal treatments (oxidation, ALD, CVD, activation annealing, etc). In full sheet, the internal stresses cannot relax. Then, when the gates are fabricated by photolithography and etching, the symmetry breaking (edges) allows the various layers to react to these internal stresses and deform. This image shows that the channel is under tension (in plane) below the gate, with a maximum strain of about 0.8%. The gate tends to relax some internal compressive stress and deforms the underlying, originally unstrained Si channel. The same phenomenon is observed on the SiGe layers for p-MOS transistors, which are under compression after their fabrication by the Ge enrichment technique.

The stress exerted by the gate is mostly due to presence of the TiN contact which, when back at room temperature after deposition, is highly compressively stressed (-2.35 GPa). This contact transfers its deformation through the gate dielectric putting the channel under tension. This effect is consolidated by the opposite effect of the SiN spacer (intrinsically tensile) which tends to compress further the Si film on both sides of the channel.

Finally, we will follow two subsequent and important processing steps; the fabrication of the raised source and drain and of the contact silicide. Both steps affect the strain state of the channel of the devices (n- and p-MOS). The composition of the source and drain (Si, Ge, B, P, C…) can be craftily adjusted to manipulate further strain in the channel of the devices. Silicidation of the source and drain has almost no effect on the strain state of the channel as the raised source and drain can relax laterally without affecting the channel. Partial BOX creeping at high temperature and strain relaxation at free edges are the main ingredients needed to understand and simulate the strain behavior of the channel during these fabrication steps.

In most cases, DFEH images not only provide more precise results than Nano Beam Diffraction (NBD) but additional important information such as the presence of defects, precipitates, heterogeneous compositions, etc., all locally but strongly impacting strain distributions.

Figure 1