bluuebunny/crossref_metadata_2025 huggingface dataset:
Small-chip Attachment on Copper Leadframe with Sintered Nanosilver Paste
Authors: Calata Jesus N. , Zheng Hanguang , Lu Guo-Quan , Ngo Khai , Nguyen Luu
Published: October 2015

Sintered nanoscale silver paste provides a low-temperature alternative to solder for die attachment. Unlike solder, the sintered attachment does not melt upon reaching the original attachment temperature and therefore may be used at higher temperatures. Higher electrical and thermal conductivities mean less Joule heating and better heat dissipation characteristics and the porous microstructure imparts low elastic modulus for lower thermomechanical stress and enhanced reliability. The state of the technology has reached a point where it is now possible to obtain die-shear strengths comparable to solder at sintering temperatures between 250°C and 280°C with little or no applied pressure, depending on the chip size. In addition to attachments on silver or gold-coated surfaces, it is possible to form bonds on bare copper if done under inert or slightly reducing atmosphere. Because attainment of a strong bond depends on the paste being in contact with a clean (oxide-free or untarnished) surface, a study was made to determine if the attachment process will work on copper leadframes with either an anti-tarnish or anti-EBO (epoxy bleed-out) coating. Small mechanical silicon chips less that 3 mm × 3 mm in size were attached without pressure at temperatures as low as 260°C. The sintering atmosphere in the chamber was varied from pure nitrogen, to nitrogen + 4% hydrogen and to nitrogen + 1% oxygen. Attachments sintered in pure nitrogen or nitrogen with hydrogen produced die-shear strengths of at least 30 MPa and were just as strong as those bonded on bare copper. Sintering in nitrogen + 1 % oxygen caused the die-shear strength to drop below 30 MPa but still above 20 MPa. In the presence of oxygen, the binder removal is due to oxidative combustion but the low level of oxygen caused incomplete binder burnout that interfered with the sintering while also causing some oxidation of the copper. On the other hand, the addition of hydrogen appeared to enhance the sintered microstructure accompanied by a slight increase in die shear strength. Sheared attachments that exposed the copper surface showed patches of silver still attached indicating formation of strong bond with the copper.
Copper Wirebond Compatibility with Organic and Inorganic Ions Present in Mold Compounds
Authors: Mathew Varughese , Chopin Sheila , Higgins Leo , Zhang Yingrui
Published: October 2015

Copper wirebond (CuWB) packaging is emerging as a replacement to gold wire technology because of the increases in the price of gold. However, copper is more susceptible to corrosion than inert gold so there are several reliability concerns regarding the integrity of the Cu-Al interface. Copper wirebond compatibility with the surrounding encapsulating mold compound is critical as this material combination can produce a corrosive environment in the presence of moisture and ionic impurities. Mold compounds consist of different chemical components that can yield several ionic organic and inorganic species. The effect of chloride on CuWB reliability has been published in the literature, the impact of other ions typically present in mold compound matrix is not widely discussed. It is important to understand the role of these ions on the CuWB reliability to design appropriate mold compounds for product encapsulation as some of the ions are corrosive while others are of benign or beneficial in nature. This paper examines the impact of organic anions such as formate, acetate and oxalate and inorganic anions phosphate and nitrites on CuWB reliability with regards to the integrity of the vulnerable Cu-Al interface. Corrosion depends on the pH conditions of the mold compound matrix in presence of moisture.Cu-Al integrity under various pH conditions and ionic concentrations will be presented and the effect of these ions on the corrosive behavior of chloride will be examined. The combined influences of different anions on the Cu-Al integrity will be discussed. Finally, a relatively simple method to examine the integrity of the Cu-Al interface will also be described.
Effects of Sb and Zn Addition on Impact Resistance Improvement of Sn-Bi Solder Joints
Authors: Okamoto Keishiro , Nomura Kenji , Doi Shuichi , Akamatsu Toshiya , Sakuyama Seiki , Uenishi Keisuke
Published: October 2015

We investigated the effect of adding Sb and Zn on improving the impact resistance of Sn-Bi solder joints. Sn-57Bi-0.5Sb-0.5Zn showed a better resistance property than did Sn-58Bi, Sn-57Bi-1Ag, and Sn-57.5Bi-0.5Sb against package drop tests. Sn-57Bi-0.5Sb-0.5Zn had a resistance increase of less than 10% even when annealed at 125 °C, and the other three had an increase of more than 200 %. It is thought that the fall-proof characteristic greatly improved because the formation of a brittle Bi rich layer was controlled by the existing Cu5Zn8 layer formed at the joint interface after high temperature soaking.
Effect of ENEPIG Surface Finish on the Vibration Reliability of Solder Interconnects
Authors: Menon Sandeep , Pearl Adam , Osterman Michael , Pecht Michael
Published: October 2015

Surface finishes are used to preserve and promote solderability of exposed copper metallization on printed wiring boards. While in the best of worlds, the solder used in assembly should dictate the solder interconnect reliability, surface finishes are known to have an effect. The effect of surface finishes on solder interconnect reliability can be particularly strong under high strain rate loading conditions. In this study, durability of solder interconnects formed between BGAs and electroless nickel, electroless palladium, immersion gold (ENEPIG) finished pads assembled using SnPb and SAC305 solders under harmonic vibration loading is examined. ENEPIG test specimens with two thicknesses of palladium were evaluated. Isothermal preconditioning levels at 100°C for 24 hrs and 500 hrs were included to evaluate the impact of intermetalic evolution on the durability of the soldered interconnects. For comparison, tests specimens created with immersion silver (ImAg) finished printed wiring boards were also included. The failure data obtained found the durability of interconnects formed with ENEPIG finish was comparable or better durability than the durability of interconnects formed with ImAg finish irrespective of the solder. The tests indicate that the use of a thicker palladium layer reduced the degradation in durability which occurred from isothermal aging.
Thermal Cycle Consideration in Applying Lead-Free TFBGA Simulation to a Design
Authors: Tsai Yi-Chuan , Wu Mei-Ling
Published: October 2015

Three-dimensional (3D) stacked die packaging has become the trend to improve efficiency for transmitting signals, reduce the volume of the package, and help with functions integration. It is more and more applied popularly in telecommunications. Solder joints, interconnections in the packaging structure, are more easily damaged by critical stress from thermal cycle loading when the component is operating, because the coefficient of the thermal expansion of various materials mismatch. People have studied the common single die during the thermal cycle loading for a long time, but the researches for the stacked die BGA are not as complete. In addition, to protect the environment and comply with legislation, the semiconductor industry wants to find a lead-free material to replace the lead solder joints. Therefore, most extant or new types of packaging started using lead-free material to do thermal cycle testing. The critical solder ball location is not the same as in a single die package where at the die corner, due to it is influenced by stacked die with different geometry, the difference in dice length helps to redistribute the die stress.

In this paper, we used FEA software, ANSYS, to build up a 3D thin-profile, fine-pitch, ball grid array (TFBGA) model. The modeling investigated the effect on solder joints under thermal cycle and included deformation, von-Mises stress and strain energy density (SED). Then we utilized Darveaux's approach, which is a common methodology used to calculate the fatigue life based on energy and damage accumulation theories, to predict the fatigue life of the critical solder joint and modify our model with the theory. We changed various kinds of SAC solder joints with different ratios of the components and Anand's constants, analyze the divergence and compared them with the lead solder material. We develop a model to forecast the failure phenomenon and fatigue damage on an electronic package. This would help engineers and designers raise the reliability of the package. In addition, we hope to find a lead-free material that can be substituted for the lead solder material. If this is the case, based on simulating results, we hope to improve it and have much a better reliability performance than the original lead solder.
Smart Power Module Molding Advances: Evaluating high temperature suitability of Molding Compounds
Authors: Becker K.-F. , Thomas T. , Bauer J. , Kahle R. , Braun T. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D.
Published: October 2015

During the last years within power electronics packaging a trend towards compact power electronics modules for automotive and industrial applications could be observed, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics yielding maximum miniaturization. Transfer molding is the method of choice for cost effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package:

Typically those packages are asymmetric, a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed providing a heat path for optimized cooling. This asymmetric geometry is prone to yield warped substrates, preventing optimum thermal contact to the heatsink and also putting thermo-mechanical stress on the encapsulated components, possibly reducing reliability.

Such packages being truly heterogeneous, combining powerICs, wire bonds, SMDs, controlICs, substrate and leadframe surfaces, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally those packages need to operate at elevated temperatures for long time, e.g. operate at 200 °C for 1000 h and more, so high thermal stability is of ample importance.

Within this paper the main goal is to identify transfer molding compounds suitable for the encapsulation of smart power modules, ready to be used at 200 °C and determine the actual maximum temperature of use of such high performance molding compounds currently available in the market. Summarized a detailed description of the high temperature suitability of high performance molding compounds is provided – additionally an extended test methodology is described to facilitate future material evaluation for HT or harsh environment use of polymeric materials as encapsulants or base materials.
Hybrid In-Mould Integration
Authors: Alajoki Teemu , Koponen Matti , Huttunen Arttu , Tuomikoski Markus , Heikkinen Mikko , Keränen Antti , Keränen Kimmo , Mäkinen Jukka-Tapani , Jaakola Tuomo , Aikio Janne , Rönkä Kari
Published: October 2015

Next generation of electronic modules and systems in different application areas such as automotive, medical and home appliances will utilize various electronic, optical and mechanical functions integrated in freeform intelligent products with benefits such as decreased volume and weight, lower costs and higher freedom of design when compared to currently available electronics manufacturing and packaging methods. The hybrid in-mould integration technology concept is based on combination of roll-to-roll (R2R) printed electronics, discrete component assembly, film forming and injection overmoulding/in-mould labelling (IML) processes. In this study, compatibility and feasibility of the technology for low-cost disposable healthcare sensor applications, especially pulse oximeters, was investigated. Flexible printed circuit (FPC) substrates for pulse oximeter applications were manufactured in high-volume and low cost fashion by R2R printing and etching processes. Surface mount technology (SMT) and leadframe components were assembled on FPCs by using adhesive bonding technology. The assembly process was also demonstrated using automated, high-volume capable machine. It was proven that SMD components and their interconnections on flex withstand the injection overmoulding process and can thus be embedded seamlessly inside plastic parts. By the use of the same injection moulding process it was also demonstrated that rigid mechanical locking features manufactured by film overmoulding can be combined with the flexibility of FPC. In order to speed up the iteration cycles of the hybrid integration design flow, a new method was developed for rapid prototyping of in-mould integrated products. In the method, 3D printing was used to create a master for a silicone mould, and assembled FPC was overmolded in vacuum casting process with polyurethane material. This paper presents also other research activities at VTT Technical Research Centre of Finland in the field of hybrid system integration carried out in various collaborative projects with companies and research institutes in Europe. The demonstrators realised in these projects include autonomous, intelligent lighting and signaling systems for automotive and traffic signs, in-molded optical touch panel and flexible printed organic light-emitting diode (OLED) embedded into 3D plastic structure using IML-like process in which active OLED foils are used instead of graphic foils. The demonstrators prove that hybrid in-mould integration could be a feasible technology enabling seamless integration of optical, electrical and mechanical features into 3D plastic products.
A friction based approach for modeling wire bonding
Authors: Althoff Simon , Neuhaus Jan , Hemsel Tobias , Sextro Walter
Published: October 2015

A model approach for wedge/wedge bonding copper wire is presented. The connection between wire and substrate is based on a variety of physical effects, but the dominant one is the friction based welding while applying ultrasound. Consequently, a friction model was used to investigate the welding process. This model is built up universal and can be used to describe the formation of micro welds in the time variant contact area between wire and substrate.

Aim of the model is to identify the interactions between touchdown, bond normal force, ultrasonic power and bonding time. To do so, the contact area is discretized into partial areas where a Point Contact Model is applied. Based on this approach it is possible to simulate micro and macro slip inside the contact area between wire and substrate. The work done by friction force is a main criterion to define occurring micro joints which influence the subsequent welding.
Stacking of known good rebuilt wafers for high performance memory and SiP
Authors: Couderc Pascal , Noiray Jerome , Val Christian
Published: October 2015

Based on Wire-free Die on Die disruptive technology (WDoD™), high density memory can be manufactured in a small form factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices. Dual die (DD) and Quad die (QD) DDR3 memories exhibit outstanding performance and show the path to highly densified System in Package (SiP) for Medical, Defense and Industrial markets
A Study on the Effectiveness of Underfill in the High Bandwidth Memory with TSV
Authors: Lee Woong-Sun , Lee Dae-Woong , Son Ho-Young , Lee Jin-Su , Suh Min-Suk , Kim Nick , Byun Kwang-Yoo
Published: October 2015

HBM-High Bandwidth Memory- has 128 GB/s band width and construction of stacked memory device with TSV –Through Silicon Via-. Stacked structure is basically composed of base die which has a logical circuit to control memory cell and 4 high stacked memory devices. HBM package size is around 5 mm × 7mm, smallest form factor and attached to the Si interposer by micro bump joining. Also stacked DRAM dies have 20 μm diameter micro-bumps and underfill material for supporting mechanical strength of stacked HBM structure. In this study, we investigate the stress evolution of underfill material to the thinned die of HBM and also verify the environmental reliability of HBM.
Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications
Authors: Huang Jhin-Fang , Lai Wen Cheng , Jiangn Yong-Jhen
Published: October 2015

An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The measured results of the chip show an input return loss of 20 dB, a conversion gain of 29 dB, a double-side band (DSB) noise figure (NF) of 5 dB, and a third-order intercept point (IIP3) of −24.4 dBm. The on-chip oscillator shows the measured tuning range of 5.17–5.98 GHz and phase noise of −118.5 dBc/Hz at 1 MHz offset from the 5.8 GHz carrier. The proposed receiver front-end is fabricated in a 0.18 μm CMOS process with a power consumption of 27.6 mW from a 1 V supply voltage. The chip area including PADs is 1.75 × 1.2 mm2.
RF MEMS DPDT Switch Using Novel Simulated Seesaw Design
Authors: Al-Amin Mohammed , Yousef Sufian , Morris Barry
Published: October 2015

This paper investigates an RF MEMS (Radio Frequency Micro Electro-Mechanical System) switch from DC to 5.8 GHz switching, for use in mobile communications systems and devices. The RF MEMS switch uses a novel seesaw design to create a Double-Pole Double-Throw (DPDT) Switch which increases the capabilities of the seesaw design structure. A low Switching supply voltage with high RF isolation was achieved during its development. After looking at other available seesaw designs, it was discovered that an improvement could be attained by adding additional contacts.

An improved concept over existing Single-Pole Single-Throw (SPST) seesaw switches was achieved by using a DPDT switch with a set of upper and lower contacts at each side of the seesaw. To conform to the Microscale, from 1 μm – 100 μm, a length of 41μm was chosen to provide an adequate size for fabrication.

Copper Bulk General (Cu) was chosen for the pivot material due to its good electrical conductivity and sufficient flexibility for elastic recovery.

A working simulation was achieved without compromising the ‘Air-Gap’ between the contacts, which retains high isolation when the switch is open-circuited. The electrostatic supply voltage has been significantly reduced to a value which is closer to that used in mobile devices.
Silver oxalate: towards a new solder material for highly dissipative electronic assemblies
Authors: Kiryukhina K. , Le Trong H. , Tailhades P. , Lacaze J. , Gougeon M. , Baco V. , Courtade F. , Dareys S. , Vendier O. , Raynaud L.
Published: October 2015

This work presents a new route to obtain a highly conductive silver solder (with thermal conductivity around 100 W/m.K) by thermal decomposition of a silver oxalate precursor at moderate temperature (<300°C) and low pressure (<0.5MPa).
Development of low temperature sintered nano silver pastes using MO technology and resin reinforcing technology
Authors: Sasaki Koji , Mizumura Noritsuka
Published: October 2015

Traditional thick film technology is widely used in various electronics products. There are two type of paste based on thick film technology. Typically, over 400°C is required for high temperature sintering type which contains glass for adhesion function. It shows high electrical and thermal performance. On the other hand, 150–300°C range process is used for low temperature process type as silver epoxy. In last decade, nano silver technology shows amazing progress to address low temperature operation by low temperature sintering.

This paper will discuss the results on fundamental study of newly developed nano silver pastes with unique approach which uses MO (Metallo-organic) technology and resin reinforcing technology.

Nano silver pastes contain several types of dispersant as surface coating to prevent agglomeration of the particles. Various coating technique has been reported to optimize sintering performance and stability. MO technology provides low temperature sintering capability by minimizing the coating material. The nano silver pastes show high electrical and thermal performance. However, degradation of die shear strength has been found by thermal cycling test due to the fragility of porous sintered structure. To improve the mechanical property, resin reinforcing technology has been developed. By adding special resin to the pastes, the porous area is filled with the resin and the sintered structure is reinforced. Degradation of die shear strength was not found by thermal cycling test to 1000 cycles.

Nano silver pastes using MO technology and resin reinforcing technology will meet lots of requirement on various thick film applications.
Five layer Cu-coated Zn/Al clad solder for die attachment
Authors: Yamaguchi Takuto , Ikeda Osamu , Hata Shohei , Oda Yuichi , Kuroki Kazuma
Published: October 2015

Zn/Al and Zn/Al/Cu clad materials have been developed for high-temperature die attachment. The clad structure is used in an attempt to improve the wettability of Zn-Al solder by preventing oxidation of Zn and Al. The materials were produced by clad-rolling of Zn, Al, and Cu strips, and they act as a solder following eutectic melting at temperatures above 382°C. The wettability, bondability, and reliability of the clad materials were evaluated. It was found that the Zn/Al/Cu clad material could be used under an atmospheric oxygen concentration of 100 ppm. In addition, the thermal cycle life of a chip-to-substrate joint formed using the Zn/Al/Cu clad material was longer than that using Pb-Sn-Ag solder.
A Switched-Line Phase Shifter Fabricated with Additive Manufacturing
Authors: O'Brien Jonathan M. , Rojas Eduardo , Weller Thomas M.
Published: October 2015

Additive manufacturing, also known as 3D printing, has proven to be advantageous compared to conventional planar methods when utilizing the volume of a structure to miniaturize the design. The use of additive manufacturing can allow for high frequency circuitry to be conformed to an arbitrary shape while maintaining or enhancing performance. Recent advancements in low loss materials applicable to additive manufacturing have pushed performance levels even further.

Utilizing additive manufacturing to build a three dimensional structure can improve factors such as reliability and repeatability by making the structure one solid piece as opposed to assembling multiple planar objects into the 3D shape. This allows the circuitry to be built around the structure. With this design approach other considerations, such as stability and strength, can be concentrated on during the structure design to realize new shapes.

The purpose of this work is to investigate a 3D printed material, ULTEM, for radio frequency use and design a switched line phase shifter using the derived material properties. The first step in any high frequency circuit design is to have accurate material properties. An efficient way to determine the permittivity and loss tangent of a material is to place a ring resonator on the substrate and measure the resonant frequency and Q factor. An equivalent circuit model can then be built to match the measured response and the material properties extracted through circuit theory. From here accurate transmission line models can be analyzed to optimize the performance of the RF circuit.

In this paper a ring resonator was designed on ULTEM to characterize the material properties. A 90° phase shifter was then fabricated on a 3D printed ULTEM substrate and a benchmark model was fabricated using traditional planar methods on Rogers RO4003C substrate. A comparison between the two models is given in this paper.
Precision Patterned Thin Films without Photolithography: Additive Manufacturing of Printed Electronics
Authors: Lauer Scott , Little Whitten , Ambrose Thomas , Conrad Jeff , Cowen Tim
Published: October 2015

Additive manufacturing is the application of layer manufacturing techniques to fabricate microelectronic products. These techniques differentiate themselves from incumbent technologies in that they only add material to build the device and are an alternative to subtractive technologies such as lithography that globally coat layers and then etch-away unrequired materials. In this paper we discuss an additive technology that performs material evaporation through shadow masks. This process has shown significant potential for the fabrication of chip packaging, microelectronic devices and circuitry; specifically, high density interposers, fine conductor lines and embedded components such as capacitors, resistors, and transistors. The process is compatible with a number of both rigid and flexible substrates and deposition materials. Examples of devices and lines that have been manufactured by this technique are shown and discussed. Preliminary test data shows line / space resolution that has reached 5 / 20 microns and better.
Thermal Evaluation of High-Current Polyimide Rigid and Rigid-Flex Printed Wiring Board Trace Widths in a Vacuum
Authors: Cannon Bennion , Friedl Frank , Gisler Gary
Published: October 2015

This paper details the thermal evaluation of high-current polyimide rigid and rigid-flex printed wiring boards in a vacuum. Although industry standards, such as IPC-2152 or MIL-STD-275, can be used to determine required trace width for PWB traces that carry current to between 20 or 30 amps for multiple copper plane thicknesses, they typically cannot be used to determine trace width for PWB traces that handle current greater than 15 amps. This paper presents results from testing and analysis of high-current rigid and rigid-flex PWBS that must carry current of up to 60 amps. Testing was performed in vacuum on a controlled-temperature platen, measuring board temperature at specific locations to determine performance of different trace widths using 2 and 4 ounce copper layers. A thermal imaging camera was used to identify PWB hot spots. Test results were compared to IPC-2152 standards, extrapolated to 60 amps current.
DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications
Authors: Sun Zhuowen , Chen Kevin , Crisp Richard
Published: October 2015

The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration onto motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 MT/s) with much reduced footprint and z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design.

To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5×17.5×1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each ×16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD™ ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4). It also enables dual-rank operations in each channel when double-sided assembly is used.

We successfully demonstrated in production build that 1GB ×64 DDR3L QFD with data rate of 1600 MT/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under study with different memory bus topologies for even higher data rate up to 2400 MT/s using the same QFD technology.

Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate >1600 MT/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.
Electrical characterization of TSVs with varying process knobs and temporary bond/adhesive system robustness studies for 2.5D/3D manufacturing
Authors: Kumar Niranjan
Published: October 2015

TSVs are used to carry power/ground and signals straight to the heart of the logic/memory devices where all the intricate and busy architectures lie. I consider it like the downtown area inside a city where the real estate is more expensive and requires intricate design and execution. As a result in case of the TSVs, there is no room for electrical degradation and stress interaction with transistor devices (keep out zone). The Cu protrusion, it's interaction with the intricate local interconnects (M1 and below structures), the current leakage, capacitance, reliability, become highly critical to fully achieve the power per watt advantage of the TSVs. As a result, a thorough electrical characterization of TSVs with varying film properties and the process window becomes very critical for integration with the 20nm node (and below) devices. In this paper we will discuss implementation of modified oxide liner, barrier/seed, ECD fill and CMP of films to achieve robust TSVs for electrical parameter extraction. We will closely examine the impact of these film properties on the electrical performance and its repeatability to achieve wide process windows. Such studies are expected to improve manufacturing yields of TSV product wafers at fabs/foundries. Alternately, we will present detailed metrology studies of two temporary bond method/adhesive systems as it progresses through the thin wafer downstream processes (via-reveal processes). This exercise is targeted to address productivity and yield challenges with thin wafer processing (backside via-reveal process). We will attempt to demonstrate a robust temporary bond/adhesive system that exhibits no thin wafer damage/wrinkling and no edge profile degradation issues over repeated runs (production like). This study will help to characterize the adhesive and low temperature passivation film interfaces in details to support the thin wafer processing robustness for TSV manufacturing.
Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization
Authors: Li Zhe , Tan Siow Chek , Yew Yee Huan , Teh Pheak Ti , Lee MJ , Xie John
Published: October 2015

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.
Modeling and Reliability Analysis of TSVs for High Frequency Applications
Authors: Kannan Kaushal , Kim Bruce , Kannan Sukeshwar , Noh Seok-Ho
Published: October 2015

This paper presents electrical modeling of thermo-mechanical delamination in TSV. Previously, several papers in electrical modeling of TSV have been published in open literature; however, these do not consider the thermal-mechanical delamination in TSV. Stress-induced thermo-mechanical delamination in TSV has been analyzed by considering the thermo-mechanical stress loading effects of high aspect ratio copper electroplated TSVs. Two-dimensional mechanical finite element models have been built to analyze the stress distribution in TSV structures. The mechanical models and energy release rate at the crack are then translated to electrical defect models to evaluate the functional electrical performance of TSVs with delaminations. Simulation was performed on 7 μm by 60 μm TSVs using an RF signal with −10 dBm power on a crack length of 0.2 um and width of 0.15 um. We observed output power of −11.8 dB at a frequency of 77 GHz. When the crack length was increased, the output power decreased to −11.2 dBm due to increased parasitics resulting in more attenuation of RF output. This reliability analysis enables us to evaluate the electrical performance of TSVs for high frequency applications.
Design for Solder Joint Fatigue Life of BGA Package Subject to Mechanical Environment
Authors: Lan Jia-Shen , Wu Mei-Ling
Published: October 2015

There has been a dramatic proliferation of research concerned with thermal stress in electronic package for the last three decades. Moreover, reviewing the mechanical bending during printed circuit board (PCB) assembly has become important in the reliability assessment of modern electronic systems. The primary research demonstrates that the assessment approach can be applied successfully to the design model of a ball grid array (BGA) package with a more complete and accurate assessment model for solder joint fatigue life under mechanical bending. Previous research has focused mostly on the thermal analysis in electronic packages; however, most modern portable electronic products used in mobile devices, personal digital assistants, and aircraft have to endure extreme environments that involve not only thermal but also mechanical bending conditions. Initially, mechanical bending tests were conducted to demonstrate the reliability of the electronic packaging during the manufacturing and shipping process. Currently, the microelectronic packaging faces mechanical bending when everyone uses his or her Smartphones. The mechanical bending occurs when the user touches the screen on the Smartphone. Therefore, interest in the mechanical bending of BGA packaging has increased with the uptake in mobile device use.

In this research, the analytical solution and finite element analysis (FEA) are both presented to investigate the solder joint fatigue life. The analytical solution is presented for a PCB assembly subjected to mechanical bending by taking the axial stress, shear stress, and moment of the solder joints with discontinuity function into account. A FEM is proposed to analyze the solder joint fatigue life and to investigate the reliability of solder joints in BGA packaging subjected to mechanical bending.
An overview of molded underfill in flip chip packaging applications
Authors: Roa Fernando
Published: October 2015

Flip chip packaging is a wide-spread process used in high frequency, high IO count IC devices. It consists of joining the IC chip with the substrate using solder alloys or Cu pillars to form a continuous interconnection for the electronic signals to travel through. However, because during operation these devices dissipate heat, the temperature at the bumps interface rise and drop in cycles which cause thermal stress to build up due to the different thermal expansion of the materials. If left unchecked, these stresses will weaken and eventually cause fatigue failures. Therefore, stress absorbers are dispensed or underfilled to fill the gap between the substrate and the die. Underfills, as these materials are commonly known, are typically dispense as liquids using a variety of techniques like spraying, jetting, injection dispense, etc.

In this paper we'll discuss the benefits and challenges of a new type of process that integrates the overall encapsulation of the package with the underfill process in one single process step, called molded underfilling. We'll discuss this application for simple devices consisting of one IC chip and then extend the discussion towards more complex package configurations consisting of IC chips and passive components to demonstrate the flexibility and robustness of this new process solution.
Packaging Materials for 2.5/3D Technology
Authors: Schmaltz Brian
Published: October 2015

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).
Adhesion and Cure Mechanism Studies for Advanced Lidded Flip Chip Applications
Authors: Larson Lyndon J. , Steinbrecher Kristen E.
Published: October 2015

As packages utilizing the next technology nodes increase in power density and end-customers demand more functionality per device, many designs are facing thermo-mechanical and reliability challenges at an unprecedented level. Area array flip chip packages have become the package of choice for many of these advanced devices. These flip chip packages often require a complex arrangement of polymeric, metal, and ceramic components to work together in order to provide such performance, and maintain that performance for a given set of conditions and durations. One important aspect of this symbiosis is the design of the heat dissipation aspects of the package and how it is integrated with the electromechanical aspects of the package –in particular the adhesive technology used for coupling these two components. In this paper, the adhesive material properties are characterized along with the impact on the assembly process as well as on the package reliability.
Multipurpose Wire Bonding – Bumps, Wires, Combination Interconnects, and Operation Efficiency
Authors: Evans Daniel D.
Published: October 2015

Today's multipurpose wire bonding machines are required to deliver a combination of wires, bumps, and specialty interconnects for RF, automotive, and optical markets with odd-form factor parts. These market production requirements are generally lower volume with a higher mix of products compared to typical high-volume semiconductor packaging of memory and logic. These markets also require multipurpose wire bonders to accommodate large work area, deep access, and a complex mix of bond surfaces, wire shapes, and bumps. The number of components in a package can vary from one with a few wires up to hundreds of components with thousands of wires. Programming methods, process development, traceability, and rework are different for customers using this class of bonder.

A survey of customer application cases shows the range of capabilities available to packaging engineers.

The four primary cases presented highlight the range of applications that can be handled for odd-form factor packages and specific areas of focus to maximize productivity for these classes of products.Case 1: Ball Bump Size and Shape Examples: acheiving 119μm down to 44μm bonded ball diameters and range of shapes.Case 2: Ambient Wire Bonding to a 6″ Tall Package: demonstrating allowable bonding volume and tooling flexibility plus the ability to bond Au with substrates at ambient temperature.Case 3: Batch Load Tray (Mechanical and Vacuum Clamping): allowing quick change over for radically different sized packages.Case 4: Complex High Part Count Packages: supporting alternate parts and alternate bonding wires, stand-off stitch, and security bonds require special features for programming and navigation methods to allow easy creation and navigation of complex programs for maximum productivity. Breakdown of timing and efficiency is provided showing programming efficiencies of 2X or better.

These cases will help packaging engineers extrapolate to their own cases and show how a multipurpose automatic wire bonder can be an effective way of automating or semi automating these manually or automatically presented packages for higher throughput, higher quality and consistency, and less labor usage for lower cost.
Implementing Inductor Function with Vibrating Capacitor Structures
Authors: Marinis Thomas F. , Soucy Joseph W.
Published: October 2015

One of the most common uses of inductors is in filtering electrical signals to remove oscillations over selected frequency ranges. In this application, they are combined with capacitors to build resonant circuits to either block or dissipate signals at the unwanted frequencies. Similar, but larger current capacity filters are used to eliminate oscillatory ripple voltages from DC power supply outputs. Inductors are also essential components in buck converter type power supplies in which they store energy supplied by an oscillatory source to power a circuit, which generates a constant voltage. Inductors of various constructions have proven highly successful in all of these applications, but their performance is not ideal. For one, they dissipate the energy that is stored in them via a number of mechanisms. The conductivity of the wire comprising their windings is finite, so they suffer Ohmic losses. Their magnetic fields induce eddy currents within their cores and dissipative currents in surrounding circuit elements. Inductors also exhibit parasitic capacitance between their windings, which can give rise to dielectric losses. Because of these loss mechanisms, the quality factor of an inductor, which is its time average ratio of stored to dissipated energy, is typically less than a few hundred. By contrast, mechanical resonators, fabricated from single crystal silicon, attain quality factors that are orders of magnitude higher. Hence, mechanical filters could be made with sharper roll offs and smaller bandwidths than inductor based filters. They would also be more efficient in power supply applications. Inductors are also relatively heavy components, when compared to capacitors, resistors and integrated circuits, due to their high content of copper and iron. A mechanical oscillator could be made significantly lighter than an inductor that is capable of storing the same amount of energy. We have been investigating mechanical oscillators that use flat beams, suspended at both ends above substrates with electrode patterns that form a capacitive dive to excite oscillations in the beam. We are examining a number of configuration variables, including beam geometry, mass distribution and excitation loading. We use finite element analysis and lumped parameter models to characterize beam deflection and MatLab scripts to predict performance in electrical circuits. We are also preparing to fabricate our first design for testing.
Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers
Authors: Choi Kwang-Seong , Bae Ho-Eun , Lee Haksun , Bae Hyun-Cheol , Eom Yong-Sung
Published: October 2015

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.
Redistribution Layers (RDLs) for 2.5D/3D IC Integration
Authors: Lau J. , Tzeng P. , Lee C. , Zhan C. , Li M. , Cline J. , Saito K. , Hsin Y. , Chang P. , Chang Y. , Chen J. , Chen S. , Wu C. , Chang H. , Chien C. , Lin C. , Ku T. , Lo R. , Kao M.
Published: October 2015

Redistribution layer (RDL) is an integral part of 3D IC integration, especially for 2.5D IC integration with a passive interposer. The RDL allows for fans out of the circuitries and allows the lateral communication between the chips attached to the interposer. There are at least two ways to fabricate the RDL, namely (a) polymers to make the passivation and Cu-plating to make the metal layer, and (b) semiconductor back-end-of-line Cu damascene. In this study, the materials and processes of these methods are presented. Emphasis is placed on the Cu damascene method.
3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency
Authors: Vincent Michael , Mitchell Doug , Wright Jason , Foong Yap Weng , Magnus Alan , Gong Zhiwei (Tony) , Hayes Scott , Chhabra Navjot
Published: October 2015

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.