bluuebunny/crossref_metadata_2025 huggingface dataset:
Thermoelastic Problems for Electronic Packaging
Authors: Lau J.H.
Published: February 2008

The basic equations (infinitesimal strain‐displacement relations, constitutive equation, conservation of mass, conservation of momentum, conservation of energy, rate of change of entropy, heat conduction equation, and definition of specific heat) and the governing equations (coupled, coupled‐quasi‐static, uncoupled‐quasi‐static, isotropic‐uncoupled‐quasi‐static and isotropic‐uncoupled‐steady) of thermoelasticity for a linear elastic package are briefly mentioned in the present study. The assumptions and limitations of these equations are also highlighted. Furthermore, two electronic packaging examples with closed form solutions using these equations are provided.
Palladium/Silver Multilayers
Authors: Vanden Berghe R. , Demolder S. , Saillé M. , Van Calster A. , Schotte H.
Published: February 2008

The reliability of thick film multilayer systems, based on palladium‐silver conductors, and obtained from several suppliers, is evaluated. A test structure is presented and the impact of different parameters, such as humidity, temperature, voltage bias and presence of overglaze, on the data is discussed. A SEM analysis of the failed samples allows identification of the failure mechanisms as due to flaws (pinholes and inclusions) in the dielectric.
Polystrate and Ultrastrate: Complementary Multichip Module Technologies
Authors: Sutcliffe E.C.
Published: February 2008

CMOS devices are approaching the 50 MHz threshold at which conventional electronic assemblies—based on packaged components (SMD, PGA, etc.) mounted on high‐density printed circuit boards—impose a serious penalty on the speed of the raw die provided by the semiconductor vendors. To improve the packaging density and to reduce the resistive and capacitive loads as well as signal delays at the second level of interconnection, new packaging concepts for VLSI and ULSI components are imperative. Multichip modules (MCM) seem to be the only adequate solution to the interconnect problem. Ultrastrate—the author's company's MCM technology with multilayer thin‐film build‐ups—is briefly presented. Life cycles for products in the electronics industry are becoming ever shorter. Electronics engineers must package more complicated circuits in smaller volumes and in a shorter time. On the other hand, prototyping an MCM from the electrical schematic takes at least 12 weeks. There is as yet no equivalent of a PCB breadboard for MCMs! In response to this situation, Polystrate is a new process which has been developed to provide a flexible and fast prototyping tool for MCMs. It satisfies the most stringent requirements with regard to performance, economics and ease of modification, and offers a very fast turn‐around time. The technological synergies between Ultrastrate and Polystrate allow for a smooth transition between the prototyping and production phases.
Effects of Across Belt Temperature Uniformity on Fired Resistor Values
Authors: Teng Robert K.F. , Berdner Tom , Ethridge M.P.
Published: February 2008

The effects of temperature gradients across the belt width on fired resistor values are well known and become increasingly important in wide belt production conveyor furnaces. This paper discusses the experimental and theoretical study of this problem. Physical data were collected from experiments and the results were analysed statistically. Particular attention was paid to the exit end firing zone because heat losses from this zone differ from that of the other zones. High resistor values at the centre of the belt, gradually decreasing towards both sides, have been observed. This phenomenon seems to be caused by loss of heat radiation to the exit opening at the belt centre. Mathematical models using the basic laws of heat transfer as they apply to the particular structure of the furnace have been developed. The study shows that it is possible to reduce the range of fired thick film resistor values by modifying the temperature conditions near the end zone.
Aspects of Indium Solder Bumping and Indium Bump Bonding Useful for Assembling Cooled Mosaic Sensors
Authors: Plötner M. , Sadowski G. , Rzepka S. , Blasek G.
Published: February 2008

Indium solders are frequently used for interconnections in cooled systems because of their high ductility down to very low temperatures. Very fine contact pitches are required for hybrid mosaic radiation sensors compared with those for conventional flip‐chip technology. This paper presents solutions for bumping and bonding indium bumps based on the measured properties of indium solders in relation to the requirements of, and possibilities for, manufacture of fine pitch solder bump features.
Multi‐chip Modules for Telecom Applications
Authors: Gustafsson K. , Flodman G. , Bakszt M.
Published: February 2008

System performance can be improved by the use of MCM (multi‐chip module) technology. Better signal transmission properties, lower power dissipation if C‐MOS chips are used and decreased physical volume will be obtained. Today MCM is an expensive technique, but the authors' cost analysis shows that it has the potential to become more cost‐effective than the standard technique of using single chip packages. It can also become more cost‐effective to use the MCM technique than to increase the number of gates on the silicon chip over a certain level. In order to study the properties of MCM technology, a project has been started at the authors' company in which a processor application is built up on three different types of MCM substrates.
Voltage Divider Networks for Photomultipliers (PM Bridge): High Voltage Thick Film Resistor System
Authors: Schmitt S. , Kuznicki H.
Published: February 2008

In many nuclear experiments, photomultipliers (PM) with voltage divider networks are required. Very often it is also necessary to locate these PMs in a chamber under vacuum and different problems then appear. Only thick film technology, in contrast to conventional technology, permits resolving them. The characteristics and advantages of these voltage dividers are mentioned.
On the Resistance Increase of Gold‐aluminium Wire Bonds
Authors: Haag J.F.
Published: February 2008

The ageing behaviour of aluminium wire bonds (Al‐1%Si wire, 25 µm diameter) on five different gold thick film inks from three different manufacturers has been investigated. A new mechanism, the oxidation of the gold‐aluminium intermetallics, is proposed to explain the degradation of contact resistance for this system. With this theory the degradation of bond resistance, as well as the ‘healing effect’, can be explained. The oxidation can be proven by ageing in a vacuum. Surface analytical methods have shown the compound Au4Al to be responsible for the oxidation.
Transparent Protective Coating Technique for Amorphous Si Image Sensor
Authors: Tobita T. , Niki K. , Makita T. , Takasago H. , Miki H.
Published: February 2008

To obtain the best moisture‐proof and most reliable protective coating for an amorphous silicon image sensor (A4 documents), three methods of coating and patterning processes and 15 types of resin classified into five kinds of materials were evaluated. Through this study, a screen‐printing method using silicone resin material cured under conditions of 150°C for 60 minutes to form a 60 µm thick protective coating film was selected because of the simplicity of its fabrication process compared with the other two methods. The a‐Si photodiodes were tested under conditions of 121°C‐2 atm. for 300 hours, −30°C to 100°C for 350 cycles and 85°C for 500 hours, and their characteristics were not negatively affected.
VLSI Package Reliability
Authors: Speicher P.S.
Published: February 2008

The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board (PWB). One of the options employed has been tape automated bonding (TAB). However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center (RADC), there is regular assessment (through in‐house failure analysis studies) of parts destined for military and space systems. In addition, Department of Defense (DoD) high tech development programmes, such as very high speed integrated circuits (VHSIC), have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive non‐destructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection (PIND) test failures (internal particles). Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material (potential heat dissipation problems), and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental tests—e.g., salt atmosphere and moisture resistance—provide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and well‐controlled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration (VLSI) devices in severe military and commercial environment applications.
Low Tg Epoxy Adhesives for Thermal Management
Authors: Chung K.K.T. , Avery E. , Boyle A. , Dreier G. , Koehn W. , Govaert G. , Theunissen D.
Published: February 2008

The complexity of microelectronic circuits, their scale of integration and clock speed requirements have been increasing steadily. All these changes have the effect of increasing the power density of the microcircuits. ICs with a power of several watts and an area of over a square centimetre are quite common. Thus, there is more heat generated per device at die, component and substrate‐attach levels of electronic packaging. In order to maintain reliability of finished products, the junction temperature of the constituent devices must be kept low. It has been demonstrated that thermal management can be one key to lowering the cost and increasing the performance life of microelectronic products. The cost‐effectiveness of lowering device temperature has been demonstrated to be dramatic compared with the cost of thermal management materials. Proper thermal management of advanced microelectronic devices has to be addressed at all levels. One should address the problem from the basic level of die‐attach, through component‐attach, and eventually substrate‐attach to thermal drains. Thermal management is almost invariably coupled with a thermally induced stress problem. The increase in temperature at the device level also means a larger fluctuation of temperature from the ambient. Each cycle of on‐off for the device represents one thermal cycle. Stress‐induced failure due to coefficient of thermal expansion (CTE) mismatch is much more acute for higher power devices. In this paper, the authors address the issue of thermally induced stress on the microelectronic product at all levels of packaging, with major emphasis on component and substrate levels. Various ways and examples of reducing or eliminating this stress, which is a major cause of device failures, will be demonstrated. One of the proven methods is through the use of low Tg epoxies with high thermal stability.
Thick‐film Hybrid Applications on Stainless Steel Baseplate
Authors: Lahdenperä M.
Published: February 2008

In this research work thick‐film manufacturing technology on stainless steel baseplates was developed. Adequate adhesion of dielectric IP211 to the steel substrate was achieved only by sand blast roughening. Standard PdAg thick‐film conductors were not solderable to IP211. The solution was to have a separate multilayer dielectric under conductors to be soldered. The reliability of soft soldering and gold wire bonding of thick‐film metallisation on stainless steel and other baseplate materials was evaluated. The technology developed was applied to manufacturing an intelligent signal node. Present expertise enables the manufacture of thick‐film hybrids on stainless steel baseplates. Development of an industrial production line would, however, involve considerable effort.
The Rôle of Rheological Characterisation in the Manufacture of Multilayer Ceramic Capacitors
Authors: McAuley I.
Published: February 2008

The rheology of thick film materials has proven to be a key factor in the fabrication of ceramic capacitors. Alternative techniques have been developed for rheological characterisation which have led to improved raw material control and enhanced product quality.
Interactions between Thick Film Superconductors and Various Metal Substrates
Authors: Hrovat M. , Bernik S. , Kolar D.
Published: February 2008

Interactions between stainless steel and silver and gold based thick film conductors and YBa2Cu3O7 thick film superconductors were studied by SEM and EDX. The stainless steel reacted with the superconducting layer, forming a Ba‐Fe‐O compound on the interface, while BaO‐depleted YBa2Cu3O7 compound transformed into insulating Y2BaCuO5 compound. When YBa2Cu3O7 is fired on a gold thick film conductor, a thin layer of Y2BaCuO5 compound forms between the conductor and the superconducting film. In the case of a thin Ag conductor, BaO diffused through the silver film and reacted with alumina ceramic to the depth of a few μm. When a thicker silver layer (40–50 μm) was used, diffusion did not occur.
A Conformal Mapping Analysis of Polygonal Planar Resistors with Curved Boundaries
Authors: Chaudhry M.A. , Schinzinger R.
Published: February 2008

Introduction of curved boundaries in polygonally shaped integrated circuit planar resistors causes a crease in maximum electric field intensities and current densities present in them, and consequently decreases the likelihood of their failure. The presence of curved boundaries can also decrease the area occupied by the resistor. Therefore, polygonal resistors with curved boundaries can be highly desirable in integrated circuits. Resistances of conductors with curved boundaries are readily computed using conformal mapping, particularly the numerically, extended Schwarz‐Christoffel transformation developed by the authors. The resulting algorithm is applicable to polygonal resistors of arbitrary shape and is easily programmable. Several examples are presented. Rapid convergence and accurate results are obtained.
Accuracy of Temperature Computation in Hybrid Microelectronics
Authors: Kos A.
Published: February 2008

Temperature field computations of hybrid power circuits require considerable numerical effort. This paper presents rules which show both how to limit the number of terms of the Fourier series and how to estimate the error which is the effect of this reduction.
Education in Hybrid Microelectronics
Authors: Atkinson J. , Pitt K. , Williams K.
Published: February 2008

ISHM, acting as a professional body for a very large sector of microelectronics manufacturing and design, naturally takes a strong and active interest in the education and training of people working in its industry. An annual Education Prize is awarded by the Society at either undergraduate or post‐graduate level and sometimes both. The aim of the awards is to encourage the writing up of work completed by students as part of the education route. It may be from an internal project such as a B.Eng. report or a Masters Dissertation. It may also be work done by the student in an industrial placement. These three authors or their institutions have been associated with entries which have been awarded a prize. The winning paper is normally published in Hybrid Circuits.
ISHM news
Authors: Waterfield B. , Griffiths Geoff
Published: February 2008

At the Annual General Meeting of ISHM‐France, held on 12 June 1991, the following were elected:
Silicon Hybrids in Action
Authors: Harcourt R.W. , Zorba O. , Whitaker A.G.
Published: February 2008

The custom hybrid manufacturer must be able to offer the optimal multi‐chip module (MCM) solution from a portfolio of technologies. At present no single interconnect technology satisfies all the desired performance and cost requirements of the range of multi‐chip modules. Instead there is a hierarchy of interconnect technologies which offer various combinations of density, power handling, attenuation, signal transmission, testability and, of course, cost. Silicon hybrids have some specific merits and disadvantages which are discussed and compared with other technologies, such as fineline plated metal on ceramic (FPMC). Some examples are shown of the miniaturisation achieved. The silicon hybrids discussed use thin film interconnect with both conventional inorganic and the newer organic dielectrics.
Crystal Oscillator with Temperature Compensation Realised in Thick Film Technology
Authors: Pavšek M. , Belavič D. , Kunaver U. , Hrovat M.
Published: February 2008

The design of temperature‐compensated quartz crystal oscillators (TCXOs) in thick film hybrid technology is described. TCXOs controlled by varicap diodes are usually realised with discrete NTC thermistors and resistors. Data obtained by precision measurements of voltages on varicap diodes for the same oscillator frequencies over the operating temperature range are used for calculating values of the NTC thermistors and resistors. In most cases these values cannot be found in the Renard scale, with the result that manipulation or ‘juggling’ of values is necessary. The realisation of temperature‐compensating circuits in thick film technology has certain advantages, such as miniaturisation, better characteristics at high frequencies and in particular the possibility to trim thick film resistors and NTC thermistors to values calculated for each oscillator. The method of realisation of TCXOs in thick film hybrid technology was developed and verified on prototypes. The compensation curves were obtained by measuring compensation voltages for each oscillator over the operating temperature range from — 20°C to 70°C. From these data the values of resistors and NTC thermistors were calculated. A computer program was used to minimise frequency instability error as a function of six parameters (resistance). The frequency stability (Δf/f) of TCXOs obtained was better than ±2 ppm.
Multichip Module Technology: The Transition from Research to Manufacture
Authors: Pedder D.J.
Published: February 2008

The benefits of the thin film multichip module (MCM‐D) approach to high density packaging for VLSI devices have now been amply demonstrated by a number of research groups. The successful emergence of a viable multichip module industry from this research base will, however, depend upon the installation of an industry‐wide manufacturing infrastructure. This will have to provide the necessary range of concurrent design capabilities, make pretested bare die available, and include multichip module vendors who can offer an integrated capability in module design, substrate layout and manufacture, advanced module assembly, packaging and test. Each of these areas of MCM‐D technology merits detailed attention in its own right, sufficient to justify many individual papers and presentations. This present paper focuses on just one of these topics and addresses the approach taken by GEC Plessey Semiconductors (GPS) to the development and control of a highly manufacturable MCM‐D silicon substrate process. The GPS ‘Process I’ four‐layer metal, aluminium‐polyimide substrate technology is described, the technology development and process control test structures are detailed and process characterisation data presented.
Copper Thick‐film Firing Optimisation Using a New Nitrogen‐based Atmosphere Control System
Authors: Mellul S. , Dupin P.
Published: February 2008

A new proprietary nitrogen‐based atmosphere control system (Alix 1) has been developed by L'Air Liquide, allowing control and regulation of the oxygen partial pressure in the burnout zone of a copper thick‐film firing furnace. The results of a collaboration programme whose objective was to test this system in industrial production conditions at Power Compact are presented. Use of this new system enables improvement of the adhesion results reached by this company in their copper thick‐film hybrid production and ensures a constant level of performance.
Development of a Cost‐effective and Flexible Bumping Method for Flip‐chip Interconnections
Authors: Liu J.
Published: February 2008

Many bumping techniques for flip‐chip interconnections have been developed based on sputtering and electrolytic plating processes. In order to allow bumping on single chips, a new approach is adopted. Suitable metallisation layers are obtained by chemical plating techniques; bump formation is achieved by wire bonding of lead base wires or reflow melting of atomised spherical powders (solder balls). Flip‐chip modules on silicon substrate are created after reflow soldering in vacuum or in vapour phase. The quality and reliability of the interconnections are characterised by scanning electron microscopy, shear testing, microhardness measurement, non‐destructive testing, temperature and power cycling. It is found that high strength, high quality flip‐chip interconnections can be achieved. The present method is also economically competitive in comparison with sputtering techniques for the formation of metallisation layers.
The Material Science of a Non‐warp, Hermetic, Non‐battery Effect, Crystallising Dielectric for Simplification of Multilayer Hybrid Circuitry Construction
Authors: Sjoeling B. , Turvey S.
Published: February 2008

To meet the hybrid industry's growing need for low‐cost, high‐reliability, high‐density multilayer circuitry, the authors' company has developed a non‐warp, hermetic, non‐battery effect, crystallising dielectric for use with gold (Au) and silver (Ag) ‐based conductors. The crystallising nature of the dielectric, together with the use of glasses which do not contain highly mobile ions, ensures high dielectric Ag‐migration resistance. The crystalline structure of the dielectric also has the advantage of ensuring excellent solderability and bondability of top conductors. This paper will deal with the most important theoretical considerations when developing such a dielectric, together with its main properties and advantages. The results are supported by graphs and diagrams showing the properties of this new material.
Solderability Testing in Hybrid Technology
Authors: Vanden Berghe R.A.L. , Willems B.
Published: February 2008

The solderability of a material is considered as the ability of the surface to be wetted by solder, and the rate at which this process occurs. The solderability of thick film conductors based on palladium—silver, by Pb/Sn/Ag solder, was evaluated using a meniscograph. The influence of the composition of the conductor and that of the temperature of the solderbath on the solderability were measured. The usefulness of meniscographic data for the production line is indicated by showing the relation between the production data, reported as the rate at which a full automated solder machine is operated, and the meniscographic results.
Planar Thick Film Varistors
Authors: Aleksić O.S. , Nikolić P.M. , Grozdić T.D. , Luković
Published: February 2008

Various thick film varistor constructions were made and characterised: ‘sandwich’, ‘interdigitated’ and ‘segmented’ varistors. The varistor active layer thickness, the electrode surface value and shape were varied. The Ul characteristics of these varistors were compared mutually, and with the Ul characteristics of the smallest chip varistors. In accordance with the results obtained, it has been shown that thick film printed varistors composed of ZnO and with additives could be applied as discrete components or integrated into a hybrid circuit.
Thick‐film Fine‐line Fabrication Techniques — Application to Front Metallisation of Solar Cells
Authors: Dziedzic A. , Nijs J. , Szlufcik J.
Published: February 2008

Different techniques applied for the fabrication of thick‐film fine lines have been analysed. The basics, achievements, advantages and disadvantages of improved screen printing, screen printing with metal masks, the direct writing method, offset printing and photoformed or photoetched thick‐film are presented. In addition, current trends in front metallisation of silicon solar cells are described. Based on a critical review, the use of thick‐film fine lines for this purpose is discussed.
Fabrication of High Density Multi‐chip Modules with Standard IC Production Equipment
Authors: De Meulemeester B. , Van Calster A. , De Bruycker A. , Allaert K.
Published: February 2008

Since the first appearance of high density interconnection systems about ten years ago, researchers have tried to exploit this concept to the full. By introducing new technologies and materials, they have succeeded in building a module that equals wafer scale integration (WSI) in speed and efficiency. However, MCMs have not yet experienced rapid growth and acceptance as a result of the large capital investment and rather small volumes involved. This paper sets out to show that MCMs can be fabricated using technology and processes already in existence at most conventional IC and thin‐film production facilities.
Vapour Phase Soldering and Removal of Flux Residues after Soldering in the Electronics Industry: Substitution of Organic Solvents
Authors: Sørensen F. , Styhr Petersen H.J.
Published: February 2008

When providing substitutes for CFC‐113 in processes such as vapour phase soldering and removal of flux residues after soldering in the electronics industry, it is also important to avoid the use of other organic solvents at the same time. Vapour phase soldering can be replaced by soldering in an infra‐red belt oven or by using a closed wave soldering system with an inert gas such as nitrogen. The use of organic solvents in the removal of flux residues can be replaced by the following three procedures: eliminating removal, by using a flux with a low residue content; eliminating removal, by using a flux such as adipic acid (and formic acid) in a closed wave soldering system with an inert gas such as nitrogen; and removal with water using a water‐soluble flux.
Hybrid Substrates for Power Electronic Applications: An Investigation of Thermal Resistance and Mechanical Stress
Authors: Bjorneklett A. , Halbo L. , Kristiansen H. , Nilsen L.M. , Storfossene T. , Tuhus T.
Published: February 2008

A new hybrid substrate technology for power electronic applications has been characterised by thermal resistance and mechanical stress measurements. The new substrate utilises thermal spray technology for deposition of dielectric layer and electrical conductors. The results are compared with the more established technology of alumina substrates with direct copper bonding (DCB) metallisation. Silicon test chips for thermal resistance and mechanical stress measurement were used for the characterisation. The experimental results were compared with finite element analysis and a reasonable agreement was found.
Design Constraints for the Use of Insulated Metal Substrates®
Authors: Fick H.
Published: February 2008

Power electronics used in consumer product assemblies require thermal management. Several current products rely on ‘printed wiring’ designs. These have copper patterns separated from a metal substrate by a performance dielectric. The acceptance of this design concept ensures the availability of insulated metal substrates (IMS) for these applications. Available design guides do not describe the design constraints forced on these assembly designs by the physical characteristics of the materials in use. The following three design issues are discussed in this paper: — Dielectric strength testing does not relate to the proof stress testing required for product agency approval. — There is a special case for conformal coating or the use of potting compounds when IMS assemblies are used. — The choice of the metal substrate is based on quantity, thermal coefficient of expansion and thermal conductivity, often in that order.
ISHM news
Authors: George Barry , Somora M.
Published: February 2008

On 8 October 1992 the ISHM‐Benelux Chapter organised a one‐day conference entitled ‘New Trends in Electronic Packaging and Interconnection’ which took place in the Holiday Inn, Gent, Belgium. This conference was attended by 45 participants from the Benelux countries and Great Britain.
In‐situ Electrical Measurements on Thick Film Dielectrics
Authors: Manca J.V. , De Schepper L. , De Ceuninck W. , D'Olieslager M. , Stals L.M. , Barker M.F. , Pickering C.R. , Craig W.A. , Beyne E. , Roggen J.
Published: February 2008

In this paper, it is shown that the so‐called in‐situ electrical measurement technique is a valuable tool for understanding failure mechanisms in thick film dielectrics. The technique makes it possible to measure important electrical characteristics of thick film dielectric systems in the temperature range from room temperature up to 900°C. This information is essential to understand failure mechanisms and to optimise the system with respect to quality and reliability. Mainly two electrical properties have been investigated: (i) the electrical resistance of the dielectric as a function of temperature and (ii) the spontaneous electromotive force occurring at higher temperatures between two metal layers with the dielectric in between. A significant result of the work is the observation of a close correlation between the leakage current measured through the dielectric at elevated temperatures, and the ability of the dielectric to resist shorting and blistering effects during the preparation of circuits. Secondly, from in‐situ voltage measurements, it was confirmed that the mixed metallurgy system Au(bottom)‐dielectric‐Ag(top) acts at 850°C as a spontaneous battery, and the battery voltage (i.e., the spontaneous electromotive force) was measured. Depending on the type of dielectric, a battery voltage up to 200 mV between the two metal layers was observed. As a result of this spontaneous electromotive force, blistering occurs. The battery voltage was shown to be much smaller in unmixed metallurgy systems with Ag(bottom)‐dielectric‐Ag(top) or Au(bottom)‐dielectric‐Au(top). However, if an external voltage of 300 mV is applied to such a system during a temperature profile up to 850°C, blisters can also be induced. This shows unambiguously that blistering is a voltage driven effect.
Temperature Computations in Power Microcircuits
Authors: Kos A.
Published: February 2008

This paper deals with the computation of thermal fields of power hybrid circuits using the finite difference method (FDM). The FDM is one of the classical methods used for temperature calculation of microcircuits having any shape and any boundary conditions. The equation written in the matrix form, describing thermal equilibrium, is solved using Choleski's method. The need for sufficient computer memory capacity is one of the main problems when using a small personal computer. This work attempts to show how to reduce the necessary computer memory capacity as much as possible. A compromise between memory capacity and CPU time is achieved.
Sensitivity Analysis in the Determination of Thermal Parameters
Authors: Wiedemann M.
Published: February 2008

This paper will describe how methods developed in structural dynamics may be used to solve a problem of microsystem technologies. In microsystem simulation, determination of the physical properties is of considerable interest. The method of thermal wave measurement is often used today to describe the thermal behaviour of microstructures. The simulation of thermal wave effects based on thermal mode vectors and followed by a sensitivity analysis enables the correction of primarily estimated thermal parameters by fitting calculated results with measured information. Model description and sensitivity analysis offer an effective tool for determining thermal parameters by thermal wave measurement in a fast and clear manner. Thermal wave measurement, simulation and sensitivity analysis together may be used for device design as well as for testing.
Adhesives for Electronic Applications
Authors: Adell J.A. , Molina M. , Cavero J.M.
Published: February 2008

This paper describes the results of an analysis carried out on thermally conductive and electrically conductive adhesives, in order to characterise their behaviour for electronics and telecommunications applications.
Singapore's Hybrid Industry in the '90s ‐ the Dynamic Decade?
Authors: Liu F.T.
Published: February 2008

Despite great developments in silicon technology over the past decade, hybrid microelectronics continue to survive for a number of reasons. One reason is the difficulty of achieving acceptable component tolerances for resistors and capacitors in silicon. Another reason is the ability to trim resistors in thick film, which makes it more attractive for use in analogue circuits. Furthermore, if the volume of production is not high enough to justify a high non‐recurring expense (NRE), a hybrid circuit would be a feasible solution. The rediscovery of the advantages of multi‐chip modules (MCMs) will further boost the growth of the hybrid microcircuits market in the '90s. MCMs offer the advantages of high reliability, performance (high speed) and miniaturisation (size and weight). This paper briefly outlines the activities of certain government bodies and tertiary institutions in the field of microelectronics. Emphasis is given to the areas of activity where hybrid industry professionals may participate. Perceptions of trends in the '90s are explored in a way that should inspire and generate enthusiasm among microelectronics professionals.
A Comprehensive Microelectronics Programme: Education and Research at Virginia Polytechnic Institute and State University (VPI & SU)
Authors: Elshabini‐Riad A. , Moore D.J.
Published: February 2008

The Hybrid Microelectronics Laboratory in the Bradley Department of Electrical Engineering at Virginia Polytechnic Institute and State University (VPI & SU), also named Virginia Tech, was established during the 1979–1980 academic year in order to provide classroom/laboratory instruction and research capabilities in the area of hybrid microelectronics. The laboratory was initially designed for the hybrid and thick film areas of microelectronics. Thin film design and fabrication capability was added in the Fall Semester, 1987. Currently, efforts are under way to develop the area of monolithic diffusion and processing of semiconductor wafers using both elemental and compound materials, initiated in the Fall Semester, 1991.
ISHM news
Authors: Heřmanský Vojtěch , Bilinski M. , Binner H. , Lee Joon , Lowrie Dave , Whiteside M.
Published: February 2008

The members of the chapter at the annual meeting held on 27 November 1992 in Brno decided not to split after the separation of Czechoslovakia. It was suggested to organise a larger chapter from the Central European States to provide greater co‐operation and better functioning of the smaller chapters. A new name for the chapter was proposed — Central European Chapter (CEC) — to express neutrality and to point out that the chapter is open to other neighbouring chapters and to new members from the states where no national chapter yet exists.
Industrial Microelectronics towards the Year 2000
Authors: Ohlckers P. , Sundby Avset B. , Bjorneklett A. , Evensen L. , Gakkestad J. , Hanneborg A. , Hansen T. , Kjensmo A. , Kristiansen E. , Kristiansen H. , von der Lippe H. , Nese M. , Nygård E. , Serck‐Hanssen F. , Søråsen O.
Published: February 2008

The Center for Industrial Research (SI), the University of Oslo (UiO) and a group of Norwegian companies have collaborated between 1990 and 1992 in the research programme ‘Industrial Microelectronics’ with a total cost of 30 MNOK. The programme was sponsored by the Norwegian Scientific and Industrial Research Council (NTNF) as one of the twin programmes constituting a national research initiative in microelectronics. The motivation for the programme is the recognition of microelectronics as a key technology commanding the performance and market success of many of the electronics systems from the Norwegian electronics industry towards the year 2000. The main objective is to stimulate industrial innovation by developing, transferring and exploiting knowledge and methods based upon advanced microelectronics. Focused activities are silicon sensor technology, combined analogue/digital design of application‐specific integrated circuits, large scale instrumentation, sensor packaging and thermal management of electronic systems. SI is focusing on applied research, UiO on education, and collaborating Norwegian companies are using the results in their own R&D projects. It is anticipated that the research results will be fully industrialised within 3–5 years. The programme is co‐ordinated with other Norwegian government‐sponsored research activities as well as European research programmes based on microelectronics. The programme is organised in projects and monitored with a set of milestones strongly indicating the achievement of successful industrial innovation, research results of international standing and high‐quality education of key personnel for the industry. Several successful examples of the research results are highlighted: Design and process methodology for double‐sided microstrip silicon radiation sensors for detection of high energy elementary particles, silicon‐to‐silicon and silicon‐to‐thin film anodic bonding processes for sensor fabrication, combined analogue/digital application‐specific integrated circuits for front‐end instrumentation applications, packaging of radiation sensors and thermal management of electronic systems by evaporation cooling. It is concluded that the programme has successfully achieved results in harmony with the objective.
Spin Coating with High Viscosity Photoresist on Square Substrates — Applications in the Thin Film Hybrid Microwave Integrated Circuit Field
Authors: Carcano G. , Ceriani M. , Soglio F.
Published: February 2008

The importance of miniaturisation of hybrid microwave integrated circuits (HMICs) and the increasingly stringent demands on the line‐width control of conductor lines in satellite communications and digital radio systems are well established. The importance of photolithographic processes for achieving accuracy and control of the line width necessary to guarantee performance and repeatability of HMICs is acknowledged. The purpose of this paper is to discuss problems concerning the photoresist deposition process and how spin coating is necessary for obtaining the quality, precision and repeatability required for fine line HMICs for high frequency applications.
Overlapping of Thick Film NTC Thermistors and Resistors: A Way to Optimise Laser Trimming of Narrow Tolerance NTC Thermistors
Authors: Hrovat M. , Belavič D. , Markošek A.
Published: February 2008

The direct overlapping of thick film NTC thermistors and resistors was attempted to enable the trimming of NTC thermistors to relatively narrow tolerances with little influence on beta factors. Different combinations of 1 kohm/□ thick film NTC material (4993, Remex) and 1 and 10 kohm/□RuO2 and ruthenate based thick film resistors (HS‐80 series, Du Pont), fired either together or separately, were tested. The sheet resistivities, TCR and beta factors of these combinations were measured. Microstructures were investigated by SEM and analysed by EDS. The results, i.e., the large decrease of sheet resistivities (up to ten times) and a resistivity vs. temperature dependence which changed from negative to positive TCR for some combinations, indicate the interaction between NTC materials and resistors during the firing process. These interactions are more distinctive for materials fired together. In all cases the beta factors were lower than calculated. Based on these experiments, the ‘best’ thick film resistor paste for NTC/resistor combination (HS‐8041, Du Pont) was chosen. Several layouts with partially or entirely overlapped NTC thermistors/resistors were designed. Unprotected, glass protected or organic protected circuits were laser trimmed. The resistivities and beta factors were measured as a function of resistor geometries and laser cut lengths. The results obtained demonstrated that NTC thermistors, partially overprinted with an ‘ordinary’ thick film resistor, can be trimmed to tolerances around 0.5% without any special precautions during trimming.
Hybrid Chemical and Physical Sensor Arrays
Authors: Atkinson J.K.
Published: February 2008

The University of Southampton has been active in the area of thick‐film sensors since their initial conception through to the present. Recent research at the university has concerned the use of thick‐film sensor arrays for the discrimination of chemical species in both gaseous and dissolved form. In addition, the detection of many physical parameters is now being addressed through the use of arrays of sensing elements with a view to improving on factors such as noise immunity, environmental cross‐sensitivity and long‐term accuracy. In the area of chemical sensing, extensive use has been made of thick‐film technology to allow low‐cost arrays of chemical sensors to be fabricated. The lack of specificity exhibited by the individual sensing elements has been demonstrably overcome through the use of signal processing techniques applied to the outputs of the array of sensors. Thick‐film chemical sensor research currently under way at Southampton includes a UK DTI/SERC funded LINK project concerning dissolved species monitoring for water quality assessment. Additionally, gas sensor arrays for the detection of toxic and flammable gases are being explored as part of a well established ongoing research programme. The use of thick‐film technology for the fabrication of physical sensors has been extensively documented. Current research at the University of Southampton includes an industrially sponsored project involving the use of thick‐film strain sensing resistors in the design of an accelerometer. The use of Z‐axis piezoresistivity and an array approach to solving noise and drift problems is seen as a significant novelty in this work.
Flip‐chip Bonding on Green Tape Ceramic Substrates
Authors: Zakel E. , Kloeser J. , Distler H. , Reichl H.
Published: February 2008

Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip (FC) bonding is a suitable method for high interconnection densities. Compared with wire bonding and TAB, FC provides the highest contact density. This is due to the possibility of using the whole chip surface for bondpads (area bumps). In this paper, an adapted FC technology on green tape ceramic substrates was investigated. In order to reduce the substrate costs, FC bonding was performed directly on the thick film metallisation without the application of thin film technology for the upper substrate layers. Two solder bump metallurgies: PbSn95/5 and Au/Sn solder bumps were applied for fluxless FC bonding on adapted substrate metallisations. Fluxless soldering is performed by single chip bonding and requires substrates with narrow planarity tolerances. An alternative method using a wet eutectic Au/Sn solder paste on the substrate and Au bumps permits the application of substrates with standard planarity tolerances used in thick film applications. A common reflow of all chips of a multichip module is possible. First reliability results of metallurgical analysis and of the mechanical and electrical behaviour of the FC contacts after thermal cycling are presented.
REPORT
Authors: Griffiths Geoff
Published: February 2008

In his introduction to the proceedings, Jean Joly said that the accent in the selection of papers had been on the basis of applications and products rather than materials.
Introduction to Thick Film Fine Line Printing Screens
Authors: Carr B.P.
Published: February 2008

Military and commercial hybrids, using high speed integrated circuits with increased input/output density, require low cost, high reliability thick film circuits providing high density, multilayered interconnections with controllable electrical and mechanical characteristics. To meet these criteria it was necessary to adapt the silk screen printing process, including design, materials and reproduction processes, to cater for ‘thick film’, that is able to reproduce extremely fine lines without sacrificing the edge definition of the circuit layout. Printing screens were developed to deposit gold and silver pastes with line/space widths of 50 microns (0.002 in.) on bare ceramic and 100 microns (0.004 in.) on dielectric layers. Interconnection between layers was achieved with 150 micron (0.006 in.) dielectric via openings with corresponding via‐fill conductive connections (gold or silver). The development of the photo‐image onto the emulsion of the screen was deemed to be the most important single step in determining the final print definition of the circuit's design. The main body of this work was concentrated on this approach. The selection of the screens, emulsion system, UV exposure and development processes are also discussed. A capability circuit (CQC) was produced, consisting of five metal layers with line/spaces of 100 microns connected on each side of the ceramic by front to back lasered ‘through‐hole’ connections of 125 microns (0.005 in.) and layer interconnections through 150 micron (0.006 in.) dielectric vias. This capability circuit is classed as an Electronic Component of Assessed Quality by Capability Approval in accordance with BS 63200.
New Composite Packaging
Authors: Keck S. , Leighton J. , Morgner R.
Published: February 2008

This paper describes some of the benefits of electronic packages manufactured from silicon carbide reinforced aluminium composites. The housings which were analysed and tested consisted of iron‐nickel alloy sidewalls soldered to composite bases. The metal matrix composite bases were produced using Lanxide's PRIMEX™ pressureless metal infiltration process. Hermeticity test results on the base to sidewall seals are presented along with comparative electrical performance of the composite versus conventional base materials. Analysis of the thermal, mechanical and weight performance of this approach is also provided.
Flexible Laser Tracing Systems for Defining Thin Film Hybrid Geometries
Authors: Arnone C. , Giaconia C. , Pace C. , Greco M.
Published: February 2008

A recent programme of technical collaboration between Alelco, DIE of Palermo and CRES of Monreale has led to the development and operative confirmation of a technique for delineating conductive microgeometries on various types of substrates. This technique, using a flexible system of laser microlithography on planar (2‐D) or three‐dimensional (3‐D) surfaces, has led to the development of several types of thin film components for use at both low and high frequencies.