Study of the Effects of GaN Buffer Layer Quality on the dc Characteristics of AlGaN/GaN High Electron Mobility Transistors
Authors: Ahn Shihyun , Zhu Weidi , Dong Chen , Hwang Ya-Hsi , Kim Byung-Jae , Ren Fan , Pearton Stephen J. , Lind Aaron Gregg , Jones Kevin Scott , Kravchenko Ivan 
Published: February 2020

AlGaN/GaN high electron mobility transistors (HEMTs) are promising candidates for high power and high current applications with its high mobility and high breakdown field. Epitaxial films for device substrate are typically grown on sapphire or silicon carbide, SiC, with dislocation densities in the order of 108 - 1010cm-2 due to their thermal coefficient and lattice mismatches. The thinner GaN buffer layers on SiC have been reported to have higher threading dislocation density in the GaN, but lead to higher off-state breakdown voltages. However, thick GaN buffer layers on sapphire and their impact on dc performance have not been widely studied.

In this study, the impact of GaN buffer layer quality on dc and gate-lag pulse performance of AlGaN/GaN HEMTs was studied. Transmission electron microscopy (TEM) was used to measure the dislocation density in the GaN buffer layer of the HEMT samples. Dc characteristics, including drain I-Vs, transfer characteristics, and gate pulsed drain I-V characteristics of the HEMTs, were measured to establish a correlation between the AlGaN/GaN HEMTs’ dc and gate-pulsed performance and GaN buffer layer quality.

AlGaN/GaN HEMT structures grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates were acquired from two different vendors. Both types of wafers had 24% Al concentration in the AlGaN barrier layer. One type of wafer had a 5 µm GaN buffer and the other had a 2 µm GaN buffer layer. HEMT fabrication was started with mesa patterning by conventional optical lithography. The mesa-etching was achieved using a unaxis shuttle-lock reactive ion etcher with inductively coupled plasma module (ICP) for device isolation with a Cl2/Ar plasma. Ohmic metallization of electron-beam evaporated Ti/Al/Ni/Au (25 nm/125 nm/45 nm/100 nm) was patterned by lift-off and subsequently rapid thermally annealed at 850⁰C in a flowing N2 ambient for 45 seconds. Schottky gates of e-beam evaporated Ni/Au (20 nm/80 nm) with 100 μm width and 1 μm length were obtained by standard lift-off patterning. DC current–voltage (I-V) characteristics were measured using an HP4156 parameter analyzer, and gate-lag pulse measurements were measured using an Agilent 8114A pulse generator.

Figure 1 shows the bright field cross-sectional transmission electron microscopy (BF-XTEM) pictures of AlGaN/GaN surface for the top layers of (a) HEMT structure with 2 µm GaN buffer layer, (b) HEMT structure with 5 μm GaN buffer layer as well as the GaN/sapphire interface for the (c) HEMT structure with 2 μm GaN buffer layer, and (d) HEMT structure with 5 μm GaN buffer layer. Dislocations are seen to originate near the GaN/sapphire interface and propagate up through the AlGaN/GaN interface to the surface of both HEMT wafers. However, it is clear that the HEMT structure with 2 μm GaN buffer layer exhibited a much higher defect density. The calculated defect density for 2 μm GaN buffer layer substrate had an order of magnitude higher defect density. However, 5μm GaN buffer layer wafer showed that it was under high strain with larger height difference across the 2 inch with lower radius of curvature. There was no major difference in HEMTs’ dc performance was observed. In the other hand, Figure 2 (a) and (b) shows that gate lag measurement on fabricated HEMTs on 5 μm GaN buffer layer wafer showed no degradation and on 2 μm GaN buffer layer wafer showed the otherwise.

The effects of defect density on HEMT dc and radio frequency performance were studied. HEMTs were fabricated on 2 and 5 μm of GaN buffer layers with the same composition of active layers. Despite there was no significant difference was seen in dc characteristics, significant reduction in pulse measurements was observed on thinner GaN layer HEMTs. These results suggest that the defects created in GaN buffer layer do not largely influence device dc performance but are closely related to high frequency performance.

Figure 1