Vertically Integrated ZRAM toward Extremely Scaled Memory
Authors: Lee Byung-Hyun , Ahn Dae-Chul , Kang Min-Ho , Jeon Seung-Bae , Bang Tewook , Bae Hagyoul , Park Jun-Young , Hong Dae-Won , Park Nam-Soo , Choi Yang-Kyu 
Published: February 2020

Conventional dynamic random access memory (DRAM), which is composed of 1 transistor (1T) and 1 capacitor (1C), has been used as main memory. With the advent of 18 nm DRAM, however, manufacturing of DRAM has been confronted with a few technical challenges for continuous scaling. In particular, the fabrication of a cell capacitor is one of the most insurmountable obstacles for extreme scaling. Under this circumstance, reconsidering a zero capacitor-DRAM (zRAM) that consists of solely 1T is a timely approach. Compared to the conventional DRAM, the main advantages of the zRAM are the cell size reduction and nondestructive reading. Moreover, one of the greatest advantages of the zRAM is that there is no need to make a sense amplifier (S/A) for identifying a data state. This can allow versatile core and periphery circuit architecture. In this regard, the notable increment of data sensing margin (ION
/IOFF
) due to the vertically integrated multi-stacked channels, which do not increase a layout area, is very attractive for future DRAM technology.

As mentioned above, memory device has considerably been miniaturized for improving productivity as well as performance and lowering fabrication cost. But, suppression of the short-channel effects (SCEs) stemmed from continuous miniaturization has been a crucial concern. Therefore a three-dimensional (3-D) structured transistor has been developed beyond a conventional two-dimensional (2-D) transistor. Among various 3-D structures, a gate-all-around (GAA)-based silicon nanowire (SiNW), which is ranked at the end of the roadmap, showed the strongest gate controllability and thereby effectively suppressed the SCEs. On the contrary, the extreme scaling of the SiNW (e.g., diameter (dNW
) of the SiNW) inevitably sacrifices ION
because of increased parasitic resistance and reduced density of 2-D electron gas, even though it is attractive to minimize IOFF
. Thus there is no choice but to compromise the controllability of IOFF
and the drivability of ION
. In this regard, vertically integrated multi-stacked channels can recover the sacrificed ION
, which was caused by extremely scaled dNW
for the reduction of IOFF
. Up to date, there were a few reports to describe the vertical stacking of the SiNWs to provide high performance with good scalability and to suppress the SCEs. As the transition to the next phase, hybrid integration to combine zRAM and the vertically integrated multi-stacked GAA SiNW channels can lead to driving the extremely scaled DRAM for high performance and enlarged memory window even without the S/A.

In this work, vertically integrated-zRAM (VI-zRAM) comprised of the GAA SiNW channels, which were implemented to a bulk silicon substrate, is demonstrated for the first time. The vertical stacking of the SiNW, which is the most critical procedure in the entire fabrication, is achieved by employing the one-route all-dry etching process (ORADEP). Unlike previous works, the ORADEP produced the vertically integrated multi-stacked SiNWs without any stiction failure thus it harnessed high controllability and reproducibility with process simplicity, i.e., just one-route etching. Representative images of the VI-zRAM with the GAA SiNW channels that stacked up to five-story, were clearly shown with the aid of high-resolution transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS). In the TEM image, the clear separation of each SiNW fully surrounded by the poly-Si gate proves the complete GAA structure. Undamaged crystallinity of the fabricated SiNW was approved by the fast Fourier transform (FFT) image. Hence it supports that there are no process related defects originated from optimized ORADEP. Compared with the single SiNW channel-based zRAM, ION
is threefold increased at the three-story channels and fivefold enhanced at the five-story channels without significant degradation of other device parameters such as IOFF
and subthreshold slope. This increase of ION
by the number of SiNW without both the sacrifice of other performances and the extra increment of the cell size, allows us to project the ultimate DRAM at the endpoint of the roadmap. In addition, the VI-zRAM showed reliable switching endurance with negligible change of memory characteristics. Thus it is capable of identifying the data state without the S/A. In terms of the chip size reduction, no use of the S/A can increasingly be favored for continuous DRAM scaling. It reveals that additional versatile circuit architecture to replace presumable S/A can be allowed. Throughout the demonstration of the fabricated VI-zRAM by the ORADEP process, it will drive ultimate scaled DRAM technology toward the roadmap end.

Figure 1