bluuebunny/crossref_metadata_2025 huggingface dataset:
Relative Contributions of Lipooligosaccharide Inner and Outer Core Modifications to Nontypeable Haemophilus influenzae Pathogenesis
Authors: Morey Pau , Viadas Cristina , Euba Begoña , Hood Derek W. , Barberán Montserrat , Gil Carmen , Grilló María Jesús , Bengoechea José Antonio , Garmendia Junkal
Published: August 2013

Nontypeable
Haemophilus influenzae
(NTHi) is a frequent commensal of the human nasopharynx that causes opportunistic infection in immunocompromised individuals. Existing evidence associates lipooligosaccharide (LOS) with disease, but the specific and relative contributions of NTHi LOS modifications to virulence properties of the bacterium have not been comprehensively addressed. Using NTHi strain 375, an isolate for which the detailed LOS structure has been determined, we compared systematically a set of isogenic mutant strains expressing sequentially truncated LOS. The relative contributions of 2-keto-3-deoxyoctulosonic acid, the triheptose inner core, oligosaccharide extensions on heptoses I and III, phosphorylcholine, digalactose, and sialic acid to NTHi resistance to antimicrobial peptides (AMP), self-aggregation, biofilm formation, cultured human respiratory epithelial infection, and murine pulmonary infection were assessed. We show that
opsX
,
lgtF
,
lpsA
,
lic1
, and
lic2A
contribute to bacterial resistance to AMP;
lic1
is related to NTHi self-aggregation;
lgtF
,
lic1
, and
siaB
are involved in biofilm growth;
opsX
and
lgtF
participate in epithelial infection; and
opsX
,
lgtF
, and
lpsA
contribute to lung infection. Depending on the phenotype, the involvement of these LOS modifications occurs at different extents, independently or having an additive effect in combination. We discuss the relative contribution of LOS epitopes to NTHi virulence and frame a range of pathogenic traits in the context of infection.
The Acyl-Homoserine Lactone Synthase YenI from Yersinia enterocolitica Modulates Virulence Gene Expression in Enterohemorrhagic Escherichia coli O157:H7
Authors: Nguyen Y N. , Sheng Haiqing , Dakarapu Rambabu , Falck John R. , Hovde Carolyn J. , Sperandio Vanessa
Published: August 2013

The human pathogen enterohemorrhagicEscherichia coli(EHEC) O157:H7 colonizes the rectoanal junction (RAJ) in cattle, its natural reservoir. Colonization at the RAJ poses a serious risk for fecal shedding and contamination of the environment. We previously demonstrated that EHEC senses acyl-homoserine lactones (AHLs) produced by the microbiota in the rumen to activate thegadacid resistance genes necessary for survival through the acidic stomachs in cattle and to repress the locus of enterocyte effacement (LEE) genes important for colonization of the RAJ, but unnecessary in the rumen. Devoid of AHLs, the RAJ is the prominent site of colonization of EHEC in cattle. To determine if the presence of AHLs in the RAJ could repress colonization at this site, we engineered EHEC to express theYersinia enterocoliticaAHL synthase geneyenI, which constitutively produces AHLs, to mimic a constant exposure of AHLs in the environment. TheyenI+EHEC produces oxo-C6-homoserine lactone (oxo-C6-HSL) and had a significant reduction in LEE expression, effector protein secretion, and attaching and effacing (A/E) lesion formationin vitrocompared to the wild type (WT). TheyenI+EHEC also activated expression of thegadgenes. To assess whether AHL production, which decreases LEE expression, would decrease RAJ colonization by EHEC, cattle were challenged at the RAJ with WT oryenI+EHEC. Although theyenI+EHEC colonized the RAJ with efficiency equal to that of the WT, there was a trend for the cattle to shed the WT strain longer than theyenI+EHEC.
Cellular Response to Trypanosoma cruzi Infection Induces Secretion of Defensin α-1, Which Damages the Flagellum, Neutralizes Trypanosome Motility, and Inhibits Infection
Authors: Johnson Candice A. , Rachakonda Girish , Kleshchenko Yuliya Y. , Nde Pius N. , Madison M. Nia , Pratap Siddharth , Cardenas Tatiana C. , Taylor Chase , Lima Maria F. , Villalta Fernando
Published: August 2013

Human defensins play a fundamental role in the initiation of innate immune responses to some microbial pathogens. Here we show that colonic epithelial model HCT116 cells respond toTrypanosoma cruziinfection by secreting defensin α-1, which reduces infection. We also report the early effects of defensin α-1 on invasive trypomastigotes that involve damage of the flagellar structure to inhibit parasite motility and reduce cellular infection. Short exposure of defensin α-1 to trypomastigotes shows that defensin α-1 binds to the flagellum, resulting in flagellar membrane and axoneme alterations, followed by breaking of the flagellar membrane connected to the trypanosome body, leading to detachment and release of the parasite flagellum. In addition, defensin α-1 induces a significant reduction in parasite motility in a peptide concentration-dependent manner, which is abrogated by anti-defensin α-1 IgG. Preincubation of trypomastigotes with a concentration of defensin α-1 that inhibits 50% trypanosome motility significantly reduced cellular infection by 80%. Thus, human defensin α-1 is an innate immune molecule that is secreted by HCT116 cells in response toT. cruziinfection, inhibitsT. cruzimotility, and plays an important role in reducing cellular infection. This is the first report showing a novel cellular innate immune response to a human parasite by secretion of defensin α-1, which neutralizes the motility of a human parasite to reduce cellular infection. The mode of activity of human defensin α-1 againstT. cruziand its function may provide insights for the development of new antiparasitic strategies.
Mri Evaluation of Metal Acupuncture Needles
Authors: Mei Ling , Long Xiaojing , Diao Yanjun , Yu Haibo , Yang Wanzhang , Standish Leanna J , Qiu Bensheng
Published: August 2013

Objective

To evaluate the MR compatibility of three metal acupuncture needles (a standard stainless steel needle, a gold needle and an austenitic stainless steel needle) by comparing their imaging artefacts, radiofrequency heating effects and ease of operation.

Methods

The MRI artefacts of the three metal needles were first evaluated by placing them in an agar gel phantom and performing MRI of the phantom. The increase in temperature during MRI was recorded using an MR-compatible fibreoptic thermometer. MRI of acupuncture at SP6 was performed using the MR-compatible gold needle and the austenitic stainless steel needle.

Results

The standard stainless steel acupuncture needle produced large imaging artefacts on MRI. The gold needle was superior for MRI but not rigid enough for some clinical applications such as scalp acupuncture. The austenitic stainless steel needle is non-ferromagnetic and compatible with MRI. None of these acupuncture needles introduced radiofrequency heating during MRI.

Conclusions

The evaluation of MR compatibility showed that gold and austenitic stainless steel needles are MR-compatible and therefore can be used for MRI of acupuncture.
Motivating factors and perceived barriers to participating in continuing professional development: a national survey of veterinary surgeons
Authors: Dale V. H. M. , Pierce S. E. , May S. A.
Published: August 2013

Although continuing professional development (CPD) is regarded as mandatory by the Royal College of Veterinary Surgeons, it is not yet a statutory requirement. To understand what motivates veterinary surgeons to engage in CPD and perceived barriers to participation, a national survey was administered to a sample of the profession. The study sought to report overall opinion and to compare the views of different groups in terms of decade of graduation, gender, employment status, area of employment and position in the workplace. The results of the study are encouraging in that recent graduates would like to engage in more CPD, compared with their predecessors, and are the most intrinsically and extrinsically motivated. However, significant barriers to participation exist, including personal barriers, a lack of workplace support and a lack of CPD activities at a suitable time, location or level. Part‐time workers reported higher barriers than full‐time workers. Although the majority (90 per cent) of respondents receive all or part of their CPD funding from employers, a significant proportion (41 per cent) are required to fund at least part of their CPD. First‐opinion practitioners reported significantly less access to a professional library, which has implications for lifelong learning and the practice of evidence‐based veterinary medicine.
Does postharvest silviculture improve convergence of avian communities in managed and old-growth boreal forests?
Authors: Thompson Ian D. , Kirk David A. , Jastrebski Christopher
Published: August 2013

Habitat change following forest management may reduce biodiversity in boreal forests, as it has done globally in many forest types. Postharvest silviculture (PHS) is implemented to improve the yield of commercial tree species and has been applied to large areas of boreal forests. PHS may also influence animal communities and so we assessed songbird responses to these treatments in stands 20–52 years old in Ontario, Canada. We expected that several old-forest species would respond positively to PHS, that avian assemblages in treated forests would be distinct from those in untreated managed forests regardless of age, and that assemblages in our oldest treated stands would begin to converge with those of mature unmanaged forests. PHS stands had higher conifer density than naturally regenerating managed stands. The avian assemblage differed between treated and untreated stands at 20–30 years but not at 31–52 years. Convergence with old-forest assemblages was incomplete at 31–52 years after harvesting, although abundances of seven of 13 old-forest species did not differ from those in unmanaged forests. Of 10 old-forest species with competitive models, only Bay-breasted Warbler (Setophaga castanea (Wilson, 1810)) responded positively to PHS at the stand level, whereas two species responded positively at the landscape scale. Brown Creeper (Certhia americana Bonaparte, 1838), Boreal Chickadee (Poecile hudsonicus Forster, 1772), and Blackburnian Warbler (Setophaga fusca (Müller, 1776)) were absent from most managed stands and so require specific attention in planning for forest management, including retention of old-forest and delaying harvest of second-growth stands to ensure their occurrence and persistence.
TRANSVERSAL KILLING AND TWISTOR SPINORS ASSOCIATED TO THE BASIC DIRAC OPERATORS
Authors: IONESCU ADRIAN MIHAI , SLESAR VLADIMIR , VISINESCU MIHAI , VÎLCU GABRIEL EDUARD
Published: August 2013

We study the interplay between the basic Dirac operator and the transversal Killing and twistor spinors. In order to obtain results for the general Riemannian foliations with bundle-like metric, we consider transversal Killing spinors that appear as natural extension of the harmonic spinors associated with the basic Dirac operator. In the case of foliations with basic-harmonic mean curvature, it turns out that this type of spinors coincide with the standard definition. We obtain the corresponding version of classical results on closed Riemannian manifold with spin structure, and extending some previous results.
DIRAC EQUATION IN (1+3)- AND (2+2)-DIMENSIONS
Authors: NIETO J. A. , PEREYRA C.
Published: August 2013

We develop a systematic method to derive the Majorana representation of the Dirac equation in (1+3)-dimensions. We compare with similar approach in (2+2)-dimensions. We argue that our formalism can be useful to have a better understanding of possible Majorana fermions.
Synthesis of symmetrical and unsymmetrical subphthalocyanine dimers containing a hydroquinone bridge
Authors: Viswanath Lakshmi C. Kasi , Shirtcliff Laura D. , Berlin K. Darrell
Published: August 2013

Three novel hydroquinone-based symmetrically and unsymmetrically substituted subphthalocyanine (SubPc) dimers have been synthesized through the axial substitution of the macrocycle. The mono SubPc hydroquinone derivative (Hq-SubPc) first prepared acts as a nucleophile which replaces the chlorine atom of the second SubPc molecule to form the dimer. The dimers were obtained by reacting hydroquinone and the respective SubPcs in a 1:1 molar ratio in toluene at 180 °C in a pressure vessel. This new approach allowed stoichiometric quantities of reactants to be utilized. All dimers were characterized by 1 H NMR, 13 C NMR, UV-vis, fluorescence and mass spectral analysis.
Architectures of flexible symmetric key crypto engines—a survey
Authors: Bossuet Lilian , Grand Michael , Gaspar Lubos , Fischer Viktor , Gogniat Guy
Published: August 2013

Throughput, flexibility, and security form the design trilogy of reconfigurable crypto engines; they must be carefully considered without reducing the major role of classical design constraints, such as surface, power consumption, dependability, and cost. Applications such as network security, Virtual Private Networks (VPN), Digital Rights Management (DRM), and pay per view have drawn attention to these three constraints. For more than ten years, many studies in the field of cryptographic engineering have focused on the design of optimized high-throughput hardware cryptographic cores (e.g., symmetric and asymmetric key block ciphers, stream ciphers, and hash functions). The flexibility of cryptographic systems plays a very important role in their practical application. Reconfigurable hardware systems can evolve with algorithms, face up to new types of attacks, and guarantee interoperability between countries and institutions. The flexibility of reconfigurable crypto processors and crypto coprocessors has reached new levels with the emergence of dynamically reconfigurable hardware architectures and tools. Last but not least, the security of systems that handle confidential information needs to be thoroughly evaluated at the design stage in order to meet security objectives that depend on the importance of the information to be protected and on the cost of protection. Usually, designers tackle security problems at the same time as other design constraints and in many cases target only one security objective, for example, a side-channel attack countermeasures, fault tolerance capability, or the monitoring of the device environment. Only a few authors have addressed all three design constraints at the same time. In particular, key management security (e.g., secure key generation and transmission, the use of a hierarchical key structure composed of session keys and master keys) has frequently been neglected to the benefit of performance and/or flexibility. Nevertheless, a few authors propose original processor architectures based on multi-crypto-processor structures and reconfigurable cryptographic arrays. In this article, we review published works on symmetric key crypto engines and present current trends and design challenges.
Semantic trajectories modeling and analysis
Authors: Parent Christine , Spaccapietra Stefano , Renso Chiara , Andrienko Gennady , Andrienko Natalia , Bogorny Vania , Damiani Maria Luisa , Gkoulalas-Divanis Aris , Macedo Jose , Pelekis Nikos , Theodoridis Yannis , Yan Zhixian
Published: August 2013

Focus on movement data has increased as a consequence of the larger availability of such data due to current GPS, GSM, RFID, and sensors techniques. In parallel, interest in movement has shifted from raw movement data analysis to more application-oriented ways of analyzing segments of movement suitable for the specific purposes of the application. This trend has promoted semantically rich trajectories, rather than raw movement, as the core object of interest in mobility studies. This survey provides the definitions of the basic concepts about mobility data, an analysis of the issues in mobility data management, and a survey of the approaches and techniques for: (i) constructing trajectories from movement tracks, (ii) enriching trajectories with semantic information to enable the desired interpretations of movements, and (iii) using data mining to analyze semantic trajectories and extract knowledge about their characteristics, in particular the behavioral patterns of the moving objects. Last but not least, the article surveys the new privacy issues that arise due to the semantic aspects of trajectories.
Survey and taxonomy of botnet research through life-cycle
Authors: Rodríguez-Gómez Rafael A. , Maciá-Fernández Gabriel , García-Teodoro Pedro
Published: August 2013

Of all current threats to cybersecurity, botnets are at the top of the list. In consequence, interest in this problem is increasing rapidly among the research community and the number of publications on the question has grown exponentially in recent years. This article proposes a taxonomy of botnet research and presents a survey of the field to provide a comprehensive overview of all these contributions. Furthermore, we hope to provide researchers with a clear perspective of the gaps that remain to be filled in our defenses against botnets. The taxonomy is based upon the botnet's life-cycle, defined as the sequence of stages a botnet needs to pass through in order to reach its goal.

This approach allows us to consider the problem of botnets from a global perspective, which constitutes a key difference from other taxonomies that have been proposed. Under this novel taxonomy, we conclude that all attempts to defeat botnets should be focused on one or more stages of this life-cycle. In fact, the sustained hindering of any of the stages makes it possible to thwart a botnet's progress and thus render it useless. We test the potential capabilities of our taxonomy by means of a survey of current botnet research, and find it genuinely useful in understanding the focus of the different contributions in this field.
Analyzing and defending against web-based malware
Authors: Chang Jian , Venkatasubramanian Krishna K. , West Andrew G. , Lee Insup
Published: August 2013

Web-based malware is a growing threat to today's Internet security. Attacks of this type are prevalent and lead to serious security consequences. Millions of malicious URLs are used as distribution channels to propagate malware all over the Web. After being infected, victim systems fall in the control of attackers, who can utilize them for various cyber crimes such as stealing credentials, spamming, and distributed denial-of-service attacks. Moreover, it has been observed that traditional security technologies such as firewalls and intrusion detection systems have only limited capability to mitigate this new problem.

In this article, we survey the state-of-the-art research regarding the analysis of—and defense against—Web-based malware attacks. First, we study the attack model, the root cause, and the vulnerabilities that enable these attacks. Second, we analyze the status quo of the Web-based malware problem. Third, three categories of defense mechanisms are discussed in detail: (1) building honeypots with virtual machines or signature-based detection system to discover existing threats; (2) using code analysis and testing techniques to identify the vulnerabilities of Web applications; and (3) constructing reputation-based blacklists or smart sandbox systems to protect end-users from attacks. We show that these three categories of approaches form an extensive solution space to the Web-based malware problem. Finally, we compare the surveyed approaches and discuss possible future research directions.
A survey on reactive programming
Authors: Bainomugisha Engineer , Carreton Andoni Lombide , Cutsem Tom van , Mostinckx Stijn , Meuter Wolfgang de
Published: August 2013

Reactive programming has recently gained popularity as a paradigm that is well-suited for developing event-driven and interactive applications. It facilitates the development of such applications by providing abstractions to express time-varying values and automatically managing dependencies between such values. A number of approaches have been recently proposed embedded in various languages such as Haskell, Scheme, JavaScript, Java, .NET, etc. This survey describes and provides a taxonomy of existing reactive programming approaches along six axes: representation of time-varying values, evaluation model, lifting operations, multidirectionality, glitch avoidance, and support for distribution. From this taxonomy, we observe that there are still open challenges in the field of reactive programming. For instance, multidirectionality is supported only by a small number of languages, which do not automatically track dependencies between time-varying values. Similarly, glitch avoidance, which is subtle in reactive programs, cannot be ensured in distributed reactive programs using the current techniques.
Critical success factors in enterprise resource planning systems
Authors: Shaul Levi , Tauber Doron
Published: August 2013

Organizations perceive ERP as a vital tool for organizational competition as it integrates dispersed organizational systems and enables flawless transactions and production. This review examines studies investigating Critical Success Factors (CSFs) in implementing Enterprise Resource Planning (ERP) systems. Keywords relating to the theme of this study were defined and used to search known Web engines and journal databases for studies on both implementing ERP systems per se and integrating ERP systems with other well- known systems (e.g., SCM, CRM) whose importance to business organizations and academia is acknowledged to work in a complementary fashion. A total of 341 articles were reviewed to address three main goals. This study structures previous research by presenting a comprehensive taxonomy of CSFs in the area of ERP. Second, it maps studies, identified through an exhaustive and comprehensive literature review, to different dimensions and facets of ERP system implementation. Third, it presents studies investigating CSFs in terms of a specific ERP lifecycle phase and across the entire ERP life cycle. This study not only reviews articles in which an ERP system is the sole or primary field of research, but also articles that refer to an integration of ERP systems and other popular systems (e.g., SCM, CRM). Finally it provides a comprehensive bibliography of the articles published during this period that can serve as a guide for future research.
Sharing computer science education ideas
Authors: Fraiman Zeev , Kanel Evgeny , Gal-Ezer Judith , Lapidot Tami
Published: August 2013

This article describes a unique Israeli-Russian project, in which Israeli high school computer science (CS) teachers promote curricular reform in the Russian region of Penza, based on the Israeli high school CS curriculum. The reform involves local schools, universities, the hi-tech industry and local government officials. It includes changes in courses, textbooks and other teaching materials. The Israeli teachers provided workshops to assist the Russian teachers in the assimilation of the reform. This collaboration may encourage other countries to collaborate and not necessarily re-invent the wheel; for some countries it can serve as a catalyst to assist in bringing computer science education into schools.
SPIRE
Authors: Jia Ning , Yang Chun , Wang Jing , Tong Dong , Wang Keyi
Published: August 2013

Dynamic binary translation system must perform an address translation for every execution of indirect branch instructions. The procedure to convert Source binary Program Counter (SPC) address to Translated Program Counter (TPC) address always takes more than 10 instructions, becoming a major source of performance overhead. This paper proposes a novel mechanism called SPc-Indexed REdirecting (SPIRE), which can significantly reduce the indirect branch handling overhead. SPIRE doesn't rely on hash lookup and address mapping table to perform address translation. It reuses the source binary code space to build a SPC-indexed redirecting table. This table can be indexed directly by SPC address without hashing. With SPIRE, the indirect branch can jump to the originally SPC address without address translation. The trampoline residing in the SPC address will redirect the control flow to related code cache. Only 2-6 instructions are needed to handle an indirect branch execution. As part of the source binary would be overwritten, a shadow page mechanism is explored to keep transparency of the corrupt source binary code page. Online profiling is adopted to reduce the memory overhead.

We have implemented SPIRE on an x86 to x86 DBT system, and discussed the implementation issues on different guest and host architectures. The experiments show that, compared with hash lookup mechanism, SPIRE can reduce the performance overhead by 36.2% on average, up to 51.4%, while only 5.6% extra memory is needed.

SPIRE can cooperate with other indirect branch handling mechanisms easily, and we believe the idea of SPIRE can also be applied on other occasions that need address translation.
Improving dynamic binary optimization through early-exit guided code region formation
Authors: Hsu Chun-Chen , Liu Pangfeng , Wu Jan-Jan , Yew Pen-Chung , Hong Ding-Yong , Hsu Wei-Chung , Wang Chien-Min
Published: August 2013

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces.

In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multi-threaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NET-variant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of up to 72% (27% on average), and to 49% (23% on average) for IA32 and ARM, respectively.
Superblock compilation and other optimization techniques for a Java-based DBT machine emulator
Authors: Kaufmann Marco , Spallek Rainer G.
Published: August 2013

Superblock compilation techniques such as control flow graph (CFG) or trace compilation have become a widely adopted approach to increase the performance of dynamically compiling virtual machines even further. While this was shown to be successful for many conventional virtual machines, it did not result in a higher performance for Java-based DBT machine emulators so far. These emulators dynamically translate application binaries of a target machine into Java bytecode, which is then eventually compiled into the native code of the emulating host by the Java Virtual Machine (JVM). Successful superblock compilation techniques for this class of emulators must consider the special requirements that result from the two-stage translation as well as the characteristics of the JVM, such as the inability of most Java JIT compilers to handle large bytecode methods efficiently.

In this paper, we present a superblock compilation approach for a Java-based DBT machine emulator that generates a performance increase of up to 90 percent and of 32 percent on average. The key idea of our design is to provide a large scope over the control flow of target applications across basic block boundaries for the JVM, while still keeping small bytecode methods for the execution units.

In addition, we also present two further optimizations -- interpreter context elimination and program counter elimination -- which increase the emulation performance by 16 percent again. In total, the optimization techniques discussed in this paper provide an average performance gain of 48 percent for the surveyed emulator.
Optimizing virtual machine live storage migration in heterogeneous storage environment
Authors: Zhou Ruijin , Liu Fang , Li Chao , Li Tao
Published: August 2013

Virtual machine (VM) live storage migration techniques significantly increase the mobility and manageability of virtual machines in the era of cloud computing. On the other hand, as solid state drives (SSDs) become increasingly popular in data centers, VM live storage migration will inevitably encounter heterogeneous storage environments. Nevertheless, conventional migration mechanisms do not consider the speed discrepancy and SSD's wear-out issue, which not only causes significant performance degradation but also shortens SSD's lifetime. This paper, for the first time, addresses the efficiency of VM live storage migration in heterogeneous storage environments from a multi-dimensional perspective, i.e., user experience, device wearing, and manageability. We derive a flexible metric (migration cost), which captures various design preference. Based on that, we propose and prototype three new storage migration strategies, namely: 1) Low Redundancy (LR), which generates the least amount of redundant writes; 2) Source-based Low Redundancy (SLR), which keeps the balance between IO performance and write redundancy; and 3) Asynchronous IO Mirroring, which seeks the highest IO performance. The evaluation of our prototyped system shows that our techniques outperform existing live storage migration by a significant margin. Furthermore, by adaptively mixing our proposed schemes, the cost of massive VM live storage migration can be even lower than that of only using the best of individual mechanism.
Parallelizing live migration of virtual machines
Authors: Song Xiang , Shi Jicheng , Liu Ran , Yang Jian , Chen Haibo
Published: August 2013

Live VM migration is one of the major primitive operations to manage virtualized cloud platforms. Such operation is usually mission-critical and disruptive to the running services, and thus should be completed as fast as possible. Unfortunately, with the increasing amount of resources configured to a VM, such operations are becoming increasingly time-consuming.

In this paper, we make a comprehensive analysis on the parallelization opportunities of live VM migration on two popular open-source VMMs (i.e., Xen and KVM). By leveraging abundant resources like CPU cores and NICs in contemporary server platforms, we design and implement a system called PMigrate that leverages data parallelism and pipeline parallelism to parallelize the operation. As the parallelization framework requires intensive mmap/munmap operations that tax the address space management system in an operating system, we further propose an abstraction called
range lock
, which improves scalability of concurrent mutation to the address space of an operating system (i.e., Linux) by selectively replacing the per-process address space lock inside kernel with dynamic and fine-grained
range locks
that exclude costly operations on the requesting address range from using the per-process lock. Evaluation with our working prototype on Xen and KVM shows that PMigrate accelerates the live VM migration ranging from 2.49X to 9.88X, and decreases the downtime ranging from 1.9X to 279.89X. Performance analysis shows that our integration of
range lock
to Linux significantly improves parallelism in mutating the address space in VM migration and thus boosts the performance ranging from 2.06X to 3.05X. We also show that PMigrate makes only small disruption to other co-hosted production VMs.
Traveling forward in time to newer operating systems using ShadowReboot
Authors: Yamada Hiroshi , Kono Kenji
Published: August 2013

Operating system (OS) reboots are an essential part of updating kernels and applications on laptops and desktop PCs. Long downtime during OS reboots severely disrupts users' computational activities. This long disruption discourages the users from conducting OS reboots, failing to enforce them to conduct software updates. This paper presents ShadowReboot, a virtual machine monitor (VMM)-based approach that shortens downtime of OS reboots in software updates. ShadowReboot conceals OS reboot activities from user's applications by spawning a VM dedicated to an OS reboot and systematically producing the rebooted state where the updated kernel and applications are ready for use. ShadowReboot provides an illusion to the users that the guest OS travels forward in time to the rebooted state. ShadowReboot offers the following advantages. It can be used to apply patches to the kernels and even system configuration updates. Next, it does not require any special patch requiring detailed knowledge about the target kernels. Lastly, it does not require any target kernel modification. We implemented a prototype in VirtualBox 4.0.10 OSE. Our experimental results show that ShadowReboot successfully updated software on unmodified commodity OS kernels and shortened the downtime of commodity OS reboots on five Linux distributions (Fedora, Ubuntu, Gentoo, Cent, and SUSE) by 91 to 98%.
A modular approach to on-stack replacement in LLVM
Authors: Lameed Nurudeen A. , Hendren Laurie J.
Published: August 2013

On-stack replacement (OSR) is a technique that allows a virtual machine to interrupt running code during the execution of a function/method, to re-optimize the function on-the-fly using an optimizing JIT compiler, and then to resume the interrupted function at the point and state at which it was interrupted. OSR is particularly useful for programs with potentially long-running loops, as it allows dynamic optimization of those loops as soon as they become hot.

This paper presents a modular approach to implementing OSR for the LLVM compiler infrastructure. This is an important step forward because LLVM is gaining popular support, and adding the OSR capability allows compiler developers to develop new dynamic techniques. In particular, it will enable more sophisticated LLVM-based JIT compiler approaches. Indeed, other compiler/VM developers can use our approach because it is a clean modular addition to the standard LLVM distribution. Further, our approach is defined completely at the LLVM-IR level and thus does not require any modifications to the target code generation.

The OSR implementation can be used by different compilers to support a variety of dynamic optimizations. As a demonstration of our OSR approach, we have used it to support dynamic inlining in McVM. McVM is a virtual machine for MATLAB which uses a LLVM-based JIT compiler. MATLAB is a popular dynamic language for scientific and engineering applications that typically manipulate large matrices and often contain long-running loops, and is thus an ideal target for dynamic JIT compilation and OSRs. Using our McVM example, we demonstrate reasonable overheads for our benchmark set, and performance improvements when using it to perform dynamic inlining.
Preemptable ticket spinlocks
Authors: Ouyang Jiannan , Lange John R.
Published: August 2013

When executing inside a virtual machine environment, OS level synchronization primitives are faced with significant challenges due to the scheduling behavior of the underlying virtual machine monitor. Operations that are ensured to last only a short amount of time on real hardware, are capable of taking considerably longer when running virtualized. This change in assumptions has significant impact when an OS is executing inside a critical region that is protected by a spinlock. The interaction between OS level spinlocks and VMM scheduling is known as the Lock Holder Preemption problem and has a significant impact on overall VM performance. However, with the use of ticket locks instead of generic spinlocks, virtual environments must also contend with waiters being preempted before they are able to acquire the lock. This has the effect of blocking access to a lock, even if the lock itself is available. We identify this scenario as the Lock Waiter Preemption problem. In order to solve both problems we introduce Preemptable Ticket spinlocks, a new locking primitive that is designed to enable a VM to always make forward progress by relaxing the ordering guarantees offered by ticket locks. We show that the use of Preemptable Ticket spinlocks improves VM performance by 5.32X on average, when running on a non paravirtual VMM, and by 7.91X when running on a VMM that supports a paravirtual locking interface, when executing a set of microbenchmarks as well as a realistic e-commerce benchmark.
Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on GPU
Authors: Wu Bo , Zhao Zhijia , Zhang Eddy Zheng , Jiang Yunlian , Shen Xipeng
Published: August 2013

The performance of Graphic Processing Units (GPU) is sensitive to irregular memory references. Some recent work shows the promise of data reorganization for eliminating non-coalesced memory accesses that are caused by irregular references. However, all previous studies have employed simple, heuristic methods to determine the new data layouts to create. As a result, they either do not provide any performance guarantee or are effective to only some limited scenarios. This paper contributes a fundamental study to the problem. It systematically analyzes the inherent complexity of the problem in various settings, and for the first time, proves that the problem is NP-complete. It then points out the limitations of existing techniques and reveals that in practice, the essence for designing an appropriate data reorganization algorithm can be reduced to a tradeoff among space, time, and complexity. Based on that insight, it develops two new data reorganization algorithms to overcome the limitations of previous methods. Experiments show that an assembly composed of the new algorithms and a previous algorithm can circumvent the inherent complexity in finding optimal data layouts, making it feasible to minimize non-coalesced memory accesses for a variety of irregular applications and settings that are beyond the reach of existing techniques.
Correct and efficient work-stealing for weak memory models
Authors: Lê Nhat Minh , Pop Antoniu , Cohen Albert , Zappa Nardelli Francesco
Published: August 2013

Chase and Lev's concurrent deque is a key data structure in shared-memory parallel programming and plays an essential role in work-stealing schedulers. We provide the first correctness proof of an optimized implementation of Chase and Lev's deque on top of the POWER and ARM architectures: these provide very relaxed memory models, which we exploit to improve performance but considerably complicate the reasoning. We also study an optimized x86 and a portable C11 implementation, conducting systematic experiments to evaluate the impact of memory barrier optimizations. Our results demonstrate the benefits of hand tuning the deque code when running on top of relaxed memory models.
Distributed merge trees
Authors: Morozov Dmitriy , Weber Gunther
Published: August 2013

Improved simulations and sensors are producing datasets whose increasing complexity exhausts our ability to visualize and comprehend them directly. To cope with this problem, we can detect and extract significant features in the data and use them as the basis for subsequent analysis. Topological methods are valuable in this context because they provide robust and general feature definitions.

As the growth of serial computational power has stalled, data analysis is becoming increasingly dependent on massively parallel machines. To satisfy the computational demand created by complex datasets, algorithms need to effectively utilize these computer architectures. The main strength of topological methods, their emphasis on global information, turns into an obstacle during parallelization.

We present two approaches to alleviate this problem. We develop a distributed representation of the merge tree that avoids computing the global tree on a single processor and lets us parallelize subsequent queries. To account for the increasing number of cores per processor, we develop a new data structure that lets us take advantage of multiple shared-memory cores to parallelize the work on a single node. Finally, we present experiments that illustrate the strengths of our approach as well as help identify future challenges.
Fast concurrent queues for x86 processors
Authors: Morrison Adam , Afek Yehuda
Published: August 2013

Conventional wisdom in designing concurrent data structures is to use the most powerful synchronization primitive, namely compare-and-swap (CAS), and to avoid contended hot spots. In building concurrent FIFO queues, this reasoning has led researchers to propose
combining-based
concurrent queues.

This paper takes a different approach, showing how to rely on fetch-and-add (F&A), a less powerful primitive that is available on x86 processors, to construct a
nonblocking (lock-free) linearizable concurrent FIFO queue
which, despite the F&A being a contended hot spot, outperforms combining-based implementations by 1.5x to 2.5x in all concurrency levels on an x86 server with four multicore processors, in both single-processor and multi-processor executions.
Ownership passing
Authors: Friedley Andrew , Hoefler Torsten , Bronevetsky Greg , Lumsdaine Andrew , Ma Ching-Chen
Published: August 2013

The number of cores in multi- and many-core high-performance processors is steadily increasing. MPI, the de-facto standard for programming high-performance computing systems offers a distributed memory programming model. MPI's semantics force a copy from one process' send buffer to another process' receive buffer. This makes it difficult to achieve the same performance on modern hardware than shared memory programs which are arguably harder to maintain and debug. We propose generalizing MPI's communication model to include ownership passing, which make it possible to fully leverage the shared memory hardware of multi- and many-core CPUs to stream communicated data concurrently with the receiver's computations on it. The benefits and simplicity of message passing are retained by extending MPI with calls to send (pass) ownership of memory regions, instead of their contents, between processes. Ownership passing is achieved with a hybrid MPI implementation that runs MPI processes as threads and is mostly transparent to the user. We propose an API and a static analysis technique to transform legacy MPI codes automatically and transparently to the programmer, demonstrating that this scheme is easy to use in practice. Using the ownership passing technique, we see up to 51% communication speedups over a standard message passing implementation on state-of-the art multicore systems. Our analysis and interface will lay the groundwork for future development of MPI-aware optimizing compilers and multi-core specific optimizations, which will be key for success in current and next-generation computing platforms.
Parallel schedule synthesis for attribute grammars
Authors: Meyerovich Leo A. , Torok Matthew E. , Atkinson Eric , Bodik Rastislav
Published: August 2013

We examine how to synthesize a parallel schedule of structured traversals over trees. In our system, programs are declaratively specified as attribute grammars. Our synthesizer automatically, correctly, and quickly schedules the attribute grammar as a composition of parallel tree traversals. Our downstream compiler optimizes for GPUs and multicore CPUs.

We provide support for designing efficient schedules. First, we introduce a declarative language of schedules where programmers may constrain any part of the schedule and the synthesizer will
complete
and
autotune
the rest. Furthermore, the synthesizer answers debugging queries about how schedules may be completed.

We evaluate our approach with two case studies. First, we created the first parallel schedule for a large fragment of CSS and report a 3X multicore speedup. Second, we created an interactive GPU-accelerated animation of over 100,000 nodes.
The tasks with effects model for safe concurrency
Authors: Heumann Stephen T. , Adve Vikram S. , Wang Shengjie
Published: August 2013

Today's widely-used concurrent programming models either provide weak safety guarantees, making it easy to write code with subtle errors, or are limited in the class of programs that they can express. We propose a new concurrent programming model based on
tasks with effects
that offers strong safety guarantees while still providing the flexibility needed to support the many ways that concurrency is used in complex applications. The core unit of work in our model is a dynamically-created task. The model's key feature is that each task has programmer-specified
effects
, and a run-time scheduler is used to ensure that two tasks are run concurrently only if they have non-interfering effects. Through the combination of statically verifying the declared effects of tasks and using an effect-aware run-time scheduler, our model is able to guarantee strong safety properties, including data race freedom and atomicity. It is also possible to use our model to write programs and computations that can be statically proven to behave deterministically. We describe the tasks with effects programming model and provide a formal dynamic semantics for it. We also describe our implementation of this model in an extended version of Java and evaluate its use in several programs exhibiting various patterns of concurrency.
Exploring different automata representations for efficient regular expression matching on GPUs
Authors: Yu Xiaodong , Becchi Michela
Published: August 2013

Regular expression matching is a central task in several networking (and search) applications and has been accelerated on a variety of parallel architectures. All solutions are based on finite automata (either in deterministic or non-deterministic form), and mostly focus on effective memory representations for such automata. Recently, a handful of work has proposed efficient regular expression matching designs for GPUs; however, most of them aim at achieving good performance on small datasets. Nowadays, practical solutions must support the increased size and complexity of real world datasets. In this work, we explore the deployment and optimization of different GPU designs of regular expression matching engines, focusing on large datasets containing a large number of complex patterns.
Parallel programming with big operators
Authors: Park Changhee , Steele Guy L. , Tristan Jean-Baptiste
Published: August 2013

In the sciences, it is common to use the so-called "big operator" notation to express the iteration of a binary operator (the reducer) over a collection of values. Such a notation typically assumes that the reducer is associative and abstracts the iteration process. Consequently, from a programming point-of-view, we can organize the reducer operations to minimize the depth of the overall reduction, allowing a potentially parallel evaluation of a big operator expression. We believe that the big operator notation is indeed an effective construct to express parallel computations in the Generate/Map/Reduce programming model, and our goal is to introduce it in programming languages to support parallel programming. The effective definition of such a big operator expression requires a simple way to generate elements, and a simple way to declare algebraic properties of the reducer (such as its identity, or its commutativity). In this poster, we want to present an extension of Scala with support for big operator expressions. We show how big operator expressions are defined and how the API is organized to support the simple definition of reducers with their algebraic properties.