Flash Lamp Annealed LTPS TFTs with ITO Bottom-Gate Structures
Authors: Packard Glenn , Rosenfeld Adam , Manley Robert G. , Hirschman Karl D. 
Published: December 2020

Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistors (TFTs) are usually built as a top-gate structure. This is due to the serious challenge presented by locally crystallizing a thin layer of amorphous silicon that has regions of overlap with an absorptive and thermally conductive gate electrode and areas of thermally insulating glass. Early attempts to create LTPS devices quickly switched from the industry standard of bottom-gate to the more attainable top-gate, in which a gate structure is deposited subsequent to crystallization [1]. Despite this difficulty, bottom-gate devices offer potential benefits in breakdown voltage and dielectric-semiconductor interface quality, as well as being a requirement for double-gate devices and enabling higher fill-factor pixel designs in TFT display backplanes. Bottom-gate TFTs have been realized with crystallization via excimer laser annealing (ELA) with a demonstrated improvement over top-gate devices [2]. This is of particular interest for the development of LTPS devices that employ an alternative crystallization technique, such as metal-induced lateral crystallization [3, 4] and continuous-wave laser annealing [5, 6], motivated by potential advantages in large-panel manufacturing.

FLA (Flash lamp annealing) has been explored as an alternative to ELA LTPS [7], and has the potential to streamline and decrease the cost of fabrication while providing applicable electrical performance. In this method, amorphous silicon is exposed to a single pulse of light emitted from a xenon flash lamp, causing melting and recrystallization in an area of cm2 rather than nm2 in less than a millisecond. FLA has shown value in crystallizing silicon and activating dopants in both PFET and NFET TFTs [8]. Early attempts to produce bottom-gate FLA-LTPS TFTs were ineffective; the high degree of light absorption and reflectivity in metal or polysilicon gates resulted in severe, localized ablation of the overlying channel silicon. Reducing FLA emission intensity prevented this catastrophic channel loss, but also reduced the crystallization of source/drain region silicon to the point where device performance was dominated by series resistance.

In this work, bottom-gate LTPS TFTs are realized using FLA by incorporating indium-tin oxide (ITO) as a transparent conductive gate electrode material. The reduction in absorbance and reflectivity, as well as the enhanced thermal and chemical stability, of ITO allows for the simultaneous, comparable crystallization of both channel silicon above the gate and adjacent source/drain silicon regions above SiO2 and glass substrate. A finalized ITO bottom-gate PFET is shown in Figure 1A and an in-progress image after FLA and ion implantation in 1B. A distinction is visible between silicon over the gate and freestanding silicon, with an even sharper distinction between implanted source-drain silicon over the gate and the true, non-implanted channel. It is clear that the presence of an ITO gate locally enhances silicon crystallization with a slight lateral bleed, but this effect does not dominate to the point of damaging the channel. A subsequent 630 °C furnace treatment provides for both dopant activation and recrystallization of amorphized regions.

P-channel TFTs fabricated with ITO bottom gates demonstrated excellent device performance, as shown in Figures 1C and 1D. The ION/IOFF
ratio is between 6 and 7 orders of magnitude with notably low off-state leakage. The typical device shown exhibits a threshold voltage VT
~ -5.0 V. The channel mobility was extracted using the maximum transconductance method, indicating a hole µch
~ 190 cm2/Vs. Most transfer characteristics experienced significant degradation at higher drain bias conditions for reasons still under investigation. Nevertheless, these preliminary results provide direction for further investigation, which include the study of a double-gate structure for comparisons in device performance and stability. The additional presence of a top gate will improve electrostatic control of the channel charge, mitigating problems caused by interface trap states with an effect similar to enhanced channel passivation. Further passivation efforts using hydrogen/nitrogen plasma treatments will be incorporated in tandem; these are more effective on bottom and double-gate structures due to easier channel access at the processing back-end. In addition, FLA is being explored as a replacement for the long furnace anneal currently used for dopant activation.

Figure 1