bluuebunny/crossref_metadata_2025 huggingface dataset:
Dynamically managing the communication-parallelism trade-off in future clustered processors
Authors: Balasubramonian Rajeev , Dwarkadas Sandhya , Albonesi David H.
Published: July 2004

Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, thereby allowing more aggressive use of instruction-level parallelism (ILP), the inter-cluster communication increases as data values get spread across a wider area. As a result of the emergence of this trade-off between communication and parallelism, a subset of the total on-chip clusters is optimal for performance. To match the hardware to the application's needs, we use a robust algorithm to dynamically tune the clustered architecture. The algorithm, which is based on program metrics gathered at periodic intervals, achieves an 11% performance improvement on average over the best statically defined architecture. We also show that the use of additional hardware and reconfiguration at basic block boundaries can achieve average improvements of 15%. Our results demonstrate that reconfiguration provides an effective solution to the communication and parallelism trade-off inherent in the communication-bound processors of the future.
Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history
Authors: Thomas Renju , Franklin Manoj , Wilkerson Chris , Stark Jared
Published: July 2004

Deep pipelines and fast clock rates are necessitating the development of high accuracy, multi-stage branch predictors for future processors. Such a predictor uses a collection of predictors, each of which provides its predictions at a different stage of the pipeline front-end. A simple 1-cycle latency line predictor provides predictions in the first stage, followed in a couple of stages later by predictions from a more accurate global predictor. Finally, one or two stages later, a highly accurate corrector predictor selectively corrects the global predictor's prediction. As the corrector predictor has the final say, its accuracy must be very high. The focus of this paper is to propose and evaluate techniques to build high-accuracy corrector predictors.Our techniques rely on using a long global history, and identifying correlated branches in this history by using runtime dataflow information. In particular, we identify for each dynamic branch a set of branches called "affectors", which control the computation that affect that branch's outcome. We propose efficient hardware structures to track dataflow and to identify the affector branches for each dynamic branch; the hardware overhead for identifying affectors for all dynamic branches from a 64 branch global history is only 312 bytes. We then propose two prediction schemes that put to use the affector branch information. Experimental studies show that adding an 8KB corrector predictor (that uses affector information) to a 16KB perceptron predictor (total size 24.2KB) reduces the average misprediction rate for 12 benchmarks from 6.3% to 5.7%, an improvement achieved only by a 64KB perceptron predictor.
Virtual simple architecture (VISA)
Authors: Anantaraman Aravindh , Seth Kiran , Patil Kaustubh , Rotenberg Eric , Mueller Frank
Published: July 2004

Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis tools can safely and tightly bound execution time on in-order single-issue pipelines with caches and static branch prediction. However, this simple pipeline appears to be a complexity limit, due to the need for analyzability. This excludes a whole class of high-performance processors from many embedded systems.We reconcile the complexity/safety trade-off by decoupling worst-case timing analysis from the processor implementation, through a virtual simple architecture (VISA). A VISA is the timing specification of a hypothetical simple pipeline and is the basis for worst-case timing analysis. However, the underlying microarchitecture can be arbitrarily complex. A task is divided into multiple sub-tasks which provide a means to gauge progress on the complex pipeline. Each sub-task is assigned an interim deadline, or checkpoint, based on the latest allowable completion time of the sub-task on the hypothetical simple pipeline. If no checkpoints are missed, then the complex pipeline is as timely as the safe pipeline. If a checkpoint is missed, the pipeline switches to a simple mode of operation that directly implements the VISA so that execution time of unfinished sub-tasks is safely bounded. The significance of our approach is that we circumvent worst-case timing analysis of the complex pipeline, by dynamically confirming its behavior is bounded by worst-case timing analysis of a simpler proxy pipeline.The benefit of using a high-performance processor is that tasks finish much sooner than they would have on an explicitly-safe processor. The new slack in the schedule can be exploited for higher throughput or lower power. With the VISA approach, an arbitrarily complex SMT processor can safely run non-real-time tasks at the same time as a real-time task. Alternatively, frequency/voltage can be safely lowered to take up slack. We explore the latter application and show a VISA-compliant complex pipeline consumes 43--61% less power than an explicitly-safe pipeline.
DISE
Authors: Corliss Marc L. , Lewis E. Christopher , Roth Amir
Published: July 2004

Dynamic Instruction Stream Editing (DISE)
is a cooperative software-hardware scheme for efficiently adding customization functionality---e.g, safety/security checking, profiling, dynamic code decompression, and dynamic optimization---to an application. In DISE, application customization functions (ACFs) are formulated as rules for macro-expanding certain instructions into parameterized instruction sequences. The processor executes the rules on the fetched instructions, feeding the execution engine an instruction stream that contains ACF code. Dynamic instruction macro-expansion is widely used in many of today's processors to convert a complex ISA to an easier-to-execute, finer-grained internal form. DISE co-opts this technology and adds a programming interface to it.DISE unifies the implementation of a large class of ACFs that would otherwise require either special-purpose hardware widgets or static binary rewriting. We show DISE implementations of two ACFs---memory fault isolation and dynamic code decompression---and their composition. Simulation shows that DISE ACFs have better performance than their software counterparts, and more flexibility (which sometimes translates into performance) than hardware implementations.
Overcoming the limitations of conventional vector processors
Authors: Kozyrakis Christos , Patterson David
Published: July 2004

Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of the centralized vector register file limits the number of functional units. Second, precise exceptions for vector instructions are difficult to implement. Third, vector processors require an expensive on-chip memory system that supports high bandwidth at low access latency.This paper introduces CODE, a scalable vector microarchitecture that addresses these three shortcomings. It is designed around a clustered vector register file and uses a separate network for operand transfers across functional units. With extensive use of decoupling, it can hide the latency of communication across functional units and provides 26% performance improvement over a centralized organization. CODE scales efficiently to 8 functional units without requiring wide instruction issue capabilities. A renaming table makes the clustered register file transparent at the instruction set level. Renaming also enables precise exceptions for vector instructions at a performance loss of less than 5%. Finally, decoupling allows CODE to tolerate large increases in memory latency at sub-linear performance degradation without using on-chip caches. Thus, CODE can use economical, off-chip, memory systems.
DSP architectures
Authors: Tan Edwin J. , Heinzelman Wendi B.
Published: July 2004

As far as the future of communication is concerned, we have seen that there is great demand for audio and video data to complement text. Digital signal processing (DSP) is the science that enables traditionally analog audio and video signals to be processed digitally for transmission, storage, reproduction and manipulation. In this paper, we will explain the various DSP architectures and its silicon implementation. We will also discuss the state-of-the art and examine the issues pertaining to performance.
Hardware Resources: a generalizing view on computer architectures
Authors: Matthes Wolfgang
Published: July 2004

Computer hardware is seen as a collection of resources. Performance, functional capabilities, and quantity of these resources are decisive to overall system performance.Starting from this paradigm, computer architecture design may be handled systematically in the future even by formalized methods.
Combinatorial power in multimedia processors
Authors: Thorup Mikkel
Published: July 2004

We point out the significance of a few multimedia instructions in fundamental combinatorial problems such as hashing, sorting, minimum spanning tree and single source shortest paths. The hope is convince the processor design community to give these instructions a more central role so that they will be supported consistently as a standard in future multimedia processors. At the same time, we provide a simple model of multimedia processors for the algorithms community, highlighting the aspects of relevance in combinatorial algorithms.
Support of Java API for the jHISC system
Authors: Hau Gary K. W. , Fong Anthony , Lun Mok Pak
Published: July 2004

This paper presents the evolution and improvement of the Java API (Application Programming Interface) for Java which used in jHISC Runtime Environment. The jHISC Running Environment is an object-based, single addressing execution environment, specially designed for running object-oriented programming languages such as Java. The jHISC core is a HISC-architecture processor created for executing Java programs. The jHISC API is designed for object-oriented systems to support object model inside jHISC. The jHISC API includes elemental objects such as jhisc.Object, jhisc.Integer and few redesigned objects such as jhisc.util.Vector, jhisc.util.Hashtable. The jHISC API is developed in order to take advantage of using jHISC core and provides a hardware support delegate function in the system.
Hardware/software cooperation in the iAPX-432
Authors: Rattner Justin
Published: July 2004

The Intel iAPX-432 is an object-based microcomputer system with a unified approach to the design and use of its architecture, operating system, and primary programming language. The concrete architecture of the 432 incorporates hardware support for data abstraction, small protection domains, and language-oriented run-time environments. It also uses its object-orientation to provide hardware support for dynamic heap storage management, interprocess communication, and processor dispatching.

We begin with an overview of the 432 architecture so readers unfamiliar with its basic concepts will be able to follow the succeeding discussion without the need to consult the references. Following that, we introduce the various forms of hardware/software cooperation and the criteria by which a function or service is selected for migration. This is followed by several of the more interesting examples of hardware/software cooperation in the 432. A comparison of cooperation in the 432 with several contemporary machines and discussions of development issues, past and future, complete the paper.
Hardware/software tradeoffs for increased performance
Authors: Hennessy John , Jouppi Norman , Baskett Forest , Gross Thomas , Gill John
Published: July 2004

Most new computer architectures are concerned with maximizing performance by providing suitable instruction sets for compiled code and providing support for systems functions. We argue that the most effective design methodology must make simultaneous tradeoffs across all three areas: hardware, software support, and systems support. Recent trends lean towards extensive hardware support for both the compiler and operating systems software. However, consideration of all possible design tradeoffs may often lead to less hardware support. Several examples of this approach are presented, including: omission of condition codes, word-addressed machines, and imposing pipeline interlocks in software. The specifics and performance of these approaches are examined with respect to the MIPS processor.
An overview of the mesa processor architecture
Authors: Johnsson Richard K. , Wick John D.
Published: July 2004

This paper provides an overview of the architecture of the Mesa processor, an architecture which was designed to support the Mesa programming system [4]. Mesa is a high level systems programming language and associated tools designed to support the development of large information processing applications (on the order of one million source lines). Since the start of development in 1971, the processor architecture, the programming language, and the operating system have been designed as a unit, so that proper tradeoffs among these components could be made.
The operating system and language support features of the BELLMAC
TM
-32 microprocessor.
Authors: Berenbaum Alan D. , Condry Michael W. , Lu Priscilla M.
Published: July 2004

The BELLMAC-32 microprocessor is a 32-bit microprocessor, implemented with CMOS technology, designed to support operating system functions and high level languages efficiently. The architecture was designed with the following objectives in mind:

• High performance.

• Enhanced operating system support capabilities.

• High level language support.

• High reliability, availability and maintainability.
Register allocation for free
Authors: Ditzel David R. , McLellan H. R.
Published: July 2004

The Bell Labs C Machine project is investigating computer architectures to support the C programming language.
1
One of the goals is to match an efficient architecture to the language and the compiler technology available. Measurements of different C programs show that roughly one out of every twenty instructions executed is either a procedure call or return.
2
Procedure call overhead is therefore a very important consideration in the overall machine design. A second and related area of primary concern in overall machine efficiency is the register allocation strategy. While use of additional registers can offer considerable improvement in execution times, adding registers usually has the adverse effects of increasing the procedure call overhead due to register saving and creating an undue burden on the compiler. In this paper we describe a piece of the C Machine architecture which effectively eliminates the register allocation problem, and improves procedure calling by drastically reducing storage references required by traditional register saving. The technique can be generalized for other languages and architectures, though we will only directly address those issues involving the C language.
An architectural alternative to optimizing compilers
Authors: Harbison Samuel P.
Published: July 2004

Programming languages are designed to make
programming
productive. Computer architectures are designed to make
program execution
efficient. Although architectures should be designed with programming languages in mind, it may be as inappropriate to make the computer execute the programming language directly it is to make the programmer use machine language. It is the compiler's job to match the programming language and the computer architectures, and therefore making compiler's efficient and easy to write are important design goals of a complete hardware/software system. This paper summerizes research completed in 1980 [5] on a computer architecture,
TM
, that takes over some of the more burdensome tasks of optimizing compilers for high-level-languages (HLL's), performing these tasks dynamically during the execution of the object program. This is a different approach to making compilers efficient than is commonly taken; more common approaches include devising more efficient optimization algorithms[I], being clever about when to do optimizations [4], and building the compilers semiautomatically [6].
Systematic protection mechanism design
Authors: Jones Douglas W.
Published: July 2004

This work describes an attempt to systematically design a hardware resource protection mechanism when given the requirements of a particular language as a target. The design process is formalized as a structured walk through the multidimensional computer design space towards a hypothetical class of optimal machines. Each step in this walk involves a change in the distribution of work between the compiler and run-time system but no change in the source language semantics. The starting point for this walk is the result of a semantic analysis of the language to be implemented; typically, this produces a very high level machine where the compiler, if any, is trivial. The walk ends when no changes result in a net improvement. This does not guarantee that the result is even locally optimal, since the changes tried depend on the ingenuity and persistence of the designer.

This design approach has been used to arrive at a practical, general purpose protection mechanism oriented towards the needs of the Ada language (preliminary version). This architecture was evaluated by comparing it with the PDP-11/45. For the purpose of this comparison, the protection mechanism was incorporated into a partially specified PDP-11 like instruction set. The number of bits making up the processor state and the number of operations involved in address computation were evaluated. On this basis, the result appears to be competitive and worth further investigation.
On a general property of memory mapping tables
Authors: Reed Karl
Published: July 2004

The paper shows that memory mapping tables can be used to implement the display registers used in providing architectural support for block-structured languages such as Algol 60. This allows full lexical level addressing to be implemented on so-called von-Neuman machines.

The problems of fragmentation of the paged address space are explored, and machines with memory mapping schemes capable of supporting the proposals identified.

Attention is drawn to the similarity between segmented and paged schemes, and it is suggested that the latter may be used to support the former.
Compiler chip
Authors: Fusaoka Akira , Hirayama Masaharu
Published: July 2004

In this paper we discuss about another approch:
Compiler Chip
, which is a VLSI implementation of a compiler. Constructing a compiler by a few VLSI chip, the computer manufacturer can deliver compilers by sets of VLSI chips, and these chips are installed in a intelligent terminal in order to remove the compilation from the tasks which are processed in the mainframe.
Architectural support for the efficient generation of code for horizontal architectures
Authors: Rau B. R. , Glaeser C. D. , Greenawalt E. M.
Published: July 2004

Horizontal architectures, such as the CDC Advanced Flexible Processor [I] and the FPS APi20-B [2}, consist of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. Such architectures have been developed to perform high speed scientific computations at a modest cost: Figure 1 displays those characteristics of horizontal architectures that are germane to the issues discussed in this paper. The simultaneous requirements of high performance and low cost lead to an architecture consisting of multiple pipelined processing elements (PEs) such as adders and multipliers, a memory (which for scheduling purposes may be viewed as yet another PE with two operations: a READ and a WRITE), and an interconnect which ties them all together. The interconnect allows the result of one operation to be directly routed to another PE as one of the inputs for an operation that is to be performed there. The required memory bandwidth is reduced since temporary values need not be written to and read from the memory. The final aspect of horizontal processors that is of interest is that their program memories emit wide instructions which synchronously specify the actions of the multiple and possibly dissimilar PEs. The program memory is sequenced by a conventional sequencer that assumes sequential flow of control unless a branch is explicitly specified.

As a consequence of the simplicity of such an architecture, it is inexpensive relative to the potential performance of the multiple pipelined PEs. However, if this potential performance is to be realized, the multiple resources of a horizontal processor must be scheduled effectively. The scheduling task for conventional horizontal processors is quite complex and the construction of highly optimizing compilers for them is a difficult and expensiw3 project. The polycyclic architecture [3- 6] is a horizontal architecture with architectural support for the scheduling task. The cause of the complexity involved in scheduling conventional horizontal processors and the manner in which the polycyclic architecture addresses this issue are outlined in this paper.
Guidelines for creating a debuggable processor
Authors: McLear R. E. , Scheibelhut D. M. , Tammaru E.
Published: July 2004

Hardware without software is of little use. Systems that ease the task of debugging software reduce cost and speed development. This paper presents guidelines for designing processors that ease debugging for real-time computer systems. Special hardware can aid the debugging process by tracing execution and accesses to memory. Such hardware requires access to signals that may not be readily available. Other, less exotic hardware provides an interface to the programmer and other processors. The hardware and software of the debugging system should not alter the real-time characteristics of the system under test and should be able to operate on a field-grade processor. It is undesirable to require special versions of processor hardware and software for the debugging system.
Hardware support for memory protection
Authors: Wilkes M. V.
Published: July 2004

This paper is intended to stimulate discussion on the present state of hardware supported capability systems. Interest in such systems grew up in the mid-1960's and since that time information has been published on several different versions. In the opinion of some observers, the software complexity of these systems outweighs the advantage gained. The paper surveys the situation, and endeavors to set out the general features that a hardware supported capability system should possess. An attempt is made to identify the causes of the complexity and to make recommendations for removing them. The arguments for and against the tagging of capabilities are discussed and attention is drawn to a system of semi-tagging previously proposed by the author.
Supporting ada memory management in the iAPX-432
Authors: Pollack Fred J. , Cox George W. , Hammerstrom Dan W. , Kahn Kevin C. , Lai Konrad K. , Rattner Justin R.
Published: July 2004

In this paper, we describe how the memory management mechanisms of the Intel iAPX-432 are used to implement the visibility rules of Ada. At any point in the execution of an Ada® program on the 432, the program has a protected address space that corresponds exactly to the program's accessibility at the corresponding point in the program's source. This close match of architecture and language did not occur because the 432 was designed to execute Ada—it was not. Rather, both Ada and the 432 are the result of very similar design goals.

To illustrate this point, we compare, in their support for Ada, the memory management mechanisms of the 432 to those of traditional computers. The most notable differences occur in heap-space management and multitasking. With respect to the former, we describe a degree of hardware/software cooperation that is not typical of other systems. In the latter area, we show how Ada's view of sharing is the same as the 432, but differs totally from the sharing permitted by traditional systems. A description of these differences provide some insight into the problems of implementing an Ada compiler for a traditional architecture.
Some requirements for architectural support of software debugging
Authors: Johnson Mark Scott
Published: July 2004

Architectural support of high-level, symbolic debugging is described at three levels of abstraction: the user's view of desired debugging functionality, the debugger implementor's view of architectural requirements that support the functionality, and the computer architect's view of architectural features or attributes that implement the requirements. References are made where possible to computing systems that meet the requirements. The paper is written from the viewpoint of debugger implementors, and is addressed primarily to computer architects.
The effect of the PDP-11 architecture on code generation for chill
Authors: Middelburg C. A.
Published: July 2004

This paper outlines the implementation of the CCITT*) high level programming language CHILL on PDP-11 computers in the CHILL compiler constructed at the Dr. Neher Laboratories. The characteristics and structure of the compiler are briefly described. The relationship between the PDP-11 architecture and the implementation of CHILL is outlined in more detail.
A case study of VAX-11 instruction set usage for compiler execution
Authors: Wiecek Cheryl A.
Published: July 2004

Analysis of an instruction set as large and varied as the one specified for the VAX-11 architecture is important for aiding processor design evaluation. This paper looks at dynamic VAX-11 instruction set usage by one class of programs, and discusses the methodology and tools which have been developed to provide that information. Six VAX/VMS native mode compilers from Digital Equipment Corporation were used: BASIC, BLISS, COBOL, FORTRAN, PASCAL, and PL/I. A summary of results generated by analyzing executions of these six compilers is presented. Information is included for instruction and class frequency, general instruction features, operand specifiers, the memory data stream, register utilization, instruction sequencing, and branch displacements.
Firmware structure and architectural support for monitors, vertical migration and user microprogramming
Authors: Maekawa Mamoru , Sakamura Ken , Ishikawa Chiaki
Published: July 2004

This paper describes firmware and hardware support necessary for constructing easy-to-understand and high performance operating systems including language translators and interpreters. Basic principles are one-to-one correspondence between logical hierarchy and physical hierarchy, and vertical migration. Implementation of monitors in firmware and architectural support for it are discussed, and a sample system is shown. Architectural support for user microprogramming is then discussed and an example is shown. After a total system firmware structure is discussed, an experiment of vertical migration is described. It is shown that a proper selection of modules for migration is extremely important. It is suggested that the direction shown in this paper is one of future directions of computer systems.
A multi-microprocessor architecture with hardware support for communication and scheduling
Authors: Ahuja Sudhir R. , Asthana Abhaya
Published: July 2004

We describe a multiprocessor system that attempts to enhance the system performance by incorporating into its architecture a number of key operating system concepts. In particular:

— the scheduling and synchronization of concurrent activities are built in at the hardware level,

— the interprocess communication functions are performed in hardware, and,

— a coupling between the scheduling and communication functions is provided which allows efficient implementation of parallel systems that is precluded when the scheduling and communication functions are realized in software.
Associative/parallel processors for searching very large textual data bases
Authors: Bird R. M. , Tu J. C. , Worthy R. M.
Published: July 2004

This paper describes an approach to solving a major problem in the information processing sciences— that of searching very large (5-50 billion characters) data bases of unstructured free-text for random queries within a reasonable time and at an affordable price.

The need by information specialists and knowledge workers for large, fast low-cost text and document retrieval systems is growing rapidly. Conventional approaches to the problem have usually depended upon expensive, general purpose computers, upon special pre-preprocessing of the textual data (e.g. file inverting, indexing, abstracting, etc.), and upon elaborate, costly software. The resulting retrieval systems often cost hundreds of dollars per query and the full scanning of an uninverted, unstructured billion byte textual data base could take hours of computer services. However, in spite of these restrictions, such full text search systems have proved useful and even indispensible for many applications.

Computer technology of the late 1960's and the 1970's, in both hardware and software (e.g., minicomputers, low-cost, high density disk storage, “chip” electronics, natural language query systems, etc.), have made i t practical to build special purpose, low-cost text retrieval systems. Such a system has been built, tested, and is now in a production stage. The system called the Associative File Processor (AFP), utilizes a conventional minicomputer (DEC's PDP-11/45) for control, off-the-shelf high density disks for storage, a special purpose parallel search module as a text term detector, and query and retrieval software. The AFP is currently being field tested at two sites. Full text, parallel searches on un-preprocessed textual data bases are being performed at the effective matching rates of 4 billion bytes per second (8K byte key memory times 500 Kbyte/second data stream). Estimated costs are 10 to 25 cents per query for a one billion byte data base. The costs per query and the time for searching increase in a linear fashion as data base increases. A basic architecture for the AFP is described and an implemented version is discussed. A more powerful term detector module is also under development. This system is designed around a finite state automaton algorithm.
On imaginary fields, token transfers and floating codes in intelligent secondary memories
Authors: Lipovski G. J.
Published: July 2004

In analyzing two implemented intelligent secondary memories, CASSM and RAP, we recognize a common mechanism which is here called an imaginary field. The mechanism can be generalized to suggest further design possibilities. It further explains the complex and controversial CASSM mechanism, “pointer transfer” in terms of separate but related principles—imaginary fields, token transfers, and floating codes—such that further designs can utilize some or all of the techniques.
Microprocessors for non-numeric processing
Authors: Zaky S. G.
Published: July 2004

The problem of processing of non-numeric data has received considerable attention in the last few years. This is primarily motivate by the pressing needs in the are a of data base management. It has long been recognized that the parallel processing capabilities of an associative processor are fundamentally well suited to this environment. However, the complexity and cost of truely associative memories make this approach impractical. In this paper, the demands that non-numeric processing place on memory and processor hardware are discussed. Some emerging trends are presented, and a suggestion is given regarding the development of a “general purpose” microprocessor that is suited to this environment.

Basically, the microprocessor discussed here is capable of performing simple search and update functions on a high speed, serial data stream. Therefore, it is suited to any application where such a situation is encountered, such as in digital communications.
The architecture of a database computer - a summary
Authors: Hsiao David K. , Kannan Krishnamurthi
Published: July 2004

The motivation for seeking hardware solutions to database management functions traditionally carried out by software has been apparent to data-base designers for sometime now. Firstly, database management software has grown in complexity and size over the years. This growth is prompted by the increase in user requirements, by the formulation of sophisticated models and by the change in data processing mode from an off-line, batched, single user environment to an on-line, concurrent and multi-user environment. Large and complex software systems tend to be failure-prone. Further-more, practical verification methods for software systems are still not in sight. On the other hand, methods for verifying hardware functionality, design and production have long been available. Advanced technology has also overcome some of the problems of the logic complexity and capacity requirements, making the construction of relatively large and complex computers viable. By incorporating basic database management functions into hardware, not only can we provide more reliable basic functions, but we can also improve the software reliability since the software requirements will be less complex and the system software will be smaller in size.
Trends in non-software support for input-output functions
Authors: McDonell Ken J.
Published: July 2004

Input-output subsystem architectures have evolved over the past 20-odd years to the point where two divergent approaches have found acceptance in current computer systems; the 'IBM channel' is the archetype of the lower level alternative, while the functionally more complex techniques involve a wide spectrum of distributed processor architectures supporting database and/or storage management functions independently with respect to the central processor. The paper traces the historical development of support (outside central processor based software) for input-output functions and concludes with a preliminary comparison of the relative merits of the software interfaces provided by the alternative input-output subsystem architectures.
Ulisse
Authors: Cerretti R. , Jasilli D. , Matteucci D. R.
Published: July 2004

The paper describes a project conducted in collaboration between CNUCE, an Institute of the Italian National Research Council, and a private research center, concerning a multifunctional system (Ulisse) capable of operating both as a stand alone unit for office administration and automation (word processsing, file management and retrieval) and as an intelligent terminal with local facilities for text editing, text formatting and storage.

The first results of the application of Ulisse in the environment of the scientific users of CNUCE are illustrated.
Data management requirements
Authors: Bray Olin H.
Published: July 2004

Memory management, database management, and message processing have in the past been defined in a relatively narrow way. With memory management the problem was to obtain cost effective use of real memory. Given a multiprogrammed environment, virtual memory systems allowed more effective use of expensive real memory. Memory management has become even more important with the development of very large and complex memory hierarchies. Database management systems were developed to allow the more effective use, sharing, and control of data resources - objectives which operating systems had previously provided for hardware resources. The driving force behind message processing has been the increased use of data communications and computer networks. This paper will consider the basis of the overlap in these areas, their common data management functions. Data management, as defined in this paper, includes the locating, routing, moving, and translating of data resources and the locating, reserving, and releasing of physical resources, i.e., primary and secondary storage.

The analysis performed in this paper is essential because of trends in computer architecture discussed below. Early hardware was designed for general purpose environments with software used to tailor it to specific applications. However, according to Gagliardi
9
future systems will consist of a set of subsystems, including a storage subsystem at the core surrounded by computational, spooling, and communications subsystems. The computational subsystem is the traditional “number cruncher” part of the system. The spooling subsystem provides the I/O interface between the system and the outside world. The communications subsystem links the various subsystems together and provides an interface to the rest of the network if the system is part of a larger distributed system. The storage subsystem consists of all the system's storage resources and their control processes. It controls all levels of the system memory and storage hierarchy. The storage subsystem controls the allocation of the physical storage resources and the movement of the data resources through the system. Depending on how these resources are used, they may be non-conserved or conserved, and if conserved, either serially reusable or sharable. Physical and data resources may be located, and if necessary reserved, independently or jointly.
A comparison of sequential and associate computing of priority queues
Authors: Landson Barry M. , Sargent Robert G.
Published: July 2004

A comparison of priority queues on four different types of computer memories are made by ring a model to determine the total time to do comparable tasks. The four types of memories compared are random access (RAM), associate (AM), hybrid consisting of an associate memory and a random access memory (AM/RAM), and the hybrid memory with an auxiliary memory having the @@@@pability to perform Lewin's Associate algorithm @@@@], (AM/RAM/AML).

The model used for the comparisons is an extension of the MIX model developed by Knuth [1]. The MIX model was extended to include the four types of memories and the instruction set expanded include @@@@ instructions for the memories added. This @@del allows direct comparisons to be made of the different architectures and different software algorithms in performing the same tasks.
Test bench for software development of object-oriented processor
Authors: Yu Ryan W. S. , Hau Gary K. W. , Fong Anthony S.
Published: July 2004

HISC (High-level Instruction Set Computer) is proposed to provide hardware support for OOP. It applies the concept of object-orientation in the architecture and provides special instructions for object manipulation. An operating system is under developing for HISC. It divided into several modules by using the object-oriented paradigm. It includes some special modules for object-manipulation such as object management and garbage collection which traditional operating system do not support.In order to do the functional verification of each module, a test bench is needed. Its aims are to ease the effort to written the testing program and to simulate the working environment. It can make it easier to evaluate if an algorithm is suitable for HISC or not. In this paper, we discuss the design of the test bench. The architecture of the system will be described, together with the implementation of the modules and the pluggable modules architecture.
Object-oriented processor requirements with instruction analysis of Java programs
Authors: Lun Mok Pak , Fong Anthony , Hau Gary K. W.
Published: July 2004

Application development adopts the concept of Object-Oriented Programming (OOP) in order to achieve better organization in module partitioning. OOP have three tenets, which are encapsulation, inheritance, and polymorphism. These tenets in OOP offer the program with enhanced security, organized partitioning, data hiding and code sharing, etc. In OOP system, programs perform as objects in the system. An application can be defined into different classes, or object templates, where each class shares some responsibility of the application. In the current practice, OOP system is based on a non-OOP processor. This approach generates overhead on the mapping of OOP features to the non-OOP processor. Therefore, there is need of OOP processor for the OOP system.Java is one of the most popular OOP languages today. Its portability, sharing ability, security, and integration of Internet make it a great success in software development, especially on network computing. In this paper, we will investigate the instruction behavior of some Java programs and benchmarks. By doing the instruction analysis of java programs, we can specify what is needed in an OOP processor in order to provide a fully OOP system in both hardware and software.
String storage and searching for data base applications
Authors: Copeland George P.
Published: July 2004

User and hardware cost trends dictate that data base systems should provide more complete functionality, simplicity of use, and reliability by increasing the amount of hardware present in the system. These goals are accomplished with a simple hardware arrangement within a one-dimensional cellular storage system called INDY. The INDY backend kernel is intended as a powerful tool for implementing all data models. The INDY cellular storage array is intended to provide functionality that is difficult to implement efficiently using a conventional hardware arrangement. It allows a simple implementation of improved data independence at high speeds. INDY simultaneously satisfies the time windows of future hardware technologies and user requirements.The importance of strings as a mechanism for defining abstract data types for data base languages is discussed in more detail in another paper. In that paper, a language called STRING is introduced which allows names of data objects to be semantically defined as variable-length strings and compared based on string pattern membership. This paper is concerned with the implementation of string storage and searching required by the STRING language. Implementation of higher level structures and searching requirements (such as sets, rows, tables and hierarchies) on the INDY kernel is treated elsewhere.
Text file inversion
Authors: Bird R. M. , Newsbaum J. B. , Trefftzs J. L.
Published: July 2004

This paper compares inversion of text files with inversion of more structured records. The unique characteristics of textual data which restrict the utility of inversion are identified and discussed. Inversion is shown to be useful only for small, static data bases, and when full text search is not required.
Coordinating concurrent access in a distributed database architecture
Authors: Stucki M. J. , Cox J. R. , Roman G. C. , Turcu P. N.
Published: July 2004

A distributed architecture for an interactive information system is described, and a scheme for coordinating concurrent access to its data is presented. The scheme is deadlock free and is carried out without the need for centralized control. Conflicts are detected as they occur, and competing processes are given exclusive access to the data they need.
A hierarchical controller for concurrent accessing of distributed databases
Authors: Gouda Mohamed G.
Published: July 2004

An access controller for a distributed database is a (central or distributed) structure which routes access requests to the different components of the database. Such a controller is also supposed to resolve the conflicts between concurrent requests, if any, such that deadlock situations never arise.In this paper, some architectures for distributed access controllers of distributed databases are investigated. In particular, three controllers with hierarchical architectures are considered. The controllers are evaluated based on three criteria: (i) freedom of deadlocks, (ii) robustness, and (iii) parallelism. The third criterion implies that the added redundancy to increase the controller robustness against failure conditions should also contribute to the amount of achieved parallelism during the no-failure periods. We then define a controller architecture which satisfies all the three criteria.
An extensible architecture for data flow processing
Authors: Gavish Bezalel , Koch Harvey
Published: July 2004

In this research, we propose a general model for computer architectures. This model allows us to integrate some of the existing system architecture approaches for increasing computer capacity and indicates new possibilites for improving the cost/performance ratio of future computer systems. The model leads to the development of general purpose data flow machines and to different degrees of sophistication within these machines. Our fundamental approach is to separate the CPU into elementary components. This allows us to make a distinction between components for control and components for performing various processing functions, thus yielding a high degree of resource sharing.
Bubbles for relational database
Authors: Chang Hsu
Published: July 2004

The mechanical disk storage is limited by long initial delay, few inputs/outputs, and serial access, thus necessitating large complex programs in existing database systems in order to map the user's view into the physical storage and to provide different access paths in response to different queries. Bubble devices are capable of set-oriented processing and associative addressing architecture. This paper presents concepts on data structure, storage structure, and access methods for bubble implementation of relational database.
A distributed structure for the automization of the catalog of the national cultural heritage
Authors: Matteucci Dante R.
Published: July 2004

Efforts to automate the handling of information concerning the Catalog of the Italian cultural and artistic heritage have been made in the past by the Institute for the Catalog and Documentation (ICCD) of the Ministry of Cultural and Environmental Heritage.A feasibility study for the realization of a data base of the national cultural heritage has been conducted by CNUCE, the scientific computing center of the Italian National Research Council and ICCD. This study led to the determination of the caracteristics of data contained on the record cards, to the location of some samples areas, sufficiently representative of the Italian situation, for the setting up of a model of information system and to the implementation of a data bank on CNUCE computers using the IBM STAIRS information retrieval system.Following this study, a project is presently conducted by the two institutions, with the aim of setting up a distributed structure for the preparation, acquisition, access to and dissemination of the information concerning the Italian cultural and artistic heritage.This paper describes the functions of this proposed structure, with reference to the results of the first experiences and implementations.