bluuebunny/crossref_metadata_2025 huggingface dataset:
Detection of outliers with respect to a MUSIC geotechnical database
Authors: Ching Jianye , Phoon Kok-Kwang , Huang Pengsheng
Published: September 2023

This study proposes a novel method that addresses a nontraditional class of outlier detection problems. The purpose of most outlier detection methods in the literature is to detect outliers within a dataset. A record can be considered an outlier if it is distinct from the regular records in the dataset. However, the purpose of the novel outlier detection method proposed in this study is to detect outlier data groups (a data group may denote a site or a project) with respect to a soil/rock property "MUSIC" database. A data group is an outlier group if its characteristics (mean, variance, correlation, or higher order dependency) are distinct from the regular data groups in the database. This study frames the outlier detection problem into a formal hypothesis testing problems with the null hypothesis that “the target data group is identically distributed as the regular groups in the database.” With the hierarchical Bayesian model previously developed by the first two authors, the p-value for this hypothesis testing problem can be estimated rigorously. Numerical and real examples show that the p-value can effectively detect outlier data groups as well as outlier records with respect to a database.
Nesting-tree preferences of the black woodpecker—the biggest cavity excavator in a conifer-dominated forests in Poland
Authors: Zawadzki Grzegorz
Published: September 2023

The black woodpecker Dryocopus martius is an ecologically disproportionately important forest species owing to its abundance. Its large cavities provide breeding sites and shelter for many species—large birds, mammals, and social insects. I evaluated the nest tree preferences of black woodpeckers in the Augustów Forest, northeast Poland. Approximately 400 black woodpecker cavities were observed. The Scots pine, Pinus sylvestris, was the most commonly selected tree species, accounting for 90%. The cavity trees were 55–225 years old. All trees younger than 90 years were broadleaved tree species. The trees used to excavate the cavities had a larger diameter at the breast height (DBH) than the average of the stand. The trees selected by black woodpeckers were significantly shorter than the average height of the stands. Over 60% of the cavities were excavated 10–16 m above ground level. I found that the DBH and the first branch height were critical factors affecting the cavity entrance height. In pine-dominated forests, black woodpeckers preferred dead trees. Approximately 44% of new cavities were excavated from dead trees. Leaving dead or dying large trees in commercial forests benefits black woodpeckers and large secondary cavity nesters that depend on it and promotes biodiversity conservation. Birds excavate new cavities at a high rate yearly, in contrast with beech-dominated forests.
Hephaestus
: Codesigning and Automating 3D Image Registration on Reconfigurable Architectures
Authors: Sorrentino Giuseppe , Venere Marco , Conficconi Davide , D’Arnese Eleonora , Santambrogio Marco Domenico
Published: September 2023

Healthcare is a pivotal research field, and medical imaging is crucial in many applications. Therefore finding new architectural and algorithmic solutions would benefit highly repetitive image processing procedures. One of the most complex tasks in this sense is image registration, which finds the optimal geometric alignment among 3D image stacks and is widely employed in healthcare and robotics. Given the high computational demand of such a procedure, hardware accelerators are promising real-time and energy-efficient solutions, but they are complex to design and integrate within software pipelines. Therefore, this work presents an automation framework called
Hephaestus
that generates efficient 3D image registration pipelines combined with reconfigurable accelerators. Moreover, to alleviate the burden from the software, we codesign software-programmable accelerators that can adapt at run-time to the image volume dimensions.
Hephaestus
features a cross-platform abstraction layer that enables transparently high-performance and embedded systems deployment. However, given the computational complexity of 3D image registration, the embedded devices become a relevant and complex setting being constrained in memory; thus, they require further attention and tailoring of the accelerators and registration application to reach satisfactory results. Therefore, with
Hephaestus
, we also propose an approximation mechanism that enables such devices to perform the 3D image registration and even achieve, in some cases, the accuracy of the high-performance ones. Overall,
Hephaestus
demonstrates 1.85× of maximum speedup, 2.35× of efficiency improvement with respect to the State of the Art, a maximum speedup of 2.51× and 2.76× efficiency improvements against our software, while attaining state-of-the-art accuracy on 3D registrations.
Rectifying Skewed Kernel Page Reclamation in Mobile Devices for Improving User-Perceivable Latency
Authors: Chou Yi-Quan , Shen Lin-Wei , Chang Li-Pin
Published: September 2023

A crucial design factor for users of smart mobile devices is the latency of graphical interface interaction. Switching a background app to foreground is a frequent operation on mobile devices and the latency of this process is highly perceivable to users. Based on an Android smartphone, through analysis of memory reference generated during the app-switching process, we observe that file (virtual) pages and anonymous pages are both heavily involved. However, to our surprise, the amounts of the two types of pages in the main memory are highly imbalanced, and frequent I/O operations on file pages noticeably slows down the app-switching process. In this study, we advocate to improve the app-switching latency by rectifying the skewed kernel page reclaiming. Our approach involves two parts: proactive identification of unused anonymous pages and adaptive balance between file pages and anonymous pages. As mobile apps are found inflating their anonymous pages, we propose identifying unused anonymous pages in sync with the app-switching events. In addition, Android devices replaces the swap device with RAM-based zram, and swapping on zram is much faster than file accessing on flash storage. Without causing thrashing, we propose swapping out as many anonymous pages to zram as possible for caching more file pages. We conduct experiments on a Google Pixel phone with realistic user workloads, and results confirm that our method is adaptive to different memory requirements and greatly improves the app-switching latency by up to 43% compared with the original kernel.
CABARRE: Request Response Arbitration for Shared Cache Management
Authors: Modi Garima , Bagchi Aritra , Jindal Neetu , Mandal Ayan , Panda Preeti Ranjan
Published: September 2023

Modern multi-processor systems-on-chip (MPSoCs) are characterized by caches shared by multiple cores. These shared caches receive
requests
issued by the processor cores. Requests that are subject to cache misses may result in the generation of
responses
. These responses are received from the lower level of the memory hierarchy and written to the cache. The outstanding requests and responses contend for the shared cache bandwidth. To mitigate the impact of the cache bandwidth contention on the overall system performance, an efficient request and response arbitration policy is needed.

Research on shared cache management has neglected the additional cache contention caused by responses, which are written to the cache. We propose
CABARRE
, a novel request and response arbitration policy at shared caches, so as to improve the overall system performance.
CABARRE
shows a performance improvement of 23% on average across a set of SPEC workloads compared to straightforward adaptations of state-of-the-art solutions.
Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks
Authors: Sharma Harsh , Pfromm Lukas , Topaloglu Rasit Onur , Doppa Janardhan Rao , Ogras Umit Y. , Kalyanraman Ananth , Pande Partha Pratim
Published: September 2023

Recent advances in 2.5D chiplet platforms provide a new avenue for compact scale-out implementations of emerging compute- and data-intensive applications including machine learning. Network-on-Interposer (NoI) enables integration of multiple chiplets on a 2.5D system. While these manycore platforms can deliver high computational throughput and energy efficiency by running multiple specialized tasks concurrently, conventional NoI architectures have a limited computational throughput due to their inherent multi-hop topologies. In this paper, we propose Floret, a novel NoI architecture based on space-filling curves (SFCs). The Floret architecture leverages suitable task mapping, exploits the data flow pattern, and optimizes the inter-chiplet data exchange to extract high performance for multiple types of convolutional neural network (CNN) inference tasks running concurrently. We demonstrate that the Floret architecture reduces the latency and energy up to 58% and 64%, respectively, compared to state-of-the-art NoI architectures while executing datacenter-scale workloads involving multiple CNN tasks simultaneously. Floret achieves high performance and significant energy savings with much lower fabrication cost by exploiting the data-flow awareness of the CNN inference tasks.
GHOST: A Graph Neural Network Accelerator using Silicon Photonics
Authors: Afifi Salma , Sunny Febin , Shafiee Amin , Nikdast Mahdi , Pasricha Sudeep
Published: September 2023

Graph neural networks (GNNs) have emerged as a powerful approach for modelling and learning from graph-structured data. Multiple fields have since benefitted enormously from the capabilities of GNNs, such as recommendation systems, social network analysis, drug discovery, and robotics. However, accelerating and efficiently processing GNNs require a unique approach that goes beyond conventional artificial neural network accelerators, due to the substantial computational and memory requirements of GNNs. The slowdown of scaling in CMOS platforms also motivates a search for alternative implementation substrates. In this paper, we present
GHOST
, the first silicon-photonic hardware accelerator for GNNs.
GHOST
efficiently alleviates the costs associated with both vertex-centric and edge-centric operations. It implements separately the three main stages involved in running GNNs in the optical domain, allowing it to be used for the inference of various widely used GNN models and architectures, such as graph convolution networks and graph attention networks. Our simulation studies indicate that
GHOST
exhibits at least 10.2 × better throughput and 3.8 × better energy efficiency when compared to GPU, TPU, CPU and multiple state-of-the-art GNN hardware accelerators.
SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip
Authors: Clair Judicael , Eichler Guy , Carloni Luca P.
Published: September 2023

Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed with limited concerns to the problem of integrating it with other components in a heterogeneous System-on-Chip (SoC). Building on a state-of-the-art reconfigurable neuromorphic architecture, we present the design of a neuromorphic hardware accelerator equipped with a programmable interface that simplifies both the integration into an SoC and communication with the processor present on the SoC. To optimize the allocation of on-chip resources, we develop an optimizer to restructure existing neuromorphic models for a given hardware architecture, and perform design-space exploration to find highly efficient implementations. We conduct experiments with various FPGA-based prototypes of many-accelerator SoCs, where Linux-based applications running on a RISC-V processor invoke Pareto-optimal implementations of our accelerator alongside third-party accelerators. These experiments demonstrate that our neuromorphic hardware, which is up to 89× faster and 170× more energy efficient after applying our optimizer, can be used in synergy with other accelerators for different application purposes.
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility
Authors: Ikeda Sosei , Awano Hiromitsu , Sato Takashi
Published: September 2023

A delayed feedback reservoir (DFR) is a type of reservoir computing system well-suited for hardware implementations owing to its simple structure. Most existing DFR implementations use analog circuits that require both digital-to-analog and analog-to-digital converters for interfacing. However, digital DFRs emulate analog nonlinear components in the digital domain, resulting in a lack of design flexibility and higher power consumption. In this paper, we propose a novel modular DFR model that is suitable for fully digital implementations. The proposed model reduces the number of hyperparameters and allows flexibility in the selection of the nonlinear function, which improves the accuracy while reducing the power consumption. We further present two DFR realizations with different nonlinear functions, achieving 10× power reduction and 5.3× throughput improvement while maintaining equal or better accuracy.
VADF:

V

ersatile

A

pproximate

D

ata

F

ormats for Energy-Efficient Computing
Authors: Mishra Vishesh , Mittal Sparsh , Hassan Neelofar , Singhal Rekha , Chatterjee Urbi
Published: September 2023

Approximate computing (AC) techniques provide overall performance gains in terms of power and energy savings at the cost of minor loss in application accuracy. For this reason, AC has emerged as a viable method for efficiently supporting several compute-intensive applications, e.g., machine learning, deep learning, and image processing, that can tolerate bounded errors in computations. However, most prior techniques do not consider the possibility of soft errors or malicious bit-flips in AC systems. These errors may interact with approximation-introduced errors in unforeseen ways, leading to disastrous consequences, such as the failure of computing systems. A recent research effort, FTApprox (DATE’21) proposes an error-resilient approximate data format. FTApprox stores two blocks, starting from the one containing the most significant valid (MSV) bit. It also stores location of the MSV block and protects them using error-correcting bits (ECBs). However, FTApprox has crucial limitations such as lack of flexibility, redundantly storing zeros in the MSV, etc.

In this paper, we propose a novel storage format named Versatile Approximate Data Format (VADF) for storing approximate integer numbers while providing resilience to soft errors. VADF prescribes rules for storing, for example, a 32-bit number in either 8-bit, 12-bit or 16-bit numbers. VADF identifies the MSV bit and stores a certain number of bits following the MSV bit. It also stores the location of the MSV bit and protects it by ECBs. VADF does not explicitly store the MSB bit itself and this prevents VADF from accruing significant errors. VADF incurs lower error than both truncation methodologies and FTApprox. We further evaluate five image-processing and machine-learning applications and confirm that VADF provides higher application quality than FTApprox in the presence and absence of soft errors. Finally, VADF allows the use of narrow arithmetic units. For example, instead of using a 32-bit multiplier/adder, one can first use VADF (or FTApprox) to compress the data and then use a 8-bit multiplier/adder. Through this approach, VADF facilitates 95.97% and 79.3% energy savings in multiplication and addition, respectively. However, the subsequent re-conversion of the 8-bit output data to 32-bit data using Inv-VADF(16,3,32) diminishes the energy savings by 9.6% for addition and 0.56% for multiplication operation, respectively. The code is available at
https://github.com/CandleLabAI/VADF-ApproximateDataFormat-TECS
.
ObNoCs
: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks
Authors: Halder Dipal , Merugu Maneesh , Ray Sandip
Published: September 2023

Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineering the NoC topology and routing logic. In this paper, we develop an infrastructure,
ObNoCs
, for protecting NoC fabrics against such attacks.
ObNoCs
systematically replaces router connections with switches that can be programmed after fabrication to induce the desired topology. Our approach provides provable redaction of NoC functionality: switch configurations induce a large number of legal topologies, only one of which corresponds to the intended topology. We implement the
ObNoCs
methodology on Intel Quartus™ Platform, and experimental results on realistic SoC designs show that the architecture incurs minimal overhead in power, resource utilization, and system latency.
Computationally Efficient DNN Mapping Search Heuristic using Deep Reinforcement Learning
Authors: Bakshi Suyash , Johnsson Lennart
Published: September 2023

In this work, we present a computationally efficient Reinforcement Learning mapping search heuristic for finding high quality mappings for N-dimensional convolution loops that uses a computationally inexpensive reward function based on potential data reuse of operands to guide the search process. We also present a RL state representation generalizable to N-dimensional convolution loops, and a state representation parsing strategy ensuring that only valid mappings are evaluated for quality. Our RL search heuristic is applicable to multi-core systems with a memory hierarchy. We show that our RL based search heuristic for a range of 3D convolution layers, at significantly lower computational expense than random search, generally yields mappings with lower Energy-Delay Product (EDP) for an architecture with multiple processing elements with shared memory connected to DRAM. Our evaluation results demonstrated across 19 3D convolution layers, shows that our RL method performed only an average 11.24% of the operations of that of Timeloop’s random search for assessing same number of valid mappings. The mappings found using Timeloop had an average 12.51% higher EDP compared to lowest EDP mapping found using our RL method. Further, the lowest EDP mappings found using our method had an average only 4.69× higher EDP than the theoretical lower bound EDP, with the best case being only 1.29× higher.
ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices
Authors: Ravi Akshara , Chaturvedi Vivek , Shafique Muhammad
Published: September 2023

There has been a tremendous growth of edge devices connected to the network in recent years. Although these devices make our life simpler and smarter, they need to perform computations under severe resource and energy constraints, while being vulnerable to malware attacks. Once compromised, these devices are further exploited as attack vectors targeting critical infrastructure. Most existing malware detection solutions are resource and compute-intensive and hence perform poorly in protecting edge devices. In this paper, we propose a novel approach ViT4Mal that utilizes a lightweight vision transformer (ViT) for malware detection on an edge device. ViT4Mal first converts executable byte-code into images to learn malware features and later uses a customized lightweight ViT to detect malware with high accuracy. We have performed extensive experiments to compare our model with state-of-the-art CNNs in the malware detection domain. Experimental results corroborate that ViTs don’t demand deeper networks to achieve comparable accuracy of around 97% corresponding to heavily structured CNN models. We have also performed hardware deployment of our proposed lightweight ViT4Mal model on the Xilinx PYNQ Z1 FPGA board by applying specialized hardware optimizations such as quantization, loop pipelining, and array partitioning. ViT4Mal achieved an accuracy of ~94% and a 41x speedup compared to the original ViT model.
ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs
Authors: Deb Dipika , Jose John
Published: September 2023

Data prefetching efficiently reduces the memory access latency in NUCA architectures as the Last Level Cache (LLC) is shared and distributed across multiple cores. But cache pollution generated by prefetcher reduces its efficiency by causing contention for shared resources such as LLC and the underlying network. The paper proposes Zero Pollution Prefetcher (ZPP) that eliminates cache pollution for NUCA architecture. For this purpose, ZPP uses L1 prefetcher and places the prefetched blocks in the data locations of LLC where modified blocks are stored. Since modified blocks in LLC are stale and request for such blocks are served from the exclusively owned private cache, their space unnecessary consumes power to maintain such stale data in the cache. The benefits of ZPP are (a) Eliminates cache pollution in L1 and LLC by storing prefetched blocks in LLC locations where stale blocks are stored. (b) Insufficient cache space is solved by placing prefetched blocks in LLC as LLCs are larger in size than L1 cache. This helps in prefetching more cache blocks, thereby increasing prefetch aggressiveness. (c) Increasing prefetch aggressiveness increases its coverage. (d) It also maintains an equivalent lookup latency to L1 cache for prefetched blocks. Experimentally it has been found that ZPP increases weighted speedup by 2.19x as compared to a system with no prefetching while prefetch coverage and prefetch accuracy increases by 50%, and 12%, respectively compared to the baseline.

1
CRIMP:

C

ompact &

R

eliable DNN Inference on

I

n-

M

emory

P

rocessing via Crossbar-Aligned Compression and Non-ideality Adaptation
Authors: Huai Shuo , Kong Hao , Luo Xiangzhong , Li Shiqing , Subramaniam Ravi , Makaya Christian , Lin Qian , Liu Weichen
Published: September 2023

Crossbar-based In-Memory Processing (IMP) accelerators have been widely adopted to achieve high-speed and low-power computing, especially for deep neural network (DNN) models with numerous weights and high computational complexity. However, the floating-point (FP) arithmetic is not compatible with crossbar architectures. Also, redundant weights of current DNN models occupy too many crossbars, limiting the efficiency of crossbar accelerators. Meanwhile, due to the inherent non-ideal behavior of crossbar devices, like write variations, pre-trained DNN models suffer from accuracy degradation when it is deployed on a crossbar-based IMP accelerator for inference. Although some approaches are proposed to address these issues, they often fail to consider the interaction among these issues, and introduce significant hardware overhead for solving each issue. To deploy complex models on IMP accelerators, we should compact the model and mitigate the influence of device non-ideal behaviors without introducing significant overhead from each technique.

In this paper, we first propose to reuse bit-shift units in crossbars for approximately multiplying scaling factors in our quantization scheme to avoid using FP processors. Second, we propose to apply kernel-group pruning and crossbar pruning to eliminate the hardware units for data aligning. We also design a zerorize-recover training process for our pruning method to achieve higher accuracy. Third, we adopt the runtime-aware non-ideality adaptation with a self-compensation scheme to relieve the impact of non-ideality by exploiting the feature of crossbars. Finally, we integrate these three optimization procedures into one training process to form a comprehensive learning framework for co-optimization, which can achieve higher accuracy. The experimental results indicate that our comprehensive learning framework can obtain significant improvements over the original model when inferring on the crossbar-based IMP accelerator, with an average reduction of computing power and computing area by 100.02× and 17.37×, respectively. Furthermore, we can obtain totally integer-only, pruned, and reliable VGG-16 and ResNet-56 models for the Cifar-10 dataset on IMP accelerators, with accuracy drops of only 2.19% and 1.26%, respectively, without any hardware overhead.
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures
Authors: Ahmed Soyed Tuhin , Danouchi Kamal , Hefenbrock Michael , Prenat Guillaume , Anghel Lorena , Tahoori Mehdi B.
Published: September 2023

Recent development in neural networks (NNs) has led to their widespread use in critical and automated decision-making systems, where uncertainty estimation is essential for trustworthiness. Although conventional NNs can solve many problems accurately, they do not capture the uncertainty of the data or the model during optimization. In contrast, Bayesian neural networks (BNNs), which learn probabilistic distributions for their parameters, offer a sound theoretical framework for estimating uncertainty. However, traditional hardware implementations of BNNs are expensive in terms of computational and memory resources, as they (i) are realized with inefficient von Neumann architectures, (ii) use a significantly large number of random number generators (RNGs) to implement the distributions of BNNs, and (iii) have a substantially greater number of parameters than conventional NNs. Computing-in-memory (CiM) architectures with emerging resistive non-volatile memories (NVMs) are promising candidates for accelerating classical NNs. In particular, spintronic technology, which is distinguished by its low latency and high endurance, aligns very well with these requirements. In the specific context of Bayesian neural networks (BNNs), spintronics technologies are very valuable, thanks to their inherent potential to act as stochastic or as deterministic devices. Consequently, BNNs mapped on spintronic-based CiM architectures could be a highly efficient implementation strategy. However, the direct implementation on CiM hardware of the learned probabilistic distributions of BNN may not be feasible and can incur high overhead. In this work, we propose a new Bayesian neural network topology, named
SpinBayes
, that is able to perform efficient sampling during the Bayesian inference process. Moreover, a Bayesian approximation method, called
in-memory approximation
, is proposed that approximates the original probabilistic distributions of BNN with a distribution that can be efficiently mapped to spintronic-based CiM architectures. Compared to state-of-the-art methods, the memory overhead is reduced by 8× and the energy consumption by 80×. Our method has been evaluated on several classification and semantic segmentation tasks and can detect up to 100% of various types of out-of-distribution data, highlighting the robustness of our approach, without any performance sacrifice.
Sound Mixed Fixed-Point Quantization of Neural Networks
Authors: Lohar Debasmita , Jeangoudoux Clothilde , Volkova Anastasia , Darulova Eva
Published: September 2023

Neural networks are increasingly being used as components in safety-critical applications, for instance, as controllers in embedded systems. Their formal safety verification has made significant progress but typically considers only idealized real-valued networks. For practical applications, such neural networks have to be quantized, i.e., implemented in finite-precision arithmetic, which inevitably introduces roundoff errors. Choosing a suitable precision that is both guaranteed to satisfy a roundoff error bound to ensure safety and that is as small as possible to not waste resources is highly nontrivial to do manually. This task is especially challenging when quantizing a neural network in fixed-point arithmetic, where one can choose among a large number of precisions and has to ensure overflow-freedom explicitly.

This paper presents the first sound and fully automated mixed-precision quantization approach that specifically targets deep feed-forward neural networks. Our quantization is based on mixed-integer linear programming (MILP) and leverages the unique structure of neural networks and effective over-approximations to make MILP optimization feasible. Our approach efficiently optimizes the number of bits needed to implement a network while guaranteeing a provided error bound. Our evaluation on existing embedded neural controller benchmarks shows that our optimization translates into precision assignments that mostly use fewer machine cycles when compiled to an FPGA with a commercial HLS compiler than code generated by (sound) state-of-the-art. Furthermore, our approach handles significantly more benchmarks substantially faster, especially for larger networks.
Stochastic Analysis of Control Systems Subject to Communication and Computation Faults
Authors: Vreman Nils , Maggio Martina
Published: September 2023

Control theory allows one to design controllers that are robust to external disturbances, model simplification, and modelling inaccuracy. Researchers have investigated whether the robustness carries on to the controller’s digital implementation, mostly looking at how the controller reacts to either communication or computational problems. Communication problems are typically modelled using random variables (i.e., estimating the probability that a fault will occur during a transmission), while computational problems are modelled using deterministic guarantees on the number of deadlines that the control task has to meet. These fault models allow the engineer to both design robust controllers and assess the controllers’ behaviour in the presence of isolated faults. Despite being very relevant for the real-world implementations of control system, the question of what happens when these faults occur simultaneously does not yet have a proper answer. In this paper, we answer this question in the stochastic setting, using the theory of Markov Jump Linear Systems to provide stability contracts with
almost sure
guarantees of convergence. For linear time-invariant Markov jump linear systems, mean square stability implies almost sure convergence – a property that is central to our investigation. Our research primarily emphasises the validation of this property for closed-loop systems that are subject to packet losses and computational overruns, potentially occurring simultaneously. We apply our method to two case studies from the recent literature and show their robustness to a comprehensive set of faults. We employ closed-loop system simulations to empirically derive performance metrics that elucidate the quality of the controller implementation, such as the system settling time and the integral absolute error.
Formal Synthesis of Neural Barrier Certificates for Continuous Systems via Counterexample Guided Learning
Authors: Zhao Hanrui , Qi Niuniu , Dehbi Lydia , Zeng Xia , Yang Zhengfeng
Published: September 2023

This paper presents a novel approach to safety verification based on neural barrier certificates synthesis for continuous dynamical systems. We construct the synthesis framework as an inductive loop between a
Learner
and a
Verifier
based on barrier certificate learning and counterexample guidance. Compared with the counterexample-guided verification method based on the SMT solver, we design and learn neural barrier functions with special structure, and use the special form to convert the counterexample generation into a polynomial optimization problem for obtaining the optimal counterexample. In the verification phase, the task of identifying the real barrier certificate can be tackled by solving the Linear Matrix Inequalities (LMI) feasibility problem, which is efficient and makes the proposed method formally sound. The experimental results demonstrate that our approach is more effective and practical than the traditional SOS-based barrier certificates synthesis and the state-of-the-art neural barrier certificates learning approach.
B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles
Authors: Szeto Matthew , Andert Edward , Shrivastava Aviral , Reisslein Martin , Lin Chung-Wei , Richmond Christ
Published: September 2023

5G Millimeter Wave (mmWave) technology holds great promise for Connected Autonomous Vehicles (CAVs) due to its ability to achieve data rates in the Gbps range. However, mmWave suffers from a high beamforming overhead and requirement of line of sight (LOS) to maintain a strong connection. For Vehicle-to-Infrastructure (V2I) scenarios, where CAVs connect to roadside units (RSUs), these drawbacks become apparent. Because vehicles are dynamic, there is a large potential for link blockages. These blockages are detrimental to the connected applications running on the vehicle, such as cooperative perception and remote driver takeover. Existing RSU selection schemes base their decisions on signal strength and vehicle trajectory alone, which is not enough to prevent the blockage of links. Many modern CAVs motion planning algorithms routinely use other vehicle’s near-future path plans, either by explicit communication among vehicles, or by prediction. In this paper, we make use of the knowledge of other vehicle’s near future path plans to further improve the RSU association mechanism for CAVs. We solve the RSU association algorithm by converting it to a shortest path problem with the objective to maximize the total communication bandwidth. We evaluate our approach, titled B-AWARE, in simulation using Simulation of Urban Mobility (SUMO) and Digital twin for self-dRiving Intelligent VEhicles (DRIVE) on 12 highway and city street scenarios with varying traffic density and RSU placements. Simulations show B-AWARE results in a 1.05× improvement of the potential datarate in the average case and 1.28× in the best case vs. the state-of-the-art. But more impressively, B-AWARE reduces the time spent with no connection by 42% in the average case and 60% in the best case as compared to the state-of-the-art methods. This is a result of B-AWARE reducing nearly 100% of blockage occurrences.
Probabilistic Reaction Time Analysis
Authors: Günzel Mario , Ueter Niklas , Chen Kuan-Hsun , von der Brüggen Georg , Chen Jian-Jia
Published: September 2023

In many embedded systems, for instance, in the automotive, avionic, or robotics domain, critical functionalities are implemented via chains of communicating recurrent tasks. To ensure safety and correctness of such systems, guarantees on the reaction time, that is, the delay between a cause (e.g., an external activity or reading of a sensor) and the corresponding effect, must be provided.

Current approaches focus on the maximum reaction time, considering the worst-case system behavior. However, in many scenarios, probabilistic guarantees on the reaction time are sufficient. That is, it is sufficient to provide a guarantee that the reaction does not exceed a certain threshold with (at least) a certain probability.

This work provides such probabilistic guarantees on the reaction time, considering two types of randomness: response time randomness and failure probabilities. To the best of our knowledge, this is the first work that defines and analyzes probabilistic reaction time for cause-effect chains based on sporadic tasks.
Energy-efficient Personalized Federated Search with Graph for Edge Computing
Authors: Yang Zhao , Sun Qingshuang
Published: September 2023

Federated Learning (FL) is a popular method for privacy-preserving machine learning on edge devices. However, the heterogeneity of edge devices, including differences in system architecture, data, and co-running applications, can significantly impact the energy efficiency of FL. To address these issues, we propose an energy-efficient personalized federated search framework. This framework has three key components. Firstly, we search for partial models with high inference efficiency to reduce training energy consumption and the occurrence of stragglers in each round. Secondly, we build lightweight search controllers that control the model sampling and respond to runtime variances, mitigating new straggler issues caused by co-running applications. Finally, we design an adaptive search update strategy based on graph aggregation to improve personalized training convergence. Our framework reduces the energy consumption of the training process by lowering the training overhead of each round and speeding up the training convergence rate. Experimental results show that our approach achieves up to 5.02% accuracy and 3.45× energy efficiency improvements.
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology
Authors: Kalomiros John , Vourvoulakis John , Vologiannidis Stavros
Published: September 2023

The semi-global matching stereo algorithm is a top performing algorithm in stereo vision. The recursive nature of the computations involved in this algorithm introduces an inherent data dependency problem, hindering the progressive computations of disparities at pixel clock. In this work, a novel hardware implementation of the semi-global matching algorithm is presented. A hardware structure of parallel comparators is proposed for the fast computation of the minima among large cost arrays in one clock cycle. Also, a hardware-friendly algorithm is proposed for the computation of the minima among far-indexed disparity costs, shortening the length of computations in the datapath. As a result, the recursive path cost computation is accelerated considerably. The system is implemented in a Stratix V device and in a Zynq UltraScale+ device. A throughput of 55,1 million disparities per second is achieved with maximum disparity 128 pixels and frame resolution 1280 × 720. The proposed architecture is less elaborate and more resource efficient than other systems in the literature and its performance compares favorably to them. An implementation on an actual FPGA board is also presented and serves as a real-world verification of the proposed system.
Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation
Authors: Jain Vaibhav , Sharma Devendra Kumar , Gaur Hari Mohan , Singh Ashutosh Kumar , Wen Xiaoqing
Published: September 2023

For the past several decades, VLSI design has been focused on lowering the size, power, and delay. As of now, this miniaturization does not seems to be a possible way to address the demands of consumers. Quantum Dot Cellular Automata (QCA) technology is a promising technique that is able to provide low-power high-speed circuits at nano-scale. Much work has been done in this area where the researchers have proposed a variety of combinational and sequential logic circuits for future computation. This article presents a concrete review of design approaches, logic circuits, clocking schemes, implementation tools, and possible fabrication methodologies presented so far in QCA technology. A critical comparative analysis is provided on the basis of reported performance parameters in the domain. The aim of this article is to collect all necessary information into a single source, highlight the research challenges to be taken in the near future, and enlighten the path for upcoming researchers in the area.
Demystify the Fuzzing Methods: A Comprehensive Survey
Authors: Mallissery Sanoop , Wu Yu-Sung
Published: September 2023

Massive software applications possess complex data structures or parse complex data structures; in such cases, vulnerabilities in the software become inevitable. The vulnerabilities are the source of cyber-security threats, and discovering this before the software deployment is challenging. Fuzzing is a vulnerability discovery solution that resonates with random-mutation, feedback-driven, coverage-guided, constraint-guided, seed-scheduling, and target-oriented strategies. Each technique is wrapped beneath the black-, white-, and grey-box fuzzers to uncover diverse vulnerabilities. It consists of methods such as identifying structural information about the test cases to detect security vulnerabilities, symbolic and concrete program states to explore the unexplored locations, and full semantics of code coverage to create new test cases. We methodically examine each kind of fuzzers and contemporary fuzzers with a profound observation that addresses various research questions and systematically reviews and analyze the gaps and their solutions. Our survey comprised the recent related works on fuzzing techniques to demystify the fuzzing methods concerning the application domains and the target that, in turn, achieves higher code coverage and sound vulnerability detection.
The Relationship between Pain Catastrophizing and Cognitive Function in Chronic Musculoskeletal Pain: A Scoping Review
Authors: Alcon Cory , Bergman Elizabeth , Humphrey John , Patel Rupal M. , Wang-Price Sharon
Published: September 2023

Objective. Chronic musculoskeletal pain (CMP) poses a considerable threat to physical, mental, and financial health worldwide. Beyond physical difficulties, CMP has a pronounced impact on pain behaviors and cognitive function. The purpose of this scoping review was to examine the relationship between pain catastrophizing (PC) and cognitive function in CMP, identify gaps in the literature, and provide future directions for research on the topic. Methods. Search strings were entered in the following databases: PubMed, CINAHL, Nursing and Allied Health, Ovid Emcare, PsycInfo, and Scopus. Data from the included articles were extracted thematically based on diagnostic classification and included author(s), year of publication, country, aim, sample, methods, intervention (if applicable), and key findings. Results. 30 articles were included after screening. The studied populations included patients with fibromyalgia, chronic low back pain, and CMP. Two studies were designed to assess the relationship between PC and cognition as the primary aim. The included studies demonstrated variable evidence regarding the relationship between PC and cognition. Only four studies included clinically relevant PC populations (i.e., Pain Catastrophizing Scale score >30), and all found significant correlations. Conclusion. Although evidence exists for the relationship between cognitive function and PC, there is a lack of rigorous research to indicate the strength of this relationship and the specific cognitive functions affected. The literature lacks appropriate populations needed to investigate clinically relevant PC and is limited by heterogeneous neuropsychological test batteries. Future research should include populations demonstrating the behaviors being studied, intentional analysis of outcomes, and appropriate cognitive tests.
O IDORT e a habitação econômica: a difusão de experiências internacionais (1932-1960)
Authors: Correia Telma de Barros , Almeida Caliane Christie Oliveira de
Published: September 2023

Trata do papel e da importância do Instituto de Organização Racional do Trabalho (IDORT), fundado em São Paulo em 1931, na difusão entre técnicos e empresários brasileiros das noções de eficiência e racionalidade no campo da moradia. Destaca o esforço do órgão na busca de inspiração e sincronia com debates e realizações internacionais, colocando sua revista como instrumento de divulgação destas experiências e de reflexão sobre elas. Investiga as diferentes abordagens pelas quais o tema da habitação surge na revista em um conjunto de matérias referentes a experiências internacionais: urbanismo, projeto arquitetônico, layout interno, padronização de materiais e componentes da construção, organização das tarefas domésticas, aperfeiçoamento de instalações prediais, ação do Estado e estratégias de financiamento da construção. Mostra como este conjunto de artigos constrói uma visão abrangente da questão da busca de racionalização e eficiência no âmbito da habitação, abordando ações e debates sob diferentes perspectivas em termos de escala de intervenção no espaço, de processos e de agentes envolvidos. Considerando a abrangência da abordagem da moradia pelo periódico do IDORT e a influência de seus leitores nos meios empresariais, técnicos e administrativos, avalia que o órgão e sua publicação oficial tiveram um papel relevante durante o período tratado nos rumos dos debates e das realizações no âmbito da moradia econômica no Brasil.
A Still Small Voice: Psalms and Correlation as Media of Communication in Hermann Cohen’s Philosophy
Authors: Alon-Altman Talya
Published: September 2023

This article examines communication between a human being and God in the Jewish philosophy of Hermann Cohen (1842–1918). The article focuses on two distinct forms of biblical communication: lyrical psalms and a godly revelation in a still small voice. It investigates Cohen’s Jewish philosophy in light of communication theories to deepen the philosophical and theoretical discussion. The article examines previously unexplored ideas in Cohen’s writings, analyzes his religious perceptions in terms of communication, and at the same time expands the concept of communication. This new perspective sheds new light on Cohen’s Jewish philosophy and offers a new philosophic perception of divine-human communication.
The Myth of Zero-Sum Responsibility: Towards Scaffolded Responsibility for Health
Authors: Levy Neil , Savulescu Julian
Published: September 2023

Some people argue that the distribution of medical resources should be sensitive to agents’ responsibility for their ill-health. In contrast, others point to the social determinants of health to argue that the collective agents that control the conditions in which agents act should bear responsibility. To a large degree, this is a debate in which those who hold individuals responsible currently have the upper hand: warranted appeals to individual responsibility effectively block allocation of any significant degree of responsibility to collective agents. We suggest that a different understanding of individual responsibility might lead to a fairer allocation of blame. Scaffolded agency is individual agency exercised in a context in which opportunities and affordances are structured by others. Appeals to scaffolded agency at once recognize the role of the individual and of the collective agents who have put the scaffolds in place.
Multiparty Coalition Governments, Portfolio Allocation and Ministerial Turnover in Morocco and Algeria
Authors: Resta Valeria , Daadaoui Mohamed
Published: September 2023

The article analyzes multiparty coalition governments under authoritarian tutelage in Morocco and Algeria. While in Morocco multiparty coalition governments are just a means for the King to dress their windows, in Algeria they represent a new arena of power bargaining. In both cases, portfolio allocation follows the Gamson’s law but cases of advantage for the formateur are also given. Nonetheless, the parties included in multiparty coalition governments are almost always regime-controlled ones, as is the case in Algeria, or encounter reserved domains constitutionally defined, as is the case in Morocco. Moreover, in both cases the democratic potential intrinsic to multiparty coalition governments is defused by preventing grassroots parties to access top-weighted ministerial portfolios and by envisaging a relevant role for non-party ministries. This renders cabinet positions hardly contestable and adds up to the durability of multiparty coalition governments while making them barely apt at channeling grassroots demands for political change.