bluuebunny/crossref_metadata_2025 huggingface dataset:
Correlations between Crystal Quality and Electrical Properties by Means of Simultaneous Photoluminescence and Photocurrent Analysis
Authors: Privitera Stefania , Camarda Massimo , Piluso Nicolò , Anzalone Ruggero , La Via Francesco
Published: July 2015

In this paper we have studied the connection between crystal quality and electrical transport in 4H-SiC by simultaneous micro-photoluminescence (μPL) and micro-photocurrent (μPC) measurements. We have used a focused HeCd laser at 325nm (i.e. above bandgap) to measure with a spatial resolution of few microns both the μPL spectra and the I-V characteristics in 4H-SiC/NiSi Schottky diodes. We found that extended defects exhibiting a photoluminescence peak located at 2.9eV (i.e single Shockley or bar shaped stacking faults) can produce an increase of the measured PC whereas other defects, such as the (4,4) stacking fault, can be considered as ‘killer defects’, strongly reducing the photocurrent.
Effects of Crystalline Polarity and Temperature Gradient on Step Bunching Behavior of Off-Axis 4H-SiC Solution Growth
Authors: Endo Shota , Kamei K. , Kishida Y. , Moriguchi K.
Published: July 2015

The off-axis solution growth of 4H-SiC was studied focusing on the morphological instabilities by using conventional TSSG technique. The morphology depends strongly on the crystalline polarity, and that on Si surface can be characterized by wandering while that on C surface is characterized by strong step-bunching. By raising the temperature gradient, step bunching on Si surface is considerably suppressed which can be consistent to the constitutional super cooling scheme. However, C surface exhibits strong step bunching as the temperature gradient increase. These behaviors can be explained by the difference in Ehrlich-Schwoebel barrier and diffusion behavior of adatoms.
Two-Dimensional Carrier Profiling on Lightly Doped n-Type 4H-SiC Epitaxially Grown Layers
Authors: ROSSMANN Harald , Gysin Urs , Bubendorf Alexander , Glatzel Thilo , Reshanov Sergey A. , Schöner Adolf , Jung T.A. , Meyer Ernst , Bartolf Holger
Published: July 2015

Electronically active dopant profiles of epitaxially grown n-type 4H-SiC calibration layer structures with concentrations ranging from 3.1015 cm-3 to 1·1019 cm-3 have been investigated by non-contact Scanning Probe Microscopy (SPM) methods. We have shown that Kelvin Probe Force Microscopy (KPFM) and Electrostatic Force Microscopy (EFM) are capable of resolving two-dimensional carrier maps in the low doping concentration regime with nanoscale spatial resolution. Furthermore, different information depths of this wide band gap semiconductor material could be assessed due to the inherent properties of each profiling method. We additionally observed a resolution enhancement under laser illumination which we explain by reduced band-bending conditions. To gauge our SPM signals, we utilized epitaxially grown layers which were calibrated, in terms of dopant concentration, by C-V measurements.
A Novel Approach to Measuring Doping in SiC by Micro Spot Corona-Kelvin Method
Authors: Marinskiy Dmitriy , Savtchouk Alexandre
Published: July 2015

In this work we propose a novel approach to measuring doping concentration in SiC based on a micro-scale time-resolved corona-Kelvin technique. In this method corona charging of SiC surface into depletion is done within a micro size corona spot and a Kelvin-force micro-probe is used to measure surface voltage decay in the center of the spot. The voltage decay is due to charge decay due to surface diffusion producing analogy of voltage-charge scanning under the probe. We use 2D charge diffusion analysis to extract two parameters – 1) doping concentration in the SiC epitaxial layer and 2) diffusion coefficient of corona ions on the SiC surface. The micro-spot corona-Kelvin method demonstrated in this work shall prove of importance for testing of doping uniformity on micro scale and measurements on a small area in SiC production wafers.
Elimination of Basal Plane Dislocations in Epitaxial 4H-SiC via Multicycle Rapid Thermal Annealing
Authors: Tadjer Marko J. , Mahadik Nadeemullah A. , Feigelson Boris N. , Stahlbush Robert E. , Imhoff Eugene A. , Klein Paul B. , Freitas Jaime A. , Greenlee Jordan D. , Kub Fritz J.
Published: July 2015

Elimination of basal plane dislocations (BPDs) in epitaxial 4H-SiC is demonstrated via a novel pulsed annealing technique in a moderate N2 overpressure of 0.55 MPa. BPD removal in 15 µm thick epitaxial 4H-SiC was confirmed using ultraviolet photoluminescence (UVPL) imaging before and after the annealing process. The samples were capped with a carbon cap, introduced into the annealing chamber, and brought up to a base temperature (TBASE) of around 1550 °C for the pulsed anneal. The multicycle rapid thermal anneal (MRTA) was then performed in the TBASE:TMAX range, where TMAX = 1875 °C was the peak temperature reached by the annealing cycles. Post-anneal surface quality and carrier lifetime were characterized by atomic force microscopy and time-resolved photoluminescence decay.
Basal Plane Dislocation Analysis of 4H-SiC Using Multi Directional STEM Observation
Authors: Sato Takahiro , Ohtsu Yoshihiro , Orai Yoshihisa , Isshiki Toshiyuki , Fukui Munetoshi
Published: July 2015

A peculiar surface defect on a silicon carbide (SiC) epitaxial wafer, found to be associated a basal plane dislocation (BPD), was studied using a low energy scanning electron microscope (LESEM), and a novel method we are calling multi directional scanning transmission electron microscopy (MD-STEM). We have confirmed that an etch pit with double cores neighboring a peculiar surface defect is derived from the extended BPD. The BPD consisted of two partial dislocations with a stacking fault width of about 100 nm. Observation of only one viewing direction in a previous study missed the extended dislocation but through the use of the MD-STEM method in the current study, the dislocation has been confirmed to be extended into a stacking fault.
Annealing Temperature Dependence of Dislocation Extension and its Effect on Electrical Characteristic of 4H-SiC PIN Diode
Authors: Tanaka Atsushi , Kawabata Naoyuki , Tsujimura Masatoshi , Furukawa Yukihiro , Hoshino Taizo , Ueji Yoshinori , Omote Kazuhiko , Yamaguchi Hirotaka , Matsuhata Hirofumi , Fukuda Kenji
Published: July 2015

In this study, we investigated the annealing temperature dependence of dislocation extension in an ion-implanted region of a 4H-silicon carbide (SiC) C-face epitaxial layer, revealing that a high temperature annealing led to dislocation formation. We also investigated the current-voltage (I-V) characteristics of a 4H-SiC PIN diode with and without these extended dislocations. We demonstrated that the forward biased I-V characteristics of samples with extended interfacial dislocations have a kink at lower current regions.
Studies of the Origins of Half Loop Arrays and Interfacial Dislocations Observed in Homoepitaxial Layers of 4H-SiC
Authors: Wang H. , Wu F. , Yang Yu , Guo J.Q. , Raghothamachar Balaji , Venkatesh T.A. , Dudley Michael , Zhang Jie , Chung Gil Yong , Thomas Bernd , Sanchez Edward , Mueller Stephan G. , Hansen Darren , Loboda Mark J.
Published: July 2015

Dislocation behavior during homo-epitaxy of 4H-SiC on offcut substrates by Chemical Vapor Deposition (CVD) has been studied using Synchrotron X-ray Topography and KOH etching. Studies carried out before and after epilayer growth have revealed that, in some cases, short, edge oriented segments of basal plane dislocation (BPD) inside the substrate can be drawn towards the interface producing screw oriented segments intersecting the growth surface. In other cases, BPD half-loops attached to the substrate surface are forced to glide into the epilayer producing similar screw oriented surface intersections. It is shown that the initial motion of the short edge oriented BPD segments that are drawn from the substrate into the epilayer is caused by thermal stress resulting from radial temperature gradients experienced by the wafer whilst in the epi-chamber. This same stress also causes the initial glide of the surface half-loop into the epilayer and through the advancing epilayer surface. These mobile BPD segments provide screw oriented segments that pierce the advancing epilayer surface that initially replicate as the crystal grows. Once critical thickness is reached, according to the Mathews-Blakeslee model, these screw segments glide sideways under the action of the mismatch stress leaving IDs and HLAs in their wake.
3D Raman Spectroscopy Investigation of Defects in 4H-SiC Epilayer
Authors: Hara Kazukuni , Naito Masami , Fujibayashi Hiroaki , Akiba Atsuya , Takeuchi Yuuichi , Milikofu Olga , Kozu Tomomi
Published: July 2015

In this report we were able to successfully identify and localize in 3D 3C and 6H foreign polytypes and stress in the embedded epilayer by high resolution 3D Raman spectroscopy, that were otherwise invisible under the microscope or SEM, in non-contact and non-destructive way. Stripe patterned deep trenches with aspect ratio about 2 (depth=3.0μm; width=1.5μm) were formed on 4H-SiC substrate by ICP. The epitaxial layer was embedded in these trenches by SiC CVD. Poly type defects and stress in the embedded epilayer were mapped by curve-fitting of spectra obtained from Raman measurement of the embedded SiC epilayer. The location of the foreign polytypes and the stress inside the stripe pattern allows speculating on the origin of the defects and correlating it to the manufacturing process.
Reduction of Implantation-Induced Point Defects by Germanium Ions in n-Type 4H-SiC
Authors: Sledziewski Tomasz , Ellrott Gunter , Rösch W. , Weber Heiko B. , Krieger M.
Published: July 2015

We have investigated the electrical properties of germanium-implanted n-type 4H-SiC epitaxial layers. Deep level transient spectroscopy (DLTS) was employed in order to study the influence of germanium ions on implantation-induced point defects. In particular, we observe a decrease of the concentration of Z1/2 defect with increasing dose of implanted germanium.
Atomic-Scale Defects in Silicon Carbide for Quantum Sensing Applications
Authors: Dyakonov Vladimir , Kraus Hannes , Soltamov V.A. , Fuchs Franziska , Simin Dmitrij , Vaeth Stefan , Sperlich Andreas , Baranov Pavel , Astakhov G.
Published: July 2015

Atomic-scale defects in silicon carbide exhibit very attractive quantum properties that can be exploited to provide outstanding performance in various sensing applications. Here we provide the results of our studies of the spin-optical properties of the vacancy related defects in SiC. Our studies show that several spin-3/2 defects in silicon carbide crystal are characterized by nearly temperature independent axial crystal fields, which makes these defects very attractive for vector magnetometry. The zero-field splitting of another defect exhibits on contrast a giant thermal shift of 1.1 MHz/K at room temperature, and can be used for temperature sensing applications.
Tuning Optoelectronic Properties of 4H-SiC QDs Using -H, -OH and -F Surface Functionalisation
Authors: Rashid Marzaini , Tiwari Amit Kumar , Wood Neal , Briddon Patrick , Goss Jonathan P. , Rayson M.J. , Wright Nick , Horsfall Alton B.
Published: July 2015

Density functional calculations were performed for the –H, –OH and –F functional groups adsorbed onto the surface of pseudo-spherical 4H-SiC quantum dots with diameters ranging from 10 to 22 Å. We find that for the investigated diameter range, the H-terminated SiC-quantum dots exhibit strong size dependent quantum confinement effects, while for –F and –OH terminations, the optical gap remains largely unchanged. The –H termination shows an optical absorption onset well above that of –F and –OH for a similar cluster size, which is attributed to the localisation of HOMO and LUMO states to the quantum dot core. Based on our calculations, we suggest that the –H functionalisation is a more promising route for engineering the optical properties of SiC-quantum dots, since this could lead to a wider control over the optical absorption onsets, when compared to –OH and –F terminations.
SiC Device Manufacturing: How Processing Impacts the Material and Device Properties
Authors: Grossner Ulrike , Alfieri Giovanni , Nipoti Roberta
Published: July 2015

Studies in the literature have shown how the different processing steps can have an impact on the electronic properties of SiC devices. In this contribution, we will review the importance of preserving the crystalline integrity of SiC epilayers through the major processing steps like etching, implantation and oxidation. It will be shown that the major cause for SiC device failures, e.g bipolar degradation and low field effect mobility, is the presence of carbon-related defects like the carbon vacancy (VC) and carbon interstitials (Ci). At last, the different techniques devised to reduce the presence of these harmful defects will also be reviewed.
Distribution of Secondary Defects and Electrical Activation after Annealing of Al-Implanted SiC
Authors: Furukawa Yukihiro , Suzuki Hideo , Shimizu Saburou , Ohse Naoyuki , Watanabe Masahide , Fukuda Kenji
Published: July 2015

We investigated the relationship between secondary defects and electrical characteristics in the activation annealing (1600 °C-1800 °C) of 4H-SiC after Al implantation (3 × 1017 cm-3-3 × 1019 cm-3). X-ray topography revealed that the dislocation density did not increase after implantation and annealing. Scanning transmission electron microscopy (STEM) images revealed black spots that aggregate with increase in Al dose. The results of energy dispersive X-ray spectroscopy analysis suggested that these black spots are due to the strain of secondary defects. The I-V characteristics at reverse bias of a pin diode fabricated with Al implantation show that secondary defects shown as black spots in the STEM images do not affect the electrical characteristics under the implantation and annealing conditions used in this experiment.
Process Compatibility of Heavily Nitrogen Doped Layers Formed by Ion Implantation in Silicon Carbide Devices
Authors: Vassilevski Konstantin , Roy Sandip Kumar , Wood Neal , Horsfall Alton B. , Wright Nick G.
Published: July 2015

Heavily doped layers were formed in 4H-SiC device epitaxial structures comprised of moderately doped n layer (channel) and heavily doped p+ layer (gate). The n+ regions were formed by local ion implantation of nitrogen followed by post-implantation annealing with graphite capping layer. It was shown that annealing at 1700 °C is required for complete activation of implanted impurities. The post-implantation anneals were found to have no significant effect on the moderately nitrogen doped channel layer. On the other hand it resulted in noticeable deterioration of electrical propertied of heavily doped epitaxial p+ layers leading to the increase of contact resistivity which has to be taken into account in design and processing of SiC devices.
About the Hole Transport Analysis in Heavy Doped p-Type 4H-SiC(Al)
Authors: Parisini Antonella , Nipoti Roberta
Published: July 2015

The knowledge of the Hall factor is essential to convert Hall to drift transport data, in order to fit them and reliably evaluate doping and compensation levels of samples. By introducing empirical mass anisotropy factors, reasons were given in favour of a generalized use of the unique experimental evaluation of the Hall factor reported by the literature for p-type 4H-SiC, which has been assessed for an Al acceptor density in the range of 1.8×1015 - 2×1018 cm-3. Using such a curve, carrier transport data, taken in Al+ implanted 4H-SiC for an Al concentration of 5×1019 cm-3 after either 2000°C/30s microwave annealing or 1950°C/300s conventional annealing, were analysed through a standard relaxation time approximation model. A slight difference was evidenced in the compensation level of the samples, also resulting in a different ionization energy of the acceptor.
Silicon Nitride Encapsulation to Preserve Ohmic Contacts Characteristics in High Temperature, Oxygen Rich Environments
Authors: Roy Sandip Kumar , Vassilevski Konstantin , Wright Nicholas G. , Horsfall Alton B.
Published: July 2015

Ohmic contacts with low contact resistance, smooth surface morphology, and a well-defined edge profile are essential to ensure optimal device performance. Ohmic contacts often require annealing under vacuum at over 1000 °C, whilst high-κ dielectrics are usually annealed in O2 rich ambient at temperatures of 800 °C or less, affecting the specific contact resistivity (ρC) and RMS surface roughness. Therefore, protection of the Ohmic contacts during the annealing of a high-κ dielectric layer is a key enabling step in the realisation of high performance MOSFET structures. In order to prevent damage during the high-κ formation, a passivation layer capable of protecting the contacts during annealing is required. In this work we have investigated the suitability of PECVD silicon nitride as a passivation layer to protect Ohmic contacts during high temperature, oxygen rich annealing.
Preliminary Study on the Effect of Micrometric Ge-Droplets on the Characteristics of Ni/4H-SiC Schottky Contacts
Authors: Vivona Marilena , Giannazzo Filippo , Alassaad Kassem , Soulière Véronique , Ferro Gabriel , Roccaforte Fabrizio
Published: July 2015

This work reports on the morphological and electrical characteristics of Ni/4H-SiC Schottky contacts, fabricated on epitaxial layers intentionally covered by micrometric size Ge-droplets. Specifically, the Ge-droplets behave as preferential paths for the vertical current conduction, as observed at nanometric scale by conductive atomic force microscopy. As a consequence, the electrical I-V characteristics of these Ni contacts revealed the presence of a double-barrier, thus indicating an inhomogeneity in the interface. This behavior was associated to the local Schottky barrier lowering contribution due to the Ge-presence. These results can be useful to explore the possibility of controlling the contact (Schottky or Ohmic) properties by changing the size and the distribution of the surface impurities.
Electrical Characterization of Ni-Silicide Schottky Contacts on SiC for High Performance Temperature Sensor
Authors: Pascu Razvan , Pristavu Gheorghe , Brezeanu Gheorghe , Draghici Florin , Badila Marian , Rusu Ion , Craciunoiu Florea
Published: July 2015

The electrical behavior and stability of a temperature sensor based on 4H-SiC Schottky diodes using Ni2Si as Schottky contact, are investigated. The ideality factor and the barrier height were found to be strongly dependent on the post-annealing temperature of the Ni contact (which lead to the formation of Ni2Si). A nearly ideal Schottky device, with the barrier height approaching the high value of 1.7eV, and a slight temperature dependence, was obtained after an annealing at TA=800°C. This high barrier height proves that Ni2Si is suitable as Schottky contact for temperature sensors, able to reliably operate up to 450°C. Sensor sensitivity levels between 1.00mV/°C and 2.70 mV/°C have been achieved.
Evaluation of F-N Tunneling Emission Current in MOS Capacitor Fabricated on Step Bunching
Authors: Yamada Keiichi , Ishiyama Osamu , Sako Hideki , Senzaki Junji , Kitabatake Makoto
Published: July 2015

This work reports about influence of step bunching of SiC epitaxial-wafer surface on Fowler-Nordheim (F-N) tunneling emission current of SiC-MOS capacitor. We have measured the effective barrier height (ΦB) of SiO2/SiC interface, and estimated the deterioration factor of the effective ΦB on step bunching surface by calculating the local tunneling emission currents. Step bunching fluctuates the gate oxide thickness. The effective ΦB value can be successively derived using our proposed partitioned model in which constant ΦB value of flat surface is used. The fluctuation of the oxide film thickness results in the convergence of F-N tunneling emission currents at the thinner oxide in the MOS capacitor.
Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces
Authors: Mikhaylov A.I. , Afanasyev Alexey V. , Luchinin V.V. , Reshanov Sergey A. , Schöner Adolf , Knoll Lars , Minamisawa Renato Amaral , Alfieri Giovanni , Bartolf Holger
Published: July 2015

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.
Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation
Authors: Suvanam Sethu Saveda , Martin David M. , Zetterling Carl Mikael , Hallén Anders
Published: July 2015

In this paper effects of carbon (C), silicon (Si) and nitrogen (N) implantation on the interface properties of 4H-SiC/SiO2 and the implications for 4H-SiC bipolar junction transistors (BJT) passivation are discussed. 4H-SiC epi-layer have been implanted with 12C, 14N and 28Si ion at three different doses with energies of 3, 3.5 and 6 keV, respectively, resulting in a projected range of 8 nm for the three ions. Then metal oxide semiconductor (MOS) structures with SiO2 as dielectric have been fabricated. Capacitance voltage measurements show an increase in the negative fixed charges for all the implanted samples as a function of implantation induced damage. Similarly, in the case of C and Si, the surface roughness increases as a function of dose and the mass of the ions. No reduction of Dits due to the implantations is seen for any of the ions. Furthermore, TCAD device simulations of npn bipolar junction transistors (BJT), using the interface and fixed charges extracted from CV measurements, show a way to further optimize current gain and breakdown properties for the BJT.
Passivation of 4H-SiC/SiO2 Interface Traps by Oxidation of a Thin Silicon Nitride Layer
Authors: Mikhaylov A.I. , Afanasyev Alexey V. , Luchinin Victor V. , Reshanov Sergey A. , Schöner Adolf , Knoll Lars , Minamisawa Renato Amaral , Alfieri Giovanni , Bartolf Holger
Published: July 2015

The effect of the alternative nitridation process of the 4H-SiC/SiO2 interface by introduction of a thin silicon nitride layer on the electrical properties of the gate oxide has been investigated. C-V and G-V measurements on inversion-channel MOS devices revealed similar results to the conventional N2O oxidation. Higher field-effect mobility values are achieved due to lower interface roughness of the alternative nitridation process. However, insignificant degradation of the reliability was observed.
Removal of Mechanical-Polishing-Induced Surface Damages on 4H-SiC by Chemical Etching and its Effect on Subsequent Epitaxial Growth
Authors: Yao Yong Zhao , Ishikawa Yukari , Sugawara Yoshihiro , Sato Koji
Published: July 2015

To remove the surface damages induced during mechanical polishing (MP) of 4H-SiC, a variety of wet etching recipes and etching conditions were studied. By evaluating the epilayers grown on these etching-treated wafers, it has been found that triangular defects (TRDs) are the main defects originated from the MP-induced damages in these samples. High temperature molten KCl etching at 1100 °C with KOH additive is very effective to remove the damaged surface while keeping a relatively flat surface. Epilayer grown on the KCl+KOH etched wafer showed a TRD density <0.9 cm-2.
Effect of Surface Damage on SiC Wafer Shape
Authors: Moeggenborg Kevin , Kegg Thomas , Parfeniuk Christopher , Stoney Thomas , Quast Jeffrey
Published: July 2015

The flatness of a silicon carbide wafer in terms of bow and warp is the result of the combination of factors both material and process related. Sub-surface damage (SSD) from the wafering process steps can be considered as a thin film under compressive stress on the wafer surface. SSD is generally decreased with each subsequent processing step after the multiwire saw. Single-sided process steps can produce very different levels of SSD on opposing wafer surfaces, leading to high bow and warp values. The present study investigates the effects of SSD on wafer flatness at various process steps as well as methods to minimize shape effects due to SSD during and after processing.
Si1-xCx/Si(001) Heterostructures for Use in Schottky Diode Rectifiers Demonstrating High Breakdown Voltage and Negligible Leakage Current
Authors: Colston Gerard , Myronov Maksym , Rhead Stephen , Shah Vishal A. , Sharma Yogesh , Mawby Philip  Andrew , Leadley David
Published: July 2015

Vertical Schottky diodes have been fabricated on low C content Si1-xCx and 3C-SiC epilayers epitaxially grown on Si(001) substrates. Significant leakage current was observed in 3C-SiC diodes under reverse bias, masking any rectifying behavior. This issue is far less pronounced in Si1-xCx based Schottky diodes which demonstrate a clear critical breakdown. Leakage current is shown to be greater in relaxed Si1-xCx layers. While crystalline Si1-xCx is not currently a viable material for high power electronics it is useful for assessing the impact lattice mismatch and crystalline quality has on the behavior of rectifiers.
Fabrication and Application of 1.7KV SiC-Schottky Diodes
Authors: Chen Gang , Bai Song , Liu A. , Wang Lin , Huang Run Hua , Tao Yong Hong , Li Yun
Published: July 2015

High voltage 4H-SiC Ti Schottky junction barrier schottky (JBS) diode with breakdown voltage of 1700 V and forward current of 5 A has been fabricated. A low reverse leakage current below 3.8×10-5 A/cm2 at the bias voltage of -1700 V has been obtained. The forward on-state current was 5 A at VF= 1.7 V and 15.8 A at VF= 3 V. The active area is 1.5 mm × 1.5 mm. The turn-on voltage is about 0.9 V. The on-state resistance is 3.08 mΩ·cm2. The doping and thickness of the N-type drift layer and the device structure have been performed by numerical simulations. The SiC JBS devices have been fabricated and the processes were in detail. The die was assembled in a TO-220 package. The thickness of the N- epilayer is 17 µm, and the doping concentration is 3.2 × 1015cm−3. The number of floating guard p-rings was chosen to be 25, the distance between the rings was chosen to be 0.7 µm ~ 1.3 µm and the width of the p-rings is 2.5 µm. We use the PECVD SixNy/SiO2 as the passivation dielectric and a non photosensitive polyamide as the passivation in the end. The reverse recovery current Ir was 1.26A and the reverse recovery time Trr was 26ns when the diode was switched from 5A forward current to a reverse voltage of 700V. The reverse recovery electric charge Qrr of 16nC was obtained.
Temperature-Dependent Characteristics of 4H-SiC Buried Grid JBS Diodes
Authors: Lim Jang Kwon , Reshanov Sergey A. , Kaplan Wlodek , Zhang A. , Hjort Tomas , Schöner Adolf , Bakowski Mietek , Nee Hans Peter
Published: July 2015

4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased, which introduced a low channel resistance. By the encapsulation in TO-254 package, the forward voltage drop was decreased approximately 10% due to a lower contact resistance. The on-state resistance of the identical device measured on bare die and in TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to pure SBD and commercial JBS diodes.
Comparison of the Planar-JBS against the Trench-MOS Rectifier-Design Based on 4H-SiC for 3.3 kV Applications
Authors: Bartolf Holger
Published: July 2015

We compare the static electronic performance of the state-of-the-art Junction-Barrier-Schottky (JBS) rectifier (manufactured by ion-implantation) against the Trench-MOS Barrier Schottky (TMBS) rectifier (manufactured by trench-etching and subsequent oxidation). In our 2D numerical simulations, we have chosen identical specifications for the epitaxial drift-layer (3.3 kV application voltage, e.g. traction) and back-side device-design, while investigating the impact of the top-cell active area design on both rectifier IV-characteristics. To enable a meaningful comparison, we designed the depth d of the shields for the electric field E equally deep (p+ peak-plateau dJBS equals trench-depth dt), such that the peak E-field (close to avalanche breakdown) inside the drift-layer of the device is located at a comparable depth near the anode-side of the rectifier (see Fig. 2). By studying systematically the ratio between shield-to Schottky contact-length (w/s ratio), we found that the unipolar conduction state of the TMBS design is basically unaffected by enlarging the Schottky-contact length s, which is enterly different for the JBS-case.
A New 1200V SiC MPS Diode with Improved Performance and Ruggedness
Authors: Draghici Mihai , Rupp Roland , Gerlach Rolf , Zippelius Bernd
Published: July 2015

Infineon’s 5th Generation of 1200V SiC diodes uses a new compact chip design, realized by an optimized hexagonal merged-pn cell structure in the active area. This allows a higher n-doping in the epi layer due to improved E-field shielding resulting in a smaller differential resistance per chip area. Thanks to the merged-pn cell structure, depending on the diode ampere rating, a surge current capability now rated up to 14 times the nominal current ensures robust diode operation during surge current events in the application. The previous generations of 1200V SiC diodes could not make full use of the high breakdown field strength of the SiC material due to the instable avalanche which occurs at the edge termination only, and therefore, requiring a significant safety margin between rated voltage and breakdown voltage. Now the 5th Generation is designed in a way that each cell contributes to the avalanche, enabling a much more avalanche rugged device.
Thermal Simulation of Paralleled SiC PiN Diodes in a Module Designed for 6.5 kV/1 kA
Authors: Bayer Christoph Friedrich , Bär Eberhard , Kallinger Birgit , Berwian Patrick
Published: July 2015

This work shows thermal simulations of a package of 48/96 high-voltage (6.5 kV/1 kA) PiN diodes. A temperature dependent heat generation for a forward voltage of 3.6 V with a realistic heat generating volume in the diode of (2.7x2.7x0.01) mm3 was used. The thermal coupling of two diodes was determined to be less than 1 % for a distance between the diodes of 10 mm. The temperature distribution for the entire module has been studied for two different ceramic insulating materials, AlN and Al2O3, as well as for two numbers of diodes, 48 and 96. This led to a maximum temperature of 106 °C/118 °C (AlN, 48/96 diodes) and 123 °C/144 °C (Al2O3, 48/96 diodes). Assuming a constant applied voltage, a variance of ±0.5 V of the characteristic curve (forward voltage versus current) due to variations in the production process was considered fork single diodes. For a shift of +0.5 V for a single diode, the maximum temperature difference to the cooler temperature becomes approximately twice the original difference. Additionally, the operation under constant current (7.1 A, 10.2 A, 14.2 A) was studied including single diode failure. For single diode failure, the resulting change of the maximum temperature would be less than 3 %.
Analytical Prediction of the Cross-Over Point in the Temperature Coefficient of the Forward Characteristics of 4H−SiC p+−i−n Diodes
Authors: di Benedetto Luigi , Licciardo Gian Domenico , Bellone Salvatore , Nipoti Roberta
Published: July 2015

Forward JD–VD curves of 4H−SiC p−i−n diodes are analyzed by means of an analytical model in order to justify the presence of a crossing−point. The interlacing behaviour occurring in the JD–VD curves of 4H−SiC diodes at different temperatures is predicted by a simple formula, which can be used for a first-order design of such devices. Numerical simulation of diodes designed with different epilayer thickness and carrier lifetime values have been used in order to analyze the crossing−point behaviour. Comparisons with experimental data confirm the analytic and simulated results.
Observation of the Surface Morphology on the (0001)C Facet of 4H-SiC Boules
Authors: Yamaguchi Tomoki , Sato Shunsuke , Ohtani Noboru , Katsuno Masakazu , Fujimoto Tatsuo , Sato Shinya , Tsuge Hiroshi , Yano Takayuki
Published: July 2015

The surface morphology on the (000-1)C facet of 4H-SiC boules grown by the physical vapor transport method was examined in various scales (from millimeter to nanometer) using different types of microscopies such as differential interference contrast (DIC) optical microscopy and atomic force microscopy (AFM). The DIC optical microscope observation revealed that there exist three distinct morphological regions at the growth front of the 4H-SiC boules; they are facetted, non-facetted, and the intermediate region between them. The local inclination of the facet surface from the (000-1) basal plane increases toward the facet edge and then decreases over the intermediate region. AFM observations revealed characteristic step structures in these two regions and also that they are significantly influenced by nitrogen-doping. Based on the results, the formation mechanism of the facet morphology on 4H-SiC boules is discussed.
4H-SiC P+N UV Photodiodes for Space Applications
Authors: Berenguier B. , Ottaviani Laurent , Biondo Stéphane , Lazar Mihai , Milesi Frédéric , Palais Olivier , Torregrosa Frank , Lyoussi A. , Kalinina Evgenia V. , Lebedev A.
Published: July 2015

Spectral sensitivity measurements versus temperature have been carried out on irradiated SiC p+n photodiodes, fabricated using two different doping processes: Aluminium standard implantation and Boron plasma immersion ion implantation. The spectral sensitivity of Al doped photodiodes increase for incident wavelength higher than 270 nm, and are very stable below. Boron doped irradiated photodiodes show a general increase of the photoresponse for all wavelengths. In both cases, an hysteresis effect is observable when with the temperature. Results are presented and discussed.
The Impact of Interface Charge on the Breakdown Voltage of Terminated 4H-SiC Power Devices
Authors: Matsushima Hiroyuki , Okino Hiroyuki , Mochizuki Kazuhiro , Yamada Renichi
Published: July 2015

A novel method for analyzing a decrease in breakdown voltage (VBD) in the termination of 4H-SiC power devices after reverse-bias stressing on the basis of change in depletion-layer capacitance is proposed. Test PN diodes terminated with a junction-termination extension (JTE) were fabricated on n-type 4H-SiC and analyzed by I-V and C-V measurements. According to the results of the measurements, VBD after stressing decreases, and the capacitance of the test devices decreases after stressing. Measurements with different chip sizes but the same termination width show that the capacitance decrease occurs in the termination area. The simulated capacitance change, on the supposition that positive charge accumulated at the SiO2/SiC interface, and the measured capacitance change show the same tendency. These results indicate that the origin of VBD decrease is positive charge accumulated at the SiO2/SiC interface of the termination after reverse-bias stressing.
Robust Double-Ring Junction Termination Extension Design for High Voltage Power Semiconductor Devices Based on 4H-SiC
Authors: Hürner Andreas , di Benedetto Luigi , Erlbacher Tobias , Mitlehner Heinz , Bauer Anton J. , Frey Lothar
Published: July 2015

In this study, a new robust double-ring junction-termination-extension (DR-JTE) for high-voltage pn-diodes is presented and analyzed using numerical simulations. As figured out, the DR-JTE reduces the electrical field at both, the edge of the single-JTE region and the MESA-transition, respectively. Thereby, due to the reduction of the electrical field, the maximum breakdown voltage is increased to 91.5% of the theoretical, parallel-plane breakdown voltage of 6.5kVand the maximum acceptable deviation of the optimum implantations dose is twice than that of the single-JTE structure. Furthermore, due to the internal ring, the MESA-transition is shielded from the electrical field and therefore the breakdown voltage is much less affected by the angle of the MESA.
Instability of Critical Electric Field in Gate Oxide Film of Heavy Ion Irradiated SiC MOSFETs
Authors: Deki Manato , Makino Takahiro , Kojima Kazutoshi , Tomita Takuro , Ohshima Takeshi
Published: July 2015

The critical electric field (Ecr) of the gate oxide in 4H-Silicon Carbide (SiC) MOSFETs was measured under inversion bias conditions with ion irradiation. The Linear Energy Transfer (LET) dependence of the Ecr at which the gate oxide breakdown occurred in these MOSFETs was evaluated. The linear relationship between the Ecr-1 and LET was observed for SiC MOSFETs. The slope of the LET-1/Ecr for SiC MOSFETs is almost the same that of the LET-1/Ecr lines for SiC MOS capacitors. The Vds dependence of Ecr was also evaluated. The correlation between the direction of electric field of drain-source region and direction of ion incidence affects to instability of Ecr.
SiC MOSFETs in Hard-Switching Bidirectional DC/DC Converters
Authors: Heckel Thomas , Eckardt Bernd , März Martin , Frey Lothar
Published: July 2015

In this study, the necessity and beneficial characteristics of SiC power devices for novel power electronic applications are shown from an application point of view. The body diode properties of state of the art 1200 V SiC MOSFETs are discussed and the dependencies of switching speed are derived. Furthermore, the calculation of the fundamental efficiency limit of 99.67 % at the example of a bidirectional DC/DC converter operating at 100 kHz is shown.
Impact of Nitric Oxide Post Oxidation Anneal on the Bias Temperature Instability and the On-Resistance of 4H-SiC nMOSFETs
Authors: Rescher Gerald , Pobegen Gregor , Aichinger Thomas
Published: July 2015

We study the impact of different nitric oxide (NO) post oxidation annealing (POA) procedures on the on resistance Ron of n-channel MOSFETs and on the threshold voltage shift ∆Vth following positive bias temperature stress (PBTS). All samples were annealed in an NO containing atmosphere at various temperatures and times. A positive stress voltage of 30 V was chosen which corresponds to an electric field of about 4.3 MV/cm. The NO POA causes a decrease in overall ∆Vth for longer NO POA times and higher NO POA temperatures. As opposed to the change in ∆Vth, the device Ron increases with NO POA temperature and time.
Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides
Authors: Banzhaf Christian T. , Grieb Michael , Rambach Martin , Bauer Anton J. , Frey Lothar
Published: July 2015

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.
Quantitative Study of the Role of Supersaturation during Sublimation Growth on the Yield of 50 mm 3C-SiC
Authors: Rankl Dominik , Jokubavicius Valdas , Syväjärvi Mikael , Wellmann Peter J.
Published: July 2015

We have investigated the growth of 3C-SiC using sublimation growth in the temperature range from 1800°C to 1950°C. The supersaturation was determined using numerical modeling of the temperature field and gas phase composition by applying quasi-equilibrium thermodynamic conditions. Analysis of the 3C-SiC yield was carried out by optical microscopy, optical absorption, Raman spectroscopy and x-ray analysis. Quantitative data on supersaturation are compared with most stable 3C-SiC nucleation and growth condition. Finally the application to large area growth in a physical vapor transport growth reactor is briefly addressed.
Electrical Properties Evaluation on High Quality Hetero-Epitaxial 3C-SiC(001) for MOSFET Applications
Authors: Anzalone Ruggero , Privitera Stefania , Alberti Alessandra , Piluso Nicolo’ , Fiorenza Patrick , La Via Francesco
Published: July 2015

The effect of the crystal quality and surface morphology on the electrical properties of MOS capacitors has been studied in devices manufactured on 3C-SiC epitaxial layers grown on Silicon (100) substrate. The interface state density, which represents one of the most important parameters for the 3C-SiC MOSFET development, has been determined through capacitance measurements. A cross-correlation between High Resolution X-ray Diffraction, AFM analysis and electrical conductance measurements has allowed determining the relationship between the crystalline quality and the interface state density. By improving the crystalline quality, a decrease of the interface state density down to 1010 cm-2 eV-1 was observed.
Short-Circuit Capability Exploration of Silicon Carbide Devices
Authors: Berthou Maxime , Planson Dominique , Tournier Dominique
Published: July 2015

With the commercial availability of SiC power transistors, this decade will mark an important breakthrough in power transistor technology. However, in power electronic systems, disturbances may place them in short-circuit condition and little knowledge exist about their SC capability. This paper presents our study of SiC MOSFETs, JFETs and BJT under capacitive load short-circuit up to 600V.
Improvement of Current Gain and Breakdown Voltage in 4H-SiC BJTs Employing High-k Dielectric as an Interfacial Layer
Authors: Yuan Lei , Zhang Yu Ming , Song Qing Wen , Tang Xiao Yan , Zhang Yi Men
Published: July 2015

This paper proposes a new structure of 4H-SiC bipolar junction transistor, which can both achieve high current gain and high open base breakdown voltage. By introducing a groove type of metal-high k dielectric-silicon carbide (MIS) structure into the active region along the base-emitter sidewall which is formed with the process of isolation etching, a large electric field appears at the interface between high-k dielectric and bulk material by analyzing the potential distribution in forward mode, thus accelerating the electron transport. Based on a doping concentration of 4×1017cm-3 and thickness of 0.6um base region, current gain of as high as 191 is obtained using TCAD simulation, and that is almost double of the conventional structure in the same simulation setup. Furthermore, a field plate structure is composed combined with the base contact metal simultaneously, and the open base breakdown voltage is obviously increased from 634V to 948V with a 6μm-thick n-SiC collector (Nd=3×1015cm-3).
Development of a PSPICE Model for 1200 V/800 A SiC Bipolar Junction Transistor Power Module
Authors: Johannesson Daniel , Nawaz Muhammad
Published: July 2015

The characteristics of a 1200 V and 800 A bipolar junction transistor (BJT) power module has been measured, simulated and verified for the first time in the PSPICE platform. The simulation model is based on a silicon carbide (SiC) Gummel-Poon model for high power applications. The implemented model has been extended with temperature dependent equations in order to extend the BJT operating temperature range. PSPICE simulations are performed to extract technology dependent modeling parameters coupled with static and dynamic characteristics of BJTs at different temperatures and validated against the measured data. The performance of the SiC BJT model is fairly accurate and correlates well with the measured results over a wide temperature range.
4.5-kV 20-mΩ.cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension
Authors: Elahipanah Hossein , Salemi Arash , Zetterling Carl Mikael , Östling Mikael
Published: July 2015

A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.