bluuebunny/crossref_metadata_2025 huggingface dataset:
Current Status and Future Prospects of GaN HEMTs for High Power and High Frequency Applications
Authors: Kikkawa Toshihide , Kanamura Masahito , Ohki Toshihiro , Imanishi Kenji , Watanabe Keiji , Joshin Kazukiyo
Published: March 2013

In this paper, recent progress of GaN high electron mobility transistors (HEMTs) will be addressed. GaN HEMTs have been developed mainly for power amplifiers and power conversion units. For mass production, suppression of trapping phenomena, such as current collapse was required. Surface structures and GaN buffer layers are key features for controlling trap formation, resulting in long reliability. Drift phenomena which are critical characteristics for power amplifier were also investigated in detail. For power conversion, normally-off technology is essential. In this study, we developed the insulated-gate structure using atomic layer deposition.
Thermal Behavior of SiC Power Diodes
Authors: Millán José , Godignon Philippe , Jordà Xavier , Berthou Maxime , Banu Viorel
Published: March 2013

The electro-thermal characteristics of 1.2 kV SiC diodes are investigated in this paper. SBD and JBS diodes with different P+/N area ratio have been fabricated with Ti/Ni and Tungsten anode contact metals, which are able to work at high temperature (300ºC). Novel solutions are proposed for improving the thermal behavior of SiC JBS turn-off process, surge current and power cycling. Forward, reverse and switching characteristics are analyzed in the 25ºC-300ºC temperature range. Furthermore, to get SiC diodes able to operate up to 300ºC, different technological approaches have been considered, mainly concerning interconnection techniques and metallization layers to reduce the package thermal resistance. This work makes also a comparison of various interconnection techniques: Al wedge bonding on Al metallization, Au ball bonding on Au metallization and the press-pack encapsulations. The press-packaged SiC diodes are highly stable, showing no degradation after 650,000 power cycles.
Merits of Buried Grid Technology for SiC JBS Diodes
Authors: Bakowski Mietek , Lim Jang-Kwon , Kaplan Wlodek
Published: March 2013

SiC Schottky diodes for 250C operation have been developed and analysed. 2A and 10A, 1700V diodes use an implanted buried grid technology with epitaxial overgrowth. A dense grid from 1.5 to 6 µm have been investigated. 10A buried grid JBS diodes have leakage current at least three orders of magnitude lower compared to the commercial devices. The leakage current at 250C is comparable to that of the commercial devices at 175C. The analysis is supported by simulations.
Characterizations of GaN Films Grown on Si (111) Substrates with Various Growth Temperatures of Multiple AlN Buffer Layers
Authors: Tinh Tran Binh , Chang Yi Edward , Lin Kung Liang , Luong Tieng Tung , Yu Hung Wei , Huang Man Chi , Chung Chen Chen , Trinh Hai Dang , Nguyen Hong Quan , Nguyen Chi Lang , Luc Quang Ho
Published: March 2013

We present the effect of multiple AlN buffer layers on characterizations of GaN film quality, which includes a thin high-low-high- temperature (HLHT) AlN buffer layers. The study is based on two different thicknesses of the GaN films on the buffers and found that the HLHT AlN buffer layers could significantly affect on the GaN films qualities. The buffer plays a very important role for the growth of GaN film on Si (111) substrate. The GaN film with an uniformly faceted surface and very high quality has been obtained at the optimized multiple HLHT AlN buffer layers of 50-nm-thick at 1010-800-1010 0C.
(Invited) Ultra-Low Switching Power RRAM Using Hopping Conduction Mechanism
Authors: Chin Albert , Cheng C. H. , Chiu Y. C. , Zheng Z. W. , Liu Ming
Published: March 2013

Very low 0.4 pJ switching energy, fast 50 ns switching time, large >1E5 retention window at 85oC, and 1E6 cycling endurance were achieved in Ni/GeOx/SrTiOy/TaN RRAM. This RRAM device has negative temperature coefficient (TC) and ruled by bulk hopping conduction mechanism that lead to potentially better distribution. This is in sharp contrast to the positive TC and randomly distributed metallic filament RRAM. Such low switching energy is necessary for large-array NAND memory application, a unique merit of this RRAM device.
(Invited) Hafnium Oxide Based CMOS Compatible Ferroelectric Materials
Authors: Schroeder Uwe , Martin Dominik , Mueller Johannes , Yurchuk Ekatarina , Mueller Stefan , Adelmann Christoph , Schloesser Till , van Bentum Ralf , Mikolajick Thomas
Published: March 2013

The ferroelectric behavior of capacitors based on hafnium oxide dielectrics will be reported. Thin films of 6-30 nm thickness were found to exhibit ferroelectric polarization-voltage hysteresis loops when integrated into TiN-based metal-insulator-metal capacitors. A remanent polarization up to 25 µC/cm2 and a high coercive field of about 1 MV/cm was observed. Doping of HfO2 by different dopants with an atomic radius ranging from 110 nm (Si) to 188 nm (Gd) was evaluated and in all cases ferroelectric behavior was verified by P-V hysteresis, small signal capacitance-voltage, and for Si by piezoelectric measurements. Polarization retention showed no significant decay within a measurement range of up to two days.
Epitaxial Si and Gd2O3 Heterostructures - Distributed Bragg Reflectors with Stress Management Function for GaN on Si Light Emitting Devices
Authors: Dargis Rytis , Clark Andrew , Arkun Erdem , Roucka Radek , Williams David , Smith Robin S. , Lebby Michael
Published: March 2013

Tensile stress in GaN layers grown directly on Si is a serious obstacle for the implementation of this technology for electronic and photonic devices. The problem can be solved by stress engineering using epitaxial buffer layers grown on a Si-substrate. Heteroepitaxial Si and Gd2O3 multilayer structures that can be used both as a tensile strain compensating buffer for GaN epitaxial layers and an efficient reflector for light emitting devices are demonstrated in this work. A three-periods distributed Bragg reflector has been fabricated. It exhibits 82% reflectivity at the design wavelength of 450 nm. In situ curvature measurements of the 200 mm diameter wafers with the grown structure reveal compressive stress in the Gd2O3 -Si multilayer structure. The compressive stress compensates the tensile stress which arises during subsequent growth and cooling of the GaN layer.
Correlation between Electrical and Optical Properties of Tantalum Anodic Oxide and Electron Cyclotron Resonance Etching Studies of E-beam Deposited Ta2O5 Films
Authors: Kulpa Alina , Jaeger Nicholas A. F.
Published: March 2013

The anodicTa2O5 films were grown in 5ml/98%H2SO4 electrolyte. Discharge currents were collected immediately after growth. The optical properties were studied with a Spectroscopic Ellipsometer, over a wide range of frequencies from the UV to the IR. It was established that films for which the discharge current followed the known "~ -1" power dependence (characteristic of films that can sustain electric fields of MV/cm) have different optical properties as compared to films for which the discharge current is not represented by that function. Etching studies of the e-beam deposited Ta2O5 films, combined with reflectance measurements after each etch step, resulted in a shift in the reflectance spectrum as a function of film thickness, d. This empirical f versus d dependence (where f is the frequency corresponding to the reflectance minimum for each d) was used to calculate the energies of the 4d doublet of Ta+5 in Ta2O5.
Thiol-Ene Reaction Derived Sol-Gel Hybrid Dielectric Layer for Oragnic Thin Film Transistors
Authors: Kim Joon-Soo , Kim Yongho , Ko Ji-Hoon , Bae Byeong-Soo
Published: March 2013

Thiol-ene reaction derived dielectric layer, phenyl-sulfur-hybrimer(PSH) was synthesized by mercaptopropyl-phenyl-oligosiloxane(MPO) and phenyl-vinyl-oligosiloxane(PVO). These oligosiloxane was synthesized by sol-gel process. MPO is a result of non-hydrolytic sol-gel condensation between (3-mercaptopropyl)trimethoxysilane and diphenylsilanediol, and PVO is a result of non-hydrolitic sol-gel condensation between vinyltrimethoxysilane and diphenylsilanediol. In this work, the thiol-ene derived dielectric layer is applied to OTFT for the first time. It has relatively high dielectric constant (k=4.1) than silicon dioxide (k=3.9) which is generally used for dielectric layer and shows hysteresis-free behavior.
(Invited) III-V/Oxide Interfaces Investigated with Synchrotron Radiation Photoemission Spectroscopy
Authors: Tallarida Massimo , Adelmann C. , Delabie A. , Van Elshocht S. , Caymax Matty , Schmeisser Dieter
Published: March 2013

We used synchrotron radiation photoemission spectroscopy (SR-PES) to investigate the surface of GaAs and other III-V semiconductors after tri-methyl-aluminum (TMA) pulses performed at 250{degree sign}C. We observed the removal of native oxide and the growth of Al-oxide upon measuring the As3d, Ga3d, Al2p and VB spectra. After seven TMA pulses we performed one water pulse. As3d and Ga3d peaks showed almost no lineshape change, but a decrease of intensity due to the water adsorption. The valence band shows a change in the secondary electron cut-off and the decrease of work function. We conclude that water mostly adsorbs molecularly and induces the work function decrease. The molecular absorption of water indicates that the seven TMA pulses produce a passivated surface only partially terminated with OH groups.
(Invited) Surface Preparation and In/Ga Alloying Effects on InGaAs(001)-(2x4) Surfaces For ALD Gate Oxide Deposition
Authors: Edmonds Mary , Melitz Wilhelm , Kent Tyler J. , Chagarov Evgueni , Kummel Andrew C.
Published: March 2013

High resolution STM images of In0.53Ga0.47As(001)-(2x4) were obtained and surface defects were quantified as a function of sample preparation technique. Published STM images of InGaAs(001)-(2x4) samples of varying In composition were examined and missing dimer unit cells, adatom trough defects, and incomplete atomic terraces were quantified for comparison with the In0.53Ga0.47As(001)-(2x4) surface. Density Functional Theory (DFT) modeling of α2(2x4) and β2(2x4) unit cell constructions and electronic structures show that the missing dimer defect creates conduction band edge states not readily passivated by trimethy aluminum; therefore, the density of dimer defects may cause trap state formation at oxide/InGaAs(001) interfaces.
Effect of In0.53Ga0.47As Surface Nitridation on Electrical Characteristics of High-k/ Capacitors
Authors: Suzuki Yuya , Zadeh Daryoush H. , Kakushima Kuniyuki , Ahmet Parhat , Kataoka Yoshinori , Nishiyama Akira , Sugii Nobuyuki , Tsutsui Kazuo , Natori Kenji , Hattori Takeo , Iwai H.
Published: March 2013

InGaAs surface nitridation effect on La2O3/InGaAs interface has been investigated. It was found that by controlling nitridation conditions such as temperature interface quality can be improved. Also a new covalent structure based on nitridated Si and La2O3 is proposed to reduce dielectric and substrate intermixing, thus improving the high-k/InGaAs interface.
MOSFETs on InP Substrate with LaAlO3/HfO2 Bilayer of Different LaAlO3 Thickness and Single LaXAl1-XO Layer with Different La Doping Level
Authors: Wang Yanzhen , Chen Yen-Ting , Xue Fei , Zhou Fei , Chang Yao-Feng , Lee Jack C.
Published: March 2013

Electrical performances of HfO2-based InP metal-oxide-semiconductor field-effect-transistor (MOSFETs) with different thicknesses of LaAlO3 interfacial layer are compared. With 20Å LaAlO3/28Å HfO2, effective channel mobility increases by 40% and maximum drive current increases by 50% compared with MOSFETS with single 50Å HfO2. Also MOSFETs with single LaXAl1-XO of different La doping level (X =0.25, 0.33, 0.5, 0.67, 0.75) was fabricated. Maximum effective channel mobility of 704 cm2/Vs and maximum drive current of 27mA/mm are achieved in devices with LaXAl1-XO of 33% La doping level (W/L=600μm/20μm, EOT~2.7nm). These results suggest a tradeoff between the interface quality and bulk fixed charge for MOSFETs with LaXAl1-XO.
Interface Dipole Cancellation in SiO2/High-k/SiO2/Si Gate Stacks
Authors: Hibino Shinya , Nishimura Tomonori , Nagashio Kosuke , Kita K. , Toriumi Akira
Published: March 2013

Dipole layer formation at high-k/SiO2 interface is now recognized to be the dominant origin for threshold voltage (VTH) shift in metal gate high-k CMOS, though the dipole formation mechanism is still in debate. The dipole effect is practically used for VTH tuning in the band-edge metal/high-k gate stack CMOS. The optimum conditions might be found by changing the material and/or process conditions, but there is still a missing fact in the high-k/SiO2 dipole formation experiment. It is the dipole cancellation (counter dipole formation) in SiO2/high-k/SiO2/Si gate stacks. This paper reports experimental results on the counter dipole effect.
Investigation of Mg Diffusion in Ta(N) Based Electrodes on HfO2 for Sub-32nm CMOS Gate-Last Transistors
Authors: Gassilloud Rémy , Maunoury Cécile , Leroux Charles , Chevalier Pascal , Veillerot Marc , Dressler Cyril , Aussenac Francois , Martin Francois , Maitrejean Sylvain
Published: March 2013

Magnesium alloyed with Ta and TaN is investigated as possible gate electrode on HfO2 dielectric. When Mg is deposited on Ta, we observe TaMg alloy formation and HfO2 degradation induced by Mg annealed at 440{degree sign}C. When TaN is deposited on HfO2 prior to Mg, TaN acts as chemical barrier against Mg diffusion and minimizes direct reaction of Mg with HfO2. TaN controls the Mg diffusion through complex mechanisms. Beside, sub-stoichiometric TaNx electrode without any additive is stable on HfO2 at 440{degree sign}C, with N+ 4.3eV band-edge work-function. We discuss on the relevance to use low-work-function additive in refractory metal gate on HfO2 dielectric.
(Invited) Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-Design Approach
Authors: Gupta Sumeet Kumar , Roy Kaushik
Published: March 2013

We present device-circuit co-design techniques for FinFETs, based on spacer thickness optimization. We show that short channel effects in deeply scaled technologies can be mitigated by engineering the spacer thickness to introduce a gate underlap. FinFETs with symmetric and asymmetric gate underlap are presented and their device characteristics are analyzed. The implication of introducing underlap in FinFETs on circuit design is also discussed. We show that spacer thickness optimization leads to 86% lower leakage and 14% lower dynamic energy consumption with comparable performance. We also present the benefits of FinFETs with asymmetric gate underlap in mitigating the read-write conflict in 6T SRAMs. This technique enhances the read stability by 10% with only 3% lower write margin compared to standard FinFET SRAM. In addition, 58% reduction in leakage, 3% lower write time and 3% higher hold stability is achieved at the cost of 19% higher access time and 4% larger area.
Characterization of Stress Transfer from Process Induced Stressor Layer to Substrate in MOSFETs
Authors: Thomas Remi , Benoit Daniel , Pofelski Alexandre , Clement Laurent , Morin Pierre , Cooper David , Bertin François
Published: March 2013

The performance of electronic devices can be improved by applying stress to conduction channel to increase the carrier mobility. This can be achieved using contact etch stop layer (CESL). Its intrinsic stress is transmitted into the silicon substrate, inducing a strain in the conduction channel. This phenomenon results in an enhancement of about 8 % to 10 % of the channel electrical conductivity. Several techniques exist to characterize the stress. Currently, to obtain a high spatial resolution, the only possible solution to characterize the stress is to use TEM-based techniques. Dark-field electron holography has the advantage of producing strain maps that combine a nanometre-scale spatial resolution, a high sensitivity and a large field of view. As a consequence, this technique is employed in this paper to observe the deformation of silicon crystalline lattice in the transistor conduction channel.
(Invited) Si Nanowire Technology
Authors: Iwai H.
Published: March 2013

Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels. However, it is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into market, due to performance concerns - such as Ion/Ioff ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. We have conducted nano-CMOS studies in advance to provide possible solutions to the future expected problems. Si Nanowire FETs have been found to have very promising characteristics with high Ion/Ioff ratio and high drive current which could give them a strong foothold in the near future device structures.
(Invited) Fabrication of High-Quality GOI and SGOI Structures by Rapid Melt Growth Method - Novel Platform for High-Mobility Transistors and Photonic Devices -
Authors: Watanabe Heiji , Suzuki Yuichiro , Ogiwara Shimpei , Kataoka Nobuaki , Hashimoto Tatsuya , Hosoi Takuji , Shimura Takayoshi
Published: March 2013

High-quality germanium-on-insulator (GOI) and fully relaxed silicon germanium(SiGe)-on-insulator (SGOI) structures have been demonstrated by the rapid melt growth method. We successfully fabricated single-crystalline local GOI structures, that is, Ge wires over 100 um long within microcrucibles of a few um wide by means of lateral liquid phase epitaxy (lateral LPE). GOI MOSFETs produced by lateral LPE exhibited superior carrier mobility and on/off current ratio to those of conventional SOI devices, indicating excellent electrical properties of Ge-channel and MOS interface formed by LPE. Moreover, dislocation-free fully relaxed SiGe layers on SOI substrates were demonstrated by vertical LPE, in which crystallographic defects were found to be confined within the compositionally graded SiGe interlayer between the epitaxcially grown relaxed SiGe and SOI layers. These novel methods based on the rapid metal growth will open up a new pathway to realize platform for next-generation Ge-based high-mobility transistors and photonic devices.
A Study of Metal Gates on HfO2 Using Si Nanowire Field Effect Transistors as Platform
Authors: Li Qiliang , Zhu Hao , Yuan Hui , Kirillov Oleg , Ioannou Dimitris , Suehle John , Richter Curt A.
Published: March 2013

In this work, we present an experimental study on the effect of metal gates / high-k dielectrics stacks on threshold voltage and carrier mobility in nanowire field effect transistors. The difference between effective mobility and field effect mobility of nanowire FETs has been first demonstrated. The interface states and effective work functions of the engaged metals can also be extracted by studying various metal gates.
Local-Loading Effects for Pure-Boron-Layer Chemical-Vapor Deposition
Authors: Mohammadi Vahid , de Boer Wiebe , Scholtes Tom L.M. , Nanver Lis K.
Published: March 2013

The so-called local-loading effect is studied for pure boron (PureB) depositions from B2H6 in a chemical-vapor deposition (CVD) reactor. This effect occurs because the boron is not deposited on oxide and this increases the deposition rate (DR) of boron in open Si areas in the oxide. Experiments are performed for wide range of local-oxide ratio (LOR). Three regions can be distinguished. For LOR < 0.1 the oxide areas are too small to have any significant influence on the DR and for 0.1 < LOR < 1 the DR increases as the oxide area increases. An empirical model is developed to describe this behavior in the latter region and it is experimentally verified. This formulation can be used to model the lateral diffusion component of the boron atoms and to develop a comprehensive model to predict the PureB deposition rate on any 2-D uniform or non-uniformly patterned wafer. For LOR > 1, the experimental data deviates from the model, showing saturation of DR as the oxide area increases. In this region the gas phase diffusion of the boron atoms across the oxide is limited by their diffusion length. Conditions that allow reliable deposition of 2-nm-thick PureB layers are found.
(Invited) Hybrid-Formation of Ge-on-Insulator Structures on Si Platform by SiGe-Mixing-Triggered Rapid-Melting Growth --- A Road to Artificial Crystal ---
Authors: Miyao Masanobu , Kurosawa Masashi , Toko Kaoru , Tojo Yuki , Sadoh Taizoh
Published: March 2013

Single-crystal Ge layers on insulating films (GOI) are desired to achieve advanced 3-dimensional large-scale integrated circuits and high-performance thin-film transistors. We have developed the rapid-melting Ge growth seeded from Si substrates, which achieves chip-size (~cm length) GOI structures with (100), (110), and (111) orientations. Driving force to initiate the lateral growth over insulating films is clarified as the solidification temperature gradient originating from melting-induced Si-Ge mixing. Combination with the artificial Si micro-seed techniques and the rapid melting growth enables the formation of hybrid-orientation GOI arrays, i.e., (100), (110), and (111) stripes, on (100) Si platform. High hole mobility (~1000 cm2/Vs) in hybrid-orientation GOI is also demonstrated.
Low Temperature Fluorinated Silicon Films Synthesis
Authors: Milovzorov Dmitry Evgenyevich
Published: March 2013

The plasma-enhanced chemical vapor deposition (PECVD) at low temperature of preparation of fluorinated and hydrogenised nanocrystalline silicon films was studied by using Fourier-transform infrared spectroscopy and atomic-force microscopy. There are numerous molecular configurations are incorporated into silicon net. The silane molecule dissociates and SiH or SiH2 fragments are chemisorbed on substrate. By using the additional SiF4 there is etching on the surface, and SiF and SiF2 bonding are appeared on the film's surface. It is assumed that the hydrogen is incorporated in silicon net by low temperature (>100oC) and reacts with oxygen to produce the H4SiO4 assembly. By increasing in temperature of deposition the molecular creation and dissociation rates increase. By the same way the HF acid interacts with the SiF4 and produces H2SiF6. In addition, SiF4 react with H2O and are appeared H2SiF6 in silicon net, too.
Long-Range Interaction between H and (B, P, As, Sb) Dopant Atoms in Silicon Crystals Investigated by First Principles Calculation
Authors: Kamiyama Eiji , Sueoka Koji
Published: March 2013

The energy gain in Si crystal systems as a function of the distance between a hydrogen (H) atom and a boron (B), a phosphorus (P), an arsenic (As), an antimony (Sb) dopant atom was investigated using first principles calculation. The giving and taking of an electron between an H atom and a dopant atom was found to respectively result in a gain of about 0.98 eV (B), 0.67 eV (P), 0.66 eV (As), 0.74 eV (Sb), even when the atoms were fully separated and had no direct interactions. An ionized H atom in B-doped Si crystals always was found to exist at the bond-center site whether it was located near a B atom or not. H atoms in n-type Si crystals were found to be stable at tetrahedral sites except in the vicinity of a donor atom. In this vicinity, H atoms prefer to go into an anti-bonding site.
(Invited) Boron-Oxygen Related Lifetime Degradation in p-type and n-type Silicon
Authors: Voronkov Vladimir V , Falster Robert J , Lim Bianca , Schmidt Jan
Published: March 2013

Minority carrier lifetime degradation induced by illumination was studied in n-type Czochralski silicon co-doped with phosphorus and boron. The recombination centre that emerges during the degradation was found to be identical to the fast-stage centre (FRC) which is known for p-Si where it is produced at a rate proportional to the squared hole concentration, p2. In n-type material where holes are excess carriers of a relatively low concentration, the time scale of FRC generation in n-Si is increased by several orders of magnitude. The generation kinetics is non-linear as a result of the dependence of p on the concentration of FRC. This non-linearity is well reproduced by simulations. An analysis of the injection level dependence of the minority carrier lifetime shows that FRC exists in 3 charge states (-1, 0, +1) possessing 2 energy levels. The recombination is controlled by both levels. FRC is identified as a BsO2 complex of a substitutional boron and an oxygen dimer. The nature of the major lifetime-degrading centre in n-Si is thus different from that in p-Si - where the dominant one (a slow-stage centre, SRC) was found to be BiO2 - a complex involving an interstitial boron.
(Invited) The Impact of Oxide Precipitates on Minority Carrier Lifetime in Czochralski Silicon
Authors: Murphy John D , Bothe Karsten , Krain Rafael , Voronkov Vladimir V , Falster Robert J
Published: March 2013

Oxide precipitates form in silicon for microelectronic and photovoltaic applications, and act as strong recombination centres. We have measured the injection-dependence of minority carrier lifetime in ~50 samples from p-type and n-type Czochralski silicon wafers with a wide range of precipitate densities. We find that all the data can be parameterized in terms of two independent Shockley-Read-Hall centres. The first is at EV + 0.22eV, and has a capture coefficient for electrons 157 greater than that for holes. The second is at EC - 0.08eV and has a capture coefficient for holes ~1,200 greater than that for electrons. The density of the centres is approximately dependent on the precipitate concentration. The existence of dislocations and stacking faults around the precipitates increases the density of both centres.
Diode Characteristics and Thermal Donor Formation in Germanium-Doped Silicon Substrates
Authors: Rafi Joan Marc , Vanhellemont Jan , Simoen Eddy , Chen Jiahe , Zabala Miguel , Yang Deren
Published: March 2013

Germanium-doped silicon is studied actively for application in microelectronics, in particular, as an improvement of the radiation hardness of the silicon substrate can be achieved. However, the impact of the introduced germanium on the electrical stability and properties of the silicon material and devices is also of special concern. In this contribution we report the results of a study on the effects of low temperature thermal anneals relevant for backend processing, on the electrical characteristics of p-on-n diodes fabricated on Czochralski-grown (CZ) Ge-doped-Si with two different germanium concentrations (1•1019 cm-3 and 1.2•1020 cm-3), as well as on control CZ Si wafers without Ge doping. The results show good diode yield and uniformity, with little differences between the electrical characteristics of the fabricated diodes on the different substrates. However, interestingly for device applications, a significantly lower thermal donor generation (by one order of magnitude) is found for the case of the higher Ge-doped material subjected to 450ºC thermal anneals.
Radiation Influence on Biaxial+Uniaxial Strained Silicon MuGFETs
Authors: Bordallo Caio Cesar Mendes , Agopian Paula Ghedini Der , Martino Joao Antonio , Simoen Eddy , Claeys C.
Published: March 2013

In this work the effects of proton irradiation and mechanical stress on the off-state current of MuGFET devices are analyzed for different temperatures. Two different splits are evaluated: an unstrained and biaxial+uniaxial strained one. The off-state current grows with the stress effectiveness due to the GIDL increase and this off-current is even worse when these devices are submitted to proton irradiation due to the increase of the conduction through the back interface. The off-state current of irradiated strained devices reaches unacceptable values, in the range of 26µA at a temperature of 100ºC. The temperature has a strong influence on the off-state current since it impacts on both GIDL and back interface conduction.
Difficulties in Characterizing High-Resistivity Silicon
Authors: Nayak Pinakpani , Richert Ranko , Schroder Dieter K
Published: March 2013

High-resistivity silicon (HRS) plays an important role in modern telecommunication IC chips and HR Czochralski (CZ) crystals are gaining more importance. During our study of CZ-HRS wafers, both bulk and Silicon-On-Insulator (SOI), we observed it is not easy to use traditional characterization techniques such as capacitance-voltage (C-V) or resistivity measurement techniques on HRS. During C-V measurements using a Schottky contact directly on HRSOI film we observed a bias spreading effect, where the capacitance was much higher than that due to the gate area. Effects of various factors such as frequency, contact size, light, temperature, and annealing are discussed. The challenges in accurate resistivity measurement using four-point probe, Hall method, and C-V profile are highlighted and a new approach using Impedance Spectroscopy to extract resistivity is discussed.
(Invited) Defect Engineering at the Nanoscale: Challenges and Trends
Authors: Seebauer Edmund G , Gorai Prashun
Published: March 2013

Progression of Si-based device processing ever deeper into nanoscale dimensions is creating stiffer challenges for the control and manipulation of atomic-scale defects. For example, the increasing use of multiple chemical elements creates a much more complicated network of defect reactions. The growing surface-to-volume ratios that stem from device shrinkage accentuate the importance of defect interactions with surfaces and interfaces, even though the understanding of these interactions remains in embryonic stages. And previously unrecognized effects of temperature on defect creation during ion implantation, as well as of photostimulated defect diffusion during annealing, manifest themselves more clearly in the nanoscale regime. The present work briefly describes these phenomena, and makes the case that modeling of defect behavior through a combination of quantum calculations, molecular dynamics, Monte Carlo, and continuum simulations - coupled with appropriate experiments - has become ever more integral to effective defect engineering.
(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances
Authors: Polignano Maria Luisa , Mica Isabella , Carnevale Gianpietro P. , Mauri Aurelio , Bonera Emiliano , Speranza Serenella
Published: March 2013

This paper collects the results of some experiments aimed at investigating the physical mechanisms of defect generation in devices. It is shown that suitable limits for the mechanical stress can be defined to prevent defect generation. In addition, a high temperature stress release annealing can be beneficial for stress reduction and defect prevention. The annealing of implanted layers may result in crystal defect formation even with no contribution from mechanical stress. In this case, the silicon surface plays a relevant role in reducing the point defect concentration and hence the nucleation of extended defects. In the annealing process of high energy implantations, the most damaged region is far from the wafer surface. Under these conditions, impurities in the silicon substrate play a relevant role in determining the resulting defect morphology. The presence of interstitial oxygen forces defects to grow along <110> directions parallel to the silicon surface, thus preventing them to reach the device region.
Syntheses of a Variety of Silicide Nanowire and Nanosheet Bundles
Authors: Tatsuoka Hirokazu , Li Wen , Meng Erchao , Ishikawa Daisuke
Published: March 2013

A variety of nanostructured silicide bundles using abundant, non-toxic materials have been prepared. The CrSi2 nanowire, Mg2Si/MgO composite nanowire and Mg2Si nanowire bundles were synthesized using a Si substrate, a SiOx nanofiber bundle, and a Si nanowire array, respectively. The hexagonal MoSi2 nanosheet bundles were also synthesized using a MoS2 layered material as the template. The growth phenomena and the structural properties of the nanostructured materials have been investigated. In addition, the preparation of the CrSi2/SiOx radial nanowire structures is examined.
Bottom-up Process to Fabricate Periodic Arrays of β-FeSi2 Nanopillars for Photonic Applications
Authors: Kaneko Yasuyuki , Suzuki Motofumi , Nakajima Kaoru , Kimura Kenji
Published: March 2013

We propose a novel self-assembly process to fabricate periodic arrays of β-FeSi2 nanopillars for photonic applications. Self-assembled monolayers of polystyrene nanospheres (PSNSs) are coated with SiO2 by oblique evaporation at a deposition angle of 70{degree sign}. After the PSNSs are removed by annealing in air at 650 {degree sign}C, periodic arrays of SiO2 nanospherical crowns (NSCs) remain. On the NSC template, Si and Fe are deposited alternatively at a deposition angle of 80{degree sign} and a substrate temperature of 470 {degree sign}C. Due to the strong shadowing effect, non-close-packed nanopillar arrays of β-FeSi2 are successfully fabricated. Periodic arrays of β-FeSi2 are useful to manipulate thermal and/or solar radiation.
Synthesis and Photoelectrochemical Property of PbS Quantum Dots Modified WO3 Nanoflowers
Authors: Zhong Junwen , Li Xianchang , Hu Bin , Yuan Longyan , Feng Yutian , Li Tianqi , Song Ting , Hu Jiming , Zhou Jun
Published: March 2013

PbS quantum dots modified WO3 nanoflowers were synthesized on conductive glass through a low-temperature hydrothermal process and a dip coating method. The photoelectrochenical properties of the structure were intensively studied. The results indicated that the structures exhibited an excellent photoelectrochemical performance with a maximum photocurrent density of ~1.8 mA/cm2 and a maximum photoconversion efficiency of ~1.3% under solar light (AM 1.5, 100 mW/cm2) illumination, highlighting its enormous potential in hydrogen generation.
Photoacoustic Emission from Local Plasmon Resonators Nanostructured by Glancing Angle Deposition
Authors: Namura Kyoko , Suzuki Motofumi , Nakajima Kaoru , Kimura Kenji
Published: March 2013

We investigated thermal generation in Au nanoparticle array/dielectric layer/Ag mirror sandwiches, namely, local plasmon resonators, resulting from their local plasma resonance. The local plasmon resonator chips can be self-assembled using a dynamic oblique deposition technique. Because of the strong interference, the optical absorption of the chips we prepared is successfully controlled between 0.0% and 97% in the near-infrared region, by changing the thickness of the dielectric layer. To show the temporal controllability of heat generation, we performed photoacoustic measurements on the local plasmon resonator chips using the photoacoustic cell. The acoustic signal from the chips is much larger than that from either highly reflective Ag thin film or graphite. These features indicate that the local plasmon resonators are suitable for use as dynamically controllable nanoheaters.
Direct Growth of Au-Ga2O3 Core-Shell Nanowires and Their Field Emission Properties
Authors: Cheng Kai-Yuan , Hsu Chia Wei , Chou Li-Jen
Published: March 2013

A simple, direct synthesis method for the growth of Au-Ga2O3 core-shell nanowires was reported in the work. The uneven concentration of precursor in Au catalyst in the vapor-liquid-solid process was proposed to induce a different growth rate at the interface between substrate and catalyst. The as-synthesized nanostructures were investigated by the use of transmission electron microscope. The existence of ~10 nm Ga3O layer at the surface of Au tip was verified by high angle annular dark field images. The small electron affinity of the thin layer Ga3O results in a remarkably high field enhancement factor of ~1200, and a lower turn-on field of ~4.7 V um-1 in the field emission measurement. This simple approach and outstanding field emission performance promises future applications of core-shell nanowires in nanoelectronics and vacuum electronic.
Ultra-Compact Photonic Circuit Components based on Propagation of Exciton Polaritons in Organic Dye Nanofibers
Authors: Takazawa Ken , Inoue Jun-ichi , Mitsuishi Kazutaka
Published: March 2013

We fabricated a micron-sized ring resonator channel drop filter by micromanipulation of nanofibers of thiacyanine dye that propagate exciton polaritons along the fibers. The device consisted of a microring with a radius of r ≈ 4 μm and a straight nanofiber that functioned as an I/O bus channel. The performance of the device was evaluated using spatially resolved fluorescence microscopy. The device exhibited an extinction ratio of re = 2-4 dB for the visible wavelength region of 490-540 nm. Our results demonstrate that thiacyanine nanofibers are promising building blocks for exciton polariton-based photonic circuits, which can be highly miniaturized compared with conventional waveguide-based photonic circuits.
Near-Infrared Light Detection of n-Type β-FeSi2/Intrinsic Si/p-Type Si Heterojunction Photodiodes at Low Temperatures
Authors: Iwasaki Ryuhei , Yamashita Kyohei , Promros Nathaporn , Izumi Shota , Funasaki Suguru , Shaban Mahmoud , Yoshitake Tsuyoshi
Published: March 2013

n-Type β-FeSi2/intrinsic Si/p-type Si heterojunction photodiodes were prepared by facing-targets direct-current sputtering, and their near-infrared light detection performances were evaluated in the temperature range of 50 - 300 K. The rectification current ratio at bias voltages of {plus minus}1 V and the ratio of the photocurrent to the dark leakage current were remarkably enhanced with a decrease in the temperature. The detectivity at zero bias was estimated to be 3.8×109 cmHz1/2 /W at 300 K, and it was enhanced to be 8.9×1011 cmHz1/2/W at 50 K. It was demonstrated that β-FeSi2 is a potential material applicable to near-infrared photodetectors that are compatible with Si.
Visible Light-Induced Immobilization of Gold Nanoparticles on Silicon Substrates
Authors: Mo Shihang , Ichii Takashi , Murase Kuniaki , Sugimura Hiroyuki
Published: March 2013

Ordered and high-density AuNP structures were successfully immobilized on Si(111) substrates via a photochemical reaction, using the immersion method and the LB method, respectively. Because of partial oxidation of the substrate, island-like structures were formed using the immersion method. While that in the LB method, because AuNPs were immobilized in nitrogen atmosphere and not in liquid solution, oxidation was minimized thus a more compact structure was obtained. Furthermore, the plasmonic properties of the AuNP structure were found to be tunable by controlling the particle density and the interparticle distance.
Single-Nanowire CMOS Inverter Based on Ambipolar Si Nanowire FETs
Authors: Yuan Hui , Li Qiliang , Zhu Hao , Li Haitao , Ioannou Dimitris , Richter Curt A.
Published: March 2013

We have successfully fabricated an inverter based on ambipolar Si nanowire FETs. The inverter is consisted of two identical nanowire FETs on a single Si nanowire. The engaged FETs showed asymmetric ambipolar characteristics under positive and negative gate bias. A CMOS-like inverter can be realized on the single nanowire, where one of the devices behaves as an nMOSFET and the other behaves as a pMOSFET.
Transparent Conductive CNT/PMMA Nanocomposite Via Electrostatic Adsorption Technique
Authors: Muto Hiroyuki , Hakiri Norio , Phuc Nguyen H.H. , Kawamura Go , Matsuda Atsunori
Published: March 2013

We report a conductive nanocomposite prepared with single-wall carbon nanotubes (SWCNTs) and poly (methyl methacrylate) (PMMA). The fabrication of SWCNTs and PMMA was obtained via electrostatic adsorption technique with the usage of two kinds of polyelectrolytes, i.e. poly (sodium 4-styrene sulfonate) (PSS, Mw 70,000) and poly (diallyl dimethyl ammonium chloride) (PDDA, Mw 100,000 - 200,000), as biding agents between SWCTs and PMMA matrix particles. SWCNTs were homogeneously adsorbed on PMMA particles surface by proposed technique and the obtained composite has electrical resistivity of 3.5 Ω.m with 0.02% vol. of SWCNTs with optical transparency of 30%.
Synthesis, Characterization and Device Applications of InGaAs Nanowires
Authors: Hou Jared J. , Han Ning , Wang Fengyun , Yip SenPo , Xiu Fei , Hung TakFu , Ho Johnny Chung Yin
Published: March 2013

As a type of promising nanomaterials, semiconductor nanowires have been extensively studied in the past few years; however, the difficulty of synthesizing nanowires with desirable morphology and high crystal quality hinders the further development. In this study, we provide a simple two-step method to synthesize nanowires with smooth surface, excellent crystal quality and large processing window. These ternary InGaAs nanowires exhibit outstanding electrical performance with high Ion/Ioff ratio (~1E6) and electron mobility (~1300 cm2/Vs), which could be utilized in future integrated circuits.
Progress in Nonpolar and Semipolar GaN Materials and Devices
Authors: Kelchner Katherine M , Speck James S.
Published: March 2013

GaN and its alloys with InN and AlN have revolutionized the solid-state lighting market for their ability to emit a wide range of wavelengths in the visible spectrum. Development of GaN-based light emitting diodes (LEDs) and laser diodes (LDs) on the standard basal plane is challenged by the polar nature of the GaN wurtzite crystal structure, particularly for emission wavelengths beyond 500 nm, contributing to low efficiencies in this spectral region, known as the "green gap." Alternate crystal orientations of GaN offer reduced or no polarization, referred to as semipolar and nonpolar planes, they offer several benefits for light emitting applications. This talk outlines some of latest developments in material properties, growth issues and design considerations for GaN-based LED and LD devices on nonpolar and semipolar planes for visible wavelength applications.
Detection of Severe Acute Respiratory Syndrome (SARS) Coronavirus Nucleocapsid Protein Using AlGaN/GaN High Electron Mobility Transistors
Authors: Hsu You-Ren , Lee Geng-Yen , Chyi Jen-Inn , Chang Chung-ke , Huang Chih-Cheng , Hsu Chen-Pin , Huang Tai-huang , Ren Fan , Wang Yu-Lin
Published: March 2013

AlGaN/GaN high electron mobility transistors (HEMTs) were used to detect the SARS coronavirus (SARS-CoV) nucleocapsid protein interaction without fluorescent labeling. The detection limit in our system was approximately 0.003 nM of protein sample. Our result showed that this technique was more competitive than isotope-labeling EMSA. We demonstrated AlGaN/GaN was highly potential in constructing a semiconductor-based-sensor binding assay to extract the dissociation constants of nucleic acid-protein interaction.
Improved Hydrogen Sensing Performance of AlGaN/GaN Based Sensor with Platinum Nanonetworks
Authors: Kim Hyonwoong , Pearton S. J. , Ren Fan , Jang Soohwan
Published: March 2013

Platinum nanonetworks with 2~3 nm diameter were synthesized by a simple solution phase method, and applied to AlGaN/GaN based diode and HEMT for the hydrogen sensing. Uniformly distributed selective-area deposition of the Pt nanonetworks was achieved by the standard photoresist lift-off technique and spin coating method. Compared to conventional Pt thin film diode and HEMT sensors, the Pt nanonetwork sensors showed remarkably larger current changes for 4% H2 exposure, which resulted from the dissociating of larger amount of hydrogen molecules on the increased surface area of the Pt nanonetworks.
Oxide-Semiconductor-Based TFTs for Displays and Flexible Electronics
Authors: Lin Chang-Yu , Chien Chih-Wei , Wu Cheng-Han , Hsieh Hsing-Hung , Wu Chung-Chih , Yeh Yung-Hui , Cheng Chun-Cheng , Lai Chih-Ming , Yu Ming-Jiue , Leu Chyi-Ming , Lee Tzong-Ming
Published: March 2013

We report successful implementation of top-gate staggered a-IGZO TFTs with decent performance and environmental stability by adopting the SiOx/SiNx bi-layer gate-insulator stack. We successfully integrated the top-gate staggered a-IGZO TFTs into a working 2.2-inch AMOLED display panel, demonstrating the real use of the developed TFTs. We had also successfully implemented flexible top-gate staggered a-IGZO TFTs on colorless and transparent polyimide-based nanocomposite substrates using fully lithographic and etching processes that are compatible with existing TFT mass fabrication technologies. The TFTs showed decent performances (with mobility>10 cm2/V⋅s) either as fabricated or as de-bonded from the carrier glass. By bending the devices to different radii of curvature, influences of mechanical strains on characteristics of the flexible a-IGZO TFTs were also investigated.
CMOS-Compatible Precise Placement of Ge Quantum Dots for Nanoelectronic, Nanophotonic, and Energy Conversion Devices
Authors: Chen Inn-Hao , Chen Kuan-Hung , Wang Ching-Chi , Li Pei-Wen
Published: March 2013

We have developed a self-assembled CMOS compatible scheme for the generation of Ge QDs through thermal oxidation of Si1-xGex patterned structures as well as demonstrated precise QD placement by guiding Ge nucleus migration along the oxidation path and thus arranging them onto targeted locations where the ultimate oxidation occurs. Thereby a single QD self-aligned with electrodes through nanoscale tunnel barriers of SiO2/Si3N4 is realized for an effective management of single electron tunneling. On the other hand, using the fidelity of lithographic patterning and selective oxidation of SiGe pillars well-organized 3D stacked Ge QDs are precisely placed vertically and laterally, and the stacking number is managed by conditions of etching and layer deposition. Stacked QDs luminescence tunable over the visible and possess low thermal conductivity, showing promise for nanophotonic and energy conversion devices.
Mechanism that Dictates Pore Width and <111>A Pore Propagation in InP
Authors: Lynch Robert P , Quill Nathan , O'Dwyer Colm , Nakahara Shohei , Buckley Denis Noel
Published: March 2013

We report a mechanism for pore growth and propagation based on a three-step charge transfer model. The study is supported by electron microscopy analysis of highly doped n-InP samples anodised in aqueous KOH. The model and experimental data are used to explain propagation of pores of characteristic diameter preferentially along the <111>A directions. We also show evidence for deviation of pore growth from the <111>A directions and explain why such deviations should occur. The model is self-consistent and predicts how carrier concentration affects the internal dimensions of the porous structures.
Advanced Compound Semiconductor and Silicon Fabrication Techniques for Next-Generation Solar Power Systems
Authors: Nielson Gregory N. , Okandan Murat , Cruz-Campa Jose L. , Gupta Vipin P. , Resnick Paul J. , Sanchez Carlos A. , Paap Scott M. , Kim Bongsang , Sweatt William C. , Lentine Anthony L. , Cederberg Jeffrey G. , Tauke-Pedretti Anna , Jared Bradley H. , Anderson Benjamin J. , Biefeld Robert M. , Nelson Jeffrey S.
Published: March 2013

Microsystem technologies have the potential to significantly improve the performance, reduce the cost, and extend the capabilities of solar power systems. These benefits are possible due to a number of significant beneficial scaling effects within solar cells, modules, and systems that are manifested as the size of solar cells decrease to the sub-millimeter range. To exploit these benefits, we are using advanced fabrication techniques to create solar cells from a variety of compound semiconductors and silicon that have lateral dimensions of 250 - 1000 µm and are 1 - 20 µm thick. These fabrication techniques come out of relatively mature microsystem technologies such as integrated circuits (IC) and microelectromechanical systems (MEMS) which provide added supply chain and scale-up benefits compared to even incumbent PV technologies.