VECTOR-LOGIC FAULT SIMULATION
Authors: Hahanov V. I. , Chumachenko S. V. , Lytvynova E. I. , Khakhanova H. V. , Hahanov I. V. , Rozhnova T. G. , Obrizan V. I. 
Published: December 2024

Context. The technological trends of Design&Test computing for the IT industry and academic science are determined by the following directions: in-memory computing, immersive computing, AI computing, focused on energy saving and reduction of computing time when providing services. A mechanism for simulating faults as addresses on smart data structures is proposed, which eliminates the algorithm for simulating input test sets to obtain a test map for logic functionality. The proposed mechanism is focused on the service of SoC IP-cores under the control of the IEEE 1500 standard, which can be perceived positively by engineers in the EDA market.
Objective. The purpose of the research is time- and energy-saving mechanisms for simulating malfunctions, such as addresses, by using read-write transactions of in-memory computing to build a test map of any functionality on smart data structures.
Method. Smart data structures are represented by a logical vector and its derivatives in the form of truth tables and matrices. The test map is a matrix whose coordinates are determined by the combinations of all logical faults that are tested on the binary sets of the comprehensive test. The construction of the test map is focused on the architecture of in-memory computing based on read-write transactions, which makes the simulation mechanism economical in terms of simulation time and energy consumption due to the absence of a central processor. A logical vector as a single component of input data does not require synthesis into a technologically permitted structure of elements. Synthesis of smart data structures based on four matrix operations creates a fault test map like addresses for any logic.
Results. Deductive matrix vectors are effectively used to model faults as addresses in digital structures of any configuration, including convergent branches and feedback loops. The resulting test map is used to find the minimum fault-checking test of the input variables. The proposed fault simulation mechanism technologically easily fits into the architecture of in-memory computing and uses only read-write transactions. The vector logic engine can also be used to test graph structures that are described by a truth table or a logical vector. The truth table addresses used for fault simulation are effectively used for processorless processing of large data in the in-memory computing architecture.
Conclusions. Scientific novelty – a vector-logic in-memory computing mechanism for building a test map is proposed, characterized by the construction of intelligent data structures that reset the fault modeling algorithm. The proposed mechanism has no analogues in the design & test industry in terms of simplicity and predictability of data structure sizes and the absence of a test set modeling algorithm. The practical significance is determined by the application of the mechanism for testing logical functionalities of any complexity to solve verification tasks. Prospects of the research – increasing the object of diagnosis to the scheme, i.e. building a test map of the scheme logical structure.