(Invited) Heterogeneous Integration of Silicon CMOS Electronics and Compound Semiconductor Electronics for Miniature RF Photonic Transceivers
Authors: Nordquist Christopher D , Skogen Erik , Fortuna Seth , Hollowell Andrew E , Hemmady Caroline , Saugen Justine , Forbes Travis , Wood Michael G , Jordan Matthew , McClain Jaime , Lepkowski Stefan , Alford Charles , Peake Gregory , Pomerene Andrew , Long Christopher M , Serkland Darwin , Dean Kenneth A 
Published: December 2020

We are exploring heterogeneous integration (HI) for realizing transceivers that enable short-range and long-range RF photonic interconnect using wavelength-division multiplexing to aggregate RF signals, provide galvanic isolation, and reduce crosstalk and interference. The intimate integration of these functions will allow for higher signal density in congested volumes as well as reduced size weight and power (SWaP).

HI of silicon Complementary Metal-Oxide-Semiconductor (CMOS) electronics with compound semiconductor photonics enables high-performance microsystems that combine complex electronic functions with optoelectronic capabilities enabled by rich bandgap engineering opportunities. CMOS is an ideal technology for controlling and interfacing with optoelectronic circuits because of its maturity, accessibility through multiple foundries, and capability for a broad range of mixed-signal and RF functions. However, accessible state-of-the-art CMOS offerings do not include integrated photonic capability, and post-process monolithic integration of photonics is cost-prohibitive for all but the highest volume applications. For photonics, InP-based compound semiconductor technologies offer higher speeds than silicon photonic technologies plus the capability to exploit bandgap engineering to realize the monolithic integration of many functions including lasers, modulators, detectors, couplers, and filters. Unfortunately, compound semiconductor electronics offer poorer integration density and digital logic capabilities compared to CMOS, and monolithic integration of electronic and photonic functions in compound semiconductor technology is very complicated and has only been demonstrated in limited research environments. The differences in materials and processes between CMOS electronics and InP optoelectronics necessitates separate fabrication of the two technologies, followed by HI to achieve a microsystem that takes advantages of the capabilities of these two technologies.

In this work, we are comparing and evaluating approaches for integrating 180 nm CMOS RF interface circuits with planar InP photonic integrated circuits and surface-normal GaAs-based optoelectronics. To avoid the critical sub-micron alignment tolerances of optical interfaces, optical signals are constrained to the photonic chip and the interface between the two technologies is limited to electrical signals. Prototype RF electrical-optical transmitters and optical-electrical receivers are being fabricated using both wire-bond and flip-chip integration approaches, and the performance and SWaP benefits provided by HI are being evaluated.

In this HI application, the dissimilar materials and small CMOS die present challenges beyond that of either wafer-to-wafer bonding or standard chip-scale solder integration. To address a capability gap for high-density integration of CMOS die with Al pads obtained through multi-project-wafer runs, we are developing methods for adding appropriate under-bump-metallization and process bumps to the Al pads on single die. Flip-chip integration approaches being explored include solder ball scaling down to 75 µm pitch, as well as Cu pillars and Au microbumps with targeted pitches as low as 25 microns.

HI offers electrically short interconnects that do not require controlled impedance transmission lines and resistive load termination for high-speed data transfer. Controlled impedance routing with load termination is generally used for high-speed chip-to-chip interconnect because the pads and packaging add parasitic impedance, and the routing length is both uncontrolled by the chip designer and significant relative to an electrical wavelength. Using HI to control and minimize the inter-chip interface allows for electrically short interconnect with a significant power reduction for a given optical driver requirement. At frequencies well below cutoff with 1 Vpeak drive, modeling predicts that an unterminated link has negligible power consumption and 0 dB voltage loss, while a terminated link has 5 mW power consumption and 6 dB loss. For an unterminated link, simulations indicate that using a 25 micron-square bump instead of a 1 mm-long wire bond doubles the low-power bandwidth from 9 GHz to 18 GHz.

This presentation will cover the architecture and technical challenges of this HI activity, describe the constituent InP and CMOS technologies, provide updated results from wirebonded and flip-chipped test prototypes, and discuss future opportunities for scaling and improved performance.

Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia LLC, a wholly owned subsidiary of Honeywell International Inc. for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. SAND2020-5502A

Figure 1