bluuebunny/crossref_metadata_2025 huggingface dataset:
Impact of Ni Content on the Thermoelectric Properties of Half-Heusler Thermoelectrics
Authors: Tang Yinglu , Landmann Daniel , Battaglia Corsin
Published: February 2020

Motivated by high peak zT values reported 13 years ago for the (Ti,Zr,Hf)NiSn Half-Heusler system, Half-Heusler materials are identified as a promising materials class for thermoelectric applications. We investigate the TiNiSn sub-system, which does not rely on expensive Hf. From phase boundary mapping, we find that the thermoelectric TiNiSn Half-Heusler phase shows a narrow solubility range on the Ti-Ni-Sn phase diagram primarily in the range of excess Ni that can be approximated as TiNi1+xSn, where x is temperature dependent with 0 ≤ x ≤ 0.06 at 1223 K. Four phase boundary compositions with different Ni contents associated with four three-phase regions are identified. We characterize the thermoelectric properties of these stable compositions and find significant difference between Ni-rich and Ni-poor phase boundary compositions of TiNiSn, which amounts up to 41%, 58%, and 25% difference in Seebeck coefficient, lattice thermal conductivity, and thermoelectric figure of merit respectively. This explains the large discrepancy of literature data on the thermoelectric properties of TiNiSn within a unified phase diagram framework. We demonstrate that Ni-rich TiNiSn results in a narrower band gap using the Goldsmid formula, which we interpret to be due to the formation of an impurity band from interstitial Ni in the forbidden gap as previously suggested. Interstitial Ni atoms scatter both electrons and phonons, with the latter effect being much stronger, thus a lower lattice thermal conductivity compensates the decrease in electron mobility leading to a high zT value of 0.6 at 850 K for intrinsic Ni-rich TiNiSn. With Sb doping, the carrier concentration in these stable boundary compositions can be tuned but the distinct features in their transport properties remain unchanged. A maximum zT value of 0.6 was also achieved at 850 K for intrinsic Ni-poor TiNiSn upon Sb doping. We further present results on the integration of n-type TiNiSn Half-Heusler material into 36-legs modules in conjunction with p-type FeTiNb Half-Heusler material including their multi-physics modelling-assisted matching and integration into a heat exchanger mounted and tested in the exhaust gas system of a compact van.

Y. Tang, X. Li, L.H.J. Martin, E. Cuervo Reyes, T. Ivas, C. Leinenbach, S. Anand, M. Peters, G.J. Snyder, C. Battaglia, Energy & Environmental Science, 2018, 11, 311

D. Landmann, Y. Tang, D. Widner, R. Huber, P. Rickhaus, R. Widmer, C. Battaglia, in preparation
(Invited) Advances in Testing Inorganic & Hybrid Organic Thermoelectric Thin Films
Authors: Baumgart Helmut , Chen Xin , Linseis Vincent , Redel Engelbert , Reith Heiko
Published: February 2020

In this work, a novel Si-based Lab-on-a-Chip test platform is introduced to perform in-plane ZT measurements of various classes of thermoelectric films with a complete set of thermoelectric test structures. The electrical conductivity σ, the Seebeck coefficient S, the thermal conductivity κ, and the power factor PF and the figure of merit ZT values can be experimentally determined in a single simultaneous measurement run as a function of temperature. It is shown that this Lab-on-a-Chip test system can be applied to classic inorganic thermoelectric films such as PbTe and PbSe and also to hybrid inorganic-organic films such as SURMOF films and as well as to conducting organic PEDOT:PSS films. Generally, the thermoelectric film can be deposited in the exposed test area of the chip by using a shadow mask. All the parameters can be measured in the temperature range of 300 K to 370 K with a 1 T magnet field. Applications are demonstrated for all three film material categories. Here, PbTe and PbSe thin films and double-layer PbTe/PbSe films were synthesized by Atomic Layer Deposition (ALD) technology directly on the pre-structured Si chip. A thin Al2O3 protection and diffusion barrier layer was applied to avoid oxidation and degradation of PbTe/PbSe films. The Seebeck coefficient, electrical conductivity and thermal conductivity for PbTe, PbSe and double-layer PbTe/PbSe film were measured simultaneously by applying in-pane ZT chips. Furthermore, this Lab-on-a-Chip test system can be extended to Surface Anchored Metal-organic-framework (SURMOF) films, which consist of quasi-liquid phase epitaxially grown highly ordered crystalline films. MOF films are designed scaffold-like compounds that consist of metal ions connected by organic ligands. Furthermore, the example of a complete thermoelectric characterization of a conductive organic polymer thin film material will be discussed.
Electrodeposition in Supercritical Fluids
Authors: Black Alex , Bartlett Philip N. , Cook David Andrew , Reid Gill , Zhang Wenjian , Smith David Christopher , Alibouri Mehrdad
Published: February 2020

Supercritical fluids possess several characteristics which make them interesting for electrodeposition. Supercritical fluids have low viscosity, allowing fast mass transport and therefore rapid deposition. Additionally, adjusting the pressure and temperature influences the density and viscosity of the solvent, therefore allowing tuning of the solvent properties1 2. Low surface tension and phase separation also allows penetration of electrolyte into porous templates, meaning high aspect ratio nanowires can be deposited, with reported diameters as low as 3 nm3. This is a capability pertinent to the manufacture of the next generation of p-block based electronic devices, such as thermoelectric or phase change memory materials. As the current fabrication methods begin to reach their limits of size and control capabilities, extracting the maximum potential from these materials requires a new approach.

Where possible, aqueous conditions remain the most popular for electrodeposition, however its small cathodic limit can put refractory metals out of reach. Supercritical difluoromethane (scR32) is a promising solvent for supercritical electrodeposition. It has a large cathodic limit (-2 V), and a high enough dielectric constant to provide reasonable conductivity, and coordinates poorly with reagents1. Electrodeposition from scR32 has yielded films and nanowires of several p-block metals, including Te, Bi, Sb and Ge4-6. Extending this capability to alloys and compounds is the next challenge.

We present an introduction into the practical aspects of electrochemistry in supercritical fluids, often a non-trivial task. We will also present preliminary results concerning electrodeposition from a bismuth and tellurium electrolyte. The films produced were of varying, controlled composition. Bismuth telluride is a thermoelectric material, with the highest known room temperature thermoelectric figure of merit7, and is currently the subject of significant research efforts. The combination of supercritical fluids and electrodeposition holds significant promise for the fabrication of nanostructured materials.

This work has been supported by the EPSRC Programme Grant, Advanced Devices by Electroplating (EP/N0354371/1). Work from the EPSRC Programme Grant EP/I013394/1 also contributed.

1 Abbott A. P., Eardley C. A., Tooth R., J. Chem. Eng. Data, 1999, 44, 112

2 Abbott A. P., Hope E. G., Palmer D. J., Anal. Chem., 2005, 77, 6702

3 Ke J. et al., Phys. Chem. Chem. Phys., 2012, 14, 1517

4 Bartlett P. N. et al., Phys. Chem. Chem. Phys., 2014, 16, 9202

5 Bartlett P. N. et al., Chem. Eur. J, 2016, 22, 309

6 Bartlett P. N. et al., RSC Adv., 2017, 7, 40720

7 Rosi F., Abeles B., Jensen R., J. Phys. Chem. Solids, 1959, 10, 191

Figure 1
Change in Thermal Conductivity By Hydrogen Intercalation in Amorphous WO3 Film
Authors: Nakamura Ayano , Harada Shunta , Kobayashi Ryota , Tagawa Miho , Ujihara Toru
Published: February 2020

We are developing “thermal switching materials”, whose thermal conductivity varies over a wide range. It has a wide range of applications such as temperature controls, thermal energy storages and so on. WO3 is expected as a thermal switching material because the electrical conductivity of WO3 can widely change owing to the metal-insulator transition (MIT) caused by hydrogen interactions. Moreover, hydrogens can be intercalated into and deintercalated from WO3 film reversibly and quickly by an electrochemical reaction. Therefore, the thermal conductivity is expected to change reversibly. Here, we report the thermal conductivity changes in WO3 film associated with hydrogen intercalations.

WO3 film was prepared on ITO coated glass at room temperature by RF magnetron sputtering method in an Ar-O2 atmosphere. The total pressure and the oxygen content of the atmosphere were 4.0 Pa and 13%, respectively. The thickness of WO3 film was 0.7-1.4 μm. Hydrogen intercalations into WO3 film on ITO coated glass were performed in an 0.5 M H2SO4 electrolyte with a Pt counter electrode and a calomel reference electrode. The structure of the films was determined by x-ray diffraction analysis. The thermal diffusivity of the films was measured by an ac calorimetric method and the thermal conductivity was calculated by the differential method using measured thermal diffusivity. The electrical conductivity was measured by a four-point probe method.

X-ray diffraction measurements showed that the WO3 films were amorphous. The value of thermal conductivity decreased with increasing hydrogen content x in H
x
WO3, from x = 0 to x = 0.33, and the value of thermal conductivity increased markedly with increasing x above x = 0.33. The hydrogen content of x = 0.33 is close to that of MIT. On the other hand, the electrical conductivity after MIT was 1×105 times higher than that before MIT. However, a variation of the electron thermal conductivity given from the electrical conductivity by the Wiedemann-Franz law is much smaller than a variation of the thermal conductivity. Therefore, the lattice thermal conductivity is expected to contribute to a change in the thermal conductivity. Present results indicate that the thermal conductivity of WO3 film can be controlled by hydrogen intercalations and potentialize the hydrogen-induced active control of thermal switches.
Low Temperature Microwave Anneal in FinFET Fabrication
Authors: Kassim Joseph , Lee Rinus T.P. , Krishnan Rishikesh , Ferrer Domingo , Yang Jie , Shusterman Yuriy , Ramirez Isreal , Liu Huang , Lui Jinping , Krishnan Bharat
Published: February 2020

Low temperature anneal solutions are attractive for 7 nm CMOS transistor fabrication and beyond. This desire is necessitated by the introduction of new materials, novel integration flows and alternate device architectures that are incompatible with high temperature anneal solutions. Recently, microwave anneal has emerged as a potential approach for low temperature processing.

We have demonstrated an alternate low temperature anneal run path using microwave anneal for Titanium silicidation. The best in class microwave annealed split had matched contact resistivity and slightly improved device performance relative to the mSec annealed control wafer. HRTEM of both anneal processes revealed comparable silicidation.

Moreover, we demonstrated densification of FCVD grown oxide using low temperature microwave anneal. The wet etch rate ratio (WERR) achieved was comparable to that obtained from high temperature steam oxidation process. This low temperature process could be highly useful for fabrication of devices that use materials that suffer from unwanted diffusion, oxidization, and defects resulting from high temperature anneals.

Keywords—microwave, anneal, activation, trench, contacts, silicide, TiSi, FinFET, processes, materials.

Figure 1
(Invited) a Novel Metallization Process Using Slotogo As a Conducting Layer for HDI-Msap and Cu Pillar Applications
Authors: Yeh Ding-Chiang
Published: February 2020

With the demand of miniaturization, multifunction, and faster manufacturing for package substrates and the 3D packaging technology, fabricating high-density interconnection printed circuit boards (HDI PCBs) with a smaller line-space ratio becomes a challenging problem. There are several critical issues of conventional HDI-mSAP process: (1) Low thickness uniformity between the high-dense trace and the ground area. (2) Not only the planarity of the lines is greater than 20% but also voids and missing vias appear during copper via-filling plating. (3) It is not vialbe when line/space design is smaller than 30/30 um. On the other hand, copper (Cu) pillar bump seems promising in design for the next generation interconnections, there are still some issues such as low productivity, non-uniformity, and high energy consumption in manufacturing. Therefore, we developed SLOTOGO by using reduced Graphene Oxide (rGO) as a conducting layer to solve HDI-mSAP and Cu pillar problems.

In this study, the filling performance of micro via can get the extra-thin plated surface Cu by rGO special property in 3D narrow space. By modifying the mSAP process, two steps are needed for Cu plating: (1) via filling (2) pattern plating for line trace. By doing so, we can not only increase the via filling power to avoid the impurity of the residual dry film in the hole but also achieve the excellent planarity of the line by reverse pulse plating. Moreover, using rGO on pattern plating of Cu pillar also can improve the yield by using only 1/10 of the energy as opposed to the conventional process. Hence, with the SLOTOGO, the defects in conventional mSAP and Cu pillar process can be avoided and the manufacturing quality of HDI can be greatly improved.
The Stability of Cu Electroless Deposition Solution Employing Copper Nanoparticle As the Catalyst
Authors: Chen Yi-Ching , Dow Wei-Ping
Published: February 2020

Cu electroless deposition (ELD) technology has been widely used in the metallization of non-conductive materials, such as a printed circuit board (PCB) and polyimide film (PI). In the ELD process, industries use traditional Sn/Pd colloid as the catalyst to initiate the Cu ELD. However, palladium is an expensive noble metal. In addition, the residual palladium adsorbed on the resin surface has to be removed after copper patterning to prevent a possible short between two copper lines in the semi-additive process (SAP). This would increase the overall process cost. As a result, we use copper nanoparticle (CuNP) as the catalyst to initiate the Cu ELD on the resin surface and the sidewall of through holes of a PCB. In this work, the stability of the Cu ELD solution is important for industrial production. We select different chelators and reducers to study their effect on the stability of Cu ELD solution under the condition of using CuNP as the catalyst. The stability of the Cu ELD solution was characterized by UV-Vis spectroscopy and electrochemical analysis. The morphology of the ELD Cu layer was imaged by scanning electron microscope (SEM) and optical microscope (OM). Results show that the Cu ELD solution (i.e., formula) is different from that is formulated for Pd catalyst system.

Keywords:

Electroless copper deposition, Copper nanoparticle, Stability, Semi-additive process

Reference:

Kyung Ju Park, Hyo-Chol Koo, Taeho Lim,a Myung Jun Kim, Oh Joong Kwon, and Jae Jeong Kim, “Evaluation of Stability and Reactivity of Cu Electroless Deposition Solution by In-Situ Transmittance Measurement”, Journal of The Electrochemical Society, vol. 158, pp. D541-D545, 2011.

Fumihiro Inoue, Harold Philipsen, Alex Radisic, Silvia Armini, Yann Civale, Shoso Shingubara, and Peter Leunissena, “Electroless Copper Bath Stability Monitoring with UV-VIS Spectroscopy, pH, and Mixed Potential Measurements”, Journal of The Electrochemical Society, vol. 159, pp. D437-D441, 2012.
Copper Superfilling without a Copper Pad at the Microvia Bottom Due to Reduced Graphene Oxide (rGO) Coating
Authors: Yang Zong-Lin , Dow Wei-Ping
Published: February 2020

Reduced graphene oxide(rGO) has outstanding thermal and electrical conductivity. Compared to electroless (ELS)copper plating process, rGO grafting process is more environmentally friendly because ELS copper plating solution contains toxic species (i.e. formaldehyde as a reducer) and precious metal (i.e., Pd as a catalyst). rGO grafting process has less step than ELS deposition process, which makes it has a great prospect. Particularly, if the copper pad at microvia bottom was removed before the rGO grafting process and the sidewall and the bottom of the microvia were coated with rGO, the copper superfilling exhibited more excellent compared with ELS copper deposition process. This special process is related to the physical property of rGO. In other word, the issue of seam formation between the filled copper and the copper pad due to ELS deposition process is solved. Moreover, this approach also can be used to perform copper pillar plating, which exhibits excellent bottom-up deposition in the photoresistant hole. In this work, copper pad at the microvia bottom was removed by piranha solution at first. To enhance the filling performance, the effect of sonication in graphene oxide(GO)solution and plating time were discussed. In addition, the effect of the sidewall roughness of the microvia was evaluated to inference the exact nucleation position of plated copper the mechanism thereof. Result show that, the brand-new copper super-filling process was expected to replace the ELS copper deposition process in the future.

Keyword

Microvia, Electroplating, reduced Graphene Oxide, Copper superfilling

References
:

Pei, S. F.; Cheng, H. M., The reduction of graphene oxide. Carbon
2012,
50 (9), 3210-3228.

Chen, P. Y.; Sodhi, J.; Qiu, Y.; Valentin, T. M.; Steinberg, R. S.; Wang, Z. Y.; Hurt, R. H.; Wong, I. Y., Multiscale Graphene Topographies Programmed by Sequential Mechanical Deformation. Advanced Materials
2016,
28 (18), 3564-+.
Polymer and Bump Planarization for Fine Pitch Micro-Bump Stacking
Authors: Inoue Fumihiro , Derakhshandeh Jaber , Moeller Berthold , Gokita Yohei , Duval Fabrice , Bex Pieter , Capuz Giovanni , June Rebibis Kenneth , Miller Andy , Sleeckx Erik , Beyer Gerald , Beyne Eric
Published: February 2020

Advanced packaging, including fan-outs, 2.5D and 3D integration is gaining more interests as alternative driving force for performance improvement instead of scaling. A key element for the advanced packaging is interconnection technology between different chips. Flip chip micro-bumping enables electrical connection of different chips with shorter length than that of wire bonding. Although it is promising method for advanced packaging, there are several challenges need to be tackled to obtain robustness stacking below 10 μm pitch. For instance, the mechanical stability of micro-bumps become low due to the shape of the bumps. The bump height uniformity also becomes an issue when the pitches shrunk. In addition, the thermo-compression bonding (TCB) alignment and stacking will require incredibly high accuracy tool. In order to overcome these issues, alternative concept of flip chip bumping structures, which is embedded bump was introduced [1]. In this embedded bump concept, neither top nor bottom surfaces have topography, which improves the mechanical stability. In addition, it can be feasible in high-accuracy TCB process.

One of the challenge for this concept is to planarize Sn bumps and polymer. The well-known method for material planarization in CMOS technology is chemical mechanical polishing (CMP). However, optimization of polishing on soft adhesive polymer and metal Sn bump requires comprehensive CMP development. On the other hand, pure machining process such as flat milling has wider range of process window. Therefore, we are investigating to apply a single diamond flat milling process, so called surface planer, for this embedded bump concept. The surface planer process is able to mechanically remove polymer top surface and bumps by a diamond bit.

In the presentation, we will report characterization results of surface planer process for embedded bump concept. In addition, the stacking performance on 10 μm pitch bumps are shown. The middle images in the figure show that the planarized adhesive polymer and 10 μm pitch bump (top: schematic image, bottom: actual cross-sectional FIB image). The step height between bump and polymer is about 200 nm. By the planarization process, 10 μm pitch of Sn bumps can be connected by thermal compression bonding with minimum misalignment. By this feasibility study of polymer/bump planarization process, compatibility and challenges of embedded bump concept were laid out.

[1] Jaber derakhshandeh et al,” 3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects” ECTC2016

Figure 1
(Invited) Additive Impact on Cu Pillar Electrodeposition Process for Packaging Applications
Authors: Pokhrel Ravi , Lee Yil-Hak , Lee Won-Hyun , Woo Su-Han , Scalisi Mark , Kao Yu Hua , Gomez Luis , Lefebvre Mark , Prange Jonathan D , Thompson Kirk
Published: February 2020

The micro-electronics packaging industry is seeking new Cu electroplating products to achieve improved I/O density in chips and to enable a variety of packaging architectures. Solder-capped copper pillars are currently used as interconnects in advanced chip packaging. The technology trend is to utilize finer pitch size and smaller Cu pillar interconnects, thereby categorizing electroplated Cu pillars as standard pillars (20-75 µm feature sizes) and µ-pillars (<20 µm feature sizes). A new technology in chip packaging that allows multiple chip stacking to improve I/O density is the Fan-Out Wafer Level Packaging (FO-WLP) technology which also utilizes electroplated Cu pillars with dimensions in the order of 200 x 200 µm, also called mega pillars. Key performance metrics for µ-, standard, and mega Cu pillar products are their ability to plate Cu pillars with exceptional height uniformity along with the ability to maintain a void-free integration with the lead-free solder. For some Cu pillar applications, especially mega pillars, the industry is seeking Cu pillar products that can support very high electrodeposition rates in order to enable high wafer throughput. R&D efforts to develop new products that meet industry requirements in the Cu pillar technology space will be shared with a focus on the design and impact of additives in achieving these design goals.
Transition Layer Thickness Control in Additive-Assist Electroplated Nanotwin Copper
Authors: Chung Stream , Chen Yao-Tsung , Chen Zong-Cyuan
Published: February 2020

Unidirectional (111) nanotwin copper has shown exceptional performance such as thermal stability, mechanical strength, fatigueless behavior, electromigration resistance, electric conductivity, low bonding temperature, and ultra-large grain growth. These unique properties make it a promising solution to several IC applications including fine line RDL in fan-out WLP, copper direct bond in 3D IC vertical interconnect, high conductivity Cu interconnect for VLSI etc. Both electrochemical deposition and physical vapor deposition are able to form such microstructure, and electrochemical deposition is considered the suitable production method in terms of process flexibility, throughput, and overall cost. Direct current was successfully applied to nanotwin copper formation in many reports, but the common feature of these tests is using low or no acid electrolyte with pH around 1. This approach greatly hinders the industrial implementation because of poor deposit uniformity from low electrolyte conductivity. Pulse plating with low duty cycle was also tried, and able to produce nanotwin in high acid electrolyte. However, throughput and hardware cost are the downside of this method. Another approach is DC plating with additives of crystal plane adsorption selectivity, and then electrolyte acid concentration over 100g/L could be used to form nanotwin copper. During the preferred orientation grain development, a micrometer transition layer between non-nanotwin substrate and columnar nanotwin grain is formed. The transition layer thickness is found sensitive to substrate copper grain orientation as well as electrolyte acid concentration, and may dominate the material property when overall deposition thickness reduces in fine line RDL application. In order to reduce the transition layer thickness, two additive modification approaches are demonstrated in this paper. The first one is to increase columnar grain nucleation density by reducing nucleation overpotential, and the second one is to increase lateral grain growth rate by increasing nucleation overpotential. The prior approach results in smaller columnar grain diameter, and the later one results in larger columnar grain diameter. Both approaches are effective in reducing transition layer thickness.

Figure Caption: Transition layer boundary represented by green dash line on TiW/Cu substrate. (a) thick, irregular transition layer with nt-Cu additive. (b) thin transition layer with modified nt-Cu additive increasing substrate nucleation sites.

Figure 1
Process Optimization of through Silicon Vias Metallization Using Reduced Graphene Oxide As a Conductive Layer
Authors: Geng Hong-Jyun , Dow Wei-Ping
Published: February 2020

Three-dimensional (3D) IC chip stacking has been proposed for a long time. An interposer designed between two chips for interconnection [i.e., through silicon vias (TSVs)] is a bridge for vertical signal transmission. Recently, reduced Graphene Oxide (rGO) has also been developed because it not only is a good conductor, but also it can be grafted onto the surface of many substrates and makes them be conductive through rGO grafting process. TSV is a silicon-based substrate, so self-assembled monolayer (SAM) of amino-silane is usually used as an adhesive layer in the rGO grafting process, and it can form a thin film with positive charges, which can adsorb the functional groups of GO sheets due to charge attraction. After GO is grafted onto the surface, a chemical reducer is used to reduce the grafted GO to rGO. However, silane must be dissolved in an organic solvent for stabilization. Otherwise, it easily forms “islands” on the surface, which then cause non-uniform and discontinuous rGO film. In this work, deionized water was employed to replace the organic solvent to dissolve the amino-silane. Effects of operating parameters, surface treatments and modifications on rGO grafting performance were investigated to improve the uniformity and continuity of the grafted rGO using several analysis methods and instruments, like water contact angle, atomic force microscopy(AFM) and conductive atomic force microscopy(C-AFM), etc. Cross-section images of TSVs after copper and cobalt electroplating were also used to evaluate the filling performance and uniformity. Eventually, a stable and optimized aqueous rGO grafting process is developed and can be used as a conducting layer of TSV for copper and cobalt superfilling.

Keywords:

Through Silicon Via, Electroplating, reduced Graphene Oxide, 3D IC

Reference:

Songfeng, and C. Hui-Ming, “The Reduction of Graphene oxide ”, Carbon., 2012, 50, 3210-3228.

Figure1. Scheme of the rGO grafting process. TSV was immersed in Beaker A for surface pre-treatment, surface modification with amino-silane was carried out in Beaker B, the GO grafting step was performed in Beaker C, and GO reduction was conducted in Beaker D.

Figure 1
Process Optimization for Electron Down-Flow Electromigration Improvement in Copper Interconnects
Authors: Cheng Yi-Lung , Lee Chih-Yen
Published: February 2020

Due to asymmetric structure of Copper (Cu) interconnects, Cu electromigration (EM) is related to the electron flow direction. In various technological nodes, Cu EM performance with electron down-flow direction is generally worse than that with electron up-flow direction due to the presence of voiding underneath the via. This study investigates Cu EM behavior with electron down-flow. The failure modes were verified and optimized processes were provided to improve EM performance. Additionally, layout geometry effect on electron down-flow EM was discussed.
Hybrid Heterostructure (1T/2H) MoS2/α-MoO3 Nanoflowers Toward Superior Dye Adsorbent and Electrocatalyst for Hydrogen Evolution Reaction
Authors: Manikandan Arumugam , Ilango P.Robert , Chen Chia-Wei , Wang Yi-Chung , Shih Yu-Chuan , Lee Ling , Chueh Yu-Lun
Published: February 2020

Finding a low-cost material with properties that satisfy the requirement of energy crises and a cleaner environment is imperative. In this work, by employing a one-step hydrothermal method, we demonstrate the successful synthesis of a phase-engineered (1T/2H) MoS2/α-MoO3 heterostructure nanoflower at a temperature of 200°C. We tuned the 1T-rich phase of MoS2 to the 2H-rich phase by optimizing the synthesis time. Additionally, the morphology and crystallinity of the as-prepared samples were characterized through scanning electron microscopy, X-ray diffraction, and high-resolution transmission electron microscopy. The MoS2 phase and the presence of α-MoO3 were analyzed through Raman and X-ray photoemission spectroscopy. The sample prepared at 16 h attained a high surface area of 37.97 m2g−1, and 97% of the RhB dye with the initial concentration of 47.9 mg L−1 was removed within 10 min through adsorption; this is the highest known removal efficiency reported in the literature. As a hydrogen evolution reaction (HER) electrocatalyst in an acidic solution, the sample prepared at 12 h exhibited highly efficient catalytic action by achieving a lower overpotential of 232 mV at a current density of 10 mA cm−2, which is comparable with previously reported HER catalysts based on MoS2. Moreover, this sample reached a lower Tafel slope of 81 mV dec−1 and was stable over 1000 cycles. This superior dye degradation ability and these highly efficient electrocatalytic properties are attributable to the heterostructure nanoflower morphology.
(Invited) Deep-Level Analysis of Passivation of Transition Metal Impurities in Silicon
Authors: Mullins J. , Markevich Vladimir , Leonard S. , Halsall M.P. , Peaker A.R.
Published: February 2020

Experimental results on the interactions of transition metal (TM) impurities with hydrogen and on passivation by the displacement of the metals from interstitial to substitutional sites in crystalline silicon will be presented in this talk. Iron, titanium and vanadium from the 3d series, and Zr and Mo from the 4d series have been studied. The results have been obtained by means of deep level transient spectroscopy (DLTS), high resolution Laplace DLTS, minority carrier transient spectroscopy and secondary ion mass spectroscopy.

The 3d metals are the most important TM series in relation to recombination in silicon. The most recombination active site is with the 3d metal in an interstitial position. It is found that in the presence of excess vacancies 3d TMs tend to move to substitutional sites and are quite stable in this position with no or much reduced recombination activity and much reduced diffusion.

The experimental results on passivation of TMs with hydrogen show that in general the reactions of H atoms with TM impurities are much more effective in n-type material than in p-type Si. These findings can be easily explained considering charge states of the interacting species. Essentially the initial H-TM reaction is driven coulombically at equilibrium conditions. We have managed to promote reactions of hydrogen atoms with Fe, Mo and V impurities in p-type silicon by changing charge states of the interacting defects either by shifting the Fermi level upon the application of reverse bias to Schottky barrier diodes or by illumination of the contaminated and hydrogenated Si samples with the use of light emitting diodes with photon energies above the Si band gap energy.

It has been found that the binding of hydrogen to the metal atoms, in all cases we have examined, is rather weak … of the order of 2 eV. This implies that the passivated fraction of the TMs resulting from the reaction of hydrogen with metals in bulk silicon is diminishingly small at device processing temperatures.

Based on the results obtained we try to understand some of the previously published data on lifetime improvement in Si crystals by hydrogenation. In some of the commercially important cases, particularly those reporting on multi-crystalline slices, this is far from simple as other important effects such as enhanced diffusion, precipitation and gettering can take place during hydrogenation simultaneously with hydrogen-metal reactions. It appears that in some cases hydrogen-metal reactions does not seem to be the most important processes in enhancing the minority carrier lifetime of the silicon.
(Invited) Dual-Gate and Gate-All-Around Polycrystalline Silicon Nanowires Field Effect Transistors: Simulation and Characterization
Authors: Salaun Anne-Claire , Le Borgne Brice , Pichon Laurent
Published: February 2020

The need of miniaturization following Moore’s law has intensified research efforts on silicon nanostructures such as nanowires or nanoribbons that can be used as active part of electronic nano-devices. In this way, nanowires offer great potential as field effect transistors channel region for ultra large scale integration electronics, and also as sensitive units for the detection of charged biochemical species for sensors on CMOS platforms. Top-down approach favors patterning architectures in a planar layout, most of the SiNWs are patterned on high cost silicon-on-insulator substrates (SOI). Polycrystalline silicon SiNWs (poly-SiNWs) synthesis using sidewall spacer top down method seems to be a lower cost alternative, fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. In such new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allow a better electrostatic gate control.

In our study, nanowires are elaborated using a classical fabrication method commonly used in microelectronic industry: the sidewall spacer formation technique. Assets of this technological process rest on the use of low cost lithographic tools, and the possibility to get by direct patterning numerous parallel nanowires with precise location on the substrate. We develop a low temperature (≤ 600°C) fabrication process of top-gate, bottom-gate and GAA FETs. Independent biasing of each gate allows a possible threshold voltage control of these bottom gate (BGT), top gate transistors (TGT) and GAA architecture. Electrical performances are analyzed as a function of the density of state highlighting oxide/semiconducting nanowire interfaces difference in top and bottom gate configurations. Applications for chemical and biochemical species sensing have also been investigated.
Channel-Length Dependent Performance Degradation of Thermally Stressed IGZO TFTs
Authors: Kabir Muhammad Salahuddin , Ganesh Prashant , Chowdhury Rahnuma Rifat , Sethupathi Harithshanmaa , Okvath Julia , Konowitch Jason , Manley Robert G. , Hirschman Karl D
Published: February 2020

The focus of this work is on the performance degradation of thermally stressed IGZO TFTs with SiO2 for both the gate dielectric and back-channel passivation material. The TFT fabrication process included a post-passivation 400 °C O2 anneal to adjust the IGZO semiconductor properties. I-V characteristics of TFTs with bottom-gate (BG) and double-gate (DG) electrode configurations were observed to left-shift and degrade with 200 °C hotplate treatments as shown in Fig. 1. The mechanism causing the instability is not completely understood, however experimental results indicate the instability occurs either directly or indirectly due to the influence of H2O within the passivation oxide above the IGZO channel region. The instability of DG devices was consistently more pronounced, suggesting a reaction between H2O and the aluminum top-gate electrode resulting in the liberation of monatomic hydrogen. This interpretation is supported by complementary experiments on MOS capacitors fabricated on bulk silicon substrates. The application of an alumina capping layer deposited by atomic layer deposition (ALD) was successful in improving thermal stability, with representative results shown in Fig. 2.

While most BG capped devices remained stable over several successive thermal treatments, DG devices demonstrated the onset of degradation with noted variation in both the time required and occurrence frequency. The analysis revealed an unanticipated dependence on channel length, with long-channel devices (L = 48 µm) being much more prone to an early onset of degradation compared to shorter devices (L = 12 µm) as shown in Fig. 2. With H2O remaining as the expected origin of thermal instability, a hypothesis has been developed to explain the observed channel length dependence. The results are consistent with the molybdenum source/drain contact regions acting as gettering sites for H2O molecules during the 400 °C annealing process. The removal of H2O from the back-channel region is a two dimensional process limited by the diffusivity of water, with the process more complete in short channel devices. Remaining H2O molecules at or near the back-channel interface in long-channel devices are able to migrate during thermal stress treatments, establishing complete coverage on devices that experience degradation. Experiments which explore the addition of getter features on or adjacent to the back-channel region, as illustrated in Fig. 3, in addition to localized materials analysis techniques such as secondary ion mass spectroscopy (SIMS) will provide additional evidence either in support or denial of the proposed hypothesis.

Figure 1
(Invited) Multi-Terminal Oxide-based Electric-Double-Layer Thin-Film Transistors for Neuromorphic Systems
Authors: He Yongli , Wan Qing
Published: February 2020

Our brain is a highly parallel, energy efficient and event-driven information processing system, which is fundamentally different from traditional von Neumann computers. Neuron is the most important building block, and information processing in individual neuron involves the transformation of input synaptic spike train into an appropriate output spike train. Inspired by biological neural computing, neuromorphic systems may open up new paradigms to deal with complicated problems such as pattern recognition, classification and decision making. The idea of building brain-inspired adaptive artificial devices has been around for decades, and hardware implementation of neuron by individual ionic/electronic hybrid device is of great significance for enhancing our understanding of the brain and solving sensory processing and complex recognition tasks. Although two-terminal memristors can performe some basic synaptic and neural functions, our human brain contains many more synapses than neurons. This fact suggests that multi-terminal devices are more favorable for complex neural nwtwork emulation. In recent years, multi-terminal electric-double-layer (EDL) Thin-film transistors (TFTs) based on interfacial ion-modulation have attracted significant attention in mimicking synaptic dynamic plasticity and neural functions. Here, we provide the proof-of-principle artificial synapses/neurons based on solid electrolytes coupled oxide-based EDL TFTs with multiple driving and modulatory inputs terminals. Paired-pulse facilitation, dendritic integration and orientation tuning were successfully emulated. Additionally, neuronal gain control (arithmetic) in the scheme of rate coding is also experimentally demonstrated. Our results provide a new-concept approach for building brain-like cognitive systems.

References

[1] Feng Shao, Changjin Wan, Ping Feng, Xiang Wan, Yi Yang, Liqiang Zhu, Yi Shi, and Qing Wan*, “Multifunctional Logic Demonstrated in a Flexible Multi-Gate Oxide-based Electric-Double-Layer Transistor on Paper Substrate”, Advanced Electronic Materials. 3, 1600509, (2017).

[2] Changjin Wan, Liqiang Zhu, Yanghui Liu, Ping Feng, Zhaoping Liu, Hailiang Cao, Peng Xiao, Yi Shi, and Qing Wan*, “Proton Conducting Graphene Oxide Coupled Neuron Transistors for Brain-Inspired Cognitive Systems”. Advanced Materials. 28, 3557 (2016).

[3] Xiang Wan, Yi Yang, Yongli He, Ping Feng, Wenjun Li, and Qing Wan*, “Neuromorphic Simulation of Proton Conductors Laterally Coupled Oxide-based Transistors with Multiple In-Plane Gates”, IEEE Electron Device Letters. 38, 525-528 (2017).

[4] Liqiang Zhu, Changjin Wan, Liqiang Guo, Yi Shi, and Qing Wan*. “Artificial Synapse Network on Inorganic Proton Conductor for Neuromorphic Systems” Nature Communications, 5. 3158 (2014).

[5] Jie Jiang, Qing Wan*, Jia Sun, and Aixia Lu, “Ultralow-voltage transparent electric-double-layer thin-film transistors processed at room-temperature”, Applied Physics Letters.95, 152114 (2009)

Figure 1
(Invited) Inside of 10 Nm Technology Node
Authors: Chen JC
Published: February 2020

In this paper, material analysis on two CPUs with 10 nm technology node from most advanced mobile phones (iPhone and Samsung) in the market has been delivered. With the help of high spatial resolution transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS), details of processes can be clearly unveiled and analyzed. For Samsung, Exynos8895 has a higher fin height and broader fin width, tsmc, A11, on the other hand, has shorter fin pitch and thinner interconnection thickness. More detailed differences between these two chips will be presented.
(Invited) Whirligig-Inspired Triboelectric Nanogenerator with Ultrahigh Specific Output As Reliable Portable Instant Power Supply for Personal Health Monitoring Devices
Authors: Yeh Min-Hsin , Ho Kuo-Chuan , Guo Hengyu , Hu Chenguo
Published: February 2020

With lightweight, high energy conversion and low cost, the triboelectric nanogenerators (TENGs) have presented its tremendous potential as a portable sustainable power source to small-scale portable/wearable electronic device. However, the insufficient output power of TENG is a bottleneck for its practical applications. Here, we report an ultrahigh output power, a whirligig-inspired TENG (Wi-TENG) designed according to an antique whirligig toy that is capable of converting low-frequency pulling motion into a high-frequency rotation. It shows that the rotor in the Wi-TENG achieves a maximum speed of 11,250 rpm. Ultrahigh charge transfer quantity of ~310 μC and output power of 40.18 mW are obtained by per pulling of Wi-TENG. Moreover, a maximum short-circuit current of 317 μA and a constant open-circuit voltage peak value of 153 V can be generated by the Wi-TENG, which can rapidly charge a commercial capacitance (100 μF) to ~14 V within 10 s. After power management, this Wi-TENG is successfully demonstrated as a portable sustainable power source for driving a commercial blood glucose meter or a temperature-humidity sensor. This study presents the potential of Wi-TENG as a reliable portable instant power supply for personal health monitoring devices.
(Invited) GaN, SiC Power Devices are Competing with Si Insulated Gate Bipolar Transistors
Authors: Shur Michael
Published: February 2020

The high breakdown voltage, good thermal properties, and (in case of GaN) a higher field effect mobility compared to Si make the expected performance of GaN and SiC based power devices to be potentially vastly superior to that of the today leading power device technology - Si Insulated Gate Bipolar Power Transistors (Si IGBTs). After many year of development, commercial SiC power diodes and MOSFETs now outperform recent Si IGBTs and are poised to compete in the renewable energy and electrical vehicle markets. The recent generation of the hybrid SiC-Si IGBT modules combine the best features of both competing technologies.. These device hybrid modules handle powers up to 350 kW range at voltages well over 1 kV and have several times higher switching speed than the recent generations of Si IGBTs. SiC power technology is more mature than GaN power technology. However, the GaN enhancement mode High Electron Mobility Transistor (E-HEMT) on Si technology reached power ratings over 10 kW operating at 200 kHz with lower switching losses than Si MOSFETs and SiC MOSFETs. GaN devices already take about 20% of the RF power market with expectations of reaching 40% by 2025. Still, the existing device designs are not fully taking advantages of the superior materials properties of GaN. The lateral-vertical designs for a higher breakdown voltage; quantum well channel designs limiting high electron injection into the buffer layers; a low conducting passivation making the electric field distribution in the gate-to-drain spacing more uniform and therefore increasing the breakdown voltage, improving reliability, and increasing lifetime; perforated channel designs for decreasing the effect of the parasitic resistances and increasing the switching speeds are the innovative design features poised to improve the competitive edge of SiC and GaN technologies. For ultimate performance, the Si substrate in the GaN on Si technology should be replaced by SiC or even diamond, even though in a short run it would be hard for such technologies to be cost competitive. In a more distant feature, even diamond by itself might emerge as superior high power material. In a more near future, AlInN/AlN/GaN on Si technology could become a leading technology for high power applications.
(Invited) Packaging Material Technology for Wide Band Gap Power Devices and Its Performance/Reliability Evaluation
Authors: Suganuma Katsuaki , Sato Naoki , Suetake Aishi , Choe Chanyang , Sugahara Toru , Nagao Shijo , Chen Chuantong
Published: February 2020

Wide band gap semiconductors such as SiC and GaN have been expected to be established as the next generation power semiconductors, which are capable to reduce huge energy-loss in electric power conversion. The application of them will increase power density resulting in operation temperature rise beyond 200 °C. In addition, both increase of current and of frequency will also increase stress on devices. In general, power devices must possess robustness and high reliability for safe control of power conversion. Heat dissipation from the hot die in operation is one of the essential key factors for establishing high performance WBG devices. Here we report the current status of high temperature packaging materials including die-attach, wiring, substrates and molding compounds. In addition, reliability issues including thermal shock, power cycling and transient thermal properties will be summarized.

A series of DBC and DBA substrates, composed of Al and Cu as metal layers and of Al2O3, AlN and Si3N4, were examined by thermal shock test between -50 °C and 250 °C. DBC substrates with Al2O3 and AlN fractured only after 10 cycles due to severe thermal stress while all DBA and DBC with Si3N4 substrates survived. Al and Cu layer of all DBC and DBA substrates severely deformed by thermal shock. By microstructural observation, grain boundary sliding during thermal shock has a key to cause deformation of metal layers on ceramics. Ni and Ni-P plating on metal layer also deformed followed by Al and Cu layer deformation. Ni-P plating showed severe cracking which can be attributed to brittleness of Ni-P plating while Ni plating did not.

Ag sinter joining can be successfully applied for die attach by low temperature and low pressure bonding in air. For better bonding quality, Ag coating is the best metallization due to the specific reaction of Ag in air. By modifying solvent, Ag particles paste was modified to form a good bonding with Au surface finish. It can provide not only high temperature structural stability but also excellent thermal dissipation capability. High die-shear strength beyond 30 MPa was maintained by thermal shock between -50 °C and 250 °C up to 1000 cycles for a DBC die-attach structure. The thermal resistance of Ag sinter joined die attach is much lower than that of solder.　Figure shows the example of a GaN die-attached on DBC substrate with a new Ag sinter materials at 200 °C in air without any pressure. Even on the Au metallization, the GaN die was bonded with high strength. The interface shows a good bonding between Au and Ag.

This work was supported both by JST ALCA project on GaN packaging and by METI standardization project for evaluation methods of thermal properties of ceramics substrates.

Figure 1