Electrical Characterization of Ultra-Thin Silicon-on-Insulator Films Doped By Means of Phosphorus End-Terminated Polymers
Authors: Pulici Andrea , Kuschlan Stefano , Seguini Gabriele , Taglietti Fabiana , Fanciulli Marco , Chiarcos Riccardo , Laus Michele , Perego Michele 
Published: February 2024

Starting at the 3 nm node, the microelectronics industry is anticipated to transition toward new stacked device architectures, such as gate-all-around field-effect transistors (GAAFETs). In GAAFETs, the gate completely surrounds a silicon nanosheet that serves as a channel, improving the control of the current and performances. The introduction of ultra-scaled stacked 3D devices posed new technological and fundamental problems. In particular, doping techniques commonly used in the mass production of advanced transistors, such as ion implantation or diffusion, present some limitations when applied to these 3D structures. Perego et al.[1] suggested the use of dopant end-terminated polymers as a mild and simple alternative approach to achieve semiconductor doping. Considering the current trend in ultra-scaled microelectronic devices, exploitation of this doping technology requires the demonstration of the possibility to dope thin silicon membranes, achieving a uniform doping concentration throughout the entire film and optimized electrical properties.

In this work, ex-situ doping of silicon-on-insulator (SOI) substrates, with device layer thickness ranging from 6 to 70 nm, is performed by using poly(methylmetachrylate) polymers end-terminated with a P containing moiety (PMMA-P), following a procedure described in our previous works.[1,2] Accordingly, a phosphorus δ-layer is created at the interface between a SiO2 capping layer and the underlying Si device layer. Drive-in of the P atoms is performed by annealing the samples in a RTP system at temperatures ranging from 900 to 1200 °C in N2 atmosphere. Annealing time is selected to inject a constant P dose of ∼ 1 x 1013 cm-2 into the SOI substrate, achieving a uniform dopant concentration, as verified by ToF-SIMS measurements. Sample resistivity (ρ), carrier concentration (ne
) and mobility (μ) are determined through sheet resistance and Hall measurements in van der Pauw configuration.

Figure 1 shows the results of the electrical and compositional measurements obtained on SOI samples with 30 nm thick device layer as a function of the drive-in temperature. An average activation rate (ηa) above 95% is observed at room temperature in the samples annealed at 1000 °C, indicating full activation of the injected dopants. In the temperature range considered, the mobility is almost constant and is perfectly compatible with values reported in the literature for bulk Si,[3]as shown in the inset. Moreover, the low temperature (5-300 K) electrical characterization indicates that the evolution of ρ, ne
and μ values with temperature is consistent with those reported for a P doped bulk Si.[3]

Figure 2 shows the results of the electrical and compositional measurements obtained on SOI samples with device layer thickness ranging from 6 to 70 nm upon drive-in of the P dopants at 1000 °C for 100 s. When decreasing the thickness of the device layer, P concentration progressively increases above 1019 atoms/cm3, suggesting that the capping SiO2 film and the buried oxide act as diffusion barrier for P atoms injected into the device layer. ηa well above 80% are achieved for the SOI substrates with device layer thickness greater than 10 nm. However, ηa drops below 10% when further decreasing the thickness of the device layer. A similar reduction of the activation rates was observed in silicon nanowires by Bj
ö
rk et al.[4]

Interestingly, in extremely-thin SOI samples, donor deactivation is correlated to an increase in electron mobility with computed values even greater than those reported for a bulk Si[3], as shown in the inset of Figure 2. Figure 3 shows the relative electron mobility variation as a function of the ratio between the thickness and the average distance between donors for SOI samples annealed at 900 and 1000 °C. The computed values are perfectly compatible with those reported by Kadotani et al.[5] Their model suggests that the enhanced electron mobility observed in heavily doped extremely-thin SOI is caused by the transition from 3D to almost 2D conduction, which results in the reduction of the Coulomb scattering due to the lower number of neighbor donor ions.

In conclusion, an experimental study of the doping of ultra-thin SOI by means of phosphorus end-terminated polymers, demonstrates effective doping of silicon with extremely high activation rates of the dopants. Significant deactivation of P atoms and extremely high electron mobility are observed when decreasing the thickness of the device layer below 20 nm where bulk conducting properties transitioned to confinement related phenomena.

[1] M.Perego et al., ACS Nano 12 (2018) 178-186.

[2] M.Perego et al., J.Mater.Chem.C 8 (2020) 10229-10237.

[3] S.M.Sze, K.K.Ng, Physics of Semiconductor Devices (2006) 5-75.

[4] M.T.Björk et al., Nature Nanotechnology 4 (2009) 103-107.

[5] N.Kadotani et al., Journal of Applied Physics 110 (2011) 034502.

Figure 1