bluuebunny/crossref_metadata_2025 huggingface dataset:
Fault Diagnosis on the TMS320C80 (MVP) Using FastScan™
Authors: Platt J. , Butler K.M. , Venkataraman S. , Hetherington G. , Lorig G.
Published: December 2020

With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.
A Signature Analysis Method for IC Failure Analysis
Authors: Henderson C.L. , Soden J.M.
Published: December 2020

A new method of signature analysis is presented and explained. This method of signature analysis can be based on either experiential knowledge of failure analysis, observed data, or a combination of both. The method can also be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. The model is developed in the paper and an example is given for its use.
The Study of ESD Destructive Mechanism for PN-Junction
Authors: Wakai N. , TsuTsumi M. , Setoya T.
Published: December 2020

Mechanism of destruction caused by electrostatic discharge of PN junction was examined from two viewpoints; classification of destruction mode with consideration to destructive energy density, and comparison of destruction shape. Destructive energy density of PN junction was calculated based on Speakman model, and destruction mode was classified by Wunsch-Bell plot. As a result of Wunsch-Bell plot, electric discharge which occur at low resistance, for example machine model (MM: C∙R = 200pF ∙ 0Ω), resulted in adiabatic destruction that does not involve thermal diffusion. With electric discharge at high resistance, for example human body model (HBM: C∙R = 100pF ∙ 1500Ω), excessive destruction in intermediate region that involves thermal diffusion, and depending on the device, destruction at equilibrium region were proven to be reproducible. In case of MM, (adiabatic region destruction) destruction was confirmed in a wide extent of the joint part, but in case of HBM (intermediate region destruction) destruction was confirmed near the center of the joint part. From this fact, it was found that by verifying the places of destruction and their shapes, although in special cases, it is possible to know the destruction mode when destruction occurs.
Dielectric Breakdown in Printed Circuit Boards at Elevated Temperatures
Authors: Singh P. , Galyon G.T. , Obrzut J. , Alpaugh W.A.
Published: December 2020

A time delayed dielectric breakdown in printed circuit boards, operating at temperatures below the epoxy resin insulation thermo-electrical limits, is reported. The safe temperature-voltage operating regime was estimated and related to the glass-rubber transition (To) of printed circuit board dielectric. The TG was measured using DSC and compared with that determined from electrical conductivity of the laminate in the glassy and rubbery state. A failure model was developed and fitted to the experimental data matching a localized thermal degradation of the dielectric and time dependency. The model is based on localized heating of an insulation resistance defect that under certain voltage bias can exceed the TG, thus, initiating thermal degradation of the resin. The model agrees well with the experimental data and indicates that the failure rate and truncation time beyond which the probability of failure becomes insignificant, decreases with increasing glass-rubber transition temperature.
TPLY for Yield Improvement
Authors: Matusiewicz G.
Published: December 2020

A strategy for improving yield lately is this: wafers are electrically tested to determine which chips are defective. Defects are located and classified by the failure analyst who establishes a root cause for each type of defect. This information is delivered to the process engineers who then eliminate the root causes of the most frequently occurring defects. This process is known as TPLY. for Tested Product Limited Yield. This method gives the physical failure analyst the job of finding statistical numbers of defects. Defects are located by deprocessing chips and examining them with an optical or electron microscope, usually in an area of the chip identified by a bit fail map or some other technique, such as liquid crystal hot spot detection. This presentation offers practical suggestions for improving the efficiency of the TPLY process. It includes general considerations for TPLY, methods for delayering chips and finding defects quickly, and statistical methods for identifying the cause of low yield with minimum sample sizes. A simple yield model is developed for relating test site yield to product chip final test yield, and explains why test sites do not always adequately predict yield of the product. Case studies and other examples are discussed to demonstrate the application of these techniques.
An Investigation into Moisture-Induced Cracking in Plastic Packages Using Thermal Analysis Techniques
Authors: Chew S.
Published: December 2020

Pop-corn package cracking in thin quad flatpack packages (TQFP) during surface mount solder reflow can be minimized by adopting precautionary measures such as design changes, selection of new grades of epoxy mold compound (EMC) with lower affinity for moisture and lower expansivity, shipment and storage of epoxy mold compound under dry pack, as well as drying of plastic package prior to solder reflow. This paper investigates, using thermal analysis techniques, the cause of pop-corning phenomenon from pad-plastic interface in a particular batch of TQFPs despite the precautionary measures adopted. By comparing the difference in EMC properties between a control and reject batch of TQFP, this study suggest that ensuring optimum degree of polymerization or cure of the epoxy encapsulant can also assist in minimizing package delamination and pop-corn cracking.
Focused Ion Beam Irradiation Induced Damages on CMOS and Bipolar Technologies
Authors: Benbrik J. , Rolland G. , Perdu P. , Benteo B. , Casari M. , Desplats R. , Labat N. , Touboul A. , Danto Y.
Published: December 2020

Focused Ion Beam is commonly used for IC repairs and modifications. However, FIB operation may also induce a damaging impact which can takes place far from the working area due to the charge-up phenomenon. A complete characterization joined to an in-depth understanding of the physical phenomena arising from FIB irradiation is therefore necessary to take into account spurious FIB induced effects and to enhance the success of FIB modifications. In this paper, we present the effects of FIB irradiation on the electrical DC performances of different electronic devices such as nMOS and pMOS transistors, CMOS inverters, PN junctions and bipolar transistors. From the observed behavior of the DC characteristics evolution of the devices, some suggestions about physical mechanisms inducing the electrical degradation are proposed.
Performing Circuit Modification and Debugging Using Focused-Ion-Beam on Multi-Layered C4 Flip-Chip Devices
Authors: Li Susan X.
Published: December 2020

The task of circuit repairing and debugging using a Focused-Ion-Beam system on multi-layered IC devices is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or nontarget metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly denser. These conditions result in a decreased success rate utilizing the FIB and an increased turn-around time for design debugging. Besides significant improvement of the FIB equipment and tools, new techniques that can be used to overcome the difficulties encountered during FIB operations on multi-layered IC devices need to be utilized. In this paper, we will focus on discussion of some new techniques that can be used for FIB device modification work and device debugging on multi-layered IC devices, including C4 (controlled-collapse chip connection) flip-chip devices. Some recommendations and tips for using these techniques on complicated fib modification work will also be shared based on the author’s experience.
Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM
Authors: Perungulam Srikanth , Wills Scott , Mekras Greg
Published: December 2020

This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.
ESD Effects on Electromigration Performance of Aluminum Metallization Systems
Authors: Vinson J. E. , Dion M. J.
Published: December 2020

The semiconductor industry continues to challenge designer’s ability to provide adequate protection for ESD by scaling to ever-smaller geometries. The metal lines used to connect these circuit elements are also scaled. The effect of non-destructive ESD events on aluminum metal lines is investigated showing a reduction in electromigration lifetime for ESD events close to the failure threshold of the metal. The mechanism contributing to the reduction is a change in the microstructure of the metal resulting in void formation similar to traditional electromigration damage rather than melting and crystallization into smaller grains.
Guidelines for Two-Dimensional Dopant Profiling Using Scanning Capacitance Microscopy
Authors: Born Axel , Wiesendanger R.
Published: December 2020

This paper provides guidance and insights on the use of scanning capacitance microscopy (SCM) in semiconductor failure analysis. It explains why SCM systems are constrained by rigid performance tradeoffs and how CV measurements are affected by large stray capacitance and as well as edge effects associated with the 3D geometry of the sample and probe. It also explains how samples should be prepared and how proper sample preparation techniques combined with optimally selected voltages make it possible to accurately determine doping concentrations, even in p-n junctions.
Magnetic Current Imaging Techniques: Comparative Case Studies
Authors: Crépel Olivier , Descamps Philippe , Poirier Patrick , Desplats Romain , Perdu Philippe , Firiti Abdelhatif
Published: December 2020

Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.
Electrical Characterization of Sub-30nm Gatelength SOI MOSFETs
Authors: Kane Terence , Tenney Michael P.
Published: December 2020

Atomic Force Probe (AFP) techniques are well suited for the electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k interlevel dielectric films. This paper discusses the use of these techniques on sub-30nm gatelength SOI MOSFETs.
IC Specification Improvement Through Direct Passive Component Modification in the FIB
Authors: Domengès B. , Feron B. , Ledain S. , Tiphaigne B.
Published: December 2020

It is shown in this study that it is possible to modify under a controlled way the resistance of a passive component either through the milling of part of the volume of a polysilicon resistor or on the contrary through the deposition of a Pt strap parallely connected to the involved device polysilicon resistor. In the latter case, each modification step being followed by an electrical characterization, the evolution of device VCO phase noise versus equivalent resistor value could be drawn and the optimum value quantified.
Photon Emission Microscopy in 90 nm CMOS Technologies
Authors: Kruseman Bram , Goossens Martijn , Zieren Victor
Published: December 2020

The capabilities of photon emission microscopy with CCD and MCT camera systems for the 90 nm CMOS technology node were investigated. This was done with a dedicated test circuit with selectable shorts with resistance between 0 to 40 kΩ. Our investigations showed that conventional PEM with CCD systems is not possible anymore due to the reduction in photon emission intensity in the visible range. However, photon emission can be enhanced by using elevated supply voltages. For these overdrive conditions PEM with a CCD system is still feasible. We furthermore show that PEM is in principle capable of determining the state of a circuit and that PEM in combination with defect simulations can determine defect characteristics. In this manner, for example, the resistance of a short can be estimated by localising the PMOST emission spot.
Quantifying the Work of Adhesion Between an AFM Cantilever Tip and MEMS Test Structures After Packaging
Authors: Thoreson E. J. , Burnham N. A. , Martin J.
Published: December 2020

Adhesion is important to the yield and performance of MEMS (Micro-Electro-Mechanical Systems) and NEMS (Nano- Electro-Mechanical Systems). Measuring the work of adhesion, with an AFM (Atomic-Force Microscope), allows one to study surface interactions from an energy perspective as opposed to an adhesion (force) perspective. The works of adhesion were measured with different AFM tip radii on multiple types of samples. Two sample variables were examined: four die attach conditions (no attachment, silicone, polyimide silicone, and silver glass), and two surface conditions (native oxide with and without a few angstroms of vapor-deposited diphenyl siloxane). For a normal silicon cantilever, the work of adhesion seems to be slightly less for the treated surfaces than the untreated, except for the silverglass die attach material. There were at least three orders of magnitude difference in the works of adhesion for the different AFM tip radii. Presumably, the trend is due to some combination of material properties, interfacial roughness, and torque on the AFM cantilever.
Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint
Authors: Armendariz Norman J. , Paulraj Prawin
Published: December 2020

The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.
A Methodology for Characterizing System-Level ESD Sensitivity
Authors: Chagny Marie-Pascale , Naoum John A.
Published: December 2020

Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.
A Study of Power Plane Shapes, Their Contribution to Inter-Planar Electric Field Intensities, and Pre-Preg Breakdown
Authors: Kuriakose Eldho V. , Birdsley Jeff , Naoum John A.
Published: December 2020

The presence of sharp, “pointed” features on Printed Circuit Board (PCB) power planes and their contribution to increased plane-to-plane electric fields is studied as a potential root cause for PCB level dielectric breakdown. The results of this study are used to gauge the propensity for heat generation due to current leakage through pre-preg. A first order approximation for the E-field between a power and ground plane is Ê = V/d (1) where Ê is the electric field, V is the potential across the planes, and d is the separation between the planes. While this first order approximation is correct for infinite parallel planes, simulations show that second and third order effects that exist on real boards can multiply the effective Ê by more than 100x. The second order effects are primarily dependent on the local sharpness of planar shapes, and plane-to-plane separation. This amplified Efield could potentially breakdown pre-preg locally and initiate current leakage. Leakage through prepreg can grow over time as a leakage path becomes established and can wreak havoc with power rails or create a local ohmic conduction path that can lead to board level failures. A test platform and a series of experiments were developed to understand and quantify the various parameters that contribute to these failures. Tests revealed that given an ambient temperature of 70C, the presence of pointed features in planes reduces the breakdown voltage by at least 75%. It is suspected that under the right conditions, a breakdown will occur on a sharp shape if given sufficient duration of exposure to even low voltages.
In-Situ Sample Preparation and High-Resolution SEM-STEM Analysis
Authors: Young Richard J. , Bernas Michael P. , Moore Mary V. , Wang Young-Chung , Jordan Jay P. , Schampers Ruud , van Hees Ian
Published: December 2020

The dual-beam system, which combines a high-resolution scanning electron microscope (SEM) with a focused ion beam (FIB), allows sample preparation, imaging, and analysis to be accomplished in a single tool. This paper discusses how scanning transmission electron microscopy (STEM) with the electron beam enhances the analysis capabilities of the dualbeam. In particular, it shows how, using the combination of in-situ sample preparation and integrated SEM-STEM imaging, more failure analysis and characterization problems can be solved in the dual-beam without needing to use the Ångstrom-level capabilities of the transmission electron microscope (TEM).
Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy
Authors: Ho H.W. , Phang J.C.H. , Altes A. , Balk L.J.
Published: December 2020

In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.
Frequency Domain Imaging: Acoustic Microscopy Technique for Die Stacking Application
Authors: Aspera France B. , Flores Christopher , Salvador Ma. Cristina
Published: December 2020

Die stacking package technology continues to become the trend of manufacturing integrated circuits (IC) today. This primary design offers smaller and thinner packages that would optimize board space and assembly cost. Consequently, this packaging technology has posed challenges in conducting failure analysis. Nondestructive techniques like acoustic microscopy are bound for advancement to make them feasible for use in this packaging technology. This paper will present frequency domain imaging in the field of acoustic microscopy as applied in the detection of delamination defect on a stacked die package. Fast Fourier Transform (FFT) was used as an algorithm to reconstruct and reveal the delamination defect which was not clearly detected in time domain imaging of the package. Frequency domain imaging was found to offer a better image contrast of delamination. This gives the failure analyst another approach to characterize the location and extent of delamination defect, a set of information that is substantial in the root cause analysis of adhesion related failures in stacked die packages.
Defect Snap Shot: Quick Isolation and Mapping of Interconnect Defects for Backend Yield Improvement
Authors: Fan Jenny , Mark Dave
Published: December 2020

Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.
Material and Doping Contrast in Semiconductor Devices at Nanoscale Resolution Using Scattering-Type Scanning Near-Field Optical Microscopy
Authors: Wittborn J. , Weiland R. , Kazantsev D. , Huber A. , Hillenbrand R. , Keilmann F.
Published: December 2020

The usefulness of scattering-type near-field optical microscopy for mapping the material and doping in microelectronic devices at nanoscale resolution is demonstrated. Both amplitude and phase of infrared (λ = 10.7 μm) laser light scattered by a metallised, vibrating AFM tip scanned a few nanometers above the sample are detected and transformed into images showing contrast of materials, as well as of doping concentration. Cross-sections through layers as thin as 20 nm have been clearly imaged.
A System for Electromechanical Reliability Testing of MEMS Devices
Authors: Spinner Stefan , Doelle Michael , Ruther Patrick , Paul Oliver , Polian Ilia , Becker Bernd
Published: December 2020

This paper reports on a setup and a method that enables automated analysis of mechanical stress impact on microelectromechanical systems (MEMS). In this setup both electrical and optical inspection are available. Reliability testing is possible on a single chip as well as on the wafer level. Mechanical stress is applied to the tested structure with programmable static forces up to 3.6 N and dynamic loads at frequencies up to 20 Hz. The applications of the presented system include the postmanufacturing test, characterization and stress screens as well as reliability studies. We report preliminary results of long-term reliability testing obtained for a CMOS-based stress sensor.
Mixed-Signal Test Software Generation Process—Open Environment, Software Engineering Methods and Tools for Improving Quality and Productivity
Authors: Vock Stefan , von Staudt Hans Martin
Published: December 2020

Typical mixed-signal ICs are approaching 1000 or even more parametric tests. These tests are usually coded in a procedural or a semi-object oriented language. The huge code base of the programs is a significant challenge for maintaining code quality which inherently translates into outgoing quality. The paper will present software metrics of typical mixedsignal power management and audio devices with regard to the number of tests conducted. It will be shown that classical ways to handle test programs are error prone and tend to systematically repeat known mistakes. The adoption of selected software engineering methods can avoid such mistakes and improves the productivity of the mixed-signal test generation. Results of a pilot project show significant productivity improvement. Open-source based software is employed to provide the necessary tool support. They establish a potential roadmap to become independent of proprietary tester specific tool sets.
Image Intensity Analysis for Defect Localization Utilizing SEM BSE Imaging
Authors: Demarest J. , Chanda K. , Klepeis S. , Redder B. , Shore A. , Wang Y. , Christiansen C. , Rue C.
Published: December 2020

Failure analysts occasionally find themselves faced with the problem of having one of the various defect isolation techniques indicating a defect location, and yet no defect is readily visible through the various imaging methods available. Many common conventional imaging tools, such as scanning electron microscopes (SEM), display images in shades of gray. The human eye is inherently more sensitive to changes in color rather than changes in grayscale. As a result, subtle variations in grayscale which could indicate the defect location can go unobserved unless a careful examination of the image intensities is performed. One useful way to highlight these variations is through intensity profiling where a line scan is drawn through the region under investigation and compared to an identical reference location contained within the same image. Subtle variations in the intensity profiles can then be identified and defect locations can be pinpointed to specific locations for later cross sectioning and final root cause determination. This paper discusses the application of this methodology to two case studies: a resistive short and a resistive open.
Applications of Soft Defect Localization (SDL) on AMD Advanced SOI Microprocessors
Authors: Seah Yi-Xuan , Palaniappan M. , Chin J.M.
Published: December 2020

In this paper, we present application of the SDL technique towards full root cause analysis of functional and structural failures from BIST, SCAN etc. on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on a 90 nm process technology node. The devices were exercised at speed using production testers. SDL is used on these microprocessors with failure modes which pass at a lower temperature/voltage but fail at higher temperature/voltage or vice versa to isolate the failing logic/node. The SDL sites are examined for a full root cause analysis and possible process improvements.
Back Side Die Preparation for Check of Backend Related Problems
Authors: Huettinger Michael , Papenberg Uwe , Touzel Jerome , Janeiro Abel , Guedes Ricardo , Caldeira Conceicao , Ribeiro Carla
Published: December 2020

Damage on the top metal layer caused by backend packaging processes often results in unlocalizable electrical failures like column select fails in DRAM products. Consequently, crosssections through an exact address are unhelpful. Decapping from the front side of the die by removing the package (Top- Down preparation), only uncovers the damaged die area. The root cause is removed with the package. A preparation method that preserves the package at the failure (Bottom-Up preparation) is necessary. This paper presents a preparation method for investigations and assessment of backend related problems by removal of the Si-die from the back side, leaving the package and connections layers free for a quick and reliable review. Typical applications described here are the localization of imprint-originated fails or monitoring of the bonding processes.
Indirect Electrostatic Discharge Stressing Mechanism in VLSI Chips with Multiple Power Supply Domains
Authors: Sofer Sergey , Fefer Yefim , Shapira Yoram
Published: December 2020

Indirect electrostatic discharge stressing of a chip with multiple isolated power domains was analyzed. The stress penetrates to the victim domain via common nets having nonnegligible complex impedance and via coupling of the interdomain parasitic capacitors and in some cases may cause chip damage.
An Advanced Integrated Circuit Analysis System
Authors: Keyes Edward , Abt Jason
Published: December 2020

Historically, the extraction of circuitry from an integrated circuit was normally within the abilities of the average FA laboratory and could be accomplished with little more than an optical microscope and film camera. Dramatic increases in the level of integration and number of metal interconnect levels coupled with shrinking feature sizes have rendered these techniques obsolete. This paper describes techniques and methods for the fast, semi-automated extraction of detailed circuit schematics from modern, nanometer scale integrated circuits.
Yield Learning with Layout-aware Advanced Scan Diagnosis
Authors: Mekkoth Jayanth , Krishna Murali , Qian Jun , Hsu Will , Chen Chien-Hui , Chen Yuan-Shih , Tamarapalli Nagesh , Cheng Wu-Tung , Tofte Jan , Keim Martin
Published: December 2020

Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.
NBTI Reliability of Strained SOI MOSFETs
Authors: Thareja Gaurav , Lee Jack , Thean Aaron Voon-Yew , Vartanian Victor , Nguyen Bich-Yen
Published: December 2020

We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values was observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.
Atomic Force Probe Analysis of Nonvisible Defects in Sub-100nm CMOS Technologies
Authors: Mulder Randal , Subramanian Sam , Chrastecky Tony
Published: December 2020

Traditional micro-probing and electrical characterization at the transistor level for sub-100nm technologies has become very difficult if not virtually impossible. Scanning probe microscopy technology specifically atomic force probing was developed in response to these issues with traditional micro-probing. The case studies presented in this paper demonstrate how atomic force probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms, and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even though physical analysis with scanning election microscope/transmission electron microscope was not able to image and identify a failure mechanism. The probable causes for the transistor level failures are being identified through test methods, computer simulations, and electrical analysis by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors.
90nm Technology SRAM Soft Fail Analysis Using Nanoprobing and Junction Stain TEM
Authors: Zimmermann Gunnar , Mueller Stefan
Published: December 2020

This article describes a 90nm technology SRAM soft fail analysis. The bitmaps of affected wafers show a large number of wafer edge dies failing with single cell cluster fails at supply voltages below 1.0V. The fails appear in characteristic areas within a 256k dualport SRAM memory block. Nanoprobing was used for electrical localization at the cell level by means of a Multiprobe atomic force probe (AFP) system. Fail areas exhibit very weak PFET drain currents several orders of magnitude below the target values, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to TEM samples to delineate areas with different doping levels. Due to differences in etch behavior between failed and reference areas, missing LDD extensions and a partially blocked source/drain (S/D) implantation were identified as the root cause of the fails.
Integrated Raman – IR Thermography for Reliability and Performance Optimization and Failure Analysis of Electronic Devices
Authors: Kuball Martin , Sarua Andrei , Pomeroy James W. , Falk Aaron , Albright Grant , Uren Michael J. , Martin Trevor
Published: December 2020

We report on the development of a novel thermography technique, integrated Raman – IR thermography, illustrated here on AlGaN/GaN electronic devices. As it is a generic technique future application to Si, GaAs and other devices is anticipated. While IR thermography can provide fast temperature overviews, its current use for many of today’s technologies is complicated by the fact that it does not provide the spatial resolution needed to probe sub-micron/micron size active device areas. Integrating IR with micro-Raman thermography, providing temperature information with ~0.5 µm spatial resolution, enables unique thermal analysis of semiconductor devices to a level not possible before. This opens new opportunities for device performance and reliability optimization, and failure analysis of modern semiconductor technology, in research, development, and quality control / manufacturing environments.
Re-Thin a TEM Lamella by Using a Novel TEM Sample Preparation
Authors: Chen C. R.
Published: December 2020

Conventional FIB ex-situ lift-out is the most common technique for precise TEM sample preparation. But this method has some limitations and so in-situ lift-out technique was developed to overcome these drawbacks. The in-situ lift-out technique lifts-out the sample and then attaches the sample to a half-cut copper grid inside the FIB chamber by mini-probing system. This paper introduces a novel and simple technique that can overcome the above problems and a wide application of TEM samples preparation. The examples highlighted here demonstrate the novel method of low cost and high image quality TEM sample preparation. The method can reduce the amorphous phenomenon on the sidewall of specimen; no shield effect was found during the reprocess of thinning by ion-miller; and no contamination induced by the ion-miller sputtering was formed.
Detection and Verification of Silicide Pipe Defects on SOI Technology Using Voltage Contrast Inspection
Authors: Patterson Oliver D. , Kang Hyoung H. , Strane Jay , Lavoie Christian , Barth Karl , Ouyang Xu , Wu Kevin
Published: December 2020

A methodology for detecting silicide pipes on SOI technology in-line soon after their formation is described. Techniques currently exist to detect pipes in-line, but only much later in the process. This methodology, which is based on voltage contrast inspection of test structures, allows experiments to be completed more quickly providing much faster cycles of learning. Two different test structures are described. The first one was designed for other purposes but was adopted for silicide pipe detection at M1. The second was specially designed and allows pipe detection at silicide anneal, W CMP and M1. A procedure for determining the cause of buried shorts detected by the eS32 is also described. Experimental results are presented to demonstrate the benefit of this technique.
Concepts for In Situ Diagnostics in Analog Microelectronic Circuits
Authors: Kolasa Ted , Mendoza Alfredo
Published: December 2020

Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.
An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages
Authors: Hertl Michael , Weidmann Diane , Ngai Alex
Published: December 2020

A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles.
Laser Timing Probe with Frequency Mapping for Locating Signal Maxima
Authors: Koh L.S. , Marks H. , Ross L.K. , Chua C.M. , Phang J.C.H.
Published: December 2020

A Laser Timing Probe (LTP) system which uses a noninvasive 1.3 µm continuous wave (CW) laser with frequency mapping and single point measurement capabilities is described. The frequency mapping modes facilitate the localization of signal maxima for subsequent single point measurements. Measurements of waveforms with long delays and 50 ps response time from NMOS and PMOS transistors are also shown.
Electrical Signature Verification of a Lightly Doped Drain Profile Abnormality in a 65nm Device via Nano-Probing and Junction Stain TEM
Authors: Su Jie , Liang Sanan , Wen Yoyo , Yang May , Wu Linfeng , Niou Chorng , Chen Xianfeng , Zhao Gary
Published: December 2020

Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.
Non-Destructive Failure Analysis in Organic Thin-Film Transistors
Authors: Liu Shih-Ting , Liu Tao-Chi , Chang Ming-Lun , Chiang King-Ting , Chiu Su-Ping , Lin Jandel , Lo Po-Yuan , Li Pei-Wen
Published: December 2020

Contrary to conventional Si-based device, organic thin-film transistors (OTFTs) constituting organic semiconductors are easily destroyed. Investigating failures using traditional FA techniques like electron microscopy or cross section is hard to procure. Therefore, the purpose of this paper attempts to develop approaches for failure analysis of OTFTs. We successfully demonstrate a non-destructive technique for defect inspection and localization, exactly specifying the failure of OTFT with a void existing in the organic dielectric. Application of optical beam induced resistance change (OBIRCH) in current leakage localization is shown. Non-distorted cross-section sample preparation and analysis of internal structure by electron microscopy are also developed. Moreover, the failure of OTFT induced by high driving voltage punch-through is analyzed using techniques established in the article. Particular elongation of the gate metal was found to be the failure mode.
Approaches to Photovoltaic Systems Reliability
Authors: Granata Jennifer E , Collins Elmer , Mundt Mike , Robert Sorensen N. , Quintana Michael A.
Published: December 2020

Although crystalline silicon PV technology has been in use for more than 30 years, PV has remained a "cottage industry" until the recent expansion. This paper provides an introduction to the issues of reliability in the photovoltaic (PV) field, and the work the Department of Energy's Solar Energy Technologies Program is focused on to address these issues. In particular, the works of the Reliability Programs at both Sandia National Laboratories and the National Renewable Energy Laboratory are reviewed with several examples of results included and sited. Expanding reliability assessment and failure analysis techniques for components and systems can enhance the reliability of PV systems, which is necessary for large-scale deployment of PV as a power generation source.
Doping Profile Inspected by SEM Dopant Contrast, Wet Stain and SCM
Authors: Chou Po Fu , Chen Chun Yen
Published: December 2020

The techniques of doping profile inspection, such as SEM (Scanning Electron Microscope) dopant contrast, SEM wet stain and SCM (Scanning Capacitance Microscope) have been widely used in failure analysis for implant root causes identification. The applications of real FA (Failure analysis) cases and advantages/disadvantages will be discussed and demonstrated in this paper. To sum up, SEM dopant contrast is the most convenient method for doping profile inspection, and SCM is the best method for low doping profile observation.
A Novel Technique of Device Measurement after Cross-Sectional FIB in Failure Analysis
Authors: Chang Chih-Chung , Lin Jian-Chang , Wu Wen-Sheng , Tasi Chih-Ying , Chang Ching-Lin
Published: December 2020

A dual beam FIB (Focused Ion Beam) system which provides the ion beam (i-beam) and electron beam (e-beam) function are widely used in semiconductor manufacture for construction analysis and failure cause identification. Although FIB is useful for defect or structure inspection, sometimes, it is still difficult to diagnose the root cause via FIB e-beam image due to resolution limitation especially in products using nano meter scale processes. This restriction will deeply impact the FA analysts for worst site or real failure site judgment. The insufficient e-beam resolution can be overcome by advanced TEM (Transmission Electron Microscope) technology, but how can we know if this suspected failure site is a real killer or not when looking at the insufficient e-beam images inside a dual beam tool? Therefore, a novel technique of device measurement by using C-AFM (Conductive Atomic Force Microscope) or Nano-Probing system after cross-sectional (X-S) FIB inspection has been developed based on this requirement. This newly developed technology provides a good chance for the FA analysts to have a device characteristic study before TEM sample preparation. If there is any device characteristic shift by electrical measurement, the following TEM image should show a solid process abnormality with very high confidence. Oppositely, if no device characteristic shift can be measured, FIB milling is suggested to find the real fail site instead of trying TEM inspection directly.
Effectiveness of Non Destructive Physical Analysis Method Using X-ray CT Imaging
Authors: Mizoguchi Akira , Takeuchi Koichiro
Published: December 2020

Now we are attempting to apply non destructive analysis from evaluation tests or failure analysis to acceptance tests or production tests. Needless to say non destructive analysis has an advantage of conserving the state of samples and the reducing the time of analysis as compared to conventional methods with destructive physical analysis. Moreover, we are paying attention to the following reasons for nondestructive physical analysis. It is difficult to keep the reproducibility of the analysis because of the high skill level required for destructive physical analysis. On the other hand, high reproducibility can be easily achieved by fixing the condition or parameters of the device during nondestructive analysis when performed by tools like X-ray. Moreover, we expect that neither the analytical result nor the quality of the nondestructive analysis depends upon the worker's capability. In this paper we will discuss the following two items from the viewpoint of quality assurance. 1. The method of the screening for fake parts (1) The procedure flow for the production discontinued parts (2) The comparison and examination between the diagnostic using X-ray computed tomography (X-ray CT) images and various examinations (3) Other observation cases using X-ray CT images 2. Effectiveness and consideration in reliability evaluation test using X-ray CT image (1) Comparison of observation cases with a variety of jointing points in parts (2) Consideration of application of nondestructive observation technique in reliability test Use of X-ray CT images is effective in diagnosing the quality of the product or the process. Moreover, we find that use of X-ray CT images is effective for the improvement of the reproducibility of the evaluation examination. Then we find that use of X-ray CT images can reduce the time of evaluation examination too.