(Invited) Particles Removal on Challenging Surfaces
Authors: Garnier Philippe , Galbes Hugo 
Published: December 2024

Keywords: deep trenches, hydrophobic surfaces, particles, bevel, dies to wafer

Introduction

Particles removal in semiconductors manufacturing is key to achieve high yield. This process needs to keep evolving with respect to the huge variety of used surfaces: materials, dimensions shrink, and features’ aspect ratio. Some new methodology is proposed hereby to study the cleaning efficiency on very different challenging surfaces: deep trenches, wafer bevel and bonded dies to wafer.

Experimental and characterizations

In this work, 300mm silicon-based wafers are considered.

Various sizes and nature of particles (silica, Silicon nitride or ceria, nanometer to micron size) are used to intentionally contaminate the studied surfaces on a manual spin dryer. The particles amount is measured on wafer frontside surface by SP3 SurfscanTM tool, and by CIRCLTM on wafer bevel, both from KLA Tencor.

Several cleaning methods are used: nitrogen cryogeny on AntaresTM tool from TEL, and NanoliftTM on SU3300 from Screen.

Results and discussion

Several challenging surfaces are hereby discussed.

There’s still no standard for particles removal efficiency tests, since many parameters impact the result: particles nature, size, surface, queue time, relative humidity, contamination media, pH etc. Whereas only a few thousand particles are usually used for such tests, a huge number of discrete particles is relevant to acquire a fingerprint of the cleaning tool. This enables us to detect hardware or process concerns. For example, figure 1 shows two wafers, intentionally contaminated with about 100 000 SiN particles (40-200nm size) that are cleaned with two different processes. On the left, a nitrogen cryogeny process is performed. Straight vertical lines of remaining particles are evidenced. Ice clusters from the cryogeny are probably less energetic or numerous between two nozzle holes [1]. These lines are also discontinued (horizontal lines) when ice clusters atomization is pulsed (slight instability). On the right, some hardware bad settings are evidenced, with the spray scanning the wafer, not reaching the wafer edge.

Secondly, wafers with 7 µm deep trenches have been intentionally contaminated with silica and ceria particles, either on a spin dryer, or a CMP tool (figure 2 left). Since the surfaces are hydrophilic, most of the particles are deposited on the top surface next to the trenches, not inside [2]. Although such trenches need to be extremely clean [3], there’s a mild probability for particles to fall into very tiny trenches. Nevertheless, several cleaning methods have been compared: nanoliftTM [4] with incomplete deep trench filling [5], cryogeny and pure chemical action. The number of passes under the cryogenic aerosol influences the PRE(Particles Removal Efficiency) of the silica particles on top of the surface, but not inside the trenches. Indeed, the clusters are too big to convey some cleaning energy and remove such particles (figure 2 right).

Another challenging surface is the wafer bevel. Some solutions (wet etch, plasma, CMP, laser) are already proposed to mainly remove unstable films on this wafer area but no solution to simply remove particles. 0.5 µm ceria particles have been deposited on the wafer bevel, in a spin dryer, then measured on a CIRCLTM tool before and after (figure 3) the particles’ removal tests, some strong differences are noticed, especially in the cleaning uniformity within the wafer bevel surface, and the particles peeling method with the polymer gives the best performance (table 1).

Finally, some new challenges arise with the bonding of dies on wafers. Whereas some fluidics behavior has been previously shown [6], the cleaning efficiency with such high aspect ratio hasn’t been discussed yet. A fair comparison of cleaning performances between various physical cleans will be given (figure 4).

Conclusions

A new methodology is given to generate the cleaning tool fingerprint and evidence hardware / process failures. Then several challenging surfaces have been optimized

And eventually, some solutions are given to remove particles on challenging surfaces: deep trenches, wafer bevel and wafer with bonded dies.

References

[1] J. Lauerhaas, Advanced Semiconductor Manufacturing Conference and Workshop (2005).

[2] F. Wali, Solid State Phenomena, Vols 145-146, p 65-68 (2009).

[3] P. Garnier, ECS Trans., Vol. 80 (2), p 101-109 (2017).

[4] T. Mercadier, Solid State Phenomena, Vol. 346, p 268-274 (2023)

[5] A. Salhab, Physica Scripta, Vol. 98 (10) (2023).

[6] C. Lorant, improving clean performance for advanced packaging, SPCC conference (2019)

Figure 1