bluuebunny/crossref_metadata_2025 huggingface dataset:
Chip Embedding for Printed Circuit Boards and Subsystems
Authors: Gottwald Thomas , Neumann Alexander
Published: October 2015

The reason for chip embedding by means of PCB technology are manifold. Actually there are several emerging technologies on the market which all face one common problem: To realize the escape routing of a high pin count die one has to use several build up layers or very fine lines & spaces for the PCB. Both approaches have a significant influence on the cost of a electrical component because both solutions raise the manufacturing complexity. Due to this problem approaches like “chip first” or “chip last” are being discussed in plenty of papers.

With this paper, an alternative way of producing embedded systems is mentioned, which overcomes many of the actual problems.
Inkjet Printable Dispersions of Silver and Gold Nanoparticles
Authors: Balantrapu Krishna , Lu Lu , Halaciuga Ionel , Goia Dan V.
Published: October 2015

Miniaturization and increased complexity of electronic devices are two major trends in the electronic industry. Recent research indicates that inkjet printing can be successfully used in building smaller and more complex structures. This paper describes new methods for generating inkjet printable dispersions of highly dispersed silver and gold nanoparticles. The patterns deposited with a ‘drop-on-demand’ inkjet printer were sintered at different temperatures and converted into thin, highly conductive metal layers. In the case of silver, we show that the film microstructure and electrical resistivity can be tailored by using bimodal particle size distributions.
Correlation of Dispense Characteristics of Conductive Inks to Substrate Temperature
Authors: Haring Fred , Vignes Justin , Ahmad Syed Sajid , Shankaran Arun , Gerstner Kaycie , Dahlman Nicole , Reinholz Aaron
Published: October 2015

Formation of conductors on a substrate can be achieved by dispensing conductive materials on its surface. The quality and reliability of these conductors depends upon the ink characteristics, substrate characteristics and the dispensing parameters.

In this study, two materials were dispensed on a substrate commonly used in the industry at various temperatures. Results of the effect of substrate temperature on the quality of conductors dispensed on it are presented. The line width, its cross section area and its resistance and resistivity were measured at increasing temperature of the substrate and correlated to the substrate temperature.
Characteristic Life Based Acceleration Transforms for Lead-Free Solder Joint Reliability under Thermal Cycling Conditions
Authors: Ahmad Mudasir , Liu Kuo-Chuan
Published: October 2015

The conversion to Pb-free solders has already been implemented in the consumer market. However, the transition to Pb-free solders in the high performance, mission critical networking/server industry has not yet been fully implemented.

A significant factor in the slow transition to Pb-free solders is the absence of industry accepted Pb-free acceleration transforms that can translate lab test results into field reliability life data. Without such industry accepted acceleration transforms, it is difficult to translate lab test data into reliable predictions of field life performance.

In this two-phase study, a comprehensive set of test data have been generated over a wide spectrum of package types, solder joint metallurgies, joint size, pitch, die sizes, PCB thicknesses and thermal cycling conditions. The effect of aging on acceleration transforms was also included. The data has been analyzed and compared with existing Pb-free and SnPb acceleration transform models.

The data helps explain contradictions in the existing literature, and offers more comprehensive acceleration transforms for Pb-free solders. Some publications indicate that the acceleration transforms for Pb-free solders are the same as SnPb acceleration transforms [1]. Comprehensive results of this study also show that in specific conditions, Pb-free acceleration transforms could even be lower than SnPb acceleration transforms.
Pb-free v/s Tin-Lead Reliability Comparison for Telecom/High Reliability Applications
Authors: Iyer Ganesh , Ramakrishna Gnyaneshwar , Gopalakrishnan Lavanya , Liu Kuo-Chuan
Published: October 2015

With the European Union's (EU's) RoHS directives coming into force in July 2006 for consumer electronics products, the transition to lead-free (Pb-free) solder has occurred at a rapid pace. This push has driven many OEM suppliers/manufacturers to adopt Pb-free solder and End of Life many of their conventional Tin-Lead (Sn-Pb) components. This has forced telecom or high reliability applications to adopt Pb-free solder compositions with many reliability anomalies unanswered. While there have been many studies published on long term reliability of Pb-free solder joints at the component level, there have been few studies focused on the time zero reliability of the joints at the printed circuit board assembly (PCBA) level. The goal of this study is to help the OEM suppliers and their customers (like service providers) to come up with a common PCBA test methodology that will help identify and weed out early, marginal manufacturing and design defects that would crop up due to transition to the Pb-free solder. A normalized reliability data comparison and impact of the test on Pb-free and Tin-Lead solder alloys using test vehicles is presented in this study. The sequential PCBA level evaluation methodology involves a series of tests that include Thermal Aging, Mechanical Shock, Vibration, Functional test over elevated temperature and Destructive Analysis (Dye & Pry and Cross-sectional analysis) . The solder joint reliability comparisons for different components are presented against this methodology using different PCBA constructions (test vehicles).
Spin Coating of Dielectrics on Thin Silicon To Enhance Strength Characteristics
Authors: Haring Fred , Ahmad Syed Sajid , Schneck Nathan , Gerstner Kaycie , Dallman Nicole , Hoffarth Chris , Reinholz Aaron
Published: October 2015

Use of very thin wafers in the semiconductor industry poses handling challenges during manufacturing. The goal of this study was to determine whether applying thin coatings could create stronger, easy to handle wafers. Standard three-point bend testing of coated and uncoated thin wafer samples was used to determine whether the coating strengthened the wafers to improve their handling properties. Data indicated that only the thinnest coating on the thinner silicon increased the peak break strength in three-point bend testing.
Processing aspects to achieve high-end hybrid backside illuminated imagers
Authors: De Vos Joeri , De Munck Koen , Erismis Mehmet Akif , Rao Padmakumar Ramachandra , Minoglou Kiki , Zhang Wenqi , Tezcan Deniz S. , De Moor Piet , Soussan Philippe
Published: October 2015

We present a successful integration scheme of a backside illuminated 1024×1024 pixel sensor array, flip chipped on top of a ROIC with 10μm diameter Indium micro bumps, where the pixel pitch is 22.5μm. Backside illumination results, as compared to front side illumination, in a large gain in quantum efficiency because no incoming light is lost in the metal and dielectric layers. At the other side however, backside illuminated imagers requires more complex post processing because the detector array has to be thinned down to 30μm or less. Surface treatment reduces surface combination and lead to an improvement of the quantum efficiency of the device. Any damage induced at the backside of the imager is detrimental for the quantum efficiency since defects act as recombination centers for the light generated electron-hole pairs. In the end, all process optimizations on the hybrid backside illuminated imager device lead towards a quantum efficiency of 80–90% (over the visible spectrum). Next to the discussion on the critical steps (such as wafer thinning on carrier, wafer flip, cleaning), we introduce a novel backside alignment strategy to avoid using pyrex substrate as temporary carrier for thinning. Pyrex is namely not compatible in a high-end Si process environment due to its fragile nature. It is also shown that through introduction of a high aspect ratio pixel separating trenches, inter pixel electrical crosstalk can be avoided. Finally an alternative micro bump formation by means of CuSn bumps is presented.
PCB Effects on On-chip Capacitor Requirements and an Efficient Resonance-Prevention ASIC Methodology
Authors: Budell Timothy , Tremble Eric
Published: October 2015

A method for determining adequate quantities and locations of on-chip capacitors to maintain supply voltages at all locations on a chip within pre-specified limits given the switching activity of on-chip circuits was presented in [3]. In this paper, we extend the method to include current flow from the package and PCB. The effects of on-chip capacitance and other system parasitics on the time it takes for additional supply current to flow into a chip are discussed. The relationship between switching current, capacitance, system parasitic inductances, and on-chip noise is presented. These concepts are then applied to the subject of power delivery network (PDN) resonance. A 1-dimensional model for simulating PDN resonance is presented. The model includes chip, package, and PCB components, along with explicit networks for each chip power supply and their interactions. The topology of the model and the contributions of each model component are described. A design methodology for avoiding PDN resonance, presently in use on all IBM ASIC modules, is presented.
Statistical Analysis Approach to Improve the High Speed Signal Quality by Including the Manufacturing Process Variations of Printed Circuit Board
Authors: Baek Seungyong , Sapozhnikov Mike , Meggitt Warren , Pun Philip , Visneski Jason , Velugoti Ramesh , Agrawal Amit
Published: October 2015

In this paper, we propose a statistical analysis approach to consider the contributions across wide process variation permutations. The methodology is applied to a chip-to-connector high speed differential channel design for a multi-layer PCB. In addition, the contribution factor of each process variation parameter can be determined by the use of a sensitivity analysis. The DOE can be significantly reduced by over 50,000X using the Taguchi method reduction to 27. Finally, we acquire the sensitivity coefficient of each process variation parameters and probability distribution function of differential impedance, insertion loss, return loss and mode-conversion. And ±3σ impedance values were calculated and the statistical s-parameters are plotted. From these results, we can increase the confidence level of correlation between simulation and measurement because the proposed approach let us know the trend of variation of impedance and s-parameter by process variation.
Imminent Needs in Future Development of Air Cooled Microprocessors Heat Sinks
Authors: Ganescu V. , Pascu A.
Published: October 2015

This study reiterates the fact that revolutionary heat sink geometries, materials and overall exponentially higher performing alternatives are continuously and highly needed as applied to the air cooling of a typical computer system microprocessor. Attention was focused on forced convection regimes of operation and from a system level approach. Minor improvements in the performance of air cooled microprocessor heat sinks via typical small design improvements are discussed. Laminar convection and constant heat dissipation were looked at. The CFD simulations exemplified were completed for several power levels and ambient air characterized by a Pr = 0.71. The numerical results presented coincided in large with the experimentally derived documented data. In conclusion, the authors stress the fact that leading-edge alternatives in air-cooled heat removal of such applications are imperiously necessary.
Challenges of Wire Bonding In High Value and High Performance Medical Devices
Authors: Ohneck James A.
Published: October 2015

Wire bonding is a fairly mature technology that has been used in medical implantable products for over twenty years. Today however, its relevance continues to grow as the size of die continues to get smaller. Size, weight and volume are paramount when developing and manufacturing an implantable medical device, which often needs to perform a specific function such as, monitoring or adjusting parameters of the device itself, monitoring patient data or communicating data from the device to the healthcare professional.

Wire bonding can be the answer to addressing many of the requirements mentioned above. This paper will review the current status of the use of gold ball wire bonding and its relevance to the medical device industry as well as discuss how advancements in wire bonding processes benefit today's implantable products.

Wire bond interconnections can be made using gold, aluminum and copper wires. They each have different bonding characteristics and therefore require different application methods and equipment. The advantages and characteristics of gold ball wire bonding will be reviewed as this process relates to High Value Medical Devices.

Achieving high yields can also be a challenge with any wire bonding processes. Today's smaller die and pads require smaller gage wires. Typical production requirements are .8 – 1.2 mil wire and 4X4 pads. The demand to still go smaller requires continual adaptations and ingenuity as wire thicknesses are being pushed to .5 mils and below. Bond pull testing at the beginning, mid and end of production runs becomes important to verify integrity of the wire bonds with such small wire gages.

The complexities involved in wire bonding can lead to increased cost as well. To address this, a single process procedure is being adopted by many, which eliminates pattern plating and saves time and money. This new process will also be explained and reviewed.
A robust CUP pad structure design with thin pad metal for Cu wire bonding
Authors: Han ChangHee , Kim SG , Shim JH , Jiang DH , Ko SW , Lee BJ , Kim KC , Lee HG , Yoon JS , Jiang BT , Hong SW , Kim HD , Yoo IS , Song YS , Kim DalSoo , Choe Shihyun
Published: October 2015

In order to save the manufacturing cost of ULSI semiconductor device, there are two significant approaches; shrinking chip size by adopting CUP Pad (circuit under pad) and reducing package cost by using Cu wire bonding as a substitute for Au wire. However, these two approaches have a conflict that CUP pad is more sensitive to higher mechanical stress induced by Cu wire bonding than mechanical stress from Au wire. Thick pad metal is a way to enhance the strength of CUP pad but it brings enlargement of top metal design rule, which can increase chip size. Therefore it is highly required to develop a robust CUP pad structure with thin pad metal in order to apply Cu wire bonding without any negative effect on chip size. This study deeply investigated on the crack in CUP pad structure of ULSI with thin top metal caused by high mechanical stress of Cu wire bonding. FIB cross-sectional analysis for the crack revealed how and where the crack is started and propagated over the whole pad. Mechanism of pad crack was discovered by strain and strength analysis on each film layer which forms bonding pad structure. Cu wire bonding experiment was performed with several pad structures at various bonding conditions, the outcome of the experiment delivered major factors to enhance the strength of pad structure against physical damage during Cu wire bonding process. This study concentrates on a robust CUP pad structure of ULSI with thin pad metal for Cu wire designed with considering the major factors.
Free Air Ball Consistency of Palladium Coated Copper Wire
Authors: Yeung Johnny , Sutiono Sylvia , Milke Eugen
Published: October 2015

The formation of good free air ball (FAB) in palladium coated copper wire depends on many factors including the type of protection gas used, flow rate, Electric Flame Off (EFO) current, firing time and gap between the tip of wire and EFO wand. These factors can individually or, in combination of which, affect how good a ball can be formed prior to bonding onto the bond pad of a device. It is therefore important to find an optimum condition in forming good FAB so as to avoid poor bonded ball quality, or worse, non-uniform ball hardness that could lead to damage of the bond pad upon impact. The microstructure of the free air ball from palladium coated copper is unlike that of pure copper wire. It consists of palladium or palladium rich phase that can either exist partially or majority on surface of the ball making the structure non-uniform and inconsistency from one condition of EFO firing to the either. The hardness of the ball is also complicated by the non-uniform microstructure in such a way that determining the microhardness of the ball is never a straight forward characterisation. This paper covers the effect of process condition on the FAB size and quality of the wire. Microstructure and hardness of the FAB processed with different conditions are also presented and discussed.
Wire Bonding UPH and Stitch Bond Improvement using 20 Micron Diameter Insulated Wire with Security Bump
Authors: Nan Chunyan , Mayer Michael , Zhou Y. Norman , Pisigan Jairus L. , Persic John , Song Young-Kyu , Bathan Henry
Published: October 2015

In this study, security bumps are used for strengthening the stitch bonds of two 20 micron diameter insulated Au wire bonding example processes. Bump bonding as a variant of the ball bonding process has been commonly used in the microelectronic industry to make bumps on dies that will later be flip-chip bonded. The optimized stitch bond parameters combined with the security bumps placed upon the stitch bonds substantially improve the second bond strength demonstrated on the two example processes on two different types of wire bonding equipment. A comparison of pull test results shows that security bumps increase stitch pull force up to 100%. The effect of varying the relative position (shift) of the security bump relative to the stitch bond location is investigated for one process. The window with the highest pull force improvement is ranging from 16 to 31 micron shift towards the ball bond. Looping with insulated wire is faster than with bare wire because of less effort to mitigate the risks of wires touching each other and producing a short. If two wire loops touch each other e.g. after molding, the wire insulation prevents shorts. Therefore, the looping requirements of the example processes with security bumps can be relaxed by reducing the number of kinks (reverses) from four to two. Due to the reduced looping complexity, the overall UPH increased with insulated wire by about 3.0 % and 4.9 % for the two processes, respectively. This increase is in spite of the time required for the additional security bumps, and compared to bare wire processes without security bumps but with more complex looping.
The reliability of COF Joints with Tin Bumps and Non-Conductive Adhesives for Image Sensor Module Application
Authors: Lee Chang-Bae , Kim Jin-Gu , Kweon Young-Do , Harr Kyoung-Moo , Kim Young-Ho
Published: October 2015

We developed a low cost and low temperature chip-on flex(COF) bonding technology by using Sn bumps and non-conductive adhesive(NCA) for image sensor device. Two types of Sn bumps, square and hemispherical bumps, were fabricated. Sn bumps were formed sequentially by electroplating and then were reflowed to form the hemispherical bumps. Device with Sn bumps was bonded with flexible-printed circuit board(F-PCB) using NCA at 180°C after the NCA was dispensed. To evaluate the reliability of the COF joints, a thermal cycling (TC) test, high temperature storage (HTS) test, and temperature and humidity (T&H) test have been performed. The bondability and reliability of joints were evaluated by measuring the contact resistance of each bump. The electrical test showed that COF bonding was successful with no failed bumps, and the contact resistance of COF joints was very low about 10mΩ per bump. After aging treatment at 150°C slightly increased the contact resistance. But failed COF joints were not observed before and after aging treatment. The reliability of COF joints fabricated using hemispherical bumps was good more than that of joint with square Sn bump. NCA trapping in the interface between bump and pad had an influence on the reliability of COF joints. The results of our experiments were successfully performed in application for the temperature sensitive devices such as image sensor module.
Optimization of photovoltaic power generation using a Measurement and Management Technology (MMT) platform
Authors: Klein Levente J. , Rodrigues Sergio Bermudez , Nitta Satya , Sandstrom Robert , Guha Supratik , Hamann Hendrik
Published: October 2015

In this article we describe preliminary results for a general data acquisition and management platform applied to system level solar farm energy optimization. The system optimization takes into account weather, solar radiance, sky cloud coverage, and solar panel characteristics. Despite continuous improvement in photovoltaic (PV) systems, the generated power of many installations is underperforming due to factors like: light obstruction, orientation and tilt of the solar panels, variation in manufacturing and installation process and debris or soiling on the solar panels. To overcome the above challenges, we leverage the capabilities of an energy management analytic platform to monitor in real time the power generation from solar panels under real operating conditions. The generated power of the solar panel is correlated with predictive weather models where the influence of sky coverage, temperature and opacity of air are integrated in physical models to predict the solar panel performance. Furthermore, it is recognized that in large scale photovoltaics system the generated power is dependent on the performance of individual cells and solar panels. Analyzing spatial and temporal trends of individual solar panels and combining it with real time power performance enable an increased visibility in the PV system performance and optimization through power management of the individual solar panel.
Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration
Authors: Wu Chien-Ying , Chen Shang-Chun , Tzeng Pei-Jer , Lau John H. , Hsu Yi-Feng , Chen Jui-Chin , Hsin Yu-Chen , Chen Chien-Chou , Shen Shang-Hung , Lin Cha-Hsin , Ku Tzu-Kun , Kao Ming-Jer
Published: October 2015

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.
Use of Wafer Applied Underfill for 3D Stacking
Authors: La Manna Antonio , Rebibis K. J. , Gerets C. , Beyne E.
Published: October 2015

A key element for improving 3D stacking reliability is the choice of the right Underfill materials.

The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).
Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects
Authors: WANG Tao , CAI Jian , WANG Qian , ZHANG Hao , WANG Zheyao
Published: October 2015

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically.

The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.
SerDes Design and Modeling over 25+ Gb/s Serial Link
Authors: Aziz Pervez M. , Healey Adam , Liu Cathy , Zhong Freeman , Zabroda Alex
Published: October 2015

In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.
Influence of film thicknesses on the electrical properties of RuO2-thick film resistors on aluminum nitride ceramics (AlN)
Authors: Schmidt Richard , Kretzschmar Christel , Eberstein Markus
Published: October 2015

Aluminum nitride ceramics are very suitable as substrate material for thick film- / hybrid applications in the field of power electronics and microwave technology. Main features are high thermal conductivity, a thermal expansion coefficient close to silicon, good mechanical stability and dielectric properties. Thick film resistor pastes are usually composed of lead- and bismuth oxide free glass frit and ruthenium dioxide as electrical conductive component. In contrast to oxide ceramics like alumina ceramics, thermo dynamical calculations predict the reaction of ruthenium dioxide with AlN. Thus, resistor pastes for AlN are designed to build defined porosity in the films. In dependence of composition of the paste, substrate roughness and -quality varying interactions of the components and deviating film structures can be observed. On basis of different paste compositions resistors were built with varying film thicknesses. Electrical properties like resistance and its temperature coefficient as well as the power dissipation and short term overload voltage were correlated with geometrical data, chemical composition and substrate properties. Furthermore FESEM was used to characterise film properties like porosity and the interface resistor – ceramics. Users of thick film pastes are shown aspects under which conditions high quality resistors are maintained under maximum materials savings.
Screen printed RFID antennas on low cost flexible substrates
Authors: Janeczek Kamil , Jakubowska Małgorzata , Kozioł Grażyna , Młożniak Anna , Sitek Janusz
Published: October 2015

Recently, more and more studies are carried out in the field of printed RFID tags. It is connected with rapid development of new electronic technology, i.e. printed electronics which utilizes printing techniques, like screen printing, inkjet, flexography or gravure, for production of electronic components. This method is on one hand environmentally friendly because it allows eliminating wastes emerging during etching process used commonly in electronics. On the other hand, components can be printed on low cost flexible substrates, like foil or paper. These two factors cause that such products are cheap and can be competitive with their equivalents used currently.

In this study, investigations of RFID tag antennas working in UHF frequency range made with screen printing technique are described. Conductive polymer pastes containing silver nanopowder, silver flakes or carbon nanotubes were used for antenna fabrication. Each of them was deposited on foil and paper. Properties of printed antennas were investigated by return loss measurements performed in the frequency range 0.5 ÷ 1.5 GHz. Achieved results were compared with simulation carried out in CST Microwave Studio. Antenna surface profile was checked using optical profilometer or metallographic microscope. Its mechanical tests were also conducted. The obtained results showed that the best candidate for antenna printing on flexible substrate was the paste with silver nanopowder because it combined high conductivity and high mechanical durability.
The Road towards Fully Hybrid CMOS Imager Sensors.
Authors: De Vos Joeri , Jourdain Anne , Zhang Wenqi , De Munck Koen , De Moor Piet , La Manna Antonio
Published: October 2015

Monolithic imagers contain the photosensitive elements as well as the read-out IC (ROIC) on the same substrate. Backside thinning on carrier enables efficient collection of photo-generated carriers through back illumination, resulting in almost 100% fill factor. This contrary to front side illumination where light loss is introduced by reflection on metal interconnects. Together with an optimized backside ARC coating, high quantum efficiency (QE) can be achieved. Hybrid imagers consist of a detector array that is produced separately and hybridized on a ROIC. A fully-hybrid backside illuminated imager has more flexibility because the detector array and the ROIC can be separately optimized to the needs of the application leading towards further improvement on QE and inter pixel cross talk. Fully processed thinned diode arrays were flip-chipped onto the ROIC by means of an Indium bump per pixel. The choice of the bump type is very critical for yielding imager assemblies, or more in general, 3D assemblies. The Indium bump process has however limited fab compatibility to evolve towards a production mature hybrid imager process. Therefore an alternative electroplated CuSn micro bump process is described. We report an average daisy chain yield above 90% for die-to-die assemblies with CuSn bumps. Measurements were performed on a dedicated 1M bump area array test design with very long daisy chains of bumps on a 20μm pitch. Processing aspects like choice of plating seed layer, the influence of cleaning agents and seed layer etchants on the micro bump performance are being discussed. Finally, the impact on the daisy chain yield after thermal cycling is shown.
Packaging and Integration Concept for High-Performance and Cost-effective IQM-based Transmitter Module for 160 Gb/s Applications
Authors: Delrosso G. , Curran B. , Rothermund M. , Maaß U. , Oppermann H. , Ndip I.
Published: October 2015

Photonic packaging and interconnection design of Polarization Multiplexed RZ-DQPSK format are actually gaining interests because of the urgent need to fit 100+ Gbit/s channels into existing DWDM systems, with the associated advantage to use driving electronics at the effective speed-rate needed for each driving port. However, packaging and integration of IQM (In-phase/Quadrature Modulator) chips for 100+Gb/s applications poses huge design and process challenges. In this contribution, we present a systematic concept for efficient and cost-effective packaging and integration of a 4 × 43 Gb/s Polmux RZ-DQPSK transmitter module for 160 Gb/s applications. This concept takes into consideration electrical and thermo-mechanical design challenges right at the beginning of the design cycle, so as to prevent any system failure or possible re-designs. The two InP IQM chips are flip-chip bonded on a BGA-based ceramic package, preserving signal integrity, simplifying routing and dramatically minimizing overall size and assembly costs.
RF Sensitivity of Multi Chip Package Development by Using Embedded Resistor in Package Substrate
Authors: Lee Woong-Sun , Lim Sang-Joon , Shin Heung-Jae , Lee Jong-Tae , Park Jung-Kwon , Chung Qwan-Ho , Byun Kwang-Yoo
Published: October 2015

Recently, mobile age is blooming and makes change of 21st century. Especially multi chip package – MCP- is located center position of this flash era. Moreover, radio frequency –RF- sensitivity determines the product quality and life, therefore we try to develop the RF sensitivity of MCP in wireless circumstance. In this study, MCP comprised NAND Flash memory, Mobile DRAM, and a substrate, we focused on the substrate, changed substrate design and performance by using resistor embedded into 1 layer of substrate. The purpose of adaption of embedded resistor is in order to control the slew rate of signal channel of DRAM. NiCr thin film was used for the resistor in substrate. NiCr material presents superior temperature coefficient of resistance –TCR- to thick film material. NiCr coated on Cu foil and this foil laminated by conventional substrate manufacturing method. Embedded resistor applied on signal line as 3 kinds; 1. Signal and signal strobe line by 50 Ohm, 2.Signal strobe line by 50 Ohm, and 3. Signal and signal strobe line by 20 Ohm. In case of 3, result showed 0.5 dBm increment of RF sensitivity in full strength mode, also we got the same performance at half strength mode. Embedded resistor formed substrate did not affect the reliability of MCP, from the results of reliability test; pre-conditioning test, thermo-cyclic, temperature humidity, HAST, un-Bias HAST, and hot temperature storage test. This study showed signal waveform of DRAM is significantly effective in RF sensitivity for MCP. Passive component, resistor, made change of slew rate and revealed increase of sensitivity level finally.
Power Efficiency Improvement for Low Ohm Current Sense Resistor by Optimum Thermal Management
Authors: Rahman Akhlaq , Olinger Fred
Published: October 2015

To improve power efficiency, design engineers need to detect current throughout the circuit to minimize power loss. Low ohm current sense resistors are used to detect current to measure and monitor power. These components need to handle higher power to achieve optimal performance. In this work, we extensively studied to improve the power handling capability of low ohm current sense resistors, while maintaining smaller size. We optimized power dissipation by applying innovative thermal management techniques. Employing novel packaging technique, we optimized heat dispersion and minimized the peak surface temperature rise. Using proprietary thermal protection material, we avoided direct heat transfer from component to PC board and minimize the risk of thermal damage against PCB and extreme thermal cycle. We extensively discussed the thermal fatigue of resistor termination structure. Solid metal package construction leads to solder cracks due to thermal fatigue, hence decreases resistor reliability. We improved the packaging footprint and significantly reduced the chance of solder cracking. We optimized the resistor structure for current sensing and shunting purpose. We laid out electrodes and termination in parallel and minimized the contact resistance. Considering these parameters, we manufactured low ohm current sense resistor of 0.5 milli ohm to 100 milli ohm values with up to 5W rated power with tolerance as low as 0.5%.
Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter
Authors: Dohle Rainer , Härter Stefan , Goßler Jörg , Franke Jörg
Published: October 2015

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability.

Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing.

A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.
Printable Materials and Devices for Next Generation Packaging
Authors: Das Rabindra N. , Lin How T. , Huang Jianzhuang , Lauffer John M. , Poliks Mark D. , Markovich Voya R.
Published: October 2015

This paper examines the use of different materials in the area of printing technology. A variety of printable nanomaterials for electronic packaging have been developed. This includes nano capacitors and resistors as embedded passives, nano laser materials, optical materials, etc. Materials can provide high capacitance densities, ranging from 5nF/inch2 to 25 nF/inch2, depending on composition, particle size and film thickness. The electrical properties of capacitors fabricated from BaTiO3-epoxy nanocomposites showed a stable dielectric constant and low loss over a frequency range from 1MHz to 1000MHz. The change in capacitance after 3X IR-reflow and after 1000 cycles of deep thermal cycling (DTC) between −55°C and 125°C was within 5%. A variety of printable discrete resistors with different sheet resistances, ranging from ohm to Mohm, processed on large panels (19.5 inches × 24 inches) have been fabricated. Low resistivity materials, with volume resistivity in the range of 10−4 ohm-cm to 10−6 ohm-cm depending on composition, particle size, and loading can be used as conductive joints for high frequency and high density interconnect applications. The CITC (Current Induced Thermal Cycling) life at 245C is greater than 10 cycles and life at 220C is over 25 cycles to fail, which is at least equivalent to copper PTH (plated through hole) performance. Thermosetting polymers modified with ceramics or organics can produce low k and low loss dielectrics. Altogether, this is a new direction in the development of printable materials and devices suitable for next generation packaging.
CubeSat Fabrication through Additive Manufacturing and Micro-Dispensing
Authors: Gutierrez Cassie , Salas Rudy , Hernandez Gustavo , Muse Dan , Olivas Richard , MacDonald Eric , Irwin Michael D. , Wicker Ryan , Newton Mike , Church Ken , Zufelt Brian
Published: October 2015

Fabricating entire systems with both electrical and mechanical content through on-demand 3D printing is the future for high value manufacturing. In this new paradigm, conformal and complex shapes with a diversity of materials in spatial gradients can be built layer-by-layer using hybrid Additive Manufacturing (AM). A design can be conceived in Computer Aided Design (CAD) and printed on-demand. This new integrated approach enables the fabrication of sophisticated electronics in mechanical structures by avoiding the restrictions of traditional fabrication techniques, which result in stiff, two dimensional printed circuit boards (PCB) fabricated using many disparate and wasteful processes. The integration of Additive Manufacturing (AM) combined with Direct Print (DP) micro-dispensing and robotic pick-and-place for component placement can 1) provide the capability to print-on-demand fabrication, 2) enable the use of micron-resolution cavities for press fitting electronic components and 3) integrate conductive traces for electrical interconnect between components. The fabrication freedom introduced by AM techniques such as stereolithography (SL), ultrasonic consolidation (UC), and fused deposition modeling (FDM) have only recently been explored in the context of electronics integration and 3D packaging. This paper describes a process that provides a novel approach for the fabrication of stiff conformal structures with integrated electronics and describes a prototype demonstration: a volumetrically-efficient sensor and microcontroller subsystem scheduled to launch in a CubeSat designed with the CubeFlow methodology.
High-Fidelity Optical Microphone Manufactured in Laminates
Authors: Tsai Jonas , Zhang Yang , Li G.P. , Bachman Mark
Published: October 2015

We have built an optical MEMS microphone using processes commonly found in the packaging and printed circuit industry. Optical elements used to detect sound are manufactured using laminate processes and integrated onto printed circuit boards (PCB). Laminate MEMS (LMEMS) processing is an enabling technology that allows designers more freedom in designing MEMS and the packaging and printed circuit industry the capabilities of fabricating their own MEMS component. Using optics grade films and high-tolerance substrates, high-end electro optical components have been manufactured in the form of laminate waveguides, optical microphones and passive switches.
3D Packages and Assembly Methodologies
Authors: Appelt Bernd K
Published: October 2015

3D packaging is coming of age. Initially it was conceived to provide more memory in the same space. Memory die were stacked after thinning the die and bonding them on top of each other using conventional, thin die bond adhesive. The interconnect method remained wire bonding. While at first same die were stacked, the functionality was soon expanded by stacking different type of memory and or controllers in the same package. The explosive growth in mobile products and new applications while shrinking the form factor demanded a new packaging concept: the stacking of packages. The bottom package contains typically the application processor while top package holds memory, often stacked as well. Here, interconnects between packages are solder joints. As the demand for functionality and performance continues to grow relentlessly, bandwidth and electrical performance increase again demand more advanced packaging. It appears that silicon interposers, also called 2.5 D, will be the next type of packaging. The silicon interposer acts as a very high density substrate interconnecting die of different functionality. The interposer still requires an organic substrate as a CTE mismatch mitigator to connect to the motherboard. The ultimate step of the packaging technology evolution will be the real 3D package based on die to die interconnects based through silicon vias (TSV) providing the densest levels of interconnects between heterogeneous die and components.
Cost effective Precision 3D Glass Microfabrication for Electronic Packaging
Authors: Flemming Jeb H. , Dunn Kevin , Gouker James , Schmidt Carrie , Buckley Colin
Published: October 2015

The most singular focus of the electronics industry during the last 50 years has been to miniaturize ICs by miniaturization of transistors and on-chip interconnections. Two major problems are foreseen with this approach; (1) electrical leakage and (2) the lack of improved electrical performance beyond 16nm. As a result, the industry is transitioning from the current SOC-based approach to a through-silicon-via (TSV) based 3D IC-stacked approach. However, a major challenge remains; these 3D ICs need to be interconnected to other ICs with a much higher number of I/Os than are available with current ceramic or organic interposers. While silicon interposers currently in development can provide these high I/Os, they cannot do so at low enough cost.

In this extended abstract, 3D Glass Solutions, a division of Life BioScience, Inc., presents our efforts in glass interposer microfabrication. Glass interposers possess many advantages over silicon interposers including: cost, production time, and scale. 3D Glass Solution’s APEX™ Glass ceramic is a photo-sensitive material used to create high density arrays of through glass vias (TGVs) using three simple processing steps: exposure, baking, and etching. To date, we have been successful in producing large arrays of 12 micron diameter TGVs, with 14 micron center-to-center pitch, in 125 micron thick APEX™ Glass ceramic. This extended abstract covers (1) on our efforts producing high aspect ratio TGVs in ultra thin (75–250 micron) APEX™ Glass ceramic wafers, (2) maximum TGV aspect ratios, and (3) TGV fidelity and limits of manufacturing.
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration
Authors: Sheu Shyh-Shyuan , Lin Zue-Hua , Hung Jui-Feng , Lau John H. , Chen Peng-Shu , Wu Shih-Hsien , Su Keng-Li , Lin Chih-Sheng , Lai Shinn-Juh , Ku Tzu-Kun , Lo Wei-Chung , Kao Ming-Jer
Published: October 2015

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieving the function of monitoring the SiO2 thickness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.