Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures
Authors: Perina Welder Fernandes , Silva Vanessa Cristina Pereira , Martino Joao Antonio , Agopian Paula Ghedini Der , Simoen Eddy , Veloso Anabela 
Published: May 2020

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2).

The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm.

The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5).

It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart.

In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC.

The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2).

The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av.

As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length.

Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively.

Figure 1