Mechanism of Hump Phenomenon in the I-V Characteristics of Amorphous in-Ga-Zn-O Thin Film Transistors Under Positive Bias and Illumination Stress
Authors: Cho Yong-Jung , Lee Yeol-hyeong , Kim Woo-Sic , Kim Byeong-Koo , Park Kyung Tae , Kim Ohyun 
Published: February 2020

Amorphous indium-gallium-zinc-oxide (a-IGZO) has been considered as attractive material, because it has high electron mobility, good uniformity, high on/off ratio, and low processing temperature. Despite their promising features, a-IGZO TFTs are unreliable under gate-bias stress and illumination stress. In particular, under positive bias temperature stress (PBTS), a-IGZO TFTs have threshold voltage shift because of electron trapping at the gate insulator (GI) or interface between GI layer and a-IGZO layer. Another reliability problem under PBTS is a hump that occurs in the subthreshold regime of the I-V characteristics. Mechanism of the hump under PBTS has been studied consistently; however, effects of illumination to hump phenomenon was not considered. In real applications, TFTs are inevitably exposed to visible light emitted from the backplane unit in AMLCD panels or the self-emitting diode in OLED panels. Therefore the effects of positive bias illumination temperature stress (PBITS) to the hump phenomenon on a-IGZO TFTs have to be understood to solve reliability problem.

Back channel etch (BCE) structure a-IGZO TFTs were subjected to PBTS and PBITS. A gate voltage stress VGS
of 40 V was applied to the gate electrode while drain and source electrodes were grounded. Temperature was 90 ℃. Intensity of White LED was 5000 lux. The stress was interrupted periodically to measure the I-V characteristics of TFTs. During measurements, gate voltage VGS
was swept from -20 to 20 V, keeping the drain voltage VDS
at 0.1 V. We defined two kinds of threshold voltages : (1) On-current threshold voltage VON
(VGS
at which drain current ID
is 100 nA), and (2) Hump threshold voltage VH
(VGS
at which drain current ID 
is 1 nA) (Fig. 1).

Threshold voltage is more positively shifted under PBTS than under PBITS, however in terms of the hump, degradation of a-IGZO TFTs is more serious under PBITS than under PBTS; after the hump was induced, VH
is shifted more negatively under PBITS than under PBTS. When VH
is shifted more negatively, high negative gate bias should be applied to off the TFTs. I-V characteristics shifted positively at the early stage of stress time. After hump was induced, however, I-V characteristics had bidirectional shift (Fig. 1); VON
shifted positively and VH
shifted negatively. VON
shifted more positively under PBTS than under PBITS, while VH
shifted more negatively under PBITS than PBTS (△VH
under PBTS = 0.74 V and △VH
under PBITS = 1.88 V, from 4000 s to 10000 s) (Fig. 2). To investigate effects of illumination in detail, a-IGZO TFTs under PBITS with different wavelength illumination was measured. VON
shifted more positively under red illumination than under blue illumination, while VH
shifted more negatively under blue illumination than under red illumination (△VH
under PBITS with red illumination = 0.76 V and △VH
under PBITS with blue illumination = 2.55 V, from 4000 s to 10000 s) (Fig. 3). This means that VH 
was affected by the illumination with short wavelength lights.

In this work, I-V characteristics of a-IGZO TFTs was measured to quantify the mechanism that causes the hump in the I-V curve of a-IGZO TFTs under PBTS and PBITS. We focused on finding hump phenomenon in terms of illumination effects that have remained unclear. We will explain the effects of illumination to hump phenomenon, and difference between mechanism of the hump under PBTS and PBITS. Through this study, we could broaden our knowledge about the effect of illumination on a-IGZO TFT.

Figure 1