bluuebunny/crossref_metadata_2025 huggingface dataset:
Optical Run-Out Correction for Improved Lithography Overlay Accuracy for FOWLP Applications
Authors: Hichri Habib , Vis William , Arendt Markus
Published: December 2018

Finer features sizes in advanced Wafer-level-packaging (WLP) processes create increasing demands to improve lithography equipment overlay control. The improvement goes beyond the inherent overlay capability of the equipment (“tool-to-itself”), but requires ways to compensate for mismatches in actual feature size and position on the wafer with respect to the photomask pattern. In Fan-Out wafer level packaging (FOWLP), error contributions from the die placement robot, and especially errors from expanding and shrinking mold compound in which the dies are embedded (magnification error), lead to undesirable errors in layer to layer overlay. Mask-less laser direct imaging (LDI) technologies or die-by-die alignment strategies on steppers can deal with these error contributions, but they cannot provide adequate throughput and have a high cost-of-ownership, and therefore offer a limited solution for the industry.

An Active Optical Magnification Correction and Beam-Steering technology option has been developed, available on a full-field UV projection scanner tool. This option allows compensating any type of run-out or run-in up to +/− 200 ppm, or die shifts of +/− 30 μm on a 300 mm wafer, which corresponds to the amount of magnification error caused by the embedding of dies in mold compound nowadays. In addition, an additional optical asymmetrical correction function has been developed to compensate shifts of up to 50ppm in either X or Y. This paper will detail the principle and realization of this optical magnification correction technology. Performance data results for magnification error mitigation will be presented, and its effects on overlay, patterning performance, resolution, and throughput will be studied.
5G Systems and Packaging Opportunities
Authors: Sturdivant Rick
Published: December 2018

5G systems are being developed to meet the ever increasing desire for additional data bandwidth in mobile devices. Two enabling technologies for these systems are millimeter-wave electronics and phased arrays. Phased arrays have traditionally been used on military radar and satellite systems. However, they provide the capability to direct communication antenna beams directly to users or groups of users. In fact, standards committees agree that all network elements (including base stations, Access Points, and User Equipment) will be equipped with directional steerable antennas and can direct their beams in specific directions. In other words, phased arrays will be deployed at a variety of points in the 5G system even down to user equipment such as mobile phones, tablets, and lap tops. However, the components and modules used in 5G systems come with their unique packaging challenges. Those challenges will be described and some solutions will be given. 5G systems alternatives will also be described based on several architectures that are available for phased arrays. The two main reasons they are a challenge to package will be described. Several alternative solutions including heterogeneous packaging and 3D integration are described.
Cu diffusion into the glass under bias temperature stress condition for through glass vias (TGV) applications
Authors: Kim Hoon , Cai Ling , Fahey Albert , Vaddi Rajesh , Zhu Bin , Mazumder Prantik
Published: December 2018

For Through Glass Via (TGV) applications, significant copper migration in-between vias would result in failure of the device. The Cu migration occurs due to a combination of thermal and applied electrical field. Thus, it is critical to generate data of Cu diffusivity through glass as function of temperature and electrical field to determine whether a Cu diffusion barrier is required for this application. In this study, the Cu diffusion profiles in the Corning SG 3.4 glass, under varying electrical fields and temperature are evaluated. Using a planar capacitance test structure and a bias temperature stress test at elevated temperature, an Arrhenius plot of Cu diffusivity was obtained. Cu diffusion in the SG 3.4 glass has an activation energy of 1.1 eV which is in the range of thermal SiO2 and low-k of the references. Based on this Arrhenius plot, Cu diffusion depth at various combinations of operating temperatures and electrical fields can be determined. Based on the calculated diffusion lengths we infer that Cu diffusion barrier may not be required in most TGV applications.
Processing Through Glass Via (TGV) Interposers for Advanced Packaging
Authors: Woychik Charles , Lauffer John , Bajkowski David , Gaige Michael , Edwards Robert , Benninger Gordon , Wilson William
Published: December 2018

In recent years new applications for RF and MEMS devices require the insulating properties of glass. In order to realize these applications using a glass substrate, it becomes necessary to be able to deposit a metalized layer on both surfaces as well as create vias through the glass substrate. In this paper we will present results of glass interposers that have fine line circuitry on both sides of the substrate and that have through glass vias (TGVs). One major challenge is creating TGVs, using either electrically conductive adhesives (ECAs) or Cu plating methods, to achieve high conductivity and reliable via connections. In addition, it is important to have the capability to produce fine line metallization on the surface of the glass substrate. We employ a semi-additive plating (SAP) method to produce the fine line metallization. The combination of a robust process to create a TGV and the ability to use SAP to do fine line circuitry are the fundamental building blocks to generate advanced carriers for these new future electronic packaging applications.
Smart Passivation Materials with a Microencapsulated Liquid Metal for Self-Healing Conductors in Sustainable Electronic Devices
Authors: Chu Kunmo , Song Byong Gwon , Kim Yongsung , Lee Chang Seung
Published: December 2018

Passivation and self-healing of electric circuits are of importance in the area of electronic packaging for improving durability of devices. In particular, flexible or stretchable devices are vulnerable to mechanical stimuli, such as cutting, piercing, scratching, and pressing. The damage to a circuit results in the breakdown of devices. Therefore, a passivation layer has been essential to preserve the soft circuits and provide self-healing of the electrical pathways after they are damaged.
Evaluation of Low Cost, High Temperature Die and Substrate Attach Materials for Silicon Carbide (SiC) Power Modules
Authors: Seal Sayan , Passmore Brandon , McPherson Brice
Published: December 2018

The performance of SiC power devices has demonstrated superior characteristics as compared to conventional Silicon (Si) devices. Some of the advantages of SiC power devices over Si include higher voltage blocking capability, low specific on-resistance, high switching frequency, high temperature operation, and high power density. Thus, SiC modules are capable of processing significant levels of power within much smaller volumes compared with its Si counterparts. These high thermal loads present a formidable challenge in integrating SiC devices in power modules. For example, known-good materials and processes for silicon power modules are not rated at the aggressive operating conditions associated with SiC devices. Two of the most critical interfaces in a power electronics module are the die-attach and substrate- attach. A degradation in these interfaces often results in potentially catastrophic electrical and thermal failure. Therefore, it is very important to thoroughly evaluate die-attach materials before implementing them in SiC power modules. This paper presents the methodology for the evaluation of die attach materials for SiC power modules. Preforms of a lead-free high-temperature attach material were used to perform a die and substrate attach process on a conventional power module platform. The initial attach quality was inspected using non- destructive methods consisting of acoustic microscopy and x-ray scanning. Die attach and substrate attach voiding of < 5% was obtained indicating a very good attach quality. Cross-sectioning techniques were used to validate the inspection methods. The initial attach strength was measured using pull tests and shear tests. The measurements were repeated at the rated temperature of the module to ensure that the properties did not degrade excessively at the service temperature. At the rated module temperature of 175 °C, the die bonding strength was found to be ~ 75 kg. This was only 25% lower than the strength at room temperature. In addition, the contact pull strength was measured to be > 90 kg at 175 °C, which was 25% lower than the value measured at room temperature. The effect of power cycling and thermal cycling on the quality and strength of the die and substrate attach layers was also investigated.
Design and demonstration of Glass Panel Embedding for 3D System Packages for heterogeneous integration applications
Authors: Ravichandran Siddharth , Yamada Shuhei , Ogawa Tomonori , Shi Tailong , Liu Fuhan , Smet Vanessa , Sundaram Venky , Tummala Rao
Published: December 2018

This paper demonstrates a next generation high-performance 3D packaging architecture with smaller form factor, excellent electrical performance and reliability for heterogeneous integration. High density Logic-HBM integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are again limited by package size and ability to integrate many components. WLFO promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This paper presents the first demonstration of 3D Glass Panel Embedding (GPE) technology for high-performance large package applications involving heterogeneous integration. The tailorable CTE of glass allows a reliable direct board SMT of large GPE packages that not only benefits form factor and signal speed, but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump limited and can support BEOL-like I/O densities with Silicon-like RDL at much lower costs. The fundamental limitations like die-shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die-shift to <2 um while also improving the RDL surface planarity for high-yielding fine-line structures. This paper describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40um I/O pitch while also enabling double-side assembly of chips to achieve 3 levels of device integration.
A Reusable 3D Printed Cavity Resonator for Liquid Sample Characterization
Authors: Karuppuswami Saranraj , Mondal Saikat , Ghazali Mohd Ifwat Mohd , Chahal Premjeet
Published: December 2018

In this paper, additive manufacturing (3D printing) is used to fabricate and demonstrate a reusable microfluidic coupled rectangular cavity resonator for characterizing liquids in small volumes. The designed cavity operates in the fundamental TE101 mode and resonates at 4.12 GHz. The resonance of the cavity is perturbed by the sample placed in a small volume sample holder through a slot in the top cover. Two different perturbation configurations are investigated: i) strongly coupled (liquids with low to medium dielectric constants), and ii) weakly coupled (liquids with medium to high dielectric constant). The sample holder is loaded with different solvents and the shift in the resonance frequency is monitored. Based on these changes, the dielectric constant of the solvent is theoretically estimated and compared to standard values. The reusable liquid sensor holds significant potential in identifying and quantifying unknown liquid samples in the supply chain.
Reversed Pulse Plating of Silver-Cobalt for Connector Applications
Authors: Dadvand Nazila , Dadvand Mina , Kipouros Georges
Published: December 2018

The manuscript describes the use of anti-galling silver-cobalt alloy as a novel metallic contact finish for connector applications. The purpose of this work was to develop a cost-effective and cyanide-free and self-lubricated silver-cobalt alloy deposited using reversed pulse electrodeposition process for silver-based contact finishes in electrical contacts applications. The manuscript describes a novel silver-cobalt alloy deposited through reversed pulse-electroplating process that provides exceptionally low friction coefficient (similar to hard gold) and outstanding wear resistance compared to standard silver and any commercially available electroplated silver alloys such as silver-tin, silver palladium, silver antimony, silver-bismuth, silver-tellurium, and silver-tungsten.
X-ray Advances in Support of Advanced Packaging – Today and Tomorrow
Authors: Bernard David
Published: December 2018

As advanced packaging continues to develop to support novel and emerging technologies, the need for, ideally non-destructive, test and inspection continues to be vital to ensure the quality and assurance of functionality, wherever the package may go. This is made ever more difficult as the package complexity increases, whilst the feature sizes within continue to decrease. X-ray technology has long been an important part of the non-destructive inspection protocol over the history of advanced packaging and will continue to need to play a more important part in the future. This paper will review the advances made in both 2D and 3D X-ray inspection over recent years and the new opportunities that are now starting to be available, especially in 3D, or CT, inspection, that will enable this 120-year-old technology to remain relevant to and supportive of the needs of advanced packaging.

To highlight the above, a case study will be presented on the faults that 2D and CT X-ray analysis can find in LEDs during their manufacture. LEDs are a good example of the remarkable developments in packaging and technology over the last 20 years, where the use of higher powers, smaller sized features and increased reliability requirements intensify the need for higher quality, more consistent production output. Flaws cannot be accepted, especially as higher usage powers mean higher operating temperatures which, in turn, then requires very good thermal conductivity in the package to move heat away from key areas. Without good heat dissipation then heat stresses at the interfaces can cause delamination or die fractures, so reducing LED lifetimes. The presence of voids, particularly at the die to package interface, creates air gaps that reduces heat transfer efficiency. As many LEDs are potted, or encapsulated, the only non-destructive test option to check for voiding and other faults is by using 2D and CT X-ray analysis.
Low Dk and Df Photosensitive Insulation Material for Low Transmission Loss Packages
Authors: Abe Shinichiro , Mitsukura Kazuyuki , Imazu Yuki , Toba Masaya , Masuko Takashi , Kurafuchi Kazuhiko
Published: December 2018

The interposer or fan-out packaging technology with ultra-fine line/space and high frequency signal has been required in order to achieve high speed interconnection between chips with low cost. In this paper, we have newly developed low Dk and Df photosensitive insulation material. The additional features of the developed materials are very low moisture absorptivity less than 0.3 wt%, low anion impurities and high resistance to hydrolysis. The micro-strip line was fabricated to evaluate the influence of developed material. The insertion loss from transmission lines on Material C shows much lower loss than the conventional reference material at higher frequencies. The peel strength to the sputtered Ti and Cu is over 0.7 kN/m. The material also demonstrated SAP fabrication compatibility with fine circuitry and passed insulation reliability by biased-HAST showing no copper migration measured by EDX.
Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging
Authors: Kaessner S. , Scheibel M.G. , Behrendt S. , Boettge B. , Nickel K.G.
Published: December 2018

Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such future electronic devices, it is necessary to incorporate wide bandgap semiconductor technology such as silicon carbide and gallium nitride operating at higher temperatures. Therefore, the development of novel materials with high thermal conductivities and stability, withstanding harsh environments up to 300°C is of major interest. Especially, polymeric encapsulation materials have to be improved because of common degradation effects above 175°C. Ceramic (nonpolymeric) materials with thermal conductivities above 5 W/(m·K) already illustrated promising results for the encapsulation of power electronics. The present work illustrates recent developments and improvements on novel ceramic encapsulation materials, which finally avoid critical interactions with the chip surface. Furthermore, advances in reliability will be discussed in terms of passed high-temperature reverse bias and humidity tests correlated with relevant material properties.
Advanced Packaging for Automotive Dashboard Application
Authors: Islam Nokibul , Choi HC
Published: December 2018

The current automotive market for the integrated circuit (IC) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus to prioritize the development of advanced packages for next generation automotive market requirements.

Automotive IC's are traditionally wirebond packages. Due to the increasing complexity and higher performance requirements of automotive applications, the packaging industry is moving towards high performance flip chip packages for automotive infotainment, GPS, and radar applications. In this study, a comprehensive view of the evolving packaging landscape from traditional wirebond to flip chip interconnect to advanced fan-out wafer level packages will be discussed. The pros and cons of each packaging technology will be examined. Packaging roadmap details will be discussed along with assembly process information, determining the right bill of materials (BOM), and extensive package and board level reliability (BLR) including grade 1 and grade 0 reliability data will be discussed.
Novel Low Temperature Curable Photosensitive Negative-tone Polyimide with Higher Resolution and Reliability
Authors: Matsukawa Daisaku , Yotsuyanagi Hiroko , Sakakibara Shiori , Yamazaki Noriyuki , Enomoto Tetsuya , Motobe Takeharu
Published: December 2018

Hitachi Chemical DuPont MicroSystems (HDMS) has been developing photo sensitive negative-tone polyimides (PIs) as dielectrics for re-distribution layers (RDLs) in wafer level packages (WLPs) and as protection layers in semiconductor ICs. Photo sensitive negative-tone PIs can simplify the manufacturing process and ensure high reliability owing to their good mechanical properties, high thermal stability, and high electrical properties. On the other hand, since advanced packaging application such as Fan-Out WLP (FO-WLP) requires finer L/S design as well as higher reliability, lithographic performance of PIs has to be further improved and good cured film property should be achieved when cured at lower temperature (<230 °C). In order to meet these requirements, HDMS started the development of new PI which shows enhanced lithographic performance with good film property.

In this paper, we will demonstrate our novel low temperature curable photo sensitive solvent developable negative-tone PI. By adopting a new photo-package to improve lithographic performance, this PI can achieve 3 μm via opening at 5 μm cured thickness and 5 μm via opening at 10 μm cured thickness with smooth pattern profile after cure. In addition, this PI shows good film property when cured at 200 °C and no electrical failure is observed during 300h bias-HAST using 2/2 μm L/S pattern.
Fine Pitch Paste for System-in-Package Applications
Authors: Ruifen Zhang , Murali Sarangapani , Sureshkumar Vinobaji , Lingling Teo , Keong Loke Chee , Li-San Chan
Published: December 2018

Water soluble solder paste developed using T7 powder particles revealed good solderability when printed on copper, tin, gold flash nickel plated surfaces and on reflow as well. Its cross-section showed absence of voids, good wetting and soldering to the plated surfaces with angle of contact from 42° to 84° on reflow. All the solder interface are integral with pad/substrate surfaces and revealed formation of tin based intermetallics. T7 solder powder processed using Welco technology showed spherical, clean, smooth, un-agglomerated powder particles with the size range of 2 to 12μm. The developed solder paste is used for fine pitch applications.
Elevated Stand-Off Heights in Solder Joint Interconnections of Surface Mounted IC Packages Result in Appreciable Stress and Warpage Relief
Authors: Suhir Ephraim , Yi Sung , Hwang Jennie S. , Ghaffarian R.
Published: December 2018

The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of IC packages with conventional (small) stand-off heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: 1) attributes of the manufacturing process, 2) solder material properties and 3)design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the PCB-package assembly and particularly to the differences in the thermally induced curvatures of the PCB and the package. In this analysis the stress-and-warpage issue is addressed using an analytical predictive stress model. This model is a modification and an extension of the model developed back in 1980-s by the first author. It is assumed that it is the difference in the post-fabrication deflections of the PCB-package assembly that is the root cause of the solder materials failures and particularly and perhaps the HnP defects. The calculated data based on the developed analytical thermal stress model suggest that the replacement of the conventional ball-grid-array (BGA) designs with designs characterized by elevated stand-off heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design referred to as ball-grid-array (BGA) and a design with solder joints with elevated stand-off heights referred to as column-grid-array (CGA) are compared. The computed data indicated that the effective stress in the solder material is relieved by about 40% and the difference between the maximum deflections of the PCB and the package is reduced by about 60%, when the BGA design is replaced by a CGA system. Although no proof that the use of solder joints with elevated stand-off heights will lessen the package propensity to the HnP defects is provided, the authors think that there is a reason to believe that the application of solder joints with elevated stand-off heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.
Ultra-Fine Pitch Wedge bonding for Device Reliability Characterization
Authors: Badger Lacey L. , Toledo Nikholas G. , Slottke Derek W. , Thomas John , Alamillo Miguel , Gunnarsson Elliott , Le Rutt Mark L. , Tsameret Ilan
Published: December 2018

Intel's EM (electromigration) package level stress lab has historically used 1mil aluminum wire to bond to pads 53 μm by 60 μm, with a pitch of 86 μm by 88 μm. The lab was challenged to align its wedge bonding capabilities to match the pitch used at wafer level probing with a pad size of 30 μm by 37 μm and pitch of 43 μm by 50.6 μm. In order to achieve the 43 μm by 50.6 μm pitch, 0.7 mil aluminum wire and an ultra-fine pitch wedge was used. In this paper, the benefits or matching the wafer level probe card capabilities are discussed as well as the concerns and considerations of implementing such a small pitch process. The primary concerns are heel shorting and bond placement repeatability but many factors influence these parameters. A brief summary of electrical testing performed to validate the process is discussed as well as new challenges that have arose due to the new testing capabilities.
Process Development of Al-alloy Wire Bonding for High-Temperature Power Electronics
Authors: Che Xuan , Xu Tao , Fu Jason , Niayesh Omid
Published: December 2018

In this work, process parameters are developed for an Al-alloy wire for high-temperature power electronics. Shear and pull forces of the bonds on IGBT devices reach 2200 g and 1100 g respectively, without causing any die cratering. Comparison of the Al-alloy wire and standard Al wire bonded on battery cells shows that both the pull and shear forces of the bonds with the Al-alloy wire are improved by ~20%. This indicates that this Al-alloy wire potentially could be used for bonding on the power electronics and batteries in automotive industry, where better mechanical strength and wider bond window are required.
Intelligent Production of Wire Bonds using Multi-Objective Optimization – Insights, Opportunities and Challenges
Authors: Unger Andreas , Hunstig Matthias , Meyer Tobias , Brökelmann Michael , Sextro Walter
Published: December 2018

Ultrasonic wire bonding is an indispensable process in the industrial manufacturing of semiconductor devices. Copper wire is increasingly replacing the well-established aluminium wire because of its superior electrical, thermal and mechanical properties. Copper wire processes differ significantly from aluminium processes and are more sensitive to disturbances, which reduces the range of parameter values suitable for a stable process. Disturbances can be compensated by an adaption of process parameters, but finding suitable parameters manually is difficult and time-consuming. This paper presents a physical model of the ultrasonic wire bonding process including the friction contact between tool and wire. This model yields novel insights into the process. A prototype of a multi-objective optimizing bonding machine (MOBM) is presented. It uses multi-objective optimization, based on the complete process model, to automatically select the best operating point as a compromise of concurrent objectives.
Comparisons of Soldering Alloys in Large Ceramic Substrate to Metal Heatsink Attachment Application
Authors: Wang Frank Fan , McKeague William , Polwarth Christina
Published: December 2018

Tin-lead alloys have historically been popular in the electronics industry for use in solder-attach applications. Despite recent restrictions related to lead content, some industries continue to use lead based alloys in solder applications. Tin-lead based alloys, in particular, have proven to have excellent solderability to tin, nickel, copper, gold, and silver metallization surfaces. They have also performed better in reliability than most of the lead free solders. As a result of this, they are still widely used in the aerospace and military electronics industry.

Hybrid microelectronics built for space applications use both Tin-Lead-Silver Alloy Sn62 and Lead Free Soldering Alloy Sn96; these solders are used both for wire and component attach as well as substrate to header attach.

This article discusses the differences of these two solders, using both literature and experimental study. Experimental testing involving pull tests further supports this conclusion.
Mechanical Insertion and Reliability Testing of Thermal Interface Materials for Semiconductor Test and Burn-in Applications
Authors: Saums Dave , Jensen Tim , Gowans Carol , Homer Seth , Hunadi Ron
Published: December 2018

Semiconductor test and burn-in requirements for thermal interface materials (TIMs) are challenging, with difficult mechanical reliability requirements that are not found in other types of applications for these materials. To demonstrate the ability of certain newly-developed TIMs to not only provide suitable thermal performance for the device under test and meet these mechanical requirements, a contact cycling test has been devised in three phases for evaluating TIM mechanical performance and durability.
Novel formaldehyde-free electroless copper for plating on next-generation substrates
Authors: Wendeln Christian , Steinhäuser Edith , Stamp Lutz , Dosse-Gomez Bexy , Langhammer Elisa , Reiber Sebastian , Dünnebeil Sebastian , Röseler Sandra
Published: December 2018

This work describes a new type of formaldehyde-free electroless copper electrolyte that can be used for a broad set of applications and materials, especially for the processing of next-generation substrates. The plating solution was successfully applied in both, a laboratory and production-scale environment. The results have been evaluated in detail and were benchmarked against a formaldehyde-based reference. A characterization of the obtained metal films was carried out by different analytical techniques, including microscopy, X-ray fluorescence (XRF), scanning electron microscopy (SEM), adhesion tests and non-blister verification. Additionally, studies concerning chemical bath stability, throwing power and electrical reliability have been made. Based on the obtained data we believe that the current achievements represent a suitable technology to replace formaldehyde in existing printed circuit board (PCB) production without loss of process performance and thus provide a sustainable “green” alternative to the industry.
Optimization of Cupric Chloride Subtractive Etching for Cu High Density Interconnects
Authors: Lambert Alexander , Issac Goutham , Salunke Ashish , Lu Luwen , Chyan Oliver
Published: December 2018

The continuously increasing demand for innovation in the miniaturization of microelectronics has driven the need for ever more precise fabrication strategies for device packaging, especially for printed circuit boards (PCBs). Subtractive copper etching is a fundamental step in this processes, requiring very precise control of etch rate and etch profile. Cu etching baths are typically monitored with several parameters including oxidation-reduction potential, conductivity, and specific gravity. However, the etch rate and etch profile can be difficult to control even under strict engineering controls of those monitoring parameters. The mechanism of acidic cupric chloride etching, regeneration and recovery is complex, and the current monitoring strategies can have difficulty controlling the complex interlocking chemical equilibria. We report that thin-film UV-Vis spectroscopy has the capability to effectively monitor the complex changes to the etch bath. UV-Vis also reveals various underlying mechanism reasons for etch bath behavior and illuminates the roles of H+ and Cl− to the etch bath while also providing a means to monitor the Cl−. Furthermore, UV-Vis can be utilized to improve current monitoring strategies, as it can identify and predict etching behavior that the current standard methodologies may have difficulty predicting.
Development of skills and tools for micro opto-electrical integration on wafer level
Authors: Schröder Saskia , Stenchly Vanessa , Quenzer Hans-Joachim , Reinert Wolfgang
Published: December 2018

New devices for a digital lifestyle like augmented reality (AR) glasses may find their wide spread use only if consumer relevant pricing can be achieved. Low cost RGB-light sources are a key element for AR. assembly productivity for these micro opto-electrical RGB-light sources and a further reduction in their package dimensions. We present our new approach to build miniature RGB-light sources on structured silicon wafers and elaborate the required skill set and our future process infrastructure based on our existing high volume capable optical packaging platform. The platform provides an optical bench with integrated heat spreader and emission windows enabling miniature hermetic housing for laser diodes assemblies on 8″ wafers.
Laser Power Supply Thermo-Structural Analysis for the Mars 2020 Rover
Authors: Cepeda-Rizo Juan , Tuman David
Published: December 2018

Operation of the Laser Power Supply (LPS) module provides the dual challenge of high power dissipation, and the need for strict dielectric isolation, while needing to survive in an environment on Mars that will see a chilly night-time temperature of −123°C, and to a daytime instrument environment in excess of 50°C. Additionally, power restrictions prevent the use of survival heating during the night. The harsh mechanical vibration environment of launch and landing provides an additional challenge to reliability. A multi-physics simulation was created that took into account temperature property variations, as well as solving the transient analysis that also included rapid variation in power-pulsing during the operation of the laser. The steady state analysis employed a more traditional finite element based analysis, but with provisions for Mars gas convection and thermal radiation.
MOCVD Copper Metallization for High Aspect Ratios TSV 3D Integration.
Authors: Fadloun Sabrina , Stephens Dean , Gergaud Patrice , Blanquet Elisabeth , Mourier Thierry , Jones Chris , Burgess Steve , Rastogi Amit
Published: December 2018

MOCVD (Metal-Organic Chemical Vapor Deposition) copper metallization was developed on 300mm wafers, to fulfil 3D Through-Silicon Via (TSV) interconnect requirements. Using a fluorine-free organometallic precursor, the bis(dimethylamino-2-propoxy)copper (II) Cu[OCHMeCH2NMe2]2 at low temperature deposition, we developed a high purity, low stress copper film with strong adhesion to a TiN barrier layer. Argon was used as a carrier gas and H2 and/or H2O as a co-reactant. This MOCVD technique offers good conformality observed with 10μm×120μmTSVs. The thin copper seed layer was successfully integrated on 300mm wafers. A new XRD protocol was developed to characterize the copper seed layer along the TSV sidewalls, revealed higher microstructure quality, lower stressed in the case of copper film deposited by CVD compared to those deposited by i-PVD.
Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation
Authors: Bluck Terry , Smith Chris , Werbaneth Paul
Published: December 2018

Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. In fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. For these RDL barrier/seed layers, PVD cluster tools, wafer transport architectures that have been widely used since the mid-1980s, are the current Process of Record (POR) in advanced packaging; however, these tools typically operate in a regime where wafer transport is robot-limited to approximately 50 wafers per hour, which limits overall throughput and greatly influences Cost of Ownership (COO) for the sputter deposition step(s), because the central handling robot occupied with a transfer from the Ti PVD module to the Cu PVD module, for example, has no opportunity to be doing anything other than that specific transfer.

Other wafer transport architectures are more efficient from a wafer handling perspective. In linear transport carrier-based PVD tools, wafers or panels passing through the system benefit from a mechanical transfer time budget that is considerably less than for a cluster tool. Transport time overhead per wafer on linear transport systems is quite low, and scheduler software optimization becomes less onerous too, as a result of the simpler wafer transport architecture.

We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition process, and present details here of how the time spent moving wafers to various processing chambers affects overall system productivity. In the case of the cluster tool architecture, with its central wafer handling robot, wafer throughputs are approximately 50 wafers per hour, while on the linear transport system wafer throughputs as high as 240 wafers per hour are possible. The significant difference in system throughputs greatly affects the relative Cost of Ownership (COO) per wafer processed, with the linear transport system returning COO results that are less than half those of the typical cluster PVD tool.
Ultra-Wideband High Gain Vivaldi Antennas Using Additive Manufacturing
Authors: Ghazali Mohd Ifwat Mohd , Chahal Premjeet
Published: December 2018

In this paper, a low-cost fabrication technique using additive manufacturing (3D printing) is demonstrated for the fabrication of ultra-wide band (UWB) Vivaldi antennas. In communications, UWB antennas are required that have high gain and wide bandwidth (3.1 GHz to 10.6 GHz) enabling high-data rates and efficient use of frequency spectrum. 3D printing has evolved into an important technology that allows rapid and simple fabrication method for printing antennas, and other components. Two different Vivaldi antennas designs (i) Vivaldi with a slot line, and (ii) Corrugated Vivaldi are presented. The fabricated antennas have a wide bandwidth of 14 GHz and a high gain of 10 dBi. For example, the corrugated antenna exploits the capability of 3D printing to incorporate slots in the design that aids in low frequency matching with increased gain.
Aqueous Washable Thermal Resistant Coatings and Adhesives
Authors: Moore John
Published: December 2018

Many packaging processes require thin and fragile components to be protected or held securely in place for temporary periods of time. The most common process flow is to: apply the coating, cure or use to bond a device, conduct the process, and finish with removing the coating by washing in a liquid chemistry. Aqueous cleaning is deemed safer for devices on organic laminates and in the presence of molding compounds. These reagents use water as their major constituent. They are compatible with organic substrates (panels, laminates, boards), are worker safe, and require less expensive operating equipment. Aqueous washing is generally green and exempt from the complexity and cost of environmental and waste management regulations. Daetec's washable coatings qualify as green, and exhibit thermal resistance over 300°C, making them one of the most unique materials on the market. These coatings enable soldering, laser processing, plasma etching, and dielectric curing, all following with simple water washing. Water washable DaeCoatTM 525 is a key choice in laser processing for debris removal around the heat activation zone (HAZ), while the etch-resistant DaeCoatTM 534 supports laser patterning for plasma singulation [1]. While DaeCoatTM 532 is water soluble, another material from the same family, DaeCoatTM 537 is not, yet will wash away in an aqueous surfactant, DaeClean™ S20 (10% in water). In many ways, these products act, as surfactants, but depending upon the chemistry, will dissolve in water or an aqueous agent. Customers desiring a green protective coating or adhesive for plating or etching processes, may apply DaeCoatTM 537, send through the processes, and then wash away in the S20 aqueous agent. All products are cast from water. Film forms as 50μm thick with peel away liners are available for DaeCoatTM 532 and 537. UV curable high solids versions are also available. Applications include planarizing coatings, adhesive for die solder attach, and C4 or micro bump protection. Protective coatings for EMI/RFI shielding, dicing operations, and temporary bonding operations that may use porous carriers have been demonstrated with water washable coatings and adhesives. The success in these and related temporary applications depend upon the use of the proper washable coating. Our experience in creating solutions for these and other industry needs will be discussed as well as the criteria for using temporary washable coatings.
Molecular epidemiology of non-viral sexually transmitted infections in the central Alpine province of Bolzano, northern Italy from April 2016 to March 2017
Authors: Aschbacher Richard , Romagnoli Francesca , Masi Elisa , Pasquetto Valentina , Perino Franco , Eisendle Klaus , Braghetto Monica , Messini Sergio , Delbue Serena , Pagani Elisabetta
Published: December 2018

Chlamydia trachomatis, Neisseria gonorrhoeae, Trichomonas vaginalis, Ureaplasma parvum, Ureaplasma urealyticum, Mycoplasma hominis and Mycoplasma genitalium are established or presumed as (??) STI pathogens. The present study aims  at ng describing the one-year molecular epidemiology of these seven pathogens in the Province of Bolzano, Northern Italy. From April 2016 to March 2017, a total of  2,949 patients, mainly females, were enrolled and 3,427 urine, vaginal, endocervical and/or urethral samples were subjected to simultaneous analysis of the seven pathogens by means of Real Time Polymerase Chain Reaction (AnyplexTM II STI-7 Detection Kit Seegene, Seoul, Korea). At least one of the seven microorganisms was detected in 40.7% of patients, with an uneven distribution: 43.1% in females (F) and 29.8% (p<0.001) in males (M). The prevalence of microorganisms was as follows: 30.3% U. parvum (F: 35.6%, M: 8.3%), 6.9% U. urealyticum (F: 6.8%, M: 7.0%), 4.9% M. hominis (F: 5.4%, M: 2.3%), 4.9% C. trachomatis (F: 3.4%, M: 11.4%), 1.1% M. genitalium (F: 1.0%, M: 1.2%), 1.2% N. gonorrhoeae (F: 0.17%, M: 5.6%) and 0.40% T. vaginalis (F: 0.38%, M: 0.53%). Mixed infections were detected in 7.4% of patients. The highest prevalence was observed for U. parvum, followed by U. urealyticum and M. hominis and a significant  presence of multi-pathogen infections was registered.
Developing an assessment of epistemic trust: a research protocol
Authors: Schröder-Pfeifer Paul , Talia Alessandro , Volkert Jana , Taubner Svenja
Published: December 2018

Epistemic trust (ET) describes the willingness to accept new information from another person as trustworthy, generalizable, and relevant. It has been recently proposed that a pervasive failure to establish epistemic trust may underpin personality disorders. Although the introduction of the concept of ET has been inspiring to clinicians and is already impacting the field, the idea that there may be individual differences in ET has yet to be operationalized and tested empirically. This report illustrates the development of an Epistemic trust assessment and describes the protocol for its validation. The sample will include 60 university students. The Trier Social Stress Test for Groups will be administered to induce a state of uncertainty and stress, thereby increasing the relevance of information for the participants. The experiment will entail asking information from the participants about their performance and internal states during a simulated employment interview, and then tracking how participants are able to revise their own judgments about themselves in light of the feedback coming from an expert committee. To control for social desirability and personality disorder traits, the short scale for social desirability (Kurzskala Soziale Erwünschtheit-Gamma) and the Inventory of Personality Organization are utilized. After the procedure, the participants will complete an app-based Epistemic trust questionnaire (ETQ) app. Confirmatory Factor Analysis will be utilized to investigate the structure and dimensionality of the ETQ, and ANOVAs will be used to investigate mean differences within and between persons for ET scores by item category. This study operationalizes a newly developed ET paradigm and provides a framework for the investigation of the theoretical assumptions about the connection of ET and personality functioning.
Oriented mentalization-based treatment for borderline personality disorder patients: preliminary results at Camposampiero Mental Health Center
Authors: Carrera Stefano , Pandolfi Guia , Cappelletti Jee Yun , Padoani Walter , Salcuni Silvia
Published: December 2018

This contribution presents two brief reports about preliminary results of 18 months of oriented Mentalization-Based Treatment (MBT), with Borderline Personality Disorder patients, recruited at the Camposampiero Mental Health Center. Following in large part Bateman and Fonagy guidelines for MBT in institutional settings, this paper presents preliminary results in two brief reports related to two cohorts of patient underwent to the oriented MBT in Camposampiero Mental Health Center (MHC). In the first study, we analyzed a group of 9 patients: an anamnestic schedule was administered; then, symptoms (SCL-90-R), psychodiagnostic scale and global health functioning (Health of the Nation Outcome Scale, Structured Clinical Interview for DSM-IV Axis II Disorder [SCID-II], Global Assessment of Functioning, [GAF]), data on service impact and service costs (Cassel Community Adjustment Questionnaire, Patient Evaluation Schedule and folder data) were provided at the beginning (T0), at the end of the treatment (T2) and 1 year after the end of the MBT project. The second study showed a micro-analytical change on a second patient cohort (n=6) at T0, 3, 6 and 9 months (T1) were presented considering specifically mentalization (Comparative Psychotherapy Process Scale, Modes of Mentalization Scale, Mentalization Imbalances Scale) and patienttherapist session evaluation trends (Session Evaluation Questionnaire) and patient reflective functioning at T0 and T2 (Reflective Functioning Questionnaire). Aims and hypotheses of the two studies pointed out how the oriented MBT bring to an improvement of the overall functioning of the patients, a reduction of the symptoms, a decrease of the diagnostic criteria for the Borderline Personality Disorder (BPD) and the other Axis II disorders, a reduction of the workload hours for the MHC staff and of the costs of the assistance. The analyses of both the studies were carried out using non-parametric statistics (Friedman test, Spearman correlation, Chi-square). Preliminary results confirmed the improvement in the overall functioning of patients (GAF), the reduction in BPD-related symptoms and in diagnostic criteria for BPD (SCID-II), the improvement of patients’ mentalization skills, and a significant reduction in workload for health staff. Standing the limits and the preliminary results, the two brief reports demonstrate the feasibility of an oriented MBT within an Italian Public Service and the effectiveness of this treatment pathway for patients with BPD, leaving some open questions to stimulate a fruitful clinical discussion.