bluuebunny/crossref_metadata_2025 huggingface dataset:
Design of an LTCC Structure for a Micro-Ceramic Combustor
Authors: Belavic Darko , Hrovat Marko , Dolanc Gregor , Makarovic Kostja , Zarnik Marina Santo , Holc Janez
Published: October 2015

Advanced micro- or macro-systems are in some cases made with multilayer ceramic technology. Low-Temperature Co-fired Ceramic (LTCC) technology is considered as one of the more suitable technologies for the fabrication of ceramic micro-systems that integrate screen-printed, thick-film electronic components as well as three-dimensional buried structures, for example, cavities and channels. One of the applications is a ceramic combustor. The chemical energy of the fuel is converted into thermal energy in a chemical micro-combustor through a burning process, while the accompanying high temperatures and, frequently, high pressures impose harsh conditions on the combustor structure. Therefore, the combustor must be carefully designed not only from the functional, thermal and chemical points of view, but also with respect to the mechanical strength.

The combustor device was prepared by laminating of Du Pont 951PX LTCC green tapes. The fabricated 3D LTCC structures with buried cavities and channels including two inlets (for fuel and air), the evaporator for the fuel, the mixing system of the channels (for mixing the evaporated fuel and air), the distribution channels and eight microburners were realized. The main parts are eight micro-burners realized as buried cavities. In the burners a platinum-based catalyst was deposited to assist the oxidation, i.e., the burning, of the methanol with the air. Thickfilm, platinum-based heaters and temperature sensors are incorporated within the structure. The device was tested with different flow rates of liquid methanol (1 ml/h to 5 ml/h) and air (7 l/h to 15 l/h). The obtained temperatures were between 250°C and 450°C.
Combined 3D Micro Structuring of Ceramic Green Tape Using Punching, Embossing and Laser Processing
Authors: Hagen Gunter , Kopp Thomas , Ziesche Steffen , Partsch Uwe , Ruprecht Ester
Published: October 2015

Multilayer ceramics technology, as LTCC, offers several advantages for the fabrication of miniaturized three-dimensional structures, e.g. for microsystem applications, where electrical, mechanical and fluidic functions can be combined in robust and compact packages. 3D features, required by those applications, are e.g. vias for electrical and thermal interconnection, cavities for chip integration and channels for fluidic functions. They can be realized, in principle, in the sintered, as well as in the green state, but structuring in the green state dominates due to the then far better machinability of the material. Ceramic green tape structuring is usually accomplished by mechanical or laser machining. Punching is the standard process for realizing vias or cavities in LTCC. By nature, only through tape features can be realized, but 3D features can be realized by stacking of several layers. Embossing can be used for the realization of quite complex 3D structures with high resolution. It can be carried out either at elevated temperature, at which the binder of the tape is softened (hot embossing) or at room temperature (cold embossing). Laser structuring is a quite flexible method, which allows both through-cutting and engraving without any specific tool. However, a certain roughness of ablated areas cannot be avoided, and depth control and uniformity of laser engraved features remain challenging.

In the present paper, the different techniques will be compared regarding their appropriateness for different structuring tasks. A combined use of punching, embossing and laser processing is described, which has been made possible by a novel machine and tool concept.
Embedded Ferrite LTCC Inductors
Authors: Marić Andrea , Radosavljević Goran , Blaž Nelu , Smetana Walter , Živanov Ljiljana
Published: October 2015

This paper presents for the first time one realization of simple planar inductor realized inside the stack of ferrite LTCC (Low Temperature Co-fired Ceramic) tapes. Presented inductor is one layer square spiral fabricated in the LTCC technology. In order to point out benefits of implementation of ferrite material on inductor inductance, the same inductor geometry was fabricated between two dielectric LTCC tapes. Commercially available LTCC material (both ferrite and dielectric) were implemented for the realization of proposed inductors. Designed structures were characterized and obtained experimental results show that even implementation of a very thin layer of ferrite material around inductor lines drastically increases its inductance. For the same inductor design that occupies the same chip area the inductance enhancement over 11 times is achieved. In addition this enhancement is followed with maintenance of good performance of the inductor.
LTCC Based Multi-Electrode Arrays for In-Vitro Cell Culture
Authors: Bartsch Heike , Stöpel Dirk , Himmerlich Marcel , Baca Martin , Stadie Philipp , Hyttinen Jari , Müller Jens , Schober Andreas
Published: October 2015

Neurobiological concepts based on state-of-the art technology have so far lacked the complexity of actual high-level neurobiological systems. Two key advances are needed to improve our understanding of such systems: in vitro 3D-neuronal cell culture and 3D MEA systems for measuring such 3D-cultures. These requirements call for smart multilayer and packaging technology. The material Green Tape TM from DuPont Nemours is chosen for the presented works, because its compatibility and those of available metallisation with cell cultures is already proven. An LTCC multilayer circuit with gold electrodes is the base of the 3D MEA. The layout of the 3D MEA is designed to fit the MEA2100-System for in vitro recording from Multi Channel Systems and enable thus a comparable data processing to established 2D MEAs Slots. The surface topography of the thick film electrodes and the surface state is investigated with laser scanning microscopy, SEM, XPS and measurements of the wetting angle of contact. The impedance of the screen printed electrodes is discussed taking these data into account. Their impedance amounts to 24 kΩ and are falls thus below the impedance of commercially available electroplated gold electrodes of 30 kΩ. First promising results have been achieved using 3D MEAs for 2D culture of human pluripotent stem cell derived neural cells.
Novel thermoelectric temperature sensors
Authors: Rebenklau L. , Irrgang K. , Wodtke A. , Augsburg K. , Bechtold F. , Gierth P. , Grießmann H. , Lippmann L. , Niedermeyer L.
Published: October 2015

Nearly every industrial application needs temperature measurement. Typical temperature sensors are based on thermocouples or resistance elements. Nevertheless, these sensors are not always desired for every application. For example, temperature sensing of fluids or gases in pipes. A standard sensor inside such a material flow has an influence on the flow itself (flow resistance, turbulences) which would lead to incorrect temperature result. Additionally, application that need periodical cleaning of their pipe system (food or pharmaceutical production) can't use such sensors because of hygienically reasons. Novel thermoelectric temperature sensors, which could reduce the previously demonstrated problems have been developed as part of a research project. The basic idea of the novel sensor concept is to use thick film technology to enable novel sensor geometries. The typical use of thick film technology is realization of ceramic circuit boards, in which metal-based thick film pastes were screen printed and fired as conductive material. The sensor concept uses a combination of different commercially available metal-based pastes (platinum, silver, nickel, gold) to creates thermocouples based on the Seebeck effect.
Eutectic Zn-Al Die Attachment for Higher Tj SiC Power Applications: Fabrication Method and Die Shear Strength Reliability
Authors: Tanimoto Satoshi , Matsui Kohei , Zushi Yusuke , Sato Shinji , Murakami Yoshinori , Takamori Masato , Iseki Takashi
Published: October 2015

This paper comprehensively describes the fabrication method and shear strength reliability of a eutectic Zn-Al (m.p. = 382°C) attachment system, built by soldering SiC dies (2×2 mm2) onto Cu foil active-metal-brazed with a SiN ceramic plate. Four essential soldering conditions are presented and discussed for the formation of a strong and reproducible attachment. Die shear strength reliability data at Tj = 250°C are reported here for the first time. Storage tests at 250°C revealed that, after an initial slight decline, die shear strength stayed virtually constant at a sufficient level (∼110 MPa) for at least 3000 hours. Thermal cycle test results indicated that the attachments can withstand thermal cycle stress for 3000 cycles between −40°C and 250°C. The average die shear strength after 3000 cycles was 18.5 MPa, a value that is three times higher than the IEC standard of 6.2 MPa specified in Document 60749-19.
Performance and Reliability Characteristics of 1200 V, 100 A, 200°C Half-Bridge SiC MOSFET-JBS Diode Power Modules
Authors: Scofield James D. , Merrett J. Neil , Richmond James , Agarwal Anant , Leslie Scott
Published: October 2015

A custom multi-chip power module packaging was designed to exploit the electrical and thermal performance potential of silicon carbide MOSFETs and JBS diodes. The dual thermo-mechanical package design was based on an aggressive 200°C ambient environmental requirement and 1200 V blocking and 100 A conduction ratings. A novel baseplate-free module design minimizes thermal impedance and the associated device junction temperature rise. In addition, the design incorporates a free-floating substrate configuration to minimize thermal expansion coefficient induced stresses between the substrate and case. Details of the module design and materials selection process will be discussed in addition to highlighting deficiencies in current packaging materials technologies when attempting to achieve high thermal cycle life reliability over an extended temperature range.
High Temperature Dynamic Pressure Measurements Using Silicon Carbide Pressure Sensors
Authors: Okojie Robert S. , Meredith Roger D. , Chang Clarence T. , Savrun Ender
Published: October 2015

Un-cooled, MEMS-based silicon carbide (SiC) static pressure sensors were used for the first time to measure pressure perturbations at temperatures as high as 600 °C during laboratory characterization, and subsequently evaluated in a combustor rig operated under various engine conditions to extract the frequencies that are associated with thermoacoustic instabilities. One SiC sensor was placed directly in the flow stream of the combustor rig while a benchmark commercial water-cooled piezoceramic dynamic pressure transducer was co-located axially but kept some distance away from the hot flow stream. In the combustor rig test, the SiC sensor detected thermoacoustic instabilities across a range of engine operating conditions, amplitude magnitude as low as 0.5 psi at 585 °C, in good agreement with the benchmark piezoceramic sensor. The SiC sensor experienced low signal to noise ratio at higher temperature, primarily due to the fact that it was a static sensor with low sensitivity.
Nanocomposite Film Dielectrics for High Temperature Power Conditioning Capacitors
Authors: Slenes Kirk , Bragg Lew
Published: October 2015

Emerging power electronics in a broad range of military, aerospace, hybrid vehicle, renewable energy and drilling applications rely on advances in dielectric materials for capacitors. Compact capacitors possessing low dielectric loss and high operating temperature capability are needed for power conditioning in advanced converter and inverter designs for these applications. Wound film capacitors represent the preferred capacitor technology but are limited by low operating temperature capabilities, < 150°C, and low volumetric efficiency, capacitance per unit volume less than 1.0 μF/cc.

TPL is developing processes and manufacturing techniques for fabrication of advanced capacitor films comprised of high temperature polymers modified with ceramic nanoparticles. The selected polymers enable high temperature operation and the ceramic nanoparticles enhance volumetric efficiency by increasing the dielectric constant. The fabricated films are directly adaptable to conventional wound film capacitor construction methodologies.

This paper provides an overview of TPL's experience to-date with a film dielectric material system comprised of fluorenone polyester polymer and titanate nanoparticle filler. The fluorenone polyester polymer was selected to provide a stable operating temperature of at least 300°C, while the addition of the titanate powder increases the dielectric constant and, in turn, the volumetric efficiency of wound film capacitors constructed with this film system. Status and ongoing capacitor development issues are provided relative to the intended high temperature power conditioning applications.
Thin Film Multichip Packaging for High Temperature Digital Electronics
Authors: Fang Kun , Zhang Rui , Isaacs-Smith Tami , Johnson R. Wayne , Andarawis Emad , Vert Alexey
Published: October 2015

Digital silicon carbide integrated circuits provide enhanced functionality for electronics in geothermal, aircraft and other high temperature applications. A multilayer thin film substrate technology has been developed to interconnect multiple SiC devices along with passive components. The conductor is vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride is used for the interlayer dielectric. Adhesion testing of the conductor and the dielectric was performed as deposited and after aging at 320°C. The electrical characteristics of the dielectric as a function of temperature were measured.

Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Since polymer underfills are not compatible with 300°C operation, AlN was used as the base ceramic substrate to minimize the coefficient of thermal expansion mismatch between the SiC die and the substrate. Initial die shear results are presented.
Gate Stack Engineering for High Temperature Silicon Carbide CMOS ICs
Authors: Weng M.H. , Murphy A.D. , Clark D.T. , Smith D.A. , Thompson R.F. , Young R.A.R. , Ramsay E.P. , Chan H.K. , Horsfall A.B.
Published: October 2015

The potential to thermally grow SiO2 on silicon carbide has resulted in it becoming the technology of choice to realise high temperature CMOS circuits. The challenge to achieve a high quality gate stack relies on engineering the metal-insulator-semiconductor interfaces to enable reliable high temperature functionality. Here we describe the effect of different process conditions for the formation of the dielectric layer on the characteristics of the resulting devices. The operating characteristics at elevated temperatures depend critically on the quality of the gate stack. Therefore a systematic evaluation of the intrinsic properties of the gate stack and data from reliability tests are needed.
Reliability of High Temperature Laminates
Authors: Shaddock David , Yin Liang
Published: October 2015

Printed circuit boards have been reported to have limited lifetime at 200 to 250°C. Characterization of high temperature laminates for application at 200 to 250°C was conducted to better quantify their lifetime using accelerated testing of key functional parameters. Eight high temperature laminates consisting of 3 material types was evaluated. Life testing was applied for via cyclic life, weight loss, peel strength, and surface insulation resistance. Via lifetime was characterization using Interconnect Stress Test (IST) coupons. Weight loss was measured at intervals during the life of the tests. Peel strength was tested using IPC IPC-TM-650 method 2.4.8c. Weight loss was characterized using isothermal aging. Comparison of lifetime is made between the laminate samples. The non-polyimide laminates exhibited the longer life times than polyimide laminates in most tests except peel strength. Peel strength is the life limiting parameter for the laminates. Parylene HT was found to improve stability in peel strength and weight loss of one PTFE laminate tested.
Packaging technologies for high temperature control electronics
Authors: Slater Conor , Cojbasic Radisav , Maeder Thomas , Leblebici Yusuf , Ryser Peter
Published: October 2015

Current low temperature electronics (<175°C) with logical functions (CPUs, MCUs) have exceptional levels of reliability in terms of packaging, stemming from decades of research. However, electronics that operate at higher temperatures (>175°C) for prolonged periods of time require packaging technologies that have to tackle many new problems. At high temperatures traditionally used materials such as organic circuit boards, adhesives and standard solders degrade rapidly or undergo changes in structure and properties. An even more critical issue than high-temperature survivability is resistance to temperature cycling. Thermal mismatch between organic boards and semiconductor dies leads to high thermomechanical strains during swings from high to low temperature extremes, which can make an otherwise high temperature resistant assembly fail after a relatively low number of cycles. This work focuses on the packaging technologies for high temperature control modules, those with logical and signal conditioning applications. Although control modules share many similarities with power modules, they present their own unique design challenges, such as significantly higher complexity and a limitation of compatible materials. Here, recent research on substrates, die attach technologies and wirebond interconnects suited for high temperature ICs are presented along with packaging technologies for discrete components (capacitors and resistors) with the aim of identifying the current best solutions. Test vehicles for the various technologies were constructed and were subjected to high temperature storage at temperatures higher than 200°C. They were analysed in terms of degradation (i.e. loss in shear strength, pull strength, change in resistance, etc.). In parallel, a separate set of samples were subjected to temperature cycles from −20°C to 180°C and then analysed using the same tests as before for comparison. The combined data allow a recommendation to be made on how to assemble a viable control module such as one based on an SOI microcontroller designed at EPFL to operate at high temperatures.
A 4H-SiC Bipolar Technology for High-temperature Integrated Circuits
Authors: Lanni L. , Malm B. G. , Zetterling C.-M. , Östling M.
Published: October 2015

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on Aluminium and Platinum. Successful operation of low-voltage bipolar transistor and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27 up to 500 °C for both the metallization systems. When operated on −15 V supply voltage, Aluminium and Platinum OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of Aluminium and Platinum interconnect were evaluated by performing accelerated electromigration tests at 300 °C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors.
Structural Electronics through Additive Manufacturing and Micro-Dispensing
Authors: Olivas Richard , Salas Rudy , Muse Dan , MacDonald Eric , Wicker Ryan , Newton Mike , Church Ken
Published: October 2015

Implementing electronics systems that are conformal with curved and complex surfaces is difficult if not impossible with traditional fabrication techniques, which require stiff, two dimensional printed circuit boards (PCB). Flexible copper based fabrication is currently available commercially providing conformance, but not simultaneously stiffness. Consequently, these systems are susceptible to reliability problems if bent or stretched repeatedly. The integration of Additive Manufacturing (AM) combined with Direct Print (DP) micro-dispensing can provide shapes of arbitrary and complex form which incorporate 1) miniature cavities for insetting electronic components and 2) conductive traces for electrical interconnect between components. The fabrication freedom introduced by AM techniques such as stereolithography (SL), ultrasonic consolidation (UC), and fused deposition modeling (FDM) have only recently been explored in the context of electronics integration. Advanced dispensing processes have been integrated into these systems allowing for the introduction of conductive inks to serve as electrical interconnect within intricately-detailed dielectric structures. This paper describes a process that provides a novel approach for the fabrication of stiff conformal structures with integrated electronics and describes several prototype demonstrations: a body conformal helmet insert for detection of Traumatic Brain Injury (TBI), a 3D magnetic flux sensor with LED indicators for magnitude and direction and a floating sensor capable of detecting impurities in water while maintaining orientation through density gradients.
Counterfeit Detection Strategies: When to Do It / How to Do It
Authors: Caswell Greg
Published: October 2015

Counterfeit components have been defined as a growing concern in recent years as demand increases for reducing costs. In fact the Department of Commerce has identified a 141% increase in the last three years alone. A counterfeit is any item that is not as it is represented with the intention to deceive its buyer or user. The misrepresentation is often driven by the known presence of defects or other inadequacies in regards to performance. Whether it is used for a commercial, medical or military application, a counterfeit component could cause catastrophic failure at a critical moment.

The market for long life electronics, based on commercial off the shelf (COTS) parts, such as those used in medical, military, commercial depot repair, or long term use applications (e.g. street and traffic lights, photovoltaic systems), seems to create a perfect scenario for counterfeiters. With these products, components wear out and need to be replaced long before the overall product fails. The availability of these devices can be derived in many ways. For example, a typical manufacturer may render a component obsolete by changing the design, changing the functionality, or simply discontinuing manufacture. Also, the parts that are available after a design has been discontinued are often distributed by brokers who have very little control over the source or supply. Recycling of devices has also emerged as a means of creating counterfeit devices that are presented as new. And finally, as demand and price increase, the likelihood of counterfeits also increases.

This paper will address the four unique sources of counterfeit components and insight into how they occur. Detection methodologies, such as visual inspection, mechanical robustness, X-Ray, XRF, C-SAM, Infrared Thermography, electrical characterization, decapsulation, and marking evaluations, will be compared and contrasted, as well as multiple examples of counterfeit parts identified by DfR.
Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS® Finite Element Analysis
Authors: Mallik Aditi , Stout Roger
Published: October 2015

Wafers warp. It is important to minimize warpage in order to achieve optimal die yield and potentially prevent future device failure. Although the word warpage is widely used in the literature to represent wafer bow (convex or concave shape), in the real world wafers are often seen into warp into saddle shapes. This complicates the characterization of both the sources of and solutions to warpage, because (as will be discussed) Stoney's formula (relating intrinsic stress and curvature) does not apply for structures warped with compound curvature, and standard wafer warpage measurements are not designed to measure compound curvature. During thin film deposition, wafer warpage occurs due to the intrinsic stresses and the coefficient of thermal expansion (CTE) mismatch of the different thin films and the substrate. Unfortunately, whereas the introduction of the thermal stresses due to CTE mismatch into a finite element model is easily understood, the introduction of intrinsic stress is not. Further, although a saddle shape is clearly a physically realizable (indeed, often preferred) equilibrium configuration for a circular disk (consistent with an appropriate state of stress), obtaining a saddle shape in a finite element solution turns out to be extremely difficult, as convex or concave shapes may also be stable and numerically preferred. In this paper, a finite element technique (using ANSYS software) to model wafer warpage is presented. Simulations have been done for silicon wafers with aluminum or standard UBM films on top. Saddle-shaped warpage has been successfully modeled, and the aggravating effects of thinning (back side grinding) have been reproduced.
Packaging in IBIS-AMI Technology
Authors: Dvorscak Daniel , Becker Dale , Cocchini Matteo , Pytel Steven G. , Waldron Isaac , Kirsanov Danil
Published: October 2015

As serial links become faster and more complex, it is ever more challenging to model the silicon in an accurate and efficient manner. Traditional IBIS package models are simply not accurate enough and lack the bandwidth required for high-speed serial channels. The IBIS Algorithmic Modeling Interface (AMI) is a promising standard that is able to accurately model drivers and receivers that include equalizers and clock data recovery circuits. The introduction of the AMI modeling standard presents the opportunity to combine accurate driver and receiver models with high quality scattering parameter and W-element models of the passive IC, package, and PCB structures. In this paper we explore simulation with AMI models driving accurate high-bandwidth channel models of packages and printed circuit boards for robust simulation of high-speed serial systems. We also use these simulations to investigate the effects of variability in the manufactured channel.
Transfer molding technology for smart power electronics modules - materials and processes
Authors: Becker K.-F. , Joklitschke D. , Braun T. , Koch M. , Thomas T. , Schreier-Alt T. , Bader V. , Bauer J. , Nowak T. , Bochow-Ness O. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D.
Published: October 2015

During the last years within power electronics packaging a trend towards compact power electronics modules for automotive and industrial applications could be observed, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics yielding maximum miniaturization. Transfer molding is the method of choice for cost effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package:

Typically those packages are asymmetric, a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed providing a heat path for optimized cooling. This asymmetric geometry is prone to yield warped substrates, preventing optimum thermal contact to the heatsink and also putting thermomechanical stress on the encapsulated components, possibly reducing reliability.

Such packages being truly heterogeneous, combining powerICs, wire bonds, SMDs, controlICs, substrate and leadframe surfaces, the encapsulant used needs to adhere sufficiently to all surfaces present.

Additionally those packages need to operate at elevated temperatures for increased times, e.g. operate at 150 °C for 2000 h and more, so high thermal stability is of ample importance.

Within this paper a reference application is described, integrating power and control logic inside a leadframe based molded package. Taking into account the challenges mentioned above, a detailed description of material selection for this module will be given, including material analysis as rheology, reactivity, change in ɛr and thermomechanical properties as f(t,T) and of media storage. Process development tools for module molding are used to ensure manufacturability and useability. Concluding rules for encapsulant material selection and package setup are provided.
Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm
Authors: Oppert Thomas , Dohle Rainer , Franke Jörg , Härter Stefan
Published: October 2015

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process.

To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively.

Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide.

The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1].

Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.
Case Study: Radial Cracks in a Rigid-Flex Assembly
Authors: Matsuoka Christopher
Published: October 2015

Crane Aerospace & Electronics in Redmond, WA, develops, qualifies, and manufactures a variety of implantable devices for leading medical companies. An unusual phenomenon was discovered during a routine visual inspection step on a recent development project. On the flexible portion of a rigid-flex PCB assembly, visible radial cracks were found on the annular rings of ENIG-plated thru-holes. The thru-holes remain unpopulated during Crane’s assembly process, and the defect was primarily seen on the top side of the PCB. Additionally, the occurrences of these cracks vary in frequency and severity. This paper describes the testing and analysis Crane performed in order to determine the root cause of this defect.
Towards highly conductive silver pastes for LTCC power electronics
Authors: Eberstein Markus , Kretzschmar Christel , Seuthe Thomas , Marcinkowski Manja , Ihle Martin , Ziesche Steffen , Partsch Uwe , Gora Frieder
Published: October 2015

The realization of high current conductors in LTCC multilayer architectures was studied. By mixtures of spherical silver powders, maximum tap densities above 7 g/cm3 could be obtained. On pressed cylinders a good correlation between tap density and total shrinkage was found. Pastes were made of the highly packed silver powders and detailed investigations regarding paste sintering kinetics and interactions between paste ingredients among one another as well as between paste ingredients and LTCC substrates were made. The pastes did not show a pronounced correlation between tap density and total densification. With increasing solid content of the pastes, the shrinkage printed-dry, the shrinkage dry-fired and the specific sheet resistance decreases. These findings can be used to control the filling degree of channels or grooves as well as the properties of the fired conductor. Expansion effects of the pure silver powders during sintering could be correlated to gas pressure effects, whereby there are obviously different kinds of gas formation in fine and coarse powders. Avoiding of camber of freely sintered LTCC should be attained if new LTCC materials are showing different sintering behavior, e. g. strong and early crystallization building of diffusion barriers or the possession of a glass phases which will not incorporate silver oxide. Research on this target should be done. The realization of high current conductors in constrained sintered LTCC was successfully shown. A paste comparable to standard values for direct copper bond (DCB) substrates with a thickness 35 μm of 0,48 mOhm/sq is introduced
Build-up Electrical Insulation Material with Low-Dielectric Loss Tangent, Low-CTE and Low-Surface Roughness
Authors: HORIKI Eita , SUZUKI Isao , TANAKA Toshiaki , UENISHI Akihiro , KOUYANAGI Hiroshi
Published: October 2015

With the increasing speed of information and communication equipments in recent years, together with the high-speed signal processing of LSIs, there is a requirement for build-up electrical insulation materials (used in IC package substrates) to have low-dielectric loss tangent which reduces dielectric loss so as to achieve low transmission loss in the high-frequency GHz bands. At the same time, there is an increasing need for materials to have low-CTEs (Coefficient of Thermal Expansion) so as to ensure highly reliable substrates.

With ou formulation technology, we have developed a next-generation film-shaped build-up electrical insulation material compatible with high-frequency signal transmission by using a composition of practical thermosetting epoxy resin, which has realized both a low-dielectric loss tangent and at the same time, a low-CTE.

In addition, this material can show a low-surface roughness after the film desmear process. It is thus expected to help reduce not only dielectric loss by means of a low-dielectric loss tangent, but also conductor loss caused by the skin effect, and will promote fine line formation by means of SAP (Semi Additive Process).
European R&D Trends in wire bonding technologies
Authors: Schneider-Ramelow M. , Göhre J.-M. , Geißler U. , Schmitz S. , Lang K.-D.
Published: October 2015

Asian industry and development is currently very focused on replacing extremely expensive Au wire with Cu or Pd-plated Cu in IC (mass production) packaging technologies (ball/wedge bonding). In contrast, Europe traditionally is researching and developing in the field of wedge/wedge bonding using heavy wire (> 100 μm) for power electronic modules or standard (thin) wire (< 100 μm, mostly 25–50 μm) for chip-on-board (COB) applications.

One primary failure mechanism limiting the lifetime of power modules is Al wedge lift-off due to the different coefficients of thermal expansion (CTE) of the Al wedge and the chip (Si). This classical type of fatigue cracking can be reduced by using materials of higher strength and/or lower CTE. Key strategies include doping or alloying elements and/or optimizing bonding conditions to improve the microstructure. Cu-based wire or Cu-Al bimetal ribbons are another option, although these include changes to the chip structure and metallization.

AlSi1 has been the industry standard bonding material in wedge/wedge thin wire bonding for many years. Its thermal stability is limited at temperature above ≈100°C due to recrystallization, grain growth and Si coagulation. For example, glob top material curing processes used in chip on board (COB) applications (e.g. several hours at 160°C) can decrease the strength of standard AlSi1 wire to less than 60% of its original value. Research and development is currently attempting to improve this situation by alloying and doping Al base material to increase high-temperature behavior or by using Al-coated Au or Cu wires.

The presentation will give an overview of alternative wedge/wedge wire bonding materials and discuss the challenges to processing and reliability.
Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application
Authors: Wu Sheng-Tsai , Lau John H. , Chien Heng-Chieh , Chao Yu-Lin , Tain Ra-Min , Li Li , Su Peng , Xue Jie , Brillhart Mark
Published: October 2015

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.
Through-Silicon-Via (TSV) for silicon package: ″via-bridge″ approach
Authors: Lamy Y. , Joblot S. , Ferrandon C. , Carpentier J.F. , Simon G.
Published: October 2015

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The top via is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with high temperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs (short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer is backgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE process create the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cu plating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle (AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. The mechanical simulations show that this ″TSV bridge″ has reduced residual stresses inside the TSV. Our electrical measurements exhibit an average single TSV resistance below 10mOhms with excellent yield (∼95% on Kelvin and 82 TSV chains), and low contact resistances (4.7×10−9 Ω.cm2) extrapolated on 4 different contact diameters. This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.
Scallop Free Si Etching and Low Cost Integration Technologies for 2.5D Si Interposer.
Authors: Morikawa Yasuhiro , Murayama Takahide , Sakuishi Toshiyuki , Nakamura Toshiyuki , Kurimoto Takashi , Nakamuta Yuu , Kimura Isao , Suu Koukou
Published: October 2015

In order to realize the manufacturing and cost benefits of via middle and via last technology for the 3D stacked integration, creation of through silicon via (TSV) spanning all layers of fully formed chips must be realized. This is particularly new etching method challenging for TSV devices. The etch system is new TSV etcher that is a kind of high electron density ICP / NLD. In this paper, study on non Bosch Si etch method to get a smooth sidewalls with no scalloping and a good control of the etched profile using new planar ICP plasma, and trying high selectivity to photo-resist mask for TSV etching to provide the total lowest cost processes.
Thermal Cycling Reliability of Alternative Low-Silver Tin-based Solders
Authors: George Elviz , Osterman Michael , Pecht Michael , Coyle Richard , Parker Richard , Benedetto Elizabeth
Published: October 2015

Sn-3.0Ag-0.5Cu (SAC305) alloy is the most widely used solder in electronic assemblies. However, issues associated with cost and drop/shock durability have resulted in a continued search for alternative solder alloys. One approach to improve the drop/shock reliability has been to reduce the silver content in Sn-Ag-Cu alloys. Another approach is doping Sn-Ag-Cu solder with additional elements. Moreover, conflicting results have been reported in literature on the effects of aging on Sn-Ag-Cu alloys. In 2008, International Electronics Manufacturing Initiative (iNEMI) started the “Characterization of Pb-Free Alloy Alternatives” project to provide a comprehensive study of fifteen tin-based solder interconnect compositions benchmarked against the eutectic tin-lead solder. For this study, temperature cycle durability was the primary focus and solders were selected to study the effect of varying silver content, microalloy additions, and aging. This paper reports the preliminary findings from one of the test conditions conducted under the iNEMI project. The cycles to failure for a temperature cycling test condition from −15°C to 125°C, with dwell times of 60 minutes at both extremes are presented. The test assembly consisted of sixteen 192 I/O BGAs and sixteen 84 I/O BGAs soldered on to LG451HR laminate. Preliminary findings revealed that the reduction of silver resulted in a reduction in cycles to failure. In all cases, the fifteen tin-based solders were more durable than the eutectic SnPb solder. Aging did not affect the cycles to failure in SAC105 solder; however, the cycles to failure decreased with aging in SAC305 solder. In addition, aging resulted in a wider distribution of cycles to failure in 192 I/O BGAs.
Voiding and Reliability of Assembly of BGA with SAC and 57Bi42Sn1Ag Alloys
Authors: Liu Yan , Keck Joanna , Page Erin , Lee Ning-Cheng
Published: October 2015

Low melting 57Bi42Sn1Ag (BiSnAg) was explored for replacing SAC solders as a low-cost solution. In this study, BGAs with SAC105, SAC305, and BiSnAg balls were assembled with SAC105, SAC305 or 57Bi42Sn1Ag solder paste. Joint mechanical strength, drop test performance, and voiding performance were evaluated against the reflow profile. SnPb was included as a control. The findings are as follows: (1) The microstructure of solder joints showed that, among all of the combinations, only BiSnAg-105 LT and BiSnAg-305 LT exhibited well-distinguishable alloy regions. For SAC-BiSnAg systems, Sn-dendrites were noticeable at LT, while Ag3Sn needles developed at HT. The joints were homogeneous for the rest of the combinations. (2) In the shear test, combinations involving BiSnAg solder were brittle, regardless of the Bi alloy location and reflow profile, as evidenced by stress-strain curves and morphology of the ruptured surface. The strong influence of Bi on the rupture site may have been caused by the stiffening effect of solder due to the homogenized presence of Bi in the joint. With the stiffened solder, the brittle IMC interface became the weakest link upon shearing, although the brittle BiSn crystalline structure also contributed to the rupture. (3) In the drop test, all Bi-containing solder joints performed poorly compared with Bi-free systems, which was consistent with shear test results. Drop numbers increased with increasing elongation at break of solder bumps as measured in the shear test. (4) Voiding was affected by flux chemistry and reduced by low alloy homogenization temperatures and solid top factors, but was increased by low surface tension factor, melting sequence factor, overheating factor and wide pasty range factor. Compared to SAC or SnPb systems, the BiSnAg system is low in voiding if reflowed at LT. In this study, voiding had an insignificant effect on shear strength and drop test performance.
Improved compensation for a reduction stepper to meet the challenges for advanced packaging applications
Authors: Webb James E , Gardner Steven , DaSilveira Elvino
Published: October 2015

Advanced packaging manufacturers require steppers that will provide solutions for the challenges encountered with new advances in wafer-level packaging technologies such as TSV, eWLB, silicon and glass interposers being utilized in leading edge mobile devices. Step and repeat photolithography systems capable of finer imaging with tighter overlay are being introduced to meet the challenging manufacturing requirements associated with the mix and match needed for volume production on larger wafers.

A 2X reduction stepper with unique features incorporated that extend the range of compensation is necessary to achieve the tighter specifications needed for many advanced packaging applications printed on 300 to 450mm wafers. A high throughput projection optical system is used to expose circuit patterns from a reticle mask onto a substrate to image features with the optimal fidelity required for advanced packaging technologies. The camera incorporates 350–450nm light from a mercury arc lamp that is transmitted through the mask containing circuit patterns. The imaging field prints a large 52mm × 66mm area in a single exposure. These features enable a system to process wafers in fewer shots which result in higher throughput using lower power.

Substrates are positioned with a precise X, Y, Θ stage by locating marks using an off-axis, bright field alignment system with fully trainable mark feature capability. The approach results in precisely placed features within a layer and from layer to layer without directly referencing the reticle. The integrated metrology and precision positioning subsystem technologies are combined with a low distortion projection lens and a wide range of adjustments, allowing the stepper to be integrated into a production line in a mix and match setup with other lithography systems. This equipment can be used to image critical layers on substrates while ensuring grid registration and alignment with other lithography systems that are also printing images in the same process line.

Several important global and intra-field image placement relationships for devices requiring multiple layer patterning have been combined in the stepper matching correction software. Further adjustment to the tool can be made to improve overlay when incorporated with fab-wide yield management software for automated, real-time process control. The types of adjustments needed and techniques that can be applied to compensate for image placement errors over large areas are discussed.