bluuebunny/crossref_metadata_2025 huggingface dataset:
Artifact systems with data dependencies and arithmetic
Authors: Damaggio Elio , Deutsch Alin , Vianu Victor
Published: September 2012

We study the static verification problem for data-centric business processes, specified in a variant of IBM's “business artifact” model. Artifacts are records of variables that correspond to business-relevant objects and are updated by a set of services equipped with pre- and postconditions, that implement business process tasks. The verification problem consists in statically checking whether all runs of an artifact system satisfy desirable properties expressed in a first-order extension of linear-time temporal logic. Previous work identified the class of
guarded
artifact systems and properties, for which verification is decidable. However, the results suffer an important limitation: they fail in the presence of even very simple data dependencies or arithmetic, both crucial to real-life business processes. In this article, we extend the artifact model and verification results to alleviate this limitation. We identify a practically significant class of business artifacts with data dependencies and arithmetic, for which verification is decidable. The technical machinery needed to establish the results is fundamentally different from previous work. While the worst-case complexity of verification is nonelementary, we identify various realistic restrictions yielding more palatable upper bounds.
Report from the first international workshop on realizing artificial intelligence synergies in software engineering (RAISE 2012)
Authors: Harrison Rachel , da Cruz Daniela , Henriques Pedro , Pereira Maria João Varanda , Liu Shih-Hsi , Menzies Tim , Mernik Marjan , Rodriguez Daniel
Published: September 2012

The aim of the Realizing Artificial Intelligence Synergies in Software Engineering (RAISE) series of workshops is to provide a forum for researchers and industry practitioners to exchange and discuss the latest innovative synergistic AI and SE techniques and practices. Namely, we are interested in AI solutions to SE problems and SE practices to answer AI obstacles, and techniques that could benefit these realms bidirectionally. This report summarizes the First International RAISE Workshop and indicates some future activities.
Deployment of formal methods in industry
Authors: Romanovsky Alexander
Published: September 2012

The work of the major
EU-funded ICT
DEPLOY Integrated Project (February 2008 -- April 2012) on Industrial Deployment of Advanced\ System Engineering Methods for High Productivity and Dependability [1] was driven by the tasks of achieving and evaluating industrial takeup, initially by DEPLOY industrial partners, of DEPLOY methods and tools, together with the necessary further research on methods and tools. Our previous SEN paper [2] introduced the project. The project has been one of the most significant efforts ever focusing on understanding the issues researchers and engineers face during the deployment of formal methods. This paper briefly reports on the project legacy and provides pointers to the various sources of information produced by the project.
Avoidance of security breach through selective permissions in android operating system
Authors: Sekar Lakshmi Priya , Gankidi Vinitha Reddy , Subramanian Selvakumar
Published: September 2012

The current Android application framework has an "all or none" permission policy, viz., an application can be installed if and only if all the permissions are granted. Also, no provision exists to deny granted permissions after installation. Therefore, any application can misuse the granted permission. CyanogenMod addresses this issue by denying the unwanted permissions which might cause the application to crash. WhisperCore, has worked on this problem but the working model is unavailable at the moment. APEX, also is currently doing some research on this issue but there is no publicly available document.

In this paper, the problem of misusing the granted permission n in Android is addressed and a novel idea of 'shadow manifest' is proposed. The proposed shadow manifest is implemented by creating a novel Content Provider, viz., SelPermProvider, which hosts the user permissions. In general, during the resource request phase, the system manifest is checked and the resources are allocated. But, in our implementation, the control is altered to flow through the shadow manifest after the system manifest is checked. If the query to shadow manifest is TRUE, then the resource is granted else a dummy or null value is returned. This facilitates the user to identify the malware and block the malware from achieving the intended task. Thus, the application is unaware of the indirect permission denial and continues to run normally. The user can decide which permission to restrict by checking a log of all recent permission requests, a facility provided in our app.

The proposed shadow manifest has been implemented and tested using an application called 'Contacts_Retrieve'. It was found to successfully complete the application if the shadow manifest returned TRUE, and unsuccessfully complete otherwise.
On a new masters level program in software engineering
Authors: Solomon A. D.
Published: September 2012

In a 1998 note [1] I described a new study program leading to the Bachelor's Degree in Software Engineering. I now report on a new Master's level program in Software Engineering evolving from the Bachelor's Degree program, and beginning in the fall semester of this year. I discuss some of the events of our 14 year old Bachelor's program, and the structuring of our Master's program.
Challenges in building a real, large private cloud
Authors: Kotsovinos Evangelos
Published: September 2012

Virtualization and internal cloud are often touted as the solution to many challenging problems, from resource underutilization to data-center optimization and carbon emission reduction. However, the hidden costs of cloud-scale virtualization, largely stemming from the complex and difficult system administration challenges it poses, are often overlooked. Reaping the fruits of internal Infrastructure as a Service cloud requires the enterprise to navigate scalability limitations, revamp traditional operational practices, manage performance, and achieve unprecedented cross-silo collaboration.
CompSC
Authors: Pan Zhenhao , Dong Yaozu , Chen Yu , Zhang Lei , Zhang Zhijiao
Published: September 2012

Live migration is one of the most important features of virtualization technology. With regard to recent virtualization techniques, performance of network I/O is critical. Current network I/O virtualization (e.g. Para-virtualized I/O, VMDq) has a significant performance gap with native network I/O. Pass-through network devices have near native performance, however, they have thus far prevented live migration. No existing methods solve the problem of live migration with pass-through devices perfectly.

In this paper, we propose CompSC: a solution of hardware state migration that will enable the live migration support of pass-through devices. We go on to apply CompSC to SR-IOV network interface controllers. We discuss the attributes of different hardware states in pass-through devices and migrate them with corresponding techniques. Our experiments show that CompSC enables live migration on an Intel 82599 VF with a throughput 282.66% higher than para-virtualized devices. In addition, service downtime during live migration is 42.9% less than para-virtualized devices.
DDGacc
Authors: Pavlou Demos , Gibert Enric , Latorre Fernando , Gonzalez Antonio
Published: September 2012

Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualization. However, the software layer in such systems introduces non-negligible overheads which affect performance and user experience. Hence, reducing DBT/DBO overheads is of paramount importance. In addition, reduced overheads have interesting collateral effects in the rest of the software layer, such as allowing optimizations to be applied earlier. A cost-effective solution to this problem is to provide hardware support to speed up the primitives of the software layer, paying special attention to automate DBT/DBO mechanisms and leave the heuristics to the software, which is more flexible. In this work, we have characterized the overheads of a DBO system using DynamoRIO implementing several basic optimizations. We have seen that the computation of the Data Dependence Graph (DDG) accounts for 5%-10% of the execution time. For this reason, we propose to add hardware support for this task in the form of a new functional unit, called DDGacc, which is integrated in a conventional pipeline processor and is operated through new ISA instructions. Our evaluation shows that DDGacc reduces the cost of computing the DDG by 32x, which reduces overall execution time by 5%-10% on average and up to 18% for applications where the DBO optimizes large code footprints.
Unpicking the knot
Authors: Lin Yi , Blackburn Stephen M. , Frampton Daniel
Published: September 2012

Flexible and efficient runtime design requires an understanding of the dependencies among the components internal to the runtime and those between the application and the runtime. These dependencies are frequently unclear. This problem exists in all runtime design, and is most vivid in a metacircular runtime --- one that is implemented in terms of itself. Metacircularity blurs boundaries between application and runtime implementation, making it harder to understand and make guarantees about overall system behavior, affecting isolation, security, and resource management, as well as reducing opportunities for optimization. Our goal is to shed new light on VM interdependencies, helping all VM designers understand these dependencies and thereby engineer better runtimes. We explore these issues in the context of a high-performance Java-in-Java virtual machine. Our approach is to identify and instrument transition points into and within the runtime, which allows us to establish a dynamic execution context. Our contributions are: 1) implementing and measuring a system that dynamically maintains execution context with very low overhead, 2) demonstrating that such a framework can be used to improve the software engineering of an existing runtime, and 3) analyzing the behavior and runtime characteristics of our runtime across a wide range of benchmarks. Our solution provides clarity about execution state and allowable transitions, making it easier to develop, debug, and understand managed runtimes.
Simultaneous branch and warp interweaving for sustained GPU performance
Authors: Brunie Nicolas , Collange Caroline , Diamos Gregory
Published: September 2012

Single-Instruction Multiple-Thread (SIMT) micro-architectures implemented in Graphics Processing Units (GPUs) run fine-grained threads in lockstep by grouping them into units, referred to as warps, to amortize the cost of instruction fetch, decode and control logic over multiple execution units. As individual threads take divergent execution paths, their processing takes place sequentially, defeating part of the efficiency advantage of SIMD execution. We present two complementary techniques that mitigate the impact of thread divergence on SIMT micro-architectures. Both techniques relax the SIMD execution model by allowing two distinct instructions to be scheduled to disjoint subsets of the the same row of execution units, instead of one single instruction. They increase flexibility by providing more thread grouping opportunities than SIMD, while preserving the affinity between threads to avoid introducing extra memory divergence. We consider (1) co-issuing instructions from different divergent paths of the same warp and (2) co-issuing instructions from different warps. To support (1), we introduce a novel thread reconvergence technique that ensures threads are run back in lockstep at control-flow reconvergence points without hindering their ability to run branches in parallel. We propose a lane shuffling technique to allow solution (2) to benefit from inter-warp correlations in divergence patterns. The combination of all these techniques improves performance by 23% on a set of regular GPGPU applications and by 40% on irregular applications, while maintaining the same instruction-fetch and processing-unit resource requirements as the contemporary Fermi GPU architecture.
Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)
Authors: Van Craeynest Kenzo , Jaleel Aamer , Eeckhout Lieven , Narvaez Paolo , Emer Joel
Published: September 2012

Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The effectiveness of heterogeneous multi-cores depends on how well a scheduler can map workloads onto the most appropriate core type. In general, small cores can achieve good performance if the workload inherently has high levels of ILP. On the other hand, big cores provide good performance if the workload exhibits high levels of MLP or requires the ILP to be extracted dynamically.

This paper proposes Performance Impact Estimation (PIE) as a mechanism to predict which workload-to-core mapping is likely to provide the best performance. PIE collects CPI stack, MLP and ILP profile information, and estimates performance if the workload were to run on a different core type. Dynamic PIE adjusts the scheduling at runtime and thereby exploits fine-grained time-varying execution behavior. We show that PIE requires limited hardware support and can improve system performance by an average of 5.5% over recent state-of-the-art scheduling proposals and by 8.7% over a sampling-based scheduling policy.
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Authors: Krimer Evgeni , Chiang Patrick , Erez Mattan
Published: September 2012

A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing speculation, where the pipeline operates at an unsafe voltage with any rare errors detected and resolved by the architecture, has been demonstrated to significantly improve the energy-efficiency of scalar processor designs. Unfortunately, applying the same timing-speculative approach to wide-SIMD architectures, such as those used in highly-efficient GPUs, may not provide similar gains.

In this work, we make two important contributions. The first is a set of models describing a parametrized general error probability function that is based on measurements of a fabricated chip and the expected efficiency benefits of timing speculation in a SIMD context. The second contribution is a decoupled SIMD pipeline that more effectively utilizes timing speculation and recovery, when compared with a standard SIMD design that uses only conventional timing speculation. The proposed lane decoupling enables each SIMD lane to tolerate timing errors independent of other adjacent lanes, resulting in higher throughput and improved scalability. We validate our models and evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. Our results show that timing speculation can achieve up to 10.3% improvement in efficiency.
Euripus
Authors: Doudalis Ioannis , Prvulovic Milos
Published: September 2012

Bidirectional debugging and error recovery have different goals (programmer productivity and system reliability, respectively), yet they both require the ability to roll-back the program or the system to a past state. This rollback functionality is typically implemented using checkpoints that can restore the system/application to a specific point in time. There are several types of checkpoints, and bidirectional debugging and error-recovery use them in different ways. This paper presents Euripus
1
, a flexible hardware accelerator for memory checkpointing which can create different combinations of checkpoints needed for bidirectional debugging, error recovery, or both. In particular, Euripus is the first hardware technique to provide consolidation-friendly undo-logs (for bidirectional debugging), to allow simultaneous construction of both undo and redo logs, and to support multi-level checkpointing for the needs of error-recovery. Euripus incurs low performance overheads (<5% on average), improves roll-back latency for bidirectional debugging by >30%, and supports rapid multi-level error recovery that allows >95% system efficiency even with very high error rates.
Reducing memory reference energy with opportunistic virtual caching
Authors: Basu Arkaprava , Hill Mark D. , Swift Michael M.
Published: September 2012

Most modern cores perform a highly-associative transaction look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it with L1 cache access, but this overlap does not hide the power dissipated by TLB lookups. It can even exacerbate the power dissipation by requiring higher associativity L1 cache. With today's concern for power dissipation, designs could instead adopt a virtual L1 cache, wherein TLB access power is dissipated only after L1 cache misses. Unfortunately, virtual caches have compatibility issues, such as supporting writeable synonyms and x86's physical page table walker.

This work proposes an Opportunistic Virtual Cache (OVC) that exposes virtual caching as a dynamic optimization by allowing some memory blocks to be cached with virtual addresses and others with physical addresses. OVC relies on small OS changes to signal which pages can use virtual caching (e.g., no writeable synonyms), but defaults to physical caching for compatibility. We show OVC's promise with analysis that finds virtual cache problems exist, but are dynamically rare. We change 240 lines in Linux 2.6.28 to enable OVC. On experiments with Parsec and commercial workloads, the resulting system saves 94-99% of TLB lookup energy and nearly 23% of L1 cache dynamic lookup energy.
Improving writeback efficiency with decoupled last-write prediction
Authors: Wang Zhe , Khan Samira M. , Jiménez Daniel A.
Published: September 2012

In modern DDRx memory systems, memory write requests compete with read requests for available memory resources, significantly increasing the average read request service time. Caches are used to mitigate long memory read latency that limits system performance. Dirty blocks in the last-level cache (LLC) that will not be written again before they are evicted will eventually be written back to memory. We refer to these blocks as last-write blocks. In this paper, we propose an LLC writeback technique that improves DRAM efficiency by scheduling predicted last-write blocks early. We propose a low overhead last-write predictor for the LLC. The predicted last-write blocks are made available to the memory controller for scheduling. This technique effectively re-distributes the memory requests and expands writes scheduling opportunities, allowing writes to be serviced efficiently by DRAM. The technique is flexible enough to be applied to any LLC replacement policy. Our evaluation with multi-programmed workloads shows that the technique significantly improves performance by 6.5%-11.4% on average over the traditional writeback technique in an eight-core processor with various DRAM configurations running memory intensive benchmarks.
A defect-tolerant accelerator for emerging high-performance applications
Authors: Temam Olivier
Published: September 2012

Due to the evolution of technology constraints, especially energy constraints which may lead to heterogeneous multi-cores, and the increasing number of defects, the design of defect-tolerant accelerators for heterogeneous multi-cores may become a major micro-architecture research issue.

Most custom circuits are highly defect sensitive, a single transistor can wreck such circuits. On the contrary, artificial neural networks (ANNs) are inherently error tolerant algorithms. And the emergence of high-performance applications implementing recognition and mining tasks, for which competitive ANN-based algorithms exist, drastically expands the potential application scope of a hardware ANN accelerator.

However, while the error tolerance of ANN algorithms is well documented, there are few in-depth attempts at demonstrating that an actual hardware ANN would be tolerant to faulty transistors. Most fault models are abstract and cannot demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators.

In this article, we introduce a hardware ANN geared towards defect tolerance and energy efficiency, by spatially expanding the ANN. In order to precisely assess the defect tolerance capability of this hardware ANN, we introduce defects at the level of transistors, and then assess the impact of such defects on the hardware ANN functional behavior. We empirically show that the conceptual error tolerance of neural networks does translate into the defect tolerance of hardware neural networks, paving the way for their introduction in heterogeneous multi-cores as intrinsically defect-tolerant and energy-efficient accelerators.
A case for exploiting subarray-level parallelism (SALP) in DRAM
Authors: Kim Yoongu , Seshadri Vivek , Lee Donghyuk , Liu Jamie , Mutlu Onur
Published: September 2012

Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the high latency of off-chip memory. Adding more banks to the system to mitigate this problem incurs high system cost. Our goal in this work is to achieve the benefits of increasing the number of banks with a low cost approach. To this end, we propose three new mechanisms that overlap the latencies of different requests that go to the same bank. The key observation exploited by our mechanisms is that a modern DRAM bank is implemented as a collection of subarrays that operate largely independently while sharing few global peripheral structures.

Our proposed mechanisms (SALP-1, SALP-2, and MASA) mitigate the negative impact of bank serialization by overlapping different components of the bank access latencies of multiple requests that go to different subarrays within the same bank. SALP-1 requires no changes to the existing DRAM structure and only needs reinterpretation of some DRAM timing parameters. SALP-2 and MASA require only modest changes (< 0.15% area overhead) to the DRAM peripheral structures, which are much less design constrained than the DRAM core. Evaluations show that all our schemes significantly improve performance for both single-core systems and multi-core systems. Our schemes also interact positively with application-aware memory request scheduling in multi-core systems.
PreSET
Authors: Qureshi Moinuddin K. , Franceschini Michele M. , Jagmohan Ashish , Lastras Luis A.
Published: September 2012

Phase Change Memory (PCM) is a promising technology for building future main memory systems. A prominent characteristic of PCM is that it has write latency much higher than read latency. Servicing such slow writes causes significant contention for read requests. For our baseline PCM system, the slow writes increase the effective read latency by almost 2X, causing significant performance degradation.

This paper alleviates the problem of slow writes by exploiting the fundamental property of PCM devices that writes are slow only in one direction (SET operation) and are almost as fast as reads in the other direction (RESET operation). Therefore, a write operation to a line in which all memory cells have been SET prior to the write, will incur much lower latency. We propose PreSET, an architectural technique that leverages this property to pro-actively SET all the bits in a given memory line well in advance of the anticipated write to that memory line. Our proposed design initiates a PreSET request for a memory line as soon as that line becomes dirty in the cache, thereby allowing a large window of time for the PreSET operation to complete. Our evaluations show that PreSET is more effective and incurs lower storage overhead than previously proposed write cancellation techniques. We also describe static and dynamic throttling schemes to limit the rate of PreSET operations. Our proposal reduces effective read latency from 982 cycles to 594 cycles and increases system performance by 34%, while improving the energy-delay-product by 25%.
Staged memory scheduling
Authors: Ausavarungnirun Rachata , Chang Kevin Kai-Wei , Subramanian Lavanya , Loh Gabriel H. , Mutlu Onur
Published: September 2012

When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from the CPU cores, leading to low system performance and starvation of CPU cores. Unfortunately, state-of-the-art application-aware memory scheduling algorithms are ineffective at solving this problem at low complexity due to the large amount of GPU traffic. A large and costly request buffer is needed to provide these algorithms with enough visibility across the global request stream, requiring relatively complex hardware implementations.

This paper proposes a fundamentally new approach that decouples the memory controller's three primary tasks into three significantly simpler structures that together improve system performance and fairness, especially in integrated CPU-GPU systems. Our three-stage memory controller first groups requests based on row-buffer locality. This grouping allows the second stage to focus only on inter-application request scheduling. These two stages enforce high-level policies regarding performance and fairness, and therefore the last stage consists of simple per-bank FIFO queues (no further command reordering within each bank) and straightforward logic that deals only with low-level DRAM commands and timing.

We evaluate the design trade-offs involved in our Staged Memory Scheduler (SMS) and compare it against three state-of-the-art memory controller designs. Our evaluations show that SMS improves CPU performance without degrading GPU frame rate beyond a generally acceptable level, while being significantly less complex to implement than previous application-aware schedulers. Furthermore, SMS can be configured by the system software to prioritize the CPU or the GPU at varying levels to address different performance needs.
Can traditional programming bridge the Ninja performance gap for parallel computing applications?
Authors: Satish Nadathur , Kim Changkyu , Chhugani Jatin , Saito Hideki , Krishnaiyer Rakesh , Smelyanskiy Mikhail , Girkar Milind , Dubey Pradeep
Published: September 2012

Current processor trends of integrating more cores with wider SIMD units, along with a deeper and complex memory hierarchy, have made it increasingly more challenging to extract performance from applications. It is believed by some that traditional approaches to programming do not apply to these modern processors and hence radical new languages must be discovered. In this paper, we question this thinking and offer evidence in support of traditional programming methods and the performance-vs-programming effort effectiveness of common multi-core processors and upcoming many-core architectures in delivering significant speedup, and close-to-optimal performance for commonly used parallel computing workloads.

We first quantify the extent of the "
Ninja gap
", which is the performance gap between naively written C/C++ code that is parallelism unaware (often serial) and best-optimized code on modern multi-/many-core processors. Using a set of representative throughput computing benchmarks, we show that
there is an average
Ninja gap
of 24X (up to 53X
) for a recent 6-core Intel® Core™ i7 X980 Westmere CPU, and that this gap if left unaddressed will inevitably increase. We show how a set of well-known algorithmic changes coupled with advancements in modern compiler technology can bring down the Ninja gap to an average of
just 1.3X
. These changes typically require low programming effort, as compared to the very high effort in producing Ninja code. We also discuss hardware support for programmability that can reduce the impact of these changes and even further increase programmer productivity. We show equally encouraging results for the upcoming Intel® Many Integrated Core architecture (Intel® MIC) which has more cores and wider SIMD. We thus demonstrate that we can contain the otherwise uncontrolled growth of the Ninja gap and offer
a more stable and predictable performance growth
over future architectures, offering strong evidence that radical language changes are not required.
Harmony
Authors: Kambadur Melanie , Tang Kui , Kim Martha A.
Published: September 2012

Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effort by exposing relevant features of multithreaded applications. This paper describes parallel block vectors, which uncover previously unseen characteristics of parallel programs. Parallel block vectors provide block execution profiles per concurrency phase (e.g., the block execution profile of all serial regions of a program). This information provides a direct and fine-grained mapping between an application's runtime parallel phases and the static code that makes up those phases. This paper also demonstrates how to collect parallel block vectors with minimal application perturbation using Harmony. Harmony is an instrumentation pass for the LLVM compiler that introduces just 16-21% overhead on average across eight Parsec benchmarks.

We apply parallel block vectors to uncover several novel insights about parallel applications with direct consequences for architectural design. First, that the serial and parallel phases of execution used in Amdahl's Law are often composed of many of the same basic blocks. Second, that program features, such as instruction mix, vary based on the degree of parallelism, with serial phases in particular displaying different instruction mixes from the program as a whole. Third, that dynamic execution frequencies do not necessarily correlate with a block's parallelism.
iSwitch
Authors: Li Chao , Qouneh Amer , Li Tao
Published: September 2012

Large-scale computing systems such as data centers are facing increasing pressure to cap their carbon footprint. Integrating emerging clean energy solutions into computer system design therefore gains great significance in the green computing era. While some pioneering work on tracking variable power budget show promising energy efficiency, they are not suitable for data centers due to lack of performance guarantee when renewable generation is low and fluctuant. In addition, our characterization of wind power behavior reveals that data centers designed to track the intermittent renewable power incur up to 4X performance loss due to inefficient and redundant load matching activities. As a result, mitigating operational overhead while still maintaining desired energy utilization becomes the most significant challenge in managing server clusters on intermittent renewable energy generation. In this paper we take a first step in digging into the operational overhead of renewable energy powered data center. We propose iSwitch, a lightweight server power management that follows renewable power variation characteristics, leverages existing system infrastructures, and applies supply/load cooperative scheme to mitigate the performance overhead. Comparing with state-of-the-art renewable energy driven system design, iSwitch could mitigate average network traffic by 75%, peak network traffic by 95%, and reduce 80% job waiting time while still maintaining 96% renewable energy utilization. We expect that our work can help computer architects make informed decisions on sustainable and high-performance system design.
End-to-end sequential consistency
Authors: Singh Abhayendra , Narayanasamy Satish , Marino Daniel , Millstein Todd , Musuvathi Madanlal
Published: September 2012

Sequential consistency (SC) is arguably the most intuitive behavior for a shared-memory multithreaded program. It is widely accepted that language-level SC could significantly improve programmability of a multiprocessor system. However, efficiently supporting end-to-end SC remains a challenge as it requires that both compiler and hardware optimizations preserve SC semantics. While a recent study has shown that a compiler can preserve SC semantics for a small performance cost, an efficient and complexity-effective SC hardware remains elusive. Past hardware solutions relied on aggressive speculation techniques, which has not yet been realized in a practical implementation.

This paper exploits the observation that hardware need not enforce any memory model constraints on accesses to thread-local and shared read-only locations. A processor can easily determine a large fraction of these safe accesses with assistance from static compiler analysis and the hardware memory management unit. We discuss a low-complexity hardware design that exploits this information to reduce the overhead in ensuring SC. Our design employs an additional unordered store buffer for fast-tracking thread-local stores and allowing later memory accesses to proceed without a memory ordering related stall.

Our experimental study shows that the cost of guaranteeing end-to-end SC is only 6.2% on average when compared to a system with TSO hardware executing a stock compiler's output.
Viewsheds on terrains in external memory
Authors: Toma Laura
Published: September 2012

Visibility is one of the fundamental problems on terrains. It is at the core of many applications, such as planning the placement of communication towers or watchtowers, planning buildings and roads such that they have a good view or such that they do not spoil somebody else's view, and finding routes on which you can travel while seeing a lot, or without being seen. A variety of problems pertaining to visibility have been researched in computational geometry and graphics, as well as in GIS and geospatial engineering.
Unstable path routing in urban-scale WSN
Authors: Mirza Farrukh , Bouroche Mélanie , Cahill Vinny
Published: September 2012

Wireless sensor networks (WSNs) may suffer from congestion at the nodes near the sink, and partition due to the failure of crucial nodes. In urban environments, mobile devices, such as vehicles and smart phones, present in the vicinity of the sensor field could be opportunistically used for data forwarding. Such devices, controlled by third parties, introduce paths that may appear for only very small intervals.

This paper discusses how exploiting such unstable paths to shift the routing-related processing and communication load to more capable mobile devices can alleviate traffic congestion, improve fault tolerance and reduce WSN energy consumption.
Collaborative localization of mobile users with Bluetooth
Authors: Barreira Alexandre , Sommer Philipp , Kusy Brano , Jurdak Raja
Published: September 2012

Location awareness is a key requirement for many pervasive applications. Collaborative localization can improve accuracy and coverage indoors and improve power consumption by duty-cycling GPS outdoors. We use Bluetooth for collaborative localization of mobile personal devices. Specifically, we embed information in Bluetooth device names to improve latency of information exchange between participating nodes. We identify and demonstrate on real hardware two problems in the Bluetooth stack that negatively impact localization accuracy: a) device name caching that introduces significant device-specific delays in transmitting information between nodes, and b) poor accuracy of time synchronization in modern mobile devices. Our solution is to append additional time information to the device name and track time offsets between nodes. We verify experimentally that this helps to both detect outliers and correct for time-synchronization errors and thus mitigate localization errors.
Internet Impact on the Insertion of Genitourinary Tract Foreign Bodies in Childhood
Authors: Sinopidis Xenophon , Alexopoulos Vasileios , Panagidis Antonios , Ziova Alexandra , Varvarigou Anastasia , Georgiou George
Published: September 2012

Foreign body self-insertion into the urethra is an uncommon paraphilia. Variety in object form, motivation, clinical presentation, complications, and treatment options is a rule. In childhood it is very rare, and it is attributed to curiosity or mental disorders so far. However, the internet impact on daily life of all age groups has created a new category of sexual behavior in childhood and adolescence, the “internet induced paraphilia.” Such is the case of an electrical cable inserted in the urethra of a 12-year-old boy reported here, which is representative of this kind of impact.
Pharmacological Effects of Ginseng on Liver Functions and Diseases: A Minireview
Authors: Huu Tung Nguyen , Uto Takuhiro , Morinaga Osamu , Kim Young Ho , Shoyama Yukihiro
Published: September 2012

Ginseng, an ancient and famous medicinal herb in the Orient, has been used as a valuable tonic and for the treatment of various diseases including hepatic disorders. Ginseng saponins, commonly known as ginsenosides, are principal constituents and have believed to be responsible for multiple ginseng health benefits. There are more 40 ginsenosides isolated from ginseng. To date, treatment options for common liver diseases such as cirrhosis, fatty liver, and chronic hepatitis remain problematic. In this regard, ginseng extracts and individual ginsenosides have shown a wide array of beneficial role in the regulation of regular liver functions and the treatment of liver disorders of acute/chronic hepatotoxicity, hepatitis, hepatic fibrosis/cirrhosis, hepatocellular carcinoma, and so on in various pathways and mechanisms. In this paper, we first outline the pharmacological effects of ginseng and ginsenosides on the liver functions.
Case of Eosinophilic Cystitis Treated with Suplatast Tosilate as Maintenance Therapy
Authors: Yoshino Tateki , Moriyama Hiroyuki
Published: September 2012

Eosinophilic cystitis is a rare inflammatory lesion of the bladder, characterized by massive eosinophilic infiltration of the bladder wall. Its cause is not known definitely. A 49-year-old man consulted our department with a miction pain, gross hematuria, and frequent micturition. Urinalysis showed combined hematuria and pyuria, but urine culture was sterile. Abnormal findings of laboratory examination included an elevated white blood cell (WBC) count (15,700/μL) and the proportion of eosinophils in the peripheral blood was 12% of the WBCs (normal 0–5%). Cystoscopy revealed a solid mass with severe edematous mucosa. Magnetic resonance imaging (MRI) also indicated marked bladder wall thickening, which was suspected for invasive bladder cancer. Transurethral biopsy of the bladder mass was performed with pathological examination revealing features of eosinophilic cystitis. After administration of a combination of prednisolone and suplatast tosilate, followed by monotherapy with suplatast tosilate, regression of the bladder mass, and normalization of the count of peripheral eosinophils were achieved. Fourteen months after steroid therapy, under treatment with suplatast tosilate, there was no relapse of urinary symptoms and the bladder mass.
Association of Social Engagement with Brain Volumes Assessed by Structural MRI
Authors: James Bryan D. , Glass Thomas A. , Caffo Brian , Bobb Jennifer F. , Davatzikos Christos , Yousem David , Schwartz Brian S.
Published: September 2012

We tested the hypothesis that social engagement is associated with larger brain volumes in a cohort study of 348 older male former lead manufacturing workers () and population-based controls (), age 48 to 82. Social engagement was measured using a summary scale derived from confirmatory factor analysis. The volumes of 20 regions of interest (ROIs), including total brain, total gray matter (GM), total white matter (WM), each of the four lobar GM and WM, and 9 smaller structures were derived from T1-weighted structural magnetic resonance images. Linear regression models adjusted for age, education, race/ethnicity, intracranial volume, hypertension, diabetes, and control (versus lead worker) status. Higher social engagement was associated with larger total brain and GM volumes, specifically temporal and occipital GM, but was not associated with WM volumes except for corpus callosum. A voxel-wise analysis supported an association in temporal lobe GM. Using longitudinal data to discern temporal relations, change in ROI volumes over five years showed null associations with current social engagement. Findings are consistent with the hypothesis that social engagement preserves brain tissue, and not consistent with the alternate hypothesis that persons with smaller or shrinking volumes become less socially engaged, though this scenario cannot be ruled out.
Prevalence and Risk Factors ofToxoplasma gondiiInfection in Domestic Cats from the Tropics of Mexico Using Serological and Molecular Tests
Authors: Castillo-Morales Virgen J. , Acosta Viana Karla Y. , Guzmán-Marín Eugenia del S. , Jiménez-Coello Matilde , Segura-Correa José C. , Aguilar-Caballero A. J. , Ortega-Pacheco Antonio
Published: September 2012

The aim of this study was to determine the prevalence and risk factors associated withToxoplasma gondiiinfection in domestic cats using an indirect-ELISA (IgM and IgG) and PCR. Samples collected from 220 cats from Merida, Yucatan, Mexico, were analyzed. Cases were reported as acute or chronic. Cases when positive to IgM and IgG and PCR were considered as reactivated chronic infection. Risk factors (sex, age, body condition, diet access to hunting, and number of cats in home) were assessed with a multivariate analysis, 75.5% (166/220) of the cats were IgM and 91.8% (202/220) IgG-seropositive and 79% were PCR-positive (173/220). Number of cats per household and low body condition score were associated with reactivated chronic infection (). It is concluded thatT. gondiiis scattered in the studied population with several periods of reinfection, and therefore an environmental contamination with infecting oocysts exists and there are intrinsic associated factors in cats that increase the risk of becoming infected.
Tuning Metamaterials for Applications at DUV Wavelengths
Authors: Estroff Andrew , Smith Bruce W.
Published: September 2012

The unique properties of metamaterials, namely, their negative refractive index, permittivity, or permeability, have gained much recent attention. Research into these materials has led to the realization of a host of applications that may be useful to enhance optical nanolithography. A selection of materials has been examined both experimentally and theoretically to verify their support of surface plasmons, or lack thereof, in the DUV spectrum via the attenuated total reflection (ATR) method using the Kretschmann configuration. At DUV wavelengths, materials that were previously useful at mid-UV and longer wavelengths no longer act as metamaterials. Structured materials comprised of alternating layers of aluminum and aluminum oxide (Al2O3), as well as some other absorption-free dielectrics, exhibit metamaterial behavior, as do some elemental materials such as aluminum. These elemental and structured materials exhibit the best properties for use in plasmonic nanolithographic applications. Therefore, a simulator was created to examine material and thickness combinations to generate a tunable metamaterial for use in the DUV. A method for performing plasmonic interference lithography with this metamaterial has been proposed, with calculations showing the potential for half-pitch imaging resolution of 25 nm.
A Weak Comparison Principle for Reaction-Diffusion Systems
Authors: Valero José
Published: September 2012

We prove a weak comparison principle for a reaction-diffusion system without uniqueness of solutions. We apply the abstract results to the Lotka-Volterra system with diffusion, a generalized logistic equation, and to a model of fractional-order chemical autocatalysis with decay. Moreover, in the case of the Lotka-Volterra system a weak maximum principle is given, and a suitable estimate in the space of essentially bounded functionsL∞is proved for at least one solution of the problem.
The Evolution of Mindfulness-Based Physical Interventions in Breast Cancer Survivors
Authors: Stan Daniela L. , Collins Nerissa M. , Olsen Molly M. , Croghan Ivana , Pruthi Sandhya
Published: September 2012

Survivors of breast cancer are faced with a multitude of medical and psychological impairments during and after treatment and throughout their lifespan. Physical exercise has been shown to improve survival and recurrence in this population. Mind-body interventions combine a light-moderate intensity physical exercise with mindfulness, thus having the potential to improve both physical and psychological sequelae of breast cancer treatments. We conducted a review of mindfulness-based physical exercise interventions which included yoga, tai chi chuan, Pilates, and qigong, in breast cancer survivors. Among the mindfulness-based interventions, yoga was significantly more studied in this population as compared to tai chi chuan, Pilates, and qigong. The participants and the outcomes of the majority of the studies reviewed were heterogeneous, and the population included was generally not selected for symptoms. Yoga was shown to improve fatigue in a few methodologically strong studies, providing reasonable evidence for benefit in this population. Improvements were also seen in sleep, anxiety, depression, distress, quality of life, and postchemotherapy nausea and vomiting in the yoga studies. Tai chi chuan, Pilates, and qigong were not studied sufficiently in breast cancer survivors in order to be implemented in clinical practice.
7α-Hydroxy-β-Sitosterol fromChisocheton tomentosusInduces Apoptosis via Dysregulation of Cellular Bax/Bcl-2 Ratio and Cell Cycle Arrest by Downregulating ERK1/2 Activation
Authors: Tasyriq Mohammad , Najmuldeen Ibrahim A. , In Lionel L. A. , Mohamad Khalit , Awang Khalijah , Hasima Noor
Published: September 2012

In continuation of our interest towards the elucidation of apoptotic pathways of cytotoxic phytocompounds, we have embarked upon a study on the anticancer effects of 7α-hydroxy-β-sitosterol (CT1), a rare natural phytosterol oxide isolated fromChisocheton tomentosus. CT1 was found to be cytotoxic on three different human tumor cell lines with minimal effects on normal cell controls, where cell viability levels were maintained ≥80% upon treatment. Our results showed that cell death in MCF-7 breast tumor cells was achieved through the induction of apoptosis via downregulation of the ERK1/2 signaling pathway. CT1 was also found to increase proapoptotic Bax protein levels, while decreasing anti-apoptotic Bcl-2 protein levels, suggesting the involvement of the intrinsic pathway. Reduced levels of initiator procaspase-9 and executioner procaspase-3 were also observed following CT1 exposure, confirming the involvement of cytochrome c-mediated apoptosis via the mitochondrial pathway. These results demonstrated the cytotoxic and apoptotic ability of 7α-hydroxy-β-sitosterol and suggest its potential anti-cancer use particularly on breast adenocarcinoma cells.