bluuebunny/crossref_metadata_2025 huggingface dataset:
Fault Isolation of Open Defects Using Space Domain Reflectometry
Authors: Xie Mayue , Qian Zhiguo , Pacheco Mario , Wang Zhiyong , Dias Rajen , Talanov Vladimir
Published: December 2020

Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.
FemtoFarad/TeraOhm Endpoint Detection for Microsurgery of Integrated Circuit Devices
Authors: Colvin Jim
Published: December 2020

Interactive electrical endpoint detection when thinning conductive and capacitive materials opens the door to approaching a suspect site in an IC without relying on the traditional iterative approach. Controlled approach of embedded conductors in insulators (packages) as well as controlled die thinning with submicron control will be shown, allowing safe approach to the desired feature without overshoot.
Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology
Authors: Tsang Yuk L. , Wang Xiang D. , Ricklefs Reyhan , Goertz Jason
Published: December 2020

In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.
Words for the “Whys”
Authors: Ross Richard J.
Published: December 2020

In an era where the complexity and cost of Failure Analysis tools and techniques is rapidly expanding, it is easy sometimes to lose sight of the basic tool and technique required for successful root-cause analysis. That technique is intellectual curiosity and the tool is the human brain. This paper will describe a simple methodology to insure that this tool and technique are properly engaged either concomitant with or in the absence of state-of-the-art instrumentation and computation. Two simple case studies will be used to illustrate where the Failure Analysis process can easily go awry without proper attention to detail, and, conversely, from too much attention to detail.
Lock-in Thermography-Based Local Efficiency Analysis of Solar Cells
Authors: Breitenstein Otwin
Published: December 2020

The electronic properties of solar cells, particularly multicrystalline silicon-based ones, are distributed spatially inhomogeneous, where regions of poor quality may degrade the performance of the whole cell. These inhomogeneities mostly affect the dark current-voltage (I-V) characteristic, which decisively affects the efficiency. Since the grid distributes the local voltage homogeneously across the cell and leads to lateral balancing currents, local light beam-induced current methods alone cannot be used to image local cell efficiency parameters. Lock-in thermography (LIT) is the method of choice for imaging inhomogeneities of the dark I-V characteristic. This contribution introduces a novel method for evaluating a number of LIT images taken at different applied biases. By pixel-wise fitting the data to a two diode model and taking into account local series resistance and short circuit current density data, realistically simulated images of the other cell efficiency parameters (open circuit voltage, fill factor, and efficiency) are obtained. Moreover, simulated local and global dark and illuminated I-V characteristics are obtained, also for various illumination intensities. These local efficiency data are expectation values, which would hold if a homogeneous solar cell had the properties of the selected region of the inhomogeneous cell. Alternatively, also local efficiency data holding for the cell working at its own maximum power point may be generated. The amount of degradation of different cell efficiency parameters in some local defect positions is an indication how dangerous these defects are for degrading this parameter of the whole cell. The method allows to virtually 'cut out' certain defects for checking their influence on the global characteristics. Thus, by applying this method, a detailed local efficiency analysis of locally inhomogeneous solar cells is possible. It can be reliably predicted how a cell would improve if certain defects could be avoided. This method is implemented in a software code, which is available.
Analysis of Fractures of Printed Circuit Board Traces
Authors: Nail Carl , Rice Larry
Published: December 2020

A PCB trace was repeatedly cracking in the same location. Visual inspection showed cracking there and at structurally similar locations, with solder mask missing from one side of the trace of interest. Fracture analysis suggested that these issues and etch pitting caused crack initiation, followed by fatigue failure that ultimately led to full fracture. A FIB section of a second failure reinforced the finding that the fundamental cracking mechanism was fatigue.
Characterization of Ion Beam Current Distribution Influences on Nanomachining
Authors: Tan Shida , Livengood Richard H. , Greenzweig Yuval , Drezner Yariv , Hallstein Roy , Scheffler Chris
Published: December 2020

The requirements for focused ion beam (FIB) systems to provide higher image resolution and machining precision continue to increase with the continuation of Moore’s Law. Due to the shrinking geometry and increasing complex structures and materials, it is ever more critical to scale the entire ion probe. The necessity for comprehensive analysis of the ion beam profile and understanding how the ion beam current distribution profile influences different aspects of nanomachining are becoming increasingly important and more challenging.
Photon Emission Microscope as a Tool for 3-Dimensional Semiconductor Device Failure Analysis
Authors: Chun Steven J.
Published: December 2020

A three dimensional (3-D) photon emission failure analysis method has been developed to pinpoint failure sites or emission sites on the x, y, and z planes of a degraded diode. The 3-D analysis consists of a cross-sectioning step process on two adjacent sides of a diode utilizing two photon emission sites from respective sides of the die as a map. This process negates the uncertainty and long processing times during cross-sectional analysis to find minute defects in diodes.
Scan Chain Bridge Defect on a 28 nm Technology Node Circuit, Localization Using Dynamic Power Supplies
Authors: Parrassin Thierry , Petit Emmanuel , Celi Guillaume , Mousseau Yann , Dudit Sylvain
Published: December 2020

The bridge defect is one of the most difficult defects to locate. When classical static and dynamic optical techniques reach their limits, applying a dynamic signal on the power supplies for stimulating the defect allows obtaining useful additional information helping the localization. In this paper, we explore these techniques on a real case analysis of bridge defect in a scan chain on a 28nm technology node circuit. We will show that OBIRCH, LVI, static & dynamic EMMI do not give significant signatures for the defect localization. Finally we show that EMMI and LVI signatures applying a clock on the power supply bring relevant information to locate efficiently the defect.
Marginal RF Gain Investigation and Root Cause Determination
Authors: Harber Keith , Brockett Steve
Published: December 2020

This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.
Anamnesis in Failure Analysis—How a System-Related Approach Can Save Failure Analysis (FA) Time, Shorten Learning Loops and Reduce Cost
Authors: Jacob Peter
Published: December 2020

Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.
Advantage of AFP Nanoprobing on the 28 nm Technology Failure Analysis
Authors: Chen C.Q. , Ang G.B. , Zhao S.P. , Alfred Q. , Dayanand N. , Dnyan K. , Liu B.H.
Published: December 2020

As the rapid developments of semiconductor manufacturing technologies, the CD of the device keep shrinking. The IC devices have a smaller feature sizes and higher densities, and thus there are many challenges come up in terms of the failure analysis and localized device characterization. Besides the challenge of smaller feature size, there is another challenge as well. Some of the traditional FA method can no longer be employed on advanced technologies, such as 28nm and beyond. Quickly and successfully isolating the failed location and obtaining electrical signature of the defect has become more of a challenge, especially for the device level analysis and characterization. AFP nanoprobing system provides some solutions to advanced nodes fault isolation through its AFM imaging mode of CAFM.
Applications of Nanoprobing for Localization of Design for Manufacturing Issues on Analogue-to-Digital Converter on Advanced Technology Node
Authors: Quah A.C.T. , Chen C.Q. , Ang G.B. , Nagalingam D. , Li Y. , Zhu J. , Neo S.P. , Zhao S.P.
Published: December 2020

This paper describes 2 case studies where device characterizations using Atomic Force Probe (AFP) nanoprobing, allow for the localization and verification of design weakness and process variations on the Analog-to-Digital (ADC) block that resulted in degraded device performance and severe yield loss. In these cases, the sensitive resistor structures in the ADC block was impacted due to design pattern density interaction with process fabrication steps. In addition, close collaboration with customer was also essential for quick root cause identification, design and process fix.
Nondestructive Analysis Solution Using Combination of Lock-In Thermography (LIT) and 3D Oblique X-Ray CT Technology
Authors: Seimiya Naoki , Watanabe Takuhei , Ichinomiya Takashi
Published: December 2020

We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method.
Advanced Fault Localization through the Use of Tester Based Diagnostics with LVI, LVP, CPA, and PEM
Authors: Safran Laura , Sylvestri John , Albert Dave , Song Zhigang , McGinnis Patrick
Published: December 2020

Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.
Optimization of Soft Defect Localization Technique Scan Time Using Dummy Subroutine Test Vector Insertion
Authors: Yeoh B.L. , Goh S.H. , Chan Y.H. , You G.F. , Koh Y.E. , Lam Jeffrey
Published: December 2020

Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.
A Simple Polishing Technique for Removing the Entire Metallization Stack for Sub 100 nm Device Technologies
Authors: Mulder Randal , Anderson Robert
Published: December 2020

The physical analysis of sub-100nm device technologies in many cases requires the total or partial removal of the multiple layers of metallization that route electrical signals and power through the device. This paper presents a simple and quick polishing technique that will remove the entire metallization stack above metal 1 for a 55nm technology device, which results in significantly reducing the time needed to reach the transistor level of the device and also greatly improving uniform planarity across the device. This method is intended for those cases in which gaining access to the transistor layer is required for electrical characterization and physical analysis. The improved speed of this polishing technique to reach the transistor layer has greatly reduced cycle time. The results for the polishing method have been relatively reliable with over a 95% success rate.
Data Center Equipment Reliability Concerns—Contamination Issues, Standards Actions, and Case Studies
Authors: Muller Chris , Arent Chuck , Yu Henry
Published: December 2020

Lead-free manufacturing regulations, reduction in circuit board feature sizes and the miniaturization of components to improve hardware performance have combined to make data center IT equipment more prone to attack by corrosive contaminants. Manufacturers are under pressure to control contamination in the data center environment and maintaining acceptable limits is now critical to the continued reliable operation of datacom and IT equipment. This paper will discuss ongoing reliability issues with electronic equipment in data centers and will present updates on ongoing contamination concerns, standards activities, and case studies from several different locations illustrating the successful application of contamination assessment, control, and monitoring programs to eliminate electronic equipment failures.
Silicon Junction Profile Delineation by Anodic Etching in HF/HNO3/CH3COOH Solution
Authors: Lee Jeng-Han , Chen Y.M. , Huang C.M. , Tseng F.Y. , Chen C.J. , Yin K.M. , Lin Y.T. , Huan Y.S. , Su David
Published: December 2020

An anodic etching is used for silicon junction profile delineation. Experimental results show that the etching rate is determined by dopant type, of which P type silicon etching rate will be enhanced while the N type silicon become inactive when an external positive voltage is applied. The experiment verifies the role of holes on the silicon etching. The proposed method is applicable for exploring the profile of P+/N-well, N+/P-well, and N-well/P-well junctions, using the same recipe.
Validity-Study of Commercial Semiconductor with TO-18 Package for Space Application by PIND Test
Authors: Nakatake Yusuke , Okabe Makoto , Sato Shota
Published: December 2020

In this paper, we carried out PIND (Particle Impact Noise Detection) test and X-ray inspection of a transistor in a TO-18 package for commercial and industrial applications. From our evaluation results, we explain the validity of the PIND test by comparing PIND test and X-ray inspection results. We make clear that PIND test is able to detect internal foreign material that may be transparent to X-ray inspection. In addition, we report analysis results of internal foreign materials from defective devices. This matter suggests that a problem is contamination control in the manufacturing process, most likely the sealing process.
Case Studies on Application of 3D Real Time X-ray for Flip Chip C4 Package
Authors: Cao Lihong , Donna Wallace , Tran Loc , Tuttle Lynda
Published: December 2020

This article describes how 3D Real Time X-Ray (RTX) technique enhances the capability of package-level failure analysis of a flip-chip package. 3D RTX was successful in detecting different failure signatures. This paper outlines detailed applications of 3D RTX with case studies.
Observation of Channel Strain Release in pMOS Device with Low Idsat Using Energy-Filtered Nano-Beam Diffraction Technique
Authors: Zhu Jie , Du An Yan , Liu Bing Hai , Er Eddie , Zhao Si Ping , Lam Jeffrey
Published: December 2020

In this work, energy-filtered TEM nano-beam diffraction (NBD) technique was used to evaluate channel strain profile in pMOS transistors suffering low Idsat issue. TEM and EDX analysis showed nickel deep diffusion into embedded SiGe source/drain. Such defect not only led to leakage current from S/D to substrate but might also reduce compressive strain induced to channel by eSiGe. Comparison of channel-direction strain between bad and good samples using NBD confirmed strain relaxation in bad sample which explained low Idsat as a result of reduced holes mobility.
Marginal Failure Diagnosed with LADA—Case Studies
Authors: Lee Sukho , Kim Keonil , Lee Yunwoo , Lee Euncheol , Kim Yojoung , Kapilevich Izak
Published: December 2020

During the early stage of process development, the major activities are yield ramp up with DFT test such as Memory BIST and SCAN test. There are plenty of commercial and inhouse diagnostics tools for DFT so in case of failure FA procedures are rather simple and standardized: run EDA tool, get fail location, perform pFA then feedback to process engineering. However in the case of marginal failure FA procedures are generally more complicated. FA engineer should consider many different scenarios to find the root cause. The marginal voltage fail is caused by many different reasons. The analysis of marginal fail is of course very important to screen out healthy devices and detect any problem of process technology or design methodology. In this paper, the authors deal with three marginal voltage fail case studies: scan chain fail, digital function fail and analog function fail. Throughout these case studies, LADA was successfully used to define the fault location. The reason of device alteration was well explained with further study. It is obvious that LADA is a very effective way to analyze marginal failures in cases where the FA engineer doesn’t have much design information because the results are very intuitive and clear. There is little doubt of LADA results accuracy because LADA is utilizing the tester to make an accurate Pass/Fail decision. LADA results are direct indication of device sensitivity to parametric changes, in our case voltage margin.
Metal Bridge Defects Localization by a Tiny Leakage between One of Bridged Signals and VDD (GND)
Authors: Wu Chunlei , Yao Suying
Published: December 2020

As semiconductor technology continues to advance to smaller dimensions and more complex circuit designs, it is becoming more challenging to locate the resistive short directly between two metal lines (signals) due to a metal bridge defect. Especially these two metal lines are very long and relevant to many functional modules. After studying the failed circuit model, we found there should be a tiny leakage between one of the bridged signals and one of common power signals (such as VDD and GND) on a failed IC compared with the reference one, if there is a metal bridge defect between these two bridged signals. The tiny leakage between one of the bridged signals and one of power signals is an indirect leakage that is a mapping of the direct resistive short between these two bridged signals. The metal bridge defect could be pinpointed with the tiny leakage between one of the bridged signals and one of power signals by Lock-in IR-OBIRCH. It is an easier and faster way to locate the metal bridge defects. In this paper, the basic and simple circuit model with a metal bridge defect will be presented and two cases will be studied to demonstrate how to localize a metal bridge defect by the tiny leakage between one of the bridged signals and one of power signals.
Quantitative Analysis of Heterogeneous Materials by SEM/EDS by Use of Rapid Phase Decomposition
Authors: Konopka John
Published: December 2020

Algorithms for quantification by SEM/EDS always specify that the material being analyzed should be homogeneous. Every instruction on analysis by SEM/EDS warns against analyzing heterogeneous samples. However, in day-to-day analysis, it is extremely common to encounter samples which are heterogeneous and these samples must be analyzed. It is very common for an analyst to simply scan an entire field of view in the SEM, acquire an x-ray spectrum from this field of view, press the button for standardless quantification, and hope for the best. This work explores the magnitude of this problem and characterizes it with measurements. A solution is then proposed for performing this kind of analysis. The results of analyses of multiple areas showed larger variations than the variation between the area-weighted and gross spectrum calculations. The results obtained were consistent with the nominal bulk concentrations for homogeneous materials.
Temperature-Dependent Logic Failure in a GaAs Power Amplifier-Duplexer Module Caused by a Subtle Parasitic Schottky Diode
Authors: Emergo Rose , Brockett Steve , Hamilton Pat
Published: December 2020

A single power amplifier-duplexer device was submitted by a customer for analysis. The device was initially considered passing when tested against the production test. However, further electrical testing suggested that the device was stuck in a single power mode for a particular frequency band at cold temperatures only. This paper outlines the systematic isolation of a parasitic Schottky diode formed by a base contactcollector punch through process defect that pulled down the input of a NOR gate leading to the incorrect logic state. Note that this parasitic Schottky diode is parallel to the basecollector junction. It was observed that the logic failure only manifested at colder temperatures because the base contact only slightly diffused into the collector layer. Since the difference in the turn-on voltages between the base-collector junction and the parasitic Schottky diode increases with decreasing temperature, the effect of the parasitic diode is only noticeable at lower temperatures.
A Novel Method for the Specified Site Planar View TEM Sample Preparation
Authors: Duan Shuqing , Zhao Yanli , Li Ming
Published: December 2020

This paper reports a novel method for site specific plan view transmission electron microscopy (TEM) sample preparation. The detailed procedure is introduced step by step. To demonstrate the practicality of this technique in failure analysis, case studies on 45nm and below technology nodes using the novel method are reported. The results showed that the method is very useful for the analysis of the specified failure location and is helpful to improve the success rate of failure analysis.
Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage
Authors: Zhu Jie , Du An Yan , Liu Bing Hai , Er Eddie , Zhao Si Ping , Lam Jeffrey
Published: December 2020

In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.
Cross-Section Sample Preparation Method for Imaging Dopant Related Anomalies Using Scanning Probe Microscopy Techniques
Authors: Subramanian Swaminathan , Ly Khiem , Chrastecky Tony
Published: December 2020

Visualization of dopant related anomalies in integrated circuits is extremely challenging. Cleaving of the die may not be possible in practical failure analysis situations that require extensive electrical fault isolation, where the failing die can be submitted of scanning probe microscopy analysis in various states such as partially depackaged die, backside thinned die, and so on. In advanced technologies, the circuit orientation in the wafer may not align with preferred crystallographic direction for cleaving the silicon or other substrates. In order to overcome these issues, a focused ion beam lift-out based approach for site-specific cross-section sample preparation is developed in this work. A directional mechanical polishing procedure to produce smooth damage-free surface for junction profiling is also implemented. Two failure analysis applications of the sample preparation method to visualize junction anomalies using scanning microwave microscopy are also discussed.
Soft Defect Localization on Analog and Mixed-Signal ICs Using an OBIRCH Tool
Authors: Wu Chunlei , Li Xiaocui , Che Yi
Published: December 2020

It is difficult to localize the soft defect on analog and mixed-signal ICs only by OBIRCH, because OBIRCH laser scanning module could not synchronize with the IC under functional test, and the failure modes on analog and mixed-signal ICs are complicated. In this paper, a dynamic synchronization method is proposed to localize the soft defect precisely only with an OBIRCH tool on analog and mixed-signal ICs. The methodology and system configuration are presented. A case is studied successfully on an analog and mixed-signal IC using this method.
Comparison of Photon and Thermal Emission Microscopy for Dynamic Fault Isolation
Authors: Goh S.H. , You G.F. , Tan Alan , Bharadwaj C.V. , Hao Hu , Yeoh B.L. , Lam Jeffrey
Published: December 2020

Unlike photon emission microscopy which is usually the first go-to technique in tester-based or dynamic electrical fault localization, infrared thermal microscopy does not play a similar routine role despite its comparable ease in application. While thermal emission lacks in optical resolution, we demonstrate superior sensitivity and accuracy over photon emission on dynamic fault localization of backend-of-line short defects.
Alleviating Sample Charging during FIB Operation
Authors: Liu Q. , Kor H.B. , Siah Y.W. , Gan C.L.
Published: December 2020

Dual-beam focused ion beam (DB-FIB) system is widely used in the semiconductor industry to prepare cross-sections and transmission electron microscopy (TEM) lamellae, modify semiconductor devices and verify layout. One of the factors that limits its success rate is sample charging, which is caused by a lack of conductive path to discharge the accumulated charges. In this paper, an approach using an insitu micromanipulator was investigated to alleviate the charging effects. With this approach, a simple front side semiconductor device modification was carried out and the corresponding stage current was monitored to correlate to the milling process.
An Infrared Microscope for Use on a Focused Ion Beam for Circuit Edit and Backside Edit Applications
Authors: Richards Alexander , Weschler Matthew , Durller Michael
Published: December 2020

To help solve the navigational problem, i.e., being able to successfully locate a circuit for probing or editing without destroying chip functionality, a near-infrared (NIR), near-ultraviolet (NUV), and visible spectrum camera system was developed that attaches to most focused ion beam (FIB) or scanning electron microscope vacuum chambers. This paper reviews the details of the design and implementation of the NIR/NUV camera system, as instantiated upon the FEI FIB 200, with a particular focus on its use for the visualization of buried structures, and also for non-destructive real time area of interest location and end point detection. It specifically considers the use of the micro-optical camera system for its benefit in assisting with frontside and backside circuit edit, as well as other typical FIB milling activities. The quality of the image obtained by the IR camera rivals or exceeds traditional optical based imaging microscopy techniques.
Analysis of Integrated Current Sense in Multiphase Buck Converters
Authors: Kearney Ian
Published: December 2020

Accurate and lossless current sensing is vital for high performance multiphase buck converters used in the latest voltage regulation modules (VRMs). A synchronous FET onstate resistance based approach is an alternative topology to DCR based sensing and is compatible with any controller, which requires inductor current information. The MOSFET driver has built-in sense circuitry, which when co-packaged with the MOSFETs reduces total footprint and ease of design. The Powerstage embodiment virtually eliminates the parasitic inductance and resistance between Control and Synchronous power MOSFETS; and using thick copper clips substantially reduce the parasitics associated with the input supply voltage (VIN) and the switch node output voltage (VSW) connections when compared to wire-bonded solutions. This paper presents a novel investigation into a contradictory low on-resistance paradox in a stacked 3D configuration. Through analysis, characterization and simulation the author deciphered the conundrum leading to a root cause explained by a mismatch of internal gain and referenced on-resistance. Building on previous metrology improvements the innovative insights drove analysis toward root-cause.
SIMS Quantitative Analysis and Optimization for Ion Implantation Angle Deviation
Authors: Shi JiangBei , Chien WeiTing , Zhang QiHua , Li AiMin , Liu ChuanJun
Published: December 2020

The accuracy of ion implantation is very important in semiconductor manufacturing and will directly affect the performance of the individual devices and even the whole chip. The deviations of ion implantation energy, dose and angle often result from abnormality of implant equipment or process design limit. The information of ion implantation energy, dose and angle can be qualitatively and quantitatively analyzed by SIMS (Secondary Ion Mass Spectrometry) [1], which provides a way to diagnose ion implanter issue. Based on SIMS analysis results, we can judge whether ion implanter meets the requirements and whether the process design achieves the expected goal. In this paper, we report a SIMS data analysis method determine the deviation of ion implantation angle. A term of deviation rate is defined and a related calculation method was introduced, which is proportional to the deviation angles of the ion implanter. Then, a statistical analysis on a large number of data of deviation rates and ion implantation angles showed that the sampling data followed normal distribution, and thus the corresponding 3 sigma could be obtained. Using the determined 3 sigma range of the deviation rates, we can define the acceptable range for deviation rate. Further, we can use the actual deviation rate to judge if the implant equipment needs maintenance or not, or suggest the direction for improvement. Finally, we set up an oriented and quantitative optimization method of angle deviation by the full mapping of SIMS depth profiles, which can directly set the relationship between the angle deviation and the adjustment parameters of ion implantation disk (Δ alpha, Δ beta). The equipment’s maintenance time and cost can thus be minimized. This method can be used as early detection to the abnormity of ion implant equipment.
Failure Analysis Induced by Bit Line Sense Amplifier Noise in High Density DRAM
Authors: Lee Myungjae , Ko Sanghoon , Bae Daegi , Hong Heeil , Hwang Hongsun , Rhee Sangjae , Cho Kangyong , Jin Gyoyoung
Published: December 2020

The open bit line architecture scheme is an effective method to achieve higher density memory devices. With the scaling of DRAM, we have adopted a bit line sense amplifier (BLSA) design using a shared local power line for reducing the circuit layout dimensions. As a result of this new design, the write time of the memory cell was sometimes degraded because of an increase in initial sensing noise. This paper gives a detailed analysis of the problem caused by the initial sensing noise by examination of the behaviour of the opposite data portion of the cell array matrix when the word line is not activated. Finally, we propose a design improvement to reduce the magnitude of noise peaks and the results of this improvement when implemented in the test vehicle.
High Resolution Electron Beam Induced Resistance Change for Fault Isolation with 100 nm2 Localization
Authors: Buchea Brett A. , Butler Christopher S. , Ryu H.J. , Chuang Wen-hsien , von Haartman Martin , Tong Tom
Published: December 2020

A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.
A Simple Method to Fabricate a Tunable In Situ SIL
Authors: Kimball Mark
Published: December 2020

The SIL is now an essential component of the modern FA lab. But the SIL has very specific requirements to produce good results: and the aplanatic SIL (or ASIL) has even more stringent requirements. In particular, it requires a very specific sample thickness, and a very flat surface. In addition, there are situations where a commercial SIL lens is not compatible with the requirements at hand. This paper describes a method for fabricating an in-situ SIL that can be adjusted for different sample thicknesses, using a combination of materials and techniques that are both readily available and easily learned. In contrast to diffractive lenses, our SILs are much more efficient with regard to delivering a focused laser beam to the spot of interest, and do not require the use of a FIB to fabricate them.
The Changing Role of Advanced Sample Preparation in X-Ray Inspection Supporting 2.5D and 3D Sample Failure Analysis
Authors: LaVoy Rosanne M. , Babian Fred , Mulholland Matthew , Silverman Scott
Published: December 2020

The X-ray inspection of fully assembled samples is becoming ever more important as the benefits of using area array packages/chip scale packages/flip chips are applied to more and more products. Sample preparation has traditionally been used to improve access to geometry or a specific location with a known defect that requires verification. The novel paradigm is an integrated approach to sample preparation and X-ray inspection to optimize resolution and throughput time performance with minimally deprocessed sample. This paper, covering the limitations of X-Ray imaging and 3D tomographic reconstruction, discusses the development of models for throughput time and resolution by failure analysis labs. It also discusses the processes involved in advanced sample preparation techniques and global BGA removal to obtain improved resolution at die level.
Decapsulation of Multichip BOAC Devices with Exposed Copper Metallization Using Atmospheric Pressure Microwave Induced Plasma
Authors: Tang Jiaqi , Staller Kristopher D. , Beenakker Kees
Published: December 2020

With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.
Contactless Fault Isolation for FinFET Technologies with Visible Light and GaP SIL
Authors: Lohrke Heiko , Scholz Philipp , Beyreuther Anne , Boit Christian , Uhlmann Eckart , Kühne Stefan , Jagodzinski Marco , Ganesh Ulrike , Iwaki Yoshitaka , Chivas Robert , Silverman Scott
Published: December 2020

The visible approach of optical Contactless Fault Isolation (VIS-CFI) serves the perspective of application in FinFET technologies of 10 nm nodes and smaller. A solid immersion lens (SIL) is mandatory to obtain a proper resolution. A VISCFI setup with SIL requires a global polishing process for sub-10 µm silicon thickness. This work is the first to combine all these necessary components for high resolution VIS-CFI in one successful experiment. We demonstrate Laser Voltage Imaging and Probing (LVI, LVP) on 16/14 nm technology devices and investigate a focus depth dependence of the LVI/LVP measurement in FinFETs.
Localization of Nonlinear Defects in Sub 14 nm BEOL Structures
Authors: Kane Terence , Tenney Michael
Published: December 2020

This paper explains how SEM two-point specimen current localization combined with TEM imaging/elemental mapping overcomes the limitations of conventional SEM and gallium ion beam FIB voltage contrast methods, pinpointing the location of nonlinear defects in advanced technology (<14nm) nodes.
Analysis of an Asynchronously Generated Race Condition
Authors: Howard Clifford , Dickson Kris , Erington Kent
Published: December 2020

An asynchronous Low Voltage Detect (LVD) interrupt during the self-test portion of the reset sequence of a microcontroller randomly caused a corrupted clock state that was not recoverable except through a power on reset, or POR. This paper discusses the techniques used to overcome the many obstacles encountered to determine the root cause of the race condition that corrupted the clock state machine registers.
Physical Failure Analysis Techniques for Front-End-of-Line Defect Analysis
Authors: Doyle Dirk , Benedict Lawrence , Awitan Fritz Christian
Published: December 2020

Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.
Identification of Wet Chemical Deprocessing Induced Artifacts—A Common Problem Affecting All MOS and CMOS Technologies
Authors: Mendaros Raymond G. , Marquez Christian Renan B. , Mazon Bernardino D.
Published: December 2020

Wet Chemical Deprocessing is one of the techniques in exposing embedded structures in an integrated circuit (IC). Layers of the die from the passivation to silicon substrate can be selectively etched using this technique. From series of evaluations conducted, it was discovered that there are silicon damage sites that are induced during wet chemical deprocessing. Their physical attributes are almost identical to the attributes of electro-static discharge (ESD) defects. It only differs in the locations where they occur. ESD defects are expected near the edges of the transistors’ gate channel where high electric fields are present while deprocessing artifacts are observed at the center of the gate channel. Deprocessing artifacts are represented by mechanically induced damage sites in the silicon substrate. These mechanical damage sites manifest in the form of silicon pits, voids, slits and fractures as a result of tensional or shearing stresses in the silicon substrate when the polysilicons separate from the silicon substrate. If deprocessing artifacts are not well understood by the analysts then these can be mistakenly reported as ESD or fabrication defects.
Process Flow Employed for Parametric Test Structure Chain Opens Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries
Authors: Kodali Satish , Ma Yinzhe , Oh Chong Khiam , Zhao Wayne , Beaudoin Felix
Published: December 2020

With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of a line. This work provides a process flow sheet for root cause identification on chain opens on advanced 20 nm and sub-20 nm technologies setting a standard guideline for a specific category fail type. It provides a consistent way of attack in a much more streamlined fashion. Further, dependability on TEM rather than convention FIB cross-sections provides shortest time to root cause identification. Three typical cases encountered are discussed to demonstrate the idea: embedded chain opens by electron beam absorbed current (EBAC) isolation, chains opens at level by EBAC isolation, and chains opens at level by passive voltage contrast isolation.
Direct Charge Measurement in Floating Gate Transistors of Flash EEPROM Using Scanning Electron Microscopy
Authors: Courbon Franck , Skorobogatov Sergei , Woods Christopher
Published: December 2020

We present a characterization methodology for fast direct measurement of the charge accumulated on Floating Gate (FG) transistors of Flash EEPROM cells. Using a Scanning Electron Microscope (SEM) in Passive Voltage Contrast (PVC) mode we were able to distinguish between '0' and '1' bit values stored in each memory cell. Moreover, it was possible to characterize the remaining charge on the FG; thus making this technique valuable for Failure Analysis applications for data retention measurements in Flash EEPROM. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Only a relatively simple backside sample preparation is necessary for accessing the FG of memory transistors. The technique presented was successfully implemented on a 0.35 μm technology node microcontroller and a 0.21 μm smart card integrated circuit. We also show the ease of such technique to cover all cells of a memory (using intrinsic features of SEM) and to automate memory cells characterization using standard image processing technique.
Optimizing Gas-Assisted Processes for Ga and Xe FIB Circuit Edit Application
Authors: Ray Valery , Oboňa Josef V. , Sharang Sharang , Rotkina Lolita , Chang Eddie , Tolua Kevin
Published: December 2020

Despite commercial availability of a number of gas-enhanced chemical etches for faster removal of the material, there is still lack of understanding about how to take into account ion implantation and the structural damage by the primary ion beam during focused ion beam gas-assisted etching (FIB GAE). This paper describes the attempt to apply simplified beam reconstruction technique to characterize FIB GAE within single beam width and to evaluate the parameters critical for editing features with the dimensions close to the effective ion beam diameter. The approach is based on reverse-simulation methodology of ion beam current profile reconstruction. Enhancement of silicon dioxide etching with xenon difluoride precursor in xenon FIB with inductively coupled plasma ion source appears to be high and relatively uniform over the cross-section of the xenon beam, making xenon FIB potentially suitable platform for selective removal of materials in circuit edit application.