bluuebunny/crossref_metadata_2025 huggingface dataset:
Structural and Electrical Characterization of Dielectrics, Carbon Nanotubes and Nanoelectronic Devices by Means of Scanning Probe Microscopy
Authors: Schwalke Udo
Published: September 2007

During the past years, atomic force microscopy (AFM) has become an indispensable tool for non-destructive characterization of structures at the nanometer-scale. By implementing current sensing techniques, the topographic imaging capabilities of the AFM have been extended. Conductive atomic force microscopy (C-AFM) allows direct correlations of feature locations with the corresponding electrical properties. In this paper, several examples on the application of combined AFM and C-AFM techniques will be presented in order to illustrate the potential of the scanning probe microscopy (SPM) technique for structural and electrical characterization of gate dielectrics, carbon nanotubes as well as nanoelectronic device structures.
Emerging Research Nanoelectronic Devices: The Choice of Information Carrier
Authors: Zhirnov Victor , Cavin Ralph
Published: September 2007

Many different approaches are being explored for information carriers that will enable continued geometrical scaling beyond the estimated physical limits of electron-based devices. In this paper we offer the proposition that as transistor channel length decreases below 5 nm, the mass of the information carrier must rapidly increase if acceptable ON-OFF switch characteristics are to be maintained. Several different possibilities for the realization of sub-5-nm switches are outlined.
Strain Control of Si and Si1-xGex Layers in the Si/Si1-xGex/Si Heterostructures by Stripe-Shape Patterning for Future Si-Based Devices
Authors: Murota Junichi , Uhm Jangwoong , Sakuraba Masao
Published: September 2007

By stripe-shape patterning of the Si/strained Si/1-xGex/Si(100) heterostructures, the strained Si1-xGex layer is relaxed and the relaxation induces tensile strain in the capping Si layer. The degree of the relaxation becomes larger for a narrower stripe, higher Ge fraction, and thinner capping Si layer. It is found that the relaxation in Si1-xGex layer proceeds in the region from the stripe edge to the inner position of 0.4 um away from the edge. The strain degree in the capping Si layer becomes smaller towards depth direction for the thicker capping Si layer than 5-10 nm. The resistivity measurements of the in-situ doped capping Si and Si1-xGex layers in the stripe-shape patterned heterostructure show that the tensile strain induces mobility enhancement for both electron and hole, and the relaxation of strain induces mobility reduction for hole in Si1-xGex layer.
Nano-Scale Profile of the Dielectric Constant Near the Si/oxide Interface: A First-Principles Approach
Authors: Nakamura Jun , Wakui Sadakazu , Eguchi Shunsuke , Yanai Ryosuke , Natori Akiko
Published: September 2007

Spatial variation in dielectric constants near the Si/SiO2 interfaces has been revealed using the first-principles ground-states calculations in external electrostatic fields. It has been shown that both the optical and the static dielectric constants change abruptly in the vicinity of the SiO2/Si interfaces, while the energy gap changes gradually on SiO2 side. These results indicate that the profile of dielectric constant is determined by the local polarization which directly reflects the local atomic arrangement. Dielectric properties of isolated ultra-thin Si(111), SiO2, and La2O3(0001) films have also been investigated. Both the optical and the static dielectric constants of oxide films hardly depend on the film thickness and the spatial variation of the local dielectric constant is also very small as contrasted to the semiconducting Si film.
Angle-Resolved Photoelectron Spectroscopy Study on Ultrathin Gate Dielectrics
Authors: Nohira Hiroshi , Hattori Takeo
Published: September 2007

The paper reviews the non-destructive depth profiling of the composition and the chemical structure of ultrathin oxynitride films and ultrathin silicon nitride films using angle-resolved photoelectron spectroscopy. Depth profiles of nitrogen atoms in silicon oxynitride films were determined by applying the maximum entropy concept to angle-resolved photoelectron spectra. The layered structures of silicon nitride films formed using nitrogen-hydrogen radicals were determined by measuring soft X-ray excited angle-resolved photoemission from Si 2p, N 1s, and O 1s core levels with the same probing depth.
Novel SONOS and Floating-Gate Flash Memory Cell Structures for High Density and High Reliability Applications
Authors: Huang Ru
Published: September 2007

The flash memory technology meets physical and technical obstacles for further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density, low power and high reliability memory applications. One is the newly-proposed dual doping floating gate (DDFG) flash cell with compatible fabrication technology. The DDFG flash cell with the floating gate of lateral PNP sandwich doping profile shows higher programming speed, lower power, better data retention characteristics and comparable erasing performance in comparison with conventional n-type floating gate cells. To further enhance the storage density, VD-NORM with dual-nitride-trapping-layer and vertical structure is proposed and experimentally demonstrated for four-bit-per-cell storage capability. The novel DDFG flash cell and VD-NORM structures can be considered as potential candidates for different flash memory applications.
Integration Solutions for 65 nm Back End of Line Defect Reduction and Manufacturability
Authors: Hichri Habib , Oakley Jennifer S. , Grunow Sarah L. , Bunke C. , Kelp J. , Fang R. , Kulkarni D. , Angyal M. , Houghton T. , Santiago A. , Kumar K. , Majors C. , Fitzsimmons J. , Nye H. , Watts David , Mazzotti J.
Published: September 2007

This paper outlines yield improvements in the integration of damascene copper in low-k SiCOH intermetal dielectric at 65 nm dimensions. Large defect reductions were seen by RIE, wet cleans and CMP process optimization. RIE improvements led to reductions of thirty three percent for missing pattern defects while wet clean optimization resulted in more than a fifty percent reduction in metal voids. CMP carrier head changes provided a more corrosion resistant process and higher throughput. Additionally, a high performance M1 module that maintained process window for all sectors was developed.
Performance Boost Using a New Device Structure Design for SOI MOSFETs Beyond 25nm Node
Authors: Cheng Weitao , Teramoto Akinobu , Ohmi Tadahiro
Published: September 2007

We demonstrate that very high performance ultra short-channel MOS transistors can be realized in accumulation mode SOI MOSFETs benefited from device structure with higher current drivability and a good suppression of degradation resulted from the gate electrode depletion. Furthermore, we reveal that the short channel effect is suppressed in accumulation mode devices by thinning the SOI layer and BOX thicknesses with both the polysilicon gate electrode and metal gate.
Towards Graphene Field Effect Transistors
Authors: Lemme Max C. , Echtermeyer Tim , Baus Matthias , Szafranek B. N. , Schmidt Mathias , Kurz Heinrich
Published: September 2007

Field effect device (FED) manufactured from monolayer graphene are investigated. A conventional CMOS-compatible top-down process flow is applied, except for graphene deposition. From IVcharacteristics carrier mobilities in graphene pseudo-MOS structures are extracted and compared to state-of-the-art silicon MOSFETs. The extracted values outperform the universal mobility of silicon and silicon-on-insulator MOSFETs.
High-Frequency Device Options for Systems-on-Chip
Authors: Schwierz Frank
Published: September 2007

In this paper, the state-of-the-art of high-frequency transistors and their prospects for application in the high-frequency parts of systems-on-chip is reviewed. It is shown that Si-based high-frequency transistors, in particular Si MOSFETs, offer very competitive performance and fulfill most of the requirements of current system-on-chip solutions. Although today III-V HEMTs and HBTs show the best performance in terms of cutoff frequency and maximum frequency of oscillation, their widespread application in systems-on-chip is rather unlikely in the medium term. The prospects of other high-frequency device concepts, such as III-V MOSFETs and carbon-based transistors, are also discussed.
Analysis of the Pre-epi Bake Conditions on the Defect Creation in Recessed SiGe S/D Junctions
Authors: Bargallo Gonzalez Mireia , Thomas Nicole , Simoen Eddy , Verheyen Peter , Hikavyy Andriy , Leys Frederik , Okuno Yasutoshi , Vissouvanadin Soubaretty Bertrand , Van Daele Benny , Geenen Luc , Loo Roger , Claeys C. , Machkaoutsan Vladimir , Tomasini Pierre , Thomas Shawn , Ping Lu Jiong , Weijtmans J.W. , Wise Rick
Published: September 2007

This paper reports on the impact of the pre-epi bake conditions on the epitaxial growth of Si1 xGex Source-Drain (S/D) stressors as studied by p-n junction leakage analysis. It has been demonstrated that the presence of impurity-related (O, C) defects located at the epi/substrate interface, can act as nucleation sites for misfit dislocations, which degrade device performance. It has been shown that the area current density decreases exponentially with the pre-epi bake temperature. An empirical approach has been developed to quantify the leakage current enhancement due to the formation of the impurity-related (O, C) defects present at the epi/substrate interface, when the pre-epi bake is insufficient to remove the interface contamination. Moreover, the impact of the waiting time before the loading of the wafer inside the reactor on the defect creation is discussed. Finally, it has been demonstrated experimentally that the study of p-n junction characteristics is a highly sensitive technique for the assessment of the quality of the epitaxial interface, when C and O levels at the epi/substrate interface approach the SIMS detection limits.
Material Characterization Issues of Nitrogen in Silicon
Authors: Alt Hans C.
Published: September 2007

Nitrogen doping is considered a most important technique for the improvement of defect-related properties of CZ and FZ silicon. The present status of experimental techniques for the diagnostics of nitrogen in its various configurations is reviewed. Infrared spectroscopy on the local vibrational modes of nitrogen and the electronic transitions of nitrogen-oxygen complexes has the highest potential for the routine assessment of nitrogen. Recent progress in clarification of the structural identity of nitrogen-oxygen complexes allows an extremely sensitive detection of nitrogen in CZ silicon and gives new insight into the mechanisms of interaction between nitrogen and oxygen.
Characterization of Pinhole in Patterned Oxide Buried in Bonded Silicon-on-Insulator Wafers by Near-Infrared Scattering Topography and Microscopy
Authors: Wu Xing , Uchikoshi Junichi , Hirokane Takaaki , Yamada Ryuta , Arima Kenta , Morita Mizuho
Published: September 2007

Patterned oxides buried in bonded silicon-on-insulator (SOI) wafers before thinning have been characterized by near-infrared scattering topography and microscopy combination system. The micron-scaled pinhole in oxide patterned buried in the bonded SOI wafer has been observed by the scattering topography. The edge of the patterned oxide has also been observed by both scattering topography and transmission microscopy. With the combination of scattering topography, transmission and reflection microscopy, this system is effective to evaluate the visibility of the patterned oxide buried in the bonded SOI wafer.
Evaluation of Surface Defects in Silicon on Insulator using Modified HF Defects and Cu Decoration Method (HCM)
Authors: Lee Eun Joo , Lee Ki-Sang , Hwang Don-Ha , Lee Bo-Young
Published: September 2007

The control and evaluation of surface defects are important issues in SOI production. We introduce new a technique which is mixing of the HF dipping and Cu decoration method (HCM). HCM has high sensitivity to detect potential defects, such as small holes, imperfect top Si, imperfect buried oxide (BOX) and isolated BOX layer. Furthermore, the defects can be observed visually, so we can easily find the position and distribution of defects.
Characteristic of Junction Leakage Current with Bulk Micro Defect Density in p-n+ Junctions
Authors: Lee Woo Sung , Kim Ja Young , Kim Kwang Salk , Lee Ki Sang , Hwang Don-Ha , Lee Bo Young
Published: September 2007

We investigated the correlation between the junction leakagecurrent and bulk micro-defect (BMD) density for p-n+ junctions fabricated on Czochralski (CZ) Si wafers. In order to measure BMD, the wafers were annealed at 800oC for 4hr, followed by 1000oC for 8, 16, and 24 hr in a N2 ambient. After that, they were polished by 15 μm to remove the denuded zone (DZ) to disclose the BMD for detection using p-n+ junctions. We confirm the junction depth and dopant concentration of the p-n+ junctions by using secondary ion mass spectrometry (SIMS). After the electrical measurements we confirmed that the junction leakage current increases with increasing BMD density. The correlation factor between the junction leakage current and BMD density was about 99%.
X-Ray Metrology for the Semiconductor Industry
Authors: Bowen Keith , Ryan Paul
Published: September 2007

The scaling of traditional CMOS processes, and their associated metrologies, to produce smaller and faster devices was very successful down to the 90 nm node. However, to progress further, it has been found necessary to use novel materials, for which established metrologies are inadequate. In this article we demonstrate with examples that X-Ray Metrology (XRM) methods are particularly well-suited to provide characterization and measurement of the new materials systems being considered for advanced silicon processing, and for meeting the requirements of sub-90 nm nodes. These methods can be used for materials research, process development and integration and for in-line process control of product wafers.
Permittivity Enhancement of Mechanically Strained SrTiO3 MIM Capacitor
Authors: Kuroki Shin-Ichiro , Toda Masayuki , Umeda Masaru , Kotani Koji , Ito Takashi
Published: September 2007

The possibility of strain engineering on SrTiO3 high-k insulator was discussed. The tensile strain on SrTiO3 thin films increased dielectric constant, and as a frequency became higher, the increment of dielectric constant increased. The mechanism of the tensile strain-induced capacitance increase was also discussed. The tensile strain reduced a damping of titan-oxygen oscillator in SrTiO3 film, and titan-oxygen dipole moment was increased.
Application of Scanning Probe Microscopy Techniques for Structural and Electrical Characterization of Dielectrics, Carbon Nanotubes and Nanoelectronic Devices
Authors: Schwalke Udo
Published: September 2007

The challenges in the metrology of nanoelectronic structures demand for powerful and cost-efficient diagnostic techniques. In recent years, scanning probe microscopy techniques, like atomic force microscopy (AFM), have become indispensable tools for non-destructive characterization at the nanometer scale. More recently, the topographic imaging capabilities of the AFM have been extended by implementing current sensing techniques so that a direct correlation of a feature location with its electrical signature is possible. Several examples on the application of combined AFM and conductive AFM techniques will be presented in order to illustrate the potential of the SPM technique for structural and electrical characterization of semiconductor surfaces, dielectrics, carbon nanotubes as well as fabrication of nanoelectronic devices.
Manifestation of Cu Impurities on Silicon Surfaces, Implication for Monitoring Cu Contamination
Authors: Wilson Marshall , Savtchouk Alexandre , D'Amico John , Tasarov Igor , Jastrzebski Lubek , Lagowski Jacek
Published: September 2007

The electrical manifestations of Cu on silicon surfaces were investigated using Contact Potential Difference (CPD) and ac-Surface Photovoltage (SPV) measurements of Si intentionally contaminated with Cu. The corresponding physical model involves Cu-induced surface states. The Cu-induced negative surface charge is manifested by an increase of the work function and a decrease of the surface depletion barrier,Vsb, in p-type Si and an increase in n-type Si. The SPV manifestation of Cu is a decrease of the surface lifetime, tau s. These manifestations should enable Cu monitoring within the 1e8 atom/cm2 range. In practice, this limit is not reached because only a small fraction of surface Cu is electrically active. This obstacle is overcome using an optical surface treatment that electrically activates surface Cu and isolates the Cu contribution. With this approach we demonstrated Cu detection in the 1e9 atoms/cm2 range using Vsb and in the 1e10 atoms/cm2 range using tau s.
Implementing ALD Layers in MEMS Processing
Authors: Puurunen Riikka L. , Saarilahti Jaakko , Kattelus Hannu
Published: September 2007

Layers manufactured by the ALD technique have many interesting applications in microelectromechanical systems (MEMS), for example as protective layers for biocompatible coating, high-dielectric-constant layers, or low-temperature conformal insulating layers. Before an ALD process can be successfully implemented in MEMS processing, several practical issues have to be solved, starting from patterning the layers and characterizing their behaviour in various chemical and thermal environments. Stress issues may not be forgotten. We have recently implemented two ALD processes, namely the trimethylaluminium/water process to deposit Al2O3 and the titanium tetrachloride/water process to deposit TiO2 in our MEMS processing line and carried out the necessary characterization, details of which are reported here. For us, ALD has been a truly enabling technology in the processing of a three-dimensional micromechanical compass based on the Lorentz force, where Al2O3 acted as a pinhole-free electrical insulation grown at low temperature.
Application of Atomic Layer Deposition for Gas Permeation Barrier Thin Films
Authors: Carcia Peter F. , McLean Robert , Groner Markus , Dameron Arrelaine , George Steven
Published: September 2007

We determined by a Ca-test with optical modeling that a 25 nm thick Al2O3 film, grown by atomic layer deposition on polyester, reduced the effective water vapor transmission rate to < 10-5 g-H2O/m2-day. This is a reduction of more than 105x compared to the bare polyester. The corresponding diffusion coefficient for water vapor through this film was calculated to be D=2.5x10-17 cm2/s, and the threshold thickness for barrier properties was ~ 5 nm of Al2O3. We further concluded that these values were likely at the lower limit of this Ca-test method, because of edge diffusion of gas through the epoxy seal in the test structure.
An Ab Initio Evaluation of Cyclopentadienyl Precursors for the Atomic Layer Deposition of Hafnia and Zirconia
Authors: Zydor Aleksandra , Elliott Simon , Leese Thomas , Song Fuquan , Rushworth Simon
Published: September 2007

Thin film dielectrics based on hafnium or zirconium oxides are being introduced to increase the permittivity of insulating layers in nanoelectronic transistor and memory devices. Atomic layer deposition (ALD) is the process of choice for fabricating these films, and the success of this method depends crucially on the chemical properties of the precursor molecules. Much promise is shown by Hf and Zr precursors that contain cyclopentadienyl (Cp=C5H5-xRx) ligands. We have carried out ab initio calculations of a range of heteroleptic metallocenes [M(Cp)4-n(L)n], M=Hf/Zr, L=Me and OMe. Based on optimized monomer structures, we analyze reactivity with respect to ligand elimination, independent of surface effects, and thus compare the reactivity of the Cp-based precursors with amines and halides. The order in which different ligands are eliminated during ALD follows their energetics. The utility of computed dipole moments in predicting precursor volatility is discussed.
Developments in the Understanding of ALD Processes and Applications of ALD in Critical Technologies
Authors: Pemble Martyn , Povey Ian , Chalvet Francis
Published: September 2007

In part 1 of this paper the use of near-IR diode laser spectroscopy to detect short (<20 ms) gas pulses entering a reactor under ALD growth conditions is demonstrated using water and ammonia as example gases. The subsequent decay of the diode laser signal due to absorption of the target species is shown to depend on the reactor design and pumping characteristics. In part 2 of this paper the modification og colloidal photonic crystals using the ALD growth of Al2O3 and VOx is described. Al2O3 growth is shown to be extremely conformal and capable of producing patterned substrates using the colloidal photonic crystal as a mask. VOx growth is shown to produce a photonic crystal possessing an easily observable thermochromic shift in stop band.
Ultra- Thin Conformal Pore-Sealing of Low-k Materials by Plasma-Assisted ALD
Authors: Cecchi Joseph L. , Brinker C. Jeffrey , Jiang Ying-Bing
Published: September 2007

We have developed a plasma activated atomic layer deposition (PA-ALD) process to produce a few-nm-thick conformal SiO2 cap layer that seals the pores of patterned and unpatterned self-assembled mesoporous low-k dielectric films for integrated circuit fabrication. Tetraethoxysilicate plus O2 and hexamethyldisilazane plus O2 were used as the ALD precursors. In both cases, the plasma was formed in Ar and O2 during the O2 exposure step. By choosing the plasma conditions appropriately, we were able to ensure that unlike conventional ALD, the SiO2 deposition did not occur in the pores. We found that the PA-ALD process did not change the dielectric constant of the mesoporous film. Additionally, we found that for a 1.6 nm thick film, the N2 permeance of the capped film was reduced by a factor of 1600 compared to the uncapped film.
Stress Reduction of Ge2Sb2Te5 Crystallization by Capping Al2O3 Film Grown by PEALD
Authors: Park Young Sam , Lim Jung Wook , Yang Woo Seok , Lee Seung Yun , Yoon Sung Min , Yu Byoung Gon
Published: September 2007

Ge2Sb2Te5 (GST), the key phase change material in PRAM (Phase-change Random Access Memory) is accompanied by volume- and stress-changes during its crystallization. This suggests that the changes may induce reliability issues of PRAM. In this work, the stress is reduced by half by capping GST with Al2O3 film. To maintain amorphous-GST state of as-fabricated samples, GST was sputtered at room temperature and Al2O3 was grown by PEALD (Plasma Enhanced Atomic Layer Deposition) method at 120oC. To accomplish GST crystallization, heat treatment was conducted. After the heat treatment, radius changes were measured using thin film stress measurement system and stress changes were calculated using the Stoney equation.
Aqueous Ge Atomic Layer Deposition on Au
Authors: Liang Xuehai , Jayaraju Nagarajan , Stickney John L.
Published: September 2007

Electrodeposition of germanium on gold has been investigated by means of cyclic voltammetry and EQCM. The data from CVs and EQCM yielded a picture of the Germanium deposition process. An apparent underpotential deposition feature appears between -0.25V to 0.93V. The deposition of Ge appeared to start with the Ge (IV) species reducing to GeOH, with subsequent reduction to GeH. Below -0.93V, a limited amount of a bulk Ge species begins to form. The charges for oxidative Ge stripping was a function of the potential and time used for deposition, and the pH of the solution used. The maximum Ge stripping charge was observed for pH 9, and appeared independent of the concentration of germanium dioxide used. Work is continuing on development of a cycle for the deposition of Ge using electrochemical ALD.
Yield Improvement Using Cryogenic Aerosol for BEOL Defect Removal
Authors: Lauerhaas Jeff , Kok Yav San , Hamzah Ameer , Tan Ling Tze
Published: September 2007

A dry, cryogenic aerosol has been integrated into an advanced copper low k dielectric process flow for defect removal. The cryogenic aerosol is able to remove particulate defects from the exposed substrate materials without etching, charging or altering the conducting or insulating properties of the exposed materials. In this work, the cryogenic aerosol is composed of a mixture of argon and nitrogen. The results have confirmed high defect removal efficiency ultimately resulting in a yield increase. The application of a wet clean was not possible without adverse, yield decreasing side effects. Three BEOL processing steps will be covered in this work. The three steps are defect removal after via etch, film deposition, and in-line electrical probe.
Thermal Cleaning of Silicon Nitride with Fluorine and Additive Mixture
Authors: Shigemoto Takamitsu , Sonobe Jun
Published: September 2007

We describe improved gas mixtures for the thermal cleaning of low pressure CVD reactors used for silicon nitride deposition. F2 and HF mixture are widely used for thermal chamber cleaning today, however the F utilization rate is low, and the required cleaning temperature is higher than desired for productivity and equipment maintenance considerations. We identified NO as a promising low concentration additive that could be used to enhance the performance of fluorine. While F2 - N2 mixtures were unable to thermally clean CVD chambers with an acceptable rate, small additions of NO dramatically improved the cleaning rate. We performed numerous experiments to optimize the thermal cleaning condition. A thermal cleaning temperature of 300C, and a cleaning gas composition of 10% F2, 2% NO with a balance of N2 at 10Torr was the best recipe identified. Experiments were also performed to clarify the gas phase chemistry and to indicate the role of the NO for improving the thermal cleaning process.
Removal of Organic Wax and Particles on Silicon after Batch type Polishing by Ozonated DI Water
Authors: Yi Jae-Hwan , Lee Seung-Ho , Kim Tae-Gon , Park Jin-Goo , Lee Gun-Ho , Bae So-Ik
Published: September 2007

To manufacture the wafer used for device chip, several polishing and cleaning process are required. In this study, new concept cleaning process was developed with ozonated DI water (DIO3) to achieve low COO (cost of ownership). Ozone concentration of 55 ppm is used to remove the wax film and particles. A commercial dewaxer was combined with DIO3 to reduce dewaxing time and SC-1 steps. DIO3 rinse resulted in less than 50Aå of wax thickness while DI water rinse did thicker than 300 Aå. Replacing DI rinse with DIO3 rinse resulted in lower contact angle and completely hydrophilic surface. Optical images of surfaces treated with DIO3 showed thinner wax layer which indicates no further cleaning steps required. Particle removal efficiency improved further by combining SC-1 cleaning step with DIO3 rinsing process.
High Efficiency Wafer Backside Cleaning with Full Coverage Megasonics Spin Process
Authors: Xie Bo , Park Sung Won , Han Jung Ho , Li Z Fred , Gouk Roman , Lu Wei , Jeon Chung H. , Subbaraman Ven , Child Kent , Wright Jason , Papanu James , Tang Jianshe
Published: September 2007

As the technology node scales down to 45nm and beyond, removal of particles and metal contamination from wafer backsides have become critical for advanced lithography with smaller depth of focus, as well as to enable efficient metrology tool sharing between various applications. Smaller particles are usually held by van der Waals' force, and removal of these particles usually requires mechanical force, such as acoustic energy which creates cavitation. Just as the wafer frontside, backside cleaning requires full liquid coverage for high efficiency cleaning. Backside clean with full coverage backside megasonics can achieve higher particle removal efficiency (PRE), especially for smaller particles. In this paper, we report a novel full coverage backside megasonic spin process that demonstrates high PRE and metal contamination removal and achieve high PRE for advanced lithography and wafer metrology.
Post Ion-Implant Photoresist Removal via Wet Chemical Cleans Combined with Physical Force Pretreatments
Authors: Totir George G. , Frank Martin , Vos Rita , Arnauts Sophia , Bearda Twan , Kenis Karine , Delande Martine , Le QuocToan , Kesters Els , Vereecke Guy , Mannaert Geert , Lux Marcel , Hoflijk Ilse , Conard Thierry , Banerjee Souvik , Malhouitre Stephane , Leunissen Leonardus H.A. , Mertens P.
Published: September 2007

A combination of wet chemistry and high-velocity solid CO2 aerosol pre-treatment was used to remove ion-implanted resist from patterned Si structures. The top resist surface is modified by heavy ion-implantation forming a crust ~100nm thick. The aerosol treatment, which is aimed at breaking and partially removing the crusted top layer of implanted resist, produces circular openings in this surface, with diameters on the order of tens to hundreds of micrometers. No resist is detected by either optical microscopy or localized SEM inspection, after immersion in hot SPM mixture, on aerosol-pre-treated wafer fragments. In contrast, resist residue is still observed on similarly pre-treated specimens, after immersion in either N-methyl pyrrolidone or Microstrip2001{trade mark, serif}, even under ultrasonic agitation. Overall, the aerosol pre-treatment is a key step in reducing the amount of resist residue, for both aqueous-based and solvent-based wet cleaning. Full-wafer defect-count results, post aerosol treatment, are reported for poly-Si line widths down to 40 nm.
Novel Wet Photoresist Strip for Wafer Level Packaging
Authors: Verhaverbeke Steven , Zhao Jun
Published: September 2007

An important module of the packaging based on flip-chip is the formation of solder or Cu bumps. Solder bumps are usually defined lithographically with a thick photoresist mask. After the solder bump is built up, the photoresist needs to be stripped. Solder bumps are not compatible with photoresist ashing and FEOL strip chemistries. Hence, traditionally, photoresist strip with solder bumps exposed has been carried out with solvent strip chemistries. Over the last decade, there has been a lot of research on the use of ozone for photoresist stripping. However, no real breakthrough has happened because of the limited solubility of ozone in aqueous solution and hence it's extremely slow strip rates. In this work, we are describing a novel way of using ozone in solvent chemistries that have very high strip rates. This process is widely applicable, but is extremely useful for stripping photoresist with solder bumps exposed.
The Effect of Delay Between Dry Etch and Wet Clean Processing Steps on Cleaning of Post-Etch Residues
Authors: Hellin David , Vos Ingrid J. , Vereecke Guy , Pavel Elizabeth , Boullart Werner , Vertommen Johan
Published: September 2007

The benefits of the integration of wet cleaning using short and controlled exposure times with plasma dry etch processes have been investigated. Selectivity for post-etch residue removal versus substrate loss and the effect of delay time between etch and clean processes are investigated for shallow trench isolation (STI) and hardmask-based poly-silicon gate applications, including screening of process windows. Several hypotheses about the underlying mechanisms are formulated and tested against the experiment.
Challenges in Nickel Platinum Silicide Wet Etching for Sub-65nm Device Technology
Authors: Goh Felicia , Sih Vincent K.T. , Tan Wee Leng , Ismail Zainab
Published: September 2007

The wet stripping of unreacted Ni(Pt) and TiN using Aqua Regia, after Ni(Pt) silicidation, was evaluated in this study. It was observed that Aqua Regia attacked Ni(Pt) silicide formed at low annealing temperatures. Resultant degradation of silicided sheet resistance of narrow linewidth structures would outweigh the benefits of improved reverse linewidth effect and junction leakages. By using an optimum RTA temperature and Aqua Regia duration, an operating window could be established for low temperature Ni(Pt) silicidation process.
Effect of Particle Deposition and Wet/Dry Cleaning Methods on Particle Removal Efficiency
Authors: Kim Tae-Gon , Hu Shan , Busnaina Ahmed A. , Park Jin-Goo
Published: September 2007

The effect of wet/dry deposition methods and wet/dry cleaning methods on particle removal efficiency (PRE) was investigated. PRE strongly is strongly dependent on particle deposition and removal methods. IPA deposition method was easier to remove silica and PSL particles than DI deposition method when a dry cleaning, a laser shock wave cleaning was applied. DI water deposited PSL particles on both oxide and silicon nitride wafers are much easier to remove than IPA deposited particles in wet cleaning by DI water. However, PRE of silica particles did not show dependency on deposition methods.
Nano Particle Control on 300mm-wafers in Supercritical Fluid Technology
Authors: Inahara Junichi , Okamoto Ryuji , Kang Shin Chul , Nakahira Megumi , Hasegawa Shinichi , Takahagi Takayuki
Published: September 2007

The nano particle control in the supercritical fluid technology using CO2 (SCCO2) is extremely essential for SCCO2 to enter a 300 mm-Si-wafer semiconductor industry as a viable technology. In this study, we explored the basic particle removal behavior of SCCO2, varying the process recipe of the SCCO2 operation and the size of nano particles (PSL: polystyrene latex). The SCCO2 with Methanol as a non-solvent for PSL has indicated that PRE (particle removal efficiency) has the dependency of the nano particle size (weight) and hit the highest level of around 45 % on the smallest PSL (75 nm-dia.) particles. The SCCO2 with Pyridine as a solvent for PSL has shown that its PRE has a similar tendency as seen on Methanol, but indicates a higher level of around 55 % than that of the SCCO2 with Methanol.
Elimination of Post Cu-CMP Watermark by Optimizing Post CMP Clean to Control Cu Dissolution
Authors: Petitdidier Sebastien , Mellier Maxime , Trouiller Chantal , Euvrard Catherine , Juhel Marc
Published: September 2007

The continuous decrease of the effective dielectric constant of the dielectric stack forces Cu-CMP to either directly polish the low-k films or completely remove a higher-k protective cap layer on top of it. The exposure of hydrophobic low-k films to post CMP clean elicits the formation of watermarks on the inhomogeneous wetted patterned surface. In this study, we first confirm the benefit of IPA dryer vs. conventional spin dryer but also in improving the passivity of the Cu surface before the final water rinse by clean chemicals. The improvement in Cu passivity is correlated with lower Cu contamination on the dielectric surface.
Effect of Poly Silicon Wettability on Polymeric Residue Contamination
Authors: Kang Young-Jae , Park Jin-Goo , Hong Yi-Koan , Han Sang-Yeob , Yun Seong-Kyu , Yoon Bo-Un , Hong ChangKi
Published: September 2007

The adhesion and removal of the polymeric residues were investigated as a function of wettability of the poly Si surface during poly-Si CMP process. An oxidizer can make poly silicon surface more hydrophilic. Adhesion force between pad particle and poly Si wafer decreased and saturated as a function of concentration of oxidant. Much more pad particles with water marks were observed on hydrophobic poly silicon surfaces than on hydrophilic. The mechanism of wettability and high adhesion force of hydrophobic surfaces indicates that the controlling of the wettability of wafer surface played an important role in the adhesion and removal of organic residues on the poly Si surface. The control of poly silicon wettability during polishing could reduce the attraction force of organic particles thus lead to a lower organic defects after CMP.
Interface Characaterization in Nanoelectronics
Authors: Garfunkel Eric , Goncharova Lyudmila , Rangan Sylvie , Hsueh ChienLan , Celik Ozgur , Bartynski Robert , Gustafsson Torgny
Published: September 2007

A central requirement in the integration of III-V substrates in highly scaled CMOS gate stacks is to develop an ability to assure that we create a high capacitance, high mobility transistor structure with a low concentration of defects. In this contribution, recent studies of the compositional profile and interdiffusion of high-K gate stacks on III-V substrates are reviewed. Sulfur passivation methods have been explored to help ensure that the starting III-V surface (InGaAs in this case) has a low defect concentration. Diffusion processes associated with the introduction of oxygen-gettering metal gate materials will also be discussed.
Bonding States and Coverage Calculations for HfO2 Deposited on H2O Terminated Si (100)-2x1 Using Atomic Layer Deposition
Authors: Mathew Anoop , Wielunski Leszek S. , Opila Robert , Willis Brian
Published: September 2007

A one-cycle ALD growth reaction on the water terminated Si(100)-2x1 surface is shown to lead to successful nucleation, high metal oxide coverage, and an abrupt metal-oxide/silicon interface as confirmed by XPS, RHEED, and RBS measurements. Photoemission results confirm the coordination states of the hafnium and oxygen atoms. A Hf 4f core level shift is observed and assigned to the presence of the Si-O-Hf bonding environment with the more electronegative Si atom inducing the binding energy shift. This Hf 4f shift is smaller than that reported previously for silicates because of the difference of the semiconductor bonding environment. Experiments indicate that the hydroxyl sites bound to Si(100) are active for ligand exchange reactions. The abrupt interface could be useful for aggressive Effective Oxide Thickness (EOT) scaling.
Electrical Characterization Methodologies for the Assessment of High-k Gate Dielectric Stacks
Authors: Young Chadwin D. , Bersuker Gennadi , Heh Dawei , Neugroschel Arnost , Choi Rino , Kang Chang Yong , Tun Joey , Lee Byoung Hun
Published: September 2007

Various conventional and novel electrical characterization techniques have been combined with comprehensive analysis to properly evaluate high-k gate dielectric stack structures. These measurement methodologies and analysis techniques are intended to separate contribution from the pre-existing defects, which may serve as charge traps, from the stress-generated defects. In addition, the differentiation of electrically active bulk high-k traps and interfacial layer traps has been demonstrated.
Electronic Properties of Adsorbates on In0.37Ga0.63As(001)-(2×4)
Authors: Winn Darby L. , Grassman Tyler J. , Kummel Andrew C.
Published: September 2007

Molecular and electronic structures of In2O and Ga2O bonding to the As-rich In0.37Ga0.63As(001)-(2×4) surface were investigated using density functional theory (DFT) modeling. Calculated enthalpies of adsorption revealed that the bonding geometries of In2O and Ga2O on In0.37Ga0.63As(001)-(2×4) were essentially identical to those on GaAs(001)-(2×4). However, the calculated electronic structures resulting from the adsorbates/semiconductors systems exhibited subtle differences. Both oxides induced state density in the band gap consistent with Fermi level pinning on In0.37Ga0.63As(001)-(2×4) and GaAs(001)-(2×4). In addition, the state density worsened with increasing adsorbate coverage. However, a greater adsorbate density was required for the onset of Fermi level pinning for InGaAs than GaAs. This effect was attributed to reduction in band gap for In0.37Ga0.63As(001)-(2×4) vs. GaAs(001)-(2×4). Variations in the alloy structure of InGaAs (i.e. subsurface locations of In and Ga atoms) were found to play only a minor role on the resulting oxide adsorbate bonding geometries and electronic structures.
Dramatic Improvement of GeO2/Ge MIS Characteristics by Suppression of GeO Volatilization
Authors: Kita Koji , Suzuki Sho , Nomura Hideyuki , Takahashi Toshitake , Nishimura Tomonori , Toriumi Akira
Published: September 2007

We investigated thermal desorption behavior of GeO2 films and its impact on the electrical properties of GeO2/Ge MIS capacitors. It was clarified that the GeO desorption was driven by the interface reaction at GeO2/Ge during the annealing at 600oC, which was the origin of interface deterioration of the MIS capacitors. We found that a Si cap layer formed on top of GeO2 film could suppress the GeO desorption efficiently. Then a dramatic improvement of C-V characteristics was successfully demonstrated with GeO2/Ge MIS capacitors by employing FUSI process, where NiSiX electrode could work as a cap layer to suppress the GeO desorption. These results give us a quite important guideline to form high-quality dielectric/Ge interfaces.
First-Principles Investigation of (100)Ge/Ge(Hf)O2 Interfaces
Authors: Houssa Michel , Pourtois Geoffrey , Bellenger Florence , Caymax Matty , Meuris Marc , Heyns Marc
Published: September 2007

The structural and electronic properties of (100)Ge/GeO2 and (100)Ge/Ge(Hf)O2 interfaces are investigated, using density functional theory. It is found that the formation of Ge-O bonds or Hf-O-Ge bonds at or near the interface does not result in the presence of surface states in the Ge band-gap. On the other hand, the formation of a Ge-Hf bond at the interface, likely present if Hf is located in the sub-oxide interfacial layer (GeOx with x<2), result in the formation of a defect level in the upper part of the Ge band-gap, hampering the electrical properties of metal-oxide-semiconductor devices. These findings can explain recent results reported on Ge/GeOx/HfO2 gate stacks.
Microscopic Understanding of PBTI and NBTI Mechanisms in High-k / Metal Gate Stacks
Authors: Sato Motoyuki , Yamabe Kikuo , Shiraishi Kenji , Miyazaki Seiichi , Yamada Keisaku , Tamura Chihiro , Hasunuma Ryu , Inumiya Seiji , Aoyama Takayuki , Nara Yasuo , Ohji Yuxuru
Published: September 2007

We have established a comprehensive understanding of the PBTI and NBTI reliability of high-k/metal gate stacks. PBTI is found to exhibit a universal relationship, in terms of fast transient carrier traps and stress voltage, due to the formation of positive oxygen vacancies. The use of metal gates for Tinv scaling is promising for the improvement of drain current without PBTI lifetime degradation. However, in the case of NBTI, interface state degradation becomes more serious with Tinv scaling. Thus, the use of a high quality interfacial layer, such as a wet oxide interface, is a promising solution for the improvement of NBTI lifetime.
Role of Bulk HfO2 and Interfacial SiO2 Layer in Breakdown Characteristics of TiN/HfO2/SiO2/Si Gate Stacks
Authors: Rahim Nilufa , Chowdhury Naser , Misra D.
Published: September 2007

Defect generation in the interfacial SiO2 layer seems to be the leading breakdown mechanism in metal/high-k/interfacial layer/Si gate stack. In this work we reaffirm the claim by studying systematically the breakdown mechanisms of HfO2 and SiO2 separately, deposited under same growth conditions. Individual breakdown characteristics of HfO2 without any interfacial layer using MIM capacitors and in situ steam grown (ISSG) SiO2 MOS capacitors with of identical thicknesses were compared (I-t, Stress-induced leakage current) to that of the high-κ/IL/metal gate stack. It was observed that charge trapping and stress-induced trap formation in the interfacial layer continues to be the soft spot for grate stack breakdown.
Stability of Pt-Ru/C Catalysts: Effects of Ru Content
Authors: Yamada Hirohisa , Shimoda Daisuke , Matsuzawa Koichi , Tasaka Akimasa , Inaba Minoru
Published: September 2007

Stability of four kinds of commercially available Pt-Ru/C (Pt:Ru = 1:1 for Samples A1, B1, and C1, and Pt:Ru = 1:2 for Sample B2) anode catalysts was investigated in 0.5 M H2SO4 by potential cycling. When the upper limit was set at potentials higher than 0.4 V, all Pt-Ru(1:1)/C samples were unstable and Ru concentration on the surface decreased during potential cycling tests. The degradation rate increased with increasing the upper potential limit. On the other hand, Samples A1 and B1 showed different tendencies in stability in the potential range of 0.05 to 0.2 V, depending on the crystallinity and the surface state (e.g. the presence of RuOx). Sample B2 (Pt:Ru = 1:2) had a higher stability than Sample B1 (Pt:Ru = 1:1) at high potentials > 0.4 V. On the contrary, the former had an inferior stability in the potential range of 0.05 to 0.2 V.
Analysis of Reactant Gas Transport in a Catalyst Layer
Authors: Mashio Tetsuya , Ohma Atsushi , Yamamoto Shinji , Shinohara Kazuhiko
Published: September 2007

An analytical in-situ technique was investigated for evaluating reactant gas transport in a catalyst layer of a fuel cell using limiting current measurements. It was hypothesized that the reactant gas diffusivity in the catalyst layer might be found from the other transport resistance, including Knudsen diffusion resistance and transport resistance through the ionomer and liquid water, when a GDL without an MPL was used. The other transport resistance was estimated by subtracting the molecular diffusion resistance from the total gas transport resistance obtained by measuring the limiting current. The correlation between the catalyst layer specifications, specifically the ionomer carbon weight ratio, and the gas diffusivity in the catalyst layer was investigated using this technique. The results showed that the other transport resistance increased with a larger I/C ratio. It was considered that the difference in porosity due to the variation of the I/C ratio affected the Knudsen diffusion coefficient.
Effect of Porosity Distribution of Gas Diffusion Layer on Performance of Proton Exchange Membrane Fuel Cells
Authors: Shi Zhongying , Wang Xia , Draper Owen
Published: September 2007

The gas diffusion layer (GDL) is an important and integral part of the proton exchange membrane(PEM) fuel cell. The porosity of the GDL is not uniform due to the compression by the shoulder of the bipolar plate and the accumulation of water produced on the cathode side. In this study, the GDL porosity variation due to both compression and water production is investigated. Four types of porosity distributions are investigated. Using a 2D isothermal single phase PEMFC model, the simulation results under various porosity distributions are compared with the experimental data. The results show that the compression by shoulders affects the local current density distribution, especially under the shoulder of bipolar plates, and the water accumulation affects the local current density distribution along the electrode. The porosity distribution which considers both compression and water accumulation effects is shown to provide a better prediction of the cell performance.
Harmonizing of Experiment and Computation Model for Estimating Cell Performance and Water Distribution Inside of Polymer Electrolyte Membrane
Authors: Moon Cheor Eon , Yang Jang Sik , Choi GyungMin , Kim DuckJool
Published: September 2007

In this study, we estimated the performance of PEMFC as changing operating temperature in different inlet humidity condition at cathode side but anode dry, and tried to match experimental results with 1-dimensional simulation to construct database for advanced computation model. We used Nafion®112 membrane and a self-manufactured PEMFC with 25cm2 active area was used. The range of operating temperature was 40~70{degree sign}C and oxygen through bubbled humidity chamber was supplied 0~80% humidity condition as changing water temperature in humidity chamber. For figuring out governing equations express water contents in electrolyte membrane, the linear forward difference method was applied about time progress and quadratic central difference method was used about space progress. In low operating temperature condition, 40~60{degree sign}C, increasing temperature rarely effected cell performance but we can see performance drop at 70{degree sign}C. By modifying Henrry's constant and/or diffusion coefficient, the modified one-dimensional model was accomplished for calculation.