bluuebunny/crossref_metadata_2025 huggingface dataset:
Resistive Switching Characteristics of VOX Thin Films Deposited onto Cu Buffer Layer
Authors: Wei Xiaoying , Hu Ming , Zhang Kailiang , Wang Fang , Miao Yinping , Zhao Jinshi
Published: March 2012

This paper is focused on the effect of annealing time on resistive switching characteristics of Cu/VOX/Cu memory units. VOx thin films were prepared on Cu substrates by reactive sputtering and annealed under vacuum for 30min, 60min, and 90min, respectively. AFM and XRD were employed to characterize the morphology and crystalline component of the films. Electrical switching properties were characterized by Semiconductor Device Analyzer. The apparently morphology change and phase transition of the VOx thin films were not observed. I-V curves showed that the forming voltages decreased with the increase of annealing time. The sample was annealed for 30min exhibited a reversible resistive switching behavior, while which were annealed for 60min and 90min did not show the same behaviors. It is considered that annealing time influenced the Cu buffer layer, and Cu atoms play an important role on resistive switching characteristics of the Cu/VOX/Cu structure.
CMOS Technology Scaling for System-On-Chip Integration - Past, Present and Future
Authors: Jan Chia-Hong
Published: March 2012

The challenges of System-on-Chip (SoC) technology scaling are reviewed. It is shown that the key ingredients of an SoC process technology, including high performance logic transistors, low power transistors, high voltage transistors, memory, passives, analog and RF features are all benefited by Moore's Law. State-of-the-art CMOS technologies are powered by not just dimensional scaling, rather it incorporates the introduction of innovative device structures, development of the new materials and construction of new manufacturing equipment. It is expected that Moore's Law and CMOS scaling will continue in the near future, being powered by 3-D innovations in transistors, interconnects and packaging, supported by new materials and equipment.
Contact Resistance Study in MOCVD TiN Process
Authors: Han Jerry , Li Bigtree , Zhang Ji-Wei , Jiang Jian-Yong , Lin Paul-Chang
Published: March 2012

ILB (Integration liner barrier) is the combination of IMP (Ionic Metal Plasma) Ti and MOCVD (Metal-Organic-Chemical-Vapor-Deposition) TiN, which is widely employed in semiconductor manufacturing as a tungsten glue/barrier layer. Contact resistance is the parameter to measure the performance of ILB and the W process. The TiN process plays a very important role in the performance of contact resistance. In -previous studies, process temperature and RF power treatment post process -was shown to influence contact resistance directly (1,2). In this paper, the influence of chamber condition before processing was studied, then some index is given to monitor these phenomena and prevent contact resistance fail.
Optimization of Metallization Processes for 28-nm-Node Low-k /Cu Multilevel Interconnects
Authors: Bao Yu , Jing Xuezheng , Tan Jingjing , Ping Yanlei , Zhang Ziying , Xiao Haibo , Wang Xiaona , Bai Fanfei , Zhang Beichao
Published: March 2012

As design rules shrink, integrated circuits speed becomes more impacted by low k (LK) dielectric / Cu back end of line (BEOL) interconnects. At 28 nm node, the copper line aspect ratio (AR) is usually equal to or greater than 2.5, and the line trench gap-fill AR is even bigger (> = 3.5). This makes the BEOL copper metallization very challenge, but a Cu void-free dual damascene gap-fill performance must be delivered. In this study, 28nm interconnect development experiments were carried out, and a comprehensive analysis of gap-fill improvement was conducted, based on titanium nitride (TiN) metal hard mask (MHM) integration scheme. This MHM scheme may have increased the aspect ratio of copper line due to the existence of the remaining TiN layer and its beneath sacrificial films. Furthermore, in the conventional physical vapor deposition (PVD) barrier / seed process, the overhang of barrier / seed at top corner will be enlarged significantly due to the nature of physical vapor deposition (PVD) re-sputtering. When hydrogen peroxide (H2O2) clean was used to recess TiN layer, the protruded underneath dielectric layer is modified to form a triangle shaped trench entrance. The deformed trench entrance would increase Cu seed deposition rate at the top corner and further enhance the overhang feature. This paper shall report the latest success of the 28nm Cu / low-k BEOL development.
Optimization of Slurry and Technological Parameter on Chemical Mechanical Polishing of Titanium Dioxide Film for IC
Authors: Ren Jun , Zhang Kailiang , Wang Fang , Zhang Taofeng , Yuan Yujie
Published: March 2012

Titanium dioxide (TiO2) has shown a great potential to be used in resistive random access memory, capacitor, solar cell and sensor. However, the surface topography as-deposited TiO2 film cannot meet the requirement of IC. Therefore, TiO2 film must be flattened before apply into semiconductor device. In this paper, chemical mechanical polishing (CMP) was used for polishing TiO2 film. We studied the effect of slurry pH of polishing from the viewpoint of chemical we found the removal rate with acid slurry is lower than the removal rate obtained by alkali slurry. The effect of the process parameter such as down force, platen rotation rate were also studied in detail and found the removal rate still exist when there is no pressure and velocity, hence Preston equation was slightly modified. Final, the surface roughness was reduced from 36Aå to 1.2Aå, and the removal rate was up to 38.2nm/min.
Novel CuCMP Slurry Evaluation for 45/40nm BEOL Low-k Technology and Beyond
Authors: Zhao Feng , Liu Hongtao , Hu Tony , Chen Feng , Liu Kent , Deng Wufeng , Cao Junzhu , Zhou Sky , Zhang Jason , Zhou Erico , Song Kerry , Zhao Jun , Bao Ethan , Chen Larry
Published: March 2012

Novel CuCMP slurry was evaluated under different polishing conditions and its impact on topography, thickness and in line test performance was investigated. Generally, topography, such as dishing and erosion, results from over-polishing after Cu polishing step and it can be modified and reduced by fine tuning process parameters. Firstly, different Cu polishing condition has been attempted to produce different topography for barrier polishing to compensate in order to cater for different integration scheme with different oxide material. Secondly, topography can be modified by barrier polishing condition due to high selectivity slurry is used during barrier polishing. Longer polishing time can cause Cu protruded in narrow dense arrays. Electrical data shows Cu polishing overpolishing time has impact on Rs, and longer overpolishing results in higher Rs, as well as high head/platen rotation speed.
CMP Slurry and Process Development for TSV Front-Side Polishing
Authors: Xu Jinhai , Lin Paul-Chang , Li Pei , Zhu Tony , Ma Zhiyong , Chen Danny , Pang Keliang , Wang Xucheng , Wang Yuchun
Published: March 2012

3D integration utilizing TSV (Through-Silicon Via) is a promising technology to achieve high performance 3DIC (three-dimentional integrated circuit), not only because it exponentially increases connection efficiency between dies, but also because it can be practically integrated into current IC manufacture processes with minimal impact on both FEOL and BEOL design and processing. During construction of TSV, CMP (Chemical-Mechanical Polishing) is required to reveal the vias and finish the wafer surface for future processing. Reported in this paper is our recent effort in developing a series of slurries for TSV front-side polishing by close collaboration in device design, slurry formulation and process fine-tuning. Specifically, high through-put and well performed Cu slurries, along with high SiO2/Si3N4 selectivity barrier slurries, are introduced. These slurries are tested on laboratory-scale instruments as well as foundry CMP tools. Polishing results from both blanket and pattern wafers are discussed.
Application of Real-Time Cu Thickness Profile Control in Cu CMP
Authors: Tan Changxing , Zhang Weifeng , Huang Oliver , Gao Hanson , Zhao Runtao , Zhu Zhize
Published: March 2012

In this paper, a real-time profile control (RTPC) system in Cu CMP is introduced. The system mainly contains two parts: 1). Real-time metal thickness monitoring based on electromagnetic induction of eddy current in conductive metal layer; 2). Real-time new polishing pressure computing and adjusting for desired metal thickness profile. The RTPC system has been applied in bulk Cu removal step of Cu CMP. The result showed that the Cu thickness profile after bulk Cu removal was flatter and its WIW uniformity was improved by greater than 35% while WTW uniformity could be improved by greater than 65%.
CMP Defects; Their Detection and Analysis on Root Causes
Authors: Park Jin-Goo , Kwon Tae-Young , Venkatesh R. P. , Cho Byoung-Jun
Published: March 2012

Particles and scratches are most wanted defects to be minimized in CMP processes. The root causes for them are mostly consumables related such as pad, slurry and diamond conditioning. The evaluation of additives in slurry is neglected in terms of their defect generation on wafer. The adhesion force can be measured between particle and wafer surface in given chemistry to select the additive which causes least particle contamination in both slurry and cleaning solutions. Also, the scratch detection and analysis are very time consuming and require advanced methodology even in wafer production facility. The lab scale scratch detection method was developed to study the effect of slurry and conditioning on wafer during CMP. In this presentation, we report the utilization of particle adhesion force on CMP process development and the detection of scratches on oxide wafer. The effect of slurry, pad and diamond conditioner on scratch formation was investigated with their classification
Development of Post-CMP Cleaners for Better Defect Performance
Authors: Tran Cuong , Zhang Peng , Sun Laisheng , Penta Naresh K. , Lagudu Uma Rames K. , Shipp Devon , Babu S.V
Published: March 2012

In the copper CMP process, organic residues that are related to Benzotriazole (BTA) adsorbed on copper surface after Cu CMP process have to be removed during the cleaning. In order to address this organic defect issue, we present here the study of the performance of BTA removal by post-CMP cleaners using copper particles as substrates instead of copper wafers. In this work, different copper particles including Cu(0), Cu(I) and Cu(II) oxide particles with high surface area, were chosen to study the removal of BTA adsorbed on different copper states. TGA and UV-Vis spectra were used to detect and quantify the BTA removal efficiency. The results by different post CMP cleaners on various Cu particles will be presented.
Evaluation of Hydrogen Peroxide on Chemical Mechanical Polishing of Amorphous GST
Authors: Wang Liangyong , Song Zhitang , Liu Weili , Liu Bo , Zhong Min , He Aodong , Feng Songlin
Published: March 2012

As chemical mechanical polishing (CMP) becomes an essential step for fabrication phase change memory (PCM) device, industry always concerns that aggressive chemical components in the slurry might affect the composition and reliability of the phase change material Ge2Sb2Te5 (GST). In this study, we evaluated typical slurry component hydrogen peroxide on amorphous GST CMP. Silica-based slurries without H2O2 and with H2O2 at low (0.5wt%) and high concentrations (5wt%) were used for investigation. First, the polishing performance was compared. Then, auger electron spectroscopy (AES) was adopted to analyze the depth profile of Ge, Sb, Te and O for GST samples processed by different concentrations' H2O2. We also evaluated the phase change properties as a function of ageing time for those samples. To further evaluate the effect of H2O2 induced surface oxidation layer on PCM device, thermal simulation was used to compare the difference of thermal consumption and distribution during the operation.
An Analytical Model for Contact Height and Contact Pressure in Chemical Mechanical Polishing (CMP) for Different Pattern Structure
Authors: Wu Lixiao , Yan Changfeng
Published: March 2012

Pattern structures have a great effect on CMP. Predicting the evolution of pattern structures in CMP is important in pattern design and in polishing parameters determination. Determining the contact pressure between the wafer and the pad in CMP and the contact height at which the pad will be in continuous contact with the profile on the wafer is essential for the pattern evolution calculation. An analytical model for calculating the contact pressure and the contact height for different pattern structure is proposed in the paper. The evolutions of pattern structure with different pattern densities are simulated and compared with the experimental data.
WCMP Endpoint Application for the Dishing Erosion Improvement
Authors: Huang Zhipeng , Zhang Weifeng , Tan Changxing , Xu Ying , Zhao Runtao , Zhu Zhize
Published: March 2012

In the semiconductor manufacturing industry, W CMP has been widely used in both in FEOL and BEOL. However, in the advanced technology (≤65nm), WCMP is used primarily in FEOL. For FEOL WCMP process, dishing erosion performance is very critical. If the dishing erosion performance is not good, the downstream Cu CMP process will be impacted resulting in copper residue and potential yield loss
An Analytical Model of Contact Pressure Caused by 2-D Wafer Topography in Chemical-Mechanical Polishing Process
Authors: Wu Lixiao
Published: March 2012

Topography on wafer surface affects chemical-mechanical polishing (CMP) greatly. In this paper, 2-D wafer topography's effects on the contact pressure in CMP are investigated and calculated. It is found that the wafer can be treated as a rigid punch and pad as an elastic half space when the effects of the pattern features on the wafer surface are investigated. Based on the linear small strain theory of elasticity, the formula of calculating the contact pressure between the wafer and the pad is given. The performance of CMP system is shown to be a linear time invariant (LTI) system in a mathematical way. The magnitude spectra and phase spectra of the system are obtained exactly by the formula. The contact pressure for 2-D wafer topography during CMP can be calculated easily by the formula.
Process Variation Improvement and Stress Analysis of Contact Module
Authors: Luoh Tuung , Liao Hsiang-Chou , Chen Po-Chou , Yang Ling-Wu , Yang Tahone , Chen Kuang-Chao , Lu Chih-Yuan
Published: March 2012

Process window simulation results are implemented into a yield drop case induced by ILD contact module process shift. Signatures of blind voltage contrast and ILD thickness variation coincide with failure map of wafer sort. Lower down the edge pressure of ILD CMP and increase the O2 flow ratio in BPSG SACVD process can well-control the ILD CMP thickness variation within 500A, and get more uniform dopant distribution in ILD layer. Yield is back to normal after processes optimization.
Erasing Characteristics of Stacked-Gate Flash Memories with High-k Dielectrics
Authors: Chen Yung-Yu , Lin Yi-Xiang
Published: March 2012

By 2-D MEDICI simulation, flash memories with high-k IPDs clearly exhibit significant improvement in SFN erasing speed over those with conventional ONO IPD. Choosing HfO2 as the IPD, erasing voltage can be reduced larger than 48% at a typical 0.1ms erasing time due to significantly improved gate coupling ratio. However, effects of high-k TDs on erase performance of the stacked-gate flash memories with fixed HfO2 IPD is quite contrary with respect to the improvement observed for the flash memory with high-k IPDs. Due to reduced gate coupling ratio, erasing speed of the stacked-gate flash memories with high-k TDs using SFN tunneling is helpless. Compared to the flash memory with HfO2 IPD and SiO2 TD, erasing voltage for the flash memory with both HfO2 IPD and TD will degrade erasing voltage larger than 41% at a 0.1ms erasing time. On the other hand, increased electric field on HfO2 IPD would produce excess charge loss and narrow the operation window between programmed and erased state.
Investigation of Intermittent Haze in 300mm SiGe Epitaxy Process and its Impact on PMOS Device Performance
Authors: He Yonggen , He Youfeng , Tu Huojin , Jin Lan , Lin Jing , Xu Weizhong , Yu Tzu Chiang , Lu Wei , Wu Jinggang , Wang Chenyu , Cong Zhepeng , Tang Ji Yue
Published: March 2012

One big challenge of epitaxy growth SiGe process is defect control. Many factors have impacts on SiGe film property, such as surface oxide remaining, surface damage of Si substrate post dry etch or wet etch, impurity of chamber ambient and etc. In this work, a special intermittent crater-like "haze" was discussed for surface characterization. It was found that haze happened intermittently and most likely tends to occur after tool idle over twenty hours. Furthermore the haze intensity trend down company with wafer seasoning. As a consequential result, the CMOS devices processed SiGe-epi under intermittent haze condition would result in performance degradation especially for junction leakage. Some countermeasures (or suggested solutions) to suppress this intermittent haze are proposed.
Vertical Assembly of Carbon Nanotubes for VLSI Via Interconnection
Authors: Wei Qinqin , Yin Jinze , Zhao Huabo , Wei Zijun , Fu Yunyi , Huang Ru , Zhang Xing
Published: March 2012

As VLSI technologies scale down, the performance of copper interconnects is greatly degraded by the electromigration problems. The alternative interconnect materials need to be developed. Carbon nanotubes (CNTs) have emerged as a promising nanostructured materials for interconnect applications in the future integrated circuits (ICs) due to their unique molecular structure and excellent properties. In this paper, we have developed a new via interconnection technique by employing alternating current dielectrophoresis (AC-DEP) of the CNT bundles at room temperature. By predefining via holes, high density CNTs have been successfully assembled using AC-DEP technique between the top and bottom electrodes. Our method is controllable, scalable and also compatible with conventional CMOS process, which demonstrates that the carbon nanotubes can be used as interconnects in future VLSI circuits.
The Integration of Ge and III-V Materials on GaAs and Si for Post CMOS Applications
Authors: Chang Edward Y. , Chang Chia Hua , Tang Shih Hsuan , Trinh Hai Dang , Kuo Chien I , Hsu Ching Yi , Su Yung Hsuan
Published: March 2012

In the study, the growth of InAs on Si is demonstrated using "interface blocking" technique with SiGe layers as buffer layer. And the growth of high quality Ge film on GaAs is demonstrated using ultra high vacuum chemical vapor deposition (UHVCVD). Both Ge film grown on GaAs and InAs film grown on Si substrate demonstrate high crystallinity and good surface morphology as observed by XRD and AFM. Furthermore, the fabrication process and electric characteristics of Ge/GaAs and InAs/Si is discussed in the study. The developed epitaxial materials systems and device fabrication including InAs on Si, Ge on GaAs are useful for future III-V and Ge integration on Si substrate for next generation high speed low power CMOS as well as for RF/digital mixed signal circuit applications in the future.
3D Stacking Heterogeneous Integration for Devices and Modules
Authors: Sun Xiao , De Raedt Walter , Beyne Eric
Published: March 2012

This paper presents a 3D heterogeneous approach to integrate a FBAR device and some 3D modules, which provide both addition-al interconnects, RF functions and packaging functionality. The feasibility of this approach has been proven by the successful reali-zation of 3D demonstration vehicles. The RF behavior of the de-monstrators has been assessed and good performances have been obtained.
Effective Approach for Hillock Defect Reduction in Cu Metallization Process
Authors: Li Guang-Ning , Lin Paul-Chang , Jiang Jian-Yong , He Peng , Sun Ri-Hui , Yang Yi , Xing Charles
Published: March 2012

Hillock is formed at the film surface in Cu metallization process. During the growth of hillock, the tensile stress built in the copper (Cu) metal film due to the relieved thermal expansion coefficients. These "hillocks" are just areas of localized copper elevation relative to the rest of the surface that can lead to non-uniformity during etch-stop dielectric deposition. It is important to understand how the hillock is created in order to develop an effective preventative process. In this paper, the degas temperature performance and effect on the hillock in Cu metallization process is introduced, then an effective approach to reduce hillock defect is demonstrated.
40nm Low Power MOSFET Transistor VT Fluctuation Control
Authors: Zhang HongXin , Li Jessey , Lin David , Huang S.K , Shi Wei Min , Ju Jianhua
Published: March 2012

This paper presents an approach to reduce threshold voltage (VT) fluctuation in 40nm low power MOSFET transistor. Introducing nitrogen (N) co-implantation in pocket architecture and reducing pocket implant tilt angle are two factors known for decreasing the VT fluctuation (σVt). In this paper, we combined these two VT fluctuation reduction approaches in source and drain extension (SDE) process and demonstrated that it could not only improve VT mismatch (σVt) ~30%, but also reduce MOSFET overlay capacitance ~ 8%
Effects of High Temperature Rapid Thermal Processing on the Formation of Oxidation Induced Stacking Faults in 300 mm Nitrogen-Doped Czochralski Silicon Wafers
Authors: Xu Ze , Ma Xiangyang , Tian DaXi , Yang Deren
Published: March 2012

Oxidation induced stacking faults (OSFs) are more readily generated in nitrogen-doped Czochralski (NCz) silicon wafers because of possessing more grown-in oxygen precipitates (OPs). This issue is worthy to be addressed. In this work, the effects of rapid thermal processing (RTP) at high temperature in different atmospheres on the formation of OSFs in 300 mm NCz silicon wafers have been investigated. It is found that the prior RTP at 1250 °C in Ar atmosphere can effectively annihilate OSFs, while that in N2 atmosphere promotes the formation of OSFs instead. The reason for this result has been elucidated in the text.
Analysis of Crosstalk in Multi-Wall Carbon Nanotube Interconnection
Authors: Liu Yuhang , Zhang Kailiang , Wang Fang , Tian Bo , Wei Jun
Published: March 2012

Carbon nanotube interconnection has been considered as substitute of copper interconnection in the future VLSI, due to its high current carrying capacity and thermal conductivity. The crosstalk effects in multi-wall carbon nanotube (MWCNT) interconnection are investigated with simulation software SPICE in this paper.Equivalent-circuit modelswhich based on electromagnetism and quantum theory were extractedare modified for MWCNT interconnection.The crosstalk of MWCNT interconnection in different diameters and lengths are simulated at room temperature. The performance of MWCNT interconnection is evaluated and compared with double-wall carbon nanotube (DWCNT). It turned out that MWCNT interconnection can achieve smaller crosstalk effects than that of same size DWCNT interconnection. The MWCNT interconnection is actually performed better.
Study on Defect Reduction and Yield Improvement of MIM Al Deposition Process
Authors: Chang Vincent , Gu Athics , Li Terry , Zhang Ji-Wei , Jiang Jian-Yong , Lin Paul-Chang
Published: March 2012

MIM is the three words of metal insulator metal. This structure is always designed into IC device and act as a big capacitor to keep the stable working voltage. In MIM loop, the upper capacitor board is made of thin Al film. Because of this character, the defect on upper capacitor board is difficult to control and even lead yield loss. In this paper, defect of MIM Al layer is introduced and the mechanism is studied. Through DOE test, MIM defect such as arcing and tiny defect can be reduced to a low level and yield can be improved.
Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry
Authors: Lau John H.
Published: March 2012

"There's Plenty of Room at the Bottom" is the title of Richard Feynman's lecture on December 29th, 1959 to the American Physical Society at California Institute of Technology (Caltech) and is generally considered to be the very first speech about nanotechnology. Some important milestones of nanotechnology will be briefly mentioned and the emphasis is placed on the applications and outlooks of nanotechnology in electronics. "Computing Machines in the Future" is the title of the Nishina Memorial Lecture at Gakushuin University in Tokyo given by the 1965 Nobel Physics Laureate, Richard Feynman on August 9th, 1985. During the lecture, Feynman not only told us to go for 3D integration, but also taught us how to do it! In this study, 3D integration will be the focus and the emphasis is placed on 3D IC integration and their recent advances and new trends. 3D Si integration will be briefly discussed
Wafer Backside Thinning Process Integrated with Post-Thinning Clean and TSV Exposure Recess Etch
Authors: Zhao Ming , Hayakawa Susumu , Nishida Yoshiteru , Jourdain Anne , Tabuchi Tomotaka , Leunissen Leonardus H.
Published: March 2012

The development of 3D-SIC technology has been requiring more delicate backside processing with increasing complexity and process requirements. As one of the key enabling process steps, wafer backside thinning must also evolve to satisfy the emerging demands. In addition to extreme wafer thickness control, the process requirements has also been extended into contamination control and cost reduction aspects, etc. In this work, we demonstrated a novel wafer backside thinning process integrated with post thinning clean and TSVs exposure recess etch in the context of imec's 300 mm wafer backside integration scheme. We expected that implementation of this process in the production line could dramatically simplify and eventually reduce the totally cost of wafer backside processing for 3D-SIC.
Packaging Materials Trends and Outlook
Authors: Tracy Daniel P.
Published: March 2012

Packaging materials represent over a US$22 billion market to the companies supplying these materials to the semiconductor industry, and it is a market that has experience remarkable change with the introduction of new materials and for some packages a complete change in the material set over the past number of years. The surge in new packaging form factors recent years attest to the importance of semiconductor packaging in delivering increased functionality in a small form factor. Numerous new materials have been developed and introduced for these applications to improve reliability, to respond to environmental concerns, and to reduce costs. New material developments include low cost mold compounds and underfills compatible with devices fabricated with low-κ dielectrics; cost effective die attach films for die stacking and thin wafer handling; fine pitch laminate substrates; copper bonding wire; and more.
Underfill and Flux Compatibility from a Curing Perspective
Authors: Tan Kevin , Sun Juan , Pong Yew Kong , Ng Casey
Published: March 2012

The curing compatibility of Anhydride, Cyanate Ester, Amine, Catalyzed Amine and Cationic chemistry underfills was studied in relation to four different lead free fluxes. Differential scanning calorimetric analysis of the curing exotherms for the underfill flux mixtures showed that Anhydride chemistry underfill have best flux compatibility. The Cationic chemistry displayed the worst compatibility and further thermal analysis revealed that the localized underfill to flux weight ratio has a drastic effect on the curability and cure onset of the underfill flux mixture. Field emission scanning electron microscope analysis showed that a flux compatible underfill is able to remove the flux layer during cure and the underfill cures directly on the substrate, whereas in an incompatible underfill flux combination, the underfill cures on top of the flux layer, rendering the flux substrate layer as the weakest layer in such situations
Effect of Solder Volume on Interfacial Reaction between Sn-3.0Ag-0.5Cu Solder Balls and the Substrates
Authors: Yang Fan , Liu Luwei , Zhou Qiang , Liu Ting , Huang Mingliang
Published: March 2012

Nowadays, with the continuous miniaturization of electronic packages, the solder balls used to join chips and substrates are downsizing. While the decrease in solder size may have a detrimental effect on the reliability of solder joints. In this paper, Sn-3.0Ag-0.5Cu solder balls were reflow soldered on two kinds of pads (Cu and Ni-P) to give a comparative study of the volume effect. Cu/Sn-3.0Ag-0.5Cu and Ni-P/Sn-3.0Ag-0.5Cu joints displayed volume effect of different forms. In the reaction of Cu/Sn-3.0Ag-0.5Cu, scallop-type Cu6Sn5 grains formed at the interface. The grain size and thickness of Cu6Sn5 IMC together with the Cu consumption were influenced by solder volume. In the reaction of Ni-P/Sn-3.0Ag-0.5Cu, different type of interfacial IMCs formed for solder balls with different sizes. Changes of Cu content in solder balls play an important role in both kinds of reactions.
Ball Bond Process Optimization with Cu and Pd-Coated Cu Wire
Authors: Qin Ivy W. , Chylak Bob , Clauberg Horst , Shah Aashish , Foley John
Published: March 2012

Cu and Pd-coated Cu (PdCu) wire have been replacing Au wire in electronic packaging. The biggest reason for this transition is the high cost of gold. Methods for process characterization and optimization in Cu and Pd-coated Cu wire differ substantially from those typically used for Au wire. This paper will examine how modifications and newly developed metrology tools are used in the characterization of PdCu and Cu wire bonding. Shear strength, traditionally the most important measure of bond quality in Au wire bonding, is of only limited use in Cu wire bonding. Ball pull has become a much more useful measure of bond quality since it is a more direct measure of too little bonding (ball lifts) and too much bonding (pad peeling). Other important measurements for Cu wire bonding include measurement of Al pad splash and bonded ball cross-sectioning to inspect the ball pad interface and the remaining Al thickness. For Au bonding, the process recipe can be fairly easily optimized and transferred to another bonder. Process windows are much narrower in the Cu and PdCu 1st bond process. It is very critical to develop a robust process with an acceptable process window for Cu wire bonding and to have good control for equipment and material during production. Due to the high demand of process optimization, equipment repeatability, material and production control, collaborations between companies in the electronic packaging supply chain is important to ensure advances in Cu wire bonding technology.
Reducing Metal-Lifting Defect during Wire Bonding through Device Structure and Process Optimization
Authors: Cao Jian , Yan Fang , Zhang Xing
Published: March 2012

This article focuses on the methods of reducing Lifted Metal (LM) defects by optimizing the semiconductor manufacturing process. The LM defect was found to be associated with the insufficient adhesion between metal layers and Inter Metal Dielectric (IMD) together with cracking IMD layers. 5 feasible methods are applied to decrease LM defects. The wire bonding test results show that the incorporation of Tetraethoxysilane (TEOS) layer between Nitrogen Doped Carbide (NDC) and Black Diamond (BD) proves the most useful to decrease Au wire bonding LM defect to 1/39.8 and Cu wire bonding LM defect to 1/9.25. This method to reduce LM defects has passed all the wafer qualification tests, thus it is being used in IC mass production.
An Investigation on Mechanical Behavior on Pt-Coated Copper Wire from a Nanoscale Perspective
Authors: Hsu Hsiang-Chen , Lee Guowei , Feng Wen-Ruei , Kuo Chun-Hsien
Published: March 2012

The aim of present research is to investigate the nanomechanical properties of ultra-thin copper wire (o̸=0.6mil) and nanotribology along the interfacial between free air ball (FAB) and aluminum (Al) bond pad. Micro-tensile mechanical properties were conducted through wire pull test. Microstructure of Cu FAB has been carefully examined and nanoindentation was applied to obtained thin surface elastic modulus on FAB. Nanotribology and interfacial frictional behavior along smashed FAB and bond pad were measured by Atomic Force Microscopy (AFM). The interfacial coefficient of frictional force can be derived from a serial of calculations.
The Optical Sensors Packaging Solution
Authors: Lee Y. F.
Published: March 2012

The market demand for portable consumer electronic devices are growing exponentially, it is because of the electronics devices are installed with multiple functions and user friendly applications. When the electronics devices are equipped with multiple functions and applications, the power consumption of the electronics devices is also rising exponentially. Therefore, the need of reducing power consumption has become a very critical design in the electronics design as to provide end users with increasing battery life. In this paper, we focus on ambient light sensor, one of optical sensor devices which is developed to detect light in the manner similar to human eyes. It is a sensor that detect light so if it is dark the screen monitor brightness will dim down, when it is bright the screen monitor brightness will go up to compensate for the extra light around you so you can see the monitor comfortably.
SOI Wafer Thin - Backgrind and Assembly Capability
Authors: Phang HK , Chan B. M. , Ng PN , Liew SH , Chung K. F. , Wu Robin , Tan BW
Published: March 2012

The evolvement in semiconductor technology is on fast-track with difficult challenges in the continuous drive in seeking for technology breakthrough. Hence, the electronic designers are racing to invent innovative applications via powerful electronic devices that serve to ease today's aggressiveness in technology advances. By inventing greater performance & powerful ICs steer into a wider market sectors such as 1.) Automotive segments & Heavy Industrial which need robust voltage isolation from an IC chip, 2.) Global Corporate Organizations that required distinctive speed and precise information to be disseminated seamlessly via the Super Computers that is embedded with faster device operation (speed/ powerful device) from an IC thus, not neglecting 3) Latest advance consumer mobile devices which are also the highest market commodities like Smart phone, Tablet devices, Notebooks, Play Stations (PS), Media players, etc. Higher performance device is needed in order to meet the above new technology requirement.
Multi Beam Grooving and Full Cut Laser Dicing of IC Wafers
Authors: Van Borkulo Jeroen , Hendriks Rene , Dijkstra Peter
Published: March 2012

This paper will discuss the multiple beam laser dicing technology, an enabling technology that allows semiconductor manufacturers to execute the technology roadmap and continue to comply to Moore's law in an efficient manner. The multiple beam laser dicing technology has already been widely adopted by several other semiconductor technologies (e.g. RFIC, LED, T&D) and has a proven track record. The paper will address how the grooving profile generated by the multi beams give a similar or better performance compared to the single beam grooving profiles. Together with large IDM's ALSI has done an evaluation of the saw blade yield for various grooving technologies. During the conference we will present the results which will demonstrate an equal or better saw yield with a high productivity.
Board Level Reliability of Solder Joint with a Low CTE PCB
Authors: Harr Kyoungmoo , Lee Chang-Bae , Kim Yoon-Su , Park Seungwook , Kim Jin-Gu , Kweon Youngdo
Published: March 2012

With increasing market demands of electric products for smaller, thinner, and faster, printed circuit board (PCB) are pushed to accommodate these requirements. A PCB with low CTE and high elastic modulus could be an alternative to be able to meet the requirements needed for the next generation of high-performance microsystems. In this study, the board level reliability test was performed to evaluate solder joint reliability of low CTE PCB and conventional PCB. Solder joint could be generated the failure due to stresses induced by large coefficient of thermal expansion (CTE) mismatch between silicon and printed circuit board (PCB) under temperature variation. Also, in daily use portable devices such as cellular phones, PDAs, and MP3 players, it is common for them to be subjected to accidental drop impacts resulting in damage and hence failures. Therefore, the reliability performance of solder joints during temperature cycling and drop test is a key issue and it was focused to obtain the board level reliability of solder joint on low CTE PCB. After board level reliability test, cross-section SEM and OM was done to analyze fracture modes of solder joint reliability.
Resolving No Solder Joint Issue Thru Understanding of Basic Principle in Solder and Heat Transfer
Authors: Lee Y. F. , Cham S. F. , Teh SW , Lau SH , Goh KS
Published: March 2012

Cu clip is one of the interconnect technology used in semiconductor packaging. It has a distinct advantage over Au and Cu wire as well as Al ribbon electrical performance. In a standard SO8 package the cu clip electrical resistance is less than 10% of eight 2.0mil Au wires. The better electrical performance coupled with the increase in Au prices, Cu clip has become more and more attractive for MOSFET discrete product like DC-DC converter. This paper discusses the one of the challenges faced during the Cu clip development for 8MLPD3.3x3.3, no solder joint. Thru the understanding of solder properties and basic principle of heat transfer the issued was resolved through solder reflow oven modification and profile optimization.
Intercepting Market Fast-Trends in Integration Packaging via Adaptive NPI System
Authors: Bayona Daniel E. , Erfe Eric
Published: March 2012

The challenge to be profitable in a fast-paced highly commoditized market has put pressure in the supply chain. OEM's, fabless players and system makers engage OSAT (assembly & test houses) for their time-to-market launches. Key differentiating advantages goes to those with (1) R&D facility for materials testing and design simulations (2) proto-line for quick-turn builds and (3) adaptive NPI system and infrastructure. Poor supplier choice means delayed product launch, sluggish ramp or worse - lost business opportunity. This paper demonstrates highly successful OEM-subcon collaborative product launches featuring solutions for packaging integration in small and thin QFN or Micro Leaded Package (MLP) and mixed wafer (Si-GaAs-GlassIPD) format where product functions include intelligent motion-sensing MEM's and RF "Controller-Switch-Filter" combo. In step with market driven trends, fast-track NPI can be realized via "adaptive NPI system". This approach is a business enabler and a key differentiator for OSAT companies.
Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis
Authors: Yang Wu , Tai Ting-Pu , Chandilya Thryambak , Hao Cynthia , Carder Darrell
Published: March 2012

The time to market of a digital device includes first silicon debug, yield ramp and mature yield improvement. Manufacturing test failures caused by defects during mature yield state are usually hard to characterize for advanced technologies and resemble baseline pattern. Diagnosis driven yield analysis (DDYA) is a solution which can be used efficiently during different stages of product life. Instead of relying on just a handful of high quality diagnosis results, it takes volume layout-aware diagnosis results, performs yield analysis, identifies systematic signature, facilitates root cause analysis, and picks the best candidate die for physical failure analysis (FA). The confirmed PFA result can then be used to adjust fabrication process to improve baseline yield and reduce future occurrences of such failures. Case study in this paper shows this flow helped improve a mature yield by 1.7%.
Fast Jitter Test Solutions of High-Speed IO Based on Timing and Frequency Domain
Authors: Lu Ming
Published: March 2012

To quantify the transmission quality of HSIO with high-level confidence is the big challenge in front of SOC ATE test engineers. The mainstream approaches can be separated into 3 types: BIST loopback, golden device and fast eye-mask test. All these 3 approaches cannot meet the strict specifications of the leading-edge high-speed device which need random jitter and deterministic jitter separation. This paper introduces one fast jitter test solution which can get accurate RJ/DJ value from either timing domain or frequency domain. This solution has been implemented in production of real devices and the result shows its high accuracy.
Arc Detection in Plasma Etching Using Fuzzy Model and Dempster-Shafer Theory
Authors: Kim Min-Woo , Han Yi-Seul , Shin Sung-Hwan , Han Seung-Soo
Published: March 2012

In current semiconductor manufacturing process, plasma processes such as etch and CVD take the portion at least 40% throughout the integration processes. In etch and CVD using plasma, particles created during processes produce abnormal discharge with relatively large energy and light. This energy must be detected because this energy causes damage directly or indirectly to wafer. Using Optical Emission Spectroscopy (OES), it is possible to detect status changes of plasma and also to find arc generation. The OES is often used for analysis of plasma physics and chemistry in real-time. The OES system gathers a series of optical emission intensity of the plasma in the chamber. But OES has large amount data because of using the full range of wavelength. Therefore, it takes a long time to process the data. To solve this problem, a new method is proposed using Fuzzy model and Dempster-Shafer theory by utilizing equipment data from matching network. Six data from matching network such as Cap position, RF reflective powers, are used to make Fuzzy model for arc detection. Fuzzy model normalizes these matching network data between 0 and 1. Output of Fuzzy model is used as a reference to detect abnormal data from on-line data. Six matching network parameter are compared at the same time and Dempster-Shafer theory is used to make a decision whether current state is in arc state or not. The results show that the proposed method detects arc point accurately.
OCD Metrology Evaluation of p-MOS Silicon Recess with Three Dimensional Design Pattern
Authors: Huang Yi , Han Qiu-Hua , Sui Yun-Qi , Xu Chuan-Jin , Meng Xiao-Ying , Li Chao-Wei , Ni Sheng
Published: March 2012

OCD metrology has been proven to be a fast, accurate, and non-destructive knob for in-situ monitoring of line width and profile. In order to main Moore's law, device dimension is moving towards 45nm technology node and beyond, it is becoming increasingly difficult to perform the in-situ evaluation for those complicated structures by either CD-SEM or AFM. In this work, we come up with one specific 3D pattern to realize the 3D monitoring of p-MOS silicon recess (PSR) etch performance. The corresponding OCD library was identified and implemented on Nova OCD 3090 next. Several key floating parameters include PSR & STI depth, gate & AA CD, nitride spacer width and SWA. Good CD correlation between OCD and CD-SEM is obtained on the same 3D pattern. Consistent trench depth match is also observed between OCD and blanket pattern based AFM. Besides, dynamic repeatability test shows the acceptable reliability for 3D PSR OCD monitoring as well.
Length Dependence Effect in 40nm Cu Low-k Dielectric Breakdown
Authors: Song Zhuo , Han Kun , Zhang Liwen , Atman Zhao Y. , Wang York
Published: March 2012

Voltage breakdown (Vbd) and time-dependent dielectric breakdown (TDDB) of low-k dielectrics is considered as a key reliability concern for advanced technologies. The lifetime projection to a real chip application requires a more accurate model to avoid over-optimistic or over- conservative result. Length dependence, a study aimed to clarify the relationship between time to fail (TTF) on test structures experimental and lifetime extrapolated on chip wideness level, can not be treated simply by area scaling with Weibull distribution slope due to obvious slope change among structures along with various lengths (and also Weibull slope less than 1 sometimes). Based on Vbd and TDDB test result with various structures of 40nm low-k dielectrics (k~2.75), this work illustrates the effect of the test structure length which alters the Weibull distribution as well as lifetime. By theoretical and experimental analysis, line edge roughness (LER) is taken as the dominated factor to this length dependence effect.
A Novel Reliability Failure Mode of Cu Single Damascus Process
Authors: Wang Du-Lin , Cheng Arthur , Ma Jenny , Zhao Atman , Gong Excimer , Wang Yuke
Published: March 2012

Ultra thick top metal has been identified as the most promising technology enhancement for RF IC applications. As the top metal's ultra thickness, top via etching will have a high aspect ratio and will easily over etch the via bottom and damage the under layer metal in conventional dual Damascus Cu process. Single Damascus instead of traditional dual Damascus Cu process was selected for thick top metal fabrication to improve the etch window. But a novel failure mode, void formed in via top at anode side is observed during the electromigration (EM) reliability evaluation, which leads a bad reliability performance. A physical model is proposed in this paper to explain the strange failure mode. Based on our model, an optimized pre-clean (to increase the adhesion between the cooper and barrier) and barrier/seed thickness (to reduce the stress of interface) split is developed and shows better EM performance.
Using System-like ATE to Improve the IC Design Verification
Authors: Song Wen-jing , Chen Zai-man
Published: March 2012

Identifying design problems as early in design cycle as possible is very critical to complete the IC design project on time and within budget. Most people today are using bench instruments, like spectrum analyzer, to validate their design in system level. These instruments are easy to setup but lack of data processing capability. On the other hand, ATE is very powerful at data collection and analysis, e.g. shmoo, data capture, and automatic test. But it's not easy to do system-like test on ATE. This paper will introduce a new solution to do system-like test on ATE, which is cost effective, and simplify the test programming on ATE. With this solution, design and verification engineer can work together to setup system-like test environment on ATE within several days, which can greatly improve the design verification efficiency and time to market.
Run-to-Run Fault Prediction for Semiconductor Manufacturing Process Based on Variable Forgetting Factor RLS
Authors: Liu Shujie , Zheng Ying , Luo Ming
Published: March 2012

Run-to-Run (RtR) control has been widely used in semiconductor manufacturing industry nowadays. Recursive Least Squares (RLS) approach is an important data-driven algorithm. Both the drift disturbance and the fault will seriously affect the product quality in semiconductor manufacturing process. This paper proposes a variable forgetting factor RLS output prediction method for semiconductor manufacturing process with a fault and the disturbance without and with a drift. In order to improve the accuracy of predictions, we propose a kind of method which adjusts the forgetting factor online, making predicted values track the wide fluctuations of actual output values well, and predict the output 's future fluctuations in case of faults. It has both a strong ability to track parameters, and a small convergence estimate error. Simulation results show that this prediction method works well, has better portability and higher accuracy, can provide effective information for fault warning, fault-tolerant control and health management, furthermore will avoid huge losses in actual production.