bluuebunny/crossref_metadata_2025 huggingface dataset:
Advanced FinFET Devices for Sub-32nm Technology Nodes: Characteristics and Integration Challenges
Authors: Veloso Anabela , Collaert Nadine , De Keersgieter An , Witters Liesbeth , Rooyackers Rita , Van Dal Mark J. , Duffy Ray , Pawlak Bartek J. , Lander Rob J. , Hoffmann Thomas , Biesemans Serge , Jurczak Malgorzata
Published: May 2009

We report a comprehensive evaluation and overview of the latest developments and technology challenges of FinFET-based devices. They offer improved electrostatics and steeper sub-threshold slopes, attractive for enabling further CMOS scaling, but can also suffer from higher parasitic resistance and parasitic capacitance for narrow Fin devices. Critical solutions to minimize the impact of the latter are here addressed, demonstrating their viability for replacing planar CMOS devices. Multiple-VT CMOS can be achieved with capping technology, with aggressively scaled Ring Oscillators (RO) and SRAM cells showing excellent performance and matching behavior.
SOI and Other Semiconductor-On-Insulator Substrates Characterization
Authors: Abbadie Alexandra , Le Vaillant Yves -M. , Figuet Christophe , Guiot Eric
Published: May 2009

We focus in this paper on SOI and new engineered on-insulator substrates characterization. After a short review of on-line characterization techniques, we will detail off-line monitoring techniques such as preferential etching and Raman spectroscopy. We will especially highlight their complementarity on strained layers and the need for a proper evaluation of structural quality of on-insulator substrates.
Morphological and Electrical Comparison of GeOI Enriched Structures Obtained from SOI and sSOI Substrates
Authors: Damlencourt Jean-Francois , Vincent Benjamin , Clavelier Laurent , Le Royer Cyrille , Campidelli Yves , Bernasconi Sophie , Morand Yves , Nguyen Tuan , Cristoloveanu S.
Published: May 2009

Fabrication of high quality Ge/SGOI bilayer by Ge enrichment technique has been investigated. Using a strain SOI (20%) wafer as a starting substrate leads to the delay of plastic relaxation and thus, the crystalline defects generation, during the Ge enrichment. These sGeOI substrates show a lower layer roughness and a high resistivity compared to the ones obtained on conventional GeOI. Unfortunately, plastic relaxation is evidenced during the Ge thickening (final thickness up to 30nm). This can be overcome by using extremely strain SOI (XsSOI) as starting substrates.
Comparison of SOI FinFETs and Bulk FinFETs
Authors: Lee Jong-Ho , Lee Ju-Wan , Jung Han-A-Reum , Choi Byung-Kil
Published: May 2009

Bulk FinFETs and silicon-on-insulator (SOI) FinFETs were compared in terms of device structure, fundamental characteristics, speed characteristics, model, and application. Bulk FinFETs have shown several advantages over SOI FinFETs while keeping nearly the same scaling-down characteristics as those of SOI FinFETs. Compared to bulk FinFETs, SOI FinFETs could suppress any possible leakage between source and drain, and has low source/drain to substrate capacitance so that speed characteristics could be better. Since SOI FinFETs have two more corners in the bottom of the fin body than bulk FinFETs, bulk FinFETs can have less process variation. Both devices seem to have their specific applications.
SOI as Platform for Transition from Micro to Nano
Authors: Balestra Francis
Published: May 2009

Silicon On Insulator (SOI)-based devices seem to be the best candidates for the ultimate integration of ICs on silicon. The performance and physical mechanisms are addressed in single- and multi-gate thin film Si, Ge and III-V MOSFETs. The impact of tensile or compressive uniaxial and biaxial strains in the channel, of high k materials and metal gates as well as metallic Schottky source-drain architectures are discussed. The interest of SOI-based emerging and beyond-CMOS nanodevices for long term applications, based on nanowires, carbon electronics or small slope switch structures is presented. Finally, the possible 3D integration of multi-channels and stacked nanowires is also shown.
Diamond-on-SOI Field Emission Device Patterning
Authors: LeQuan Xuan-Anh C. , Choi Bo , Kang Weng Poo , Davidson Jim
Published: May 2009

Nanocrystalline diamond films deposited on SOI and electron beam patterning techniques are used to fabricate a field emission device with sub-micron cathode-anode separation. The subsequent aluminum evaporation and dry etch creates a mask for the electrode features, demonstrating that the nanodiamond (ND) roughness does not compromise the device delineation when proper EBL write parameters are used. A mixture of BCl3 and Cl2 were used to dry etch the aluminum, oxygen O2 plasma was used to etch the nanodiamond, and SF6 gas was used to etch the active layer of silicon followed by KOH:DIH2O wet etching.
H-shaped Vertical Polycrystalline Silicon Thin Film Transistor on Insulator
Authors: Toure Himi-Deen , Gaillard Thierry , Coulon Nathalie , Bonnaud Olivier A.
Published: May 2009

We introduce a new design of vertical fully depleted type of the polycrystalline silicon (polysilicon) on insulator thin film transistor (TFT). This new structure fabricated based on polysilicon is characterized by vertical channels, an H-shaped geometry and also a technology similar to classical silicon on insulator (SOI) one. In practice, the design corresponding to a FinFET one is close to multigate SOI MOSFET and thus requires less area than planar design. It allows increasing easily the channel width simultaneously to better control and reduction of channel length, leading to an increase of the average driven current and device densities. This paper describes the low temperature fabrication process of this new structure that is compatible with SOI or glass substrates. A first run involving simple plastics masks allowed electrical characterizations of the transistors, mainly output and transfer characteristics that are discussed, confirming the potentiality of such a structure.
Device Physics and Simulation Techniques for Nanoscale SOI-MOSFETs
Authors: Tsuchiya Hideaki , Yamada Yoshihiro , Souma Satofumi , Ogawa Matsuto
Published: May 2009

The silicon-based planar CMOS technology is expected to face fundamental limits in the near future, and therefore, new types of nanoscale devices are being investigated aggressively. To understand the device physics and assess their performance limits, new types of simulation techniques considering quantum mechanical phenomena, carrier's ballistic transport and atomistic effects are also needed. In this paper, we present our recent approaches toward the quantum and atomistic transport modeling, and make a performance projection of emerging nano-MOS transistors employing new device structures and new channel materials.
Three-Dimensional NEGF Simulations of Constriction Tunnel Barrier Silicon Nanowire MUGFETs
Authors: Afzalian Aryan , Lee Chi-Woo , Yan Ran , Dehdashti Akhavan Nima , Colinge Cindy , Colinge Jean-Pierre
Published: May 2009

In this paper, we investigate the effect of cross-section variations in nanowire MUGFETs through 3D quantum simulations based on Non-Equilibrium Green's Function (NEGF) formalism. We show that the effect of cross-section variations in a nanowire results in energy barriers in the conduction band that can be interpreted as a local increase of the bandgap. In narrow nanowires with a cross section of a few nanometers, this can strongly influence the current and the characteristics of the device. A small constriction resulting in a barrier of the order of a 0.1eV is shown to be an effective way to create a tunnel barrier that can be used to improve the on/off current ratio in ultra-scaled transistors.
Floating-Body SOI Memory: Concepts, Physics and Challenges
Authors: Bawedin Maryline , Cristoloveanu S. , Flandre Denis , Udrea Florin
Published: May 2009

We present an overview of the single-transistor memory cells (1T-DRAMs), which are based on floating-body effects in SOI MOSFETs. The typical device architectures, principles of operation and key mechanisms for programming are described. The various approaches (Z-RAM, MSDRAM, etc) are compared in terms of performance and potential for aggressive scaling.
65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs
Authors: Raynaud Christine , Haendler Sebastien , Guegan Georges , Gianesello Frederic , Martineau Baudouin , Touret Patricia , Planes Nicolas
Published: May 2009

We present a 65nm RF SOI CMOS technology, targeted as Low Power (LP) to serve mobile applications. The integration has been made on High Resistive (HR) back substrate 300mm SOI wafers from SOITEC to improve performances in high frequency range, compared to bulk [1, 2]. For the first time, low leakage SRAM (Isb< 10pA at 0.9V, 25{degree sign}C, for 0.62µm2 and 0.52µm2 cells) are integrated on these HR wafers, and the paper reports a 30% power reduction in operation for a given maximum speed, compared to similar SRAM design on bulk. Furthermore, we have demonstrated a 21% measured power-delay product reduction compared to bulk, at 125{degree sign}C, on loaded ring oscillators.
Comparison of Short-Channel Effects in SOI and sSOI Triple-Gate MOSFETs
Authors: Na Kyoung Il , Cristoloveanu S. , Bae Young Ho , Xiong Wade , Cleavelin C. Rinn , Patruno Paul , Lee Jung Hee
Published: May 2009

We have compared the short-channel effects (SCE) in triple-gate MOSFETs fabricated on SOI and strained SOI (sSOI) substrates. The triple-gate sSOI MOSFETs exhibit high gain in mobility but show earlier threshold voltage roll-off than unstrained devices. This indicates that the low effective mass and the narrow band-gap, due to tensile stress in sSOI substrate, increase the junction and gate tunneling leakage current and hence enhance the SCE. The off-current of sSOI device at Vg = 0 is one order of magnitude higher than that of SOI device, decreasing the on/off current ratio. The subthreshold slope of sSOI device is also affected. The stronger short-channel effect in sSOI device is correlated with a more intense channel-to-substrate coupling.
High-K Ta2O5 Polyoxide Deposited on Polycrystalline with NH3 Plasma Treatment
Authors: Kao Chyuan H. , Chen K. S. , Chiu J. S. , Chen C. S. , Chen T. C. , Luo W. S. , Chung Y. T.
Published: May 2009

The high-k Ta2O5 in our study is used to apply as gate dielectric in polyoxide and low-temperture polycrystalline silicon thin-film transistor (LTPS-TFT) for performance improvements. Therefore, we employ the NH3-plasma treatment to improve the electrical characteristics of the high-k Ta2O5 polyoxide dielectric such as higher breakdown voltage and lower leakage current. It's seen that the nitrogen can pile up at the high-k Ta2O5 dielectric and polysilicon interface to form strong Si-N bondings from the SIMS and XPS analysis.
Dr. CHEMFET
Authors: Janata Jiri
Published: May 2009

A personal account of the 50 year-long journey from being a student of electroanalytical chemistry to a teacher of modern chemical sensors is given. Many interesting people encountered on this trip will be recalled. In other words, it will be a reflection on some fifty years of major global political and technological changes and their effect on sensor science.
Carbon Nanotube Based Chemical Sensors for Space and Terrestrial Applications
Authors: Li J. , Lu Yijiang
Published: May 2009

A nanosensor technology has been developed using nanostructures, such as single walled carbon nanotubes (SWNTs), on a pair of interdigitated electrodes (IDE) processed with a silicon-based microfabrication and micromachining technique. These sensors have been exposed to nitrogen dioxide, acetone, benzene, nitrotoluene, chlorine, and ammonia in the concentration range of ppm to ppb at room temperature. Due to the large surface area, low surface energy barrier and high thermal and mechanical stability, nanostructured chemical sensors potentially can offer higher sensitivity, lower power consumption and better robustness than the state-of-the-art systems, which make them more attractive for defense and space applications. Combined with MEMS technology, lightweight and compact size sensors can be made in wafer scale with low cost. Additionally, a wireless capability of such a sensor chip can be used for networked mobile and fixed-site detection and warning systems for military bases, facilities and battlefield areas.
All-Solid-State Potassium Ion-Selective Electrode with Conducting Polymer Doped with Carbon Nanotubes and C60 as the Ion-to-Electron Transducing Layers
Authors: Mousavi Zekra , Han Tingting , Kvarnström Carita , Bobacka Johan , Ivaska Ari
Published: May 2009

The conducting polymer poly(3,4,-ethylenedioxythiophene), PEDOT, doped with multi-walled carbon nanotubes and fullerenes, C60, were used as the ion-to-electron transducing layers in all-solid-state potassium selective electrodes. The electrochemical properties of the transducing layers were studied by cyclic voltammetry and electrochemical impedance spectroscopy. Electrodes with both solid contacts showed good linear potentiometric response with almost Nernstian slope. Purging the solution with oxygen and carbon dioxide did not affect the potential stability of the electrode with the conducting polymer transducing layer. Selectivity of the electrode with the fullerene solid contact is comparable with conventional K+ selective electrodes. Electrodes with both type of solid contacts showed good long term potential stability.
In Vitro Dopamine Sensing Capabilities of Polycarbazole Film-Modified Platinum Electrodes
Authors: White Bradley , Rubinson Judith F.
Published: May 2009

The characterization of neurological pathways and processes is necessary both to better understand diseases such as Alzheimer's disease and Parkinson's disease, and to investigate the functions of various neuroactive agents. With this in mind, we report here results for the detection of dopamine at polycarbazole electrodes. After determination of the appropriate conditions for electropolym-erization of robust films of polycarbazole and detection of dopamine at polycarbazole, films were produced on a rotating disk electrode and used for the detection of dopamine detection at pH 7.4, both alone and in the presence of varying concentrations of ascorbic acid. Both interelectrode and interday testing as well as interference studies for dopamine in the presence of ascorbic acid suggest that these electrodes will provide a sensitive and selective choice for in vivo detection of dopamine.
Gel Hybrid Material as Sensing Gate of CHEMFET
Authors: Mayo India S , Jonke Alex , Janata Jiri , Josowicz Mira
Published: May 2009

Properties of chemically sensitive field effect transistor (CHEMFET) sensor fabricated using variable proportion of room temperature ionic liquids (ILs) as an additive to polyaniline (PANI) doped with camphorsulphonic acid (CSA) have been examined as a gel-hybrid sensitive material. Almost 60 % increase in sensitivity to ammonia gas was observed after the addition of 1-butyl-3-methylimidazolium bis(trifluoromethanesulfonyl)amide ([BMIM][Tf2N]) and tetrahexyl ammonium bis(trifluoromethane-sulfonyl)amide ([THA][Tf2N]). Also a considerable improvement in response time of CHEMFET to NH3 was observed with PANI⋅CSA gate material containing 0.68 or 0.76 mole fraction of [BMIM][Tf2N].
Electrodeposition of Poly(phenylene oxide) Nanoscale Patterns with Nanosphere Lithography
Authors: Kang Jason , Li Huaqing , Cushing Scott , Wang Jin , Wu Nianqiang
Published: May 2009

Nanosphere lithography is used to generate a poly(phenylene oxide) (PPO) nanowell nanopattern. The thickness of the PPO film increased with increasing the scan cycle number and the monomer concentration and reached the maximum thickness of a bout 20 nm. The size and pitch of the nanowells can be adjusted by the size of the nanospheres used.
Controlling the Sensitivity, Specificity, and Time Signature of Sensors through Architectural Design on the Nanoscale
Authors: Rolison Debra R. , Pietron Jeremy J. , Long Jeffrey W.
Published: May 2009

When multifunctionality and molecular transport paths are critical, as they are in chemical sensing, architectural design enables high performance. The chemical interactions that trigger recognition (i.e., sensing) of molecules are more effective when they structured within mesoporous architectures with continuous, but aperiodic networks that wrap around the reactive solid network in 3-D.
Development of Novel Humidity Sensor based on a Polymer Silver Nanoparticle Composite
Authors: Power Aoife , Cassidy John F. , Betts Anthony
Published: May 2009

Humidity sensing is of particular concern for many industrial applications. Humidity sensors have typically been based on a reversible interaction between a polymer and water vapour. There is work published on gas sensors based on polymer gold nanoparticle composites, where the conductivity of the composite decreases on interaction with the gas. This happens because the swelling of the polymer which increases the electron hopping distance between the gold nanoparticles. The device in this work is a poly vinyl alcohol silver nanoparticle composite cast on an interdigital electrode array. On application of a dc bias, a current develops which is proportional to levels of humidity from 10% to 60%. The response is reversible and fast at room temperature. Details are provided of the synthesis, characterisation and use of the composite for humidity sensing. In addition the device forms the basis of a sensor for an array of gases.
Electropolymerization of a Cation-permeable Layer using 1-pyrrolyl-10-decanephosphonic Acid
Authors: West Ryan M. , Josowicz Mira , Janata Jiri
Published: May 2009

The electrochemical deposition of a novel N-substituted polypyrrole, 1-pyrrolyl-10-decanephosphonic acid, is presented. The properties of the film are found to be highly dependent on the potential range used during deposition. Self-terminated growth of a thin, non-conducting layer is observed when using anodic switching potentials of at least 1.8 V versus Ag/AgI. At anodic potentials between 1.5 V and 1.8 V, growth of a conducting polymer layer is possible, although, continued growth results in increased resistance of the film and gradual transition to a non-conducting state. A long-lived intermediate formed during the oxidation of the monomer is observed. Reduction of this intermediate, resulting in changes in the cyclic voltammogram, occurs at c.a. 400 mV. Fourier Transform Infrared Spectroscopy of the film confirms the presence of the tethered phosphonates in the film. In aqueous solution the insulating films are permeable to Ru(NH3)62+/ Ru(NH3)63+ but impermeable to Fe(CN)63-/ Fe(CN)64-.
A Novel Electrode Material for H2O2 Oxidation of Electrochemical Glucose Sensors
Authors: Morimitsu Masatsugu , Okazaki Aya
Published: May 2009

The oxidation behaviors of H2O2 in a neutral buffer solution on an iridium oxide-tantalum oxide coating formed on a titanium substrate were investigated to develop a new electrode material for electrochemical glucose sensors. The oxidation current of H2O2 on the IrO2-Ta2O5/Ti electrode was linear with the concentration, and the slope of the linear relationship, i.e., the sensitivity to H2O2, was higher than that obtained with a platinum electrode. The IrO2-Ta2O5/Ti electrode also showed an excellent selectivity to H2O2 in the solution containing NaN3, which is used as the anti-oxidant of the buffer solution in commercial glucose sensors. The oxidation of N3
- observed on the platinum electrode at the same potential region as the H2O2 oxidation was completely suppressed on the IrO2-Ta2O5/Ti electrode.
Tuning the Sensitivity and Temperature Stability of NO2 Gas Sensors based on Networked Single-wall Carbon Nanotubes: A Surface Density Effect
Authors: Sasaki Isao , Minami Nobutsugu
Published: May 2009

Our objective in this paper is to minimize the temperature interference, an inherent problem to environmental gas sensing, with the NO2 gas sensitivity of gas sensors based on SWNT (single-wall carbon nanotube) networks. We systematically change the surface density of the networked SWNTs and compare the NO2 sensitivities at various sensing temperatures (30 to 75 ºC). The results show that the NO2 gas sensitivity and its temperature stability are highly dependent on the surface density of the networks. Lower surface density leads to higher NO2 sensitivity, which is consistent with previous studies. However, SWNT networks with higher surface density are more stable against the temperature changes. Based on these findings, we propose to optimize the surface density of the networks to suppress the temperature interference while maintaining high detection sensitivity sufficient for environmental monitoring (53 ppb by the National Ambient Air Quality Standards).
Film-Based Sensors: Fundamental Impact of Film Structure
Authors: Hettige Chaminda , Leddy Johna
Published: May 2009

Sensors embodied in inert films on electrodes establish selectivity and sensitivity for an electroactive analyte extracted from solution. Typically, analytes are assayed on short voltammetric time scales to confine analyte diffusion lengths to the film. But measurements made on longer time scales can capitalize on film structure to match voltammetric wave shape to measurement methodology (e.g., derivative and steady state methods). Cyclic voltammetric wave shapes that range from Gaussian waves of thin layers through avian shapes established by semi-infinite linear diffusion to sigmoids of steady state transport are accessed by tailoring film structure. Three film structures are considered: uniform, graded, and bilayer. The role of relative flux in dictating cyclic voltammetric response as diffusion length exceeds film thickness is described.
Magnetic Quartz Crystal Microbalance: Alternating Ferromagnetic/Diamagnetic Multilayers
Authors: Yu George , Vavra Kevin Y. , Janata Jiri
Published: May 2009

A new technique for using quartz crystal microbalance (QCM) in magnetic ﬁeld is described. This technique takes advantage of the sensitive nature of QCM to load changes. The idea is to perturb the oscillations of a QCM with deposited magnetic materials by applying magnetic ﬁeld. A new instrument called magnetic QCM (MQCM) has been constructed to explore this technique. Past MQCM investigations have shown that QCM frequency and phase responds to magnetic nano-dispersions in elastic non-magnetic matrix and also to alternating layers of ferromagnetic and diamagnetic materials. We have found that this type of alternating multilayer structure on QCM is very sensitive to weak magnetic fields.
Revolutionary Nanoelectronic Devices and Processes for Post 32nm CMOS Era
Authors: Nishi Yoshio
Published: May 2009

Possible device structure alternatives and material alternatives for CMOS beyond 32nm technology node are discussed placing emphasis on active device performance enhancement. Issues on metal gate/high k coupled with high mobility materials and opportunity for possible functional replacement of conventional devices, especially in memory devices, are discussed.
High-k Dielectrics and Metal Gates for Future Generation Memory Devices
Authors: Kittl Jorge A. , Opsomer Karl , Popovici M , Menou N. , Kaczer Ben , Wang X. P. , Adelmann C. , Pawlak M. A. , Tomida K. , Rothschild Aude , Govoreanu Bogdan , Degraeve R. , Schaekers M. , Zahid M , Delabie A. , Meersschaut J. , Polspoel W. , Clima Sergiu , Pourtois Geoffrey , Knaepen W. , Detavernier Christophe , Afanas'ev Valery , Blomberg T. , Pierreux D. , Swerts J. , Fischer P. , Maes J. W. , Manger D. , Vandervorst Wilfried , Conrad T. , Franquet A. , Favia P. , Bender Hugo , Brijs B. , Van Elshocht S. , Jurczak Malgorzata , Van Houdt J. , Wouters Dirk J.
Published: May 2009

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.
High Temperature Ion Implantation: a Solution for n-Type Junctions in Strained Silicon
Authors: Heiermann Wolfgang , Buca Dan , Trinkaus Helmut , Holländer Bernd , Breuer Uwe , Kernevez Nelly , Ghyselen Bruno , Mantl Siegfried
Published: May 2009

Elastic strain intentionally applied to thin layers can be reduced or even completely relaxed by amorphization during ion implantation. Sb implantation and activation in unstrained and strained-SOI substrates and effects on the crystal quality for different implantation conditions were investigated. Implantation induced amorphization can be avoided and simultaneously high dopant activation up to 55% can be achieved by implanting at elevated temperature. For a low implantation energy of 6 keV, no dopant profile broadening is measured after dynamic annealing in strained-SOI.
Dopant and Carrier Concentration Profiling with Atomic Resolution by Scanning Tunneling Microscopy
Authors: Kanayama Toshihiko , Nishizawa Masayasu , Bolotov Leonid
Published: May 2009

We show that the scanning tunneling microscopy (STM) has the ability to detect the surface potential and the individual dopant atoms with extremely high spatial resolution on flat and electrically inert Si surfaces. The actual measurements are demonstrated for both the ultra-thin oxidized surface and the NH4F-treated Si (111) surface. The latter treatment yields atomically flat hydrogenated surfaces, on which atomic resolution is available. This surface enabled us to analyze correlation between the potential variation and the statistical fluctuation of dopant atom distribution for a p-n junction region. Another example is quantitative potential profiling based on scanning resonance tunneling spectroscopy of molecular levels of C60 deposited on oxidized Si surfaces. Mechanisms of these measurements are discussed.
Characterization of Annealing Effects in Ultra-Shallow Boron-Implanted Si Wafers using Raman Scattering
Authors: Fukumoto Masashi , Minami Hiroaki , Hasuike Noriyuki , Harima Hiroshi , Yoshimoto Masahiro , Yoo Woo Sik
Published: May 2009

Raman scattering was used as a non-contact and non-destructive characterization technique to present a systematic study on the crystallinity and diffusion of impurities in ultra-shallow ion-implanted Si wafers. In this study, the samples were prepared by the implantation of Si (100) wafers with B. The thermal annealing was carried out to investigate the effect of annealing under various conditions. The crystallinity of the samples was deteriorated with increase in B implantation level. Especially, near the surface, the crystallinity was seriously deteriorated, and the Raman spectra showed the generation of the amorphous Si phase. By thermal an-nealing, the surface amorphous Si was re-crystallized, and the im-planted B was diffused enough to the top surface region. Further-more, by using an N2 and O2 gas mixture, as an annealing atmos-phere, promoted the recrystallization of surface amorphous Si and improved suppression of diffusion of the implanted B.
The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs
Authors: Caymax Matty R. , Leys Frederik , Mitard Jerome , Martens Koen , Yang Lijun , Pourtois Geoffrey , Vandervorst Wilfried , Meuris Marc , Loo Roger
Published: May 2009

Recently, best 65 nm Ge pMOSFET performance has been reported (13) with a standard Si CMOS HfO2 gate stack module. The Ge passivation is based on a thin, fully strained epitaxial Si-layer grown on the Ge surface. We investigated in more detail how device performance (hole mobility, Ion, Vt etc) depends on the characteristics of this Si layer. We found that surface segregation of Ge through the Si layer takes place during the growth, which turns out to be determining for the interfacial trap density and distribution in the finalized gate stack. Based on a better understanding of the fundamentals of the Si deposition process, we optimized the process by switching to another Si precursor and lowering the deposition temperature. This resulted in a 4 times lower Dit and in improved device performance.
Defects, Junction Leakage and Electrical Performance of Ge pFET Devices
Authors: Eneman Geert , Simoen Eddy , Yang Rui , De Jaeger Brice , Wang Gang , Mitard Jerome , Hellings Geert , Brunco David , Loo Roger , De Meyer Kristin , Caymax Matty R. , Claeys Cor , Meuris Marc , Heyns Marc
Published: May 2009

The different leakage components in a germanium MOS technology are studied, with the main focus on highly-doped p+/n junctions designed for short-channel Ge pFET fabrication. Three main components of junction leakage are discerned, depending on the position (the active area, the perimeter of the isolation, under the spacer). Each of these components shows a different temperature sensitivity, indicative of the different dominant leakage mechanisms. Suggestions are given to keep each component as low as possible. Furthermore, junction leakage results in novel thin selectively grown Ge-in-STI substrates are reported. These thin substrates offer lower perimeter leakage at the expense of a slightly higher area leakage. In a commercial design, however, the advantage of the lower perimeter current is expected to outweigh the effect of area leakage.
The Challenges in Introducing PMOS Dual Channel in CMOS Processing
Authors: Harris Harlan R. , Majhi Prashant , Kirsch Paul D. , Sivasubramani Prasanna , Oh Jung Woo , Song Seung Chul
Published: May 2009

The benefit of a SiGe channel in the adjustment of the threshold voltage in PMOS devices is outlined. However, difficulties in the implementation make the full CMOS integration challenging. We examine these difficulties of implementation and the complexities of the processes. The issues are divided into two categories to better understand the complexity: active area related and complementary process related. In particular, the process issues associated with epitaxy, gate etch, silicide and lithography are particularly examined. It is concluded that the issues can be overcome with excellent transistor results.
Modeling the Influence of Defects on the Electrical Response of Multi-Dielectric Gate-Stack Structures
Authors: Hjalmarson Harold P. , Devine Roderick
Published: May 2009

The effects of bulk and interface traps in a gate stack are used to explain positive-bias temperature instability (PBTI) electrical measurements.
Electrical and Wafer Surface Profile Characterization of NiSi Formation Process using a Four Point Probe and Optical Surface Profilometer
Authors: Yoo Woo Sik , Ueda Takeshi , Ishigaki Toshikazu , Kang Kitaek
Published: May 2009

Sheet resistance and surface profiles of TiN (~10nm thick) capped, Ni films (~30nm thick) on (100) oriented p-type 300mm blanket Si wafers were measured using a conventional four point probe and WaferMasters' optical surface profilometer (OSP-300) system. Process induced surface profile changes were characterized and traced between process steps. Measurements were done after NiSi formation using WaferMasters SAO-300LP (stacked annealing oven) system and removal of the TiN capping layer and unreacted Ni layer by wet etching. Annealing of the NiSi formation was done in the temperature range of 200~425oC in N2 at 1 atmosphere for 5 min. Significant changes in wafer surface profile were observed near the phase transition (Ni/Si→Ni2Si→NiSi) temperatures as determined by the temperature sensitivity curve of sheet resistance. Wafer surface profiles became flatter after wet etching due to the release of build up between the TiN capping layer and the nickel silicide layer. The origin of the wafer distortion after annealing was found to be at the interface between the TiN capping layer and the silicide layer.
Emerging Devices Based on Spin Transfer Torque Effect
Authors: Heindl Ranko , Rippard William H.
Published: May 2009

In recent years, there have been intense research efforts directed towards using the spin-transfer-torque (STT) effect to induce reversal or precession of magnetization in ferromagnetic layers. This new effect has the potential to create a new generation of magnetic random access memory (STT-MRAM) and nanoscale current-tunable microwave sources and oscillators. STT-MRAM devices are characterized by non-volatility, unlimited write endurance, compatibility with complementary metal-oxide semiconductor (CMOS) processing, nanosecond operation, and good scalability to future semiconductor nodes. Nanoscale oscillators are attractive for future technological applications because of their small size, electronic control, low power consumption, and ability to efficiently frequency-modulate the devices and phase lock them to external reference signals. This paper presents the fundamentals of the spin-transfer torque effect, device concepts, and an overview of some of the work performed at the National Institute of Standards and Technology.
Synthesis, Characterization, and Properties of Large-Area Graphene Films
Authors: Li Xuesong , Cai Weiwei , Jung In Hwa , An Jin Ho , Yang Dongxing , Velamakanni Aruna , Piner Richard , Colombo Luigi , Ruoff Rodney S.
Published: May 2009

Graphene and few-layer graphene films exhibit unique properties and show promise as electronic devices as well as for passive applications. A significant challenge however is the synthesis of large area graphene and/or multilayer films. A method that is showing promise is the growth of graphene on metal substrates by chemical vapor deposition. In this paper we report on a method to grow large-area graphene films on Cu foils and graphene transfer methods to other substrates. The transferred graphene films were characterized by optical, scanning and transmission electron microscopy, Raman and UV-VIS spectroscopy, and four-point probe electrical measurements. The data shows that graphene can be grown directly on Cu substrates by chemical vapor deposition. The graphene films transferred to SiO2/Si substrates show low defects as determined by the near absence of the "D" band at 1350 cm-1 in the Raman spectrum. In addition, the films were found to have high optical transmittance and electrical conductivity.
Freestanding Graphene and Its Applications
Authors: Banerjee Amrita , Grebel H.
Published: May 2009

The ability to fabricate freestanding graphene opens up the door for new applications in the electronic, optoelectronic, bio-chemical and electro-chemical areas. We follow the advent of this remarkable crystallographic phase through examples.
Optical and Conductivity Properties of Films from Liquid-Phase Exfoliation of Natural Graphite
Authors: Obrzut Jan , Migler Kalman B.
Published: May 2009

We experimentally determine the conductivity and optical transmittance of graphite layers, obtained from the liquid phase exfoliation of natural crystalline graphite. The measured transmittance values range from 0.9 to 0.97, comparable to the theoretical transmittance of graphene. In the low frequency limit the conductivity of the films follows the percolation model for two-dimensional networks. Solution processed graphene materials are attractive for applications as conductive transparent films and scalable graphene devices.
HRTEM Observation of Mechanically Exfoliated Graphene from Natural Graphite and HOPG
Authors: Park SeongYong , Suh YoungJoon , Floresca Herman , Kim Moon
Published: May 2009

Suspended graphene layers were prepared by a micromechanical cleavage method. Adhesive layer was pasted on the surface of meshed Cu TEM grid followed by stamping of natural graphite (NG) and highly ordered pyrolytic graphite (HOPG) on the grid. HRTEM and diffraction pattern analyses were carried out in order to identify number of graphene layers and observed for graphene structure. Intensity ratio of I{11-20}/ I{1-100} varied depending on the number of layers and stacking sequence. By using the intensity ratio, monolayer could be distinguished from multilayer. Edge shape and interlayer structure of graphene were observed by HRTEM analysis.
Effect of Surface Adsorbates on Graphene Probed by Hall-Effect and Raman Spectroscopy
Authors: Claflin Bruce , Park Jeongho , Eyink Kurt , Tomich David , Albrecht John
Published: May 2009

The impact of adsorbed gases on graphene layers grown by SiC sublimation is investigated by temperature-dependent Hall-effect and Raman spectroscopy. For samples stored in ambient laboratory conditions, irreversible changes are seen in sheet resistance (\rho\textsubscript{sh}), mobility, and carrier concentration after heating to 400 K in vacuum. Subsequent heating to 400 K produces no additional changes in \rho\textsubscript{sh}, mobility or carrier concentration. Re-exposure of this 'clean' surface to air produces only minor changes in the electrical characteristics of the film. These kinetics suggest chemisorbed species produce a larger impact on electrical transport in graphene layers than do physisorbed species. The graphene Raman 2D peak is shifted ~15 cm\textsuperscript{-1} at 500 {degree sign}C in vacuum, while the room temperature Raman 2D frequency is unchanged after heating.
Large-Area Epitaxial Graphene: Effect of Strain and Thickness on Electronic Properties
Authors: Robinson Joshua , Fanton Mark , Stitt T. , Stitt T. , Snyder David , Frantz Eric , Tedesco Joseph L. , VanMil Brenda , Jernigan Glenn , Campbell Paul , Myers-Ward R. L. , Eddy Charles , Gaskill D. K.
Published: May 2009

The recent success of graphene transistor operation in the giga-hertz range has solidified the potential of this material for high speed electronic applications. Realization of a graphene technology on the production scale; however, requires the ability to synthesize large area graphene, and rapidly characterize the material's structural and electronic quality. We report a direct link between carrier mobility and Raman topography of epitaxial graphene grown on silicon carbide. We have examined epitaxial graphene with mobility values of 25 - 1100 cm2/V-s, and show that the Hall mobility of epitaxial graphene on the Si-face of SiC (SiC(0001)) is not only highly dependent on thickness uniformity, but also on mono-layer strain uniformity. It is not until the thickness and strain uniformity is approaches 50% of the device width that one is able to achieve mobility values higher than 1000 cm2/V-s.
Surface Passivation Using Silane for Epitaxial Growth of Graphene on SiC substrate
Authors: Kang Byung Jin , Lim Sung Kyu , Cho Byung Jin
Published: May 2009

We report surface pre-treatment technique for high quality graphene layer formation on SiC surface. It has been demonstrated that silicon passivation of SiC surface using silane flow and subsequent sacrificial oxidation can significantly improve surface condition of the graphene layer on SiC with much fewer carbon dumps and wrinkles, reduced electrical resistance, smoother surface roughness of ~ 2.7 Aå and larger domain size of ~380 Aå. Our results suggest that surface treatment before graphitization is the key to synthesize high quality epitaxial graphene layer.
3C-SiC Films Grown on Si(111) Substrates as a Template for Graphene Epitaxy
Authors: Fanton Mark , Robinson Joshua , Weiland Brian , Moon Jeong
Published: May 2009

High quality (111) oriented SiC films were grown Si(111 substrates using a low temperature halogen-based process. The goal of this work was to produce SiC films with a high crystal quality and very low surface roughness for subsequent epitaxial growth of graphene films. SiC films with narrow x-ray diffraction peak widths and surface roughnesses less than 1nm were grown while avoiding common processing defects such as voids at the substrate-film interface.
A Critical Assessment of the Synthesis of Diameter and Chirality Controlled CNTs in Zeolites
Authors: Van Noyen J. , Roeffaers M. , De Cremer G. , Vosch T. , Hofkens J. , Clemente Francesca , Jacobs P. , Sels Bert
Published: May 2009

We here present the controlled synthesis of ultra-small diameter nanotubes in well-defined subnanometer sized confined space within zeolites. A critical view on the zeolite occluded nanotube growth is presented. Thermogravimetric analysis and optical techniques are evaluated for nanotube characterization. The introduction of Bro̸nsted acid sites in the zeolite framework leads to optimized yields. As temperatures below 500{degree sign}C are envisioned for nanotube synthesis, zeolite occluded nanotubes are compatible with current CMOS technology platform, in densities in accordance with ITRS standards for future interconnects, making zeolites a viable pathway for integration of SWCNTs in the chip of the future.
Supramolecular Functionalization of Graphene
Authors: Yang W. , Grennberg Helena
Published: May 2009

Graphene dispersions, produced in a chemically assisted exfoliation process, have been treated with two new pyrene derivatives that may adsorb to the graphene in a non-covalent supramolecular fashion that does not cause irreversible damage to the graphene π system. The initial qualitative studies by absorption and fluorescence spectroscopy have shown that the desired interaction indeed takes place, results that are important for future developments of functional materials based on high-quality graphene.
Atomic-Layer-Deposited Al2O3 as Gate Dielectrics for Graphene-Based Devices
Authors: Lee Bongki , Mordi Greg , Park Taejoo , Goux Laurence , Chabal Yves J. , Cho Kyeongjae , Vogel Eric M. , Kim Moon , Colombo Luigi , Wallace Robert M. , Kim Jiyoung
Published: May 2009

We present a facile route to deposit a uniform Al2O3 layer on a highly oriented pyrolytic graphite (HOPG) surface using atomic layer deposition (ALD). Al2O3 layers deposited from TMA (trimethylaluminum)/ H2O chemistry showed selective deposition only on step edges. However, TMA/O3 chemistry resulted in the deposition of Al2O3 layers on basal planes of HOPG, which has a chemically inert surface. An O3-pretreatement followed by Al2O3 deposition using TMA/O3 chemistry produced conformal and uniform Al2O3 dielectric layers with a small RMS roughness of ~ 0.2 nm. This suggests that O3-pretreatement prior to ALD deposition makes the chemically inert HOPG surface reactive toward ALD precursors, which leads to the desired two-dimensional growth mode. High-resolution transmission electron microscopy (HR-TEM) and Raman spectroscopy revealed that this O3 process used for Al2O3 deposition does not introduce a significant defect concentration to the top graphene layer. The dielectric constant of the deposited Al2O3 film on top of the HOPG surface was found to be ~ 9 from C-V measurements.
CMOS Scaling Beyond 22 nm Node
Authors: Sadana Devendra , Bedell Stephen W. , De Souza J. P. , Sun Y. , Kiewra E. , Reznicek A. , Adams T. , Fogel Keith , Shahidi G. G. , Marchiori C. , Webb D. J. , Richter M. , Gerl C. , Sousa M. , Fompeyrine J. , Germann R.
Published: May 2009

Silicon CMOS scaling continues to defy all previous doom and gloom scenarios and is poised to extend to 15 nm node. There is a paradigm shift though; in previous generations of CMOS (before 90 nm) both performance and transistor density scaling could be achieved simultaneously with passive cooling. Currently, the density scaling appears to continue unabated due to advances in optical lithography (immersion, phase contrast imaging, double exposure, etc). However, performance scaling requires power-performance trade off consideration as the peak performance is limited by heat dissipation that can be managed via passive cooling (< 100 watts/cm2). Nevertheless, performance targets for CMOS products are being met at system level by multi-core architecture which allows massive parallel data processing. Current and future CMOS scaling is undoubtedly being driven by innovations at all levels, including system architecture, circuit design, integration, device design and new high mobility channel materials. This presentation is focused on the channel materials which we believe are most promising for future CMOS nodes.
Review of Current Status of III-V MOSFETs
Authors: Thayne Iain , Hill Richard , Holland Martin , Li Xi , Zhou Haiping , Macintyre Douglas , Thoms Stephen , Kalna Karol , Stanley Colin , Asenov Asen , Droopad Ravi , Passlack Matthias
Published: May 2009

To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) (1) to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. A wide range of high electron mobility channel materials, device architectures and gate oxides are currently being considered, and in this review, key performance metrics of III-V MOSFETs will be compared.
Integration of III-V and Si CMOS Devices by Molecular Beam Epitaxy
Authors: Lubyshev Dmitri , Fastenau Joel , Liu W. K.
Published: May 2009

Heterogeneous integration of III-V devices on Si may realize high performance integrated circuits for analog and digital applications. Such integration provides the combined advantages of high volume production of Si-based electronic circuitry with superior high speed performance of III-V components. Various technologies have been implemented to achieve this, from pick and-place die transfer to full wafer bonding to direct growth of III-V's on Si, but all require the implementation of high-quality III-V epilayers on Si CMOS host substrates. This paper presents the current status of various efforts at IQE to realize III-V device performance on Si substrates using molecular beam epitaxy (MBE) crystal growth technology.
InGaAs MOSCAPs and self-aligned inversion-channel MOSFETs with Al2O3/Ga2O3(Gd2O3) as a gate dielectric
Authors: Lin T. D. , Chiu H. C. , Chang P. , Lee W. C. , Chiang T. H. , Kwo J. R. , Tsai W. , Hong M.
Published: May 2009

Ultra-high-vacuum deposited Al2O3/Ga2O3(Gd2O3) dual-layer gate dielectrics were used to fabricate metal-oxide-semiconductor capacitors (MOSCAPs) and MOS field-effect-transistors (MOSFETs). Excellent electrical properties of well-behaved C-V characteristics with very small frequency dispersions, a very low leakage current density of 2.5×10-9 A/cm2 at Vg = Vfb + 1V, and a low Dit of 2.5×1011 cm-2eV-1 near the mid-gap, have been demonstrated in In0.2Ga0.8As MOSCAPs, which were RTA to 850°. Moreover, 1μm-gate-length self-aligned inversion-channel In0.53Ga0.47As MOSFETs have achieved record-high maximum drain current of 1.05 mA/μm and peak transconductance of 714 μS/μm. Both device performances are the highest among all-types of enhancement mode MOSFETs, fabricated by self-aligned or non-self-aligned process. Various enhancement-mode MOSFETs in the configurations of inversion-channel and non-inversion-channel, fabricated with self-aligned and non-self-aligned processes are compared.