Fabrication of InP Vertical Gate-All-Around Transistors Using Crystal Phase Transition Heterojunction
Authors: Uchida Ryosei , Takeda Yuki , Azuma Yuki , Zheng Ziye , Motohisa Junichi , Tomioka Katsuhiro 
Published: December 2024

Introduction

Crystal phase transition can stabilize metastable crystal phase as single crystal structure. For example, zinc-blende (ZB) stable crystal phase in InP nanostructures can be easily transformed into wurtzite (WZ) crystal structure [1]. One of the advantages in this phenomenon is band-structure change from indirect gap to direct gap. Another advantage of the crystal phase transition enables us to form a kind of heterojunction in single materials, named crystal phase heterojunction (CPHJ). The CPHJ can form ideal heterojunction regardless of misfit dislocations in conventional heterostructure based on lattice mismatched systems. The InP-based CPHJ have been found to form a Type-II band discontinuity by optical characterization [2]. There was, however, few report on electronics application the InP CPHJ. Here we report on fabrication of vertical-gate-all-around (VGAA) transistors using the InP CPHJ, which was formed by the WZ- InP NWs on ZB InP(111)A substrates by selective-area growth.

Experiment

A 20 nm-thick SiO2 layer was deposited on n-InP (111) A substrates by RF-sputtering. Periodical circular-shaped mask openings were formed on SiO2 mask by electron beam lithography and wet chemical etching. The opening patterns were designed with diameter of 50 nm and 70 nm and pitch of 400 - 2000 nm. Vertical InP NWs were formed by selective-area metal organic vapor phase epitaxy (MOVPE). Trimethylindium (TMIn) and tertiarybutylphosphine (TBP) were used as source materials, and diethylzinc (DEZn) and monosilane (SIH4) as p- and n- type dopants. The growth temperature for the InP NWs was 660°C. V/III ratio was 24.

We fabricated the VGAA structure by using the InP NWs. First, we deposited 10 nm-thick Hf0.8Al0.2O as gate oxides by atomic layer deposition (ALD) on NWs. Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal by sputtering. Benzocyclobutene (BCB) was deposited by spin-coating as isolation layer between gate and drain layers. The top portion of the NWs was exposed by reactive ion etching (RIE). Then drain (Ti/Pd/Au) and source (Ni/Ge/Au/Ni/Au) metals were evaporated on the top of the NWs and on the substrate. Finally, the devices were annealed at 400°C in N2 for 3 min.

Result and Discussions

Position controlled vertical InP NWs were uniformly formed on the n-InP (111) A substrates. The NW morphology had hexagonal pillar shaped structure surrounded with vertical side facets, that was rotated with thirty-degree against the {-110} cleavage planes. This means {-211} facets were formed as the vertical sidewalls and the crystal structure grown NW was composed of WZ phase.

The photoluminescence (PL) spectra of the grown NWs showed the three peak origins whose peaks were at 1.33 eV, 1.37 eV, and1.43 eV, respectively. The peak at 1.33 eV was originated from the InP ZB bandgap, and 1.43 eV was caused from the optical transition of WZ bandgap. The peak at 1.37 eV was assumed to be a type-II optical transition at the InP CPHJ. The PL also evidenced that the grown NWs had WZ structure.

The fabricated VGAA transistor showed drain current was moderately modulated by the gate bias. Interesting point was that the Shottky barrier height at the InP CPHJ was modulated by the gate bias and the tunneling transport across the potential barrier in the CPHJ contributed to the drain current. The subthreshold slope of the transistor was 112 mV/dec. The threshold voltage (VTH) was -0.07 V. Gate leak current was about 10-9 – 10-3 A/μm, which was quite high as compared to the other III-V NW-based VGAA-FETs [3]. This was because that gate-oxide/InP interface was degraded. Further investigation will be required for achieving high-quality gate oxides/InP interface and will be discussed the improvement of the demonstrated devices.

[1] Y. Kitauchi et al., Nano Lett., 10, 1699-1703 (2010).

[2] A Jash et al., ACS Photonics, 10, 3143-3148 (2023).

[3] H Gamo et al., IEEE Electron Device Lett, 41, 1169-1172 (2020).