Investigating Polycrystalline III-V Thin Films As Channel Materials for “Above IC” Logic and Memory Applications
Authors: Curran Anya , Secco Eleonora , Pescaglini Andrea , Gocalinska Agnieszka , Mura Enrica , Thomas Kevin , Povey Ian M , Pelucchi Emanuele , O'Dwyer Colm , Hurley P. K. , Gity Farzan 
Published: February 2020

As conventional semiconductor devices approach the limit of dimensional scaling, the hardware underpinning Information and Communication Technologies is entering an exciting new phase where further increases in integration density will depart from conventional scaling approaches. Future integrated circuits for high performance systems would benefit greatly from a practical realisation of heterogeneous 3D integration, where memory is interleaved with logical computation layers [1]. This approach has the potential for significant gains in energy efficiency, area, and performance. To realise these potential benefits requires the development of semiconductor switches fabricated at temperatures low enough for ‘above IC’ applications, which generally limits processing (on time scales from minutes to hours) to temperatures < 450℃. As dopant activation is typically the highest temperature in a transistor process, this points to semiconductor material systems where dopant activation is not required. In the case of certain III-V and III-N semiconductors, a high density free carrier concentration is present on the surface, with no intentional doping and no activation annealing. For example, it is known that InAs exhibits a high surface electron sheet density (1012-1013cm-2) even in the absence of intentional n-type doping or any thermal annealing for activation [2]. In this work we report on research activities exploring if this high electron concentration can be exploited for above IC device applications. The electronic and structural properties of InAs and Al doped InAs deposited by chemical vapour deposition (CVD) on SiO2/Si and glass substrates at temperatures ≤ 475℃ are reported, with a view to their application as low temperature formed n and p channel transistors which could be integrated in the traditionally passive back-end-of-line metallization of integrated circuits.

Figure 1(a) shows the electron mobility and carrier concentration obtained for a nominally undoped polycrystalline (poly) InAs layer (~35nm) on glass formed by CVD at 475℃. The poly-InAs layer demonstrates a high electron concentration in the 6-8x1018 cm-3 range. The carrier type is electrons, with a mobility value around 100 cm2/Vs, which is almost independent of temperature from 125K to 400K, indicating the electron mobility is limited by surface roughness. It is noted that poly-GaAs films demonstrate measured electron mobility values of 0.14 cm2/Vs and measured carrier concentration of 1.3x1016 cm-3. Moving to poly-InAs, the carrier concentration increases to values in the 1018 cm-3 range, with electron mobility values typically from 20-100 cm2/Vs. Forming InAlAs/InAs/InAlAs heterostructures (T< 475℃) results in electron mobility values which are consistently above 100cm2/Vs.

If we consider the devices to be embedded within upper metal layers of the IC, then a simplest device architecture would be to utilize the thin InAs channel in a junctionless device architecture [3]. This may require control of the electron concentration to ensure full InAs charge depletion for a high Ion/Ioff ratio. Figure 1(b) demonstrates how the InAs electron concentration can be controlled through Zn incorporation. Moreover, the InAs can be inverted to a p-type semiconductor with increasing Zn flux. Initial hole mobility values around 5 cm2/Vs have been achieved (see Figure 1(c)), demonstrating the potential of this approach for low temperature (T≤ 475℃) formed complementary n and p channel semiconductors for logic or memory (select transistor or SRAM) devices above IC. Figure 1(d) shows a functioning top gated n-channel MOSFET formed on a composite InAs (nominal thickness = 10nm)/GaAs (nominal thickness = 25nm) channel on glass. The device Ion/Ioff ratio is 100. The largest value obtained for the Ion/Ioff ratio to date is ~800. Work is on-going to introduce Al into the InAs channel to increase the energy gap, with the view to achieve higher Ion/Ioff ratios. The presentation will include results from XPS to analyse the % Al incorporation and how this addition of aluminium impacts the carrier mobility and MOSFET behaviour.

Finally, it is noted that there is considerable scope for innovation in III-V heterostructure design for optimising device performance, as the spectrum of options is extensive, and epitaxy is not required. In addition, low temperature devices with high electron mobility could be of interest to logic and display technology on flexible substrates.

[1] Wong et al., Nature Nanotechnology 10, 191 (2015)

[2] Weber, J. R. et al., Appl. Phys. Lett. 97, 192106 (2010)

[3] Colinge, J.P. et al., Nature Nanotechnology 5, 225-229 (2010)

Figure 1