(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options
Authors: Peralagu Uthayasankaran , Li Xu , Ignatova Olesya , Fu Yen-Chun , Millar David Alan John , Steer Matthew J , Povey Ian M , Hossain Khalid , Jain Manish , Golding Terry G , Droopad Ravi , Hurley P. K. , Thayne Iain G 
Published: February 2020

In an era of power-constrained transistor scaling, III-V semiconductors, with high electron velocities, appear promising as the n-channel solution in post-Si CMOS technologies [1]. To make this a reality, substantial undertaking has gone into finding solutions for the technological challenges facing III-V MOSFETs [1,2]. InGaAs, in particular, has been the centre of extensive research effort. This has led to the development of surface passivation measures capable of significantly minimizing the defects at the gate dielectric/III-V interface [3,4], ultra-low resistance source/drain contact technology [5], III-V heterointegration capability on Si substrates [6] and demonstration of record performing planar MOSFETs suited for high-performance and low-power logic [7-9].

Currently, InGaAs is being primed for entry into CMOS at the 7nm technology node and beyond. However, given the transition to FinFETs in CMOS technology [10], there is a need to develop dry etch processes capable of nanometer-scale fin definition in III-Vs. Key requirements of the dry etch process are vertical sidewalls and minimum etch damage. The former provides for efficient device electrostatics while the latter is required for a high quality sidewall MOS interface [11]. However, satisfying both criteria is challenging. Highly anisotropic dry etching required for sidewall verticality is more damaging due to the physical nature of the process. Unlike Si, the induced damage cannot be cured by post etch annealing in III-Vs [1].

In this talk we will first report on the dry etch processing systematically investigated for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. Fins were etched in InGaAs, masked with HSQ of nanometric linewidths, for a variety of dry etch gas chemistries using either a RIE or an ICP process. A fin profile within 3¢ª of vertical was achieved with an ICP etch process based around Cl2/CH4/H2 gas chemistry (Fig. 1a). Highly vertical 10nm fins with 16:1 aspect ratio, perhaps the highest aspect ratio, smallest critical dimension fins to date in InGaAs, have also been demonstrated using this chemistry (Fig. 1b). Impact of the various ICP processes were assessed on Al2O3/InGaAs(100) MOS capacitors subject to blanket etch processing prior to (NH4)2S wet treatment and  ALD gate dielectric. Despite the promising fin profile, the Cl2/CH4/H2 based ICP process yielded a severely degraded CV characteristic, featuring a peak Dit that is ~5x higher than the control (unetched) sample (Fig. 2). TEM and AFM were used to further elucidate the impact of the various ICP etch processes on the physical properties of the Al2O3/InGaAs interface.

The second part of the talk will focus on the mitigation of etch-induced sidewall damage via dry etch process optimization and sidewall passivation techniques. It will be demonstrated that the modification of Cl2/CH4/H2 gas chemistry to include O2 results in the substantial reduction of etch-induced damage, due to the lowering of the ICP power. A near-vertical sidewall profile similar to that obtained for the etch chemistry without O2 is further retained. Some examples of nanowires realized using this gas chemistry will also be shown. The sidewall damage arising from Cl2/CH4/H2/O2 etch chemistry will be assessed on both (100) and (110) oriented InGaAs. To alleviate the damage two post-etch sidewall passivation schemes were explored. The first was based on a photon-assisted hydrogenation process developed by Amethyst Research Inc., applied post-etch or post ALD high-k, and was investigated on Al2O3/InGaAs(100) MOS capacitors subject to Cl2/CH4/H2 blanket etch. The CV results indicated a larger reduction of etch damage for hydrogenation done post ALD high-k (Fig. 3). In the second approach, a wet “digital” etch surface clean was applied following a Cl2/CH4/H2/O2 blanket etch, resulting in a complete recovery of etch damage as determined from CV characteristics of Al2O3/InGaAs(100) MOS capacitor. The process was also investigated for (110) oriented InGaAs. Details of the passivation schemes and the associated results will be discussed further. 

References

[1] J. del Alamo, Nature, 479, 317 (2011).

[2] S. Oktyabrsky et al., IJHSES, 18, 761 (2008).

[3] P.K. Hurley et al., IEEE T-DMR, 13, 429 (2013).

[4] V. Chobpattana et al., JAP, 116, 124104 (2014).

[5] R. Oxland et al., IEEE EDL, 33, 501 (2012).

[6] R.J.W. Hill et al., IEEE IEDM, 2010.

[7] S. Lee et al., VLSI Symp., 2014.

[8] C.Y. Huang et al., IEEE IEDM, 2014.

[9] S.W. Chang et al., IEEE IEDM, 2013.

[10] C.C. Wu et al., IEEE IEDM, 2010.  

[11] X. Zhao et al., IEEE EDL, 35, 521 (2014).

Figure 1