Underlayer Selection to Improve the Performance of Polycrystalline Ge Thin Film Transistors
Authors: Imajo Toshifumi , Moto Kenta , Yamamoto Keisuke , Suemasu Takashi , Nakashima Hiroshi , Toko Kaoru 
Published: December 2020

1. Introduction

To improve the performance of Ge-thin film transistors (TFTs), it is essential not only to enhance the crystallinity of poly-Ge but also comprehensively study the relationship between its electrical properties and TFT characteristics. We recently advanced conventional solid-phase crystallization (SPC) method, significantly enlarged the grain size of poly-Ge and recorded the highest Hall effect hole mobility (μ
Hall) of 620 cm2/Vs [1,2]. We fabricate poly-Ge TFTs using SPC-Ge and discuss the relationship between the film properties and TFT characteristics [3]. In the present study, we discuss the Ge thickness effects on the poly-Ge TFTs. To further improve the TFT performance, we enhanced the Ge crystallinity at thin film region (< 100 nm) by inserting Al2O3 underlayer.

2. Experimental Procedure

The a-Ge layers were deposited on SiO2 glass substrates by vacuum deposition while heating at 125 °C. The initial film thickness of the a-Ge layer (t
i) ranged from 25 to 200 nm. The samples were also prepared in which the insulating underlayer (Al2O3, GeO2) was sputtered at 10-50 nm for Ge with t
i = 50-300 nm. The samples were then loaded into a conventional tube furnace in an N2 atmosphere annealed at 450 °C for 5 h to induce SPC.

We fabricated accumulation-mode metal source/drain (S/D) p-channel TFTs using SPC-Ge. Figure 1 shows the process and structure. Pt and TiN were sequentially formed as a metal S/D and a capping layer, respectively. We used Al/SiO2/Al2O3/SiO2/GeO2 for the gate stack. The channel width and length (W/L) were 55 and 10 μm, respectively. All process including SPC were conducted below 450 °C.

3. Results and Discussion

Figures 2(a)‒2(e) show the grain size dramatically varies with t
i. All samples showed p-type conduction because the defects in Ge provides shallow acceptor levels that generate holes at room temperature. Therefore, larger grain sizes provide lower hole concentration p, as shown in Figs. 2(f) and 2(g). Figure 2(g) also shows that μ
Hall peaks at t
i = 200 nm, whereas the grain size peaks at t
i = 100 nm. This behavior is likely attributed to the carrier scattering near the Ge/SiO2 interface [2].

Figure 2(h) shows that on-current I
on increases with increasing t
i, which reflects μ
Hall. Off-current I
off is determined by the relationship between t
i and the maximum depletion layer width (d
max), which can be estimated from p. From the relationship between d
max and t
i, we found that the lower t
i provides the higher occupation of the depletion layer in the whole SPC-Ge layer, which decreases I
off. Reflecting I
on, I
off, and the on/off current ratio I
on/I
off reaches the maximum at t
i = 50 nm. Figure 2(i) shows that field-effect mobility (μ
FE) is consistent with the trend of μ
Hall, while μ
FE is much lower than μ
Hall. This is likely because not only carrier scattering at the MOS interface, but also large I
off causes underestimation of transconductance and μ
FE.

We thinned the t
i = 100 nm sample to 55 nm using chemical-mechanical polishing. The film keeps low p enough to get full-depleted, and was processed into TFT as before. Figures 3(a) and 3(b) show the typical p-channel transistor operation, high I
on/I
off (102) and μ
FE (170 cm2/Vs) because of both the high I
on due to the high μ
Hall and low I
off. Therefore, to improve the TFT performance, a Ge layer compatible with high μ
Hall and a thin film is desirable.

Because the nucleation in a thin film occurs at the substrate interface, we modulated the interface by preparing Al2O3 and GeO2 underlayers. Figures 4(a)‒4(f) show the grain size is almost doubled by inserting underlayers for both t
i = 50 nm and 300 nm, while the t
i = 50 nm Ge layer with GeO2 did not crystallize completely due to the slow growth rate. Compared to the samples without underalyers, Fig. 4(g) shows the underlayers reduce p reflecting the large grain size. Figures 4(h) shows the GeO2 underlayer provides high μ
Hall for t
i = 300 nm, while low μ
Hall for t
i < 300 nm. This behavior is likely due to the carrier scattering near the Ge/GeO2 interface. Conversely, the Al2O3 underlayer provides high μ
Hall for t
i < 300 nm. In particular, the t
i = 50 nm Ge layer exhibits relatively low p and high μ
Hall. These results suggest that the Al2O3 underlayer has the potential to further improve the performance of poly-Ge TFTs.

References

[1] K. Toko et al., Sci. Rep.
7, 16981 (2017).

[2] T. Imajo et al., Appl. Phys. Express
12, 015508 (2019).

[3] K. Moto et al., Appl. Phys. Lett.
114, 212107 (2019).

Figure 1