bluuebunny/crossref_metadata_2025 huggingface dataset:
EFFECTS OF GENDER, PRELOAD, AND TRUNK ANGLE ON INTRINSIC TRUNK STIFFNESS
Authors: Miller Emily M. , Bazrgari Babak , Nussbaum Maury A. , Madigan Michael L.
Published: April 2012

Gender, lifting loads, and flexed trunk postures are three risk factors associated with low back pain. Previous studies have not found gender differences in effective trunk stiffness (intrinsic stiffness plus reflex response) using force perturbations, but these measures may have been confounded by differences in trunk kinematics between males and females. The purpose of this study was to investigate the effects of gender, trunk extensor preload, and trunk flexion angle on intrinsic trunk stiffness using position perturbations, which have the potential to eliminate kinematic differences between research subjects and to separate intrinsic stiffness from reflex responses. A total of 13 males and 12 females were exposed to sudden, small trunk flexion position perturbations with two trunk extension preloads (0 and 30% maximum) and three trunk flexion angles (0, 20, and 40 degrees). Data collected during position perturbations were used along with a two degree of freedom model of the trunk and connecting elements to estimate intrinsic trunk stiffness. Intrinsic stiffness was lower in females compared to males, and increased with increasing preload and trunk flexion angle. Intrinsic stiffness increased more substantially among males with increasing preload and trunk angle, and effects of trunk angle were diminished with a preload. A lower intrinsic stiffness and smaller increases with preload and trunk angle, may contribute to the increased rate of occupational LBP and injury among females.
CLASSES OF GRADIENT RICCI SOLITONS ON GENERALIZED POINCARÉ MANIFOLDS
Authors: BERCU GABRIEL , POSTOLACHE MIHAI
Published: April 2012

This paper aims to be a natural continuation of our very recent research, published in [Int. J. Geom. Meth. Mod. Phys.8(4) (2011) 783–796]. Using as geometric background a generalized Poincaré manifold, this work presents models of new explicit classes of manifolds within the class of gradient Ricci solitons. In Sec. 1 we shortly introduce a history of this topic to motivate its relevance both for theoretical and applied sciences, and in Sec. 2 our work contains its notations and assumptions. In Sec. 3 we give our framework and introduce the basic result, and in Sec. 4 we develop our theory. Finally, in Sec. 5, we conclude this paper and suggest possible further development. While the background in the first two sections is introductory, the theory in Secs. 3 and 4 is new as a whole, containing original results.
Fast Light-Emitting Silicon-Germanium Nanostructures
Authors: Lockwood D. J. , Wu Xiaohua , Baribeau J.-M. , Modi N. , Tsybeskov L.
Published: April 2012

Epitaxially-grown three-dimensional Si/SiGe nanostructures produce photoluminescence and electroluminescence in the desired spectral range of 1.3-1.6 μm. We show that by controlling and modifying such Ge-rich SiGe nanoclusters during growth it is possible to fabricate very fast and hence more efficient SiGe light-emitting devices. Models for the physics of carrier recombination in these Si/SiGe nanostructures are presented, and a new route toward CMOS compatible light emitters is proposed.
(Invited) Passivation of III-V Nanowires for Optoelectronics
Authors: LaPierre Ray R. , Chia Andrew C. , Haapamaki Chris M. , Tajik Nooshin , Li Y. , Zhao S. , Mi Z.
Published: April 2012

Surface passivation of III-V compound semiconductor nanowires is presented. InAs and GaAs nanowire cores were grown using gas source molecular beam epitaxy followed by a passivating shell of InAl(As,P). Improvements in electrical and optical (luminescence) properties of the nanowires were observed upon passivation due to removal of detrimental surface states. Passivation of InP nanowires by polysulfide solution is also demonstrated to improve luminescence.
Emissive Semiconductor Nanocrystals: Recent Progress
Authors: Lesnyak Vladimir , Panda Subhendu K. , Hickey Stephen G. , Miao Shiding , Gaponik Nikolai , Eychmüller Alexander
Published: April 2012

Here we present recent progress in the area of the colloidal synthesis of semiconductor nanocrystals related to the exploration of novel materials, and the fabrication of alloyed and doped particles exhibiting bright emission. The approaches shown increase the number of nanoparticulate semiconductors, and tune and extend their electronic and optical properties to specific regions of interest.
Two-Photon Photoluminescence from Hierarchical ZnO Nanostructures
Authors: Grinblat G. , Capeluto M.G. , Tirado M. , Comedi D. , Bragas A.V.
Published: April 2012

Hierarchical ZnO nanostructures (such as nanowires, nanocombs and nanohedgehogs) were grown by means of a vapor-phase transport technique in a tubular furnace. Silicon based substrates were used, over which Au nanoclusters were deposited as growth catalyzers. We study the two-photon absorption induced photoluminescence (TPPL) from the various ZnO nanoobjects grown using a micrometer sized polarised laser beam as the excitation source. The UV region of the TPPL spectra contains various peaks whose different patterns depend on the type of nanostructure and its orientation with respect to the incident polarization. We identify the peaks in the TPPL spectra, which are found to be dominated by free exciton emission and their phonon replicas. For the nanocomb, however, Fabry-Perot modes originating from optical multiple reflections within the comb's teeth are demonstrated.
(Invited) Strategies for Isolating Colloidal Quantum Dot Luminescence from External Fluctuations: Alloyed Shells on CdSe and Mn2+ Doping of ZnSe
Authors: Allen Claudine N. , Lamarre Sébastien A. , Tessier Jonathan , Lachance-Quirion Dany , Lecavalier Marie-Ève , Veilleux Vincent
Published: April 2012

ZnxCd1-xS alloyed shells and Mn2+ ions were studied as means to confine charge carriers away from the surface of nanocrystals. In the former case, the electron confinement potential increased with the Zn fraction in CdSe/ZnxCd1-xS colloidal quantum dots and their photoluminescence blueshifted by ~50 nm. However, structural defects and polydispersity became important in samples with x >0.7 likely due to a phase transition and to strain increasing with core/shell lattice mismatch reaching 12% when x = 1. In the latter case, the Mn2+ ions diffused within MnyZn1-ySe/ZnSe nanocrystals act as localized luminescent centers and their density can be controlled with the Mn fraction in the alloyed core. The ions are excited through energy transfers from excitons in the ZnSe, and given the long lifetime of the Mn2+ first excited state, thermoactivated reverse energy transfer also occurred and emission from the ZnSe excitons was observed.
(Invited) Synthesis of New Fluorescent Semiconductor Nanoparticles and Their Optical Uses
Authors: Kuwabata Susumu , Uematsu Taro , Torimoto Tsukasa
Published: April 2012

Solid solution nanoparticles of AgInS2-AgGaS2 emitting intense photoluminescence were synthesized by thermal decomposition of a single-source precursor, AgInyGa1−y(S2CN(C2H5)2)4 in oleylamine. They have chalcopyrite structure with their size ranging from 4 to 5 nm. Photoluminescence and absorption spectra were change by changing ratio of Ga in the crystal, due to the larger bandgap of AgGaS2 compared with AgInS2. Quantum yields larger than 30% were maintained in the composition range between 0.4 < y < 1.0, below which it decreased largely.
Thermal Effect on Electroluminescence Quenching in SiO2 with Ge and ReOX Nanoclusters
Authors: Tiagulskyi Stanislav I. , Tyagulskiy Igor P. , Nazarov А.N. , Nazarova Tamara M. , Rymarenko Nataliya L. , Lysenko Volodymyr S. , Rebohle Lars , Lehmann Jan , Skorupa Wolfgang
Published: April 2012

Thermal quenching and thermal dependences of the electrical quenching of electroluminescence in metal-oxide-silicon light-emitting devices implanted by Ge and Tb ions containing Ge and TbOx nanoclusters after annealing are studied. Light thermal quenching of the main green line (541 nm) in the EL spectrum of Tb implanted structures is observed. The strong temperature dependence of the electrical quenching of EL both for Ge and Tb implanted structures is explained by the participation of mobile ions in negative and positive charge generation in the bulk of SiO2 and near the SiO2-Si interface, correspondingly.
Processing-Induced Modification of Photo- and Cathodoluminescence Spectra of TiO2 Nanotubes
Authors: Enachi Mihai , Stevens-Kalceff Marion , Burlacu Alexandru , Tiginyanu Ion , Ursaki Veaceslav
Published: April 2012

Cathodoluminescence and photoluminecsence are investigated in titanium dioxide nanotubes (TiO2 NTs) produced in an ethylene glycol based electrolyte with the variation of the temperature of the electrolyte which allows the control of the inner diameter of nanotubes. The crystal structure of the produced nanotubes is controlled by the post-anodization thermal treatment. A new fast and cost-effective method for the fabrication of anatase TiO2 NTs is proposed. The cathodoluminescence spectra and panchromatic images from the produced TiO2 nanotubes suggest the formation of resonator modes in clusters of nanotubes. The enhancement of the ultraviolet near-bandgap or the green photoluminescence is demonstrated by means of coating the anatase TiO2 nanotubes with thin Ag or Au films, respectively.
Reliability of Nanoparticle-Coated Phosphors for White LED Application
Authors: Cho In Hyun , Yoo Jae Soo , Suh Dong Wook , Anoop G. , Lee Seung J. , Kwon Sang J.
Published: April 2012

For the application to a light emitting diode, phosphors require thermal resistance and proper optical spectra with high quantum efficiency. Specially, reliability issues are getting critical due to the harsh operating environment as the solid state lighting application is getting dominant. Here, oxynitride material system, which is not introduced into commercial market yet, is investigated. In Eu- doped MO-Si3N4 system, thermal, moisture, and photonic resistance are examined. It is found that the surface state and cystallinity are important for guaranteeing the device reliability, even though the powder chemical and optical properties are good enough, comparing to well known commercialized phosphor such as Y3Al5O12:Ce and Sr2SiO4:Eu.
Bilayer Pseudo-Spin Field Effect Transistor (BiSFET): Concepts and Critical Issues for Realization
Authors: Register Leonard F. , Mou X. , Reddy Dharmendar , Jung Wooyoung , Sodemann Inti , Pesin Dima , Hassibi Arjang , MacDonald Allan H. , Banerjee Sanjay K.
Published: April 2012

The Bilayer pseudo-spin Field Effect Transistor (BiSET) has been proposed as one means of taking advantage of possible room temperature superfluidity in two graphene layers separated by a thin dielectric. In principle, the switching energy per device could be on the scale of 10 zJ, over two orders of magnitude below estimates for "end-of the roadmap" CMOS transistors. However, achieving both the goal of room temperature superfluidity and harnessing it for low-power switching pose substantial challenges, both theoretical and experimental. In this work we review the basic graphene superfluidity and BiSFET concepts, our current understanding―and limits to that understanding―of the requirements for condensate formation, and how these requirements could impact BiSFET design.
Current Switching in Crossed Graphene Nanoribbons
Authors: Lake Roger K. , Habib K. M. Masum
Published: April 2012

Current switching by voltage control of the quantum phase has been demonstrated theoretically in crossed graphene nanoribbons. Notable features are the large suppression of the transmission over a wide range of energy of 1.2 eV at zero bias and the high sensitivity of the transmission to an applied bias, changing by 3 orders of magnitude with a bias change of 0.15 V. The magnitude of the current is modulated by a factor of 1000. The area of the intersection that is the active region of the device is 1.8nm x 1.8nm consisting of 120 atoms.
Device Characteristics of In Situ CCVD Grown Bilayer Graphene FETs at Elevated Temperatures
Authors: Wessely Pia Juliane , Wessely Frank , Birinci Emrah , Riedinger Bernadette , Schwalke Udo
Published: April 2012

In this paper we report on transfer-free fabrication of bilayer graphene field effect transistors (BiLGFETs) on oxidized silicon wafers. By means of catalytic chemical vapor deposition CCVD) the in-situ grown BiLGFETs are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. BiLGFETs exhibit ultra-high on/off-current ratios of 1e7 at room temperature, exceeding previously reported values by several orders of magnitude. The transfer characteristic shows a pure unipolar p-type device behavior. Furthermore, when increasing the ambient temperature to 200 degree C, the on/off-current ratio only degrades by one order of magnitude for BiLGFETs. Besides the excellent device characteristics, the complete CCVD fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.
In Situ Electrical Studies of Ozone Based Atomic Layer Deposition on Graphene
Authors: Jandhyala Srikar , Mordi Greg , Lee Bongki , Kim Jiyoung
Published: April 2012

In this study, we present in-situ electrical studies of back-gated graphene field-effect transistors (GFETs) exposed to ozone at room temperature. Here, we compare the effect of the ozone exposure on transport characteristics in two different environments using a vacuum probe station with static vacuum and an atomic layer deposition (ALD) chamber having a dynamic environment with continuous nitrogen purge. We observed that in both the cases there is a p-type doping in graphene upon exposure to ozone, but, there is a significant difference in the ozone exposure time required to witness a noticeable effect on the transport properties, with the dynamic environment requiring a longer ozone treatment period. The observed effect on graphene devices was found to be reversible under vacuum suggesting a physisorption process. We also demonstrate top-gate GFETs on chemical vapor deposited (CVD) graphene using 10 nm ALD Al2O3 as gate dielectric deposited with the ozone functionalization approach.
Direct Graphene Growth on Oxides: Interfacial Interactions and Band Gap Formation
Authors: Kelber Jeffry A. , Zhou Mi , Gaddam Sneha , Pasquale Frank L. , Kong Ling Mei , Dowben Peter A.
Published: April 2012

Direct graphene growth on oxides, without a metal catalyst, is a critical step towards the industrial-scale development of graphene devices. Such growth has been accomplished on MgO(111) by physical and chemical vapor deposition, and on Co3O4(111) by molecular beam epitaxy. For MgO(111), there is evidence of significant oxide reconstruction and reaction with the first carbon layer, and a ~ 0.5-1 eV band gap, suggesting a commensurate graphene/oxide interface. For Co3O4(111), growth occurs in a layer-by-layer fashion, with an incommensurate interface. In both cases, there is significant graphene-to-oxide charge transfer. The different results for the two different oxides appear to be due to the relative instability of the O-terminated (111) MgO surface. These results suggest a broad variety of potential electronic/spintronic applications, and indicate feasible routes towards fabrication of graphene devices by industrially practical and scalable methods.
Large Area Mapping of Graphene Grain Structure and Orientation
Authors: Floresca H.C. , Hinojos D. , Lu N. , Chan J. , Colombo L. , Wallace R.M. , Wang J. , Kim Jiyoung , Kim Moon J.
Published: April 2012

Chemical vapor deposited (CVD) graphene grows as a polycrystalline sheet with grains that are oriented in many directions. There is a push to increase the size of these grains until a large single-crystal graphene sheet can be achieved. With the increase in grain size comes the need to be able to determine the lattice orientation of larger areas. Here we present a method using a simple well-known transmission electron microscopy (TEM) technique that allows us to map the orientation of a 50µm by 50µm area of graphene. This method created the largest graphene orientation map to date and has the ability to scale with the increasing grain sizes. From the map, statistics and interpretations were drawn, giving details about the graphene grown through the CVD recipe.
Reduced Pressure-Chemical Vapor Deposition of High Quality Ge Layers on SiGe/Si Superlayers for Microelectronics and Optoelectronics Purposes
Authors: Chen Da , Xue Zhongying , Liu Su , Zhang Miao
Published: April 2012

We have investigated the structural properties of Ge thick films grown directly onto SiGe/Si superlayers/Si substrates using a production-compatible reduced pressure-chemical vapor deposition system. The thick Ge layers grown using germane and a low-temperature/high-temperature approach are in a tensile-strain configuration. X-ray-diffraction measurements showed that the Ge layer possesses a litter higher tensile strain as large as 5% than L/H conventional approach, which is generated during the cooling from the high growth temperature due to the thermal-expansion mismatch between Ge and Si. In addition, we also exhibited the variations of Ge layers with changes of the superlayers. The process described in this letter for making high-quality Ge is uncomplicated and can be easily integrated with standard Si processes.
III-Sb MOSFETS : Opportunities and Challenges
Authors: Nainani Aneesh , Yuan Ze , Kumar Archana , Bennett Brian R. , Boos J. Brad , Saraswat Krishna C.
Published: April 2012

Antimony (Sb) based compound semiconductor materials have the highest electron and hole mobilities amongst all compound semiconductor materials. Transistors using Sbchannel deliver much higher performance at significantly lower power. As compared to InxGa1-xAs/InP system Sb's have higher band offsets for a heterostructure design and higher mobility for holes. Sb-based channel materials are the only candidates, which can offer a complementary technology outperforming silicon in a single channel material. A CMOS technology in a single channel material is more advantageous for integration vs. one which requires two different materials with different lattice constants for the nMOS and pMOS. Besides this the ~6.1Aå InAs-GaSb-AlSb lattice system offsets rich possibilities for band engineering as shown in Figure. 1, which can be applied to other applications such as tunnel FETs as well.
Passivation Challenges with Ge and III/V Devices
Authors: Sioncke Sonja , Lin Dennis , Nyns Laura , Delabie Annelies , Thean Aaron , Horiguchi Naoto , Struyf Herbert , De-Gendt S. , Caymax Matty
Published: April 2012

Ge and III/V materials are investigated as high mobility channel materials for devices beyond the 14 nm technology node. Passivation of the interface is a prerequisite as dangling bond states trap charges and reduce the mobility. Passivation of the Ge/high-κ interface can be done by using GeO2 as a passivation layer. However, large thicknesses are needed to keep a low defect density. Introduction of S at the interface can solve this issue. Passivation of III/V materials is still a major problem. Oxidation of the III-As surface leads to stress at the surface creating As-As bonds. Oxides can be partially removed by wet treatment or during the ALD deposition. The defects related to As-As bonds cannot be removed by the ALD process. We demonstrate that also for InP, an oxide free interface does not solve the passivation problem.
Investigations on Thermal Stress Relief Mechanism Using Air-Gapped SiO2 Nanotemplates during Epitaxial Growth of Ge on Si and Corresponding Hole Mobility Improvement
Authors: Ghosh Swapnadip , Leonhardt Darin , Han Sang M.
Published: April 2012

We demonstrate the implementation of air-gapped SiO2 nanotemplates embedded in epitaxially grown Ge on Si for relieving stress caused by the thermal expansion coefficient mismatch between Ge and Si. The air-gap is formed around the SiO2 template during growth and eventual coalescence of adjacent Ge islands merging over the template. The stress map obtained from finite element modeling corroborates the experimental observation, suggesting that the thermal stress can be reduced nearly by half. The templates also filter threading dislocations propagating from the underlying Ge-Si interface, reducing the defect density from 9.8×108 to 4.4×107 cm-2 in the demonstration case. We further investigate the influence of threading dislocation density on the effective hole mobility in undoped Ge between substrates grown with the template and without the template. Using the Hall mobility measurements, we have obtained a peak effective hole mobility of 925 cm2/V-s at room temperature for Ge grown with the template, compared to 297 cm2/V-s for Ge grown without the template.
Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Authors: Waldron Niamh , Wang Gang , Nguyen Ngoc D. , Orzali Tommaso , Merckling Clement , Brammertz Guy , Ong Patrick , Winderickx Gillis , Hellings Geert , Eneman Geert , Caymax Matty , Meuris Marc , Horiguchi Naoto , Thean Aaron
Published: April 2012

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 Ω.cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.
Deterministic Assembly of In0.53Ga0.47As p+-i-n+ Nanowire Junctions for Tunnel Transistors
Authors: Kuo Meng-Wei , Li Jie , Liu Huichu , Vallett Aaron , Mohata Dheeraj Kumar , Datta Suman , Mayer Theresa S.
Published: April 2012

Electric-field-assisted deterministic assembly is used to position arrays of p+-i-n+ In0.53Ga0.47As nanowires on a Si substrate for de-vice integration. Forces induced on the solution-suspended wires by a spatially varying, nonuniform electric field determines the po-sition of each wire with respect to lithographic features on the sub-strate. The electrical properties of the sub-50 nm diameter In0.53Ga0.47As junctions with a 100 nm thick unintentionally doped channel were characterized after adding source and drain contacts. The junctions showed clear rectification, with a forward bias ideal-ity factors as low as 1.8, and reverse leakage current as small as 20 pA at a -1 V bias. This represents an important step towards demonstrating an In0.53Ga0.47As-based nanowire tunnel transistor.
New Method to Produce High-Quality Epitaxial Ge on Si Using SiO2-Lined Etch Pits and Epitaxial Lateral Overgrowth for III-V Integration
Authors: Leonhardt Darin , Han Sang M.
Published: April 2012

We have developed a unique method of reducing the threading dislocation density in Ge epitaxially grown on Si. A heteroepitaxial layer of Ge is initially grown on Si substrate in which the threading dislocation density is 2.6 x 108 cm-2. The Ge film is etched to produce pits on the surface that correspond to the location of threading dislocations. The Ge surface with etch pits is processed further to produce a 15 nm thick layer of SiO2 within the etch pits, but not on the top planar Ge film surface. Further lateral and selective epitaxial Ge growth results in a Ge film that forms and coalesces over the SiO2 lined etch pits. The SiO2 blocks the threading dislocations from propagating into the subsequent Ge epilayer. Etching the subsequent Ge epilayer reveals a density of 1.7 x 106 cm-2 threading dislocations. This corresponds to a decrease in the overall defect density by a factor of 31 compared to the initial Ge on Si layer. The threading dislocations likely result from shallow etch pits in which SiO2 is inadvertently removed from the pit during one of the processing steps. The dislocations in pits without SiO2 continue to propagate into the subsequent Ge epilayer. Reducing the dislocation density in the initial Ge layer should result in fewer defects in the subsequent Ge layer, making the layer suitable for electronic device fabrication.
Germanium Doping, Contacts, and Thin-Body Structures
Authors: Duffy Ray , Shayesteh Maryam
Published: April 2012

Interest in Ge has risen sharply in since the turn of the century, as it has enabled applications ranging from field-effect-transistors, solar cells, photonics, and sensors. In this paper the state-of-the-art will be reviewed in the areas of (i) dopant behavior and ultrashallow junction performance metrics, (ii) thin-body structure formation, and (iii) contact methodologies in Ge.
Multiple-Gate In0.53Ga0.47As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contacts
Authors: Zhang Xingui , Guo Hua Xin , Gong Xiao , Guo Cheng , Yeo Yee-Chia
Published: April 2012

Sub-100 nm multiple-gate In0.53Ga0.47As channel n-MOSFETs with self-aligned Ni-InGaAs contacts were demonstrated for the first time. With self-aligned Ni-InGaAs contacts formed on in-situ doped n++ In0.53Ga0.47As source and drain, the device exhibits low series resistance of 364 Ω⋅μm. The multiple-gate device with 50 nm channel length has a drive current of more than 411 μA/μm at VD = 0.7 V and VG = 0.7 V. The device also shows a peak extrinsic transconductance Gm of 590 μS/μm at VD = 0.5 V.
(Invited) Experimental Determination of the Electronic Density of States for Graphene Oxide
Authors: Alphenaar Bruce W. , Bansal Tanesh , Mohite Aditya D. , Shah Hemant M. , Galande Charudatta , Srivastava Anchal , Jasinski Jacek B. , Ajayan Pulickel M.
Published: April 2012

Capacitive photocurrent spectroscopy is used to probe the density of states of graphene, graphene-oxide, and reduced graphene-oxide. Three peaks in the density of states are observed near the Dirac point whose intensities scale with the oxygen coverage. Transitions between these peaks and the graphene π/π* states correlate with the luminescence spectra reported for graphene-oxide.
(Invited) Nanocontact Epitaxy of Thin Films on Si Substrates Using Nanodot Seeds Fabricated by Ultrathin SiO2 Film Technique
Authors: Nakamura Yoshiaki , Ichikawa Masakazu
Published: April 2012

We developed a new technique for heteroepitaxial growth on Si substrates, we call nanocontact epitaxy. In this technique, elastically strain-relaxed nanodots (NDs) formed by ultrathin SiO2 film technique are used as seed crystals for film growth. Using this technique, we grew high quality Ge thin films on Si(001) substrates where there is 4% lattice mismatch. Furthermore, we succeeded in the epitaxial growth of high quality GaSb thin films on Si(001) substrates with large lattice mismatch (~12%). We observed strong photoluminescence from these thin films. This demonstrated the nanocontact epitaxy is promising as a new heteroepitaxial growth technique applicable to large lattice mismatch system.
(Invited) Mechanism of Vfb Shift in HfO2 Gate Stack by Al Diffusion from (TaC)1-xAlx Gate Electrode
Authors: Nabatame Toshihide , Kimura Masayuki , Yamada Hiroyuki , Ohi Akihiko , Ohishi Tomoji , Chikyow T.
Published: April 2012

We investigate Vfb behavior of (TaC)1-xAlx gated HfO2 MOS capacitors as a function of post metal annealing (PMA) temperature. The positive Vfb shift appears in PMA temperature at above 700 °C, while the negative Vfb shift occurs at below 600 °C. At below 600 °C, the effective work function (φm,eff) of gate electrode becomes lower by increasing Al atoms with a low work function. We found that the positive Vfb shift occurs dominantly due to the φm,eff change induced by Al diffusion from gate electrode at 700 and 800 °C. At above 900 °C, Al atoms reach to the HfO2/SiO2 interface and form the AlOx layers, and results in positive Vfb shift due to the bottom interface dipole. We can divide into two components of φm,eff change of gate electrode and the bottom interface dipole due to AlOx layer as a function of PMA temperature.
(Invited) Scanning Probe Analysis of Dielectrics on High Mobility Substrates
Authors: Olsen Sarah H. , Kapoor Raman , Bull Steve J.
Published: April 2012

In this work we employ electrical scanning probe techniques to evaluate on a nanoscale the influence of semiconductor surface morphology on the electrical properties of dielectrics. Gate leakage, reliability and oxide thickness uniformity are assessed by conductive atomic force microscopy (C-AFM). Interface traps are analyzed by scanning capacitance microscopy (SCM). A correlation between nanoscale and macroscale trends is established following reverse processing of the devices. The impact of surface morphology on localized dielectric properties is evaluated by studying MOSFETs having the same silicon channel strain but different dielectric/substrate interface roughness. The correlation between surface morphology, leakage and SCM signal suggests that for dielectrics on high mobility substrates prone to surface roughening, the morphology as well as the dielectric itself play a role in the final dielectric quality. Optimized epitaxial growth will therefore enable improved device performance, reliability and variability. The results have implications for all technologies which employ relaxed SiGe templates.
Effects of the Interfacial Layer on Electrical Properties of TiO2-based High-k Dielectric Composite Films
Authors: Kim Chang Eun , Yun Ilgu
Published: April 2012

Effects of interfacial layer on the electrical properties of TiO2 based dielectric thin films prepared by atomic layer deposition are investigated. It was confirmed from XPS data that the Hf-silicate and La-silicate interfacial layers including SiOx were formed in the interface of the HfO2/TiO2/Al2O3 (HTA) and La2O3/TiO2/Al2O3 (LTA) gate stack structures, respectively. In addition, the dielectric constants and leakage currents of HTA and LTA structures were affected by the formation of Hf-silicate and La-silicate layer in the interface and crystallization of TiO2 thin film, respectively. It was also found that the LTA thin film annealed at 600 °C showed the low equivalent oxide thickness of 0.91 nm and the low leakage current of 4.16×10-6 A/cm2 at 4 MV/cm.
(Invited) In Situ XPS Study on ALD (Atomic Layer Deposition) of High-k Dielectrics: La2O3 Using La-Formidinate and Ozone
Authors: Kim Jiyoung , Kim Hyun-Chul , Wallace Robert M. , Park TaeJoo
Published: April 2012

The detailed growth behavior of lanthanum oxide (La2O3) on a silicon substrate during atomic layer deposition (ALD) is investigated by in-situ, x-ray photoelectron spectroscopy (XPS) following individual ALD pulses of tris(N,N'-diisopropyl-formamidinato) lanthanum [La(iPrfAMD)3] and highly concentrated ozone (~390 g/m3). At the initial growth stage, ozone oxidized the La-ligand as well as the silicon substrate. During oxidation of silicon substrate, a noticeable amount of silicon atoms diffused into growing La2O3 film, resulting in Si-rich and La-rich La-silicates showing composition gradient of La/Si at the deposition temperature of 250 oC. The amount of La-silicate after third ALD cycle reached more than 50 % of that generated by 30 cycles. As the thickness of the film increased with sequential ALD cycles, the substrate oxidation as well as the out-diffusion of Si atoms becomes a negligible quantity, and the pure La2O3 film starts growing leaving La-silicate layers at the interface.
(Invited) Admittance Spectroscopy of Si/LaLuO3 and Si/GdSiO MOS Structures
Authors: Ducroquet Frederique , Engström Olof , Gottlob Heinrich D. , Lopes Joao Marcelo J. , Schubert Jürgen
Published: April 2012

Interface states at the gate oxide/channel of metal oxide semiconductor (MOS) transistors generally result in detrimental effects on the device performance which need to be considered for the new generations of high-k dielectrics. In this paper, the admittance of Gadolinium silicate (GdSiO) and Lanthanum Lutetium oxide (LaLuO3) MOS capacitors were investigated as a function of the signal frequency, temperature and gate voltage. The Arrhenius plots of the peak pulsations extracted from the conductance spectra have been discussed on the bases of simulated data taking into account a distribution of the trap energy levels and a thermally enhanced capture cross-section. The consequences of a peaked interface state distribution on the evolution of activation energies are shown to lead to Arrhenius plots following the Meyer-Neldel Rule.
Impact of Si Diffusion Barrier Layer Formed on TiN Surface by In Situ Oxygen Treatment Process for Advanced Gate-First Metal/High-k Stacks
Authors: Kitano Naomu , Chikaraishi Keisuke , Arimura Hiroaki , Hosoi Takuji , Shimura Takayoshi , Seino Takuya , Watanabe Heiji , Nakagawa Takashi
Published: April 2012

We investigated the formation of Si barrier layer by an in-situ oxygen treatment process of TiN electrode surface before poly-Si deposition. The Si depth profile after post deposition annealing (PDA) showed that no Si diffused into oxidized stacks due to the formation of TiON layers as a Si-diffusion barrier. Moreover, a high effective work function (EWF) of 4.94 eV was obtained from the oxidized stack even after PDA at 1000oC. However, we observed significant growth of interfacial SiO2 after high temperature annealing. These results indicate a trade-off relationship between EWF control and equivalent oxide thickness (EOT) scaling, and imply that an additional method for EWF modulation is required for scaled high-k devices.
A New Mechanism of Symmetry of Current-Voltage Characteristics for High-k Dielectric Capacitor Structures
Authors: Lau Wai Shing
Published: April 2012

Historically, there has been a controversy regarding whether the leakage current versus voltage (I-V) relationship is governed by the Schottky mechanism or by the Poole-Frenkel (P-F) mechanism for several decades. For the P-F mechanism, the I-V characteristics is expected to be symmetrical. In this paper, the author points out that there is an extra mechanism for symmetrical I-V characteristics.
Improvement on Interface Quality and Reliability Properties of HfAlOx MIS Capacitor with Dual Plasma Treatment
Authors: Chang Kow-Ming , Chang Ting-Chia , Chang Po-Chun , Huang Bo-Wen , Wu Chien-Hung , Deng I-Chung
Published: April 2012

HfO2 is considered a promising gate dielectric material for sub-45 nm CMOS technology. It has been reported that incorporate Al into HfO2 forming Hf aluminates in order to increase the crystallization temperature. However, the growth of the low-k interfacial layer at high-k/Si interface during high-k dielectric deposition would result in reliability degradation. Recently, incorporating nitrogen into HfAlOx gate dielectrics has beneficial effect on reliability performance. In addition, fluorine incorporation into high-k dielectrics also could have several improvements. In this study, dual plasma (CF4 pre-treatment and N2 post-treatment) was performed on HfAlOx MIS capacitor in order to improve interface quality and the reliability properties. According to our experimental results, dual plasma treatment could improve interface quality and enhance reliability properties of HfAlOx thin films.
(Invited) Impact of Thermal Stability of Isolation Liner on the Electrical Characteristics of TSVs
Authors: Okoro Chukwudi , Afzal Annas , Kandel Binayak , Obeng Yaw S.
Published: April 2012

This study is focused on understanding the effect of thermal cycling on the signal integrity characteristics of TSV isolation liner (SiO2). The use of radio frequency (RF) signals is found to be a good metrology tool for the detection of discontinuities in the SiO2 isolation liner. Signal losses are found to scale with the attained number of thermal cycles. Atomic force microscopy (AFM) analysis revealed that void formation and growth in the SiO2 isolation liner is the root cause for this observed trend. Therefore the life time of TSVs will be significantly affected by the SiO2 isolation liner, thus, their understanding, engineering and optimization will be essential for prolonged high performance TSVs.
(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors
Authors: Eneman Geert , Witters Liesbeth , Collaert Nadine , Mitard Jerome , Hellings Geert , Yamaguchi Shinpei , De Keersgieter An , Hikavyy Andriy , Vincent Benjamin , Favia Paola , Bender Hugo , Veloso Anabela , Chiarella Thomas , Togo Mitsuhiro , Loo Roger , De Meyer Kristin , Mercha Abdelkarim , Horiguchi Naoto , Thean Aaron
Published: April 2012

Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1 yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1 yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.
The Impact of Mechanical Strain on Reliability Issue for PD SOI MOSFETs
Authors: Lo Wen-Hung , Chang Ting-Chang , Dai Chih-Hao , Chung Wan-Lin , Tsai Jyun-Yu , Chen Ching-En , Cheng Osbert , Huang Cheng Tung
Published: April 2012

This work studies the impact of mechanical strain on reliability issue for partial depleted silicon-on-insulator metal-oxide-semiconductor field effect transistors (PD SOI p-MOSFETs), including negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-MOSFETs and n-MOSFETs, respectively. Based on AEI model, the mechanical compressive strain was introduced into the SOI p-MOSFET under NBT stress. It shows the strained FB device exhibits a much less NBTI degradation, since significant accumulation of electron induced by strain-induced band gap narrowing, reducing the EOX during NBT stress. Additionally, the degradation of HCS on SOI n-MOSFETs is also studied. It can be seen that the FB device shows worse degradation than GB device due to FBEs. However, the impact of mechanical strain results more serious degradation on HCS for GB device. Therefore, based on the lucky electron mode, we found that strain-induced band gap narrowing dominates the increase in impact ionization rate, aggravating HCS.
Investigation of Random Telegraph Signal with PD SOI MOSFETs
Authors: Chen Ching-En , Chang Ting-Chang , Lo Hung-Ping , Ho Szu-Han , Lo Wen-Hung , Tseng Tseung-Yuen , Cheng Osbert , Huang Cheng Tung
Published: April 2012

A novel method, called random telegraphy signal (RTS), was constructed to characterize the gate oxide quality and reliability of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With the aggressive scaling of device size, drain current RTS (ID-RTS) become a critical role in carrier transport of MOSFETs. Besides, RTS in gate leakage current (I¬G-RTS) was denoted as the other new method to understand property of gate oxide. Recently, the study of RTS has also been made in MOSFETs with metal gate and high dielectric constant (metal gate/high-k). However, the RTS in partial depleted silicon-on-insulator MOSFETs (PD SOI MOSFETs) has not comprehensively been studied yet. This paper investigates RTS characteristics in PD SOI MOSFETs.
Coexistence of Bipolar and Unipolar Switching in Cu/TaOx/Pt Resistive Devices for Cu and Oxygen Vacancy Nanofilaments
Authors: Liu Tong , Verma Mohini , Kang Yuhong , Orlowski Marius K.
Published: April 2012

A Cu/TaOx/Pt device can be switched between high resistive state and low resistive state based on the formation and rupture of two types of nanofilament: Cu and oxygen vacancy conductive bridges. The Cu nanobridge and oxygen vacancy filament form when high positive and negative forming voltages are applied to the Cu electrode, respectively. The set voltage of oxygen vacancy filament is higher and of opposite polarity than that of Cu filament. Both positive and negative voltages can reset the device by Joules heating. Therefore the device can switch in bipolar and unipolar modes with either conductive filament in separate windows of operation.
Unipolar Resistive Switching Memory Characteristics Using IrOx/Al2O3/SiO2/p-Si MIS Structure
Authors: Banerjee Writam , Maikap Siddheswar , Chen Y.-Y. , Yang J. R.
Published: April 2012

Unipolar resistive switching memory characteristics using high-κ Al2O3 film in an IrOx/Al2O3/SiO2/p-Si metal-insulator-semiconductor (MIS) structure have been investigated. The devices show hysteresis memory window of ~0.9 V with a sweeping gate voltage of +/- 6 V, which proves charge trapping phenomena of the Al2O3 film. A sufficiently large resistance ratio of ~1e3 at a self limited current compliance of 100 uA is obtained, due to the defective Al2O3 film. A large resistance ratio of >1e3 after 10 years of data retention is obtained for future nanoscale nonvolatile memory application.
Forming-Free Resistive Switching Memory Characteristics Using IrOx/GdOx/W Cross-Bar Structure
Authors: Jana Debanjan , Prakash Amit , Maikap Siddheswar
Published: April 2012

Bipolar resistive switching memory characteristics in an IrOx/GdOx/W cross-bar structure have been investigated. The resistive switching mechanism is based on the filament formation/rupture in the GdOx layer which is controlled by oxygen ions migration. The memory device shows good distribution of SET/RESET voltages, long read disturb immunity of >105 times, good data retention with a resistance ratio of >30 at 85oC. This device shows great potential for future nanoscale non-volatile memory application.
Formation of CoSi2/CoSixNy Nanocrystals for Nonvolatile Memory Application
Authors: Huang Jheng-Jie , Chang Ting-Chang , Lu Jin , Chen Shih-Ching , Liu Tzu-Chia , Chen Yu-Ting , Yang Po-Chun , Huang Hui-Chun , Gan Der-Shin , Ho New-Jin , Shi Yi , Sze Simon M.
Published: April 2012

Nonvolatile nanocrystal memories recently have been one of the promising candidates to replace traditional floating gate nonvolatile memory because the discrete nanocrystal as the charge storage media have effectively improved data retention under endurance test for the device scaling down. In this study, CoSi2 nanocrystal surrounded with CoSixNy shell structure was proposed by rapid thermal annealing a nitrogen incorporated CoSi layer, which was deposited by sputtering CoSi target in the mixture gas of Ar+N2 or Ar+NH3, to improve data retention. The structures and elements composition of nanocrystal were analyzed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS), and the electrical characteristics of nanocrystals memories were defined by C-V curves. Because of the extra CoSixNy shell, the proposed memory can exhibit good data retention to 10 years.
Low Work Function between Erbium Silicide and n-type Silicon Controlled by Cap Film Stress
Authors: Tanaka Hiroaki , Teramoto Akinobu , Sugawa Shigetoshi , Ohmi Tadahiro
Published: April 2012

The electrical and physical properties of W capped ErSix on n-type Si(100), Si(111) and Si(551) surfaces are reported. The Schottky barrier heights (SBHs) are not determined by the growth of the ErSix crystal orientations, but are determined by the silicon surface orientations. And the SBHs are changed by the ratio of W capping layer thickness and ErSix thickness. These results are considered that the work function of ErSix can be controlled by the stress during the silicidation. These silicidation reactions are very important to develop the future high current drivability devices using any surface orientation.
Texturing and Tetragonal Phase Stabilization of ALD HfxZr1-xO2 Using a Cyclical Deposition and Annealing Scheme
Authors: Tapily Kandabara , Consiglio Steven , Clark Robert D. , Vasić Relja , Bersch Eric , Jordan-Sweet Jean , Wells Ilyssa , Leusink Gert J. , Diebold Alain C.
Published: April 2012

In order to enhance the dielectric properties of HfO2, the alloying of HfO2 with ZrO2 was studied. HfxZr1-xO2 films with different Hf:Zr ratios were deposited by atomic layer deposition (ALD) combined with a cyclical deposition and annealing scheme (termed DADA) in which an annealing was performed after every 20 ALD cycles. The impact of the ZrO2 addition on the structural properties of the ALD grown films was investigated by grazing incidence in-plane X-ray diffraction and pole figure measurement using synchrotron radiation as well as transmission electron microscopy and X-ray photoelectron spectroscopy. The HfxZr1-xO2 films with x=1 show the presence of monoclinic (-111) fiber texture. As the Zr content increases, stabilization of the tetragonal phase is observed. The pole figure measurements indicate the presence of tetragonal (111) fiber texture for the ALD HfxZr1-xO2 films with higher Zr content grown by DADA in contrast to random orientation in post deposition annealed films.
Electrical Properties of Silicon Nitride Using High Density and Low Plasma Damage PECVD Formed at 400ºC
Authors: Nakao Yukihisa , Teramoto Akinobu , Watanabe Tadashi , Kuroda Rihito , Suwa Tomoyuki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: April 2012

High chemical etching resistance is strongly required for silicon nitride at low temperature such as 400oC or below in order to apply to the gate spacer, the contact etching stop layer, because various new materials which are thermally instable are introduced in order to improve the performance of MISFETs. High HF resistance of silicon nitride at the sidewall has been achieved by the plasma enhanced chemical vapor deposition using microwave excited high density plasma at 400oC. In this work, the electrical properties of those silicon nitride formed with various conditions were investigated for the gate spacer. The trap density that are attributed to the Si dangling bonds decreases as the SiH4 flow rate decreases in this process. The leakage current can be suppressed by decreasing the SiH4 flow rate below 3.0 sccm, because the stoichiometric silicon nitride can be formed in this range of process condition.