TLPS Pastes for Anywhere Embedded Passive Components in Substrates and PCBs
Authors: Shearer Catherine , Legerton Gary 
Published: January 2025

The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Finding space for all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes frees up some real estate. The use of ever smaller passive devices also saves space but reintroduces old issues such as tombstoning. An ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board – like moving items from a desk to a bookshelf – by embedding components into the board.

In a typical PCB, passive components account for 80-95% of the total components and cover over 40% of the surface. Embedding a portion of the resistors and capacitors offers the opportunity to free up substantial topside real estate for added features, or to enable device shrinkage.

Embedding discrete passives at any layer provides better design flexibility and far superior performance to embedded passive layer technologies. The modern availability of very small passive devices also facilitates embedding, as the component thickness have declined along with the x-y dimensions. For instance, a 0201 MLCC has a body thickness of about 0.3mm, which is substantially thicker than a typical prepreg layer (~ 0.06 – 0.150mm), but an 008004 is just 0.125mm thick.

Attaching and electrically interconnecting the discrete passive devices is not a trivial operation. For embedded active devices, interconnection is accomplished with plated microvias. This is a relatively expensive solution for passives and significantly limits the number of embedded-passive layers that can be fabricated.

Passives can be attached to PCB subconstructions (subs) using conventional SMT reflow processing and then subsequently laminating the subs together with relief cut-outs for the component bodies. If solder is used for this operation, the subs need to be completely finished with soldermask in order to prevent the solder from running down the circuit traces. Use of the soldermask is not without risk; however, as the mechanical integrity of the laminated PCB may be compromised by poor adhesion. The use of conductive adhesives rather than solder can eliminate the need for solder mask, but conductive adhesive joints may not be sufficiently thermally robust to withstand subsequent lamination and outer-layer assembly operations.

Transient liquid phase sintering (TLPS) pastes have been successfully used for over two decades in PCB interconnects that are subjected to subsequent solder reflow. TLPS paste sintered during lamination will not remelt in subsequent assembly operations. Often, the PCBs fabricated with TLPS interconnects are for extremely complex, reliability-critical, and relatively niche, applications such as supercomputing and aerospace. The increasing demands from the cloud compute and 5G telecom markets are removing the ‘niche’ categorization from that characterization.

For z-axis interconnect, TLPS paste is installed into via layers and sinters as the prepreg cures in a standard lamination cycle. During lamination of the subassembly cores into a single PCB, the solder particles in the TLPS paste melt, wet the copper particles and form an interconnected metallic network. The metallic network formed has a melting point much higher than the original solder alloy and is therefore stable through subsequent thermal excursions such as lead-free assembly operations. Because the solder particles also wet to the copper circuits, the circuit pads become permanently metallurgically bonded to the metal network of the sintered paste interconnect. Therefore, during lamination, the sintering conductive paste delivers a continuous and robust thermal and electrical conduction path from pad to pad. By design, processing of sintered conductive pastes is done at temperatures compatible with standard printed circuit board materials and common lamination cycle conditions. Once sintered, there are a variety of metallic phases in the metallic network; however, all of the phases present in the sintered paste material are stable in thermal exposures well above the initial process temperature and can thus withstand additional lamination cycles or outer layer assembly. The metal matrix does not remelt, nor is it damaged during lead-free solder reflow.

TLPS pastes provide a low and stable electrical resistivity on the order of 20-30 micron-cm and thermal conductivity comparable to solders. Because the metallurgical joint is contiguous from pad-to-pad, the high bulk thermal and electrical conductivity is not squandered on poor interfacial transfer between the pad and the deposit as it would be in a conventional conductive adhesive. The low bulk and interfacial electrical and thermal resistance also support high current carrying capacity and excellent signal integrity.

In addition to z-axis interconnect in PCBs and substrates, TLPS pastes have also designed to be used as a solder replacement in applications in which remelt would be problematic - for instance, when multiple reflows are required to produce the final product. These solder-replacement TLPS pastes provide an attractive means to attach embedded components using conventional SMT assembly methods. Because TLPS pastes maintain the deposition footprint - even on bare copper - there is no need for soldermask. Also, TLPS paste will not remelt in subsequent lamination or outer-layer assembly operations as solder would.

As many PCB fabricators lack SMT assembly capability, an alternative strategy for embedding passive components would be to use TLPS via layers to interconnect both the components and the circuit layers - eliminating both the need for reflow capability and the use of PTH for layer interconnect. In this method, because the interconnect/embed layers are fabricated in parallel with the PCB sub-cores, components can be embedded on multiple layers in a single lamination. The ability to embed anywhere on multiple layers also provides an opportunity for improved overall signal routing vs. a single embed layer. This method is a logical extension of the long-established z-axis interconnect technology with TLPS paste.

In the TLPS paste-via connect method, cores and discrete components are joined using TLPS paste filled via layers, just as in PCB z-axis interconnect. The difference is that two layers of prepreg are used - one layer with cut outs to accommodate the passive component bodies. The prepregs and coversheets are tacked to both opposing circuit layers to be joined. The passives are inserted into the cutouts prior to the tack heating to temporarily affix them into place. Both of the joining surface are laser ablated to form blind via holes and ‘interconnect’ holes for the TLPS paste to interconnect the passive components to their attachment pads. TLPS paste is filled into the laser-ablated blind holes in the opposing surfaces, the coversheets are removed and the paste solvent evaporated, and the lamination book is made. During lamination, the z-axis interconnections - now double-high - and passive attachment connections are made while the prepreg cures. After lamination, all of the z-axis and passive interconnects are complete.

In this presentation, the results of embedding passives using TLPS pastes - both in the SMT solder-replacement configuration and in the paste-filled microvia configuration - will be analyzed and contrasted.