bluuebunny/crossref_metadata_2025 huggingface dataset:
Comparison of the Thermal Cycling Performance of Thermal Barrier Coatings under Isothermal and Heat Flux Conditions
Authors: Fry A. Tony , Banks Jim P. , Nunn John , Brown Louise.J.
Published: March 2009

Ceramic Thermal Barrier Coatings (TBCs) have been developed for advanced gas turbine
engine components to improve the engine efficiency and reliability. The integrity and reliability of
these coatings is of paramount importance. Accurate prediction of service lifetimes for these
components relies upon many factors, and is not straightforward as knowledge of the service
conditions and accurate input data for modelling are required. The main cause of failure of coatings
is through debonding which develops as a consequence of thermally induced strains between the
metallic bondcoat and the alumina TGO layers due to the differences in the thermal expansion
coefficients of the individual layers. Thermal transients due to the power cycles of turbines will then
cause these fractures to grow between the TGO and the bondcoat. When these fractures reach a
critical size they can grow rapidly and cause the TBC to spall off. Thermal cycling of TBCs is used
therefore to evaluate and rank TBC performance. Within the laboratory this is often conducted
under isothermal conditions. Whilst this test method has performed adequately in the past it does
not fully simulate service conditions. Work has been underway therefore to develop a more
complex test method, which better simulates the service conditions experienced by the TBC. The
approach here employs a gas torch to heat the operating face of the TBC whilst cooling the rear of
the substrate with compressed air, thereby imparting a heat flux on the specimen. The specimen is
then cycled by removing the gas torch and cooling with compressed air on the front and rear faces.
Tests have been conducted on a TBC system consisting of an IN738 substrate with a CN334
bondcoat and EBPVD TBC. Thermal cycling tests have been performed under both isothermal and
heat flux conditions. During the course of the tests the samples were examined non-destructively
using a thermal camera to identify early indications of spallation. This paper reports on the
performance of the flame rig equipment and the results from the exposures on the TBC system.
High Temperature Oxidation and Oxidation-Induced Degradation of Alumina Formers
Authors: Jedlinski Jerzy
Published: March 2009

This paper focuses on a systematic description of the alumina formers oxidation
behaviour by referring to a variety of observables, features and/or processes and their evolution
during the exposure. An attempt is also made to identify the key effects relevant to degradation
process. An output of this approach consists of the ‘Oxidation Routes’ and the ‘Degradation Paths’.
Softwood Degradation after Being Several Thousand Years in Shore Front Mud
Authors: Kettunen Pentti O. , Kettunen Heikki , Sarkkinen Mika , Henttu Päivi , Rissa Kati
Published: March 2009

Two man-made wooden objects, called here a “boat” and an “outrigger”, were found above one another in 2004 and 2006 in Kuusamo, Finland. A layer of shore front mud and turf covered them entirely. With partial excavations, samples were taken for age determination and structural studies from both of the items. As measured by the radiocarbon method with a probability of 95.4 %, the items appear to be from periods 5480 – 5300 CalBC and 5025 – 4770 CalBC for the boat and the outrigger, respectively.
Determination of Ambipolar Lifetime and Epilayer Thickness of 5kV SiC Bipolar Devices by Transient Switching Studies
Authors: Ben Salah Tarek , Risaletto Samien , Raynaud Christophe , Besbes Kamel , Bergogne Dominique , Planson Dominique , Morel Hervé
Published: March 2009

A novel experimental set-up is developed and validated to characterize high voltage diodes in
transient switching mode. Parameters extracted from DMTVCA and OCVD techniques, like
ambipolar lifetime, epilayer thickness and doping level, diode area, are validated in a buck converter
with resistive load. The experimental set-up allows to measure the current and voltage transient
characteristics without noise and influence of high parasitic wiring. Experimental results are
compared with device simulations and a good correlation is found.
Transient Response to High Energy Heavy Ions in 6H-SiC n+p Diodes
Authors: Onoda Shinobu , Ohshima Takeshi , Hirao Toshio , Hishiki Shigeomi , Iwamoto Naoya , Kojima Kazu , Kawano K.
Published: March 2009

Transient currents in 6H-SiC n+p diodes and those in Si PIN diodes are compared, and the
carrier dynamic response to a heavy ion collision is analyzed using Technology Computer Aided
Design (TCAD). In case of 6H-SiC n+p diodes, it is found that the contribution of the
ambipolar-diffusion current to total transient current is extremely weak compared to that in Si PIN
diodes, since plasma disruption is accelerated by the Auger recombination process in the former.
High-Temperature Static and Dynamic Reliability Study of 4H-SiC Vertical-Channel JFETs for High-Power System Applications
Authors: Cheng Lin , Martin P. , Mazzola Michael S. , Sheridan David C. , Kelly R.L. , Bondarenko Volodymyr , Morrison S. , Gray R. , Tian G. , Scofield James D. , Casady Janna R. B. , Casady Jeff B.
Published: March 2009

In this work we report the most recent high-temperature long-term reliability results of
the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A
and B) devices were subjected to different thermal and electrical stresses. One device (Group A)
reached 12,000 hours of continuous switching without a single failure. Four devices in Group A
were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the
specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the
entire duration time. The off-state characteristics were evaluated by high temperature reverse bias
(HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours.
A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for
1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for
all tested devices.
Silicon Carbide Vertical JFET Operating at High Temperature
Authors: Vassilevski Konstantin , Hilton Keith P. , Wright Nicolas G. , Uren Michael J. , Munday A.G. , Nikitina Irina P. , Hydes A.J. , Horsfall Alton B. , Johnson C. Mark
Published: March 2009

Trenched and implanted vertical JFETs (TI-VJFETs) with blocking voltages of 700 V were
fabricated on commercial 4H-SiC epitaxial wafers. Vertical p+-n junctions were formed by
aluminium implantation in sidewalls of strip-like mesa structures. Normally-on 4H-SiC TI-VJFETs
had specific on-state resistance (RO-S ) of 8 mW×cm2 measured at room temperature. These devices
operated reversibly at a current density of 100 A/cm2 whilst placed on a hot stage at temperature of
500 °C and without any protective atmosphere. The change of RO-S with temperature rising from 20
to 500 °C followed a power law (~ T 2.4) which is close to the temperature dependence of electron
mobility in 4H-SiC.
Investigation into Short-Circuit Ruggedness of 1.2 kV 4H-SiC MOSFETs
Authors: Nakao Yukiyasu , Watanabe Shoyu , Miura Naruhisa , Imaizumi Masayuki , Oomori Tatsuo
Published: March 2009

The shout-circuit ruggedness of prototype 1.2kV SiC MOSFETs has been investigated.
The short-circuit measurements were carried out at 25 °C and 125 °C with a dc bus voltage of 800 V
and an on/off state gate voltage of +20/-10 V. The small difference in tfail between 25 °C and 125 °C
indicates that the destructive breakdown occurs at temperatures much higher than 125 °C. The
temperature at destructive breakdown estimated from the Wunsch-Bell formula is about 1400 °C. At
such high temperatures, intrinsic carriers are increased markedly and generated heat leads to the
destructive breakdown. tfail of all the SiC-MOSFETs studied is longer than 10 μs, meaning that the
short-circuit ruggedness satisfies system requirements. These results show that the SiC-MOSFETs
are promising for power electronics applications.
On-State and Switching Performance of High-Voltage 15 – 20 kV 4H-SiC DMOSFETs and IGBTs
Authors: Tamaki Tomohiro , Walden Ginger G. , Sui Yang , Cooper James A.
Published: March 2009

We compare the on-state and switching performance of high-voltage 4H-SiC n-channel
DMOSFETs and p-channel IGBTs within a three-dimensional parameter space defined by blocking
voltage, switching frequency, and current density. We determine the maximum current density each
device can carry at a given switching frequency, such that the total power dissipation is 300 W/cm2.
The IGBT current depends strongly on lifetime in the NPT buffer layer, and only weakly on lifetime in
the drift layer. The MOSFET current is essentially independent of frequency.
Temperature and Time Dependent Threshold Voltage Instability in 4H-SiC Power DMOSFET Devices
Authors: Tadjer Marko J. , Hobart Karl D. , Imhoff Eugene A. , Kub Fritz J.
Published: March 2009

Threshold voltage (Vth) was measured on 4H-SiC power DMOSFET devices as a function
of temperature, gate stress, and gate stress time. Vth varied linearly with gate stress and gate stress
time and inversely with temperature. This instability is explained with the trapping rate of channel
electrons at or near the SiO2-SiC interface. Since the measurement scale of Vth is large in this case (it
takes approx. 20 s to measure Vth), it is assumed that fast interface traps, i.e., ones closer to the
interface, are already filled and do not contribute to the shift in Vth. Comparison with theoretical
calculations shows the rate of carrier detrapping becomes higher with temperature and as a result the
measured value of Vth approaches the theoretical value.
1200 V 4H-SiC BJTs with a Common Emitter Current Gain of 60 and Low On-Resistance
Authors: Lee Hyung Seok , Domeij Martin , Zetterling Carl Mikael , Ghandi Reza , Östling Mikael , Allerstam Fredrik , Sveinbjörnsson E.Ö.
Published: March 2009

This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage
(BVCEO) of 1200 V, a maximum current gain (β) of 60 and the low on-resistance (Rsp_on)of 5.2
mΩcm2. The high gain is attributed to an improved surface passivation SiO2 layer which was grown in
N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient
show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due
to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm × 1.8 mm
showed a current gain of 53 in pulsed mode and a forward voltage drop of VCE=2V at IC=15 A
(JC=460 A/cm2).
1600 V, 5.1 mΩ●cm2 4H-SiC BJT with a High Current Gain of β=70
Authors: Zhang Jian Hui , Alexandrov Peter , Zhao Jian Hui
Published: March 2009

This paper reports a newly achieved best result on the common emitter current gain of
4H-SiC high power bipolar junction transistors (BJTs). A fabricated 1600 V – 15 A 4H-SiC power
BJT with an active area of 1.7 mm2 shows a high DC current gain (b) of 70, when it conducts 9.8 A
collector current at a base current of only 140 mA. The maximum AC current gain (DIC/DIB) is up to
78. This high performance BJT has an open base collector-to-emitter blocking voltage (VCEO) of over
1674 V with a leakage current of 1.6 μA, and a specific on-resistance (RSP-ON) of 5.1 mW.cm2 when it
conducts 7.0 A (412 A/cm2) at a forward voltage drop of VCE = 2.1 V. A large area 4H-SiC BJT with
a footprint of 4.1 mm x 4.1 mm has also shown a DC current gain over 50. These high-gain,
high-voltage and high-current 4H-SiC BJTs further support a promising future for 4H-SiC BJT
applications.
4H-SiC Bipolar Junction Transistors with a Current Gain of 108
Authors: Zhang Q. Jon , Jonas Charlotte , Burk Albert A. , Capell Craig , Young Jonathan , Callanan Robert , Agarwal Anant K. , Palmour John W. , Geil Bruce , Scozzie Charles
Published: March 2009

4H-SiC BJTs with a common emitter current gain (b) of 108 at 25°C have been
demonstrated. The high current gain was accomplished by using a base as thin as 0.25 μm. The
current gain decreases at high temperatures but is still greater than 40 at 300°C. The device
demonstrates an open emitter breakdown voltage (BVCBO) of 1150 V, and an open base breakdown
voltage (BVCEO) of 250 V. A low specific on-resistance of 3.6 mW-cm2 at 25°C was achieved.
The BJTs have shown blocking capabilities over a wide range of operating temperatures up to
300°C.
Behavior of Stacking Faults in TEDREC Phenomena for 4.5 kV SiCGT
Authors: Nakayama Koji , Sugawara Yoshitaka , Miyanagi Yoichi , Asano Katsunori , Ogata Shuuji , Okada Shinichi , Izumi Toru , Tanaka Atsushi
Published: March 2009

The behavior of stacking faults with regard to Vf degradations and TEDREC phenomena
for 4.5 kV SiCGT have been investigated through the use of light emission images. Stacking faults,
which cause Vf degradations, are expanded when current densities are increased. A novel phenomena
of Vf degradation reduction, TEDREC phenomena, was found, which can reduce degradation by
increasing operating temperature. It was observed for the first time that stacking faults become
inactive by elevating temperatures to more than 150 oC in spite of existing stacking faults, which is a
factor that contributes to TEDREC phenomena.
3D Thermal Stress Model for SiC Power Modules
Authors: Tsao Bang Hung , Lawson Jacob , Scofield James D. , Laing Clinton , Brown Jeffery
Published: March 2009

Three dimensional models of both single-chip and multiple-chip power sub-modules were
generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes,
heat transfer coefficients, and device placement configurations on temperature and thermal stress
contours. Alumina, aluminum-nitride, and CVD diamond were compared as substrates. Heat fluxes
of 100 to 500 watts/cm2 resulted in SiC device junction temperatures in the range of 350 to 650 K.
The predicted maximum operating temperature for a chip, to which 300 watts/cm2 of heat flux was
applied, would be 239°C (512 K). In the applied heat flux range, the minimum and maximum Von
Mises stress of a simulated single SiC device sub-module was between 1.2 MPa to 2.4 GPa. The
maximum shear stress at 300 watts/cm2 was predicted to be 243 MPa. Both the maximum and
minimum chip temperature decreased with increasing heat transfer coefficient from 25 to 2500
watts/m2 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 250 watts/m2
K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 400 K.
If consistent with simulation results, CVD diamond integrated substrates should be superior to those
comprised of AlN or Al2O3. Asymmetric device placement in the multi-chip module proved more
effective at avoiding potential hot spots than the symmetric configuration.
600V GaN Schottky Barrier Power Devices for High Volume and Low Cost Applications
Authors: Liu Lin Lin , Zhu Ting Gang , Murphy Michael , Pabisz Marek , Pophristic Milan , Peres Boris , Hierl Tom
Published: March 2009

The first commercially viable high voltage (>600V) gallium nitride (GaN) Schottky barrier
devices are reported. Though GaN does not have any “micropipe” defects, which commonly exists in
SiC material, defects like dislocations due to lattice mismatch hamper the material development of
GaN high power devices. Improvements in the nitride epitaxial film growth have led to significant
reduction of conductive dislocations. Conductive Atomic Force Microscope (CAFM) analysis of
conductive dislocations shows only on the order of 103 cm-2 density of conductive dislocations, which
are believed to be responsible for the undesired leakage current. GaN diodes compare to SiC or Si
devices demonstrate a significant advantage in the thermal resistance. The insulating properties of
Sapphire substrates allow fabrication of the devices in TO220 packages with insulating frame and
thermal resistance better than 1.8°C/W compare to 3°C/W of SiC or Si devices with insulating frame.
Performance of GaN, SiC and Si devices in the switch mode power supplies is compared.
Growth and Characterization of AlGaN/GaN HEMT Structures on 3C-SiC/Si(111) Templates
Authors: Cordier Yvon , Portail Marc , Chenot Sébastien , Tottereau Olivier , Zielinski Marcin , Chassagne Thierry
Published: March 2009

Cubic SiC/Si (111) template is an interesting alternative for growing GaN on silicon. As
compared with silicon, this substrate allows reducing the stress in GaN films due to both lower lattice
and thermal expansion coefficient mismatch, and can provide better heat dissipation. In this work, we
first developed the epitaxial growth of 3C-SiC films on 50mm Si(111) substrates using chemical
vapor deposition. AlGaN/GaN high electron mobility transistors were grown by molecular beam
epitaxy on these films. Both the structural quality and the electrical behavior of these structures show
the feasibility of this approach.
Material Properties of GaN Films Grown on SiC/SOI Substrate
Authors: Feng Zhe Chuan , Tran C. , Ferguson Ian T. , Zhao J.H.
Published: March 2009

Material properties of GaN thin films grown on 3C-SiC/semiconductor-on-insulator (SOI)
substrate, by metalorganic chemical vapor deposition technology, are studied by X-ray diffraction,
photoluminescence and Raman scattering, with data indicating the high quality of GaN films. Our
results have shown that SiC/SOI structures obtained by carbonization have the potential to serve as
useful substrates for GaN growth.
In Situ Boron and Aluminum Doping and Their Memory Effects in 4H-SiC Homoepitaxial Layers Grown by Hot-Wall LPCVD
Authors: Sun Guo Sheng , Zhao Yong Mei , Wang Liang , Wang Lei , Zhao Wan Shun , Liu Xing Fang , Ji Gang , Zeng Yi Ping
Published: March 2009

The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52×1020 cm-3 with Hall mobility of about 1 cm2/Vs and resistivity of 1.6~2.2×10-2 Wcm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Wcm for resistivity, 5.3×1018 cm-3 for hole carrier concentration, and 7 cm2/Vs for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.
Growth Mechanism of 3C-SiC Heteroepitaxial Layers on α-SiC by VLS
Authors: Ferro Gabriel , Soueidan Maher , Kim-Hak Olivier , Dazord Jacques , Cauwet François , Nsouli Bilal
Published: March 2009

We report on the heteroepitaxial growth of 3C-SiC layers by Vapor-Liquid-Solid (VLS) mechanism on Si face 6H-SiC substrates, on-axis and 3.5° off. The Si-Ge melts, which Si content was varied from 10 to 50 at%, were fed by 3 sccm of propane. The growth temperature was varied from 1200 to 1600°C. It was found that 3C-SiC layers (either twinned or twinned free) form at low temperature while homoepitaxy is achieved at high temperature. The proposed growth mechanism involves the initial formation of 3C islands during the heating ramp (below 1200°C) and the dissolution of these islands when temperature increases. Geometrical aspects, such as the step density at the surface and the vertical component of the growth, are also considered to explain the difference observed between the on and off axis substrates.
Growth Kinetics of 3C-SiC on α-SiC by VLS
Authors: Soueidan Maher , Kim-Hak Olivier , Ferro Gabriel , Habka Nada , Nsouli Bilal
Published: March 2009

The growth kinetics of 3C-SiC heteroepitaxial layers on α-SiC substrates by Vapour-Liquid-Solid (VLS) mechanism in Ge-Si melts was investigated. Various parameters were studied such as temperature, melt composition, propane flux and substrate nature (polytype, polarity and misorientation). It was found that the growth rate increases with increasing temperature, propane flux, Si content of the melt and misorientation of the substrate. The calculated activation energy (from 4.7 to 6.6 kcal/mole depending on the substrate type) is very small suggesting that the limiting process is the diffusion of the dissolved carbon inside the melt. The carbon solubility inside the melt mainly affects the carbon dissolution kinetics from the gas phase. The results also suggest that surface effects are important through the layer polarity and crystalline quality.
Bulk SiC Crystal Growth at Constant Growth Rate Utilizing a New Design of Resistive Furnace
Authors: Tupitsyn Eugene Y. , Galyukov Alexander , Bogdanov Maxim V. , Kulik Alexey , Ramm Mark S. , Makarov Yuri , Sudarshan Tangali S.
Published: March 2009

In this work the problem of growth rate decaying during growth is considered. A new design and growth profiles are suggested in order to reduce deviations of growth parameters during the process of growth.
Studies of the Distribution of Elementary Threading Screw Dislocations in 4H Silicon Carbide Wafer
Authors: Chen Yi , Zhang Ning , Huang Xian Rong , Black David R. , Dudley Michael
Published: March 2009

The density and sense distribution of elementary threading screw dislocations in a
physical vapor transport grown 3-inch 4H silicon carbide wafer have been studied. The density of
TSDs ranges between 1.6×103/cm2 and 7.1×103/cm2 and the lowest density is observed at positions
approximately half radius off the wafer center. The dislocation sense of elementary threading screw
dislocations can be readily revealed by the asymmetric contrast of their images in grazing-incidence
x-ray topographs using pyramidal plane reflections. The circumferential and radial distributions of
the sense of elementary threading screw dislocations have been studied and no clear trends are
observed in either distribution.
Differences in Emission Spectra of Dislocations in 4H-SiC Epitaxial Layers
Authors: Liu Kendrick X. , Zhang X. , Stahlbush Robert E. , Skowronski Marek , Caldwell Joshua D.
Published: March 2009

Material defects such as Si-core and C-core partial dislocations (PDs) and threading screw
dislocations (TSDs) and threading edge dislocations (TEDs) are being investigated for their
contributions to device performances in 4H-SiC. Non-destructive electroluminescence and
photoluminescence techniques can be powerful tools for examining these dislocations. In this report,
these techniques were used to reveal the different spectral characteristics for the mentioned
dislocations. At higher injection levels, both the Si-core and C-core PDs possessed a spectral peak at
700 nm. However, at lower injection levels, the spectral peak for the Si-core PD remained at 700 nm
while the peak for the C-core moved to longer wavelengths. For the threading dislocations, TSDs
possessed a peak between 800 and 850 nm while the TEDs possessed a peak at 600 nm independent of
the injection levels.
Expansion of Stacking Faults by Electron-Beam Irradiation in 4H-SiC Diode Structure
Authors: Sugie Ryuichi , Yoshikawa Masanobu , Harada Shin , Namikawa Yasuo
Published: March 2009

The influence of electron-beam irradiation on defects in 4H-SiC diode structures was
investigated by cathodoluminescence (CL) microscopy and spectroscopy. In addition to threading
edge and screw dislocations, two types of stacking faults (SFs) were characterized by their emission
energy, geometric shape, and the sensitivity of electron-beam irradiation. The SFs at λ = 425 nm
(2.92 eV) expand from the surface of basal plane dislocation with line direction [11-20] and change
their geometric shape by electron-beam irradiation. The SFs at λ = 471 nm (2.63 eV) are only slightly
influenced by electron-beam irradiation. The former corresponds to the Shockley-type SFs
previously observed in the degraded p-i-n diodes, and the latter to in-grown SFs with 8H structure.
The panchromatic CL images constructed by the sum of monochromatic CL images suggest that there
are nonradiative recombination centers in the vicinity of Shockley-type SFs. The nucleation sites and
the driving force for SF expansion are discussed.
Defect Level of the Carbon Vacancy-Carbon Antisite Pair Center in SI 4H SiC
Authors: Zvanut Mary Ellen , Ngetich G. , Chung H.J. , Polyakov A.Y. , Skowronski Marek , Garces N.Y. , Glaser E.R.
Published: March 2009

The understanding of the structure and associated defect level of point defects in SiC is
important because the material is to be used both as a semiconductor and semi-insulator.
Production of the latter is achieved by compensation of unavoidable impurities using defects that
require more energy for ionization than the unintentional donors or acceptors. The purpose of the
present work is to measure the defect energy level of one center in high resistivity 4H SiC using
photo-induced electron paramagnetic resonance (photo-EPR). The center is identified as SI-5, an
EPR signal that others have attributed to the negative charge state of the carbon vacancy-carbon
antisite pair, −
C Si V C . Samples containing this defect exhibit two different photo thresholds, which
depend on the resistivity activation energy, Ea. For samples with Ea less than 0.8 eV, a photothreshold
at 0.75+/- 0.05 eV is observed, but for those with Ea greater than 0.8 eV, the threshold is
between 2 and 2.5 eV. Previous work focused on the former case. Here, the SiC substrates with the
larger Ea are emphasized, showing that the photo-threshold likely measures the neutral to negative
defect level, − / 0
C Si V C .
Deep Levels Responsible for Semi-Insulating Behavior in Vanadium-Doped 4H-SiC Substrates
Authors: Son Nguyen Tien , Carlsson Patrick , Gällström Andreas , Magnusson Björn , Janzén Erik
Published: March 2009

Semi-insulating (SI) 4H-SiC substrates doped with vanadium (V) in the range 5.5×1015
–1.1×1017 cm–3 were studied by electron paramagnetic resonance. We show that only in heavily
V-doped 4H-SiC vanadium is responsible for the SI behavior, whereas in moderate V-doped
substrates with the V concentration comparable or slightly higher than that of the shallow N donor or
B acceptor, the SI properties are thermally unstable and determined by intrinsic defects. The results
show that the commonly observed thermal activation energy Ea~1.1 eV in V-doped 4H-SiC, which
was previously assigned to the single acceptor V4+/3+ level, may be related to deep levels of the carbon
vacancy. Carrier compensation processes involving deep levels of V and intrinsic defects are
discussed and possible thermal activation energies are suggested.
Search for Hydrogen Related Defects in p-Type 6H and 4H-SiC
Authors: Alfieri Giovanni , Kimoto Tsunenobu
Published: March 2009

Al-doped 4H and 6H epitaxial layers have been implanted with 200 keV hydrogen or
irradiated with 1 MeV electrons. Heat treatments have been carried out up to 1000 °C and electrical
characterization, by means of deep level transient spectroscopy (DLTS), has been performed after
every annealing treatment in the 100-750 K temperature range. We have detected several deep
levels and the possible involvement of hydrogen in the microscopic structure of these defects is
discussed in the light of their thermal stability and previous results found in the literature. All the
detected defects, except for a level located at 0.55 eV above the valence band (Ev), do not display
any electric field dependence of their emission time constant.
The Formation and Annealing of Carbon Interstitial-Related Complexes in Electron-, Proton- and Helium Irradiated 4H SiC
Authors: Steeds John W.
Published: March 2009

Local vibrational mode energies of optical centres, obtained by low-temperature
photoluminescence experiments, are compared with the results of published local density
approximation calculations to arrive at atomic models for the carbon interstitial-related defects
responsible for the light emission.
Ionization Energies of Phosphorus Donors in 6H-SiC
Authors: Schmid Frank , Semmelroth Kurt , Krieger M. , Weber Heiko B. , Pensl Gerhard , Haller Eugene E.
Published: March 2009

6H-SiC was doped with phosphorus (P) donors by neutron transmutation. IR
transmission spectra were taken in the temperature range from 6 K to 300 K. A great number of
absorption lines is observed at temperatures below 140 K; these lines are attributed to transitions of
the donor electron between ground states and bound excited states of P-related donors. Based on
Faulkner's theory, three series of effective-mass-like states (P1, P2, P3) could be identified. The
corresponding ground state energies are: E(P1) = EC - 91.5 meV, E(P2) = EC - 81.8 meV,
E(P3) = EC - 73.5 meV.
Enhanced Annealing of the Main Lifetime Limiting Defect in Thick 4H-SiC Layers
Authors: Storasta L. , Miyazawa Tetsuya , Tsuchida Hidekazu
Published: March 2009

We have studied annealing of the main lifetime limiting defect Z1/2 in thick 4H-SiC
epilayers by the application of carbon-implantation/annealing method. Examination of different
implantation doses and annealing temperatures showed that finding the optimum conditions is crucial
for obtaining carrier trap concentration below 1011 cm-3 in the whole 100 μm epilayer. The carrier
lifetime increased from under 200 ns to over 1 μs at room temperature in the samples prepared by
optimized carbon-implantation/annealing technique. Fabrication of pin diodes from the improved
thick 4H-SiC epilayers confirmed the enhanced conductivity modulation and suitability of this
technique for high-voltage bipolar SiC devices.
Computational Evaluation of Electrical Conductivity on SiC and the Influence of Crystal Defects
Authors: Tsuboi Hideyuki , Kabasawa Megumi , Ouchi Seika , Sato Miki , Sahnoun Riadh , Koyama Michihisa , Hatakeyama Nozomu , Endou Akira , Takaba Hiromitsu , Kubo Momoj , Del Carpio Carlos A. , Kito Yasuo , Makino Emi , Hosokawa Norikazu , Hasegawa Jun , Onda Shoichi , Miyamoto Akira
Published: March 2009

The main electronic characteristics of silicon carbide (SiC) are its wide energy gap, high
thermal conductivity, and high break down electric field which make of it of one of the most
appropriate materials for power electronic devices. Previously we reported on a new electrical
conductivity evaluation method for nano-scale complex systems based on our original tight-binding
quantum chemical molecular dynamics method. In this work, we report on the application of our
methodology to various SiC polytypes. The electrical conductivity obtained for perfect crystal
models of 3C-, 6H- and 4H-SiC, were equal to 10-20-10-25 S/cm. For the defect including model an
extremely large electrical conductivity (of the order of 102 S/cm) was obtained. Consequently these
results lead to the conclusion that the 3C-, 6H-, and 4H-SiC polytypes with perfect crystals have
insulator properties while the electrical conductivity of the crystal with defect, increases
significantly. This result infers that crystals containing defects easily undergo electric breakdown.
Raman Characteristics of Poly 3C-SiC Thin Films Deposited on AlN Buffer Layer
Authors: Chung Gwiy Sang , Jeong Jun Ho
Published: March 2009

This paper presents the Raman scattering characteristics of poly 3C-SiC thin films
deposited on AlN buffer layer by atmospheric pressure chemical vapor deposition (APCVD) using
hexamethyldisilane (MHDS) and carrier gases (Ar + H2). The Raman spectra of SiC films deposited
on AlN layer of before and after annealings were investigated according to the growth temperature of
3C-SiC. Two strong Raman peaks, which means that poly 3C-SiC admixed with nanoparticle graphite,
were measured in them. The biaxial stress of poly 3C-SiC/AlN was calculated as 896 MPa from the
Raman shifts of 3C-SiC deposited at 1180 °C on AlN of after annealing.
Imaging and Metrology of Silicon Carbide Wafers by Laser-Based Optical Surface Inspection System
Authors: Hatakeyama Tetsuo , Ichinoseki Kyoichi , Higuchi N. , Fukuda Kenji , Arai Kazuo
Published: March 2009

There is a great need for an in-line, high-speed and non-destructive inspection system
capable of evaluating and analyzing the quality of SiC wafers for SiC power devices. We have
examined whether the laser-based optical non-destructive inspection system by KLA-Tencor meets
these requirements. Using this system, incoming inspection of purchased SiC wafers has been
performed. The obtained inspection data show that micropipe density is sufficiently low in a
device-grade wafer, and therefore, micropipes are not the main cause of device failure. The next
challenges for a device-grade SiC wafer are reduction of epitaxial defects and relatively small defects
classified as “particles”.
Theoretical Comparison of 3C-SiC and Si Nanowire FETs in Ballistic Regime
Authors: Rogdakis Konstantinos , Bescond Marc , Bano Edwige , Zekentes Konstantinos
Published: March 2009

3C-SiC is a promising material for high power and high-speed electronic devices as well
as in sensors operating at high temperatures or hostile environments. For these reasons, we solved
self-consistently the Poisson equation within the quantum Non Equilibrium Green Function
Formalism (NEGF) in order to model and compare 3C-SiC and Si nanowire (NW) Field Effect
Transistors (FETs) operating in ballistic regime (at room temperature 300 K). As a general
conclusion of our calculations, Si and SiC NW FETs have almost the same electrical behavior: they
depict the same subthreshold slope and have similar on currents [ION/IOFF (SiC)~81 % ION/IOFF (Si)
in case of 4 nm NW cross section side].
Solution Growth of SiC Crystals in Si-Ti and Si-Ge-Ti Solvents
Authors: Tanaka Ryo , Seki Kazuaki , Komiyama Satoshi , Ujihara Toru , Takeda Yoshikazu
Published: March 2009

We investigated effects of Ti and Ge additions to Si solvent on the volume and the polytype of SiC precipitate in unseeded SiC solution growth. The Ti addition increased the amount of SiC precipitates. Compared to pure Si solvent, the amount of crystal grown in Si-30at%Ti at 1600 °C increased by 5 times. In addition, the Ti addition induced the precipitation of 6H-SiC. Further, the Ge addition to Si-Ti solvent promoted several polytype precipitations (4H and 6H). These results indicate the possibility of polytype control by solvent composition.
Phase Formation and Growth Kinetics of an Interface Layer in Ni/SiC
Authors: Terui Kenichiro , Sekiguchi Atsuko , Yoshizaki Hiroshi , Koike Junichi
Published: March 2009

The reaction behavior and growth kinetic of reaction layer were investigated in the Ni
contact to n-type 6H-SiC. Annealing was performed at temperature in the range between 800 and
1000 °C for 1 to 240 minutes in Ar atmosphere. The interface reaction of Ni/SiC starts with Ni
diffusion into SiC. Ni3Si is initially precipitated and subsequently forms the continuous layer of
d-Ni2Si. Kirkendall voids are formed at the reaction front. Carbon is segregated in the interface layer
of nickel silicide. The growth rate of the interface layer follows a parabolic law, meaning that the
growth rate is controlled by diffusion. The growth occurs in two steps at all examined temperatures: a
fast growth is followed by a slow growth. In addition, in the late stage, the growth rate changes
dramatically below and above 850°C. The observed growth kinetic can be explained by the difference
of Ni diffusivity and the required concentration change for phase transition depending on the phase
composition and structure. The d-Ni2Si is formed in the early stage, while the e-Ni3Si2 and q-Ni2Si are
formed in the late stage below and above 850°C, respectively.
Anisotropic Etching of SiC in the Mixed Gas of Chlorine and Oxygen
Authors: Hatayama Tomoaki , Shimizu T. , Yano Hiroshi , Uraoka Yukiharu , Fuyuki Takashi
Published: March 2009

Anisotropic thermal etching of 4H-SiC {0001} and {11-20} substrates was studied in the
mixed gas of chlorine (Cl2) and oxygen (O2) over 900oC. Etch pits appeared only on the (0001) Si face.
Etching rates depended on the temperature, O2/Cl2 ratio, and an etching direction on the substrate
surfaces. When the mesa structure was formed by the selective etching method, sloped sidewalls were
observed around the periphery of the mesa. The angle of sidewalls depended on the orientation of
substrates.
Scattering Mechanisms in Silicon Carbide MOSFETs with Gate Oxides Fabricated Using Sodium Enhanced Oxidation Technique
Authors: Tilak Vinayak , Matocha Kevin , Dunne Greg , Allerstam Fredrik , Sveinbjörnsson E.Ö.
Published: March 2009

The improvement of the SiC-SiO2 interface has been the main focus of research in SiC
MOSFET technology due to the presence of high density of interface traps (Dit) leading to poor
threshold voltage temperature stability and poor mobility. In SiC MOSFETs with the gate oxide
grown in the presence of sodium, known as sodium enhanced oxidation(SEO), a lower Dit and higher
field effect mobility has been observed [1]. Hall effect measurements were performed from
125°K-225°K on such MOSFET samples. The Hall measurements were made as a function of
temperature for various sheet charge concentrations. The sheet charge density was measured as a
function of gate bias at 225°K and there is very little trapped charge in the sample with oxide grown
by SEO while about 50 % of the total charge is trapped in a sample with N2O grown oxide annealed in
NO. In samples with oxide grown by SEO, there is a monotonic increase in mobility with sheet charge
density and the mobility also increases with temperature. This is an indication that the main scattering
mechanism is Coulomb scattering in this regime.
Improvement of Electron Channel Mobility in 4H SiC MOSFET by Using Nitrogen Implantation
Authors: Moscatelli Francesco , Nipoti Roberta , Solmi Sandro , Cristiani Stefano , Sanmartin Michele , Poggi Antonella
Published: March 2009

We report investigations on the fabrication and electrical characterization in the range 27°C
-290 °C of normally off 4H-SiC circular MOSFET devices manufactured on p-type semiconductor.
An high quality SiO2/SiC interface is obtained by nitrogen ion implantation conducted before the
thermal oxidation of SiC. Two samples with different nitrogen concentration at the SiO2/SiC interface
and one un-implanted have been manufactured. The sample with the highest N concentration at the
interface presents the highest channel mobility and the lowest threshold voltage. With increasing
temperature, in all the samples the threshold voltage decreases and the electron channel mobility
increases, reaching the maximum value of about 40 cm2/Vs at 290 °C for the sample with the highest
N concentration. The observed improvement of the mobility is related to the beneficial effect of the N
presence at the SiO2/SiC interface, which leads to the reduction of the interface trap density with
energy close to the conduction band. Our results demonstrate that N implantation can effectively be
used to improve the electrical performance of surface n-channel 4H-SiC MOSFETs.
100 mm 4HN-SiC Wafers with Zero Micropipe Density
Authors: Leonard R.T. , Khlebnikov Y. , Powell Adrian R. , Basceri C. , Brady M.F. , Khlebnikov I. , Jenny Jason R. , Malta D.P. , Paisley Michael J. , Tsvetkov Valeri F. , Zilli R. , Deyneka E. , Hobgood H.McD. , Balakrishna Vijay , Carter Jr. Calvin H.
Published: March 2009

Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.
4H-SiC p-Channel MOSFETs with Epi-Channel Structure
Authors: Okamoto Mitsuo , Yatsuo Tsutomu , Fukuda Kenji , Okumura Hajime , Arai Kazuo
Published: March 2009

From a viewpoint of device application using p-channel SiC MOSFETs, control of their
channel properties is of great importance. We aimed to control the electrical properties of 4H-SiC
p-channel MOSFETs through locating the p-type epitaxial layer at the channel area, so called
“epi-channel MOSFET” structure. We varied the dopant concentrations and the thickness of the
epi-channel layer, and investigated their electrical properties. In case of heavily doped epi-channel
samples, the devices indicated “normally-on” characteristics, and their channel mobility decreased
slightly in comparison with the inversion-type devices. As for lightly doped epi-channel samples, the
subthreshold current increased with thickness of the epi-channel layer keeping their “normally-off”
characteristics. Their channel mobility also increased with thickness of the epi-channel layer. The
peak value of field effect channel mobility of the sample with 2.5 μm thickness and 5×1015 /cm3
dopant concentration epi-channel was 18.1 cm2/Vs.
Two Different Species of Traps Monitored at N-Implanted 3C-SiC MOS Capacitors by Conductance Spectroscopy
Authors: Beljakowa Svetlana , Krieger M. , Frank Thomas , Pensl Gerhard , Trapaidze Lia , Hatta Naoki , Abe Masayuki , Nagasawa Hiroyuki , Schöner Adolf
Published: March 2009

3C-SiC/SiO2-capacitors are fabricated by over-oxidation of an implanted Gaussian
nitrogen (N) profile and investigated by conductance spectroscopy. A double peak structure is
observed in the conductance spectra indicating two types of traps, which change their charge state at
identical time constant, however, which are located at different energy positions in the bandgap of
3C-SiC. The experimental G/w-V and C-V characteristics are simulated and the existence of two
types of traps is verified in the framework of a theoretical model.
The Effect of Nitridation on SiC MOS Oxides as Evaluated by Charge Pumping
Authors: Habersat Daniel B. , Lelis Aivars J. , McGarrity J.M. , McLean F. Barry , Potbhare Siddharth
Published: March 2009

We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or
N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer
had a nitridation anneal after the gate oxide was formed, while the other was tested as-oxidized. We
compared the two processes by making measurements on lateral MOSFETs and MOS capacitors
using ID-VGS, C-V, and charge pumping. There was no change in either flatband voltage or interface
trap density near the valence band, suggesting that the net fixed charge remained constant (within a
few 1011cm-2). However, there was a large shift in the threshold voltage which, when combined with
the C-V results, indicates a strong reduction of interface traps near the conduction band of roughly
6.0x1012cm-2 by using the nitridation process. The charge pumping measurements also showed a
strong reduction of interface traps. Charge pumping measured a trapping density of 2.5x1012cm-2 for
the as-oxidized samples and 5.3x1011cm-2 for the nitrided samples. The frequency-dependence of the
charge pumping signal also indicates a spatial distribution of traps, with volumetric trap densities of
roughly 1.3x1019cm-3 over 25Å on as-oxidized and 3.8x1018cm-3 over 19Å for nitrided.
Temperature-Dependence of SiC MOSFET Threshold-Voltage Instability
Authors: Lelis Aivars J. , Habersat Daniel B. , Green Ronald , Goldsman Neil
Published: March 2009

We have observed variations in the instability in the threshold voltage, VT, of SiC metaloxide
semiconductor field-effect transistors (MOSFETs) from various sources and/or processes due
to gate-bias stressing as a function of temperature. In some cases we see a dramatic increase in the
instability with increasing temperature, consistent with interfacial charge trapping or de-trapping.
In other cases the temperature response is very slight, and in still other cases we actually see VT
instabilities that move in the opposite direction with bias, indicating the presence of mobile ions.
Development of Lapping and Polishing Technologies of 4H-SiC Wafers for Power Device Applications
Authors: Yashiro Hirokatsu , Fujimoto Tatsuo , Ohtani Noboru , Hoshino Taizo , Katsuno Masakazu , Aigo Takashi , Tsuge Hiroshi , Nakabayashi Masashi , Hirano Hosei , Tatsumi Kohei
Published: March 2009

The development of lapping and polishing technologies for SiC single crystal wafers has
realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the
SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side
lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter
SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm,
LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed
a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth
surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2,
effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica.
AFM (atomic force microscope) observation of polished wafer surface revealed that this process
allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.
Beveling of Silicon Carbide Wafer by Plasma Chemical Vaporization Machining
Authors: Kato Takehiro , Sano Yasuhisa , Hara Hideyuki , Mimura Hidekazu , Yamamura Kazuya , Yamauchi Kazuto
Published: March 2009

Beveling is essential for preventing the chipping of the edge of a wafer during surface
polishing and other processes. Plasma chemical vaporization machining (PCVM) is an
atmospheric-pressure plasma etching process. It has a high removal rate equivalent to those of
conventional machining methods such as grinding and lapping, which are used for high-hardness
materials such as silicon carbide, due to the generation of high-density radicals in
atmospheric-pressure plasma. Furthermore, PCVM does not damage the wafer surface because it is a
purely chemical process; therefore, it is considered that PCVM can be used as an effective method of
beveling the edge of SiC wafers. In this paper, we report the investigation of the beveling of SiC
wafers by PCVM.
Characterization of Electric Discharge Machining for Silicon Carbide Single Crystal
Authors: Kato Tomohisa , Noro Toshiya , Takahashi Hideaki , Yamaguchi Satarou , Arai Kazuo
Published: March 2009

In this study, we report electric discharge machining (EDM) as a new cutting method for
silicon carbide (SiC) single crystals. Moreover, we discuss characteristics and usefulness of the EDM
for the SiC. The EDM realized not only high speed and smooth cutting but also lower surface damage.
Defect propagation in the EDM SiCs have been also estimated by etch pits observation using molten
KOH, however, we confirmed the EDM has caused no damage inside the SiCs in spite of high voltage
and high temperature during the machining.