bluuebunny/crossref_metadata_2025 huggingface dataset:
Design Considerations for Reliable High Temperature Operation of Wet Electrolytic Tantalum Capacitors
Authors: Ladd Jeremy
Published: October 2015

Wet electrolytic tantalum (Ta) capacitors have historically been utilized in a variety of applications which endure harsh ambient conditions. Thermal, electrical and mechanical stresses, though, pose significant challenges to reliable performance of these capacitors in such environments. Thermal stress can increase the internal pressure of the capacitors, as well as mechanically compromise some of the components of which the capacitors are comprised. Electrical stress, in the form of current flow due to applied voltage, can elicit hydrogen gas evolution, which further exacerbates the internal pressure issue, potentially embrittles Ta components, and degrades AC performance of the capacitors. Mechanical stress, resulting from shock and vibration for example, can jeopardize the internal mechanical integrity of the capacitors.

This paper elaborates on these obstacles, and offers design approaches to reliably overcome them. Also presented are results of high temperature performance, predominantly up to 230°C, but also a mention of limited 245°C results, of wet Ta capacitors manufactured with proper attention paid to these concerns.
High-Temperature, High-Dielectric-Constant Capacitors for Power Inverters in Hybrid Electric Vehicles
Authors: Balachandran U. , Narayanan M. , Ma B.
Published: October 2015

Future availability of high-temperature power inverters will advance the market share for hybrid vehicles that are highly fuel efficient and environmentally friendly. Capacitors have a significant influence on inverter lifetime, reliability, cost, and temperature of operation. Advanced power inverters require capacitors that operate under high voltage conditions at under-hood conditions and yet have minimal footprint. This need can be realized by embedding high-permittivity dielectrics within a printed wire board (PWB). The “film-on-foil” approach, where the dielectric is deposited on base-metal foil, is a promising method for embedding the capacitors within a PWB. We have deposited high-permittivity films of lead lanthanum zirconium titanate (PLZT) on nickel foils by a chemical solution deposition technique. These prefabricated film-on-foil dielectric sheets can be embedded into PWBs for inverter applications. Among the many challenges in fabricating these sheets is avoiding a reduction in capacitance density from the formation of a parasitic, low-permittivity, interfacial layer of nickel oxide during thermal processing of the PLZT. We inserted a conductive oxide buffer layer between the PLZT dielectric film and the nickel foil to hinder formation of the deleterious interfacial oxide. For PLZT films deposited on Ni foils, we measured a dielectric constant of 1300 (at 25°C) and 1800 (at 150°C), leakage current density of 6.6 × 10−9 A/cm2 (at 25°C) and 1.4 × 10−8 A/cm2 (at 150°C), and breakdown field strength >2.0 MV/cm (at 25°C). Film-on-foil dielectric films were thermally cycled (≈1000 cycles) between −50°C and +150°C with no measurable degradation in dielectric constant. Recently, we fabricated and measured a capacitance of ≈1 μF on a 12-mm-diameter film-on-foil dielectric layer. The fabrication procedures and dielectric properties of film-on-foil PLZT samples are presented in this talk.
A 256 kbit (32kx8) EEPROM for >200°C Applications
Authors: Adams Dennis , Black Jeff , Cunningham Garry , Lewis Randall , O'Brien Jason , Hand Bill , Marsh Greg , Manwaring Ian , Pierce Donald , Sherman Cory , Wong Sze
Published: October 2015

A memory retention study was performed on the W28C256 256k (32kx8) EEPROM device to assess its suitability for use in high temperature applications above 200°C. This study indicates this device has memory retention in excess of 5 years at 225°C. During 2014, characterization and extended life testing is planned to further assess device reliability for future high temperature applications.
Pressureless, Low Temperature Sintering of Micro-scale Silver Paste for Die Attach for 300°C Applications
Authors: Yu Fang , Johnson R. Wayne , Hamilton Michael
Published: October 2015

Low temperature Ag sintering technology provides a lead-free die attachment compatible with high temperature (300°C) applications. Previous work with Ag sintering has required pressure during the sintering process or been limited to small area die. In this paper, the pressureless sintering of micro-scale silver paste is examined for larger (8mm × 8mm) area die. Experimental combinations included: Si die metallization (Ag and Au); thick film substrate metallization (Au, Ag and PdAg); and sintering temperature.

For Au metallization (die and/or substrate), the initial shear strength results were good with 8mm × 8mm die sintered at lower temperatures (200°C). The shear strength was beyond the limit of the shear test machine (100 kg), corresponding to >15.3 MPa. However, after aging for 24 hours at 300°C, the shear strength dropped significantly. An SEM was used to characterize cross sections of as-built and aged sample. The decrease in die shear strength with high temperature sintering (250°C and 300°C) or high temperature aging is attributed to surface diffusion of Ag along the Au surface resulting in a dense Ag layer adjacent to the Au surface and a depletion layer within the die attach adjacent to the dense Ag layer. Shear failures occurred through the depleted region.

For Ag metallization (die and substrate), no decrease in shear strength was observed with 300°C aging. Shear strength of 8 mm × 8 mm dies was >100 kg ( >15.3 MPa) as-built. The shear strength remained >15.3MPa after 3000 hours of 300°C aging.
Uniqueness and Challenges of Sintered Silver as a Bonded Interface Material†
Authors: Wereszczak A. A. , Liang Z. , Ferber M. K. , Marlino L. D.
Published: October 2015

There are numerous attributes of sintered silver (Ag) as a bonded interface between die and substrate or even between substrate and heat sink in power devices. This is attested to by the relatively large number of studies devoted to it the last several years. Sintered silver potentially has a high temperature capability, high electrical and thermal conductivities, its microstructure is in equilibrium, it could predictably respond linearly elastically during thermal cycling, and the time-dependent pore coalescence and pore growth that exists with solders is apparently minimal or even nonexistent. But sintered silver bonding is a relatively new technology and solid-state sintering science and its application can be unfamiliar to solder/bonding practitioners. There are at least five different aspects of it compared to solder bonding and those are overviewed here based on the authors' experience with Ag-sintering over the last several years. For sintered-Ag interconnect bonding: it is a solid-state process (i.e., no melting); its bond strength is affected by the topography of the mating surfaces; concurrent pressure application during processing can improve bond strength; issues associated with the paste's organic binder burnout and exhaust can arise depending on the interconnect size; and porosity is indigenous to its bulk microstructure requiring its consideration and possible management. Increased understanding of these unique characteristics will help advance employment of sintered-Ag technology and the exploitation of its attributes for fabricating more reliable, higher-temperature- capable, and more thermally conductive power electronic modules.
High Temperature Performance of Coiled Glass Capacitors
Authors: Furman Eugene , Baker Amanda , Perini Steve , Monoharan Mohan , Kushner Douglas , Zhang Nanyan , Zou Chen , Mi Charles , Zhang Shihai , Murata Takashi , Lanagan Michael
Published: October 2015

Alkali-free flat panel display glass is produced in large quantity and has excellent electrical insulating properties at high temperature. Aluminum borosilicate glass with alkaline-earth modifier has low sodium content and low dielectric loss (tan δ <0.1 at 250°C), high dielectric breakdown strength (109 V/m) and excellent high temperature stability. In addition, roll-to-roll processing of thin glass sheet has been demonstrated and glass capacitors that are configured in a coil. Excellent high power capability of these glasses was confirmed by analytical, finite element, and finite difference modeling. The modeling work indicates that a combination of hybrid electrode design and effective heat loss at the interface can further extend power capability of glass capacitors. Alkali-free glass is an ideal candidate material for high temperature capacitors.
Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures
Authors: Flicker Jack , Hughart David , Kaplar Robert , Atcitty Stanley , Marinella Matthew
Published: October 2015

1200 V Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) have been characterized at high operational temperatures. For packaged JFETs obtained from a collaborating manufacturer, the threshold shift (ΔVT) was measured under both static and dynamic voltage stress and, in all cases, was less than 2 mV, which is within the measurement margin of error. Temperatures up to 250°C and stress times as long as 200 hours were evaluated. As a comparison, commercially available SiC MOSFETs demonstrated shifts of up to 300 mV after 30 minutes of static gate stress at 175°C. In addition, results from unpackaged JFET die at temperatures up to 525°C show ΔVT values of less than 10 mV for all stress conditions. Although VT remained unchanged for the duration of the test for both static and dynamic stress conditions, under dynamic stress conditions the JFET packaged parts demonstrated a linear increase in sub-threshold leakage current of around 15.6 nA per hour; in contrast, the MOSFET devices showed an exponential increase in sub-threshold leakage under dynamic stress. The increase in sub-threshold leakage current could be recovered temporarily, but long-term behavior was consistent with cumulative damage.
Enhancing Performance and Reliability of High Temperature Electronics through Thermally-Stable Parylene HT
Authors: Kumar Rakesh
Published: October 2015

Significant performance and reliability challenges exist for high temperature electronics used in many applications, including those used in down-hole, under-bonnet, well-logging and aero-engine applications. Under high temp operating environments, the life expectancy of electronic components and systems reduces exponentially if they are not designed, packaged and protected appropriately to tolerate or negate the impact of high temperatures. This presentation highlights specific materials and conformal coating issues that play a significant role in addressing above challenges and presents results of thermal aging effects on Parylene HT at 250°C and up to 450°C. In addition, it provides an in-depth analysis of its performances at high temperatures and offers solutions to some existing issues through incorporating Parylene HT in the design and final protection of high temperature electronics.
High Temperature System Design for Electric and Hybrid Electric Vehicles
Authors: Vermesan Ovidiu , Blystad Lars-Cyril , John Reiner , Ottella Marco , Mollestad Egil
Published: October 2015

The automotive semiconductor market is currently valued at around $10 billion worldwide, and is expected to rise to more than $14 billion by 2014. The steep rise of power modules for hybrid and electric vehicles is not yet included in this prognosis. Electronic systems have been the most rapidly growing element of vehicles in recent years, and this trend rise sharply with the introduction of electric vehicles (EVs) and hybrid electric vehicles (HEVs). The key parameters that determine the suitability of a power device for high temperature environment are the devices maximum allowable junction temperature and its conduction loss. The power devices are cooled to an extent that their junction temperatures do not exceed the maximum allowable value. Increasing the maximum junction temperature allows a higher base plate or heat sink temperature. A higher heat sink temperature, allows a higher ambient air temperature or coolant temperature. The semiconductor devices with low conduction loss will generate less heat, and allows a higher heat sink temperature. The paper presents the developments of a novel 400V IGBT based power module well suitable for electric vehicle applications.
KEMET SMD Film Capacitors for High Temperature Applications
Authors: Caliari Luca , Bettacchi Paola , Boni Evangelista , Montanari Davide , Gamberini Arrigo , Barbieri Luigi , Bergamaschi Francesco
Published: October 2015

Trends of several applications like down-hole drilling, commercial aviation (e.g. jet engines), heavy industrial and automotive are challenging the capabilities of capacitors and other electronic components.

The growing harsh-environment conditions for these applications are: high temperature, high voltage and high current. At the capacitor component level, required features are: very high reliability under mechanical shock, rapid changes in temperature, low leakage current (high insulation resistance), small dimensions, good stability with time and humidity, and high peak withstanding voltage. Capacitors for power-conversion circuitry must maintain a low AC loss and DC leakage at high temperatures.

KEMET has recently designed film capacitor series using PEN to address the needs of the above mentioned circuits, in particular regarding the working temperature, voltage and current.

This paper will cover technological advances in film capacitor technology to address harsh environment conditions needs, providing test results on temperature, voltage and thermal shock acceleration factor.
A High Temperature, Fast Switching SiC Multi-chip Power Module (MCPM) for High Frequency (> 500 kHz) Power Conversion Applications
Authors: Cole Z. , Passmore B. S. , Whitaker B. , Barkley A. , McNutt T. , Lostetter A. B.
Published: October 2015

In high frequency power conversion applications, the dominant mechanism attributed to power loss is the turn-on and -off transition times. To this end, a full-bridge silicon carbide (SiC) multi-chip power module (MCPM) was designed to minimize parasitics in order to reduce over-voltage/current spikes as well as resistance in the power path. The MCPM was designed and packaged using high temperature (> 200 °C) materials and processes. Using these advanced packaging materials and devices, the SiC MCPM was designed to exhibit low thermal resistance which was modeled using three-dimensional finite-element analysis and experimentally verified to be 0.18 °C/W. A good agreement between the model and experiment was achieved. MCPMs were assembled and the gate leakage, drain leakage, on-state characteristics, and on-resistance were measured over temperature. To verify low parasitic design, the SiC MCPM was inserted into a boost converter configuration and the switching characteristics were investigated. Extremely low rise and fall times of 16.1 and 7.5 ns were observed, respectively. The boost converter demonstrated an efficiency of > 98.6% at 4.8 kW operating at a switching frequency of 250 kHz. In addition, a peak efficiency of 96.5% was achieved for a switching frequency of 1.2 MHz and output power of 3 kW.
Nanocomposite Epoxy Resin for SiC Module
Authors: Okamoto Kenji , Takematsu Yuji , Hitomi Miyako , Ikeda Yoshinari , Takahashi Yoshikazu
Published: October 2015

There is a demand to improve the thermal stability of epoxy molding resins used in the power module of SiC power chips operating at temperatures of 200°C or more. This paper describes a technique for increasing the thermal stability of the resin by decreasing molecular motion through the addition of nanofiller. The experimental results showed that the glass transition temperature (Tg) of the epoxy resin increased by approximately 30°C when the silica nanofiller was added. The epoxy resin added nanofiller was investigated in order to achieve the operation temperature 200°C of power module.
285°C Resistor Drift and Failure Analysis
Authors: Watts Milton , Smith Ron
Published: October 2015

In order to improve the reliability of down-hole electronics, Quartzdyne Electronics has invested millions of device test hours in life testing circuits in both powered and un-powered modes. In addition to time at temperature, these tests include thermal cycling and high impact drop testing. Resistors drift has become a significant wear-out mechanism in these tests. Prior testing has shown that resistor material, substrate material, resistance range and trim method each play a significant role in resistor stability at elevated temperatures. Some resistance ranges tested had no acceptable performers.

The purpose of this study is to expand the range of values, materials and package sizes in hopes of identifying reliable resistors for high temperature applications. This study will focus on a broad range of NiCr-on-silicon resistors, including larger package sizes than were previously tested. Additionally, we will be testing several precision foil-type resistors. Resistors will be mounted in hermetic packages and aged at 285°C for 1000 hours. The packages will be removed from the oven periodically and the resistance of the devices will be measured at ambient temperature. This study is being done in cooperation with resistor vendors who have supplied some of the devices for this test.
Comparative Reliability Prediction Using Physics of Failure Models
Authors: Watts Milton , Harker K. Rob
Published: October 2015

Quartzdyne Electronics has invested millions of device test hours in life testing of circuits in both powered and un-powered tests. In addition to time at temperature, these tests include thermal cycling and high impact drop testing. Recent projects have required the use of larger packages and components as we have expanded the variety of circuits that we build. It is desirable to predict the effects of these changes on long-term reliability before investing in tooling. In this study we will compare a new design which contains these larger components to the simpler, smaller designs for which we have extensive life-test data. Using a physics-of-failure approach, component mounting stresses will be analyzed using finite element modeling. These results will be compared to pre and post-aging shear strengths of actual components of varying sizes. Aging models will then be developed to predict the reliability of the new design based on the comparative stress margins of the individual components coupled with circuit complexity. Once validated, the aging models will enable reliability prediction and trade-off analysis for future designs.
A High Temperature and UV Stable Vapor Phase Polymer for Electronics Applications
Authors: Kumar Rakesh
Published: October 2015

A recent development in the area of high temperature and UV stable polymers, which offers solutions to many existing packaging and reliability challenges of electronics industry, is described. Packaging, protection and reliability of various electronic devices and component, including PCB's, MEMS, optoelectronic devices, fuel cell components and nano-electronic parts are, becoming more challenging due to their long-term performance requirements. This high temperature polymer, named Parylene HT, offers solutions to many existing protective, packaging and reliability issues in the electronics and medical industries, in part because of its excellent electrical and mechanical properties, chemical inertness and long-term thermal stability at high temperature exposure (up to 350°C long-term and short-term at 450 °C). Experimental results and trial runs demonstrate the ability of Parylene HT coating to meet the growing requirements of higher dielectric capabilities, higher temperature integrity, mechanical processing, etc. of a dynamic electronics industry. In addition, Parylene HT polymer coating truly conforms to parts due to its molecular level deposition characteristics. Its suitability and biocompatibility encourage researchers to explore Parylene HT's role in sensors and in active electronic devices for various industries.
>1200 V, >50A SILICON CARBIDE SUPER JUNCTION TRANSISTOR
Authors: Singh Ranbir , Sundaresan Siddarth , Jeliazkov Stoyan , Veereddy Deepak , Lieser Eric
Published: October 2015

The electrical performance of GeneSiC's 1200 V/7 A SiC Super Junction Transistor (SJT) is compared with three best-in-class commercial Si IGBTs in this paper. Low leakage currents of < 100 μA at 325 °C operating temperature, switching transients < 15 ns at 250 °C, Common Source current gains of 63 and on-resistance as low as 220 mΩ were measured on the SiC SJTs. For switching 7 A, 800 V at 100 kHz, the SiC SJT+GeneSiC SiC Schottky rectifier as Free Wheeling Diode (FWD) achieved a total power loss reduction of about 64% when compared to the best all-Si IGBT+FWD configuration and a power loss reduction of about 47 %, when compared to the best Si IGBT + SiC Schottky FWD.
Au-Sn SLID bonding for high temperature applications
Authors: Tollefsen Torleif André , Larsson Andreas , Aasmundtveit Knut
Published: October 2015

Au-Sn solid-liquid-interdiffusion (SLID) bonding is a novel and promising interconnect technology for high temperature (HT) applications. In combination with Silicon Carbide (SiC) devices, Au-Sn SLID has the potential of being a key technology for the next generation of innovative, cost effective and environmentally friendly drilling and well intervention systems for the oil industry. However, limited knowledge about Au-Sn SLID bonding for combined HT and high power applications is a major restriction to fully realize the high temperature potential of SiC devices. This paper presents a comprehensive study of fluxless Au-Sn SLID bonding.

Two different processing techniques – electroplating of Au / Sn layers and sandwiching of eutectic Au-Sn preform between electroplated Au layers – have been studied in a simplified metallization system. The latter process was further investigated in two different Cu / Si3N4 / Cu / NiP / Au-Sn / Ni / Ni2Si / SiC systems (different Au-layer thickness). Die shear tests and cross-sections have been performed on “as bonded”, thermally cycled and thermally aged samples to characterize the bonding properties associated with the different processing techniques, metallization schemes and environmental stress tests.

A uniform Au-rich bond interface is produced (the ζ phase with a melting point of 522 °C). The importance of excess Au on both substrate and chip side in the final bond is demonstrated. It is shown that Au-Sn SLID can absorb thermo-mechanical stresses induced by large CTE mismatches (up to 12 ppm/K) in a packaging system during HT thermal cycling. The bonding strength of Au-Sn SLID is shown to be superb, exceeding 78 MPa. Importantly, Au-Sn SLID is shown to be an excellent interconnect technology for HT packaging.
High Temperature Silicon Carbide Power Modules for High Performance Systems
Authors: Hornberger J. , McPherson B. , Bourne J. , Shaw R. , Cilio E. , Cilio W. , Reese B. , Heinrichs E. , McNutt T. , Schupbach M. , Lostetter A.B.
Published: October 2015

The demands of modern high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of silicon carbide (SiC) are well known, including high temperature operation, high voltage blocking capability, high speed switching, and high energy efficiency. In this discussion, APEI, Inc. presents two newly developed high performance SiC power modules for extreme environment systems and applications. These power modules are rated to 1200V, are operational at currents greater than 100A, can perform at temperatures in excess of 250 °C, and are designed to house various SiC devices, including MOSFETs, JFETs, or BJTs.

One newly developed module is designed for high performance, ultra-high reliability systems such as aircraft and spacecraft, and features a hermetically sealed package with a ring seal technology capable of sustaining temperatures in excess of 400°C. The second module is designed for high performance commercial and industrial systems such as hybrid electric vehicles or renewable energy applications, implements a novel ultra-low parasitic packaging approach that enables high switching frequencies in excess of 100 kHz, and weighs in at just over 130 grams (offering ~5× mass reduction and ~3× size reduction in comparison with industry standard power brick packaging technology). It is configurable as either a half or full bridge converter. In this discussion, APEI, Inc. introduces these products and presents practical testing of each.
Comparison of Au-In Transient Liquid Phase Bonding Designs for SiC Power Semiconductor Device Packaging
Authors: Grummel Brian , Mustain Habib A. , Shen Z. John , Hefner Allen R.
Published: October 2015

Transient liquid phase (TLP) bonding is an advanced die-attach technique for wide-bandgap power semiconductor and high-temperature packaging. TLP bonding advances current soldering techniques by raising the melting point to over 500 °C without detrimental high-lead materials. The bond also has greater reliability and rigidity due in part to a bonding temperature of 200 °C that drastically lowers the peak bond stresses. Furthermore, the thermal conductivity is increased 67 % while the bond thickness is substantially reduced, lowering the thermal resistance by an order of magnitude. This work provides an in-depth examination of the TLP fabrication methodology utilizing mechanical and thermal experimental characterization data along with thermal reliability results.
Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments
Authors: Boufouss E. , Francis L. A. , Gérard P. , Assaad M. , Flandre D.
Published: October 2015

We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0.

To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply voltage. Measurements have validated correct operation in the temperature range from −40°C to 300°C before radiation and to 125°C after radiation up to now which will be extended further with a new set-up.

Irradiation has been performed from 10 to 30 kGy. Such very high doses cause a shift down of output voltage values, which leads to a change of the temperature detection level and also increases the power dissipation by up to six times. Annealing effects help the partial recovery of the device operation at high temperature and the remote microprocessor enables calibration after radiation to readjust the temperature detection level.
High-Temperature Component Evaluation of Commercial Flash Memory and Capacitors for Enhancement of Geothermal Tool Development
Authors: Cashion Avery , Cieslewski Grzegorz
Published: October 2015

Environments relevant to geothermal energy exploration frequently exceed the temperatures and pressures commonly experienced by downhole tools in the oil and gas industry. As such, pushing the boundaries with geothermal tool development can often necessitate exceeding manufacturer specifications for temperature and pressure of individual circuit components. High-temperature circuit designers often must dedicate considerable time and resources to determine if a component exists that they may be able to knead performance out of to meet their requirements. In light of this difficulty, Sandia National Laboratories has initiated a program funded by the Geothermal Technologies Office at the US Department of Energy to compile and make available an empirically determined, practical dataset of select high-temperature component performances beyond specification. Detailed here are the efforts surrounding geothermal temperature characterization of commercially available HT-Flash memory modules made by Texas Instruments (SM28VLT32-HT) and preliminary results of 3 commercial solid tantalum capacitors. Flash evaluation boards were modified for high temperature application and read, write and erase functionality were tracked as well as prolonged data retention at various temperatures well beyond datasheet specifications. It was observed that each flash function has a different maximum operation temperature above specification. As temperature increases, erase, write, and then read functions successively fail. Within duration and temperature limits, functionality of each operation returns after cooling back below its threshold value. Importantly for logging tools, after cooling the flash modules in this study still retain all memory previously written. Flash lifetime at temperature was examined at several temperatures by 1000hr duration tests in the oven with new writes and periodic full memory reads throughout the test. To test the capacitors, capacitance and equivalent series resistance were tracked over a 1000hr test at 260°C. Results of MatLab fault analyses are described for each aspect of this study to facilitate out-of-spec high temperature tool design.
Test Results of Sintered Nano-Silver Paste Die Attach for High Temperature Applications
Authors: Croteau Paul , Seal Sayan , Witherell Ryan , Glover Michael , Krishnamurthy Shashank , Mantooth Alan
Published: October 2015

The emergence of wide band gap devices has pushed the boundaries of power converter operations and high power density applications. It is desirable to operate a power inverter at high switching frequencies to reduce passive filter weight and at high temperature to reduce the cooling system requirement. Therefore, materials and components that are reliable at temperatures ranging from −55 to 200 °C, or higher, are needed. Sintered silver is receiving significant attention in the power electronic industry. The porous nature of sintered nano-silver paste with a reduced elastic modulus has the potential to provide strain relief between the die component and substrate while maintaining its relatively high melting point after sintering. The test results presented herein include tensile testing to rupture of sintered silver film to characterize stress strain behavior, as well as die shear and thermal cyclic tests of sintered silver bonded silicon die specimens to copper substrates to determine shear strength and reliability.
Electromigration Phenomena in Sintered Nanoparticle Ag Systems Under High Current Density
Authors: Mansourian Ali , Paknejad Seyed Amir , Wen Qiannan , Khtatba Khalid , Zayats Anatoly , Mannan Samjid H.
Published: October 2015

Electromigration (EM) refers to the movement of atoms inside a conductor due to momentum exchange with the conduction electrons. In this work the EM effect in samples of porous Ag fabricated from nanoparticles of Ag in a pressure free sintering process is studied. Current densities of 2.5×104 − 1.7×105 A/cm2 were applied to the samples for periods ranging up to 500 h. In a typical EM setup with a non-porous conductor, void formation occurs at the cathode and hillock formation at the anode. In this study, voids were not directly observed, but cracks were formed after prolonged electromigration, presumably as a result of void accumulation and coalescence. When the samples were placed in 150 °C ambient no hillocks were observed, but at room temperature nanorods were formed with sizes ranging up to 20 μm in length, typically 25 nm in diameter and with aspect ratios ranging from 20 to 1000. It was found that interrupting and restarting the current resulted in growth of new nanorods rather than growth of existing ones, and that growth was limited by welding of individual nanorods when a critical number density was reached. While similar nanorods have been formed from Ag thin films using thermal stress , the location of nanorods was unusual in that while the number density was highest at the anode, significant numbers also appeared at central and cathode locations. Another unusual feature of the observed EM was that the initial porous structure became refined with coarse pores and grains transforming into a fine grained and fine pored structure with elongated and locally orientated pores and grains. Elemental composition studies provide tentative understanding of the nanorod number density, size distribution and growth mechanism. In the geometry utilized for this study, temperature gradients are known to strongly influence the divergence of the EM induced atomic flux and hence resistivity measurements and COMSOL Finite Element modelling was used to determine the temperature in the sample taking into account joule heating, convection and conduction processes.
Increased High-Temperature Reliability and Package Hardening of Commercial Integrated Circuits (Through Die Extraction, Electroless Nickel/Gold Pad Reconditioning, and Ceramic Re-Assembly)
Authors: Spory Erick M.
Published: October 2015

There is an ever-increasing demand for electronics in higher temperature applications, both in variety and volume. In many cases, the actual integrated circuit within the plastic packaging can support operation at higher temperatures, although the packaging and connectivity is unable to do so. Ultimately, there still remains a significant gap in the volume demand required for high temperature integrated circuit lines to justify support of more expensive ceramic solutions by the original component manufacturer vs. the cheaper, high-volume PEM flows. Global Circuit Innovations, Inc. has developed a manufacturable, cost-effective solution to extract the integrated circuit from any plastic encapsulated device and subsequently re-package that device into an identical ceramic footprint, with the ability to maintain high-integrity connectivity to the device and enabling functionality for 1000's of hours at temperatures at 250C and beyond. This process represents a high-value added solution to provide high-temperature integrated circuits for a large spectrum of requirements: low-volume, quick-turn evaluation of integrated circuit prototyping, as well as medium to high-volume production needs for ongoing production needs. Although both die extraction and integrated circuit pad electroless nickel/gold plating have both been performed successfully for many years in the semiconductor industry, Global Circuit Innovations, Inc. has been able to combine the two in a reliable, volume manufacturing flow to satisfy many of the stringent requirements for high-temperature applications.
Study of the electrical and thermal properties of a silicone elastomer filled with silica for high temperature power device encapsulation
Authors: Sili E. , Locatelli M.L. , Bechara M. , Diaham S. , Dinculescu S.
Published: October 2015

In order to take the full advantage of the high-temperature SiC and GaN operating power devices, package materials able to withstand high-temperature storage and large thermal cycles are required. However, a survey of the commercially available silicone gels mostly used for power module encapsulation, highlights that this type of materials exhibits a maximum temperature limit for continuous operation of about 260 °C. A slight extension of this temperature range might be obtained by using silicone elastomers with hardness still remaining measurable on the Shore A scale. The aim of this paper is to study a silicone elastomer poly(dimethyl)siloxane (PDMS) with silica fillers, with a specified maximum operating temperature of 275 °C, in order to evaluate its ability for high temperature power device encapsulation. First, the nature and size of the filler microparticles were determined using scanning electron microscopy (SEM) observations coupled with energy dispersive X-ray spectroscopy (EDX) analysis. Second, the results of the thermal and electrical properties of this elastomer over a wide temperature range show that this type of insulating materials presents promising initial properties for the encapsulation of high temperature power devices.
Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing
Authors: Schmidt Alexander , Kappert Holger , Kokozinski Rainer
Published: October 2015

Analog circuit realized in a PD-SOI (Partially-Depleted Silicon-on-Insulator) CMOS process for a wide temperature range up to 400 °C are significantly affected by the MOSFET device characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, e.g. intrinsic gain and bandwidth tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that reverse body biasing (RBB) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300 °C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS process by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400 °C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, basic current mirrors, a two-stage operational amplifier and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. The method has also been applied to basic analog circuits. It has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400 °C.
A 250°C ASIC Technology
Authors: Reed Lynn
Published: October 2015

Tekmos has developed a 250°C ASIC technology that uses the X-Fab XI10 SOI process. A gate array architecture was chosen to allow reduced mask costs and quicker manufacturing cycle times. The design of the technology includes first determining the optimum routing grid and then designing of the basic gate array transistors. The “A” style transistor was chosen over the “H” style to create stronger transistors. The choice of the transistor in turn sets the characteristics of the basic “Block” that is used in the gate array architecture. Another factor in the block design is the requirement for a pre-determined source with “A” transistors. This prevents the use of shared diffusions that are used in most gate array architectures and resulted in a different block layout. The pre-determined sources also required a change to the logic cell library. Since the basic transmission gate found in most flop designs cannot be used, alternative logic architectures were developed. By implementing the SOI specific library into the Tekmos standard logic library, the SOI peculiarities were masked from the end designer. The 250°C ASIC technology was demonstrated in a FPGA conversion, in which a design in an Actel MX series FPGA was reimplemented in the 250°C ASIC technology. A standard FPGA design conversion flow was used, and the only issues were related to the speed and voltage differences between the FPGA and the 1.0μ ASIC. These were addressed through critical path analysis and some slight circuit modifications. The temperature derating for 250°C was significant, but enough margin was retained to allow the circuit to work. Parts were made and worked as expected at 250°C. The life testing results at 280°C have been satisfactory. On an experimental basis, parts were evaluated at temperatures of up to 305°C without failure.
Communication system for down-hole measurement tools based on real-time SNR characterization in coaxial cable used as communication channel
Authors: Mijarez Rito , Pascacio David , Guevara Ricardo , Pacheco Olimpia , Tello Carlos , Rodríguez Joaquín
Published: October 2015

Down-hole oil and gas industries are important users of high temperature electronics. In these applications the operating temperature is function of the underground depth of the wells. Oil reservoirs in Mexico are located at mean depths of 6,000 m and the typical geothermal gradient is 25°C/km, however in some areas it is greater. Consequently, the requirements for measuring thermodynamic and geophysical parameters, for instance pressure, temperature, vibration and multiphase flow, are a challenging task. Accomplishing these necessities requires a complete signal communications chain of high-performance components and effective communication techniques to provide system reliability. Nevertheless, noise interference, cable attenuation and thermal drift of the front-end passive electronic elements can lead to poor signal-to-noise ratio (SNR) and possibly loss of the communication link. This paper describes a bidirectional communication system that exchanges data from a down-hole high pressure and high temperature (HP/HT) measurement tool to the surface installation. The communication channel is a multi-conductor coaxial logging cable used also as a power supply transmission line. The system consists of a proprietary down-hole measurement tool, composed of a HP/HT sensor and a high temperature DSP-based electronic device; and located in the surface installation, a data acquisition equipment. The system employs a communication algorithm, based on the SNR characterization of the whole communication chain, which determines in real-time the optimal carrier frequency that is automatically implemented in the selected modulation/demodulation technique. The obtained laboratory tests results of the down-hole tool, using changes in temperature from 25 °C – 185 °C, provide a firm basis for testing and evaluating the system in the field.
The European SEEL (Solutions for energy efficient lighting) project: High temperature electronics for LED-lighting architectures
Authors: Habenicht S. , Funke H.J. , Gruber D. , Oelgeschläger D. , Schumacher O. , Gehn R. , Walczyk S. , Mavinkurve A. , Reiners Th. , Fiederling R. , Vogl M. , Schug J. , Willwohl H. , Blandin J. , Hutter M. , Ehrhardt C. , Oppermann H.
Published: October 2015

Due to superior properties in energy-efficiency and design freedom, the “liberation of light” by LED-technology will draw more attention in future applications. Within the European SEEL project, the partners are performing research in enabling technologies for high-temperature electronics (up to 185°C) to be designed into the next generation of high-efficient LED-driver circuits. This requires high-temperature evaluation of the product architecture of electronic components, i.e. the 1st-level interconnection, i.e. the chip metallization and the chip bonding technology. Different methods such as Au- and Cu-wirebonding as well as soft-soldering technologies are evaluated and discussed. The material properties, i.e. the encapsulating mound compound and the die adhesives play an important role as these materials tend to degrade at elevated temperatures. On top of that, also the board mounting architecture of the products, i.e. the board materials and the interconnection techniques such as high-temperature soldering play an important role and have to be discussed during the architecture evaluation, as solder joints and board materials are prominent candidates for mechanical degradation during high-temperature treatment. Thermal aspects in the circuit design in order to prevent part of the system architecture from overheating during operation, play an important role in the system design.

The current status of the project as well as the future exploitation outlook will be presented.
LT-TLPS Die Attach for High Temperature Electronic Packaging
Authors: Greve Hannes , McCluskey F. Patrick
Published: October 2015

Low temperature transient liquid phase sintering (LT-TLPS) can be used to form high-temperature joints between metallic interfaces at low process temperatures. In this paper, process analysis and shear strength studies of paste-based approaches to LT-TLPS are presented. The process progression studies include DSC-analyses and observations of intermetallic compound (IMC) formation by cross-sectioning. It was found that the sintering process reaches completion after sintering times of 15 minutes for process temperatures around 50°C above the melting point of the low temperature constituent. For the shear strength studies, test samples consisting of copper dice and copper substrates joined by sintering with a variety of pastes having different ratios of copper and tin have been assessed. A fixture was designed for high temperatures enabled shear tests at 25°C, 125°C, 250°C, 400°C, and 600°C. The influence of the ratio of the amount of high melting-point constituent to the amount of low melting-point constituent on the maximum application temperature of the sinter paste was analyzed. Ag20Sn and Cu50Sn pastes showed no reduction in shear strength up to 400°C, Cu40Sn pastes showed high shear strengths up to 600°C, and extended curing further increased the joint strength. It was shown that LT-TLPS can be used to form high temperature stable joints at low temperatures without the need of applying pressure during processing.
Precise Chip Joint Method with Sub-micron Au Particle for High-density SiC Power Module Operating at High Temperature
Authors: Kato Fumiki , Lang Fengqun , Rejeki Simanjorang , Nakagawa Hiroshi , Yamaguchi Hiroshi , Sato Hiroshi
Published: October 2015

In this work, a novel precise chip joint method using sub-micron Au particle for high-density silicon carbide (SiC) power module operating at high temperature is proposed. A module structure of SiC power devices are sandwiched between two silicon nitride-active metal brazed copper (SiN-AMC) circuit boards. To make a precise position and height control of the chip bonding, the top side (gate/source or anode pad side) of SiC power devices are flip-chip bonded to circuit electrodes using sub-micron Au particle with low temperature (250°C) and pressure-less sintering. The accuracy of the bonding position of chips was less than 10 μm and the accuracy of the height after bonding chips was less than 15 μm. Mechanical shear fatigue tests for flip-chip bonded SiC Schottky barrier diode (SBD) were carried out. As a result, initial shear strength of the joint was 36 MPa. The shear strength of 43 MPa is obtained after storage life test (500 hours at 250°C), and also 35 MPa is obtained even after thermal cycle stress test (1000 cycles between −40°C and 250°C). The flip-chip bonding of SiC-JFET is successfully realizedon the substrate without short or open failure electrically. Finally we joint the backside of the SiC-JFET (drain side) and the SiC-SBD (cathode side) to each circuit electrodes at once by means of reflow process with Au-12%Ge solder. The structured sandwich SiC power module was also successfully formed.