Analysis of the Retention Characteristic in Three dimensional Junction-less Charge Trapping Memory
Authors: Jiang Dandan , Xia Zhiliang , Jin Lei , Zou Xingqi , Zhang Yu , Tang Zhaoyun , Li Xinkai , Huo Zongliang 
Published: February 2020

To meet the storage requirement of big data, charge trap concept-based three dimensional charge trapping memory (3D-CTM) becomes the main trend of flash technology development. With the multi-layer gate stacking, the equivalent technology node can be scaled down to 10nm without the serious reliability problems from cell-to-cell coupling and SILC-inducing charge loss in conventional flash memory. Specially, the cylindrical junction-less structures such as BICS and TCAT have attracted extensive attention from academia and industry due to their merits of relatively simple procedure and full compatibility with the CMOS process. Moreover, the vertical channel and the ring shape gate stack of memory cell make the 3D memory show superior program/erase performance comparing with the conventional planar flash. However, the shape of charge trap layer is also an important factor affecting the device reliability. The uneven electrical field distribution in tunnel and block layer and the non-separated charge trapping layer of the cylindrical junction-less geometry bring some problems about charge lose in program or erase state. The retention is a critical issue for high density and reliability of 3D integration.

In this work, the retention characteristic of 3D cylindrical junction-less charge trapping memory has been investigated. The trapped charge and electron concentration distribution after programming/erasing 10 years have been simulated by sentaurus 3D device simulator. The lateral and vertical charge migrations also have been discussed during the charge losing process. Furthermore, the dominant loss path at the vertical direction has been considered.

Figure 1(a) shows schematic birds-eye view of typical 3D-CTM array structure. In order to study the retention properties of 3D vertical memory cell, a string with one cell and two select transistors is used in simulation, as shown in Figure 1(b). Sentaurus 3D device simulator was used for the simulation. The barrier tunneling model contains Fowler–Nordheim tunneling and direct tunneling components, which depends on the energy barrier and band bending calculated self-consistently. 

From the simulate result of trapped charge at the initial programmed state (initial state) and 10 years  after programming state under 85°C condition (10 years state), it can be found that the lateral charge migration happened at 10 years  state with respect to the initial state. And the lateral extention distance will be longer if the vertical charge loss is unconsidered. Also,the simulate result shows there is a competition between vertical and lateral charge loss and the vertical charge loss weaken the lateral charge migration during the retention time. Then, the dominant loss path at the vertical direction has been studied. We find that charge loss toward block layer is more serious than tunnel layer. The retention at erase state is also be investigated.Comparing with electron loss, the trapped hole nearly doesn’t loss even after 10 years. This simulation result coincides with the experiment data from Toshiba and Samsung. It’s can be attributed to the larger effective mass and deeper trap energy level of the hole, making it harder to occur tunneling and migration.

In this article, retention of 3D cylindrical junction-less CTM has been studied. For the programmed device, lateral charge migration is obvious after 10 years. Vertical charge loss also occurs and lose more seriously toward block layer than tunnel layer. For the erased device, there is nearly no trapped hole loss even after 10 years.

This work was supported by the National Natural Science Foundation of China (Grant No. 61474137, No. 61306107, No. 61404168, No. 61404160), China Postdoctoral Science Foundation funded project (No.2014M550866), and the Scientific Research Foundation of CUIT (KYTZ201318, J201404).

Figure 1