(Invited) Hot Carrier Reliability of High Voltage HVMOSFETs in BCD (Bipolar-CMOS-DMOS) Technology
Authors: Hao Jifa 
Published: February 2020

This paper discusses three important issues in hot carrier (HC) reliability of LDMOSFET ((Laterally Diffused MOSFETs) in BCD technology. One of the main reliability issues encountered during development of the LDMOSFET is optimizing the trade-offs between specific on-resistance (Rdson) and hot carrier (HC) degradation [2]. For instance, Rdson can be reduced by increasing the drift region doping concentration or shrinking the drift region length. Both of these changes result in higher lateral electric field in the drift region which lead to increased HC degradation. The second issue is how to reduce HC degradation in LDMOS due to Back-End-Of-Line (BEOL). It has been reported for CMOS devices that HC performance can be degraded by BEOL processes such as interlayer dielectric film deposition, etch, metal deposition and etch process [3, 4]. The BEOL processes in BCD technology may have a worse impact on LDMOS HC performance than on CMOS’s since it has such as higher energy implants and thicker metal deposition and etch. The third issue is the influence of self heating on the measurement of HC degradation in high gate voltages stress for HC SOA (safe-operating-area) in high voltage LDMOS [5, 6].

To address the first issue, we have compared the thin gate oxide (11.5nm) and thick gate oxide (60nm) LNDMOS hot carrier degradation results as shown in Fig.1 (b). The HC degradation has been significantly reduced in thick gate oxide LNDMOS. The main reason for the reduction may be due to drift region oxide thickness. Based on the results, we proposed a new LDMOS structure in a BCD technology that improves HC degradation without sacrificing the device breakdown voltage or Rdson [1]. The process to form the thick oxide in drift region-I in the LNDMOS is the same as to form thick gate oxide MOSFET, so only a layout change is required. The 11.5nm gate oxide thickness in the channel region remains the same for both LNDMOS structures. The maximum lateral electric field Emax in drift region-I would be reduced by over 94% if the oxide thickness increased to 60nm from 11.5nm based on our calculation. TCAD simulations clearly show that impact ionization rate for the 30V LNDMOS with the thick oxide in drift region-I has been significantly reduced, and also its peak location has been pushed away from the surface into the bulk of the silicon within drift region-I as shown in Fig.2(b).

For the second issue, we demonstrated a modified SiN barrier layer which can improve device hot carrier performance in the LDMOSFET. We show experimentally that using a barrier layer of SiN or SiON which is engineered to have a relatively high refractive index (RI) and electrical conductivity can reduce the BEOL effect on hot carrier performance. Increasing the SiH4 flow rate during deposition increases the film’s RI and also its electrical conductivity [9]. The increased electrical conductivity of the SiN barrier layer allows charge from plasma processing to be dissipated into the silicon. At 4000C, a typical BEOL dielectric deposition temperature, the conductivity of the SiN barrier layer is much higher. Thus, the SiN barrier layer can reduce the PPID for the oxide in drift region resulting in reduced HC degradation.

The HC Idlin degradation for the LNDMOS device with thick oxide in drift region and high RI SiN or SiON barrier layer has been significantly reduced to less than 1/3 the degradation observed in the standard LNDMOS as shown in Fig.2 (a). The reduced HC Idlin degradation is about 68% due to the thick oxide in drift region-I, and about 32% from the high RI SiN barrier layer. The HC Vth (threshold voltage) degradation exhibited very small degradation after the HC stress.

Our data shows self heating, caused by HC stress in the thick gate oxide HV LNDMOS, significantly affected Idlin/Rdson electrical parameter and HC degradation characteristic. The change in delay time between the removal of the HC stress after each stress cycle and the parameter measurement resulted in a significant difference in HC Idlin/Rdson degradation [6]. For a longer delay time, lower Idlin degradation was observed, see Fig.3 (a). The difference or recovery of degradation was mainly due to the self heating effect from Idlin degradation vs junction temperature change (Fig3.(b)) and temperature monitor data. The Idlin degradation from self heating effect seems to be more than from HC effect in packaged HV LNDMOS. In the final paper, we will include some methods to eliminate the self heating effect, and to separate the self heating and local HC injection effect.

Figure 1