bluuebunny/crossref_metadata_2025 huggingface dataset:
Advanced Acoustic Micro Imaging Applications: Deciphering Multiple Acoustic Echoes and Reflections
Authors: Komrowski Andrew J. , Curiel Luis A. , Sullivan Daniel J. D. , Nguyen Quang , Logan-Willams Lisa
Published: December 2020

The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.
IDDQ Testing—Conceptual Idea and Application in LED Integrated With IC Module
Authors: Joh Ng Joh , Hong Kong Boon
Published: December 2020

This paper presents IDDQ testing for LED integrated with IC module (ICM) circuit. To begin, brief introduction to IDDQ testing, the purpose and failure detectable with this method in CMOS IC context will be discussed. Then, the explanation will be focalized to ICM package and failure detectable with this method. A simulation and case study will be presented to show the usefulness of this testing. The results show that IDDQ testing is not only efficient in detecting intrinsic IC failure but also SMT process related problem like intermittent contact. Nonetheless, the discussion is merely conceptual and intended to give reader an idea of how IDDQ testing can be fully utilized in IC module testing, not the details of implementation.
Backside Application of Acoustic Micro Imaging (AMI) on Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) Packages
Authors: Curiel Luis A. , Komrowski Andrew J. , Sullivan Daniel J.D.
Published: December 2020

Acoustic Micro Imaging (AMI) is an established nondestructive technique for evaluation of electronic packages. Non-destructive evaluation of electronic packages is often a critical first step in the Failure Analysis (FA) process of semiconductor devices [1]. The molding compound to die surface interface of the Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) packages is an important interface to acquire for the FA process. Occasionally, with these packages, the standard acoustic microscopy technique fails to identify defects at the molding compound to die surface interface. The hard to identify defects are found at the edge of the die next to the bond pads or under the bonds wires. This paper will present a technique, Backside Acoustic Micro Imaging (BAMI) analysis, which can better resolve the molding compound to die surface interface at the die edge by sending the acoustic signal through the backside of the PBGA and PQFP packages.
A Novel Approach of Identifying Silicon Defects Using Passive Voltage Contrast Techniques Leading to Utilization of In-Line SEM Based Voltage Contrast Inspections to Drive Closed Loop Process Optimization and Defect Elimination
Authors: Fredrickson R. , Young R. , Cournoyer J. , Schmidt M.
Published: December 2020

The formation of silicon defects in 0.18um and smaller technology nodes has become a challenging device level defect to identify and eliminate. In this paper, we present a new method of passive voltage contrast that was initially used to locate silicon defects, experimental results revealing the key contributors to the formation of these defects, and a method of in-line identification by correlating SEM based in-line defect inspections to end of line SRAM fail bit maps. Silicon defects that form along the edge of an active region connect the source and drain with a low resistance leakage path that are successfully detected at later processing layers using voltage contrast techniques with a SEM based In-line inspection tool as well as after processing by using our method of passive voltage contrast. The systematic nature of this defect produces a consistent SRAM memory fail mode of single column fails. When these silicon defects are present, single column fails dominate the usual single and double bit fail modes. The physical location of the failing columns can be mapped back to the defect locations produced from the in-line inspections. This method was utilized to interpret experimental results in an effort to determine process parameters that produce silicon defects. It was found that STI depth plays a key role in the formation of these defects. Experiments were run where the depth was intentionally put at worst case so that the effectiveness of several alternative processes to repair the defects could be evaluated. It was shown that modulating the STI liner oxidation temperature had the largest effect compared to several other process parameters.
Time Domain Reflectometry Technique for Failure Analysis
Authors: Long Teoh King , Fern Ko Yin
Published: December 2020

In time domain reflectometry (TDR), the main emphasis lies on the reflected waveform. Poor probing contact is one of the common problems in getting an accurate waveform. TDR probe normalization is essential before measuring any TDR waveforms. The advantages of normalization include removal of test setup errors in the original test pulse and the establishment of a measurement reference plane. This article presents two case histories. The first case is about a Plastic Ball Grid Array package consisting of 352 solder balls where the open failure mode was encountered at various terminals after reliability assessment. In the second, a three-digit display LED suspected of an electrical short failure was analyzed using TDR as a fault isolation tool. TDR has been successfully used to perform non-destructive fault isolation in assisting the routine failure analysis of open and short failure. It is shown to be accurate and reduces the time needed to identify fault locations.
Multi-Layer Automatic Front Side Delayering Technique for Constructional Analysis
Authors: Coulson H. , Williamson K. , Shafrir Z. , Grimberg I. , Raz E.
Published: December 2020

Front side mechanical polishing of integrated circuits poses several technological complexities. This paper describes a unique automatic front side polishing technique, based on polishing at a shallow angle and exposing several layers, for NMOS/PMOS devices. This polishing technique is based on polishing at a very shallow angle up to 0.50 with plus or minus 0.1 micrometer accuracy to the target exposing several layers. The paper provides information on the several steps in the delayering process, namely deprocesing, chemical etching, and physical analysis. The benefits of the automatic polishing method developed are: exposing several metal layers without the need to deprocess to each layer separately, thus reducing both the polishing and the analysis time; the polishing can be stopped at any specific layer; direct and simultaneous measurements of structure overlays; direct inspection of embedded defects; and reducing artifacts associated with the etching process such as oxide steps, over etch, differential etching.
Advanced Mounting System and Method: To Establish and Maintain Predictable and Accurate Grind Plane Reference for Solder Joint Cross-Section Processing
Authors: McDonald Todd , Repko Thomas A.
Published: December 2020

Today's smaller structures, increasing standards and automation, amplify the demand for accurate and reliable cross-section mounting and grinding processes. This article presents an advanced and operated, finger adjustable, surface mount component fixturing device directly addressing these problems by holding components aligned during the encapsulation and grinding processes with greater accuracy, stability, and robustness. In the advanced method, samples are milled out of the PCB, but instead of using clips to hold the PCB, advanced mounting fixtures were employed to hold components in a true parallel and straight state, gripping the package edges and not the PCB. This advanced method for mounting and grinding cross-section samples is significantly more accurate and reliable for results establishing and maintaining the planarity of samples. When properly used, more accurate, consistent results will be achieved, and less data will be lost when compared to results of samples processed using regular mounting and grinding methods.
Inductive Operating Life Stress Metal Breakdown Mechanism
Authors: Gillette Bruce
Published: December 2020

Experimental devices in a deteriorated state were encountered after 168 hours of inductive operating life stress, (IOL) testing. A metal grain boundary breakdown mechanism was found during the analysis of the device, which was creating a low resistance current path between terminals. The AlSiCu top metal was breaking down along the grain boundaries. In addition there was alloying of the Aluminum into the underlying silicon. This alloying was creating a short to the gate, source, and drain. Several variations in the metal stack, testing conditions, number, and dimensions of bond wires die size and mold compound were evaluated to better understand the cause of the inability to withstand IOL stress and to provide a process solution. The prevention of the AlSiCu front metal grain boundary breakdown during inductive life stress testing required a die size, bond wire dimension, and testing condition change to meet the performance specification. This change resulted in a reduced grain boundary breakdown and consequently prevented Al grain boundary breakdown, TiW barrier breakdown, and Al alloy spiking. The die change and modified testing conditions resulted in a successful pass through the IOL stress testing.
Coupling C-AFM with Nanoprobing Technique for Further Junction Leakage Analysis
Authors: Shen Cha-Ming , Chuang Tsan-Chen , Huang Chen-May , Lin Shi-Chen , Chang Jie-Fei
Published: December 2020

With the evolution of advanced process technology, failure analysis has become more and more difficult because more defects are of the non-visual type (very tiny or even invisible defects) from new failure mechanisms. In this article, a novel and effective methodology which couples the conductive atomic force microscope (C-AFM) with nano-probing technique is proposed to reveal some particular failure modes which were not observable and difficult to identify with traditional physical failure analysis techniques. The capability of coupling C-AFM with nano-probing technique is used to distinguish cases which suffer general junction leakage or gate leakage from those that form the fake junction leakage or gate leakage cases. C-AFM can detect the abnormal contacts quickly, and nano-probing could provide the precise electrical characteristic further. Then, combining these variant measuring results, the favorable tactics can be adopted to deal with different states.
Laser Based Defect Localization for the Failure Analysis of Advanced Product
Authors: Cheng W.Y. , Chiu T.Y. , Lee Jon C. , Chiou J.Y.
Published: December 2020

Emission microscopy have been used for failure analysis (FA) defect isolation. But for advanced products, the working voltage of chip is getting smaller, thus many emission spots from normal transistors will be observed, which indeed affects the judgment on the emission spots from killer defects and increases the FA difficulty. Laser scanning microscope (LSM)-based techniques have been powerful defect isolation methods for many years. In this study, Checkpoint Infrascan 200TD, a laser-based tool, is used to perform defect localization. Here, thermally induced voltage alteration and optical beam induced resistance change are used to get defect locations. The study demonstrates three FA cases with 80nm/90nm technologies; metal direct short, poly leakage, and contact high resistance are also found in these cases. It is concluded that, by the selection of control parameters, Infrascan 200TD provides several capabilities of failure site localization and can be applied to different failure modes.
Enhanced Detection Sensitivity with Pulsed Laser Digital Signal Integration Algorithm
Authors: Quah A.C.T. , Phang J.C.H. , Koh L.S. , Tan S.H. , Chua C.M.
Published: December 2020

This paper describes a pulsed laser induced digital signal integration algorithm for pulsed laser operation that is compatible with existing ac-coupled and dc-coupled detection systems for fault localization. This algorithm enhances laser induced detection sensitivity without a lock-in amplifier. The best detection sensitivity is achieved at a pulsing frequency range between 500 Hz to 1.5 kHz. Within this frequency range, the algorithm is capable of achieving more than 9 times enhancement in detection sensitivity.
Nondestructive Method for Detecting Solder Defects at the Second Level Interconnect Using 3D X-Ray Tomography (uCT)
Authors: Toth Frank , Shade Gary F.
Published: December 2020

Today's printed circuit assemblies comprise of several layers with components populated on both sides of the PCBs. This presents challenges to conventional 2D nondestructive X-ray techniques due to shadowing and absorption of the x-ray energy. Tilting of the samples while imaging helps to get around this problem, however, often it might not always be adequate. This article proposes a non-destructive method for detecting solder defects at the second level interconnect using 3D X-ray tomography. A total of 6084 solder joints of 0.8mm and 0.5mm pitch BGAs were analyzed. Correlation between dye stain and package pull analysis and 3D-uCT X-ray revealed a 100% correlation. Virtual cross sections obtained using 3D x-ray tomography methods showed that it is possible to evaluate non-destructively the solder joint failure mode "H" known as "head-pillow or snowman" at the second level interconnect.
Development of the Polishing Technique for the Observation of the Intermetallic Compound at Solder Joint
Authors: Kongsubto Prong , Kongwudthiti Sirarat , Santipruksawong Nuannapa , Tippayamontri Jinusda , Promket Tewarit , Singsa Yaowalux
Published: December 2020

The monitoring of intermetallic compound (IMC) at solder joints has become more important recently because it is understood that IMC thickness and composition are the factors which determine the quality and reliability of solder joints. Normally it is quite difficult to view IMC optically due to its small (nanometer scale) thickness so scanning electron microscope (SEM) imaging is required to perform the observation. However, the most important factor for successful observation is the sample preparation, the grinding, polishing, and etching process in particular. Therefore, in this work we will discuss our experiments to develop an effective sample preparation technique to facilitate the observation of the IMC at the solder joint. Proper sample preparation will provide a good contrast between the IMC and surrounding metals under the SEM. We used the following 2 sample preparation techniques for ease of IMC observation: Fine polishing process: Polishing the sample with diamond compound followed by silica. Acid etching process: Etching the sample in HNO3 solution. This process is relatively simple and takes less time than polishing but acid etching will damage the solder so that this method is not suitable if analysis of the solder ball is also needed.
Translating Yield Learning Into Manufacturable Designs
Authors: Chowdhury Vijay , Rahim Irfan , Yu Ada , Venkitachalam Girish
Published: December 2020

Improving semiconductor yield is a multi-dimensional process that must include design, fabrication, and test aspects. Incorporating design-for-manufacturability (DFM) concepts needs to include prior and ongoing learning and experience on what worked and what did not. As feature sizes shrink beyond 130nm, it is possible to identify another class of failures that is more systematic and related not to manufacturing defects but to DFM marginalities related to layout. In this article, it is shown that DFM can also help reduce design sensitivity to process variations. Examples of these failure modes and the lessons learnt are listed: relaxed design rules for repeated patterns, relaxing design rules to reduce yield loss, and special considerations for analog circuit layout.
Soft Defect Localization Technique for Design and Debug on DRAM Devices
Authors: Versen Martin , Diaconescu Dorina , Touzel Jerome
Published: December 2020

A functional fail of a DRAM is analyzed by using an analog output of the device as an input signal of a microscope. Local heating by an IR laser changes the pass/fail behavior and thus the analog output of the DRAM. Although the observed spots do not belong to the physical defect, they give a starting point for further electrical analysis leading to the root cause of the failure. The paper will present a case study on a state-of-the art DRAM device failing with a timing problem. Especially the test aspects as well as the setup for the temperature dependent localization will be described. Finally an interpretation of the results will be proposed.
Three-Dimensional Nanometric Sub-Surface Imaging of a Silicon Flip-Chip Using the Two-Photon Optical Beam Induced Current Method
Authors: Ramsay E. , Serrels K. A. , Thomson M. J. , Waddie A. J. , Warburton R. J. , Taghizadeh M. R. , Reid D.T.
Published: December 2020

By implementing two-photon optical-beam-induced current microscopy using a solid-immersion lens, imaging inside a silicon flip chip is reported with 166nm lateral resolution and an axial resolution capable of resolving features only 100nm in height.
Effect of Inter-Die Adhesive Profile on the Integrity of Die Surface in Die Stacking Package
Authors: Flores Christopher C. , Aspera France B.
Published: December 2020

As the number of dice stacked within a microelectronic package increases, the need to maintain die surface integrity also increases. In this paper, one assembly packaging-related rootcause mechanism about passivation-metal damage (PMD) will be featured. The profile of inter-die adhesive was found to play an important role to maintain the integrity of die surface as more dice are stacked in a microelectronic package. Recommended solution to prevent this type of failure will be discussed.
A Novel Technique for Determining the Location of a Hermetic Leak in a ‘Metal Can’ (TO-x) Package
Authors: Nail Carl
Published: December 2020

Root-cause analysis of hermetic leak failures is complicated by the difficulty in isolating the leak location. Standard dye penetrant inspection is not consistently successful. The addition of pressure to the dye penetrant, followed by metallographic mounting and preparation, and subsequently followed by vacuum storage, greatly enhances the visibility of the dye and more effectively decorates the leak location.
Gradient Thermal Analysis by Induced Stimulus
Authors: Colvin Jim
Published: December 2020

In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or ebeam to induce a parametric shift, which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. SIFT (Stimulus Induced Fault Test), RIL (Resistive Interconnect Localization) and SDL (Soft Defect Localization) can identify anomalies functionally using induced thermal gradients to the metal but does not address how to analyze embedded temperature sensitive defects inaccessible to the laser. 1,2,3,4 Stacked die and similar 3 dimensional (3D) devices complicate the analysis requiring destruction/removal of one or more die. This paper will show how to create quantifiable thermal gradients to a defect and triangulate the location of the defect in 1, 2, and 3 dimensions as follows: 1. Apply a differential temperature gradient across the device in each of the X,Y, and Z-axes. The defect is localized based on its measured response in the gradient as the gradient sweeps across. 2. Induce a gradient with a laser and use the measurement of DC power required to relate the distance to the defect from various locations in relation to a heat sink. 3. Measure the time of flight of the thermal propagation to a defect from known laser positions to triangulate the location of the defect.
Software Enhanced Time Resolved Laser Assisted Device Alteration with a Non-Pulsed Laser Source
Authors: Erington Kent , Asquith John , Bodoh Dan
Published: December 2020

We describe a technique that is used to obtain timing information from laser assisted device alteration (LADA). The technique uses a non-pulsed laser scanning microscope to obtain timing information with a temporal resolution on the order of microseconds. Custom software is used to extract the timing information from the LADA images.
Near-Infrared Microscopy in Semiconductor Failure Analysis Applications
Authors: Davis Thomas B. , Reagan Robert , Sun Yangyang , Jiang Tom
Published: December 2020

There has been ample discussion concerning the use of near infrared microscopy (NIR) in fields such as medical, materials science, and more recently in applications aimed toward micro-electro-mechanical systems (MEMS); however, little attention has been paid to the application of NIR microscopy in the verification and failure analysis of semiconductor memory devices. This paper will present a discussion of NIR and laser scanning confocal near-infrared microscopy, sample preparation for NIR microscopy, and emphasize examples of laser scanning confocal NIR microscopy in the measurement and failure analysis of silicon samples typical to the semiconductor industry.
Case Study: Failure Analysis of Functional Shmoo Hole with Laser Voltage Probing
Authors: Lee S.H. , Lee Y.W. , Lee K.T. , Choi C.Y. , Shin H.W. , Ng Yin S. , Lundquist T.R.
Published: December 2020

Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.
The Method for Retaining an Intermittent Electrical Failure Signature during the Interconnect Immobilization Process throughout Failure Analysis
Authors: Schuchman Julie , Willis Julie
Published: December 2020

This paper deals primarily with the difficulties and solutions to scanning transmission electron microscope (STEM) sample preparation by dual beam focused ion beam. Approximately twenty major challenges were encountered spanning hardware, software, and material sample preparation. The main focus is upon the variety of challenges which are encountered in trying to implement automated STEM and TEM sample fabrication with minimal operator input and the engineering solutions implemented to overcome these challenges. The automated STEM script has evolved significantly from the first generation attempt and is described in more detail in this paper. The mechanical, software, and materials challenges encountered are also presented. The paper highlights a mechanical issue with the ion aperture motor mechanism, which required extensive troubleshooting to fully diagnose and correct. A long standing software routine had to be modified to fully enable script automation by extending the beam dwell time of the automatic brightness contrast routine.
Magnetic Microscopy for 3D Structures: Use of the Simulation Approach for the Precise Localization of Deep Buried Weak Currents
Authors: Infante Fulvio , Gomes Rodolphe , Perdu Philippe , Battistella Fabien , Annereau Sebastien , Lewis Dean
Published: December 2020

With the innovations in packaging technologies which have taken place over the last decade, new assemblies often include an increasing number of dies inside a single package. This is exactly what was predicted by the More than Moore’s paradigm: as the integration of ICs increases, the heterogeneity of the devices found in a single package increases. As a result, the number of potential failures which can appear at assembly level has increased exponentially. At present, no technique has been able to precisely localize defects which are deep inside a complex package. For this reason, a new technique for failure localization for three-dimensional structures is needed. In this paper the technique proposed, based on the coupling of magnetic measurements and simulations, is applied to a three-dimensional structure to precisely localize the current path which is buried deep inside it. A new method, based on parameters fittings of magnetic simulations, is then applied in order to accurately evaluate the distance between the current and the sensor.
Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis
Authors: van Hassel J.G. , Zhang Xiao-Mei
Published: December 2020

Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.
Activation Energy Analysis of Dark and Laser Illuminated I-V Characteristics of Thin-Film Poly Silicon Solar Cells
Authors: Boostandoost M. , Kerst U. , Boit C.
Published: December 2020

The temperature dependence of photocurrent of polycrystalline Si (poly-Si) thin-film solar cells on glass with interdigitated mesa structure has been locally investigated using Infrared Light Beam Induced Current (IR-LBIC) in the temperature range of -25 to +70 °C. The temperature dependence of electrical characteristics of poly-Si thin-film solar cells in reverse bias has been also analysed and compared with the monocrystalline thin-film solar cells. The poly-Si solar cell shows a temperature coefficient (TC) for the photocurrent of around +0.8 and +0.6 %/°C in the grain interior and grain boundary, respectively. The activation energy of the reverse current and also the photocurrent due to the IR laser stimulation has been evaluated, which provide information about traps and their energy levels in the absorber layer of the poly-Si thin-film solar cell. The obtained average value of the activation energy associated with the photocurrent of the poly-Si cell suggests the existence of a shallow acceptor level at around 0.045 eV in the grain boundary and 0.062 eV in the grain interior of the absorber layer of the poly-Si thin-film solar cell. The activation energies of the reverse current for poly-Si and monocrystalline cells have been calculated when the device is biased at -1 and -2 V and the results compared with the activation energy of the saturation current obtained from extrapolation of the I-V curve in the SRH (Shockley-Read-Hall) regime. The results show strong voltage dependence. In both cases the activation energy of the reverse current decreases in the reverse bias voltage, approaching the values obtained from the photocurrent.
Improvement of Optical Resolution through Chip Backside Using FIB Trenches
Authors: Glowacki Arkadiusz , Helfmeier Clemens , Kerst Uwe , Boit Christian , Perdu Philippe
Published: December 2020

Optical spatial resolution improvement using local focused ion beam (FIB) assisted silicon material removal was investigated. Two types of test structures were chosen for imaging-resolution characterization to be able to use two ways of measuring resolution. Samples of various remaining bulk silicon thicknesses were prepared and characterized in terms of image quality and spatial resolution. The resulting remaining bulk Si thickness was measured using reflectance spectrometry. Images were acquired using halogen-lamp illumination and reflected light detection using a cooled Si-CCD detector. To investigate the image quality at various wavelengths, a set of interference band-pass filters was applied.
Energy-Dispersive X-ray Spectrometry Performance on Multiple Transmission Electron Microscope Platforms
Authors: Demarest James , Deeb Chris , Murray Thomas , Zhai Hong-Ying
Published: December 2020

Energy-dispersive X-ray spectrometry (EDS) is a key analytical tool aiding root cause determination in the failure analysis (FA) process. This paper looks at a number of analytical TEM microscopes currently in use in various facilities: microscope A, a STEM operated at 200kV; microscope B, a 300kV TEM; and microscopes C and D, both 200kV TEMs. EDS counts per unit time from multiple microscope platforms were examined. Microscope D demonstrated two orders of magnitude higher counts per unit time than the other three microscopes. Microscope D represents the state-of-the-art EDS analytical TEM configuration and has achieved this through a novel windowless EDS configuration which significantly increases the detector area (by about a factor of three) that receives X-rays generated from the sample.
Systematic Defect Identification through Layout Snippet Clustering
Authors: Tam Wing Chiu , Poku Osei , (Shawn) Blanton R. D.
Published: December 2020

Systematic defects due to design-process interactions are a dominant component of integrated circuit (IC) yield loss in nano-scaled technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that affect the product. This paper describes a method that uses diagnosis to identify layout features that do not yield as expected. Specifically, clustering techniques are applied to layout snippets of diagnosis-implicated regions from (ideally) a statistically-significant number of IC failures for identifying feature commonalties. Experiments involving an industrial chip demonstrate the identification of possible systematic yield loss due to lithographic hotspots.
Characterization of a Resistive Path to a Gate Node Using Tunneling Current Measurements
Authors: Howard Clifford , Subramanian Sam , Erington Kent , Mulder Randall , Tsang Yuk , Bartlett John
Published: December 2020

Advanced technologies with higher gate leakage due to oxide tunneling current enable detection of high resistance faults to gate nodes using a straight forward resistance measurement.
Novel Circuit Edit Solution for Bulk Copper Milling
Authors: Malik Tahir , Jain Rajesh , Meijer Ferdi , Velthof Tim
Published: December 2020

Focused Ion Beam (FIB) circuit edit (CE) has been playing a pivotal role in providing insight to ramp-up yield. Numerous IC fabrication processes inherently pose unique challenges to FIB circuit edit approaches. Copper (Cu) has been the material of choice for interconnects as technology features shrink to the 180 nm node and below. Thick copper planes are used for multiple reasons that are mentioned later. Milling through thick copper planes has been tremendously challenging and time consuming during FIB circuit edits. Proposed is a methodology to enhance the bulk Cu removal process at astounding etching rates while maintaining planarity.
Instant Solid Immersion Lens Creation in Silicon with a Focused Ion Beam – Comparing Refractive and Diffractive Methods
Authors: Scholz P. , Kerst U. , Boit C. , Kujawa T. , Lundquist T.
Published: December 2020

The theoretical fundamentals of diffractive solid immersion lenses (dSILs) were revised and adapted to a new application: the direct single-step chemistry-assisted creation of binary dSILs in silicon with a focused ion beam (FIB). Current results were able to prove the general functionality of this technique, but also showed the limitations still present. These limitations were identified; the underlying problems were analyzed and were addressed by optimizing several aspects of the process. The presented dSIL has a diameter of 150 ìm and is created in 15 minutes of processing time. It is designed for a sample thickness of 70 µm, which can be well adjusted if needed. For this sample thickness, the theoretical numerical aperture is about 2.5, offering a significant improvement in resolution. Furthermore a comparison of diffractive and refractive solid immersion lenses is presented, both created in a similar process. Apart from general aspects of dSILs and rSILs (refractive SILs), details of the designs presented in this work are compared. This leads to the insight of which method (dSIL or rSIL) has its advantages for which type of application.
3DIC Fault Isolation Using the OBIRCH Approach
Authors: Hsu Ming-Sung , Kuo Yian-Liang , Lin Yu-Ting , Huang Ru-Ying , Ku Min-Feng , Chang Chih-Horng
Published: December 2020

This paper uses an interesting specific case study to highlight the non-destructive fault isolation demonstration of 3DIC stacked dies applied the optical beam induced resistance change (OBIRCH) approach.
Addressing Stress-Memorization-Technology (SMT) Induced Defects
Authors: Kane Terence , Wang Yun Yu , Tenney Michael , Oldrey Richard , Villalobos Manuel , Sylvestri John , Tverskoy Genadi
Published: December 2020

High performance source/drain (S/D) stress-memorization technology (SMT) has been previously demonstrated to enhance electron mobility in leading edge SRAM NMOS designs. Dislocations initiating from SMT induced stacking faults cause electrical fails in the device. Transmission electron microscopy (TEM) results show that these dislocations can be reduced by controlling certain processing steps following SMT processing.
Electroless Cobalt Plating on Copper Structures for Nano-Probing
Authors: Chuang Wen-Hsien , Zhong Ting , Niu Baohua
Published: December 2020

As device dimensions continue to shrink, process defects tend to become more subtle. For most failure analysis (FA) studies, it is important to identify the defect location for the subsequent material analysis. To achieve this, nano-probing has been widely used in the FA community. Copper (Cu) contacts posed a significant challenge to nano-probing since Cu is soft and tends to deform during measurements. In addition, Cu oxidizes quickly in air, increasing contact resistance significantly between the probes and devices. This paper introduces electroless cobalt (Co) plating on Cu contacts for nano-probing to overcome these technical problems. As Cu is soft and oxidized quickly in air, the technique presented in this paper provides a technical solution for nano-probing on Cu contacts. With carefully characterized Co plating time, this technique can be used not only on Cu contacts but also on Cu interconnection.
CHIPSCANNER: Reverse Engineering Solution for Microchips at the Nanometer-Scale
Authors: Klingfus Joseph , Burcham Kevin , Rasche Martin , Borchert Thomas , Damnik Niklas
Published: December 2020

Chipscanning is the high-resolution, large-area, SEM image capture of complete (or partial) IC devices. Images are acquired sequentially in matrix-array fashion over an area of interest and large image mosaics are created from the collection of smaller images. Chipscanning is of keen interest to those involved with component obsolescence, design verification, anti-counterfeiting, etc. Chipscanning, and subsequent processing of the images, can also be used to reverse engineer an IC device. The reverse engineering process can be broken down into three main tasks; sample preparation, data collection, and data processing. We present practical insight into the data collection and data processing tasks and discuss an instrument platform uniquely suited for imaging such devices.
Advanced Physical Analysis Methodology for Yield and Reliability of 28-nm, Bulk-Si, Flip-Chip ICs Using SEM and Backside Deprocessing
Authors: Li Yuanjing (Jane) , Scott Steven , Marks Howard Lee
Published: December 2020

This paper presents a backside chip-level physical analysis methodology using backside de-processing techniques in combination with optimized Scanning Electron Microscopic (SEM) imaging technique and Focused Ion Beam (FIB) cross sectioning to locate and analyze defects and faults in failing IC devices. The case studies illustrate the applications of the method for 28nm flip chip bulk Si CMOS devices and demonstrate how it is used in providing insight into the fab process and design for process and yield improvements. The methods are expected to play an even more important role during 20-nm process development and yield-ramping.
Study of Si Crystal Defects by Chemical Preferential Etching and Its Application on Si Dislocation Defects Caused by Laser Spike Annealing (LSA)
Authors: Shuting Chen , Lihong Li , Anyan Du , Younan Hua
Published: December 2020

In this work, delineation of crystal defects in Si by preferential chemical etching (Wright etch) is discussed. Investigation of defects in Si wafers by preferential chemical etching enables the study of various types of crystal defects for large area defect distribution (up to full wafer) and root cause analysis. In the case of dislocation defects, the shapes of etch pits are different for different etching duration. We show the mechanism of the pit shape evolution under preferential etching and suggested the appropriate etching duration for defect type identification with inspection by optical microscopes. The dislocation delineation method has been applied to a case of functional failure of devices caused by abnormal process in Laser Scanning Annealing (LSA). It was shown that the distribution of dislocation defects depends largely on the direction of LSA scan direction. We discuss the relationship between dislocation defect distribution and the density and uniformity of the active-Si patterns as well as possible solutions for elimination of dislocation defects in LSA process.
Four Stages of Defect Creation in Epitaxial Structures: High Resolution X-Ray Diffraction and Transmission Electron Microscopy Characterization
Authors: Faleev Nikolai N. , Honsberg Christiana B. , Smith David J.
Published: December 2020

Different epitaxial structures have been studied by high-resolution x-ray diffraction and x-ray topography, Transmission Electron Microscopy and Atomic Force Microscopy to establish correlations between epitaxial growth conditions and crystal perfection. It was confirmed that epitaxial growth under initial elastic stress inevitably leads to the creation of extended crystal defects like dislocation loops and edge dislocations in the volume of epitaxial structures, which strongly affect crystal perfection and physical properties of future devices. It was found that the type of created defects, their density and spatial distribution strongly depended on growth conditions: the value and sign of the initial elastic strain, the elastic constants of solid solutions, the temperature of deposition and growth rate, and the thickness of the epitaxial layers. All of the investigated structures were classified by their crystal perfection, using the volume density of extended defects as a parameter. It was found that the accommodation and relaxation of initial elastic stress and creation of crystal defect were up to four stages “chain” processes, necessary to stabilize the crystal structure at a level corresponding to the deterioration power of particular growth conditions.
Non-Chemical Solder Bump Removal Technique for Repackaging Flip Chip ICs
Authors: Sutton Mauri , Geoghegan George , Schopen Kenneth , Kingma Kathleen , Castro Steve , Wesley Kyle , Yahl Jack , Soto Frank
Published: December 2020

In this paper we will discuss an empirically discovered technique to remove residual solder bumps or remnants using reflow and wicking to a gold plated surface rather than mechanical or chemical means. Extraction of flip chip ICs, for the purpose of repackaging, can leave bond pads in inconsistent and undesirable conditions such as 1) retaining remnants of the solder bumps or 2) damaged or eliminated pad metal caused by acid or mechanical means used to separate the IC from the board. These conditions hinder subsequent wire bonding and probe card use. Though other techniques have been found to be suitable at times, the technique described in this paper consistently leaves the bonding area in an acceptable, more predictable condition, as the bulk of the solder bump material is removed. This lends to a higher wire bonding success rate.
VIS-NIR LED Illumination in Backside Circuit Edit and Optical Probing Applications
Authors: Tan Shida , Livengood Richard H. , Scott Dane , Hallstein Roy , Pardy Pat , Giacobbe John
Published: December 2020

High resolution optical imaging is critical in assisting backside circuit edit (CE) and optical probing navigation. In this paper, we demonstrated improved optical image quality using VIS-NIR narrow band light emitting diode (LED) illumination in various FIB and optical probing platforms. The proof of concept was demonstrated with both common non-contact air gap lenses and solid immersion lenses (SIL).
Novel Failure Analysis Sample Preparation Techniques for PoP Packaging
Authors: Chooi Ng Sea , Hock Chor Theam , Thye Ma Choo , Tshin Khoo Poh , Bockelman Dan
Published: December 2020

Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.
Simulation Studies on Fluorine Spec Limit for Process Monitoring of Microchip Al Bondpads in Wafer Fabrication
Authors: Hua Younan , Rao Nistala Ramesh , Yang Yanjing , Zhao Siping , Shailesh Redkar
Published: December 2020

In wafer fabrication, Fluorine (F) contamination may cause fluorine-induced corrosion and defects on microchip Aluminum (Al) bondpads, resulting in bondpad discoloration or non-stick on pads (NSOP). Auger Electron Spectroscopy (AES) is employed for measurements of the fluorine level on the Al bondpads. From a Process control limit and a specification limit perspective, it is necessary to establish a control limit to enable process monitor reasons. Control limits are typically lower than the specification limits which are related to bondpad quality. The bondpad quality affects the die bondability. This paper proposes a simulation method to determine the specification limit of Fluorine and a Shelf Lifetime Accelerated Test (SLAT) for process monitoring. Wafers with different F levels were selected to perform SLAT with high temperature and high relative humidity tests for a fixed duration to simulate a one year wafer storage condition. The results of these simulation results agree with published values. If the F level on bondpad surfaces was less than 6.0 atomic percent (at%), then no F induced corrosion on the bond pads was observed by AES. Similarly, if the F level on bond pad surfaces was higher than 6.0 atomic per cent (at%) then AES measured F induced corrosion was observed.
Surface Microstructure Evolution Upon Silicidation of Ni(Pt) and the Different Responses to Metal Etch
Authors: Qin Wentao , Iyer Dorai , Morgan Jim , Casteel Carroll , Watkins Robert , Crowder Rod , Thomason Mike
Published: December 2020

Ni(5 at.%Pt ) films were silicided at a temperature below 400 °C and at 550 °C. The two silicidation temperatures had produced different responses to the subsequent metal etch. Catastrophic removal of the silicide was seen with the low silicidation temperature, while the desired etch selectivity was achieved with the high silicidation temperature. The surface microstructures developed were characterized with TEM and Auger depth profiling. The data correlate with both silicidation temperatures and ultimately the difference in the response to the metal etch. With the high silicidation temperature, there existed a thin Si-oxide film that was close to the surface and embedded with particles which contain metals. This thin film is expected to contribute significantly to the desired etch selectivity. The formation of this layer is interpreted thermodynamically.
Two-Photon-Absorption-Enhanced Laser-Assisted Device Alteration and Single-Event Upsets in 28 nm Silicon Integrated Circuits
Authors: Serrels K.A. , Leslie N. , Lundquist T.R. , Vedagarbha P. , Erington K. , Bodoh D. , Farrell C. , Reid D.T.
Published: December 2020

By inducing two-photon absorption within the active layer of a 28nm test chip, we demonstrate nonlinear laser-assisted device alteration and single-event upsets by temporarily perturbing the timing characteristics of sensitive transistors. Individual qualitative and quantitative evaluations are presented for both techniques, with lateral resolutions demonstrated with sub-100nm performance. A simplistic signal response rate comparison analysis of these two technologies is also presented.
Physical and Electrical Performance Comparison of Identical 28 nm Qualcomm Telecommunication Die Produced by Samsung and TSMC
Authors: Riley Anton , Zumwalt Sean , Dixon-Warren Sinjin , Tomkins Gary
Published: December 2020

In today’s competitive semiconductor environment, product performance and market timing has never been more valuable. Design IP, speed to market, and taking advantage of the most advanced technology are three ways fabless companies can maintain an advantage over the competition. Foundries target these demands by offering superior support, competitive technology, and rapid development cycles. Using the advanced tool suites of SEM, FIB, TEM, and Atomic Force NanoProbing (AFP) the failure analysis community now has the ability to investigate and compare foundry performance on the device level. The 28 nm LP Qualcomm “SHELBY” die is dual-sourced from both Samsung and TSMC, and is the primary die in the MDM9215 4G/LTE modem used in several smartphones. This represents a unique case of leading technology, available to the public, to qualify for electrical performance on the device level using the AFP and the corresponding physical differences using SEM and TEM. These advanced FA techniques were employed and were able to identify manufacturing differences between foundries. They were then used to relate the physical variations with the electrical device performance. The HG11-N3877 fabricated by TSMC and the HG11-N9204 fabricated by Samsung were the subjects of this comparison (see Error! Reference source not found.). The investigation located spatial and geometric variations of the SRAM devices using cross sectioning and TEM imaging. This was followed by Electrical Characterization of multiple SRAM Cells using the AFP. The electrical measurements showed clear differences in device parameters. These differences highlight manufacturing process differences between the two companies that could directly relate to chip performance.