bluuebunny/crossref_metadata_2025 huggingface dataset:
Recent Advances in On-disk Viscous Micropumps
Authors: Al-Halhouli Ala'aldeen T.
Published: October 2015

This work surveys recent advances of experimental and analytical development progress of the on-disk viscous micro-pumps: spiral channel, single disk, and double disk micropumps. These micropumps have attractive advantages for handling particle-laden fluids which make them key components in laboratory-on-a-chip applications. This study builds upon existing reviews and reports on the on-disk viscous micropump concept and analytical and experimental tests. It also presents a general analytical solution that estimates for the combined effect of operational and geometrical design parameters on the flow performance of on-disk viscous micropumps. This model enables microfluidic systems designers and developers to predict flow rates and pressures according to certain geometrical or operational conditions. Quantitative comparison and verifications are provided in tabular and graphical forms.
Microactuators for Fluidic Applications: Principles, Devices, and Systems
Authors: Adamovic Nadja , Giouroudi Ioanna , Matovic Jovan , Djinovic Zoran , Schmid Ulrich
Published: October 2015

Much effort in microfluidics research has been aimed at designing microscale pumps, valves, switches, dispensers, mixers, filters, separators, and so on, which have a major role in the development of innovative systems like chemical process control, bioanalytical devices, medical drug delivery systems, environmental control, and others. Most of these microfluidic devices have one thing in common: the need for precise manipulation and control of small amounts of fluids.

MEMS/NEMS research is continuously opening up new knowledge on modeling approaches, novel materials, and MEMS/NEMS processing technologies that stimulate and accelerate the development of new actuation principles and novel actuator configurations.

This review paper presents research work on different actuation techniques that are used for the whole range of microfluidic applications. It covers thermomechanical and electrochemical actuation principles, as well as actuation induced with external electric or magnetic fields. It presents a brief explanation of the operating principle of each type of actuator, actuator configuration, its main characteristics, like power consumption, operational voltage, frequency range, and working fluids, and a discussion of comparisons among different actuation schemes.

This study compiles and provides some basic guidelines for selection of the actuation schemes that are currently implemented in microfluidic devices.
Reliability of Ceramic Column Grid Array (CCGA717) Interconnect Packages Under Extreme Temperatures for Space Applications*
Authors: Ramesham Rajeshuni
Published: October 2015

Ceramic column grid array packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performance, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, flight avionics, and payload electronics. As these packages tend to have less solder joint strain relief than leaded packages, the reliability of CCGA packages is very important for short-term and long-term space missions.

CCGA interconnect electronic package printed wiring boards (PWBs) of polyimide have been assembled, inspected nondestructively, and subsequently subjected to extreme temperature thermal cycling to assess the reliability for future deep space, short- and long-term, extreme temperature missions. In this investigation, the employed temperature range covers from −185°C to +125°C extreme thermal environments. The test hardware consists of two CCGA717 packages with each package divided into four daisy-chained sections, for a total of eight daisy chains to be monitored. The CCGA717 package is 33 mm × 33 mm with a 27 × 27 array of 80%/20% Pb/Sn columns on a 1.27 mm pitch. The resistance of daisy-chained, CCGA interconnects was continuously monitored as a function of thermal cycling. Electrical resistance measurements as a function of thermal cycling are reported and the tests to date have shown significant change in daisy chain resistance as a function of thermal cycling. The change in interconnect resistance becomes more noticeable as the number of thermal cycles increases. This paper will describe the experimental test results of CCGA testing under extreme temperatures. Standard Weibull analysis tools were used to extract the Weibull parameters to understand the CCGA failures. Optical inspection results clearly indicate that the solder joints of columns with the board and the ceramic package have failed as a function of thermal cycling. The first failure was observed at the 137th thermal cycle and 63.2% failures of daisy chains have occurred by about 664 thermal cycles. The shape parameter extracted from the Weibull plot was about 1.47, which indicates the failures were related to failures that occurred during the flat region or useful life region of the standard bathtub curve. Based on this experimental test data, one can use the CCGAs for the temperature range studied for ∼100 thermal cycles (ΔT = 310°C, 5°C/minute, and 15 min dwell) with a high degree of confidence for high reliability space and other applications.
Qualification of Bonding Process of Temperature Sensors to Extreme Temperature Deep Space Missions**
Authors: Ramesham Rajeshuni , Kitiyakara Amarit , Redick Richard , Sunada Eric T.
Published: October 2015

A process has been explored based on state of the art technology to bond a platinum resistance thermometer (PRT) on potential aerospace materials such as a flat aluminum surface and a flexible copper tube to simulate coaxial cable for flight applications. Primarily, PRTs were inserted into a metal plated copper braid to avoid stresses on the sensor while attaching the sensor with braid to the base material for long duration deep space missions. Appropriate pretreatment has been implemented in this study to enhance the adhesion of the PRTs to the base material. The NuSil product was chosen in this research to attach the PRT to the base materials. The resistance (∼1.1 kΩ) of PRTs was continuously electrically monitored during the qualification thermal cycling testing from −150°C to +120°C and −100°C to −35°C. The test hardware was thermal cycled three times the mission life per JPL design principles for the JUNO project. No PRT failures were observed during and after the PRT thermal cycling qualification test for extreme temperature environments. However, there were some failures associated with staking of the PRT pigtails as a result of the thermal cycling qualification test.
Response Time Analysis of an Active Cooling Method for 3D-ICs Utilizing Multidimensional Configured Thermoelectric Coolers
Authors: Phan Huy N. , Agonafer Dereje
Published: October 2015

Heat dissipation of 3D-ICs systems is highly nonuniform and nonunidirectional due to many factors such as power architecture and transistor packing density available on the chip. In this study, the cooling response time analysis of an active cooling method to cool a 25 W stack-dice to approximately 13°C within 400 s utilizing multidimensional configured thermoelectric coolers will be presented. The results obtained from this study are beneficial not only to 3D-ICs with or without core hopping architecture cooling, but also to thermal cycling of ICs in general, utilizing thermoelectric modules to obtain rapid and precision ramping control and lower setup costs compared to a conventional thermal chamber.
Effects of Nonuniform Base Heating on Single Stack and Multi-Stack Microchannel Heat Sinks Used for Electronics Cooling
Authors: Hegde Pradeep , Seetharamu K.N.
Published: October 2015

Numerical investigations with regard to the thermal characteristics of water cooled single stack and multistack microchannel heat sinks subjected to nonuniform base heating are conducted. Nonuniformities in base heating are accomplished by applying gradually increasing and gradually decreasing base heat fluxes with respect to coolant flow direction in the heat sink. The effects of heat concentration upstream, downstream, and in the center half of the microchannel heat sinks (similar to a hotspot) are also studied. Both parallel flow and counter coolant flow conditions in the heat sink are considered and the results are compared. The results are presented in the form of base temperature distribution and heat sink thermal resistance. The finite element method is used for the analysis.
Thermomechanical Stresses in Copper Films at Elevated Temperature
Authors: Lederer Martin , Zarbakhsh Javad , Huang Rui , Detzel Thomas , Weiss Brigitte
Published: October 2015

Thermomechanical stresses in metallic films are a root cause for material fatigue which limits the lifetime of electronic devices. Since the yield stress of metals is temperature dependent, plastic deformations during thermal cycling are increased at elevated temperature. This effect reduces the reliability of electronic parts. In order to investigate this problem, a 20 μm thick copper film was deposited on a silicon wafer. After annealing at 400°C, the sample was exposed to thermal cycles in the temperature range between room temperature and 600°C. The different values for the coefficient of thermal expansion of copper and silicon lead to a curvature of the sample. The wafer curvature was measured by a multilaser beam method. On the basis of the experimental results, a new theoretical model was developed that describes the stress evolution in the film during thermal cycling. In this investigation, the relation between wafer curvature and film stress is calculated by analogy to a model by Freund which is an improvement to the well-known Stoney formula. In addition to the elastic response, the new model considers plasticity of the copper film as well as temperature dependence of creep. It is demonstrated that the model can describe the experiment well and thus thermomechanical stress in copper films.
Application of a Flow Optimizer in a Limited Space to Increase Series Fan Performance
Authors: Jilesen Jonathan , Harrison Howard , Lien Fue-Sang , McCumber Darryl
Published: October 2015

The performance increase of cooling for a 1U SunFire 4100 server through the introduction of multiple flow optimizers is investigated in this article. We found that the power consumption of cooling fans could be decreased by 17–33% depending on operating conditions. The use of flow optimizers was found to reduce noise produced by cooling fans by at least 5.3 dB(A). We also discuss the use of the increased performance to increase thermal head room by increasing the flow rate of cooling air by 6.5–20.4%.

In addition, we found that a primary fan used with an exit stator allowed the overall fan module length to be reduced without a loss in performance. Reducing the length allowed the flow optimizers to fit into the standard 56-mm space previously occupied by the original series fans. CFD analysis was performed to better understand the effect of this stator on airflow.
Analysis of Refrigeration Requirements of Digital Processors in Subambient Temperatures
Authors: Park Won Ho , Ali Tamer , Ken Yang C. K.
Published: October 2015

The total power consumption for high-performance computing systems is a serious concern for designers of integrated circuits and systems. It is well known that cooling the operating temperature results in reduced electronic power and/or speed gains. However, total power dissipation includes both electronic power and the refrigeration power. This study explores the optimal operating temperatures and the amount of total power reduction at subambient temperatures. This paper presents a realistic system-level model that includes both the electronic and the refrigeration systems. Analysis using the model shows the optimal temperature, and sensitivity to parameters of the electronic and refrigeration systems. For instance, a system with 50% electronic leakage and a minimum refrigeration coefficient of performance (COP) of 3.3, the optimized design operates at 8°C and offers a 44% power reduction over the noncooled design. Analysis also shows that temperatures near that of domestic freezers is nearly optimal for digital processors and such cooling may be viable approach for current and future electronics due to the scaling trends of integrated circuits technology.
Integration of Electrografted Layers for the Metallization of Deep TSVs
Authors: Raynal F. , Mevellec V. , Frederich N. , Suhr D. , Bispo I. , Couturier B. , Truzzi C.
Published: October 2015

This paper describes production-readiness level of electrografted (eG) and chemical grafted (cG) layers deposited on a wide range of through silicon via (TSV) dimensions. Three layers are required to achieve via metallization: eG insulator, cG barrier, and eG copper seed.

Complete characterization of each layer of the stack has been achieved, including electrical and mechanical properties. Impact on the 3D-IC design space of the electrografting nanotechnology optimized for highly conformal growth of TSV films is discussed.

Four chemical baths are required to achieve the deposition of the three layers, shelf life, and bath monitoring strategy of each chemistry being presented in the last part of the paper. Some preliminary results of copper plating directly on top of the cG barrier are also reported.
Next Generation System in a Package Manufacturing by Embedded Chip Technologies
Authors: Boettcher Lars , Manessis D. , Karaszkiewicz S. , Ostmann A. , Reichl H.
Published: October 2015

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and thereby the third dimension will be available for further layers or assemblies.

This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial quad flat packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm, and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (resin coated copper) layers by using vacuum lamination.

The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10 × 10 mm2. All embedded chip QFN packages at the prototype level are manufactured in 250 × 300 mm2 panels.
Development of MEMS Power Sensor Package
Authors: Kim Bruce C. , Kasim Rahim
Published: October 2015

This article presents the design, fabrication, and packaging of advanced MEMS in high power applications. The advanced MEMS devices are used as a power sensor to detect high current in a distributed power network. We designed and fabricated an M × N array of low power MEMS switches to handle high power which are mass actuated by an external magnetic field. The array of MEMS devices has been packaged in a conventional package and testing was performed to validate its operation. The switching time was very compatible with the existing solid state switches with much higher order of power capability.
Advances in WLCSP Technologies to Enable Cost Reduction
Authors: Chilukuri R. , Anderson R. , Rogers B. , Syed A.
Published: October 2015

This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows (CSPX3 and CSPX2). This paper examines material options for these structures, with a focus on the redistribution layer and solder alloys. Package level and board level reliability data along with a description of the failure modes are presented.
Qualification of Fiber Optic Cables for Martian Extreme Temperature Environments†
Authors: Ramesham Rajeshuni , Roberts William T. , Lindensmith Christian A. , Rainen Richard
Published: October 2015

Thermal cycling qualification and verification (TCQV) of fiber optic cables (FOC) for the Mars Science Laboratory (MSL) flight project has been performed to enhance the mission assurance. The qualification of FOCs has been carried out to meet MSL project requirements. The FOCs were of significant interest in this study in that they survived three times (3×) the total number of expected thermal diurnal cycles resulting from all environmental and operation exposures occurring over the life of the flight hardware including all relevant ground operations and mission phases. Qualification was performed by subjecting FOC hardware to extreme temperature environments and assessing any structural failures or degradation in optical transmission due to overstress or thermal cycle fatigue. We are reporting the qualification results of FOCs for MSL project in this letter.
Determination of Electric and Magnetic Properties of Commercial LTCC Soft Ferrite Material
Authors: Blaž Nelu , Marić Andrea , Radosavljević Goran , Mitrović Nebojša , Atassi Ibrahim , Smetana Walter , Živanov Ljiljana
Published: October 2015

This paper offers an effective, accurate, and simple method for permittivity and permeability determination of an LTCC (low temperature cofired ceramic) ferrite sample. The presented research can be of importance in the fields of ferrite component design and application, as well as for RF and microwave engineering.

The characterization sample is a stack of LTCC tapes forming a toroid. Commercially available ferrite tape ESL 40012 was used and standard LTCC processing was applied for the sample fabrication. For the first time, the electrical properties of a ferrite toroid sample of ESL 40012 LTCC ferrite tape is presented at various frequencies. The electrical properties of LTCC ferrite materials, permittivity and specific resistivity, are shown in a frequency range from 10 kHz to 1 MHz using the capacitive method. The hysteresis properties of this material are also determined. B-H hysteresis loops were measured applying a maximum excitation of 2 kA/m and frequencies of 50 Hz, 500 Hz, and 1000 Hz.

Permeability is determined in the frequency range from 10 kHz to 1 GHz and a characterization procedure is divided in two segments, for low and high frequencies. Low frequency measurements (from 10 kHz to 1 MHz) are performed using LCZ meter and discrete turns of wire, while a short coaxial sample holder and vector network analyzer were used for the higher frequency range (from 300 kHz to 1 GHz).

In addition, another important factor required for the practical design of devices is presented, the temperature variation of the permeability dispersion parameters.
Electrophotographic Printing of RFID Antenna Coils on Cofired and Postfired Ceramics
Authors: Büttner Dustin , Krüger Klaus , Zobrist Beat , Schönberger Andreas , Jung Dieter
Published: October 2015

Digitally printed electronics are a major field of activity in research and industrial applications nowadays, especially in thick-film technology. Within the last decade great progress has been made in print electronics toward the goal of supplementing or replacing the established screen printing technology. The advantage of digital printing is its capability for rapid production without any layout-specific tools (i.e., screens). This highly flexible production method is especially applicable for prototyping and small series productions.

Electrophotography, commonly known as laser printing, has been considered very rarely as a method for digital printing of electronic circuits. It is a completely solvent-free method with high speeds and a high potential for precision. At Helmut Schmidt University, electrophotography is being developed as an alternative method to print silver lines as a basis for a conductive layout.

Following the publication of the first set of conductive silver lines to be printed, this paper covers the development from initial conductivity to a functional circuit element. Deficits in toner transfer to tape are examined and a more effective transfer method is established. Furthermore, the used silver toner is improved, and its performance is tested regarding the desired application. Silver lines are printed on green tape and sintered in a cofiring process, as well as on ceramic using a postfiring process. After reaching a certain level of quality, a set of functional RFID antenna coils is printed that proves the capability of the process to create a conductive layout.
Localized Temperature Stability in Multilayer LTCC
Authors: Dai Steve
Published: October 2015

Low temperature cofired ceramic (LTCC) is a multilayer 3D packaging, interconnection, and integration technology. One of the advantages of LTCC is the ability it affords to integrate passive components via the cofiring processes. For LTCC modules with embedded resonator functions targeting high frequency applications, the temperature coefficient of resonant frequency (τf) is a critical parameter. The base dielectrics of commercial LTCC systems have a τf in the range of −50 ppm/°C to −80 ppm/°C. This study explores a method to achieve zero or near zero τf embedded resonators by incorporating τf compensating materials locally into a multilayer LTCC structure. Chemical interactions and physical compatibility between the τf modifiers and the host LTCC dielectrics are investigated. A stripline (SL) ring resonator with near zero τf is demonstrated in a nonzero τf commercial LTCC.
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration
Authors: Sheu Shyh-Shyuan , Lin Zhe-Hui , Hung Jui-Feng , Lau John H. , Chen Peng-Shu , Wu Shih-Hsien , Su Keng-Li , Lin Chih-Sheng , Lai Shinn-Juh , Cheng Kuo-Hsing , Ku Tzu-Kun , Lo Wei-Chung , Kao Ming-Jer
Published: October 2015

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.
Automated Complex Permittivity Characterization of Ceramic Substrates Considering Surface-Roughness Loss
Authors: Engin A. Ege , Pasunoori Pavithra
Published: October 2015

This paper presents a new method to extract the frequency-dependent dielectric constant and loss tangent of ceramic substrates from high frequency measurements of cavity resonators. A cavity resonator can be realized using two ground planes connected with vias to form the side walls. Recently, a rapid plane solver has been developed to efficiently and accurately simulate cavity resonators and extract materials properties by manually fitting simulations to measurements. In this paper, we demonstrate how the fitting process can be automated. In order to extract the dielectric constant and loss tangent, many simulations need to be run to find the parameters that provide the best match with the measurements. This is a computationally expensive approach. We will present a new method based on tracking sensitivity, which provides a parameterized macromodel for the resonators. Using this approach, the simulation data can be expressed as a low-order rational function of the complex permittivity. Hence, varying the complex permittivity to find the best fit can be done in negligible time after the macromodel has been generated. This new method will be applied to extract the dielectric constant and loss tangent of a ceramic substrate in the presence of surface roughness loss.
Formulation of Percolating Thermal Underfills Using Hierarchical Self-Assembly of Microparticles and Nanoparticles by Centrifugal Forces and Capillary Bridging
Authors: Brunschwiler Thomas , Schlottig Gerd , Ni Songbo , Liu Yu , Goicochea Javier V. , Zürcher Jonas , Wolf Heiko
Published: October 2015

Thermal underfills are crucial to support integration density scaling of future integrated circuit packages. Therefore, a sequential process using hierarchical self-assembly of microparticles and nanoparticles is proposed to achieve percolating thermal underfills with enhanced particle contacts. The three main process steps are assembly of filler particles by centrifugation, formation of nanoparticle necks by capillary bridging, and backfilling of the porous structure with an unfilled capillary adhesive.

Numerical simulations predicting trajectories and distributions of micron-sized particles dispensed into a rotating disk are presented. The trajectories exhibit a strong dependence on particle size; thus, in the case of polydisperse filler particles, nonuniform particle beds may result. An efficient centrifugal disk design with spiral-like guiding structures is experimentally validated. Defect-free, percolating particle beds in confined space with fill fractions of 46 vol.% to 66 vol.%, that is, close to the theoretical limit, are also presented.

The self-assembly of nanoparticles, forming enhanced thermal contacts between the percolating filler particles, is discussed. Two consecutive evaporation patterns during the capillary bridging process were identified: (1) dendritic network growth, and (2) collapse of capillary bridges. The concave neck topology could only be achieved at temperatures below the boiling point. An optimal evaporation temperature of 60°C with respect to in-plane uniformity and neck shape was identified. Existing thermal gradients normal to the cavity surface resulted in strongly asymmetric neck formation in the cavity. Hence, uniform heating in an oven is the preferred method to initiate evaporation. Two types of bimodal dielectric necks are demonstrated. Polystyrene acts as the adhesive between thermally conductive alumina particles to form mechanically stable dielectric necks after an annealing step at 140°C. Interstitial and core-shell necks are presented.

Finally, a benchmark study was performed to compare the effective thermal conductivity of the percolating thermal underfill with and without necks with state-of-the-art capillary underfills. A close to fivefold improvement could be obtained for diamond filler particles with silver necks (3.8 W/m·K).
Reliability Assessment of a New Power Electronics Packaging Material: Silver Diamond Composite
Authors: Faqir M. , Pomeroy J. W. , Batten T. , Mrotzek T. , Knippscheer S. , Vendier O. , Rochette S. , Massiot M. , Letteron L. , Desmarres J. M. , Courtade F. , Kuball M.
Published: October 2015

A reliability analysis of silver diamond composites in terms of both thermal and mechanical properties is presented. This new material is an attractive solution for power electronics packaging, because an improvement of 50% in terms of thermal management and channel temperature can be obtained when using silver diamond composites as a base plate in packages compared with the more traditionally used materials such as CuW. However, to date, little is known about the reliability of this new material, such as changes induced in its properties by thermal cycling. Assessment of the reliability of silver diamond composites is the aim of this work. Samples were submitted to 10 thermal cycles from room temperature to 350°C, and subsequently, a further 500 cycles of thermal shock as well as thermal cycling from −55°C to 125°C following typical standards used in space and military applications. In the worst-case scenario, thermal conductivity only decreased from 830 W/m·K to ∼700 W/m·K. An increase in the coefficient of thermal expansion and a change in diamond stress, were also observed after thermal cycling. Some structural modifications at the silver-diamond interface were found to be the underlying reason for the observed material properties change. These structural changes take place after the initial thermal cycling, and are constant thereafter. Changes found in thermal properties are satisfactory for enabling a significant improvement to standard CuW packaging materials.
Eutectic Zn-Al Die Attachment for Higher Tj SiC Power Applications: Fabrication Method and Die Shear Strength Reliability
Authors: Tanimoto Satoshi , Matsui Kohei , Zushi Yusuke , Sato Shinji , Murakami Yoshinori , Takamori Masato , Iseki Takashi
Published: October 2015

This paper comprehensively describes the fabrication method and shear strength reliability of a eutectic Zn-Al (m.p. = 382°C) attachment system, built by soldering SiC dice (2 × 2 mm2) onto Cu foil active-metal-brazed with a SiN ceramic plate. Four essential soldering conditions are presented and discussed for the formation of a strong and reproducible attachment. Die shear strength reliability data at Tj = 250°C are reported here for the first time. Storage tests at 250°C revealed that, after an initial slight decline, the die shear strength stayed virtually constant at a sufficient level (∼110 MPa) for at least 3,000 h. Thermal cycle test results indicated that the attachments can withstand thermal cycle stress for 3,000 cycles between −40°C and 250°C. The average die shear strength after 3,000 cycles was 18.5 MPa, a value that is three times higher than the IEC standard of 6.2 MPa specified in Document 60749-19.
Reliability Investigations up to 350°C of Gate Oxide Capacitors Realized in a Silicon-on-Insulator CMOS Technology
Authors: Grella K. , Dreiner S. , Vogt H. , Paschen U.
Published: October 2015

It is difficult to use standard bulk-CMOS-technology at temperatures higher than 175°C due to high pn-leakage currents. Silicon-on-insulator-technologies (SOI), on the other hand, are usable up to 250°C and even higher, because leakage currents can be reduced by two to three orders of magnitude. Nevertheless, performance and reliability of SOI devices are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350°C. The experiments were carried out on gate oxide capacitor structures realized in the Fraunhofer 1.0 μm SOI-CMOS process. The gate oxide thickness is 40 nm. Using the data of the TDDB measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350°C was evaluated. For a more detailed investigation, the evolution of the current in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250°C, and make it possible to quickly evaluate the reliability of high temperature CMOS technologies at operation temperature.
High-Temperature Characterization and Comparison of 1.2 kV SiC Power Semiconductor Devices
Authors: DiMarino Christina , Chen Zheng , Boroyevich Dushan , Burgos Rolando , Mattavelli Paolo
Published: October 2015

Focused on high-temperature (200°C) operation, this paper seeks to provide insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor devices; namely the MOSFET, BJT, SJT, and normally-off JFET. This is accomplished by characterizing and comparing the latest generation of these wide bandgap devices from various manufacturers (Cree, GE, ROHM, Fairchild, GeneSiC, and SemiSouth). To carry out this study, the static and dynamic characterization of each device is performed under increasing temperatures (25–200°C). Accordingly, this paper describes the experimental setup used and the different measurements conducted, which include: threshold voltage, current gain, specific on-resistance, and the turn-on and turn-off switching energies of the devices. The driving method used for each device is also detailed. Key trends and observations are reported in an unbiased manner throughout the paper and summarized in the conclusion.
LT-TLPS Die Attach for High Temperature Electronic Packaging
Authors: Greve Hannes , McCluskey F. Patrick
Published: October 2015

Low temperature transient liquid phase sintering (LT-TLPS) can be used to form high-temperature joints between metallic interfaces at low process temperatures. In this paper, process analyses and shear strength studies of paste-based approaches to LT-TLPS are presented. The process progression studies include DSC analyses and observations of intermetallic compound (IMC) formation by cross-sectioning. It was found that the sintering process reaches completion after sintering times of 15 min for process temperatures approximately 50°C above the melting point of the low temperature constituent. For the shear studies, test samples consisting of copper dice and copper substrates joined by sintering with a variety of sinter pastes with different ratios of copper and tin have been assessed. A fixture was designed for high temperature enabled shear tests at 25°C, 125°C, 250°C, 400°C, and 600°C. The influence of the ratio of the amount of high melting-point constituent to the amount of low melting-point constituent on the maximum application temperature of the sinter paste was analyzed. Ag20Sn and Cu50Sn pastes showed no reduction in shear strength up to 400°C, and Cu40Sn pastes showed high shear strengths up to 600°C. It was shown that LT-TLPS can be used to form high temperature stable joints at low temperatures without the need to apply pressure during processing.
Capacitive Fringing Field Moisture Sensors Implemented in Flexible Printed Circuit Board Technology
Authors: Dean Robert N. , Hamilton Michael C. , Baginski Michael E.
Published: October 2015

Capacitive fringing field sensors are often used in applications where moisture is detected, since the dielectric constant of liquid water is approximately 80 times greater than the dielectric constant of air. Most of these sensors, however, are realized using rigid substrates. Some applications would benefit from using a flexible capacitive fringing field sensor that could be conformally mounted on a nonplanar surface. Flexible printed circuit board technology is a mature commercially available process for manufacturing flexible electronics. This same technology can also be used to realize flexible fringing field moisture sensors where the patterned Cu foil is used for the electrodes and the soldermask coating electrically insulates the electrodes from being electrically shorted by moisture in the detection environment. Sensors were designed and characterized through flat and bending tests in air and in water. The tests demonstrated that bending a sensor over a radius of curvature as small as 13.7 mm had no measurable impact on sensor performance in air or in water. The sensors achieved a 3:1 increase in capacitance when immersed in water compared with in air.
A Modeling Approach for Predicting the Effects of Dielectric Moisture Absorption on the Electrical Performance of Passive Structures
Authors: Curran Brian , Ndip Ivan , Engin Ege , Bauer Jorg , Pötter Harald , Lang Klaus-Dieter , Reichl Herbert
Published: October 2015

In this paper a modeling approach for predicting the electrical behavior of nonresonant and resonant structures under the influence of the absorption of moisture into the dielectric is presented. The paper focuses on the encapsulation materials used for printed circuit boards (PCBs) as a case study. For the investigated cases, analytical modeling shows that the loss of electrical insulation resulting from moisture absorption has minimal effects on the losses in transmission lines (TMLs), which would only cause system failure when combined with other aging effects. However, potential cases are discussed where the loss of electrical insulation could be significantly increased. Full-wave modeling shows that moisture absorption can cause the detuning of passive components, specifically antennas and impedance-controlled TMLs, that can have significant effects on system performance. Antenna resonance frequencies shift by up to 3–5%.
High Temperature Laminate Characterization
Authors: Shaddock David , Yin Liang
Published: October 2015

Characterization and modeling of high-temperature laminates for application at 200–250°C is reported to compare and better quantify the mean lifetime based on key functional parameters of via cycling, weight loss, peel strength, and surface insulation resistance (SIR). Life testing and models are applied for via cyclic life, peel strength, and weight loss. Five high-temperature laminates, consisting of three polyimides and two nonpolyimides, were evaluated. The polyimide laminates behaved similarly in via, weight loss, peel strength, and SIR testing with small variances. The nonpolyimides performed longer in via and weight loss. They degraded more rapidly than the polyimides in peel strength and failed in SIR, due to its flame retardant. A comparison of lifetime among the five laminates is presented.
Automatic Segmentation Method for Segmenting PBGA Package and PWB Regions During Warpage Measurement of Unpainted PWB Assembly
Authors: Kang Sungbum , Ume I. Charles
Published: October 2015

Among the various warpage measurement techniques, digital fringe projection (DFP) technique is recent trend because of its noncontact, full-field, and high-resolution measurement capabilities for measuring the warpage of chip packages, printed wiring boards (PWBs), and PWB assemblies (PWBAs). When using the DFP technique, reflective painting is generally sprayed on a sample surface to ensure uniform surface reflectance and to obtain better image contrast for the measurement process. However, because painted samples may no longer be reused, and the spray-painting process is not suitable inline, warpage measurement of unpainted chip packages, PWBs, and PWBAs using the DFP technique is required. One of the important tasks for measuring the warpage of unpainted PWBAs is segmentation of the chip package and PWB regions in unpainted PWBA images so that separate warpage of the chip packages and the PWBs can be determined. This paper presents a novel automatic segmentation method, region-growing method (RGM), which segments plastic-ball grid array (PBGA) packages and PWB regions in unpainted PWBA images. The experimental results show that the RGM successfully segments the PBGA package and PWB regions in unpainted PWBA images. The results also show that the RGM can be used in a DFP system to measures the warpage of PBGA packages and PWBs in unpainted PWBAs.
Enabling Manufacturable 3-D Technology and Ecosystems Using a 28-nm FPGA With Stacked Silicon Interconnect Technology
Authors: Kwon Woon-Seong , Kim Myongseob , Chang Jonathan , Ramalingam Suresh , Madden Liam , Tsai Genie , Tseng Stephen , Lai J.Y. , Lu Terren , Chiu Steve
Published: October 2015

Technology challenges and solutions in the development and manufacturing of stacked silicon interconnect (SSI) technology have been investigated with the established foundry and outsourced semiconductor assembly and test ecosystem. Key enabling technologies, such as through-silicon-via processing, interposer backside manufacturing yield enhancement, new stacking technology, interposer warpage control, and microbump processes and joining, which are the building blocks for SSI technology, were developed. Xilinx's 28-nm field programmable gate array with an SSI technology platform was used to develop and optimize the seamless integration of the processes, structures, and parameters, as well as to evaluate their yield, reliability, and device performance.
Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules
Authors: Pares G. , McMullen T. , Tomé S. , Vignoud L. , Bates R. , Buttar C.
Published: October 2015

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.
Die verhouding tussen Kolossense en Efesiërs as ’n sinoptiese probleem
Authors: Van Wyk Barry
Published: October 2015

The relationship between Colossians and Ephesians as a synoptic problem. Research by different scholars concluded that some letters traditionally ascribed to Paul were probably not written by him and drew a distinction between Pauline and Deutero-Pauline letters. The majority of scholars nowadays are of the opinion that the letters to the Colossians and the Ephesians are Deutero-Pauline and that Ephesians, at least, was surely not written by Paul. The results of research on the synoptic problem can be used and applied to the two letters under discussion because a comparison shows that there are striking similarities between the two. The most recent research shows that Ephesians made use of the letter to the Colossians but not without redactional changes to suit the author’s literary purpose. This method is exegetically known as redaction-criticism, linked to the social-science viewpoint that the author of the letter to the Ephesians acted as a change agent on behalf of a change agency.
Impact of combination antiretroviral therapy initiation on adherence to antituberculosis treatment
Authors: Knight Marlene , Van Zyl Robyn L. , Sanne Ian , Bassett Jean , Van Rie Annelies
Published: October 2015

Background: Healthcare workers are often reluctant to start combination antiretroviral therapy (ART) in patients receiving tuberculosis (TB) treatment because of the fear of high pill burden, immune reconstitution inflammatory syndrome, and side-effects.Object: To quantify changes in adherence to tuberculosis treatment following ART initiation.Design: A prospective observational cohort study of ART-naïve individuals with baseline CD4 count between 50 cells/mm3 and 350 cells/mm3 at start of TB treatment at a primary care clinic in Johannesburg, South Africa. Adherence to TB treatment was measured by pill count,self-report, and electronic Medication Event Monitoring System (eMEMS) before and after initiation of ART.Results: ART tended to negatively affect adherence to TB treatment, with an 8% – 10% decrease in the proportion of patients adherent according to pill count and an 18% – 22% decrease in the proportion of patients adherent according to eMEMS in the first month following ART initiation, independent of the cut-off used to define adherence (90%, 95% or 100%). Reasons for non-adherence were multi factorial, and employment was the only predictor for optimal adherence (adjusted odds ratio 4.11, 95% confidence interval 1.06–16.0).Conclusion: Adherence support in the period immediately following ART initiation could optimise treatment outcomes for people living with TB and HIV.
Characteristics of Travel-Related Severe Plasmodium vivax and Plasmodium falciparum Malaria in Individuals Hospitalized at a Tertiary Referral Center in Lima, Peru
Authors: Llanos-Chea Fiorella , Martínez Dalila , Rosas Angel , Samalvides Frine , Vinetz Joseph M. , Llanos-Cuentas Alejandro
Published: October 2015

Severe Plasmodium falciparum malaria is uncommon in South America. Lima, Peru, while not endemic for malaria, is home to specialized centers for infectious diseases that admit and manage patients with severe malaria (SM), all of whom contracted infection during travel. This retrospective study describes severe travel-related malaria in individuals admitted to one tertiary care referral hospital in Lima, Peru; severity was classified based on criteria published by the World Health Organization in 2000. Data were abstracted from medical records of patients with SM admitted to Hospital Nacional Cayetano Heredia from 2006 to 2011. Of 33 SM cases with complete clinical data, the mean age was 39 years and the male/female ratio was 2.8. Most cases were contracted in known endemic regions within Peru: Amazonia (47%), the central jungle (18%), and the northern coast (12%); cases were also found in five (15%) travelers returning from Africa. Plasmodium vivax was most commonly identified (71%) among the severe infections, followed by P. falciparum (18%); mixed infections composed 11% of the group. Among the criteria of severity, jaundice was most common (58%), followed by severe thrombocytopenia (47%), hyperpyrexia (32%), and shock (15%). Plasmodium vivax mono-infection predominated as the etiology of SM in cases acquired in Peru.
Efficacy and Safety of Liposomal Amphotericin B for the Treatment of Mucosal Leishmaniasis from the New World: A Retrospective Study
Authors: Cunha Mirella A. , Leão Aline C. Q. , de Cassia Soler Rita , Lindoso José Angelo L.
Published: October 2015

The standard treatment of mucosal leishmaniasis (ML) is pentavalent antimonials, agents with serious adverse effects. Alternative agents include amphotericin B deoxycholate and liposomal amphotericin B. We performed a retrospective study including 29 patients treated with liposomal amphotericin B, most of whom had comorbidities, history of previous treatment of ML, and contraindications to the use of antimonial pentavalent or amphotericin B deoxycholate. We observed a cure rate of 93.1%. Kidney failure was the most important side effect, reported in five patients (17.2%). This study showed a good efficacy and safety profile of liposomal amphotericin B in patients with ML and contraindications to the use of other agents.