Silicon Encapsulated All Solid-State Li-ion Microbatteries
Authors: Collins John , Afzali-Ardakani Ali , Papalia John , De Souza Joel , Todorov Teodor , Pacquette Adele , Krishnan Mahadevaiyer , Rozen John , Sadana Devendra K. 
Published: February 2020

The demand for safe, all solid-state energy storage for microelectronic devices is sharply increasing with the evolution of micro-electronics, namely Internet of Things (IoT). Microelectronics applications in IoT and health care industries progressively demand higher all-solid state volumetric, gravimetric and areal capacity packed in smaller volumes and areas – driving competitive exploration of next generation materials and designs especially via the solid state microbattery model. Conventional all-solid-state Li-ion batteries maintain control of performance via standard thin film encapsulation and packaging techniques (2.5D packaging), where theoretically high capacity 3D thin film microbatteries continue to fail the commercial sector due to leakage, dielectric breakdown, 3D fabrication, and parasitic cell degradation. 3D microbattery milestone failures, combined with cost, time of assembly and large active/packaging areas (>1mm2) of 2.5D form factors, limit the commercial practicality of current microbattery demand in an ever-shrinking foot print market.

The work presented herein is a novel approach in addressing the above issues through silicon-based encapsulation and packaging in conjunction with composite silicon-based electrode material. Methods were developed to fabricate conformally deposited all-solid-state Li-ion materials into 3D trench patterned silicon substrates using advanced solid polymer electrolyte (SPE), interfacial additives (e.g. LiTFSI containing Polyaniline (PANI)) and commercial electrode materials (e.g., graphite & LFP). 3D features (≤1mm2) in crystalline silicon substrates were created via standard microfabrication methods (e.g. through silicon via (TSV) reactive ion etching (RIE))— where 16 trenches (1mm2 area, 350mm depth, 2mm pitch) enabled 35mm x 35mm chiplets on a 200mm silicon wafer (Figure 1a). The field, sidewalls and base of the 3D trenches were conformally patterned with electron/ion insulating materials (e.g., SiO2 &/or Si3N4) (Figure 1b). Insulation was partially etched away at trench bases to create an electrical connection between the active battery material and silicon substrate. Active battery material slurries (graphite, solid polymer electrolyte (SPE), interfacial additives) filled the insulated trenches, were pressed, heated, and dried—yielding low impedance functioning composite cells (Figure 1c). The top of the trench was subsequently planarized with a metal contact laminated cathode material (LFP) via conductive epoxy. Finished In-silicon microbattery cell(s) were encapsulated with coin cells as a second-generation (Gen 2) test model.

By adjusting the formulation of an interfacial additive, a thinner interphase was achieved with superior interlayer adhesion of an electrochemically tailored (in-situ formed) silicon/additive/anode composite. Composite cells with Li-containing PANI compared with non-Li-containing PANI interfacial additive resulted in a charge transfer resistance 5 orders of magnitude lower and 2.8x greater areal discharge capacity (1.74uAh/mm2), lasting 60 rechargeable cycles with an average working voltage range of 2.5V to 1.0V (Figure 1d).

Gen 2+ test modules consisted of single, stand-alone, ~2.6mm2 packaging area In-silicon microbatteries with full cell charge transfer interfacial impedance less than 120W at the pre-cycle stage with the lowest interfacial impedance observed after more than 80 cycles (<50W). EIS measurements illustrated reduction in cell impedance due to in-situ formation of a composite anode containing crystalline silicon, a silicon/lithium bilayer, interfacial additive and graphite (Figure 1e). The Gen 2+ stand-alone module yielded top areal capacity greater than 1.50uAh/mm2, with more than 100 rechargeable cycles obtained over an average voltage range of 3.5V to 1.0V. Minimum rechargeable capacities of Gen 2+ test modules (1mB) were double that of Gen 2 (4mB-parallel), as enabled via an 18x reduction in packaging area, resulting in nearly 3x reduction in composite cell impedance and consequently, a 1.2 volt increase of onset discharge voltage (Figure 1f).

Active Battery to Packaging Area Ratios for the Gen 2+ In-silicon microbattery module (0.51) have already begun to rival industry standard ratios (e.g., 0.59 with ~25mm x 25mm thin film microbattery footprint). The next generation design for In-silicon microbatteries is predicted to advance active/packaging ratios higher than the thin film standard @ a ratio of 0.64 as the optimization of silicon encapsulation thickness to active battery area is realized.

It is projected that with the In-silicon microbattery technology presented, combined with current state of the art solid-state materials, In-silicon microbatteries can exceed performance of commercially available microbattery products (e.g., >2.5uAh/mm2, >200mAh/g). The In-silicon microbattery design provides superior ease of integration with any Si or non-Si based integrated circuit (IC) technology obtained via common microfabrication infrastructure, at low tool cost & production steps. Future efforts will demonstrate that In-silicon microbattery technology is scalable not only to (IoT) applications, yet with Gen 3 form factors and composite cells, such all-solid-state Lithium based capability is scalable to established mobile applications (smart phones) and extremely high energy applications including renewables, grid storage and electric vehicles (EV).

Figure 1