bluuebunny/crossref_metadata_2025 huggingface dataset:
Enhanced Microchannel Heat Sinks Using Oblique Fins
Authors: Lee Yong-Jiun , Lee Poh-Seng , Chou Siaw-Kiang
Published: January 2011

Oblique fins created in a microchannel heat sink can serve to modulate the flow, resulting in local and global heat transfer enhancement. Numerical analysis of laminar flow and heat transfer in such modified microchannel heat sink showed that significant enhancement of heat transfer can be achieved with negligible pressure drop penalty. The breakage of continuous fin into oblique sections causes the thermal boundary layers to be re-initialized at the leading edge of each oblique fin and reduces the boundary-layer thickness. This regeneration of the entrance effect causes the flow to be always in a developing state thus resulting in better heat transfer. In addition, the presence of the smaller oblique channels causes a fraction of the flow to branch into the adjacent main channels. The secondary flows thus created improve fluid mixing which serves to further enhance the heat transfer. The combination of the entrance and secondary flow effect results in a much improved heat transfer performance (the average and local heat transfer coefficients are enhanced by as much as 80%). Both the maximum wall temperature and temperature gradient are substantially decreased as a result.
Study on CAM System for Drilling in Printed Wiring Boards: Optimization of Stacking Sheet Considering Drill Processing Temperature
Authors: Hirogaki Toshiki , Aoyama Eiichi , Ogawa Keiji , Okawa Tsuyoshi
Published: January 2011

Recently, printed wiring boards (PWBs), which are employed in electronic devices, have been miniaturized, lightened, and made multifunctional. This trend demands the improvement of drilling technology and a method to raise productivity. In this study, as a processing sample, we use the aramid fiber-reinforced printed wiring board (AFRP) of the next generation PWB, which is attracting attention, and GFRP, which is most commonly used. We investigate the processing temperature and the processing quality and conduct number optimization of the sheets to improve productivity by increasing their number.
Cu-Direct Laser Drilling of Blind Via-Hole in Multi-Layer PWBs: Influence of Surface Treatment on Drilled Hole Quality
Authors: Hirogaki Toshiki , Aoyama Eiichi , Ogawa Keiji , Ayuzawa Tsukasa
Published: January 2011

This report describes the quality assessment of Blind Via Holes (BVHs) of Printed Wiring Boards (PWBs) drilled by a CO2 laser using Cu-direct drilling. In the Cu-direct drilling method, the copper foil and the build-up layer are melted at the same time, and the surface is treated to increase the laser energy absorbed by the copper foil since an untreated copper surface reflects most of the 10.6-μm-wavelength CO2 laser beam. However, there are few reports dealing with Cu-direct laser drilling of PWBs. In addition, when copper and resin with different processing thresholds are drilled at the same time, occurrences of a defect called overhang have been observed. So, in this report, first we propose a new method using thermography to measure the absorptance of a PWB surface for a CO2 laser. Moreover, we investigate how surface treatment of the outer copper foil influences the quality of a laser-drilled hole. Then, we observe the circumference of a point irradiated with the CO2 laser and explain how melting processes are different from surface treatment. Finally, based on the research we establish a method in order to cut down the overhang length as a parameter of drilled-hole quality. We also show that a high absorptance improves BVH quality.
A Computational Study of the Thermal Performance of a 69kV/3000A Solid State Current Limiter Under Transient Fault Current Loading
Authors: Warzoha Ronald , Fleischer Amy , Bird Simon D. , Gandhi Mahesh , Sundaram Ashok
Published: January 2011

This paper explores the thermal behavior of a 69kV/3000A Solid State Current Limiter in various transient fault cases. The system has been thermally analyzed in steady-state conditions and the authors have found an acceptable cooling strategy in the case of 864kW of waste heat in a three phase system. It is desired, now, to numerically model two different fault cases: bypass mode and let-through mode. In each case, it is necessary to ensure all system components remain at acceptable temperatures under intense power loading (on the order of 22,400 kW in a one-phase system) through four sets of ten inductors. This research explores the effect of liquid forced convection on the transient operating temperature of the system inductors when numerically modeled in Icepak.
Optimal Fan Speed Control for Thermal Management of Servers
Authors: Wang Zhikui , Bash Cullen , Tolia Niraj , Marwah Manish , Zhu Xiaoyun , Ranganathan Parthasarathy
Published: January 2011

Improving the cooling efficiency of servers has become an essential requirement in data centers today as the power used to cool the servers has become an increasingly large component of the total power consumption. Additionally, fan speed control has emerged in recent years as a critical part of system thermal architecture. However, the state of the art in server fan control often results in over provisioning of air flow that leads to high fan power consumption. It can be exacerbated in server architectures that share cooling resources among server components, where single hot spot can often drive the operation of a multiplicity of fans. To address this problem, this paper presents a novel multi-input multi-output (MIMO) fan controller that utilizes thermal models developed from first-principles to manipulate the operation of fans. The controller tunes the speeds of individual fans proactively based on prediction of the sever temperatures. Experimental results show that, with fans controlled by the optimal controller, over-provisioning of cooling air is eliminated, temperatures are more tightly controlled and fan energy consumption is reduced by up to 20% compared to that with a zone-based feedback controller.
Improving the Performance of an Impingement Heat Sink by Modifying the Fin Shapes
Authors: Gondipalli Sravan , Sammakia Bahgat , Refai-Ahmed Gamal
Published: January 2011

As the power dissipated by advanced microelectronic devices continues to increase, the demand for reliability also increases. This increases the requirements on the thermal performance of every part of the system, including the heat sink. One of the objectives of this study is to examine the effect of the shape of the heat sink fins on the thermal performance of the system. The pressure gradient at the center of the heat sink, near the base, tends to be high. This significantly reduces the airflow at that location and, hence, decreases transport in that region. Different fin shapes and airflow rates have been studied with the objective of searching for an optimal heat sink design that would improve the thermal performance without increasing the pressure drop across the heat sink. Parallel plate fins have been investigated by removing fin material from the region near the center of the heat sink along the length and height of the fins. The study also examines the impact of uniform and non-uniform heat sources in the device upon the overall system thermal performance. Twenty one heat sink designs with different cuts were simulated and compared and an improved heat sink design was proposed by eliminating the fin material at the center of the heat sink, thereby enhancing its thermal performance.
Thermal Characterization of a Single MOSFET Transistor at Cryogenic Temperatures
Authors: Wang Xi , Shakouri Ali
Published: January 2011

The aggressive miniaturization trend in microelectronic design has pushed the transistor gate length to a range of hundreds of nanometers. The study of heat transport and dissipation at the device level is becoming an important part of the overall thermal design. In general, temperature non-uniformity peaks in the transistor drain region due to the higher electric potential field and electron thermalization close to the drain. Drastic changes in both electrical current flow and the thermal heat flow to the heat sink can be caused by this localized temperature non-uniformity. Ballistic transport that happens when gate length approaches the phonon mean free path re-shapes the temperature distribution. Extensive theoretical studies have been done in this area during the past several years [1–3], but no direct experimental observation has yet been reported. The main challenge is the possibility to detect electron and/or lattice temperatures in sub micron ranges. In this paper, we measure the surface temperature distribution of a 180nm gate length silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor) at both ambient and cryogenic temperatures (10K). The purpose of cryogenic measurement is that the temperature distribution is significantly modified due to much longer phonon ballistic transport as well as possible thermal resistance change. We used thermoreflectance imaging to measure the surface temperature with 100’s nm spatial resolution and 0.1C° temperature resolution [4]. Thermoreflectance is a non-contact, nondestructive thermal characterization technique which is suitable for small scale, high precision measurements. A cryostat is used to keep the sample cold during experiment. The sample chamber is also kept at high vacuum condition (< 1e−5 torr) to prevent condensation and heat loss through air convection. Preliminary results show qualitative changes in the temperature distribution.
Thermal Analysis of Thermoelectric Coolers for Processors
Authors: Zhang Hengyun , Mui Y. C. , Tarin Michael , Yang Yizhang
Published: January 2011

In this paper, a thermal analysis of thermoelectric coolers (TECs) is conducted for processors based on TEC module parameters. Two sets of analytical solutions for TECs in system constraints are derived for the junction temperature Tj at a fixed power Qc, and for Qc at fixed Tj, respectively. The major advantage of the present models lies in the fact that the solutions can be obtained based on the module parameters without prior knowledge of pellet details and iterative solution procedure, as often reported in literature. Two cooling scenarios, the processor test and the processor cooling under end-user conditions, are analyzed based on the present analysis models for two commercial TECs with high power capacities. Results show that significant thermal enhancements are achievable based on optimized current and power dissipation. The validation is also conducted through experimental measurements and comparison with previous iterative solutions.
Nonlinear Response of a Printed Circuit Board in Shock
Authors: Vujosevic M. , Raghavan P. , Ramanathan G. , Hezeltine W. , Blue K.
Published: January 2011

This work focuses on deformation mechanisms taking place in a Printed Circuit Board (PCB) exposed to high impact shock. A combined experimental, theoretical, and numerical approach has been applied to address both the nature of the observed deformation and its modeling and test metrology implications. Experimental evidence overwhelmingly indicates that a PCB in both test and system applications undergoes nonlinear deformations. Geometric nonlinearity of board response is attributed to the elevated in-plane (membrane) stresses that develop when a drop height and/or inertia forces are significant. The impact of these stresses on deformations (board strain) was quantified using a specially designed test. Membrane stresses were also accounted for in a numerical (Finite Element Method) model developed and carefully validated in the course of this study. The model shows a very good agreement with test data. The nonlinearity of PCB deformation in shock, i.e. the fact that both bending moments and in-plane forces are present in the board has important implications on test metrology development and on correlation between the measured board strain and stresses in interconnects of surface mounted components. Of special importance is the impact that nonlinearity can have on development of transfer functions between strain measurements on system boards and strain measurements on test boards, which is also addressed in the paper.
Molecular Dynamics Simulation of the Thermal Resistance of Carbon Nanotube – Substrate Interfaces
Authors: Rogers Daniel J. , Qu Jianmin , Yao Matthew
Published: January 2011

The interfacial thermal resistance (ITR) between a carbon nanotube (CNT) and adjoining carbon, silicon, or copper substrate is investigated through non-equilibrium molecular dynamics simulation (NEMD). The theoretical phonon transmission also is calculated using a simplified form of the diffuse mismatch model (DMM) with direct simulation of the phonon density of states (DOS) under quasi-harmonic approximation. The results of theory and simulation are reported as a function of temperature in order to estimate the importance of anharmonicity and inelastic scattering. At 300K, the thermal conductance of CNT-substrate interfaces is ∼1500 W/mm2K for diamond carbon, ∼500 W/mm2K for silicon, and ∼250 W/mm2K for copper.
Thermal Performance of Laminate-to-Aluminum Attachment Materials
Authors: Maddox John F. , Knight Roy W. , Bhavnani Sushil H. , Evans John
Published: January 2011

A non-destructive method was used to determine the effects of thermal cycling on the thermal performance of a PCB attached to an aluminum substrate with a thermal adhesive. This method allows for a comparison of the thermal performance of various TIMs in an industrial application. Testing was done on FR4 and Flex boards, both with and without overmolding, attached using PSA and an alternative adhesive. Baseline measurements were taken, then the boards were cycled from −40 to 125°C on a 90-minute cycle with 15-minute dwells at the target temperatures. It was found that both adhesives showed an increase in thermal conductivity, possibly due to curing, and delamination occurred at 17 out of 35 locations with the alternative adhesive within the first 1000 cycles while no delamination occurred with the PSA.
Localized High-Resolution Stress Measurements on MEMS Structures
Authors: Vogel Dietmar , Gollhardt Astrid , Michel Bernd
Published: January 2011

Three different methods of stress measurement with strong spatial resolution are presented. They base on stress relief techniques caused by focused ion beam milling, on altered electron backscattering by deformed lattices and on Stokes line shift measurements by Raman spectroscopy. The capability of these methods is demonstrated by their application to typical MEMS structures. A comparison between the methods is performed in order to outline potentials and limitations.
Thermo-Mechanical Analysis of a Laser Diode Chip in an Opto-Electronic Package
Authors: Chaparala Satish C. , Hughes Lawrence C. , Kwak Jae , Park Seungbae
Published: January 2011

It is a well-known fact that the lasers have wide variety of applications in diverse fields from medicine to communications [1]. Laser packaging involves appropriate materials selection and design to ensure that the laser performance meets the required specifications. In this paper, we present a GaAs based laser diode package design. The package design enables the laser diode chip to withstand the thermo-mechanical strains that are induced during the package assembly process as well as during the operating conditions. Excessive stresses in the chips could causes cracks in the chip. Excessive strains could cause un-desired spectral characteristics in the emitted light [2]. Therefore, the objective is to design a package that is tested and characterized to avoid these failure modes. This study presents numerical and experimental investigation of thermo-mechanical strains induced due to coefficient of thermal expansion (CTE) mismatch between various package components during assembly process. Finite element (FE) analysis is used to predict the displacements, tensile strains and stresses in the chip at various assembly processes. Digital Image Correlation (DIC) technique was used to measure the strains in the laser diode. Earlier, other researchers have used photo-luminescence methods and spectroscopic methods etc to measure packaging induced strains in the laser package [3]–[9]. The authors are not aware of any prior work where the DIC technique is applied on a very small chip for strain measurements Good correlation in displacements and strains was obtained between the model and the measurements, increasing confidence in the model. In addition, experiments were conducted to estimate the fracture strength of the GaAs to predict the chip failure based on the maximum principal stress criterion. The FE model was later used to conduct parametric study to analyze the impact of other factors on the chip stress such as substrate thickness, voids, thermal gradients in the package, surface irregularities in the chip etc. Experiments and model indicated that the designed package was robust enough and does not cause any damage to the chip.
System Level Transient Thermal Performance of High-Power Dynamic Microelectronics
Authors: Chiriac Victor
Published: January 2011

System-level thermal transient analysis of High-Power Dynamic Microelectronics System is performed using numerical simulations. The SmartMOS-type device is packaged in 20 lead SOIC module with exposed copper slug. The package is attached to 4-layer PCB with embedded thermal vias. The challenge resides in the transient thermal interaction between the dynamic heat sources (high/low side motors), activated simultaneously at different powering profiles. Several operating steps are simulated, and the transient thermal behavior for each source is analyzed then optimized during the process. The low side motor reaches a peak temperature of ∼126.1°C at 2.25s, while the final temperature reached by the motor after one cycle (2.565 s) is ∼75.9°C. The DC current limit study indicates that the current over 1A exceeds the thermal budget. The case with 0.5A current limit reaches 135°C after 4 cycles, satisfying the thermal budget. Additional studies for an equivalent system were performed with only the high side driver actively dissipating 120W for 2.56 ms. The peak temperature reached by the system during the first cycle (2.56 us) is ∼65°C. Analytical study was performed to evaluate the steady state (final) temperature after a large number of dynamic powering cycles, based on heating/cooling behavior and superposition principle. The peak temperature reached by the IC will not exceed 92°C (using the steady state value and the temperature fluctuations per transient cycle). A correlation to predict the peak temperatures reached by the dynamic system after a long number of powering cycles is provided.
Device Simulation of Mechanical Stress Effects on Electrical Characteristics of nMOSFETs: Impact of Local Stress in nMOSFETs
Authors: Koganemaru Masaaki , Yoshida Keisuke , Ikeda Toru , Miyazaki Noriyuki , Tomokage Hajime
Published: January 2011

An electrical characteristic of a semiconductor device suffers from a residual stress during various packaging processes. Very few attempts have been made at developing a numerical method for evaluating such problems. Therefore, the objective of this study is to evaluate stress-induced effects by numerical simulation. That is, the effects of stress on the electrical characteristics of n-type Metal Oxide Semiconductor Field Effect Transistors (nMOSFETs) with a 85nm gate length were evaluated by mechanical stress simulation and drift-diffusion device simulation (multi-physics simulation). The device simulation model used includes the electron mobility model that considers the stress-induced effects. This study focused on the impact of the stress distribution in the nMOSFETs. The stress distribution in the nMOSFETs was considered in conducting the multi-physics simulation. As determined by mechanical stress simulation, stress concentrated around the STI, and the effect of such stress concentration reached the channel region of the nMOSFETs. Then, the drift-diffusion device simulation was carried out. The stress distribution in the nMOSFETs obtained by mechanical stress simulation was used as the stress effect in the device simulation model. As determined by device simulation, the drain current decreased under the estimated residual stress. The drain-current shift corresponded quantitatively to the stress at the region of the channel. It was demonstrated that the multi-physics simulation is essential for evaluating the effect of stress on electrical characteristics of a semiconductor device.
Performance Study of a GaAs Based Laser Diode Chip in a Condensing Environment
Authors: Madduri Sushma , Sammakia Bahgat G. , Infantolino William , Chaparala Satish C. , Hughes Lawrence C. , Harris J. Micheal
Published: January 2011

This paper presents a performance study done on semiconductor laser diodes in a moisture condensing environment. Devices with laser diodes are used in a wide variety of electronic applications and in various climatic conditions. The motivation behind this study is a common environmental exposure, where a device using a laser diode is brought into a relatively humid environment (a building) from a cold, outside environment. Under such conditions, condensation occurs on various components of the device, including the diode, and could affect the laser output power. Reliability of the device is a critical concern since the laser diode and the lens are susceptible to failure due to such repetitive condensation conditions. The test vehicle chosen for this study was a 980nm laser diode. These are used in products for a broad range of markets, including data communications, aerospace, material processing, scientific and defense industries [1–3]. These products may be used in environmental conditions that could result in condensation within the product. A hermetic package could address this concern, but it is an expensive option. Nonhermetic packaging for the laser component could help lower the cost of these devices; however reliability is a potential concern. Prior research on laser diodes consists of various reliability measurements on 980nm lasers using stress tests (e.g. accelerated aging tests; thermal cycling tests) [3–6]. Reliability analysis of laser diodes specifically addressing condensation measurements has not been previously reported. A Military Standard Specification [MIL-STD-883E Method 1004.7] titled, ‘Moisture resistance test’ was used to conduct this reliability study [10]. An experimental setup was designed and fabricated. A photonic package with a 980nm laser diode was subjected to repetitive condensing cycles and laser output power was recorded as a function of time, temperature and humidity. The variation in laser output power due to condensation was observed and quantified. The focus of this paper is on performance degradation of the laser diode. The possible mechanisms for this degradation are currently being investigated.
A Study of Acoustic Emission Produced by Strength Test on Bio-Ceramics: The Dependency of Roughness on Mechanical and AE Characteristics
Authors: Nakayama Mitsuyuki , Suzuki Hideto
Published: January 2011

Recently, ceramics has been using widely as living body material. It is called “bioceramics”. Both strength and elasticity of a living body material need almost three times larger than that of elaborate bone. However, it is difficult to satisfy the condition. So bioceramics is inferior to an elaborate bone. The purpose of this research is to obtain a basic data for improving the mechanical characteristics of bioceramics by the Acoustic Emission (AE) method. It was discussed how average roughness depends on mechanical characteristic and AE parameter of bioceramics. The following results were obtained. The first, the bioceramics showed a positive correlation between sound velocity and Kurtosis, that is one of the important parameter for the surface roughness. The second, it was clarified that same relation was obtained between Kurtosis and such mechanical parameters as stress, Young’s modulus and hardness. The third, these results were in accordance with the theory of fracture mechanics for fine ceramics reported independently by Rice and Aoki.
Mixing Behaviour of Coalescing Droplets in a Tube
Authors: Muraoka Masahiro , Ogawa Naoki , Fujita Renpei , Ueno Ichiro , Mizoguchi Hiroshi
Published: January 2011

We focus on coalescence phenomena of liquid droplets with/without suspended particles in confined geometry; in a horizontal creeping tube flow and in a vertical tube in a quiescent fluid. Correlation between the droplets’ size and the coalescence time (i.e., period between instances when the relative velocity of two droplets becomes zero after their contact and when the coalescence takes place) are examined. Effects of suspended particles in the droplets on their coalescence are discussed.
Microscale Temperature Measurements Near the Contact Line of an Evaporating Thin Film in a V-Groove
Authors: Migliaccio C. P. , Dhavaleswarapu H. K. , Garimella S. V.
Published: January 2011

Thin-film evaporation of heptane in a V-groove geometry is experimentally investigated. The groove is made of fused quartz, and electrical heating of a thin layer of titanium coated on the backside of the quartz substrate provides a constant heat flux. The effects of liquid feeding rate on the temperature suppression in the thin-film region and on the meniscus shape are explored. High resolution (∼6.3 μm) infrared thermography is employed to investigate the temperature profile in the thin-film region, while a goniometer is used to image the meniscus shape. An approximate heat balance analysis is used to estimate the fraction of total meniscus heat transfer which takes place in the contact line region.
Steady-State and Transient Thermal Performance Optimization of Power Automotive Modules
Authors: Chiriac Victor
Published: January 2011

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of power packages for automotive applications. The automotive industry deals on a daily basis with various package and module-level thermal issues when managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of IC incorporation into a system module, for present and future product development. Several packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal impact of the thicker lead frame and die attach material on the overall thermal behavior is evaluated. The main concern is exceeding the thermal budget at an external ambient temperature of 85°C, specific for the relatively extreme automotive operating environments. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ∼106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ∼260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. When the isothermal boundary is attached to package bottom, peak temperature drops by 20% after 40 ms. Additional system level with multiple optimized packages placed on a custom PCB is evaluated numerically and experimentally, placing an emphasis on the superior thermal performance of this new class of power packages for automotive applications. The optimized numerical model approximates closely the empirical results (121–126°C vs. 127.5°C), within 1–2%.
A Theoretical Model for a Flat Micro Heat Pipe With a Grooved Wick Using Nanofluids
Authors: Do Kyu Hyung , Choi Byung Il , Han Yong Shik , Jang Seok Pil
Published: January 2011

A theoretical model is developed for predicting the thermal performance of a flat micro heat pipe with a rectangular grooved wick using a water-based Al2O3 nanofluid. In the present model, the axial variations of the wall temperature and the evaporation and condensation rates are considered by solving the one-dimensional conduction equation for the wall and the augmented Young-Laplace equation for the phase change process. In particular, a model which accounts for the change of the heat transfer surface characteristics by the formation of a thin porous coating layer is suggested. By using the developed model, the thermal performance of the heat pipe using nanofluid is compared with that of the heat pipe using based fluid. It is found that the thin porous layer on the fin top and the side of the groove which is created by nanoparticles suspended in nanofluids significantly increases the thermal performance of the heat pipe.
Autonomous Detection of Thermal Anomalies in Data Centers
Authors: Marwah Manish , Sharma Ratnesh K. , Lugo Wilfredo
Published: January 2011

In recent years, there has been a significant growth in number, size and power densities of data centers. A significant part of data center power consumption is attributed to the cooling infrastructure, consisting of computer air conditioning units (CRACs), chillers and cooling towers. For energy efficient operation and management of the cooling resources, data centers are beginning to be extensively instrumented with temperature sensors. While this allows cooling actuators, such as CRAC set point temperature, to be dynamically controlled and data centers operated at higher temperatures to save energy, it also increases chances of thermal anomalies. Furthermore, considering that large data centers can contain thousands to tens of thousands of such sensors, it is virtually impossible to manually inspect and analyze the large volumes of dynamic data generated by these sensors, thus necessitating autonomous mechanisms for thermal anomaly detection. Also, in addition to threshold-based detection methods, other mechanisms of anomaly detection are also necessary. In this paper, we describe the commonly occurring thermal anomalies in a data center. Furthermore, we describe — with examples from a production data center — techniques to autonomously detect these anomalies. In particular, we show the usefulness of a principal component analysis (PCA) based methodology to a large temperature sensor network. Specifically, we examine thermal anomalies such as those related to misconfiguration of equipment, blocked vent tiles, faulty sensor and CRAC related anomalies. Furthermore, several of these anomalies normally go undetected since no temperature thresholds are violated. We present examples of the thermal anomalies and their detection from a real data center.
In-Line Evaluation Method of the Intrinsic Stress of Thin Films Used for Transistor Structures
Authors: Kishi Hiroki , Sasaki Takuya , Ueta Nobuki , Suzuki Ken , Miura Hideo
Published: January 2011

Both thermal and intrinsic stresses that occur during thin-film processing and assembly processes dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate-electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. In addition, the change of the residual stress caused by the interference of the stress concentration fields between two gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making fine slits by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. It was confirmed, therefore, that both the thin film process-induced stress and the assembly-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
Nondestructive Evaluation of Thermal Fatigue Crack Propagation in Sn-Ag-Cu Solder Joints by Synchrotron Radiation X-Ray Micro-Tomography
Authors: Tsuritani Hiroyuki , Sayama Toshihiko , Okamoto Yoshiyuki , Takayanagi Takeshi , Uesugi Kentaro , Mori Takao
Published: January 2011

An X-ray micro-tomography system called SP-μCT, which has a spatial resolution of 1 μm, has been developed in SPring-8, the largest synchrotron radiation facility in Japan. In this work, SP-μCT was applied to the nondestructive evaluation of micro-crack propagation appearing as thermal fatigue damage in lead-free solder joints. The observed specimens include two typical micro-joint structures by Sn-3.0wt%Ag-0.5wt%Cu lead-free solder. The first is an FBGA (Fine pitch Ball Grid Array) joint specimen in which an LSI package is connected to a substrate by solder bumps 360 μm in diameter, while the second is a chip joint specimen in which chip type resistors 1.6 mm in length and 0.8 mm. in width are mounted on a substrate. A thermal cycle test was carried out, and the specimens were picked up at fixed cycle numbers. The same solder joints were observed repeatedly using SP-μCT at beamline BL20XU in SPring-8. An X-ray energy of 29.0 keV was selected to obtain CT (Computed Tomography) images with high contrast among some components, and a refraction-contrast imaging technique was also applied to the visualization of fatigue cracks in the solder joints. In the FBGA type specimens, fatigue cracks appeared at the periphery of the interfaces between the solder and the UBM (Under Bump Metallization) on the LSI package. As the thermal cycle proceeds, the cracks propagate gradually to the inner region of the solder bumps in the vicinity of the interface. On the basis of the three-dimensional crack images, the fatigue crack propagation lifetime was accurately estimated by means of the average crack propagation rate. On the other hand, in the chip joint specimens, fatigue cracks appeared and propagated through the thin solder layer between the chip and substrate. In contrast to the FBGA specimen, many small voids roughly 5 to 10 μm in length were formed in the solder layer. The important observed fact is that these voids deform and connect to each other due to the thermal cyclic loading prior to crack propagation. Consequently, the obtained CT images clearly show the process of crack propagation due to the thermal cyclic loading of the same solder joint. In contrast, such information has not been obtained, whatsoever by industrially employed X-ray CT systems.
Electro-Thermal Analysis and Monte Carlo Simulation for Thermal Issue in Si Devices
Authors: Hatakeyama Tomoyuki , Fushinobu Kazuyoshi , Okazaki Ken , Ishizuka Masaru
Published: January 2011

Nowadays, precise prediction of the heat generation in semiconductor devices is significant. Electro-thermal analysis is one of the attractive methods to predict the heat generation in devices. However, in electro-thermal analysis, the relaxation time approximation is applied to calculate the scattering term in momentum and energy conservation equation. And the assumption of the constant relaxation time for the scattering term of energy conservation equation and the momentum relaxation time derived from the empirical carrier mobility are conventionally applied. For precise prediction of the relaxation times, Monte Carlo (MC) simulation can be applied. In this research, we consider the importance of these relaxation times for heat generation in semiconductor devices. We compare the results with conventional relaxation times and those with the relaxation time from MC simulation in electro-thermal analysis. The calculation results show the electro-thermal analysis with the conventional relaxation time model will overestimate the heat generation density in lower electric field of devices and in higher clock frequency devices.
Optimization of Saw Street Configuration to Save Saw Blade in Assembling QFN Packages
Authors: Yu Youmin , Bai Denis , Jiang Y. W. , Wang Sonder
Published: January 2011

Saw singulation is an indispensable process to sever the Mold Array Package (MAP) strips into individual units in assembling Quad Flat No-lead (QFN) packages. Mechanical saw, cutting the MAP strip along saw streets using dicing blade, is a mainstream mode in the saw singulation process. Accordingly, the dicing blade, a continuously consumed part, takes a significant portion of the assembly cost. The saw blade consumption is generally determined by saw blade type, MAP strip structure and process parameter. In this study, the effects of MAP strip structure, specifically, the saw street configuration in lead frame, on the saw blade saving have been experimentally investigated. The saw street configuration was first investigated by comparing the wear amount of saw blade for cutting discrete and continuous saw streets of equal length and same configuration in 3×3 mm, 6×6 mm and 9×9 mm QFN packages. It is found that (i) the wear amount of the discrete saw streets may be significantly less than its counterpart of the continuous saw streets and (ii) the saw blade saving in the discrete saw streets goes more as the package size goes smaller. The saw blade saving is attributed to the additional saw process improvement contributed by the discrete saw streets. The saw street configuration was also investigated by comparing the wear amount of saw blade for cutting saw streets of 5 mil and 8 mil lead frames in the 6×6 mm QFN package. It is proved that less metal amount in the saw street consumes less saw blade. The merit of the discrete saw street and metal amount reduction in saw street were then implemented in the revised lead frame of the 6×6 mm package, and the saw blade consumption per MAP strip dropped to 15.8 μm in revised lead frame from 113.0 μm in original lead frame in statistical sense.
Microbubble Formation in Collapsing Process of a Single Vapor Bubble Injected in Subcooled Pool
Authors: Ueno Ichiro , Hattori Yasusuke
Published: January 2011

‘Microbubble emission boiling,’ known as MEB, is a phenomenon that emerges in a narrow range of subcooled condition with a higher heat flux than critical heat flux (CHF) accompanying with microbubble emission from the heated surface. The authors focus on the condensing process of vapor bubbles in order to comprehend the mechanism of the microbubble formation and emitting processes. In order to simplify a surely complex boiling process, the authors try to extract an interaction between the vapor bubble and the subcooled bulk in a boiling phenomenon, that is, growing and collapsing processes of a vapor bubble ejected to subcooled liquid bath. Vapor bubble is produced by vapor generate system, and ejected to a bulk of saturated distilled water at a designated degree of subcooling. The degree of subcooling is varied from 0 to 50 K. The growing/collapsing of vapor bubble behavior is detected by employing a high-speed camera at frame rates up to 50,000 fps with a back-lighting system. In the present study, the process of microbubble emission as well as the process of the irrupting vapor bubbles to the subcooled bulk is compared to that in a MEB on a thin wire.
A Flow-Network Model for Predicting Rack Cooling in Containment Systems
Authors: Shrivastava Saurabh K. , VanGilder James W.
Published: January 2011

With row-based cooling systems, cooling units are placed directly in the row with the heat dissipating IT equipment racks. The cooling units are of similar dimensions to a standard IT rack but are oriented in the opposite direction relative to airflow. In order to achieve higher efficiencies and greater separation from the surrounding data center, air containment structures (plenums) are sometimes added to the entire row — on the rear and, potentially, the front side of the racks. This paper presents the development of a non-linear flow network model for predicting rack cooling performance in real time for such applications. Experimental work was performed to characterize the various leakage paths through IT racks and the containment systems in order to provide input data to the model. The Capture Index (CI) cooling performance metric is computed for each rack. Finally, flow network results are shown to be in good agreement with those from CFD.
Development of a Miniature Vapor Compression Refrigeration System for Electronic Cooling
Authors: Davies Gareth F. , Eames Ian W. , Bailey Paul B. , Dadd Michael W. , Janiszewski Adam , Stone C. Richard , Maidment Graeme G. , Agnew Brian
Published: January 2011

Computer chips have generally been cooled by means of a heat sink/fan device; however, such systems are now approaching their limits and in future alternative techniques/devices will be needed. A 3-year project, involving collaboration between groups at three UK universities, is being undertaken to develop a miniature refrigeration device for the cooling of future microprocessors and electronic systems. Using conventional vapor compression refrigeration technology for the cooling of small computer packages has generally resulted in low heat fluxes, however, microchannel devices have shown heat transfer coefficients up to 16 times greater, and porous medium channels even higher heat transfer rates. Porous media heat exchangers are being developed by Newcastle University and some results from this work are reported here. Surface contamination by lubricating oil from the compressor often causes problems with small passage heat exchangers. Oxford University’s Cryogenics Group have developed specialised oil-free compressors for low temperature cooling systems for space applications. Such a compressor is being adapted for use in the miniature vapor compression refrigeration device. The paper discusses development work on the compressor design. Conventional size refrigeration systems have sufficient capacity to dampen out transient behaviour resulting from variations in local temperatures and flow rates, but this is not the case for miniature systems. Based on earlier work at London South Bank University, a model has been developed to study transient behaviour in miniature refrigeration systems. The basis of the mathematical model is explained within the paper, as well as providing provisional results from the simulations. The paper identifies the potential need for computer cooling and highlights the opportunity to develop specific cooling solutions. Previous relevant work in this area is also highlighted. The paper provides details of novel work being carried out on modelling, micro-heat transfer and compressor development.
Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging
Authors: Huang Yu Hung , Lee Huei-Huang , Hwang Sheng-Jye , Huang Durn-Yuan
Published: January 2011

Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).
Facility Level Energy and Cost Analyses for Water Cooled Supercomputer Systems
Authors: Colgan Evan G. , Iyengar Madhusudan K.
Published: January 2011

This paper describes the facility level design of future water cooled supercomputers with an emphasis on the energy efficiency opportunities related to the use of water cooled economizer based facility cooling in lieu of traditional refrigeration chiller architectures. A hybrid cooled 80kW server rack with both air and water cooled components is considered for the analyses. In this system, 90% of the rack heat load is rejected directly to pumped water lines via CPU cold plates and conduction cooling and the remaining 10% rack power is rejected to the room ambient air and is subsequently transferred to the water loop via air to liquid heat exchanger based devices. Air to water heat exchangers are not included in the server racks. The facilities cost for water cooling of high power computer racks has been analyzed for data centers situated in two different geographic locations. The study takes into account both the energy savings resulting from the loop design as well as the duration of time for which these savings can be realized at the selected locations. Test data for the water cooled CPU modules is used to project the maximum chip junction temperature for different chilled water temperatures which are in turn determined using the outdoor air temperatures for different times of the year. After calculating the 5 year energy consumption savings over the traditional plant design for each location, for the two different geographic locations in the US considered, it was found that the outdoor weather permitted the use of the economizer based configuration for 53–76% and 60–80% of the time for A and B locations, respectively, yielding per rack energy related savings of $6–21k and $17–26k, respectively, for the thermal conditions considered.
Modeling and Simulation of Shock and Drop Loading for Complex Portable Electronic Systems
Authors: Askari Farahani F. , Al-Bassyiouni M. , Dasgupta A. , Tolchinsky S. , Crystal J.
Published: January 2011

The dynamic response of electronic assemblies to drop and shock conditions is investigated through tests and simulation. The portable electronic product tested in this study consists of a circuit card assembly and a battery pack supported in a two-piece plastic housing with a separate battery compartment. Dynamic loading, consisting of various shock profiles, is applied using an electrodynamic shaker. A number of drop tests are also conducted on a drop tower. Fourier Transform technique (FFT) is utilized to analyze the dynamic response of the PWB and the plastic housing in the frequency domain. The loading events are modeled in ABAQUS™ [11]. Flexural strains and accelerations are compared to assess the agreement between the model results obtained here and the experimental results [10]. The long-term goal of this study is to demonstrate a systematic computational capability to predict the dynamic response and failure modes expected due to drop loading, during the design phase of future products.