(Invited) Micro-Transfer-Printing: A Novel Technology for Volume D2W Integration
Authors: Wicht Sebastian , Gozdzik Sandra , Setty Kavana Mandya Sreenivasa , Rangra Aarushee , Heise Niclas 
Published: February 2024

In the past decade, the semiconductor industry has witnessed an ever-increasing demand in wafer-level integration and packaging technologies driven by increased requirements on functionality, performance, and efficiency. As one of the world’s leading specialty foundry groups for analog/mixed semiconductor technologies and more than thirty years of experience in volume manufacturing for automotive, industrial and medical applications, the X-FAB group has recognized this trend and broadened its offer accordingly. New integration techniques like wafer bonding, through-passivation vias (TSVs) processing, redistribution layers (RDLs) as well as the readiness to introduce new material systems like glass, polymers, noble metals, or compound semiconductors in a CMOS manufacturing environment clearly highlight the ongoing transformation process.

Next to the stated, also Die To Wafer (D2W) integration technologies receive an increased interest and represent one additional topic of these developments. Especially the Micro-Transfer-Printing technology (also referred as mass transfer or just transfer-printing) gained particular interest and has seen comprehensive developments over the past years.

To enable a heterogeneous chip integration, the micro-transfer-printing technology utilizes elastomeric stamps (see Figure 1 a; gray) with tunable adhesive properties to transfers devices or arrays of devices (commonly referred to as chiplets) from their native substrate (source wafer, orange) to a non-native target material (blue). This integration approach does not only enable heterogeneous 3D-wafer-level integration, it also provides several benefits like:

high potential throughput since thousands of chiplets can be transferred in a parallel manner by the elastomeric stamp,

the possibility to integrate smallest-scale devices,

the opportunity to effectively utilize expensive source wafers and to transfer chiplets to multiple devices or target wafers,

the high placement accuracy of 3σ < 1.5 µm, and

the opportunity to package devices with extremely short metallization tracks.

To offer this versatile technology, X-FAB has set-up a µTP pilot line for the development and industrialization of related processes in the MEMS clean room facilities in Erfurt, Germany.

Enabling an integration as depicted in Figure 1a) requires the development of several dedicated process sequences that have to be applied to source (orange) and target wafer (blue) to:

form chiplets that are appropriate for integration via µTP, i.e. the source wafer has to be made “print-ready”,

enable a high adhesion and thereby high print yield by adding a dedicated adhesion layer on the target wafer, and

allow wiring and passivation of the integrated devices by subsequent adhesion patterning, redistribution layer (RDL) formation and passivation layer deposition.

Out of the variety of potential integration option and material systems, X-FAB decided to focus on basically two integration scenarios, namely i) the preparation of print-ready SOI-based CMOS ASICs and ii) heterogeneous integration on CMOS wafers which both shall be explained in more detail within this presentation.

The general process to make devices print-ready involves

the chiplet singulation by multiple dry etches to form trenches down to handle wafer bulk material,

the tether formation by SixNy deposition and patterning to form a mechanical system that holds the chiplet in place and

the wet chemical release etch to separate the singulated µIC from the handle wafer.

Thereby, a print-ready µASIC is formed. It refers to a state in which the IC is separated from its original handle wafer and just kept in place by the tether systems as shown in Figure 1b. A basic requirement for the development of this process is the use of an SOI technology (such as X-FAB’s XT018), since the buried oxide layer (BOX) acts as the chiplet bottom protection in the final release etch.

Next to the scope of providing X-FAB’s µASICs for an integration via transfer-printing, X-FAB is actively working on the assembly of III/V semiconductor elements/chiplets on CMOS ICs/ wafers to improve the performance of the available CMOS devices or even add new functionality. Based on the availability of print-ready III/V semiconductor chiplets provided by X-FAB’s foundry partners, the integration process involves

the deposition of an adhesive layer on top of the CMOS wafer surface,

the transfer-printing integration of the III/V chiplets,

the final curing of the adhesive layer to adjust the material properties,

the patterning of the adhesive by a dry etching process to open the CMOS wafer contact pads,

the subsequent formation of a copper redistribution layer (RDL) and

finally, the passivation of the formed wafer-level package to protect the integrated chiplet and the metallization layer from environmental influences.

An example of such an integrated wafer-level package (without passivation) is illustrated in Figure 1 c).

Figure 1