bluuebunny/crossref_metadata_2025 huggingface dataset:
Lead Free Metal-Ferroelectric-Insulator-Semiconductor Devices for Non-Volatile Memory Appliactions
Authors: Medwal Rohit , Gupta Surbhi , Pavunny Shojan P. , Katiyar Rajesh K. , Thomas Reji , Katiyar Ram S.
Published: February 2020

The polarization bistability of the ferroelectric material offers the possibility to develop dense, energy efficient, fast and non volatile ferroelctric random access memory (FeRAM) with long retention and high endurance, as a promising replacement to both DRAM and Flash for the continued scaling. With this motivation, metal-ferroelectric-insulator-semiconductor (MFIS) structures were fabricated on p-Si <100> semiconductor substrate, by first depositing a 6 nm thick amorphous DyScO3 high-k insulator layer using metal organic chemical vapor deposition (MOCVD), followed by a 265 nm thick polycrystalline BiFeO3 (BFO) ferroelectric layer employing radio frequency (RF) sputtering, and finally a 40 nm thick platinum metal layer by DC magnetron sputtering. Electrical properties of the developed MFIS (Pt/BiFeO3/DyScO3/SiOx/Si) stacks were characterized as a function of thermal agitation (200 K to 400 K) to evaluate their device performance. Fat hysteresis loop was observed in the frequency dependent (1 kHz-1 MHz) capacitance-voltage (C-V) measurement with a memory window (ΔVFB) of 0.8 V at an exceptionally very low sweep voltage of ± 2 V.  The memory window increased to 2.2 V as the sweep voltage was raised to ± 4 V and beyond up to ± 8 V, indicating a highly stable device. Low leakage current (1.2 μA/cm2 at 4 V) and excellent data retention characteristics with distinguishable high and low capacitance values over the long time period of 106 sec, revealed strong charge storage potential of the fabricated device architecture. The non-linear hysteretic J-E curves of the MFIS structure were also investigated in detail as a function of temperature to understand the device reliability and the charge transport mechanisms. Piezoelectric force microscopy (PFM) and P-E hysteresis loop (domains reversal) studies were carried out to confirm the ferroelectric nature of the polycrystalline BFO thin films. The encouraging results achieved reveals that Pt/BiFeO3/DyScO3/SiOx/Si MFIS device architecture is a promising one for realization of FeRAM devices.
(Invited) Low Power Stt-Mram and Its Application to Normally-Off Processor
Authors: Shimomura Naoharu , Saida Daisuke , Daibou Tadaomi , Kato Yushi , Kamata Chikayoshi , Kashiwada Saori , Osawa Yuichi , Noguchi Hiroki , Ito Junichi , Fujita Shinobu , Yoda Hiroaki
Published: February 2020

Reduction of the power consumption of mobile electronic devices is one of the principal issues in current and future electronics technology. In particular, reducing the power consumption of the processor is critical because it increases as the processor’s performance improves.

Normally-off computing is one of the solutions. Standby power of a cache memory while the device power is on but the memory is idle accounts for a large proportion of the processor’s power consumption, which can be eliminated by shutting down the cache memory during the idle time and turning it on instantly when the memory becomes active. The key technology for the normally-off processor to reduce power effectively is a fast, low-power, non-volatile memory for the cache memory to replace the current SRAM cache memory.

Among the various non-volatile memories, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is the most promising candidate for the cache memory of the normally-off processor because of its potential performance in terms of fast switching and scalability. A magnetic tunnel junction (MTJ) storage element having perpendicular magnetization (p-MTJ) reduces the writing current of the STT-MRAM, which enables scaling of the STT-MRAM.

However, for power saving of the normally-off processor, small write current and short write pulse duration time must be achieved simultaneously. In other words, write charge, which is write current multiplied by write pulse width, is a key parameter for power saving. Toshiba demonstrated STT switching of the p-MTJ with write charge of 90 fC whose write pulse width was 1 ns and write current was 90 uA. Simulation of the processor’s power consumption with this STT MRAM showed good power saving.

Landau–Lifshitz–Gilbert (LLG) micromagnetic simulation of spin-transfer torque shows that a coherent precession of the spin plays an important role for fast switching of the p-MTJ. Initially, when the write current is applied to the p-MTJ, each spin precesses independently and the spin stays in the initial direction. It corresponds to incubation delay time. Immediately after the precession of each spin is synchronized and rotates coherently, switching of the spin begins. Therefore, the coherency of the spin precession needs to be controlled for further improvement of the fast switching of the p-MTJ.

A part of this work was supported by NEDO.
(Invited) Direct Physical Understanding in Memristive Devices and Corresponding Device Models
Authors: Strachan John Paul
Published: February 2020

Nanoscale devices composed of transition metal-oxide layers exhibiting a prominent resistance change (memristors) have been extensively researched for their technological potential. The mechanism for the reversible resistance change in these systems involves an interaction of many physical effects including electrochemistry, ion motion driven by electric fields and concentration gradients, and interactions with thermal effects. While a complete physical understanding is still in development, I will describe some of the insights gained from direct measurements using structurally and chemically-sensitive techniques with nanoscale resolution such as x-ray spectromicroscopy. Specifically, I will show recent studies utilizing scanning transmission x-ray microscopy (STXM) to observe oxygen migration in a working tantalum oxide memristor device. I will also describe ongoing work utilizing hard x-rays to probe the local bonding of Ta atoms within a memristor device. These studies will aid in developing a microscopic switching model, essential for guiding material selection, device engineering, and effective design of driving circuits. Ultimately, any utilization of this technology depends critically on predictive and microphysically accurate device models, and I will describe our work in this area.
(Invited) Mechanism Study of Reversible Resistivity Change in Oxide Thin Film
Authors: Hong Seungbum , Chang Seo Hyoung , Phatak Charudatta , Magyari-Kope Blanka , Nishi Yoshio , Chattopadhyay Soma , Kim Jung Ho
Published: February 2020

The field of applied physics is driven by the need to understand materials structure and electronic properties with the ultimate goal of harnessing them in functional devices such as nonvolatile memories. One needs to understand the mechanism, which dictates the behavior of the charged defects and electrons under external stimuli such as electrostatic potential, thermal gradient and photons, to obtain a more microscopic understanding of the system. Then, one arrives at a predictive description of designing functional devices.

            In the first part of the talk, we report the x-ray-induced reversible resistance change in 40-nm-thick TiO2 films sandwiched by Pt top and bottom electrodes, and propose the physical mechanism behind the emergent phenomenon. Our findings indicate that there exists a photovoltaic-like effect, which modulates the resistance reversibly by a few orders of magnitude, depending on the intensity of impinging x-rays. We found that this effect, combined with the x-ray irradiation induced phase transition confirmed by transmission electron microscopy, triggers a non-volatile reversible resistance change. Understanding x-ray-controlled reversible resistance changes can provide possibilities to control initial resistance states of functional materials, which could be useful for future nonvolatile memories.

            In the second part, we cover the investigation of Ta2O5 powder and oxygen deficient thin films using synchrotron x-ray studies at the Advanced Photon Source, combining x-ray diffraction, extended x-ray absorption fine structure (EXAFS) and resonant x-ray scattering spectroscopy (RIXS) and Ab initio band structure calculations. Ta-based resistive switching devices have been extensively investigated due to their fast switching and reliable endurance among other materials. Despite extensive recent interests, however, there is still lack of fundamental understanding of electronic structure and local structure of the Ta-based device. Oxygen vacancies play essential roles in the electric functionality of resistive switching devices, which is based on the formation and rupture of conducting paths within the insulating matrix. We found that there are strong correlations among oxygen vacancy number and positions and energy gaps. Ab initio band structure calculations successfully explain the evolution of the electronic excitation spectrum as a function of oxygen vacancy number and positions and importantly provide a predictive description of the oxygen deficient Ta oxide that may improve the desired performance based on atomic level design rather than the traditional trial-error methods.
(Invited) CH3NH3PbI3 Perovskite Solar Cells on Inorganic Materials: CuSCN and Crystal Silicon
Authors: Ito Seigo
Published: February 2020

Organo-lead halide perovskites have attracted much attention for solar cell applications due to their unique optical and electrical properties. With either low-temperature solution processing or vacuum evaporation, the overall conversion efficiencies of perovskite solar cells with organic hole-transporting material were quickly improved to over 20% during the last 3 years.  However, the organic hole-transporting materials used are normally quite expensive due to complicated synthetic procedure or high-purity requirement.  Here, we demonstrate the application of an effective and cheap inorganic p-type hole-transporting material, copper thiocyanate (CuSCN), on lead halide perovskite-based devices.  With low-temperature solution-process deposition method, a power conversion efficiency of 12.4% was achieved under full sun illumination.  This work represents a well-defined cell configuration with optimized perovskite morphology by two times of lead iodide deposition, and opens the door for integration of a class of abundant and inexpensive material for photovoltaic application.  Moreover, in the conference presentation, stability study of perovskite crystal and tandem solar cells (perovskite solar cells on home-made silicon solar cells) will be presented.
Reduction of Graphene Oxide through Intense Pulsed Light Towards Transparent Conductive Coating Applications
Authors: Draper Gabriel , Dharamsena Ruchira , Lavery Brandon , Druffel Thad
Published: February 2020

This work studies the capabilities and conditions for reduction of solution processed graphene oxide films through an Intense Pulse Light process towards flexible and additive deposition of transparent conductive coatings.  The film deposition and reduction processes occurred at room temperature without need for any vacuum processing.  The reduction for the graphene oxide is explored at different energy densities and the reduced graphene oxide’s conductivity displayed an increasing trend with increased Intense Pulsed Light processing.  Characterization techniques of Raman spectroscopy, UV-Visible spectroscopy, X-Ray Diffraction, and the four point probe method were employed for analysis.  Through the Intense Pulsed Light process, the characteristic Raman peak of graphene (2D) emerged.  When compared to the graphite (G) peak, the 2D/G ratio showed a general trend of increasing with higher energy inputs, going from 1.06 at 256 Jcm-2 and 1.76 at 1723 Jcm-2.  The defects (D peak) to G peak ratio, D/G, displayed a decreasing trend with increasing energy input going from 1 to .89 at 256 Jcm-2 and .38 at 1723 Jcm-2, suggesting that the Intense Pulsed Light process “heals” the films, in addition to the reduction.
Renewable Energy Forecast Using Machine Learning
Authors: Shao Ingrid , Lu Siyuan , Hamann Hendrik F.
Published: February 2020

Renewable energy forecasting becomes increasingly important as the contribution of solar/wind power production to the electrical power grid constantly increases.[1] Significant improvement in forecasting accuracy has been demonstrated by developing more sophisticated solar irradiance forecasting models using statistics and/or numerical weather predictions.[2] In this presentation, we report the development of a machine-learning based multi-model blending approach for statistically combing multiple meteorological models for improving the accuracy of solar power forecast. The system leverages upon multiple existing physical models for prediction including numerous atmospheric and cloud prediction models based on sky camera and satellite imagery as well as numerical weather prediction (NWP) products. Fig 1 shows an architectural view of this forecast system. Results using the system show over 30% improvement in solar irradiance/power forecast accuracy compared to forecast based on the best individual model.[3] A typical forecast time series plot is shown in Fig 2 together with measurement data and power from clear sky conditions. We also demonstrated that in addition to the parameters to be predicted (such as solar irradiance and power), including additional state parameters which collectively define a weather situation as machine learning input provides further enhanced accuracy for the machine learning result. This methodology has also been applied to wind power generation forecast and similar improvement in accuracy has been demonstrated.

The work is partially supported by Department of Energy SunShot Initiative contract #DE-EE0006017.

[1] R. Margolis,C. Coggeshall, J. Zuboy, “Integration of solar into the U.S. electric power system”, Chap 6 in SunShot Vision Study, US Department of Energy, http://energy.gov/eere/sunshot/sunshot-vision-study(2012)

[2] M. Dagne, M. David, P. Lauret, J. Boland, and N. Schmutz, “Review of Solar Irradiance Forecasting Methods and a Proposition for Small-Scale Insular Grids”, Renewable and Sustainable Energy Reviews, 27, p65 (2013)

[3] S. Lu, Y. Hwang, I. Khabibrakhmanov, H. Dang, T. van Kessel, F. Marianno, X. Shao, H. F. Hamann, “Machine Learning Based Multi-Model Blending for Enhancing Renewable Energy Forecasting”, American Meteorological Society Annual Meeting Abstract J6.4, Phoenix, AZ, January 4-8, 2015.

Figure 1
Efficiency Uniformization in Crystalline-Si Solar Cells By Numerical Simulation
Authors: Wang Laidong , Tao Meng
Published: February 2020

Efficiency uniformization is to control the efficiencies of mass-produced crystalline-Si solar cells within a narrow range, as efficiency dispersion is a major contributor to the high cost of PV systems. In order to achieve efficiency uniformization, it is necessary to evaluate the effect of material and process variation on cell efficiency, and then determine the key parameters and their allowed ranges. In this work, a simulation tool Synopsys Sentaurus is employed to perform a sensitivity analysis of cell efficiency on material and process variations. The analysis is performed on the most popular commercial cell structure. The typical ranges of material and process variations are used in the analysis. It is found that the diffusion temperature for the front emitter is the most critical parameter for cell efficiency. As the diffusion temperature in a POCl3 furnace varies from 830˚C to 770˚C, the cell efficiency drops by 5.9% absolute. Substrate resistivity and other process parameters including front metallization and antireflection coating are less important than diffusion temperature. The efficiency variation by these parameters combined is only 0.47% absolute. When the goal of efficiency uniformization is within 1% absolute of the target efficiency, the diffusion temperature is restricted to 815–840˚C. Methods to achieve more uniform emitter diffusion are outlined.
Electroplated Cu Grids on Crystalline Silicon Solar Cells and Its Long Term Degradation
Authors: Huang Qiang
Published: February 2020

Replacing screen printed Ag with electroplated Cu for silicon solar cell metallization is of great interest because of the high conductivity, low cost, and easy integration with laser patterning of the latter approach. The contact resistance and adhesion between Cu grid and Si emitter as well as the concern of Cu diffusion into the Si has motivated the invention of Silicide-Ni-Cu metallization.[1,2] In addition, the method of light induced plating or light assisted plating was invented decades ago and enabled the electroplating on the photoelectric device.[3-5] While this approach has been proposed for more than a decade, the details of the electroplating process for this new metallization scheme is not well understood. Furthermore, the impacts of this new metallization scheme on the long term stability of solar cells has not been studied until very recently.[6,7]

This paper will present the light assisted plating of Ni and the silicide formation on single crystalline silicon solar cells as well as the thermal degradation of the Cu metalized cells. Solar cells in real operation in the field will be challenged not only by heat, but also by moisture, radiation, and other natural stresses. While the reliability tests for Si solar cells with screen-printed Ag grid have been standardized already, the impacts of these stress elements are unknown to the Cu grids and are typically convoluted.

In this study, solar cells with Cu metallization were annealed at different elevated temperatures to speed up the degradation. Degradation behaviors of the grids after up to 3 years were studied. Different materials were also evaluated and compared for improvement in the grid reliability.  For example, figure 1 shows a comparison between the solar cells with the pure Ni layer and NiCo layer. The presence of Co apparently improved the stability of the final grids during the stress tests at elevated temperature. Further detailed discussion will be provided in the talk.

REFERENCES

D. A. Yates, US Patent 4,609,565 (1986).

K. Holdermann, US patent 5,543,333 (1996).

L. F. Durkee,  Patent No. 4144139 (1979).

L. A. Grenon, US patent 4,251,327 (1981).

G. Hamm and D. L. Jacques,  Patent No. 7955977 (2011).

J Bartsch, A Mondon, K Bayer, C Schetter, M Horteis, and S W Glunz, J. Electrochem. Soc., 157, H942 (2010).

J Bartsch, A Mondon, C Schetter, M Horteis, S W Glunz, IEEE 35th PVSC, Honolulu HI (2010).

Figure 1
Comparison of Different TiO2 Phase Structures and Morphologies on Dye-Sensitized Solar Cells
Authors: Tsui Tsz Cheung , Han Wei , Yeung King Lun
Published: February 2020

Dye-sensitized solar cells have been intensively studied as possible alternative to silicon solar cells. TiO2 is the most common photoanode material used in high performance DSSCs and can exist in different forms and polymorphs that can affect their performance. The most common forms of TiO2 are anatase and rutile. Generally, pure anatase exhibits higher photovoltaic activity compared to rutile TiO2 and is widely accepted that the observed incident photocurrent conversion efficiency is mainly due to a higher dye loading in anatase TiO2. Here, we demonstrate that anatase nanoparticles based DSSCs can have lower dye adsorption amount than rutile TiO2 but exhibit better photovoltaic performance. It is revealed that the ability which rutile and anatase TiO2 scatter incident light can be an important contributing factor to their performance difference. In this study, hydrothermal synthesis is the major method to fabricate anatase and rutile nanoparticles of different size and form.
Intense Pulsed Light Annealing of Perovskite Solar Cells
Authors: Lavery Brandon Wayne , Druffel Thad , Draper Gabriel , Sunkara Mahendra Kumar
Published: February 2020

Perovskite solar cells have produced significant interest in the scientific community. In the past 6 years, the perovskite solar cell has increased in efficiency from 3.8% to a staggering 20.1%. To add to the intrigue, the perovskite solar cell uses common low cost materials such as lead or tin and does not require the large manufacturing costs of using high temperatures and vacuum systems. Despite these advantages, the perovskite solar cell is still limited in efficiency due to the smaller crystal size of the perovskite material. The smaller crystal size of the perovskite material creates a more porous material with more grain boundaries that limit charge separation. Conventional methods of heating to enlarge the grain size of the perovskite crystals are limited due to the degradation reaction that converts the perovskite back to its precursor materials at 110 degrees Celsius. A newer technology called intense pulsed light is being used to generate light produced by a xenon plasma lamp at short millisecond pulses to create temperatures exceeding 500 degrees Celsius. The short bursts of heat enable higher temperatures to be reached by the perovskite crystals without degrading the material back to its precursors. Grain sizes have increased by over five times the grain sizes reported using conventional heating procedures.
Study of Nano-Filtration and Solvent Effects for Improving Efficacy of Organic Photovoltaic
Authors: Abdel-Fattah Tarek M , Younes Enas m , Namkoong Gon , El-Maghraby E M , Elsayed Adly , Abo Elazm A. H.
Published: February 2020

Conductive polymer such as poly (3,4-ethylenedioxythiophene) and polystyrene sulfonate acid (PEDOT:PSS) plays an important role for improving performance of organic photovoltaics (OPVs).

In this study, we investigated the effect of filtrating the buffer layer between the indium tin oxide (ITO) and bulk heterojunction (BHJ); poly(3-hexylthiophene) and [6,6]-phenylC71 butyric acid methyl ester (P3HT:PC71BM) used in our organic photovoltaics (OPVs) as shown in Figure 1.

This buffer layer consists of poly (3,4-ethylenedioxythiophene) and polystyrene sulfonate acid (PEDOT:PSS) doping with different solvents [isopropyl alcohol (IPA), ethanol, and methanol]. For comparison, we also studied the OPV devices without filtering the buffer layers.

The OPV devices fabricated with filtered buffer layer show better performance than OPV devices without buffer layer filtration.  The OPV devices with buffer layers; PEDOT:PSS/IPA, PEDOT:PSS/Ethanol, and PEDOT:PSS/Methanol after filtration showed 24 %, 16 %, and 11 % improvement in short circuit current density (Jsc) , respectively compared to the same OPV devices without filtration. The maximum exciton generation rates (Gmax), and the exciton dissociation probabilities [P (E, T)] were calculated for all fabricated OPV devices to explain the performance enhancement.

The data showed that the performance enhancement of OPVs devices after filtering the buffer layers originate from the large increase of Jsc.  Filtering the buffer layers enhanced light absorption of BHJs, increased the surface roughness, and decreased the sheet resistance of buffer layer after filtration.

Figure 1. A schematic diagram of ITO/PEDOT:PSS:different organic solvents/P3HT: PC71BM/Al

Figure 1
Solution-Derived NiO Hole Transport Layers on the PTB7:PC71BM Organic Solar Cells
Authors: Kiriishi Koudai , Hashiba Kousei , Qiu Jiayu , Fujii Shunjiro , Kataura Hiromichi , Nishioka Yasushiro
Published: February 2020

Energy demands are increasing all over the world, and renewable energy resources are needed. Photovoltaics is one of the attractive choice. Recently, organic solar cells have attracted great attention because of light weight and potentially low cost from printing at low temperature on flexible substrates. Traditional bulk heterojunction polymer solar cells consist of a transparent indium tin oxide (ITO) anode, a hole transport layer (HTL), a photoactive layer, and a top cathode. HTLs must have high optical transparency, good chemical stability, a large ionization potential, and good electron blocking capability. In a typical polymer solar cell, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) has been used as an HTL, and has a work function (Φ) of 5.2 eV. However, The PEDOT:PSS HTLs caused inferior device performance and degrade long term reliability due to their acidity, tendency to absorb water, and inability to block electrons effectively. Accordingly, the oxides which do not have these problems have been considered to be used as potential HTLs. Nickel oxide (NiO) has recently attracted a lot of attention because it can replace a PEDOT :PSS of HTL in solar cells. On the other hand, bulk hetero-junction (BHJ) solar cells based on [4,8- biz[Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo [1,2-b:4,5-b']dithiophene-2,6-diyl][3-fluoro-2-[(2- ethylhexyl)carbonyl]thieno[3,4-b]-thiophenediyl] (PTB7) and phenyl-C71-butyric-acid-methyl-ester (PC71BM) on ITO-coated glass substrates have recently been reported to have the efficiency as high as 9.2%. However, solar cells with a NiO HTL based on PTB7 / PC71BM have not been well investigated.

In this paper, we report on the performance of solar cells with a structure of glass/ITO/NiO/PTB7:PC71BM/LiF/Al, and also report the effects of the NiO thickness on the performance of the solar cells. To synthesize the precursor solution, we dissolved nickel acetate tetrahydrate (Ni(OAc)2·H2O) and mono ethanolamine (MEA) in 2-Methoxethanol. The NiO films were synthesized by spin-coating the NiO precursor followed by annealing on a hot plate in air at 350 °C.　The NiO thickness were optimized to realize better performance by changing concentration of nickel acetate tetrahydrate in 2-metxy ethanol solution used for spin coating deposition. The concentraton of Ni(OAc)2·H2O was prepared from 0.1 M to 0.4 M. Resulting in, the organic solar cell with NiO HTL using 0.2 M precursor shows highest performance, the device with NiO HTL using 0.4 M precursor shows worst performance. Furthermore, The solar cells with the NiO HTL layers showed improved long term reliability compared to the devices with PEDOT：PSS. As a result, the maximum power conversion efficiency of 5.14% was realized at 0.2 M of the nickel acetate tetrahydrate concentration. The PCE degradation of the solar cells with the HTL was compared to that of the control solar cells with PEDOT:PSS as an HTL.
Inverted Organic Solar Cells Based on PTB7:PC71BM with PFN Electron Transport Layer on ITO-Free Flexible PEN Substrate
Authors: Hashiba Kousei , Nagata Ryo , Kiriishi Koudai , Kataura Hiromichi , Fujii Shunjiro , Nishioka Yasushiro
Published: February 2020

Polyfluorene: poly(9,9,-bis(3'-(N,N-dimethyl)-propyl-2,7-fluorene)alt- 2,7-(9,9-dioctylfluorene)) (PFN) has been recently reported as a good electron transport layer for organic bulk-heterojunction (BHJ) solar cells by Chang et al. [1]. They fabricated BHJ solar cells based on [4,8-biz[Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl][3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]-thiophenediyl]] (PTB7)  and phenyl-C71-butyric-acid-methyl-ester (PC71BM) on indium tin oxide (ITO) glass substrates with PFN as an electron transport layer, and it showed the efficiency as high as 9.2%.

In this paper, we report on the improved long term reliability of similar solar cells with an ITO-free flexibleinverted solar cell structures of PEN/PEDOT:PSS/PFN/(PTB7:PC71BM)/MoO3/Au using, and found these devices showed much improved long-term reliability of the devices stored in air without any surface passivation layer. The J-C characteristics showed a slight reduction in the short cuircuit current density after storage in air for 4 days. The use of the PFN layer also significantly enhanced not only the open-circuit voltages and the power conversion efficiencies of the solar cells presumably due to the high electron transport efficiency and the better contact between the PEDOT:PSS cathode and the PTB7:PC71BM active layer. Although the resulted conversion efficiency was only 1.8% at this moment, and further process improvement will be continued.Furthmore we tried efficiency of the device change in the PFN thickness by spin-coating time.

[1] Yi-Ming Chang, and Chi-Yi Leu. Journal of Materials Chemistry A 1.21 (2013): 6446-6451.
(Invited) Topological States in Multi-Orbital Honeycomb Lattices of HgTe (CdTe) Quantum Dots
Authors: Beugeling Wouter , Kalesaki Efterpi , Delerue Christophe , Niquet Yann-Michel , Vanmaekelbergh Daniel , Morais Smith Cristiane
Published: February 2020

Recent advancements in colloidal chemistry demonstrate that two-dimensional single-crystalline sheets of semiconductors forming a honeycomb lattice can be synthesized by oriented attachment of semiconductor nanocrystals [1,2]. Inspired by these results, we have performed atomistic tight-binding calculations of the band structure of CdSe [3,4] and HgTe [5] sheets with honeycomb nano-geometry. We have also considered honeycomb super-lattices of quantum dots that could be made using nano-lithography of HgTe layers.

In the case of CdSe sheets [3], we predicted that their conduction band exhibits Dirac cones at two distinct energies and nontrivial flat bands. The lowest Dirac conduction band has s-orbital character and is equivalent to the π bands of graphene but with renormalized couplings. The conduction bands higher in energy have no counterpart in graphene; they combine a Dirac cone and flat bands because of their p-orbital character.

We also present very recent results on HgTe [5]. We show theoretically that honeycomb lattices of HgTe can combine the effects of the honeycomb geometry and strong spin-orbit coupling. The conduction bands, experimentally accessible via doping, can be described by a tight-binding lattice model as in graphene, but including multi-orbital degrees of freedom and spin-orbit coupling. This results in very large topological gaps (up to 35 meV) and a flattened band detached from the others. Owing to this flat band and the sizable Coulomb interaction, honeycomb structures of HgTe quantum dots constitute a promising platform for the observation of a fractional Chern insulator or a fractional quantum spin Hall phase.

[1] W. H. Evers, B. Goris, S. Bals, M. Casavola, J. de Graaf, R. van Roij, M. Dijkstra, and D. Vanmaekelbergh, Nano Lett. 13, 2317 (2013).

[2] M. P. Boneschanscher, W. H. Evers, J. J. Geuchies, T. Altantzis, B. Goris, F. T. Rabouw, S. A. P. van Rossum, H. S. J. van der Zant, L. D. A. Siebbeles, G. Van Tendeloo, I. Swart, J. Hilhorst, A. V. Petukhov, S. Bals, and D. Vanmaekelbergh, Science 344, 1377-1380 (2014).

[3] E. Kalesaki, C. Delerue, C. Morais Smith, W. Beugeling, G. Allan, D. Vanmaekelbergh, Phys. Rev. X 4, 011010 (2014).

[4] C. Delerue, Phys. Chem. Chem. Phys., 2014, doi: 10.1039/C4CP01878H.

[5] Beugeling, W. et al, Nat. Commun. 6:6316 doi: 10.1038/ncomms7316 (2015).
Effect of Hydrogen Partial Pressure on in-Situ Steam Generation Oxide Layer
Authors: Yun Jin Hyuk , Park Se Geun , Lee Young Ho , Lee Che Young , An Jung Su , Cho In Su
Published: February 2020

As device sizes are scaled down, it is very difficult to obtain the stable quality of gate oxide due to the lattice deformation and irregular oxide thickness in furnace type annealing system. In that reason, to eliminate the excessive heat budget and to improve oxide layer quality, In-Situ Steam Generation (ISSG) has been widely used in rapid thermal process (RTP) system. When the thermal heat is too low to break bond energy of oxygen molecular for O*(radical oxygen) , it is very difficult to grow the oxide layer in homogenous thickness and quality. So, to compensate this lack of O* for ISSG process, special reactant such as hydrogen gas is added. "H2 + O2 = H2O + O* + O2- + other species" is common chemical equation for ISSG process with H2 gas which helps to generate more radical oxygen.

 In this study, we improved the gate oxide reliability In ISSG process depending on the influence of H2 partial pressure and process temperature. An increased H2 partial pressure under the same temperature, it is found that an oxide growth rate has increased. In Si-O bonds strain analysis in the Si/SiO2 interface layer, due to the repairs of structural defects (three major structural defects , such as Si dangling bonds, weak Si-Si, and strained Si-O bonds), compressive strain has been decreased and also gate induced drain leakage (GIDL)  was improved. Based on the index of strain induced residual overlay values on the wafer surface, we confirmed that it became less sensitive than before. That implies less possibility of misalignment in lithography which brings about device failures.
The Effect of CoSi2 Formation Process on the CMOS Transistor Electrical Properties for Sub 100nm Memory Applications
Authors: Park Jeong Hoon , Kim Sang Jin , Lee Jung Ho , Yoo Chang Jun , Kang Hyo Jin , Lee Byung Cheol , Jeong Jae Goan
Published: February 2020

We investigated the effect of various processing conditions on the abnormal CoSi2 formation, such as well-known Co spike and crystal phase agglomeration. We also focused on the effect of CoSi2 related defects on the electrical properties in real sub 100nm ULSI devices. The mechanism of electrical failure was proposed and employed to clarify the relation between the various process conditions and electrical properties of our ULSI chips.

We used the Co metal sputtering and next thermal treatment like RTP(rapid thermal process). The effect of ion implantation condition (dopant species and concentration) and different Co deposition methods (capping material and in-situ thermal treatment) has been studied. To evaluate the electrical failure of transistors, we tried to check the full chip level drain leakage current, which is represented by “DLC_chip”, and unit transistor level drain leakage current, which is called by “DLC_unit”, at the same time.

It was found that with varying dopant species and concentration, the source-drain junction depth, dopant spatial distribution and local electric field could change, which brought about the DLC(drain leakage current) phenomenon. And, since it is believed to affect the electrical property of every single transistor, DLC_chip and DLC_unit degrade or improve simultaneously.

The different deposition methods of Co material led to the changes in the characteristics of CoSix formation. When we used the Ti/TiN capping layer and hot temperature PVD, the abnormal growth was suppressed and the interface became smooth, which could prevent the agglomeration and Co spike. For electrical properties, the DLC_chip of both cases showed the significant improvement, however, the DLC_unit showed a negligible change or even degrade a little bit contrary to DLC_chip. We concluded that, in spite of the degradation of DLC(drain leakage current) in typical transistor, the overall level of DLC_chip has improved due to the significantly decreased amount of defective sites like abnormal growth. It was also proposed that the small amount of defective site was eligible to govern the chip level DLC and responsible for electrical failure of a single chip.

Figure 1
Influence of Hydrogen Post-Implantation on Threading Dislocation Density in Strain-Relaxed Sige Layer
Authors: Park Jun-Seong , Kim Il-Hwan , Lee Gon-Sub , Shim Tae-Hun , Park Jea-Gun
Published: February 2020

According to International Technology Roadmap for Semiconductor (ITRS), the development of MOSFETs based on SiGe or Ge is necessary for the next generation technology beyond 10-nm C-MOSFETs, because electron and hole mobility of Ge substrate is three and four times higher than those of a conventional Si MOSFETs, respectively. However, due to the lattice mismatch of 4.2 % between Si and Ge, many threading dislocations are generated, resulted in increasing the leakage current of the C-MOSFETs. The threading dislocation density of graded SiGe layer utilized currently is higher than 105 cm-2, which is too high to be applied in mass production because of degrading productivity and performance of the C-MOSFETs. To overcome this drawback in realizing sub 10-nm C-MOSFETs, a novel process technology should be developed to reduce the threading dislocation density.

In this study, we designed a novel technology to reduce the threading dislocations in strain-relaxed Si1-xGex grown on Si substrate. We applied the H+ post-implantation which forms defect band at the dislocation clusters above the interface between the Si1-xGex layer and the Si substrate, acting as a dislocation sink. We investigated how the hydrogen-ion implantation followed by annealing affected the surface characteristics, such as dislocation pit and cross-hatch pattern density related the threading dislocation. In particular, the cross-hatch pattern density of the Si0.8Ge0.2 layer on the Si substrate was about 4x104 cm-1, as shown in Fig. 1(a). On the other hand, when hydrogen ions were implanted into the relaxed Si0.8Ge0.2 layer with an dose of 5x1015 cm-2, the cross-hatch pattern density was reduced to about 1.18x104 cm-1, as shown in Fig. 1(b). Also, there was a high threading dislocation density in the case of 30-at% Ge concentration, as shown in Fig. 2(a). However, for the case of hydrogen ion implantation, a dose of 5x1015 cm-2, both threading and misfit dislocations near the interface between Si0.7Ge0.3and Si substrate were significantly reduced, as shown in Fig. 2(b).

Therefore, we present the mechanism of the strain relaxation resulted in the formation of the threading dislocation in Si1-xGex/Si (100) substrate. In addition, we explain how H+ implantation affects the cross-hatch pattern density related the threading dislocation. Furthermore, we report the process technology and optimized the implanted energy, dose, and the position of dislocation sink in Si1-xGex/Si structure via ion implantation.

* This work was financially supported by the Brain Korea 21 Plus Program in 2015 and SiWEDS (Silicon Wafer Engineering and Defect Science).

Reference

[1] J. G. Park et al., Mat. Sci. Eng. B
134142-153 (2006)

[2] S. Takagi, Strained-Si CMOS Technology in Advanced Gate Stacks for High-Mobility Semiconductors, Springer Berlin Heidelberg 1 (2007)

Figure 1
(Invited) Is the Silicene a 2D Dirac Material?
Authors: Shirasawa Tetsuroh
Published: February 2020

Silicene, a 2D honeycomb layer of Si, has attracted much attention, since a Dirac fermion character like graphene was predicted.  Furthermore the silicene has a 2D topological insulator due to the 1000 times stronger spin-orbit coupling than graphene. The hypothetical silicene is a free standing layer, but in practice, experimentally fabricated silicenes so far are 2D layers of silicon epitaxially grown on substrates. We will discuss, on the basis of the structure determination on an atomic scale by using quantitative LEED analysis, the nature of the epitaxial silicenes on Ag(111) surface; the influence of the silicene-substrate interaction for the single layer silicene and if the multi-layer silicene fabricated on the substrate has the features expected for the free-standing silicene.
Plasma Dicing: Current State & Future Trends
Authors: Westerman Russ , Grivna Gordon , Mackenzie Ken , Lazerand Thierry , Doub Jason
Published: February 2020

Die singulation by mechanical sawing has been the primary technology used in semiconductor device fabrication for decades.  However as device structures continue to evolve to meet increasing performance requirements, the fundamental limitations of the sawing operation have been exposed.  Obtaining reasonable dicing throughput and yield for die less than 100µm thick is a challenge for the sawing operation.  An alternative to a saw-based dicing approach is die singulation using plasma etching.  This paper compares and contrasts plasma dicing before grind (DBG) and plasma dicing on tape (PDOT) processes to conventional mechanical saw processes, laser processes, and one another.  While saw and laser processes are serial in nature, plasma dicing is a parallel process that can offer higher equivalent cutting speeds and is supportive of the current trend to thinner wafers down to 50µm and beyond.  In addition to a wafer per hour throughput advantage, plasma dicing allows more die per wafer due to narrower lithographically defined streets; 90µm saw street widths compared to 5-20µm wide plasma dicing streets.  Along with higher die throughput, die singulated using plasma dicing have die strengths 9 times stronger than mechanically sawed die. In closing, the paper discusses issues and solutions related to PDOT process integration including maintaining tape integrity, street definition / masking approaches, and packaging compatibility.
Miniaturization and Biocompatible Encapsulation for Implantable Biomedical Silicon Devices
Authors: Souriau Jean-Charles , Herrera Morales Jorge Mario , Castagné Laetitia , Simon Gilles , Amara Karima , Boutaud Bertrand
Published: February 2020

Facing demographic aging and surging demand for advanced healthcare, the global market for active medical devices has greatly expanded these last years. Furthermore, microsystem improvement in term of miniaturization offers new perspectives for medical applications. Gradually the electronic devices that were previously external invade the human body in order to improve therapy or physiological parameter measurements. However, biological medium is a new environment for such devices and the packaging has to be reconsidered taking into account new constraints. First of all it is essential to preserve the human body from toxic elements exposure that are usually present on silicon devices such as Cu or Al. Moreover, for functionality and reliability aspect it is also crucial to preserve electronics parts from corrosive substances which constitute the major part of the body.

The objective of this paper is to present new strategy of packaging developed in the CEA-LETI for medical applications which include a Micro Electro-Mechanical Systems (MEMS) accelerometer and an Application-Specific Integrated Circuit (ASIC) inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration (fig1).

The electronic components are bonded on a wafer silicon interposer and covered by an additional silicon wafer which contain cavities. The wafer bonding is performed at the wafer level using eutectic AuSi solder. The gas content and hermeticity of the package were analyzed using Residual Gas Analysis (RGA) and the standard leak rate, which is assessed based on the formation of water droplet condensation in our package after 20 years, was estimated to ~6 10-13 atm.cc/s which guarantees a life time much more than 20 years.

The final silicon box is encapsulated with biocompatible materials that have high conformality deposition and act as good bi-directional barrier. Materials that had been reported in literature as biocompatible and compatible with fabrication in standard clean rooms were studied. These include Al2O3, BN, SiC, DLC(a-CH), HfO2, SiN, SiO2, SiOC, TiO2 and ZnO. Biodegradation tests were performed in phosphate buffer saline at different temperature. Changes in thickness and chemical composition were monitored by variable angle spectroscopic ellipsometry and x-ray photon electron spectroscopy. Non-cytotoxic test according to in-vitro tests outlined by the norm ISO10993-5 were carried out. Finally, Helium gas permeability measurements of selected packaging layers are also provided.

Figure 1
Microvia Filling in an Acidic Copper Planting Bath with Insoluble Anodes
Authors: Liu Chu-Chi , Dow Wei-Ping
Published: February 2020

Microvia filling of a printed circuit board (PCB) by acidic copper electroplating has been widely used in electronic industry. The filling mode of copper electrodeposition in microvia must be bottom-up form. Moreover, bottom-up filling phenomenon is believed to be related to the properties and interaction of plating additives. Especially, the interaction of three (accelerator, suppressor, leveler) components have significantly effect on copper filling performance.

It was confirmed that soluble anodes (i.e., P-doped Cu anode) have disadvantage when they were used in the acidic copper plating bath. For instance, the shape of the soluble anodes are changeable with operating time, which may causes non-uniform current distribution to form unequal copper thickness on substrate. Therefore, a special functional insoluble anode was used to replace the soluble anode and conventional dimensionally stable anode (DSA) to maintain better bath stability. The disadvantage of soluble anode can be improved by using the novel DSA.

In this work, a planting formula which was composed of chloride ions, suppressor (polyethylene glycol), leveler (quaternary ammonium species) and a novel accelerator instead of bis(3-sulfopropyl) disulfide (SPS). SPS is not appropriate for DSA system because of easy breakdown; therefore, we develop a novel accelerator, ACC, which has a longer lifetime and better performance for acceleration on copper deposition than SPS. Using DSA instead of P-doped Cu anode has another important contribution, that is, SPS reacts with the copper anode to produce Cu(I)-thiolate. The Cu(I)-thiolate is a strong accelerator in the presence of chloride ion. Cu(I)-thiolate will be accumulated in the copper plating bath to destroy the synergy between the suppressor and accelerator. DSA has no this issue because DSA has no copper. Herein, we will show that ACC combining with DSA can perform excellent copper fill in microvia.
Reduction of Thermal Expansion Coefficient of Electrodeposited Copper
Authors: Kondo Kazuo , Mukahara Shingo , Onuki Jin , Yokoi Masayuki
Published: February 2020

Introduction

Thermal expansion coefficient(TEC) mismatch between the chip and copper causes serious problems in 3D and PCB interconnections.  However no one even ever tried to reduce the TEC of the copper wiring formed by electrodeposition.   We are the pioneer to succeed in the TEC reduction of electrodeposited copper.

 Results

1.Figure 1 shows the thermal expansion results with and without the additive A.   Without the additive A the sample  is basically electrodeposited conventional copper and the thermal expansion is linear with the temperature(red line).   This linearity holds with multiple numbers of annealing.   With the additive A, this copper shrinks with raising the temperature for the first time anneal(green curve).   Most materials expands with raising the temperature, and this copper shrinks.   For the second time anneal, this copper shows about half of the TEC of conventional copper(blue curve) at 400°C.                        

2.There are no voids or seams and a perfect filling has been achieved of 4μm width and 25μm depth TSV.   In-situ SEM observation of pumping with annealing will be presented at the meeting.

3.Next, let’s discuss the grain size distribution by EBSD.   The electron back scattering diffraction(EBSD) observes the back scattering diffraction by irradiating electrons in the crystal sample.

The average grain size is 348nm.   With the additive A at 400°C,   the average grain size is 360nm and the grain size only grows 12nm.   Without the additive A, with annealing, 45 nm growth have been observed(1).

The deference in grain size between room temperature and 400°C is only 12nm with the additive A.   Additive A inhibits the grain growth at 400°C.

4.Symbols(⊥) indicate the dislocation(Fig.2).   The impurity from the additive A segregates at the grain boundaries.   This impurity which segregates at the grain boundary prevents the slipping transformation of piled up dislocations.   However, without additive A, this impurity does not segregate at the grain boundaries and the slipping transformation of piled up dislocation is large.    So the grain growth occurs without the additive A.

1 Kazuo Kondo, Shingo Mukahara, Taro Hayashi,  Minoru,Takeuchi,Takeyasu Saito, Naoki Okamoto, ,ECS, San Fransisco, USA, October(2013)

Figure 1