Effect of Schottky Contact Emitter on Electrical Characteristics in 2-Terminal Vertical Thyristor Based Capacitorless Memory
Authors: Kim Min-Won , Lee Byoungseok , Kim Ji-Hun , Oh Gyu-Jin , Ahn Chang-Wan , Yoo Sang-Dong , Shim Tae-Hun , Kim Eun Kyu , Park Jea-Gun 
Published: February 2020

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. Since the cell capacitor should be able to store sufficient charges of 25~30 fF/cell, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of n++-emitter/p+-base/n+-base/p++-emitter vertical structure using conventional Si technology. The two-terminal vertical thyristor based capacitorless memory cell having n++-emitter/p+-base/n+-base/p++-emitter structure could be implemented as cross-point memory array cells, as shown in Fig. 1. It utilizes latch-up features showing bi-stable current-voltage (I-V) characteristics, so that data 0 (D0) and data 1 (D1) states can be distinguished. Nevertheless, in two-terminal vertical thyristor based capacitorless memory, the latch-up and latch-down voltages decrease as the operation temperature increases, resulting in narrow memory window, as shown in Fig. 2. This is attributed to the fact that the carrier diffusion barrier decreases and carrier concentrations accumulated in base region required to generate latch-up decrease with increasing operation temperature. In our study, therefore, we propose two-terminal vertical thyristor based capacitorless memory with metal emitter replacing n++-emitter in order to reduce the temperature dependency of latch-up and latch-down voltages. The thermal conductivity of metal emitter is generally higher than that of silicon n++-emitter resulting in easier radiation of heat within the device. In addition, metal-emitter/p+-base/n+-base/p++-emitter structure can reduce the temperature dependency of latch-up and latch-down voltages since the metal emitter is immune to the decrease of bandgap with increasing temperature, unlike the silicon n++-emitter. We demonstrated the I-V characteristics depending on operation temperature of two-terminal vertical thyristor based capacitorless memory cell. Furthermore, we calculated the change of the bandgap of silicon and the magnitude of schottky barrier between metal emitter and p+-base junction in order to verify the effect of metal emitter on temperature dependency of latch-up and latch-down voltages. In addition, the heat flow and the dependency of the I-V characteristics on the metal emitter were investigated by TCAD simulation. Finally, we present the effect of schottky contact emitter on electrical characteristics in two-terminal vertical thyristor based capacitorless memory.

Acknowledgment

* This research was supported by Brain Korea 21 PLUS Program in 2019, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Figure 1