Simulation Analysis of the FIN Height Influence on the Electrical Parameters of Junctionless Nanowire Transistors
Authors: Ribeiro Thales Augusto , Cerdeira Antonio , Pavanello Marcelo Antonio 
Published: February 2020

Introduction: In the past few years junctionless nanowire MOSFETs appeared as one of the candidates for future technological nodes having great potential in digital and analog applications [1,2]. In these devices the fin height (HFIN) and the fin width (WFIN) have a strong influence on the electrostatic coupling that in turn becomes important for the ION/IOFF ratio [3]. Fig.1 shows the cross-section of a junctionless nanowire transistor with its geometrical parameters. This work analyzes the effects of the fin height on the electrical parameters of junctionless transistors through experimentally calibrated 3-D simulations. Results show that for long channel devices the better compromise is obtained with higher fin height, with higher ION/IOFF and smaller values of SS and DIBL, whereas for short channel ones the better compromise is found with smaller fin height, due to the reduced SS and DIBL and increased ION/IOFF ratio.

Results: To study the effect of the HFIN on these devices, simulations were made using Sentaurus TCAD from Synopsys. The simulations were calibrated with experimental data for long channel devices as a function of the WFIN and extrapolated for a study with variable HFIN. Fig. 2 shows the experimental and calibrated simulation for several WFIN as a function of the gate voltage with a drain voltage of 50mV [4]. The simulated devices used doping concentration of 4.1018 cm-3, Equivalent Oxide Thickness (EOT) of 1.38nm and work-function of 4.7eV. The box thickness of 150nm, WFIN of 13nm and 18nm, variable HFIN from 10nm to 60nm, channel length (LG) of 100nm, 50nm and 30nm and channel extensions of 30nm. The devices have either doped extensions with 5.1020cm-3 (to reduce the series resistance (RSD) [5]) or extensions with the same doping of the channel (referred as non-doped in this work). For these simulations, the crystallographic orientation of the device was considered and its effects on carrier mobility.

Fig. 3 shows the subthreshold slope (SS) as a function of HFIN and one can see that doping the extension increase the SS for all devices, showing the degradation caused by short channel effects [6]. One can see that for long channel (LG=100nm), the SS decreases as HFIN is increased, while the opposite occurs to the short channel devices (LG=30nm), i.e. the HFIN reduction improves the SS. Fig. 4 shows the threshold voltage (VTH) and the DIBL as a function of HFIN. For devices tending to double-gate architecture (HFIN>>WFIN) the VTH is weakly sensitive to HFIN while for smaller HFIN the VTH increases due to the electrostatic coupling of the gate. The same occurs with the DIBL and the improvement on these devices comes from a smaller HFIN.

Fig. 5 and Fig. 6 shows the On and Off currents (ION and IOFF, respectively) as a function of HFIN
, respectively. The ION
has been extracted at a gate voltage overdrive (VGT) of 0.8V and IOFF at VGT=-0.3 V. The ION values were compensated by the effect of the RSD. The use of doped extensions increase the ION, effect that is more pronounced on smaller HFIN and LG, whereas it induces a higher degradation on the IOFF for short LG than the long LG. The devices with non-doped extensions have better IOFF because of lower SS but the ION is much lower. Fig. 7 shows ION/IOFF ratio as a function of the HFIN
. We can see that for LG=100nm a higher ION/IOFF ratio comes from the increase in HFIN while for LG=30nm the better ratio comes from the decrease in the HFIN. It indicates that the better ION/IOFF is obtained moving towards double-gate shape for long-channel devices to nanowire shape for short channel ones. Also, the LG=50nm has values close to LG=100nm, but for the doped extensions the device has tendency similar to the LG=30nm.

Conclusions: For this work, we analyzed the main parameters of junctionless transistors with different HFIN and the effects for short LG with and without doped extensions shows a greater advantage with smaller HFIN (nanowire), while for long LG the advantage becomes more pronounced by the increase of HFIN as the device tends to become double gate.

Acknowledgements: The authors acknowledge Sylvain Barraud, Maud Vinet and Olivier Faynot for providing the samples and the founding agencies CNPq, CAPES and FAPESP [grant #2016/10832-1].

References:

[1] C.-W. Lee, et al. IEEE TED, 57,620-625,(2010).

[2] R. T. Doria et al. IEEE TED, 58,2511-2519,(2011)

[3] R. Yan et al. Microelectronics Reliability, 51,1166-1171,(2011).

[4] T. A. Ribeiro, et al. 32nd SBMicro,1-4,(2017).

[5] C.-H. Park et al, SSE, 73,7–10,(2012).

[6] A. Cerdeira, et al. 30th SBMicro,1-4,(2015).

Figure 1