Dependence of the Multi-Component Nature of Bias Temperature Instability in MOSFETs on Oxide and Device Type
Authors: Nguyen Duc , Kambour Kenneth , Kouhestani Camron , Devine Roderick A.B. 
Published: February 2020

Advanced metal-oxide-semiconductor field effect transistors, MOSFETs, have shown increasing sensitivity to microelectronic reliability based degradation phenomena and in particular, to negative bias temperature instability, NBTI. Previously [1] we have reported on a methodology to extract three distinct components of NBTI; recoverable charge, RC (oxide traps which discharge once the gate bias is zero), field recoverable charge, FRC (switching traps which seemingly discharged under positive gate bias), and interface state charge, IS (associated with the breaking of silicon-hydrogen bonds at the interface and do not discharge in an experimental time frame for temperatures below 180° C). Here we will report new results for NBTI for different oxide types and thicknesses and we will expand the methodology to include positive bias temperature instability, PBTI, oxide charging caused by the application of large positive biases. Both NBTI and PBTI will be examined for both p-channel and n-channel MOSFETS for each oxide type and thickness, which requires the measurement to be made in both accumulation and inversion modes.

NBTI “Pseudo DC” measurements using the methodology discussed previously [1] have been made at 120° C on p-channel and n-channel MOSFETs to extract the three components of BTI after 1500 s of stress. The stressing bias was chosen so that |Vgs,stress|/tox = 3.25 V/3.4nm in order to keep the approximately the same fields. Measurements of the source – drain current, Ids, were made in the linear regime and the measured Ids variations with stress were converted into threshold voltage shifts, DVth [1]. Measurements were performed on devices fabricated using an IBM proprietary process with gate widths of 5 mm and gate length/oxide thicknesses of 130 nm/3.4nm, 240 nm/6.2 nm, 90 nm/2.4 nm, and 240 nm/6.2 nm (processed with 90 nm technology) with a oxynitride gate. Measurements were also performed on HP devices with gate widths of 10 mm, gate lengths ranging from 350-500 nm and a Si02 oxide thickness of 7 nm.

It is worth noting that the sign of the trapped charges of each type depends upon the component being measured. In the case of IS, the sign of the charge can be inferred from the mechanism since dangling bonds are amphoteric. They will take on a charge based on the measurement Vgs, and thus for PMOS devices, the IS have positive trapped charge (negative voltage shift) whilst for NMOS the IS are negatively charged (positive voltage shift). The FRC charge component is always charged by holes and the RC charge is positive (negative voltage shift) except for PBTI in an NMOS. A sample table for the 130nm/3.4nm oxynitrided gate is shown below.

The existence of positive charge injection, for a PMOS under PBTI can be explained by realizing that PMOS devices usually have a p-type polysilicon gate electrode. When a positive gate bias is applied, electrons will be drawn to the interface between the gate oxide and the substrate; thus there are no holes present to tunnel into the oxide; however, the same field will drive holes from the poly silicon/oxide interface and this is where the positive charge is coming from under these circumstances.

A more puzzling result is that an NMOS under PBTI shows IS creation. Standard models of IS creation involve positive charge which either directly or through a complex process breaks the Si-H bond. These holes can come from the substrate for NBTI, or the polysilicon gate for a PMOS in accumulation, but the mechanism of hole injection for an NMOS undergoing PBTI is unclear.

[1] C. Mayberry, D. D. Nguyen, C. Kouhestani, K. E. Kambour, H. P. Hjalmarson and R. A. B. Devine, “Measurement and Identification of Three Contributing Charge Terms in Negative Bias Temperature Instability,” ECS Trans., 50 (4), 223-232 (2012).

Acknowledgements

D. D. Nguyen and C. Kouhestani are with COSMIAC Kirtland, AFB, New Mexico USA 87117. This material is based on research sponsored by Air Force Research Laboratory (AFRL) under agreement number FA9453-08-2-0259. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon.

The work performed by K. E. K. was supported by the US Air Force under contract FA9453-08-C-0245 sponsored, monitored, and managed by: United States Air Force Air Force Material Command, Air Force Research Laboratory, Space Vehicles Directorate, Kirtland AFB, NM 87117-5776.

Table 1 A matrix showing the threshold voltage shift for the various BTI components and type of charge trapped by each component.