bluuebunny/crossref_metadata_2025 huggingface dataset:
A Case Study on the Benefits of Functional Memory Access during ATE Test and Electrical Fault Isolation Techniques for Embedded SRAM
Authors: Goodrich Corey
Published: December 2020

Test coverage of embedded memories is often split between test modes. A BIST solution is typically used to isolate and test the memory array through test specific ports. The functional interconnect between logic and memory is tested with traditional ATPG test modes where a bypass cell on the scan chain is used to clock data through the memory. This approach may miss test coverage if the functional path is different from the test path[1]. Although commercial ATPG tools provide some capability in this area, the most advanced type of fault models which target small delay defects or cross talk faults are not as streamlined as they are for traditional fault models. Additionally, more advanced fault types don’t typically have the same diagnostic capability. In this paper, capabilities are developed for maximizing the effectiveness of test on embedded SRAM interconnects in an ATPG context. Also, a method is outlined to characterize and validate the timing robustness of the memory ports and provide a silicon diagnostic capability for localizing critical paths and isolating physical defects.
Functional Electronic Clones—The Most Dangerous New Counterfeit Threat Facing the Entire Electronics Industry Today
Authors: Sharpe Thomas
Published: December 2020

The entire electronics industry is now facing a much more insidious counterfeit threat than at any time in the past. The existence of cloned electronic components bearing the markings of major component manufacturers in today’s global supply chains has been clearly established within SMT’s labs over the past 3 years. The most worrisome aspect of these “made from scratch” fakes is their ability to easily pass current Industry-Standard counterfeit inspection processes and electrical testing to the manufacturers’ data sheet. My presentation will focus on several actual examples of this most concerning advanced counterfeiter capability and some of the processes utilized by SMT as an obsolescence component supplier and testing lab to mitigate this new and growing threat from making it to our OEM & CM customers.
In-Line Detection of Deep Trench Moat Underetch Defects Using eBeam Inspection
Authors: Hafer Richard F. , Messenger Brian , Dekker Mark T. , Patterson Oliver D. , Feng Yi , Lei Shuen-Cheng , Tang Xiaohu
Published: December 2020

E-beam Inspection (EBI) is used for in-line detection of defects in semiconductor manufacturing. This paper highlights a physical defect mode application where traditional defect inspection techniques, such as broadband plasma and dark field inspection were ineffective in finding the defects of interest. It describes the inspection setup and verification with failure analysis and the application of the technique. This inspection was implemented as a process monitor to detect excursions. The amount of process "ON" time after an etch-chamber part's change was identified as the main factor in MOAT defectivity. The correlation between EBI defect detection and leakage at in-line electrical test was further investigated by looking at each individual die and the leakage associated with the MOAT only. It was observed that the increased leakage could be due to another process factor in the process than a MOAT etch or a MOAT defect that was missed during the EBI inspection.
Studies on a Qualification Method (OSSD) for Microchip Al Bondpads
Authors: Younan Hua , Yue Shen , Yixin Chen , Chao Fu , Xiaomin Li
Published: December 2020

In authors’ previous paper, an OSAT [Optical, SEM (Scanning Electron Microscopy), Auger (Auger Electron Spectroscopy) and TEM (Transmission Electron Microscopy)] methodology was developed for qualification of microchip aluminum (Al) bondpads. Using the OSAT methodology, one can qualify microchip Al bondpads. In this paper, we will further study the NSOP (Non-Stick On Pad) problem on microchip Al bondpads. A new qualification methodology, OSSD [(Optical, SEM, and Surface and Depth profiling X-ray Photoelectron Spectroscopy (XPS)] will be proposed, in which XPS surface analysis is used to check the contamination level of fluorine and carbon on bondpad surfaces instead of Auger analysis. XPS depth profiling analysis will also be used to measure Al oxide thickness instead of TEM analysis. By using OSSD, Al bondpads can be qualified with both reduced costs and shortened turnaround times versus OSAT.
Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy
Authors: Chinone Norimichi , Cho Yasuo
Published: December 2020

Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.
Failure Modes Associated with Plastic Packages and Copper Bond Wires
Authors: Berger Kevin , Lilani Sultan Ali
Published: December 2020

The Aerospace and Defense (A&D) markets are starting to use plastic packages more significantly for Space and Military ruggedized applications. But plastic packages are also inherently less reliable than ceramic devices for A&D applications. The key to the successful use of plastic devices in A&D application is to qualify the devices for the intended application using industry accepted plastic encapsulated microcircuit (PEM) qualification techniques. This paper briefly recaps the test techniques known to be effective in assessing plastic part reliability. But more importantly, it presents actual PEM qualification data gathered over the last 15 years involving over 400 individual PEM Qual lots. The paper also shows the failures modes associated with plastic packages and Cu bond wires. SEM, X-Ray, and Acoustic Microscope images were obtained for the failure modes associated with plastic packages and Cu bond wire.
X-Ray Microscopy and Root Cause Analysis in Electronic Packaging
Authors: Mirkarimi L. , Gu A. , Hunter L. , Guevara G. , Huynh M. , Katkar R.
Published: December 2020

Advances in electronic packaging are fueled by the insatiable appetite that consumers have for bandwidth in mobile appliances. The technological answer to this demand is increase the interconnect count and shrink the pitch, solder volume and height. The features of interest and the defects in these packages are becoming increasingly smaller. Consequently, the characterization of these defects becomes more challenging due to the smaller size and new material structures. New package structures must pass the JEDEC standard tests and a critical part of qualifying new packages as products is proper identification of the root cause of failures. Therefore, innovative solutions to correct the fundamental problems in the development process enable new package solutions to be brought to the market. In this paper we describe an alternative failure analysis workflow involving X-ray microscopy which offers several advantages over standard imaging techniques. The nondestructive nature of x-ray microscopy enables engineers to image parts throughout the entire environmental stress cycle for more accurate determination of the root cause of failures. Additionally, a larger number of interconnects may be sampled, defect isolation in z direction for stacked die packages is made easier and subsequent imaging techniques may be used to complement the data. Both 3 dimensional images of defects as well as 2 dimensional cross sections will be shown to effectively analyze the true root cause of failures.
Root Cause Analysis of a Connector Time-Delayed Fracture
Authors: Singh Prabjit , Yu Ying , Davis Robert E.
Published: December 2020

A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.
Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-Thin Remaining Thickness
Authors: Chivas Robert , Silverman Scott , DiBattista Michael
Published: December 2020

Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.
Study on Effect of Electron Beam Irradiation in SEM-Based Nanoprobing on MOS Transistor
Authors: Noriko Hara , Nanami Bito , Mai Ebisuda , Suguru Tabata , Naoki Numazaki , Kazunori Masuda , Naoya Kami
Published: December 2020

Nanoprobing is an indispensable method for failure analysis to identify failure cells and to approach the root causes, providing electric characteristics of the failure of the MOS transistor. In this paper, the characteristic degradation on MOS transistors with SEM-based nanoprobing is studied to find out the critical accelerating voltage, comparing it to the characteristic obtained by the mechanical prober. In this experiment, n-type MOS transistors with thick gate oxide layer (40nm) were used. The effect of electron beam irradiation was also investigated. Significant change was not observed in n+(drain)/p-well IV curves. The paper looks at the influence of the additional phenomena during SEM-based nanoprobing analysis on a characteristics change of a specimen. For MOS transistor with thick gate oxide used in this study, irradiation influence is possibly more notable than normal voltage cell cases.
Analysis of SRAM Function Failure Due to Unformed CoSi2 Using Nanoprober and Transmission Electron Microscopy
Authors: Kim Jong Eun , Lee Jong Hak , Cho Jong Kyu , Ban Sang Hyun , Park Chang Su , Kim Nam Il , Kim Dae Woo , Wi Su Cheol , Sa Seung Hoon , Kim Sung Man , Kim Do Hwan , Lee Jae Won , Cho Min Su , Park Dong Bin , Park Ji Suk , Yi Su Hyun , Ha Jae Beom , Byun Kyung Su , Gu Tae Lim , Sung Jin Woo , Lee Jong Hwan , Son Soo Yong , Park Tae Su , Kim Jong Chae , Cho In Wook
Published: December 2020

In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.
Visible Light Probing Sample Thinning Using Targeted Lapping
Authors: Schlangen Rudolf , Lo William , Li Jane , Halteh Elia , Aguada John , Yang Jessica , Marks Howard
Published: December 2020

Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.
Studies on a Novel Qualification Method of Silicon Nitride Layer
Authors: Hua Younan , Khoo Bingsheng , Leong Henry , Chen Yixin , Chan Eason , Wang Jingyuan , Li Xiaomin
Published: December 2020

In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.
Decapsulation of IC Package by Atmospheric Microwave Plasma Needle
Authors: Kral Martin , Tsujita Yoichi , Suzuki Satoshi , Yamaichi Yasutoshi , Kando Masashi , Blajan Marius Gabriel
Published: December 2020

We present experimental results of IC package decapsulation carried out using Ar and O2 gas mixture remote plasma generated by atmospheric microwave plasma needle (“a-MPN”). Depth etch rate of up to 6.5 µm/min and volume etch rate of up to 0.1 mm3/min were shown to be obtained by a-MPN process operated at 15 W microwave power. SEM imaging suggested no damage to the bonding wire, pads, or passivation.
Failure Localization in a Multistage S-Band Power Amplifier
Authors: Rebello Clarence , Kolasa Ted , Modi Parag
Published: December 2020

During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.
Measuring the Effect of FIB Diffusion Exposure/Damage with a Gallium Focused Ion Beam for Semiconductor Circuit Edit Applications
Authors: Jain Rajesh , DiBattista Michael
Published: December 2020

Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.
3D Fault Isolation in 2.5D Device Comprising High Bandwidth Memory Stacks and Processor Unit Using 3D Magnetic Field Imaging
Authors: Orozco Antonio , Rusli Florencia , Rowlett Christopher , Zee Bernice , Qiu Wen , Chin J.M. , Foo Fang-Jie
Published: December 2020

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.
Automated Emission Data Registration and Segmentation for IC Analysis
Authors: Stellari Franco , Song Peilin
Published: December 2020

In this paper, the development of advanced emission data analysis methodologies for IC debugging and characterization is discussed. Techniques for automated layout to emission registration and data segmentations are proposed and demonstrated using both 22 nm and 14 nm SOI test chips. In particular, gate level registration accuracy is leveraged to compare the emission of different types of gates and quickly create variability maps automatically.
Making Synchrotron Tomography a Routine Tool for 3D Integration Failure Analysis through a Limited Number of Projections, an Adapted Sample Preparation Scheme, and a Fully-Automated Post-Processing
Authors: Fraczkiewicz A. , Moreau S. , Mourier T. , Bleuet P. , Autran P.-O. , Capria E. , Cloetens P. , Da Silva J. , Lhostis S. , Lorut F.
Published: December 2020

3D integration takes more and more importance in the microelectronics industry. This paper focuses on two types or objects, which are copper pillars (25 micrometer of diameter) and hybrid bonding samples. It aims at a statistical morphology observation of hybrid bonding structures, which underwent an electromigration test at 350 deg C and 20 mA. The goal of the study is two-fold. It is both to limit the overall time needed to perform a whole process flow, from sample preparation to reconstructed volume, and to limit the time of human intervention. To achieve this goal, three strategies are presented: improving the sample preparation scheme, reducing the number of projections with iterative algorithms and the Structural SIMilarity function, and automating the post-processing. The post-processing of the data is fully automated and directly renders the reconstructed volume. The high signal to noise ratio allows for further segmentation and analysis.
A Review of Well Imaging Techniques
Authors: Johnson Gregory M. , Nxumalo Jochonia , D’Aleo Christopher , Yates Brian , Khan Zaheer , Mollela Christopher
Published: December 2020

The timely and accurate imaging of problems in p/n junctions is increasingly important. Scanning Capacitance Microscopy is a current standard for precise 2D-mapping of carrier profiles, but care must be taken to choose the correct field of view because of the slow scan time. This paper provides commentary on the usefulness and possible pitfalls of a wide range of techniques available to the modern FA analyst, with examples from problem solving in a process development environment. SEM passive voltage contrast may provide imaging of junctions, but may be limited to N-well / P-well after special sample prep. OBIRCH provides reliable information on any current flows, but may not be selective specifically to those involving junction problems. Electron Beam Induced Current provides junction information at SEM resolution, but it may be hard for subtle problems to not be swamped out by massive signals. Multi-photon OBIC shows promise for high-resolution laser-based imaging, but may require highly special wiring. Photon Emission is an old standby. A case study is given which shows that one must be careful to match camera type and defect mechanism type in order to be able to see actual junction leakage.
Debugging Signal Corruption in Scan Chain Using Phase Laser Voltage Imaging
Authors: Ranganathan G. , Ravikumar V.K. , Phoa S.L. , Nemirow C. , Leslie N.
Published: December 2020

Laser Voltage imaging (LVI) is an established and widely used technique for isolating scan chain failures, especially those that are stuck-at a particular state. Enhancements such as second harmonic mapping have been beneficial in detecting a fault that is not stuck, but caused a shift in duty-cycle of the injected signal. In this paper, we describe Phase LVI which is constructed by integrating a lock-in amplifier as an enhancement to LVI for studying the relative phases between scan flops. Additionally we showcase case studies of successful fault isolation using phase LVI, where traditional LVI techniques were not successful.
Time Resolved LADA Using a Modulated Pulsed Laser to Fault Isolate Bridging Defects and Framing High Accuracy Physical FA Plan in 14 nm FinFET Technologies
Authors: Mattey Gaurav , Ranganathan Lava
Published: December 2020

Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.
Process Flow Employed for Parametric Test Structure Shorts Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries
Authors: Kodali Satish , Nasimullah Mia , Wei Yuting , Oh Chong Khiam , Beaudoin Felix
Published: December 2020

With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.
A Novel Method/Model for Fault Localization of a Subtle Open on a Large Thin-Film Resistor, Using Photon Emission Microscopy Technique and Electric Field Mechanism
Authors: Kumar Vikash , Udrea-Spenea Marian
Published: December 2020

Photon Emission Microscopy (PEM) is one of the commonly used and powerful techniques for fault localization which uses a sensitive camera (like CCD or InGaAs) to detect a light (photon) emission from an electrically biased device. The fault localization of an open anomaly can be a challenge for the failure analysis. This paper discusses a novel technique for localization of an open fault on a thin-film resistor using induced photoemission method. In this proposed method, an emission site is induced at the open fault location on the thin-film resistor. This method was found to be effective and it increases the success rate for an open fault localization on a thin-film resistor.
Resolve of OTP Failures through Electrical Simulation Using AFP Nanoprobing in Wafer Fabrication
Authors: Ang Ghim Boon , Chen Changqing , Ng Hui Peng , Ng Peng Tiong , Quah Alfred , Teo Angela , Tam Yong Seng , Mai Zhihong , Lam Jeffrey
Published: December 2020

This paper illustrated the beauty of AFP nanoprobing as the critical failure analysis tool in resolving the one-time programmable (OTP) non-volatile memory data retention failures through electrical simulation in wafer fabrication. Layout analysis, electrical simulation using Meilke’s method, UV erase methodology (to differentiate between mobile ion Meilke’s method contamination and charge trap centers) and a few other FA approaches were employed to determine the different root causes in the three OTP failure case detailed in this paper.. These include SiN trap center issue, poly stringers and abnormal layer at the initial CESL (Contact etch stop layer) nitride. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.
Novel IC Device Repackaging for SIL and Backside Analysis Capability
Authors: Muela Leandro , Kabadi Raj , Barbian Eric
Published: December 2020

A novel approach for solid immersion lens (SIL) assisted imaging and backside analysis of chip-on-board devices is presented. The procedure relies on complete die extraction from its original package, and repackage into a FA-friendly Plastic Quad-Flat Package (PQFP) chip carrier with inverted mold configuration, which enables access to the backside of the die through grinding/polishing or other methods. This procedure also relies on complementing use of device-specific DUT boards with generic arrangement of I/O, ground and power domains, coupled with a bench-test board equipped with the same pin-out configuration and a custom carrier built specifically for these DUT boards. This generic approach broadens the use of this solution to an entire family of devices and offers a balance of test capability leading to fault localization success and cost control.
Detection of Local Cu-to-Cu Bonding Defects in Wafer-to-Wafer Hybrid Bonding Using GHz-SAM
Authors: de Wolf Ingrid , Khaled Ahmad , Kim Soon-Wook , Kim Soon-Wook , Beyne Eric , Kögel Michael , Brand Sebastian , Djuric-Rissner Tatjana , Wiesler Ingo
Published: December 2020

This paper demonstrates the application of GHz-SAM for the detection of local non-bonded regions between micron-sized Cu-pads in a wafer-to-wafer hybrid bonded sample. GHz-SAM is currently the only available non-destructive failure analysis technique that can offer this information on wafer level scale, with such high resolution.
Non-Destructive Visualization of Bond Pad Defects using Acoustic Microscopy in the GHz-Band
Authors: Brand Sebastian , Kögel Michael , Altmann Frank , Oberhoff Stefan , Wiedenmann Michael , Krinke Jörg , Bosch Robert
Published: December 2020

GHz scanning acoustic microscopy (GHz-SAM) was successfully applied for non-destructive evaluation of the integrity of back end of line (BEOL) stacks located underneath wire-bond pads. The current study investigated two sample types of different IC processes. Realistic bonding defects were artificially induced into samples and the sensitivity of the acoustic GHz-microscope towards defects in BEOL systems was studied. Due to the low penetration depth in the acoustic GHz regime, a specific sample preparation was conducted in order to provide access to the region of interest. However, the preparation stopped several microns above the interfaces of interest, thus avoiding preparation artifacts in the critical region. Cratering related cracks in the bond pads have been imaged clearly by GHz-SAM. The morphology of the visualized defects corresponded well with the results obtained by a chemical cratering test. Moreover, delamination defects at the interface between ball and pad metallization were detected and successfully identified. The current paper demonstrates non-destructive inspection for bond-pad cratering and ball-bond delamination using highly focused acoustic waves in the GHz-band and thus illustrates the analysis of micron-sized defects in BEOL layer structures that are related to wire bonding or test needle imprints.
EBAC Analysis with Chemically Enhanced FIB Milling Assists Technique on Large Kerf/PCM Test Structure
Authors: Yap H.H. , Oh C.K.
Published: December 2020

The ability to expose a huge kerf/PCM (Process Control Monitor) test structure at the same level is limited from top down finger polishing. Also, in Scanning Electron Microscopy (SEM) the electron beam (e-beam) shift for electron beam absorbed current (EBAC) analysis is not able to cover the whole structure. The recently implemented technique described herein combines the focus ion beam (FIB) chemical enhanced milling method with EBAC analysis to stop the polishing at the upper layer and split the EBAC analysis into portions from the test structure. These help to improve the area of interest (AOI) evenness and enable the extension of the EBAC analysis.
Localization of Electrically Active Extended Defects in GaN Using a DualBeam FIB
Authors: Nshanian T. , Tracy B. , Ho H.
Published: December 2020

The Dual Focused Ion Beam (DFIB has been used to expose electrical fields associated with the charge of electrically active extended defects (ED) – (e.g. threading dislocations - TDs) in GaN structures. The localized electrical fields above electrically active defects in piezoelectric materials are shown to capture sputtered low energy ions, turning them back toward the surface and redepositing them on top of defects (TDs), forming Gallium-rich islands. This “Ga droplet” decorates EDs and significantly simplifies the process of locating EDs for TEM sample preparation and analyses. The size and shape of the Ga islands is correlated with the accumulated piezoelectric charge density at the EDs.
Analysis of Induced End-of-Life Failures in SRAM Through Nanoprobing
Authors: Dixon-Luinenburg Oberon , Fine Jordan
Published: December 2020

In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.
Special Sample Preparation Methodology for Cu Pillar Bump Characterization on Advance Thin Small Leadless Flip Chip with Copper Pillar Bump Interconnect Technology
Authors: Yen Gwee Hoon , Heng Chong Hock
Published: December 2020

Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.
Modern 2D & 3D X-ray Technologies for Testing and Failure Analysis
Authors: Villaraga-Gómez Herminso , Bell Joshua D.
Published: December 2020

Modern 2D and 3D X-ray technologies are among the most useful non-destructive testing methods that enable the inspection of an object's internal features without cutting or disassembling the sample. This paper discusses the basic operating principle, advantages, and disadvantages of 2D and 3D X-ray based approaches for testing and failure analysis and describes how these different methods have practical application for failure analysis and dimensional metrology. The techniques discussed are radiography, classical laminography, computed tomography, and computed laminography.
Machine Learning Assisted Signal Analysis in Acoustic Microscopy for Non-Destructive Defect Identification
Authors: Kögel Michael , Brand Sebastian , Altmann Frank
Published: December 2020

Signal processing and data interpretation in scanning acoustic microscopy is often challenging and based on the subjective decisions of the operator, making the defect classification results prone to human error. The aim of this work was to combine unsupervised and supervised machine learning techniques for feature extraction and image segmentation that allows automated classification and predictive failure analysis on scanning acoustic microscopy (SAM) data. In the first part, conspicuous signal components of the time-domain echo signals and their weighting matrices are extracted using independent component analysis. The applicability was shown by the assisted separation of signal patterns to intact and defective bumps from a dataset of a CPU-device manufactured in flip-chip technology. The high success-rate was verified by physical cross-sectioning and high-resolution imaging. In the second part, the before mentioned signal separation was employed to generate a labeled dataset for training and finetuning of a classification model based on a one-dimensional convolutional neural network. The learning model was sensitive to critical features of the given task without human intervention for classification between intact bumps, defective bumps and background. This approach was evaluated on two individual test samples that contained multiple defects in the solder bumps and has been verified by physical inspection. The verification of the classification model reached an accuracy of more than 97% and was successfully applied to an unknown sample which demonstrates the high potential of machine learning concepts for further developments in assisted failure analysis.
Contact Leakage Failure Analysis by EBIC, C-AFM and Nano-probing
Authors: Ho Kuang-Tse , Wu Chien-Wei , Chang Te-Fu , Yen Chia-Hsiang , Chan Ching-Hsiang
Published: December 2020

This research sets up failure analysis flow to verify failure mechanisms and root causes of different kinds of contact leakage. This flow mainly uses EBIC, C-AFM and nano-probing to do fault isolation and confirm electrical failure mechanisms. Appropriate sample preparation is also mandatory for FIB, SEM and TEM inspection.
Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission
Authors: Llamera Paul Hubert P. , Garcia-Awitan Camille Joyce G.
Published: December 2020

Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.
MBIST Driven SRAM Failure Analysis Using Laser Voltage Imaging and Laser Voltage Probing
Authors: Yang Jessica , Rengaraj Omprakash , Gupta Puneet , Schlangen Rudolf
Published: December 2020

Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.
A New Approach to IDDQ Failure Fault Localization Using Single Shot Logic (SSL) Patterns
Authors: Estores Rommel , Verleye Stefaan
Published: December 2020

In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area was partially isolated through fault localization, SSL patterns were created to control individual internal node logic states in a deterministic way. IDDQ was measured at each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two case studies will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.
Applying a Significant Protection Layer on Double Ex Situ Lift-out TEM Specimens to Protect Against Ion Beam Impact
Authors: Lin Chun-Hung , Hsu Hsin-Cheng , Lin Tsung-Yi , Lin Ru-Hui , Chen I-An , Hsu Pei-Lin , Chen Chao-Kun , Hsieh Iris , Yeh Chin-Chih , Lian Nan-Tzu , Yang Ta-Hone , Chen Kuang-Chao
Published: December 2020

Protection layers on double ex situ lift-out TEM specimens were investigate in this paper and two protection layer approaches for double INLO or double EXLO were introduced. The improved protection methods greatly decreased the damage layer on the top surface from 90 nm to 5 nm (or lower) during FIB milling. According to the property of different sample and its preliminary treatment in the FIB, we have the satisfactory approaches to be applied. Using this improved protection method, we demonstrate the structures within the TEM lamella can be observed without ion beam damage/implantation during FIB
Development of a Characterization Workflow for Reliable Porous Copper Films using SEM-FIB Tomography and Advanced Image Analysis
Authors: Wijaya Andi , Rosc Jördis , Sartory Bernhard , Brunner Roland , Eichinger Barbara , Mischitz Martin
Published: December 2020

The development of a characterization workflow for reliable pore characterization of porous metals especially for microelectronics applications is very important. This will help to provide design guidelines for the production and for the improved reliability of the devices. In this paper, we set up a workflow to accurately evaluate the porosity, of four different porous copper materials. The porous thin films are fabricated by using stencil printing. Within the workflow we use for the measurement non-destructive micro-X-ray computed tomography (ƒÝ-XCT) and destructive high-resolution scanning electron focused ion beam nano-tomography (nano-FIB tomography). The latter will be also used to calibrate the threshold for the ƒÝ-XCT image data, since a direct evaluation of the porosity from the non-destructively obtained ƒÝ-XCT image data due to resolution and contrast is not possible. Therefore, we develop an indirect histogram based evaluation method to get the porosity of the porous copper thin films. We validate and discuss the obtained results with respect to further studies.
New Paradigm for EBIC Amplifier on FIB X-section
Authors: Sanna Valle Valerio , Perez Guy , Bascoul Guillaume , Chauvin Helene , Viallet Benoît , Mura Giovanna , Apeddu Gian Paolo
Published: December 2020

Electron Beam Induced Current is a powerful tool for Scanning Electron Microscopy (SEM) imaging mode. In this paper, the history and evolution of this technique are discussed. Some important defects are presented as well as their technological interpretation. A new custom amplifier is presented and its implementation in Time Resolved EBIC (TREBIC) is also proposed, the main differences with EBIC are pointed out.
Capacitance Characterization of Gate to LDD Overlap Region to Understand Subtle Fail Modes in Advanced Node Technologies
Authors: Kodali Satish , Banghart Edmund , Davidson Kevin , Zhang Yu , Singh Jagar , Oh Chong Khiam
Published: December 2020

This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.
Лита копія медалі Моріца Саксонського з-під м. Кобріна Брестської обл., Республіки Білорусь
Authors: Sintchouk Ivan
Published: December 2020

Стаття присвячена атрибуції, що знайдена в Брестській обл. Республіки Білорусь, – литій копії медалі Моріца Саксонського з використанням її як заготовки для дукача. Етнографи Російської імперії відносять землі нижче Баранович до українських етнічних земель: межа проходить із заходу на схід між Брестом і Бєлостоком, Кобрином і Волковиськом, Пинськом і Слонимом. Місце знахідки – в межах ареалу української матеріальної культури. Герман Моріц (1696–1750) – позашлюбний син короля Речі Посполитої Августа II, французький військовий і державний діяч, військовий теоретик, генеральний маршал Франції. TPQ медалі визначається як 1777 р., оскільки на реверсі зображена скульптурна група мавзолею в кірсі Сен-Тома, скульптора Жана-Батіста Пигаля (1714–1785). Робота над мавзолеєм закінчилася у 1777 р., тоді ж, 20 серпня, із Страсбурзького собору була урочисто перенесена труна з прахом маршала. У другій половині 19 ст. на більшій частині території України дукачі як елемент матеріальної культури починають вироджуватися. Виходячи з відомих на сьогодні даних, артефакт слід датувати останньою чвертю 18 – першою половиною 19 ст.
EDUCAÇÃO INCLUSIVA: QUEBRA DE PARADIGMAS, DESAFIOS ENFRENTADOS NO COTIDIANO ESCOLAR
Authors: Schizzi Juliana , Pedrolo Luciana , Gregory Vera Lúcia , Bordin Cristiane de Oliveira Centa
Published: December 2020

RESUMO

O presente trabalho tem por objetivo relatar experiências tanto positivas, quanto negativas, enfrentadas no cotidiano escolar, focando o processo da educação inclusiva como forma de interação e socialização de crianças com necessidades especiais em escolas de Ensino Regular. Trazemos também algumas dificuldades enfrentadas pelos educadores, quando os mesmos chegam até as escolas e se deparam com desafios complexos, onde a falta de uma preparação específica no atendimento educacional especializado (AEE) faz toda a diferença. Sendo assim, o trabalho pedagógico com crianças que necessitam de acompanhamento especializado enfrenta sérias dificuldades. Em virtude disso, foi realizado um questionário simples para coletar dados, tanto de educadores que trabalham na Educação Infantil, quanto no Ensino Regular, tendo como foco da pesquisa o levantamento de dados para investigar se os professores estão preparados ou não para encarar o desafio de trabalhar com alunos inclusos.
Diagnostic Modality in Spine Disease: A Review
Authors: Kim Gang-Un , Chang Min Cheol , Kim Tae Uk , Lee Gun Woo
Published: December 2020

Spine diseases are common and exhibit several causes, including degeneration, trauma, congenital issues, and other specific factors. Most people experience a variety of symptoms of spine diseases during their lifetime that are occasionally managed with conservative or surgical treatments. Accurate diagnosis of the spine pathology is essential for the appropriate management of spine disease, and various imaging modalities can be used for the diagnosis, including radiography, computed tomography (CT), magnetic resonance imaging (MRI), and other studies such as EOS, bone scan, single photon emission CT/CT, and electrophysiologic test. Patient (or case)-specific selection of the diagnostic modality is crucial; thus, we should be aware of basic information and approaches of the diagnostic modalities. In this review, we discuss in detail, about diagnostic modalities (radiography, CT, MRI, electrophysiologic study, and others) that are widely used for spine disease.