bluuebunny/crossref_metadata_2025 huggingface dataset:
Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging (SiP)
Authors: Lau John , Tzeng Pei-Jer , Zhan Chau-Jie , Lee Ching-Kuan , Dai Ming-Ji , Chen Jui-Chin , Hsin Yu-Chen , Chen Shang-Chun , Wu Chien-Ying , Li Li , Su Peng , Xue Jie , Brillhart Mark
Published: October 2015

The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm × 28mm) with double sided wiring layers. This interposer is used to support a very large chip (22mm × 18mm) on its top-side and 2 smaller chips (10mm × 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm × 40mm) (with ordinary lead-free solder bumps). The lead-free micro solder bumps (Cu/Sn) on all the chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn.
GHz High Frequency TSV for 2.5D IC Packaging
Authors: Chen Chi-Han , Lu Kuan-Chung , Hung Chang-Ying , Lee Pao-Nan , Wang Meng-Jen , Hung Chih-Pin , Tong Ho-Ming , Horng Tzyy-Sheng
Published: October 2015

TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process.

From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application.

Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.
A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Reference, Legacy, & Premium Backplane Channels
Authors: Morgan Chad , Healey Adam
Published: October 2015

Standards bodies are now examining how to increase the throughput of high-density backplane links to 25 Gbps. One method for achieving this is to construct premium backplane links utilizing advanced materials and connectors. Another approach is to re-use legacy backplanes by employing PAM-4 signaling at half of the baud rate. For PAM-4 to offer an advantage over NRZ, the signal-to-noise ratio (SNR) at the slicer input, i.e. after equalization, must be ∼9.5 dB better than NRZ to overcome loss of separation between signal levels. This paper will examine 25 Gbaud NRZ and 12.5 Gbaud PAM-4 signaling across varying levels of channel insertion loss and crosstalk. The paper provides a reliable reference for engineers to use when considering when it is appropriate to use NRZ signaling at 25 Gbaud and when it is appropriate to use PAM-4 signaling at 12.5 Gbaud for successful high-density backplane operation.
Measurement-based Signal Quality Test of High-speed TSV Channel
Authors: Kim Heegon , Cho Jonghyun , Jung Daniel H. , Kim Jonghoon J. , Kim Joungho , Pak Jun So , Choi Kwang-Seong , Bae Hyun-Cheol
Published: October 2015

In this paper, measurements of high-speed TSV channel were performed in frequency- and time-domains for the signal quality test. The channel loss was measured up to 20 GHz in frequency-domain and the eye-diagram was measured up to 10 Gbps in time-domain. To analyze the measurement results, the equivalent-circuit model of high-speed TSV channel and the worst eye-diagram estimation algorithm were introduced. By using them, the impacts of silicon-conductance and oxide-capacitance on channel loss were analyzed. Moreover, the negligible impact of reflection on the signal quality of the high-speed TSV channel was also analyzed. These measurement-based signal quality analyses can provide the useful insight and design guidance for high-speed TSV channel.
Thin-Film Signal and Power Redistribution Layers Based on AL-X and Cu
Authors: Bailey John , Pfeiffenberger Alexander , Ellis Charles , Palmer Mike , Issac-Smith Tamara , Hamilton Michael
Published: October 2015

Use of unpackaged die in advanced integrated systems (i.e., 3-D integrated systems) calls for dense interconnection schemes with controlled impedance for high-speed signal routing and minimal impedance for efficient power distribution. We have evaluated a new material set for use in a thin-film-based redistribution layer (RDL) that consists of Asahi Glass AL-X spin-on low-k dielectric polymer and electroplated copper metallization. This technology allows fan-out and interconnection of high-speed signals and power to/from die pads on pitches sufficiently less than 100 μm directly to companion die over short distances or for transition to underlying board metallization for longer transmission distances that may require lower signal loss. This technology is demonstrated using Si wafers onto which the thin-film RDL is fabricated. We have developed and described the fabrication procedures used to construct multiple interconnected layers of AL-X / Cu, which are compatible with standard wafer level packaging (WLP) processes. We have also evaluated the performance of this technology for high-speed digital signal transmission by characterizing frequency parameters (i.e., S parameters) of single-ended and differential strip-line transmission line structures. We have optimized transmission line geometries for transmission of signals at rates greater than 25 Gbps. In addition to high-speed signal redistribution capabilities, we have characterized power redistribution capabilities of this technology. Results of the signal and power integrity measurements and simulations performed in this work are presented.
The Application of PEEK to Implantable Electronic Devices Packaging: Water Permeation Calculation Method and Maximum Lifetime with Desiccant
Authors: Dahan Nathaniel , Donaldson Nick , Taylor Stephen , Sereno Nuno
Published: October 2015

When packaging electronics to protect from the effects of water vapour, it is essential to be able to predict how moisture will permeate the enclosure. In the context of short term medical implants for instance, packages made of a ‘permeable’ material such as a polymer may be acceptable, provided calculations and tests show that low internal relative humidity is guaranteed for the required device lifetime. This paper presents a method to evaluate the water vapour permeation into a package which has walls or elements of different thicknesses or properties. Tests are described to evaluate the validity of this model experimentally. The method is adapted for the use of desiccant and achievable lifetimes for PEEK packages with silica gel are investigated.
Precision Jetting of Glob Top Materials – a methodology for process optimization
Authors: Becker K.-F. , Koch M. , Bauer J. , Braun T. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D.
Published: October 2015

During the last years, jetting processes for higher viscosity materials have gained widespread interest in microelectronics manufacturing. Main reasons for this interest are high throughput/productivity of jetting, contactless material deposition, high volume precision and freely designable deposition patterns.

In previous studies we have demonstrated the jetability of different resin-based materials, being exemplary for unfilled adhesive, for low viscous Underfill resin and for higher viscosity Glob Top materials. The focus of our previous work was on the dosing of Underfill material, where this study is dealing with more complex materials – Glob Top resins. These materials are non-Newtonian fluids - the flow curves of the filled materials can be described by models of Cross or Herschel/Bulkey. Furthermore, highly filled and paste-like mixtures show a significant time dependency of formation of structural equilibrium after deformation, so process development needs to take this into account, so detailed material analysis is described within this study.

To illustrate the potential of jetting as a flexible and powerful tool for Chip on Board encapsulation, both, simple test-structures (dots, lines, dams) but also more complex demonstrators have been assembled using wire bonded ICs on ceramic substrates and encapsulants showing viscosities ranging from 10 Pas to > 100 Pas. Not only basic process data on droplet diameter, resulting material depot size and positioning accuracy have been evaluated, but also statistical means have been employed to determine process homogeneity and stability depending on the respective parameter set. Additionally, the whole process was followed by a high-speed camera system, providing detailed information on actual jetting behaviour during droplet release, flight and impact.

Summarized this paper gives a detailed insight into jet process development for high viscosity Glob Top materials and describes process design rules and limitations and thus allows the optimized use of advanced jetting technology for Chip on Board assemblies.
Highly Conducting Carbon Nanotube Composite for Light-Weight Electric Heating Unit Applications
Authors: Chu Kunmo , Park Sunghoon , Lee Sangeui , Kim Dongouk , Sohn Yoonchul , Kim Dongun , Bae Minjong , Kim Hajin , Han Intaek
Published: October 2015

The fabrication of highly conducting carbon nanotubes (CNTs) / polydimethylsiloxane (PDMS) composite is presented with the aim of electric heating unit applications. High shear processing techniques were used to separate highly entangled multi-walled carbon nanotubes (MWNT) with high aspect ratio (∼5000). No notable agglomerates or phase separation between the CNTs and PDMS matrix are observed, and the CNTs are well dispersed. It is observed that the approximate percolation threshold is found to be below 0.1 vol.%, which is a lower value than previously reported. The resulting conductivity of the CNT/PDMS composite is about 223 S/m at 5.7 vol.% CNT loading. The fabricated CNT/PDMS composites can be quickly heated from room temperature to 200°C within 30 seconds by applying a DC voltage of 12V. Our proposed system of using CNT-polymer composites together with our obtained results could be used as a basis for light-weight and high effective heating unit applications.
Glass-Insulated Bonding Wire Scales to Support advances in Miniaturization
Authors: Stephan Dominik
Published: October 2015

The semiconductor industry is facing a major challenge today – it must adapt to the constant need to miniaturize, and in order to accommodate this major trend the entire ecosystem must adapt and evolve. While the current standard materials and tools make it possible to scale down to a certain level, it is simply not enough.

Although there are efforts to make smaller wires, wire makers, wire drawing equipment and tool makers are working toward a boundary of existing methods. When wire diameter is successfully reduced, more issues correlated with wire uniformity and production control of the low required tension during the drawing process appear, these may result in low yield and higher cost. Another limiting point is the drawing die which experiences yield issue and high erosion at the very small diameter.

It is clear that there is a need for smaller wire diameter to support advances in miniaturization. There are, however, intrinsic challenges of physics that may limit the ability to manufacture and use such wire, most of which are related to the mechanical strength, and concerns about wire stability and shorting.

This presentation will explore the question of bonding wire scalability, and will discuss a possible solution. Data will be provided to show how glass coated wire may effectively address issues related to the mechanical strength and stability of wire and enable relaxed chip design rules while providing a smaller effective wire diameter on smaller bonds.
A Novel Packaging Concept for Electronics in Textile UHF Antennas
Authors: Boehme Christian , Vieroth René , Hirvonen Mervi
Published: October 2015

In this paper, we present the concept and describe the miniaturized packaging of a textile integrated wireless body-area-network (WBAN) node. The electronic modules have been laminated onto a textile antenna, by applying cutting edge integration technologies. The designed 868MHz UHF antenna is wrapped around the electronic module and consists of two layer of textile. Moreover, a layer of conductive textile has been mounted on a layer of non-conductive textile. For the mechanical and the electrical connection we have employed a thermoplastic non-conductive adhesive (NCA) and an isotropic conductive adhesive (ICA). The uniqueness of this process is to demonstrate how the electronic module was placed inside a textile UHF antenna. Precise packaging is important to avoid the negative effects of electronic components inside an UHF environment. The reliability of the mechanical and electrical connection of the electronic modules was tested. These tests were used to evaluate the adhesion strength between the electronic module and the base fabric (non-conductive textile). Moreover, they provided information about the contact resistance between the conductive textile and the antenna feed lines of the electronic module. Additionally, performed cross sections and X-Ray photography provided more insight in the reliability. The achieved results demonstrate the successful operation of the designed System in Package (SiP), consisting of an electronic module attached to a textile UHF antenna.
Electrical and Mechanical Performance of Quilt Packaging with Solder Paste by Pin Transfer
Authors: Zheng Quanling , Khan M. Ashraf , Kriman Alfred M. , Bernstein Gary H.
Published: October 2015

Electrical and mechanical performance of Quilt Packaging (QP), a 2D system-in-package chip-to-chip interconnection, is presented. QP employs contacts at the edges of integrated circuit dies along their vertical surfaces. Based on 3D HFSS simulations, the self-inductance of QP can be less than 0.01 nH, and the self-capacitance can be less than 0.034 pF due to the shortness of the interconnection path. QP interconnection using solder paste with pin transfer is presented, and mechanical reliability is evaluated. A new pull test system specifically designed for QP is presented. The pull force that causes failure in a set of edge interconnects totaling 3 mm width of nodules is about 658 gram-force for Sn63Pb37 and 953 gram-force for SAC305.
Planar Power Inductor with Magnetic Film for Embedded LSI Package
Authors: Fujii Tomoharu , Kobayashi Kazutaka , Shimizu Hiroshi , Nakazawa Shinji , Sato Toshiro , Sato Fumihiro , Kobayashi Hiroki
Published: October 2015

A power inductor component is relatively very thick and large shape. Therefore, these components are not appropriate feature to be embedded into a LSI package and mounted nearby a LSI chip, it is challengeable to make the embedded application. However, LSI power delivery system is going for low voltage and large current, and losses between power supply and loads impacts on the power supply efficiency characteristic. In order to solve this problem, miniaturization for a power inductor is needed to realize the embedded applications.

As one of approaches to realize the power delivery systems, the planar power inductor with Zn-Ferrite film has been studied for the next generations. A structure of planar power inductor was designed to be configured 2-turn inner copper spiral coil covered with top and bottom magnetic core. The Zn-Ferrite film used as a magnetic core has a high resonance frequency around 300MHz and high saturation magnetization of 0.6T or more, and this film can be formed in low temperature, which can be handled in parallel way to fabricate an organic package.

We have developed the organic package with employing the power inductors covered with Zn-Ferrite as prototype of the embedded application, and evaluated the electrical and magnetic characterizations.

The thickness of embedded planar power inductor covered with Zn-ferrite film is 50um, and the size is 850um squares. Q factor is 10 to 13 in 30MHz to 100MHz. The degradation of inductance caused by the superimposed current does not happen without changing until 3A.
Investigation of electrical performance and mechanical reliability of device embedded power module
Authors: Tanaka Masaya , Sawada Keisuke , Serizawa Toru , Sagara Shuji
Published: October 2015

We investigate electrical properties and reliabilities of DC-DC converter module with the use of embedding technology. We designed and manufactured two kinds of DC-DC converter module as a means of verification for these characteristics. One is the surface mounted module with side-by-side structure for reference and another is the device embedded module.

To evaluate time-domain simulation analysis accurately, we conducted accurate built circuit model of the DC-DC converter IC and extracted multi-port S-parameters models including multi-coupled wiring models primarily. As a result of time domain voltage waveform simulation using these accurate built circuit model and multi-port S-parameters, we verified that the device embedded power module is excellent in electrical characteristics of switching operation. We demonstrated in this study that miniaturization of approximately 25% for the module size and voltage noise improvement of approximately 50% compared with the surface mounted power module when applying device embedding technology. Furthermore we validated these electrical performances of the device embedded power module by using experimental measurement method. We evaluated mechanical and electrical reliabilities of the device embedded power module collaterally, in consequence mechanical and electrical reliabilities of the device embedded module holds the sufficient performances
Obsolescence Management & the Impact on Reliability
Authors: Tulkoff Cheryl , Caswell Greg
Published: October 2015

Component obsolescence management is a strategic practice that also mitigates the risk of counterfeit parts. Left unchecked, obsolescence issues increase support, development and production costs. So, planning ahead is critical. For companies that do proactively manage component availability and obsolescence, the effect of long-term storage on manufacturability and reliability is the area of major concern. Many issues can arise depending on the component technology and storage environment. Reliability concerns to consider include solderability, stress driven diffusive voiding, moisture, Kirkendall voiding, intermetallics/oxidation and tin whiskering.

When component obsolescence isn't planned for, the secondary market is often the supply chain of last recourse. While it is possible to get high quality, genuine parts, it is also possible to get nonconforming, reworked, or counterfeit components. And, it is increasingly difficult to differentiate genuine parts from their counterfeit equivalents. Historically, the secondary market provided a mechanism for finding parts in short supply or at reduced cost. Today, high-reliability system manufacturers are less willing to risk contamination of their supply chain with potentially substandard parts in order to save a few dollars on the cost of a part.

This paper will cover obsolescence management strategies, relevant industry standards, use of managed supply programs (MSP) and contract pooled options, plus long term storage recommendations and practices.
Development of High-Dielectric-Strength Ceramic Film Capacitors for Advanced Power Electronics
Authors: Ma Beihai , Narayanan Manoj , Liu Shanshan , Tong Sheng , (Balu) Balachandran U.
Published: October 2015

Ceramic film capacitors with high dielectric constant and high breakdown strength are promising for use in advanced power electronics, which would offer higher performance, improved reliability, and enhanced volumetric and gravimetric efficiencies. We have grown lead lanthanum zirconate titanate (PLZT) on nickel foils and platinized silicon (PtSi) substrates by chemical solution deposition. A buffer layer of LaNiO3 (LNO) was deposited on the nickel foils prior to the deposition of PLZT. We measured the following electrical properties for PLZT films grown on LNO buffered Ni and PtSi substrates, respectively: remanent polarization, ≈25.4 μC/cm2 and ≈10.1 μC/cm2; coercive electric field, ≈23.8 kV/cm and ≈27.9 kV/cm; dielectric constant at room temperature, ≈1300 and ≈1350; and dielectric loss at room temperature, ≈0.06 and ≈0.05. Weibull analysis determined the mean breakdown strength to be 2.6 MV/cm and 1.5 MV/cm for PLZT films grown on LNO buffered Ni and PtSi substrates, respectively. Residual stress analysis by x-ray diffraction revealed compressive stress of ≈-520 MPa in the ≈2-μm-thick PLZT grown on LNO buffered Ni foil, but a tensile stress of ≈210 MPa in the ≈2-μm-thick PLZT grown on PtSi substrates.
Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging
Authors: Kenny Stephen , Matejat Kai , Lamprecht Sven , Mann Olivier
Published: October 2015

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications.

This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow.

Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues.

The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump.

Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.
Aerosol-Jet Printing for Functionalization of Prototyping Materials for Electronic Applications
Authors: Hörber Johannes , Goth Christian , Franke Jörg
Published: October 2015

To meet the growing demand for adapted 3D electronic devices, e. g. for customized electronic components as well as for Molded Interconnect Devices in small batches, 3D aerosol-jet printing combined with widely-used rapid prototyping methods like stereolithography and powder bed based printing is investigated. Compared to other printing methods for fine pitch structures, the innovative contact- and maskless aerosol-jetting is advantageous for structuring of spatial substrates. This is due to the large viscosity range of processible inks, a flexible stand-off between substrate and nozzle as well as the focal length of the aerosol beam. Focus of the printing tests on stereolithography materials presented in the paper is the suitability of the nanoparticle silver inks (solvent: water and ethylene glycol, respectively) for additive manufacturing of conductor tracks concerning adhesiveness, conductivity and wettability, which can be improved by plasma treatment. Furthermore, test specimens were assembled by mounting of electronic components using isotropic conductive adhesive. Long term reliability tests of these specimens (thermal cycling at −40 °C/+125 °C; temperature humidity test 85 °C/85 % r. h.) were performed in respect of conductivity of circuit tracks and quality of the adhesive joints. Compared to stereolithography materials aerosol-jet printing on powder bed materials requires adapted processing for functionalization. Due to the rough and porous surface and the low thermal stability of the PMMA powder materials, selective sintering of silver tracks by light was examined as well as printing on PU infiltrated surfaces. Despite of reduced contour definition, good conductivity was achieved.
Cost effective 3D Glass Microfabrication for Advanced Packaging Applications
Authors: Flemming Jeb H. , Dunn Kevin , Gouker James , Schmidt Carrie , Cook Roger
Published: October 2015

Interposer technologies are gathering more importance in IC packaging as the industry continues miniaturization trends in microfabrication nodes and IC packaging to meet design and utility needs in consumer electronics. Furthermore, IC packaging is widely seen as a method to prolong Moore's law. Historically, silicon has been the material of interest for interposer materials given its prevalence in IC production, but it presents many technical and costs hurdles. In contrast, glass interposer technology presents a low cost alternative, yet attempts at producing advanced through glass vias (TGVs) arrays using traditional methods, such as laser ablation, have inherent process flaws, such as reduced interposer mechanical strength and debris sputtering among others.

In this extended abstract we present 3D Glass Solutions' efforts in using our proprietary APEX™ Glass ceramic to create various interposer technologies. This extended abstract will present on the production of large arrays of 10 micron diameter TGVs, with 20 micron center-to-center pitch, in 100 micron thick APEX™ Glass ceramic and the comparisons of wet etching of APEX™ Glass vs. laser ablation.
Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules
Authors: Torok John , Canfield Shawn , Yu Yuet-Ying , Zheng Jiantao
Published: October 2015

Recent industry trends to continue enabling increased server system performance and packaging density has driven the need to implement larger form factor hybrid land grid array (LGA) attached organic modules. In addition, given the need to package multiple modules on a single printed circuit board (PCB) assembly, PCB cross-sections and their corresponding physical properties (e.g., flatness, etc.) as well as module bottom surface metallurgy (BSM) co-planarity require a more detailed understanding of impacts to the compliant as well as the soldered connector interfaces. Lastly, the migration to lead (Pb)-free solders has further complicated the issue given both the change in material properties as well as processing temperatures.

In this paper we will discuss the mechanical stress analysis and evaluation tests assessment of a recently developed 50 mm square organic processor module, hybrid LGA attached to a multiple site PCB. The analysis presented will highlight the methodology to identify both connector soldered stress and predicted contact load variation across the module's mated interface. Key parameters discuss will include the PCB flatness, Organic substrate BSM co-planarity (both predicted and measured) and the Hybrid LGA as-soldered contact co-planarity. Corroborating predicted analytical results, we will discuss various evaluation tests performed to validate the design's integrity. Key tests include, pressure sensitive film (PSF) studies and environment stress exposures, including thermal shock, mechanical shock and vibration and seismic exposure. Post test electrical integrity and test sample construction analysis, including 3D x-ray and mechanical cross-section, will also be described.

The analysis process and testing described will provide a method to evaluate more challenging hybrid LGA applications as both module sizes and/or number applied per PCB assembly increase and Pb-free assembly is introduced in future applications.
Superior Drop Test Performance of BGA Assembly Using SAC105Ti Solder Sphere
Authors: Liu Weiping , Lee Ning-Cheng , Bagheri Simin , Snugovesky Polina , Bragg Jason , Brush Russell , Harper Blake
Published: October 2015

Board-level drop test performance was evaluated and compared for the following four different solder combinations in BGA/CSP assembly: 1) SnPb paste with SnPb balls, 2) SnPb paste with SAC105Ti balls, 3) SAC305 paste with SAC105Ti balls, and 4) SAC305 paste with SAC105 balls. Presence of Ti improved the drop test performance significantly, despite the voiding side effect caused by its oxidation tendency. It is anticipated that the voiding can be prevented with the development of a more oxidation resistant flux. The consistently poor drop test performance of 105Ti/SnPb is caused by the wide pasty range resulted from mixing SAC105 with Sn63 solder paste. The effect of Ti in this system is overshadowed by the high voiding outcome due to this wide pasty range material. In view of this, use of SAC105 BGA with SnPb solder paste is not recommended, with or without Ti addition. High reflow temperature drove fracture shift to interface at package side, presumably through building up IMC thickness beyond the threshold value. A lower reflow temperature is recommended. Electrical response is consistent with complete fracture data. But, complete fracture trend is inconsistent with that of partial fracture trend, and neither data can provide a full understanding about the failure mode. By integrating complete fracture and partial fracture into “Virtual Fracture”, the failure mechanism becomes obvious and data sets become consistent with each other.
Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology
Authors: Das Rabindra N. , Lauffer John M. , Egitto Frank D. , Poliks Mark D. , Markovich Voya R.
Published: October 2015

Rigid-flex allows designers to replace multiple substrates interconnected with connectors, wires, and ribbon cables with a single package offering improved performance, reliability, and a potential cost-effective solution. However, processing and materials selection is critical in order to achieve high quality multilayer, rigid-flex structures. To date, there is no technology available which can economically produce high density multilayer rigid-flex with rigid or flex originating from any layer in the stack. In the present study, a novel strategy allowing for multi-layer rigid flex structures is reported. Specifically, metal-to-metal z-axis electrical interconnection among the flexible and rigid elements during lamination to form a single package rigid-flex structure is described. Conductive joints are formed during lamination using an electrically conductive adhesive (ECA). As a result, structures can be fabricated with multiple flexible elements at any arbitrary layer. Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Several classes of flexible materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop high-performance rigid-flex packages. Rigid-flex packages with embedded passives and actives are also being investigated.
Heterogeneous Process Development for Electronic Device Packaging with Direct Printed Additive Manufacturing
Authors: Rodriguez R. X. , Church K. , Chen X.
Published: October 2015

Next generation electronics will not change drastically in function; batteries will last longer, devices will have more functions and devices will take unique shapes, but for the next several years, electronics will travel the path it has been traveling for a couple of decades. To meet the demands of more functions per device and unique shapes, the status quo of electronic manufacturing cannot persist. Solder, wire bonds, FR4, printed circuit boards, surface mount and packaging will fight for survival, but just as hand held phones have evolved, so will the electronics that support them. Standard electronic packaging techniques are reaching size and density limits forcing a search for alternative approaches. The idea of using Additive Manufacturing as an alternative for packaging has not been taken seriously, but there is an opportunity to demonstrate the significant advantages of true 3D electronic packages by allowing the package to be the printed circuit board and by utilizing direct print and bare die approaches to print and structure diverse electronics.
Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process
Authors: Hisada Takashi , Yamada Yasuharu , Asai Junko , Aoki Toyohiro
Published: October 2015

As data transmission rate increases, flip chip plastic ball grid array (FCPBGA) utilizing a interposer for multiple chips is gaining popularity because of high electrical performance, ease of chip design, ease of thermal management with thermal lid, etc.

The authors assessed package design configuration and key design elements for two chips application assuming 1600 signal I/Os for logic and 800 signal I/Os for memory. Then, we studied warpage behavior of the interposer, and mechanical stress of solder interconnections and low-k dielectric layer under controlled collapse chip connection (C4) pad. We set three different mount process assumptions for chip to interposer and interposer to base organic substrate. The mount process assumptions are (1) two pass reflow of chip to interposer first, then interposer to base organic substrate, (2) reversed sequence of two pass reflow which is interposer to base organic substrate first, then chip to interposer, (3) one pass reflow of chip, interposer and base organic substrate all together. We also set three different interposer material assumptions of Si, glass and organic in this study.

We analyzed warpage behavior and mechanical stress using finite element method (FEM) modeling technique with a set of combinations of coefficient of thermal expansion (CTE) and elastic modulus of the interposers. The study also includes an analysis for conventional multi-chip-module (MCM) FCPBGA as a reference. We show the analysis results of interposer warpage, first principal stress at low-k dielectric layer under C4 pad and von Mises stress at solder interconnections of chip joining and interposer joining.
Alternative technology concepts for low-cost and high-speed 2D and 3D interconnect manufacturing
Authors: Roozeboom F. , Smets M. , Kniknie B. , Hoppenbrouwers M. , Dingemans G. , Keuning W. , Kessels W.M.M. , Pohl R. , Huis in't Veld A.J.
Published: October 2015

The current industrial process of choice for Deep Reactive Ion Etching (DRIE) of 3D features, e.g. Through-Silicon Vias (TSVs), Microelectromechanical Systems (MEMS), etc., is the Bosch process, which uses alternative SF6 etch cycles and C4F8-based sidewall passivation cycles in a time-sequenced mode. An alternative, potentially faster and more accurate process is to have wafers pass under spatially-divided reaction zones, which are individually separated by so-called N2-gas bearings ‘curtains’ of heights down to 10–20 μm. In addition, the feature sidewalls can be protected by replacing the C4F8-based sidewall passivation cycles by cycles forming chemisorbed and highly uniform passivation layers of Al2O3 or SiO2 deposited by Atomic Layer Deposition (ALD), also in a spatially-divided mode. ALD is performed either in thermal mode, or plasma-assisted mode in order to achieve near room-temperature processing.

For metal filling of 3D-etched TSVs, or for deposition of 2D metal conductor lines one can use Laser-Induced Forward Transfer (LIFT) of metals. LIFT is a maskless, ‘solvent’-free deposition method, utilizing different types of pulsed lasers to deposit thin material (e.g. Cu, Au, Al, Cr) layers with μm-range resolution from a transparent carrier (ribbon) onto a close-by acceptor substrate. It is a dry, single-step, room temperature process in air, suitable for different types of interconnect fabrication, e.g. TSV filling and redistribution layers (RDL), without the use of wet chemistry.
Monitoring of Wet Etch for Wafer Thinning and Via Reveal Process
Authors: Bai Chuannan , Shalyt Eugene , Liang Guang , Bratin Peter
Published: October 2015

TSV (Through Silicon Vias) are usually formed and deposited as blind vias. As a last stage, vias are opened by thinning of the back side of the wafer. While the bulk of the silicon can be removed by both wet and dry methods, the final step of the “Via Reveal” process is predominantly performed by wet etch.

Two commonly used types of etching solutions are anisotropic alkaline etch (KOH, TMAH, etc.) and isotropic etch (HF/HNO3, etc.). Etch rate, uniformity, and product characteristics strongly depend on the composition of solution: both original compounds and reaction products.

This presentation describes different approaches for process control of both alkaline and acidic etch solutions using advanced spectroscopic models and potentiometry. Pros and cons of different approaches are discussed. Specific emphasis is placed on the monitoring of reaction products.
Analysis of stress/strain in Electroless Copper Films
Authors: Bernhard Tobias , Bamberg Simon , Brüning Frank , Brüning Ralf , Gregoriades Laurence J. , Sharma Tanu , Brown Delilah , Klaus M. , Genzel Ch.
Published: October 2015

Polymer substrates were chemically coated with copper using various electroless copper baths and the internal strain/stress, as well as the adhesion quality, in the resulting copper films were studied during and after deposition as a function of the deposit thickness and the operation parameters of the electroless bath. The appearance of internal compressive stress in the copper film correlates to the probability of buckle driven delamination failure (blistering). Based on a simple theoretical concept we derived limits of allowed compressive stress in the copper film without inducing this failure mode. Furthermore depth-resolved X-ray diffraction (XRD) measurements in up to 1 μm thick electroless films indicate an approximately linear internal stress profile from about +200 MPa tensile stress at the substrate/adsorbate interface to −100 MPa compressive stress at the surface of the deposit. This will be explained in terms of a possible composition gradient of nickel in the copper film.
Development of Laser and Photodefinable Toughened Benzocyclobutene Dielectric Materials for 3D-TSV Integration
Authors: Wang Zidong , Gallagher Michael , Wang Kevin , Iagodkine Elissei , Oliver Mark , Lachowski Joe , Prokopowicz Greg , Huenger Eric , Thibault Raymond , Bai Zhifeng , Tucker Christopher , Bishop Matthew , Kisting Scott , Mills Lynne , Louks David
Published: October 2015

3D IC integration based on TSV technology has been recognized as a key enabler for next generation of electronic devices with reduced size factor and improved performances. The adoption of 3D-TSV technology also requires the development of innovative interconnect solutions that reduces the size of signal routing and therefore imposes new demands on dielectric materials used to isolate the copper interconnects. Benzocyclobutene polymers (Dow's CYCLOTENE™ Advanced Electronic Resins) have been used to isolate copper interconnects in packaging applications for more than 20 years, due to a number of good attributes of the BCB polymer including low copper drift rate, low dielectric constant and low loss, low moisture absorption and proven reliability. However, the low fracture toughness and low elongation of BCB polymer has limited its use in stress buffer applications due to solder bump failure. Here we report the development of new laser and photodefinable toughened benzocyclobutene (BCB) dielectric materials that have following improved properties and benefits over commercial materials including: 1) Higher elongation to break at 25%, 2) Higher fracture toughness, 3) Improved lithographic performance, < 8μm minimal size feature, 4) Better stability, no change in Eo after 30 days at room temperature. The patterning and integration of these toughened benzocyclobutene materials and the processing conditions are also discussed. We believe this toughened BCB material will find wide applications as a stress buffer layer in 3-D IC.
Better, Faster and Cheaper Precision Cleaning: Advanced CO2 Cleaning Technology
Authors: Jackson David
Published: October 2015

Precision cleaning of microelectronic substrates is a requirement prior to critical fabrication steps such as wire bonding and adhesive bonding, and following processes such as laser machining and soldering. With respect to adhesive bonding, difficult-to-bond materials such as thermoplastics, metals, glasses, ceramics and composites of same present special challenges. Important surface preparation steps include surface cleaning, microscopic etching, and functionalization. This is especially true for materials which exhibit low surface energy or heterogeneous surface contamination and chemistry. Surface treatment challenges are amplified when bonding adherent surfaces with dissimilar cohesive energy densities, for example metal-to-polymer and metal-to-ceramic. Post-laser processing of organic substrates leaves carbon char and particles on or near the laser kerf and surrounding area. These residues must be removed prior to the follow-on fabrication steps such as plating, adhesive bonding, wire bonding, and precision assembly operations.

In this regard, conventional precision cleaning processes typically require multiple steps, chemistries, and equipment to accomplish the decontamination and surface modification if required. Moreover, conventional cleaning methods are sometimes non-selective for both contaminant and contaminated surface. For example, conventional vacuum plasma using Ar/O2 is typically used to remove post-laser char on organic films such as Kapton flexible circuits. Vacuum plasma is usually performed off-line, taking up to 30 minutes to complete, and is generally non-selective for the organic contamination. The entire organic substrate is etched away during the cleaning process to remove laser char. In another example, surfaces are prepared for adhesive bonding using multiple steps involving vacuum plasma, organic solvents, chemical etchants or primers.

Advanced carbon dioxide (CO2) cleaning technology uniquely and consistently achieves precision clean (and functional surfaces if needed), including 2D and 3D surface geometries, for a variety of critical cleaning applications using one process chemistry – CO2. Numerous possible hybrid combinations of CO2 are possible including centrifugal CO2 immersion, supercritical CO2 extraction, CO2 composite spray, and atmospheric CO2 plasma cleaning and treatment. Besides addressing a broad spectrum of surface treatment requirements, CO2 cleaning technology can adapt to existing or new manufacturing tools or processes to improve production flow, increase equipment utilization, and decrease floor space. Measurable benefits derived from utilizing this technology include more productive processes with reduced labor and material inputs, improved worker safety and environmental quality, and cleaner parts – faster and with a lower cost-per-clean.
Effects of minor alloying additive on the shear strength of Sn-58Bi solder joint
Authors: Mokhtari Omid , Nishikawa Hiroshi
Published: October 2015

The use of Pb has been limited in the electronic industry because of the toxicity of lead. As the result, the research and development activities in developing lead-free solders have been accelerated and some lead-free solders were introduced as alternative. Sn-Bi-based alloys are an alternative to replace Pb-based solders in the low temperature ranges. However, Sn-Bi-based solders show brittle behavior in both the bulk and the interface. Generally, the addition of impurity elements to the solders can improve the ductility of the solder joint in both the bulk and the interface by refining the solder microstructure and suppressing the intermetallics at the interface, respectively. In this study, the effect of third elements, i.e., Ni and In (1 and 0.5wt.%) on the microstructure of the Sn-58Bi solder and thickness of the interface between Sn-58Bi solder and Cu substrate were investigated. Solid state IMC compound layer growth was also examined following the thermal aging of the solder joint. Results after aging show that minor added elements were effective in suppressing the intermetallics at the interface during solid state growth. The results also show that the added In was highly effective in limiting the Bi phase coarsening. Mechanical properties of solder joints, before and after heat treatment, were also investigated by shear and micro-vickers tests.
Excimer Laser Machining of Fired LTCC for Selectively Metallized Open Channel Structures
Authors: Rathnayake-Arachchige Dilshani , Hutt David A. , Conway Paul P.
Published: October 2015

Low Temperature Co-fired Ceramic (LTCC) is an important technology in high frequency electronics applications and enables the fabrication of several ceramic layers with cavities, channel structures and micro-vias for embedded passive and active components. Typically, laser cutting combined with screen printing technology are used to form metallized cavities and micro-vias on green state LTCC. However, in this study, the excimer laser (248 nm wavelength) machining process combined with electroless copper plating was successfully employed to create selectively metallized channel structures on fired LTCC substrates. Dry film photoresist was used within the process to guide the activation of the laser machined surface with Sn/Pd catalyst prior to electroless copper deposition. The effect of different laser parameters were investigated and machined channels were characterized for their maximum depth and surface roughness. It was found that there was a significant correlation between the laser machining parameters and the channel characteristics which also affected the subsequent electroless copper plating and its electrical resistance.
Integrated Passive Devices and TSV, a disruptive technology for miniaturization
Authors: Bunel C. , Tenailleau J-R. , Voiron F. , Borel S. , Lefevre A.
Published: October 2015

The 3D Silicon technology of IPDiA is a disruptive technology for miniaturization adopted by the best players in the Medical and Industrial segments for its outstanding performance and reliability demonstrated in harsh environments. The high density capacitors with multiple metal-insulator-metal (MIM) layer stacks in 3D structures reaching 250nF/mm2 already in production for several years is at the forefront of the research program where CEA-Leti and IPDiA are jointly providing innovative platforms for customers who want to combine these capacitors with Through Silicon Vias in order to demonstrate new technological concepts. The via last approach selected by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes. In this paper, the interaction between TSV and IPD will be studied. Emphasis will be placed on the robustness of the 3D trench capacitor technology. Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) will be illustrated.