(Invited) Scaling of Copper Interconnection As Opposed to Alternative Conductors
Authors: Nogami Takeshi 
Published: May 2020

Cu/low-k interconnect is facing challenges in its extension beyond 32nm metal pitch and impacting circuit RC delay adversely. As listed in Table.1, the difficulties lie in securing (#1) Cu gap fill capability in scaled via in the dual damascene process flow due to the limited step coverage of PVD Cu seed layer, (#2) Vx-Mx breakdown voltage and TDDB reliability due to scaled spacing and misalignment in lithography, (#3) Electromigration reliability when the barrier/liner is scaled, (#4) Low line resistance due to decreased Cu volume when the barrier/liner scaling is limited, (#5) Low via resistance when the barrier/liner scaling is limited, (#6) Selectivity in the CVD deposition of cobalt capping layer which is required for electromigration reliability and (#7) Low interconnect parasitic capacitance when thickness of the plasma-induced damage of the intra-layer low-k dielectric becomes comparable to the inter-metal spacing per scaling.

Because of these difficulties in extension of dual damascene Cu interconnection scheme, various alternative metallization unit processes, materials (conductors and dielectrics) and schemes (alternative to dual damascene) have been investigated. These new processes and materials include both (a) those for extension of Cu technology such as Co_Cu hybrid metallization (i.e., Co for via and Cu for wires) and (b) those for entire replacement of Cu to other conductors. However, extension of Cu interconnects is the preference in the industry rather than entire replacement to alternative conductors and/or metallization schemes. In addition, even when fine Cu lines are replaced to alternative conductors such as Co, wide power rails need to stay with Cu for the required low line resistance.

In this talk, process candidates which have potential to resolve the difficulties listed in Table 1 and enable extension of Cu interconnection scheme are reviewed such as (i) via pre-fill processes [1] and/or direct plating of Cu on Co liner [2] for #1 and #2 in Table 1, (ii) Fully Aligned Via integration process [3] for #2, (iii) plasma damage resistant low-k dielectric materials [4] for #5 and #7, (iv) PVD-assisted ALD barrier formation [5, 6] for #3, #4 and #5, (v) through cobalt self-forming barrier process barrier/liner scaling processes without loss in their integrity [1, 7 - 9] for #3, #4 and #5, (vi) graphene capping material on top of Cu interconnects for electromigration reliability [10] for #6. Then, the talk covers (vii) the composite metallization scheme [11] which is an enabler for the post-Cu alternative conductor metallization. References

[1] T. Nogami, et.al., “Technology challenges and enablers to extend Cu metallization to beyond 7 nm node”, IEEE Proc. VLSI Symp. 2019 T2-2

[2] L. J Brogan, et. al., “Improved Copper Damascene Wires Using Direct Plate on Cobalt Process”, ECS MA2019-01 1055

[3] B. Briggs, et.al., “Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node”, IEE Proc, IEDM 2017 14.2.1

[4] S. Nguyen, et. al., “Robust Low k C-rich SiCN Interlevel Dielectric with Ultrathin Barrier for Novel RC Reduction in BEOL Cu-Low K Interconnects :, IEEE IITC. Proc. 2019

[5] K. Motoyama, et. al., “Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond”, IEEE Proc. IITC 2018 pp40-42

[6] P. S. Bhosale, et. al., “Modified ALD TaN Barrier with Ru Liner and Dynamic Cu Reflow for 36nm Pitch Interconnect Integration”, IEEE IITC Proc. 2018, pp 43-45

[7] T. Nogami, et al., “Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes”, Tech. Dig. IEDM 8.1, 2015.

[8] T. Nogami, et. al., “Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node:, IEEE Proc. VLSI Symp. 2017 T11-5

[9] T. Nogami, “Overview of interconnect technology for 7nm node and beyond - New materials and technologies to extend Cu and to enable alternative conductors”, IEEE Proc. EDTM 2019 pp38-40

[10] L. Liand H.-S. P. Wong “Integrating Graphene into Future Generations of Interconnect Wires”, IEEE Proc. IEDM 2018 5.5.3

[11] T. Nogami, et. al., “Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines”, IEEE Proc. IITC 2017

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