bluuebunny/crossref_metadata_2025 huggingface dataset:
Extreme Temporary Coatings and Adhesives for High-Thermal, Low-Pressure, and Low-Stress 3D-Processing
Authors: Pettit Jared , Moore John
Published: October 2015

Although several materials are commercially available as temporary adhesives in 3-D packaging, few candidates satisfy processes of elevated temperature and extreme vacuum. Whether these include thermoplastic or thermosetting polymers, success is met by their being processed in a manner that meets the customer’s low vacuum conditions. This paper presents data on several products and methods of modeling a customer’s process. Low-cost alternatives will be presented which may be easily integrated, provided that a customer’s process can be tuned to accept such materials. Low-cost temporary support materials allow grinding and polishing to <20um while also protecting front side devices from backside processing to include through silicon vias (TSVs) and the associated cleans and metallization steps. Temporary adhesives must sustain thermal resistance to 250C, vacuum conditions of 10-6 Torr, and shear forces of grinding processes. These properties are required for via etch, CVD processing (e.g. oxide deposition), and chemical use during cleaning. These efforts are aimed at simplifying the overall process, aligning chemistry, and many times, eliminating the need for complicated cleans. By tailoring a customer’s process to accept a lower-cost adhesive, new ways of simple and rapid cleaning or even detergent washable systems may be integrated. Using these approaches, a safer working environment, or green factory, may be achieved while reducing the use of organic solvents and eliminating waste. Several options will be presented for using low-cost adhesives in thinning and backside processing towards increasing throughput and reducing cost. Examples will include semiconductor wafer and die thinning and at least one non-semiconductor thin substrate practice.
Applicability of Existing Reliability Models: Focus on Finite Element Modeling of Various BGA Package Designs and Materials
Authors: Fallah-Adl Ali , Tasooji Amaneh , Mahajan Ravi , Raravikar Nachiket , Harries Richard , Sane Sandeep
Published: October 2015

The work presented here is one of the key elements of an integrated methodology for predicting reliability in packaging systems (IMPRPK) developed by Arizona State University (ASU) and Intel. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks: (1) Finite Element analysis (FEM) to predict loading conditions, (2) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, and (3) development of a probabilistic methodology to achieve an integrated reliability solution. The focus of this paper is on FEM (task 1), evaluating the effect of package design/form-factor and solder materials on the extent of deformation (e.g., inelastic stress/strain and strain energy density) experienced by BGA solder joints. Global and Local FEM results for two different package designs (Flip-chip and wire-bonded FLI) and two different BGA solder materials (lead-free SAC405 and lead-rich eutectic Sn37Pb) are discussed. The FEM results and the applicability of the existing reliability models (e.g., energy-based model) to the complex microelectronics packaging systems are validated through independent comparison with the accelerated thermal cycled (ATC) test data.
Bond Over Active Circuitry Design for Reliability
Authors: Hunter Stevan , Martinez Jose , Salas Cesar , Salas Marco , Schofield Jason , Sheffield Steven , Wilkins Kyle , Rasmussen Bryce , Ruud Troy , Workman Jim
Published: October 2015

This paper discusses layout design rules for successful Cu wire bond-over-active-circuitry (BOAC) in 0.18 micron and other IC technologies having Al metallization interconnects (two-level metal and up) in SiO2 dielectric, with W vias. The resulting bond pad structures effectively address BOAC pad reliability concerns, permitting Au or Cu wire bonding on relatively thin top metal. Cu wire bond is attractive on BOAC designs for lower cost than Au wire, while improving the thermal capability of the product. But Cu wire bond has presented even more challenges than Au wire bond due to higher stress to the pads during bonding, typically leading to increases in underlying films deformation and cracking. The new BOAC pad layout rules are based on the physical thin films principles, substantiated and refined through analysis of a large volume of experimental and product qualification data in various IC technologies. Interconnect layout beneath pads which follows the BOAC design rules creates more robust bond pad structures, preventing Al films deformation while strengthening the dielectric against cracking, and permitting free-form Si device design beneath. Substantial freedom in interconnect design is permitted in all metal layers beneath the pad, but the rules for top via and top-metal-minus-one layers are more restrictive than the rest. The BOAC design rules do not require any changes in wafer processing, they do not prevent the adding of redistribution or other layers for solder bumping or the like, but they do enable smaller die size and less expensive wire bond without jeopardizing bonding reliability.
APPLICATIONS OF SOLDER PREFORMS TO IMPROVE RELIABILITY
Authors: Gowans Carol , Homer Seth , Lasky Ronald
Published: October 2015

As early as the 1990s people were predicting the end of through-hole components, but they are alive and well with the numbers of dual in-line packages (DIPs) and connectors still measured in the 10s of billions per year. Many of these components are assembled by wave soldering, however in mixed technology (SMT and through-hole on the same board) where the through-hole count is low, it is often advantageous to consider selective soldering or the pin-in-paste process (PIP). PIP is a process in which solder paste is printed over or near the PWB through-holes. The through-hole components are then placed and the solder joint is formed during the reflow process. PIP has the advantage of eliminating the wave soldering process step. In many cases it is difficult to print enough solder paste to make an acceptable through-hole solder joint. Solder preforms were developed to meet this need.

These solder preforms are typically shaped in the form of 0402, 0603, or 0805 passive components. The preforms are placed on the appropriate printed solder paste deposit by a component placement machine. Preforms come in tape & reel packaging.

Today solder preforms are also used in other “solder starved” applications such as radio frequency (RF) shields, connectors, and under QFN thermal pads. In all cases, the extra solder delivered by the preform is vital to the reliability of the assembled product.

In this paper, process, design, and assembly methods for solder fortification using preforms will be discussed. Four successful solder fortification examples will be presented along with the associated defect reductions.
Making Sense of Laminate Dielectric Properties
Authors: Pangier Rich , Gay Michael J.
Published: October 2015

System operating speeds continue to increase as a function of the consumer demand for such technologies as faster internet connectivity, video on demand, and mobile communications technology. As a result, new high performance PCB substrates have emerged to address signal integrity issues at higher operating frequencies. These are commonly called low Dk and/or low loss (Df) materials. The published “typical” values found on a product data sheet provide limited information, usually a single construction and resin content, and are derived from a wide range of test methods and test sample configurations. A printed circuit board designer or front end application engineer must be aware that making a design decision based on the limited information found on a product data sheet can lead to errors which can delay a product launch or increase the assembled PCB cost. The purpose of this paper is to highlight critical selection factors that go beyond a typical product data sheet and explain how these factors must be considered when selecting materials for high speed applications.
High Melting Temperature Lead Free Solder for Die Attach Application
Authors: Li Jianxing , Lau Daniel , Tu Pingliang , Delano Andrew , Knight Brian
Published: October 2015

Two lead free solders were developed for die attach application. The bismuth based solder has a melt temperature of 271C and thermal conductivity of 18W/mK. The zinc based solder has a melt temperature of 337C and thermal conductivity of 85W/mK. Both solders have acceptable wetting on bare copper and nickel plated copper substrate, could be processed using modified high lead solder process condition and survived 260C board level reflow simulation. This paper discusses the solder material properties, and presents the die attach process and reliability test results in a manufacturing environment.
Embedded Actives and Its Industry Effects
Authors: Fillion Ray
Published: October 2015

Over the 60 plus year history of microelectronics packaging, electronic devices have been mounted onto an interconnect structure to form a microelectronics circuit. The devices could be bare chips, CSPs or packaged components such as SMT or thru-hole carriers. The interconnect structures could be circuit boards, ceramic substrates or flex circuits. This methodology has enabled a clear divide between the fabrication, assembly and test of the semiconductor device, the fabrication and test of the interconnect structure and the assembly and test of the component/substrate assembly.

Over the past decade a new packaging methodology, embedded actives (chips), has been developed that changes all of these industry norms. In an embedded actives packaging approach, one or more bare or chip scale semiconductor devices are embedded within the interconnect structure. Although these approaches have significant electrical performance, size and cost benefits, the normal barriers between chip packaging, substrate fabrication and component assembly are removed. The interconnect structure is not completed prior to component embedding and the embedded component cannot be tested at packaged part level without the interconnect structure. This complicates electrical testing and makes it virtually impossible to differentiate between a defective component, a defective interconnect or a defective component to substrate contact.

This paper will look at the history of embedded active developments and go into the various processes and structures being used. It will cover their electrical, reliability and size advantages and will address the revolutionary changes that the microelectronics industry must make to effectively utilize these technologies.
Technologies and Trends to Improve Power Electronic Packaging
Authors: Schneider-Ramelow M. , Hutter M. , Oppermann H. , Göhre J.-M. , Schmitz S. , Hoene E. , Lang K.-D.
Published: October 2015

In the realm of power modules a strong trend toward high temperature and high reliability applications can be observed, which entails new technological challenges, especially for the assembly and packaging of power semiconductors. Because of the well known failure mechanisms of established lead-free standard soldering and heavy aluminum wire bonding technologies, such as fatigue and creep of die attach material and wire bonds at thermal cycling, academic and industrial research focuses on more reliable interconnection technologies.

A priority is the research of alternative top and bottom side chip interconnection materials or technologies to improve the temperature cycling capability of power chips that are typically assembled on ceramic substrates. The scientific focus is on Ag sintering as die attach and/or heavy ribbon bonding, for example with Al or bi-metal (Al-Cu). Another focus is the material behavior of ribbon bonds in combination with bonding machine improvements (higher bonding parameters, cutting tool). But there are other very promising technologies like transient liquid phase bonding, for example with Cu-Sn or Ag-Sn systems or Cu heavy wire bonding (up to 400 μm wire diameter) or Cu/Al-Bi metal ribbon bonding.

Challenges posed by these technologies have to be discussed focusing on materials and process selection and reliability issues. Process temperatures and temperature profiles must be optimized, wire bonding machines and the chip surface structures as well as finish metallizations need to be adapted.

This paper will give an overview of alternative power chip interconnection technologies and discuss the challenges related to processing and reliability.
A STUDY OF SURFACE FINISHES FOR IC SUBSTRATES AND WIRE BOND APPLICATIONS
Authors: Ganjei John , Long Ernest , Toscano Lenora
Published: October 2015

The continuing drive for ever increasing performance enhancement in the electronics industry, in combination with the recent, very significant increase in precious metal costs have left fabricators and OEMs questioning what the best, most cost effective, surface finish is for high reliability applications. Currently, the IC substrate market relies heavily on electrolytic nickel and gold as a solderable and superior wire bondable surface. The use of this finish has allowed manufacturers to avoid the reliability concerns However, this choice also results in significant design restraints being imposed. Many in the industry are now investigating the use of electroless nickel/electroless palladium/immersion gold (ENEPIG) to achieve both high reliability and performance, without the negative design restraints imparted by the use of electrolytic processes. However, over the last year alone, the industry has watched the price of gold increase by 50% and that of palladium double [1]. With this in mind, and considering the historic precedent set in the mid 1990’s when ENEPIG was also evaluated as a surface finish for printed circuit boards, when coincidentally, the cost of palladium also reached an all time high, it should be remembered that the electronics industry quickly moved to evaluate alternate, more cost sustainable, surface finishes. This paper details the use of lower cost, alternate surface finishes for IC substrate applications, with particular experimental focus on gold wire bonding capabilities and BGA solderability of the finishes described. The paper also discusses related process cycle advantages and the significantly reduced operating costs associated with these new finishes.
Materials Interaction in Cofired Platinum /Alumina High Density Feedthrough for Implantable Neurostimulator Applications
Authors: Karbasi Ali , Jones W. Kinzy
Published: October 2015

Neurostimulator applications will require much higher I/O feedthrough density for hermetic implantable enclosures, often greater than 100 I/O. This work evaluates the development of high-density platinum via structure cofired in alumina. The platinum was observed to melt when cofired at 1550°C, almost 200°C below its melting point, independent of the particle size (nano to micron size particles) or particle morphology. An analysis of the effect of particle size (nano to micron size Pt), firing atmosphere (air, hydrogen, inert), firing temperatures, intermetallic reactions and additives to control thermal expansion and adhesion strength was performed to evaluate and minimize this exothermic reaction. The interaction of platinum and alumina has been evaluated using X-ray diffraction and SEM.
Introducing DuPont™ GreenTape™ 9K5 Low Dielectric Constant, Low Temperature Co-Fired Ceramic (LTCC) Tape System
Authors: Nair Deepukumar M. , Parisi James , Nair K.M. , McCombs Mark , Smith Michael , Hughes Elizabeth , Souders Ken , Orzel Anthony , Thrasher Bradley , Beers Stephen C. , Malerbi J.C. , Gordon Scott
Published: October 2015

Low Temperature Co-fired Ceramic (LTCC) material systems have been successfully used in microwave and millimeter wave systems for several years. LTCC has very low dielectric loss, high reliability due to inherent hermeticity; high interconnect density, multilayer processing capability leading to true 3D packaging, and better cost-performance balance. While the medium range dielectric constants (7.00 – 8.00) offered by current tape systems have advantages, it is generally difficult to realize high speed systems and efficient antennas on LTCC, especially at millimeter wave frequencies. The difficulty arises from the reduced signal propagation velocity in high-speed applications, and lower radiation efficiency for antennas, both due to higher dielectric constant. To enable and extend applications of LTCC technology to these subsystems, DuPont has developed a new low dielectric constant LTCC system – DuPont™ GreenTape™ 9K5 - which has a dielectric constant of 5.80 (at 10 GHz) that is compatible with the commercial DuPont™ GreenTape™ 9K7 LTCC System. This is achieved without compromising excellent microwave loss properties of the 9KX GreenTape™ platform. These materials systems enable high-speed, high reliability applications while also realizing efficient antennas on LTCC. This paper presents initial characterization of the new DuPont™ GreenTape™ 9K5 LTCC system consisting of low K dielectric tape, gold and silver conductors to evaluate the effects of chemistry, processing conditions, processing latitude, microstructure, and microwave performance. Test coupons with various transmission and resonating structures are designed, fabricated, and tested for the evaluation of transmission losses and dielectric properties. Stability of the material system over multiple re-fire steps is also examined
Comparison of Gold and Copper Wire Bonding on Aluminum and Nickel-Palladium-Gold Bond Pads for Automotive Application
Authors: Tran Tu Anh , Mathew Varughese , Downey Harold
Published: October 2015

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on evaluating Au and Cu wire bonding on low-K-copper wafers having two types of bonding surfaces, the conventional aluminum pad and aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold. Ni thickness ranging from 1μm to 3μm was evaluated. Defects on as-plated Ni/Pd/Au bond pads such as color difference and surface roughness were determined to be due to nodule growth and plating non-uniformity. Wire bonded strip-level thermal aging was conducted to compare the high-temperature performance of the four interconnect types. Packages underwent extensive reliability stress conditions. Cross-sectioning through the ball bonds was also conducted to examine the welding region between the ball bond and bond pad. Defects in plating and wire bonding processes causing package reliability failures were identified. Recommendations for plating and wire bonding processes were derived to ensure high quality and reliable interconnect exceeding AEC grade 0 requirements.
Packaging Technology of Multi Deflection Arrays for Multi-Shaped Beam Lithography
Authors: Burkhardt T. , Mohaupt M. , Hornaff M. , Zaage B. , Beckert E. , Döring H.-J. , Slodowski M. , Reimer K. , Witt M. , Eberhardt R. , Tünnermann A.
Published: October 2015

Multi-Shaped electron beam lithography is considered a promising approach for high throughput mask and direct writing. Providing multiple apertures and individually controlled electrodes it allows for massive parallelization of exposure shots, thus significantly decreasing write time. A silicon-based micro-structured MEMS multi-beam deflection array (MDA) featuring 8×8 apertures is presented. The hybrid integration of MDA devices in ceramic system carriers utilizing a laser-based Solderjet Bumping process is demonstrated. This flux-free soldering process provides adhesive-free, long term stable and vacuum compatible joints and is used for both mechanical fixation and electrical connection. Electron beam deflection in two perpendicular directions requires the highly accurate placement of two crossed MDA devices, which is carried out by three degrees of freedom alignment procedures and solder joining. Electrical signal routing within the electron optical column using flexible printed circuit boards and flux-free soldering is also reported. The precision adjustment of two carriers is accomplished by fiducial mark detection using image processing. Results on alignment accuracy in the sub-micron range, mechanical and electrical testing of such assemblies are reported.
Vacuum Packaging for High-Performance Low Cost MEMS Gyro Used in 6 Degree of Freedom Inertial Navigation System (DOF INS)
Authors: DeRoo D. , Shcheglov K. , Inbar M. , Smukowski D. , Zappella P. , Barnes P.
Published: October 2015

Sensors in Motion Inc. is developing a navigation grade 6 DOF MEMS INS using its proprietary and patented technologies. The military is investing in INS and IMU technology which can answer its needs as well as provide the baseline for hundreds of other DOD and commercial applications which need a C-swap sensitive utility. SIM’s technology for MEMS gyros was conceived to address past problems associated with MEMS gyroscopes while leveraging the C-swap benefits of high volume, high yield batch fabrication, automated packaging, self-calibration, and thermal compensation. A key requirement for the MEMS Gyroscope is controlled vacuum-levels to obtain high Q devices. Gyro die are packaged using a multilayer package and getter system, which provides and maintains sealed vacuum cavities. Die are assembled into the LCC package using conventional assembly techniques and the package cavity is sealed using an SST 3150 high-vacuum sealing system. The SST system is used to activate a thin-film getter layer on the package lid before reflow of the solder seal. Resulting pressure levels have been determined by characterizing packaged but unlidded sensor die in a vacuum chamber. The package material, process flow and test results are summarized and reviewed. Tooling, process parameters, and test techniques are explained.
Through Silicon Vias and Holes Metallization using CoWP and Cu Nanoparticles as Barrier and Seed Layers
Authors: Dow Wei-Ping , Shen Shao-Ping , Lu Chun-Wei , Chang Yiu-Hsiang , Kubo Motonobu , Kamitamari Tohru , Cheng Eric , Lin Jing-Yuan , Hsu Fu-Chiang
Published: October 2015

Three new technologies for Cu coating and deposition in through silicon vias (TSVs) and through silicon holes (TSHs) were developed. One is to synthesize Cu nanoparticles (CuNPs) with a particle size of 3–5 nm and then coat the CuNPs onto the sidewall of TSVs by a wet process to act as catalysts for a seed layer formation through copper electroless deposition. The wet process for Cu seed layer formation can make sure of conformal coating and reduce the process cost of TSV. Second, we develop a new Cu electroplating formula that can make selective Cu fill (SCF) in TSVs, which leads to no increase in Cu thickness on the top surface after electroplating. The plating technique, SCF, can greatly reduce the loading of Cu CMP and the process cost of TSV. Finally, we develop a novel Cu plating technique for direct TSH filling, meaning that the conducting template assembled on one side of the TSH in advance is unnecessary. Cu can fill the TSH directly in a middle-up mode. This filling mode can make sure of no void after electroplating. In addition, the barrier layer employed herein was formed through CoWP electroless plating to replace the traditional dry process for cost cut.
Advanced Thermal Study of Very High Power TSV Interposer and Interconnects for 28nm Technology FPGA
Authors: Banijamali Bahareh , Ramalingam Suresh , Chaware Raghunandan
Published: October 2015

TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps.

This paper presents the thermal study of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mmx42.5mm substrate through 180um pitch C4 bumps. 3D thermal modeling and simulation for the packaged device with TSV interposer have been performed. Several DOEs have been constructed to optimize thermal interface material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. Furthermore, thermal behavior of 28nm technology monolithic FPGA was compared to the 3D TSV interposer FPGA package. Optimized passive thermal solution was recommended for this high power FPGA in order to cool down up to 100 Watt power.
Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Molded Underfill Technology
Authors: Tamil Jonathan , Ore Siew Hoon , Gan Kian Yeow , Bo Yang Yong , Ng Geraldine , Wah Park Teck , Suthiwongsunthorn Nathapong , Chungpaiboonpatana Surasit
Published: October 2015

Increasing challenges are faced to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial Moldable Underfill (MUF) is used and in particular, during panel level molding. One key challenge faced is severe void entrapment under the die. Experiments involving a large DOE matrix, which require significant time and process resources, are typically used to solve this issue. 3D flow simulation can be used to optimize the process to reduce defects without doing actual runs. Mold flow simulation can effectively reduce the design-to-implementation cycle time, identifying key problems before actual fabrication. In this paper, 3D mold flow simulation using Moldex3DTM V10 is applied to transfer molding to optimize design and process parameters.

This paper proposes and verifies a systematic method that can save computational resources by using 2 steps analysis: simplified panel simulation and single package simulation. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain balanced melt front. The second step is to study on the package level the effect of various package-scale parameters. This analysis provides a prediction of the void location and an insight on the appropriate parameters to minimize void problem. The actual voids location and size from the experiment was captured by SAT machine and short shots were obtained. For final validation, a complete panel-level flow model is built, where the process and design parameters adopted in the actual molding were implemented. The mold filling simulation showed good correlation with the experimental short shots and actual void location. With optimized parameters from the simulation used as guidelines, experimental tests were conducted and the study showed that the simulation is a useful tool to optimize the molding process.
Solder Strength Characterization Using Hot Bump Pull Testing
Authors: O’Connell Kevin , Sinha Arv
Published: October 2015

Hot and cold solder ball pull testing has emerged as an attractive alternative to the traditional ball shear method for characterizing the attachment strength of solder interconnection. This paper describes the effects of aging with relative humidity and temperature on solder strength using hot bump pull test method. The results show high dependence of solder interface strength due to aging.
Mold Compound Adhesion Reliability with SiN and SiON Passivation
Authors: Mathew Varughese , Chopin Sheila , Uehling Trent , Ibrahim Ruzaini
Published: October 2015

Delamination of mold compounds under thermal stress conditions such as Air-to-Air Temperature Cycling (AATC) (−55°C −125° C) was studied for two passivation surfaces; SiN and SiON using C-Mode Scanning Acoustic Microscope (CSAM) and electrical testing for different intervals up to 2000 cycles. Both passivation surfaces were treated with oxygen-argon plasma prior to the molding process. It is found that SiN surface performed better than SiON electrically and without showing any delamination for the mold compound studied. Both passivation surfaces were analyzed for various surface groups by TOF-SIMS analysis immediately before and after the pre-mold plasma treatment process. Different surface groups such as CH, NH etc. were identified, but the major difference was found in the OH intensity. Fraction of OH is significantly increased after plasma treatment for SiN surface while it is decreased for SiON surface. It is inferred that OH group can play a role in enhancing the mold compoundpassivation adhesion and hence provide better delamiantion resistance.
Electrical Performance of Advanced Surface Laminar Circuit in High-end FCBGA Applications
Authors: Shiroshita Makoto , Nakamura Satoshi , Terada Kenji , Yamanaka Kimihiro
Published: October 2015

Advanced Surface Laminar Circuit (Adv-SLC) is a build-up substrate technology designed to satisfy the requirement of the most advanced semiconductor chips. Adv-SLC is featuring a low Coefficient of Thermal Expansion (CTE) of 10 ppm/degC that reduces the strain in the solder joints and Cu/low-k stacked structure of semiconductor chips during the reflow process, ensures the solder joint reliability, and protects internal delamination of the Cu/low-k stacked structure. This paper describes the power integrity and signal integrity of Adv-SLC and the capability to reduce total layer count with considering X-talk, to reduce package size, and to improve Power Integrity by using Adv-SLC.
High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC
Authors: IIDA Atsuko , ONOZUKA Yutaka , YAMADA Hiroshi , NAGANO Toshihiko , ITAYA Kazuhiko
Published: October 2015

This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.
Design and Robustness of Quilt Packaging Superconnect
Authors: Khan M. Ashraf , Kulick Jason M. , Kriman Alfred M. , Bernstein Gary H.
Published: October 2015

Quilt Packaging (QP) is a novel high-speed superconnect (i.e. direct interchip interconnect), developed to improve electrical performance — signal delay, power loss, etc. Ultrahigh bandwidth has already been demonstrated for QP, but its unique structure requires thermal reliability issues to be studied. To this end, simulation models were developed to study the robustness of QP. QP structures were fabricated, and thermal cycling tests were performed focusing on the reliability for various shapes of nodules, the basic physical interconnect unit of QP. Simulations were performed to determine stress over a range of temperatures and estimate low cycle fatigue lifetimes. Simulations considered two types of solder and several adhesives. Thermal cycling experiments indicate that QP provides a robust structure, in agreement with the simulation results.
Planarization of Deep Structures Using Self-Leveling Materials
Authors: Bai Dongshun , Fowler Michelle , Planje Curtis , Shao Xie
Published: October 2015

To achieve device integration that will allow the manufacture of smaller, more functional, and more efficient microelectronics, the industry increasingly requires materials to fill and planarize devices with deep structures. Brewer Science has developed several new self-leveling materials to address these planarization needs. These newly developed materials are designed to be either temporary materials that can be removed after their use in processing steps or permanent materials that can stay in a device for its lifetime. These new materials can be applied easily by means of a spin-coating process. They are unique because they can fill and planarize high-aspect-ratio trenches and vias hundreds of microns deep. Some of the materials are photosensitive and can be patterned using photolithography. All of the photosensitive materials in this paper can be developed with industry-accepted solvents and some with an aqueous TMAH solution. Because of their good thermal stability, high transparency, and excellent planarization properties, these materials have potential applications for microelectromechanical systems (MEMS), 3-D integrated circuits, light-emitting diodes (LEDs), semiconductors, flat-panel displays, and related microelectronic and optoelectronic devices. This paper will discuss the properties of these new materials and will present the filling and leveling results obtained in several applications.
CO2 Technology Transforms Manufacturing
Authors: Jackson David
Published: October 2015

CO2 technology provides material and process engineers with a robust surface treatment platform and window for a variety of complex substrates and microscopic geometries. Substrate and surface contamination such as particulate matter, outgassing residues, ionic residues, and heat can be addressed uniquely with this technology. Available treatment processes include composite jet spray, centrifugal immersion, supercritical fluid extraction, critical drying, and both vacuum and atmospheric plasma. CO2 technology eliminates or significantly reduces both lean and green waste generation at the production operation level (source) by modifying manufacturing processes such as precision cleaning and machining. Because CO2 is non-flammable, non-corrosive and dry, CO2 processes can integrate directly into manufacturing processes and tools to provide in-situ cleaning, thermal control or lubrication. CO2 technology can be implemented in a variety of process configurations to meet the constraints of lean production layouts and product flow requirements, including direct integration into existing production lines and equipment where the surface contamination is being generated. CO2 is a very unique manufacturing agent that affords multiple cost reduction and performance improvement opportunities in microelectronics device manufacturing operations.
HIGH RELIABILITY HIGH MELTING LEAD-FREE MIXED BIAGX SOLDER PASTE SYSTEM
Authors: Zhang HongWen , Lee Ning-Cheng
Published: October 2015

In the current work, a mixed solder powder BiAgX solder paste system with the melting temperature above 260°C and the comparable or even better reliability to the high lead solders has been studied. The mixed solder powder paste system is composed of a high melting first alloy solder powder as majority and the additive solder powder as minority. The additive solder is designed to react aggressively with various surface finish materials before or together with the melting of the majority solder to form a controllable IMC layer. The IMC layer of the mixed powder system is controllable by the species and the quantity of the additive solder and it is observed to be insensitive to thermal aging and thermal cycling in current tests while the high lead ones do show a considerable increase in IMC layer thickness. Microstructure investigation shows the fishbone shape IMC layer interlocks the bonding interface between solder and components. Both micron-sized and nano-sized Ag-rich precipitations in the joints have been observed to be well distributed in the joint. The exposed Ag-rich particles and the surrounding stepwise pattern in Bi matrix on the fracture surface indicate that these Ag-rich particles constrain the dislocation movement in Bi matrix thus enhance the strength and the ductility of the joint. Under thermal aging and thermal cycling, both the micron-sized and nano-sized Ag-rich precipitations exhibit only discernible and localized coarsening. The stable interfacial IMC together with the existence of the well dispersed Ag-rich particles are attributed to the promising reliability in BiAgX solder paste system.
Parylene as Thin Flexible 3-D Packaging Enabler for Biomedical Implants
Authors: Maeng Jimin , Ha Dohyuk , Chappell William J. , Irazoqui Pedro P.
Published: October 2015

In this paper, the novel use of Parylene for implantable biomedical microsystems packaging is presented. Parylene is an excellent candidate material to be used for implantable and clinically usable miniature devices due to its biocompatibility, flexibility, near-hermeticity, and high-density integration capability in a small form factor. Here, we propose a novel all-Parylene packaging technique where Parylene is used as a package substrate, an isolation layer, a capacitor insulator, and a sealing layer. Fully-integrated embedded passive devices, transmission lines, and surface mount components on a thin-film multilayer Parylene substrate are described. Metal-insulator-metal capacitors are implemented on Parylene and their DC and RF properties are characterized. Further, high-density 3-D trench capacitors are developed on Parylene for the first time. By integrating embedded capacitors and antenna with surface mount diodes, a rectifier module is implemented. Wireless powering onto the Parylene package is demonstrated as a proof-of-concept for the implant package to be powered by external environment. The authors believe that the all-Parylene packaging method described here can be widely applied to other miniature implant applications.
Miniaturization of Electronic Substrates for Medical Device Applications
Authors: Egitto Frank D. , Das Rabindra N. , Thomas Glen E. , Bagen Susan
Published: October 2015

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. These enablers include materials selection, embedded passives and active devices, System-in-Package (SiP) designs, and flex circuits. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch.
Solder Joint Ductility
Authors: Darveaux Robert , Johnson Michael , Reichman Corey
Published: October 2015

Solder joint arrays were tested under tensile loading to determine the strain-to-failure (ductility) under a wide range of conditions. The trends in ductility with alloy, joint size, pad metallization, and test conditions were quantified and discussed. 63Sn37Pb solder joints showed a significant increase in ductility as applied stress is reduced below 40MPa. Lead free alloy ductility was much less sensitive to applied stress level. Hence, at low stress levels, eutectic SnPb has greater ductility than the lead free alloys. Larger joints showed greater ductility in a constant crosshead rate test compared to smaller joints. This is believed to be a function of the load train stiffness. Such a discrepancy was not observed in the constant load test method.
3D Electromagnetic Modeling of Through Silicon Vias and Interposers in Electronic Packaging
Authors: Kostka Darryl , Scogna Antonio Ciccomancini
Published: October 2015

3D ICs promise “more than Moore” integration by packing a lot of functionality into small form factors. Interposers along with TSVs play an important role in 3D integration from an electrical, thermal and mechanical point of view. The goal of this paper is to electrically model TSVs and 3D interposers by means of three 3D full wave electromagnetic simulations. A comparative analysis of various configurations of signal delivery networks in 3D interposers for high speed signal transmission is presented.
Thin-film High Voltage Capacitors for Hybrid Electric Vehicle Inverter Applications
Authors: Fairchild M. Ray , Berlin Carl W. , Sarma D.H.R. , Taylor Ralph S. , Lee Han S. , Staller Steven E.
Published: October 2015

The propulsion system in hybrid electric vehicles (HEVs) requires an alternating current (AC) electric motor in combination with an internal combustion engine. When the HEV is being propelled by the AC motor, the power for the motor is provided by batteries whose direct current (DC) voltage is chopped into an AC waveform via an electronic device called a power inverter. Capacitors known as DC bulk capacitors are placed between the battery and the inverter to “decouple” the AC switching inverter from the power source. Power electronics inverters use several large high voltage discrete DC bulk capacitors, which negatively influence the inverter's size, weight and are a high cost item in the assembly.

The use of a high dielectric constant (Dk) ferroelectric material enables smaller, higher temperature capable, lower-cost power capacitors. Ceramic ferroelectrics, such as (Pb,La)(Zr,Ti)O3 [PLZT], offer the highest dielectric constants. Argonne National Laboratory is developing a novel film-on-foil technology for high-power capacitors utilizing PLZT. These capacitors, with an increasing dielectric constant with temperature, low equivalent series resistance and a benign failure mode, are well suited for power applications. The PLZT is deposited onto a metal foil via a chemical deposition process and the top electrode metal (Pt or Al) is then deposited by electron beam evaporation onto the top surface of the dielectric thus creating the capacitor.

This project involved the fabrication and electrical evaluation of film-on-foil capacitors for HEV inverter applications. Capacitors utilizing both nickel and platinum-on-silicon as the base substrate, and PLZT as the dielectric material were fabricated. These capacitors were tested for dielectric integrity, capacitance, voltage breakdown, and benign failure mode. Results from these mechanical and electrical evaluation tests will be presented. Key processing challenges and implementation methods will also be described.
Pushing the 3rd Dimension – Floppy Wafers, Die and Packages? Stress Induced Chip Package Interactions on Thin Mobile Devices
Authors: Nakamoto Mark , Zhao Wei , Radojcic Riko
Published: October 2015

Ever thinner form factors for smart phones, tablets and other mobile devices are driving an aggressive scaling of the semiconductor devices/packages that enable them. A survey of the challenges of this trend points to mechanical stress as the major challenge apart from handling damage. Stress driven Chip Package Interactions impact the manufacturing flow, performance and the reliability of the finished product. We examine a number of the factors and risks driven by mechanical stress and discuss some ideas on how to manage and monitor these issues.
Highly Flexible Die Attach Adhesives for MEMS packages
Authors: Königer Tobias
Published: October 2015

Die attach materials for most MEMS packages must be highly flexible as temperature changes during the assembly process and application may lead to thermo-mechanical stress as a consequence of dissimilar coefficients of thermal expansion of substrate, chip and adhesive. Thermo-mechanical stress results in a distortion of the signal characteristics of the extremely stress-sensitive MEMS device. Within the scope of this paper, highly flexible heat-curing adhesives with a Young's modulus down to 5 MPa (0.725 ksi) at room temperature were developed. DMTA measurements show that temperature storage at +120 °C (+248 °F) does not cause the adhesive to embrittle, which would have a negative effect on the MEMS package's reliability. After storage at +120 °C (+248 °F) for up to 1000 h, no increase in Young's modulus can be observed. The adhesives cure at extremely low temperatures down to +100 °C (+212 °F), which reduces stress development during the assembly process. In addition, the adhesives have very process-friendly properties. Processing times of more than one week can be achieved. The option of dual curing enables preliminary light fixation of the chip within just seconds.
Development of Synergistic Opto-Electronic Sensing Platform based on Zinc Oxide Semiconducting Nanostructures
Authors: Gupta Anurag , Kim Bruce C. , Spryn Mitchell , Edwards Eugene , Brantley Christina , Ruffin Paul
Published: October 2015

Potential of zinc oxide nanowires for developing a sensitive opto-electronic platform was demonstrated. Zinc oxide nanowires synthesized on insulating sapphire substrates were functionalized with an optically active receptor, 1-pyrenebutyric acid. Appropriate characterization studies including XPS and FT-IR ATR are reported. I-V curves of pristine and receptor-modified nanowires were utilized to highlight the potential of zinc oxide nano-heterostructures for developing a sensitive opto-electronic platform for p-nitrophenol sensing. Packaging issues for achieving an efficient and cost-effective sensor platform have also been outlined.