(Invited) Non Volatile Resistive and Magnetic Memories: Materials, Integration Challenges and Opportunities
Authors: Cyrille Marie-Claire , Nowak Etienne , Tillie Luc , Molas Gabriel , Navarro Gabriele , Sousa Véronique , Castellani Niccolo , Vianello Elisa , Lamard Nathalie , Guerfi Youssouf , Langer Juergen , Ocker Berthold , Boulle Olivier , Gaudin Gilles , Garello Kevin , Gambardella Pietro , Perniola Luca 
Published: February 2020

Demand for on chip memories has increased due to the need for more data storage and the increasing gap between processor and off chip memory speed. One of the solutions proposed to improve power consumption and to fill the memory gap is to introduce non volatility at different levels of the memory hierarchy (storage class, main memory, cache memory). Several disruptive technologies have been proposed in the last decades for non-volatile memory (NVM) applications. The more investigated ones are Phase-Change Memories (PCM), Conducting-Bridge RAM (CBRAM), Oxide-based Resistive RAM (OxRAM), and Perpendicular Spin Transfer Torque Magnetic Memories (pSTTMRAM). Intensive studies and demonstrations have being carried out in order to develop and improve those emerging memory concepts. Some memory stacks have shown promising results in term of high speed, good endurance or retention but not necessarily all of the above.

A survey of published results [1] as well as internal studies carried out at LETI [2, 3] using a memory test vehicle developed to evaluate various memory concepts using the same 130nm CMOS logic have led us to infirm that the universal memory ie an optimized memory stack that fits all requests of memory hierarchy does not exist.

However, because requirements for cache memories (ie high speed, endurance, but low data retention) are completely different from requirements for embedded memories (ie high temperature or long data retention), different technology or optimized memory stacks can be targeted to fulfill specific applications.

It will be shown that despite very different physical concepts, universal signatures can be extracted unifying the characteristics of different technologies and thus drawing conclusions on their behaviors and tradeoffs (such as programming window vs endurance, programming window vs data retention, and endurance vs data retention). This is illustrated in Fig 1 where the relation between the programming window and the endurance capabilities of the different technologies is presented. It is shown that high programming window is typically associated to poor endurance capabilities, (as shown by some classes of chalco-based CBRAM or non-polar OxRAM). For these technologies the overall filament is believed to participate to the creation and the dissolution events. On the contrary, displacing very few atoms/ions, or spins, during the write or erase event allows to guarantee a long-lasting endurance (examples are certain class of polar OxRAM and STT MRAMs). Data also show that a universal tradeoff exists between the endurance and data retention itself. The better the performances in endurance, the lower the data retention capabilities at high temperature. Write latency speed will be discussed and ultra fast (<1ns) writing MRAM technology based on a recently discovered effect Spin Orbit torque (SOT MRAM) will be discussed.

The characteristics and performances of the different emerging will be presented (materials, integration, speed, endurance, consumption and scalability) in regards of the needed specifications required for potential applications.

[1] ] H.-S. P. Wong, C. Ahn, J. Cao, et al., “Stanford Memory Trends,” https://nano.stanford.edu/stanford-memory-trends, accessed Nov 11, 2015

[2] C. Nail; G. Molas; P. Blaise et al “ Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations”: IEDM 2016 Pages: 4.5.1 - 4.5.4, DOI: 10.1109/IEDM.2016.7838346

[3] V. Sousa, G. Navarro, N. Castellani et al., “Operation Fundamentals in 12Mb Phase Change Memory Based on Innovative Ge-rich GST Materials Featuring High Reliability Performance”, VLSI Tech. Symp., pp.98-99, 2015

Figure 1