bluuebunny/crossref_metadata_2025 huggingface dataset:
Indium Tin Oxide Nanofibers and their Applications for Dye-Sensitized Solar Cells
Authors: Chuangchote Surawut , Sagawa Takashi , Yoshikawa Susumu
Published: October 2011

Indium tin oxide (ITO) nanofibers were fabricated by the combination of sol-gel and electrospinning techniques, from a mixed solution of ITO precursors and an easily spinnable polymer, polyvinylpyrrolidone (PVP). The optimum conditions in electrospinning for the fabrication of smooth and uniform fibers were studied. Calcination of the composite fibers at 570åC resulted in degradation of PVP and highly crystalline nanofibers. The obtained ITO nanofibers showed one-dimensional structure with the diameters about 200 nm. These nanofibers were applied to construct the dye sensitized solar cells (DSSCs) as an upper layer of the transparent conducting oxide (TCO) substrate (between conventional TCO and the metal oxide photoelectrode). When the ITO nanofibers were applied, enhanced photovoltaic performance was attained as compared with the conventional devices.
Graphene Formation on 4H-SiC(0001) Surface Flattened by Catalyst-Assisted Chemical Etching in HF Solution
Authors: Nishitani Keisuke , Sakane Hiroki , Hattori Azusa N. , Okamoto Takeshi , Kawai Kentaro , Uchikoshi Junichi , Sano Yasuhisa , Yamauchi Kazuto , Morita Mizuho , Arima Kenta
Published: October 2011

The preparation of a silicon-carbide (SiC) surface composed of atomically flat terraces and single bilayer steps is essential for the epitaxial growth of high-quality graphene films. We develop a method to flatten a 4H-SiC(0001) surface on the atomic scale in HF solutions with Pt catalysts. After explaining the principle and the setup of our unique process, we reveal the flattening performance by atomic force microscopy (AFM) and scanning tunneling microscopy. Then we graphitize the flattened 4H-SiC(0001) surface at 1150°C in ultrahigh vacuum, and investigate the quality of graphene films by AFM and Raman spectroscopy.
Observation of Removal Process of Thin Metal Film on Glass Surface by Steam-Water Mixed Spray: Application to Au Film Removal in LED Manufacturing
Authors: Sanada Toshiyuki , Hashimoto Kentaro , Hayashida Atsushi , Watanabe Masao
Published: October 2011

In the LED manufacturing process, a thin Au film is deposited on a wafer, and then most of it is removed with small pieces of Au film left for electrodes. For this removal, we apply physical cleaning method, which can remove the metal film without chemicals. In this study, we investigate a removal process of a thin aluminum film deposited on a glass surface by steam-water mixed spray. At the initial stage of this process, tiny spots, whose sizes are the order of droplet diameter, are observed. And then very characteristic removal profiles, which are typically lines with sub-millimeter width, are observed. We discuss the removal mechanism due to high-speed droplet impact.
High-Speed Droplet Impact as an Elementary Process of Physical Cleaning
Authors: Fujikawa Toshihide , Tatekura Yuuki , Kobayashi Kazumichi , Sanada Toshiyuki , Hayashida Atsushi , Watanabe Masao
Published: October 2011

In the steam-water mixed spray-cleaning technique, droplet impact on the solid surface is the one of the primarily important physical processes. We experimentally studied a droplet impact on a solid plate that moves with a speed ranging from 1 to 50 m/s using high-speed video camera. We observed that high-speed liquid film flows radially outward along the surface just after the impact. In addition, we also observed that liquid turns into corona splash in the cases of higher impact velocities. These flows with large velocities can generate huge shear stress on the solid surface, which may contribute to cleaning. Furthermore, we numerically studied the velocity field development and found that gas flow also spreads obliquely upward. The obliquely upward flow field may also contribute in advecting removed particles or stripped resists away from the original place.
Analysis on Threshold Energy of Particle Removal in Spray Cleaning Technology
Authors: Sato Masanobu , Sotoku Kouta , Yamaguchi Kumiko , Tanaka Takayoshi , Kobayashi Mai , Nadahara Soichi
Published: October 2011

In the manufacturing of semiconductor devices, the reduction in the physical strength of device structures due to scaling has caused the problem of pattern collapse by the physical force required for removing particles. A novel advanced spray technology has been developed to accurately and tightly control the droplet size and velocity. The influence of droplet characteristics on particle removal was quantitatively investigated using this technology. It was observed that the amount of removed particles was linked to the droplet energy density on the wafer. The threshold energy to remove particles was analyzed and the relationship between particle removal and pattern damage generation was determined. Finally the process window, which is a particle removable area without pattern collapse, was clearly revealed by the gap between the particle removal and the damage threshold curves.
Improving Megasonic Exposure Uniformity for EUV Mask Substrate Cleaning
Authors: House Matthew , Rastegar Abbas , Dussault Don , Liebscher Eric
Published: October 2011

To achieve surface roughness and flatness requirements, EUV mask substrates should undergo chemical mechanical polishing (CMP), These processes can generate both pit and embedded particles on the surface of low thermal expansion material (LTEM) masks. Megasonic-induced pits are one of the critical defectivity modes for EUV mask blank substrates. Pit defects are generated by cavitation collapse near the surface. This work compares a conventional megasonic nozzle system and a proximity-type radially uniform megasonic system with respect to pit creation. In typical cleaning processes used to remove particles on EUV substrates, the megasonic nozzle generates about 3 times more pits than the radially uniform megasonic system. These pits are located at the center of the plate. Distribution of pits generated by the radially uniform proximity system is uniform throughout the plate as megasonic exposure is uniform across the plate.
Silicon Nano-Pillar Test Structures for Quantitative Evaluation of Wafer Drying Induced Pattern Collapse
Authors: Vos Ingrid , Hellin David , Vertommen Johan , Demand Marc , Boullart Werner
Published: October 2011

Silicon nano-pillars as test structures for quantitative evaluation of advanced wafer drying are presented. The method consists of the use of pillar structures with an aspect ratio up to 28 in combination with top-down SEM inspection and subsequent image analysis for quantification. The test vehicle allows characterizing cleaning techniques by a threshold aspect ratio below which value the features do not collapse. As such, a higher critical aspect ratio corresponds to a superior wetting/drying method. Furthermore, as the metrology is specific and includes cluster size distribution analysis, it can bring new insights in the mechanism of pattern collapse.
Effects of Varying Surface Film Thickness on Particle Adhesion in Semiconductor Material-Based Systems
Authors: Smith Katie M. , Butterbaugh Jeffery , Beaudoin Stephen
Published: October 2011

The effects of surface film thickness on particle adhesion are examined for a number of common microelectronics device materials. These effects are investigated for a laboratory-scale model system, using atomic force microscopy, as well as an industrial-scale system, via particle removal efficiency experiments. Our results show that surface films below a critical thickness δ* are effectively invisible, from an adhesion perspective, while those having thicknesses greater than δ* exhibit bulk material behavior, essentially screening any influence from the underlying substrate. In systems with surface films of thicknesses (approximately) equal to δ*, the net adhesion results from a combination of film and substrate contributions.
Interactions between Developable Bottom Anti Reflective Materials and Surface Preparations
Authors: Garnier Philippe , Briend Guillaume , Jeanjean Damien , Babaud Laurene , May Michael
Published: October 2011

Latest generations of integrated circuits require some tight control of critical dimensions during photolithography's operations. Hence the introduction of dBARCs (developable Bottom Anti Reflective Coating) at many litho steps. This greatly improves the optical performances [1], especially when the photo lithography is performed on wafers with irregular topology. Nonetheless a high care is required on the areas where the resist is developed. Indeed, organic residues are often left on these surfaces with serious consequences. This article brings some characterizations' data and solutions.
Water Motion over a Wafer Surface Rotating in a Single-Wafer Wet Cleaner
Authors: Habuka Hitoshi , Ohashi Shintaro , Tsuchimochi Taka-Aki , Kinoshita Tetsuo
Published: October 2011

Water motion over a 200-mm diameter wafer surface rotating in a single-wafer wet cleaner was observed and calculated, by means of the water flow visualization technique and the computational fluid dynamics, respectively. The tracer, the blue-colored ink, injected from the wafer center symmetrically spread over the rotating wafer surface from its center to the edge. The radial velocity of the water was nearly constant over the wafer surface except at its center area. The water layer thickness in the rotation rate range, approximately 0.1 mm, gradually decreased with the increasing rotation rate. The tracer injected from non-center positions tended to be localized in the peripheral region of the wafer, particularly at the high rotation rates.
Deoxification of Liquids for Advanced Semiconductors Processing
Authors: Gottschalk Christiane , Brammer Ulrich , Le Tiec Yannick
Published: October 2011

Deoxification offers new opportunities in Back End Of Line (BEOL) and also in Front End Of Line (FEOL) to optimize transistor performance. This work presents how to treat ultra pure water (UPW), with and without chemistry, to decrease oxygen concentration to reach ultra low levels. A new approach for a deoxification system will be discussed to meet these upcoming requirements. By creating a semi-empirical model considering the permeation of oxygen through tubes back into the liquid, the necessary dimensions of the deoxification system can be predicted and the final concentration at the point of use (POU) calculated. Parameters like gas flow and liquid flow rate, material, grade of inert gas and system pressure were varied. The efficiency of measures to avoid oxygen permeation after the deoxification step is evaluated as well.
Characterization of Semiconductor Surfaces during Surface Conditioning and Functionalization
Authors: Chabal Yves J. , Seitz Oliver , Aureau Damien , Thissen Peter , Peixoto Tatiana
Published: October 2011

Semiconductor surface cleaning, passivation and functionalization are critical steps for applications such as microelectronics, MEMS, sensors, and solar energy harvesting. Progress has relied in part on the development of surface chemical treatments. However, the ability to characterize surfaces at all steps of processing has also been essential and will be emphasized here. This work focuses on the chemical modification of oxide-free, hydrogen-passivated silicon, including wet chemical treatments, atomic layer deposition, and physical deposition. Characterization methods include in-situ infrared absorption spectroscopy, low energy ion scattering, x-ray photoelectron spectroscopy and mass spectrometry, and is complemented by ex-situ spectroscopic ellipsometry and atomic force microscopy.
Electrochemical Impedance Spectroscopy (EIS) Analysis of BTA Removal by TMAH during Post Cu CMP Cleaning Process
Authors: Venkatesh Rajaraman Prasanna , Kim Hyuk Min , Ramanathan Srinivasan , Park Jin-Goo
Published: October 2011

In the present study, the efficiency of TMAH in removing BTA organic layer from Cu surface is evaluated through electrochemical impedance spectroscopy studies. As the conventional EIS measurements could not be applied in situ to study the cleaning system, a modified EIS experimental procedure is adopted in the present work. The impedance data is validated by Kramers Kronig transform (KKT) and modeled by electrical equivalent circuit (EEC) model. Contact angle measurements were also conducted to complement the studies. The results show that a minimum concentration of 0.5 wt % TMAH is required for complete removal of BTA from the Cu surface.
(Invited) SiC Power Devices for Next Generation Energy Efficiency
Authors: Palmour John W. , Das Mrinal , Ryu Sei-Hyung , Hull B. , Cheng L. , Zhang Q. , Callanan R. , O'Loughlin Michael , Burk Al , Agarwal Anant K.
Published: October 2011

Silicon carbide (SiC) materials technology has made rapid advances in recent years. While increasing the wafer diameter from 75 mm to 100 mm, the substrate quality has been greatly improved with much reduced defect density, resulting in higher device yields. Cree is poised to increase the wafer diameter to 150mm in 2012, which will further reduce the cost of SiC devices. SiC Schottky diodes have demonstrated very high reliability in the field and are being extensively used in Switch Mode Power Supplies (SMPS), and solar inverters, and other applications. Cree has also commercially released a 1200 V, 20 A SiC MOSFET which has been used in solar inverter along with SiC Schottky diode to provide an efficiency gain of 2.36%. More recent R&D results at Cree indicate that the on-resistance of the MOSFET can be reduced by 2x, which will further improve performance and reduce cost.
(Invited) Reliability-Driven SiC Power Device Development for Army Applications
Authors: Scozzie Charles J. , Lelis Aivars , Green Ronald
Published: October 2011

The Army is incorporating more and more electronic functionality into its vehicle platforms by converting many hydraulic functions to electronic to allow better power management, performance, and fuel efficiency. Because of high operating temperature (80å-110åC coolant), reliability, and efficiency requirements for these future power electronic systems, silicon carbide (SiC) technology has been under investigation by the Army since 1992. Since a recent demonstration by the Army Research Laboratory (ARL) of a 900-A power module implemented using 1200 V / 80 A SiC MOSFETs has confirmed SiC's high-temperature and high-efficiency advantage over silicon IGBT switches, the assessment of reliability and qualification of these SiC MOSFETs has become an imperative focus. Initial investigation of these large-area 80-A SiC MOSFET die shows that there is a threshold instability that is accelerated at junction temperatures of 150åC and greater and may affect long-term reliability for 10,000-15,000 hr operation. Further, initial attempt at using Si industry reliability standards to qualify these SiC MOSFETs suggests that such standards may need to be modified.
(Invited) GaN-HEMTs for High-Voltage Switching Applications
Authors: Saito Wataru
Published: October 2011

GaN HEMTs can realize high-power-density operation with low power loss in power electronic systems due to ultra low specific on-resistance below the Si-limit. The dynamic on-resistance, however, is degraded by the current collapse phenomena. The relation between the dynamic on-resistance and the maximum electric field peak showed universality, which was independent from the field plate (FP) structure and the wafer. The gate-edge electric field strongly affects the increase of the dynamic on-resistance. Yellow luminescence intensity strongly related with current collapse phenomena and can be utilized as a useful index for improving the wafer quality. High speed switching was obtained at the turn-off switching test with an inductive load. The switching speed of the GaN-HEMT can be controlled by the external gate resistance as same manner as the Si-MOSFET.
(Invited) Driving eGaN FETs in High Performance Power Conversion Systems
Authors: Lidow Alexander , Strydom Johan , De Rooij Michael , Ferencz Andrew , White Robert
Published: October 2011

As enhancement mode gallium-nitride-on-silicon (eGaN®) FETs gain wider acceptance as the successor to the aged power MOSFET, designers have been able to improve power conversion system efficiency, size, and cost. eGaN FETs, however, are based on a relatively immature technology and only recently have they begun to hit the market in applications such as Power over Ethernet (PoE) and DC-DC converters for telecom and computing applications. An overview of the capability of this technology is followed by the exploration of four common circuit topologies: (1) Flyback converters where costs are sensitive and power levels low, (2) forward converters that are best suited in applications requiring high power density and low power, (3) buck converters for applications requiring high power densities, and (4) full bridge isolated converters for applications requiring high power density, high power, and input-to-output isolation. These four topologies cover the majority of applications where eGaN FETs are making the earliest inroads and offer greatest value to the user.
(Invited) High Voltage Normally-Off Transistors and Efficient Schottky Diodes based on GaN Technology
Authors: Wuerfl Joachim , Bahat-Treidel Eldad , Brunner Frank , Cho M. , Hilt Oliver , Knauer Arne , Kotara Przemyslaw , Weyers Markus , Zhytnytska Rimma
Published: October 2011

High voltage GaN based power switching transistors in normally-off technology and efficient GaN Schottky di-odes are indispensable for a steady improvement of effi-ciency in power converters and for cutting down volume and weight of these systems. To obtain ultimate device performance, novel concepts in epitaxial design and growth techniques as well as in processing and packaging technology are required. At FBH, normally-off GaN based power transistors and Schottky diodes have been and are being developed. These efforts cover the full val-ue added chain from epitaxial growth of GaN/AlGaN de-vice structures on 3" n-type SiC substrates, device proc-essing, characterization and interfacing to novel packag-ing techniques. The paper will summarize the most im-portant achievements towards high power GaN devices at FBH and will show up important dependencies towards further improved GaN power devices.
(Invited) Perspectives on SiC and III-N Based Devices for Power Electronics
Authors: Brylinski Christian O. , Planson Dominique
Published: October 2011

SiC devices for power electronics are a reality. A first generation of reliable SiC rectifier devices outperforming all silicon devices has been released on the market with up to 1500V voltage handling capability. At best, GaN based rectifiers, with similar electrical performance and production cost, may reach the market by year 2015. For the same voltage range, prototypes of switching triode SiC devices with control electrode, using JFET and BJT topologies, are also under market evaluation. It seems nobody knows yet whether SiC MOS will finally get reliable enough for voltage over 200 V. III-N based HEMT hetero-junction devices may become superior alternative to the existing SiC switching triode devices. Still, a lot of work will be needed for reaching good enough reliability. On the long term, due to expectable Gallium shortage, SiC based heterojunction devices would offer sustainable solution, although the ideal hetero-structure has not been demonstrated yet.
(Invited) Merits of Buried Grid Technology for Advanced SiC Device Concepts
Authors: Bakowski Mietek , Lim Jang-Kwon , Kaplan Wlodek , Schöner Adolf
Published: October 2011

Some chosen examples of the use of buried grid technology for advanced SiC devices are discussed. First example is development of normally-off and normally-on JFETs. Second is the development of Schottky diodes for high temperature operation. Other examples are efficient junction termination and avalanche UV detector. Experimental results are used in support of simulations.
(Invited) Silicon Carbide Bipolar Power Devices
Authors: Östling Mikael , Ghandi Reza , Malm B. G. , Buono Benedetto , Zetterling Carl Mikael
Published: October 2011

This paper reviews the current state of the art in active switching device performance for SiC BJTs. In addition, some results from simulations are shown with particular attention on temperature and design dependence of the current gain. A design to improve conductivity modulation is also suggested. Finally, performance of a 2.8 kV BJT are illustrated. This device demonstrates high current gain of 52, low on-resistance of 6.8 mΩcm2, fast switching, and no bipolar degradation
(Invited) Electric-Field and Thermally-Activated Failure Mechanisms of AlGaN/GaN High Electron Mobility Transistors
Authors: Zanoni Enrico , Meneghesso Gaudenzio , Meneghini Matteo , Stocco Antonio , Rampazzo Fabiana , Silvestri Riccardo , Rossetto Isabella , Ronchi Nicolò
Published: October 2011

Main failure modes of AlGaN/GaN HEMTs can be divided into three main categories: 1) Catastrophic increase of gate leakage, accompanied by an increase in trap density which closely resembles time dependent dielectric breakdown effects of MOS structures; 2) hot-electrons and trap-induced effects, which induce increase in parasitic drain resistance and threshold voltage shifts; 3) thermally-activated degradation of drain current, which has been observed especially during long-term accelerated tests, with a very wide range of activation energies, from 1.05 eV to 2.47 eV. In the following, some recent results concerning these three failure modes are presented, together with some hypothesis on the degradation mechanisms involved.
(Invited) Mitigating Defects within Silicon Carbide Epitaxy
Authors: Caldwell Joshua D. , Stahlbush R.S. , Mahadik N.
Published: October 2011

Over the past decade, significant progress has been made in reducing the density of several extended and point defects within silicon carbide substrates and epitaxy. For instance, great success has been achieved in the elimination of micropipes and reductions in the lifetime killing point defect Z1/2. However, a wide-array of extended defects persist, ranging from various types of stacking faults and threading dislocations. An overview of the current status of these efforts is outlined here.
(Invited) Numerical Simulation of the GaN Growth Process in a MOCVD Process
Authors: Meng Jiandong , Jaluria Yogesh
Published: October 2011

This paper describes a model for the GaN growth in a vertical impinging metalorganic chemical vapor deposition (MOCVD) reactor. The flow, temperature, concentration profiles and growth rate are predicted by numerical modeling, which is performed using a commercial CFD software package CFD-ACE+. A detailed mathematical model is developed first, and the complete chemical mechanisms are introduced. Then, the dependence of the growth rate and uniformity of the deposited layers on operating conditions, such as reactor operating pressure, susceptor temperature, inlet velocity and concentration of the precursors is investigated to gain greater insight into the reactor performance and characteristics. Based on the simulation results, some discussion is presented to offer the possibility of a deeper understanding of the GaN film growth process and to ultimately lead to an optimization of the process and to ultimately lead to an optimization of the process, with respect to production rate and film quality.
(Invited) MOCVD Growth and Characterization of GaN HEMT Material
Authors: Guo Shiping , Gao Xiang , Gorka Daniel , Pan Ming , Oliver Mark
Published: October 2011

AlGaN/GaN HEMTs are of interest for high power and high frequency device applications due to their superior material properties. MOCVD growth of GaN HEMTs shows great promise for scale-up volume production with high fabrication yield and subsequently low manufacture cost. Volume production of GaN HEMTs on 3" and 100 mm SiC has been demonstrated at IQE. Various characterizations have been used to evaluate the material quality, uniformity and epi growth reproducibility. SPC charts show superb wafer-to-wafer reproducibility with a Cpk of ~2.0 for sheet resistance uniformity. Lehighton, contactless Hall, XRD and Accent PL measurements show excellent wafer uniformity. Bow/Warp tests indicate that the epi growth process only adds up to 10 μm bow/warp. AFM measurements indicate an atomic smooth surface.
(Invited) Passive Component Technologies for Advanced Power Conversion Enabled by Wide-Band-Gap Power Devices
Authors: Sullivan Charles R. , Yao Di , Gamache Garet , Latham Alexander , Qiu Jizheng
Published: October 2011

Modern power electronics typically operate with switching frequencies in the tens of kilohertz to a few megahertz. SiC and GaN power switches promise to enable increasing these frequencies by an order of magnitude or more. Doing so would allow reducing the energy storage requirements for passive components, particularly transformers and inductors, which typically take up the largest portion of the volume of a power converter, and which are also responsible for much of the power loss, cost, and design difficulty in the converter. In principle, a smaller energy storage requirement should make these components smaller and lower in loss and cost. However, material, fabrication, and design constraints make it hard to achieve such improvements. These issues are reviewed and new results on design optimization of low profile air-core inductors and loss characterization of high-performance magnetic materials for 10 to 100 MHz are presented.
(Invited) Integrated Power Inductors and Capacitors Enabled by a Multilevel Molding Process
Authors: Meyer Christopher D. , Bedair Sarah S. , Xue Lin , Dougherty Christopher M. , Bashirullah Rizwan , Arnold David P. , Morgan Brian C.
Published: October 2011

We summarize here recent advancements toward integration of electronic passives for electrical power converters. Microscale inductors and capacitors with three-dimensional, free-standing copper traces are formed via a multi-layer molding and electroplating process. This capability creates two complementary routes for passives microfabrication: (a) high inductance density air-core inductors with vertically-stacked windings; and (b) inductors and capacitors with ferromagnetic and dielectric nanoparticles deposited through capillary-driven self-assembly. Several designs of air-core inductors are tested with inductance densities >100 nH/mm2 and quality factors >20. A suspended transmission line is encapsulated in NiFe2O4 magnetic nanoparticles for 25% greater inductance and no detriment to the quality factor up to 100 MHz. Deposition of BaTiO3 dielectric nanoparticles between nested capacitor electrodes yields up to a 6x increase in capacitance.
(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs
Authors: Takagi Shinichi , Zhang Rui , Hoshii Takuya , Taoka Noriyuki , Takenaka Mitsuru
Published: October 2011

In order to realize high current drive and low supply voltage CMOS, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO2/Ge interfaces have been regarded as promising. We have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al2O3/GeOx/Ge gate stacks were fabricated by exposing the ALD Al2O3/Ge structures to ECR oxygen plasma. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer is shown to reduce Dit down to low order of 1011 cm-2eV-1.
Interaction of Aluminum Oxide with Germanium during Thermal Annealing in Ar, N2/H2,O2, or H2O
Authors: Radtke Cláudio , Molina Bom Nicolau , Vieira Soares Gabriel , Krug Cristiano , Jacob Rabin Baumvol Israel
Published: October 2011

Five-nanometer-thick Al2O3 films were deposited on Ge substrates by reactive sputtering and submitted to post-deposition annealings (PDAs) in argon, forming gas, oxygen, or water vapor at 350 or 500oC for 30 min. Photoelectron spectroscopy evidenced that Ge was oxidized during the deposition process. Thermal annealing in argon or forming gas reduced the amount of oxidized Ge. Oxygen and water strongly interacted with the Ge substrate. Particularly for water at 500oC, ion scattering analyses evidenced the presence of Ge throughout the Al2O3 layer and on the sample surface. This was attributed to the formation and desorption of GeO from the dielectric/Ge interface.
Fabrication of High-k/Ge Stacks with High Quality GeO2 Interlayer
Authors: Suzuki Yuya , Oniki Yusuke , Iwazaki Yoshitaka , Ueno Tomo
Published: October 2011

Successful fabrication process of high-k/Ge with GeO2 interlayer has been proposed. Low temperature oxidation of Ge substrate gave rise to no GeO desorption at GeO2/Ge interface, that maintains the interface property to be good except a large VFB shift. Deposition of component metals of high-k material on the GeO2/Ge structure was effective to improve the VFB shift with low temperature annealing. Therefore, low temperature oxidation annealing of metal on GeO2/Ge structure has been expected to fabricate high-k/GeO2/Ge with good interface property. In case of Al2O3/GeO2/Ge, this prediction has been proved. In case of HfO2/GeO2/Ge, however, during the thermal treatment the Hf metal diffuse into Ge substrate which causes the formation of the hillocks. The good characteristic was obtained by preventing the hillocks being formed.
(Invited) Defects and Impurities in Ge-Based Electronic Devices
Authors: Tsetseris Leonidas
Published: October 2011

Further advances in the performance and reliability of Ge-based electronic devices require an understanding of the most prominent types of defects and impurities in these systems. In this respect, computational studies can play an important role for the elucidation of the physical mechanisms that control the stability and dynamics of these defects. Here we will review recent results of first-principles calculations within density-functional theory on Ge-related imperfections in the bulk of various dielectrics and at the boundary between a gate oxide and a Ge substrate. We will also discuss results on the stability of hydrogen impurities and dopant-hydrogen complexes in SiGe alloys.
Theoretical and Experimetal Demonstration of Electronic State of GeO2
Authors: Chang Hung-Chih , Lu S.-C , Chang W.-C , Chou T.-P , Lan H.-S , Lin C.-M , Liu C.W.
Published: October 2011

The transition levels of oxygen vacancy (Vo) in GeO2 with different charge state are calculated by first principle method. The formation energy of GeO2 indicate there is a (+2/0) fix charge state in bulk GeO2. The (+1/0) transition level near Ge valence band maximum which shows positive charge trap of GeO2. We demonstrate a Ge MOS capacitor with thermal oxidation. The hysteresis of CV shows a negative Vfb shift which correspond to the positive charge trap as theoretical calculation imply.
(Invited) Growth of InAs/InAlAs Core-Shell Nanowires on Si and Transistor Application
Authors: Tomioka Katsuhiro , Tanaka Tomotaka , Fukui Takashi
Published: October 2011

We review the fabrication process for a surrounding-gate transistor using InAs and InAs/InAlAs core-multishell nanowires (NWs) heterogeneously integrated on Si. Selective-area metal-organic vapor-phase epitaxy (SA-MOVPE) that allows for the position-controlled growth of vertical InAs NWs on (111) oriented surfaces using lithographic techniques was used to grow these nanowires. The nanometer-scale growth enabled for the integration of III-V NWs on Si regardless of apparent lattice mismatches. A non-planar vertical transistor architecture, which is a vertical surrounding-gate structure, was demonstrated on Si substrate. This demonstrated device should have broad applications for use in high-electron mobility transistors with a functionality not made possible using conventional Si-CMOS techniques.
Enhanced Electrical Properties of Carbon Doped Epitaxial Gd2O3 Thin Films on Si Substrates
Authors: Laha Apurba , Bin A , Babu P R P , Fissel A , Osten H Jörg
Published: October 2011

The impact of carbon doping on electrical properties of epitaxial Gd2O3 grown on Si substrates has been studied. The doping with low concentration of carbon into epitaxial Gd2O3 shows strong influence on dielectric properties especially to the reduction of leakage current behavior. The structural quality of the oxide layer is merely influenced by small amount of carbon incorporation. The most critical observation of this study is that the very often found adverse effect of oxygen vacancy induced defects in oxides grown at higher temperature could be eliminated by moderate amount of carbon doping during growth.
Effects of Iridium Oxide Thickness and Post Annealing Temperature on the Size and Density of Core-Shell IrOx-Based Nanocrystals of a Nonvolatile Memory Device
Authors: Li WeiChih , Yang Jer-Ren
Published: October 2011

The purpose of this study is to investigate the size and density of IrOx nanocrystals with the conditions of two iridium oxide thicknesses under two post deposition annealing temperature treatments. Through the microstructural investigation, growing mechanism of IrOx nanocrystals is well explained.
Size-Dependent Trapping Effect in Nano-Dot Non-Volatile Memory
Authors: Tsai Chun-Yang , Cheng Chun-Hu , Chang Ting-Yu , Chou K. Y. , Chin Albert , Yeh F. S.
Published: October 2011

We report a flash memory using deep traps nano-dot formed in ZrON charge trapping layers by As+ implantation to improve the device performance of MONOS CTF device. The TaN-[SiO2-LaAlO3]-[As+-implanted ZrON]-[LaAlO3-SiO2]-Si device shows a 6 nm ENT, a large initial memory window of 9.8 V, a 10-year extrapolated retention window of 3.6 V at 85oC, and an endurance window of 5.1 V after 105 cycles under fast 100 μs and low μ16 V program/erase. The performance of As+-implanted ZrON is significantly better than that of stacked Si3N4/Ir-dot/HfON device with poor thickness scaling due to excess Ir metal dot.
(Invited) Epitaxial HfO2 Thin Films on Si Substrates: Strategy for Sub-1 nm EOT Technology
Authors: Migita Shinji , Ota Hiroyuki
Published: October 2011

Equivalent oxide thickness (EOT) of gate dielectric films was scaled to sub-1 nm by epitaxial growth of HfO2 films on Si substrates. The process consists of two parts; deposition of amorphous HfO2 films on Si substrates and crystallization in a solid-phase epitaxy manner. Conventional productions tools of atomic-layer deposition and rapid thermal anneal were applied to construct this technique. Epitaxial growth of HfO2 films was confirmed on both Si (100) and Si (111) substrates. Metal-oxide-semiconductor capacitors and field-effect transistors were fabricated, and electrical properties were measured. The thinnest EOT accomplished by this technique was 0.5 nm, and the gate leakage current was about 6 times smaller than the SiO2 case at the same EOT. Potential of crystalline high-k films in future gate stack technology is discussed on the basis of their crystal growth behaviors.
The NH3 Nitridation Effects on a Al2O3 Passivation by Atomic Layer Deposition (ALD) in the HfO2/GaAs Systems
Authors: Cho Young Dae , Suh Dong Chan , Ko Dae-Hong , Lee Yongshik , Cho Mann-ho
Published: October 2011

We investigated the nitridation effects on a passivating Al2O3 layer formed by atomic layer deposition (ALD) process at the interface of HfO2/GaAs. Results reveal that formation of Ga-O is suppressed greatly when annealed under NH3 ambient for the HfO2/GaAs system. Moreover if the Al2O3 layer is thick enough, diffusion of Ga into the high-k dielectric is blocked effectively, even after heat treatment at 500oC. This not only suppresses formation of interfacial oxide, but also improves the electrical properties. The nitrogen contents present in NH3 ambient lead to a decrease in the interfacial layer, which in turn decreases the effective oxide thickness (EOT). Results of chemical analyses by x-ray photoelectron spectroscopy (XPS) and micro-structure analyses by high-resolution transmission electron microscopy (HR-TEM) are presented.
Study of the Structural and Thermal Properties of Single Crystalline Epitaxial Rare-Earth-Metal Oxide Layers Grown on Si(111)
Authors: Dargis Rytis , Williams David , Smith Robin , Arkun Erdem , Semans Scott , Vosters Gary , Lebby Michael , Clark Andrew
Published: October 2011

Stress due to crystal lattice mismatch of rare-earth-metal oxide layer epitaxial grown by molecular beam epitaxy on Si(111) substrates and thermal expansion induced stress in the system were studied. X-ray diffraction measurements of the layers were performed during heating up to 1000åC. The layers are almost fully relaxed at room temperature. Only minor tetragonal distortion of the crystal lattice was detected. No thermal stress relaxation was indicated by x-ray diffraction in the oxide layer during the heating and cooling procedure. The time-domain thermo-reflectance technique was used for measurement of the thermal conductivity of the oxide layers. Thermal conductivity of the rare earth oxides is approximately five times higher than that of silicon dioxide.
(Invited) Active Trap Determination at the Interface of Ge and In0.53Ga0.47 as Substrates with Dielectric Layers
Authors: Molle Alessandro , Baldovino Silvia , Lamagna Luca , Spiga Sabina , Lamperti Alessio , Fanciulli Marco , Tsoutsou Dimitra , Golias Evangelos , Dimoulas Athanasios , Brammertz Guy , Merckling Clement , Caymax Matty
Published: October 2011

Due to the high carrier mobility, Ge and III-V semiconductors are attractive as active channels for post-Si metal oxide semiconductor (MOS) devices. However, integration of gate dielectrics on high-mobility substrates is frequently jeopardized by the electrical activity of traps nearby the interface. Active traps determination at the interface between the two semiconductors with gate dielectrics has been conducted with the aim to validate several electrical passivation methodologies. In particular, GeO2 and LaGeOx passivations of Ge are investigated by conjugating magnetic resonance spectroscopy and electrical response of the MOS capacitors. The case of In0.53Ga0.47As is addressed by tailoring the surface treatments and the growth parameters in the trimethyaluminum based atomic layer desposition of Al2O3 films. The electrical quality of the Al2O3/In0.53Ga0.47As interface is assessed by exploring the temperature dependent electrical response of the MOS capacitors and admittance spectroscopy of the active traps energetically distributed in the In0.53Ga0.47As bandgap.
In Situ Deposited HfO2 with Amorphous-Si Passivation as a Potential Gate Stack for High Mobility (In)GaSb- Based P-MOSFETs
Authors: Nagaiah Padmaja , Tokranov Vadim , Yakimov Michael , Madisetti Shailesh , Greene Andrew , Novak Steven , Moore Robert , Bakhru Hassaram , Oktyabrsky Serge
Published: October 2011

Electrical and structural properties of GaSb metal-oxide-semiconductor capacitors with in-situ deposited HfO2 gate dielectric and in-situ deposited amorphous silicon interface passivation layer are presented. Capacitance-voltage characteristics with low C-V stretch out, reduced hysteresis, lower EOT is obtained in a temperature range of 3500C-5500C post deposition annealing in forming gas. The gate leakage current of the gate stack was ≤ 1μA/cm2. p-MOSFETs fabricated on epitaxially grown strained (In)GaSb quantum channel (ε=1.6%) channels using this all in-situ high-k gate stack showed a maximum ION=23mA/mm for a 3μm gate length device
Characterization of the Solid State Properties of Anodic Oxides on Ta-Nb Alloys as a Function of the Anodizing Conditions
Authors: Di Franco Francesco , Zampardi Giorgia , Santamaria Monica , Di Quarto Francesco , Habazaki Hiroki
Published: October 2011

Tantalum oxide, niobium oxide and Ta-Nb containing mixed oxides were grown by anodizing sputter-deposited TaxNb(1-x) alloys with 0 ≤ x ≤ 1. A photoelectrochemical investigation was performed in order to estimate the band gap values of the oxides as a function of their composition as well as to estimate their flat band potential. Differential capacitance curves were recorded for all the investigated oxides in a wide range of electrode potential and for several frequencies of the alternative signal. The dependence of C on the applied potential and a.c. frequency was interpreted on the basis of amorphous semiconductor Schottky barrier, and allowed to estimate the dielectric constant of the investigated oxides.
(Invited) Dielectric Breakdown in Ultra-Thin Hf Based Gate Stacks: A Resistive Switching Phenomenon
Authors: Rodriguez Rosana , Martin-Martinez Javier , Crespo-Yepes Albert , Porti Marc , Nafria Montserrat , Aymerich Xavier
Published: October 2011

The gate dielectric breakdown (BD) reversibility in MOSFETs with ultra-thin hafnium based high-k dielectric is studied. The phenomenology is analyzed in detail and the similarities with the resistive switching phenomenon emphasized. The results show that after BD, the switch between two different conductive states in the dielectric is possible. We have demonstrated that the conduction in both states is local, which has been verified through CAFM measurements. Additionally, the injected charge to the first recovery (QR) has been proposed as a parameter to describe the BD reversibility phenomenon. The BD recovery partially restores not only the current through the gate, but also the MOSFET channel related characteristics. The electrical performance of MOSFETs after the dielectric recovery has been modeled and introduced in a circuit simulator. The simulation of several digital circuits shows that their functionality, though somehow affected, can be restored after BD recovery.
Impact of Constant Voltage Stress on High-κ Gate Dielectric for RF IC Performance
Authors: Paliwoda Peter , Misra Durga
Published: October 2011

Challenges in modern CMOS RF IC design include optimizing gain, noise and linearity. These parameters are highly dependent on transconductance (gm) and threshold voltage (Vt). Introduction of high-κ dielectrics with metal gates in advanced CMOS gate stacks requires that the impact of any variation of gm and Vt due to stress on RFIC performance needs to be investigated thoroughly. This paper investigates the effect of positive constant voltage stress (CVS) on device parameter degradation which may have a potential impact on analog and mixed-signal CMOS circuitry. Significant decrease in gm and increase in Vt was observed under CVS due to electron trapping.
Characteristics of Liquid-Phase-Deposited SrTiO3 Films on GaN and AlGaN/GaN Wafer
Authors: Wu Tsu-Yi , Sze Po-Wen , Hu Chih C. , Huang Tong-Jyun , Adriyanto Feri , Wu Chang-Luen , Wang Yeong-Her
Published: October 2011

Through a simple, low-temperature liquid-phase deposition (LPD) method, SrTiO3 thin films were deposited on GaN as the gate dielectric for metal oxide semiconductor high electron mobility transistor application. X-ray photoelectron spectroscopy was employed to characterize the films. Electrical characteristics of the SrTiO3 films on GaN showed that the lowest leakage current was 4.2x10-9 A/cm2 at -1 MV/cm after annealing at 400°C. AlGaN/GaN MOSHEMTs with LPD-SrTiO3 of 20 nm-thick as the gate dielectric were also fabricated. The suppressed gate leakage current improves both subthreshold slope and on/off current ratio. Wider gate voltage swing and flatter transconductance of the MOSHEMT demonstrate better device linearity.
Near Room-Temperature Liquid-Phase Deposition of Barium-Doped TiO2 on n-GaN and its Application to AlGaN/GaN MOSHEMTs
Authors: Hu Chih C. , Lin Mon-Sen , Wu Tsu-Yi , Adriyanto Feri , Sze Po-Wen , Wu Chang-Luen , Wang Yeong-Her
Published: October 2011

Barium-doped TiO2 films deposited on GaN layers at low temperature through a simple liquid-phase deposition method is investigated. The use as a gate dielectric in AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs) is also demonstrated. The electrical characteristics of the metal-oxide-semiconductor (MOS) structure on n-doped GaN show that the leakage current density is about 5.09 × 10-9 A/cm2 at 1 MV/cm, and the breakdown field is more than 13 MV/cm. The maximum drain current density of the AlGaN/GaN MOSHEMTs is higher than that of HEMTs, in which a wider gate voltage swing, a lower sub-threshold swing (112mV/dec), and a higher ION/IOFF ratio (4.5×105) are obtained.
(Invited) Synchrotron Radiation Nano-Spectroscopy of Dielectrics for LSI and ReRAM
Authors: Oshima Masaharu , Toyoda Satoshi , Horiba Koji , Yasuhara Ryutaro , Kumigashira Hiroshi
Published: October 2011

Metal/high-k gate dielectrics stack structures for LSIs and metal/transition-metal-oxides(TMO)/metal structures for resistance random access memory (ReRAM) have been analyzed using synchrotron radiation nano-spectroscopy from the viewpoint of interfacial chemical and electronic states. We have developed a scanning photoelectron microscope(SPEM) with an angle-resolved electron analyzer and succeeded in obtaining chemicalstate-resolved images and pin-point in-depth profiles of LSI gate patterns with 70 nm lateral resolution. For ReRAM, chemical-state-resolved images of Cu for a planar-type Pt/CuO/Pt resistance switching (RS) device revealed conductive filaments in TMO using photoelectron emission microscope (PEEM). Furthermore, in and out diffusion phenomena of oxygen corresponding to bias polarity for RS were observed for Pt/TaOx/Pt switching devices. Interfacial redox reactions which are common to all ReRAM devices are also observed for Al/TMO interfaces.
High Speed Switching Characteristics of Pt/Ta2O5/Cu Memristive Switch
Authors: Shrestha Pragya , Ochia Adaku , Cheung Kin P. , Champbell Jason P. , Baumgart Helmut , Harris Gary
Published: October 2011

Accurately measure the transient details of switching memristive switch is crucial to the elucidation of the switching mechanism. Such high-speed measurements often plagued by artifacts. Here we describe a measurement technique capable of capturing Set/Reset characteristics of memristive switches with high accuracy. It can accurately measure the transient current during the Set/Reset operation with rise time as short as 2 ns. The circuit is designed to cycle through (Set/Reset) and sense (read the state) rapidly to enable the study of endurance. The sense circuit is able to measure currents as low as 30 pA yielding accurate measurement of the resistance in the off state up to 1.6 GΩ. Pt/Ta2O5/Cu memeristive switches are examined that exhibit ON and OFF state resistance (Ron and Roff) ratio of >104 and endurance cycles of >6x104.
Effect of Top Electrode Material on Resistive Switching Characteristics in MnO2 Nonvolatile Memory Devices
Authors: Tsai Yu-Ting , Chang Ting-Chang , Lin Chao-Cheng , Chiang Lan-Shin , Chen Shih-Cheng , Sze Simon M. , Tseng Tseung-Yuen
Published: October 2011

The inﬂuence of top electrode material on the resistive switching properties of MnO2-based memory film using Pt as a bottom electrode was investigated in this study. In comparison with Pt/ MnO2/Pt and Al/ MnO2/Pt devices, the Ti/ MnO2/Pt device exhibits resistive switching current-voltage (I-V) curve, which can be traced and reproduced more than 105 times only showing a little decrease of resistance ratio between high and low resistance states. Furthermore, transmission electron microscopy analyses are used to confirm the crystalline structure of MnO2 on Pt bottom electrode. Secondary ion mass spectrometry reveals a change of oxygen distribution in MnO2 thin film due to material characteristic of variant top electrodes. We suggest that the interface between MnO2 and electrodes play an important role on the resistive switching behaviors.