bluuebunny/crossref_metadata_2025 huggingface dataset:
Implementation of DMAs in Intermittent Water Supply Networks Based on Equity Criteria
Authors: Ilaya-Ayza Amilkar , Martins Carlos , Campbell Enrique , Izquierdo Joaquín
Published: November 2017

Intermittent supply is a common way of delivering water in many developing countries. Limitations on water and economic resources, in addition to poor management and population growth, limit the possibilities of delivering water 24 h a day. Intermittent water supply networks are usually designed and managed in an empirical manner, or using tools and criteria devised for continuous supply systems, and this approach can produce supply inequity. In this paper, an approach based on the hydraulic capacity concept, which uses soft computing tools of graph theory and cluster analysis, is developed to define sectors, also called district metered areas (DMAs), to produce an equitable water supply. Moreover, this approach helps determine the supply time for each sector, which depends on each sector’s hydraulic characteristics. This process also includes the opinions of water company experts, the individuals who are best acquainted with the intricacies of the network.
Updates on Dietary Models of Nonalcoholic Fatty Liver Disease: Current Studies and Insights
Authors: Stephenson Kristen , Kennedy Lindsey , Hargrove Laura , Demieville Jennifer , Thomson Joanne , Alpini Gianfranco , Francis Heather
Published: November 2017

Nonalcoholic fatty liver disease (NAFLD) is a disease of increasing interest, as its prevalence is on the rise. NAFLD has been linked to metabolic syndrome, which is becoming more common due to the Western diet. Because NAFLD can lead to cirrhosis and related complications including
hepatocellular carcinoma, the increasing prevalence is concerning, and medical therapy aimed at treating NAFLD is of great interest. Researchers studying the effects of medical therapy on NAFLD use dietary mouse models. The two main types of mouse model diets are the methionine- and choline-deficient
(MCD) diet and the Western-like diet (WD). Although both induce NAFLD, the mechanisms are very different. We reviewed several studies conducted within the last 5 years that used MCD diet or WD mouse models in order to mimic this disease in a way most similar to humans. The MCD diet inconsistently
induces NAFLD and fibrosis and does not completely induce metabolic syndrome. Thus, the clinical significance of the MCD diet is questionable. In contrast, WD mouse models consisting of high fat, cholesterol, and a combination of high-fructose corn syrup, sucrose, fructose, or glucose not
only lead to metabolic syndrome but also induce NAFLD with fibrosis, making these choices most suitable for research.
Long-Term Protective Effect of N-Acetylcysteine against Amikacin-Induced Ototoxicity in End-Stage Renal Disease: A Randomized Trial
Authors: Vural Alperen , Koçyiğit İsmail , Şan Furkan , Eroğlu Eray , Ketenci İbrahim , Ünal Aydin , Tokgöz Bülent , Ünlü Yaşar
Published: November 2017

Background

The aim of the study is to evaluate the long-term protective effect of N-acetylcysteine (NAC), an antioxidant agent, against aminoglycoside (AG)-induced ototoxicity.

Methods

A total of 40 patients receiving continuous ambulatory peritoneal dialysis (CAPD) and having their first peritonitis attacks and planned to be treated with AGs were enrolled in the study. They were randomized into 2 groups: 1 group received additional NAC and the other did not. All patients underwent hearing tests with pure tone audiometry (PTA) after the diagnosis, at 1 month and 12 months and at the same time the tumor necrosis factor (TNF)-α and interleukin (IL)-6 levels were measured.

Results

Patients taking NAC had better hearing test results in both ears at 1 month except 2,000 Hz for the left ear, which wasn't significantly different between the 2 groups. Although patients taking NAC had generally better PTA results at 12 months, differences between the 2 groups were not statistically significant. Baseline IL-6 level was significantly higher in the NAC group than the control group. Both TNF-α and IL-6 levels at 1 month were significantly lower in the NAC group than in the control group. On the other hand, there was no significant difference between the 2 groups in terms of TNF-α and IL-6 levels at 12 months.

Conclusions

The results of the current study showed that NAC, a potent anti-inflamatory drug, may be otoprotective, but that the effect is not long-lasting.
One-pot syntheses of blue-luminescent 4-aryl-1H-benzo[f]isoindole-1,3(2H)-diones by T3P® activation of 3-arylpropiolic acids
Authors: Denißen Melanie , Kraus Alexander , Reiss Guido J , Müller Thomas J J
Published: November 2017

In situ activation of 3-arylpropiolic acids with T3P® (n-propylphosphonic acid anhydride) initiates a domino reaction furnishing 4-arylnaphtho[2,3-c]furan-1,3-diones in excellent yields. Upon employing these anhydrides as reactive intermediates blue-luminescent 4-aryl-1H-benzo[f]isoindole-1,3(2H)-diones are formed by consecutive pseudo three-component syntheses in a one-pot fashion. The Stokes shifts correlate excellently with the Hammett–Taft σR parameter indicating an extended degree of resonance stabilization in the vibrationally relaxed excited singlet state.
H2 Ortho-to-para Conversion on Grains: A Route to Fast Deuterium Fractionation in Dense Cloud Cores?
Authors: Bovino S. , Grassi T. , Schleicher D. R. G. , Caselli P.
Published: November 2017

Deuterium fractionation, i.e., the enhancement of deuterated species with respect to non-deuterated ones, is considered to be a reliable chemical clock of star-forming regions. This process is strongly affected by the ortho-to-para H2 ratio. In this Letter we explore the effect of the ortho–para (o–p) H2 conversion on grains on the deuteration timescale in fully-depleted dense cores, including the most relevant uncertainties that affect this complex process. We show that (i) the o–p H2 conversion on grains is not strongly influenced by the uncertainties on the conversion time and the sticking coefficient, and (ii) that the process is controlled by the temperature and the residence time of ortho-H2 on the surface, i.e., by the binding energy. We find that for binding energies between 330 and 550 K, depending on the temperature, the o–p H2 conversion on grains can shorten the deuterium fractionation timescale by orders of magnitude, opening a new route for explaining the large observed deuteration fraction D
frac in dense molecular cloud cores. Our results suggest that the star formation timescale, when estimated through the timescale to reach the observed deuteration fractions, might be shorter than previously proposed. However, more accurate measurements of the binding energy are needed in order to better assess the overall role of this process.
Vélocemen, hiverneurs et Algériens
Authors: Pas Niek
Published: November 2017

Cet article porte sur l’histoire sociale et culturelle de l’introduction et du développement du cyclisme en Algérie, des années 1880 à 1914. Avec la boxe et le football, le cyclisme compte parmi les sports les plus populaires. Le vélo est considéré comme le vecteur d’une culture sportive internationale qui dépasse le cadre Métropole-Algérie. Sa pratique est multifonctionnelle et représente un espace de rencontres variées. En Algérie française, elle constitue à la fois un espace de compétition et de confrontation, de domination et d’émancipation, et un lieu d’échanges, au niveau local, régional et international.
Inflorescence and floral traits of the Colombian species of Tristerix (Loranthaceae) related to hummingbird pollination
Authors: González Favio , Pabón-Mora Natalia
Published: November 2017

Floral diversification in Loranthaceae reaches its highest peak in the Andes. The flowers of the exclusively Andean genus Tristerix exhibit tubular and vividly coloured flowers pollinated by hummingbirds. We studied inflorescence and flower morphoanatomy of the two Colombian species, T. longebracteatus and the highly endangered T. secundus. Both species have terminal racemes with up to 26 ebracteolate flowers, of which the proximal one opens and sets fruits first. The slightly irregular calyx initiation is followed by the simultaneous initiation of petals and the successive initiation of stamens. Anthesis is fenestrate, explosive, and triggered by the tension of the style against the abaxial petals, a mode so far not reported in Loranthaceae. Anthetic petals spread symmetrically in T. longebracteatus and asymmetrically in T. secundus. Nectar is produced by a supraovarial disk and by the petal mesophyll. Floral lifespan lasts up to 20 days. The hummingbirds Eriocnemis vestita and Pterophanes cyanopterus are the likely pollinators of T. secundus. Morphological traits are inconclusive to support one of the two competing sister group relationships that involve Tristerix, as the lack of cataphylls in renewal shoots links Ligaria and Tristerix, whereas the terminal inflorescences support its relationship with Desmaria and Tupeia.
Stencil Print solutions for Advance Packaging Applications
Authors: Vallabhajosyula Phani
Published: November 2017

This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging.

As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high-performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um–40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package.

Cavity technology can be an effective solution in reducing the total assembled PCB thickness (Z-height), most importantly, on designs utilizing taller - stacked devices. Traditionally, dipping process or dispensing process was used to deposit solder paste, flux, or glue on uneven surfaces. However, this takes a longer time when compared to printing using a stencil printer. Reservoir printing using a stencil printer has greater potential in such application. Extensive work has been done in the past to print glue, solder paste and/or flux into cavities using reservoir printing. This paper focuses on printing solder paste into multiple cavities (stencil pockets) with depths ranging from 355 microns to 450 microns, and with varying cavity size, wall angles and various stencil thicknesses ranging from 100 microns to 150 microns. Apertures varying in area ratio were placed in these cavities and experiments were conducted to analyze the print performance of the stencils. As the size of the components and boards/substrates gets smaller - closer placement of components to the cavity (stencil pocket) walls needed to be assessed as well.

These applications, the associated stencil design and print results were discussed in detail in this paper.
Rapid Prototyping Tape Stencils for the Application of Solder Paste
Authors: Yang Mimi X. , Dowling Karen , Senesky Debbie , Wong H.-S. Philip
Published: November 2017

This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.
High Current Testing and Simulation for Land Grid Array Sockets
Authors: Beaman Brian , Audet Jean
Published: November 2017

Land grid array (LGA) sockets are commonly used for industry standard and custom microprocessors to meet the increased performance challenges for a variety of server applications. Along with the need for increased high speed signaling capabilities comes the challenge to support lower voltages and higher currents. Typical testing that is conducted by the LGA socket suppliers does not provide an accurate assessment of the maximum current capabilities in a real product application due to the test card design and construction limitations. Typical test card designs use daisy chain connections to wire multiple LGA socket contacts in series. The daisy chain wiring in the test card adds to the resistive heating and results in an inaccurate maximum current rating. Also, the test cards typically do not have a cross section construction that is representative of a real product application with multiple ground planes that provide improved thermal dissipation of the heat generated by the LGA socket interface.

Hardware testing was conducted to better understand the performance limitations for a new product application. The test card was designed to use multiple voltage and ground planes in the circuit card cross section to provide a low impedance path for current flow and a low voltage drop through the LGA socket interface. In addition to the test card construction, the test hardware included a special test module with a shorted chip to provide a more accurate power distribution path through the socket and processor package. The test variables included different plating metallurgy options for the LGA socket and the processor module along with different configurations for the voltage supply and ground return contacts. Electrical and thermal modeling techniques were used to simulate the test hardware configuration with good correlation between the hardware and modeling results. Based on the positive correlation results, additional modeling was conducted to simulate the worst case power mapping conditions for the processor chip along with a more accurate power distribution. The additional modeling results provided further insights into the maximum current capabilities for the LGA socket based on the temperature increase from the resistive heating in the socket contacts.
Relation between relative humidity and electrical performance of electrochromic displays
Authors: Garcia Alexandre , Jin Huiting , Olafsen Kjell , Kolberg Sigbjørn , Wright Daniel Nilsen , Visser Taklo Maaike M. , Eveborn Annelie , Hagel Olle , Eriksson Torbjörn
Published: November 2017

Electrochromic displays are among the key components of smart tags and their performance, defined by the color switch time, is directly linked to the level of humidity inside the displays. A time-efficient procedure, based on the use of a gravimetric moisture analyzer, was implemented, where the water content in a display could be related to the temperature and relative humidity of the manufacturing environment. The electrical performance of the displays was evaluated by measuring current as a function of time during voltage pulses of 4 s as these measurements quantified the time needed for color switch (should be < 1 s). The electrical performance was also measured as a function of the temperature and relative humidity of the manufacturing environment. By varying the temperature and the relative humidity systematically and measuring water content and display performance, a correlation between water content, switch time and manufacturing environment could be established and a safe range for manufacturing conditions could be found.
3D Printed Integrated Microfluidic Cooling for High Power RF Applications
Authors: Craton Michael , Ghazali Mohd Ifwat Mohd , Wright Brian , Park Kyoung Youl , Chahal Premjeet , Papapolymerou John
Published: November 2017

This paper presents the design and fabrication of microfluidic channel integration in a plastic substrate using 3D printing. The microfluidic channels are integrated along with a copper plate which the coolant is in direct contact with. To demonstrate the design, a diode intended for switched power supplies is integrated onto the copper plate and its performance characterized. 3D printing or additive manufacturing (AM) allows for fast prototyping of such package designs and can be readily adopted in the fabrication of RF circuits. This paper, to the best of our knowledge, for the first time will demonstrate a 3D printed integrated microfluidic channel for the cooling of electronic circuits. Details of design, fabrication and characterization are presented.
Journey to Success for New Analog Technologies for Texas Instruments
Authors: Magaña Mario , Chatterjee Basab , Javier Rey
Published: November 2017

TI's commitment to meeting customer requirements has resulted in the development of package technologies and process to improve performance and higher power at lower cost for wire-bonded packages and automotive products are requiring more stringent reliability requirements.

Some of the strategies we have adopted include using thinner metal and low-K ILD for lower parasitics and higher performance, thick copper routings for higher power and larger wafer diameters and smaller scribe streets for lower cost and using Copper (Cu) wire. Cu wire is a key enabler due to higher electrical conductivity and lower cost than gold), but also poses integration challenges due to hardness, CTE mismatch and corrosion susceptibility. The hardness of the copper wire imposes significant challenges for wire-bonding on pads w thin metal and low-k ILD. This required co-design of die bond pad structure for enhanced reliability as well as Cu wire process development requires comprehensive approach encompassing multiple areas including ball and stitch parameters, capillary design, bonding processes like segmented bonding and validation of process margins using ‘hammer’ test. Copper wire also requires metrology and test/detection tools like Nomarski, stitch pull test in addition to the traditional wire pull at mid span and neck, rapid-bake test, measuring intermetallics & Al remaining under ball, and Al-splash. The susceptibility of Cu wire to corrosion required us to introduce new materials like PCC and Au-flash PCC, tight environmental controls in the form of forming gas, monitoring of Ph and ion-trappers in BOM, wire oxidation check at outgoing/incoming inspection as SERA (Sequential Electrochemical Reduction Analysis), and paying close attention to handling and non-process gases. More stringent qualification requirements like AEC-006 is driving additional changes to lead frame design and finish, selection of EMC and Die attach, to reduce delamination and epoxy bleed-out.

The demands for lower cost is driving us to use larger sized wafers (like 300mm) and narrower scribe width, while packing more functionality into smaller dies thereby driving higher metal densities. Additional requirements for thinner and 3D packages requiring post backgrind thickness as low as 50–75um imposing challenges in terms of warpage and saw. The demand for higher power applications is requiring us to use thick copper routings. We have developed test structures and redesigned layout of the scribe street and scribe seal and pursuing new saw methods. We have also learned many lessons in terms of handling and corrosion risks and implemented safeguards in terms of process and material selection.
Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design
Authors: Sethu Raj Sekar , Kulkarni Salil Hari , Ha How Ung , Soon Kok Heng
Published: November 2017

Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.
Operation of Silicon Carbide Integrated Circuits under High Temperature and Pressure
Authors: Barlow M. , Francis A. M. , Holmes J.
Published: November 2017

Silicon carbide integrated circuits have demonstrated the ability to function at temperatures as high as 600 °C for extended periods of time. Many environments where high temperature in-situ electronics are desired also have large pressures as well. While some validation has been done for high pressure environments, limited information on the parametric impact of pressure on SiC integrated circuits is available. This paper takes two leading-edge SiC integrated circuit processes using two different classes of devices (JFET and CMOS), and measures the performance through temperature and pressure variation. Circuit functionality was verified at high temperature (475 °C) as well as high pressure (1700 psig).
Solderability and Reliability Evolution of No-Clean Solder Fluxes For Selective Soldering
Authors: Guéné Emmanuelle , Anisko Richard , Puechagut Céline
Published: November 2017

Flux consumption for wave soldering tends to decrease, mainly due to its gradual replacement by reflow soldering methods (i.e. pin-in-paste) in many electronics applications. However, in several cases, wave soldering still remains a must, with an increasing share of “selective” soldering processes, either using wave frames with dedicated apertures or solder fountains. Such processes are more challenging for the fluxes in terms of reliability under operation, since some chemistries remaining on the printed circuit boards after soldering may promote corrosion. Thus, flux manufacturers had to adapt their formulations to minimize such issues while keeping an efficient activation level, with several types of alloys (tin-lead, tin-silver-copper and low/no-silver) and associated with the numerous types of finishes encountered.

The paper will cover the types of flux used in the electronic industry according to their chemistry and activation level (rosin-based, halides, alcohol-based or water-based flux…), and their characteristics with reference to standards. The limits of current standards will be discussed in regards to the last generation solder fluxes.

Then, the development of two low-residue new generation fluxes, an alcohol-based flux and a true VOC-free flux, will be described, according to requirements: the lab tests results (surface tension, spread tests, wettability tests…) will be presented and discussed. Reliability will be especially investigated through surface insulation resistance, electro-chemical migration test, ionic contamination as well as Bono tests to determine the candidates able to provide high processability combined with chemical inertness of residues. Finally, the performance of flux will be assessed through customer tests, involving several types of boards, finishes and different solder alloys and wave equipment.
Characterizations of Fan-out Wafer-Level Packaging
Authors: Li Ming , Li Qingqian , Lau John , Fan Nelson , Kuah Eric , Kai Wu , Cheung Ken , Li Zhang , Tan Kim Hwee , Xu Iris , Chen Dong , Beica Rozalia , Ko CT , Yang Henry , Lim Sze Pei , Ran Jiang , Xi Cao
Published: November 2017

The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.
Effective Inspection Methods for Advanced Packaging Technologies
Authors: Brueckner Julia , Schwander Michael , Jurgschat Moritz , Tuason Ramon
Published: November 2017

Advanced packaging technologies have ramped up to provide solutions for new high density devices that are based on the integration of several components with different functions. The need for thin packages with memory, APU, modem and analog all packed in one requires each individual layer thickness to have exacting specifications. In this work we concentrate on the challenging task of measuring epoxy mold compound (EMC) thickness distribution across the wafer. We will present how an optical sensor based on spectral coherence interferometry (SCI) can be utilized to collect critical measurements related to mold thickness, uniformity and height information between bumps and the mold surface. SCI provides an optical, non-destructive, high-throughput solution to measure mold thickness and surface warpage simultaneously. This is done by utilizing a sensor with high numerical aperture (NA) which enables one to measure layers and surfaces of mold materials despite the usual measurement constraints introduced from high roughness values, high internal scattering, and severe wafer warpage. By adding a bottom sensor in a so called twin-configuration, further simultaneous data collection is possible.
Photoresist Residue Detection in Advanced Packaging
Authors: Cohen Jonathan , Han Woo Young , Singh Gurvinder , Best Keith , Shay Amy , Marshall Mike
Published: November 2017

Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required. With continued focus on device miniaturization, the rapid detection of trace chemical residue during intermediate processing steps becomes increasingly difficult. In the lithography area, detection of polymer residue on wafer surfaces presents special opportunities. One area of opportunity for the detection of lithographic polymer residue takes advantage of the fact that these materials possess unique optical properties not found in metals or other inorganic materials used in semiconductor manufacturing. Rudolph Technologies has submitted patent applications for a novel defect illumination technique that offers key advantages over traditional white light inspection. This paper will present the results of using this inspection technique for the detection of photoresist residue on test wafers as well as on actual customer devices. Sample data included herein are representative of advanced packaging technology used today by a wide range of semiconductor manufacturers and OSAT facilities. While this novel inspection technique will not be a panacea for all trace residue detection problems, it offers a method complementary with bright field or dark field inspection when these two traditional inspection methods lack the sensitivity required.
Planar Antenna for Terahertz Application in Fan Out Wafer Level Package
Authors: Ishibashi Daijiro , Nakata Yoshihiro
Published: November 2017

This paper shows the terahertz planar antenna integration module structure using a fan out wafer level package (FOWLP), and the important parameters when that structure is designed. A FOWLP enabled a low-loss connection. Embedding an insulator and reflector into the mold resin improved flexibility of the module design. In this paper, the patch antenna was employed as a planar antenna in a proposed structure, and that antenna was operated at 300 GHz. For the design of this structure, two parameters were noted as the most important factors. One was the thickness of the insulator of the patch antenna. The optimal thickness of between 40 μm and 80 μm allowed the radiation efficiency to remain high. The other factor was the gaps of the vias between the ground of the microstrip line and the reflector. The gaps of a quarter-wavelength or less made the antenna characteristics excellent.
Fully Printed Static Gain Reconfigurable Conformal Patch Antenna Arrays
Authors: Grant Nolan , Haghzadeh Mahdi , Akyurtlu Alkim
Published: November 2017

This work presents design and fabrication processes for creating statically gain-reconfigurable conformal patch array antennas. In our previous work, a fully printable and conformal antenna array on a flexible substrate with a new Left-Handed Transmission Line (LHTL) phase shifter based on a Barium Strontium Titanate (BST)/polymer composite was computationally studied for radiation pattern correction and beam steering applications. In this work, additive manufacturing techniques were used to experimentally demonstrate the phase compensation needed to improve the degraded performance of the conformal arrays. An Aerosol Jet direct-write printer was used to print several patch antenna arrays and was tested in an anechoic chamber to establish baseline gain metrics. Once a baseline is established, a high dielectric constant material (BST nano-ink) was dispensed onto the IDCs in several configurations, to provide the necessary phase compensation. The antennas were retested and the changes in their gain profiles were investigated. The findings of this work and the proposed method allow for gain compensation of curved conformal antennas and post-production modification of the radiation pattern of antenna arrays. This work has potential applications in the automotive industry due to the low cost of production and the ability to be integrated onto curved conformal surfaces without interfering with super structure or other mechanical design related criteria.
RELIABILITY; WHAT'S RIGHT FOR YOUR BUSINESS?
Authors: Mohanty Rita
Published: November 2017

In today's high-tech world, we heavily depend on electronics for our health, safety, mobility and economic welfare. When they fail, the results can be as minor as consumer annoyance to as severe as loss of life. Not to mention a significant financial penalty to the producer in the form of warranty cost. In the electronics industry, especially in the consumer electronics segment, warranty expense cost can be 1% - 2% of the total revenue1. As an example, for a $1B company, this can impact the bottom line by $10M–$20M. For this reason, reducing warranty cost through increased product reliability is not only necessary for survival but also smart.

However, achieving product reliability in today's environment with limited development resources and demand for reducing product development cycle time creates a special challenge. In addition, many small to medium size organizations struggle to understand the basic concepts behind reliability engineering, often confusing it with quality. This paper presents a lean approach to developing and implementing a reliability program that is simple, flexible and woven into a product development program.
Modeling Vibration Induced Fatigue Failure of Free Standing Wire Bonds
Authors: Shen Zhenzhen , Storey James , Fanini Otto , Osterman Michael
Published: November 2017

Wire bonds are used to connect device terminals to package terminals or substrate terminal that forms circuits that are needed to create desired higher level functions. If a wire bond breaks or becomes detached during operation, the desired function will be lost. Depending on the design, a loss in function could be catastrophic. Aluminum, gold, and copper wires are used to create wire bonds in electronic products. These materials have been selected for their ability to be formed as fine wires and their ability to provide low electrical resistance.

In many electronics packages, wire bonds are encapsulated in a polymer molding compound that is used to protect the electronic device. However, in some electronic devices such as hermetically sealed cavity packages, wire bonds may be free-standing. Under vibration loading, free-standing wire bonds may be subject to failure due to mechanical fatigue.

In this work, an analytic model is presented for predicting natural frequency of a free-standing wire bond and for assessing a wire bond time to failure under a harmonic loading condition. The model for natural frequency is calibrated by finite element analysis and validated through experimental testing. The life prediction model, a test plan, and preliminary test results are presented.
Reinforced Solder Technology for Increased Reliability
Authors: Jensen Tim , Neoh Sunny , Murling Adam
Published: November 2017

The reliability of solder joints have been studied for many years. The selection of a solder for a particular application is often limited based on melting point requirements. This limits the number of options that are available for use. When alloy selection options are limited, people look to process changes to try and improve the reliability. Two such areas that have been identified that can impact reliability are bondline control and void reduction. This paper analyzes a new reinforced solder technology to maintain a consistent solder joint bondline. Experiments were also conducted to determine how best to design these preforms to minimize voiding.
Reduction of Thermal Stress - Part III: UBM and Passivation Thickness Optimization
Authors: Sethu Raj Sekar , Kulkarni Salil Hari , Ha How Ung , Soon Kok Heng
Published: November 2017

Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps. Finite Element Analysis (FEA) of such designs can help identify possible root causes early in the design process and i.e. before actual fabrication. This would help save valuable prototyping & testing costs. In Part III of this series of FEA studies, two factors i.e. silicon nitride thickness (from the BEOL process), and the Under Bump Metalization (UBM) thickness (from the WLP process) were identified as significant factors in changing the maximum first principal stress levels in the passivation layer.
Supply Chain Hardware Integrity for Electronics Defense (SHIELD) Using Small “Dielets”
Authors: Chorosinski Len , Sundaram Venky , Wolter Klaus , Calatayud Richard , Ralston Parrish , Suko Scott , Fry David , Ellerhoff Nathanael
Published: November 2017

Under the DARPA/MTO SHIELD program, a Northrop Grumman led team is developing a supply chain traceability and authentication method to protect against the growing threat of counterfeit electronic parts. The foundation of our SHIELD solution is an advanced 100μm × 100μm × 20μm near-field RFID “dielet” fabricated on 14nm CMOS. This dielet will be embedded in a host component's packaging and provides a hardware root-of-trust through the integration of advanced key protection and cryptographic techniques. Throughout the life-cycle of the host component, the authenticity can be verified using an RF probe to energize and communicate with the dielet, performing a cryptographic challenge and providing a response to a centralized secure server and SHIELD authenticity database. This paper provides a general overview of the dielet design, packaging, and host component insertion.

This research was developed with funding from the DARPA. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.
Nondestructive Imaging of Packaged Microelectronics using Pulsed Terahertz Technology
Authors: Bowman Tyler , El-Shenawee Magda
Published: November 2017

This work presents the use of terahertz reflection imaging for nondestructive evaluation of packaged microelectronics. Power MOSFETs and SRAM devices are placed in a pulsed terahertz imaging system in the reflection mode with an incident angle of 30°. From the received signal at each point on the sample under test, the internal structure of the device can be clearly seen. For transistors, terahertz nondestructive imaging has been successful in determining die size and location as well as the bond wire size, number, and connections. High-pass frequency filters are utilized to enhance the image quality for viewing the bond wires. In addition, the terahertz B-scans are used to determine additional information including the vertical position of the bond wires and the die inside the packaged device. For the SRAM, the terahertz nondestructive imaging shows similar effectiveness in defining the layout of the metal connections inside the package and the wire positions. Thus terahertz imaging is shown to have a strong potential for nondestructive evaluation of these devices.
Development of Thinner POP Base Package by Die Embedded and RDL Structure
Authors: Kyozuka Masahiro , Kiso Takahiko , Toyazaki Hiroki , Tanaka Koichi , Koyama Tetsuya
Published: November 2017

As mobility products, such as smart phones, tablets and wearable devices, continue on the paths of both miniaturization and high performance, components and packaging are likewise driven to become smaller and thinner. In mobile devices, a thinner package is required, especially for the Application Processor and memory combination.

The Package-on-Package structure can achieve module thinness by embedding a die (or dies) into a package and is thus attractive for reducing the height of an AP. The Die-Embedded and RDL structure has been in development as a package corresponding to POP structure. This structure has two characteristics of manufacturing method, based on the substrate manufacturing process. One is the RDL-first process, whereby the RDL is manufactured before die attachment. This process decreases the die loss from defects in the RDL formation. The other method is to manufacture the packages in panel form instead of wafer form.

The key features of this structure are panel-form manufacturing and via connection between the substrate and the top-RDL. In IMAPS 2016, the Die Embedded and RDL structure on i-THOP®, which was used as the substrate was reported. The die-to-die inter connection was fabricated on i-THOP® for a 2.1D application. Both the die attachment and the RDL formation were successfully performed. The reliability tests proceeded. The results indicated that the i-THOP® with the Die Embedded and RDL structure can be applied to packaging of AP in mobile devices.

The next challenge is to make a smaller package using the Die Embedded and RDL structure. To decrease the package area, a finer-pitch via connection that was less than the design rule of 200μm was evaluated. For reduction of package thickness, a thinner substrate, approximately 160μm thickness, was applied. The new test sample with these improvements was designed and proceeded to evaluation. The dimensions of the sample are 15 × 15 mm2 size and 340μm thickness (without solder ball), a 100μm-thick die was embedded and a one-layer of RDL was formed on the die.

In this development, the warpage of the thin substrate after die attachment might be large, so there is an issue of package warpage and the handling of a thin substrate. In this report, results of low warpage structure design and development status of fine via connection formation are described.
Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging
Authors: Palesko Chet , Lujan Amy
Published: November 2017

Fan-out wafer-level packaging (FOWLP) and embedded die packaging offer similar advantages over traditional packaging technologies. For example, both packages can be quite thin since the die is placed early in the manufacturing process and the package is fabricated around the die. This is in contrast to traditional packaging technologies, in which the package is fabricated first, and then the die is placed on top of the package. This results in a thicker package compared to fabricating the package around the die. Due to the ongoing miniaturization market requirements, thinner packages are becoming increasingly important. Both FOWLP and embedded die packaging also provide the capability of placing multiple die and passives in a single package. This capability can have both size and performance benefits since the interconnect distance between the embedded components is shorter.

In this paper, the cost and cost drivers of FOWLP and embedded die packaging technologies will be compared. Activity based modeling will be used to characterize the cost of each activity in the two manufacturing flows.
Multichip Module Planarity Requirements Derived From Solder Surface Tension Models
Authors: Marinis Thomas F. , Soucy Joseph W.
Published: November 2017

The number of die and routing layers in multichip modules has been steadily increasing, which has exasperated the problem of maintaining module planarity for interconnect to a system board. The usual remedies are to try to balance the composition of the layers on either side of the module's neutral axis or to build the layers on a stiff, planar interposer. Both of these approaches can impact module performance, size and cost. We have examined an alternative approach to accommodating module bow, by allowing the solder ball interconnects to compress or elongate as necessary to maintain electrical connections. This approach is further enhanced by making the module very thin, which does not reduce its bow, but rather allows the high surface tension force exerted by molten solder to flatten the module. We have derived a model for the surface tension force exerted by a solder ball as a function of the degree to which it is compressed or elongated. This model also predicts the maximum elongation that the solder connection can sustain before it ruptures. We have applied this model in a design tool, which allows us to predict the maximum module bow that can be accommodated as a function of the number, size and location of the solder connections and the physical composition of the multichip module.
High Reliability and High Throughput Ball Bumping Process Solution – Solder Joint Encapsulant Adhesives
Authors: Liu Mary , Yin Wusheng
Published: November 2017

The miniaturization of microchips is always driving force for revolution and innovation in the electronic industry. When the pitch of bumps is getting smaller and smaller the ball size has to be gradually reduced. However the reliability of smaller ball size is getting weaker and weaker, so some traditional methods such as capillary underfilling, corner bonding and edge bonding process have been being implemented in board level assembly process to enhance drop and thermal cycling performance.

These traditional processes have been increasingly considered to be bottleneck for further miniaturization because the completion of these processes demands more space. So the interest of eliminating these processes has been increased. To meet this demand, YINCAE has developed solder joint encapsulant adhesives for ball bumping applications to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. In this paper we will discuss the ball bumping process, the reliability such as strength of solder joints, drop test performance and thermal cycling performance.
Power cycle reliability of SiC devices with metal-sinter die-attach and thermostable molding
Authors: Nagao Shijo , Fujita Hirofumi , Shimoyama Akio , Seki Shinya , Zhang Hao , Suganuma Katsuaki
Published: November 2017

Metal paste sintering die-attach is recently attracting much attention as an alternative to Pb containing high temperature solders, particularly required for power device packaging with post-Si wide band-gap semiconductors. For high voltage and high power devices, which are used in electric vehicles, railway trains, or power grid systems, SiC MSOFET/SBD devices are emerging replacing Si IGBT devices. These SiC devices have two prominent advantages to traditional Si based devices: fast switching and high maximum junction temperature TJ. The excellent characteristics serve for miniaturization of the device module; the former allows to use smaller capacitor and reactors because of the high frequency, and the latter excludes cooling system without affecting the device life time. However, the thermal reliability should be critically tested before used in industrial applications. We have hence conducted comprehensive reliability tests using several types of metal sintering die-attach including Ag and Cu. High temperature storage tests at 250°C certify that the device structure is truly thermostable, and thermal cycling between −50°C and 250°C indicates that the thermomechanical stress caused by device package design is the key for high reliability of power devices. Power cycling demonstrates the usefulness for effective acceleration tests to estimate the device life time. Our results conclude that present metal paste die-attach is ready for use in the product instead of high temperature solders.