bluuebunny/crossref_metadata_2025 huggingface dataset:
MULTI-STANDARD RECEIVER BASEBAND CHAIN USING DIGITALLY PROGRAMMABLE OTA BASED ON CCII AND CURRENT DIVISION NETWORKS
Authors: MAHMOUD SOLIMAN A. , SOLIMAN EMAN A.
Published: March 2013

In this paper, a digitally programmable OTA-based multi-standard receiver baseband chain is presented. The multi-standard receiver baseband chain consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF. The receiver is suitable for Bluetooth/UMTS/DVB-H/WLAN standards. Three different programmable OTA architectures based on second generation current conveyors (CCIIs) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and good linearity — better than -50 dB HD3 — is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6 mW. The DC gain varies over a 68 dB range with 1 MHz to 13.6 MHz programmable bandwidth. The receiver baseband chain is realized using 90 nm CMOS technology model under ±0.5 V voltage supply.
CHIRAL AND UA(1) SYMMETRY IN CORRELATION FUNCTIONS IN MEDIUM
Authors: LEE SU HOUNG , CHO SUNGTAE
Published: March 2013

In this review, we will discuss how the chiral symmetry and UA(1) breaking effects are reflected in the correlation functions. Using the Banks–Casher formula, one can identify the density of zero eigenvalues to be the common ingredient that governs the chiral symmetry breaking in correlation functions between currents composed of light quarks with or without a heavy quark. Similarly, the presence of the UA(1) breaking effect is determined through the contribution of the topologically nontrivial configurations that depends on the number of flavors. We also discuss how the symmetry breaking effects are reflected in the gluon correlation functions. Finally, we review the Witten–Veneziano (WV) formula for the η' mass in medium.
REFINING THE NPD/INNOVATION PATH TO PRODUCT MARKET SUCCESS WITH PARTIAL LEAST SQUARES PATH ANALYSIS
Authors: MILLSON MURRAY R.
Published: March 2013

In this paper, a refinement of the NPD/innovation process and its relationship with new product success is explored. Through a review of the literature, a rationale for a research model and the associations among its constructs were developed. In this study, a factor analysis was performed on data describing the proficiency by which major, traditional NPD/innovation process activities were performed. This analysis led to the development of seven parsimonious NPD/innovation process activities. This research evaluated new product success by employing four measures: profit, sales, successfully opening new markets, and successfully entering existing markets with new products. Respondents to a mail survey process directed to NPD managers in the medical instruments, heavy construction equipment, and electrical products industries provided the study's empirical data. The research model was examined by performing a Partial Least Squares (PLS) path analysis on the study data. PLS path analysis was employed to provide an answer to the research question: How does the proficiency with which new product development activities are performed relate to the market success of newly developed products? The factor analysis and subsequent PLS path analysis suggest that (1) there are seven important NPD/innovation activities that form the basis for a prudent view of new product development/innovation, (2) there is a parallel path to new product success much of which occurs after new product commercialization, and (3) NPD proficiency continues to significantly influence the market success of new products. Implications from this research are provided.
NETWORK STRUCTURE AND INNOVATION IN STRATEGIC INNOVATION NETWORKS
Authors: ROXENHALL TOMMY
Published: March 2013

This paper seeks to improve our understanding of how network structure affects innovation outcomes in strategic innovation networks. The theoretical argument is illustrated by the case of a Swedish strategic innovation network. Asocial network analysis of the relationships between 58 network members was conducted. Roughly half of the network actors were involved in producing innovations; they had significantly larger, higher-density networks and occupied more central positions in their networks than did those not participating in the innovation or scientific work.
A call for champions
Authors: Nakano Hiroaki , Styles Matthew G. , Draper Geoffrey M.
Published: March 2013

Anecdotal evidence suggests that, despite a widespread consensus on the importance of studying the history of computing, courses on this subject are rarely taught at the university level. This paper provides data in support of the anecdotal evidence. After surveying over 20 faculty members who have taught or currently teach courses on the history of computing, we found that offerings of this course are indeed on the decline. We report reasons why this may be so, and, more importantly, suggest ways in which computer science (CS) departments, with a bit of creativity, can develop a successful course on the history of computing at their institutions.
CS 1 language adoption at California Community Colleges
Authors: Nevins Dean
Published: March 2013

This paper studies the languages used in introductory programming courses by all the computer science programs in the California Community College system for the calendar year 2012. Most colleges offer a single language (82%) using the face-to-face modality (73%) with C++ (48% of total sections offered) as their instructional language. Other instructional languages and percent using them are Java (31%), C (9%), BASIC (8%), and Others (4%). Comparing these use patterns to other language adoption studies shows that the California Community College system differs from most other institutions in its choice of C++ over Java.
On consistent inconsistencies
Authors: Sapir Amir
Published: March 2013

The most common measure for an algorithm's efficiency is its running time, described as a function of the input length. Traditionally, however, several inconsistencies have found their way even to the analysis of the most classical algorithms. In some cases these are 'slight' inconsistencies, in the sense that their effect may change the result by a factor of lgn. Some others have a polynomial effect, and on the extreme---an exponential one. We discuss this matter, bringing pairs of examples for each of the categories of effect. In the first member of the pair, the algorithm's running time is calculated accurately, whereas in the other member, it is analyzed incorrectly, demonstrating that the computing community is being inconsistent when it comes to algorithm analysis. The article's intention is not to ask authors of textbooks on algorithms to produce modified editions of their books. Rather, it wishes to raise the question of inconsistency in our treatment of algorithm analysis among various algorithms.
(Invited) In-situ Observation of Formation of Bonded Interface using MEMS-in-TEM at the Nanoscale
Authors: Ishida Tadashi , Fujita Hiroyuki
Published: March 2013

It is important to establish bonding technology to have strong bond between two wafers for future integrated device with high performance and multi functions. Direct bonding and eutectic bonding are the major techniques and are utilized for packaging and connection in commercial devices. However, the understandings of the mechanism of these techniques are not enough. Therefore, we establish a unique experimental setup combining micro-electro-mechanical systems (MEMS) of transmission electron microscope (TEM) in order to visualize the bonding interface at the nanoscale. In this paper, we introduce the in-situ observation of silicon-silicon and gold-gold interface for direct bonding, and that of gold-silicon interface for eutectic bonding at the nanoscale.
The Study on Defects of Germanium-on-Insulator Fabricated by a Low Temperature Smart-Cut Process
Authors: Zhang Xuanxiong , Yang Fan , Ou Yi , Ye Tianchun , Zhuang Songlin
Published: March 2013

Germanium-on-insulator (GeOI) was manufactured by a low temperature Smart-cut process. The blistering of H-implanted Ge wafer was first studied and the kinetics of blistering onset (time) as a function of annealing temperature was described to determine the subsequent splitting. Germanium layer transfer was achieved by a 2700C annealing after the atomic level Ge/SiO2 wafer bonding was formed by a 1500C annealing. The defects on the transferred Ge layer were mitigated thanks to the extended annealing and mainly distributed at the rim of GeOI wafer.
High Resolution Double-Crystal X-ray Diffraction Imaging for Interfacial Defect Detection in Bonded Wafers
Authors: Sharma Saurabh , Goorsky M. S.
Published: March 2013

Wafer bonding is used for the integration of heterogeneous semiconductor materials, without the constraints of lattice constant or crystal structure mismatch. The most important aspect of such bonding is the surface flatness and the absence of particles in the bonded interface. It is very important to identify these particles, which can further result in poor bonding. The most common method for identifying has been IR imaging, but it is limited to materials which are transparent in the operating region of the CCD camera. Also, the resolution of IR image is low. X-ray diffraction imaging (topography) has been identified as the most sensitive and high resolution imaging technique capable of resolving variations due to very small particles within both the bonded and the unbonded areas. It also allows for imaging of samples which are opaque to IR, like heavily doped wafers.
Evaluation of Titanium Direct Bonding Mechanism
Authors: Baudin Floriane , Delaye Vincent , Guedj Cyril , Chevalier Nicolas , Mariolle Denis , Imbert Bruno , Fabbri Jean-Marc , Di Cioccio Léa , Bréchet Yves
Published: March 2013

Direct metal bonding represents an advanced joining technology that allows vertical stacking with electrical conduction and even heat dissipation. For most metals used as bonding layers, direct bonding when operating at ambient air involves metal oxides. The bonding interface saddles with a trapped oxide layer that might affect electrical conduction and even complete sealing of bonding interface. Titanium especially, because of its high affinity with oxygen, makes oxide free direct bonding very difficult. In the mean time, the remarkable getter effect of Ti matrix allows the dissolution of oxygen during post bonding annealing. In this paper, the bonding limits with regards to the titanium thickness have been investigated. The key role of layer roughness on the bonding quality and energy has been pointed out. A titanium thickness below 10nm appears as a limit for an oxide free bonding.
A Study of Factors Influencing Micro-Chevron-Testing of Glass Frit Bonded Interfaces
Authors: Naumann Falk , Bernasch Michael , Brand Sebastian , Wünsch Dirk , Vogel Klaus , Czurratis Peter , Petzold Matthias
Published: March 2013

On industrial scale, glass frit bonding is widely used for assembly and encapsulation of MEMS. A key task to guarantee functionality and reliability is the classification of the quality and strength of the bonding interface. Caused by the wide range of used test setups and test parameters, the estimated strength values are not directly comparable to each other. The presented work discusses critical parameters and test setups, which influence resulting strength values of glass frit bonded interfaces. For this purpose, mechanical testing is supported by scanning acoustic microscopy inspection for sample validation. The results can provide a guideline for the evaluation of comparable strength properties of glass frit bonded interfaces.
Advanced Characterization of a Direct Wafer Bonding-compatible Germanium Exfoliation Process
Authors: Ferain Isabelle Pauline , Kou Xiaolu , Moulet-Ventosa Caroline , Goorsky M. S. , Colinge Cindy
Published: March 2013

In this study, it is demonstrated that the propagation of long-range cracks in hydrogen-implanted germanium with a low-temperature exfoliation process (300 {degree sign}C max) is as complete as with conventional exfoliation processes that take place at higher temperatures. Such low-temperature exfoliation process is fully compliant with direct silicon to germanium wafer bonding. It allows for limited lattice deformation - enhanced bond strength i.e. - and limited voids formation at the bond interface during post-bonding anneal.
Integrating Laser Diode and Optical Isolator by Photosensitive Adhesive Bonding
Authors: Yokoi Hideki , Ichishima Norihiko , Myouenzono Isamu
Published: March 2013

An integrating technique between a laser diode and an optical isolator is proposed. The optical isolator has a magneto-optic waveguide with a Si guiding layer. The laser diode is integrated with the optical isolator by use of photosensitive adhesive bonding. A coupling efficiency between an active layer of the laser diode and a passive waveguide is discussed. Photosensitive adhesive bonding between a garnet crystal and a SiO2 substrate is demonstrated.
MgZnO/ZnO Heterostructure Field-Effect Transistors Fabricated by RF-Sputtering
Authors: Cheng I-Chun , Wang Bo-Shiung , Hou Hsin-Hu , Chen Jian-Zhang
Published: March 2013

We study the rf-sputtered MgZnO/ZnO heterostructure material system. Two dimensional electron gases are observed in the defective polycrystalline material system. As the MgZnO thickness increases, the sheet resistance reduces rapidly and then saturates. The enhancement of the interfacial polarization effect becomes stronger, corresponding to a larger amount of resistance reduction, when the Mg content in the MgZnO layer increases. Al-doped MgZnO is then introduced as the modulation doping layer to further raise the carrier density without diminishing the carrier mobility. Finally, rf-sputtered MgZnO/ZnO heterostructure thin film transistors (TFTs) are successfully demonstrated. The threshold voltage, field-effect mobility and on/off current ratio of the Mg0.2Zn0.8O/ZnO heterostructure thin film transistor are -0.55 V, 84.2 cm2V-1s-1, and 2x10^6, respectively. In comparison to the ZnO counterpart (VTH= 0.47V, μFE= 1.5 cm2V-1s-1, ON/OFF = 10^5), the polarization effect truly increases the carrier concentration at the interface and improves the field-effect mobility.
The Stability and Reliability of Mixed Oxide-Based Thin Film Transistors under Gamma Irradiation
Authors: Alford Terry L , Indluru Anil , Vemuri Rajitha N. P. , Holbert Keith E.
Published: March 2013

This research reports the performance of low temperature fabricated indium zinc oxide (IZO) TFTs under the influence of gamma radiation. Irradiation with a dose of 1.7 Mrads resulted in a negative threshold voltage shift and degradation in the subthreshold swing. The electron mobility however increased on gamma exposure from 2.8 to 8.8 cm2/V-s. The variation in the density of interface states created and electron-hole pairs generated attribute to the change in electrical properties. Moreover, the reliable electrical behavior of IZO TFTs over a-Si:H TFTs under gamma radiation makes them a promising alternative for future applications that require radiation hard TFTs.
Study of Electronic Structure and Film Composition at Back Channel Surface of Amorphous In-Ga-Zn-O Thin Films
Authors: Hino Aya , Kishi Tomoya , Morita Shinya , Hayashi Kazushi , Kugimiya Toshihiro
Published: March 2013

Electronic structure and film composition at back channel surfaces of amorphous In-Ga-Zn-O (a-IGZO) thin films were characterized using photoelectron yield spectroscopy (PYS), ultraviolet photoelectron spectroscopy (UPS), and photoelectron spectroscopy for chemical analysis (ESCA). Surface gap states near the valence band maximum were observed. Downward band bending was also detected near the surface (up to 5~7 nm) region. In accordance with the band bending, the film composition was changed; the content of In increased as approaching to the surface, while that of Ga decreased. Photoluminescence spectra suggested that the composition change caused the increase in the gap states at the back channel surfaces of a-IGZO thin films.
(Invited) Transparent Amorphous Oxide Semiconductors for System on Panel Applications
Authors: Liu Po-Tsun , Chu Li-Wei , Teng Li-Feng , Fan Yang-Shun , Fuh Chur-Shyang
Published: March 2013

We demonstrate the applications of amorphous InGaZnO thin film transistor (a-IGZO TFT), extended from the pixel switcher/current driver, gate driver on array (GOA) to resistive random access memory (RRAM) technologies for system-on-panels (SoPs). The high-performance IGZO TFT with mobility of 13.5 cm2/Vs is proposed by microwave annealing process at room temperature only for 100 sec. Furthermore, an integrated gate driver scheme with the a-IGZO TFT as backbone is demonstrated in comparison with the amorphous Si TFT backplane. The rise and fall time of a-IGZO gate driver circuits is shorter than that of a-Si TFT gate driver. In addition, the ASK demodulator with a-IGZO TFT is realized successfully, and potentially to be applied for the system of low-frequency RFID tag. The study on a-IGZO RRAM reveals excellent reliability including 1000 times DC sweep endurance, 104 pulse endurance, 104 s data retention with read disturb immunity. The flexibility of a-IGZO RRAM device is also examined for flexible electronics applications.
Stress Techniques and Mobility Enhancement in FinFET Architectures
Authors: Eneman Geert , Witters Liesbeth , Mitard Jerome , Hellings Geert , De Keersgieter An , Brunco David P. , Hikavyy Andriy , Vincent Benjamin , Simoen Eddy , Favia Paola , Bender Hugo , Veloso Anabela , Chiarella Thomas , Boccardi Guillaume , Kim Minsoo , Togo Mitsuhiro , Loo Roger , De Meyer Kristin , Horiguchi Naoto , Collaert Nadine , Thean Aaron
Published: March 2013

Novel device architectures offer improved scalability but come at the price of increased layout sensitivity and reduced effectiveness of stressors. This work focuses on stress effects in n-type FinFETs with gate-first or gate-last stacks, and relies mainly on TCAD results. On n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. CESL becomes very ineffective for layouts with narrow fin pitches with merged fins. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a mobility degradation is predicted. Si:C source/drain stressors are very effective and show similar width dependence as on planar FETs. Significant mobility enhancement is predicted both in isolated and tight-pitch fin configurations.
Understanding the Effects of Epitaxy Artifacts on SiGe HBT Performance through Detailed Process/Device Simulation
Authors: Camillo-Castillo Renata , Johnson J. B. , Liu Q.Z. , Cheng Peng , Adkisson James , Harame D. L.
Published: March 2013

Faceting at the periphery of the shallow trench isolation during SiGe epitaxial base growth and its influence on SiGe HBT collector-base capacitance are investigated utilizing Technology Computer Aided Design techniques. The simulations suggest peripheral diffusion of boron from the extrinsic base into the intrinsic device may be attributed to depletion of germanium and carbon on the faceted plane that drives the boron diffusion and contributes to the collector-base capacitance, Ccb. Increases in the angle of the facet relative to the {110} plane are shown to reduce Ccb. Moreover, a significant reduction in Ccb was observed with no faceting, suggesting that moving the facet away from the active silicon region was desirable for reducing this key parasitic capacitance. These results serve to highlight the role that faceting plays in extrinsic device parasitic capacitances and identifies a focus area for scaling the device capacitance.
(Invited) Implant Free SiGe-Quantum Well: From Device Concept To High-Performing pFETs
Authors: Mitard Jerome , Eneman Geert , Hellings Geert , Witters Liesbeth , Hikavyy Andriy , Vincent Benjamin , Loo Roger , Bender Hugo , Horiguchi Naoto , Collaert Nadine , Thean Aaron
Published: March 2013

In this work, three important processing steps controlling the performance of SiGe-channel Implant Free Quantum Well pFETs are presented: the thermal budget, the source/drain SiGe stressors and the narrow width effect. In the first part, it is demonstrated that the thermal budget applied on these devices needs to remain low enough to avoid channel relaxation, especially when Si1-xGex -channel with x>0.45 is considered. Second, both raised or embedded SiGe source/drain uni-axially strain the SiGe channel which highly contributes to the final device performance. Outlook for ultra-scaled SiGe-channel IFQW pFETs is also given. Last but not least, SiGe-channel has an inherent strain booster which is the narrow width effect. The latter is fully explained through experimental and simulation data. Controlling all the three aforementioned parameters allows the demonstration of a 1.5mA/um ION at 100nA/um IOFF SiGe-pFET which is in line with the best results seen from the literature.
Hole Mobility Boost of Ge p-MOSFETs by Composite Uniaxial Stress and Biaxial Strain
Authors: Lan H.-S. , Chen Y. -T. , Lin J. -Y. , Liu C. W.
Published: March 2013

The hole mobility of relaxed Ge channel, and strained Ge channel on relaxed Si0.6Ge0.4 substrate were simulated and compared to our experimental work (Al2O3/GeO2 gate stack) and previous data. The rougher interface at GeO2/Ge than SiO2/Si makes a faster roll-off of Ge hole mobility at high field. For SiO2/Ge interface, the Ge hole mobility has a similar roll-off as Si universal mobility. Ge has higher mobility enhancement than Si under uniaxial compressive stress along [110] direction. For composite uniaxial compressive stress (-3GPa) and biaxial compressive strain (2.4%) on Ge p-MOSFETs, Ge mobility enhancement can reach as high as 23 times of Si mobility. The mass reduction of Ge is mainly responsible for the mobility enhancement.
Physical Mechanism of Enhanced Uniaxial Stress Effect on Carrier Mobility in ETSOI MOSFETs
Authors: Ohashi Teruyuki , Oda Shunri , Uchida Ken
Published: March 2013

This paper presents the comprehensive study of strain effect on carrier mobility in ETSOI MOSFETs. We firstly demonstrate that the mobility enhancement ratio increases as SOI thickness (TSOI) decreases from 60 nm to 4 nm by applying the uniaxial <110> tensile stress parallel to the channel. On the other hand, by applying the uniaxial <110> tensile stress perpendicular to the channel, mobility enhancement ratio does not necessarily increase as TSOI decreases. We discuss this result in terms of deformation potential (Dac) and effective mass (m*).
(Invited) Gate Stack and Source/Drain Junction Formations for High-Mobility Ge MOSFETs
Authors: Nakashima Hiroshi , Yamamoto Keisuke , Yang Haigui , Wang Dong
Published: March 2013

Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS, high-quality gate-stack and source/drain (S/D) junction formations are essential. We fabricated Ge n- and p-MOSFETs using the gate-stack formation by bilayer (SiO2/GeO2) passivation and using S/D junction formations by thermal diffusion of P and ion implantation of B. The electron and hole channel mobilities of the fabricated MOSFETs were 1097 and 376 cm2V-1s-1, respectively, despite the very thin GeO2 thickness. We will present the detailed fabrication method and device performance.
Thermally Stable NiSi2 for Ge Contact with Schottky Barrier Height Modulation Capability
Authors: Yoshihara Ryo , Tamura Yuta , Kakushima Kuniyuki , Ahmet Parhat , Kataoka Yoshinori , Nishiyama Akira , Sugii Nobuyuki , Tsutsui Kazuo , Natori Kenji , Hattori Takeo , Iwai H.
Published: March 2013

Agglomeration resistant contact of NiSi2 with Ge substrates has been performed using stacked silicidation process. Stable Schottky barrier height at NiSi2/Ge interface with ideality factor of less than 1.2 can be maintained up to annealing temperature of 500 oC. Incorporation of P atom at NiSi2/Ge interface modulates the Schottky barrier height to produce Ohmic contact.
Heteroepitaxy of III-V Compound Semiconductors on Silicon for Logic Applications: Selective Area Epitaxy in Shallow Trench Isolation Structures vs. Direct Epitaxy Mediated by Strain Relaxed Buffers
Authors: Cantoro Mirco , Merckling Clement , Jiang Sijia , Guo Weiming , Waldron Niamh , Bender Hugo , Moussa Alain , Douhard Bastien , Vandervorst Wilfried , Heyns Marc M. , Dekoster Johan , Loo Roger , Caymax Matty
Published: March 2013

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.
(Invited) Electrically Pumped Lasing from Ge-on-Si
Authors: Michel Jurgen
Published: March 2013

Electrically pumped lasing has been demonstrated from highly n-type Ge monolithically integrated with Si in a CMOS compatible process. The optical power of the laser was above 7mW with an optical gain of about 1000 cm-1.
Optical Characterization of Ge-on-Si Grown by using RTCVD
Authors: Kim Taek Sung , Kil Yeon-Ho , Hong Woong-Ki , Yang Hyeon Deok , Kang Sukill , Jeong Tae Soo , Shim Kyu-Hwan
Published: March 2013

We have investigated the characterization of Ge-on-Si Grown by using RTCVD. From the HR-XRD analysis, the Ge epi-layer shows good crystalline homogeneity and the lattice parameter of the Ge layer along the growth direction was calculated as 5.654 Å, indicating the compressive strain of 0.07%. The Ge peak Raman shift for each sample indicates compressive strain from the bulk Ge reference. The roll-off in photocurrent after 1600 nm is expected due to the decreased absorption of Ge.
Effects of HCl on the Growth of Epitaxial Ge
Authors: França Daniel L.
Published: March 2013

The goal of the work is to understand and optimize growth conditions to effectively grow Ge in oxide trenches, using HCl as an agent to control selectivity, growth rate, and growth profile. The intention is to selectively grow the Ge to an overfilled level, while controlling and optimizing vertical and lateral overgrowth.
High Quality Silicon Cap Layer for 28nm and Beyond PMOS Processes
Authors: Liao Chin I. , Hsuan Teng Chun , Chien Chin Cheng , Chan Michael , Yang Chan Lon , Wu J. Y. , Ramachandran Balasubramanian
Published: March 2013

High quality embedded SiGe film with [Ge] concentration > 35% with Epitaxial grown Silicon (Si) cap layer has been demonstrated on a state-of-the-art 28nm logic flow. Si cap layer is a significant benefit to SiGe device for p-MOSFET contact resistance improvement but adversely affects the SiGe film strain relaxation especially for the high concentration [Ge] (> 35%). High quality, relaxation free SiGe film, with surface roughness improved from 4.21 to 0.65nm and 30% device contact resistance reduction are characterized in this work.
Ge-on-Si: Single-Crystal Selective Epitaxial Growth in a CVD Reactor
Authors: Sammak Amir , de Boer Wiebe , Nanver Lis K.
Published: March 2013

A standard Si/SiGe ASM CVD reactor that was recently modified for merging GaAs and Si epitaxial growth in one system is utilized to achieve intrinsic and doped epitaxial Ge-on-Si with low threading dislocation and defect densities. For this purpose, the system is equipped with 2% diluted GeH4 as the main precursor gas for Ge deposition; and 0.7% diluted AsH3 and B2H6 precursor gases as well as a TriMethylGallium (TMGa) bubbler system for As, B and Ga doping of epitaxial Ge, respectively. The quality of Ge epitaxy on Si is investigated by plan-view and cross-sectional transmission electron-microscopy (TEM) and atomic-force microscopy (AFM) analysis.
Strain Engineering in GeSnSi Materials
Authors: Radamson Henry H. , Noroozi Mohammad , Jamshidi Asghar , Thompson Phillip E. , Östling Mikael
Published: March 2013

In this study, Ge1-x-ySnxSiy layers (0.01{less than or equal to}x{less than or equal to} 0.06 and 0{less than or equal to}y{less than or equal to}0.12) using Ge2H6, SnCl4 (SnD4) and Si2H6 have successfully grown at 290-310 {degree sign}C on Ge virtual layer on Si(100) by using RPCVD technique. It has been demonstrated that the quality of epitaxial layers is dependent on the growth parameters, layer thickness and the quality of Ge virtual layer. The incorporation of P and B in GeSn matrix has been studied and the effect of dopant specie and concentration on Sn content has been presented. It was found that a proper balance of P, B or Si and Sn flux during the epitaxy improves the incorporation of Sn in Ge matrix. This is explained by the compensation of tensile strain induced by dopants or Si with the compressive strain caused by Sn to obtain the minimum energy in Ge matrix. P-i-n type doped structures of Ge-Sn-Si were grown and the layer quality was analyzed.
(Invited) Spin Coherence in Si and Applications to Quantum Information Processing
Authors: Lyon Stephen A. , Tyryshkin Alexei M. , He Jianhua , Jock Ryan M.
Published: March 2013

While Si and Si-based materials have dominated classical electronic device technology for 50 years, quantum information processing requires very different types of devices. Silicon has also been found to be an ideal host for long-coherence quantum bits, or qubits, which are based upon the spins of electrons. The spins of electrons bound to donor impurities in isotopically enriched 28Si have been shown to have coherence times of 10 seconds or longer, at least three orders of magnitude longer than in any other solid. Considerable progress also is being made in understanding decoherence processes and extending coherence times for electrons at hetero-interfaces and in quantum dots.
A Design Scheme for Topological Insulators based Bonds, Bands, Symmetry and Spin Orbit Coupling
Authors: Felser Claudia , Müchler Lukas , Chadov Stanislav , Fecher G. H. , Yan B. , Kübler J. , Zhang Haijun , Zhang Shou Cheng
Published: March 2013

We report about a design scheme for topological insulators from the viewpoint of materials science or solid state chemistry. Topological insulators are a nice example for theory guided materials research. The electronic structure can be translated into the language of chemistry. The symmetry of the crystal- and the band structure, orbitals and spin orbit coupling determine whether a semiconductor is topologic or trivial. In this paper we will discuss the necessary and sufficient conditions for new TI materials, based in symmetry and bonding arguments.
(Invited) Electron Transport and Strain Mapping in Ge-SixGe1-x Core-Shell Nanowire Heterostructres
Authors: Dillen David C , Nah Junghyo , Varahramyan Kamran M. , Banerjee Sanjay K. , Tutuc Emanuel
Published: March 2013

We study the role of the structural parameters of Ge-SixGe1-x core-shell nanowires, namely shell thickness and composition, on the strain and transport properties of the heterostructure. Using Raman spectroscopy in combination with lattice dynamical theory, we measure the core strain in such a NW heterostructure. We show that the measured strain increases with decreasing the core/shell thickness ratio. Using Ge-SixGe1-x core-shell nanowire heterostructures with different shell content, we investigate the effect of carrier confinement on mobility, and show that the hole mobility is markedly higher in Ge-SixGe1-x core-shell nanowires with a high Si shell content.
Liquid-Phase Deposition of Thin Si and Ge Films Based on Ballistic Electro-reduction
Authors: Ohta Toshiyuki , Mentek Romain , Gelloz Bernard , Mori Nobuya , Koshida Nobuyoshi
Published: March 2013

An alternative wet process for depositing thin Si and Ge films is presented based on the ballistic electron injection into solutions. A nanocrystalline silicon (nc-Si) diode, composed of a thin Au (10 nm), nc-Si layer (~1 µm), polycrystalline silicon, and n+-Si substrate, operates as a surface-emitting active cold cathode in solutions. When driven alone in SiCl4 and GeCl4 solutions without using any counter electrodes, quasi-ballistic electrons generated in the nc-Si layer and ejected from the outer surface directly reduce Si and Ge ions followed by the deposition of thin amorphous Si4+ and Ge4+ films on the emitting surface with neither byproducts nor contaminations. Based on the structural and compositional characterizations of deposited Si and Ge films, the specific features of this deposition mode are discussed in comparison with the conventional dry process.
Modeling Two Dimensional Solid Phase Epitaxial Growth for Patterned Ge Substrates
Authors: Darby Blake L , Yates Bradley R , Kumar Ashish , Kontos Alex , Elliman Robert G. , Jones Kevin S
Published: March 2013

Modeling the two-dimensional (2D)c solid phase epitaxial growth (SPEG) of amorphized Ge has become important due to the renewed interest in Ge as an alternative material in complementary metal-oxide-semiconductor (CMOS) devices. No one has modeled the two-dimensional 2D SPEG of amorphized Ge. In this work, a 2D SPEG model that uses level set techniques as implemented in the Florida object oriented process simulator (FLOOPS) to propagate regrowth fronts with variable crystallographic orientation patterned material is presented. Apart from the inherent orientation dependence of the SPEG velocity, it is established that nitride induced stress can affect mask edge defect formation for patterned samples. Data acquired from TEM experiments matches well with simulations, thus providing a stable model for simulating 2D regrowth and mask edge defect formation in Ge.
(Invited) Germanium/Silicon Heterostructures for Terahertz Emission
Authors: Kelsall Robert W , Dinh Viet Thanh , Ivanov Pavlo , Valavanis Alex , Lever Leon J.M. , Ikonic Zoran , Velha Philippe , Dumas Derek , Gallacher Kevin Francis , Paul Douglas J , Halpin John , Myrnov Maksym , Leadley David R
Published: March 2013

Progress towards Si/Ge terahertz quantum cascade lasers is reviewed, and the relative merits of different Si/Ge materials configurations for such lasers are compared. The prospects for Ge-based quantum cascade lasers are discussed, and supported by simulation work for realistic laser designs. Experimental progress and challenges are assessed.
Fabrication of Ge-on-Si Substrates for the Integration of High-Quality GaAs Nanostructures on Si
Authors: Bietti Sergio , Cecchi Stefano , Frigeri Cesare , Grilli Emanuele , Fedorov Alexey , Vinattieri Anna , Gurioli Massimo , Isella Giovanni , Sanguinetti Stefano
Published: March 2013

Ge-on-Si substrates, made by a thin Ge relaxed layer with a low threading dislocation density and reduced surface roughness deposited on Si, are capable of accommodating the mismatch between GaAs and Si substrate and can be used for the growth of high quality AlGaAs/GaAs layers and of GaAs nanostructures by droplet epitaxy, while maintaining a low thermal budget compatible with the integration of CMOS devices.
Channel Strain Evolution of Recessed Source/Drain Si1-xCx Structures by Modifying Scaling Factors
Authors: Kim Sun-Wook , Byeon Dae-Seop , Jung Mijin , Ko Dae-Hong , Chopra Saurabh , Kim Yihwan , Lee Hoo-Jeong
Published: March 2013

We experimentally evaluated the effects of scaling on the channel strain in terms of scaling factors in recessed source/drain Si1-xCx structures. Epitaxial Si1-xCx films were deposited on recessed source/drain structures using a selective epitaxial growth process combined with reduced pressure chemical vapor deposition. Based on nano beam diffraction analyses and device simulation, it showed that the major transistor dimensions (gate length, source/ drain length, and the raised source/ drain height) influenced the channel strain: the channel strain increased with the gate length decreasing, and the raised height increasing, while declining with the reduction of the source/ drain length.
(Invited) Optical Spin Orientation in SiGe Heterostructures
Authors: Isella Giovanni , Bottegoni Federico , Cecchi Stefano , Ferrari Alberto , Ciccacci Franco , Pezzoli Fabio , Giorgioni Anna , Gatti Eleonora , Grilli Emanuele , Guzzi Mario , Lange Christoph , Köster Niko S. , Woscholski Ronja , Chatterjee Sangam , Trivedi Dhara , Li Pengki , Song Yang , Dery Hanan
Published: March 2013

Ge is emerging as an interesting material for spintronic applications. We demonstrate that in SiGe heterostructures strain and quantum confinement effects can be used to tailor spin related properties enhancing the spin polarization of injected carriers above the bulk limit. Moreover the fast Γ-L electron scattering and the strain induced removal of the heavy-hole, light-hole degeneracy, make SiGe heterostructures an ideal material platform for the study of hole dynamics.
Enhancement-Mode Buried Strained Silicon Channel Double Quantum Dot with Integrated Electrometer
Authors: Lu Tzu-Ming , Bishop Nathan , Pluym Tammy , Kotula Paul , Lilly Mike , Carroll Malcolm
Published: March 2013

We proposed and demonstrated an enhancement-mode SiGe/strained-Si stack for a quantum dot [1], which both spaces the quantum dot away from interface defects and removes dopants. Smooth and predictable potentials for single electron quantum dots are highly desirable for beyond Moore's law approaches like quantum annealing and quantum computing. Enhancement-mode SiGe/sSi field-effect transistors (FETs) have been demonstrated previously [2,3] and have recently achieved mobilities as high as 1.6x106 cm2/V s [4], indicating that a smooth potential approaching other model systems like GaAs can be produced in Si. This material stack has subsequently been used successfully by a different group to produce coherent qubit spin rotations [5]. We report in this letter that low-disorder quantum dots can be formed using a double-top-gated lateral quantum dot nanostructure, defined using 180 nm line width platform and fabricated in a 150 mm wafer batch-processing tool set in the Sandia National Labs silicon foundry. This is an important step towards showing that defects, lithography and process tolerances in a Si foundry are sufficient to build low disorder double quantum dots for both quantum computing and quantum annealing.
Local Quantity Analysis of Nanosize Electronics and Spintronics Material
Authors: Senami Masato , Tachibana Akitomo
Published: March 2013

New analysis method using novel local quantities is introduced for the purpose of the analysis of nanosize materials in microscopic viewpoints. The importance and availability of these quantities are discussed for particularly two types of quantities. First one is the polarizability and dielectric constant density tensors. By these quantities, the linear response to the electric field is investigated in atomic viewpoints. This approach is suitable for the analysis of nanomaterials, such as high-k thin film, particularly, in viewpoints of the study of the effects of defects and interfaces. Second one is the spin toque and the zeta force. These quantities clarify the local dynamics of the electron spin. Hence, this quantity is useful for a field of spintronics.
Tin Deuteride (SnD4) Stabilization
Authors: Spohn Ronald F. , Richenberg Carl B.
Published: March 2013

We evaluated six different cylinder passivation procedures to increase the room temperature stability of gaseous tin deuteride (SnD4). Two were successful in extending the lifetime of a 1% SnD4 mixture in hydrogen at 50 PSIA for more than six months. Higher concentrations and/or higher total pressure reduced the lifetime.
SiGe Band-to-Band Tunneling Calibration based on p-i-n Diodes: Fabrication, Measurement and Simulation
Authors: Kao Kuo-Hsing , Verhulst Anne , Rooyackers Rita , Hikavyy Andriy , Simoen Eddy , Arstila Kai , Douhard Bastien , Loo Roger , Simoen Alexey Milenin , Tolle John , Dekkers Harold , Machkaoutsan Vladimir , Maes Jan , De Meyer Kristin , Collaert Nadine , Heyns Marc , Huyghebaert Cedirc , Thean Aaron
Published: March 2013

For the purpose of calibrating the nonlocal Kane band-to-band tunneling model for Si1-xGex based on TCAD simulations, SiGe p-i-n tunnel diodes are fabricated by epitaxial growth. The quality of the tunnel junction is examined by the ideality factors of the diodes and the band-to-band tunneling regime is determined based on activation energy extractions. By comparing experimental data to simulations with theoretically calculated prefactors of Kane's model, we conclude that the TCAD simulator overestimates the tunneling current in strained Si1-xGex diodes.
Si/SiGe Tunneling Static Random Access Memories
Authors: Ternent Gary , Paul Douglas J
Published: March 2013

One of the limits to the low power operation of MOSFET devices is the minimum subthreshold slope defined by the p-n junctions in the devices. A tunneling static random access memory is demonstrated with a supply voltage of 0.42 V, well below the minimum supply voltage that MOSFET technology is capable of delivering. The memory is produced using two Si/SiGe resonant tunneling diodes with peak voltages of 0.175 V fabricated on top of a silicon substrate.
(Invited) Heterogeneous Integration of InP HBTs on CMOS: Leveraging and Providing Value to Conventional Silicon Technologies
Authors: Li James Chingwei , Royter Yakov , Patterson Pamela , Hussain Tahir , Duvall Janna R. , Montes Mary C. , Valles Irma , Ku Fiona , Boag-O'Brien Margaret F. , Lopez Aurelio , Le Dustin , Zehnder Daniel , Kim Samual , Chen Steven T.W. , Oh Thomas , Akmal Moonmoon , Wang Eason F. , Hitko Donald A. , Sokolich Marko , Chow David H. , Brewer Peter D. , Elliott Kenneth R.
Published: March 2013

Historically, compound semiconductors have enjoyed the benefit of material properties that lend themselves to high performance electron devices, but the ability to fabricate complex, high transistor count ICs is limited by the relative immaturity of the material system and small commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. However, a large commercial market has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both compound semiconductors and silicon based CMOS/BiCMOS to enable a new class of high performance ICs. This work will review HRL's efforts in wafer scale integration of an advanced 250nm, 350GHz fT/fMAX InP DHBT technology with RF-CMOS technologies whose device proximity; heterogeneous interconnect density; and additional technology features both leverage and provide additional value to conventional silicon technologies.
Low Specific Ohmic Contacts to n-type Germanium Using a Low Temperature NiGe Process
Authors: Gallacher Kevin Francis , Velha Philippe , Paul Douglas J , Maclaren Ian , Myronov Maksym , Leadly David R.
Published: March 2013

A new n-Ge Ohmic contact scheme is demonstrated using a three stage deposition of Ni, Ge and Ni. The lowest specific contact resistivity demonstrated was (1.68 +/- 0.4) x 10^-7 Ω-cm^2, with a low transfer length of (0.95 +/- 0.12) for deposited Ni and Ge annealed at 340 oC for 30 s on n-Ge with a doping density of 3 x 10^19 cm-3.
Formation of 1.7-nm-thick-EOT Germanium Dioxide Film with a High-Quality Interface Using a Direct Neutral Beam Oxidation Process
Authors: Wada Akira , Zhang Rui , Takagi Shinichi , Samukawa Seiji
Published: March 2013

Germanium dioxide (GeO2) films with a high-quality interface were formed using a damage-free and low-temperature neutral beam oxidation (NBO) process. Combining the NBO process with hydrogen (H) radical native oxide removal treatment creates a high-quality GeO2/Ge interface (EOT = 1.7 nm) with an extremely low interface state density (Dit) of less than 1 × 1011 cm-2eV-1.
Investigation of the Crystallization of NiFe81/19 Depending on the Annealing Temperature
Authors: Wurz Marc C. , Shaganov Anton , Rissing Lutz , Filimonov Alexey , Vakhrushev Sergey
Published: March 2013

Soft magnetic materials are used in a multitude of applications in magnetic micro electro-mechanical systems (MEMS) such as microsensors or microactuators. The most commonly applied softmagnetic material for microsensor applications is permalloy with a composition of NiFe81/19. This paper investigates the magnetic material properties as a function of the film thickness and a subsequent temperature treatment. For this the magnetic properties are measured with a Vibrating Sample Magnetometer (VSM) and for the investigation of the crystallographic structure a diffractometer is used.
Electroplating of Cu/Sn Layers for Hermetic Encapsulation for Vacuum Applications
Authors: Rissing Lutz , Wurz Marc C. , Cvetković Srecko , Bach Friedrich-Wilhelm
Published: March 2013

To create a hermetic package the application of Cu and Sn is a suitable way. By using the eutectic phase of these two materials the bonding temperature can be limited by 300{degree sign}C, which is in the range for the most micro electro-mechanical systems (MEMS) applications. In this investigation Si chips are bonded using electroplated Cu on the one part and a stacked combination of sputter deposited Sn and electroplated Cu on the counterpart. For the characterization of the quality of the bond shear tests are carried out to find the optimum heights of the bonding material.
(Invited) SiGe Spintronics with Single-Crystalline Ferromagnetic Schottky-Tunnel Contacts
Authors: Hamaya Kohei , Yamada Shinya , Takemoto Gotaro , Masaki Kohei , Fujita Yuichi , Kasahara Kenji , Ando Yuichiro , Sawano Kentarou , Miyao Masanobu
Published: March 2013

We present two important technologies for silicon-germanium (SiGe) spintronics. First, we show high-quality epitaxial growth of bcc-type ferromagnetic alloys on Si or Ge with atomically controlled interfaces. Second, we establish electrical spin injection and detection across the high-quality interfaces in Si- or Ge-based devices. Combining these technologies with a metal-oxide-semiconductor field-effect transistor structure, we can demonstrate room-temperature detection of spin accumulation and control the magnitude of the spin signals. These novel and interesting results are expected to build the basis of a key technology toward developing next-generation SiGe spintronic devices.
Separation of Magnetic Nano Beads by Using Soft Magnetic Flux Concentrators
Authors: Kaiser Matthias , Chen Jue , Taptimthong Piriya , Rissing Lutz
Published: March 2013

Magnetic Nano Beads (MNBs) can be successfully manipulated not only in vitro but also in vivo by a magnetic field generated by a permanent magnet or an electromagnet. Nonetheless, the magnetic flux has to be concentrated in a well defined area for a precise positioning of the MNB. The idea is to collect the MNBs after a medical application in a defined area of the body using a soft magnetic flux concentrator. The collectible MNBs could be used for controlled drug delivery or marking of disease. Afterwards the MNBs could be removed from the body without any traces or residua. For this purpose the Institute for Micro Production Technology (IMPT) designed, fabricated and characterized soft magnet flux concentrators made of NiFe45/55 and NiFe81/19. This contribution describes the thin-film fabrication, characterization and the investigations carried out on the developed flux concentrator. The experiments were accomplished with a fluid containing dispensed MNBs.