bluuebunny/crossref_metadata_2025 huggingface dataset:
Herpes Simplex Virus 1 VP22 Regulates Translocation of Multiple Viral and Cellular Proteins and Promotes Neurovirulence
Authors: Tanaka Michiko , Kato Akihisa , Satoh Yuko , Ide Takahiro , Sagou Ken , Kimura Kayo , Hasegawa Hideki , Kawaguchi Yasushi
Published: February 2012

Herpes simplex virus 1 (HSV-1) protein VP22, encoded by the UL49 gene, is a major virion tegument protein. In the present study, we showed that VP22 was required for efficient redistribution of viral proteins VP16, VP26, ICP0, ICP4, and ICP27 and of cellular protein Hsc-70 to the cytoplasm of infected cells. We found that two dileucine motifs in VP22, at amino acids 235 and 236 and amino acids 251 and 252, were necessary for VP22 regulation of the proper cytoplasmic localization of these viral and cellular proteins. The dileucine motifs were also required for proper cytoplasmic localization of VP22 itself and for optimal expression of viral proteins VP16, VP22, ICP0, UL41, and glycoprotein B. Interestingly, a recombinant mutant virus with alanines substituted for the dileucines at amino acids 251 and 252 had a 50% lethal dose (LD
50
) for neurovirulence in mice following intracerebral inoculation about 10
3
-fold lower than the LD
50
of the repaired virus. Furthermore, the replication and spread of this mutant virus in the brains of mice following intracerebral inoculation were significantly impaired relative to those of the repaired virus. The ability of VP22 to regulate the localization and expression of various viral and cellular proteins, as shown in this study, was correlated with an increase in viral replication and neurovirulence in the experimental murine model. Thus, HSV-1 VP22 is a significant neurovirulence factor
in vivo
.
The Peru Urban versus Rural Asthma (PURA) Study: methods and baseline quality control data from a cross-sectional investigation into the prevalence, severity, genetics, immunology and environmental factors affecting asthma in adolescence in Peru
Authors: Robinson Colin L , Baumann Lauren M , Gilman Robert H , Romero Karina , Combe Juan Manuel , Cabrera Lilia , Hansel Nadia N , Barnes Kathleen , Gonzalvez Guillermo , Wise Robert A , Breysse Patrick N , Checkley William
Published: February 2012

Objectives

According to a large-scale international survey, Peru has one of the highest prevalences of asthma worldwide; however, data from this survey were limited to participants from urban Lima. The authors sought to characterise the epidemiology of asthma in Peru in two regions with disparate degrees of urbanisation. In this manuscript, the authors summarise the study design and implementation.

Design

A cross-sectional study.

Participants

Using census data of 13–15-year-old adolescents from two communities in Peru, the authors invited a random sample of participants in Lima (n=725) and all adolescents in Tumbes (n=716) to participate in our study.

Primary and secondary outcome measures

The authors asked participants to complete a questionnaire on asthma symptoms, environmental exposures and socio-demographics and to undergo spirometry before and after bronchodilator, skin allergy testing and exhaled nitric oxide testing. The authors obtained blood samples for haematocrit, total IgE levels, vitamin D levels and DNA in all participants and measured indoor particulate matter concentrations for 48 h in a random subset of 70–100 households at each site.

Results

Of 1851 eligible participants, 1441 (78%) were enrolled and 1159 (80% of enrolled) completed all physical tests. 1283 (89%) performed spirometry according to standard guidelines, of which 86% of prebronchodilator tests and 92% of postbronchodilator tests were acceptable and reproducible. 92% of allergy skin tests had an adequate negative control. The authors collected blood from 1146 participants (79%) and saliva samples from 148 participants (9%). Overall amounts of DNA obtained from blood or saliva were 25.8 μg, with a 260/280 ratio of 1.86.

Conclusions

This study will contribute to the characterisation of a variety of risk factors for asthma, including urbanisation, total IgE levels, vitamin D levels and candidate genes, in a resource-poor setting. The authors present data to support high quality of survey, allergic, spirometric and genetic data collected in our study.
Minocycline and aspirin in the treatment of bipolar depression: a protocol for a proof-of-concept, randomised, double-blind, placebo-controlled, 2×2 clinical trial
Authors: Savitz Jonathan , Preskorn Sheldon , Teague T Kent , Drevets Douglas , Yates William , Drevets Wayne
Published: February 2012

Introduction

New medication classes are needed to improve treatment effectiveness in the depressed phase of bipolar disorder (BD). Extant evidence suggests that BD is characterised by neural changes such as dendritic remodelling and glial and neuronal cell loss. These changes have been hypothesised to result from chronic inflammation. The principal aims of the proposed research is to evaluate the antidepressant efficacy in bipolar depression of minocycline, a drug with neuroprotective and immune-modulating properties, and of aspirin, at doses expected to selectively inhibit cyclooxygenase 1 (COX-1).

Methods and analysis

120 outpatients between 18 and 55 years of age, who meet DSM-IV-TR criteria for BD (type I or II) and for a current major depressive episode will be recruited to take part in a randomised, double-blind, placebo-controlled, parallel-group, proof-of-concept clinical trial following a 2×2 design. As adjuncts to existing treatment, subjects will be randomised to receive one of the four treatment combinations: placebo-minocycline plus placebo-aspirin, active-minocycline plus placebo-aspirin, placebo-minocycline plus active-aspirin or active-minocycline plus active-aspirin. The dose of minocycline and aspirin is 100 mg twice daily and 81 mg twice daily, respectively. Antidepressant response will be evaluated by assessing changes in the Montgomery–Asberg Depression Rating Scale scores between baseline and the end of the 6-week trial. As secondary outcome measures, the anti-inflammatory effects of minocycline and aspirin will be tested by measuring pre-treatment and post-treatment levels of C reactive protein and inflammatory cytokines.

Ethics and dissemination

Minocycline has been widely used as an antibiotic in doses up to 400 mg/day. Low-dose aspirin has been safely used on a worldwide scale for its role as an antithrombotic and thrombolytic. The study progress will be overseen by a Data, Safety and Monitoring Board, which will meet once every 6 months. Results of the study will be published in peer-reviewed publications.

Trial registration number

Clinical Trials.gov:NCT01429272.
Potential role of urinary angiotensinogen in predicting antiproteinuric effects of angiotensin receptor blocker in non-diabetic chronic kidney disease patients: a preliminary report
Authors: Jang Hye Ryoun , Lee Yu-Ji , Kim Sung Rok , Kim Sung Gyun , Jang Eun Hee , Lee Jung Eun , Huh Wooseong , Kim Yoon-Goo
Published: February 2012

Objectives

Many chronic kidney disease (CKD) patients have persistent overt proteinuria despite angiotensin receptor blocker (ARB) treatment. This study investigated whether the initial difference in intrarenal renin–angiotensin system activity measured with urinary angiotensinogen would affect the antiproteinuric effects of ARB.

Methods

Between September 2005 and September 2008, in 50 non-diabetic proteinuric CKD patients not taking renin–angiotensin system inhibitors, the urinary protein/creatinine ratio (P/Cr), angiotensinogen/creatinine ratio (AGT/Cr), plasma renin and aldosterone were measured before starting valsartan, and were followed for 18 months.

Results

Patients were divided into three groups according to their initial urinary AGT/Cr. The urinary P/Cr was lower in the low angiotensinogen group, but similar in the high and extremely high angiotensinogen groups (1.3±0.38 vs 2.0±0.92 vs 2.2±0.78). In all groups, the urinary P/Cr was decreased most for the first 6 months. The urinary P/Cr reduction at 6 months was greatest in the high angiotensinogen group (−24.2% vs −46.2% vs −16.4%). The urinary AGT/Cr was decreased most in the high angiotensinogen group. Renal functional deterioration was attenuated in the high angiotensinogen group compared with the extremely high angiotensinogen group.

Conclusions

The antiproteinuric effects of ARB were different according to the initial urinary angiotensinogen levels. These results suggest the potential value of the initial urinary AGT/Cr for predicting the therapeutic effect of ARB in proteinuric non-diabetic CKD patients.
Provenance variations in northern Appalachian Avalonia based on detrital zircon age patterns in Ediacaran and Cambrian sedimentary rocks, New Brunswick and Nova Scotia, Canada
Authors: Barr S.M. , Hamilton M.A. , Samson S.D. , Satkoski A.M. , White C.E.
Published: February 2012

Avalonia in the northern Appalachian orogen is generally assumed to have originated near the margin of Gondwana, although its position along that extensive margin and the timing of its separation remain disputed. U–Pb ages determined by laser ablation – inductively coupled plasma – mass spectrometry are reported here for detrital zircon from Avalonian clastic sedimentary units, three in southern New Brunswick, and one in southeastern Cape Breton Island, with depositional ages ranging from ca. 630 to ca. 505 Ma. Considered in combination with previously published detrital data sets from two other samples from southern New Brunswick deposited in a similar age range, the samples show a wide spectrum of ages from Ediacaran to Neoarchean (as old as 3.2 Ga). The dominant zircon populations in all six samples are Ediacaran–Cryogenian with ages between 770 and 540 Ma and can be matched with known magmatic events in Avalonia. Pre-Avalonian cycle detrital zircon dates in the samples are relatively sparse and do not reveal a consistent signature that might be used to place Avalonia in a unique paleogeographic position, although they are compatible with Amazonian provenance. An increase in ca. 2.2–1.9 Ga zircon dates in Early Cambrian through Early Ordovician samples suggests that sources for zircon of those ages became available in Avalonia by the end of the Ediacaran, possibly by motion of Avalonia to a different part of the Amazonian margin or to the West African craton.
POTTS MODEL WITH INVISIBLE COLORS: RANDOM-CLUSTER REPRESENTATION AND PIROGOV–SINAI ANALYSIS
Authors: VAN ENTER AERNOUT C. D. , IACOBELLI GIULIO , TAATI SIAMAK
Published: February 2012

We study a variant of the ferromagnetic Potts model, recently introduced by Tamura, Tanaka and Kawashima, consisting of a ferromagnetic interaction among q "visible" colors along with the presence of r non-interacting "invisible" colors. We introduce a random-cluster representation for the model, for which we prove the existence of a first-order transition for any q > 0, as long as r is large enough. When q > 1, the low-temperature regime displays a q-fold symmetry breaking. The proof involves a Pirogov–Sinai analysis applied to this random-cluster representation of the model.
MODELING OF INTERNET INFLUENCE ON GROUP EMOTION
Authors: CZAPLICKA AGNIESZKA , HOŁYST JANUSZ A.
Published: February 2012

Long-range interactions are introduced to a two-dimensional model of agents with time-dependent internal variables ei = 0, ±1 corresponding to valencies of agent emotions. Effects of spontaneous emotion emergence and emotional relaxation processes are taken into account. The valence of agent i depends on valencies of its four nearest neighbors but it is also influenced by long-range interactions corresponding to social relations developed for example by Internet contacts to a randomly chosen community. Two types of such interactions are considered. In the first model the community emotional influence depends only on the sign of its temporary emotion. When the coupling parameter approaches a critical value a phase transition takes place and as result for larger coupling constants the mean group emotion of all agents is nonzero over long time periods. In the second model the community influence is proportional to magnitude of community average emotion. The ordered emotional phase was here observed for a narrow set of system parameters.
RECENT PROGRESS IN DOUBLE BETA DECAY
Authors: ELLIOTT STEVEN R.
Published: February 2012

At least one neutrino has a mass of about 50 meV or larger. However, the absolute mass scale for the neutrino remains unknown. Studies of double beta decay offer hope for determining the absolute mass scale. Furthermore, the critical question "Is the neutrino its own antiparticle?" is unanswered. In particular, zero-neutrino double beta decay (0 νββ) can address the issues of lepton number conservation, the particle–antiparticle nature of the neutrino, and its mass. A summary of the recent progress in 0 νββ, and the related technologies will be discussed in the context of the future 0 νββ program.
RARE DILEPTONIC DECAYS OF ΛbIN A QUARK MODEL
Authors: MOTT L. , ROBERTS W.
Published: February 2012

Hadronic form factors for the rare weak transitions Λb→ Λ(*)are calculated using a nonrelativistic quark model. The form factors are extracted in two ways. An analytic extraction using single-component wave functions (SCA) with the quark current being reduced to its nonrelativistic Pauli form is employed in the first method. In the second method, the form factors are extracted numerically using the full quark model wave function (MCN) with the full relativistic form of the quark current. Although there are differences between the two sets of form factors, both sets satisfy the relationships expected from the heavy quark effective theory (HQET). Differential decay rates, branching ratios (BRs) and forward–backward asymmetries (FBAs) are calculated for the dileptonic decays Λb→ Λ(*)ℓ+ℓ-, for transitions to both ground state and excited daughter baryons. Inclusion of the long distance contributions from charmonium resonances significantly enhances the decay rates. In the MCN model the Λ(1600) mode is the dominant mode in the μ channel when charmonium resonances are considered; the Λ(1520) mode is also found to have a comparable BR to that of the ground state in the μ channel.
CANONICAL TENSOR MODELS WITH LOCAL TIME
Authors: SASAKURA NAOKI
Published: February 2012

It is an intriguing question how local time can be introduced in the emergent picture of space–time. In this paper, this problem is discussed in the context of tensor models. To consistently incorporate local time into tensor models, a rank-three tensor model with first class constraints in Hamilton formalism is presented. In the limit of usual continuous spaces, the algebra of constraints reproduces that of general relativity in Hamilton formalism. While the momentum constraints can be realized rather easily by the symmetry of the tensor models, the form of the Hamiltonian constraints is strongly limited by the condition of the closure of the whole constraint algebra. Thus the Hamiltonian constraints have been determined on the assumption that they are local and at most cubic in canonical variables. The form of the Hamiltonian constraints has similarity with the Hamiltonian in the c < 1 string field theory, but it seems impossible to realize such a constraint algebras in the framework of vector or matrix models. Instead these models are rather useful as matter theories coupled with the tensor model. In this sense, a three-index tensor is the minimum-rank dynamical variable necessary to describe gravity in terms of tensor models.
THE STRONG COUPLING CONSTANTS gDs1D*K AND $g_{D_{s1}D^{*}K_0^{*}}$ IN QCD SUM RULES
Authors: GHAHRAMANY N. , KHOSRAVI R. , JANBAZI M.
Published: February 2012

The structure of the Ds1(2460) meson has not yet been exactly known in the quark model. Considering the Ds1 meson as a conventional [Formula: see text] meson, we investigate the strong form factors and coupling constants gDs1D*K and [Formula: see text] in the framework of the three point QCD sum rules. Any future experimental measurement on these form factors as well as coupling constants gDs1D*K and [Formula: see text] and their comparison with the obtained results in the present work can give considerable information about the structure of this meson.
THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs
Authors: KUMARI RITI , GOSWAMI MANISH , SINGH B. R.
Published: February 2012

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.
On the Interface Flattening Effect and Gate Insulator Breakdown Characteristic of Radical Reaction Based Insulator Formation Technology
Authors: Kuroda Rihito , Teramoto Akinobu , Li Xiang , Suwa Tomoyuki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: February 2012

Insulator/Si interface flattening effects and gate oxide breakdown characteristics are evaluated for the oxygen radical oxidation and the wet oxidation at 750 °C. The radical oxidation is confirmed to exhibit a superior flattening effect than the wet oxidation. To obtain atomically flat top surface and interface to Si for oxides, radical oxidation on atomically flattened surfaces is indispensable. When the oxides are formed by radical oxidation on conventional flat Si surfaces withRa≥0.12 nm, early breakdowns occur more frequently than wet oxides. These early breakdowns are eliminated when surfaces withRa≤0.06 nm are employed before oxidation. It is suggested that the early breakdowns occur at local spots that induce excess electric field due to the flattening of micro-roughness by the radical oxidation. To apply the radical reaction based insulator formation technology to the gate insulator formation, the surface before gate insulator formation must be sufficiently flattened.
Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors
Authors: Shin Hong-Sik , Oh Se-Kyung , Kang Min-Ho , Kwon Hyuk-Min , Oh Jungwoo , Majhi Prashant , Jammy Raj , Lee Ga-Won , Lee Hi-Deok
Published: February 2012

In this paper, the thermal stability of Ni-germanide is improved by utilizing Ni/Co/Ni/TiN structure for Ge metal–oxide–semiconductor field effect transistors (MOSFETs) technology. It was shown that the Ni/Co/Ni/TiN structure improved the thermal stability of Ni-germanide mainly due to the suppression of Ni diffusion, and/or the retardation of agglomeration. The incorporated Co atoms distributed, mainly in the top region of the Ni-germanide and it is believed that this Co-rich Ni-germanide layer in the upper region of Ni-germanide enhanced the thermal stability. Therefore, the proposed Ni/Co/Ni/TiN structure is promising for the formation of a highly thermally immune Ni-germanide for nanoscale Ge MOSFETs technology.
Evaluation of Anisotropic Strain Relaxation in Strained Silicon-on-Insulator Nanostructure by Oil-Immersion Raman Spectroscopy
Authors: Kosemura Daisuke , Tomita Motohiro , Usuda Koji , Ogura Atsushi
Published: February 2012

Precise stress measurements have been desired in order to apply strained Si substrates to next-generation transistors. Oil-immersion Raman spectroscopy enables the evaluation of the anisotropic stress state in the strained Si layer of the strained Si substrate even under (001)-oriented Si backscattering geometry. First, we found that the phonon deformation potentials (PDPs) reported by Anastassakis et al. in 1990 was the most valid among the three sets of PDP previous reported. Using these PDPs, the precise Raman measurements of biaxial stress in strained Si-on-insulator (SSOI) nanostructures were performed. The biaxial stresses σ
x
x
and σ
y
y
decreased with the decrease in SSOI width and length, which was consistent with the finite element method calculation.
Extremely Scaled (∼0.2 nm) Equivalent Oxide Thickness of Higher-k (k = 40) HfO2 Gate Stacks Prepared by Atomic Layer Deposition and Oxygen-Controlled Cap Post-Deposition Annealing
Authors: Morita Yukinori , Migita Shinji , Mizubayashi Wataru , Ota Hiroyuki
Published: February 2012

We fabricate ultrathin HfO2 gate stacks of very high permittivity by atomic layer deposition (ALD) and oxygen-controlled cap post-deposition annealing. The HfO2 layer is directly deposited on a wettability-controlled Si surface by ALD. To enhance permittivity, a cubic crystallographic phase is generated in ALD-HfO2 by short-time annealing with a Ti capping layer. The Ti layer absorbs residual oxygen in the HfO2 layer, which suppresses the growth of the interfacial SiO2 layer. The dielectric constant of ALD-HfO2 is increased to ∼40, and a gate stack of extremely scaled equivalent oxide thickness (∼0.2 nm) is obtained.
Suppressed Thermally Induced Flatband Voltage Instabilities with Binary Noble Metal Gated Metal–Oxide–Semiconductor Capacitors
Authors: Choi Changhwan , Ahn Jinho , Choi Rino
Published: February 2012

We investigated thermally induced flatband voltage (V
FB) instabilities with single noble metals (Pt, Ir, Pd), their binary metal (IrPt) and control TiN used for gate electrodes in metal oxide semiconductor devices with atomic layer deposited HfO2 gate dielectric. As-deposited e-beam evaporated noble metals and sputtered TiN gated devices show near band-edge p-type metal–oxide–semiconductor (pMOS) characteristics and higher V
FB than midgap value, respectively. After 450 °C at 30 min forming gas anneal, V
FB of devices with e-beam evaporated single metals and sputtered TiN is substantially shifted toward mid-gap position, indicating thermally induced V
FB instability. However, device with binary metal alloy gate shows suppressed V
FB shifts and work-function as high as 4.95 eV is attained with 450 °C at 30 min FGA. It can be explained by oxygen diffusion within gate stack structure into interfacial layer (IL) between Si and HfO2 during anneal, leading to thicker IL and vacancy generation in dielectric.
Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers
Authors: Kume Ippei , Inoue Naoya , Hijioka Ken'ichiro , Kawahara Jun , Takeda Kouichi , Furutake Naoya , Shirai Hiroki , Kazama Kenya , Kuwabara Shin'ichi , Watarai Msasatoshi , Sakoh Takashi , Takahashi Takafumi , Ogura Takashi , Taiji Toshiji , Kasama Yoshiko , Sakamoto Misato , Hane Masami , Hayashi Yoshihiro
Published: February 2012

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.
System-on-Package Platform with Thick Benzocyclobutene Layer for Millimeter-Wave Antenna Application
Authors: Jeon Namcheol , Kim Youngmin , Min Ilhong , Ryoo Yeon-mi , Seo Kwang-Seok
Published: February 2012

Integrated antennas operating at millimeter-wave (mm-wave) frequency have been implemented on a benzocyclobutene (BCB)-based system-on-package (SOP) substrate. A novel BCB-based SOP substrate with a Si bump and a Si cavity was proposed to increase the BCB thickness, thus enhancing the gain of the microstrip patch array antenna and reducing the transfer loss of the transmission line. The mechanical issues of adhesion and stress of BCB are studied. The adhesion between gold and BCB was improved significantly by the insertion of a layer of Si oxide (SiO2) by plasma-enhanced chemical vapor deposition (PECVD). SiO2can also reduce the wafer bow by stress compensation. Wafer bow of whole structure was decreased from 79.3 to 55.2 µm by the insertion of a 1-µm-thick SiO2layer. A series-fed 1 ×8 linear array antenna is impedance matched well at 77 GHz. The process flow including BCB chemical mechanical polishing (CMP) was described. The proposed SOP substrate can be a candidate for overcoming the constraint of BCB thickness.
New Performance Indicators of Metal–Oxide–Semiconductor Field-Effect Transistors for High-Frequency Power-Conscious Design
Authors: Katayama Kosuke , Fujishima Minoru
Published: February 2012

With the progress of complementary metal–oxide–semiconductor (CMOS) process technology, it is possible to apply CMOS devices to millimeter-wave amplifier design. However, the power consumption of the system becomes higher in proportion to its target frequency. Moreover, CMOS devices are biased at a point where the device achieves the highest gain and consumes much power. In order to reduce the power consumption without any compromise, we introduce two types of indicator. One works towards achieving the highest gain with the lowest power consumption. The other works towards achieving the highest linearity with consideration of the power consumption. In this work, we have shown the effectiveness of those indicators by applying measured data of the fabricated metal–oxide–semiconductor field-effect transistors (MOSFETs) to cascade common-source amplifiers.
Experimental Study of Silicon Monolayers for Future Extremely Thin Silicon-on-Insulator Devices: Phonon/Band Structures Modulation Due to Quantum Confinement Effects
Authors: Mizuno Tomohisa , Tobe Keisuke , Maruyama Yohichi , Sameshima Toshiyuki
Published: February 2012

We have experimentally studied Si monolayers, fabricated by thermal oxidation of silicon-on-insulator (SOI) substrates at high temperature, for future extremely thin SOI (ETSOI) complementary metal oxide semiconductor (CMOS) devices, and have shown the strong quantum confinement effects in the ETSOIs. We have successfully formed 0.52-nm Si monolayers, as confirmed by transmission electron microscopy (TEM) and a UV/visual reflection method. We have experimentally shown the asymmetric broadening and the peak downshift of the Raman peak of ETSOIs evaluated by UV-Raman spectroscopy, which is enhanced in the ETSOI thickness T
SOI of less than about 5 nm. These results are due to the quantum phonon confinement effects in ETSOIs. Using the TEM observation and UV-Raman spectroscopy of ETSOIs, we have also shown the tensile strain of ETSOIs due to the Si bending and the T
SOI variations in ETSOI substrates. In addition, we have observed photoluminescence (PL) from the ETSOIs with a T
SOI of less than about 5 nm and the PL intensity strongly depends on the T
SOI. However, the peak photon energy of about 1.85 eV in the PL spectrum is independent of the T
SOI. We cannot explain the PL results perfectly at present, but we have introduced a possible three-region model of electron/hole pair generation in a two-dimensional Si layer and electron/hole pair recombination at the Si/SiO2 interface state region.
Device Physics and Design of a L-Shaped Germanium Source Tunneling Transistor
Authors: Low Kain Lu , Zhan Chunlei , Han Genquan , Yang Yue , Goh Kian-Hui , Guo Pengfei , Toh Eng-Huat , Yeo Yee-Chia
Published: February 2012

A novel tunneling field-effect transistor (TFET) with an L-shaped Ge source is investigated. The device comprises a Ge source that extends underneath a Si-channel region and separated from the drain by an insulator (SiO2). By optimizing the overlap length of the extended source L
OV and the Si body thickness T
Si, the current due to vertical band-to-band tunneling (BTBT) of the Ge–Si hetero-junction could be increased significantly and is scalable with L
OV. This leads to higher I
ON and improved S. The SiO2 also reduces OFF-state current I
OFF by blocking leakage paths. With extensive simulation, the device physics and design guidelines of this novel structure are outlined.
Unified Reaction–Diffusion Model for Accurate Prediction of Negative Bias Temperature Instability Effect
Authors: Ma Chenyue , Mattausch Hans Jürgen , Miyake Masataka , Matsuzawa Kazuya , Iizuka Takahiro , Yamaguchi Seiichiro , Hoshida Teruhiko , Kinoshita Akinari , Arakawa Takahiko , He Jin , Miura-Mattausch Mitiko
Published: February 2012

In this study, we developed a unified reaction–diffusion (R–D) model for the negative bias temperature instability (NBTI) effect over a wide range of stress times. The newly developed model provides a physics-based uniform solution and overcomes the limitations of the classical R–D models that cannot describe both the short and the long term stress regions simultaneously. In our modeling framework, the chemical reaction between inversion channel carriers and Si–H bonds at the Si/SiO2 interface dominates the short-term NBTI effects at the beginning of the stress application. Then the H2 diffusion into the polycrystalline silicon (poly-Si) gate becomes responsible for long term stress degradation. Finally, the developed R–D model is implemented into the advanced metal oxide semiconductor field effect transistor (MOSFET) model HiSIM to enable accurate circuit-aging simulation. Simulation results for the current degradation and their comparison with measurements verify the achieved high accuracy and the practical applicability of the developed NBTI model.
Enhanced Degradation by Negative Bias Temperature Stress in Si Nanowire Transistor
Authors: Ota Kensuke , Saitoh Masumi , Tanaka Chika , Nakabayashi Yukio , Uchida Ken , Numata Toshinori
Published: February 2012

Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.
The Generation Process of Interface Traps by Hot-Carrier Injection in Nanoscale Metal–Oxide–Semiconductor Field-Effect Transistors
Authors: Hu Ming , Yamane Takuya , Tsuchiya Toshiaki
Published: February 2012

The generation process of interface traps by hot-carrier injection in nanoscale metal–oxide–semiconductor field-effect transistors (MOSFETs) was evaluated by the charge pumping (CP) method, and degradation of the threshold voltage by these interface traps was studied. The generation process is found to follow the conventional ΔI
cp∼t

n
relationship for a short period of stress and then shows a saturation behavior after longer stress times. The factors that determine the interface trap generation before and after saturation are analyzed. A new equation to describe the generation process is given.
Effect of La2O3 Capping Layer Thickness on Hot-Carrier Degradation of n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with High-k/Metal Gate Stacks
Authors: Kim Dongwoo , Lee Seonhaeng , Kim Cheolgyu , Oh Taekyung , Kang Bongkoo
Published: February 2012

The effect of La2O3 capping layer thickness on the hot-carrier degradation of n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with high-k/metal gate stacks is investigated. The hot-carrier degradation is monitored by measuring the threshold voltage V
th, transconductance g
m, and subthreshold slope SS. As the thickness of the La2O3 layer increases, V
th degradation is enhanced regardless of whether the La2O3 layer is deposited above or below the HfSiO layer. The generation of interface traps induced by hot-carrier stress is intensified with an increase in the bottom capping layer thickness. On the other hand, the generation of oxide traps induced by hot-carrier stress is intensified with an increase in the top capping layer thickness.
Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor
Authors: Lin Zer-Ming , Lin Horng-Chih , Liu Keng-Ming , Huang Tiao-Yuan
Published: February 2012

In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors.
Design Optimization of Back-Gated Thin-Body Silicon-on-Insulator Capacitorless Dynamic Random Access Memory Cell
Authors: Cho Min Hee , Shin Changhwan , Liu Tsu-Jae King
Published: February 2012

Highly scaled (22 nm-node) capacitorless single-transistor dynamic random access memory (DRAM) cell design is investigated via technology computer-aided design (TCAD) simulations. It is found that the gate-sidewall spacer width and operating voltages can be adjusted to reduce band-to-band tunneling (BTBT) and thereby increase data retention time for bipolar junction transistor (BJT)-based operation. Read current variations due to random dopant fluctuations (RDF) are investigated via three-dimensional Kinetic Monte Carlo (KMC) simulations. It is found that BJT-based operation is more robust to RDF effects than metal–oxide–semiconductor field-effect transistor (MOSFET)-based operation.
Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate
Authors: Seo Moon-Sik , Endoh Tetsuo
Published: February 2012

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the V
th distribution with interference and disturbance problems and V
th shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.
Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme
Authors: Higuchi Kazuhide , Miyaji Kousuke , Johguchi Koh , Takeuchi Ken
Published: February 2012

This paper proposes a verify-programming method for the resistive random access memory (ReRAM) cell which achieves a 50-times higher endurance and a fast set and reset compared with the conventional method. The proposed verify-programming method uses the incremental pulse width with turnback (IPWWT) for the reset and the incremental voltage with turnback (IVWT) for the set. With the combination of IPWWT reset and IVWT set, the endurance-cycle increases from 48 ×103 to 2444 ×103 cycles. Furthermore, the measured data retention-time after 20 ×103 set/reset cycles is estimated to be 10 years. Additionally, the filamentary based physical model is proposed to explain the set/reset failure mechanism with various set/reset pulse shapes. The reset pulse width and set voltage correspond to the width and length of the conductive-filament, respectively. Consequently, since the proposed IPWWT and IVWT recover set and reset failures of ReRAM cells, the endurance-cycles are improved.
Multi-Level Phase Change Memory Cells with SiN or Ta2O5Barrier Layers
Authors: Gyanathan Ashvini , Yeo Yee-Chia
Published: February 2012

This work compares the effects of SiN and Ta2O5barrier layers in a multi-level phase change random access memory (PCRAM) cell. The PCRAM cell comprises a phase change material stack between a top and a bottom electrode. The phase change material stack comprises a nitrogen-doped Ge2Sb2Te5(NGST) layer on top of a thin barrier layer on an undoped GST layer. The thermal conductivity and electrical resistivity of the barrier layer affect multi-level switching performance in terms of endurance as well as power consumption. Extensive electrical characterization was performed on these PCRAM multi-level devices. Thermal analysis was also performed to investigate the thermal efficiency of each barrier layer. It was observed that for a constant barrier layer thickness of 1.5 nm, the endurance of the multi-level device with the SiN barrier layer was better than that with the Ta2O5barrier layer; however, the multi-level device with the Ta2O5barrier layer had a lower power consumption than that with the SiN barrier layer.
Endurance Enhancement of Elevated-Confined Phase Change Random Access Memory
Authors: Hongxin Yang , Luping Shi , Koon Lee Hock , Rong Zhao , Chong Chong Tow
Published: February 2012

Phase change random access memory (PCRAM) is the most promising candidate for the next-generation nonvolatile memory. Recently, elevated-confined PCRAM using an elevated metal column was proposed as a promising approach to achieve lower RESET current. This paper studied the writing strategy to enhance the endurance of elevated-confined PCRAM through both experiment and simulation. Elevated-confined PCRAM incorporating Ge2Sb2Te5 were fabricated and tested. The overwriting test showed that the failure mode of elevated-confined PCRAM was stuck SET. As diffusion, which is the main reason for stuck SET, is highly dependent on working temperature, writing strategies are investigated to minimize the over-heating in elevated-confined PCRAM. From the simulation results, it is found that RESET pulse width is more effective than RESET pulse amplitude in controlling of over-heating. The testing results showed that the endurance cycles can be improved from 106 to 108 with shorter and lower RESET pulse, which is consisted with simulation results.
Simulation of Retention Behavior for the Phase Change Memory
Authors: Chen Jian , Song Decheng , Du Gang , Lian Guijun , Kang Jinfeng , Liu Xiaoyan
Published: February 2012

We developed a comprehensive simulation program of phase change memory (PCM) including the electrical, thermal, phase change and percolation model. The set, reset and retention behavior for a typical thin film phase change material (GST) are simulated and evaluated. Both the resistance evaluation and the micro phase change process are simulated that can help to understand of the phase change physical mechanism. The influence of pre-existing grains on the retention is evaluated considering the pre-existing grains' amount and its distribution.
Improved Near-Infrared Sensitivity with a Side-Illuminated Photosensor
Authors: Ariyoshi Tetsuya , Uryu Noriyuki , Baba Akiyoshi , Arima Yutaka
Published: February 2012

To improve the sensitivity of silicon photosensors to near-infrared light, we proposed a method in which the photosensor is illuminated from the side. That method allows the PN junction of the photodiode to be formed to a length that covers the entire depth of incident light penetration. The result is efficient collection of the photocharge produced by the injected light and improvement in quantum efficiency. We fabricated a 4.20 ×3.33 mm2 test chip using a 0.35-µm complementary metal oxide semiconductor (CMOS) 1-poly 3-metal process. Because side illumination is used, the side of the chip is etched by high-speed deep reactive ion etching (D-RIE). For a 150-µm-long photodiode, the quantum efficiency to 970-nm wavelength near-infrared light is 28 times as high as for a conventional device. It was confirmed that the effectiveness of the proposed method increases with the wavelength of the incident light.
A 220-nA 32-kHz Crystal Oscillator with Wide Voltage Range (1.0–5.5 V) for Battery-Operated Microcontrollers
Authors: Ozawa Osamu , Horiguchi Masashi , Okuda Yuichi , Ito Takayasu , Shibata Hisao , Hiraki Mitsuru
Published: February 2012

Most microcontrollers (MCUs) have a real-time clock function driven by a 32-kHz crystal oscillator. A low-power 32-kHz crystal oscillator for operation in battery-operated MCUs over a wide voltage range (1.0–5.5 V) is described. The circuit features a proportional to absolute temperature (PTAT) bias-current generator to ensure an oscillation margin and an adaptive comparator for detecting small oscillation signals with little effect from by process and temperature variations. Experimental results indicate that the circuit achieves a small operating current of only 220 nA while ensuring a 10-times oscillation margin with a low-C
L (3.1 pF) quartz crystal, providing sufficient noise tolerance and quick start-up. The duty cycle is 40–60% and start-up time is less than 0.6 s. This circuit is expected to realize the smallest MCU standby current of 420 nA.
High-Voltage-Tolerant Level Converter for Embedded Complementary Metal–Oxide–Semiconductor Nonvolatile Memories
Authors: Huang Chih Yang , Lin Hongchin
Published: February 2012

In this paper, a high-voltage-tolerant level converter for embedded complementary metal–oxide–semiconductor (CMOS) nonvolatile memories is proposed. The level converter circuit includes a high-voltage driver and a level shifter, which makes use of 1×V
DD devices to generate 2×V
DD signals without overstress. In addition, it features one select signal to make the level converter have the tri-state. The high-voltage driver efficiently stacks two transistors to allow a voltage drop of V
DD for each transistor, which helps maximize the driving ability. The level shifter using the cross-coupled structure with small metal–oxide–semiconductor (MOS) capacitors drives the high-voltage driver without the “preconditioning” process. The level converter implemented using the 0.35 µm CMOS process on the area of 0.002 mm2 was measured at V
DD = 3.5 V to generate the output signal swinging from 0 to 7 V.
Complementary Metal Oxide Semiconductor Operational Amplifier Offset Calibration Technique Using Closed Loop Offset Amplifier and Folded-Alternated Resistor String Digital-to-Analog Converter
Authors: Morimoto Hiroyuki , Goto Hiroaki , Fujiwara Hajime , Nakamura Kazuyuki
Published: February 2012

In this paper, we describe the development of a circuit system that enables the offset calibration of an operational amplifier (op-amp) circuit after production. A closed-loop feedback system was developed to realize high-speed and accurate offset calibration action. For the digital-to-analog converter (DAC) which occupies most of the area for the additional calibration circuit, the Folded-Alternated Resistor String DAC was developed. This reduced the area by more than 50% and realized low power consumption while maintaining the same accuracy as a conventional type of DAC. The fabrication with standard 0.35 µm complementary metal oxide semiconductor (CMOS), followed by actual measurement, has confirmed that the offset can be confined to no more than 1.5 mV using the new calibration circuit. With this technique, miniaturization of a whole op-amp system can be achieved, because the layout size of each circuit consisting of op-amps can be reduced when using this offset correction circuit.
Application of Sputtering-Deposited AlN Films to Gate Dielectric for AlGaN/GaN Metal–Insulator–Semiconductor Heterojunction Field-Effect Transistor
Authors: Shih Hong-An , Kudo Masahiro , Akabori Masashi , Suzuki Toshi-kazu
Published: February 2012

AlN films deposited by RF magnetron sputtering are applied to AlGaN/GaN metal–insulator–semiconductor heterostructure field-effect transistors (MIS-HFETs) as a gate dielectric. X-ray photoelectron spectroscopy (XPS) was used to characterize the AlN films, showing their chemical bonds and the bandgap by N 1s electron energy loss spectroscopy. The AlGaN/GaN MIS-HFET with a gate length of 150 nm was successfully fabricated, exhibiting low gate leakage currents for both reverse and forward biases, which are at least four orders of magnitude lower than those of reference Schottky-HFETs. Although these results support the possibility of sputtering-deposited AlN as a gate insulator, there are AlN/AlGaN interface states unfavorable for device performance, which were investigated by the frequency dispersion in the capacitance–voltage (C–V) characteristics.
In0.53Ga0.47As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Shallow Metallic Source and Drain Extensions and Offset N+ Doped Regions for Leakage Suppression
Authors: Zhu Zhu , Gong Xiao , Yeo Ivana
Published: February 2012

In this paper, we report the first demonstration of In0.53Ga0.47As n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with a shallow metallic source/drain extension (SDE) and offset n+ regions for leakage suppression. A SDE-last process flow was developed, i.e., the Ni–InGaAs metallic SDE was formed last, after formation of n+ doped source/drain (S/D) regions. The n+ S/D regions were offset from the gate edge with the use of sacrificial spacers. After spacer removal, self-aligned highly-abrupt Ni–InGaAs SDE was formed. Junction leakage between drain and body was effectively suppressed by ∼40 times by the n+ S/D regions.
Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition
Authors: Kawamura Yumi , Tani Mai , Hattori Nozomu , Miyatake Naomasa , Horita Masahiro , Ishikawa Yasuaki , Uraoka Yukiharu
Published: February 2012

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2V-1s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.