bluuebunny/crossref_metadata_2025 huggingface dataset:
TRAGEDY OF THE COMMONS MEETS THE ANTI-COMMONS: WATER MANAGEMENT AND CONFLICT ON THE SOUTHERN PLAINS OF THE UNITED STATES
Authors: WOHLERS TONY , MASON AARON , WOOD JOHN , SCHMALTZ ERIC
Published: March 2014

Based on longitudinal data, and relying on the tragedy of the commons and the tragedy of the anti-commons theoretical frameworks, we argue: (1) groundwater permit patterns in Oklahoma are likely to contribute to the tragic overuse of groundwater resources; and (2) involvement of large and opposing groups that operate within an environment of fragmented access rights undermines the emergence of an efficient water management regime for Sardis Lake on Native American land in southeastern Oklahoma. Based on quantitative and qualitative research approaches, this study seeks to reveal patterns of groundwater overexploitation and deconstruct the complex processes surrounding the water dispute over Sardis Lake so that policymakers understand the relevant dangers and are able to identify sound policy solutions to manage common pool resources.
RNA Helicase Proteins as Chaperones and Remodelers
Authors: Jarmoskaite Inga , Russell Rick
Published: March 2014

Superfamily 2 helicase proteins are ubiquitous in RNA biology and have an extraordinarily broad set of functional roles. Central among these roles are the promotion of rearrangements of structured RNAs and the remodeling of ribonucleoprotein complexes (RNPs), allowing formation of native RNA structure or progression through a functional cycle of structures. Although all superfamily 2 helicases share a conserved helicase core, they are divided evolutionarily into several families, and it is principally proteins from three families, the DEAD-box, DEAH/RHA, and Ski2-like families, that function to manipulate structured RNAs and RNPs. Strikingly, there are emerging differences in the mechanisms of these proteins, both between families and within the largest family (DEAD-box), and these differences appear to be tuned to their RNA or RNP substrates and their specific roles. This review outlines basic mechanistic features of the three families and surveys individual proteins and the current understanding of their biological substrates and mechanisms.
Seafloor Geodesy
Authors: Bürgmann Roland , Chadwell David
Published: March 2014

Seafloor geodetic techniques allow for measurements of crustal deformation over the ∼70% of Earth's surface that is inaccessible to the standard tools of tectonic geodesy. Precise underwater measurement of position, displacement, strain, and gravity poses technical, logistical, and cost challenges. Nonetheless, acoustic ranging; pressure sensors; underwater strain-, tilt- and gravimeters; and repeat multibeam sonar and seismic measurements are able to capture small-scale or regional deformation with approximately centimeter-level precision. Pioneering seafloor geodetic measurements offshore Japan, Cascadia, and Hawaii have substantially contributed to advances in our understanding of the motion and deformation of oceanic tectonic plates, earthquake cycle deformation in subduction zones, and the deformation of submarine volcanoes. Nontectonic deformation related to down-slope mass movement and underwater extraction of hydrocarbons or other resources represent other important targets. Recent technological advances promise further improvements in precision as well as the development of smaller, more autonomous, and less costly seafloor geodetic systems.
Expectations in Experiments
Authors: Wagener Florian
Published: March 2014

The rational expectations hypothesis is one of the cornerstones of current economic theorizing. This review discusses a number of experiments that focus on expectation formation by human subjects in a number of learning-to-forecast experiments and analyzes the implications for the rational expectations hypothesis. In these experiments, most agents are rational in an operational sense, and their expectations coordinate quickly, but not necessarily on the rational expectations value. In several situations, the homogeneous rational expectations hypothesis of Lucas and Prescott poorly describes the expectational dynamics and is outperformed by other hypotheses. But even in those situations in which the hypothesis gives a good description, it is more likely that coordination on rational values is brought about by the institutional structure of the market rather than the rationality of the agents.
Professional Medical Education and Genomics
Authors: Demmer Laurie A. , Waggoner Darrel J.
Published: March 2014

Genomic medicine is a relatively new concept that involves using individual patients' genomic results in their clinical care. Genetic technology has advanced swiftly over the past decade, and most providers have been left behind without an understanding of this complex field. To realize its full potential, genomic medicine must be both understood and accepted by the greater medical community. The current state of professional medical education in genomics and genomic medicine is reviewed, including ongoing plans to expand educational efforts for medical students, clinical geneticists, and nongeneticist physicians.
Why We Kill: The Political Science of Political Violence against Civilians
Authors: Valentino Benjamin A.
Published: March 2014

This article reviews the political science literature on political violence against civilians, including genocide, mass killing, and terrorism. Early work on these subjects tended to portray this kind of violence as irrational, random, or the result of ancient hatreds between ethnic groups. Most scholars studying political violence today, however, understand it to be primarily, if not exclusively, instrumental and orchestrated by powerful actors seeking to achieve tangible political or military objectives. Scholars continue to disagree, however, about the specific motives that drive belligerents to target civilians or the conditions under which large-scale violence against civilians is most likely.
(Invited) Parastic Elements in Gate Stacks and Contacts of Planar and Fin Transistors
Authors: Wachnik Richard , Lu Ning , Lee Sungjae , Johnson Jeffrey B. , Li Hongmei , Solomon Paul , Kwon Unoh , Krishnan Siddharth
Published: March 2014

Reduction of dimensions or scaling has reduced cost and enhanced performance of integrated circuits. These reduced dimensions have increased the importance of parasitic elements associated with the gate structure and contact structure to rf circuit design and more recently to microprocessors, standard products, and application specific integrated circuits. The net lists and compact models must account for the physical structure to enable scalability, must be efficient to enable circuit design and must be verifiable through hardware measurement. The hardware measurements can serve as a diagnostic tool for enhancing process technology of planar and FINFET field effect transistors.
Formation Energy Study of Oxygen Vacancies in Undoped, Aluminum-Doped and Nitrogen-Doped Taox-Based RRAM by First Principle Simulation
Authors: Deng Haopei , Cai Yimao , Yu Muxi , Huang Ru
Published: March 2014

Formation and transfer of oxygen vacancies are essential to transitional metal oxide RRAM’s switching behavior. In this paper, first principle is used to simulate the formation energy of oxygen vacancies in undoped, Al-doped and N-doped TaOx based RRAM. In Al-doped TaOx, oxygen vacancies’ formation energy is reduced significantly near the dopant atom. However, in N-doped TaOx, the formation energy of oxygen vacancies is slightly decreased compared with the undoped one. Our simulation results provide insight and guidance on the approach to improving RRAM’s performance by doping atoms.
A Compact Behavioral Simulation Model for CMOS Vertical Hall-Effect Devices
Authors: Huang Haiyun , Xu Yue , Wang Dejun , Wu Jun , Qin Huibin , Hu Yongcai
Published: March 2014

A compact behavioral simulation model for CMOS five-contact vertical Hall devices is presented. In term of the internal current flow geometry, the vertical Hall device is modeled based on an asymmetric Wheatstone bridge structure, including four current-controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge are calculated preliminarily by conformal mapping method. More importantly, the model takes into account the lateral diffusion effect and junction field effect which further improves the simulation accuracy. The behavioral model has been written in Verilog-A language with ten more physical and process parameters. The behavioral model simulation has been successfully performed in the Cadence Spectre environment with 0.8 μm high voltage CMOS technology parameters. The model’s simulation results are in good agreement with the reported experimental results.
The Influence of Top Metal (TM) Layer Stress on Underneath Inter-Metal VBD Performance
Authors: Wang Zong tao , Zhou Ming , Zhang Beichao
Published: March 2014

SiCN film is widely used in modern integrated circuit fabrication industry as etch stop layer and copper block layer. But the interface quality of SiCN/Cu is usually not good enough, which will lead to VBD test fail. In this paper we reported that the top metal stress have a strong side effect on inter metal, especially the layer right under top metal, VBD performance. By increase top via depth or by introduce ultra violet light cure of top SiCN film, we can obviously improve inter metal VBD performance. We also put forward a mechanism to explain all these phenomena.
Arsenic Dimer (As2
+) Lightly Doped Drain (LDD) Implantation Study for 20nm Logic Device Development
Authors: Sun Hao , Li Yong , Zhang Shuai , Xie Xinyun , Cai Gorge , Zhou Zuyuan , Shi Xuejie , He Yonggen , Shi Weimin , Ju Jianhua , Chen Larry , Yu Shaofeng
Published: March 2014

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As2
+) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As+ so it is more favorable for much lower energy (＜ƒ5KeV) implantation. A comparison of electrical parameters including drive current, Rtotal, junction breakdown voltage, gate to drain overlap capacitance and dopant SMIS profile indicates equivalent process performance for dimer and As+ implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As+ implantation.
Effect of AlGaN Barrier Thickness on the Transconductance of AlGaN/GaN High Electron Mobility Transistors
Authors: Yahyazadeh Rajab
Published: March 2014

An analytical- numerical model for the drain source and gate source currents of AlGaN/GaN based HEMTs has been developed that is capable to predict accurately the effects of AlGaN barrier thickness on the transconductance in different gate source and drain source biases. Salient features of the model are incorporated of fully and partially occupied sub-bands in the interface quantum well, combined with a self-consistent solution of the Schrödinger and Poisson equations. In addition current in the barrier of AlGaN, traps density in AlGaN are also take in to account. The calculated model results are in very good agreement with existing experimental data for HEMTs device.
The Application of AGILE for 40nm Via Hole Development of Lithography Process and Solutions
Authors: Dong Xianguo , Miao Zhibiao , Wang Wuping , Yang Zhengkai , Liu Biqiu , Zhao Long , Leng Jianghua , Zhang Yu
Published: March 2014

As the chip industry enters 45/40 nm technology node and beyond, Via photolithography process is becoming more and more challenging due to decrease of critical dimension (CD) and narrow process window. The effective control on Via CDU becomes more important to improve SRAM yield, however, the CDU has shown highly sensitive to the variations of wafer topography and the leveling capability of a scanner. The Air Gauge Improved Process Leveling (AGILE) function of ASML immersion scanner is a very effective leveling system for the improvement of CDU performance. This paper studies on the implementation and performance of AGILE focus corrections for advanced photo lithography in volume production as well as advanced development in Huali’s 300 mm facility. In particular, a logic hierarchy that manages the air gage sub-system corrections to optimize tool productivity with sufficient sampling frequency to ensure focus accuracy for stable production processes is described.
Study of Si Green Transistor with an Ultra-Shallow Pocket Junction
Authors: Xu Gaobo , Xu Qiuxia , Yin Huaxiang , Zhou Huajie , Wang Guilei , Li Chunlong , Liu Jinbiao , Li Junjie , Xiong Wenjuan , Wang Dahai , Li Junfeng , Zhao Chao
Published: March 2014

Achieving large on-state current at low power supply voltage is one great challenge for tunneling transistors (TFETs). In this paper, an N-type Green transistor (gFET) with an ultra-shallow pocket junction has been fabricated. The main feature of the device is that the pocket junction was formed by germanium (Ge) preamorphization implantation (PAI) plus arsenic (As) ultra-low energy implantation combined with spike annealing. The Ge PAI can form a Si1-xGex/Si heterojunction in the N+ pocket region. Combined with a heavily doped N+ pocket, it can realize an abrupt tunnel junction between N+ pocket and P+ source, which is helpful to increase the tunneling probability and get higher on-state current. The fabricated gFET exhibits good electrical characteristics. The device’s on-state current is up to 215µA/µm (@VDS=VGS=2V).
Source Doping Profile Design for Si and Ge Tunnel FET
Authors: Chen Shaowen , Huang Qianqian , Huang Ru
Published: March 2014

The source junction doping profile design for Si and Ge tunnel FET (TFET) is discussed and compared in this paper. By using Sentaurus TCAD tools with calibrated dynamic non-local band-to-band tunneling and non-local trap-assisted-tunneling models, it is shown that when Si TFET’s source doping gradient increases from 1.5 to 15 nm/dec, due to the gradual band bending and lower electric field at tunnel junction, average subthreshold slope (SS) increases from 38 to 64 mV/dec, onset voltage increases by 0.1 V and ON-current decreases by almost one decade. Although Ge TFET has larger tunneling electric field, the doping profile impact on SS is more severe than that of Si TFET. The design margin for doping profile under different gate length, gate oxide thickness and source-gate overlap is also discussed. Results show that for short channel Si TFETs, doping profile design margin for SS below 60mV/dec decreases as gate length shortens. For short channel Si TFETs design, the process requirement of abrupt source doping profile can be relaxed if thin gate oxide and a small underlap at the source junction are employed, and more stringent process control is required for Ge TFETs.
A Low-Cost 900V Rated Multiple RESURF LDMOS Ultrahigh-Voltage Device MOS Transistor Design without EPI Layer
Authors: T V Anil Kumar , Yang Shao-Ming , Sheu Gene , Chen PA
Published: March 2014

In this paper, a low-cost 900V rated multiple RESURF lateral double-diffused MOS (LDMOS) transistor in junction-isolated power IC technology without EPI layer is developed and successfully simulated. Don't think that the bigger the processing node the lower the cost. There are LDMOS processes today at the 0.35-micron node that use the same number of masks that are required at the 1.0-micron node. Moreover, smaller processing nodes yield smaller chip sizes, which carry both performance and cost benefits. Evaluate EPI vs. non-EPI wafers, and if your performance requirements can be met with non-EPI that is the best choice for lower cost implementation. Detailed device simulations and structure designs have been done. The optimized devices show excellent performance, which have been demonstrated with characterization results from device. The proposed multiple RESURF LDMOS without EPI Layer is able to achieve a specific on-resistance of lower than 250 mΩ-cm2 while maintaining a breakdown of over 900 volts.
Study of Random Telegraph Noise in UTBOX Silicon-on-Insulator nMOSFETs
Authors: Li C K , Fang W , Simoen E , Aoulaiche M , Wu Y R , Luo J , Zhao C , Claeys Cor
Published: March 2014

This paper reports on the behavior of Random Telegraph Signals (RTSs) in ultra-thin buried oxide (UTBOX) Silicon-on-Insulator (SOI) nMOSFETs. Emphasis is on the amplitude ΔID, which is studied in function of the front-gate, the back-gate and the drain bias. As will be shown, a careful analysis of the drain-to-source bias-dependence in forward and reverse operation enables to determine the lateral trap position in the channel. Combined with the back-gate voltage dependence, it is concluded that the Generation-Recombination (GR) centers responsible for the RTS are in the silicon film rather than in the gate oxide.
Impact of Pre- and Post-Growth Treatment on the Low-Frequency Noise of InGaAs nMOSFETs
Authors: Scarpino M , Lin D , Alian A , Merckling C , Crupi F , Collaert N , Thean A , Simoen E , Claeys Cor
Published: March 2014

The low-frequency noise is studied in planar InGaAs channel nMOSFETs, with Al2O3 gate dielectric in combination with different pre- and post-gate treatments, namely, pre-gate TMA exposure or post-gate Forming Gas Annealing (FGA). It is shown that the oxide trap density is reasonably uniform in the gate stack between 1 and 2 nm from the interface, whereby a FGA yields a lower noise power spectral density compared with the TMA or untreated devices.
Innovative Layout Styles to Boost the Mosfet Electrical Performance
Authors: Gimenez Salvador Pinillos
Published: March 2014

This paper describes how to potentiate the electrical performance of MOSFETs using non-conventional layout styles (rectangular gate geometry), without causing any extra burden to the current ICs manufacturing CMOS process. This layout approach is based on “drain-channel region-source interfaces engineering”, which is capable to add new effects to the MOSFET structure that contributes to improve the analog and digital electrical parameters of MOSFETs. Besides that, some of these new structures can enhance the transistor robustness in harsh environment (high temperature and radiation). Furthermore, as a first insight into exploration of this layout approach was applied in Multi-Gate MOSFETs (FinFET) by three-dimensional simulations and the results are very promising.
Investigation of Passivation of Ge Substrate by N2O Plasma and N2 plasma Treatment
Authors: Lin Meng , Li Ming , An Xia , Yun Quanxin , Li Min , Li Zhiqiang , Liu Pengqiang , Zhang Bingxin , Zhang Xing , Huang Ru
Published: March 2014

In this paper, passivation of Ge substrate by N2O plasma is proposed and compared with N2 plasma treatment. Results show that both N2O and N2 plasma treatment can improve the quality of the interface between high K dielectric and Ge substrate and the CV characteristics of MOS capacitors. Results show that, stoichiometric GeO2 is achieved by N2O plasma oxidation and GeOxNy is formed by N2 plasma treatment, due to native oxide residue or oxidation after aqueous cleaning. Comparing to GeOxNy passivation, GeO2
passivation is superior in reducing interface state density to ~2×1011cm-2eV-1, suppressing EOT degradation and modulating the surface potential, which is promising for high performance Ge NMOSFETs fabrication.
Investigation of SiGeB Epitaxy on Different Film Substrates
Authors: Jin Lan , Tu Huojin , He Youfeng , Lin Jing , Wu Jiaqi , He Yonggen , Wu Jingang
Published: March 2014

Selective epitaxial embedded SiGe(B) (e-SiGe) is widely used for Source/Drain in advanced CMOS technologies for introducing compressive strain to the PMOS channel which improves the hole mobility. In this paper, we investigated SiGeB epitaxy on different substrates including SiGe, Si:B, SiGeB and also dielectric films including ALD/ CVD SiN, thermal/CVD SiO2. For SiGeB epitaxy on crystallized film substrates, results show that Germanium would prevent Boron inter-diffusion between the substrate and the following deposited SiGeB. Growth Rate (GR) of the epitaxy e-SiGe film is also investigated. A combination of the SiGeB film concentration and GR study shows that Boron concentration and strain introduced by lattice mismatch between the substrate and the epitaxial film are two competitive factors to the GR. The film grows faster when Boron concentration is higher while larger strain would degrade the GR. Selectivity study shows that CVD SiN film have the best selectivity. We also investigated the film selectivity before and after thermal anneal. Results show that film selectivity become worse after thermal anneal.
Effect of Pt Redistribution on Ni(Pt)Si1-XGex Germanosilicide
Authors: Liu Qingbo
Published: March 2014

The Ni(Pt)Si1-xGex films with 5 at.% Platinum (Pt) were prepared using a two-step annealing scheme. The variation of the Rsh with the Rapid Thermal Annealing (RTA) temperature determined the optimal silicidation process with RTA1 treatment at 300 oC/60s and RTA2 treatment at 400 oC/30s. A physical model of Pt diffusion during the silicidation process was proposed to illustrate the Pt redistribution phenomenon. By using X-ray diffraction (XRD), transmittance electron microscope (TEM), energy dispersive X-ray (EDX) element mapping and line-scanning, the phase composition, morphology and the element distribution of as-formed films were analyzed.
Contact Etch Schemes at Advanced Logic Technology Nodes
Authors: Huang Jingyong , Zhang Cheng-Long , Han Qiu-Hua
Published: March 2014

Since CMOS technology moved to sub40nm node and beyond, the limits of both pre-etch and post-etch process have posed the huge challenges to contact etch itself, contact etch is playing a more and more critical role in yield enhancement. In this paper, we addressed the different schemes for both gate-first process and gate-last process to deal with the limits of pre-etch conditions including the ILD (inter-layer dielectrics) thick variation related litho local defocus, the random photo resist footing/scumming, the much thinner ILD thickness on gate, the excessively small pitch related overlay effect and the impact of gate height, and to handle the limits of post-etch processes such as WET clean related polymer remaining and W gap-fill related W missing. In brief, besides the well optimized traditional etch processes to deliver the vertical contact hole, both the pre-etch treatment and the special flush step are indispensable to broaden the overall contact loop process window, reduce the contact open and/or high Rc issue. Both indexes are highly related to final yield performance.
Double Patterning Lithography Alignment and OVL-Control Strategy for 20nm Technology
Authors: Yue Liwan , Hao Jingan , Jiang Yuntao , Zhou Junqing , Huang Ruixuan , Deng Guogui
Published: March 2014

Double patterning using 193 nm immersion lithography has been adapted as the solution to enable 20 nm technology nodes. In the Back end, Litho Etch Litho Etch (LELE) is considered as the most suitable process for this technology. The overlay control is one of the key figures for the successful realization of this technology. This paper presents a method called indirect alignment and indirect overlay measurement comparing with the common method (so called direct alignment and overlay the overlay (OVL) measurement) based on process complexity. While doing LELE, the common method need two or more films to get enough signal intensity for alignment measurement while the present method need only one film. In this paper, we will compare with the two overlay control methods and we also evaluate the risks for the present method and try to design a new APC control system to reduce the risks.
(Invited) Mueller Matrix Polarimetry: A Powerful Tool for Nanostructure Metrology
Authors: Liu Shiyuan , Chen Xiuguo , Zhang Chuanwei
Published: March 2014

Recently, ellipsometry-based scatterometry has gained more and more attention in semiconductor manufacturing. Among the various types of ellipsometry, Mueller matrix polarimetry (MMP) can obtain up to 16 quantities of a 4×4 Mueller matrix, and consequently, MMP-based scatterometry can acquire much more useful information about the sample. In this paper, the basic principle and instrumentation of MMP are presented, and then the fundamental concept of computational metrology is introduced. Several case studies are finally provided to demonstrate the potential of MMP in nanostructure metrology.
Systematic Hot Spots Finding By Pattern Search with Similarity
Authors: Luoh Tuung , Lv Rong , Chen Chi-min , Liao Hsiang-Chou , Yang Ling-Wu , Yang Ta-hone , Chen Kuang-Chao , Lu Chih-Yuan
Published: March 2014

As device rule shrinks, the finding of systematic hot spots is no longer just relied on design rule checking (DRC) and lithography rule checking (LRC). There still have some unexpected systematic hot spots impact the yield of production. Using image contour extraction technique to extract the images of issued failure sites into unit clipped patterns and then do the patterns search with a similarity algorithm. Transfer these specific pattern search care areas into an in-line inspection recipe, and then prevent the failure issues happening again. Through regrouping the seed patterns after hot scan on focus exposure matrix (FEM) or process window qualification (PWQ) wafers, the exactly or similar pattern search of these seed patterns can help us to find out the unknown risky similar pattern of interests.
Spin-Coating Defect Theory and Experiments
Authors: Zhu Zhimin , Lowes Joyce , Berron John , Smith Brian , Sullivan Dan
Published: March 2014

This paper presents a theory to explain how detectable defects are generated during a material’s transition from a liquid state into a solid film. The hypothesis of defect formation is that it occurs as a result of an imbalance of molecular forces and molecular motion during the material phase transition. Experimental validation was done using a model spin-on silicon hardmask. Spin time and bake temperature were studied as process parameters to control defect counts. Wide variations in the resulting defect counts show strong statistical significance. The experimental results fit very well with the hypothesis. This preliminary study on defect mechanisms gives a direction to develop next-generation defect-free materials.
Study of Over-Etching Behaviors on Silicon Nitride Patterned Wafers
Authors: Yao Guo Feng , He Xiao Ming , Chen Xing Jian , Zhang Li , Chang Toney
Published: March 2014

To ensure the reliability of passivation etch in wafer fabrication, behaviors of over-etching (OE) on silicon nitride (SiN) patterned wafers were investigated under various chamber conditions in a capacitively coupled plasma (CCP) etching system. C4F8/O2/Ar gas chemistry is used. It was found the etch rate (ER) was dependent not only chamber conditions but also the previous process. Copper (Cu) is inevitably sputtered onto the chamber wall during passivation etch. It was observed the etch rate raised from 796 to 1060 Å/min with the accumulation of copper. Moreover, ER would be quite stable if no prior waferless clean (WLC) process was performed, regardless of the residual copper amount. OES intensity data indicated the surface loss of CF2 radicals was significant in idle or clean chamber, but was inhibited by fluorocarbon (CF) polymer coatings. Finally, it was confirmed copper could promote the formation of and thus affect the etch rate.
Defect Free HDIS Process for Sub 28nm HKMG Using Reducing Chemistry
Authors: Diao Li , Meng Xiaoying , Han Qiuhua , Zhang Haiyang , Elliston Robert , PhanVu HaiAu , Vaniapura Vijay , Zhang Nancy , Zhou Keith , Lee Christopher
Published: March 2014

High dose implant strip (HDIS,) has been one of the focuses for yield enhancement. It is a moving target since implantation dose, energy and layer number are continuously optimized for better device performance. The pure reducing processes developed are optimized for gate first high κ metal gate (HKMG) integration scheme to accommodate low gate oxidation requirement. Higher hydrogen containing content and other parameters were tested and showed good trend on residue removal yet reaching a limit. Mechanism study has led to a new reactor design. The processes developed showed zero defect post dry and reduction trend of SiGe substrate loss in short loop tests. The throughput can be more than doubled compare to a baseline FG process.
Complex Film Stack Etch Application for BSI CIS in Mesa Etcher
Authors: Ma Ming , Huang Ying , Zhao Ganming , Ren Frank , Zhong Neil
Published: March 2014

For most people, Apple’s introduction of backside-illuminated (BSI) CMOS image sensors (CIS) in their iPhone4 may have been the first time they became aware of this technology. Compared with traditional front-illuminated CMOS, light in a BSI CIS can strike the photocathode directly without passing through wiring layer. Thus, photon absorption efficiency increases from 60% to 90%. As the size of the CIS decreases, this performance improves. Now, BSI CIS are widely used in digital cameras, smartphones, etc. However, placing the active matrix transistors behind the photocathode gave rise to a host of new problems, such as cross-talk, which would cause noise and dark-current, and color mixing between adjacent pixels. Solving these problems calls for a low-cost solution in the etch process used in volume production. Etching a BSI CIS film stack is very complex. The etch must pass through approximately half a micron of silicon oxide or nitride, a high-k film and more than 2 microns of silicon. As many of the pre-layers have been planarized, the thickness of oxide/nitride film or silicon film is very variable (typically more than 10%). High etch selectivity and precise time control are therefore necessary. The Applied Materials Centura® AdvantEdge™ Mesa™ etch chamber maintains a high silicon etch rate while preserving a vertical sidewall profile. The oxide/nitride etch rate was acceptable; it also exhibited high selectivity and minimal micro-loading. This chamber was therefore the best choice for this application. The EyeD® endpoint system was used to monitor the interface of the film to control process time. The backside grounding layer (application 1) is similar to pad1. To eliminate deposition voids, a very tapered profile was required (70º+/-5°). The SF6/Cl2/C4F8 recipe could achieve that profile, but had very high silicon etch rate. It would create serious sub-trench issues when the high-k layer was punched through. Its process window was also very marginal. CF4/CHF3 was tested as an alternative, but produced excessive polymer deposition. The profile of high-k became unacceptably tapered. We ultimately used a two-step approach to precisely control polymer deposition and this approach produced a very good profile. For the backside interconnection layer (application 2), tapered profiles were also required. More importantly, the etch had to pass through more than 2 microns of silicon while retaining an approximately 70° profile angle. The gas ratio had to be precise, and pressure was kept at a mid-level. The final profile, which was very good, was superior to that achieved by our competitors. The silicon thickness is very variable because of the limitations of the planarization process. For best production flexibility, we use the EyeD optical endpoint system. Initially, the signal was very weak when the process was deep in the silicon. However, a very robust endpoint was obtained by fine-tuning the EyeD algorithm.
Study of Solving the Outgas Induced Defect in Metal Hard Mask All-in-One Etch Process
Authors: Lv Yu-Kun , Jiang Min , Liu Bin , Zeng Lin-Hua , Ren Yu , Huang Ya-Hui , Shi Xiao-Bing , Yao Li-Min
Published: March 2014

This article introduced the issues when running 55nm BEOL MHM (Metal Hard Mask) AIO (All-In-One) Etch during manufacturing. Two kinds of issues are studied: one is the post etching condensation and another is the particles formed on un-etch wafers. Both issues show slot correlation which depends on wafer position in FOUP (Front Open Unified Pod): lower slots are defect free while upper slots getting worse. Experiments are carried on to study the slot effect as well as Q-time impact. It is identified that F (Fluorine) contained outgas generates the defects which impacted the wafers in the upper slots within FOUP. Compared to tightening Q-time and FOUP splitting, installing Purge Storage is much easier to control for massive production. It’s a kind of “In-situ” degas solution, simple but very effective. Furthermore it could be good reference to other more applications.
A Study of Self-Aligned-Via Based All-in-One Etch
Authors: Zhou Jun-Qing , Hu Min-Da , Zhang Cheng-Long , He Qi-Yang , Zhang Hai-Yang
Published: March 2014

Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized together with punch-through-via (PTV) scheme for copper interconnect formation since sub-65nm CMOS technology node. In this work, compared to the traditional PTV scheme on sub-45nm test vehicle, we successfully demonstrate that the self-aligned-via (SAV) based all-in-one (AIO) etch process could be fulfilled on thin metal hard-mask and is capable of delivering much better via related TDDB performance without the performance degradation of electromigration (EM), while the contact resistance (Rc) exists different trend with PTV scheme. The high etch selectivity is imperative in both partial via etch, trench etch and liner removal step to reduce the via encroachment on metal hard-mask, the via CD along the unconfined (metal hard-mask) direction should be also optimized to achieve the above desired performance without tiger teeth beneath via bottom. Both via and trench etch recipe need be well optimized to deal with etch stop, via bottom grass and polymer residue issues. Besides, SAV delivers much good yield performance even at misalignment via chain test key, which indicates its very robust overlay margin. But it suffers yield loss at some sub-rule test structure in which trench line end CD is strictly confined by nearby pattern.
Advanced STI Etch Process Development on NMC Etcher
Authors: Wang Dongjiang , Zhang Yi-Ying , Han Qiu-Hua , He Qi-Yang , Fu Ya Li , Yang Meng , Zhang Hai-Yang
Published: March 2014

As the dimensions of semiconductor devices continuously shrink, it becomes critical and challenging to control process loading in reactive ion etch (RIE) to ensure precise patterning and to avoid performance degradation among different patterns. Basically, the loading effect in RIE comes from its inherent local environment discrepancy around different patterns such as dense and isolated (ISO) patterns. Some part of the etch process loading can be reduced by adopting proper pattern schemes. Shallow trench isolation (STI) etch process demonstrated the hard mask (HM) approach could significantly improve the depth loading by reducing the aspect ratio as thinner HM can be used. While other methods such as etch process optimization are needed to further reduce the process loading. In this paper, we systematically investigated the profile (sidewall angle) and depth loadings among dense and semi-isolated lines in STI etch from the point of view of various process parameters such as pressure, power, and chemical gases. It was found that proper chemical gases were critical for loading control on sidewall angle and depth. Besides, bias power was also found to drastically impact the loading performance. Based on the above learning, an STI etch process was successfully demonstrated on an NMC 612B etcher with both WAT and yield verification.
The Challenges and Solutions of High-K First Dummy Gate Etch
Authors: He Qi-Yang , Meng Xiao-Ying , Zhang Hai-Yang
Published: March 2014

In this work, we focused on the dummy gate etch process for high-k first process and firstly investigated two etch schemes with end-cut based double patterning technique. The pure hard-mask scheme is proven to be superior from the point of view of the aspect ratio, the control of the selectivity of ODL over poly-Si and the impact of ODL removal on HK capping layer and silicon substrate. Compared with the traditional poly-Si gate etch, HK capping layer can serve as more reliable etch stop layer. However, the extra steps dedicated to HK and its capping layer affect the bottom profile of poly-Si gate, ending up with notched bottom profile. Treatment after poly-Si etch has been demonstrated to remarkably alleviate such impact. Besides, we also demonstrated different sidewall profile of HK and its capping layer, which can affect final transistor performance and needs precisely control.
The Improvement of Poly-Si Gate Line Width Roughness
Authors: Meng Xiao-Ying , Sui Yun-Qi , Han Qiu-Hua , He Qi-Yang , Zhang Xuan , Zhang Hai-Yang
Published: March 2014

LWR (line width roughness) is normally defined as the 3 sigma of critical dimension (CD) variation along a segment of a line. As CDs of semiconductor devices continue to be scaled down, LWR, the looming critical index, needs to be well controlled within 8% of gate line CD for advanced logic technology nodes as ITRS states. In this contribution, we mainly focused on the gate etch solution to reduce post-gate etch LWR including PPT (pre-plasma treatment), post-Barc (bottom anti-reflective coating) treatment (cure) and plasma induced polymer formation (coating). Besides, we also leveraged the uniform design experiment (UDE) to investigate the impact of Barc/Cure/Darc (dielectric anti-reflective coating) open steps on LWR and identified the optimal Barc/Darc condition among 25 UDE pi-runs. Finally, we obtained the optimal gate etch condition which achieved 2.8nm (the strictest CD-SEM algorithm ever reported) overall LWR performance including both low frequency and high frequency components), roughly more than >30% LWR improvement compared to the initial photoresist LWR. As implant has been reported to be the only way to reduce the low frequency LWR for photoresist, LWR improvement from various implant species and doping levels, the side-effects of implantation and its potential contribution to the overall improvement of post-etch LWR are also addressed.
TiN Hardmask Etch Residue Removal for Cu Interconnect Fabrication
Authors: Cui Hua
Published: March 2014

A novel high TiN etch rate, wet cleaning formulation approach was developed with a TiN etch rate of more than 400 Å/min at 60ºC. The chemicals are compatible with Cu and low-k materials, and provide complete etch residue removal and more than 24 hours formulation pot life
A Proprietary Chemical Bath Life Study in MHM ULK Scheme Wet Cleaning
Authors: Yuan Zhugen , Liu HX , Hu Chunzhou , He Yonggen
Published: March 2014

As technology evolves to 45nm and beyond, IC companies adopt TiN metal hardmask instead of PR (photo resist) to gain better etching profile, CD uniformity and less low-k material damage. To improve Cu gap fill capability, an in situ TiN pull back is needed in the subsequential wet clean step. This pullback can be done by mixing some additive with clean media, like H2O2. But H2O2 tends to decompose along the time, it also bring the challenges to the wet clean media stability. In this paper, we study a proprietary wet clean chemical behavior with pH, Cu ion concentration, H2O2 additive and bath lifetime. Cu ions content is demonstrated critical to the mixture instability when H2O2 presents. Chemical degradation mechanism is also discussed.
The Defect Reduction of Via Opens by the Integration of Inter-Metal-Dielectric Film, Metal Hard Mask, and All-in-One Etch Processes
Authors: Gu Xiaofang , Chen Hunglin , Long Yin , Ni Qiliang , Fan Rongwei
Published: March 2014

This research aims at the pattern failure defects by the backend all-in-one (AIO) etching process during a recent technology development in a 12-inch FAB. The AIO etch directly defines the shape of both trench and via, however, those previous process steps involving the deposition of inter-layer-dielectric film, metal hard mask and the wet clean would contribute to the AIO etch performance and even cause pattern defects. The investigation elucidates the count of pattern failure defects strong correlates with the life time of ST250 which was used to remove polymer post metal hard etch process. The experiments shows that to extend ST250 rise time and add a scrubber process step can achieve a comparable defect performance with the old acid which run time > 50hrs. Eventually, the additional scrubber process was added to reduce defect counts and gained end-of-the-line 4% yield.
SaDP Process Challenges and Solutions on NAND Flash Cell
Authors: Zhang Yi-Ying , He Qi-Yang , Zhang Hai-Yang
Published: March 2014

Self-aligned double patterning (SaDP) technology has been successfully developed for three critical layers (AA, CG and M2) in NAND flash memories with 3X design rule. In SaDP process, the core performance is extremely critical for even/odd performance which will impact the final profile and etch depth. In this paper, we investigated two etch schemes for core etch. Results showed that scheme I, the traditional core etch, is capabable of forming the vertical core without top corner rounding. Howerer, the remained hard mask on the core top narrows down the subsequent spacer etch window which will influences the pattern transfer performance. Scheme II, with the removal of core hard mask during core etch, is proven to be superior from the point of view of pattern transfer. However, it’s challenging to get vertical and the core without sub-trench. After the optimization of the etch process, the core profile can be well controlled. Besides, the line-end cut process is a must item for SaDP process to separate the adjacent twin lines. Line-end cut could be completed after spacer patterning, final patterning or any other subsequent processes. For control gate (CG), cutting in the subsequent processes is a good choice to avoid the line end extension and AA damage.
TSV Backside Reveal by a Wet Etching Process
Authors: Wang Lei , Li Heng fu , Song Chong shen , Zhang Wen qi
Published: March 2014

TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency. In via-middle TSV integration, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grinding followed by a reveal etch. The backside reveal determines the TSV connection performance, and is a key step in the fabrication. In this paper we demonstrate a controlled wet etch back method that uses a spin wet etch back process having excellent repeatability, reduced process defect and reduced copper contamination. We will briefly review TSV integration technology; samples preparation and single wafer wet etch equipment. Then a set of experiments is described, which is used to select etch parameters to achieve the desired TSV reveal height and selectivity. Lastly we will show results of our TSV reveal process.
Total Solutions for 40nm Metal Hard-Mask All-In-One Etch Process
Authors: Gai Chen-Guang , Huang Jun , Zhang Yu , Shi Xiao-Bing , Yao Li-Ming
Published: March 2014

MHM (Metal Hard Mask) AIO (All-In-One) etch is one of key BEOL (Back-End-Of-Line) processes for 40/45nm technology node and beyond. In this work, we focus on some key issues and solutions that we encountered during 40nm MHM AIO etch process development in HLMC. Main issues including: TiN thickness optimization, trench profile optimization, kink profile optimization, chamfer profile control, TixFy residue issue, via profile control, trench Bottom roughness issue, via bottom integrity control etc. For above process challenges, the article gives detail analysis and then provides final solutions which can meet all process requirements after balancing and optimizing all process parameters under current hardware’s conditions.
(Invited) Electroless Technology for the Upcoming Challenges in Interconnect Metallization
Authors: Kolics Artur
Published: March 2014

Electroless metallization has been implemented in semiconductor manufacturing as capping for electromigration improvement. Further expansion of the electroless technology in other areas of semiconductor industry may be possible considering the upcoming challenges in metallization for future technology nodes. Challenges related to PVD Cu seed continuity in vias, high resistivity of alternate seed/liner schemes, reliability of Cu interconnects, transition to 450mm, and questions related to “what is beyond Cu metallization” are among the areas where the electroless approach can hold some key advantages over existing technologies such as CVD or electroplating. In the presentation, we review the main features/capabilities of the technology and compare it with other metallization schemes to highlight potential applications.
Investigating and Solving Popcorn Defect Produced from Low Dielectric Film of SiOCH Silicon Oxycarbide at 45nm Technology Node
Authors: Zhou Ming , Zhang Beichao
Published: March 2014

The main purpose of this paper was to investigate formation of popcorn defect in low dielectric constant film (SiOCH, silicon oxycarbide) and put forward solution. To eliminate popcorn defect, the oxygen plasma post treatment was in situ used to remove suspended particle in chamber after the deposition of low dielectric constant film was finished. Scanning defect results showed that there were still buried defects with popcorn type in SiOCH low k film. When clean chamber process was adjusted, the quantities of the defects in SiOCH film were decreased. Moreover, deposited seasoning film covered all chamber after cleaning process, and its adhesion was directly relative with buried defect. For improving among chamber surface-seasoning film-SiOCH low k film, OMCTS/O2 in season process was adjusted from1.3/900 into 0.9/900, and the defect counts were decreased obviously. By optimizing cleaning and seasoning process, the buried defects were not found in SiOCH film.
Plasma Damage Improvement during Cu Capping Layer Deposition for Advanced Nodes
Authors: Cao Christian , Song Kerry , Bai Fanfei , Chen Larry
Published: March 2014

Cu capping layer deposition plays an important role in BEOL plasma induced damage. In this paper, PID issue by Cu capping layer deposition process studied. The PID performance was studied with Cu capping layer deposition recipe optimization. And, the impact on PID performance of different Cu capping layer equipment was also compared. The PID performance is different with antenna ratio increase, both NMOS and PMOS PID performance with different antenna ratio have been investigated. In order to get clear supporting evidence for plasma damage, plasma charged voltage of wafer surface is also studied by Quantax in this paper. Finally we developed an optimized Cu capping layer deposition process with acceptable PID performance and without any reliability degradation.
K Repair and RC Improvement in 28nm Logic Devices and Beyond
Authors: Zhou Ming , Chai Qinglin , Chen Yingjie , Li Xianyuan , Deng Hao , Wang Zongtao , Zhao Ganming , Zhang Beichao
Published: March 2014

As interconnects continue to scale, enabling faster device speed and lower power consumption by reducing the κ value (capacitance) of each insulating dielectric layer becomes more imperative. Low-κ dielectrics are exposed to many process steps in fabricating a multiple-metal-layer structure, and must then withstand the stresses of packaging and assembly. The Applied Producer ® Onyx™ chamber is a newly-developed chamber for κ repair treatment in logic devices at 28 nm and beyond. The novel Onyx process and its mechanism are discussed by FTIR analysis. K repair and RC improvement are also demonstrated.