bluuebunny/crossref_metadata_2025 huggingface dataset:
Fouling Mitigation of Ion Exchange Membranes in Reverse Electrodialysis
Authors: Han Soo-Jin , Chae Soryong , Park Jin-Soo
Published: February 2020

Reverse electrodialysis converts electrochemically into energy conversion technology due to the difference in salinity between diluted salt solutions such as seawater and dilute salt solutions such as fresh water. The RED stack has a cation exchange membrane and anion exchange membrane alternately arranged between two electrodes that selectively transmit anions and cations. Ion exchange membranes are easily contaminated with multivalent ions and organic matter, which affects the performance of RED. In this study, the fouling phenomena of cation and anion exchange membranes for various foulants possibly found in seawater and river water were investigated. Ion exchange membranes were contaminated with NaCl solution containing foulants, and the electrical resistance and the degree of contamination with contamination time were measured. The cation exchange membrane is contaminated with a cationic foulants and the anion exchange membrane is contaminated with anionic foulants. The fouled membranes were regenerated, and the electric resistance and the degree of contamination with regeneration time were measured.

Acknowledgment

This work was conducted under the framework of Research and Development Program of the Korea Institute of Energy Research (KIER) (B8-2441).
Evaluating Microstructure and Transport within Flow Electrodes for Capacitive Deionization
Authors: Dixit Marm , Moreno Daniel , Hatzell Kelsey B , Hatzell Marta C.
Published: February 2020

Flow electrode capacitive deionization is a emerging approach for electrochemical desalination. It mitigates several challenges associated with film or membrane capacitive deionization through transforming the electrodes from a static electrode into a suspension electrode. This enables greater surface area, and by consequence higher saline water treatment. The major disadvantage associated with flow electrode capacitive deionization is the high cell resistance and pumping energy. Electrodes with high weight percent minimize resistance but maximize pumping energy, and conversely low weight percent electrodes have reduced pumping energy but increased whole cell resistance. Here, we will present structure-property relationships relevant for static and flowing flow electrodes. The structure-property relationships are obtained through reconstructing the 3-D structure using x-ray tomography[1]. these relationships are then used to predict desalination performance in a bench scale desalination cell.

[1]Hatzell, K. B., Eller, J., Morelly, S. L., Tang, M. H., Alvarez, N. J., & Gogotsi, Y. (2017). Direct observation of active material interactions in flowable electrodes using X-ray tomography. Faraday discussions, 199, 511-524.
Self-Regenerating Oil Absorbent Via Wettability Switch Using Electrochemical Redox of Conjugated Polymer Surfaces
Authors: Xu Jian , Fu Shichen , Xu Wei , Yang Eui-Hyeok
Published: February 2020

There exists a huge demand for efficient, reliable and safe technologies for oily water treatment and/or oil recovery. Among many techniques, absorbent-based technology shows the possibility of full removal and reclaim of oils from water, while bringing little adverse effects to the environment [1]. In spite of their promises, the issues pertaining to the recycling and regenerating of saturated absorbents have been less-explored [1, 2].

In this work, we demonstrate a conjugated polymer mesh as oil absorbent capable of in situ self-regeneration via wettability switch during electrochemical oxidation and reduction. We fabricate the absorbent through electropolymerization of polypyrrole-dodecylbenzenesulfonate (PPy(DBS)) on the surfaces of carbon nanotubes (CNTs) grown out of the surface of a stainless steel (SS) mesh. The PPy(DBS)-coated mesh shows oleophilic property when electrochemically oxidized, allowing the mesh to absorb oils (i.e., oils stick to the polymer surface; oils are trapped within the micro-pores of mesh). Under reduction, the surface switches to oleophobic (i.e., oils do not stick to the polymer surface), which allows trapped-oils by the mesh to be released, while in situ self-regenerating the polymer surface. We also observe that this switchable adhesion property is further enhanced incorporating CNTs into the structure. Using this approach, in situ absorbing and releasing of dichloromethane (DCM) in aqueous solution is demonstrated using a rolled-up absorbent mesh. We further demonstrate the wettability switch performance (characterizing the retention force when oxidized and switch time when reduced) of the absorbent during 250 redox cycles. In addition, the potential usage of this oil absorbent for oil/water separation is demonstrated by transporting DCM from one vial to another. Together, this novel adsorbent shows great promise towards high-efficient continuous oil/water separation applications.

[1] J. Ge, H. Zhao, H. Zhu, J. Huang, L. Shi, and S. Yu, “Advanced sorbents for oil-spill cleanup: recent advances and future perspectives,” Advanced Materials, 28 (47), 10459–10490, (2016).

[2] Z. Chu, Y. Feng, and S. Seeger, “Oil/water separation with selective superantiwetting/superwetting surface materials,” Angewandte Chemie - International Edition, 54 (8), 2328–2338, (2015).
Study to Carry out the Degradation of Industrial Dyes Applying Electrochemical/BDD Process in a Laboratory Stirred Tank Reactor
Authors: Alcocer Salvador , Picos Alain Ricardo , Uribe Agustin , Pérez Tzayam , Peralta-Hernández Juan Manuel
Published: February 2020

Degradation of the real industrial dyes Blue BR, Violet SBL and Brown MF 50 mgL-1 has been studied by the electrochemical oxidation (EOx), electro-Fenton (EF), photoelectro-Fenton (PEF) process based on BDD electrode. Each dye was tested in 0.05 mM Na2SO4 with 0.5 mM Fe2+ at pH 3.0, and electrolyzed in a stirred tank reactor under galvanostatic conditions with 2.0, 5.0, 7.0, 11.0 and 18.0 mAcm-2. Dyes were oxidized via hydroxyl radicals (·OH) formed at the BDD anode from water oxidation coupled with Fenton’s reaction cathodically produced hydrogen peroxide (H2O2). Under Na2SO4 medium close to 100% the decolorization was achieved. Through the color abatement rate the dyes behavior was analyzed at the beginning of the oxidation process. Dissolved Organic Carbon (DOC) was tested to evaluate the degradation. From DOC removal, it was established an increasing relative oxidation power of the PEF>80%, according with their decolorization trend. This study highlights the potential of the electrochemical/BDD process for the degradation of industrial dyes found in wastewaters under appropriate experimental conditions.
Simulations of Current Distribution Along a Rotating Cylinder Electrode Under Turbulent Flow Conditions and Continuous Mode of Operation
Authors: Nava José Luis , Rosales Mario
Published: February 2020

This communication deals with the simulations of turbulent flow, mass transport and tertiary current distribution on the cathode of a rotating cylinder electrode reactor (RCE) in continuous mode of operation. The electrolyte inlet was located at the bottom and the electrolyte exit at the top. Silver electrodeposition (1300 ppm Ag(I) in 23000 ppm CN− at pH 13) was employed as a model system. A 316-type stainless steel cylinder with a 3.8 cm diameter and a length of 11 cm was used as a cathode, while six Ti-IrO2 plates were used as anodes. Electrolyzes were performed at holding potential of −1.2 V SCE, which guaranteed mass transport control. The volumetric inflow rate tested was 0.1 L min−
1 giving a mean flow rate of 0.037 cm s−
1 (performed at the inter-electrode gap). The rotational speeds at the RCE surface were 100, 200, 300, 400, and 600 rpm (peripheral velocity of 10.5, 20.9, 31.4, 41.9, and 62.8 cm s−
1; Re of 7600, 15100, 22700, 30200, and 45400, respectively). It is worth mentioning that the peripheral velocities predominate in two magnitude orders over the inflow electrolyte rate. Therefore, the mass transport is determined by the electrode rotation speed.1 Simulations were obtained solving the RANS equations with the standard k−ε turbulence model. For mass transport simulations, the averaged diffusion-convection equation was solved. For the simulations of tertiary current distribution, wall functions were adapted. The current distribution along the RCE interface in the z-coordinate developed one edge effect near to the electrolyte inlet, afterwards, homogeneous current distribution was attained. The edge effect is formed by the abruptly silver concentration depletion at the electrolyte inlet. Excellent agreement between mass transport correlation and current distribution simulations with experimental data were obtained.

References

M. Rosales, and J.L. Nava, J. Electrochem. Soc., 164 (11), E3345 (2017).
CFD Modelling of an Electrodialysis Cell
Authors: Quiñones Félix Tonatiuh , Camacho Mara Patricia , Rodríguez Francisca Alicia , Ortega Arturo , Cruz-Díaz Martin Rogelio , Rivero Eligio Pastor
Published: February 2020

Electrodialysis (ED) cells are based on the selective transport of ions through membranes which ideally exclude the co-ions, so that when a potential difference is applied to the cell all ions are transported in solution but only the counter ions can cross the membrane. Thus, concentration polarization occurs in solutions adjacent to membrane surfaces due to the different transport number between the membrane and the solution. The concentration profiles formed in the solution near the membrane depends on the mass transport fluxes and hydrodynamic pattern in the channel; operating conditions and geometrical configuration of the cell affect greatly the concentration polarization [1]. Therefore, the performance of ED cells depends not only on the membrane properties but also on the electrolyte hydrodynamics being important to provide an adequate flow patter avoiding channeling, stagnant zones, jet formation, among others flow deviations. Keeping a homogeneous flow patter minimizes variations of mass transfer fluxes and current density over the membrane surface preventing high polarization zones that could give rise to water dissociation, low efficiency and premature membrane failure. The examination of relevant mass transport mechanisms by modelling can help to evaluate the effect of design characteristics and operating conditions on the performance of an electrodialysis cell through the analysis of concentration, potential and current density distributions. In this task, CFD has proven to be a valuable tool for the analysis of flow and mass transfer in membrane separation systems [2]. Therefore, this work presents the modelling of a laboratory ED cell coupling hydrodynamics and mass transport, taking into consideration changes of Donnan potential. The flow pattern inside channels of ED cell were obtained by 3D CFD modeling and the results were used to calculate the residence time distribution (RTD) to compare with experimental RTD. The hydrodynamic behavior was used then to solve the mass transport model to obtain a description of the concentration distribution of each of the ionic species in the cell, as well as of the amounts derived as fluxes of each of the components, current density and Donnan potentials at every point of the membrane.

[1] Gurreri L., Tamburini A., Cipollina A., Micale G., Ciofalo M., CFD prediction of concentration polarization phenomena in spacer-filled channels for reverse electrodialysis J. Membr. Sci. 468, 133–148 (2014).

[2] Fimbres-Weihs G.A., Wiley D.E., Review of 3D CFD modeling of flow and mass transfer in narrow spacer-filled channels in membrane modules, Chem. Eng. Process. 49 759–781 (2010).
Impact of Multiple Debonding on Adhesion Energy
Authors: Fournel Frank , Larrey Vincent , Rieutord François , Morales Christophe , Bridoux Claudine , Mauguen Gaelle , Lobo Sofia
Published: February 2020

Direct bonding energy relates to the well-known “strength” or “toughness” of direct bonding interface. It is the energy needed to separate two bonded surfaces. In contrast, adhesion energy is the energy available to bring the two surfaces together. Due to hysteretic effects, the two energies may be different and, while the first energy has been largely measured, the second one is the subject of very few papers only [1, 2, 3].

In this study, a new phenomenon will be shown in the adhesion energy behaviour using two silicon wafers. As shown in figure 1b, several partial debondings and rebondings of the same silicon direct bonding structure result in an increase of the bonding wave speed. After reaching a maximum bonding wave speed, a full debonding brings the speed back to its initial value. As it has already been shown theoretically by Rieutord et al. [4] and verified experimentally by Larrey et al. [3], the bonding wave speed is linked to the adhesion energy of the system. Therefore, an increase of the bonding wave speed consequently indicates an increase of the adhesion energy. As shown in figure 1b, multiple partial debondings increase the bonding wave speed by more than 50%, which increases the adhesion energy by more than 40%. The relationship between adhesion energy and bonding wave speed is not linearly dependent, as defined in the equation of figure1a [4] and shown in figure1c.

Different experiments have been done to find the cause of this peculiar behavior. A model will be proposed and discussed.

REFERENCES

[1] D. Grierson and K.T. Turner, ECS Trans. 33, 573 (2010).

[2] D. Radisson, Direct Bonding of Patterned Surfaces, phdthesis, Université Grenoble Alpes, 2014.

[3] V. Larrey, G. Mauguen, F. Fournel, D. Radisson, F. Rieutord, C. Morales, C. Bridoux, and H. Moriceau, ECS Trans. 75, 145 (2016).

[4] F. Rieutord, B. Bataillou, and H. Moriceau, Physical Review Letters 94, (2005).

Figure 1
Temporary Bonding Technologies for Thin Wafer Handling
Authors: Mazumder Prantik , Bellman Robert , Manley Robert G. , Bhattacharyya Indrani , Adib Kaveh
Published: February 2020

Thin glass substrates offer low dielectric constant and high temperature process capability for faster and thinner packages but handling is challenging due to lack of mechanical stiffness. Temporary bonding of thin wafers to stiffer carrier substrates offers a solution and has been an active area of research and development in recent years. Polymeric and tape wafer bonding solutions are available but usually for low temperature processes. In Corning, we have developed an array of surface treatment/coating technologies that offer high temperature capability (as high as 700°C). The common theme of all these technologies entails surface treatment or coating of a carrier substrate to achieve strong non-covalent bonding with the thin wafer. The desired attributes are: (a) high enough bond energy at room temperature to withstand vacuum, thermal, and wet processing steps, (b) low enough bond energy after the thermal processing steps rendering the pair mechanically separable, (c) spontaneous bonding via self-propagating bond wave, and (d) minimal outgassing or bubble formation between carrier and thin wafer due to degradation of bonding material. The technologies range from vacuum based sub-monolayer surface functionalization to vacuum based organometallic coating to high throughput solution processed ultra-thin molecular coatings. In this talk we will first describe the theoretical underpinnings of various surface and chemical forces that control the bond energy between the carrier and the thin wafer, models to predict the bond energy as function of surface chemistry and surface energy parameters, influence of surface chemistry on various process attributes such as bond wave propagation and outgassing during thermal treatment. We will also briefly review various processes developed and their relative strengths and applicability.
Temporary Bonding for High Temperature Processing of Thin Glass Using Plasma Activated DLC Layer
Authors: Bellman Robert , Mazumder Prantik , Manley Robert G. , Adib Kaveh , Liu Shiwen
Published: February 2020

Commercial temporary bonding technologies utilize relatively thick polymeric materials whose use is limited to below 400oC, typically below 250oC. While adequate for many BEOL processes, the temperature limitation and outgassing from the bonding media are incompatible with higher temperature processes such as CVD growth, Au eutectic bonding and other processes for MEMS, photonics, or packaging applications. This talk describes a temporary van der Waals wafer bonding method using a thin continuous layer of PECVD deposited diamond like carbon (DLC) layer suitable for smooth glass, silicon and sapphire substrates. Rapid self-propagating bonding is achieved through plasma activation of the bonding surface. Raman and optical characterization of the DLC layer are consistent with a hydrogenated amorphous carbon structure. A 4 nm thick N2-O2 treated DLC layer is shown to bond thin glass to a display glass carrier with a bond energy <500mJ/m2 and minimal blistering at temperatures up to 600C. Bond energy of thin glass bonded with DLC was shown to be less than 400 mJ/m2 throughout a simulated LTPS TFT thermal cycle. The DLC bonding layer remains adherent throughout the vacuum, thermal and wet processing steps of typical semiconductor and MEMS fabrication; yet the bond energy between the pair remains low-enough after the thermal processing steps that renders the pair fully detachable.
Collective Die Direct Bonding for Photonic on Silicon
Authors: Sanchez Loic , Fournel Frank , Montmayeul Brigitte , Bally Laurent , Szelag Bertrand , Adelmini Laetitia
Published: February 2020

Integrated transmitters incorporating lasers and modulators on silicon are of primary importance for all communication applications, and at the same time are the most challenging to manufacture due to the need of hybrid III-V integration. In order to introduce III-V materials in low cost silicon platform manufacturing, direct bonding approach could present a great interest due to the growth limitation of III-V hetero-epitaxial layers directly onto silicon. Furthermore, by using a 100 nm silicon dioxide layer between the silicon wave guide and the III-V active stack, direct bonding allows the optical coupling necessary to build active optical device.

Nevertheless, the potential low cost model of silicon photonic is based only on the hypothesis that we are able to work on the full surface of the 200/300 mm SOI photonic wafer. III-V wafer direct bonding is not suitable to fulfill this requirement for two main reasons. First, the maximum diameter available for III-V wafers is limited to 150 mm up to now. Secondly, the III-V material is necessary only on the emitter and receiver areas which represent only a very little part of the device area. Therefore, the most part of the reported full III-V wafer is lost by the layer patterning on required areas.

To overcome this limitation in term of wafer diameter and to limit the loss of a very expensive starting material we have developed at LETI a collective die direct bonding process. The idea is to bond collectively III-V chips only where there are necessary and on the full photonic SOI surface. The die size is selected to be slightly higher than the targeted area in order to be compatible with a wafer notch alignment and avoid any accurate alignment with alignment marks. The requirements for direct bonding are exactly the same than for wafer bonding, but die direct bonding is obviously more difficult due to the dicing step which generates a high level particle contamination. All the process steps have to be adapted to be compatible with die handling and the die cleaning before bonding have to be strongly optimized to remove this high particle contamination. We have then developed specific silicon die holder in order to clean the die surfaces collectively in classical microelectronics high performance cleaning tools. A test vehicle containing few hundred 3*3 mm² dice will be used to evaluate the collective die direct bonding process. Because III-V materials are not as mature as silicon, the bonding process will be firstly evaluated with silicon dies. After optimization, Indium phosphide dice will be used to validate the global process. Bonding interfaces of dice are finely characterized by Scanning Acoustic Microscopy and SAM images will be processed in order to quantify the bonding yield and the die positioning accuracy.

Figure 1
Temperature Effects on the Performance of Activated Carbon Electrochemical Cell in Aqueous and Non-Aqueous Electrolytes
Authors: Forghani Marveh , Donne Scott W
Published: February 2020

The aim of this study is to observe the effects of temperature changes on the cycability and the electrochemical performance of activated carbon (AC) electrochemical cell in aqueous (K2SO4) and organic (TEABF4 in acetonitrile) electrolytes.

A series of experiments have been carried out inside of the environmental chamber with temperature ranging from 273 to 313 K for aqueous electrolyte and 263 to 333 K for organic electrolyte. The AC electrochemical cells have been tested using cycling voltammetry (CV) at 25 mV/s sweep rate. This was followed by the step potential electrochemical spectroscopy (SPECS) experiment with a 25 mV potential step and 300 s equilibration time.

SPECS method is based on applying a series of equal magnitude potential steps on a working electrode, with sufficient rest time to allow for equilibrium to be established for each step throughout an applied potential window. This method has been used to effectively differentiate the charge storage contributions from electrical double layer capacitance at the geometric and porous surface areas and diffusion-limited capacitance as a function of scan rate [1].

The outcome of this work indicates the systematic effects of changes in temperature on different charge storage mechanisms. It was expected that the overall electrochemical performance of AC electrochemical cell increases by increasing the temperature in both aqueous and non-aqueous electrolytes, due to increase of kinetic energy of ions in solvent. However, different charge storage mechanism behaved differently in the aqueous and non-aqueous electrolytes. Figure 1. shows the comparison for CV tests (a) in aqueous and (b) in organic electrolytes at different temperatures.

It was found that, the total specific capacitance of AC electrochemical cell is increased by increasing the temperature in aqueous electrolyte. While, in non-aqueous electrolyte, the total specific capacitance decreases by increasing the temperature.

Additionally, SPECS method was used to obtain the contribution of different charge storage mechanisms at different temperatures. The result indicates that the electrical double layer and diffusion limited processes behaved differently in each electrolyte. For instance the capacitance contribution from diffusion-limited processes decreases by increasing the temperature while, the electrical double layer capacitance at the geometric and porous surface areas increases by increasing the temperature in aqueous electrolyte.

Finally, the specific capacitance obtained by the SPECS method was used to obtain the performance of the AC electrochemical cell in the aqueous and non-aqueous electrolytes in the form of a Ragone diagram.

[1]. Marveh Forghani and Scott W. Donne, Journal of the Electrochemical Society 2018 165: A664-A673.

Figure 1
Inherent Area-Selective Growth and Nucleation Enhancement during Ru ALD Using the RuO4-Precursor and H2-Gas
Authors: Minjauw Matthias M. , Rijckaert Hannes , Van Driessche Isabel , Detavernier Christophe , Dendooven Jolien
Published: February 2020

Ruthenium is a candidate to replace copper in future sub-10 nm interconnects. At these dimensions the resistivity of Ru lines is expected to be lower compared to Cu due to the lower sensitivity to size effects.1 In addition, it is likely that Ru interconnects won’t require a diffusion barrier, and will show a better electromigration performance.2 At feature sizes below 10 nm it will be difficult to align subsequent lithography steps, and the conformality of the deposition method is increasingly important, such that area selective atomic layer deposition (ALD) of ruthenium is of high interest.3

We first report inherent area selective ALD of Ru on H-terminated Si (Si-H) versus SiO2, using the thermal RuO4 (ToRuSTM)/ H2-gas ALD process.4 In situ spectroscopic ellipsometry (SE) on blanket substrates shows that Ru growth initiation occurs from the first cycle on Si-H, while on SiO2 the growth is delayed, resulting in a substrate selectivity window of ~ 70 cycles. Area selective Ru ALD was evaluated using a patterned substrate of 1-10 µm wide Si-H lines separated by 10 µm wide SiO2 regions, and exposing it to 20 cycles of the RuO4 / H2-gas ALD process. Ex situ scanning electron microscopy (SEM) and cross section high resolution transmission electron microscopy (HRTEM) measurements show that a 4.5 nm Ru film could be deposited on the Si-H, with no Ru detected on the SiO2. In vacuo X-ray photoelectron spectroscopy (XPS) experiments showed that exposure of Si-H to a single RuO4 pulse leads to the oxidation of the Si surface, together with the deposition of RuO2. On SiO2 however, the surface is already oxidized, and in vacuo XPS shows that for the same exposure to RuO4 no Ru is deposited on the surface. Therefore, we propose that the mechanism behind the inherent substrate selectivity is the oxidation of the Si-H surface by RuO4. Secondly, we report for a methodology to enhance the nucleation of the RuO4 / H2-gas process on oxide substrates. In vacuo XPS and in situ SE experiments show that a single exposure of SiO2 to trimethylaluminum (TMA) makes the surface reactive towards RuO4, which allows for Ru growth initiation from the first cycle. We propose that this is due to the combustion of surface CH3-groups by RuO4. As TMA is known to be reactive towards many oxide substrates, this methodology presents a way to achieve Ru metallization of virtually any surface.

[1] S. Dutta et al. IEEE Elec. Dev. Lett.
2017, 38, 949.

[2] O. V. Pedreira et al
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2017 IEEE IRPS
, Monterey, CA, 6B-2.1.

[3] P. C. Lemaire et al. J. Chem. Phys.
2017, 146, 052811.

[4] M. M. Minjauw et al. J. Mater. Chem. C. 2015, 3, 132.
(Invited) Epitaxial Germanium and Germanium Tin Alloys By Thermal Chemical Vapor Deposition
Authors: Huang Yi-Chiau
Published: February 2020

In this work we will discuss the epitaxial growth of both germanium (Ge) and germanium tin (Ge1-xSnx) by thermal chemical vapor deposition. The focus of the discussion is on the challenges we encountered in the development of a low-temperature process to form a Ge layer with a smooth surface and a reasonably low defect level, a Ge1-xSnx layer in a metastable state, or a Ge/Ge1-xSnx stack structure. Examples of surface roughening, relaxation, intermixing, and segregation are given. Device fabrication from individual Ge/Ge1-xSnx layers and stacks will be mentioned.

For Ge growth on Si, we further discuss the importance of process conditions both to minimize the in-film defectivity and to enhance the surface smoothness. The growth selectivity to various dielectric materials shows some interesting dependence on in situ doping and other growth parameters. The dependence of film properties, such as crystallinity and resistivity, on substrate type, such as silicon, silicon germanium, and germanium, is studied. Growth on patterned Si substrates will also be discussed.

With an optimized low-temperature growth process, Sn can be uniformly distributed in Ge to form a homogeneous phase of Ge1-xSnx. The dependence of growth rate and Sn concentration on the Ge and Sn sources is discussed. Sn concentration up 16% can be achieved with decent film quality on a relaxed Ge layer. Fully strained Ge1-xSnx alloys and Ge/Ge1-xSnx stacks have both been used in the fabrication of electronic and photonic devices. The techniques used in stack formation are discussed together with in situ boron and phosphorus doping of Ge/Ge1-xSnx.
(Invited) Defect Engineering in Ge QDs for Light Emission in Si Photonics
Authors: Brehm Moritz
Published: February 2020

The search for a practical, low-cost and monolithic light source that allows for straightforward implementation on CMOS-based microprocessors and that can be easily coupled to existing active and passive Silicon photonics components is ongoing. In this presentation, we will demonstrate an alternative approach to hybrid III-V on Si and strained bulk group-IV (Ge, GeSn) light emitters. This concept makes use of epitaxially grown Ge quantum dots (QDs) in a defect-free crystalline Si matrix, as they are known since the early nineties [1-3]. However, we will show that the light emission properties of such Ge/Si QDs can be boosted by intentional, low-dose and low-energy implantation of heavy ions (such as Ge and Si) into the QDs. We demonstrate CMOS-compatible lasing from these novel QDs in which defined point-defects states spatially confine electrons after their tunnelling into the nanostructures [1-4]. This leads to optically direct transitions and, hence, efficient light emission. In contrast to conventional epitaxial Ge/Si QDs - these defect-enhanced QDs (DEQDs) exhibit dramatically shortened carrier lifetimes and negligible thermal quenching of the photoluminescence above room-temperature (RT) [1]. Embedding the DEQDs into microdisk resonators leads to lasing characteristics up to RT upon optical excitation [3]. Contact doping and hence fabrication of electrically driven devices is straightforward in this nanosystem since DEQDs are embedded into a defect-free Si matrix. LEDs containing DEQDs show bright emission up to 100°C, the temperature limit of the measurement setup [5].

[1] Grydlik, M.; Hackl, F.; Groiss, H.; Glaser, M.; Halilovic, A.; Fromherz, T.; Jantsch, W.; Schäffler, F.; Brehm, M. ACS Photonics
2016, 3 (2), 298–303

[2] Grydlik, M.; Lusk, M. T.; Hackl, F.; Polimeni, A.; Fromherz, T.; Jantsch, W.; Schäffler, F.; Brehm, M. Nano Lett.
2016, 16 (11), 6802–6807

[3] Brehm M. and Grydlik, M. Nanotechnology
2017, 28, 392001

[4] Groiss H., Spindlberger L., Oberhumer P., Schäffler F., Fromherz T., Grydlik M. and Brehm M, Semicond. Sci. Technol.
2017 32 (2), 02LT01

[5] Rauter P., Spindlberger L., Schäffler F., Fromherz T., Freund J., and Brehm M., ACS Photonics
2018, 5 (2), pp 431–438
(Invited) Scalable, Layer-Controlled Synthesis of 2D Semiconductors
Authors: Chiappe Daniele , El Kazzi Salim , Afanasiev Valeri , Leonhardt Alessandra , Ludwig Jonathan , Celano U. , Brems Steven , Pourtois Geoffrey , Caymax Matty , Schram Tom , Huyghebaert Cedric , Asselberghs Inge , De Gendt Stefan , Radu Iuliana
Published: February 2020

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, transition metal dichalcogenides (TMDs) with a unique layered structure have attracted tremendous interest in recent years mainly motivated by the characteristic 2D nature together with distinctive and tunable optoelectronic properties which make them appealing for a wide variety of applications. Their ultra-thin body nature, in particular, is expected to provide superior immunity to short channel effects therefore extending the potential to scale transistors down to the few-nanometer-scale. [1-4] Another key feature of 2D materials is the absence of surface dangling bonds. The latter property has the potential to eliminate lattice mismatch constraints thus paving the way for hybrid integration of TMDs into artificial heterostructures with sharp interfaces and designed band alignment. As researchers explore the physics and applications of layered semiconductors, it is now becoming important to find a wafer-scale path towards technology implementation and integration of these novel materials.

In this context, it has been recently demonstrated that metal-organic chemical vapor deposition (MOCVD) can be used to manufacture large area 2D semiconductor materials. [5]. The goal of this work is to unravel some of the fundamental aspects of film formation and provide a pathway towards a layer-controlled, wafer-scale synthesis of TMD films. More in details, we will provide insights on the different growth mechanisms of TMD films on amorphous and crystalline templates. In this framework, we will discuss the key aspects to enable and control a real van der Waals epitaxy of TMD films. The target, of course, is to achieve unidirectional and high quality monocrystalline domains by forcing an epitaxial relationship between the 2D film and the underlying substrate. In-depth structural AFM, XPS, TEM analyses along with Raman, Photoluminescence and lifetime measurements are used in our study. In order to establish a direct link between electrical performance and material quality, FET devices using our layers are also fabricated. A careful link between the structural analyses and the electrical results is made in order to asses material quality and offer a step further on the understanding of 2D TMDs for nanoelectronics.

B. Radisavljevic et al. Nature Nanotechnol., 6, 147 (2011).

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A. Nourbakhsh et al. Nano Lett., 16 7798 (2016).

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K. Kang et al. Nature volume 520, 656 (2015)
(Invited) The New Silicon Industry: Silicon CMOS ASICs Incorporating Compound Semiconductors
Authors: Fitzgerald Eugene A.
Published: February 2020

Computation has defined technology leadership in the silicon industry, driving development from bipolars to MOS to CMOS and finally incorporating adaptions like strained Si to continue effective scaling. The previous world of application specific integrated circuits (ASICs) has been largely absorbed into dense digital die with software defining application. As end markets demand IC innovation for product differentiation, de-integration of silicon systems is occurring, as leading edge CMOS nodes for intense computation are not optimized for communication, photonics, or power management. Silicon ICs incorporating III-V LEDs and HEMTs into their design will usher in a new age of high growth ASICs in a variety of different applications.
Metal-Semiconductor-Metal Photodetector with Interdigitated Graphene Finger Electrodes Fabricated on Ge Epilayer Grown on Si Substrate
Authors: Zagarzusem Khurelbaatar , Zumuukhorol Munkhsaikhan , Choi Chel-Jong
Published: February 2020

Based on Ge epitaxial layer grown on Si substrate, we have fabricated metal-semiconductor-metal (MSM) photodetectors (PD) with interdigitated graphene finger electrodes and demonstrated its opto-electrical properties. High quality Ge epitaxial layers were grown on n-type Si (100) wafers with a resistivity of 5 - 15 Ω•cm by using a rapid thermal chemical vapor deposition (RTCVD) method. The monolayer graphene grown on Cu foils using CVD method was transferred onto the cleaned Ge epilayer and was patterned by O2 plasma reactive-ion etching (RIE) process to form interdigitated finger electrodes. From temperature dependent current-voltage (I-V) characteristics, the barrier height of graphene/Ge epilayer Schottky junction was measured to be 0.42 eV, of which value was comparable to the barrier height of graphene Schottky contact to bulk-Ge. The manufactured MSM PD with interdigitated graphene finger electrodes exhibited a considerable spectral response for wavelengths in the range of 1530 – 1560 nm, demonstrating effective photo-detection for the entire C-band (conventional band) spectrum range. On the other hand, for wavelengths > 1560 nm, its responsivity fell off rapidly, which was consistent with the Ge absorption coefficient trend. Under the illumination of incident light with a power of 3.5 mW, the maximum values of responsivity and detectivity at - 2V reverse bias were measured to be 0.35 A/W and 3.86×1010 Jones (cmHz1/2/W) at the wavelength of 1545 nm, respectively.
(Invited) High-Resolution X-Ray Diffraction Characterization and Metrology for Advanced Logic
Authors: Wormington Matthew , Ryan Paul A. , Kasper Nikolai , Gin Peter
Published: February 2020

High-Resolution X-ray Diffraction (HRXRD) is a well-established technique for the characterization and metrology of epitaxial materials encountered in a variety of important technologies such as nano, opto and power electronics. Traditionally the technique was mainly used for blanket films, and this is still a significant application. However, complex epitaxial nanostructures continue to grow in importance to enable advanced CMOS logic transistors that must combine high-performance with low power consumption and cost with scaled dimensions. Hence, the need to measure and analyze such structures becomes necessary. Several new transistor architectures being considered for logic nodes beyond 10 nm, including more sophisticated FinFETs, gate-all-around (GAA) FETs and the use of fully-depleted silicon-on-insulator (FDSOI) substrates. Equally varied is the range of epitaxial materials proposed, which include SiGe, SiP, Ge as well as III-V materials. Each of these innovations has specific challenges for both process development and control. In this presentation we will discuss the recent advances in HRXRD tools, measurements and analysis methods for the characterization and metrology of arrays of nanostructures on patterned wafers with a spot-size < 50 µm and production worthy throughputs and reliability. We will discuss how HRXRD measurements such as high-speed reciprocal space maps (RSMs) are used to determine the composition, strain, and quality of epitaxial nanostructures, and illustrate the challenges and results using representative examples drawn from our recent collaborations.
(Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors
Authors: Loubet Nicolas J , Li Juntao , Chao Robin , Yeung Chunwing , Frougier Julien , Durfee Curtis , Arceo de la Pena Abraham , Muthinti Raja , Bi Zhenxing , Sankarapandian Muthumanickam , Xu Wenyu , Mignot Yann , Sieg Stuart , Conti Richard , Veeraraghavan Basker , Jagannathan Hemanth , Haran Bala , Divakaruni Rama , Bu Huiming
Published: February 2020

Stacked horizontal Gate All Around Nanosheet transistors were recently proposed as a replacement of FinFET for the sub-7nm device nodes. In order to stack Nanosheet channels, a specific SiGe/Si superlattice epitaxy is employed, with SiGe being used as a sacrificial layer that will define the suspension thickness (Tsus) between the channels. In this paper, we will consider the optimization of SiGe/Si multilayer epitaxy for Nanosheet channel definition (Fig. 1). Stacks with different Ge compositions are physically characterized and studied. With strain characterization and x-ray diffraction measurements on (100) substrates, we will show that it is possible to form pseudomorphic defect-free SiGe/Si multilayers over a wide range of Ge concentrations in the sacrificial SiGe (Fig. 2 and 3). The uniformity obtained on blanket 300mm substrates will be presented (Fig. 4), with a discussion on the SiGe/Si interface abruptness. In the context of CMOS device integration, it is necessary to employ a low temperature STI process to mitigate the Ge inter-diffusion in the silicon channel and to avoid the possible generation of defects from plastic relaxation of SiGe. The SiGe and Ge-Si intermixed regions are removed with appropriate selective etch process in two Nanosheet specific modules: inner spacer formation in the extension regions (Fig. 5) and post channel release in the gate regions (Fig. 6), leaving only 5nm intrinsic silicon Nanosheets. We will report the etch rate and selectivity of our in-house vapor-phase channel release process performed at low temperature. This process enables us to remove SiGe versus Si with a great selectivity and a limited amount of silicon loss during channel release, before gate stack deposition around the stacked Nanosheets. From a device perspective, we will show that the optimization of the silicon thickness in the SiGe/Si superlattice plays an important role in the Nanosheet device performance and electrostatics (Fig. 7). Finally, with a good SiGe/Si multilayer uniformity control, a reduced thermal budget and after optimization of our in-house SiGe selective etch process, we will show the capability to form 5nm silicon Nanosheet channels with small within wafer variation, low device variability and good process control, compatible with the fabrication of very large scale integrated circuits for future CMOS device nodes.

Acknowledgements:

This work was performed by the Research Alliance Teams at various IBM Research Facilities.

Figure 1
(Invited) Epitaxy and Applications of Group-IV Semiconductors in Quantum Computing
Authors: Scappucci Giordano
Published: February 2020

The first quantum revolution provided a microscopic understanding of nature and underpinned the development of transistors, originally made in germanium. The following assembly of silicon transistors into integrated circuits triggered the digital age, which completely changed our daily life. We are now in the midst of the second quantum revolution, in which quantum matter is engineered to develop disruptive technologies beyond the reach of classical understanding.

Quantum computing is considered by many the man on the moon goal of such second quantum revolution. How will we get there? In this talk I will discuss, from a materials perspective, how we are turning everyday silicon into the quantum computing wonder material by using quantum dots defined electrostatically in SiGe heterostructures.

Group-IV semiconductors Si and Ge offer several advantages for the realization of spin quantum bits. Si and Ge can be isotopically purified into a nuclear spin free materials, which allows long spin coherence time. A quantum dot defined by metallic gates in a strained Si/SiGe heterostructure can trap a single electron, such that the electron spin can be operated as a quantum bit, the elementary unit of quantum computation. Quantum dots in Si/SiGe heterostructure are promising because bear similarities from a materials and integration perspective to the transistors used in advanced semiconductor manufacturing. Advanced quantum control in Si qubits allows to run quantum algorithms on two qubit processors. Strong spin-photon coupling has been achieved in Si, a first step towards realizing large networks of quantum dot based spin qubit registers.[1] Additionally, SiGe heterostructures allows us to explore high mobility holes in strained Ge as a complementary option for fast quantum hardware due to the different band structure properties of Ge compared to Si. Recently, gate-controlled stable quantum dots were demonstrated in planar Ge, a first step towards Ge hole qubits.[2]

However, to deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. In this talk we will focus on carrier mobility and energetic valley splittings in SiGe heterostructures, which are two key electrical metrics of substrate quality relevant for qubits. To ensure rapid progress in quantum wells development we have implemented fast feedback loops from materials growth, to innovative heterostructure field effect transistor fabrication, and low temperature characterization. In this direction we show progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

[1] N. Samkharadze, G. Zheng, N. Kalhor, D. Brousse, A. Sammak, U. C. Mendes, A. Blais, G. Scappucci, and L. M. K. Vandersypen, Science , eaar4054 (2018).

[2] N. W. Hendrickx, D.P. Franke, A. Sammak, M. Kouwenhoven, D. Sabbagh, L. Yeoh, R. Li, M. L. V. Tagliaferri, M. Virgilio, G. Capellini, G. Scappucci, M. Veldhorst, arXiv:1801.08869 (2018)
(Invited) Compact Telluride Films Prepared By Electrochemical Deposition and Their Applications for Integrated Micro- Thermoelectric Devices
Authors: Li Guodong , Garcia Javier , Sieger Tom , Schnatmann Lauritz Ule , Lara Ramos David Alberto , Barati Vida , Perez Rodriguez Nicolas , Reith Heiko , Schierning Gabi , Nielsch Kornelius
Published: February 2020

Thermoelectric materials of Tellurium (Te) and its based compounds (binary Bi2Te3 and Sb2Te3, or ternary Bi2(TexSe1-x)3 and (BixSb1-x)2Te3) as the n-type and p-type materials, respectively), possess the best thermoelectric figure-of-merit in the temperature range of room temperature up to 200 °C. Preparing thick and compact Telluride films with thickness in the range of tens of micrometers by electrochemical deposition (ECD) allows to realize on-chip integration of thermoelectric devices. ECD offers additional advantages regarding up-scalability, cost effective processing, and compatibility with microelectromechanical systems processing.

In our work, we firstly put efforts on growing thick and compact Telluride films for both n- and p- type materials by ECD technique. Secondly, various measurement techniques (in-situ and ex-situ) are utilized to characterize the thermoelectric transport properties, which are further analyzed to tune the ECD parameters to optimize the material properties. Thirdly, integrated micro- thermoelectric coolers (µTECs), with a leg pair packing density over 5000/cm2 are successfully fabricated by combining conventional techniques of ECD and photolithography. Long-term performance and stability of the as-fabricated µTECs are systematically studied using a CCD-based thermoreflectance imaging setup. Finally, model simulations based on finite-element method show consistency with the experimental results, indicating high quality thermoelectric materials (for both n and p legs) and negligible contact resistances in the as-fabricated µTECs.