bluuebunny/crossref_metadata_2025 huggingface dataset:
Particle-in-Cell Simulation at Low Pressure Oxygen Discharges: Comparison with Experimental Data
Authors: Parada Sergio W. , Pessoa Rodrigo S. , Roberto Marisa , Petraconi Gilberto
Published: October 2010

The structure of molecular oxygen discharge generated by a capacitively coupled reactor was experimentally investigated using a Langmuir probe and the results were compared to the Particle-in-Cell (PIC) simulation. The electron energy distribution functions (EEDF) were measured for a pressure range of 10 to 100 mTorr, keeping the power injected into the plasma at about 50 and 200W. The simulation calculated the EEDFs taking into account three main charged particle species presented in oxygen plasma: electron, O- and O2+. The PIC simulation gives the specie profiles; however is time-consuming for discharges with many species such as oxygen discharges. Despite that, the order of magnitude is the same as the experimental data. The simulation results show that the cold and hot electron temperatures are in a good agreement with the experimental data. Moreover, the results indicate that the EEDFs measured at lower pressures are bi-Maxwellian distributions.
Humidity Sensor Thanks Array of Suspended Gate Field Effect Transistor
Authors: Rodrigues Bruno D. , De Sagazan Olivier , Salaün Anne-Claire , Crand Samuel , Le Bihan France , Mohammed-Brahim Tayeb , Bonnaud Olivier , Morimoto Nilton I.
Published: October 2010

This work deals with a sensor using array of Suspended Gate Field Effect Transistor (SGFET) to measure the relative humidity (%RH). Technics of microtechnology are used to fabricate a polysilicon bridge with a gap de 0,5 µm which acts as transistor gate. Electrical measures have been realized by sampling mode, involving a sensitivity of -5 µA/%. Also the SGFET humidity sensors are very interesting due to the simplicity to polarize and to analyze the output signal.
(Invited) The Silicon Nanowire Accumulation-Mode MOSFETs
Authors: Wu Jian , Garg Pranav , Fonash Stephen
Published: October 2010

The accumulation-mode MOSFET (AMOSFET) is a very simple structured FET configuration which offers the potential for fabricating low cost, high performance FETs on semiconductor nanostructures. The configuration consists of a single doping type silicon nanowire, ohmic source and drain contacts, and a partially gated region. Despite their simple structure, AMOSFETs are capable of showing excellent device characteristics. AMOSFETs fabricated on undoped VLS-grown silicon nanowires exhibit transfer characteristics, with ION/IOFF ratios ~105, and subthreshold swings as low as 150 mV/dev. However, contrary to expectations, AMOSFETs fabricated on intentionally p-type doped silicon nanowires exhibit very poor transfer characteristics; this we attribute to a decrease in conductivity of the doped silicon nanowire upon oxidation. A new device structure, called the AMISFET is demonstrated, which overcomes the problems associated with oxidation of doped nanowires, and is capable of exhibiting good transfer characteristics for FETs fabricated on doped nanowires.
(Invited) Reliability of Polycrystalline Silicon Thin-Film Transistors on the Glass Substrate
Authors: Choi Sung-Hwan , Han Min-Koo
Published: October 2010

We have investigated electrical characteristics of laser-crystallized polycrystalline silicon thin film transistors (poly-Si TFTs) under various stresses such as bias, temperature, light illumination. The threshold voltage of short channel TFT (LCH=1.5μm) was significantly shifted to negative direction due to bias temperature stress (ΔVTH = -3.75V) compared with that of long channel TFT (ΔVTH = -0.32V) at 100{degree sign}C. We have also investigated the effects of light illumination on the laser-crystallized poly-Si TFT. In order to improve the reliability of laser-crystallized poly-Si TFT, a novel multiple-channel structure was proposed and fabricated without any additional processes. In addition, in order to enhance the electric characteristics and stability of alternating magnetic-field-enhanced rapid thermal annealing (AMFERTA) poly-Si TFTs, we have employed the NH3 plasma pretreatment prior to crystallization process. The NH3 plasma pretreatment process could effectively improve the reliability of AMFERTA poly-Si TFTs.
The AC-Bias Stability of Short Channel a-Si:H TFT
Authors: Park Sang-Geun , Lee Soo-Yeon , Woo Jong-Seok , Yoo Juhn-Seok , Han Min-Koo
Published: October 2010

The AC-bias stress was applied at 2um gate length a-Si:H TFT and 4.2um gate length a-Si:H TFT respectively in order to investigate the stability of short channel a-Si:H TFT. The peak voltage of applied AC bias was 7.5 V and the base voltage of it was -7.5 V respectively. The AC bias stress was applied for 100,000 seconds at 60oC. The VTH of short channel a-Si:H TFT was decreased about 0.34V after the AC bias stress while that of long channel a-Si:H TFT was increased about 0.20V. Because the VTH of short channel a-Si:H TFT was less increased than that of long channel a-Si:H TFT during on state period the increase of short channel a-Si:H TFT was compensated more efficiently than that of long channel one at off sate period. Our experimental result showed that the AC stability of short channel a-Si:H TFT was better than that of long channel one.
Enhanced Performance and Thermal Stability of a-Si:H TFTs
Authors: Indluru Anil , Alford Terry L.
Published: October 2010

We report the effect of anneal time on the performance and elevated temperature stability of hydrogenated amorphous silicon (a-Si:H) thin-film-transistors (TFTs). The sub-threshold swing and off-current are reduced by a factor of 2.5 and by almost two orders of magnitude for 48 h annealed TFTs, respectively when compared to unannealed TFTs. Furthermore, long annealed TFTs show significant elevated temperature stability when compared to the unannealed TFTs. The sub-threshold swing, hysteresis, electron mobility, and off-current are stable even at elevated temperatures. For all the TFTs at positive gate bias threshold voltage shift (Vt) follow a power law-dependence with time indicating state-creation mechanism. Life-time values for the 48 h annealed TFT shows improvement by a factor of 3 when compared to unannealed TFTs (when Vt is extrapolated to 10 V). The stability at elevated temperatures and better performance of long annealed TFTs is attributed to improved a-Si:H channel and/or the a-Si:H/insulator interface.
The Influence of Electromechanical Stress on the Stability of Nanocrystalline Silicon Thin Film Transistors Made on Colorless Polyimide Foil
Authors: Chiu I-Chung , Huang Jung-Jie , Chen Yung-Pei , Cheng I-Chun , Chen Jian Z. , Lee Min-Hung
Published: October 2010

Staggered bottom-gate hydrogenated nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs) fabricated on flexible transparent polyimide substrates were investigated. The saturation electron field-effect mobility and electrical bias-stress stability of these TFTs were evaluated under applied tensile mechanical strain parallel to the source-drain direction. The mobilities increased accompanying with deteriorated electrical stabilities as the applied tensile strain increased. The power-law dependence between threshold voltage shift and gate-bias stressing time indicates that the instability is mainly caused by the state creation at the interface between nc-Si:H channel and gate dielectric.
The 1/f Noise Performance for TFTs Fabricated in Three TFT Technologies: Monocrystalline Silicon on Glass, Low Temperature Polysilicon on Glass, and Silicon on Insulator
Authors: Marshall Stephen A. , Nassar Christopher J. , Choi Jae Won , Jang Jin , Kosik Williams Carlo , Mozdy Eric , J. Tredwell Timothy , Bowman Robert J.
Published: October 2010

The 1/f noise characteristics were measured for CMOS devices fabricated in three different process technologies: conventional SOI (SmartCut), monocrystalline silicon on glass (SiOG) and low temperature polysilicon (LTPS). Noise slope and bias current parameters, from the SPICE2 low frequency noise model, were extracted from the 1/f measurements. The SPICE2 noise coefficient parameter, Kf, was extracted for each device. SOI PMOS (which exhibit the least amount of 1/f noise) establish a baseline noise level to compare TFT technologies against. SiOG and LTPS PMOS devices exhibit noise coefficients that were 1.89 and 2.93 times larger than the SOI PMOS device, respectively. The degraded 1/f performance of SiOG and LTPS devices when compared to SOI can be linked to the silicon-silicon dioxide interface trap density. All devices exhibited similar 1/f noise slopes, between 0.8 and 0.98, where processing variations were found to correspond to low slope values.
High Field Induced Stress Suppression of GIDL Effects in Accumulation-Mode P-Channel TFTs
Authors: McCabe Andrew , Manley Robert G. , Couillard J. Gregory , Kosik Williams Carlo , Hirschman Karl
Published: October 2010

By utilizing the effects of high energy, or "hot", electrons the GIDL current in an accumulation mode thin-film PFET can be suppressed. Both SOI and single crystal silicon-on-glass (SiOG) substrates were used to examine this effect. This suppression is proposed to be due to local injection of charge into the gate-oxide at the drain end of the transistor creating a mirror charge in the silicon which mimics an asymmetrical lightly-doped drain structure. An overview of theory, modeling, and device characterization is presented in this study. This effect has been shown to be stable and reproducible; a technique to measure the location and quantity of injected charge is under development.
Capacitance Model for Thin-Film Transistors with Interface Traps
Authors: Tsuji Hiroshi , Kamakura Yoshinari , Taniguchi Kenji
Published: October 2010

A capacitance model for polycrystalline silicon thin-film transistors with large grains is developed. In this model, the influence of traps located at the gate-oxide/silicon interface is taken into account to reproduce the frequency dispersion of the capacitance-voltage characteristics. The results of calculations performed using the developed model are in good agreement with the results obtained from a two-dimensional device simulator over a wide range of interface trap densities.
A Charge Based Compact Modeling Technique for Monocrystalline TFTs on Glass
Authors: Nassar Christopher J. , J. Tredwell Timothy , Kosik Williams Carlo , Revelli Joseph , Bowman Robert J.
Published: October 2010

A thin-film monocrystalline CMOS display technology has been realized by implementing a conventional NMOS inversion device and a PMOS accumulation device. In this paper, a charge based modeling technique is introduced which provides the dc current-voltage characteristics for both inversion and accumulation devices. Since conduction occurs at the surface and in the bulk of accumulation devices, traditional charge sheet models are invalid. Starting directly from the Pao-Sah equation by applying the 1-D Gauss' Law, C-∞ expressions able to capture the effect of both surface and bulk conduction suitable for circuit simulations are derived. The model is validated against the two-dimensional device simulation.
(Invited) A New Insulator for Thin-Film Transistor Backplanes and for Flexible Passivation Layers
Authors: Han Lin , Song Katherine , Wagner Sigurd , Mandlik Prashant
Published: October 2010

We describe a new flexible material that functions as a gate dielectric of amorphous-silicon thin-film transistors, as a passivation layer for plastic substrates, and as an environmental barrier for organic light-emitting diodes. The material is SiO2 with some silicone polymer character. It is deposited, typically at room temperature, from a glow discharge in which a silicone precursor molecule, hexamethyl disiloxane, is oxidized. Films of the material can be made with a broad range of properties, which vary from those of SiO2 to those of plasma-polymerized silicone. Many macroscopic properties of these films suggest that they are homogeneous. We call the films "hybrid."
Characterization of Silicon-on-Glass Substrates Using Variable Angle Spectroscopic Ellipsometry
Authors: Rettmann Ryan D. , Couillard J. Gregory , Hirschman Karl
Published: October 2010

Development of a measurement technique for non-destructive characterization of a new silicon-on-glass (SiOG) substrate is presented. Optical constants for the multi-layer substrate are measured and analyzed, and challenges related to measurement of a transparent substrate are addressed. A formalized method of extracting key layer properties and thicknesses is demonstrated. The technique yields thicknesses for two critical layers, silicon crystallinity, and the dispersion properties of the substrate glass. Flexibility to measure variations in substrate fabrication is also demonstrated.
Using Fluorine-Ion Implanted a-Si Layer to Reduce Ni Contamination and Passivate the Defects in NILC Poly-Si
Authors: Chen Chien-Chih , Wu YewChung S.
Published: October 2010

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have been widely used in active matrix organic liquid crystal displays (AMOLCDs) because their higher carrier mobility and lower threshold voltage than conventional amorphous thin-film transistors (a-Si TFTs). Ni-metal-induced lateral crystallization (NILC) is one of these effective methods that can reduce the crystallization temperature to fabricate poly-Si TFTs on inexpensive glass substrates. However, the poly-Si grain boundaries which included dangling bonds would trap Ni and NiSi2 precipitates. This phenomenon resulted in threshold voltage shifting and lower field-effect mobility. In order to reduce the Ni contamination and passivate the dangling bonds in the active layer, the a-Si layer with fluorine-ion implanted was used as gettering layer (F-G layer) to resolve the issue. In the gettering process, Ni precipitates would diffuse to the fluorine-ion implanted a-Si layer because of the concentration gradation difference. Concurrently, fluorine-ion also diffused into the active layer and passivated the dangling bonds which associated with trap states density.
Improved Electrical Performance of NILC Poly-Si TFTs Manufactured Using H2SO4 and HCl Solution
Authors: Chen Yu-Chung , Chao Yu-Cheng , Wu YewChung S.
Published: October 2010

In this study, we fabricated a NILC surface on a SiO2-coated silicon wafer, and then used HCl solution and H2SO4 + H2O2 solution to do surface treatment. The treatment could reduce Ni or NiSi2 that was trapped at the surface of silicon and therefore the electrical characteristics of these devices were improved.
Improved Performance of NILC Poly-Si Nanowire TFTs by Using Ni-Gettering
Authors: Wang Bau-Ming , Yang Tzu-Ming , Wu YewChung S. , Su Chun-Jung , Lin Horng-Chih
Published: October 2010

Nickel contamination inside nickel-metal induced lateral crystallization polycrystalline silicon is an issue to fabricate high performance nanowire thin film transistors. The phosphorous-doped α-Si/chem-SiO2 films were employed as Ni-gettering layers to investigate effect of Ni residues on the performance of NILC poly-Si NW TFTs. It was found that the performance of NW TFTs was greatly improved after Ni-gettering process.
Electrical Characteristics of a Reduced-Gate Structure Polycrystalline Silicon Thin Film Transistor Using Field-Aided Lateral Crystallization
Authors: You Jung Sun , Lee Kwang Jin , Choi Duck-Kyun , Kim Young-Bae
Published: October 2010

In order to reduce the leakage current in n-channel polycrystalline silicon thin film transistors processed by field-aided lateral crystallization, we applied a reduced gate structure that enables an offset region between the channel and source-drain. The structure in this study was much simpler than those of other methods in the sense that it could accomplish both offset-gate and Ni-offset effects simultaneously without employing any additional masks or processes. The leakage current decreased as the offset region length ΔL per side increased. When ΔL = 2 μm, which corresponded to 10 percent of the total channel length of L = 20 μm, the off-state leakage current decreased to 3.2 pA/μm at VD = 0.1 V and VG = -10 V, which is more than two orders of magnitude lower than that in the conventional structure. In addition to a reduction in leakage current, other device parameters did not change significantly.
High Performance and Reliability of Poly-Si TFTs Using Nickel Drive-In Induced Lateral Crystallization
Authors: Wu YewChung S. , Chang Chih-Pang
Published: October 2010

In this study, polycrystalline silicon thin film transistors using drive-in Ni induced lateral crystallization (DILC) was proposed. In DILC, F+ implantation was used to drive Ni in the α-Si layer. To reduce the Ni contamination, the remained Ni film was then removed, and subsequently annealed at 590°C. It was found DILC TFTs exhibit high field-effect mobility, low threshold voltage, low subthreshold slope, high on-state current, lower trap state density, smaller standard deviations, and low off-state leakage current compared with conventional Ni-metal-induced lateral crystallization (MILC) TFTs.
Characterization and Reliability of Gate-All-Around Poly-Si TFTs with Multinanowire Channels
Authors: Liu Han-Wen , Chiou Si-Ming , Hung Chung-En , Wang Fang-Hsing
Published: October 2010

The electrical characteristics and reliability of n-type gate-all-around (GAA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with multi-nanowire channels are investigated. The multi-nanowire channels are fabricated by the spacer formation technique without any advanced lithography technology. And the GAA structure is constructed after the suspended nanowire is conformally deposited by the gate insulator and in-situ doped poly-Si gate in sequence. Due to the completely surrounding gate, the original electrical characteristics of GAA poly-Si TFTs are superior to that of traditional planar poly-Si TFTs, resulting from the improvement of gate controllability in the short dimensional TFTs. Lower threshold voltage, higher driving current and the suppression of drain-induced barrier lowering (DIBL) and kink effects are exhibited for the GAA poly-Si TFTs with multi-nanowire channels. However, owing to the enlargement of electric field of a spacer with three sharp corners, the GAA poly-Si TFTs suffer from severer hot carrier effect than planar TFTs. No matter what dc or ac hot carrier stress, the degradation of device's electrical parameters of GAA poly-Si TFTs is larger than that of conventional planar poly-Si TFTs.
High Performance Micro-Crystalline Silicon TFT Using Indirect Thermal Crystallization Technique
Authors: Choi Byung Gook , Kim Ki-Tae , Bae Jun Hyeon , Lee Sul , Lee Hong Koo , Kim Sung Ki , Park Kwon-Shik , Kim Chang-Dong , Hwang Yong Kee , Chung In-Jae
Published: October 2010

High performance n-channel micro-crystalline silicon (μc-Si) TFT was fabricated by 5 mask process. Indirect thermal crystallization (ITC) method was applied to crystallize amorphous silicon (a-Si) thin films. ITC technique adopted infrared laser with 808 nm wavelength and heat transition layer of Molybdenum on a-Si. We analyzed the crystallinity of a-Si with the width of crystallization area which is marked by semiconductor laser beam on the surface of a-Si films. Crystallinity of μc-Si films was calculated by Raman spectra and it shows correlation of field effect mobility with crystallinity fraction. In this study, we presented field effect mobility of 6.2 cm2 /Vs and sub-threshold slope of 0.41 V/dec. And bias temperature stress characteristics confirmed the reasonable reliability of device employing ITC technique compare to that of a-Si TFT.
Electrical and Mechanical Behaviors of Microcrystalline TFTs Deposited on PEN
Authors: Janfaoui Sabri , Kandoussi Khalid , Simon Claude , Coulon Nathalie , Crand Samuel , Mohammed-Brahim Tayeb
Published: October 2010

Coplanar N-type TFTs are fabricated at low temperature T<180{degree sign}C on a plastic PEN (Polyethylene naphthalate) substrate. Then, these TFTs are electrically characterized to extract their parameters. TFTs are bended at different radius of curvature R. Mobility field effect increases when the radius of curvature decreases. TFT present characteristics up to R = 1 cm, beyond it characteristics fall down. Conductivity increases also when bending the undoped µc-Si:H film only.
Influence of Bank Structure on the Film Morphology and Electrical Properties of Ink-Jet Printed TIPS Pentacene Thin-Film Transistors
Authors: Kim Yong-Hoon , Oh Min-Suk , Park Sung Kyu , Han Min-Koo
Published: October 2010

The effects of bank geometry on the morphology of ink-jet printed TIPS pentacene channel layer and electrical properties of TFT devices. It was found that the size and shape of the bank had a significant influence on the film morphology as well as the electrical properties of transistors. It is suggested that a specific bank shape and size have to be selected considering the ink-jet drop volume and solid concentration.
Improved Performance of Pentacene OTFT with HfLaO Gate Dielectric by Annealing in NH3
Authors: Deng Linfeng , Lai Pui To , Xu Jingping , Choi H. W. , Chen Weibing , Che Chi Ming
Published: October 2010

Pentacene organic thin-film transistors with HfLaO as gate dielectric were fabricated. The dielectric was prepared by sputtering method with a dielectric constant over 11, and hence the OTFTs could operate at a voltage less than 5 V. The dielectric was annealed in N2, NO or NH3 at 400 oC after sputtering to passivate the surface of the dielectric. The OTFT treated in NH3 displayed higher carrier mobility, smaller sub-threshold swing, and lower 1/f noise than the OTFTs annealed in N2 and NO respectively. SEM image indicated that pentacene inclined to form larger grains on the dielectric annealed in NH3 than the dielectric annealed in N2 or NO. The enhanced electrical performance of OTFTs annealed in NH3 can be attributed to the improved interfacial characteristics between the organic film and the gate dielectric.
Low Temperature, High-Performance, Solution-Processed Indium Oxide Based Thin Film Transistors
Authors: Han Seung-Yeol , Herman Gregory , Chang Chih-hung
Published: October 2010

Indium oxide (In2O3) and indium zinc oxide (IZO) thin film transistors (TFTs) were fabricated by spin-coating metal halide-acetonitrile precursor solutions for the active device layer. We have evaluated the effect of annealing temperature and annealing environment on TFT performance with the focus on lower temperature processing and directly comparing the influence of air and O2/O3 ambient conditions. Field effect mobilities for In2O3 and IZO TFTs annealed at 500 {degree sign}C in air resulted in values of 55.26 and 6.06 cm2/V•s with Ion/off of 107, respectively. The In2O3 and IZO TFTs annealed in O2/O3 environments at temperature < 300 °C resulted in excellent n-type transistor behavior with field effect mobilities > 0.84 cm2/V•s and Ion/off of >105. We have demonstrated that high-performance metal oxide TFTs can be achieved with low processing temperatures by annealing in an O2/O3 atmosphere.
Low Temperature Solution-Processed Zinc Tin Oxide Thin Film Transistor with O2 Plasma Treatment
Authors: Lee Jeong-Soo , Kim Yong-Jin , Lee Yong-Uk , Cho Seung-Hwan , Kim Yong-Hoon , Kwon Jang-Yeon , Han Min-Koo
Published: October 2010

We fabricated solution-processed ZTO TFTs at annealing temperature of 350 °C with employing O2 plasma treatment on active layer in order to improve the electrical characteristics of ZTO TFTs fabricated at low temperature. Threshold voltage of solution-processed ZTO TFTs without plasma treatment was larger than 35 V but reduced to 20.74 V with 15 ml/min and 300 W of O2 plasma treatment since oxygen vacancies in ZnO⋅SnO2 and SnO2 would increase and then electron concentration are also increased by ion bombardment from O2 plasma treatment. Saturation mobility and Subthreshold Swing (S.S) of TFTs without plasma treatment was 0.09 cm2/V⋅sec and 1.65 V/decade respectively, but saturation mobility increased to 0.58 cm2/V⋅sec and S.S decreased to 1.20 V/decade, respectively, with 15 ml/min and 300 W of O2 plasma treatment, since ZnO⋅SnO2 is produced which could work as semiconducting material, rather Zn(OH)Cl is vanished which could work as impurity by O2 plasma treatment.
The Electrical Properties of Atomic Layer Deposition of ZnO:N Thin Film Transistors by Ultraviolet Exposure
Authors: Kim Jae-Min , Lim S. J. , Kim Hyungjun
Published: October 2010

We investigated the ultraviolet (UV) light photostability of nitrogen doped atomic layer deposition (ALD) ZnO:N thin film transistor (TFT). ALD ZnO:N thin films were used as active layers for back-gate TFT devices. The as-fabricated ALD ZnO:N TFT grown at 125 °C shows proper drain current modulation by gate voltage sweep with 5.4 V of threshold voltage and clear pinch-off. However, the threshold voltage was significantly shifted to negative direction by UV exposure due to the increment of carrier concentration, producing the TFT device with no modulation by gate voltage. In addition, we observed the resistivity change of ALD ZnO:N thin films with time after UV exposure. The resistivity decreased by UV light exposure from 1581 to 4.532 Ω cm and then it recovered toward its original value after switching off UV light. Accordingly, the transfer curves of TFT device using ZnO:N active layer were also exhibited recovery characteristics. We adopted a thin Al2O3 passivation layer on the top surface of TFT and observed that the recovery effect was effectively suppressed.
The Stability of Oxide TFTs under Electrical Gate Bias and Monochromatic Light Illumination
Authors: Lee Soo-Yeon , Kim Sun-Jae , Lee Young-Wook , Park Sang-Geun , Kwon Jang-Yeon , Han Min-Koo
Published: October 2010

We have investigated a stability of oxide TFTs (IGZO) under electrical bias and monochromatic light illumination. Under -20 V gate bias, when 650 nm monochromatic illumination with intensity of 1 mW/cm2 was radiated, threshold voltage (Vth) was shifted by about -1.55 V while Vth was almost constant without illumination. Even though the photon energy of 650 nm is much smaller than optical band gap of oxide active layer (Eopt~3.0 eV), Vth was changed due to generation of carriers through localized state. However, under positive gate bias of 20 V, Vth was not changed with and without 650 nm light illumination. In terms of 300 nm wavelength light, Vth was shifted positively under negative bias stress and negatively under positive bias stress. It is considered that light affected not only the active layer but also the gate insulator layer.
Study of the Effect of Electrical Stress on ZnO TFTs
Authors: Su Liang-Yu , Lin Hsin-Ying , Wang Sung-Li , Yeh Yung-Hui , Cheng Chun-Cheng , Peng Lung Han , Huang JianJang
Published: October 2010

In this paper, the stability of threshold voltage (Vth) of ZnO thin film transistors (TFTs) fabricated on the glass substrate was examined under a 20V gate bias stress. The device demonstrates a significant reduction of the threshold voltage shift (ΔVth) around 2.2V after a stress time up to 1.3×104s. The characteristic trapping time of carriers (τ) around 1.26×106s was extracted by fitting into the stretch-exponential time dependence relationship. An effective energy barrier for trapped carriers Eτ of 0.57eV was also obtained. The mechanism of threshold voltage instability was mainly attributed to charge trapping at the ZnO/a-SiNx interface, which can be effectively annealed out by post thermal annealing under 400° condition.
Characteristics of Zinc Oxide Thin Film Transistors Fabricated by Location-Controlled Hydrothermal Method
Authors: Yang Po-Yu , Wang Jyh-Liang , Tsai Wei-Chih , Wang Shui-Jinn , Chen Po-Chih , Su N. C. , Lin J. C. , Lee I-Che , Chang Chia T. , Wei Yin-Chang , Cheng Huang-Chung
Published: October 2010

In this paper, high-performance Zinc oxide (ZnO) thin-film transistors (TFTs) with bottom-gate (BG) structure and artificially location-controlled lateral grain growth have been prepared by low-temperature hydrothermal method. As the proper design of source/drain structure of ZnO/Ti/Pt thin films, the lateral grain growth can be artificially controlled in the desired location and the vertical grain boundary perpendicular to the current flow in the channel region can be reduced to single one. As compared with the conventional sputtered ZnO BG-TFTs, the proposed location-controlled hydrothermal ZnO BG-TFTs (W/L = 250 µm/10 µm) demonstrated the higher field-effect mobility of 6.09 cm2/V•s, lower threshold voltage of 3.67 V, larger on/off current ratio above 106, and superior current drivability, which can be attributed to the high-quality ZnO thin films with the reduced vertical grain boundaries in the channel region.
(Invited) Mechanism and Performance of Floating-Gate a-Si:H TFT Nonvolatile Memory Devices
Authors: Kuo Y.
Published: October 2010

The floating-gate a-Si:H thin film transistor provides the memory function that is not available with the conventional a-Si:H thin film transistor. Mechanisms of charge trapping and detrapping in the floating-gate a-Si:H TFT are discussed based on the transfer characteristics curve. Influences of two critical factors, i.e., the starting gate voltage of the forward transfer characteristics and the channel-contact layer thickness, on the memory window were investigated. The amount of electrons trapped to the gate dielectric layer is dependent on the maximum gate voltage at the end of the forward curve but independent of the original amount of holes trapped. The memory window can be well defined when no excessive holes are trapped to the gate dielectric layer in the forward curve.
Amorphous Oxide Semiconductor Memory Using High-k Charge Trap Layer
Authors: Rha Sang-Ho , Jung Ji Sim , Kim Jeong Hwan , Kim Un Ki , Chung Yoon Jang , Jung Hyung-Suk , Lee Sang-Yoon , Hwang Cheol Seong
Published: October 2010

Amorphous oxide semiconductor memory devices with HfInZnOx as the channel layer and high k dielectric stacks as the charge storage medium were fabricated. HfO2 and Al2O3 and HfAlOx films were examined as the charge trap layers. The drain current - gate voltage transfer curves of the fabricated charge trap memories show a large hysteresis due to the electron trapping and de-trapping at the interfaces between the high-k charge storage layer and the SiO2. The device structure and operational scheme for the amorphous oxide semiconductor charge trap memories were suggested based on these properties.
(Invited) Towards EPC Compatible Plastic RFID Tags
Authors: Myny Kris , Steudel Soeren , Vicca Peter , Smout Steve , Beenhakkers Monique J. , Van Aerle Nick A.J.M. , Furthner François , Van der Putten Bas , Tripathi Ashutosh K. , Gelinck Gerwin H. , Genoe Jan , Dehaene Wim , Heremans Paul
Published: October 2010

A target application for plastic RFID tags is Electronic Product Coding (EPC). The EPC-specifications set some demanding requirements for RFID tags. In this work, we review the work that has been done to fulfill some of these specifications. We describe a complete 64-bit RFID tag that is inductively-coupled at a base carrier frequency of 13.56 MHz, and transmits data at rates below 1 kb/s. Next, we demonstrate 8-bit RFID transponder chips having data rates of 50 kb/s, an important milestone for organic RFID tags in view of EPC specifications.
Polysilicon Source-Gated Transistors for Mixed-Signal Systems-on-Panel
Authors: Sporea Radu A. , Guo Xiaojun , Shannon J. M. , Silva S. Ravi P.
Published: October 2010

The performance benefits of using source-gated transistors (SGTs) in large-area analog electronic circuits are examined by both experiments and numerical simulations. As one of the key blocks in analog electronics, the current mirror circuit is taken as an example in the investigation. A comparison of current mirrors implemented with standard field effect transistors (FETs) and SGTs shows that the SGT based circuits can operate at a lower voltage and has larger output dynamic range for a given device geometry. The results are explained in relation to the saturation mechanisms of the SGT and are supported by experimental measurements of polysilicon devices.
Physical and Electrical Properties of MOCVD and ALD Deposited HfZrO4 Gate Dielectrics for 32nm CMOS High Performance Logic SOI Technologies
Authors: Kelwing Torben , Mutas Sergej , Trentzsch Martin , Naumann Andreas , Trui Bernhard , Herrmann Lutz , Graetsch Falk , Klein Christoph , Wilde Lutz , Ohsiek Susanne , Weisheit Martin , Peeva Anita , Richter Inka , Prinz Hartmut , Wuerfel Alexander , Carter Rick , Stephan Rolf , Kücher Peter , Hansch Walter
Published: October 2010

The physical properties of metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) deposited HfZrO4 films have been analyzed in detail by atom probe tomography, X-ray photoelectron spectroscopy, Rutherford backscattering spectrometry, transmission electron microscopy, atomic force microscopy, variable angle spectroscopic ellipsometry as well as temperature dependent grazing incidence X-ray diffraction. In addition we extend our recently presented electrical 32nm device results with MOCVD and ALD deposited HfZrO4 gate dielectrics by further evaluating 32 nm high performance logic devices on silicon on insulator (SOI) substrates with respect to interface trap charge densities Dit and time dependent dielectric breakdown (TDDB) reliability. All investigated parameters revealed a comparable behavior between ALD and MOCVD and therefore MOCVD is demonstrated to be a promising alternative to ALD in high volume manufacturing in this work.
Alternative High-k Dielectrics for Metal-Insulator-Metal Applications
Authors: Lukosius Mindaugas , Baristiran Kaynak Canan , Wenger Christian , Rushworth Simon
Published: October 2010

Atomic Vapor Deposition (AVD) technique was successfully applied for the depositions of amorphous HfO2, Sr-Ta-O and Ti-Ta-O thin films, which were investigated as alternative dielectrics to replace the standard SiO2 or Si3N4 dielectrics used in Metal-Insulator-Insulator (MIM) capacitors. Metal oxides were grown on 200 mm TiN/Si (100) substrates within the thermal budget of back-end-of-line (BEOL) process. Electrical properties, investigated after sputtering Au top electrodes, revealed that the main characteristics are different for each dielectric. On one hand, Ti-Ta-O based MIM capacitors possessed a dielectric constant of 50, which is more than a factor of 2 higher compared to the ones of Sr-Ta-O (20) and HfO2 (18). On the other hand, Sr-Ta-O based MIM capacitors showed the lowest leakage current densities as well as the smallest capacitance-voltage linearity coefficients.
(Invited) Issues on Interfacial Oxide Layer (IL) in EOT Scaling of High-k/Metal Gate CMOS for 22nm Technology Node and Beyond
Authors: Park Chang Seo , Kirsch Paul D.
Published: October 2010

According to the International Technology Roadmap for Semiconductors (ITRS), scaling to the 22 nm technology generation and beyond is facing significant challenges related to the timely implementation of high-k/metal gate stacks, including appropriate tuning of the metal gate work function, adequate channel mobility, and reliability. Scaling equivalent oxide thickness (EOT) becomes more challenging as it will reflect interfacial oxide layer (IL) scaling causing some issues such as mobility degradation and difficulty in achieving PMOSFET Vt target. This paper discusses issues on IL in the scaling the EOT of high-k/metal gates tacks.
The VFB Modulation Effect of ALD Grown Al2O3, SrO, La2O3 Capping Layers with HfO2 Gate Dielectrics
Authors: Lee Sang Young , Jung Hyung-Suk , Kim Hyo Kyeom , Lee Sang Woon , Choi Yu Jin , Hwang Cheol Seong
Published: October 2010

The effect of atomic layer deposited Al2O3, SrO, and La2O3 capping layers with HfO2 gate dielectrics were examined ffor flat band voltage (VFB) modulation. Al2O3 capping layers cause a VFB shift into the positive voltage direction, while SrO and La2O3 capping layers cause a shift into the negative voltage direction. The bottom capping layer, which positions between the Si substrate and the HfO2 dielectric was more effective in modulating the VFB compared to the top capping layer. The insulating properties of the gate dielectric stacks with different capping layers were also examined. X-ray photoelectron spectroscopy analysis verified that top capping layers did not generally diffuse to the interface between the Si substrate and the HfO2 dielectrics, which supports the result that bottom capping layers are more effective in modulating the VFB.
Role of Hetero Interface of Ionic/Covalent Oxides for Pt/High-k/SiO2/Si MOS Capacitors on Vfb Shift
Authors: Nabatame Toshihide , Ohi Akihiko , Chikyow Toyohiro
Published: October 2010

We have investigated the role of hetero interface of ionic high-k / covalent SiO2 for Pt gate MOS capacitors with strong and weak ionic high-k dielectrics on Vfb shift. The HfO2-based high-k and HfSiON materials of the strong ionic oxide caused the positive Vfb shifts due to dipole, while the Vfb of the HfSiOx-based high-k materials of the weak ionic oxide was almost constant. These suggest that the ionicity of high-k materials is an important because the oxygen diffusion which is related to the dipole formation strongly depends on the ionicity.
Impact of Alkali-Earth-Elements Incorporation on Vfb Roll-Off Characteristics of La2O3 Gated MOS Device
Authors: Koyanagi Tomotsune , Kakushima K. , Ahmet P. , Tsutsui K. , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori T. , Iwai H.
Published: October 2010

The impacts of Mg, MgO, CaO, SrO or BaO incorporation on La2O3 MOS devices have been examined. Roll-off behavior in the flat-band voltage (Vfb) of the MOS capacitors on equivalent oxide thickness (EOT) has been observed. The roll-off characteristic has been suppressed with Mg incorporation. On the other hand, with MgO, CaO, SrO or BaO incorporation, the characteristic has been enhanced. Interface-state density (Dit) has slightly increased and leakage-current density (Jg) has unchanged with the incorporation.
Optimizing Band-Edge High-κ/Metal Gate n-MOSFETs with ALD Lanthanum Oxide Cap Layers: Oxidant and Positioning Effects
Authors: Clark Robert D. , Jagannathan Hemanth , Consiglio Steve , Jamison Paul , Wajda Cory , Edge Lisa , Paruchuri Vamsi , Narayanan Vijay , Leusink Gert
Published: October 2010

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.
(Invited) Tip Cleaning and Sample Design for High Resolution MOSCAP x-KPFM
Authors: Melitz Wilhelm , Shen Jian , Lee S. , Lee J.S. , Royer J.E. , Bentley Steven , Macintyre Douglas , Holland Martin , Thayne Iain , Kummel Andrew C.
Published: October 2010

Kelvin probe force microscopy (KPFM) is a unique technique that can provide two dimensional potential profiles inside a working device. A procedure is described to obtain high-resolution KPFM results on ultra-high vacuum (UHV) cleaved III-V MOSCAPs. Two tip preparation methods: field emission and Cr coating show reproducible high spatial and energy resolution KPFM images. A unique sample design has been developed which is compatible with UHV cross-sectional KPFM (x-KPFM). Key design features are high density of devices on the cleave face, a buried device interface, and a cleavable gate contact. Using x-KPFM, the first UHV cleaved MOSCAP surface potential mapping is demonstrated.
Bonding Geometries at the In2O and SiO/III-V Semiconductor Interface
Authors: Shen Jian , Melitz Wilhelm , Feldwinn Darby L. , Lee Sangyeob , Droopad Ravi , Kummel Andrew C.
Published: October 2010

Oxide monolayers and submonolayers formed by vapor depositon of In2O and SiO oxides on InAs(001)-(4x2) were studied by scanning tunneling microscopy (STM). At low coverage, In2O molecules bond to the edges of the rows and most likely form new In-As bonds to the surface without any disruption of the clean surface structure. Annealing the In2O/InAs(001)-(4x2) surface to 380åC results in formation of flat ordered monolayer rectangular islands. The annealed In2O no longer bonds with just the As atoms at the edge of row but also forms new O-In bonds in the trough. SiO chemisorption on InAs(001)-(4x2) is completely different than In2O chemisorption. At room temperature, even at low coverage SiO adsorbates bond to themselves and form nanoclusters. For SiO/InA(001)-(4x2) post-deposition annealing (PDA) does not disperse the nanoclusters into flat islands. Both In2O and SiO depositions on InAs(001)-(4x2) surface do not displace surface atoms during both room temperature deposition and PDA.
(Invited) Electronic and Structural Properties at Ge/GeO2 Interfaces: A Density-Functional Investigation
Authors: Broqvist Peter , Binder Jan Felix , Pasquarello Alfredo
Published: October 2010

The electronic and structural properties at the Ge/GeO2 interface are addressed through a density-functional simulation scheme, which includes the use of hybrid functionals for achieving defect levels and band gaps comparable to experiment. The present work discusses the determination of the germanium dangling bond levels, the band alignment in a model structure of the Ge/GeO2 interface, the thermodynamics of GeOx, the stability of the oxygen vacancy across Ge/GeOx/HfO2 stacks, the structural and electronic properties of GeOx, and its ability to trap electrons.
Evaluation of Narrow Gap Filling Ability in Shallow Trench Isolation by Organosiloxane Sol-Gel Precursor
Authors: Watanuki Kohei , Inokuchi Atsutoshi , Banba Akinori , Manabe Nobuyuki , Suzuki Hirokazu , Koike Tadashi , Adachi Tastuhiko , Goto Tetsuya , Teramoto Akinobu , Shirai Yasuyuki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: October 2010

High quality SiO2 film formation in the narrow trench pattern is important for many applications such as large scale integration (LSI) circuit and micro electro mechanical system (MEMS) industry. We have evaluated the process conditions, electrical properties, structural characteristics, and gap filling abilities of SiO2 film using organosiloxane-based silica sol-gel precursor derived from the mixture of tetraethoxysilane (TEOS) and methyltrimethoxysilane (MTMS) by changing the molar ratio of TEOS/MTMS. This sol-gel precursor was converted to high quality SiO2 film by optimizing baking conditions. The SiO2 film from this sol-gel precursor has excellent dielectric characteristics of low leakage current density and high breakdown voltage whose values are comparable to those of thermal oxide SiO2 film. In addition, the breakdown field intensity of these films was improved by adding a small amount of metal oxide such as TiO2, HfO2, and ZrO2. Furthermore, by introducing the optimum pressure (<26666 Pa) in the oxidation baking process, the film has excellent surface planarization and uniformly gap filling abilities of narrow trench pattern without void formation
Development of Lanthanide Precursors as Dopants for Advanced High-k Materials
Authors: Rao Venkateswara P. , Besancon Brian , Omarjee Vincent , Dussarrat Christian
Published: October 2010

In an effort to replace SiO2 as a gate dielectric, many high-k materials are under evaluation. Rare earth oxides have demonstrated potential to be used as dopants in electronic devices such as gate oxides in CMOS transistors or in DRAM trench capacitors. This interest is motivated by their relatively high-k value and their compatibility with silicon. This work evaluated several lanthanide precursors by TGA and DSC to determine their thermal properties and select promising molecules to be tested in atomic layer deposition (ALD). Then, important process characteristics such as growth rate and process window were then evaluated by ALD. Relatively high growth rates were observed varying from 0.37 A/cycle with Pr(EtCp)3 to 0.65 A/cycle with Dy(iPrCp)3. No obvious trend for the growth rate as a function of the atomic number was found.
Methodology of ALD HfO2 High-κ Gate Dielectric Optimization by Cyclic Depositions and Anneals
Authors: Jagannathan Hemanth , Clark Robert D. , Consiglio Steve , Jamison Paul , Linder Barry , Hopstaken Marinus , Leusink Gert , Paruchuri Vamsi , Narayanan Vijay
Published: October 2010

This paper presents the optimization of HfO2 high-κ gate dielectrics by utilizing cyclic depositions and anneals during atomic layer deposition (ALD). An order of magnitude reduction in gate leakage is obtained by tuning the anneal temperature, duration and sequence in the ALD. The films are also seen to have three to four times reduction in carbon content. These optimized films are moreover observed to be densified without compromising equivalent oxide thickness (EOT), carrier mobility and threshold voltage. Further electrical characterization supports that there is a suppression of trap assisted tunneling with the optimized ALD process by revealing a stronger temperature dependence on the annealed samples as opposed to the conventional ALD process.
Synthesis of LaxAl2-xO3 Films Using Ultrasonic Spray Pyrolysis Technique
Authors: Meza-Rocha Abraham N. , Pérez-Arrieta Leticia , Zaleta-Alejandre Efrain , Rivera Zacarias , Balderas-Xicohténcatl Rafael , Falcony Ciro
Published: October 2010

The synthesis of LaxAl2-xO3 films using ultrasonic spray pyrolysis technique are reported. The films were deposited from a spraying solution of aluminum acetylacetonate (Al(acac)3) and lanthanum(III) nitrate hexahydrate La(NO3)36H2O dissolved in N,N-Dimethylformamide on (100) Si substrates. The substrate temperature during was in the range 500-600°C. The mean roughness was lower than 18 Aå in all cases. The films were amorphous in all cases. The optical band gap was 5.42 eV and the refractive index was in the 1.64-1.72 range depending of the deposition conditions.
Comparison of HfSiOx Thin Films Deposited by ALD with Moisture Using Different Silicon Sources
Authors: Besancon Brian , Weiland Conan , Omarjee Vincent , Rao Venkateswara P. , Dussarrat Christian
Published: October 2010

The scaling of semiconductor devices using various high-k materials has been investigated, and replacing the standard SiO2 gate dielectric by high-k material was a major step. Hafnium-based material is currently one of the preferred candidates. To improve integration of Hafnium into the gate dielectric, HfSiOx has been chosen for low power devices while HfZrOx is more common for high-performance applications. Using widely available processes, HfO2 can be deposited using amine or alkoxide based compounds and different reducing agents such as ozone, oxygen or moisture. However, depositing HfSiOx by Atomic Layer Deposition (ALD) with moisture is more challenging. Few or no available Silicon precursors are reactive with H2O alone to deposit SiO2 by ALD. This work is intended to present precursor solutions to deposit hafnium silicate using moisture as oxidant.
Electronic Properties of Silicene: Insights from First-Principles Modelling
Authors: Houssa Michel , Pourtois Geoffrey , Heyns Marc M. , Afanas'ev Valeri V. , Stesmans André
Published: October 2010

The electronic properties of two-dimensional hexagonal silicon (silicene) are investigated using first-principles simulations. Though silicene is predicted to be a gapless semiconductor, due to the sp2-hybridization of the Si atoms, the weak overlapping between their 3pz orbitals leads to a very reactive surface, resulting in a more energetically stable semiconducting surface upon the adsorption of foreign chemical species. It is predicted that silicene inserted into a graphite-like lattice, like ultrathin AlN stacks, preserves its sp2-hydridization, and hence its graphene-like electronic properties.