bluuebunny/crossref_metadata_2025 huggingface dataset:
Optimization of Lead Free Plating for Flip Chip Applications
Authors: Arvin Charles L. , Stahl Jurg , Sauter Wolfgang , cox Harry , Perfecto Eric , Oberson Valerie , Normand Nathalie
Published: October 2015

Traditional flip chip processes have consolidated to a SnAgCu (SAC) solder system. Each company based upon their own needs and application space has come to their own method to achieve the desired final composition of the interconnect. These have included different solder compositions for both the pre-solder and the C4. The various interconnect solutions can range from no solder on one side such as pure Cu or Ni to an interconnect that has identical solder composition for both the substrate and the C4.

Decisions for the optimized solution include the need for reliability, cost and yield. Picking the right solution also enables the elimination of defects such as solder voids, interfacial voids, white bumps, micro-solder bumps and non-wets. The optimized solutions are dependent upon many factors that include the fragility of the silicon dielectric, the size of the die, type of flux used at assembly, the assembly process used, method by which SnAg is plated such as various layering techniques, final processes steps in C4, test probe concepts, DSP methods and many more. In order to pick the appropriate scheme for each product and for each industry, it is imperative to know the interaction of all of these factors.

This paper provides concepts and data about how to optimize assembly and lead free plating for a particular process. In the plating process, this includes the importance of various layering steps and analysis of incoming chemicals, especially the acids, and in the assembly process, the knowledge and matching of solder hierarchy, warpage, flux characteristics and preparation / cleaning steps prior to underfill. In particular, we will provide the data and the scheme by which it is possible to produce void free solder processes without bleed and feed on SnAg baths that are over 100 amp-hr per liter and over 1 year old.
A Decade of High Accuracy Die Attach Equipment and Process Developments (Addressing Photonics Device Packaging Challenges)
Authors: Weinhaendler Johann , Kaiser Rudolf , Kellermann Hardy
Published: October 2015

Fueled by the Internet and nowadays unlimited connectivity expectations, the assembly of optoelectronic packages became a key element to enable the explosive growth in the communication field around the entire globe.

The primary challenge in the field of advanced optoelectronics and photonic device packaging (e.g. laser diodes, VCSEL's, optical benches, lenses etc.) is to accurately align the different optical components in reference to each other for optimal optical device performance. This growing need for high precision die attach (<= 0.5um @ 3 sigma) systems and solutions at the shortest possible cycle times has been studied and implemented by AMICRA Microtechnologies. AMICRA's state of the art high accuracy automated assembly system solutions have been successfully used for over a decade in both a laboratory setup and a high volume manufacturing environment.

From handling a large variety of substrate materials, thin and fragile chips with odd aspect ratios, lenses and other components, the flexible and dynamic vision alignment concept and the bonding process controls required to achieve high overall component placement accuracies has been AMCIRA's industry focus since the company's inception. While significant progress has been made to provide solutions for all communications and photonics applications there are currently still some challenges out there to be overcome, challenges that can also change on an application by application basis. Besides the technical challenges the cost effectiveness or cost per bond for those applications is a very critical overall success factor as well.

This paper will elaborate on manufacturability concerns and equipment automation challenges associated with the key parameters of a Photonics applications high accuracy die attach process which, amongst others, not only require highly sophisticated vision alignment algorithms but also thermal transfer processes either using an eutectic process or a laser soldering technique.

Given the ever shrinking packaging form factors, all of AMICRA's research and developments in the Photonics field have also been successfully introduced and applied in more traditional semiconductor applications which have an increasing need for high accuracy die attach.
A New Method for Testing Electrolytic Capacitors to Compare Life Expectancy
Authors: Gulbrandsen Stephani , Arnold Joelle , Kirsch Nick , Caswell Greg
Published: October 2015

Power system applications, such as street lighting, typically have a 10 year warranty. When these systems include electrolytic capacitors, it is important to choose a supplier that meets these requirements. Traditional lifetime testing of electrolytic capacitors to ascertain their life expectancy requires specialized equipment, is time consuming, labor intensive, and for most OEMs, is ultimately cost prohibitive.

Electrolytic capacitors with the same capacitance and voltage ratings from different suppliers may be rated to the same lifetime, but historical data confirms that they can have significantly different operational expected lives. An accelerated testing methodology is needed to compare the reliability of electrolytic capacitors from different suppliers.

DfR has developed an approach that reduces test times from thousands of hours to several weeks by taking advantage of two key behaviors of electrolytics. The first involves the rate at which capacitors lose electrolyte, which is fairly predictable at a given temperature and electrical stress. The second key behavior is the dependence of the equivalent series resistance (ESR) of electrolytic capacitors on the volume of liquid electrolyte.

The approach that will be described in this paper will demonstrate a means of comparing the time to failure for comparable capacitors from different suppliers under the same conditions. Case studies will demonstrate how this method avoids the extended testing that is typically required.
SiPs in the medical domain and in the defense and industrial domain produced with WDoDTM technology
Authors: COUDERC Pascal , NOIRAY Jérôme
Published: October 2015

Based on Wire free Die on Die disruptive technology (WDoDTM), complex SiPs can be manufactured in a small factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices (1).

Wafer processing is done with e-WLB technology and a specific redistribution layer (RDL) is designed to match with 3D PLUS bus metal edge interconnect technology. 300 mm rebuilt wafers are processed and thinned down to 200 μm before stacking and polymer bonding. Bonding alignment is within ±5 μm allowing small lateral pitches demonstrating WDoDTM versatility with denser IO products such as FPGA. Besides, this new process integration scheme allows the stacking of both conventional boards with SMDs not available at wafer level together with rebuilt wafers made of known good dies.

WDoDTM technology has been successfully used with different kind of products in the defense and medical markets.

A calculator node including a 484 I/O FPGA with 2 mDDR and an EEPROM in addition to more than 150 decoupling capacitors was manufactured and is exhibiting better electrical performance when compared to the 2 dimensions version.

Moreover, a medical implant has been successfully developed embedding 2 ASICS and several PICS capacitors allowing an 8 times shrink of the electronics compared to advance lead based pacemakers..

With this new technology, 3D PLUS is highlighting the way to highly integrated System in Package (SiP) and demonstrates its know-how in the three dimensional integration.
An In Situ Atmospheric Probe for Real Time Weather Monitoring
Authors: Adams Mark L. , Shapland Audrey Rose , Gutierrez Matthew , Owen Evan
Published: October 2015

Weather affects many aspects of our daily lives from our individual commutes to the global economy. Although much progress has been made in understanding atmospheric physics and weather forecasting, there is still a need for better in situ atmospheric data. Forecasts are based on high performance computer models which solve the differential equations that represent the dynamics of the atmosphere. In all of these models, initial conditions based on the current state of the atmosphere are ingested into the models. The initial conditions are based on data from many sources including remote sensing satellites, ground based weather stations, weather balloons and even aircraft. However, the amount of in situ atmospheric data is very limited and so often times the initial conditions for the models are not truly representative of the current atmosphere. This is especially true for severe storms such as super cell thunderstorms, tornadoes, and hurricanes. Severe weather impacts millions of people every year costing both human life and substantial resources. A better understanding of severe weather will have a significant impact on human safety and infrastructure protection.

Electronics miniaturization and advances in manufacturing such as 3D printing have allowed for the development of low-cost, light-weight probes capable of providing real-time in situ information about the atmosphere which can improve forecasts models and provide a better understanding to atmospheric scientists. The probes provide temperature, relative humidity, pressure, position and velocity data. MEMS sensors are used to monitor the ambient weather conditions and an on-board GPS provides position information. The sensors are combined with a microcontroller and radio to transmit data back to a receiver on the ground. Power is provided by zinc-air batteries and antennas for both the GPS and data radio are integrated into the package. In order to ensure correct operation of the electronics, 3D printing is used to generate a custom electronics/mechanical package that is both functional and robust while maintaining low weight and high drag coefficient. The desire is for the probes to stay airborne as long as possible without any active means of propulsion or buoyancy.

The probes are designed to be small, light-weight and low-cost. They can be deployed from aircraft, weather balloons or launched directly into a storm. Although most probes can be recovered, our design is focused on minimizing the environmental impacts of any probes that are not recovered.
Shrinking Package Footprint by Embedding Top-Side Real Estate Using Core-to-Core Joining
Authors: Shearer Catherine , Holcomb Ken , Haley Jim
Published: October 2015

The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Shoehorning all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes and stacked ICs in various configurations has freed up some real estate. The use of ever smaller passive devices also saves space, but reintroduces old issues such as tombstoning. The ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board – like moving items from a desk to a bookshelf – by embedding components into the board. In this paper, an alternative strategy is presented for embedded components. Sub-PCB constructions are built and populated on both sides, and then are joined using an interposer with sintering conductive paste interconnects. Sintering paste z-axis interconnections have been successfully used in this type of core-to-core joining for many years. The combination of the sintering paste interconnect and an interposer element is the key to enabling this architecture. This manufacturing strategy presents a number of advantages. The board may be broken down into logical substructures such as high density, core or RF portions. Each of the sub-PCBs can be fabricated according to best manufacturing practices for that portion of the circuit board rather than trying to fabricate a single complicated board. Yield losses from sequential process steps and multiple laminations may be reduced. The embedded components may be assembled onto the sub-PCBs using conventional solder reflow technology. The component placement can facilitate point-of-source architecture for high electrical performance. The process flow and some laboratory demonstrations of this technique will be presented in this paper.
Integrated Localized MicroCooling Using High-Displacement Piezoelectric Actuators
Authors: Kranz Michael , Booth Janice , LeFevre Vicki , Hudson Tracy , English Brian , Whitley Michael
Published: October 2015

RF communication and radar systems present an extreme thermal management challenge. These systems are comprised of tightly packaged, high-power components requiring a controlled temperature to meet performance and reliability parameters. In these systems, there is little space available for macro-scale air flow or other traditional cooling methods. In addition, heat generating components are typically microscale semiconductor devices fabricated on integrated circuit substrates buried deeply within the system. Localized cooling using integrated microsystems may provide a solution to these thermal management issues. One approach is the integration of miniature synthetic air jets near the heat generating components. Synthetic jets are generated using oscillating piezoelectric actuators that force air through a small nozzle at high flow rates and in close proximity to the heat generating component. The resulting jets provide vorticity within the fluid, leading to enhanced mixing with the surrounding lower temperature environment and a subsequent increase in the heat transfer coefficient. The US Army AMRDEC has been developing and operating microactuator test beds, utilizing high-displacement actuator architectures, including THUNDER and Lightweight Piezo-Composite Actuator (LIPCA) approaches, to reduce actuator size while maintaining sufficient flow rates and vorticity. This investigation has modeled and fabricated potential high-displacement miniature actuators, as well as predicted and characterized resulting jet parameters and heat transfer coefficients utilizing these actuators. This paper will present actuator designs, fabrication process, and cooling results using these high-displacement piezoelectric actuators as the drive element.
A Cost and Yield Analysis of Wafer-to-wafer Bonding
Authors: Palesko Amy , Palesko Chet
Published: October 2015

When a product requires the bonding of two die or wafers, there are a number of methods that may be used. Not only does the type of bonding process itself have to be selected, but it must also be determined whether the items being bonded will be in wafer or die form. This paper will focus on wafer-to-wafer bonding, which has the highest throughput compared to die-to-wafer and die-to-die bonding; it also has the potential to be the lowest cost option if proper yields are achieved.

This paper will introduce the background and general pros and cons of wafer-to-wafer, die-to-wafer, and die-to-die bonding. Activity based cost modeling will be used to construct a generic flow of a wafer-to-wafer bonding process. The process flow will be divided into a series of activities, and the total cost of each activity will be identified. The cost of each activity will be determined by analyzing the following attributes: time required, amount of labor required, cost of material required (consumable and permanent), tooling cost, depreciation cost of the equipment, and yield loss associated with the activity.

The model will be used to explore multiple variables that affect the total cost of the wafer-to-wafer bonding process, including: incoming wafer cost, incoming wafer defect density, time required for the dicing process, time required for the bonding process, cost of the equipment for the bonding process, and the yield of the bonding process. First, a sensitivity analysis will be conducted to determine the impact each variable has on the total cost. Then scenarios will be created to conduct trade-offs between multiple variables.

Only one, generic wafer-to-wafer bonding model will be created, but there will be enough variables to accurately reflect different bonding methods in use by the industry today. Methods for bonding two wafers together will also be discussed in the paper, as well as the cost and yield issues associated with each. An example of these methods are thermo compression bonding and direct bonding.

The goal of this analysis will be to understand the cost and yield drivers associated with wafer-to-wafer bonding, and to determine scenarios in which wafer-to-wafer bonding is a suitable, cost effective technology selection.
Thin Wafer Handling Using Mechanical- or Laser-Debondable Temporary Adhesives
Authors: Fleming David , Kim Jong-Uk , Okada Janet , Wang Kevin , Gallagher Michael , Barr Bob , Calvert Jeff , Zoschke Kai , Wegner Matthias , Töpper Michael , Rapps Thomas , Griesbach Tim , Lutter Stefan
Published: October 2015

The development of adhesives that enable handling, processing, and assembly of thin wafers and die is a key technical challenge for the realization of 3D devices. We will present on temporary adhesive technology for processing of thinned wafers that is amenable to either mechanical or laser-assisted debonding that can occur at room temperature.

Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, thermal stability to 300 °C or higher, and clean room-temperature release directly from the device wafer using either mechanical or laser-assisted debonding

We will present successful temporary wafer bonding using a BCB (benzocyclobutene)-based material that can meet these requirements. The mode of adhesive release from a device wafer will be discussed in detail as it relates to wafer thinning and handling, and material physical properties and resistances will be expressed. Formulation requirements needed for successful debonding will be presented, with an emphasis on a laser-debonding scheme that utilizes either a 248nm or 308nm laser source capable of ablating a laser sensitive layer residing between a glass carrier and the temporary wafer bonding material. Successful room temperature tape-peeling of the adhesive film after ablation and carrier removal will be discussed.
Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications
Authors: Prange Jonathan , Qin Yi , Thorseth Matthew , Lee Inho , Imanari Masaaki , Lee Yil-Hak , Woertink Julia , Lefebvre Mark , Tachikawa Wataru , Dong Jianwei , Calvert Jeffrey
Published: October 2015

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.
FEA INVESTIGATION OF FACTORS AFFECTING BUMP FATIGUE LIFE
Authors: Wang Mingji , Li Wei
Published: October 2015

Second level interconnect (SLI) or board level reliability (BLR) solder joint fatigue has been investigated extensively by OEM, ODM and OSAT. The influencing factors are well understood that package form factor (FF) and BGA pattern are primary factors. Modeling and testing correlate well in identifying failure location and predicting fatigue life. Previously bump level (FLI) is less touched due to large pitch and less fatigue reliability concerns. With the technology shift to more Chip Scale Package (CSP) FF and finer bump pitch, bump fatigue failure frequently occurs and meeting the reliability requirement become more challenging. However, even bump fatigue becomes more prominent, still not enough effort has been invested due to the modeling complexity when UF is present. As the first step towards developing bump fatigue life prediction, we carried out parametric finite element analysis (FEA) and investigated the factors from material, packaging design aspects that are often neglected in BLR. FEA study showed that with the presence of underfill, more factors than SLI/BLR influence the bump fatigue failure prediction. Key parameters that could affect failure location and life prediction are presented here.
Self Priming Low Stress Aqueous Developable Benzocyclobutene (AD-BCB) Photodielectric Materials for Advanced Wafer Level Packaging
Authors: Dong Hua , Prokopowicz Greg , Barr Bob , Lachowski Joe , Calvert Jeff , Gallagher Mike , Aoude Tina , Bell Rosemary , McNamara Sue , Kondoh Masaki , Oh Joon-Seok , Louks David , Kim Jong-Uk
Published: October 2015

As the semiconductor industry drives to more functionality in smaller and lighter devices, it requires new materials to meet the changing requirements of new and more advanced chip designs and packaging solutions. Photoimagable polymeric dielectric materials are a key building block for wafer level packaging (WLP); these include polyimide (PI), polybenzoxazole (PBO), acrylics, silicones, epoxy-phenolics and benzocyclobutene (BCB). Because of low copper diffusion, low temperature curing, high reliability and low moisture adsorption, BCB was the platform chosen for modification. In this work, we will focus on the development of self priming, low stress, aqueous developable version of BCB, known as AD-BCB. This new photodielectric material has improved mechanical properties of <25MPa film stress value and >28% elongation while maintaining good post develop and post cure adhesion on various substrates including silicon, silicon oxide, silicon nitride, copper, aluminum and epoxy molding compound. Elongation is significantly increased for this positive tone, aqueous developable, photodielectric materials, while film stress and wafer bow are significantly reduced. In addition, this new formulation is self priming and does not require a spin-on adhesion promoter. The material can be cured at as low as 200 °C with lithographic feature size of <10 μm and dielectric constant of 3.0.
Flexible Hand-Free Microelectronics assembly Line for the Chip and Wire industry
Authors: Bhartia Prakash , Angeloni Jim , Bolinger Will
Published: October 2015

This paper presents Natel's effort in pioneering the design and development of the first Touch-Free Microelectronics assembly Line for the Chip and Wire industry. When the Surface Mount Technology (SMT) industry first started, it began as a series of discrete pieces of equipment that performed the functions required to populate Circuit Cards. Over the years, the technology has evolved as has the industry such that fully integrated, automated lines are available where the circuit cards are installed at one end of the line, reels or tubes of components, such as packaged resistors, inductors, capacitors and semiconductors etc., loaded, the machine programmed and assembled circuit cards are available at the other end. However, no such line has been developed for the Chip and Wire industry, with most assembly houses still using individual stand alone die attach, bonders, plasma clean machines to populate substrates.

Natel has developed the first of its kind integrated Auto line for the Chip and Wire industry, which conceptually replicates a SMT line. This Auto Line is touch–free and incorporates die attach ( including eutectic), ball and ribbon bonding , plasma clean and in line testing. The line is ideal for high volume production of Hybrid and Microwave Integrated Circuits. The obvious advantages of this approach are the “ hands-free” continuous flow aspect with significant reduction in product defects, increase in efficiency and cost reduction thereby increasing competitiveness against low labor rate overseas operations.

This paper will provide details of the line, and discuss what additional capabilities can be added and hopefully promote the future development of the Chip and Wire industry built on this pioneering development.
Embedded Power Modules – A new approach using Power Core and High Power PCB
Authors: Boettcher Lars , Boettcher Lars , Karaszkiewicz S. , Manessis D. , Ostmann A.
Published: October 2015

Power electronics packaging applications has strong demands regarding reliability and cost. The fields of developments reach from low power converter modules, over single or multichip MOSFET or IGBT packages, up to high power applications, like needed e.g. for solar inverters and automotive applications. This paper will give an overview about these applications and a description of each ones demand.

The spectrum of conventional power electronics packaging reaches from SMD packages for power chips to large power modules. In most of these packages the power semiconductors are connected by bond wires, resulting in large resistances and parasitic inductance. Additionally bond wires result in a high stray inductance which limits the switching frequency.

The embedding of chips using Printed Circuit Board (PCB) technology offers a solution for many of the problems in power packaging. This paper will show today's available power packages and power modules, realized in industrial production as well as in European research projects. All technologies which are used are based on PCB materials and processes. Chips are mounted to Cu foils, lead frames, high power PCBs or even ceramic substrates, embedded by vacuum lamination of laminate sheets and electrically connected by laser drilling and Cu plating.

A new approach for embedded power modules will be presented in detail. In this project, different application fields are covered, ranging from 50 W over 500 W to 50kW power modules for different applications like single chip packages, over power control units for pedelec (Pedal Electric Cycle), to inverter modules for automotive applications. This approach will focus on a power core base structure for the embedded semiconductor, which is then connected to a high power PCB. The connection to the embedded die is realized by direct copper connection only. The technology principle will be described in detail. Frist manufactured demonstrators will be presented. The presented new approach for the realization of a power core structure offers new possibilities for the module manufacturing, avoiding soldering or Ag sintering of the power semiconductors and the handling of thick copper substrates during the embedding process.
Advancements in Through Glass Via (TGV) Technology
Authors: Shorey Aric , Lu Rachel , Pollard Scott , Kuksenkova Ekatarina , Smith Gene
Published: October 2015

Glass provides many opportunities for advanced packaging. The material properties give many opportunities. As an insulator, glass provides advantages in providing low electrical loss, particularly at high frequencies. The relatively high stiffness and ability to adjust coefficient of thermal expansion gives advantages to manage warp in glass core substrates and bonded stacks.

Forming processes allow the potential to both form in panel format as well as to form at thicknesses as low as 100 um, giving opportunities to provide cost-effective solutions for the industry. Via fabrication technology development continues to advance providing via diameters < 20 um in size in production ready environment. [1–5]

As the industry adopts glass solutions, significant advancements have been made in downstream processes such as glass handling and via/surface metallization. We will provide an update on advancements in these areas as well as handling techniques to achieve desired process flows. There also continues to be increasing amounts of data showing the ability to achieve electrical and thermo-mechanical reliability of substrates with TGV and latest data here will also be provided.
A Random Stimulation Source for Evaluating MEMS Devices using an Exact Solvable Chaotic Oscillator
Authors: Beal Aubrey N. , Dean Robert N.
Published: October 2015

MEMS devices are nearly ubiquitous, with applications ranging from automobiles to toys, medical equipment to missiles, and cell phones to industrial equipment. At the microscale, fabrication tolerances are significantly less precise than at the scale of traditional machining techniques. This can result in significant differences in the operating characteristics between otherwise identical MEMS devices. A wide bandwidth random excitation source is ideal for evaluating these components, whether used as the forcing function for an electromechanical shaker employed to measure transmissibility, or as a voltage source to evaluate actuator structure resonances and instabilities.

An electronic chaotic oscillator provides an ideal wide bandwidth voltage source which is provably random from first principles and may be simply integrated for the aforementioned MEMS testing. This type of system is easily integrated through standard Si MEMS processes and readily lends itself to application as a built-in-self test (BIST) component. These systems guarantee uniform frequency content from D.C. up to 100kHz due to their characteristically random behavior and serve as a strong candidate for providing uniform spectral density to a device under test.

The proposed system is a simple, electronic circuit that creates a random, wideband excitation voltage for observing characteristics of MEMS devices. This functionality is achieved by the analog, digital or mixed signal computation of nonlinear differential equations that describe various exactly solvable chaotic systems. By creating Si microsystems which perform these computations, these test sources may be readily fabricated as integrated BIST components for MEMS devices or fabricated separately and integrated by flip chip assembly techniques. Furthermore, by considering the iterated map of this particular category of stimulation source, a direct and easy measurement of the stimulation entropy may be monitored and corrected.

This work begins as a theoretical treatment involving the Nonlinear Dynamics of these types of systems including chaotic systems which permit closed form solutions. These systems are described classically through nonlinear differential equations and intuitively through iterated maps. These techniques reveal inherent methods for entropy measurement in these sources which may be implemented and controlled easily using electronic circuits. Subsequently, the simulation, circuit design methodology, circuit simulation, fabrication, testing and hardware verification of these wideband chaotic sources is presented. The development of this work delineates simple, wideband electronic testing circuits which may be fully integrated with MEMS devices using standard Si MEMS processes. The resulting microsystem may be used as the forcing function when measuring transmissibility of MEMS devices, or as a BIST element to evaluate MEMS microstructure characteristics through direct microelectronic fabrication or flip chip integration.
Smart Processing of Solid Electrolyte Dendrites with Ordered Porous Structures for Fuel Cell Miniaturizations
Authors: Kirihara Soshu , Noritake Katsuya , Tasaki Satoko , Abe Hiroya
Published: October 2015

Solid electrolyte dendrites of yttria stabilized zirconia with spatially ordered porous structures were successfully fabricated for fuel cell miniaturizations by using micro patterning stereolithography. Micrometer order ceramic lattices with the coordination numbers 4, 6, 8 and 12 were propagated spatially in computer graphic space. Aspect ratios of the lattice diameters and lengths were designed between 1.0 and 2.0 to value the porosities in higher levels from 50 to 80 %. On the fabrication process, nanometer sized yttria stabilized zirconia were dispersed in to photo sensitive liquid resins at 30 % in volume fraction to obtain thixotropic slurries. The paste material was spread on a grass substrate with 10 μm in layer thickness by using mechanic knife edge movements, and an ultra violet micro pattern was exposed on the surface to create cross sectional solid layer with 2 μm in part accuracy. After the layer stacking process, the ceramic dispersed resin lattices of 100 μm in diameter were obtained exactly. These composite precursors were dewaxed and sintered at 600 and 1500 °C in an air atmosphere, respectively, and the fine ceramic lattices of 98 % in relative density were created. Gaseous fluid profiles and pressure distributions in the formed ceramic lattices with the various coordination numbers and porosity percents were visualized and analyzed by using finite element method. The fabricated solid electrolytes with the extremely high porosities and wide surface areas are expect to be applied to novel electrodes in the compact fuel cells. The smart processing of the solid electrolytes by utilizing computer aided design, manufacturing and evaluation methods will be demonstrated.
Design and Fabrication of LTCC Catalyst Chambers.
Authors: Towner Tyler W. , Plumlee Donald G.
Published: October 2015

The reduction in satellite size and mass presents the need to develop a proportionally smaller propulsion system for orbital station keeping. A liquid, monopropellant micropropulsion device made from Low Temperature Co-Fired Ceramics (LTCC) has been developed at Boise State University. This robust, simple design uses an embedded silver catalyst chamber to decompose a rocket-grade hydrogen peroxide monopropellant into a hot gas, which is then expelled out through a nozzle to generate thrust. Using LTCC eliminates the planar geometry fabrication constraint commonly found in silicon MEMS processing.

This report presents the design and fabrication, and optimization of the hydrogen peroxide catalyst chamber used in these monopropellant microthrusters. Using the standard fabrication process for LTCC an initial prototype was developed. The design of this initial device was developed to measure the efficiency of the catalyst chamber by evaluating the ability of the device to decompose hydrogen peroxide. Catastrophic cracking within the device substrate was observed during initial testing. In order to obtain sufficient data, it was assumed that the cracking was due to thermal expansion and so a new functional design was implemented that decreased the overall cross sectional area of the device and decreased failure rates. To ensure that this assumption is correct, an investigation of device failure will be presented using an embedded resistor to simulate the catalytic reaction occurring inside the substrate. The results from this investigation will be documented. Additionally, optical microscope images will be used to document the failure investigation process. Several conclusions will be presented to improve the ability to use LTCC for high temperature applications.
A Low Loss Fully Embedded Stripline Parallel Coupled BPF for Applications using the 60 GHz Band
Authors: Schulz Alexander , Rentsch Sven , Xia Lei , Mueller Robert , Mueller Jens
Published: October 2015

This paper presents a low loss fully embedded bandpass filter (BPF) using low temperature co-fired ceramic (LTCC) for multilayer System-in-Package (SiP) and Multi-Chip-Module (MCM) applications, e.g. wireless applications for the unlicensed 60 GHz band. The measured insertion loss was 1.5 dB at the center frequency 58 GHz, and a return loss of less than −10 dB was achieved, including two grounded coplanar waveguide transmission line (CPWg) to stripline transitions. The four layers BPF has a 3 dB bandwidth of about 11 GHz which supplies e.g. broadband and high data rate applications. The whole BPF requires a substrate area of 5.6 × 2.1 × 0.42 mm3 with transitions and a shielding via fence. This BPF suits well for V-band applications in a LTCC package because of the compact dimensions and the good performance.
An Assembly-Based Structural Model for LTCC Package Design and Reliability
Authors: Young Nathan , Massad Jordan , Ewsuk Kevin
Published: October 2015

Packaging a high power radio frequency integrated circuit (RFIC) in low temperature cofired ceramic (LTCC) presents many challenges. Within the constraints of LTCC fabrication, the design must provide the usual electrical isolation and interconnections required to package the IC, with additional consideration given to RF isolation and the structural integrity issues. While iterative design and prototyping is an option for RFIC packaging development, it is a tedious and expensive process that would most likely be unsuccessful due to the complexity of the problem. To facilitate package design and optimization, thermo-mechanical assembly simulations were used to identify and manage the critical process parameters to control solder failures in the LTCC package assembly. The modeling results were confirmed through comparisons to prototype testing. This paper summarizes an assembly-based modeling approach to RFIC package design and solder failure analysis, and presents some results and key findings to date.

Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin company, for the United States Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000
An Investigation of the Process Stability of RF SiP Made of DuPont 943 and 9K7
Authors: Bartnitzek Thomas , Purtova Tatyana , Rusch Christian , Kaminski Slawomir , Feger Till
Published: October 2015

RF packaging is one of the most challenging topics in LTCC technology. Today LTCC is particularly capable for advanced packages and systems-in-package because of its electrical, functional, thermomechanical properties as well as its excellent long-term stability and reliability. LTCC combines the potential for miniaturization, low loss handling of high frequencies up to 110 GHz and offers the opportunity to integrate additional features. Therefore it has to go through various manufacturing steps and several refirings without any performance degradation or loss of dimensional accuracy.

This paper discusses the impact of thermal post processing on RF characteristics and geometrical properties of LTCC. Ceramic substrates with radar front ends, calibration structures and other test vehicles made of Du Pont Green Tape® 943 and 9k7 were cofired following the recommended conditions and refired several times in order to investigate and compare the influence of the postfiring. The flatness, dimensions and RF performance of the ceramics up to 110 GHz were evaluated and compared.
Punching technology for ceramic applications
Authors: Kohlberger Carsten
Published: October 2015

Miniaturization also takes place in Multilayer ceramics technology, such as Low Temperature Co-fired Ceramic (LTCC). Even if the functionalities seem to rise endless. In the traditional LTCC manufacturing, there is a development to thin materials recognizable, limited by the minimum thickness of the Mylar foil. The only variable parameter is the thickness of the ceramic cast on the foil. Also, in other ceramic applications, there is a development to thicker sheet thickness for various applications from different industries. Furthermore embossing is taking place in the ceramic industry as a production method. In order to perform high class punched and embossed quality for the hole/structures such as via, alignment or cavity raises the requirements for the complete punching tool and as well for the punching components - for example punch, die guide or stripper bushing. Where the laser technologies may see his limits, punching technology can be the right solution. This paper is to report the advantages and the limits of punching technologies in the ceramic as well as to explore the feasibility and current punching technological limits of today's manufacturing technologies
Continuous Manufacture of Submicron Thick Ceramic Green Tapes and Coatings Demonstrated for TCO Nano Particles
Authors: Straue Nadja , Roosen Andreas
Published: October 2015

This presentation introduces a new technique to manufacture continuously submicron thick ceramic green tapes and coatings from nano particulate suspensions. A profiled steel rod is used to coat large areas with a very low film thickness of down to 250 nm. This technique can easily be scaled up and is therefore suitable for mass production at high throughput and low cost. The profile rod technique could be a method to overcome the limit of the tape casting process and therefore this technique exhibits an enormous economical potential.

The technique is demonstrated at the example of nano particulate indium tin oxide (ITO) and zinc oxide (ZnO) particles, which are both transparent conductive oxides (TCOs) and therefore interesting materials for printed displays etc. Nano particles from Evonik Degussa GmbH were first dispersed and stabilized in organic solvents. Subsequently, dispersions as well as slurries were prepared. Their rheological and wetting behavior were studied and the effect on the microstructure of the resulting layer was evaluated. Furthermore, the influence of the processing parameters during coating on the layer quality was analyzed. Finally, the functionality of the printed layers was proven by electrical measurements as well as the assembly of electron devices.
Study of self-actuated screen-printed PZT-cantilevers
Authors: LAKHMI Riadh , CASTILLE Christophe , DEBEDA Hélène , MAGLIONE Mario , LUCAT Claude
Published: October 2015

Usually, resonating cantilevers come from silicon technology and are generally activated with pure bending mode. In this work, we suggest to combine high sensitive cantilever structure with full self-actuated piezoelectric thick-film for high electrical-mechanical coupling. This cantilever is realized through the screen-printing deposition associated with a sacrificial layer. The beam part of the cantilever is composed of a PZT layer between two gold electrodes.

Optimum performances of ferroelectric ceramics strongly rely on their composition and microstructure which imply generally the use of mechanical pressure and very high sintering temperature. These conditions are not compatible with the screen-printing process. As already shown with ceramics, addition of eutectic composition Li2CO3-CuO-Bi2O3 or borosilicate glass-frit to PZT powder and application of isostatic pressure, the sintering temperature of cantilevers may be decreased. Screen-printed piezoelectric samples are thus fired at 850°C, 900°C and 950°C. SEM analyses show the densification of the microstructure while increasing the sintering temperature. Electrical and mechanical characterizations are then achieved after poling the self-actuated cantilevers of different dimensions. In addition to the bending mode observed with a vibrometer, we pointed out other resonances related to the piezoelectric properties of the PZT cantilevers. Indeed, the three first orders of “in-plane” 31-longitudinal vibration mode and the first order “out-of-plane” 33-thickness resonance mode are revealed. The resonance frequencies deduced from analytical modeling are linked to the cantilever dimensions and thus confirm the experimental results. The piezoelectric parameters of PZT cantilevers approach those of ceramics. Quality factors of 300 to 400 associated to the unusual 31-longitudinal mode make self-actuated screen-printed PZT cantilevers good candidates for detection in liquid and gaseous media.
Thin Film on LTCC for Connectivity and Conductivity
Authors: Wolf J. A. , Peterson K. A.
Published: October 2015

The topic of this paper is the development, and characterization of multilayer thin films on Low Temperature Co-fired Ceramic (LTCC) for the purpose of attaining robust connectivity and improved conductivity, aimed at the RF single digit GHz frequency range. The aspect of connectivity primarily covers both standard SnPb eutectic solder as well as Au wire/wedge connections to the same thin film materials. This multi-purpose film ages well, as do solder joints—even after rework. In circuit development, this allows the re-appropriation of solder pads for wire bond purposes and vice versa, greatly enhancing the flexibility of the substrates. The useful lifetime of such substrates has been extended significantly by this work. The photolithographically-defined circuits further enable smaller features and tolerances and better geometrical uniformity. Vias received special attention due mainly to topography encountered at via boundaries and at the top of vias. Preparation and pattern generation for the thin film traces and pads will be discussed with attention to each material and thickness. Ion milling and post-processing for solder masking as well as unique soldering properties of the film edges are also presented. Results for adhesion and performance with respect to the various functions will be presented, as well as a detailed study of the thin film integrity and robustness.
Ceramic-Based Planar Heat Pipe (Plate) for Passive Electronics Cooling
Authors: Wilson M. , Anderson H. , Fellows J. , Lewinsohn C.
Published: October 2015

Heat dissipation has become a major hurdle for the electronics industry, especially as higher performance integrated circuits are being developed for the power industry. Two of the primary hurdles in dissipating this heat are:The thermal contact resistance between the IC and the cooling device.The ability to effectively spread the heat, such that traditional cooling technologies can be effective.By selecting ceramic materials that are thermo-mechanically matched (CTE) to IC materials, the proposed heat plate can be directly bonded by typical solder or braze techniques to the back-side of the IC. This eliminates thermal resistances due to contact and thermal interface materials. Within these heat plates, a three dimensional network of gas channels and fluid wicks spread the high-flux heat loads from localized hot spots to the surrounding regions via phase change fluids and mass transport. Like traditional heat pipes, these heat plates operate at nearly uniform temperature due to the phase change. The internal networks provide for multidimensional heat and mass flow, increasing their dissipating capability.

By using matched ceramic materials, and the inclusion of a heat plate, these primary hurdles for heat dissipation can be mitigated. The performance of prototypical planar heat plates will be presented.