bluuebunny/crossref_metadata_2025 huggingface dataset:
The Mechanism of The Die Crack in exposed Pad Quad Flat Package(ePad QFP) with Large Die due to Die-attach Adhesive with high modulus
Authors: Kim Jin-Ho , Kim Dong-Nam , Jo Young-Chul , Kim Nam-Yong , Kang Seung-Geun , Lee Byung-Ju , Kim Dal-Soo , Yun Tea-Seob , Kim Sung-Jun
Published: October 2015

Thermal-enhanced plastic packages, such as exposed Pad Quad Flat Package (ePAD QFP), are more sensitive to thermal stress and warpage. As a result, thermal stress and warpage in ePAD QFP can lead to severe die cracking. This stress and warpage are mainly due to the thermal mismatch of packaging materials with different coefficient of thermal expansion (CTE). In particular, the die attach adhesive plays an important role in controlling stress and warpage in the package.

In this paper, both experimental data and simulation were employed to gain a better understanding in a stress development and failure mechanism in ePAD QFP with a large die. Theoretical die-attach adhesives with different modulus were used for the evaluation of die crack and delamination by analysis of finite-numerical element method (FNEM). And the effect of the adhesion between Si die and Die-attach adhesive on the die crack was also discussed in this paper by FNEM. The simulation for thermal stress due to CTE mismatch was done by shadow moiré measurement technique and dynamic profiling method to verify the stress concentration area around the die in the package. And the delamination and die crack were simulated by thermal cycling test after changing appropriate adhesive materials that can directly affect on the die crack and the stress. The mechanism of die crack and the crack propagation through the die were mainly discussed in details at first and then the stress concentration and die crack initiation was verified by FNEM analysis and physical experimental validation. Finally, the major property of the die-attach adhesive to be considered for better reliability performance in ePAD QFP was suggested with die size.
Surface Properties of Laser-etched LTCC Ceramic
Authors: Zaraska Krzysztof , Gaudyn Janina , Bieńkowski Adam , Czerwiński Andrzej , Płuska Mariusz
Published: October 2015

In the LTCC process, metal layers are usually deposited by screen printing conductor material on unfired tape substrate. Despite being widely used, this method has certain disadvantages, such as limited resolution of the printing process. An alternative method of producing conductor patterns is to deposit a uniform conductor paste layer on the substrate and the use a Nd:YAG laser to selectively ablate the conductor material, producing a desired pattern. This method allows achieving a higher patterning precision and also eliminates photochemical process of screen preparation, which makes it an attractive choice for rapid prototyping applications. Laser ablation step can be performed either post-firing (for a top conductor layer) or pre-firing (which allows for patterning buried layers). The aim of this paper is to investigate surface properties of LTCC ceramics processed by laser etching. Precision optical imaging and SEM are used to determine etched surface properties, and EDS analysis is used to determine its chemical composition. Effectiveness of conductor removal is investigated by comparing surface resistivity and metal content in raw and etched samples.
Strength and Reliability Estimation of a Low Temperature Co-Fired Ceramic (LTCC) With and Without Metallic Features
Authors: Tandon Rajan , Newton Clay S.
Published: October 2015

The use of Low Temperature Co-Fired Ceramics (LTCC) is a very attractive material option for advanced packaging. For applications, a variety of features are printed in the base material: thermal and electrical vias, resistors, solder pads to name a few. Most of these features have materials that are thermally and elastically mismatched from the LTCC, producing a localized residual stress. These stresses impact the strength and reliability of the LTCC package. Here we present results and analysis for the strength and reliability assessment of an LTCC (Dupont™ 951) with and without Au vias. The reliability of the ceramic material is assessed from the perspective of its susceptibility to sub-critical crack growth (SCG). Metallic vias can significantly lower the strength of the LTCC, however, their presence does not change the measured susceptibility of the material to SCG. Using our experimental data, and empirical descriptions of SCG laws, safe design life for LTCC packages under a particular stress state is estimated.
Electromagnetic Isolation Solutions in Low Temperature Cofired Ceramic (LTCC)
Authors: Krueger Daniel , Peterson Ken , Euler Laurie
Published: October 2015

Low Temperature Cofired Ceramic (LTCC) is a commercial ceramic-glass multilayer technology with compelling advantages for microelectronics, microsystems and sensors. High frequency applications require good electrical properties such as low dielectric los,s and newer applications require extreme isolation from electromagnetic interference (EMI) that is even difficult to measure (−150db). Approaches to providing this isolation, once provided by via fences, have included sidewall coating and full tape thickness features (FTTF) that have been introduced by the filling of slots with via-fill compositions. Several techniques for creating these structures have been modeled for stress and temperature effects in the face of other necessary attachments, such as metallic seal frames. The relative effects of attachment media, FTTF geometry, and alternative measures will be reported. Approaches for thick film and thin film implementations are described.
A Novel Design of a Planar SOFC with the Anode Supported on the Base Ceramic Structure
Authors: Dziurdzia Barbara , Magonski Zbigniew
Published: October 2015

The paper presents the innovative design of a ceramic high temperature solid oxide fuel cell (SOFC) in which the anode consists of two parts: the bottom supportive part with microchannels for fuel distribution and the upper operating part which takes part in the electrochemical reaction in the cell. Both parts of the anode are made of co-fired yttrium-stabilized zirconia (Ni/YSZ) foils. Microchannels as well as the manifold for combustion products are engraved mechanically in the isostatic pressed stack of Ni/YSZ foils before their firing. The electrolyte and the cathode are performed on the upper functional part of the anode by successive screen printing and firing of the electrolyte paste and the cathode paste. The paper reveals details of the fuel cell processing, test fixture and measurement set-up for testing the cells as well as the results of open circuit voltage and short-circuit current measurements.
Properties and Reliability of Silicon Nitride Substrates with AMB Copper Conductor
Authors: Gaby Böhm , Dieter Brunner , Ina Sichert , Andreas Pönicke , Jochen Schilm
Published: October 2015

This paper focuses on the properties of Si3N4 substrate material with AMB (active metal brazing) copper conductor.

A recently developed type of tape casted, gas pressure sintered silicon nitride ceramic with a three times higher thermal conductivity than known from typical standard silicon nitride materials and with good flexural strength was applied. The increase of thermal conductivity is the result of using different species of sintering aids and the optimization of their ratio in the material. The high bending strength allows creating a thinner substrate compared to other standard ceramic materials for power electronics, e.g. aluminum nitride. This reduction in thickness leads to a decrease of the total thermal resistance of the substrate which improves heat dissipation. For the AMB process a silver based active brazing solder composition optimized for Silicon Nitride was used. This optimization could be obtained by an investigation of the physical and chemical interactions between the brazing and the base material. A void free joint without short circuits between adjacent structures could be formed. The copper surface can be coated on demand with Nickel or Nickel/Gold for improved solderability and wire bondability as well as for corrosion protection.

The silicon nitride substrate with AMB copper conductor lines and fully covered back side ground shows a higher reliability than comparable substrates made out of common, well known ceramic materials. The heat dissipation is comparable with conventional AMB substrates made of high thermal conductive ceramic such as Aluminum Nitride, but thermal cycling behavior exceeds the limits well known from AlN-AMB or AlN-DCB.
ELECTRICAL BEHAVIOR OF A DOUBLE SIDED PV SOLAR PANEL
Authors: Ganescu V. , Shoaff R. , Pascu A.
Published: October 2015

An innovative low power (5W) consumer grade dual face PV solar panel assembly is presented in this research. The authors propose capitalizing indirectly on the shadowed face of a typical solar panel by augmenting the panel’s total active area of exposure (via the panel’s “back side” and respective “deflectors”) and aiming at an increase in the overall efficiency of the assembly. Standard environmental operating conditions were taken into account. No CPV were used. The resulting power output profile of this unit is presented in detail and compared with the output of a single sided “standard” solar PV module configuration. In addition, under similar design and operating environmental variables, the behavior of crystalline cells panels is intended to be contrasted with thin film panels’ as variants of this proposed solution.
Resistance Brazing of Alumina Ceramic to Titanium Using Pure Gold
Authors: Siddiqui Mohammad , Jones W. Kinzy
Published: October 2015

Pure gold brazing of 96% alumina ceramic with CP titanium using electrical resistance heating has been analyzed. Wetting studies of gold with different refractory metals and titanium were performed. HTCC alumina ceramic was metalized with a 500 nm Nb layer yielding hermetic joints having leak rate of the order of 1.6 × 10−8 atm-cc/ sec. Adhesion strength was tested using nanoscratch testing using a nanoindentor on 100 nm Nb on polished alumina.
Finding “The Buffy” Talent Acquisition and Retention in Today’s Market
Authors: Troy Patrick J. G.
Published: October 2015

Human Capital is a company’s most valuable asset and market success is directly linked to employee performance. Adopting best practices for recruiting, hiring, and retaining top performers is critical to successful talent acquisition and sustaining bench strength.

A recent survey found that a bad hire can cost an organization anywhere from one to five times the employee’s annual salary. Twenty-six percent of survey respondents reported that replacing an employee who doesn’t work out cost their organizations three times annual salary, and another 42 percent said bad hires cost two times annual salary. Hiring managers who do not utilize best practices will statistically experience fifty percent of their hires as underperforming employees.

An “Ideal Fit” is a comprehensive high order match of a candidate’s skills, talents, attributes, and abilities equally balanced with style, culture, values, and environment. Objectively grading each aspect of “Fit” is critical to evaluating potential. Utilizing process based on proven best practices gives employers a statistically higher probability of making good hires; building the company’s talent roster and brand; and producing a positive contribution to the company’s “bottom Line” by on-boarding successful contributors.

The focus of this paper is to present best practices, show how to implement these practices with real world examples, and expose practices that produce marginal or poor results
Manual Assembly of 400um Bumped-Die GaN Power Semiconductor Devices
Authors: Henning Stephan W. , Jenkins Luke , Hale Sidni , Wilson Christopher G. , Tennant John , Moses Justin , Palmer Mike , Dean Robert N.
Published: October 2015

Until recently, power semiconductors were usually produced as TO, power-PAK, and D-PAK style packaging, due to die size, thermal dissipation requirements, and the vertical flow of current through the devices. The introduction of GaN to power semiconductors has allowed manufactures to produce devices with approximately 9% the footprint of similar rated D-PAK Si MOSFETs. In addition, GaN semiconductors have much better theoretical limits of specific on-resistance to breakdown voltage, when compared to Si and SiC. As of now, GaN devices offer very good performance at much less the cost of SiC, very small footprints, no reverse recovery losses of a body diode, very low RDS(ON), and very fast turn-on and turn-off times due to QGS in single-digit nC range. GaN semiconductors are expected to make vast improvements over the next decade. Unfortunately, this decrease in package size has made design prototyping significantly more challenging. Traditional manual solder iron assembly is not sufficient for these devices. Difficulties include board design, device handling, alignment, solder reflow, flux residue removal, and post-assembly inspection. The EPC 2014 and 2015 devices both have a 4mm pitch and are 1.85mm2 and 6.70mm2, respectively. In many situations, the decreased pitch and small overall size of these devices mandate the use of automated assembly equipment, such as a pick & place, to ensure quality and repeatability of assembly. However, this may not be feasible for initial prototyping, due to cost and time constraints. Here we will present a technique for manual assembly of these chip scale devices, applied specifically to the EPC 2014 and 2015. This should decrease the cost and turn time for prototype assembly when utilizing these types of chip scale packaged power semiconductor devices.
Predicting the Reliability of Zero-Level TSVs
Authors: Caswell Greg , Hillman Craig
Published: October 2015

Through Silicon Vias (TSV) are the next generation technology for system in package devices and are similar to plated through holes in a PCB from a reliability behavior perspective. The promised advantages include thinner packages and a greater level of integration between active die. The process is still being optimized and costs must be reduced for widespread adoption.

TSV is rarely justified by just miniaturization alone as it is more cost-effective to thin, stack and wire bond. Cost can be 2X–4X price of flip chip ($200/wafer is the goal) and 5X–10X the price of wire bonding. TSV will be justified by performance; specifically an increase in inter-die I/O, increase in bandwidth, and a corresponding decrease in interconnect length as shown in Figure 1.

This paper will present two different approaches to the generation of TSVs as the vias can be created at various stages of the process: By the wafer provider, IC manufacturer, or packaging house.

The paper will also address the techniques for creating the TSVs e.g. etching and lasering with respect to their differences and results as well as provide insight into the various approaches for filling the vias. A comparison between solid fill, polymer fill and no fill concepts will be made.

Finally, the paper will address the three primary failure mechanisms for TSVs, that of, cracking of the copper plating, cracking of the silicon /change in resistance of silicon and interfacial delamination of the via wall from the silicon. The paper will conclude with a focus on the challenges for this technology as the exact process and architecture (materials, design) for TSV has yet to be finalized which in turn can lead to large changes in stress states.
Optimizing Product Cost with Supply Chain Cost Modeling
Authors: Palesko Chet , Palesko Alan
Published: October 2015

Demands on the electronics industry for smaller, better, and cheaper packages have made the supply chain more complex. Outsourcing, new technologies, and increasing performance requirements make designing and building the right product for the right price more difficult than ever. We will present a framework for understanding and managing the supply chain through cost modeling. Cost models that accurately reflect the cost impact from technology and design decisions enable a more precise understanding of supply chain behavior. Cost models can show the extra cost of adding a layer, the expected savings from relaxing design rules, or the cost of package on package assembly compared to 3D packaging with through silicon vias (TSVs).

The models also provide context to understanding the ″should cost″ of a product and the path to achieving it. Since the guidance from cost models is based on the actual supplier cost drivers and pricing behavior, designer cost reduction efforts will result in higher savings compared to not using the cost models. Without cost models, designers risk missing their suppliers' real cost drivers and, therefore, the opportunity to decrease cost. This cost modeling framework allows the designers to realize the lowest cost product by matching the right design with the right supplier. It is a method for understanding a design decision's cost impact: a design change, a supplier change, or even the impact of new technology.
NiV Stress Control Utilizing PVD with an Ar / N2 Gas Mixture
Authors: Seryogin G. , Golovato S. , Smith S. , Williams K. , Limburn N. , Winn A. , Mundada G. , Adema G.
Published: October 2015

Physical Vapor Deposition (PVD) is a commonly used technique for back side metallization (BSM) and under bump metallization (UBM). Cutting edge BSM and UBM stacks require good adhesion, low contact resistance and low intrinsic stress. Nickel Vanadium (NiV) is commonly used as a barrier layer in these BSM and UBM stacks. As a non-magnetic material, NiV is more suitable for magnetron sputtering than pure Ni, which is magnetic. NiV tends to be sputtered in a high stress state and high stress in thin films has often degraded adhesion, resulting in long term reliability issues, and bowing of thinned wafers.

NiV films deposited by PVD using argon (Ar) process gas are usually under high tensile stress. In these cases, film stress can be controlled by various means during the PVD process: deposition temperature, deposition pressure, and RF bias applied to the wafers during deposition. This paper explores how changing the process gas from pure Ar to a mixture of argon and nitrogen gasses can control film stress. Stress neutral NiV(N) films were achieved by adding up to 50% of nitrogen to the Ar/N2 mixture. Stress, deposition rate, and sheet resistance were studied as a function of nitrogen percentage in the process gas mixture. Electrical and barrier properties of the resulting NiV(N) films were found to be comparable to or better than NiV films deposited with a pure Ar gas.
XTRONIC®: Enabler of Improved Performance with Reduced Precious Metal Usage in Microelectronics
Authors: Baskin D.M. , Muñoz B.C. , Sylvester J.S. , Cahalen J.P. , Lund A.C.
Published: October 2015

XTRONIC®, a tailored nanocrystalline nickel alloy, has been qualified as a new metal barrier layer replacing pure nickel in many traditional hard and soft gold applications. XTRONIC is produced using a proprietary combination of electroplating chemistry and pulse-reverse applied current waveforms that enables dynamic control of the deposited material's composition and grain structure. The resulting deposits have been shown to provide superior performance in a variety of areas that are critical to microelectronics. These improved performance metrics include resistance to corrosive environments, wear durability, wire bonding, and temperature aging performance. The novel suites of properties possible provide enhanced performance for microelectronics, and can also enable equivalent or improved overall performance even with significant reductions of precious metal use in many applications. Proven areas of application include high-speed backplane connectors and multiple printed circuit board applications such as dual in-line memory module (DIMM) and flash memory card (FMC) applications. In the current paper we focus on properties for printed circuit board applications.
Effects of Extended Dwell Time on Thermal Fatigue Life of Ceramic Chip Resistors
Authors: George Elviz , Osterman Michael , Pecht Michael , Coyle Richard
Published: October 2015

The understanding of the effects of temperature cycling parameters, such as dwell and ramp times, mean cyclic temperature, and temperature range, on the fatigue life of solder interconnects is critical for qualification and reliability testing. After the solder achieves complete stress relaxation, a further increase in dwell time does not decrease the fatigue life of solder interconnects. Studies have shown that an increase in dwell time beyond a certain limit (10–20 minutes) has no effect on the fatigue life of eutectic tin-lead solder when cycled at peak cycle temperatures at or above 100°C. The duration of stress relaxation is longer in SnAgCu and SnCu solders than in eutectic tin-lead solder, resulting in higher creep damage accumulation and thereby reducing the fatigue life of solder interconnects. Experimental data for modeling of the effects of extended dwell time (beyond 60 minutes) on the temperature cycling reliability of tin-silver-copper solders is limited. In this study, forty 2512 ceramic chip resistors soldered onto an FR4 board using SAC105, SAC305, SN100C, and eutectic SnPb solders were subjected to temperature cycling tests with dwell time durations of 10 and 120 minutes, respectively. Resistors soldered on standard and narrow pads were compared to study the effects of pad size on thermal fatigue reliability. In eutectic SnPb-soldered narrow pad resistors, the increase in dwell time to 120 minutes did not change the cycles to failure. However, SnPb-soldered standard pad resistors showed a decrease in fatigue life with the increase in dwell time. For SAC105- and SAC305-soldered narrow and standard pad resistors, the 120-min dwell decreased the thermal fatigue life, compared to the 10-min dwell. The thermal fatigue life of SN100C-soldered narrow pad resistors increased when the dwell time was increased to 120 minutes, while that of the standard pad decreased. In the case of narrow pad resistors, extended dwell may be have annealed the SN100C solder, making it more robust to solder fatigue.
SYSTEMATIC FEEDBACK LOOP FOR SILICON DIE PICK&PLACE PROCESS IN RECONSTITUTED FAN-OUT EWLB WAFERS IN HIGH VOLUME PRODUCTION
Authors: Martins Alberto , Pinho Nelson , Meixner Harald
Published: October 2015

NANIUM S.A. Portugal recently started producing eWLB fan-out [1][2] wafer level packaging technology on 300mm reconstituted wafers. Initial setup of this process demonstrated that the stable die Pick&Place accuracy plays a key role for product feasibility. In the subsequent volume production ramp-up it became apparent that the dynamic expansion of molded eWLB wafers, caused by thermal stress and CTE mismatch throughout the thin film redistribution and passivation layer up to bumping and reflow manufacturing processes requires a very tight die position monitoring over the complete wafer diameter. Feedback loop to the initial die placement and implementation of correction measures is essential to meet the quality and yield targets of different product configurations (die sizes, distance between dies, die thickness, wafer thickness, single die or system-inpackage) in high volume manufacturing. Stability and repeatability is of outermost importance. The paper will discuss the effects seen on the wafer, the monitoring and the strategies for feedback loop process enabling implementation of corrections into the reconstituted wafer before forming the artificial backend wafer by compression molding. The setup of adequate metrology steps throughout the process line supports the control of the various interlayer alignments. The end result is a centered process in the initial Pick&Place and various subsequent lithography steps (Stepper and Mask Aligner). Sustained data availability and processed data visualization made possible the development of an elaborate theoretical model enabling systematic optimizations of machine parameters and material expansion/compression correction factors. The model also permits the immediate visualization of the impact of each machine parameter on the global result.
Packaging of High Power UV-LED Modules on Ceramic and Aluminum Substrates
Authors: Schneider Marc , Leyrer Benjamin , Herbold Christian , Maikowske Stefan
Published: October 2015

An LED module consisting of 98 UV-LEDs with an emission wavelength of 395 nm placed on a ceramic substrate of 211 mm2 is presented. The module is cooled by a forced air heat sink as well as a high performance microstructured water cooler to lower the thermal resistance. For high thermal conductance a liquid metal as the thermal interface material between substrate and heat sink is used. With the forced air heat sink a maximum irradiance of 27.3 W/cm2 at a forward current of 700 mA and 220 W electrical input power was achieved. The microstructured water cooler enabled an almost doubling of the electrical input power (430 W) while maintaining the chip's maximum temperature. For a reduction of the module's thermal resistance a thick film process for aluminum sheet metal substrates was developed. A prototype LED module with 25 UV-LED chips on an area of 54 mm2 achieved a maximum optical power density of 31.6 W/cm2 at a forward current of 900 mA using a forced air heat sink. For an improved cooling of the LED chips a chip-on-heat sink-technology with embedded water cooling channels is developed to eliminate the thermal interface between substrate and heat sink.
A Practical Approach to Analyze Copper Surface Roughness Effects with Applications to Stripline Structures
Authors: Guo Xichen , Chen Ji , Jackson David R. , Koledintseva Marina Y. , Drewniak James , Pan Christopher
Published: October 2015

Conductor loss due to the roughened metal foil surface has significant effects on high-speed signals propagation on backplane traces designed for 10+ Gbps network. A practical method to evaluate these effects, including the signal attenuation and the propagation phase velocity, is proposed in this paper. A periodic structure is assumed to model the morphology of the roughness profile. The equivalent surface impedance is extracted from the grating surface wave propagation constant to model the roughness. This modified surface impedance can hence be used in the traditional attenuation constant formula to calculate the actual conductor loss. This approach is validated using both full-wave simulation tool and measurement, and is shown to be able to provide robust result within 0.2 dB/m relative error.
Virtual Ground Fence: A Simple Method for Protection against High Frequency Simultaneous Switching Noise
Authors: Bowman Jesse , Engin A. Ege
Published: October 2015

When integrating sensitive RF analog devices with complex VLSI digital components, simultaneously switching drivers cause supply voltage fluctuations which can propagate both horizontally and vertically between the power/ground planes. The same voltage source on a printed circuit board can be shared to increase power efficiency and reduce space used. In order to accomplish this, on board filtering is needed to isolate the noise between these two types of devices for proper operation. Hence, accurate estimation and improvement of the performance of power/ground planes is critical in a mixed-signal system. We present a new method to minimize the noise transfer at high frequencies to the power distribution system, called the Virtual Ground Fence. At its basic level, the Virtual Ground Fence consists of quarter-wave transmission-line stubs that act as short circuits between power and ground planes at their design frequency. We will present various configurations of Virtual Ground Fence for different coupling scenarios.
Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application
Authors: Tran Tu Anh , Mathew Varughese , Koh Wen Shi , Yow K. Y. , Au Y. K.
Published: October 2015

New automotive requirements expect plastic packages to survive higher operating temperatures with extended thermal duration. Mission profiles for under-the-hood and transmission application historically specified minimal duration at maximum junction temperature, such as 50 total hours at 150C, while keeping most of the total operating duration at lower temperatures. Further module integration and more stringent environmental requirements push modules and thus plastic packages closer to the heat source. As such, new mission profiles include more than 3500 total hours at 150°C. To satisfy new automotive requirements, plastic packages must meet AEC Grade 0 or higher. One key limitation of the conventional plastic package is the use of gold bond wire on aluminum bond pad. Au-Al intermetallic degradation due to intermetallic transformation in high temperature storage condition remains the main reliability concern. More reliable intermetallic systems have been proposed that change the wire material and/or the bond pad metallization. An alternative wire material to gold, copper, has many benefits including low cost, high electrical and thermal conductivities and excellent reliability with aluminum pad metallization. Pad re-metallization using nickel/palladium, nickel/gold or nickel/palladium/gold over aluminum bond pad or copper bond pad offers a noble and reliable metal interconnect. This study focused on the development of dicing process for low-K-copper wafers having aluminum pad re-metallized with electroless nickel / electroless palladium / immersion gold Over Pad Metallization (OPM). Development wafers were pizza mask wafers on which multiple die designs and scribe grid production control (SGPC) modules were designed. SGPC modules are designed with aluminum probe pads that are used to monitor wafer-level process control. All aluminum features on the wafer were plated with nickel/palladium/gold OPM. With nickel about four times as hard as aluminum, OPM plated SGPC's were much more difficult to dice than conventional SGPC's with aluminum pads. Cracking on silicon sidewall with crack propagating towards the die was found to cause back-end-of-line (BEOL) delamination and device failure. Surface roughness and hardness measurements were taken on OPM variations. Extensive mechanical dicing studies were conducted to modulate the failures and resolve the dicing challenge. Laser grooving followed by mechanical dicing of OPM wafers was also performed. Packages underwent extensive reliability stress conditions. The associated process improvements described in this paper supported a successful integration of a 55nm die technology in Low Profile Quad Flat Package with Exposed Pad (LQFP-EP) meeting and exceeding AEC grade 0 requirements.
Thin PoP: Warpage Control for Thinner PoP Package in Mobile Applications
Authors: Tamadate Yuka , Sato Seiji , Imai Hitomi , Takeda Kota , Meguro Takeshi , Ozawa Takashi
Published: October 2015

In order to significantly improve warpage of a PoP bottom package, Shinko developed an enhanced PoP structure. The inclusion of a support material attached to the backside of the flip chip die and over molded resin is the structure's key attribute. By adjusting the balance of each material (mold resin, substrate and support material thickness), we can better control warpage at both room temperature and reflow temperature. This enhanced thin PoP structure can be easily incorporated into a standard assembly process with existing equipment sets.

This paper describes simulation results, along with measured warpage characteristics of the new package.
A Low Firing Temperature Copper Conductor for use on an Aluminum Metal Compatible Dielectric in LED Thermal Substrate Applications
Authors: Shahbazi Samson , Grabey Steve , Persons Ryan
Published: October 2015

One of the most important contributing factors in the long life of LEDs (Light Emitting Diode) is keeping them cool, i.e., lowering the junction temperature, which can get as high as 150 °C. One way to accomplish this when building a circuit containing many LED packages is to use a thermal substrate. The majority of High Power/High Brightness (HP/HB) LED thermal circuits manufactured today are based on Metal Core Printed Circuit Board (MCPCB) technology. The MCPCB system consists of a copper foil, polymer dielectric layer and either an aluminum or copper base layer that are laminated together. The process of making MCPCB is a subtractive process, where most of the copper foil is removed. The copper foil is etched to create a circuit layer, the polymer dielectric provides the insulation between the copper foil and the metal base, and the aluminum or copper base provides thermal dissipation.

The thick film copper paste discussed in this document is processed using an additive process, like screening printing, where the copper conductor is deposited only in the chosen area. The copper thick film paste is screen printed to create a circuit design on top of a thick film dielectric (insulated area) layer which is also printed on a metal base layer. The selective deposition allows for less material usage, and potentially lower overall cost as well as improved thermal performance with inclusion of thermal vias.

This paper discusses the results of a newly developed lead (Pb) and cadmium (Cd) free low firing temperature (580–600°C) copper thick film conductor paste on top of a low temperature firing dielectric paste. This study includes evaluations based on SEM photos, solderability, leach resistance, and initial and long term adhesions using SAC 305 solder and RMA flux. There are many different applications for HP/HB LED circuits, from general lighting to street lighting to automotive lighting and more. All of them have varying degrees of performance testing requirement. To try to cover as much of the reliability testing as possible we have included tests such as thermal aging (150°C), thermal cycling from −50 to+150°C, as well as 85°C/85% RH reliability testing under bias.
Wedge Bonding RF and Microwave Devices
Authors: Bubel Joe , Levine Lee
Published: October 2015

Interconnecting RF and Microwave devices requires demanding capabilities that can only be provided by wedge bonding. Flat, extremely low loop shape, constant wire length and ribbon bonding are all normal capabilities of wedge bonders that cannot be produced by ball bonders. The flexibility and design of wedge bonding equipment enables all of these capabilities by designing the wire clamp so that both round and ribbon wire can be easily interchanged on the same bond head with only minor adjustments. The shape and functionality of the wedge, feeding the wire from behind and under the face of the tool, naturally produces lower height loops than ball bonders. Enhanced software assists the process by making the programming of low stress-free loops user friendly.
Demonstration of Inkjet Printed Nanoparticle-based Inks for Solder Bump Replacement
Authors: Sadie Jacob , Volkman Steven , Subramanian Vivek
Published: October 2015

Conventional eutectic solders suffer from scaling limitations related to their relatively poor conductivity, electrochemical and thermochemical stability, and toxicity/regulatory restrictions. Novel materials and systems that aim to replace conventional eutectic solders for future packaging applications must be able to meet both the throughput and the thermal demands of standard bumping processes while simultaneously providing the electrical and mechanical properties characteristic of high performance and extended lifetimes. Inkjet printing is a fast-growing deposition technique aptly suited for wafer bumping processes because the feature sizes and pitches capable are appropriate for solder bumps and the droplet-on-demand functionality is an attractive alternative to blanket films processing. Metallic nanoparticle-based inks represent the functional material for eutectic solder replacement, and these inks are attractive due to their relative ease in synthesis and dispensation, their low thermal budget, and electrical conductivities that routinely exceed those of even the best lead-based solders. Furthermore, such material systems have been shown to deliver very good reliability due to their bulk-like properties and avoidance of intermetallic complications as seen in eutectic systems. In this work, we present the capability of printing three dimensional features with nanoparticle inks and demonstrate the critical processing parameters that dictate size control. We fabricate micropillars using a commercially available gold nanoparticle ink, demonstrating feature sizes and techniques appropriate for solder bump replacement. Further, we investigate, for the first time, the process of sintering in three-dimensional nanoparticle features. Using extracted conductivity and mechanical strength measurements, we suggest a model for the sintering in three-dimensional features using our printed micropillars as test structures.
Comparison between Single & Multi Beam Laser Grooving of Low-K layers
Authors: van Borkulo Jeroen , Hendriks Rene , Dijkstra Peter
Published: October 2015

The traditional blade dicing technology has gone through an impressive evolution keeping up with quality, cost and miniaturization requirements that the semiconductor technology roadmaps introduced and specified. However, since wafer technologies have dropped below 90nm node and low k materials were introduced it became clear that blade dicing evolution came to an end and expensive hybrid solutions such as combined laser grooving processes and blade dicing technologies were required to achieve the desired product reliability.

Similar situations have been seen with the ongoing trend to thinner wafer that are needed for miniaturization, 3D packaging and IC performance improvements. To achieve sufficient mechanical strength, complex dicing technologies and sequences have been introduced which do not respond to the requirements for current and near future technologies.

This paper will discuss the low-k grooving process by laser pulses for IC wafers. The low-K laser grooving technology allows semiconductor manufacturers to execute the technology roadmap and continue to comply with Moore's law in an efficient manner. In specific this paper will elaborate on the comparison study made between the single beam and multi beam low-K grooving process. Together with a large IDM customer a comparison has been done to determine the results on quality, Heat Affected Zone (HAZ), productivity and yield.
Electromigration Reliability of Glass Ceramic Multilayer Substrate with Various Surface Finishes
Authors: Matsumoto Hiroshi , Wakazaki Akira , Sato Shingo , Okunosono Takashi , Makihara Chihiro
Published: October 2015

The process speed of high-end servers and supercomputers are steadily increasing. As a result, the backbone of the high speed processing, such as high-end LSI (flip-chip type), and associated substrate circuits is also becoming more dense and miniaturized, while supporting higher current densities. However, recent studies indicate that the higher current density triggers an electromigration (EM) at the solder bumps connecting the under bump metallurgy (UBM) of the flip-chip pad (e.g. Ni) and substrate pads (e.g. Ni/Au). This electromigration leads to voids within the solder joints, which may result in an open circuit. As of result, the life-cycle of the packaged devices is shortened. Thus solution to the EM issue is critical. To respond to such concerns, we have studied the mechanism of the void development, by closely examining differences in diffusion rate among the connective metals - within the pads and the solders. We have mitigated the EM occurrence by reducing the differences in diffusion rate by utilizing high purity Cu for the substrate metallization pads, Cu exhibits a diffusion rate similar to Sn used in solder bumps. Also, solder wettability was improved by utilizing a solder on pad (SOP) construction. As of result we were able to successfully demonstrate an improved life-cycle of the flip-chip solder joints, while accommodating a higher current density. Furthermore, a glass ceramic substrate was used for our study. Since this particular glass ceramic substrate has a coefficient of thermal expansion of 11.8ppm/K, there is an improvement in 1st and 2nd level reliabilities associated with thermal stress from device heat generation. At the same time, it possesses a dielectric constant of 5.8, which is conductive with superior electrical performance (high speed and high frequency). Thus, this glass ceramic substrate is capable of supporting increases in current density, while sustaining high reliability.
Small Pitch Micro-Bumping and Experimental Investigation for Under Filling 3D Stacking
Authors: La Manna Antonio , Rebibis K. J. , De Vos J. , Bogaerts L. , Gerets C. , Beyne E.
Published: October 2015

Although 3D-IC integration is largely acknowledged as most promising technology to push further the scaling concept of Moore's law, a few important uncertainties are delaying high volume production. Among these uncertainties, the reliability of 3D-IC stacked components is the most important. A key element in 3D stacking reliability is the choice of the correct UF to integrate in the assembly processing: die stacking and final packaging. In this paper we report the recent results coming from the UF screening and 3D stacking activities. These activities are performed at Imec in the frame of the 3D Imec Industrial Affiliation Program (3D-IIAP).

After describing the test vehicle used in this work, we introduce some of the requirements in term of process improvement and stacking accuracy to enable 3D stacking in case of small pitch micro-bumps. We then present recent results coming from the UF screening activity and report on the electrical characterization of the 3D stacks. This characterization is done by measuring the electrical resistance of the daisy chains connections between top/bottom dies bumps. The stacks are done with thermo-compression bonding and using die-to-die approach. The stacks are lately exposed to thermo-cycling processing followed by further characterization.
Challenges in 3D Inspection of Micro Bumps Used in 3D Packaging
Authors: Asgari Reza
Published: October 2015

2.5D/3D devices are the next major packaging technologies, driven by the need for more functionality, lower power consumption and smaller footprint. Many device manufacturers are devoting capital to develop their own processes and some are already shipping devices such as FPGA (Field Programmable Gate Array) on interposers. 3D packages often require hundreds of thousands of I/O per die. Micro Pillar bumps and C4 bumps are the main bump geometries used in 3D packages as their small pitch and size allow the required number of I/Os. Inspecting these bumps throughout the process is critical because failure after chip to chip or chip to wafer bonding is very costly. This paper describes the use of a camera and laser triangulation to provide complete 2D and 3D measurement and inspection capability.
Use of 3D Packaging Technology for Satellite Active Antennas Front-ends
Authors: Bonnet B. , Chiniard R. , Legay H. , Nevo D. , Monfraix P. , Vendier O. , Couderc P. , Cazaux J.-L.
Published: October 2015

Multi-Chip Module Vertical (MCM-V) technology, also called 3D packaging technology, enables the realization of a compact and low loss integrated feed for active antennas in Ka band. The active devices can be located in the vicinity of the radiating element, which reduces dramatically the volume and complexity of the antenna front-end for future architectures with more than a hundred beams in Ka band.

This paper deals with the optimization of 3D packaging technology to reach the requirements of 30GHz microwave modules for space applications. The technological developments that have been led on the design and the assembly processes are detailed. The measurement results of an integrated feed module in radiation are given and the circuit designed to optimize the signal-to-noise ratio of the front-end for receiving antennas is characterized. The performance is as good as for an optimized planar front-end with a waveguide access for a much more compact module, especially in terms of footprint in an antenna array. These results successfully position 3D packaging as a disruptive technology for future space and telecom subsystems.
A Ceramic Tubular Probe For Online Substance Concentration Measurement, Manufactured By Ceramic Injection Molding
Authors: Hartmann Matthias , Schmidt Bertram
Published: October 2015

The current research presents recent respective to the work development of a ceramic tubular probe for online substance concentration measurements. The aim was to develop a robust and acid-resistant sensor device, which can be easily included in existing procedural pipeline systems. To archive those goals a lot of factors had to be checked. For the substance concentration measurements a capacitive sensor effect was chosen. With this method even low substance concentrations down to one-tenth of a per cent can be indentified.

For the package material zirconium oxide (tetragonal zirconia polycrystal – TZP) was used. Zirconium oxide is a technical ceramic which is wear-resistant, acid-resistant, has a low thermal conductivity, is electrically isolating and can be uses in a ceramic injection molding (CIM) process. In the phase of the sensor design process multiple geometries for the sensor effect and integration space for the evaluation electronics had to be considered. A standardized DN 10 DIN 32676 flanged joint was also added for an unproblematic connection to the pipelines. All these needed geometries had to be integrated into one ceramic element. As a result of these requirements a 3D CAD model of the sensor element was designed. The CAD-file has shown that there was only the CIM technology left to comprehend developed sensor geometry. CIM is a low cost process for large-scale production which is distinguished by high size accuracy. In the CIM process the material shrinkage, this is caused by the needed debindering and sintering steps, had to be considered.

The developed ceramic tubular probe was successfully tested in multiple fluidic systems. It has left the test phase and is now ready for maturity phase.
Comparison of Silver vs. Gold Systems in High-Q FTTF LTCC Inductors
Authors: Clewell Matthew J. , Kuhn William B.
Published: October 2015

Two different types of full tape thickness feature (FTTF) inductors designed to operate in the VHF/UHF bands were fabricated using the DuPont Green Tape 5738 Gold System and the 6141 Silver System. The first was a 50 nH inductor, with 5 turns and an 80 mil diameter. The second inductor was 20 nH with an 80 mil diameter, but with only 3 turns. High-Q measurements were taken to characterize the inductors. The measured results show that the Silver System produces inductors with Qs up to 110 whereas the Gold System only produced inductors with Qs up to 80. Depressions in the Q measurements were noticed at certain frequencies due to electromagnetic radiation losses. Methods to reduce these dips are also discussed.
Evaluation of Exothermic Reactions in Cofired Platinum /Alumina Microsystems
Authors: Karbasi Ali , Jones W. Kinzy
Published: October 2015

Cofired platinum/ high temperature cofire ceramic (HTCC) alumina ceramic microsystems are emerging as a technology of choice for implantable medical devices due to the long reliable history of Pt wire /alumina ceramics use as feedthrough structures in pacemakers. This work evaluates the materials interactions developed in a platinum / alumina cofired materials system. Reactions previously unreported have been investigated, including the catalytic reaction with organic binders, the reduction of alumina into PtAl3 and the reduction of the melting point of platinum 300 – 500 °C below its melting point, independent of the particle size (nano to micron size particles) or particle morphology. High temperature X-ray diffraction and SEM with EDS analysis were used to characterize each of these reactions.