Trap Densities at Gate Dielectric/2D Channel Interface By Capacitance Measurements
Authors: Krishnaprasad Adithi , Roy Tania 
Published: February 2020

The scaling of CMOS technology is reaching its saturation to the point where research for successors to silicon as the channel material has gained a high momentum. Two-dimensional (2-D) materials, such as transition metal dichalcogenides (TMDCs) and black phosphorus can be scaled down to a single atomic layer with uniformity, and without any out-of-plane dangling bond, thereby establishing them as potential candidates for beyond CMOS technologies.,. But the absence of out-of-plane bonds also prevents the atomic layer deposition (ALD) of dielectrics on them. An intermediate layer called the nucleation or seeding layer is required to be deposited on them for high quality uniform ALD of dielectrics as the gate material. However, the seeding layer introduces traps at the interface of the 2D channel and the gate dielectric, causing scattering of carriers and degrading the mobility of the channel. It is crucial to reduce the interface trap density in order to improve the device performance and reliability. Capacitance measurements on a top-gated 2-D field effect transistor (FET) can give valuable insight into the nature and density of the interface traps. We use capacitance-voltage and capacitance-frequency measurements to quantify the interface trap density (Dit
) for various types of nucleation layers for ALD. Also we compare the Dit
for various ALD high-k dielectrics, including Al2O3, HfO2 and ZrO2. The change of Dit
with the number of layers of 2D material constituting the channel is studied.

We use the most commonly studied 2-D material, MoS2 as the channel material for our interface studies. MoS2 flakes are obtained by mechanical exfoliation with scotch tape on a p+ Si substrate with 260 nm thick thermally grown SiO2. Source and drain contacts are patterned on the MoS2 flakes by electron beam lithography followed by the electron-beam evaporation and lift-off of Ni/Au. The under-lapped top gate is patterned by e-beam lithography. The seeding layer for ALD is e-beam evaporated next. Three types of seeding layers are used, viz. Ti (1 nm), Al (1 nm) and SiOx (1 nm). The elemental metals used as seeding layer are allowed to oxidize in air before introducing into the ALD chamber. The high-k dielectrics are deposited by ALD at lower temperatures (~110 oC), which facilitates the lift-off of the resist used in e-beam lithography (PMMA). Then Ni is e-beam evaporated as the gate contact, followed by the lift-off of the gate stack in warm acetone.

The characterization of the top-gated FETs is done in several stages. Firstly, the drain current vs. top gate voltage (VTG
) characteristics of an FET is measured at varying back gate voltages (VBG
). At high positive VBG, the underlapped regions in the FET are populated with electrons, and the series resistance is low. The subthreshold swing from the1
ID-VTG
curves, gives an idea of the interface trap density. Our devices show an average subthreshold swing of ~70 mV/dec, indicating that interface traps, albeit being low in density, are present. Next, the capacitance is measured in a top-gated 2-D FET by which the interface trap density of 2D material/high-k dielectric stack is extracted. The source/drain electrodes are shorted and the capacitance form the gate to the source/drain electrodes are measured. The gate capacitance is extracted for a known thickness of the high-k dielectric layer in the accumulation region. The dependence of frequency in the C-V characteristics indicates the presence of the interface traps. The Dit
is calculated by the conductance method, described by Takei et al.1 This method will be used to identify the seeding layer that contributes to the least Dit
.

The high-k gate dielectric material will be varied next, to evaluate its effect on the trap density. The interface trap densities in the case of HfO2, ZrO2 and Al2O3 will be extracted and compared. The effect of number of layers in the 2-D channel will be studied. The best combination of channel thickness, seeding layer and high-k gate dielectric producing the lowest Dit
will be reported.

1 Kuniharu Takei, Rehan Kapadia, Hui Fang, E. Plis, Sanjay Krishna, and Ali Javey, Applied Physics Letters 102 (15) (2013).