bluuebunny/crossref_metadata_2025 huggingface dataset:
FLASH vs. (Simulated) FLASH
Authors: Gibson Jeff , Kunz Robert , Ofelt David , Horowitz Mark , Hennessy John , Heinrich Mark
Published: July 2004

Simulation is the primary method for evaluating computer systems during all phases of the design process. One significant problem with simulation is that it rarely models the system exactly, and quantifying the resulting simulator error can be difficult. More importantly, architects often assume without proof that although their simulator may make inaccurate absolute performance predictions, it will still accurately predict architectural trends.This paper studies the source and magnitude of error in a range of architectural simulators by comparing the simulated execution time of several applications and microbenchmarks to their execution time on the actual hardware being modeled. The existence of a hardware gold standard allows us to find, quantify, and fix simulator inaccuracies. We then use the simulators to predict architectural trends and analyze the sensitivity of the results to the simulator configuration. We find that most of our simulators predict trends accurately, as long as they model all of the important performance effects for the application in question. Unfortunately, it is difficult to know what these effects are without having a hardware reference, as they can be quite subtle. This calls into question the value, for architectural studies, of highly detailed simulators whose characteristics are not carefully validated against s real hardware design.
Power aware page allocation
Authors: Lebeck Alvin R. , Fan Xiaobo , Zeng Heng , Ellis Carla
Published: July 2004

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory is a particularly important target for efforts to improve energy efficiency. Memory technology is becoming available that offers power management features such as the ability to put individual chips in any one of several different power modes. In this paper we explore the interaction of page placement with static and dynamic hardware policies to exploit these emerging hardware features. In particular, we consider page allocation policies that can be employed by an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation environments: a trace-driven simulator with workload traces that are representative of mobile computing and an execution-driven simulator with a detailed processor/memory model and a more memory-intensive set of benchmarks (SPEC2000). Our results make a compelling case for a cooperative hardware/software approach for exploiting power-aware memory, with down to as little as 45% of the Energy• Delay for the best static policy and 1% to 20% of the Energy• Delay for a traditional full-power memory.
Hoard
Authors: Berger Emery D. , McKinley Kathryn S. , Blumofe Robert D. , Wilson Paul R.
Published: July 2004

Parallel, multithreaded C and C++ programs such as web servers, database managers, news servers, and scientific applications are becoming increasingly prevalent. For these applications, the memory allocator is often a bottleneck that severely limits program performance and scalability on multiprocessor systems. Previous allocators suffer from problems that include poor performance and scalability, and heap organizations that introduce false sharing. Worse, many allocators exhibit a dramatic increase in memory consumption when confronted with a producer-consumer pattern of object allocation and freeing. This increase in memory consumption can range from a factor of
P
(the number of processors) to unbounded memory consumption.This paper introduces Hoard, a fast, highly scalable allocator that largely avoids false sharing and is memory efficient. Hoard is the first allocator to simultaneously solve the above problems. Hoard combines one global heap and per-processor heaps with a novel discipline that provably bounds memory consumption and has very low synchronization costs in the common case. Our results on eleven programs demonstrate that Hoard yields low average fragmentation and improves overall program performance over the standard Solaris allocator by up to a factor of 60 on 14 processors, and up to a factor of 18 over the next best allocator we tested.
Thread-level parallelism and interactive performance of desktop applications
Authors: Flautner Kristián , Uhlig Rich , Reinhardt Steve , Mudge Trevor
Published: July 2004

Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear for desktop applications. Nevertheless, architects are designing processors that count on the availability of thread-level parallelism. Unlike server workloads, the primary requirement of interactive applications is to respond to user events under human perception bounds rather than to maximize end-to-end throughput. In this paper we report on the thread-level parallelism and interactive response time of a variety of desktop applications. By tracking the communication between tasks, we can focus our measurements on the portions of the benchmark's execution that have the greatest impact on the user. We find that running our benchmarks on a dual-processor machine improves response time of mouse-click events by as much as 36% and 22% on average---out of a maximum possible 50%. The benefits of multiprocessing are even more apparent when background tasks are considered. In our experiments, running a simple MP3 playback program in the background increases response time by 14% on a uniprocessor while it only increases the response time on a dual processor by 4%. When response times are fast enough for further improvements to be imperceptible, the increased idle time after interactive episodes could be exploited to build systems that are more power efficient.
Software profiling for hot path prediction
Authors: Duesterwald Evelyn , Bala Vasanth
Published: July 2004

Recently, there has been a growing interest in exploiting profile information in adaptive systems such as just-in-time compilers, dynamic optimizers and, binary translators. In this paper, we show that sophisticated software profiling schemes that provide highly accurate information in an offline setting are ill-suited for these dynamic code generation systems. We experimentally demonstrate that hot path predictions must be made early in order to control the rising cost of missed opportunity that result from the prediction delay. We also show that existing sophisticated path profiling schemes, if used in an online setting, offer no prediction advantages over simpler schemes that exhibit much lower runtime overheads.Based on these observation we developed a new low-overhead software profiling scheme for hot path prediction. Using an abstract metric we compare our scheme to path profile based prediction and show that our scheme achieves comparable prediction quality. In our second set of experiments we include runtime overhead and evaluate the performance of our scheme in a realistic application: Dynamo, a dynamic optimization system. The results show that our prediction scheme clearly outperforms path profile based prediction and thus confirm that
less
profiling as exhibited in our scheme will actually lead to
more
effective hot path prediction.
Hardware support for dynamic activation of compiler-directed computation reuse
Authors: Connors Daniel A. , Hunter Hillery C. , Cheng Ben-Chung , Hwu Wen-mei W.
Published: July 2004

Compiler-directed Computation Reuse (CCR) enhances program execution speed and efficiency by eliminating dynamic computation redundancy. In this approach, the compiler designates large program regions for potential reuse. During run time, the execution results of these reusable regions are recorded into hardware buffers for future reuse. Previous work shows that CCR can result in significant performance enhancements in general applications. A major limitation of the work is that the compiler relies on value profiling to identify reusable regions, making it difficult to deploy the scheme in many software production environments. This paper presents a new hardware model that alleviates the need for value profiling at compile time. The compiler is allowed to designate reusable regions that may prove to be inappropriate. The hardware mechanism monitors the dynamic behavior of compiler-designated regions and selectively activates the profitable ones at run time. Experimental results show that the proposed design makes more effective utilization of hardware buffer resources, achieves rapid employment of computation regions, and improves reuse accuracy, all of which promote more flexible compiler methods of identifying reusable computation regions.
Symbiotic jobscheduling for a simultaneous multithreaded processor
Authors: Snavely Allan , Tullsen Dean M.
Published: July 2004

Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coscheduleThis paper demonstrates that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without any advance knowledge of a workload's characteristics, using sampling to identify jobs which run well together.We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about various possible schedules, and a symbiosis phase which uses that information to predict which schedule will provide the best performance. We show that a small sample of the possible schedules is sufficient to identify a good schedule quickly. On a system with random job arrivals and departures, response time is improved as much as 17% over a schedule which does not incorporate symbiosis.
A cost-effective approach to implement a long instruction word microprrocessor
Authors: Oyang Yen-Jen , Chang Bor-Ting , Lin Shu-May
Published: July 2004

This paper presents a cost-effective approach to implement a long instruction word microprocessor. The proposed approach achieves the goal of optimal performance/cost tradeoff by selectively, instead of unconditionally, duplicating the hardware resources in a uniprocessor. A hardware resource is duplicated only if the performance improvement gained by doing so can justify the cost incurred. In accordance with this guideline, a long instruction word microprocessor architecture called the MPA architecture is proposed. The MPA architecture has two parallel execution units and, with a minimal increase of hardware cost, delivers a performance significantly higher than that of a RISC (Reduced Instruction Set Computer) uniprocessor, more than 50% higher in average for the five benchmark programs used in this sutdy. On the other hand, a long instruction word microprocessor with everything duplicated delivers a performance just slightly higher than that of the MPA architecture, less than 1% higher in average for the same five benchmark programs, but the cost incurred is a lot higher.
A model for recentralization of computing
Authors: Lorin Harold
Published: July 2004

Distributed systems commonly contain heterogencity at all lcvels of systems structure, differentiated by function (special servers), operating systems and architecture within a single system. On the other hand, large mainframes tend to be more homogeneous in their structures, even when they are multiprocessors. This paper explores a way of using the models of heterogeneous distributed computing within a mainframe. The argument is that appropriate restructuring of the mainframe can achieve a convergence of network oriented and mainframe oriented models of computing and show that a mainframe is just a special case of a distributed system that happens to exist in a box rather than be distributed across wider distances. While there are different views about how many of the "aspects" of distributed processing such a system would have, it would potentially have the advantage of putting large frames on the same power and price/performance curves as collections of distributed nodes. And it would add some attractive features to mainframes.A key concept is that computer structures scale up and down an communications becomes less of a barrier. When looking at a map of a coastline, it is necessary to have reference points to know whether the shape is a few miles, a few hundred miles or a few thousand miles. The analogy for computing is that in the future it will be true that in regarding a population of processors one will need a reference point to know whether the population exists within a frame, within a room, within a building, or spans greater geographical distances.A new structure for mainframes and their relationships to endpoint devices is presented. The author feels that this structure reflects a realistic interpretation of a number of technology trends and information management concerns.It is tremendously important for the reader to remember that a paradigm of computing dominating thinking at the beginning of a decade need not be the paradigm that actually emerges, Historically we move quickly from one pardigm to another. It took just 5 years to move from concepts of highly centralized MULTICS driven computer utilities to complete decentralization of computing, and on to various images of distributed processing. Current paradigms that stress agglomerations of small machines may be just as ephemeral and our notions of where to place enduser interface functions may well not yet be mature.
A microcoded RISC
Authors: DuBose D. K. , Fotakis D. K. , Tabak D.
Published: July 2004

A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal microcode) corresponds to a specific machine language instruction. A large 2048 x 32 CPU Register file, using the register window approach, is implemented. A bit-sliced (AMD2900) prototype is currently under construction.
A recursively microcodable tagged architecture
Authors: Harland David M.
Published: July 2004

Highly interactive polymorphic programming environments which rely heavily upon higher-order data-driven primitives, dynamic type and range checking, and efficient symbolic lookup would greatly benefit from a ultra high level instruction sets.Facilities for microcoding higher-order, data-driven nested and even recursive algorithms are advocated. It is argued that a tagged storage system provides a natural basis for such an architecture.
Distributing and load-balancing for loops in scientific applications
Authors: Ligon W. B. , Stanzione Daniel C.
Published: July 2004

We present experimental results for two engineering applications that have had load balancing and fault tolerance mechanisms added through the use of a standard interface. The abstraction technique employed forms the foundation of a problem solving environment under development at Clemson.
Speculative precomputation
Authors: Collins Jamison D. , Wang Hong , Tullsen Dean M. , Hughes Christopher , Lee Yong-Fong , Lavery Dan , Shen John P.
Published: July 2004

This paper explores Speculative Precomputation, a technique that uses idle thread context in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. This technique is evaluated by simulating the performance of a research processor based on the Itanium™ ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.
Data prefetching by dependence graph precomputation
Authors: Annavaram Murali , Patel Jignesh M. , Davidson Edward S.
Published: July 2004

Data cache misses reduce the performance of wide-issue processors by stalling the data supply to the processor. Prefetching data by predicting the miss address is one way to tolerate the cache miss latencies. But current applications with irregular access patterns make it difficult to accurately predict the address sufficiently early to mask large cache miss latencies. This paper explores an alternative to predicting prefetch addresses, namely precomputing them. The
Dependence Graph Precomputation
scheme (DGP) introduced in this paper is a novel approach for dynamically identifying and precomputing the instructions that determine the addresses accessed by those load/store instructions marked as being responsible for most data cache misses. DGP's dependence graph generator efficiently generates the required dependence graphs at run time. A separate precomputation engine executes these graphs to generate the data addresses of the marked load/store instructions early enough for accurate prefetching. Our results show that 94% of the prefetches issued by DGP are useful, reducing the D-cache miss stall time by 47%. Thus DGP takes us about half way from an already highly tuned baseline system toward perfect D-cache performance. DGP improves the overall performance of a wide range of applications by 7% over tagged next line prefetching, by 13% over a baseline processor with no prefetching, and is within 15% of the perfect D-cache performance
.
Better exploration of region-level value locality with integrated computation reuse and value prediction
Authors: Wu Youfeng , Chen Dong-Yuan , Fang Jesse
Published: July 2004

Computation-reuse and value-prediction are two recent techniques for improving microprocessor performance by exploiting value localities. They both aim at breaking the data dependence limit in traditional processors. In this paper, we propose a speculative multithreading scheme in which the same hardware can be efficiently used for both computation reuse and value prediction. For the SpecInt95 benchmarks, our experiment shows that the integrated approach significantly out-performs either computation reuse or value prediction alone. For example, the integrated approach improves over computation reuse from a speedup of 1.25 to 1.40, and improves over value prediction from 1.28 to 1.40. In particular, the integrated approach out-performs a computation reuse configuration that has twice as much reuse buffer entries (from a speedup 1.33 to 1.40). Furthermore, unlike the computation reuse approach, the performance of the integrated approach does not rely on value profile during region formation and thus our approach is more suitable for production systems.
CryptoManiac
Authors: Wu Lisa , Weaver Chris , Austin Todd
Published: July 2004

The growth of the Internet as a vehicle for secure communication and electronic commerce has brought cryptographic processing performance to the forefront of high throughput system design. This trend will be further underscored with the widespread adoption of secure protocols such as secure IP (IPSEC) and virtual private networks (VPNs).

In this paper, we introduce the CryptoManiac processor, a fast and flexible co-processor for cryptographic workloads. Our design is extremely efficient; we present analysis of a 0.25um physical design that runs the standard Rijndael cipher algorithm 2.25 times faster than a 600MHz Alpha 21264 processor. Moreover, our implementation requires 1/100
th
the area and power in the same technology. We demonstrate that the performance of our design rivals a state-of-the-art dedicated hardware implementation of the 3DES (triple DES) algorithm, while retaining the flexibility to simultaneously support multiple cipher algorithms. Finally, we define a scalable system architecture that combines CryptoManiac processing elements to exploit inter-session and inter-packet parallelism available in many communication protocols. Using I/O traces and detailed timing simulation, we show that chip multiprocessor configurations can effectively service high throughput applications including secure web and disk I/O processing.
Locality vs. criticality
Authors: Ju Roy Dz-ching , Lebeck Alvin R. , Wilkerson Chris
Published: July 2004

Current memory hierarchies exploit locality of references to reduce load latency and thereby improve processor performance. Locality based schemes aim at reducing the number of cache misses and tend to ignore the nature of misses. This leads to a potential mis-match between load latency requirements and latencies realized using a traditional memory system. To bridge this gap, we partition loads as critical and non-critical. A load that needs to complete early to prevent processor stalls is classified as critical, while a load that can tolerate a long latency is considered non-critical.

In this paper, we investigate if it is worth violating locality to exploit information on criticality to improve processor performance. We present a dynamic critical load classification scheme and show that 40% performance improvements are possible on average, if all critical loads are guaranteed to hit in the Ll cache. We then compare the two properties, locality and criticality, in the context of several cache organization and prefetching schemes. We find that the working set of critical loads is large, and hence practical cache organization schemes based on criticality are unable to reduce the critical load miss ratios enough to produce performance gains. Although criticality-based prefetching can help for some resource constrained programs, its benefit over locality-based prefetching is small and may not be worth the added complexity.
DAISY
Authors: Ebcioğlu Kemal , Altman Erik R.
Published: July 2004

Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call
DAISY
(
D
ynamically
A
rchitected
I
nstruction
S
et from
Y
orktown
).
DAISY
is specifically intended to emulate existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes on the VLIW. Each time a new fragment of code is executed for the first time, the code is translated to VLIW primitives, parallelized and saved in a portion of main memory not visible to the old architecture, by a
Virtual Machine Monitor
(software) residing in read only memory. Subsequent executions of the same fragment do not require a translation (unless cast out). We discuss the architectural requirements for such a VLIW, to deal with issues including self-modifying code, precise exceptions, and aggressive reordering of memory references in the presence of strong MP consistency and memory mapped I/O. We have implemented the dynamic parallelization algorithms for the
PowerPC
architecture. The initial results show high degrees of instruction level parallelism with reasonable translation overhead and memory usage.
Implementing multidestination worms in switch-based parallel systems
Authors: Stunkel Craig B. , Sivaram Rajeev , Panda Dhabaleswar K.
Published: July 2004

Multidestination message passing has been proposed as an attractive mechanism for efficiently implementing multicast and other collective operations on direct networks. However, applying this mechanism to switch-based parallel systems is non-trivial. In this paper we propose alternative switch architectures with differing buffer organizations to implement multidestination worms on switch-based parallel systems. First, we discuss issues related to such implementation (deadlock-freedom, replication mechanisms, header encoding, and routing). Next, we demonstrate how an existing central-buffer-based switch architecture supporting unicast message passing can be enhanced to accommodate multidestination message passing. Similarly, implementing multidestination worms on an input-buffer-based switch architecture is discussed. Both of these implementations are evaluated against each other as well as against a software-based scheme using the central buffer organization. Simulation experiments under a range of traffic (multiple multicast, bimodal, varying degree of multicast, and message length) and system size are used for evaluation. The study demonstrates the superiority of the central-buffer-based switch architecture. It also indicates that under bimodal traffic the central-buffer-based hardware multicast implementation affects background unicast traffic less adversely compared to a software-based multicast implementation. Thus, multidestination message passing can easily be applied to switch-based parallel systems to deliver good collective communication performance.
Effects of communication latency, overhead, and bandwidth in a cluster architecture
Authors: Martin Richard P. , Vahdat Amin M. , Culler David E. , Anderson Thomas E.
Published: July 2004

This work provides a systematic study of the impact of communication performance on parallel applications in a high performance network of workstations. We develop an experimental system in which the communication latency, overhead, and bandwidth can be independently varied to observe the effects on a wide range of applications. Our results indicate that current efforts to improve cluster communication performance to that of tightly integrated parallel machines results in significantly improved application performance. We show that applications demonstrate strong sensitivity to overhead, slowing down by a factor of 60 on 32 processors when overhead is increased from 3 to 103 µs. Applications in this study are also sensitive to per-message bandwidth, but are surprisingly tolerant of increased latency and lower per-byte bandwidth. Finally, most applications demonstrate a highly linear dependence to both overhead and per-message bandwidth, indicating that further improvements in communication performance will continue to improve application performance.
The design and analysis of a cache architecture for texture mapping
Authors: Hakura Ziyad S. , Gupta Anoop
Published: July 2004

The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. Despite a recent surge in interest in three-dimensional graphics from computer architects, high-quality high-speed texture mapping has so far been confined to costly hardware systems that use brute-force techniques to achieve high performance. One obstacle faced by designers of texture mapping systems is the requirement of extremely high bandwidth to texture memory. High bandwidth is necessary since there are typically tens to hundreds of millions of accesses to texture memory per second. In addition, to achieve the high clock rates required in graphics pipelines, low-latency access to texture memory is needed. In this paper, we propose the use of texture image caches to alleviate the above bottlenecks, and evaluate various tradeoffs that arise in such designs.We find that the factors important to cache behavior are (i) the representation of texture images in memory, (ii) the rasterization order on screen and (iii) the cache organization. Through a detailed investigation of these issues, we explore the best way to exploit locality of reference and determine whether this technique is robust with respect to different scenes and different amounts of texture. Overall, we observe that there is a significant amount of temporal and spatial locality and that the working set sizes are relatively small (at most 16KB) across all cases that we studied. Consequently, the memory bandwidth requirements of a texture cache system are substantially lower (at least three times and as much as fifteen times) than the memory bandwidth requirements of a system which achieves equivalent performance but does not utilize a cache. These results are very encouraging and indicate that caching is a promising approach to designing memory systems for texture mapping.
Complexity-effective superscalar processors
Authors: Palacharla Subbarao , Jouppi Norman P. , Smith J. E.
Published: July 2004

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of 0.8µm, 0.35µm, and 0.18µm. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future.A microarchitecture that simplifies wakeup and selection logic is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is measured in clock cycles. Furthermore, because only instructions at queue heads need to be awakened and selected, issue logic is simplified and the clock cycle is faster --- consequently overall performance is improved. By grouping dependent instructions together, the proposed microarchitecture will help minimize performance degradation due to slow bypasses in future wide-issue machines.
Coherence controller architectures for SMP-based CC-NUMA multiprocessors
Authors: Michael Maged M. , Nanda Ashwini K. , Lim Beng-Hong , Scott Michael L.
Published: July 2004

Scalable distributed shared-memory architectures rely on coherence controllers on each processing node to synthesize cache-coherent shared memory across the entire machine. The coherence controllers execute coherence protocol handlers that may be hardwired in custom hardware or programmed in a protocol processor within each coherence controller. Although custom hardware runs faster, a protocol processor allows the coherence protocol to be tailored to specific application needs and may shorten hardware development time. Previous research show that the increase in application execution time due to protocol processors over custom hardware is minimal.With the advent of SMP nodes and faster processors and networks, the tradeoff between custom hardware and protocol processors needs to be reexamined. This paper studies the performance of custom-hardware and protocol-processor-based coherence controllers in SMP-node-based CC-NUMA systems on applications from the SPLASH-2 suite. Using realistic parameters and detailed models of existing state-of-the-art system components, it shows that the occupancy of coherence controllers can limit the performance of applications with high communication requirements, where the execution time using protocol processors can be twice as long as using custom hardware.To gain a deeper understanding of the tradeoff, we investigate the effect of varying several architectural parameters that influence the communication characteristics of the applications and the underlying system on coherence controller performance. We identify measures of applications' communication requirements and their impact on the performance penalty of protocol processors, which can help system designers predict performance penalties for other applications. We also study the potential of improving the performance of hardware-based and protocol-processor-based coherence controllers by separating or duplicating critical components.
Reactive NUMA
Authors: Falsafi Babak , Wood David A.
Published: July 2004

This paper proposes and evaluates a new approach to directory-based cache coherence protocols called
Reactive NUMA
(R-NUMA). An R-NUMA system combines a conventional CC-NUMA coherence protocol with a more-recent Simple-COMA (S-COMA) protocol. What makes R-NUMA novel is the way it dynamically reacts to program and system behavior to switch between CC-NUMA and S-COMA and exploit the best aspects of both protocols. This reactive behavior allows each node in an R-NUMA system to independently choose the best protocol for a particular page, thus providing much greater performance stability than either CC-NUMA or S-COMA alone. Our evaluation is both qualitative and quantitative. We first show the theoretical result that R-NUMA's worst-case performance is bounded within a small constant factor (i.e., two to three times) of the best of CC-NUMA and S-COMA. We then use detailed execution-driven simulation to show that, in practice, R-NUMA usually performs better than either a pure CC-NUMA or pure S-COMA protocol, and no more than 57% worse than the best of CC-NUMA and S-COMA, for our benchmarks and base system assumptions.
Data prefetching on the HP PA-8000
Authors: Santhanam Vatsa , Gornish Edward H. , Hsu Wei-Chung
Published: July 2004

Memory latency is a major issue for many modern microprocessor based systems, including the Hewlett-Packard PA-8000. Due to its fast clock rate and wide issue capability, cache misses in the PA-8000 are very expensive. The PA-8000 combines out-of-order execution with multiple outstanding memory requests to tolerate memory latency; however, this approach has its limitations. In order to substantially reduce much of the memory latency penalty, the PA-8000 uses software-based data cache prefetching. In this paper, we discuss the implementation of the data prefetch generation algorithm in the Hewlett-Packard Precision Architecture (HP-PA) compiler. We present performance results for SPECfp95 on a PA-8000 system that show speedups, due to data prefetching, of up to 100%.
An integrated system for neural network simulations
Authors: Garth Simon , Pike Danny
Published: July 2004

A specialist MIMD parallel processing computer has been constructed for high speed simulation of neural network systems. Custom-designed integrated circuits have been combined with conventional microprocessors to give a machine which is highly tuned for neural network computations but which runs a wide range of commercial software packages. In addition, an operating system is presented which assists in the partitioning of problems and allows code which has been developed remotely to be run in parallel on the machine without modification. The machine is intended for research purposes, particularly where large quantities of data need to be processed (e.g. in image processing applications).
Logarithmic indices for multiprocessor evaluation
Authors: Tabak Daniel
Published: July 2004

A method of logarithmic indices for a partial evaluation of potential performance capability of multiprocessors is proposed. The method is independent of the nature of the programs run or any available software capabilities. Consideration parameters can be flexibly added or eliminated as well as relatively weighted. The method is applied to three commercial multiprocessors as an example.
An approach to fault tolerance and error recovery in a parallel graph reduction machine: MaRS—a case study
Authors: Contessa Alessandro
Published: July 2004

This article deals with the issue of fault tolerance and error recovery in a parallel graph reduction computer such as the "MaRS" machine presently under development at CERT. This is a multiprocessor system with decentralized control and asynchronous, delayed communications between cooperating, tightly coupled processes. A solution for the problem of MaRS error recovery is derived, based on the machine's execution model (successive reductions performed on the program graph, i.e. evaluations on the functional expression to be computed) and on its architectural organization (a number of reduction units and memory units interconnected by a message switching network). Under the basic assumption that the errors generated by faults in Reduction and Communication Processors can be detected and confined so as to avoid system contamination, it is shown that a coherent and errorfree recovery state can be restored. Although specifically developed for the MaRS machine, this solution is in principle applicable to other machines using the graph reduction model.
Structuring an instruction cache
Authors: Good Philip l.
Published: July 2004

Structuring an instruction cache to take advantage of known patterns of access reduces its complexity and space requirements and enhances its performance. Two changes are necessary: 1) Caching a program's instructions in packets simplifies the cache's address mechanism and reduces the number of accesses per run. 2) Replacing only those packets which are not anticipating a return reduces the number of cache misses. These changes require only minor modifications to existing cache designs, yet yield immediate benefits in reduced cost and increased performance.
Completing an MIMD multiprocessor taxonomy
Authors: Johnson Eric E.
Published: July 2004

MIMD multiprocessor architectures have been classified as shared memory, message passing, or "hybrid" architectures. This taxonomy is shown to be incomplete, and an alternative complete taxonomy is suggested. Examples of each class of the taxonomy are discussed, along with general attributes of the classes.
A minimal CISC
Authors: Jones Douglas W.
Published: July 2004

The minimal CISC architecture presented here is an extremely simple zero-address architecture suitable for microprogrammed implementation. It is sufficiently simple to be introduced in one lecture, with time left over for discussion of implementation or enhancement options.
Shared cache multiprocessing with pack computers
Authors: Lass Stanley
Published: July 2004

A typical cache accesses a block, then returns a selected word. In a pack computer design, the cache accesses and returns a block to the computer. The computer selects the word from the block and also retains blocks for reuse. The retained blocks constitute a software cache.Separate block wide caches for instructions, read data, and write data provide enough bandwidth for several pack computers to execute several instructions per cache cycle time.The concept of a pack (bundle of information) is used to bridge part of the conceptual gap between blocks and high level languages.The pack computer design has parallel issue of instructions and has vector operations.
A national trace collection and distribution resource
Authors: Thornock Niki C. , Flanagan J. Kelly
Published: July 2004

Computer systems are modeled before construction to minimize errors and performance bottlenecks. A common modeling approach is to build software models of comptuer system components, and use realistic
trace
data as input. This methodology is commonly referred to as trace-driven simulation. Trace-driven simulation can be very accurate if both the system model and input trace data represent the system under test. The accuracy of the model is typically under the control of the researcher, but so far little or no trace data has been available that accurately represents current or future workloads. To address this issue, we describe the Brigham Young Univ. Address Collection Hardware (BACH) and introduce our national trace distribution center and trace collection facility (http://traces.byu.edu). We also illustrate the types of traces we collect and make available to others.
Internet nuggets
Authors: Thorson Mark
Published: July 2004

This column consists of selected traffic from the comp.arch newsgroup, a forum for discussion of computer architecture on Internet---an international computer network. As always, the opinions expressed in this column are the personal views of the authors, and do not necesarily represent the institutions to which they are affiliated. Text which sets the context of a message appears in italics; this is usually text the author has quoted from earlier messages. The code-like expressions below the authors' names are their addresses on Internet.
An intelligent memory system
Authors: Asthana A. , Jagadish H. V. , Chandross J. A. , Lin D. , Knauer S. C.
Published: July 2004

SWIM(Structured Wafer-Scale Intelligent Memory) is a high bandwidth, multi-ported, disk-sized memory system capable of storing, maintaining, and manipulating data structures within it, independent of the main processing units. Up to thousands of active storage elements, each element having some storage and some associated processing logic, function independently or in groups to implement userdefined objects. SWIM increases memory functionality to better balance the time spent in moving data with that involved in actually manipulating it. Just as one may associate a cache with each processor, each memory module has processing logic associated with it. Such logic decreases the processormemory bandwidth requirements, improves memory utilization, scales better in a multiprocessor, and yields a faster response from memory. The faster response results from proximity, a specialized micro architecture and parallelism.
Optimized communication in an extended remote procedure call model
Authors: Pucci Marc F. , Alberi J. L.
Published: July 2004

Increased latency associated with remote operations is a serious problem facing any distributed system. This problem is compounded if the distributed system must work over several forms of interconnect since designing an efficient solution for one may make accommodating another awkward or impractical. On the other hand, a common interprocessor communications protocol may not exploit the advantages of new technology. This paper describes an interprocessor communications model that provides a uniform interface to high level system functions, while encouraging optimizations based on unique characteristics of a particular interconnect. It has been successfully applied to local, backplane and traditional network style interconnects.
Modelling and performance evaluation of multiprocessors organization with shared memories
Authors: Naderi M.
Published: July 2004

This paper is primarily concerned with theoretical evaluation of the performance of multi-processors system. A markovian waiting line model have been developed for various different multi-processors configurations, with shared memory.The system is analysed at the request level rather than job level.
A survey of commercial parallel processors
Authors: Gehringer Edward , Abullarade Janne , Gulyn Michael H.
Published: July 2004

This paper compares eight commercial parallel processors along several dimensions. The processors include four shared-bus multiprocessors (the Encore Multimax, the Sequent Balance system, the Alliant FX series, and the ELXSI System 6400) and four network multiprocessors (the BBN Butterfly, the NCUBE, the Intel iPSC/2, and the FPS T Series). The paper contrasts the computers from the standpoint of interconnection structures, memory configurations, and interprocessor communication. Also, the shared-bus multiprocessors are compared in terms of cache-coherence strategies, and the network multiprocessors are compared in terms of node structure. Where possible, price and performance information has been included. The reader is cautioned that this survey is based largely on information submitted by manufacturers; the authors have not performed any independent evaluation.
An overview of the Kyushu University reconfigurable parallel processor
Authors: Murakami Kazuaki , Fukuda Akira , Sueyoshi Toshinori , Tomita Shinji
Published: July 2004

As a testbed to investigate systemwide aspects of highly parallel processing, a reconfigurable parallel processor system is currently developed at the Kyushu University in Japan. The system is a MIMD- type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S N×N crossbar networks (currently S is 1). Each processing-element (PE) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set and 4 Mbytes of memory. Although memory are organized to be distributed among all PEs, the system can be reconfigured as either a memory-shared tightly coupled multiprocessor or a message-passing loosely coupled multiprocessor at run time; also as a hybrid of the two. The crossbar network allows users to take arbitrary topologies for inter-PE (i.e. processor-memory and/or processor-processor) paths under software control of an operating system. The parallel/distributed operating system is also under development to exploit parallelism by making the best of reconfigurability. The full 128-PE configuration will provide up to 1.28 GIPS, 205 MFLOPS (single precision LINPACK), 141 MFLOPS (double precision LINPACK), 512 Mbytes of memory and 1.28 Gbytes/s inter-PE communication. This paper outlines the reconfigurable network and memory architectures among several unique architectural features of the reconfigurable parallel processor.
From defects to failures: a view of dependable computing
Authors: Parhami Behrooz
Published: July 2004

A unified framework and terminology for the study of computer system dependability is presented. Impairments to dependability are viewed from six abstraction levels. It is argued that all of these levels are useful, in the sense that proven dependability procurement techniques can be applied at each level, and that it is beneficial to have distinct, precisely defined terminology for describing impairments to and procurement strategies for computer system dependability at these levels. The six levels in the proposed framework are:1. Defect level or component level, dealing with deviant atomic parts.2. Fault level or logic level, dealing with deviant logic values or path selections.3. Error level or information level, dealing with deviant internal states.4. Malfunction level or system level, dealing with deviant functional behavior.5. Degradation level or service level, dealing with deviant performance.6. Failure level or result level, dealing with deviant outputs or actions.Briefly, a hardware or software component may be
defective
(perfect hardware may also become defective due to wear and aging). Certain system states expose the

defect

, resulting in the development of a logic-level

fault

. Information flowing within a

faulty

system may become contaminated, leading to the presence of an

error

. An

erroneous

system state may result in a subsystem

malfunction

. Automatic or manually controlled reconfiguration can isolate or bypass the malfunctioning subsystem but may lead to a
degraded
performance or service. Serious performance degradation may lead to a result-level system
failure
when untrustworthy or untimely results are produced. Finally, a failed computer system can have adverse effects on the larger societal or corporate system into which it is incorporated.