(Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates
Authors: Claeys Cor , Simoen Eddy 
Published: July 2021

Implementation of high-mobility channel materials enables to increase the device performance due to the higher carrier mobility compared to silicon devices. III-V based materials such as GaAs and ternary systems (e.g. InxGa1-xAs alloys) are achieving high performing n-channel transistors. The strong progress in hetero-epitaxy using nano ridge engineering [1] leading to monolithic heterogeneous integration of III-V materials on silicon substrates resulted in state-of-the-art FinFETs, gate-all-around (GAA) and horizontal or vertical stacked nanowires (NW) on 300 mm Si wafers [2,3]. Very promising results have also been reported for GaN on Si triggering their use for high power and RF applications [4].

One of the main challenges remains a good defect control in order not to degrade the electrical performance of devices and circuits [5]. The nucleation of extended defects is directly related to the hetero-epitaxial growth of layers with a lattice mismatch and their concentration depends on the composition of the layers such as e.g. the In content in InxGa1-xAs and the Al content in AlxGa1-xN. The defects have a direct impact on the generation and recombination lifetime and the leakage current [5], while also the low frequency noise (LFN) performance is influenced [6]. The identification of the defects (energy level ET, capture cross section and concentration) can be determined using Deep Level Transient Spectroscopy (DLTS) and low frequency noise spectroscopy by measuring LFN as a function of temperature.

The goal of this work is to review the knowledge about defect engineering and to analyze the electrical activity of extended defects in III-V semiconductors on silicon substrates. Different case studies will be used to illustrate both the defect identification and the electrical activity of the defects. The impact of the used processing schemes to fabricate the devices is also discussed. It will e.g. be shown that defects in GaN/AlGaN MOSHEMTs increase the low frequency noise due to generation-recombination centers in the GaN depletion layer [7]. These traps can lead to a distortion of the current-voltage characteristics of short channel devices. DLTS studies are a powerful tool to identify traps and to investigate their impact on the leakage current of III-V on Si devices. Double correlation DLTS investigations on GaAs/InGaP/GaAs diodes pointed out that traps associated with sidewall interface states can dominate the peripheral diode leakage current. The focus of the presentation will be on the current understanding of defect engineering associated with the monolithic integration of III-V materials on Si and a discussion of recent results concerning the electrical activity of the defects and the defect modeling.

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[3] A.P. Milemin et al., Microelectron. Eng., 192, 14 (2019).

[4] L. Li et al., IEEE
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[5] C. Claeys et al., ECS Solid State Electronics, 9, 03301 (2020).

[6] C. Claeys et al., J. Phys.
Cond. Ser., 1190, 012001 (2019).

[7] K. Takakura et al., IEEE Trans. Electron Dev., 67, 3062 (2020).