Trap Characterization of ALD Al2O3/4H-SiC Metal-Oxide-Semiconductor Interfaces
Authors: Jayawardhena Isanka Udayani , Ahyi Ayayi , Isaacs-smith Tamara , Ramamurthy Ramamurthy P , Morisette Dallas , Dhar Sarit 
Published: February 2020

4H-Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) are enabling high-efficiency power switching applications under high-temperature, and harsh environment conditions because of SiC’s superior physical properties. However, 4H-SiC MOSFETs have a much lower channel conductance due to the trapping of electrons by a high-density of near-interface traps (NITs) at the SiO2/4H-SiC interface [1,2]. These states are spatially located within ~1 nm from the interface and energetically positioned near the conduction band edge of 4H-SiC. Among the many approaches to solve this issue, using atomic layer deposition (ALD) of high k-dielectrics such as Al2O3 is promising. It has been reported that appropriate surface termination of 4H-SiC prior to ALD with hydrogen [3,4] or SiO [5,6] results in improved properties of Al2O3/4H-SiC MOS devices. The SiO termination refers to the insertion of an ultra-thin (~0.7 nm) silicon oxide layer between Al2O3 and 4H-SiC that results in effective channel mobility greater than 250 cm2Vs-1[5, 6]; significantly higher than that obtained by using standard nitrided (NO annealed) [7] SiO2 as the gate dielectric.

In this work, we studied the above two surface termination approaches for ALD Al2O3 using electrical characterization and compared to typical thermally grown SiO2. To this end, Si-face n-type 4H-SiC MOS capacitors were fabricated and characterized using the simultaneous high-low frequency capacitance-voltage (CV), current-voltage (IV) and constant capacitance deep level transient spectroscopy (CCDLTS). For H- termination, prior to ALD, samples were etched in H2 at 1600 ◦C followed by annealing in H2 at 1000 ◦C [3, 4]. Following this, ALD was performed at 200 °C using Trimethylaluminum (TMA, Al(CH3)3) as the precursor to deposit ~50 nm of Al2O3. Electrical measurements were carried out after patterning and deposition of Au/Ti gates. In these samples, the interface state density (Dit ~3x1011 cm-2eV-1) near the conduction band edge was comparable to nitrided SiO2 as shown in Fig. 1. In addition, the CCDLTS showed that the typical ‘O1’ and ‘O2’ NITs[8] detected by CCDLTS at 4H-SiC/SiO2 interfaces, with emission activation energies of about 0.15±0.05 eV and 0.39±0.1 eV[4,8] below the 4H-SiC conduction band, were absent at these Al2O3/4H-SiC interfaces (Fig.2), which is extremely encouraging. In the second surface termination approach, ultra-thin (<1 nm) silicon oxide layers were grown thermally before Al2O3 deposition. Different oxidation conditions were employed varying the furnace temperature as 550 ◦C, 600 ◦C and 650 ◦C with 5 min oxidation time. Then, ~40 nm Al2O3 was deposited using the above ALD process and Al gate contacts were formed. Figure 3 shows the typical quasistatic CVs. It can be clearly observed that, with increasing oxidation temperature, the CV curves shift to the left indicating a reduction of negative charges at the interface, consistent with Dit reduction. However as shown in Fig.1, the simultaneous high-low CV reveals much higher Dit for these devices (~1x1013 cm-2eV-1 near the conduction band edge), comparable to typical unpassivated thermal oxides. Previous reports suggest that the ultra-thin oxide film thickness should be about ~0.7 nm to obtain low Dit and high channel mobility [5,6]. Our preliminary XPS analysis suggests that our film thickness is less than this critical value which might be the cause of the higher Dit here. Therefore, within our current results, we observe that surface H-termination prior to ALD of Al2O3 results in significantly lower Dit compared to SiO termination. Further studies with thicker SiO interlayers will be presented at the conference along with chemical bonding results from XPS analysis.

Acknowledgments: This work was supported by the II-VI Foundation and US Army Research Lab. The authors thank Drs. Chunkun Jiao and Koushik Ramadoss from Purdue and Drs. Leonard C. Feldman and Ryan Thorpe from Rutgers University for sample fabrication and XPS analysis.

[1] T. Kimoto, and J. A. Cooper, Fundamentals of Silicon Carbide Technology, John Wiley, 2014.

[2] B. J. Baliga, Fundamentals of power semiconductor devices,1st edn., Springer, US, 2010.

[3] T. Seyller, Appl. Phys. A. 85. 4. 371–385, Dec. 2006.

[4] I. Jayawardhena, A. Jayawardena, C. Jiao, D. Morisette, and S. Dhar, Materials Science Forum, Proceedings of the 2018 ECSCRM (accepted 2019)

[5] T. Hatayama, S. Hino, N. Miura, T. Oomori, and E. Tokumitsu, IEEE Trans. Electron Devices. 55. 8. 2041–2045. 2008.

[6] J. Urresti, F. Arith, S. Olsen, N. Wright, and A. O’Neill, IEEE Trans. Electron Devices,66, 4, 1710–1716, Apr. 2019.

[7] G. Y. Chung et al., Appl. Phys. Lett. 76. 13. 1713–1715, 2000.

[8] A. F. Basile, J. Rozen, J. R. Williams, L. C. Feldman, and P. M. Mooney, J. Appl. Phys., 109, 6, 064514, Mar. 2011.

Figure 1