(Invited) Vertical GaN Diodes: Effect of Growth Parameters, Indium Surfactants, and Device Development for High-Power Electronics
Authors: Speck James S. , Farzana Esmat , Qwah Kai Shek 
Published: November 2022

GaN has achieved widespread interest in high-power and high-speed electronics due to its wide-bandgap (WBG), large breakdown field, and high mobility compared to Si and SiC. There is also continued interest in the growth and development of GaN vertical devices owing to their advantageous properties of high current capability from backside ohmic, better field management, scaling feasibility, and enhanced thermal transport, which is not feasible with the lateral device topology. To realize the predicted high breakdown voltage and low on-resistance from vertical devices, high-quality drift layers with low unintentional doping and low compensating defects are fundamentally required. Hence, our research aims to pursue a comprehensive investigation of growth and device development with vertical GaN structures, building from the optimization of thick GaN homoepitaxy with high growth rate but low impurities, improving surface morphology using Indium as a surfactant as well as realizing punch-through field-plate p-n diodes to maximize the average electric field in high-voltage operation.

Toward the goal of high-quality GaN epitaxy growth, we performed systematic studies of growth rate effects on the drift layer doping using ammonia molecular beam epitaxy (NH3 MBE) and plasma-assisted molecular beam epitaxy (PA MBE) [1]. The NH3 MBE homoepitaxy GaN demonstrated an unintentional doping (UID) of ~1015 cm-3, significantly lower than that of the conventional metalorganic chemical vapor deposition (MOCVD) reports, which can be potentially contributed by clean growth environment of MBE.

We further focused on improving surface morphology using Indium as a surfactant. Through a combination of varying V/III ratios, In flux and growth temperatures, an optimal condition for surface morphology, characterized by atomic force microscopy, was achieved for fast growth rates (on the order of 1 µm/hr and beam equivalent pressures on the order of 5 × 10-7 Torr). However, excessive indium causes the surface morphology to degrade, potentially due to the enhancement of the Ga desorption from the surface as a result of the reaction of indium with ammonia for high indium fluxes. The indium surfactant can also reduce silicon impurities as revealed from the Secondary ion mass spectrometry (SIMS) (Fig. 2).

Subsequently, we developed vertical p-n GaN power devices using the NH3 MBE-grown high-quality epitaxy [2]. The vertical p-n GaN diode consisted (from bottom up): ~0.25 µm of n+ GaN ([Si]: 1×1019 cm-3) buffer, ~4 µm UID GaN drift layer for n-type region, ~0.4 µm p+GaN ([Mg]: 3×1019 cm-3) for p-type region, and ~10 nm p++ GaN cap ([Mg]: 3×1020 cm-3) to support the anode ohmic contact. Circular p-n diodes of 80-100 µm diameter were fabricated with Pd/Pt anode and a backside Ti/ Au ohmic contact. The field management was achieved by field-plate of 15 µm formed with Ti/Au metals on top of a field-plate dielectric of a Al2O3 (26 nm)/ Si3N4 (205 nm) stack (Fig. 3).

The p-n GaN diodes exhibited an outstanding forward J-V behavior with a low specific on-resistance (Ron,sp) of 0.28 mΩ-cm2 and a minimum ideality factor of 1.36 (Fig. 4), which are among the best achieved in vertical homoepitaxy GaN p-n diodes [2-4]. The best diodes also exhibited a breakdown voltage of > 1 kV (equipment limit 1 kV). These reverse-voltage properties imply a punch-through characteristics with peak electric field (EC) >2.6 MV/cm, as revealed by Silvaco simulation (Fig. 5). The combination of >1 kV breakdown voltage and on-resistance of 0.28 mΩ-cm2 represents one of the best performances of the p-n GaN diodes, achieved with a significantly downscaled (~4 um) drift layer compared to the MOCVD GaN p-n diodes of ≥ 8 um (Fig. 6). Work is ongoing to develop NHE MBE p-n diodes with indium surfactant-assisted drift layer growth which will be promising to further improve the surface morphology, reduce leakage, and enhance breakdown performance of the vertical devices.

References:

[1] J. Wang, K. Jorgensen et al. APL Mater.
9, 081118 (2021)

[2] E. Farzana et al, IEEE Electron Device Lett. 41 (12), 1806 (2020).

[3] H. Fu et al, IEEE Electron Device Lett.,
41, 127, (2020).

[4] Z. Hu et al," Appl. Phys. Lett., 107, 2435011, (2015).

Figure 1