(Invited) Barriers to SiC Power Semiconductor Device Commercialization
Authors: Veliadis Victor 
Published: December 2024

There are several reasons behind silicon’s dominance of the power electronics market. Silicon is renowned for its excellent starting material quality, ease of processing, opportunity for low-cost mass production, proven reliability, and circuit design legacy. However, despite significant progress, silicon devices are now approaching their operational limits. They are held back by their relatively low bandgap and low critical electric field, traits that result in high conduction and switching losses and substandard high-temperature performance. To address these shortcomings, much effort has been directed at increasing the competitiveness of commercial SiC power devices. Transistors and diodes made with SiC have superior material properties, enabling the production of highly efficient power devices with a smaller form factor and simplified cooling management.

Silicon carbide (SiC) is ideally suited for power conditioning applications due to its high saturated drift velocity, its mechanical strength, its excellent thermal conductivity, its wide bandgap, and its high critical electric field. For power devices, the ninefold increase in critical field strength of SiC, relative to Si, allows high voltage blocking layers to be fabricated significantly thinner than those of comparably rated Si devices. This reduces device on-state resistance and the associated conduction losses, while maintaining the same high-voltage blocking capability. Indeed, the specific on-state resistance of 4H-SiC is approximately 400 times lower than that of Si at a given breakdown voltage, enabling high-current operation at relatively low forward voltage drop. Thinner layers and low specific on-resistance reduce capacitance, enabling low switching losses at high-frequency operation, which reduces the weight/volume of passive components and increases power density while lowering the cost of materials. In addition, the wide bandgap of SiC results in relatively low intrinsic carrier concentration, which combined with its high thermal conductivity, enables operation at high temperatures (where conventional Si devices fail), with low leakage currents and simplified thermal management. Today, Si, SiC, and GaN co-exist and have carved out their application space based on their competitive advantages, with certain overlapping areas where all three material technologies are competitive and vie for market share.

As SiC continues to grow, the industry is lifting the last barriers to mass commercialization, which primarily come down to three challenges. First, compared to mass-produced silicon, costs are higher — chiefly due to the complexity of synthesizing SiC substrates and to how much more labor-intensive SiC fab manufacturing and modules are. Defects are the second significant issue, as they limit chip yield and area, and compromise reliability and ruggedness. The third issue is that the workforce lacks expertise in integrating SiC technologies into systems.

In SiC power transistors, the wafer represents 50-65% of the overall device cost, a consequence of its unique complex fabrication specifics. SiC substrates are primarily grown by the seeded sublimation technique at temperatures of 2300-2500 °C, which creates process control challenges. Crystal expansion is limited requiring the use of large high-material quality seeds, and the sublimation growth rates can be relatively low in the order of 0.5-2 mm/h. Furthermore, the SiC material’s hardness, which is comparable to that of diamond, makes sawing and polishing slow and costly relative to Si. For mass SiC commercialization, high yielding fabrication processes are required. Numerous well-established processes from silicon technology have been successfully transferred to SiC. However, SiC material properties necessitate use of specific processes not available from silicon, including wafer thinning, etching, heated implantation and anneal, and low resistivity Ohmic contact formation. In addition, the relative lack of flatness of SiC wafers, compared to those of Si, can complicate photolithography. Overall, SiC wafer fabrication and fab processing are more complex, more time consuming, and more labor intensive than those in silicon.

Basal-Plane-Dislocations (BPDs) are the last major defect degrading device performance. When bipolar current flows through a SiC device, electron–hole pair recombination at BPDs provides the energy to activate dislocation glides, which give rise to stacking faults that degrade electric performance. BPDs can propagate from the wafer substrate into the epitaxial layers, and can be generated during epitaxy and during the high-temperature ion-implantation fabrication process. BPD-related degradation can be readily identified in post-fabrication production testing and is thus a yield issue; not a reliability one. Lastly, the poor SiC/SiO2 gate interface quality reduces inversion layer mobility and causes threshold voltage instability; the latter being a reliability concern.

A survey of 1200-V SiC MOSFET pricing vs. current rating will be presented. SiC MOSFETs are more expensive than similarly rated Si IGBTs, with cost disproportionally increasing with current rating due to the yield impact of defects.