Quantum Enhanced Josephson Junction Field-Effect Transistors for Logic Applications
Authors: Pan Wei , Muhowski Aaron J. , Martinez William M. , Sovinec Courtney L.H. , Mendez Juan P. , Mamaluy Denis 
Published: August 2024

The need of data centers for cloud and network computing has dramatically increased power consumption. In 2014, data centers in the U.S. consumed an estimated 70 billion kWh, representing about 1.8% of total U.S. electricity consumption [“United States Data Center Energy Usage Report," published in June 2016 and supported by the Federal Energy Management Program of the U.S. Department of Energy]. Worldwide, the International Energy Agency estimates that currently about 1% of all global electricity is used by data centers. It is expected that by 2030 the electricity use of information and communications technology may exceed 20% of all global electricity. The microelectronics industry has been focusing on aggressively shrinking the size of logic and memory devices to reduce power consumption. However, this scaling is going to eventually stop as we approach the fundamental materials limit. Moreover, the power dissipation due to the increased number of transistors is also expected to be a limiting factor for processor performance.

Superconducting computing has been suggested as a promising approach for low-energy, power-efficient circuit applications. Moreover, using superconducting interconnects can further reduce power consumption. Josephson junction field-effect transistors (JJFET, Fig. a) have recently emerged as a promising candidate for superconducting computing. JJFETs are particularly useful for low power consumption applications as they are operated with, in the superconducting regime, zero voltage drop across its source and drain. Feasibility of using JJFETs for logic operations has been explored [1]. Moreover, high noise margin has been demonstrated for the logic inputs [2]. Compared to single flux quantum approach, JJFET circuits can use designs similar to conventional silicon MOSFETs [1].

For JJFETs to perform logic operations, the gain-factor (αR) value must be larger than 1. Here αR = dIc/d(Vg–Vt) x πΔ/Ic, Δ is the superconducting gap, Vg the gate bias voltage, Vt the threshold voltage. Ic ∝ exp(-L/ξc) is the critical supercurrent, where L is the channel length and ξc the carrier coherence length [3]. In a conventional JJFET, ξc ∝ (Vg–Vt)0.5 (Fig. b), and thus dIc/d(Vg–Vt) is small (Fig. c). This translates to a requirement of superconducting transition temperature of ~ 400K for αR larger than 1, far exceeding any recorded critical temperatures. As such, it is impossible to use conventional JJFETs for logic operations.

Here, we propose a novel type of JJFET based on quantum phase transition, such as the excitonic insulator (EI) transition in a type-II InAs/GaSb heterostructure [4,5], for low-energy, power-efficient logic applications. The nature of the collective phenomenon in the EI quantum phase transition can provide a sharp transition of the supercurrent states (e.g., ξc ∝ (Vg–Vt)5 and dIc/d(Vg–Vt) very large, as shown in Figs. b and c, respectively) which will enable αR larger than 1 with an easy-to-achieve superconducting transition temperature of ~ 40K. In this talk, we will present some preliminary results demonstrating that indeed the gain factor in these quantum enhanced JJFETs can be greatly improved, thus making them a promising candidate for logic applications.

Sandia National Laboratories is a multimission laboratory managed and operated by NTESS LLC, a wholly owned subsidiary of Honeywell International Inc. for the U.S. DOE’s NNSA under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. DOE or the United States Government.

References:

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L. Du et al., Nature Communications 8, 1971 (2017).

W. Yu et al., New J. Phys. 20, 053062 (2018).

Figure caption:

(a) A schematic of JJFET device structure. (b) Schematic density dependence of carrier coherence length ξc vs. gate voltage in classical and quantum JJFETs, respectively. (c) The corresponding current Ic in classical and quantum JJFETs.

Figure 1