bluuebunny/crossref_metadata_2025 huggingface dataset:
Further Advances in the Electrical Charaterisation of Silicon-Insulator Interface Traps using Charge Pumping
Authors: Bauza Daniel , Bayon Sébastien , Ghobar Oussama
Published: April 2007

A rigorous analysis of the charge pumping (CP) mechanisms has been proposed recently. Accounting for, in this analysis, traps depth distributions in the direction of the oxide depth, provides a general model for CP. In the case of the conventional Si-SiO2 interface, this allows the CP curves to be simulated in all the experimental conditions. For that, the trap depth concentration profiles measured after assuming tunnelling for the capture of carriers are used. The energy and depth position of the traps entering the CP curves can be determined. A new spectroscopic CP technique is also proposed. It allows the separate investigation of the traps situated at the Si-SiO2 interface and of those located further towards the insulator depth. The traps situated at the Si-SiO2 interface are finally studied.
Transfer of a Positive Fixed Charge between Si and SiO2 in a Si/SiO2 Interface with Hydrogen Migration
Authors: Ushio Jiro , Maruizumi Takuya
Published: April 2007

The transfer reaction of the positive fixed charge at the Si/SiO2 interface accompanied by hydrogen migration, which is a basic phenomenon to consider negative-bias temperature instability, was investigated using the ab initio molecular orbital method. Comparing the activation energies, we determined the most likely reaction path. We found that the reaction path can be stabilized more by migration of an electrically neutral H atom from a Si substrate to a positively charged O atom than by migration of a proton from a Si substrate to an electrically neutral O atom. The calculated atomic charges and atomic spin densities also supported our conclusion.
Optimizing the Interface of Spin-on Oxide and the Active Area of Transistor in Sub70nm DRAM Structures For Better Electrical Performance
Authors: Das Arabinda , Sperlich Hans-Peter , Heidemeyer Henry
Published: April 2007

The goal of this work is to investigate the interface between the active area (AA) and Spin-on oxide to improve device properties. Various liners, like oxide/nitride liners were deposited prior to spin-on oxide and several annealings were done, including ultra-violet (UV) treatment to fabricate a cleaner interface between the dielectric and the active areas. The role of liners is also to protect and reduce Si consumption during annealings in an oxidizing atmosphere. The impact of these liners on electrical parameters is discussed in this paper.
SrTiO3 Thin Film Growth by Atomic Layer Deposition Using Ti(O-iPr)2(thd)2, Sr(thd)2, and H2O
Authors: Lee Sang Woon , Kwon Oh Seong , Han Jeong Hwan , Hwang Cheol Seong
Published: April 2007

SrTiO3 (STO) thin films were deposited by atomic-layer- deposition (ALD) at a higher temperature (370{degree sign}C) using Ti(O-iPr) 2(thd)2 and Sr(thd)2 as Ti-, and Sr-precursors, respectively, and H2O as the oxidant, in order to improve the crystallinity and film density. With these precursors, the ALD process window of the STO film could be extended up to 400{degree sign}C. With the help of a seed-layer, more dense and well-crystallized STO films could be obtained even in the as-deposited state. The adoption of a seed-layer and the seed-layer annealing temperature are the crucial factors for obtaining high capacitance. In the case of a planar capacitor structure consisting of Pt/STO (27nm)/Ru(bottom), an equivalent oxide thickness of 0.73nm and leakage current density of 1x10-7 A/cm2 at 1V were achieved.
Rare-Earth Metal Oxides and their Silicates/Aluminates as Future Gate Dielectric Films
Authors: Sakai Akira , Sakashita Mitsuo , Ogawa Masaki , Zaima Shigeaki
Published: April 2007

Pr silicate and (La2O3)1-x(Al2O3)x composite silicate films have been synthesized. In the fabrication process developed in this study, metal oxide-based films deposited by molecular beam epitaxy or pulsed laser deposition are subjected to high temperature post-deposition annealing (PDA). The PDA effectively induces intermixing of a parasitic interfacial layer with the upper high dielectric constant film and forms a homogeneous film without the interfacial layer, realizing reduced capacitance equivalent oxide thickness as a gate dielectric. Physical and chemical structures of the synthesized films were systematically analyzed as well as their electrical properties.
Resistance Switching Characteristics of Metal Oxides for Nonvolatile Memory Applications
Authors: Dong Rui , Lee Dongsoo , Xiang Wenfeng , Seong Dong-Jun , Oh Seokjoon , Choi Hyejung , Hwang Hyunsang
Published: April 2007

The resistance switching of several oxides has been reported for nonvolatile memory applications (NVM), recently. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices are not sufficient for gigabit NVM applications. In this paper, we have investigated the electrical characteristics of various binary oxides and ternary oxides for NVM. First, the non- stoichiometric polycrystalline oxides (Nb2O5, ZrOx) have been evaluated. Subsequently, the resistive switching of CuxO and heavily Cu doped MoOx film has been investigated for the compatibility to modern CMOS. Single crystal Nb-doped SrTiO3 (NbSTO) also been investigated, and the Pt/single crystal NbSTO Schottky junction exhibits excellent memory characteristics. To introduce single crystal NbSTO into CMOS process and reserve its excellent electrical characteristics, epitaxial NbSTO film has been deposited on Si substrate using conducting TiN as a buffer layer, and good uniformity and reproducibility of Pt/NbSTO Schottky junction are demonstrated.
Mechanism of Static and Dynamic Bias Temperature Instability in p- and n-MOSFETs
Authors: Nakajima Anri , Zhu Shiyang
Published: April 2007

The BTI-induced degradation of device performance has been ascribed to interface trap generation (ΔNit) and oxide charge buildup (ΔNot) at or near the SiO2/Si interface. Moreover, it has been widely recognized that degradation under dynamic BTI stressing may differ from that under static stressing. In this paper, our recent studies on BTI are reviewed. First, a modified direct-current current-voltage (DCIV) method is proposed, which can monitor ΔNit and ΔNot separately, and is independent on the measurement temperature. Second, negative BTI in pMOSFETs with ultrathin plasma-nitrided SiON gate dielectrics is systematically studied, as well as the effect of nitrogen concentration, using the modified DCIV method. Third, dynamic BTI with is studied at various stressing configurations. A transient degradation enhancement is observed upon quick gate voltage reversal from the accumulation bias to the inversion bias. Finally, a modified reaction-diffusion model is proposed to consistently explain the observed static and dynamic BTI behavior.
NBTI Mechanism Based on Hole-Injection for Accurate Lifetime Prediction
Authors: Teramoto Akinobu , Kuroda Rihito , Ohmi Tadahiro
Published: April 2007

The evaluation method of Negative Bias Temperature Instability (NBTI) based on hole-injection is proposed for accurate lifetime prediction of MOS devices. The acceleration parameters are most important for accurate lifetime prediction. Proposed acceleration parameter is not the applied voltage to the gate insulator film and the temperature but the injected hole injection quantity to the gate insulator film. The degradation mechanism in the excessive voltage and excessive temperature stresses are different from that in the operation conditions. In the relatively high hole-injection stress, the mechanism is also different from that in the operation conditions. It is considered that the difference is caused by the excess enhancement of the hole energy in the inversion layer. In the relatively low hole-injection stress, the degradation mechanism becomes the same as that in the operation conditions. The accurate lifetime prediction in MOSFET level and circuit level can be realized by hole-injection acceleration method.
Contribution of As-grown Hole Traps to NBTI
Authors: Chang Mo H. , Wang Yangang , Zhang Jian F. , Zhao Ce , Zhang Weidong , Xu Mingzhen
Published: April 2007

The increase in nitrogen concentration in the gate SiON enhances the negative bias temperature instability (NBTI) to such a level that it is limiting the lifetime of pMOSFETs. Despite early efforts, our understanding of it is incomplete. Confusions exist on the relative importance of positive charge in SiON for NBTI. Recently, tree different types of positive charge have been identified and this complicates the case further. There is little information on the contribution of each type of positive charge to NBTI. The objective of this work is to investigate the impact of one type positive charge, as-grown hole trapping, on NBTI. To suppress the charge loss during the measurement, the 'on-the-fly' technique is adopted. The as-grown hole trapping measured during negative bias temperature stress (NBTS) for sub-3nm SiON is compared with that in relatively thick SiO2 (>5nm), based on the well- established substrate hole injection technique. The saturation level in these two cases is similar. However, the capture cross section is three orders of magnitude apart. Numerical simulation is carried out to reconcile this difference. The result shows that as-grown hole trapping can dominate NBTI at short stress time, but its relative contribution reduces for longer time.
Toward Understanding the Wide Distribution of Time Scales in Negative Bias Temperature Instability
Authors: Kaczer Ben , Grasser Tibor , Fernandez Raul , Groeseneken Guido
Published: April 2007

Difficulties with evaluating Negative Bias Temperature Instability (NBTI) are linked to fast effects occurring at microsecond or possibly faster time scales. The wide distribution of time scales involved in NBTI relaxation suggests participation of some sort of dispersion in the underlying NBTI mechanism. A universal behavior of the relaxation is observed and used to benchmark several models incorporating dispersion. The impact of the boundary condition on the model based on dispersive transport is also briefly discussed. Furthermore, on-chip circuits are designed and fabricated to measure the effect of AC NBTI up to 2 GHz on individual devices. The results on both single pFET's and inverters indicate that AC NBTI is independent of the frequency in the entire 1 Hz - 2 GHz range. This suggests that any characteristic time scale of the NBTI mechanism must be below 1 ns.
Modeling and Characterization of Negative Bias Temperature Instability in p-Channel MOSFETs
Authors: Yang J. B. , Chen Tupei , Tan S. S. , Ng C. M. , Chan L.
Published: April 2007

Negative bias temperature instability (NBTI) of nitrided gate oxides prepared with different nitridation process is characterized and the NBTI results can be well described by an analytical reaction-dispersive-diffusion model in the diffusion-limited regime. The activation energies are re- calculated by eliminating the non-Arrhenius part, and it confirms that both the interfacial nitrogen concentration and the nitrogen depth profile in the nitrided oxides play important roles in the nitrogen-enhanced NBTI. Furthermore, first-principles calculations are carried out to examine the effects of nitrogen as either the reaction site or the neighboring atoms at the interface. Lower reaction energies due to the incorporation of nitrogen suggest that nitrogen is a more effective hydrogen-originated hole trapping center than oxygen, and hence enhances NBTI. It is also found that hydrogen-originated hole trapping at vacancy defect has the strongest dependence on the nitrogen neighboring effect. Moreover, the role of nitrogen in NBTI is also investigated in terms of its influence on the electro-negativity and atomic charge distribution.
An Assessment of Mobility Variation during Negative Bias Temperature Stress
Authors: Zhang Jian F. , Chang Mo H.
Published: April 2007

The negative bias temperature instability (NBTI) has been intensively investigated recently, since it is limiting the lifetime of pMOSFETs. Attention has been focused on the shift of threshold voltage and there is less information available on the mobility variation during the stress. The objective of this work is to assess the effective mobility variation during negative bias temperature stress (NBTS). To avoid the loss of charges during measurement, the 'on-the-fly' technique is adopted. Before this technique can be used to assess the mobility variation, efforts are made to justify the high level threshold voltage shift through clarifying how the mobility variation is taken into account by this technique. It will be shown that the on-the-fly technique experimentally mimics the numerical solution of a differential equation and the underlying assumption is analyzed. Against the expectation, it is found that the effective mobility actually increases during NBTS, although the low field mobility reduces. This is because the build-up of positive charges reduces the electrical field in the substrate under a constant negative gate bias during NBTS, which in turn enhances the effective mobility.
Dramatic Improvement of Vfb Shift and Gmmax with Ultra-thin and Ultra-low-leakage SiN-based SiON Gate Dielectrics
Authors: Muraoka Kouichi , Matsushita D. , Nakasaki Y. , Kato K. , Kikuchi S. , Sakuma K. , Mitani Y. , Eguchi K. , Takayanagi Mariko
Published: April 2007

The understanding of the mechanism of Vfb shift and the improvement of the [N]-Vfb shift relationship are essential for realizing SiON film with superior device performance. By forming the smooth SiN film with high-density N-Si3 structure and suppressing the deterioration of Si-N network due to oxidation, SiON films dramatically improved in terms of the [N]-Vfb shift relationship, with ultra-thin EOT (0.71 nm), ultra-low leakage current (134 A/cm2) and high Gm
max (115%), are realized. The middle temperature and low-pressure nitridation and the optimization of oxidation conditions are the keys to forming defect-free perfect Si3N4 and SiON films and to achieving these performances.
Non-Uniform Distribution of Electron Traps Generated by FN Stress in Silicon Dioxides
Authors: Zheng Xuefeng , Zhang Weidong , Zhang Jian , Hao Yue
Published: April 2007

The generation of electron traps in gate dielectrics is one major concern in MOS device reliability. It is generally believed to be the main cause for the breakdown of gate oxides. The distribution of generated electron traps across the gate dielectrics has drawn substantial amount of research interests. While many results support a uniform distribution, the others disagree. This work provides direct experimental evidences for the non-uniform distribution. After taking into account the empty electron traps, and correcting the effects of positive charges and interface states, a non-uniform distribution with more electron traps near the substrate/oxide interface was observed. The non-uniform distribution of generated electron traps will have great impacts on the prediction to oxide breakdown and stress-induced leakage current (SILC).
Stress-Induced Leakage Current in Magnetic Tunnel Junctions with Thin AlOx Barrier
Authors: Mihara Tadashi , Kamakura Yoshinari , Morifuji Masato , Taniguchi Kenji
Published: April 2007

The degradation of magnetic tunnel junctions (MTJs) with AlOx barrier was experimentally investigated. Constant voltage stress was applied to MTJs, and time evolution of the conductance and the tunneling magnetoresistance (TMR) ratio were monitored. The gradual increase of the stress-induced leakage current (SILC) was observed prior to the breakdown following a power law function of the stress time, which is similar to the case of the ultrathin gate oxide films in Si-MOSFETs. The measured results suggest that the spin-dependent SILC component is involved in the early stage of the stress. Then, the spin-independent conduction becomes dominant as the degradation progresses, resulting in a reduction of TMR ratio.
Extensive Study of the Correlation between Contact Etch Stop Nitride film Properties and Negative Bias Temperature Instabilities Measured in pMOSFETS
Authors: Benoit Daniel , Morin Pierre , Perrier Frank , Chaton Catherine , Charleux Marion , Regolini Jorge , Barla Kathy , Ferreira Paul
Published: April 2007

Mobility enhancement by process induced strain in the Si channel has been extensively used since 90nm node to improve transistor drive current. Such technique becomes mandatory to compensate scalability limits of several processes like ultra thin gate oxide growth. The Contact Etch Stop nitride Layer (CESL) is the most commonly used method to get stress induced mobility enhancement. However, the re-engineering of this nitride layer for stress enhancement needs to cover all electrical aspects including reliability characteristics, in particular the Negative Bias Temperature Instabilities (NBTI). In this work, we confirm that pMOS NBTI can be significantly impacted by the nitride CESL properties. A Design Of Experiment methodology allows demonstrating that the NBTI is enhanced by the nitride weight density, linked to hydrogen diffusivity within the film. It is finally shown that the nitride density must be set as low as possible to minimize the NBTI.
Impact of Positive Charges on NBTI Degradation and Characterization in Ultra-Thin SiON Gate Dielectrics
Authors: Lei Jin , Xu Mingzhen
Published: April 2007

Impact of positive oxide charges on NBTI degradation and characterization was studied in this work. It was found that the subthreshold swing shifts extracted by Id-Vg characteristic measurements are significantly affected by the gate voltage sweep directions. Further experimental results demonstrate that positive oxide charge is responsible for the observed phenomena, simultaneously providing new evidence for the importance of positive oxide charges in NBTI degradation and recovery. Neutralization (and re-charge) of positive charges during the measurements is considered to have significant influence on NBTI characterization. Our results show that the impact of positive oxide charges on the NBTI degradation and characterization should be taken into consideration seriously.
CaCu3Ti4O12, a Novel Material for Capacitive Applications: Thin Film Growth and Characterization
Authors: Lo Nigro Raffaella , Toro Roberta G. , Malandrino Graziella , Fragalà Ignazio L. , Fiorenza Patrick , Raineri Vito
Published: April 2007

Recently a simple and low cost route to produce high quality CaCu3Ti4O12 (CCTO) films adopting a multimetal molten single source, consisting of Ti(tmhd)2(i-Opr)2, Ca(hfa)2tetraglyme and Cu(tmhd)2 [Hhfa= 1,1,1,5,5,5-hexafluoro-2,4-pentanedione; tetraglyme= 2,5,8,11,14-pentaoxapentadecane; Htmhd= 2,2,6,6- tetramethyl-3,5-heptandione; i-Opr = iso-propoxide] precursor mixture has been realized by Metal-organic chemical vapor deposition (MOCVD) technique. The CCTO films have been deposited on different substrates, such as LaAlO3 (100) single crystal substrates and Pt conductive electrodes. Film structural characterization has been carried out by X-ray diffraction (XRD), while the morphological characteristics and chemical composition have been investigated by Transmission Electron Microscopy (TEM), Scanning Electron Microscopy (SEM) and Energy Dispersive X-Ray (EDX) analysis. The structural and morphological characteristics strongly depend on substrate nature while the chemical composition is almost identical in any case, thus indicating that no chemical interaction occurs between films and any kind of substrates.
SiN Conductivity and Capacitor Reliability
Authors: Drandova Gergana , Beall John M. , Decker Kenneth D.
Published: April 2007

Room temperature DC ramp voltage I-Vs for three different thicknesses of silicon nitride MIM capacitors fit a conduction mechanism due to Frenkel-Poole emission with deviation at low voltages due to space-charge effects. A dielectric constant value of 6.1, extracted from the I-Vs, confirms the conduction mechanism chosen. Frenkel-Poole conductivity is the basis of a published model predicting capacitor life times. Constant voltage life test data show that this model provides a useful lower bound on capacitor life times. Silicon nitride robustness under transient conditions was assessed via human body model tests. For small capacitors, ESD robustness is doubled by using twice the area or twice the dielectric thickness; however, for large capacitors, thinner dielectric results in higher HBM failure voltages. Dielectric leakage allows for safe dissipation of transient charges. Transient simulations incorporating Frenkel-Poole based leakage show good correlation between HBM failure voltage and constant voltage capacitor breakdown.
On-Wafer Test Method of Metal-Insulator-Metal Capacitor Life using Time Dependent Dielectric Breakdown
Authors: De Bhola N. , Shokrani Mohsen
Published: April 2007

We have developed a novel test method for on-wafer measurement of median time to failure (MTTF) of MIMCAP dielectric under an applied electric field using the concept of Time Dependent Dielectric Breakdown (TDDB). This method requires a small number of samples on wafer, and the tests are relatively quick. The feedback on dielectric quality to production team occurs much sooner than what is possible using conventional TDDB test method. We have also measured MTTF of MIMCAP dielectric using an alternate method called the Ramp Voltage Test, and compared the results with MTTF data from the TDDB method. The results from these two methods were in good agreement. This has enabled us to employ the on-wafer TDDB test method to assess the MIMCAP nitride quality in production and engineering environment.
Influence of Oxide Breakdown Percolation Resistance on MOSFETs (Invited Paper)
Authors: Pey Kin Leong , Lo Vui Lip , Tung Chih Hang , Lim Wai Tat , Ang Diing Shenp
Published: April 2007

A method is developed to measure the effective resistance associated with a percolation path formed during gate oxide breakdown (BD). The evolution of percolation resistance (Rperc) and channel resistance (Rch) during progressive BD (PBD) is studied in details. Our results reveal that PBD is constituted by the Rperc- and the Rch-controlled region. Additionally, Rperc is found to be a temperature- and voltage-dependent parameter, implying that PBD under different stressing conditions could be governed by different mechanisms. According to finite element analysis and infrared photoemission microscopy, a high localized temperature in the vicinity of the BD spot could exist to trigger dopant redistribution and microstructural damages. The change in diode I-V characteristics at the substrate-source/drain junction acts as a signature for the occurrence of dopant redistribution. This is confirmed by the simulation results of TSUPREM. The narrow device structures further enhance the localized heating effect during BD due to heat confinement.
Plasma Etching Technology for Low-k Porous SiOCH Films
Authors: Hori Masaru
Published: April 2007

An environmental friendly gas, C5F10O, has been proposed for etching low-k SiOCH films using dual frequency (60MHz/2MHz) capacitively coupled plasma. The main ion produced is CF3+, as compared to CF+ produced by the conventional c-C4F8 gas. The advantage of CF3+ over CF+ is the much higher etching rate. With the new etching gas, a high etching rate of about 1000 nm/min with a vertical profile pattern can be achieved. The damage to SiOCH films induced by light, radicals and ions were systematically evaluated. It was found that the most severe damage was caused by ions, followed by VUV. The resist materials can be selectively removed with respect to SiOCH with less damage by employing an O2/Ar surface wave excited plasma. An advanced plasma etching technology with controlled radicals has thus been introduced.
Luminescence from Si Nanoclusters Formed in Silicon Oxide and Silicon Nitride Based Materials
Authors: Roschuk Tyler , Zalloum Othman H. , Wojcik Jacek , Zhang Haiqiang , Mascher Peter
Published: April 2007

Si nanoclusters embedded in two different dielectric matrices, silicon oxide and silicon nitride, have been formed through annealing of Si-rich silicon oxide (SRSO) and Si-rich silicon nitride (SRSN) thin films. The light emitting properties of these materials have been analyzed through room temperature UV-excited photoluminescence (PL) experiments. Features of the PL spectra from both types are presented and the nature of light emission from Si-nanoclusters is discussed on the basis of the results from these two different host environments.
Low Temperature Silicon Nitride Deposition by Inductively Coupled Plasma CVD for GaAs Applications
Authors: Kim Harqkyun , Lee Youngkyu , Ra Yunju , Li G. P. , Yota J.
Published: April 2007

In order to take advantage of silicon nitride films as an ILD layer on GaAs devices, the ICP CVD silicon nitride films were investigated by parametric study of effects of deposition parameters on the physical properties of silicon nitride film deposited in the range of 50 ~ 200oC temperature. Good quality of films could be achieved, including low moisture absorption, low H content (<15 at.%), good resistance to BOE etching (<50 Aå/min), smooth film surface (2.0 nm roughness), and reasonable film stress, as compared to the conventional PECVD nitride film, while the process temperature is much lower than the conventional PECVD process. This silicon nitride film was applied to the GaAs HBT device structure and showed very promising results of the gap-filling capability and planarization for next level of metallization. These results indicate the possibility of using the ICP CVD silicon nitride films as an ILD layer in the GaAs devices instead of polymer type dielectrics, which typically require a long cure time at high temperature of 300oC or higher.
Photoluminescence from Magnetron Sputtered SiO2 Films Co-doped with (Er, Ge) under Excitation of a 325 nm He-Cd Laser Line
Authors: Heng Chenglin , Zalloum Othman H. , Chelomentsev Evgueni , Mascher Peter
Published: April 2007

We have studied photoluminescence (PL) from SiO2 films co- doped with (Er, Ge) deposited by magnetron sputtering of an Er+Ge+SiO2 composite target in pure Ar ambient. Under excitation of a 325 nm He-Cd laser line, blue emission bands around 400 nm and near infrared bands around 800 nm have been observed, which are attributed to Ge-related defects and Ge nanoclusters (Ge-ncls), respectively. Strong Er3+ PL at 1.54 μm was also observed from the films, while the Er PL intensity of a control Er-doped SiO2 film (i.e., without Ge), is negligible under the same excitation. All the PL intensities vary as functions of thermal annealing temperatures. The results demonstrate that the significant enhancement of Er PL in the (Er, Ge) co-doped SiO2 films are due to the incorporation of Ge. The roles of Ge-ncls and Ge-related defects to the Er3+ excitation are discussed.
Innovative Low damage Silicon Nitride Passivation of 100nm In0.45AlAs/In0.4GaAs Metamorphic HEMTs with Remote ICPCVD
Authors: Kim Donghwan , Maeng Jimin , Kim Sungwon , Her Jincherl , Yeon Seongjin , Kim Harqkyun , Seo Kwangseok
Published: April 2007

In this paper, a novel low-damage silicon nitride passivation for 100 nm In0.45AlAs/In0.4GaAs MHEMTs has been developed using remote ICPCVD. The silicon nitride deposited by ICPCVD showed higher quality, higher density, and lower hydrogen concentration than those of silicon nitride deposited by PECVD. In particular, we successfully minimized the plasma damage by separating the silicon nitride deposition region remotely from ICP generation region, typically with distance of 34 cm. The silicon nitride passivation with remote ICPCVD has been successfully demonstrated on GaAs MHEMTs with minimized damage. The passivated devices showed considerable improvement in DC characteristics and also exhibited excellent RF characteristics (fT of 200 GHz).The devices with remote ICPCVD passivation of 50 nm silicon nitride exhibited 22 % improvement (535 mS/mm to 654 mS/mm) of a maximum extrinsic transconductance and 20 % improvement (551 mA/mm to 662 mA/mm) of a maximum saturation drain current compared to those of unpassivated ones, respectively. The results achieved in this work demonstrate that remote ICPCVD is a suitable candidate for the next-generation MHEMT passivation technique.
Effects of High-Temperature Porogens on Materials Properties of Novel 2-Pahse Low-k Dielectrics
Authors: Che Mu-Lung , Leu Jihperng , Chen Yu-Hen , Huang Cheng-Ying , Choang Shindy
Published: April 2007

A solid-first scheme was employed for making ultra low-k materials (k < 2.5) based on methylsilsesquioxane (MSQ) and high-temperature porogens in order to circumvent the reliability issues related to as-deposited porous dielectric. Based on thermal stability data, the MSQ/poly(styrene-b-4- vinylpyridine) material system was recommended to be cured at 300 {degree sign}C for subsequent backend processes, and the porogen to be removed at 400 {degree sign}C for 2 hours after CMP step. The mechanical properties of ultra-low-k films used in different integration schemes were further investigated using nano-indentation and FT-IR for various porogen loading. The moduli of 2-phase films were higher than their porous films, and even better than dense MSQ, for porogen loading below a critical level (~50%), which could be attributed to their enhanced degree of crosslinking in MSQ. In addition, MSQ/porogen films cured at 300 {degree sign}C possessed good elastic modulus (> 4.0 GPa) to pass CMP test.
Three-Dimensional Compositional Characterization of High-k Gate Dielectrics with LEAP Atom Probe Tomography
Authors: Ulfig Robert M. , Thompson Kieth , Alvis Roger , Bunton Joeseph , Gorman Brian , Larson David
Published: April 2007

Laser pulsed atom probe tomography (APT) is used to quantitatively analyze oxides of interest to enable the timely the development of high-k gate dielectric films. Specific analysis of hafnium dioxide films, provided by IBM and characterized using the local electrode atom probe (LEAP®), transmission electron microscopy (TEM), and Secondary Ion Mass Spectroscopy (SIMS) are compared and contrasted. A variety of LEAP tomography data analysis techniques will be discussed, including thickness measurements, surface definitions, and buried interface surface roughness calculations based on iso- chemical concentration surfaces. This work demonstrates the ability of the LEAP technique to rapidly and accurately characterize the complex composition and structure of novel high performance semiconductor devices with sub-nanometer resolution. The compositional and spatial information is used to quantify the differences which subtle surface preparation changes have upon the interfacial region for a high-k gate dielectric film.
The Impact of F and N Incorporation Technique on Advanced Gate Stacks
Authors: Yugami Jiro , Hayashi Takashi , Nishida Yukio , Inoue Masao
Published: April 2007

Control of threshold voltage (Vth) is a common and serious problem for realizing scalable LSIs with either nitrogen rich SiON, high-k gate dielectrics, or metal gates. In this paper, we demonstrate the improvement of HfSiON pMISFETs characteristics with the F incorporation technique, which may prove to be a powerful tool for lowering |Vth| in pMISFET with both poly-Si and metal gates. Using F implantation in the channel region prior to HfSiON formation, |Vth| lowering up to ~200mV is obtained without mobility degradation. In the same manner as the F incorporation technique, N incorporation is useful for reducing Vth value in nMISFETs. Furthermore, the impact of F incorporation in HfSiON is investigated in terms of reliability. From a comparison of the F incorporation effect on SiON and HfSiON gate dielectrics, we have proposed a model for the F passivation of defects in both HfSiON and the HfSiON/Si interface.
Electrical Characterization of Advanced Gate Dielectrics
Authors: Ma T.P.
Published: April 2007

The following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects associated with advanced gate stacks will be reviewed: (1) Inelastic Electron Tunneling Spectroscopy (IETS), (2) lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of a MOSFET, (3) separation of interface traps from bulk dielectric traps; and (4) PASHEI (Pulse Agitated Substrate Hot Electron Injection) technique for measuring trapping effects in the gate dielectric.
Identifying Contributions to Electrical Instability in High-k Gate Stacks: As-Grown vs. Generated Defects
Authors: Bersuker Gennadi , Lysaght Patrick , Choi Rino
Published: April 2007

Stress-induced changes in the high-k gate stack electrical characteristics may originate in both the Hf-based dielectric film and the SiO2-like interfacial layer, in which instability could be induced by different mechanisms. In this work, we focus on the contributions from as-grown defects and defect precursors in each of these layers, as well as stress-generated defects, under low and high voltage stress regimes. Physical data, consistent with ab initio calculations, is presented in support of proposed theoretical explanations for the mechanisms that give rise to electrical performance.
Aqueous-Base-Developable Benzocyclobutene-Based Dielectric Material - An Emerging Dielectric Material for Microelectronics
Authors: So Ying-Hung , Stark Edmund , Kisting Scott , Scheck Dan , Baranek Kayla , Toepper Michael , Baumgartner Tobias
Published: April 2007

A self-priming and photosensitive aqueous-base-developable benzocyclobutene (BCB)-based dielectric material curable in air is described. The polymer is made from divinylsiloxane benzocyclobutene and BCB-acrylic acid. Patterned films have high resolution, and via openings are scum-free without a descum operation. Whether cured in nitrogen or in air, the formulation produces a film with optical, electrical, thermal, and mechanical properties desired for many microelectronic applications, such as packaging applications and a planarization layer or insulation layer in display applications.
New Polyimides Coating Technology for Next Generation Semiconductor Application
Authors: Katoh Kohji , Ohe Masayuki , Komatsu Hiroshi , Motobe Takeharu , Hattori Takashi , Ueno Takumi
Published: April 2007

In this paper, new polyimide coating technologies will be reported that are useful for next generation semiconductor applications. Traditionally, polyimide materials (PI) have been used as stress buffer and rewiring cover layers to improve semiconductor reliability. However, over recent years, due to process cost reduction, conventional PI has gradually been replaced by photosensitive PI (PSPI). In order to meet the next generation semiconductor applications for stress buffer and packaging, photolithographic performance, Cu compatibility, thicker film thickness formability and low temperature cure are critical process properties that need to be addressed. Development of functional PSPI technologies at HDM to meet each of these needs will be discussed in this paper.
Investigation of Scaling Limits for PECVD SiN and ALD HfO2/Al2O3 Integrated MIM Capacitors
Authors: Dornisch Dieter , Wilk Glen , Li Guangming , Ring Kenneth M M. , Howard David J J. , Racanelli Marco
Published: April 2007

Scalability of MIM capacitors to higher capacitance densities is commonly limited by increasing leakage current and dielectric breakdown as the dielectric film is being made thinner. MIM Capacitors using PECVD SiN with up to 4fF/μm2 capacitance density and high-k ALD HfO2/Al2O3 dielectrics with up 12 fF/μm2 capacitance density have been developed and characterized for VLSI RF-CMOS and BiCMOS technologies with up to 5.5 V power supply voltage. Linearity, matching, and reliability were found to be generally degraded with increased capacitance density. Improved linearity could be achieved with dielectric film optimization and stacking of capacitors. TDDB lifetime of PE-CVD SiN MIM capacitors with 2.7 fF/µm2 and of ALD high-k MIM capacitors with capacitance densities from 5 fF/µm2 to 7.4 fF/μm2 show suitability for applications up to 3.6V using a conservative reliability model.
Radiation Induced Charge Loss Mechanisms Across the Dielectrics of Floating Gate Flash Memories
Authors: Cellere Giorgio , Cester Andrea , Paccagnella Alessandro
Published: April 2007

One of the key factors permitting the extraordinary success of floating gate (FG) nonvolatile memories relies on the excellent insulating properties of the dielectric layers surrounding the FG itself. Among other threats, ionizing radiation may effectively affect such insulating characteristics, leading to a degradation of the FG stored charge. Radiation effects have been traditionally studied for niche applications such as the high energy physics or the satellite industry. However, modern semiconductor technologies are becoming more and more sensitive to the deposition of small amounts of charge, such as those generated by the byproducts of atmospheric neutrons, and FG memories are in fact aggressively scaled following Moore's law predictions. Loss of information may derive from two broad categories of phenomena, Total Ionizing Dose and Single Event Effect, whose actions on the FG dielectrics are reviewed in this contribution from the viewpoints of the prompt induced damage and long-term degradation effects, affecting the memory retention capabilities.
High dose Implantation Impact on the Carrier Mobility in Ultra-Thin Unstrained and Strained SOI Films
Authors: Dupre Cecilia , Fazzini Pier Francesco , Ernst Thomas , Cristiano Fuccio , Hartmann Jean-Michel , Claverie Alain , Andrieu François , Faynot Olivier , Rivallin Pierrette , Laugier Frédéric , Ghibaudo Gérard , Cristoloveanu S. , Deleonibus Simon
Published: April 2007

Based on electrical measurements and transmission electron microscopy imaging we propose in this paper a possible explanation for the measured mobility degradation with gate length reduction in short-channel MOSFETs. The carrier mobility in end-of-range implantation regions was investigated in Silicon-On-Insulator (SOI) and tensily-strained Silicon-On- Insulator (sSOI) substrates. Wafers with ultrathin films (from 8 to 35 nm) were Ge implanted at various concentrations, then annealed. The Pseudo-MOSFET measurements showed a mobility decrease (from 5 to 34%) as the implantation dose increased. The results are relevant for the optimization of the sources and drains regions of advanced nano-scale SOI transistors.
Low Temperature Chatacterization of High-k Dielectric Metal Gate FD-SOI nMOSFETs
Authors: Zafari Leily , Jomaah Jalal , Ghibaudo Gérard , Faynot Olivier , Vandooren Anne
Published: April 2007

Fully Depleted devices with HfO2 dielectric and TiN gate electrode have been studied at different temperatures. Noise measurements have also been carried out on these devices. The effects specific to short channels are evidenced and studied. The precise doping density of the silicon film has also been calculated.
Uniaxial Strain Enhancement in SOI Technology for the Improvement of Channel and Exterior Resistances
Authors: Zhang Da , Goedeke D. , Dhandapani V. , Hildreth J. , Fu C.C. , Kropewnicki T. , Lu A. , Jahanbani M. , Martinez H. , Noble R. , Eades D. , Liu N. , Kang L. , Nguyen B.-Y. , Kolagunta V. , Hall M. , Cheek J. , Venkatesan S.
Published: April 2007

Strain enhancement has been proven a viable enabler for transistor technology scaling. The implementation and performance of source/drain embedded SiGe (eSiGe) for devices on silicon-on-insulator (SOI) substrate are presented. With proper process controls to mitigate substrate challenges, significant PFET drive current improvement is obtained with SOI eSiGe. The impact of dimensional scaling factors on device enhancement is explored, and results demonstrate a good extendibility for eSiGe. It is also demonstrated that an optimized integration can lead to gate dielectric reliability improvement. The eSiGe contributions to the reductions of channel and exterior resistances are quantitatively depicted. Hole motility at high and low vertical fields has been calculated, and results show that the eSiGe enhancement on mobility changes little with vertical field variation.
Heavy Ion Induced Upset Cross-Sections of 150nm SOI CMOS SRAMs Fabricated in UNIBOND
Authors: Liu Michael S. , Nelson Dave K. K. , Tsang Joseph C. , Hughes Harold L.
Published: April 2007

This paper discusses the heavy ion performance of the 150nm SOI CMOS SRAMs with hardened active delay element in the feedback path. The limiting upset cross-section is found to be related to the average resistance of the delay element.
Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications
Authors: Xiong Weize W. , Cleavelin C. Rinn , Hsu Che-Hua , Ma Mike , Schruefer Klaus , Von Arnim Klaus , Schulz Thomas , Cayrefourcq Ian , Mazure Carlos , Patruno Paul , Kennard Mark , Shin Kyoungsub , Xin Sun , King Liu Tsu-Jae , Cherkaoui Karim , Colinge J.P.
Published: April 2007

MuGFET structure improves local transistor mismatch compared to planar bulk MOSFET. This enables further SRAM cell size reduction. GIDL current is well controlled even with a mid-gap metal gate. MuGFETs have low subthreshold leakage if Lg/Wsi ratio is kept above 1.5. The advantage of MuGFET subthreshold leakage suppression is even more pronounced at higher temperatures. Furthermore MuGFETs are compatible with local strain techniques to improve carrier mobility. The aforementioned qualities, along with low manufacturing cost of single mid- bandgap metal gate, make MuGFET a good candidate to replace planar bulk MOSFET for Low-Power Applications.
Parasitic Effects Depending on Shape of Spacer Region on FinFETs
Authors: Kobayashi Yusuke , Tsutsui Kazuo , Kakushima Kuniyuki , Hariharan Venkanarayan , Rao V. Ramgopal , Ahmet Parhat , Iwai Hiroshi
Published: April 2007

Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer region. The trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the spacer region. The gate delay characteristic of the FinFETs was optimized by gradual expansion with triangular shape. It was indicated that not only parasitic resistance but also parasitic capacitance on the spacer region was significant for transistor performance.
Modelling the Back-Gate Coupling effect in Triple-, Π- and Ω-Gate FETs
Authors: Ritzenthaler Romain , Gaillardin Marc , Akarvardar Kerem , Faynot Olivier , Jahan Carine , Cristoloveanu S.
Published: April 2007

In multiple-gate devices, coupling effects due to the 3-D architecture modify the electrical characteristics of the transistor. In this paper, electrical measurements have been carried out in order to examine the role of the back-gate voltage. In agreement with numerical simulations, it is shown that the back-gate influence is reduced for narrow devices due to a strong coupling between the different faces of the main gate. In narrow Fin devices, the Pi- and Omega-shapes of the gate provide an excellent electrostatic control of the field lines and potential, both in the buried oxide and in the silicon channel. The radiation-induced charge trapping in the BOX underneath the channel can be then much limited: narrow Fin devices exhibit a higher tolerance to ionizing radiations than its single-gate counterparts. Additionally, it is shown that the 2D dimensional coupling in these structures can be analytical calculated for Triple- and Pi-gate FETs. These models are compared with numerical simulations and show a very good agreement.
Origin of Transient Gate Current Observed in Pseudo-MOS Transistor
Authors: Sato Shingo , Nguyen Tuan , Cristoloveanu S. , Omura Y.
Published: April 2007

We discuss the origins of the transient gate current observed in the pseudo-MOS transistor in order to extract optional semiconductor parameters and its physical mechanisms. We analyze the time evolution of the gate current; its delay time is long even in quasi-static measurements at low gate voltages. Experiments show that the transient gate current characteristics are ruled by the generation-recombination process in the SOI layer and thermionic emission currents through the source and drain contacts. We address how the evaluate the generation-recombination lifetime in the SOI layer from the transient gate current behavior.
Impact of Improved Mobilities and Suppressed 1/f Noise in Fully Depleted SOI MOSFETs Fabricated on Si(110) Surface
Authors: Cheng Weitao , Teramoto Akinobu , Tye Chingfoa , Gaubert Philippe , Hirayama Masaki , Sugawa Shigetoshi , Ohmi Tadahiro
Published: April 2007

In this study, we reveal that Si(110) surface is flatted using HF(0.5wt%)/H2-UPW solution in N2 ambience without light illumination. We demonstrate that the electron effective mobility on Si(110) is obviously improved by introducing this new chemical surface flattening process. Especially, the improvement of electron mobility become larger while the effective field is increased. As a result, the electron mobility is improved about 1.3 times at the high effective field equals 1MV/cm, which is mostly limited by surface roughness. We consider that the improvement of the electron mobility is originated in the good suppression of surface micro- roughness in this experiment. However, the 1/f noise level is almost the same even introducing the chemical surface flattening process. In this paper, it is observed that the 1/f noise level of MOSFETs on Si(110) is suppressed very well by introducing the novel accumulation mode device structures.
Hot Carrier Instability Mechanism in Accumulation-Mode Normally-off SOI nMOSFETs and Their Reliability Advantage
Authors: Kuroda Rihito , Teramoto Akinobu , Cheng Weitao , Sugawa Shigetoshi , Ohmi Tadahiro
Published: April 2007

This work studies the degradation mechanism of the hot carrier instability in normally-off Accumulatin-Mode SOI nMOSFETs. From the experimental examination of degradations in transistor- transfer characteristics and low frequency noise level at various transistor operation bias regions, it is proposed that the major degradation in the Accumulation-Mode nMOSFETs is the positive charge and interface state generations at the front gate insulator/Si interface at the Drain side due to the injection of hot holes that are generated by impact ionizations caused by channel hot electrons. It is experimentally shown that the Accumulation-Mode nMOSFETs have higher hot carrier immunity than the Inversion-Mode FD-SOI nMOSFETs. Also, effects of the hot carrier stress to the transistor-transfer characteristics are shown to be smaller for devices with higher dopant concentration of SOI layer (NSOI), which originates from the smaller influence of the quality of the front gate insulator/Si interface to the current drivability in higher NSOI devices.
ELECTRONICS AND PHOTONICS DIVISION AWARD ADDRESS: Thin Film Transistor and ULSIC Technologies - Parallel or Crossing?
Authors: Kuo Yue
Published: April 2007

In the last 2 decades, the thin film transistor (TFT) technology has advanced dramatically accompanied with extraordinary growth of market. In this paper, the author compared the history of TFTs and ULSIC as well as their markets. The unique material, process, and device properties of the a-Si:H TFT was responsible for its current success and established the foundation for developments beyond liquid crystal displays (LCDs). Due to different device characters and limits, TFTs and ULSIC have separate application areas. However, they can be properly integrated to create new functions and products. The knowledge obtained from the large- area TFT array studies can help ULSIC migration to 15-inch wafers.