bluuebunny/crossref_metadata_2025 huggingface dataset:
Large Area Plan-View Transmission Electron Microscopy Sample Preparation for Direct-Bonded Interfaces
Authors: Beekley Brett , Roberts C.R. , Salazar M. S. , Goorsky M. S.
Published: September 2014

A focused ion beam (FIB) sample preparation technique is developed to produce large areas of electron transparent material for plan-view transmission electron microscopy measurements from direct-bonded interfaces without thinning the bonded wafers. A FIB cut allows plan-view sample creation from the bonded interface region, and therefore rapid characterization of the defect density as a function of bonding conditions, substrate miscut, or pre-bonding surface treatments. Uniform electron transparent plan-view areas are extracted from the interface region to facilitate observation of the interface reconfiguration. To demonstrate the technique, the electrically active interfaces of a series of bonded III-V structures is studied as a function of substrate miscut as well as in-plane misorientation. Distinct differences in the interface reconstruction are observed and the interface reconstruction produces screw and edge dislocation networks at the III-V interfaces. The degree of twist and tilt is confirmed with both cross section electron microscopy measurements as well as in-plane x-ray diffraction measurements.
Delamination Root Cause in Temporary Bonding
Authors: Vial Karine , Fournel Frank , Wimplinger Markus , Burggraf Jürgen , Bravin Julian , Montméat Pierre , Pellat Michel
Published: September 2014

The goal of the presented work is to study the delamination root cause in temporary bonding using thermoplastic material as adhesive. The parameters potentially involved in this mechanism are defined, and each of them is separately studied. At the end, the combination between some of the parameters is also tested. Finally the mechanism at the root of the delamination is discussed.
(Invited) Heterogeneously Integrated III-V on Silicon Lasers
Authors: Ben Bakir Badhise , Sciancalepore Corrado , Descos Antoine , Duprez Hélène , Bordel Damien , Sanchez Loic , Jany Christophe , Hassan Karim , Brianceau Pierre , Carron Veronique , Menezo Sylvie
Published: September 2014

Silicon photonics has generated an outstanding interest for optical telecommunications and inter/intra-chip interconnects in microelectronic systems. This platform can address a wide range of applications from very short distance data communication to long haul optical transmission. Silicon-based compounds are commonly used in commercial optical waveguide devices for applications such as passive optical interconnects and biomedical sensors. However, the integration of lasers together with Si integrated photonics-electronic circuits has proved to be much more challenging. The complexity lies in the fact that silicon is a poor light-emitting material due to its indirect energy bandgap. A particularly promising approach is based on molecular bonding of III-V materials on top of a patterned Si-on-insulator (SOI) substrate. Hybrid Si/III-V lasers are then realized following a collective fabrication procedure, enabling complex photonic integrated systems onto the silicon platform. In this communication, we describe the hybrid platform and we present the recent advances on III-V/Si lasers and transmitters.
Leak Rates and Residual Gas Pressure in Cavities Sealed by Metal Thermo-Compression Bonding and Silicon Direct Bonding
Authors: Schjølberg-Henriksen Kari , Malik Nishant , Sandvand Asmund , Kittilsland Gjermund , Moe Sigurd Teodor
Published: September 2014

The residual gas pressure (RGP) in sealed cavities was measured by residual gas analysis (RGA). The cavity sealed by fusion bonding had the lowest RGP of 16 µbar. Cavities sealed by Au-Au thermocompression bonding and plasma bonding had RGPs of 0.18 and 0.22 mbar, respectively. The cavity sealed by Al-Al thermocompression bonding had RGP of 1.3 mbar. Cavities sealed by thermocompression bonding contained 0.16 – 0.21 mbar Ar. The leak rates of the four seal types were estimated by three methods. RGA measurements revealed that the maximum leakage rates were between 10-13 and 10-15 mbar·l·s-1.
(Invited) Reactive Bonding with Integrated Reactive and Nano Scale Energetic Material Systems (iRMS): State-of-the-Art and Future Development Trends
Authors: Braeuer Joerg , Besser Jan , Hertel Silvia , Masser Robin , Schneider Werner , Wiemer Maik , Gessner Thomas
Published: September 2014

This paper introduces different principles and deposition methods that use a specific form of local heat generation. Such systems consist of integrated and nano scale energetic material systems. These materials generate heat based on a self-propagating exothermic reaction during inter diffusion. The resulting heat can be used as heat source for bonding processes.
Modeling and Integration Phenomena of metal-metal direct bonding technology
Authors: Di Cioccio Lea , Baudin Floriane , Gergaud Patrice , Delaye Vincent , Jouneau Pierre-Henri , Rieutord François , Signamarcheix Thomas
Published: September 2014

Direct metal bonding represents an advanced joining technology that allows vertical stacking with electrical conduction and even heat dissipation. Direct metal bonding is performed at room temperature, under ambient air and atmospheric pressure. Thus, for most metals used as bonding layers, it involves a surface metal oxide layer. The bonding interface saddles with a trapped oxide layer. This study focuses on the analysis and modeling of metal-metal direct bonding with regards to integration stages such as annealing or layer stacking.
(Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration
Authors: Brunet Laurent , Batude Perrine , Fournel Frank , Benaissa Lamine , Fenouillet-Beranger Claire , Pasini Luca , Deprat Fabien , Previtali Bernard , Ponthenier Fabienne , Seignard Aurélien , Euvrard-Colnat Catherine , Rivoire Maurice , Besson Pascal , Arvet Christian , Beche Elodie , Rozeau Olivier , Billoint Olivier , Turkyilmaz Ogun , Clermidy Fabien , Signamarcheix Thomas , Vinet Maud
Published: September 2014

By stacking transistor levels on each other sequentially, monolithic 3D integration appears to be an alternative solution to scaling. By taking fully advantages of the vertical dimension, circuit partitioning at the transistor scale is then possible. This papers gives the different opportunities offered by such technology and summarizes the technological challenges that raises from this concept. A general overview of the different techniques to create an active layer above a bottom transistor level is presented. Direct bonding from a SOI wafer clearly appears to be currently the best solution to obtain a defect free monocrystalline active layer with a well-controlled thickness. Finally, the challenge of realizing a top transistor level with a low temperature thermal budget is explained. This thermal budget is quantified by studying the electrical stability of the bottom level. Some electrical results on low temperature activated junctions are also presented.
Development of Materials Integration for Laser Gain Media: Single Crystals and Ceramic (Polycrystalline) Materials and Applications
Authors: McKay Jeffrey , Bai Tingyu , Goorsky M. S.
Published: September 2014

Processes for chemical mechanical polishing of yttrium aluminum garnet (YAG) and yttria (Y2O3) using commercial slurries have been developed for subsequent bonding applications. Single crystal and polycrystalline surfaces are polished to below 0.5 nm RMS surface roughness, with a controllable polishing rate of 0.3 nm / min. In addition, high resolution x-ray diffraction measurements show a reduction of subsurface damage after polishing these commercially available substrates. Surfaces are generated with < 0.5 nm RMS surface roughness are suitable for wafer bonding, and are treated with various surface preparation steps prior to bonding. Once bonded at room temperature, samples are heated at 1425° C for 72 hours to further strengthen the bond.
(Plenary) High-Performance Photonic BiCMOS – Next Generation More-than-Moore Technology for the Large Bandwidth Era
Authors: Zimmermann Lars
Published: September 2014

Photonic-electronic integration is highly desirable in modern communication systems and networks where integration is the only means to achieve the targets of increased power efficiency, lower cost, and most importantly bandwidth. Broadband driving circuits in photonic sub-systems are a sweet spot for high-performance BiCMOS technologies because of superior performance of bipolar transistors in this field. Inevitably, tight integration of BiCMOS and photonics will be required to minimize parasitics and to enable the era of large bandwidth. In this talk, our view on the convergence of electronics and photonics in an advanced Morethan- Moore technology will be presented using the example of our own photonic BiCMOS technology development.
(Invited) Towards 0.7 Terahertz Silicon Germanium Heterojunction Bipolar Technology – The DOTSEVEN Project
Authors: Lachner Rudolf
Published: September 2014

DOTSEVEN is a very ambitious European R&D project targeting the development of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) technologies with cut-off frequencies (fmax) of around 700 GHz. The project started in October 2012 and will end in March 2016. It is the continuation of the predecessor project DOTFIVE which succeeded to push fmax of SiGe HBTs into the 500 GHz region for the first time. Besides enhancing the speed performance of the SiGe HBT drastically, the challenging task of its integration into a 130 nm BiCMOS process will be addressed too. The capabilities and benefits of the technology will be demonstrated by benchmark circuits and advanced system applications in the 0.1 to 1 THz range like THz imaging and sensing, wireless Gb/s communications and millimeter-wave radar. Process development and circuit design will be assisted by improved TCAD and physics-based device simulation and accurate compact device modeling.
A Novel Approach to Isolating the Edge of the Shallow Trench Isolation in SiGe HBTs for Improved Device Performance
Authors: Camillo-Castillo Renata A. , Liu Qizhi Z. , Jain Vibhor , Adkisson James W. , Khater Marwan H. , Gray Peter , Pekarik John Jack , Malladi R , Harame D. L.
Published: September 2014

Scaling silicon germanium heterojunction bipolar transistors (SiGe HBTs) to attain simultaneous increases in the figures of merit, fT
and fMAX
has necessitated a deep understanding of the inherent features of the process as it relates to the final device performance. Layout variations in the location of the field polysilicon layer relative to the edge of the active silicon region, results in marked changes in the intrinsic device, with increases in fT/fMAX
of 15/20GHz respectively. Technology computer-aided device techniques are utilized to understand the process and device changes driving the improvements in device performance observed. Three possible theories that relate to changes in the device architecture inherent to the layout variation are examined.
Detection of Ge and Si Intermixing in Ge/Si Using Multiwavelength Micro-Raman Spectroscopy
Authors: Yoo Woo Sik , Kang Kitaek , Ueda Takeshi , Ishigaki Toshikazu , Nishigaki Hiroshi , Hasuike Noriyuki , Harima Hiroshi , Yoshimoto Masahiro , Tan Chuan Seng
Published: September 2014

To meet various physical property requirements of materials for advanced application, for specific devices, combinations of Si/Ge, Ge/Si, Si1-xGex/Si, are frequently introduced in the device fabrication process. Epitaxy, condensation and annealing processes are commonly used. Since a small variation in composition, strain and crystallinity can result in reduced device performance or failure, the composition, strain and crystallinity must be carefully monitored and controlled throughout the manufacturing process. We report the detection of Ge and Si intermixing in epitaxially grown Ge/Si after successive thermal anneals using multiwavelength Raman spectroscopy. We have studied the dependence of Ge and Si intermixing on annealing temperature and Raman excitation wavelength. Very strong dependence of signal-to-noise (S/N) ratio measurements on excitation wavelength and film structure was observed. Suitable excitation wavelengths must be chosen to properly detect and characterize Si and Ge intermixing, based on the stacking order of epitaxial films and thicknesses.
(Invited) Si Ultrathin Films on Silver Surfaces: An Intriguing Epitaxial System
Authors: Leoni Thomas , Bernard Romain , Ranguis Alain , Borensztein Yves , Prévot Geoffroy , Masson Laurence
Published: September 2014

The reported synthesis of two dimensional Si sheets on silver substrates with structural and electronic properties attributed to the formation of silicene recently aroused considerable interest. We present here a review of the state of art concerning the growth of Si ultrathin films on Ag(110), the first system interpreted within the framework of silicene models. In particular, we report in situ measurements using local and macroscopic probes to characterize the structural and optical properties of the Si layer consisting of self-organized Si nanoribbons grown on Ag(110). Our results, together with recent reported theoretical investigations, provide compelling evidence that the Si sheet cannot be interpreted within the framework of current silicene models and that the observed properties result from a subtle interplay between the Si overlayer and the Ag(110) substrate. Finally, we show that the Si grating can be used a novel Si template for the growth of one dimensional nanostructures.
(Invited) UV Excimer Laser Assisted Heteroepitaxy of (Si)GeSn on Si(100)
Authors: Chiussi Stefano , Stefanov Stefan , Benedetti Alessandro , Serra Carmen , Buca Dan , Schulze Jörg , González Pio
Published: September 2014

Fabrication of Photonic Integrated Circuits (PICs) using CMOS compatible direct bandgap Group-IV heterostructures is of increasing concern from scientific, technological, and economic point of view. Growth of group IV alloys, such as the Silicon-Germanium-Tin (Si-Ge-Sn) binaries and ternaries through CMOS compatible techniques is therefore of particular interest. This contribution presents UV-Laser based processes, such as Laser induced Chemical Vapor Deposition (LCVD) and Pulsed Laser Induced Epitaxy (PLIE) combined with conventional processing techniques, for material synthesis as well as results obtained growing different (Si)GeSn binary and ternary systems for material and lattice engineering. Synthesis of epitaxial (Si)GeSn alloys with above 10% Sn in large areas and of SiGeSn/GeSn micropatterns, through scanning and mask projection assisted PLIE, respectively, will be discussed. Emphasis will be placed on the influence of processing parameters on compositional and structural properties of the epitaxial alloys.
(Invited) Challenges and Developments in GeSn Process Technology for Si Nanoelectronics
Authors: Zaima Shigeaki , Nakatsuka Osamu , Taoka Noriyuki , Kato Kimihiko , Takeuchi Wakana , Sakashita Mitsuo
Published: September 2014

We have recently investigated and developed process technologies for Ge1-xSnx electronic applications. In this paper, we report our recent achievements in our research related to Ge1-xSnx; (1) electronic properties of defects related to Sn implantation in Ge, (2) oxidation of Ge1-xSnx epitaxial layers and electric property of metal/oxide/Ge1-xSnx gate-stack structure, (3) formation of Ni germanostanane layers on Ge1-xSnx epitaxial layer for metal/semiconductor contacts.
Electrical and Microstructural Characterization of Cu-Germanide Contacts Formed on p-Type Ge Substrate
Authors: Lim Yi-Rang , Lee Ye-Ji , Kang Min-Sung , Leem Chang-Hyun , Jyothi I. , Shim Kyu-Hwan , Choi Chel-Jong
Published: September 2014

We have investigated the electrical and microstructural properties of Cu-germanides formed on p-type Ge substrate as a function of rapid thermal annealing (RTA) temperature. As increasing RTA temperatures, Cu films reacted with Ge and formed Cu-germanides. The Cu3Ge phase appears to be the dominant phase along with Cu5Ge2 phase at annealing temperatures of 500 and 600 °C. The sheet resistance and specific contact resistivity were investigated as a function of germanide formation temperature. A minimum specific contact resistivity value of 6.19´10-6 Wcm2 is obtained after annealing at 400 °C associated with the formation of low stoichiometric Cu3Ge phase. The sheet resistance and specific contact resistivity increased after rapid thermal annealing at temperatures >500 °C, indicated the degradation of the contact properties and could be associated with the formation of copper rich Cu5Ge2 phase and the loss of structural integrity with increasing annealing temperature.
Fabrications of Size- Controlled SiGe Nanowires Using I-Line Lithography and Focused Ion Beam Technique
Authors: Noroozi Mohammad , Ergül Adem , Abedin Ahmad , Toprak Muhammet , Radamson Henry H
Published: September 2014

In this study, a novel method using Focus Ion Beam (FIB) technique was applied to scale down Si1-xGex wires (x=0.27-0.57) to 20 nm width. Originally, the wires were processed by using I-line lithography and dry etching of SiGe on oxide (SGOI) substrates. The SGOI wafers were processed through condensation method where a SiGe/Si layer was grown in the beginning on SOI wafers and oxidized at 850-1050 °C. The shape of the nanowires (NWs) during the successive FIB cutting was examined by scanning electron microscopy (SEM) and the carrier transport through the NWs was checked by resistivity measurements. The contact resistance was reduced by Ni-silicide prior to metallization. The fabricated NWs were also suspended by tilting FIB. The results present the limitations and challenges of FIB technique to create NWs for advanced sensors and transistors.
(Invited) Combining SiGe BiCMOS and InP Processing in an on-top of Chip Integration Approach
Authors: Lisker Marco , Trusch Andreas , Krüger Andreas , Fraschke Mirko , Kulse Philipp , Marschmeyer Steffen , Schmidt Jens , Meliani Chafik , Tillack Bernd , Weimann Nils , Kraemer Tomas , Ostermay Ina , Krüger Olaf , Jensen Thomas , Al-Sawaf Thualfiqar , Krozer Viktor , Heinrich Wolfgang
Published: September 2014

Applications such as radar imaging and wideband communications are driving the research on millimeter-wave circuits. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power. III-V technologies (like InP) can realize devices showing a high product of peak transit frequency multiplied with the open base breakdown voltage. Therefore, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs. Our approach combines an InP-DHBT transferred-substrate process with a Si-BiCMOS process. The key method is an aligned face-to-face wafer bonding with a subsequent removal of the InP substrate. Different integrated signal sources with an output frequency up to 246 GHz were designed and produced using different combinations of BiCMOS and InP circuit building blocks to demonstrate the capabilities of the hetero-integration routine. In this paper the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the influences on the BiCMOS devices were rather small.
(Invited) “Small Size” Effects in Si-Based Epitaxies for Advanced CMOS Technologies
Authors: Dutartre Didier , Seiss Birgit , Barge David , Loubet Nicolas
Published: September 2014

Most of the Small Size Effects that take place in epitaxies used in advanced CMOS are reviewed. The most common one is the faceting that is a consequence of different deposition kinetics of the dense crystal planes. On the other hand, when considering small areas, the deposition rate is not a constant and the effective thickness depends on the pattern size and orientation. Thus, the concepts of “time-nonlinear kinetics” or “anisotropic loading effect” have been proposed. These epitaxies are also very sensitive to temperature. Thermal rounding takes place at temperatures as low as 600-625°C. Moreover, with higher thermal budgets, surface energy is capable, as a function of boundary conditions, to create instabilities such as Plateau-Rayleight ones or on the contrary to stabilize the Stranski-Krastanov ones. Finally, the importance of these mechanisms is illustrated in two CMOS applications: thermal rounding and anisotropic loading in SiGe channels and faceting in elevated sources/drains.
Etch Pit Formation on Germanium Alloys by in situ Gaseous Hydrogen Chloride Etching
Authors: Huang Yi-Chiau , Wang Charles , Kim Yihwan
Published: September 2014

Etch pits form on epitaxial germanium alloy surfaces after in situ gaseous hydrogen chloride etching. The etch pits on the (001) surfaces of germanium, germanium-rich silicon germanium, and germanium tin are shown to be correlated with the threading dislocations in these epitaxial films. The etch pits therefore offer a direct way to characterize the distribution and density of threading dislocations in germanium alloys. Etch pits on strained and relaxed silicon germanium and germanium tin films are compared.
Characterization of Chemical Bonding Features and Interfacial Reactions in Ge-MIS Structure with HfO2/TaGexOy Dielectric Stack
Authors: Ohta Akio , Murakami Hideki , Hashimoto Kuniaki , Makihara Katsunori , Miyazaki Seiichi
Published: September 2014

As means to control interface reactions between HfO2 and Ge(100), chemical vapor deposition (CVD) of ultrathin Ta-rich oxide using tris(tert-butoxy)(tert-butylimido)tantalum (Ta-TTT) on chemically-cleaned Ge(100) has been conducted prior to atomic-layer controlled CVD of HfO2 using tetrakis (ethylmethylamino) hafnium (TEMA-Hf) and O3. An impact of post metallization annealing (PMA) in N2 ambience on chemical structure and electrical properties for TiN-gate Ge-MIS structure has been investigated. Hard x-ray photo-emission spectroscopy (HAXPES) measurements under synchrotron radiation with the excitation energy of 7939 eV show that good thermal stability of MIS structure against PMA at temperature of 400 °C. Diffusion of Ge atoms into stack dielectrics and TiN was observed after PMA at temperatures over 500 °C. As for the electrical properties of MIS capacitors, PMA at 300 °C was found to be effective to reduce the hysteresis due to charge trap and gate leakage current through the dielectrics. It was also found that the relative dielectric constant of interfacial TaGexOy thin layer was ~ 9, and calculated equivalent SiO2 thickness (CET) of 1.0 nm can be achieved for the sample with 3 nm thick HfO2/1nm-thick TaGexOy stack dielectrics.
Interfacial Layer Engineering Using Thulium Silicate/Germanate for High-k/Metal Gate MOSFETs
Authors: Hellström Per-Erik , Litta Eugenio Dentoni , Östling Mikael
Published: September 2014

Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO2/TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ~20% higher electron and hole mobility than literature data on optimized SiOx/HfO2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.
(Invited) Gate-All-Around Ge FETs
Authors: Liu C. W. , Chen Yen-Ting , Hsu Shu-Han
Published: September 2014

High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced Ion of 110 mA/mm at 1V with respect to the devices with near (110) sidewalls and subthreshold characteristics of 94 mV/dec. The JL Ge GAA pFETs with fin width (Wfin) down to 27 nm and channel concentration (Nch) of 5×1018 cm-3 has Ion/Ioff = 1.5×106, SS = 95 mV/dec, and Ion = 194 mA/mm at VGS - VT = -2V and VDS = -1 V.
Plasma Post-Oxidation for High Mobility Strained-Ge pFETs with Aggressively Scaled High-κ Dielectrics
Authors: Chern Winston , Hashemi Pouya , Kobayashi Masaharu , Park Dae-Gyu , Hoyt Judy L.
Published: September 2014

In this work, transport is explored in strained-Ge (s-Ge) p-MOSFETs with a hybrid GeOx/Al2O3/HfO2 gate stack directly on the channel with and without plasma post-oxidation (PPO). A gate-first process with ion implanted source/drains and a 625°C activation process was utilized. The gate stack is improved using PPO allowing for a demonstration of both extremely scaled CET (CET ~ 1.1 nm) and high mobility at high inversion charge. This demonstration suggests that this gate stack is a candidate for scaled s-Ge p-MOSFETs.
(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
Authors: Lu Darsen , Morin Pierre , Sahu Bhagawan , Hook Terence B , Hashemi Pouya , Scholze Andreas , Kim Bomsoo , Kerber Pranita , Khakifirooz Ali , Oldiges Philip , Rim Ken , Doris Bruce
Published: September 2014

We introduce SiGe FinFET device physics, process integration, and modeling considerations. Germanium is know to have a higher hole mobility than silicon. Enhancement of hole velocity due to lattice mismatch strain in SiGe epitaxy layers is significant. In addition, uniaxial stress is beneficial for device performance. Transformation of biaxial to uniaxial stress naturally occurs when SiGe film is etched into stripes. Furthermore, control of MOSFET threshold voltage by adjusting the SiGe-channel germanium content is possible. On the other hand, SiGe processing challenges include the elimination of interface trap states at the gate dielectric interface, fast diffusion of n-type dopants, and defects in stress relaxed buffer and critical thickness limitations. Band-to-band tunneling sets a lower bound to device static leakage current.
(Invited) Mobility Enhancement of Uniaxially Strained Germanium Nanowire MOSFETs
Authors: Ikeda Keiji , Kamimuta Yuuichi , Moriyama Yoshihiko , Ono Mizuki , Usuda Koji , Oda Minoru , Irisawa Toshifumi , Kosemura Daisuke , Ogura Atsushi , Tezuka Tsutomu
Published: September 2014

Strained Ge nanowire MOSFETs with a compressive strain as high as -3.9 % were fabricated by the 2-step Ge-condensation technique without intentional doping for the S/D. Record high hole mobility (μ
eff = 1992 cm2/Vs @ N
s = 1.7x1012 cm-2) was achieved among Ge nanowire pMOSFET ever reported. Inserting a plasma-oxide (GeOx) inter-layer between the high-k dielectric and the strained Ge nanowire channel greatly improved not only the mobility but the cut-off characteristics. A low off-current (2.7 nA/μm at V
d = -0.5 V) was achieved by the device with the gate length of 45 nm, thanks to the reduced interface state density.
Highly-Doped, Highly-Strained Germanium and Schottky Electroluminescent Diodes
Authors: El Kurdi Moustafa , Prost Mathias , Ghrib Abdelhamid , Checoury Xavier , Sauvage Sébastien , Zerounian Nicolas , Aniel Frederic , Beaudoin Gregoire , Sagnes Isabelle , Le Thanh Vinh , Luong T.P.K. , Chaigneau Marc , Ossikovski Razvigor , Baudot Charles , Boeuf Frederic , Boucaud Philippe
Published: September 2014

We demonstrate that room temperature electroluminescence can be obtained from n-doped germanium layers by using a Schottky contact. The electrical and optical properties of the Schottky device are improved by inserting a thin Al2O3 interfacial barrier. We also show that high active doping of Ge grown on Si can be obtained by molecular beam epitaxy by using a co-doping method with Sb and P. We finally discuss the transfer of tensile strain on microdisk resonators using silicon nitride stressor layers.
Photoluminescence Study of Si Quantum Dots with Ge Core
Authors: Makihara Katsunori , Kondo Keigo , Ikeda Mitsuhisa , Ohta Akio , Miyazaki Seiichi
Published: September 2014

Si quantum dots (Si-QDs) with doped Ge core were self-assembled on thermally grown SiO2 from alternate thermal decomposition of pure SiH4 and GeH4 diluted with He. When the sample was excited by a 979 nm line of semiconductor laser, photoluminescence (PL) spectra peaked at ~0.70 eV were observed, even at room temperature. The observed PL band suggested that radiative recombination of photo-generated carriers through quantized states of the Ge core is the dominant pathway for the emission from the dots, reflecting the type II energy band discontinuity between the Si clad and Ge core. We also found that, for P-delta doping to the Ge core, an ionized P donor is responsible for the efficient PL from the P-doped Ge core Si-QDs.
(Invited) Light Emission from Highly-Strained Germanium for On-Chip Optical Interconnects
Authors: Nam D. , Sukhdeo D. S. , Dutt B. R. , Saraswat K. C.
Published: September 2014

In this paper, we focus on developing an efficient silicon compatible light emitter based on highly-strained germanium technology. We present various experimental results showing enhanced light emission from strained germanium. First, we describe a thin film membrane technique in which a large residual stress in a tungsten layer is used to induce a biaxial tensile strain in germanium membranes. Second, we introduce an approach to induce sufficiently large uniaxial strain to create a direct band gap in germanium (Ge) nanowires using geometrical amplification of a small pre-existing strain. Lastly, we present a novel way to mimic double-heterostructure behavior within a single material, further enhancing light emission from Ge by capturing photo-generated carriers in a strain-induced potential well. Throughout this paper we discuss the implications of these experimental achievements toward creating an efficient Ge laser for silicon-compatible optical interconnects.
Franz-Keldysh Effect in GeSn Detectors
Authors: Bechler Stefan , Oehme Michael , Latzel Oliver , Schmid Marc , Kostecki Konrad , Koerner Roman , Gollhofer Martin , Kasper Erich , Schulze Joerg
Published: September 2014

Four different GeSn photodetectors with Sn content up to 5.6 % are investigated. From current-voltage measurements with and without illumination, the spectral optical responsivity is determined. With the responsivity and the measured reflection, the absorption and the direct band gap energies are calculated. All four samples show a voltage dependent change of the absorption due to the Franz-Keldysh effect. At a wavelength of 1950 nm, a maximum absorption ratio of 2 is observed for 4.2 % Sn for a voltage swing of 2.5 V.
Pre-Amorphization and Low-Temperature Implantation for Efficient Activation of Implanted As in Ge(100)
Authors: Murakami Hideki , Hamada Shinya , Ono Takahiro , Hashimoto Kuniaki , Ohta Akio , Hanafusa Hiroaki , Higashi Seiichiro , Miyazaki Seiichi
Published: September 2014

To improve the activation of As implanted into Ge substrate, we have studied the influence of the crystallinty of implanted region with the ion implantation on As activation after post-annealing systematically. The impact of substrate temperature on As+ implantation to Ge (100) in the range from -100°C to 400 °C and the degree of amorphization with the ion implantation has been characterized. We have confirmed that the amorphization with As+ implantation is promoted efficiently at lower temperature due to the quenching of self-heating during the ion implantation. Such an enhanced amorphization of Ge by low temperature implantation is effective to suppress As cluster formation during the re-crystallization with post-annealing and results in the improvement of the As activation in Ge(100). We have also observed the enhancement of amorphization and As activation with pre-amorphous implantation.
The Use of Dopants for Defect Monitoring for Silicon-Germanium Ultra-High Vaccuum Chemical Vapor Deposition
Authors: Hazbun Ramsey , Hart John , Nakos James , Siegel Dean , Funch Christopher , Kaushal Vikas , Hazel David Scott , Kolodzey James
Published: September 2014

Silicon-germanium epitaxy via ultra high vacuum chemical vapor deposition has the advantage of allowing low process temperatures. Deposition processes are sensitive to substrate surface preparation and the time delay between oxide removal and epitaxial growth. A new monitoring process utilizing doped substrates and defect decoration etching is demonstrated to have controllable and unique sensitivity to interfacial contaminants. Doped substrates were prepared and subjected to various loading conditions prior to the growth of typical Si/SiGe bilayers. Two different defect etches were performed, and the defect densities counted and confirmed as originating from the substrate-epitaxy interface. The defect densities were correlated to the concentration of interfacial oxygen. The result of this study is a suggestion for a defect monitoring technique that uses already commonplace equipment and chemicals, which has a rapid turnaround, with controllable sensitivity to substrate surface contaminants.
(Invited) Thin Epitaxial Film of Ge and III-V Directly Bonded onto Si Substrate
Authors: Maeda Tatsuro , Mieda Eiko , Ishii Hiroyuki , Itatani Taro , Hattori H , Yasuda Tetsuji , Maeda Atsuhiko , Kurashima Yuichi , Takagi Hideki , Aoki T , Yamamoto T , Ichikawa Osamu , Osada T , Takada T , Hata Masahiko , Yugami J , Ogawa A , Kikuchi T , Kunii Y
Published: September 2014

We have realized patterned Ge-on-Insulator wafers by large-scale layer transfer technology. In conjunction with low-temperature bonding and patterned Epitaxial Lift-Off (ELO) technique, high quality Ge or III-V layer transfer was achieved in full-wafer scale. Furthermore, to expand the transferred area, multiple chip-to-wafer bonding and thin epitaxial film transfer has been demonstrated on 300 mm Si wafer. Low temperature layer transfer technology using ELO technique provide the flexible opportunity to elaborate Ge and III-V based substrates for post silicon CMOS as well as for monolithic heterogeneous integration in a cost effective manufacturing.
Influence of Trench Width on III-V Nucleation during InP Selective Area Growth on Patterned Si(001) Substrate
Authors: Jiang Sijia , Merckling Clement , Moussa Alain , Guo Weiming , Waldron Niamh , Caymax Matty , Vandervorst Wilfried , Seefeldt Marc , Heyns Marc
Published: September 2014

The selective area growth (SAG) of InP by metal-organic vapor phase epitaxy (MOVPE) inside shallow trench isolation (STI) trenches of various widths ranging from nominally 20nm to 500nm on Si(001) substrates is investigated by SEM and AFM in this report. With different growth time, the similar morphology evolution stages in both wide and narrow trenches are identified. Nevertheless, by comparing 40nm wide trenches to 150nm ones, the coalescence stage of islands is delayed in narrow trenches, which leads to a discontinuous topology with sufficiently long time growth. We proposed a model to study the possible impact of trench width on the average inter-island distance, which can be a main mechanism for the evolution delay in narrow trenches.
(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of III-V on Si: What About Defect Density?
Authors: Merckling Clement , Waldron Niamh , Jiang Sijia , Guo Weiming , Barla Kathy , Heyns Marc , Collaert Nadine , Thean Aaron , Vandervorst Wilfried
Published: September 2014

This study relates to the heteroepitaxy of InP buffer on patterned Si substrates using the selective area growth in trenches approach. We demonstrated in a first part a high control of the two-step InP buffer growth in STI trench width under 50 nm. In a second part, X-ray diffraction reciprocal space maps, rocking curves and pole figures were used to analyze the crystallinity and defect density of the InP layer.
(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node
Authors: Hashemi Pouya , Balakrishnan Karthik , Majumdar Amlan , Engelmann Sebastian , Hopstaken Marinus , Kim Wanki , Ott John A. , Leobandung Effendi , Park Dae-Gyu
Published: September 2014

Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly challenged at extremely tight gate pitch, required for 10nm node and beyond. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. SiGe has been utilized in CMOS industry, such as IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement. Prior work on planar ET-SOI-like FETs clearly demonstrates that the built-in compression in strained-Si1-xGex (s-SiGe) layers plays a significant role in the performance of the short channel devices. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties, their reduced bandgap by increasing Ge content brings concern for some CMOS applications, such as increased drain leakage and high off-state current. In this work, we evaluate s-SiGe pFETs fabricated on SOI substrates with moderate Ge fraction, in a FinFET architecture and with aggressively scaled dimensions suitable for 10nm node. We highlight the process challenges as well as short-channel performance, leakage and scalability of s-SiGe FinFETs.
Atomistic Modeling of Strained SiGe Nanofins
Authors: Dunham Scott T. , Lai Haoyu , Chen Renyu
Published: September 2014

We utilize a hierarchical approach to atomistic modeling with density functional theory (DFT) calculations being used together with experimental observations to determine parameters for molecular dynamics (MD) potentials and kinetic lattice Monte Carlo (KLMC) simulations. MD and KLMC are used to model epitaxial growth and impurity redistribution in strained group IV alloy nanostructures.
SOI and Bulk FinFET Alternatives from the Perspective of Strain Engineering
Authors: Peidous Igor V , Lottes Charles , Jost Christopher
Published: September 2014

The mechanical stresses in the channels of strain-engineered SOI and bulk FinFETs have been studied. The dependency of the charge carrier mobility on the channel geometries and crystal orientations was analyzed using a computer modeling based on a specially developed 2D FEM algorithm that enabled fast turnaround in conducting numerous iterative simulation experiments. It is shown that embedded SiGe stressors (eSiGe) formed in Source/Drain regions of FinFETs are the key element for enhancing drive currents of PFETs to the level comparable with NFETs. eSiGe stress-induced change of the hole mobility in SOI FinFETs is about half of what can be achieved in bulk FinFETs. To compensate this deficiency, SOI FinFET designers may consider alternative crystal orientations for Fins, strained SOI, and high quality Ge or III-V semiconductors on insulator.
Spin Transport in Ge Nanowires for Diluted Magnetic Semiconductor-Based Nonvolatile Transpinor
Authors: Tang Jianshi , Nie Tianxiao , Wang Kang L.
Published: September 2014

Spintronic devices, in particular spin field-effect transistors (spinFETs), have been researched for decades as a promising candidate to replace Si transistors with potentially low power dissipation and low variability. In this paper, we propose a nonvolatile spin-base transistor (transpinor) based on diluted magnetic semiconductor (DMS) with electric field-controlled paramagnetism-to-ferromagnetism phase transition. To realize the transpinor, we demonstrate the electrical spin injection into Ge nanowires using both ferromagnetic Mn5Ge3 Schottky contacts and Fe/MgO tunnel junctions. We observe much longer spin lifetimes and diffusion lengths in Ge nanowires compared with bulk Ge. Furthermore, we successfully grow the single-crystalline MnxGe1-x DMS nanowires using pattern-assisted molecular beam epitaxy (MBE). The MnxGe1-x nanowires exhibit a Curie temperature above 400 K, and the ferromagnetism can be further modulated by an external gate voltage. The demonstrated electric field-controlled ferromagnetism, along with the successful spin injection into Ge nanowires, paves the road to build the proposed transpinor.
(Invited) Germanium at the Atomic Scale
Authors: Goldberger Joshua E.
Published: September 2014

Similar to how carbon networks can be sculpted into low-dimensional allotropes such as fullerenes, nanotubes, and graphene with fundamentally different properties, it is possible to create similar “allotropes” of Ge with unique optoelectronic properties as well. Here, we describe our recent success in the creation of hydrogen and organic-terminated germanium graphane analogues, or germananes, from the topochemical deintercalation of CaGe2. We show that the optical, electronic, and thermal properties of these materials can be controlled by substituting the surface ligand. These materials represent a new class of covalently terminated graphane analogues and have great potential for a wide range of electronic, optoelectronic and sensing applications, especially since theory predicts these materials to have direct and tunable band gaps around 1.6 eV and electron mobilities that are around five times higher than that of bulk Ge.
Lateral Gemanium Growth for Local GeOI Fabrication
Authors: Yamamoto Yuji , Schubert Markus Andreas , Reich Christian , Tillack Bernd
Published: September 2014

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.
Morphological Instability of High Ge Percent SiGe Films Grown by Ultra-High Vacuum Chemical Vapor Deposition
Authors: Hart John , Hazbun Ramsey , Nakos James , Siegel Dean , Funch Chris , Kolodzey James , Harame D. L.
Published: September 2014

The Ge content in SiGe bipolar transistors (HBTs) has been steadily increasing for the past few decades in order to meet higher frequency targets. Problems exist with higher Ge content films due to the strain from the pseudomorphic growth on Si substrates. In addition to relaxation by misfit dislocation at high Ge contents, SiGe films have been observed to exhibit morphological instability or surfaces waves. This phenomenon, known for some time, produces surface corrugations several nm in height that can have detrimental effects on SiGe devices. While historic solutions to the problem involved lowering the growth temperature, hot-wall ultra-high vacuum chemical vapor deposition presents a unique challenge due to the inability to quickly change temperatures during growth. Therefore the process parameters must be optimized for a constant growth temperature for all layers in the device structure. In this report, the process parameters including film growth rate and temperature will be described in their effect on reducing and eliminating the surface waves.
Use of a Purged FOUP to Improve H-Terminated Silicon Surface Stability Prior to Epitaxial Growth
Authors: Wostyn Kurt , Rondas Dirk , Kenis Karine , Loo Roger , Hikavyy Andriy Yakovitch , Douhard Bastien , Mertens Paul W. , Holsteyns Frank , De Gendt Stefan , D'Urzo Lucia , Van Autryve Luc
Published: September 2014

H-terminated Si surfaces serve as the starting surface for hetero-epitaxial growth. The presence of oxygen on the wafer surface can significantly reduce the epitaxial layer quality. The oxygen present on the surface is, among others, determined by the re-oxidation of the surface during the queuing between cleaning and epitaxy. In this paper we report on the use of a N2-purged FOUP to reduce the re-oxidation of Si surfaces.
Growth Studies of Doped SiGeSn/Strained Ge(Sn) Heterostructures
Authors: Wirths Stephan , Ikonic Zoran , von den Driesch Nils , Mussler Gregor , Breuer Uwe , Tiedemann Andreas , Bernardy Patric , Holländer Bernd , Stoica Toma , Hartmann Jean-Michel , Grützmacher Detlev , Mantl Siegfried , Buca Dan
Published: September 2014

Recent breakthrough in the epitaxial growth of CMOS compatible GeSn and SiGeSn alloys has enabled the development of direct to indirect gap semiconductors combinations for group IV quantum well laser structures. To advance in this emerging application field, we have investigated the epitaxial growth of highly strained Ge which is expected to exhibit an indirect to direct bandgap transition. In addition, the overgrowth of device grade SiGeSn ternaries is proven by exhaustive structural and optical analysis. Moreover, doping of SiGeSn alloys, required for carrier injection layers of electrical pumped lasers, is presented and the realization of strained Ge/SiGeSn double quantum well laser heterostructures on relaxed GeSn buffers is highlighted.
Ge1-xSnx Epitaxial Growth on Ge Substrate by MOCVD
Authors: Suda Kohei , Ishihara Seiya , Sawamoto Naomi , Machida Hideaki , Ishikawa Masato , Sudoh Hiroshi , Ohshita Yoshio , Ogura Atsushi
Published: September 2014

Metal-organic chemical vapor deposition have many advantages such as low deposition temperature compared to conventional CVD using inorganic molecules. In this study, we succeeded in the Ge1-xSnx epitaxial growth on Ge substrate by MOCVD using tertiary-butyl-germane and tetra-ethyl-tin for the precursors for the first time. The Sn concentration in the deposited film was 2 at.% which exceeds solid solubility limit of 1 at.%. The carbon impurity incorporation was confirmed to be less than the XPS detection limit.
CVD Growth of GeSnSiC Alloys Using Disilane, Digermane, Tin Tetrachloride and Methylsilane
Authors: Noroozi Mohammad , Abedin Ahmad , Moeen Mahdi , Östling Mikael , Radamson Henry H
Published: September 2014

In this study, Ge1-x-y-zSnxSiyCz layers (0.01≤x≤ 0.06, 0≤y≤0.02 and 0≤z≤0.01) have been successfully grown at 280-330 ¢ªC on Ge and Si by using RPCVD technique. It was demonstrated that the quality of epitaxial layers is dependent on the growth parameters, layer thickness and the quality of Ge virtual layer. It was found that a proper strain balance in the matrix during the epitaxy where the Si is adjusted carefully with the Sn flux improves the incorporation of Sn in Ge matrix. A similar improvement of Sn incorporation has been observed for phosphorous, boron and carbon doping in GeSn layers as well. This is explained by the compensation of the compressive strain caused by Sn by the tensile strain induced by Si to obtain the minimum energy in Ge matrix. This behavior was not observed for relaxed GeSn layers and Sn incorporation could be controlled only by the growth parameters. The thermal stability of GeSn is an important integration issue for device fabrication. The thermal stability of P- and B-doped GeSn layers was studied by rapid thermal annealing (RTA) in range of 400-600 ¢ªC and compared with intrinsic layers. The GeSn layers were stable up to 550 ¢ªC while the P-doped layers showed strain relaxation readily at 450 ¢ªC. The epitaxial quality of epi-layers was evaluated in terms of oxygen and water vapor contamination. The level of oxygen during epitaxy was as low as 10 ppb and the contamination amount was found as low as 1017 cm-3.