bluuebunny/crossref_metadata_2025 huggingface dataset:
A Versatile Optical Head for 3D IC TSV Integration Process Control
Authors: Fresquet G.
Published: October 2015

3D Integration of miniaturized systems at wafer level generates new needs of metrology and defects inspection for the control of TSV geometries, temporary wafer bonding, wafer thinning, via interconnects technology and of wafer/die stacks. In this paper we demonstrate the capabilities of a versatile optical measurement system combining several microscopy and interferometry techniques in the visible and near infrared wavelength range.

I. INTRODUCTION AND BACKGROUND

ALL roadmaps predict a large spread of 3D heterogeneous integration technologies for the fabrication of miniaturized systems in the coming years1. Beside a large development of new fabrication processes, 3D integration generates new challenges in terms of metrology and defects inspection for wafer/die bonding, thinning and interconnection processes as well as for 3D architectures. Adaptation and/or combination of existing techniques and the development of new techniques become necessary in order to perform non destructive, fast and inspections or quantitative measurements on large area wafers with high lateral and vertical resolutions. In this work we describe results obtained with an optical system combining several microscopy and interferometry techniques.
Ultra High Density Capacitors merged with Through Silicon Vias to enhance performances.
Authors: Bunel Catherine
Published: October 2015

IPDIA presents itself as the 3D Silicon leader providing innovative platforms for customers who want to demonstrate technological concepts based on Through Silicon Vias.

The market segments Medical, Lighting, and Industrial addressed by the Ipdia Technology are adopting 2.5-D and 3-D technologies to increase the performance and density of their devices through the use of silicon interposers and through-silicon vias (TSVs).

The via last approach developed by IPDIA allows large possibility of integration combining TSV with active or passive devices such as High-density trench capacitors, MIM capacitors, Resistors, High-Q inductors or Zener diodes .

The purpose of this paper is to focus on through-silicon via (TSV) combined with IPD , providing an interposer which could have two surfaces with devices. Emphasis is placed on 3D trench capacitor technology with an update of the roadmap .Examples of applications using chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) are briefly presented. Some important results and recommendations are summarized: the process steps for passive devices interposer /TSV/redistribution layer (RDL)/microbumps /, the design rules .A comparison between TSV on active chips and passive interposer with TSV will be detailed.
3D Packaging- Synthetic Quartz Substrate and Interposer for High Frequency Applications
Authors: Stygar Vern , Mobley Tim , Takahashi Shintarou
Published: October 2015

Glass for use as an Interposers with through vias (TGV) are emerging as the next generation substrates for die level and wafer level packaging substrates. This need is being driven increasing number of interconnects, desire to have a KGD (known good die) at the wafer level package (WLP), high electrical/thermal conductivity vias, and hermeticity between the PWB and the die, while being cost competitive with a TSV passive interposer. These TGV characteristics translate to longer battery life, higher yield at the end user applications, and an optimized WLP solution that not require silicon processing foundries to fabricate a passive interposer.

The next generation of communication devices will operate at much higher frequencies to allow video on demand and video vis a vis communication. Coupled with multiple frequencies, to facilitate a phone to work with GSM, CDMA and other communication schemes require multiple filter and low noise amplifiers.

This paper will describe work done with Alkali free, copper filled (not plated) hermetic vias that are both low cost and provide engineering design flexibility for the more advance low cost personal handheld devices.
CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding
Authors: Sutanto Jemmy , Kang D. H. , Yoon J. H. , Oh K. S. , Oh Michael , Lanzone R. , Huemoeller R.
Published: October 2015

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC.

The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used.

“Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.
Adopt Advanced RDL Rule to Apply Flip Chip Technology for Next Generation Si Node: Feasibility Study
Authors: Wen Shengmin , Park KyungRok , Thompson Patrick , Lee JeongSeok , Park HyunJin
Published: October 2015

With Si node shrinking to 28nm technology, smaller pitch of die pads becomes available so that more IO pads can be layed out. Sometimes the die requires flip chip packaging because of either functionality and performance requirement or cost effectiveness. This paper proposed an advanced RDL solution for a tigher pitch die. A local 10/10um L/S PBO RDL rule is applied to route a die that has three rows staggered 40/80um pitch pads into an area type die, and thermal compression method is used to assembly the chip with flip chip process. Initial construction analysis shows that this is a viable solution.
Fabrication of 3D-IC Interposers
Authors: Keech John T. , Piech Garret , Pollard Scott
Published: October 2015

Interposer fabrication has gained a lot of attention in the area of three-dimensional integrated circuit (3D-IC) integration. Glass has many properties that make it well suited for interposer substrates, such as adjustable coefficient of thermal expansion, advantaged electrical properties and unique forming processes. Furthermore, glass based solutions can also provide significant cost advantages in substrate material, via formation, and subsequent processing.

In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer substrates. Leveraging the ability to create through-glass-via (TGV) substrates in as-formed 100 μm thick precision glass, with a pristine surface, can avoid the need for back grinding and polishing operations. This has the potential to eliminate several manufacturing steps for polishing and thinning, while providing associated cost savings.

Significant progress has been made in demonstration of TGV technology. Fully populated wafers with 100,000s of through or blind holes (≥ 25 μm diameter) are fabricated today, and 10–20 μm diameters are in development. We will report on important quality parameters measured on TGV wafers and positive implications with respect to product quality and strength. The ability to leverage industry metallization techniques and performance characteristics will also be reported. Finally, we will discuss opportunities to leverage cost-effective glass interposer solutions.
Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics
Authors: Hernandez George A. , Martinez Daniel , Patenaude Stephen , Ellis Charles , Palmer Michael , Hamilton Michael
Published: October 2015

This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure.

Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms.

In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated.

In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.
The Role of Extreme Agitation in Accelerating the Removal Rate of Advanced Packaging Photoresists
Authors: Sobhian Mani
Published: October 2015

Negative Dry Film and Negative Spin-On photoresists are widely adopted as the prime choice in wafer-scale packaging processes such as bumping, TSV, and copper pillars.

High transparency of negative resist produces vertical profiles with no footing at low exposure energy, resulting in a robust, high throughput lithography process (Doki, 2005).

In plating applications, the 3-D cross-linking of negative resist provides good adhesion to wide range of substrates, enabling high-current ECD processes with high throughput.

The main challenge of negative photoresist has always been its removal difficulty. Aggressive remover chemistries consisting of DMSO, NMP, and TMAH have been used to cleave, swell, and dissolve the material (Moore, 2002).

This paper demonstrates the capabilities of a novel immersion-based strip technology that maintains a constant boundary layer at the wafer surface by providing high-speed agitation to each individual wafer. Results show an acceleration of the removal process, while reduced exposure to remover chemistries reduces risks of bump corrosion.

Removal rates of negative dry film and negative spin-on resist materials have been studied across variety of commercially available strip chemistries.
Robust Reliability Performance of Large size eWLB (Fan-out WLP)
Authors: Yoon Seung Wook
Published: October 2015

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield.

This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.
Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology
Authors: Zwenger Curtis , Khim JinYoung , Khim YoonJoo , Cha SeWoong , Lee SeungJae , Kim JinHan
Published: October 2015

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm.

Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.
Techniques and Tools for Collaborative Thermal and Mechanical Modeling of 3D ICs
Authors: Karimanal Kamal
Published: October 2015

The Industry has been using Computational Fluid Dynamics (CFD) and Finite Element Analysis (FEA) for thermal and mechanical modeling of IC packages for many years. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for newer methodologies and information exchange protocols.

One particular necessity while building low power System on Chip (SOC) is the methodology needed to ensure package specific thermal feasibility of IC stacking options at physical layout stage of the 3D IC design. A methodology built on the technique to be presented will avert the unintended consequences of stacked IC hot spot alignment during system operation. The presentation will include a validation of the technique by comparison with traditional thermal modeling technique.

The ability to fabricate such stacks using an evolving supply chain of foundry-OSAT combination is equally crucial to the viability and reliability of the packaged SOC. A process focused modeling tool for understanding the warpage, stress, and Chip Package Interaction (CPI) implications of assembly strategy choices is valuable for ensuring time to market at minimal technology development costs. The presentation will include a modeling case study with quantitative data of warpage and stress implications of process, material and stacking choices.

This presentation will introduce the tools and techniques for collaborative chip stack thermal and assembly process modeling with in-depth discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance.
3D Ics with Embedded Microfluidic Cooling and High Aspect Ratio TSV Integration
Authors: Thadesar Paragkumar , Bakir Muhannad S.
Published: October 2015

Abstract Not Available. Outline: Introduction; Liquid Cooling in 3D ICs; Integration of Electrical TSVs in Microfluidics; and Conclusion
Mobile Packaging and Interconnect Trends
Authors: Prior Brandon
Published: October 2015

This paper will focus on emerging and fast growth package solutions to meet mobile products' density and cost requirements. A short review of where package miniaturization and modularization has taken us so far, and where it will lead in the next 5 years. Teardowns of high density systems and packages will be used to illustrate key points.

Low temperature Ag sintering technology provides a lead-free die attachment compatible with high temperature (300°C) applications. Previous work with Ag sintering has required some pressure during the sintering process or been limited to small area die. In this paper, a pressureless sintering of micro-scale silver paste procedure is presented for large (8mm x 8mm) area die.

Experimental combinations included: Ag metallized Si die, Au metallized Si die, Ag thick film substrate metallization, Au thick film substrate metallization, PdAg thick film metallization and sintering temperature.

For Au metallization (die and/or substrate), the initial shear strength results were good with 8mm x 8mm die sintered at lower temperatures (200°C). The shear strength was out range of our shear test machine (100 kg), corresponding to >15.3 MPa. However, after aging for 24 hours at 300°C, the shear strength dropped significantly to 40.38 Kg (6.183 MPa). An SEM was used to characterize cross sections of as-built and aged sample. The decrease in die shear strength with high temperature sintering (250°C and 300°C) or high temperature aging is attributed to surface diffusion of Ag along the Au surface resulting in a dense Ag layer adjacent to the Au surface and a depletion layer within the die attach on the opposite side of the the dense Ag layer. Shear failures occurred through the depleted region.

For Ag metallization, no decrease in shear strength was observed with 300°C aging. Shear strength of 8x8cm2 dies was out range of our shear test machine (>100 kg, >15.3 MPa) as-built. The shear strength remained out of range (>15.3MPa) after more than 2000 hours of 300C aging.
Electrical Performance Comparison between fcBGA and eWLB Packages
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Hlaing MaPhooPwint , Kim Gwang. , Park Susan , Ahn Billy
Published: October 2015

Wafer-level packages, such as embedded-Wafer-Level-Ball-Grid-Array (eWLB) packages, can provide smaller form-factors and thinner profiles, as finer design rules on W/S, and thinner layers (both metal layers and passivation layers) can be applied in such packages.

However, a routine conversion from fcBGA to eWLB does not guarantee the electrical performance will be the same. Designer's electrical skills still play important roles to reduce design cycle-time for meeting critical electrical performance. We compare the performance from typical fcBGA and eWLB packages in the following areas: insertion-loss for signal nets, power-ground impedance for P/G nets, and cross-talk for both signal nets and P/G nets. Simulation data for both fcBGA and eWLB, along with some experimental data, is provides in the paper.

As metal-layer thickness (4um-12um) in eWLB is typically smaller, and finer design rules are used, the cross-section of a signal trace is smaller, which translates a higher metal-loss in unit- length. In addition, as the passivation layers in eWLB have slightly worse loss-tangent properties, it's substrate-loss is also little higher. The overall aspects above result in higher transmission-line (TML) loss in eWLB in unit-length. But as shorter trace-routing is possible in eWLB, given finer design rules, the overall transmission-line loss could be equivalent to that of a fcBGA transmission-line.

The finer design rules on vias in eWLB facilitate to implement Power/Ground (P/G) planes in a more continuous way, and contribute to less P/G impedance. In addition, as the layer-to-layer separation is smaller, decoupling capacitance inheritably made between the P/G planes is larger, which eventually helps to provide a better or smaller P/G loop-impedance.

Because of less separation distance between metal layers in eWLB, the signal traces see much closer GND planes (e.g., 5um in eWLB versus 50um in fcBGA) in their proximities. The closer GND planes make the electrical fields more locally contained. As a result, in a typical eWLB design (e.g., 12um/12um for L/S), the cross-talk between DDR data buses is typically smaller than that from a fcBGA design (e.g., 30um/30um for L/S).
Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements
Authors: Hunt John , Hsieh Adren , Tsai Eddie , Chen Chienfan , Wang Tsaiying
Published: October 2015

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity.

With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die.

For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured.

We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.
A Zinc Oxide nanowire-based Sensing Platform for Carbon Dioxide Detection
Authors: Kim Bruce , Gupta Anurag
Published: October 2015

ZnO nanowires have been a focus of intense research in recent decade. The superior physical and chemical properties demonstrated by these nanostructures stem from their unique morphology and surface structures. High surface-to-volume ratio concomitant with their semiconducting yet inert nature makes them a high potential material for developing varied spectrum of devices. Specifically, their favorable surface chemistry makes them an ideal candidate for developing highly sensitive chemical gas sensor. In this work, ZnO nanowires have been utilized in array morphology to develop a sensing device and platform with back-end electronics for remotely monitoring and logging real-time carbon dioxide concentration. Vertically oriented, hierarchical nanowire arrays were grown on insulating sapphire substrate. The extremities of the nanowire grown substrates were contacted with colloidal silver to form electrodes. The I-V characteristics of the sensing device were determined through a semiconductor parameter analyzer and the data obtained was used to calibrate the electronics needed for the sensing platform. The overall topology of the sensing platform comprises a nanowire-based sensing device that interfaces with an analog sensing board that processes data in real-time and transmits it over a wireless protocol. The receiver end is equipped with electronics to decode the digital packets and a GUI to display obtained data in real-time. The sensor chip is operated at 150C to provide the necessary activation energy to the oxygen surface sites on ZnO nanowires to take part in sensing operation for attracting and detecting carbon dioxide molecules.
Wet Chemical Processing with Megasonics Assist for the Removal of Bumping Process Photomasks
Authors: Seong Sohn Hong , Tracy John
Published: October 2015

A new generation of negative tone resists by TOK, JSR, and Dow Chemical is gaining momentum in advanced packaging applications. Resist thickness requirements are actually increasing to the 50-100 um range as Cu pillars are adopted to accommodate the tighter pitches required in advanced packaging. In order to form pillars the resist must be thicker to contain the entire bump structure.

Thick, negative tone resists are more transparent to exposure light wavelengths than positive tone resists and can be exposed by the lithography process much faster (~1 x 104 cross-linking chemical events are driven by 1 photochemical event vs. 100 – 1000 for positive tone resist).1 Therefore exposure times can be shorter, post-exposure bake steps can be shorter, and delay before or after exposure is not necessary, saving photolithography time and CoO. And, due to more complete cross-linking throughout the resist, the resist mask profiles are truer (from Flack et.al, “A Comparison of New Thick Photoresists for Solder Bumping”, SPIE 2005).1

The major drawback to negative tone resists is that the solvent strip times of the highly cross-linked resist masks are much longer than for positive tone. Flack et.al. noted resist strip times of 5 minutes for two positive resists used in their experiments vs. 50 minutes for the AZ-100nXT negative tone resist, using AZ400T at 80°C (most likely in an immersion tool). Long strip times or special stripping requirements are noted on the data sheets of the other majority suppliers of negative resists as well.

Akrion engineers have developed a novel, single-wafer, negative PR strip processes using organic solvents plus Goldfinger megasonics, to provide 30 - 70% reductions in process times and the associated chemical consumption when compared to processes that do not utilize a megasonics assist. The multi-step process can be accomplished in a single process chamber, with each step optimized for time and temperature based on the resist thickness and solvent stripping chemistry used.

In the Akrion process, a period of solvent exposure at low wafer spin speed is used initially to begin swelling and dissolving the thick photoresist layer. This is followed by a second solvent exposure step using aggressive frontside megasonic energy to promote polymer chain scission throughout the bulk of the photoresist layer. Following this step A DI water rinse and spin dry step are sufficient to completely remove the solvent, dissolved photoresist and any polymer residues.

This paper reviews the development of the Akrion process and several examples of improvement in stripping time and results from work with customers.
Pathfinding and Design Optimization of 2.5D/3D devices in the context of multiple PCBs
Authors: Yazdani Farhang , Park John
Published: October 2015

As the 2.5D/3D integration technologies shapes the future of semiconductor industry, pathfinding methodology and design optimization of such integration is still at its infancy. 2.5D/3D device integration generates ultra-high density interconnect between the devices. Planning and defining 2.5D/3D I/O cell placement in the context of the overall system is one challenge, optimizing such integration for performance and cost is another challenge. Defining 2.5D/3D partitions and integration feasibility at the early stages of product development is even more pronounced. Often, such early pathfinding feasibility and early assessment of the integration had direct impact on successful product.

In this paper, we disclose pathfinding and optimization methodology for integrating 2.5D/3D devices on silicon interposer in the context of multiple PCBs. Various integration schemes are investigated and trade offs are demonstrated. Additionally, we demonstrate constraint based signal assignment for early 2.5D/3D product evaluation and feasibility study. This paper teaches and contributes to rapid integration of 2.5D/3D devices in the context of multiple systems.
Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package
Authors: Zohni Wael , Katkar Rajesh , Co Rey , Cizek Rizza
Published: October 2015

Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years.

A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP.

This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware.

In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.
All-silicon multi-chip modules based on ultra-thin active pixel radiation sensors
Authors: Andricek Ladislav
Published: October 2015

The Semiconductor Laboratory of the Max Planck Society is designing and producing cutting edge radiation and particle sensors for experiments in basic science conducted by institutes of the German Max Planck Society and other international partners. One of the most challenging projects is the construction of so-called vertex detectors for experiments at high energy particle colliders like KEKB in Japan and the future International Linear Collider (ILC) as the next big international high energy physics project after the LHC at CERN, Geneva, Switzerland.

Modern vertex detectors are pixelated position sensitive particle sensors based on highly specialized silicon technology similar to CMOS or CCD sensors for commercial optical applications. The goal is to measure the track of a secondary particle and extrapolate to the point of its origin. One of the main challenges for up-to-date vertex detectors is the requirement of low mass to minimize the effect of scattering of the traversing particle in the sensor material itself and the sensor support structures.

We are developing ultra-low-mass sensors based on the DEPFET (DEpleted P-channel FET) pixel technology. DEPFETs are MOS transistors made on fully depleted detector grade silicon and combine the sensing and first signal amplification element in the same device. The thickness of the sensor is minimized and optimized for the best vertexing performance of the detector arrangement as whole. The detector is a cylindrical arrangement of sensor modules around the primary beam interaction point.

The sensor module is a silicon based multi-chip module with the module substrate being the sensor wafer itself. There are three functional regions on the MCM: the 50 μm thin sensitive active pixel area with the DEPFETs in a two metal and two poly-silicon layer technology, the ‘end of stave’ with three metal layers (two Al and one Cu) where the read-out electronic is placed and the narrow frame in the same interconnect technology with the steering ASICs. Three types of ASICs are used: a mixed-signal ASICs as the analogue front-end and ADC, a digital data handling chip and a steering chip in HV-MOS technology for the row-wise addressing and clearing of the pixel matrix. There are 12 chips in total on the module, all bump-bonded to the substrate, about 3000 area array bumps in total.

The finished module has 250 kPixels and is read out at a frame rate of 50 kHz via a wire-bonded flex cable.

Our paper will describe the technology for the production of ultra-thin DEPFET sensors and the monolithically integrated support, testing challenges during production and their solutions as well as electrical, thermal, and mechanical properties of the assembled MCMs. An outlook will be given on how micro-channels for active cooling will be integrated in the current MCM concept.
A PCB Technology Moisture Content and Electrical Conductivity Sensor Probe for Agricultural and Horticultural Applications
Authors: Dean Robert N. , Guertal Elizabeth , Newby Adam , Fain Glenn
Published: October 2015

Commercial printed circuit board (PCB) technology affords the realization of low-cost sensor probes for agricultural and horticultural applications. Plant growth can be optimized when the soil (in field crop applications) or the substrate (in greenhouse crop applications) properties can be measured and properly adjusted. Two important parameters are moisture content and electrical conductivity. Measuring moisture content allows the grower to better time irrigation for most efficient crop growth. Accurate moisture content measurement also allows the grower to apply sufficient irrigation volume for optimum plant growth while avoiding excessive irrigation volume. Likewise, measuring the electrical conductivity reveals useful information regarding ions in the soil or substrate, which can be used to optimize the application of plant nutrients or manage soil salinity.

Commercial soil probes are expensive, which limits their widespread use in commercial applications. PCB probes, on the other hand, can be very inexpensive and can quickly be redesigned to modify the form factor for different applications. These sensors make use of the materials and processes inherent in commercial PCB manufacturing, including the FR4 substrate, patterned Cu cladding and soldermask. The non-conductive E-glass FR4 substrate is used as the rigid backbone of the sensor probe. The patterned Cu cladding is used for electrodes and signal traces. The polymeric soldermask is used as a thin insulating and moisture barrier layer. With these materials, insulated fringing field sensors can be realized on the surface of the PCB to measure moisture content, while exposed metal pads on the surface can be used to measure electrical conductivity. Additionally, the PCB probe is directly compatible with the integration of any desired integrated electronic components. Furthermore, the turnaround time for a new PCB sensor design can be as little as 24 hours at modest cost, making this technology economically superior to traditional sensor technologies, such as silicon based MEMS, where it can take months to realize a new design and be very expensive.

A prototype sensor probe has been designed, fabricated and evaluated. Test data is analyzed, compared with test data from traditional sensor probes and presented.
2D PCB WITH 3D PRINT FABRICATIONS FOR RIGID-CONFORMAL PACKAGING OF MICROSENSOR IMAGING ARRAYS BASED ON BIOINSPIRED ARCHITECTURES
Authors: Fries David , Barton Chase StarrGeran
Published: October 2015

Macro sensor systems typically measure a localized space above a single sensor element. Expanding these single sensor elements into arrays permits spatial distribution measurements of a particular parameter and allow flux visualizations. Furthermore, applying microsystems technology to macro sensor systems yields imaging arrays and high resolution spatial/temporal sensing functions. Extending the high spatial resolution imaging over large areas is a desirable feature for new “vision” modes on autonomous robotic systems and for deployable environmental sensors.

Rigid-flexible PCB's are desirable for miniaturization and integration of systems for mobile technology. The hybrid substrates provide substantial flexibility in systems design and integration of multiple functions into limited spaces. Using this design and construction approach allows lightweight, complex, and space efficient systems. Flex microsystems based on structured, fiber or non-fiber filled PCB laminates permits packaging to occur at two levels, at the local (micro) substrate scale and at the macro scale with the ability to flex the system across millimeter to centimeter lengths on real everyday systems.

We continue to explore the use of PCB and PCBMEMS technology for new sensing concepts. In order to create rigid-conformal, large area imaging “camera” systems we have merged flexible PCB substrates with rigid constructions from 3D printing. This approach merges the 2D flexible electronics world of printed circuits with the 3D printed packaging world.

Furthermore employing architectures used by biology as a basis for our imaging systems we explored naturally and biologically inspired designs, and their relationships to non-visible imagery, and alternate mechanical systems of perception. Radiolaria are extremely tiny ocean organisms that utilize a similar additive construction process to 3D printing. Their cell bodies secrete a substance mainly composed of silica to form intricate exoskeletons used as a system of protection. A correlation can be made between the radiolaria's construction process and the plastic extrusion system of the 3D fused deposition model printer.

The benefits of additive construction are efficient use of materials, reduced cost and energy, and ability to customize forms. Through the use of bio-inspiration, a framework is laid out to base further research on (DFP)-design for packaging. Radiolarian exoskeletons take on a grid-like pattern while creating a cage around each microsensor interior and producing strong scaffolding. Using the 3D printed exoskeleton's form and function with flexible printed circuits one can create systems that are both rigid and form fitting with three-dimensional shape and enable new camera systems for various sensory applications.
New Lithography Requirements driven by 2.5D Interposer Manufacturing
Authors: Ruhmer Klaus , Battaglia Joe , Cochet Philippe
Published: October 2015

In recent years, 2.5D packaging has quickly turned from a buzz-word into an Advanced Packaging reality. Not dissimilar to the Multi-Chip-Modules (MCM's) of the past, 2.5D packages utilizing high density interposers with favorable electrical characteristics can be a cost efficient and high performance alternative to significantly more complex 3D or SOC integration schemes.

Dictated by the trend towards ever thinner, smaller and higher integrated and more capable devices, high density interposer technology is required to enable 2.5D packages. Patterning of these kind of substrates, regardless if manufactured on Silicon, Glass or other suitable materials requires relatively advanced lithography systems. Simple contact or proximity exposure is no longer up to the task.

This paper specifically lists the various patterning / lithography challenges which are being encountered when manufacturing high density 2.5D interposers. Typical back-end litho requirements regarding minimum resolution, overlay, maximum sidewall angle capability in relatively thick resist and depth of focus are being established and discussed. In addition, the application specific litho challenges such as a large exposure field size and IR backside alignment capability for TSV (Through-Silicon-Via) or TSG (Through-Glass-Via) definition are being reviewed and characterized.

As with all back-end processes, interposer manufacturing must be extremely cost efficient and high yielding. A middle ground between costly front-end processes and more robust, faster and lower cost back-end processes has to be found. This paper also discusses potential cost reduction via economy of scale. A detailed cost model for glass interposer manufacturing on large panels is being offered.
Efficient TSV Resist and Residue Removal in 3DIC
Authors: Pollard Kimberly , Guo Meng , Peters Richie , Phenis Mike , Mauer Laura , Taddei John , Youssef Ramey , Clark John
Published: October 2015

The continuing challenge to meet the need for lighter, smaller, faster and smarter electronic systems has pushed the advancement of 2.5D and 3D technology. The ability to create and integrate through-silicon vias (TSV) into device designs in 2.5- and 3-D platforms allows a decrease in interconnection path length, which results in improved device performance and reliability in a small form factor. Mainly due to its high silicon etch rate and selectivity to mask materials, the Bosch process is often used in the TSV fabrication. In this process, the silicon via is created by the deep reactive ion etching (DRIE). DRIE is comprised of repeating a combination of steps: an etch step and a passivation step. The passivation created in the DRIE process results in a fluoropolymer residue remaining on the wafer at the end of the process. The residue must be removed to enable deposition of a defect-free barrier, which enables a defect-free seed layer and void-free plating into the via. There are numerous technical papers and presentations on the etching and filling of these vias but the process for cleaning remains under addressed. Initially, standard processes used after RIE and consisting of an ashing process to remove any remaining photoresist, followed by immersion in a solution-based post etch residue remover were adopted for post-TSV cleans. However, the fluoropolymer does not have the same chemical characteristics as typical post-RIE etch residues and the major challenge has been the difficulty to completely remove it, especially on the via sidewall, using traditional post etches residue removers. Therefore, new formulated cleaning solutions and processes are actively sought for the removal of post etch residue for TSVs. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using a proprietary environmentally friendly chemistry, coupled with a megasonic final rinse provides a unique solution for both polymer residue and photoresist removals on high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.