Electrical stress reliability of graphene field effect transistor under different bias voltages
Authors: Wang Song-Wen , Guo Hong-Xia , Ma Teng , Lei Zhi-Feng , Ma Wu-Ying , Zhong Xiang-Li , Zhang Hong , Lu Xiao-Jie , Li Ji-Fang , Fang Jun-Lin , Zeng Tian-Xiang ,   School of Materials Science and Engineering, Xiangtan University, Xiangtan 411105, China,   State Key Laboratory of Science and Technology on Reliability Physics and Application of Electronic Component, China Electronic Product Reliability and Environmental Research Institute, Guangzhou 511300, China,   Northwest Institute of Nuclear Technology, Xi’an 710024, China
Published: November 2024

In this paper, graphene field effect transistors (GFETs) with the top-gate structure are taken as the research object. The electrical stress reliabilities are studied under different bias voltage conditions. The electrical pressure conditions are gate electrical stress (<i>V</i><sub>G</sub> = –10 V, <i>V</i><sub>D</sub> = 0 V, and <i>V</i><sub>S</sub> = 0 V), drain electric stress (<i>V</i><sub>D</sub> = –10 V, <i>V</i><sub>G</sub> = 0 V, and <i>V</i><sub>S</sub> = 0 V), and electrical stresses applied simultaneously by gate voltage and drain voltage (<i>V</i><sub>G</sub> = –10 V, <i>V</i><sub>D</sub> = –10 V, <i>V</i><sub>S</sub> = 0 V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage <i>V</i><sub>Dirac</sub> degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressures, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions have varying effects on the drift direction and degradation of <i>V</i><sub>Dirac</sub>: gate electrical stress and drain electrical stress cause <i>V</i><sub>Dirac</sub> drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate voltage and drain voltage, leading to <i>V</i><sub>Dirac</sub> degradation of GFETs. An analysis of the causes indicates that different electrical stresses produce different electric field directions in the device, which can affect the carrier concentration and movement direction. Electrons and holes in the channel are induced and tunnel into the oxide layer, and they are captured by trap charges in the oxide layer and at the interface between graphene and oxide, forming oxide trap charges and interface trap charges. This is the main reason for reducing carrier mobility of GFET. Different electric field directions under different electric stresses produce positively charged trap charges and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of <i>V</i><sub>Dirac</sub> drift in GFETs. When both trap charges coexist, they have a canceling effect on the <i>V</i><sub>Dirac </sub>drift of the GFETs. Finally, by combining TCAD simulation the simulation model of the influence of electrical stress induced trap charge on the <i>V</i><sub>Dirac</sub> generation of GFET is further revealed. The result demonstrates that the differences in the type of trap charge banding have different degradation effects on the <i>V</i><sub>Dirac</sub> of GFETs. The related research provides data and theoretical support for putting graphene devices into practical application.