(Invited) Stability under Gate Bias Stressing of Amorphous Oxide Thin Film Transistors
Authors: Niang Kham Man , Flewitt Andrew J. 
Published: February 2020

Amorphous oxide semiconductors (AOSs) are highly transparent, wide band gap materials with high electron mobility (>= 10 cm2 V–1 s–1), which are suitable for channel layers in thin film transistors (TFTs).1 With the emergence of these materials as the alternative to the incumbent a-Si:H for large area electronics and displays,2 understanding of the stability of these devices becomes vitally important.

Stability studies have been reported for the leading AOS material, amorphous indium gallium zinc oxide (a-IGZO) and others such as amorphous zinc tin oxide (a-ZTO), indium zinc oxide and polycrystalline zinc oxide. Various methods such as illumination, gate or drain bias stressing, gate pulsing and constant current stressing have been reported. The deposition technology, choice of gate dielectrics, use of passivation and operation environment can also affect the device stability, as previously reported in a comprehensive review.3 Here, we focus on gate bias stressing – namely positive bias stress (PBS) and negative bias illumination stress (NBIS). We review different experiments and the models used to analyse the threshold voltage (Vth
) shift arising from bias stressing. In particular, the oxygen vacancy migration model that is proposed for the Vth
shift in a-IGZO TFTs is discussed and contrasted with the defect creation model used for a-Si:H TFTs.4-6

We will compare the stability under PBS of a-IGZO TFTs with a-ZTO TFTs. These films are deposited by remote-plasma reactive sputtering. Staggered bottom gate architecture TFT are produced using thermal SiO2 as gate dielectric. Typical TFTs operate in enhancement mode with field effect mobility > 10 cm2 V–1 s–1, switching ratio of ~108 and a sub-threshold slope of ~ 0.6 V dec–1. TFTs were subjected to a gate bias stress field of 1MV cm-1 over the initial threshold field and IDS
was measured as a function of time up to 80,000 s at temperatures between 65 and 105 °C. The time and temperature dependence of the Vth
shift was analysed using the thermalization energy concept, which allows two parameters with some physical interpretation to be extracted: a measure of the energy barrier to the Vth
shift process and an associated attempt-to-escape frequency. The extracted parameters of oxide TFTs are also compared to those of a-Si:H TFTs.

This work is funded by the Engineering and Physical Sciences Research Council (EP/M013650/1).

References

1 K. Nomura, Nature 432 (2004).

2 J. K. Jeong, J. H. Jeong, J. H. Choi, J. S. Im, S. H. Kim, H. W. Yang, K. N. Kang, K. S. Kim, T. K. Ahn, H.-J. Chung, M. Kim, B. S. Gu, J.-S. Park, Y.-G. Mo, H. D. Kim, and H. K. Chung, SID Symposium Digest of Technical Papers 39, 1 (2008).

3 J. F. Conley, in Instabilities in oxide semiconductor transparent thin film transistors, 2009, p. 50.

4 A. J. Flewitt and M. J. Powell, Journal of Applied Physics 115, 134501 (2014).

5 S. C. Deane, R. B. Wehrspohn, and M. J. Powell, Physical Review B 58, 12625 (1998).

6 K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell, and A. J. Flewitt, Applied Physics Letters 108, 093505 (2016).