bluuebunny/crossref_metadata_2025 huggingface dataset:
Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail
Authors: Weizman Yoav , Baruch Ezra , Zimin Michael
Published: December 2020

Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.
Laser Beam Based ESD Defect Localization in ICs
Authors: Beaudoin Félix , Perdu Philippe , Desplats Romain , Doche Emmanuel , Wislez Alain , Beauchêne Thomas , Lewis Dean , Carisetti Dominique , Trémouilles David , Bafleur Marise
Published: December 2020

The application of laser beam based techniques for ESD defect localization in silicon and gallium arsenide integrated circuits is studied. The Thermal Laser Stimulation technique (OBIRCH, TIVA) is shown to precisely localize electrostatic discharge (ESD) defects under low voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline silicon generated a Seebeck voltage sufficiently large to be detected. Finally, the pulsed Optical Beam Induced Current technique (OBIC) under no bias condition was evaluated and compared to both biased and nonbiased Thermal Laser Stimulation techniques. It proved to be complementary as it offers a different insight into the ESD induced degradation.
Advanced sub 0.13µm Cu Devices – Failure Analysis and Circuit Edit With Improved FIB Chemical Processes and Beam Characteristics
Authors: Casey J. David , Gannon Thomas J. , Krechmer Alex , Monforte David , Antoniou Nicholas , Bassom Neil , Huynh Chuong , Silva Brian , Hill Raymond , Gu George , Ray Valery , Saxonis Andrew , Chandler Clive , Megorden Michael , Carleson Peter , Phaneuf Michael , Li Jian
Published: December 2020

Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (106 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.
Microwave Frequency Signal Propagation in Backside Focused Ion Beam (FIB) Fabricated Interconnects
Authors: Rowlette Jeremy A. , DiBattista M. , Fortuna Seth , Livengood Richard H.
Published: December 2020

We present for the first time the results of a comprehensive study of the increase in propagation delay of multi-GHz digital signals due to backside FIB fabricated interconnects. Signal propagation delays were measured in 90nm CMOS technology circuits as a function of interconnect material properties and physical dimensions. We compare the empirical results of this study to SPICE calculations, which were based on an equivalent circuit element model of the interconnect. We show that the empirical data obtained in these experiments supports the validity of the equivalent electrical model for the frequency range typically encountered in modern microprocessor debug. Based on the results or our analysis, we comment on the future capability of backside FIB circuit edit (CE) interconnection technology as it pertains to the debug of flip-chip packaged IC’s operating at multi-GHz frequency.
Driving Baseline Yields on ASICs Using Logic Mapping
Authors: Benware Brady R.
Published: December 2020

Logic mapping is the process of automatically correlating inline inspection defects with diagnosed faults from electrical testing. This paper presents a software based tool for this purpose and focuses on its specific use for impacting baseline yield enhancement. A detailed approach to utilizing logic mapping for this purpose is also presented. Results from a 10 wafer study using this tool are analyzed and show a defect correlation success rate of 31%. Additional work is presented for improving the logic mapping success rate and diagnosability of failures.
Boundary-Scan’s Next Plateau: Testing and In-System Configuration at the System Level
Authors: Collins Pete , Dellecker Ray
Published: December 2020

Boundary-scan is a technology that’s been around for over ten years and is delivering the results foreseen by the IEEE working group that developed the 1149.1 specification. Many SMT (surface mount) production lines around the world use boundary-scan to solve the testing challenges presented by today’s complex designs. These users are realizing the vision of the specification, using it to restore test access and fault coverage to assemblies with few physical test points relative to the number of electrical nets to be tested. As the boundary-scan standard has gained acceptance and credibility, users, chip vendors and tools providers have developed important extensions of the original vision. Among the extensions already available or under active consideration is the use of boundary-scan for analog testing, concurrent programming of multi-vendor cPLD’s, dynamic verification of high-speed communication channels, and application within higher-level electronic assemblies beyond printed circuit boards i.e. to subsystems and systems. This paper describes the effectiveness of boundaryscan at the system level, focusing on the use of IEEE Std. 1149.1 compatible devices and ATPG tools to accomplish system level testing and in-system configuration.
Case Studies of IR Based Rapid PC Motherboard Failure Analysis
Authors: Swart Jan , Woo John , Zumwalt Randall , Birdsley Jeff , Taffese Yitages
Published: December 2020

This article discusses the techniques useful in the failure discovery process in PC motherboard. It discusses the application of infrared (IR) camera in failure analysis, which overcomes time consumption problems. The article focuses on the experience gained from nine different case studies, where IR thermography system was used to both measure relative temperatures as well as absolute temperatures of components. The failures investigated are overdriven components, finding end-of-life but still functional components, correctly specified components with quality defects, incorrect component placement, internal voltage common collector to ground low resistance integrated circuits failures, PCB defects resulting in power to ground failures, soldering defects resulting in lead opens or solder bridges, and copper trace manufacturing defects or stress-induced cracks.
Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current
Authors: Stellari Franco , Song Peilin , Tsang James C. , McManus Moyra K. , Ketchen Mark B.
Published: December 2020

Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.
Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis
Authors: Pan Hui , Gibson Thomas
Published: December 2020

In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.
Fault Isolation of High Resistance Defects Using Comparative Magnetic Field Imaging
Authors: Orozco Antonio , Talanova Elena , Gilbertson Anders , Knauss L.A. , Wang Zhiyong , Skoglund Lars , Smith David G. , Dias Rajen
Published: December 2020

As integrated circuit packages become more complicated, the localization of defects becomes correspondingly more difficult. One particularly difficult class of defects to localize is high resistance (HR) defects. These defects include cracked traces, delaminated vias, C4 non-wet defects, PTH cracks, and any other package or interconnect structure that results in a signal line resistance change that exceeds the specification of the device. These defects can result in devices that do not run at full speed, are not reliable in the field, or simply do not work at all. The main approach for localizing these defects today is time domain reflectometry (TDR) [1]. TDR sends a short electrical pulse into the device and monitors the time to receive reflections. These reflections can correspond to shorts, opens, bends in a wire, normal interfaces between devices, or high resistance defects. Ultimately anything that produces an electrical impedance change will produce a TDR response. These signals are compared to a good part and require time consuming layer-by-layer deprocessing and comparison to a standard part. When complete, the localization is typically at best to within 200 microns. A new approach to isolating high resistance defects has been recently developed using current imaging. In recent years, current imaging through magnetic field detection has become a main-stream approach for short localization in the package [2] and is also heavily utilized for die level applications [3]. This core technology has been applied to the localization of high resistance defects. This paper will describe the approach, and give examples of test samples as well as results from actual yield failures.
Dynamic Infrared System Level Fault Isolation
Authors: Naoum John A. , Rahardjo Johan , Taffese Yitages , Chagny Marie , Birdsley Jeff , Woo John C. , Morris Aaron
Published: December 2020

The use of Dynamic Infrared (IR) Imaging is presented as a novel, valuable and non-destructive approach for the analysis and isolation of failures at a system/component level.
XRF Correlation of Board Reseats Due to Intermittent Failures from the Use of Thin Gold Plating finish on the Contact Fingers
Authors: Stein Dan , Hernandez Victor , Nailos Mary Ann
Published: December 2020

This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).
Real Time SEM Imaging of FIB Milling Processes for Extended Accuracy on TEM Samples for EFTEM Analysis
Authors: Gnauck P. , Zeile U. , Hoffrogge P. , Benner G. , Orchowski A. , Rau W-D.
Published: December 2020

We present application examples of site specific energy filtered transmission electron microscopy (EFTEM) analysis using advanced focused ion beam (FIB) specimen preparation techniques. Specifically, we address topics such as throughput and reliability enhancement by chemically assisted broad ion beam milling and on-line monitoring of the etch process. We discuss how integrated elemental analysis by EFTEM can be used to gain quantitative information on the broad variety of new material systems currently entering front end and back end of the IC manufacturing process line. The accelerating pace of device integration results in extreme demands for quantitative analysis in process development, yield ramp-up and process control with spatial resolution and elemental sensitivity at the very limits of currently available instrumentation. Historically, the high resolution performance of TEM analysis has been hampered by long turn around times for the required sample preparation. Meanwhile the routine use of FIB systems for “trench” and “lift-out” preparation techniques allows for an enormous increase in the efficiency of TEM analysis.
VLSI Design for Functional Failure Analysis in the < 90 nm and Flip-Chip Era
Authors: Weizman Yoav , Baruch Ezra
Published: December 2020

In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the < 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the < 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.
Microhardness Testing on Via Fill Material for Via In Pad Technology
Authors: Armendariz Norman J. , McCormick Carolyn
Published: December 2020

Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.
Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques
Authors: Perungulam Srikanth , Gleason Albert
Published: December 2020

This paper outlines some of the optical and e-beam based techniques that can be used to isolate via chain failures. The Scanning electron microscope based techniques discussed are Passive Voltage Contrast (PVC) and Substrate Current Imaging (SCI). The optical beam technique discussed is Thermally Induced Voltage Alteration (TIVA) on the Laser Scanning Microscope. A combination of these techniques can be used to effectively analyze all types of via chain failures.
Semi-Automated Cross-Section Preparation Process for Complex Multi-Face Perimeter Samples
Authors: McDonald Todd
Published: December 2020

The fixed position sample mover plates currently offered to the industry only facilitate two sided grinding and polishing. 3 and 4-sided requests cannot be accommodated with these fixed position mover plates. Ultimately this means performing some or all of the work manually. Described here is a fixture and process solution that makes semi-automation possible through the entire process.
Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Devices
Authors: Len W.B. , Liu Y.Y. , Phang J.C.H. , Chan D.S.H.
Published: December 2020

A spectroscopic photon emission microscope (SPEM) which is capable of high resolution spectroscopy for a continuous wavelength range between 300 nm to 1700 nm has been developed. Photon emissions were observed at energy levels below silicon bandgap from pn junctions and MOSFET devices at different biases. The experimental results indicate significant emission activity in this range. It was also found that the spectra is closely correlated to the electric fields present in the devices.
Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment
Authors: Chen Yuan-Shih , Lee Jeng-Han
Published: December 2020

Voltage contrast(VC) is a popular method for failure site isolation[1]. After study we find some weakness on tradition voltage contrast. This paper presents a new voltage contrast procedure that can conquer the weakness. For a CMOS technology, there are four kinds of contact node were used. They are N+/PW node, P+/NW node , poly gate node and well node. Traditional voltage contrast condition uses constant SEM primary energy like 1KV can not distinguish these four kinds of node well. For example a contact lead to P+/NW will be bright in tradition VC[2], but a contact connected to well will also be bright. It means tradition VC can not distinguish difference between contact lead to P+/NW and contact lead to well. To improve the weakness of the traditional VC, we will present a new Voltage Contrast technique, which could distinguish all contact types in CMOS technology.
A Flexible, Low Cost Test System for Failure Analysis of High Power Mixed Signal ASICs
Authors: Kolasa T. , De La Torre J. C. , Bertram L.
Published: December 2020

In this paper, we will present our solution to the problem of test based fault localization in the failure analysis laboratory environment. The test system described herein is currently used for a number of high power mixed signal application specific integrated circuits (ASICs) that incorporate functions including switching power supplies, charge pumps, high current drivers, precision references, ADCs/DACs, comparator circuits, and digital cores. The solution addresses the shortcomings of alternative options through modular construction, compact size, and use of a commercially available graphical software compiler to create the control code and graphical user interface (GUI).
Modeling Secondary Electron Emission from High Aspect Ratio Holes
Authors: Wang Q. S. , Thompson M. A. , Schultz W. , Lundquist T. R.
Published: December 2020

The success of circuit editing depends not only on x-y navigation to precise coordinates on the integrated circuits (IC), but also on precise z navigation. Certainly, secondary electron (SE) emission has proven to be the most accurate monitoring technique to accomplish this z precision. Even so, it has been amazing that SE monitoring works in high aspect ratio holes—reports have been made of high aspect ratio holes near 30:1. To explain why this occurs, therefore, is of interest and, by understanding how it works, we may improve the technique.
Characterization of Interconnect Defects Due to Electromigration Using Scanning Thermal Microscopy
Authors: Wu E.X.W. , Zheng X.H. , Phang J.C.H. , Balk L.J. , Lloyd J.R.
Published: December 2020

In this paper, the temperature distributions around interconnect defects due to electromigration are presented. A method to overlay the temperature distribution over the optical microscope image of the physical defect has also been developed. This allows a direct correlation of the temperature distribution and the physical structure of the defect.
Indium Tin Oxide (ITO) Film Removal Technique for Failure Analysis on Packaged Optoelectronic Devices
Authors: Elliott Shawn , Gordon Jean , Plourde Peter
Published: December 2020

Various detector chips in optocoupler devices have a thin indium tin oxide (ITO) film deposited over the passivation. This transparent, conductive film is found over the photodetecting area of the die. When this film is electrically connected to ground potential through contacts, it acts as a shield to avoid inversion failures by sinking any charge buildup to ground. In order to perform a full electrical failure analysis on these optocoupler detector chips, the ITO layer must be removed. An extensive search found numerous papers on etching this film over glass substrates, but no known technique was found to selectively remove the ITO layer on a packaged die. This paper discusses an approach to remove this film using an argon gas etch technique. The ideal characteristics of any process used to remove this film on a finished die would be to completely etch the ITO layer, electrically isolating it from ground, while leaving the underlying passivation and metallization fully intact. This would allow for further electrical failure analysis of the die without causing additional damage or affecting the failure mechanism. The results of an experiment using various chemical and gas etchants found that an argon gas etch would remove the ITO layer while only slightly etching the phosphosilicate glass (PSG) passivation beneath. Electrical failure analysis of the die continued at this point, and a subsequent buffered oxide etch (BOE) removed the remaining passivation, leaving the exposed metallization and oxide completely intact. This technique has been used successfully on device failures to find passivation contamination shorting the aluminum metallization to the ITO film.
Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment
Authors: Liau Eric , Schmitt-Landsiedel Doris
Published: December 2020

Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.
Dopant Region Imaging on Front Surface of Silicon Devices Using a Coaxial Photon-Ion Column
Authors: Pajak Robert G. , Baiocchi Frank A. , Roy Erwan Le
Published: December 2020

An n-well contrast enhancement process, which is used for backside navigation has been further developed to observe dopant regions on top-down prepared devices. Dopant regions for the following structures were delineated: ▪ p-active regions in n-wells; ▪ n-active regions in p-wells; ▪ n-well to p-well interface; ▪ p+/p interface. The enhancement process to obtain this contrast was done on a Credence OptiFIB using a coaxial FIB/optical column. Illumination of the sample is a critical component of the process. First, the high contrast level obtained at a p/n junction was only achieved by using light assisted FIB oxide deposition. Second, sample illumination was found to enhance contrast while imaging the region of interest using the focused ion beam. The contrast becomes permanent only after the oxide is deposited. Contrary to chemical etch techniques imaged in a SEM, this enhancement process as well as the imaging process were completed in-situ. Further, this process proved to be very reproducible. This dopant contrast enhancement process provides an alternative to wet chemical delineation methods for the verification of dopant photomask registration, for accomplishing reverse engineering and for observing missing implants.
Failure Analysis of Soft Single Column Failure in Advanced Nano SRAM Device with Internal Probing Techniques
Authors: Lin Hung-Sung , Chang Wen-Tung , Chao Chia-Hsing , Wang Jesse , Lin Chang-Tan , Lin Coswin
Published: December 2020

Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.
The Effectiveness of OBIRCH Based Fault Isolation for Sub-90nm CMOS Technologies
Authors: De la Bardonnie M. , Kwakman L.F.Tz. , Ly K. , Ross R. , Lorut F. , Lamy M. , Wyon C. , Hiruma Y. , Roux J.
Published: December 2020

Even though failure analysis performed with a latest generation Phemos 2000 Optical Beam Induced Resistance Change (OBIRCH) tool has given excellent results for 120nm and 90nm technology developments, the limitations of tool and technique become apparent when used for the 65nm technology node and beyond. This article discusses the use of a pulsed laser in combination with a lock-in amplifier for OBIRCH-based fault isolation in latest generation CMOS devices. Using such set-up with appropriate settings for laser pulse frequency, scan speed, and phase shift off-set, a ten-fold signal-to-noise ratio gain is achieved. This improved S/N ratio allows detecting faulty circuitry with higher sensitivity and isolating faults that cannot be detected with the traditional OBIRCH set-up. Various case studies on latest technology devices are presented to illustrate the interest of adding the lock-in capability to the standard OBIRCH tool.
The Joy of SOI: As Viewed from a Backside FIB Perspective
Authors: Herschbein Steven , Rue Chad , Scrudato Carmelo
Published: December 2020

For most advanced semiconductor products, the preferred methodology for achieving Focused Ion Beam (FIB) circuit modification and node access is through the backside of the chip. The high density of interconnect wiring and the presence of C4 solder bumping has made complex edits virtually impossible with conventional frontside techniques. IBM has developed a set of procedures for performing backside edit on circuits built using the Silicon-On-Insulator (SOI) process. While the basic approach and techniques parallel many of the established practices developed for handling transistors built in conventional bulk silicon, there are a number of key and critical differences. In this paper, we will address the basic instruction set developed for successful FIB work on SOI product. This will include backside silicon surface preparation, charge control, endpointing during high volume silicon removal, global and local coordinate lock techniques, floor voltage contrast phenomena, floor preparation and preservation, fill pattern issues and advantages, and finally the target structure alignment, access, connection and/or removal. Post process bake and handling will also be discussed.
Furthering the Business Proposition of a Robust System Level Failure Analysis Framework: A Focus on Enabling Product Services
Authors: Bjork Roger
Published: December 2020

A few years ago, along with colleagues from Intel and Dell, we shared with you the importance of Failure Analysis as a business proposition[1], This paper will identify even more business processes which will benefit from a robust System Level Failure Analysis framework. More and more companies strive to differentiate themselves from their competition by focusing not just on product features and price, but also on how well they serve their customers. An effective Service Plan (Figure 1) is fundamental in the provision of this service. No matter how broad a company’s service offering portfolio, a fundamental enabler of any Fault Management system is the ability to identify and predict failures. Further, a robust Knowledge Management system must exist to enable the collection and dissemination of services intellectual property (IP) in an effective manner, and facilitate a broad level commonality analysis that provides the ability to monitor trends and shifts in product performance.
Developing a More Inclusive System Level ESD Characterization Methodology
Authors: Rahardjo Johan , Miller Socorro , Lopez Leo , Williams Steve L.
Published: December 2020

ESD (Electrostatic Discharge) has become an increasing problem on electronic devices. The electronics industry is always looking for ways to improve the reliability of electronic devices by enhancing their test methods. The industry has found that the current ESD test methods do not encompass all possible scenarios to which electronic devices are exposed at the customer site. This paper describes a novel method to bridge the gap between current system level ESD specifications and customer real world situations. Field failure investigations led us to discover a new customer situation where ESD is induced on a computer system through a peripheral/cable that is already attached (different than hot-plug event). To simulate this scenario, ESD was injected directly into the signal pins of the bus being tested, creating what we call the DCD (Direct Contact Discharge) test methodology. This paper compares DCD against the current ESD standards and demonstrates that introducing DCD into the current ESD testing methodology will significantly lower the system field failures. DCD is not a replacement for current ESD testing practices in the industry; DCD is a complement that allows a more inclusive ESD test coverage
X-ray Fluorescence Imaging for High Resolution Elemental Mapping
Authors: Feser M. , Yun W. , Lyon A. , Wang Y. , Sehadri S.
Published: December 2020

X-ray fluorescence imaging is a novel non-destructive method to obtain sub-100nm spatial resolution elemental maps with short data acquisition times. The method has a wide range of applicability in the field of semiconductor manufacturing and semiconductor failure analysis. Imaging of copper interconnects on ICs for the location of voids and shorts is one particular application that is relevant for current and future needs of nondestructive inspection and failure analysis of backend processes.
3-D EBIC Technique using FIB and EB Double Beam System
Authors: Yoshida Eiji , Tanaka Tomohiro , Oyamada Taro , Koyama Tohru , Komori Junko , Maegawa Shigeto
Published: December 2020

We propose visualizing techniques of a diffusion layer using an electron beam induced current (EBIC) for a site-specific cross-section formed by focused ion beam (FIB) treatment. Moreover, we present a three-dimensional (3-D) EBIC technique using a double beam (FIB & EB) system to understand the diffusion structure. This 3-D application of the EBIC technique is very useful for delineating PN junctions and pointing out implant defects in ULSI devices. Furthermore, we applied the EBIC technique to backside circuit editing with FIB. The end-point of the silicon trench etching can be easily decided by observing the plane EBIC images. Highly reliable backside circuit editing becomes possible together with a DUV laser marking technique using an IR-optical microscope system.
Case Studies of the Use of Image Processing in Metrology and Failure Analysis
Authors: Ramanujachar Kartik
Published: December 2020

This paper describes the use of image processing techniques in metrology and failure analysis with the help of three case studies. The first study concerns a technique that significantly automates the process and hence enables both a rapid and accurate extraction of cumulative distribution function for transistor CD through the use of edge detection and quantification of image intensities. The second study is about utilizing a cross correlation algorithm and an appropriately chosen sample and image to estimate the "on image" spatial resolution of an scanning electron microscope. The last case study uses image data acquired with an atomic force microscope. The paper describes how information theoretic concepts like entropy and mutual information combined with image segmentation and nearest neighbor extraction can be used to isolate those regions of the AFM scan that can potentially benefit from further analysis.
DuPont EKC265™ as a Copper Metal Etchant to Assist FIB Edits through Large Copper Power Supply Lines
Authors: Mulder Randal E.
Published: December 2020

State-of-the-art semiconductor technologies use multiple copper metallization layers to route power and signals throughout the semiconductor device. These devices have four to six metal layers with the top layers predominately used to route the large power supply lines. To gain access to these lower signal lines, focused ion beam (FIB) must be used to cut large windows through the large power supply lines; this is very difficult. This paper demonstrates how EKC265 can be used as a copper metal etch to remove the copper of the power supply lines. This allows the FIB to cut large windows through the material layers to gain access to the lower metal layers for probing or FIB edits. Results are shown for FIB work using EKC265 and for FIB work without the using EKC265. EKC265 eliminates the need to use the FIB to remove copper giving a much more uniform milling result.
Nanomechanical Characterization in the FIB
Authors: Moore Thomas M.
Published: December 2020

The availability of the focused ion beam (FIB) microscope with its excellent imaging resolution, depth of focus and ion milling capability has made it an appealing platform for materials characterization at the sub-micron, or "nano" level. This article focuses on nanomechanical characterization in the FIB, which is an extension of the FIB capabilities into the realm of nano-technology. It presents examples that demonstrate the power and flexibility of nanomechanical testing in the FIB or scanning electron microscope with a probe shaft that includes a built-in strain gauge. Loads that range from grams to micrograms are achievable. Calibration is limited only by the availability of calibrated load cells in the smallest load ranges. Deflections in the range of a few nanometers range can be accurately applied. Simultaneous electrical, mechanical, and visual data can be combined to provide a revealing study of physical behavior of complex and dynamic nanostructures.
High Resolution Acoustic Microscopy with Low Frequency and Its Applications in Analysis of Ferroelectrics
Authors: Yin Q.R. , Yu H.F. , Zeng H.R. , Li G.R. , Ding A.L.
Published: December 2020

Nondestructive observation of domain structure of ferroelectrics, dynamic behavior under external field and related phenomena is becoming significant. As a nondestructive and subsurface characterizing technique, the authors developed acoustic microscopy based on a commercial scanning probe microscope for direct observation of local ferroelectricity, elasticity and defects on several inorganic functional materials, transparent PLZT ceramics, relax-based PMN-PT crystal and lead-free bismuth titanate ceramics without any special processing (polishing or etching) to the sample. The direct observation is particularly useful and convenient for analyzing ferroelectrics/semiconductor integrated material and devices. The excitation frequency is in the range of several kHz to decades of kHz, which is much lower than that of the traditional acoustic imaging techniques. But several applications of scanning probe acoustic microscope (SPAM) involving ferroelectric samples with the resolution of 10nm were obtained. The expanding scope of application for SPAM shows exciting possibilities for non-destructive analyses in the microelectrics industry.
Depth Measurement of Dislocations in Si Substrate by Stereo TEM
Authors: Bow Jong-Shing , Yu Speed
Published: December 2020

Traditional plane-view TEM images, which have large fields of view and are usually used to check the existence of dislocations, cannot tell whether a dislocation goes through the p-n junction or not. While XTEM images tell the local depth of a small part of a dislocation only, other methods have to be developed to explore how a dislocation goes in the substrate. In this article, the authors have modified the technique of stereo TEM, which was used to study the 3D shapes of precipitates, to study how a dislocation runs in the Si substrate. Three images recorded after tilting the TEM sample were used for measuring the dislocation depth profile. The distances between a few chosen points on the dislocation and the reference line were measured from above three images. Results suggested that the depth profiles of dislocations in the Si substrate can be accurately determined by stereo TEM.
Gate Oxide Defect Localization and Analysis by Using Conductive Atomic Force Microscopy
Authors: Lee Z. H. , Lin C. J. , Lai S. W. , Chou J. H.
Published: December 2020

This paper describes gate oxide defect localization and analysis using passive voltage contrast (PVC) and conductive atomic force microscopy (C-AFM) in a real product through two case studies. In this paper, 10% wt KOH was used to etch poly-Si and expose gate oxide. In the case studies, different types of gate oxide defects will cause different leakage paths. According to the I-V curve measured by C-AFM, we can distinguish between short mode and gate oxide related leakage. For gate oxide leakage, KOH wet etching was successfully used to identify the gate oxide pinholes.
The Enhancement of Abnormal Photon Emission Identification for Advanced Processes using a Backside Cooling PEM System
Authors: Wang C. H. , Lai S. W. , Lee Z. H. , Chou J. H.
Published: December 2020

Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing, in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.
Single Via Deprocessing Techniques to Enable Physical Analysis for Semiconductor Process Integration
Authors: Hammett Jacob E. , Qin Wentao , Theodore David
Published: December 2020

Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing; in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example, a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.
Stacked Polysilicon/Metal Capacitors Failure Analysis
Authors: Nguyen Dat T. , Huang Frank
Published: December 2020

Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.