Keynote; Material Challenges and Opportunities in Ge/III-V Channel MOSFETs
Authors: Takagi Shinichi , Kim Sang-Hyeon , Yokoyama Masafumi , Nishi Koichi , Zhang Rui , Takenaka Mitsuru 
Published: February 2020

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future. There can be several CMOS structures using III-V/Ge channels. One of the ultimate CMOS can be the co-integration of a III-V nMOSFET and a Ge pMOSFET. While Ge or III-V CMOS is also plausible in terms of the simplicity of the material integration, the key issues are the realization of high performance Ge nMOSFETs or III-V pMOSFETs. Also, even in Ge pMOSFETs and III-V nMOSFETs, the CMOS technologies have not been established yet. Thus, viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies.

In addition, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of short channel effects by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks.

Our approach for the channel formation is the wafer bonding for III-V materials and the Ge condensation technique for Ge/SiGe channels. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT.

We have proposed and demonstrated UTB InGaAs-based channel formation for III-V nMOSFETs by using direct wafer bonding. Ultrathin body (3.2 nm InGaAs)/UTBOX (Al2O3(4.4 nm)/SiO2(3.3 nm)) substrates are realized with high material quality. As channel engineering to boost the mobility in UTB InGaAs-based channels, we have introduced two boosters, higher In content InAs channels and MOS interface buffers composed of lower-In-content buffers. Based on these technologies, we have realized sub-20-nm-channel-length Tri-gate InGaAs/InAs/InGaAs-OI QW MOSFETs with good electrostatic. Here, wide-range Vth tunability in Tri-gate InAs-OI MOSFETs through VB control has been demonstrated. As for III-V pMOSFETs, we have also demonstrated UTB GaSb-OI pMOSFETs on Si by using wafer bonding. Based on these technologies, a novel III-V CMOS structure composed of GaSb/InAs hetero-structures is proposed.

One of the most critical issues in Ge MOSFETs is the realization of gates stacks with superior MOS interfaces. In order to realize low Dit, high mobility and thin EOT at the same time, we have proposed a interfacial layer formation process employing ECR oxygen plasma to form GeOx ILs after thin Al2O3 or HfO2/Al2O3 ALD. This ultrathin GeOx IL is found to effectively reduce Dit in both valence and conduction band sides. N- and p-MOSFETs with the HfO2/Al2O3/GeOx/Ge gate stacks exhibit the excellent electrical characteristics under EOT of 0.76 nm. In spite of this ultrathin EOT, high electron and hole mobility is obtained in comparison with the thick GeO2/Ge mobility and the Si mobility, particularly in high Ns region. These results strongly demonstrate that HfO2/Al2O3/GeOx/Ge gate stacks can realize high performance Ge n- and pMOSFETs with minimal mobility expense under aggressive scaling of EOT.