(Invited) A Complete Suite of Experimental Techniques for Electrical Characterization of Conventional and Incoming High-k Dielectric-Based Devices
Authors: Dueñas Salvador , Castán Helena , García Héctor , Arroval Tonis , Tamm Aile , Kukli Kaupo , Aarik Jaan 
Published: February 2020

High permittivity (high-k) dielectric films are of considerable interest as gate oxide materials in advanced complementary metal-oxide-semiconductor (CMOS) [1] as well as in dynamic and resistive random access memory devices (DRAM and ReRAM) [2]. While high-k materials can help to solve gate leakage problems with leading-edge processes, there still are some remaining challenges [3].  Drastic improvements in the quality of high-k films with respect to film density, thermal and electrical stability, quality of the interfaces with silicon substrate and/or metal gates, have been produced. However, there are several technical hurdles such as threshold voltage instabilities, carrier channel mobility degradation, and long-term device reliability. In fact, the performance of high-k film-based CMOS devices is strongly limited by the trapping and detrapping of charges in the pre-existing traps inside the high-k dielectrics [4]; also, reliability and variability are major concerns in the ReRAM development [5, 6]. During the last years, and nowadays, there has been an intense worldwide scientific and technological interest in the area of metal/oxide and oxide/semiconductor interfaces. Defects existing in these emerging materials play an important role in device operation, so their use in nano-semiconductor technology can be seriously endangered. Despite the great effort carried out in the last years, the nature and formation of these defects are not well known yet, so the study of defects is a primary concern to be able to apply techniques which can minimize them. Since electrically active defects are atomic configurations which give rise to electronic sates, developing an atomic-scale understanding of defects is mandatory. Another topic of great interest is the current mechanism observed on high-k materials. The correlation between conduction mechanisms, defect location, and preferential energy values provides very relevant information about the very nature of defects and how these defects could be removed or diminished.

In this work we show the application of the standard techniques, as well as the new ones, which we have developed, for the electrical characterization of thin high-k layer-based metal-insulator-semiconductor (MIS) and metal-insulator-metal (MIM) structures. All of them constitute a complete suite of experimental techniques to carry out an in-depth study of conventional and incoming high-k based devices. In Fig. 1 a schematic of the electrical characterization of CMOS devices is shown. As an illustration, Figs. 2(a) and (b) show some results of electrical characterization of MIM structures for ReRAM devices. A whole discussion of the use of these techniques will be given during the conference.

[1] D. Panda, and T.-Y. Tseng, Thin Solid Films 531, 1 (2013).

[2] J. A. Kittl, K. Opsomer, M. Popovici, N. Menou, et al. Microel. Engin. 86, 1789 (2009).

[3] J.-S. Jung, S.-K. Lee, C.-S. Hong, J.-H. Shin, J.-M. Kim, and J.-G. Kang, Thin Solid Films
589, 831 (2015).

[4] S. Duenas, H. Castán, H. García, and L. Bailón, in Dielectric Materials, M. A. Silaghi, ed. InTech, ISBN: 978-953-51-0764-4, pp. 213-250 (2012).

[5] J. Park, S. Jung, W. Lee, S. Kim, J. Shin, D. Lee, J. Woo, and H. Hwang, IEEE Electron Device Lett. 33, 646 (2012)

[6] A. Fantini, L. Goux, R. Degraeve, D. J. Wouters, N. Raghavan, G. Kar, A. Belmonte, Y.Y. Chen, B. Govoreanu, and M. Jurczak, in Proc. IMW, pp. 30-33 (2013).

Figure 1