Efficient Chip-cooling using Embedded Biomimetic Microfluidics
Authors: Erp Remco van , Fahrni Malik , de Troya Miguel Salazar , Boutsikakis Athanasios , Soutter Emile , Francescon Andrea , Coen Florent-Valery , Doytchinov Iordan , siddiqui Ali , Tomar Saurabh , Ramakrishnan Bharath , Turner Cam , Alissa Husam , Raniwala Ashish , Warrier Brijesh , Bianchini Ricardo , Kleewein Jim , Bilgin Selim , Belady Christian 
Published: January 2025

Power dissipation in the latest accelerator chips for artificial intelligence has exceeded 1 kW and is increasing with each successive generation, while simultaneously introducing new thermal resistances and spatially varying temperature requirements due to heterogeneous integration. In contrast, cooling design has remained largely homogeneous, relying predominantly on straight channels or arrays of fins which are not tailored to the underlying chip. As data center operators target to increase coolant supply temperatures of data centers to reduce electricity and water consumption, more power needs to be extracted from increasingly complex chips with reduced temperature differentials between the junction and coolant. Hence, cooling is becoming the main driver for both chip performance and data center efficiency. Microfluidic cooling, with coolant directly flowing through channels embedded inside the silicon chip, has been proposed as a candidate to overcome the performance limitations of standard cold plates, as it aims to minimize thermal resistance by eliminating interfaces between the chip and the coolant. In addition, the close coupling between the heat source and cooling, combined with mature silicon-based microfabrication methods, enables more design freedom for cooling structures beyond straight channels and fins. However, while prior demonstrations of microfluidic cooling on function integrated circuits have shown the feasibility of this cooling integration, they suffered from high pressure drops, large temperature gradients and localized hot-spots, in addition to packaging and integration concerns. In this work, we show that the chip-level spatial power distribution is the source of these discrepancies, and that microfluidic topology optimization can simultaneously address the temperature and pressure drop challenges with microfluidic cooling, by creating a hierarchical network of channels that balance heat transfer and pressure drop mimicking the arteries, veins and capillaries in the circulatory system. Our result demonstrates that, by utilized a bio-inspired chip-aware microfluidic cooling architecture, up to 18 ⁰C reduction in hot-spot temperature rise on functional CPUs can be achieved, or a reduction in pressure drop by over 67% compared to a canonical design of pin fins. We demonstrate a 3x reduction in core temperature spread versus unoptimized designs, and furthermore observe that average thermal resistance can be reduced by up to 55% compared to standard cold plate cooling. These results validate that including microfluidic cooling as an integral part of the chip design process may be a viable path to allow for a further extension of the roadmap of silicon CMOS chips with increasing power levels, while simultaneously addressing the sustainability concerns at the data center scale.