bluuebunny/crossref_metadata_2025 huggingface dataset:
PREPARATION AND ELECTROCHEMICAL PROPERTIES OF NANOSTRUCTURED Li0.8CoO2
Authors: LENG YONGHUA , LI XINGGUO , YANG HUAQUAN , ZHOU HENGHUI
Published: October 2006

Submicron Li 0.8 CoO 2 particles were prepared by sol–gel method, and then ball-mill grinding method was adopted to make nanosized Li 0.8 CoO 2 powders. The two kinds of powders were then examined by X-ray diffraction (XRD), ICP (inductively coupled plasma), the multi-point BET (Brunauer, Emmett and Teller) and transmission electron micrographs (TEM). It appeared that the Li 0.8 CoO 2 nanoparticles exhibited quite different electrochemical properties, such as higher open-circuit voltage and lower discharge capacity, compared to submicron Li 0.8 CoO 2 particles.
SYNTHESIS AND CHARACTERIZATION OF POLY(BUTYL ACRYLATE-CO-METHYL METHACRYLATE)/CLAY NANOCOMPOSITES VIA EMULSION POLYMERIZATION
Authors: ZHANG ZHIYI , ZHAO NING , WEI WEI , WU DONG , SUN YUHAN
Published: October 2006

Poly(butyl acrylate-co-methyl methacrylate)/clay nanocomposites were synthesized via emulsion polymerization with an emulsifier (sodium dodecyl benzene sulfonate, SDBS), an initiator (ammonium persulate, APS), acrylic acid ester monomer and Na -montmorillonite. It was found that the addition of SDBS and water widened the gap between clay layers and facilitated monomers to penetrate into clay. Through initiator, comonomers were polymerized in the montmorillonite galleries. The structure of extracted nanocomposites was confirmed by XRD, transmission electron microscopy (TEM). Their thermal property and molecule weight were investigated by differential scanning calorimetry (DSC) and gel-penetrate chromatogram (GPC).
PREPARATION OF WATER-BASED INDIUM TIN OXIDE SOL SOLUTION FOR NEAR-IR REFLECTIVE FILM
Authors: KANG HYO SIM , KANG YOUNG SOO
Published: October 2006

Indium tin oxide (ITO) nanoparticles with In/Sn = 9:1 (at.%) were synthesized by chemical coprecipitation method in an aqueous solution. The coprecipitate prepared at room temperature showed the crystal structure of indium oxide in X-ray diffraction when it was annealed at the temperature above 300°C under air atmosphere. Reduction process was accomplished to improve the electrical property of ITO powder and it changed powder color from yellow to dark green. Green ITO powder with particle sizes in the range of 15–30 nm was well dispersed by an addition of polyvinylpyrrolidone in an aqueous solution. The dispersibility of ITO sol solution was detected with ζ-potential analyzer. Near-IR reflective film was prepared by spin coating method using ITO sol solution. Transmission electron microsopy (TEM) and energy dispersive X-ray spectrometer (EDS) were used to characterize morphology and composition of ITO nanoparticles. Near-IR (NIR) spectrometer was used to determine reflectance on the surface of ITO film in the NIR-radiation region.
Age constraints for the thermal evolution and erosional history of the central European Variscan belt: new data from the sediments and basement of the Carboniferous foreland basin in western Poland
Authors: Mazur StanisŁaw , Dunlap W.James , Turniak Krzysztof , Oberc-Dziedzic Teresa
Published: October 2006

Three Carboniferous-age detrital muscovites from the Variscan foreland basin of SW Poland and two muscovites from phyllites underlying the basement have been dated by the
40
Ar/
39
Ar step-heating and single-crystal laser fusion method.
40
Ar/
39
Ar analysis of the detrital micas defines step-heating preferred ages of 370.7 ± 1.4, 363.0 ± 1.9 and 355.0 ± 1.3 Ma. Single-crystal laser fusion data indicate little dispersion for the first of three samples, with an integrated age that closely matches the step-heating data, but the latter two describe inhomogeneous populations. The white mica concentrate from one phyllite yields a step-heating preferred age of 358.6 ± 1.8 Ma. The second phyllite sample displays an incremental discordant apparent age spectrum representing a mixture of white mica grains of varying ages. Our most important finding is that the Variscan foreland basin was supplied by source rocks that were exhumed and cooled in the Late Devonian, probably as a result of an early Variscan collisional event, previously largely undocumented. Although accessible exposures of the Variscan basement in SW Poland exhibit only a minor component of rocks exhumed before the Carboniferous, our work suggests that large tracts of rocks with a Devonian cooling signature are preserved at depth beneath the foreland basin.
Hands-on, simulated, and remote laboratories
Authors: Ma Jing , Nickerson Jeffrey V.
Published: October 2006

Laboratory-based courses play a critical role in scientific education. Automation is changing the nature of these laboratories, and there is a long-running debate about the value of hands-on versus simulated laboratories. In addition, the introduction of remote laboratories adds a third category to the debate. Through a review of the literature related to these labs in education, the authors draw several conclusions about the state of current research. The debate over different technologies is confounded by the use of different educational objectives as criteria for judging the laboratories: Hands-on advocates emphasize design skills, while remote lab advocates focus on conceptual understanding. We observe that the boundaries among the three labs are blurred in the sense that most laboratories are mediated by computers, and that the psychology of presence may be as important as technology. We also discuss areas for future research.
Interview with Danny Hillis
Authors: Lee Newton , Hillis Danny
Published: October 2006

Dr. Danny Hillis is cofounder, chairman and Chief Technology Officer of Applied Minds. A former vice president of research and development at The Walt Disney Company and the first Disney Fellow, Danny has designed some of the fastest computers in the world and pioneered the concept of parallel computers, now the basis for most supercomputers, as well as the RAID disk array technology used to store large databases. Danny is also the designer of a 10,000-year mechanical clock and the author of "The Pattern On The Stone: The Simple Ideas That Make Computers Work." In the video interview, you will hear Danny's answers to the following questions:1. The Cray-1 supercomputer was used to create the visual effects in the 1982 movie "Tron," but it was very expensive. How do you see the future use of supercomputers in moviemaking?2. When you were at Disney, you invented a full sized walking robot dinosaur. What was the creative process behind it?3. You created a computer composed of 10,000 Tinker Toys that could play tic-tac-toe. Do you consider it a great example of edutainment combining education and entertainment?4. How do you see the future of entertainment technology?5. You are the designer of the 10,000-year mechanical clock for the Long Now Foundation. What is the purpose of the clock and the Foundation?6. What are some the most exciting projects that you are working on at Applied Minds?
How computer gamers experience the game situation
Authors: Clarke Delwin , Duimering P. Robert
Published: October 2006

Very little is known about computer gamers' playing experience. Most social scientific research has treated gaming as an undifferentiated activity associated with various factors outside the gaming context. This article considers computer games as behavior settings worthy of social scientific investigation in their own right and contributes to a better understanding of computer gaming as a complex, context-dependent, goal-directed activity. The results of an exploratory interview-based study of computer gaming within the "first-person shooter" (FPS) game genre are reported. FPS gaming is a fast-paced form of goal-directed activity that takes place in complex, dynamic behavioral environments where players must quickly make sense of changes in their immediate situation and respond with appropriate actions. Gamers' perceptions and evaluations of various aspects of the FPS gaming situation are documented, including positive and negative aspects of game interfaces, map environments, weapons, computer-generated game characters (bots), multiplayer gaming on local area networks (LANs) or the internet, and single player gaming. The results provide insights into the structure of gamers' mental models of the FPS genre by identifying salient categories of their FPS gaming experience. It is proposed that aspects of FPS games most salient to gamers were those perceived to be most behaviorally relevant to goal attainment, and that the evaluation of various situational stimuli depended on the extent to which they were perceived either to support or to hinder goal attainment. Implications for the design of FPS games that players experience as challenging, interesting, and fun are discussed.
Rokkatan
Authors: Müller Jens , GORLATCH SERGEI
Published: October 2006

While massively multiplayer online role-playing games (MMORPG) involve large numbers of simultaneous players, two other popular game classes -- first-person shooter (FPS) and real-time strategy (RTS) games - are still only rarely considered for massively multiplayer gaming. A main technical problem for scaling these genres to be massively multiplayer is the absence of a suitable scalable multiserver networking approach. While the commonly used zoning concept performs well for an MMORPG, it is barely suitable for RTS and FPS games. As a scalable networking alternative for these genres, this article summarizes our work on the proxy-server architecture, which uses multiple servers for a single game session and implements a full replication of the game state at all proxies. We present our work on the game Rokkatan, our online evaluator game which enables massively multiplayer real-time strategy gaming using our proxy-server network architecture. We discuss the implementation of Rokkatan and analyze the distributed computation of the proxy-server approach by integrating an analytical scalability model into Rokkatan. Our experimental game sessions demonstrate high scalability of Rokkatan, which allows several hundreds of users to participate in a single, fast-paced game session.
Call for papers
Authors: Lee Newton
Published: October 2006

Selected papers published in this conference will be considered for publication in ACM Computers in Entertainment
Call for papers
Authors: Lee Newton
Published: October 2006

A two-day event of lectures, research, tutorials and exhibitions on Computer Games Research and Development
Statistical sampling of microarchitecture simulation
Authors: Wunderlich Roland E. , Wenisch Thomas F. , Falsafi Babak , Hoe James C.
Published: October 2006

Current software-based microarchitecture simulators are many orders of magnitude slower than the hardware they simulate. Hence, most microarchitecture design studies draw their conclusions from drastically truncated benchmark simulations that are often inaccurate and misleading. This article presents the Sampling Microarchitecture Simulation (SMARTS) framework as an approach to enable fast and accurate performance measurements of full-length benchmarks. SMARTS accelerates simulation by selectively measuring in detail only an appropriate benchmark subset. SMARTS prescribes a statistically sound procedure for configuring a systematic sampling simulation run to achieve a desired quantifiable confidence in estimates.Analysis of the SPEC CPU2000 benchmark suite shows that CPI and energy per instruction (EPI) can be estimated to within ±3% with 99.7% confidence by measuring fewer than 50 million instructions per benchmark. In practice, inaccuracy in microarchitectural state initialization introduces an additional uncertainty which we empirically bound to ∼2% for the tested benchmarks. Our implementation of SMARTS achieves an actual average error of only 0.64% on CPI and 0.59% on EPI for the tested benchmarks, running with average speedups of 35 and 60 over detailed simulation of 8-way and 16-way out-of-order processors, respectively.
On the efficiency of RESTART for multidimensional state systems
Authors: Villén-Altamirano Manuel , Villén-Altamirano José
Published: October 2006

RESTART (Repetitive Simulation Trials After Reaching Thresholds) is a widely applicable accelerated simulation technique that allows the evaluation of extremely low probabilities. The focus of this article is on providing guidelines for achieving a high efficiency in a simulation with RESTART. Emphasis is placed on the choice of the importance function, that is, the function of the system state for determining when retrials are made. A heuristic approach which is shown to be effective for some systems is proposed for this choice. A two-queue tandem network is used to illustrate the efficiency achieved following these guidelines. The importance function chosen in this example shows that an appropriate choice of the importance function leads to an efficient simulation of a system with multidimensional state space. Also presented are sufficient conditions for achieving asymptotic efficiency, and it is shown that they are not very restrictive in RESTART simulation.
Making a case for split data caches for embedded applications
Authors: Naz Afrin , Kavi Krishna , Rezaei Mehran , Li Wentong
Published: October 2006

In this paper we show that cache memories for embedded applications can be designed to increase performance while reduce area and energy consumed. Previously we have shown that separating data cache into an array cache and a scalar cache can lead to significant performance improvements for scientific benchmarks. In this paper we show that such a split data cache can also benefit embedded applications. To further improve the split cache organization, we augment the scalar cache with a small victim cache and the array cache with a small stream buffer. This "integrated" cache organization can lead to 43% reduction in the overall cache size, 37% reduction in access time and a 63% reduction in power consumption when compared to a unified 2-way set associative data cache for media benchmarks from MiBench suite.
Memory bandwidth optimization through stream descriptors
Authors: López-Lagunas Abelardo , Chai Sek M.
Published: October 2006

The memory subsystem for computer vision and image processing applications must sustain high memory bandwidth to keep processors busy. This paper advocates the use of stream descriptors, a mechanism that allows programmers to indicate data movement explicitly. Stream descriptors enable the compiler to organize memory transfers more efficiently by matching data movement to the capabilities of the underlying hardware. Stream descriptors are used in this paper on an image sensor interface to describe the deterministic movements of objects in segmented image regions. The paper shows how stream descriptors reduce the bandwidth requirements for a set of computer vision applications.
Internet nuggets
Authors: Thorson Mark
Published: October 2006

This column consists of selected traffic from the
comp.arch
newsgroup, a forum for discussion of computer architecture on the Internet---an international computer network.
Extending object database interfaces with fuzziness through aspect-oriented design
Authors: Sicilia Miguel-Ángel , García-Barriocanal Elena
Published: October 2006

Fuzzy logic has been used yet for extending database models to deal with vagueness in the definitions of linguistic concepts as "tall" or "long". However, the extension of existing programming interfaces for fuzziness requires a proper modularization of the underlying concerns of numerical imprecision handling. Such modularization should not interfere with existing programming practices, and they should not obscure the original design. Aspect-oriented design (AOD) enables such form of non-intrusive extensions to be added to existing software libraries. In this paper, the main design and implementation issues of such AOD-based extensions on OJB database libraries are briefly sketched.
Report from the First and Second International Workshops on Information Quality in Information Systems
Authors: Scannapieco Monica , Berti-Équille Laure
Published: October 2006

This report summarizes the constructive discussions of the first two editions of the International Workshop on Information Quality in Information Systems, IQIS 2004 and IQIS 2005, held respectively in Paris, France, on June 13, 2004 and in Baltimore, MD, USA, on June 17, 2005.
What’s on your hard drive?
Authors: O'Hanlon Charlene
Published: October 2006

This month brings to light a new issue—the upgrade.
The Future of Human-Computer Interaction
Authors: Canny John
Published: October 2006

Personal computing launched with the IBM PC. But popular computing—computing for the masses—launched with the modern WIMP (windows, icons, mouse, pointer) interface, which made computers usable by ordinary people. As popular computing has grown, the role of HCI (human-computer interaction) has increased. Most software today is interactive, and code related to the interface is more than half of all code. HCI also has a key role in application design. In a consumer market, a product’s success depends on each user’s experience with it. Unfortunately, great engineering on the back end will be undone by a poor interface, and a good UI can carry a product in spite of weaknesses inside.
Interface surfaces for protein-protein complexes
Authors: Ban Yih-En Andrew , Edelsbrunner Herbert , Rudolph Johannes
Published: October 2006

Protein-protein interactions, which form the basis for most cellular processes, result in the formation of protein interfaces. Believing that the local shape of proteins is crucial, we take a geometric approach and present a definition of an interface surface formed by two or more proteins as a subset of their Voronoi diagram. The definition deals with the difficult and important problem of specifying interface boundaries by invoking methods used in the alpha shape representation of molecules, the discrete flow on Delaunay simplices to define pockets and reconstruct surfaces, and the assessment of the importance of topological features. We present an algorithm to construct the surface and define a hierarchy that distinguishes core and peripheral regions. This hierarchy is shown to have correlation with hot-spots in protein-protein interactions. Finally, we study the geometric and topological properties of interface surfaces and show their high degree of contortion.
Design space exploration for 3D architectures
Authors: Xie Yuan , Loh Gabriel H. , Black Bryan , Bernstein Kerry
Published: October 2006

As technology scales, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. Increasing interconnect costs make it necessary to consider alternate ways of building modern microprocessors. One promising option is 3D architectures where a stack of multiple device layers with direct vertical tunneling through them are put together on the same chip. As fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques is imperative to explore the design space to 3D microarchitectures. In this article, we give a brief introduction to 3D integration technology, discuss the EDA design tools that can enable the adoption of 3D ICs, and present the implementation of various microprocessor components using 3D technology. An industrial case study is presented as an initial attempt to design 3D microarchitectures.
iVIBRATE
Authors: Chen Keke , Liu Ling
Published: October 2006

With continued advances in communication network technology and sensing technology, there is astounding growth in the amount of data produced and made available through cyberspace. Efficient and high-quality clustering of large datasets continues to be one of the most important problems in large-scale data analysis. A commonly used methodology for cluster analysis on large datasets is the three-phase framework of sampling/summarization, iterative cluster analysis, and disk-labeling. There are three known problems with this framework which demand effective solutions. The first problem is how to effectively define and validate irregularly shaped clusters, especially in large datasets. Automated algorithms and statistical methods are typically not effective in handling these particular clusters. The second problem is how to effectively label the entire data on disk (disk-labeling) without introducing additional errors, including the solutions for dealing with outliers, irregular clusters, and cluster boundary extension. The third obstacle is the lack of research about issues related to effectively integrating the three phases. In this article, we describe iVIBRATE---an interactive visualization-based three-phase framework for clustering large datasets. The two main components of iVIBRATE are its VISTA visual cluster-rendering subsystem which invites human interplay into the large-scale iterative clustering process through interactive visualization, and its adaptive ClusterMap labeling subsystem which offers visualization-guided disk-labeling solutions that are effective in dealing with outliers, irregular clusters, and cluster boundary extension. Another important contribution of iVIBRATE development is the identification of the special issues presented in integrating the two components and the sampling approach into a coherent framework, as well as the solutions for improving the reliability of the framework and for minimizing the amount of errors generated within the cluster analysis process. We study the effectiveness of the iVIBRATE framework through a walkthrough example dataset of a million records and we experimentally evaluate the iVIBRATE approach using both real-life and synthetic datasets. Our results show that iVIBRATE can efficiently involve the user in the clustering process and generate high-quality clustering results for large datasets.
Soft concurrent constraint programming
Authors: Bistarelli Stefano , Montanari Ugo , Rossi Francesca
Published: October 2006

Soft constraints extend classical constraints to represent multiple consistency levels, and thus provide a way to express preferences, fuzziness, and uncertainty. While there are many soft constraint solving formalisms, even distributed ones, as yet there seems to be no concurrent programming framework where soft constraints can be handled. In this article we show how the classical concurrent constraint (cc) programming framework can work with soft constraints, and we also propose an extension of cc languages which can use soft constraints to prune and direct the search for a solution. We believe that this new programming paradigm, called
soft cc
(scc), can be also very useful in many Web-related scenarios. In fact, the language level allows Web agents to express their interaction and negotiation protocols, and also to post their requests in terms of preferences, and the underlying soft constraint solver can find an agreement among the agents even if their requests are incompatible.
Behavior-based modeling and its application to Email analysis
Authors: Stolfo Salvatore J. , Hershkop Shlomo , Hu Chia-Wei , Li Wei-Jen , Nimeskern Olivier , Wang Ke
Published: October 2006

The Email Mining Toolkit (EMT) is a data mining system that computes
behavior profiles or models
of user email accounts. These models may be used for a multitude of tasks including forensic analyses and detection tasks of value to law enforcement and intelligence agencies, as well for as other typical tasks such as virus and spam detection. To demonstrate the power of the methods, we focus on the application of these models to detect the early onset of a viral propagation without “content-base ” (or signature-based) analysis in common use in virus scanners. We present several experiments using real email from 15 users with injected simulated viral emails and describe how the combination of different behavior models improves overall detection rates. The performance results vary depending upon parameter settings, approaching 99 % true positive (TP) (percentage of viral emails caught) in general cases and with 0.38 % false positive (FP) (percentage of emails with attachments that are mislabeled as viral). The models used for this study are based upon volume and velocity statistics of a user's email rate and an analysis of the user's (social)
cliques
revealed in the person's email behavior. We show by way of simulation that virus propagations are detectable since viruses may emit emails at rates different than human behavior suggests is normal, and email is directed to groups of recipients in ways that violate the users' typical communications with their social groups.
Authentication and integrity in outsourced databases
Authors: Mykletun Einar , Narasimha Maithili , Tsudik Gene
Published: October 2006

In the Outsourced Database (ODB) model, entities outsource their data management needs to a third-party service provider. Such a service provider offers mechanisms for its clients to create, store, update, and access (query) their databases. This work provides mechanisms to ensure data integrity and authenticity for outsourced databases. Specifically, this article provides mechanisms that assure the querier that the query results have not been tampered with and are authentic (with respect to the actual data owner). It investigates both the security and efficiency aspects of the problem and constructs several secure and practical schemes that facilitate the integrity and authenticity of query replies while incurring low computational and communication costs.
Memory Model = Instruction Reordering + Store Atomicity
Authors: Arvind Arvind , Maessen Jan-Willem
Published: October 2006

We present a novel framework for defining memory models in terms of two properties: thread-local Instruction Reordering axioms and Store Atomicity, which describes inter-thread communication via memory. Most memory models have the store atomicity property, and it is this property that is enforced by cache coherence protocols. A memory model with Store Atomicity is serializable; there is a unique global interleaving of all operations which respects the reordering rules. Our framework uses partially ordered execution graphs; one graph represents many instruction interleavings with identical behaviors. The major contribution of this framework is a procedure for enumerating program behaviors in any memory model with Store Atomicity. Using this framework, we show that address aliasing speculation introduces new program behaviors; we argue that these new behaviors should be permitted by the memory model specification. We also show how to extend our model to capture the behavior of non-atomic memory models such as SPARC R TSO.
Conditional Memory Ordering
Authors: von Praun Christoph , Cain Harold W. , Choi Jong-Deok , Ryu Kyung Dong
Published: October 2006

Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by executing a memory barrier instruction, ensuring that recent writes have been ordered with respect to other processors in the system. We show that this model leads to superfluous memory barriers in programs with acquire-release style synchronization, and present a combined hardware/software synchronization mechanism called conditional memory ordering (CMO) that reduces memory ordering overhead. CMO is demonstrated on a lock algorithm that identifies those dynamic lock/unlock operations for which memory ordering is unnecessary, and speculatively omits the associated memory ordering instructions. When ordering is required, this algorithm relies on a hardware mechanism for initiating a memory ordering operation on another processor. Based on evaluation using a software-only CMO prototype, we show that CMO avoids memory ordering operations for the vast majority of dynamic acquire and release operations across a set of multithreaded Java workloads, leading to significant speedups for many. However, performance improvements in the software prototype are hindered by the high cost of remote memory ordering. Using empirical data, we construct an analytical model demonstrating the benefits of a combined hardware-software implementation.
Architectural Semantics for Practical Transactional Memory
Authors: McDonald Austen , Chung JaeWoong , Carlstrom Brian D. , Minh Chi Cao , Chafi Hassan , Kozyrakis Christos , Olukotun Kunle
Published: October 2006

Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional state buffering and conflict resolution. Missing is a robust hardware/software interface, not limited to simplistic instructions defining transaction boundaries. Without rich semantics, current TM systems cannot support basic features of modern programming languages and operating systems such as transparent library calls, conditional synchronization, system calls, I/O, and runtime exceptions. This paper presents a comprehensive instruction set architecture (ISA) for TM systems. Our proposal introduces three key mechanisms: two-phase commit; support for software handlers on commit, violation, and abort; and full support for open- and closed-nested transactions with independent rollback. These mechanisms provide a flexible interface to implement programming language and operating system functionality. We also show that these mechanisms are practical to implement at the ISA and microarchitecture level for various TM systems. Using an execution-driven simulation, we demonstrate both the functionality (e.g., I/O and conditional scheduling within transactions) and performance potential (2.2× improvement for SPECjbb2000) of the proposed mechanisms. Overall, this paper establishes a rich and efficient interface to foster both hardware and software research on transactional memory.
Multiple Instruction Stream Processor
Authors: Hankins Richard A. , Chinya Gautham N. , Collins Jamison D. , Wang Perry H. , Rakvic Ryan , Wang Hong , Shen John P.
Published: October 2006

Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallelism in the software. To support this trend, we present a novel processor architecture called the Multiple Instruction Stream Processing (MISP) architecture. MISP introduces the sequencer as a new category of architectural resource, and defines a canonical set of instructions to support user-level inter-sequencer signaling and asynchronous control transfer. MISP allows an application program to directly manage user-level threads without OS intervention. By supporting the classic cache-coherent shared-memory programming model, MISP does not require a radical shift in the multithreaded programming paradigm. This paper describes the design and evaluation of the MISP architecture for the IA-32 family of microprocessors. Using a research prototype MISP processor built on an IA-32-based multiprocessor system equipped with special firmware, we demonstrate the feasibility of implementing the MISP architecture. We then examine the utility of MISP by (1) assessing the key architectural tradeoffs of the MISP architecture design and (2) showing how legacy multithreaded applications can be migrated to MISP with relative ease.
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Authors: Li Feihui , Nicopoulos Chrysostomos , Richardson Thomas , Xie Yuan , Narayanan Vijaykrishnan , Kandemir Mahmut
Published: October 2006

Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the current trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this paper is to study the challenges for L2 design and management in 3D chip multiprocessors. Our first contribution is to propose a router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory. Our second contribution is to demonstrate, through extensive experiments, that a 3D L2 memory architecture generates much better results than the conventional two-dimensional (2D) designs under different number of layers and vertical (inter-wafer) connections. In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration. This also helps reduce power consumption in L2 due to a reduced number of data movements.
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Authors: Yan Chenyu , Englender Daniel , Prvulovic Milos , Rogers Brian , Solihin Yan
Published: October 2006

Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encryption/authentication scheme. Our new split counters for counter-mode encryption simultaneously eliminate counter overflow problems and reduce per-block counter size, and we also dramatically improve authentication performance and security by using the Galois/Counter Mode of operation (GCM), which leverages counter-mode encryption to reduce authentication latency and overlap it with memory accesses. Our results indicate that the split-counter scheme has a negligible overhead even with a small (32KB) counter cache and using only eight counter bits per data block. The combined encryption/authentication scheme has an IPC overhead of 5% on average across SPEC CPU 2000 benchmarks, which is a significant improvement over the 20% overhead of existing encryption/authentication schemes.
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Authors: Colohan Christopher B. , Ailamaki Anastassia , Steffan J. Gregory , Mowry Todd C.
Published: October 2006

Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range in size from hundreds to several thousand dynamic instructions and have minimal dependences between them. Recent work has shown that TLS can offer compelling performance improvements for database workloads, but only when targeting much larger speculative threads of more than 50,000 dynamic instructions per thread, with many frequent data dependences between them. To support such large and dependent speculative threads, hardware must be able to buffer the additional speculative state, and must also address the more challenging problem of tolerating the resulting cross-thread data dependences In this paper we present hardware support for large speculative threads that integrates several previous proposals for TLS hardware. We also introduce support for subthreads: a mechanism for tolerating cross-thread data dependences by checkpointing speculative execution. When speculation fails due to a violated data dependence, with sub-threads the failed thread need only rewind to the checkpoint of the appropriate sub-thread rather than rewinding to the start of execution; this significantly reduces the cost of mis-speculation. We evaluate our hardware support for large and dependent speculative threads in the database domain and find that the transaction response time for three of the five transactions from TPC-C (on a simulated 4- processor chip-multiprocessor) speedup by a factor of 1.9 to 2.9.
Quantum Memory Hierarchies
Authors: Thaker Darshan D. , Metodi Tzvetan S. , Cross Andrew W. , Chuang Isaac L. , Chong Frederic T.
Published: October 2006

The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems.
Bipartite roots of graphs
Authors: Lau Lap Chi
Published: October 2006

Graph
H
is a root of graph
G
if there exists a positive integer
k
such that
x
and
y
are adjacent in
G
if and only if their distance in
H
is at most
k
. Motwani and Sudan [1994] proved the NP-completeness of graph square recognition and conjectured that it is also NP-complete to recognize squares of bipartite graphs. The main result of this article is to show that squares of bipartite graphs can be recognized in polynomial time. In fact, we give a polynomial-time algorithm to count the number of different bipartite square roots of a graph, although this number could be exponential in the size of the input graph. By using the ideas developed, we are able to give a new and simpler linear-time algorithm to recognize squares of trees and a new algorithmic proof that tree square roots are unique up to isomorphism. Finally, we prove the NP-completeness of recognizing cubes of bipartite graphs.
Perspectives for cryptographic long-term security
Authors: Buchmann Johannes , May Alexander , Vollmer Ulrich
Published: October 2006

Cryptographic long-term security is needed, but difficult to achieve. Use flexible cryptographic tools, and have replacements ready.
Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms
Authors: Ou Jingzhao , Prasanna Viktor K.
Published: October 2006

Configurable multiprocessor platforms consist of multiple soft processors configured on FPGA devices. They have become an attractive choice for implementing many computing applications. In addition to the various ways of distributing software execution among the multiple soft processors, the application designer can customize soft processors and the connections between them in order to improve the performance of the applications running on the multiprocessor platform. State-of-the-art design tools rely on low-level simulation to explore the various design trade-offs offered by configurable multiprocessor platforms. These low-level simulation based exploration techniques are too time-consuming and can be a major bottleneck to efficient design space exploration on these platforms. We propose a design space exploration technique for configurable multiprocessor platforms using arithmetic-level cycle-accurate hardware--software cosimulation. Arithmetic-level abstractions of the hardware and software execution platforms are created within the proposed cosimulation environment. The configurable multiprocessor platforms are described using these arithmetic-level abstractions. Hardware and software simulators are tightly integrated to concurrently simulate the arithmetic behavior of the multiprocessor platform. The simulation within the integrated simulators are synchronized to provide cycle-accurate simulation results for the complete multiprocessor platform. By doing so, we significantly speed up the cosimulation process for configurable multiprocessor platforms. Exploration of the various hardware-software design trade-offs provided by configurable multiprocessor platforms can be performed within the proposed cycle-accurate cosimulation environment. After the final designs are identified, the corresponding low-level implementations with the desired cycle-accurate arithmetic behavior are generated automatically. For illustrative purposes, we provide an implementation of our approach based on MATLAB/Simulink. We show the cosimulation of two numerical computation applications and one image-processing application on a popular configurable multiprocessor platform within the MATLAB/Simulink-based cosimulation environment. For these three applications, our arithmetic-level cosimulation approach leads to speed-ups in simulation time of up to more than 800x compared with the low-level simulation approaches. The designs of these applications identified using our arithmetic-level cosimulation approach achieve execution time speed-ups up to 5.6x, compared with other designs considered in our experiments.
Enforcing efficient resource provisioning in peer-to-peer file sharing systems
Authors: Antoniadis Panayotis , Courcoubetis Costas
Published: October 2006

In this paper we focus on content availability as the main good provided by a p2p file sharing system and consider peer availability, the amount of time peers stay connected sharing their files, as their main contribution. We wish to study the effectiveness of incentive mechanisms which enforce contribution by somehow relating it with consumption. Towards this end, we propose a mechanism who wishes to regulate the time required for peers to stay on-line sharing their files by dictating a fixed upload throughput used by uploading peers and thus a certain average time for a download to finish. We formulate and analyze a suitable economic model focusing on peer availability in order to understand the role of this important system parameter and provide the means to efficiently tune it.
Battery power-aware encryption
Authors: Chandramouli R. , Bapatla S. , Subbalakshmi K. P. , Uma R. N.
Published: October 2006

Minimizing power consumption is crucial in battery power-limited secure wireless mobile networks. In this paper, we (a) introduce a hardware/software set-up to measure the battery power consumption of encryption algorithms through real-life experimentation, (b) based on the profiled data, propose mathematical models to capture the relationships between power consumption and security, and (c) formulate and solve security maximization subject to power constraints. Numerical results are presented to illustrate the gains that can be achieved in using solutions of the proposed security maximization problems subject to power constraints.
In VINI veritas
Authors: Bavier Andy , Feamster Nick , Huang Mark , Peterson Larry , Rexford Jennifer
Published: October 2006

This paper describes
VINI
, a virtual network infrastructure that allows network researchers to evaluate their protocols and services in a realistic environment that also provides a high degree of control over network conditions. VINI allows researchers to deploy and evaluate their ideas with real routing software, traffic loads, and network events. To provide researchers flexibility in designing their experiments, VINI supports simultaneous experiments with arbitrary network topologies on a shared physical infrastructure. This paper tackles the following important design question: What set of concepts and techniques facilitate flexible, realistic, and controlled experimentation (
e.g.
, multiple topologies and the ability to tweak routing algorithms) on a fixed physical infrastructure? We first present VINI's high-level design and the challenges of virtualizing a single network. We then present
PL-VINI
, an implementation of VINI on PlanetLab, running the "Internet In a Slice". Our evaluation of PL-VINI shows that it provides a realistic and controlled environment for evaluating new protocols and services.
Revisiting IP multicast
Authors: Ratnasamy Sylvia , Ermolinskiy Andrey , Shenker Scott
Published: October 2006

This paper revisits a much explored topic in networking - the search for a simple yet fully-general multicast design. The many years of research into multicast routing have led to a generally pessimistic view that the complexity of multicast routing-and inter-domain multicast routing in particular - can only be overcome by restricting the service model (as in single-source) multicast. This paper proposes a new approach to implementing IP multicast that we hope leads to a reevaluation of this commonly held view.
Interference-aware fair rate control in wireless sensor networks
Authors: Rangwala Sumit , Gummadi Ramakrishna , Govindan Ramesh , Psounis Konstantinos
Published: October 2006

In a wireless sensor network of N nodes transmitting data to a single base station, possibly over multiple hops, what distributed mechanisms should be implemented in order to dynamically allocate fair and efficient transmission rates to each node? Our interferenceaware fair rate control (IFRC) detects incipient congestion at a node by monitoring the average queue length, communicates congestion state to exactly the set of potential interferers using a novel low-overhead congestion sharing mechanism, and converges to a fair and efficient rate using an AIMD control law. We evaluate IFRC extensively on a 40-node wireless sensor network testbed. IFRC achieves a fair and efficient rate allocation that is within 20-40% of the optimal fair rate allocation on some network topologies. Its rate adaptation mechanism is highly effective: we did not observe a single instance of queue overflow in our many experiments. Finally, IFRC can be extended easily to support situations where only a subset of the nodes transmit, where the network has multiple base stations, or where nodes are assigned different transmission weights.
Capacity overprovisioning for networks with resilience requirements
Authors: Menth Michael , Martin Rüdiger , Charzinski Joachim
Published: October 2006

This work focuses on capacity overprovisioning (CO) as an alternative to admission control (AC) to implement quality of service (QoS) in packet-switched communication networks. CO prevents potential overload while AC protects the QoS of the traffic during overload situations. Overload may be caused, e. g., by uctuations of the traffic rate on a link due to its normal stochastic behavior (a), by traffic shifts within the network due to popular contents (b), or by redirected traffic due to network failures (c). Capacity dimensioning methods for CO need to take into account all potential sources of overload while AC can block excess traffic caused by (a) and (b) if the capacity does not suffice. The contributions of this paper are (1) the presentation of a capacity dimensioning method for networks with resilience requirements and changing traffic matrices, (2) the investigation of the impact of the mentioned sources of overload (a-c) on the required capacity for CO in networks with and without resilience requirements, and (3) a comparison of this equired capacity with the one for AC. Our results show that in the presence of strong traffic shifts CO requires more capacity than AC. However, if resilience against network failures is required, both CO and AC need additional backup capacity for the redirected traffic. In this case, CO can use the backup capacity to absorb other types of overload. As a consequence, CO and AC have similar bandwidth requirements. These findings are robust against the network size.
COPE
Authors: Wang Hao , Xie Haiyong , Qiu Lili , Yang Yang Richard , Zhang Yin , Greenberg Albert
Published: October 2006

Traffic engineering plays a critical role in determining the performance and reliability of a network. A major challenge in traffic engineering is how to cope with dynamic and unpredictable changes in traffic demand. In this paper, we propose COPE, a class of traffic engineering algorithms that optimize for the expected scenarios while providing a worst-case guarantee for unexpected scenarios. Using extensive evaluations based on real topologies and traffic traces, we show that COPE can achieve efficient resource utilization and avoid network congestion in a wide variety of scenarios.