bluuebunny/crossref_metadata_2025 huggingface dataset:
Identification of Root Cause Failure in Silicon on Insulator Body Contacted nFETs Using Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy
Authors: McMurray J.S. , Molella C.M.
Published: December 2020

Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.
Microstructure Analysis of Wafer Bump Nodule
Authors: Chen Xianfeng , Ge Tingfeng , Tsou Lisa , Li Ming , Niou Chorng , Kary Chien W.T.
Published: December 2020

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.
Root Cause Finding of a Diode Leakage Failure Using Scanning Magnetic Microscopy and ToF-SIMS as Key Methods
Authors: Preu H. , Mack W. , Kilger T. , Seidl B. , Walter J. , Alpern P. , Kirchberger M.
Published: December 2020

One challenge in failure analysis of microelectronic devices is the localization and root cause finding of leakage currents in passives. In this case study we present a successful approach for failure analysis of a diode leakage failure. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToFSIMS as key methods for localization and root cause identification. [1]
Case Studies in Atomic Force Probe Analysis
Authors: Mulder Randal , Subramanian Sam , Chrastecky Tony
Published: December 2020

The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.
Applications of Transmission Electron Microscopy and Secondary Ion Mass Spectrometry on Crystal Defect Analysis and Electronic Characterization of Advanced 512Mb DRAM
Authors: Lu Serena , Chen Esther , Huang Lang-Yu , Luo Jian-Shing , Russell Jeremy D.
Published: December 2020

The capabilities of analytical transmission electron microscopy (TEM), such as high spatial resolution, micro-chemical analysis, etc., have led to an increasingly essential role for TEM-based analysis in process development, defect identification, yield enhancement, and root-cause failure analysis with the dynamic random access memory (DRAM) industry. In this article, several examples are reported to carry out the applications of TEM and secondary ion mass spectrometry on crystal defect analysis and electronic characteristics of advanced 512 Mb DRAMs.
Advanced Manual Package Pulling System for Removing PCB Components in Preparation for Crack Area Measurement and Disbond Type Mapping
Authors: McDonald Todd R.
Published: December 2020

Existing tools used by industry to manually remove PCB components for disbond type mapping or crack area measurement present significant ergonomic and process quality concerns. The most common tool designs often cause damage to some of the solder joints on components during pull, and frequently, operators using these designs report safety concerns. This paper evaluates these concerns and proposes a design solution that eliminates them. With a manual T-handle pull tool system introduced here, there is no prying, lever or angular force applied to remove the component. The pull tool rotates using vertical threads to apply vertical removal force. It demonstrates a reduction in manual operator force by an average of 93% compared to the cam lobe lever design. Additionally, the pull tool reduces bending of pull bolts and angular pull direction that may interfere with availability and interpretation of subsequent disbond data.
Failure Analysis Navigation System Connecting Hardware Analysis to Software Diagnosis
Authors: Shimase Akira , Uchikado Akihito , Matsumoto Yoshikazu , Watarai Shinichi , Kawanabe Shinji , Suzuki Takeshi , Majima Toshiyuki , Hotta Kazuhiro , Terada Hirotoshi
Published: December 2020

In the failure analysis of semiconductors, layout analysis to pick up suspect nets is getting to be a time consuming work due to finer wiring pitch and multi-layer structure. This article proposes a failure analysis navigation system (FA-Navigation System), which can make it easier to extract the nets passing through the signals detected by the hardware analysis tool, such as emission microscopes or OBIRCH analysis tools. It introduces the functions of the system and shows some case studies in actual failure analyses. The IDDQ fault diagnosis is especially useful for case studies. The result of the software diagnosis can be loaded in the analysis window of the FA-navigation system, and the system correlates the result to the nets extracted by the hardware analysis and displays coincident nets in a sorted manner to make the failure analysis easier.
Usage of SAM on Fatigue Crack of Solder Joint Induced by Thermal Reliability Test
Authors: Chen Tung Hung , Shih T. I.
Published: December 2020

Thermal fatigue cracking of lead-free solder joints within flipchip packages was investigated in this study by using scanning acoustic microscope (SAM) and SEM. The distribution of substrate delaminations was mapped with SAM of high depth resolution and observed in cross-section with SEM to find the mechanism of crack growth during thermal reliability tests. The study revealed that the interfacial crack always initiated from the pad edge. This is attributed to the coefficient of thermal expansion (CTE) mismatch between underfill and the PCB substrate. The propagation of fatigue crack within solder joint is closely related to the morphology of interfacial/intergranular intermetallic compound (IMC) formed at the elevated temperature of thermal cycle.
Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor
Authors: Talacka Ray , Tendolkar Nandu , Paquette Cynthia
Published: December 2020

The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.
Buttons and Threads—Tailoring Defect Analysis
Authors: Gondran Carolyn F. H. , Paul Dennis F. , Das Sanjit K. , Foran Brendan J. , Clark Mark H.
Published: December 2020

A framework is presented for considering the relative strengths of Auger electron spectroscopy (AES)/scanning Auger microscopy (SAM) and scanning transmission electron microscopy–electron energy loss spectroscopy (STEM-EELS) when selecting a defect analysis technique. The geometry of the analysis volumes for each technique is visualized. The analysis volume for AES/SAM is shaped like a button while the STEM-EELS analysis volume is more like a thread extending throughout the thickness of the prepared sample. The usefulness of this framework is illustrated with the example of small defect particles. In this example the size and shape of the AES/SAM analysis volume is a better fit to the defect, thus it provides better chemical analysis while STEM provides better images of the defects.
Reduction of Acquisition Time for RIL, SDL, and LADA
Authors: Mels Arjan , Zachariasse Frank
Published: December 2020

Although RIL, SDL and LADA are slightly different, the main operating principle is the same and the theory for defect localization presented in this paper is applicable to all three methods. Throughout this paper the authors refer to LADA, as all experimental results in this paper were obtained with a 1064nm laser on defect free circuits. This paper first defines mathematically what 'signal strength' actually means in LADA and then demonstrates a statistical model of the LADA situation that explains the optimal conditions for signal collection and the parameters involved. The model is tested against experimental data and is also used to optimise the acquisition time. Through this model, equations were derived for the acquisition time needed to discern a LADA response from the background noise. The model offers a quantitative tool to estimate the feasibility of a given LADA measurement and a guide to optimising the required experimental set-up.
Challenges of Atomic Force Probe Characterization of Logic Based Embedded DRAM for On-Processor Applications
Authors: Kane Terence , Tenney Michael P. , Erickson Andrew , Phan Sebastien
Published: December 2020

Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.
Applications for Parallel Grinding as an Alternative to Chemical Decapsulation in Preparing Packaged Samples for Failure Analysis
Authors: Nail Carl
Published: December 2020

Acid etching of plastic packages can both remove key evidence and introduce artifacts on decapsulated samples. Parallel grinding offers a non-chemical option for removing package material that can minimize these risks. This technique was used successfully on three different types of failure analysis investigations. It also has potential for supporting the analysis of corrosion defects, though additional work is needed to confirm the utility of parallel grinding in this application.
Near-IR Photon Emission Spectroscopy on Strained and Unstrained 60 nm Silicon nMOSFETs
Authors: Tan S.L. , Toh K.H. , Isakov D. , Chan D.S.H. , Phang J.C.H. , Ang K.W. , Yeo Y.C. , Chua C.M. , Koh L.S.
Published: December 2020

Spectral analysis of near IR photon emissions was performed on unstrained as well as uniaxial tensile strained nMOSFETs with physical gate length of 60 nm. The significant differences in the observed spectra could be attributed to the strain-induced bandgap narrowing. This shows that photon emission spectroscopy could potentially be used as a tool to monitor strain in the nMOSFET channel.
Al Pad Corrosion Mechanism Study When Dicing Saw
Authors: Duan Shuqing , Li Ming , Yu Qinqin , Su Jie , Lin Sanpen , Niou Chorng , Chien W.T.Kary
Published: December 2020

The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.
Study of FBGA Burn Failure under THB Test
Authors: Zhou Jianwei , Zheng Wei , Lou Minyi , Feng Nufeng , Lee Jaisung , Lee Taekoo
Published: December 2020

Temperature humidity bias (THB) test is widely used to evaluate the moisture resistance of non-hermetic packages in semiconductor industry. During THB test, one kind of 90FBGA was found severely burned and the evidence has been completely destroyed. This brings a great challenge to failure analysis. In this paper, a double daisy chain structure substrate was designed to reproduce the short and burn failure. The substrate layout design, bias and high humidity environment were proved to be the three key factors inducing dendrite growth and burn failure. A “corner-missing” phenomenon inspected through nano-focus X-ray was reported and it could finally verify the theory of electrochemical migration. The countermeasure to prevent burn failure was proposed to the designers. The insulation property degradation due to THB test was evaluated.
A Simple Adapter for Soft Defect Localization Using OBIRCH
Authors: Kolasa Ted
Published: December 2020

Equipment manufacturers have developed peripherals for their tools that add soft defect localization (SDL) capability to existing optical beam tools, in many cases providing excellent results. However, these upgrades add significant cost to the tool. This paper presents the design considerations for a simple adapter that was developed in house to add SDL capability to optical beam induced resistance change (OBIRCH) tool, including resolution of some unexpected problems. This solution represents a simple, low cost method to add SDL testing capability to the OBIRCH tool and can also be used in conjunction with OBIC and XIVA tools with little or no modification. An early example of the SDL results provided by this adapter is also presented.
Construction of a 3-D Current Path Using Magnetic Current Imaging
Authors: Felt Frederick , Knauss Lee , Gilbertson Anders , Orozco Antonio
Published: December 2020

The need to miniaturize in the electronics industry is driving smaller form factors, and resulting in complex packaging innovations such as structures with multiple devices stacked inside a three dimensional package. These structures present a challenge for non-destructive fault isolation. Two such modules recently exhibited failures on the NASA Goddard Space Flight Center Solar Dynamic Observatory (SDO) during board-level testing. Each module consisted of eight vertically-stacked mini-boards, each mini-board with a single EEPROM microcircuit and capacitor, and connected by external gold metallization to module pins. Both failed modules exhibited low-resistance shorts between multiple pins. The orthogonal structure of the module prompted the use of magnetic current imaging (MCI) in three planes in order to construct an internal three-dimensional current path for each of the failed modules. Magnetic current imaging is able to “look through” non-magnetic, or de-gaussed packaging materials, allowing global imaging without physical deprocessing of the stacked EEPROM modules, in order to construct the internal current path and localize defects. To our knowledge, this is the first time that this has been done. Following global isolation of the defects, two types of magnetic sensors were used in parallel with limited deprocessing in order to more precisely characterize suspect failure locations before actually physically exposing the defects. This paper will show the process for using magnetic current imaging with both SQUID and magnetoresistive (GMR) sensors to isolate defects in two stacked EEPROM packages along with the final physical analysis of the defects. The failure analysis found that these devices were damaged by external heat, possibly during oven pre-conditioning or hot air soldering onto the board. The manufacturer, 3-D Plus, was not implicated in the failure.
Analysis of DC Failure in Advanced Memory Devices Using Nanoprobing and Scanning Capacitance Microscopy
Authors: Lue Jen-Lang , Lin Chin-Shun , Chiou Atup , Liao Hsuen-Cheng , Liu Hsienwen , Pai Brian , Fan Sam , Wang Tings
Published: December 2020

This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current-Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.
Localized Die Metallization Damage Induced During Laser-Marking of a Semiconductor Package
Authors: Parañal Paul Eric B.
Published: December 2020

This paper presents a new fail mechanism for laser-marking induced die damage. Discovered during package qualification, silica spheres – commonly used as fillers in the molding material, was shown to act as a propagation medium that promote the direct interaction of the scribing laser beam and the die surface. Critical to the understanding of the fail mechanism is the deprocessing technique devised to allow layer by layer examination of the metallization and passivation layers in an encapsulated silicon die. The technique also made possible the inspection of the molding compound profile directly on top of the affected die area.
BGA Package Level Failures Due to Contamination
Authors: Roepsch Jodi
Published: December 2020

Two instances of BGA package level failures were identified during in-circuit electrical test. The electrical opens occurred as a result of contamination issues originating at the board supplier. Analytical techniques including optical inspection, SEM/EDS, Raman and FTIR were key in identifying photoresist on the board surface in the first case study and nickel carbonate contamination on the board surface in the second case study. In the first case study, resolution was achieved with a Plasma etch process. In the second case study, CCAs were cleaned with a wet chemical etch process formulated specifically to attack the nickel carbonate.
Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices
Authors: Versen Martin , Diaconescu Dorina , Touzel Jerome
Published: December 2020

The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.
Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits
Authors: Shen Cha-Ming , Chang Yen-Long , Wen Lian-Fon , Chuang Tan-Chen , Lin Shi-Chen , Huang Chen-May , Chou Jin-Hong
Published: December 2020

Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.
Measurement of Bit Leakages in a Functional SRAM
Authors: Deng Xiaowei , Loh Wah Kit , Pious Beena , Raval Jayesh , Khan Bashar , Liu Larry , Lowry Taylor , Yoon DB , Houston Theodore W. , McKee Randy , Kasper Abha Singh , Corum Dan
Published: December 2020

A direct bit leakage measurement (DBLM) scheme is proposed and implemented in 8Mb and 32Mb SRAM’s in 45nm and 28nm technologies. It allows, for the first time, direct and nondestructive measurement of various defect induced leakages in each bit in a functional SRAM. It thus enables collection of various defect induced bit leakage data for low-cost and fast failure analysis. It also enables collection of massive bit leakage data for statistical evaluation and location sensitivity assessment.
The SRAM Soft Failure Analysis with SNM & TR Characterization by Nanoprobing in Sub 45nm
Authors: Hong Jakyung , Cho S.J. , Han Y.W. , Choi H.S. , Kim T.E. , Son S.J. , Kim H.S. , Kwon S.D. , Oh Y.S.
Published: December 2020

This paper presents the process of measuring static noise margin (SNM), write noise margin (WNM) with 6 pin nanoprober, and characterization and analysis of SRAM cell stability through case studies of 45nm devices SRAM soft failures. It highlights that the local mismatch in the bit cell caused by slight variations in the transistor characteristics, such as Vth shift and Idsat, off variation, also can easily induce a soft failure. The analysis of the SNM TR characteristic is successfully demonstrated through the case study of 45nm SRAM devices. The chapter explains SNM measurement in the metal layer and transistor measurements in the CA layer. Measuring the SNM TR's characteristics is an important methodology in understanding the stability of each bit cell and failure mechanism depending on voltage, defects, and other factors. The next generation of nanoprobing analysis can be expanded.
A Versatile Design of Solid Immersion Lenses in Bulk Silicon Using Focused Ion Beam Techniques
Authors: Scholz P. , Kerst U. , Boit C. , Tsao C.-C. , Lundquist T.
Published: December 2020

The topic of this work is the sequential use of Solid Immersion Lenses (SILs), created in bulk silicon in less than 20 minutes of processing time, using a focused ion beam and a bitmap milling process. Fibbed SILs can be removed by polishing, and the silicon back surface resumes a perfect planar shape for further backside analysis or the creation of more SILs. The influence of the progressively thinner sample thickness on the magnification of the SIL was analyzed. As fibbed SILs in this work are about 1.4 µm thick and have an additional magnification of 2.4, a second process after removal has been found to decrease magnification not more than 20%. The presence of interference rings in the SIL image could be almost completely removed by anti-reflective coating. Photon emission microscopy, performed using fibbed SILs, allowed to clearly distinguish between sources that were separated by 240 nm wide structures.
Localized Epoxy Layer Formation on Surface Defect Using a Micro-Brush in a Plucking System
Authors: Lin Kun-Lin , Luo Jian-Shing , Lee Hsiu-Ting , Russell Jeremy D.
Published: December 2020

This paper provides details of a novel method developed to cover a tiny epoxy layer as an intermediate buffer on the site-specific surface defect using a micro-bush on the tip of a glass needle in a plucking system without sample surface damage and localization problems. It describes the method and some real cases. The microstructures are investigated using an FEI Tecnai TF20 field emission gun transmission electron microscopy equipped with a high angle annular dark field detector, an energy dispersive X-ray spectroscopy, and Gatan image filter systems. The paper explains the micro-brushes and buffer layer preparation though figures and illustrations.
Evaluation Trial of MEMs Devices by LSI Process Diagnostics
Authors: Shimizu Wataru , Kubota Hidehisa , Murahara Daisuke , Nakamura Noriko , Kamiyama Hirokazu , Oda Tamiko , Yabe Kazuhiro
Published: December 2020

The goal of this paper is to construct a process diagnostic system of the MEMS device based on this "Large Scale Integrated (LSI) Diagnostic system" and then to perform a structural evaluation of the devices based upon the data. The paper explains the methods of analysis for the assembly process and the wafer process. The evaluation of the wafer process indicated that changes were required for MEMS devices vs. conventional LSI diagnosis. It was confirmed that "a peculiar inspection point to MEMS", "Sample making technology", and "Judgment criteria of the defect" were necessary. It is also necessary to do preliminary studies of each MEMS device and to restructure the inspection menu corresponding to the structure based on the inspection results.
UV Emission Microscopy Development for High Band Gap Components
Authors: Bouya M. , Carisetti D. , Clement J.C. , Malbert N. , Labat N. , Perdu P.
Published: December 2020

HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. As well as the improvement of the MMIC performances, the localization of the defects linked with hot electron and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by UV electroluminescence or UV light emission. Its feasibility and efficiency have been demonstrated through two case studies. So, a specific UV microscopy technique has been developed and is presented in this paper.
Ultimate Resolution for Current Localization by Means of Magnetic Techniques
Authors: Infante Fulvio , Gabarrot Mathieu , Perdu Philippe , Lewis Dean
Published: December 2020

Defect localization is a very important step in the process of failure analysis for Integrated Circuits. A very important technique, allowing the localization of the defects with a certain degree of precision, is Magnetic Current Imaging. However, this technique has strict limitations related to the working distance and the maximum current magnitude detectable. We overcame these limitations by using a simulation approach, allowing us to sensibly increase the technique resolution and to map currents which are much weaker. This is done by comparing the measurement of the Magnetic Induction Field to a set of simulations of defect assumptions.
Challenges Facing the Detection of Leakage Current in Integrated Circuit (IC) Devices
Authors: Toh S.L. , Hendarto E. , Sudijono J. , Tan P.K. , Goh Y.W. , Lin H.B. , Deng Q. , Tan H. , Zhu L. , Wang Q.F. , Li H.L. , He R. , Lam J. , Mai Z.H.
Published: December 2020

Electrical characterizations were needed to identify the root cause of leakage issues in IC devices. The methodology required was dependent on the failure mode obtained during testing and global or nano-scale isolations had to be implemented accordingly. As such, challenges encountered in sample preparation or due to detection methodology choices for every isolation technique have to be addressed in order to localize the defective sites.
The Helium Ion Microscope for High Resolution Imaging, Materials Analysis, Circuit Edit and FA Applications
Authors: Thompson William B. , Notte John , Scipioni Larry , Ananth Mohan , Stern Lewis , Sanford Colin , Ogawa Shinichi
Published: December 2020

Currently, the helium ion microscope (HIM) can be operated in three imaging modes; ion induced secondary electron (SE) mode, Rutherford backscatter imaging (RBI) mode, and scanning transmission ion imaging (STIM) mode. This paper will provide an overview of microscope’s ion source, its ion optics, the system architecture, the fundamentals of these three imaging modes and many FA related examples. Recently integrated with the microscope are a Rutherford Backscatter (RBS) detector for materials analysis and a gas injection system (GIS) for material modification. We will describe this new hardware and suggest how these additions could also contribute to the helium ion microscope being an important failure analysis tool.
Characterization and Failure Analysis of 3D Integrated Semiconductor Devices—Novel Tools for Fault Isolation, Target Preparation and High Resolution Material Analysis
Authors: Altmann Frank , Petzold Matthias , Schmidt Christian , Salzer Roland , Cassidy Cathal , Tesch Paul , Smith Noel
Published: December 2020

In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.
Design Diagnosis with E-Beam Probing to Improve Reliability Issue Due to Competitive Signal Error
Authors: Chuang T.C. , Shen C.M. , Wen L.F. , Lin S.C. , Huang C.M. , Lee Jon C.
Published: December 2020

Tiny circuit design reliability issue related to competitive signal was investigated in a sense amplifier (SA) circuitry of SRAM by E-Beam probing technique in this paper. The irregular output signals then traced back to former stage circuit and identified associated waveforms. With such design concept and technique tracing, the invisible and cunning circuit mismatch reliability issue could be revealed successfully.
Leveraging the Power Grid for Localizing Trojans and Defects
Authors: Plusquellic Jim , Acharyya Dhruva
Published: December 2020

The finite, non-zero resistance of the metal wires that define the power grid of chips require the insertion of multiple ports between the grid and the external power supply in order to meet voltage stability requirements across the 2-D plane of the chip. The ports connect to the power grid along its edges for peripheral pad configurations, while, for C4 or array pad configurations, the ports are distributed across the 2-D surface of the chip. In either case, the availability of multiple power ports can be leveraged for detecting and localizing defects and/or Trojan circuits. A localization technique is investigated in this paper that analyzes anomalies introduced by defects and/or Trojans in the measured IDDQs from these ports. The localization accuracy of the technique can be improved significantly through the use of calibration and additional information collected from simulation experiments. The method and model are validated using data collected from a set of chips fabricated in an IBM 65 nm SOI process.1
Success! > 90% Yield for 65nm/40nm Full-Thickness Backside Circuit Edit
Authors: Niles David W. , Kee Ronald W.
Published: December 2020

The authors present a detailed analysis of a full-thickness backside trenching and contact level circuit editing methodology used to achieve a success yield of greater than 90%. The methodology involves both full-thickness backside trenching and contact level circuit modifications on flip-chip parts produced with 90nm, 65nm, and 40nm foundry processes and mounted on laminated package technology. Having successfully edited >150 parts with this methodology, the authors prove that full-thickness trenching is a viable alternative to a traditional die-thinning process, and that circuit edits at the contact layer, to avoid milling into the copper metal layers, greatly reduces risk and uncertainty.
Combining Time Resolved Emission and Analog Simulation for Fault Localization
Authors: Burmer Christian , Hopsch Fabian , Vermeiren Wolfgang
Published: December 2020

In this paper, we describe a fault localization strategy for scan designs based on Time Resolved Photon Emission (TRE) and analog simulation. After characterizing the defect’s electrical footprint using TRE, analog fault simulation is applied. A user - friendly software package with an easy to use interface to scan diagnosis, layout tool and simulator was created.
Identification of a Non-LDD Induced Vt Shift Failure Mechanism via Nano-Probe Characterization
Authors: Mulder Randal , Tsang Yuk
Published: December 2020

The relationship between blocked or depleted lightly doped drain (LDD) implants and threshold voltage (Vt) shifts resulting in suppressed drive current has been thoroughly investigated and characterized through nano-probe analysis. In this paper, a review for a technique for characterizing Vt shift failures is presented as well as a brief review of the LDD Vt shift failure. A case study is also presented showing the characterization, identification, and the physical analysis results for the symmetrical Vt shift failure mechanism. The method presented allows the analyst to differentiate between a Vt shift failure caused by a depleted LDD implant mechanism and a failure caused by dopant depletion in the gate poly-silicon. The results demonstrate that there are now at least two failure mechanisms that can be responsible for threshold voltage failures and it is likely that there are more that have yet to be discovered.
Frequency Sensitive Soft Fails in SRAM Arrays
Authors: Pendyala Sweta , Kane Terence , Tenney Michael , Oldrey Richard , Villalobos Manuel , Sylvestri John
Published: December 2020

Root cause analysis of frequency sensitive “soft” failures in SRAM arrays pose unusual challenges to the failure analyst. Conventional atomic force probe (AFP) DC measurements cannot reliably identify the failure source. The employment of tester based schmoo screening have been shown to correlate with AFP AC quantitative capacitance measurements for the first time. The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for localization has been previously described [1,2,3]. By exploiting the dC/dV component of the NCVS signal shown in Figure 1 and integrating this output, a quantitative capacitance versus voltage measurement can be demonstrated. This quantitative capacitance measurement identified a frequency sensitve horizontal pair failure (HPF) in the SRAM array. Subsequent process vintage analysis identified the source and eliminated these frequency sensitive HPF characterisics. Given the sensitive nature of these fails, conventional physical analysis methods of TEM EELS, and cross section scanning capacitance analysis were not successful in finding the root cause. This underlies a paradigm shift in failure analysis. Electrical measurements may be the only means to identify a process problem and follow-up process vintage analysis is required to solution the root cause.
The Challenges of Backside Focused Ion Beam (FIB) Editing in the Presence of Deep Trench Decoupling Capacitors
Authors: Herschbein Steven B. , Scrudato Carmelo F. , Worth George K. , Hermann Edward S.
Published: December 2020

For most advanced semiconductor products, Focused Ion Beam (FIB) circuit modification and node access through the backside of the chip is the only viable approach. The high density of interconnect wiring and the presence of C4 solder bumping for chip to module attachment has made complex edits virtually impossible with long standing conventional frontside techniques. Unfortunately, the presence of buried circuit elements on the very latest designs greatly complicates the backside editing formula. The introduction of deep trench capacitors as a distributed circuit element in logic designs has had a profound impact on the established methods of backside FIB chip editing. In many cases wide area preparatory trenching down to the underside of circuitry cannot be done without damage to structures that penetrate the silicon adjacent to active transistors by as much as 10 microns. The decision whether to remove these devices or attempt to work around them requires an analysis of the impact on circuit performance and an assessment of the working space (control of anisotropy of etch, aspect ratio issues, etc.) available for executing the edit. IBM is in the process of developing a new set of procedures for performing FIB backside edits on circuits that incorporate these buried structures.
Circuit Edit and Optical Probe Development and Validation for Next Generation Process Nodes
Authors: Giacobbe John A. , Pardy Patrick , Peterson Charles A. , Shykind David , Zickel Scot E.
Published: December 2020

Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.
Improving Wire Sweep Performance by Measuring Degree of Cure of Epoxy Mold Compounds
Authors: Dal Sheila Liza B.
Published: December 2020

The choice of epoxy mold compound (EMC) for an electronic package is based mostly on how much protection it provides to the active components in the package. But the choice is not a straightforward process. Rather it is mostly trial and error using different assembly parameters to find the most robust material while assembly defects are monitored. One such defect associated to EMC processing is wire sweep, and many studies have shown that it is mainly caused by viscosity changes in the EMC. In this study, samples of EMC in various stages of shelf life and staging times were analyzed for degree of cure using a method called differential scanning calorimetry (DSC). Samples are then processed at assembly for wire sweep measurement. It was found out that degree of cure increases with staging time at different rates for each shelf life. It was also found out that wire sweep did not only increase with degree of cure but it was also found to be predictable with respect to the latter. Using this information, the age and staging limit for each material was identified that would not cause wire sweep issues.
Whisker Formation in Copper Electroplating
Authors: Han Theresa , Cho Eunin , Heo Jinwoo , Lee Seoung Jae
Published: December 2020

In the manufacture of Printed Wiring Boards (PWB), unwelcome structures, such as nodules and whiskers can be formed during copper electroplating with copper sulfate. Copper (Cu) whiskers with lengths of up to a few hundred micrometers can lead to electrical shorts between layers or patterns. In this paper, we document factors that can affect the growth of Cu whiskers; decomposition of additives in the Cu electroplating solution, surface stress, acidic cleaner, and the ingredients of a dry film. Contaminants from outside of the electroplating bath and the ingredients of the dry film were shown as key components in the formation of Cu whiskers.
Failure Analysis on Power Trench MOSFET Devices with Copper Wire Bonds
Authors: Wu Huixian , Chiang Arthur , Le David , Pratchayakun Win
Published: December 2020

With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.
New Front Side Access Approach for Low-k Dielectric/Cu Technologies in Plastic Package
Authors: Aubert Amandine , de Morais Lionel Dantas , Pétremont Stéphanie , Labat Nathalie , Frémont Hélène
Published: December 2020

This paper presents a new sample preparation process for front side access for die with organic dielectric layers that are encapsulated in plastic packages. The limitation of the standard failure analysis flow is firstly described, showing the damage caused by wet etching. Then, the decapsulation method combining laser ablation and plasma etching is presented. It is completed by the process optimization. The final process makes it possible to perform failure analysis on low-k/Cu technologies in plastic package either by the front side or by the backside of the die.
TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching
Authors: Nan Liew Kaeng , Lung Lee Meng
Published: December 2020

Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.
Fast Diagnosis and Failure Mechanism of Phosphorous Contamination in Arsenic-Implanted Silicon
Authors: Zhu Lei , Teo H. W. , Ong K. , Huang Y.H. , Koh R. , Chew P.Y. , Hua Y.N.
Published: December 2020

A particular failure analysis case where phosphorous contamination occurred in arsenic-implanted Si is presented. Time-of-Flight secondary ion mass spectroscopy (TOF-SIMS) can be used for fast diagnosis of this contamination which shows 300% surface density change relative to the baseline. It is found that the cause of the phosphorous contamination is due to a combination of implanter chamber re-deposit cross contamination and rapid thermal annealing (RTA) process induced drive-in effect.
Failure Analysis Methodology on Unique 68mm Single Ring Pattern Due to Load Lock Burr
Authors: Quah A.C.T , Ang G. B. , Chen C. Q. , Zhu David , Gunawardana M. , Indahwan J. , Lee M.T. , Neo S.P. , Chen Y.
Published: December 2020

This paper describes a low yield case which results in a unique 68 mm single ring wafer sort failure pattern. A systematic problem solving approach with the application various FA techniques and detailed Fab investigation resolved the issue. The root cause for the unique ring failure pattern was due to a burr at the implanter load lock. The burr scratched and toppled the photoresist resulting in subsequent blocked well implantation and memory failure.
Acoustic Micro Imaging of Large Objects
Authors: Sullivan Daniel J. D. , Guzman Jesse A.
Published: December 2020

Scanning acoustic microscopy (SAM) has been in use for the analysis of small devices, mostly ICs, for quite some time. [1] This paper address the use of the technique on larger objects, such as solar panels, PCBs, and brazed cooling plates, the issues that arise, and solutions to mitigate those issues.
New Failure Analysis Method for Laser Voltage Probing (LVP) Utilizing System Evaluation Board and Software
Authors: Lee Suk Ho , Lee Yun Woo , Hong Moo Jong , Yun Sung Jun , Lee Eun Cheol , Hong Kyu Shik
Published: December 2020

Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.
Evaluation of Electrical Properties of Cell Area on the Semiconductor Devices by FIB Technique
Authors: Oh Jangwon , Kim Jonghyeb , Lee Jonghak , Kim Jongmin , Back Taesun , Kim Won , Kim Hojoung , Kim Changreol
Published: December 2020

We have demonstrated the sample fabrication by focused ion beam (FIB) milling and delineation etch gas which makes it possible to directly measure resistance in a cross section of semiconductor devices with a nano probe after cell fabrication. With direct evaluation of electrical properties, this technique can help improve semiconductor devices.
The “Perfect Storm” Now Appearing in FA Labs Everywhere
Authors: Shade Gary F. , Sood Bhanu
Published: December 2020

The International Symposium for Testing and Failure Analysis (ISTFA) 2010 event added a focus topic on Counterfeiting in Electronics. This topic was chosen because of the emergence of this concern and the critical role that Failure Analysis plays in this challenge. Failure Analysts will be involved deeply as companies worldwide are attempting to reduce the impact of increasing numbers of counterfeit products in the supply line and in fielded products. This paper will attempt to provide an overview of the topic and support the contributors to ISTFA 2010 while providing additional resources for information.