bluuebunny/crossref_metadata_2025 huggingface dataset:
Wafer Conserving Full Range Construction Analysis for IC Fabrication and Process Development Based on FIB/Dual Beam Inline Application
Authors: Weiland R. , Boit C. , Ebersberger B. , Meis P. , Dawes N. , Dziesiaty A. , Zimmermann H. , Demm E. , Hirsch A. , Frey L. , Lehrer C. , Geyer S. , Kamolz M. , Rettenmaier H. , Tittes W. , Lezec H. , Treichler R.
Published: December 2020

The step into the production line environment is a quantum leap for physical failure analysis (PFA) and will change its work in the near future. Wafer sacrifice for analysis becomes obsolete. The main benefits are: 1. reduction of wafer costs, 2. more splits per development lot, 3. reduced cycle time of analysis and technology development. Machines needed for that purpose are dual beam SEM/FIB tools. In the following we present solutions how PFA in a broad range can be carried out inside of a production line. The analyzed wafers can be fed back into the production flow which results in lower overall costs and the feedback loop to production engineers is dramatically shortened leading to reduced down times of production tools etc. The highest risk that has kept the majority of semiconductor manufacturers from proceeding into this direction is the contamination of the productive wafer with Ga, the FIB beam particle, that may diffuse into productive parts of the wafer during heat cycles after the analysis step. We show that the risk of contamination by Ga and other materials can be controlled.
Investigation of Substrate Dislocation Induced Bit Line Soft Failure
Authors: Lin Jian-Chang , Hsu Yung-Tsai , Huang Chih-Kuo , Tsai Wu-Chin , Chou Yung-Hua
Published: December 2020

In modern integrated circuits (IC) using sub-micron or deep sub-micron process rules, substrate dislocation is a common failure mechanism in SRAM or embedded SRAM products. Depending on the position of substrate dislocation in the SRAM cell, it may result in problems including junction or contact leakage, gate oxide early breakdown, low threshold voltage, and poor data retention. In this paper, we’ll focus on the test methodology and physical failure analysis to dig out the failure mechanism, substrate dislocation under SRAM pass gate and node contact. In addition, we will measure the electrical behavior of such substrate dislocation. Several FA techniques, such as Passive Voltage Contrast (PVC) [1] pad deposition by Focus Ion Beam (FIB), and electrical micro probing [2] will be used during leakage verification and measurement.
A Purpose-Driven Decision-Based Methodology for Debug and Failure Analysis
Authors: Maher Steven P.
Published: December 2020

There are many different discussions and perspectives on processes for product debug and failure analysis (FA) of integrated circuits [1][2][3][4], with some even minimizing the aspect of process for FA. Most attempts to-date at a process for FA have been either task-oriented or capability-oriented. In this paper, a high-level purpose-driven decision-based methodology is proposed, with goals of: 1) Establishing a high-level discussion of Debug process; 2) Initiating a high-level discussion of FA process; 3) Encouraging a broader “world view” in the context of the product life cycle; 4) Emphasizing clarity of purpose (of Debug or FA actions) - “why do we (the analysts) do what we are doing?” 5) Establishing context for synergy between Debug and FA.
Capacity Management Solutions
Authors: Drummond John , Wolfe Jeff , Smith Martin , Conner Jeff , Brawley Ken , Seefeldt Bart , Davis Cary
Published: December 2020

This paper will cover some of the options available to manage the failure analysis process when it is capacity constrained. This paper will provide a method to model a failure analysis operations capacity to aid in the decision process of where the constraints are. Several examples of solutions to some typical constraints will be presented also.
FIB Chip Repair: Improving Success by Controlling Beam-Induced Damage and Thermal/Mechanical Stress
Authors: Herschbein Steven , Rue Chad , Scrudato Carmelo , Hermann Edward
Published: December 2020

Focused Ion Beam (FIB) success has become more difficult as microchip process technology advances, requiring new techniques for damage control both during the microsurgery procedure and before the finished product can be electrically tested. Ultra thin gate dielectrics, shallower junctions, less ‘white space,’ and new materials surrounding active devices all create additional challenges for imaging, targeting, controlling instantaneous charge damage, and the removal of residual implanted charge. On the macro level, global thinning of bulk silicon housed in hybrid packages is causing new problems with thermal management and mechanical stress. Techniques and procedures used to control electrostatic discharge type damage become ever more critical when working on poorly buffered or isolated device elements, especially from the backside. Implanted gallium and residual charge perturb electrical characteristics, and must be dispersed prior to power-up thru carefully controlled bake steps. Left in place, these FIB-induced perturbations are likely to cause poor functionality or even latchup. The mechanical rigidity and thermal dissipation properties of newer, complex package types must also be restored post-FIB, otherwise cracked silicon or a thermal overload event might be the outcome. In this paper, we will attempt to address some of the common causes of FIB-induced failure on newer silicon and package technologies, and how they might be overcome. FIB techniques and preparatory processes must continue to evolve in order to deal effectively with the problems of direct beam damage, residual charge elimination, and sample stress management.
Precise Fail Site Isolation Using a Combination of Global, Software and Tester Based Isolation Techniques
Authors: Gopu Deepa , Ontko George , Phan Chin , Ramanujachar Kartik , Wills Scott , Hales Alan
Published: December 2020

Precise fail site isolation plays a very important role today in the world of semiconductors. Its importance increases more, as the devices are of cutting edge technology with increasing complexity and decreasing dimensions. Global fail site isolations techniques (like XIVA, Photo Emission, FMI etc) and tester based techniques (using automatic test equipment, Fastscan etc) alone, are no longer sufficient and may not be successful. Long net lists and large fail sites isolated by these methods pose problems for physical failure analysis. Planarity of these large areas during parallel lap and inspection times using the SEM is difficult and tedious, thus leading to long cycle times and low resolution rates. There exists a need for precise fail site isolation. In many cases, no single technique can be used to narrow down a fail site significantly. Instead a combination of different techniques must be used. In this paper we present a case study, where a combination of complimentary techniques are used to successfully isolate a fail area of more than 1300 microns in length to less than 100 microns on a single failing net.
Doping Mapping by SSRM–Reaching Maturity and Sub-10nm Resolution
Authors: Schömann Stephan , Álvarez David
Published: December 2020

For years there has been a discrepancy between the importance of complex doping implantation schemes for advanced technology device performance and the ability to accurately measure the carrier concentrations with the gap widening at each technology node. With scanning spreading resistance Microscopy (SSRM) a major step forward in terms of resolution and quantification was achieved especially since the emergence of full diamond tip manufacturability and improvements in sample preparation techniques. This article discusses the non-trivial prerequisites for this success and some examples from the failure analysis routine that show the promising capabilities of SSRM. The examples include technology monitoring and failure analysis in SOI transistors and vertical surrounded gate transistors, as well as failure analysis on yield and performance issues. SSRM has reached a development stage that allows its application as routine tool for 2D-carrier profiling.
DEI Analysis of an OTP EPROM: Dynamic Electroluminescence Imaging (DEI) Applied to an OTP EPROM Memory Device
Authors: Hulse John , Frank David J. , Simard-Normandin Martine
Published: December 2020

Dynamic electroluminescence imaging (DEI) is a noninvasive means of obtaining high-resolution timing information from a CMOS circuit. This article reports timing measurements made on a 512K-bit EPROM enabled by the use of optical methods alone. The equipment to observe DEI is comprised of a Karl Suss probe station equipped with a position dissecting photomultiplier tube called a MEPSICRON. To demonstrate the power of the technique a 512Kbit EPROM in ~1 micron technology was prepared for DEI Measurement. The EPROM circuitry was exposed for DEI measurement by decapsulating the part with acids. DEI images are recorded in the region of the tri-state drivers for bond pads D0 through D3 and in the region of bond pad D0. The results demonstrate timing information with up to 11 ps time resolution that is correlated with the chip circuitry. DEI has obvious applications in performance evaluation, failure analysis, intellectual property evaluation, and prototype testing.
Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors
Authors: Narang Vinod , Muthu P. , Chin J.M. , Lim Vanissa
Published: December 2020

Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.
A Technique for Reliably Preparing Full-Length Metallographic Cross-Sections of Integrated Circuit Bond Wires
Authors: Nail Carl
Published: December 2020

To overcome the obstacles in preparing high-precision cross-sections of 'blind' bond wires in integrated circuits, this article proposes a different technique that generates reliable, repeatable cross-sections of bond wires across most or all of their lengths, allowing unencumbered and relatively artifact-free analysis of a given bond wire. The basic method for cross-sectioning a 'blind' bond wire involves radiographic analysis of the sample and metallographic preparation of the sample to the plane of interest. This is followed by tracking the exact location of the plane on the original radiograph using a stereomicroscope and finally darkfield imaging in which the wire is clearly visible with good resolution.
Focused Ion Beam Grounding to Alleviate Sample Charging for Scanning Auger Electron Spectroscopy
Authors: Gondran Carolyn F. H. , Morales Emily
Published: December 2020

It is shown that a focused ion beam (FIB) grounding technique can be used to alleviate charge buildup on samples that would otherwise charge in the electron beam to the point where analysis by Auger electron spectroscopy (AES) was limited or impossible. FIB grounding alleviates the sample charging and permits AES analysis. The grounding technique is quick, easy and well understood as it has been used extensively for voltage-contrast analysis. The technique is shown to be useful for enabling analysis on electrically isolated conductive features as well as insulating samples.
Investigation on the Influence of Focused Electron Beam on Electrical Characteristics of Integrated Devices
Authors: Doering S. , Harzer R. , Werner W.
Published: December 2020

This paper addresses two questions related to electrical characterization of devices at the contact level in a semiconductor failure analysis: Is it possible to use scanning electron microscope/focused electron beam based probing system to do electrical characterization at device level despite the fact that there is beam induced device degradation? What are the effects to consider if a beam exposed sample has to be characterized by a nano-probing technique during the failure analysis flow? To answer these questions, an experimental setup with a drive transistor of a single port SRAM manufactured in a 90nm CMOS process was employed. Results confirmed the effect of electron beam induced alteration on integrated devices and it was shown that several parameters influence the investigated device, e.g., beam acceleration voltage and dose used for radiation. The alteration was due to trapped charge located in the gate oxide and also electrons trapped in interface states.
Photo Process Margin Leading to IC Failure – A Case Study
Authors: Chowdhury Vijay , Hsu Clement , Yu Ada
Published: December 2020

Inherently small process margins in patterning are a dominant cause of device yield variability, when process conditions or production lines change. This paper highlights the fact that in spite of a perfect lithographic model, the post OPC variation can be substantial due to manufacturing variability. Pattern integrity is a non-intuitive complex mix of manufacturing process practices combined with manufacturable design practices. Failure analysis is the only effective means for filling the understanding gap for yield management in this case. A case study of yield drop due to layout dependent process marginality and a methodical approach to get to the root of the problem are described in this paper.
Using Statistical Methods to Optimize Patterning Parameters for Tungsten Deposition
Authors: DiBattista Michael , Skinner Kimball , Kneedler Rick , Vasilvey Leonid , Drybcak Lukas , Zbranek Jiri , Hartigan Gavin , Oosting Michiel
Published: December 2020

Circuit edit and failure analysis require tungsten deposition parameters to accomplish different goals. Circuit edit applications desire low resistivity values for rewiring, while failure analysis requires high deposition rates for capping layers. Tungsten deposition can be a well controlled process for a variety of beam parameters. For circuit edit, tungsten resistivity approaching below 150 µohm-cm and 50 μm3/nC is predicted. Material deposition rates of 80 μm3/nC can be achieved with reasonable pattern accuracy using defocus as a parameter.
Extended Circuit Edit, Analysis and Trimming Capabilities Based on the Backside Focused Ion Beam Created Ultra Thin Silicon Platform
Authors: Schlangen Rudolf , Leihkauf Rainer , Kerst Uwe , Boit Christian , Egger Peter , Lundquist Ted
Published: December 2020

Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.
Low Temperature O2 Plasma Process for Scanning Capacitance Sample Preparation
Authors: Schulte Donald W. , McMahon Terry , Hall David D. , Johnson Mark , Stickle William , Sanders Craig , Long Greg , DeHaan Gary , Cai Ruhua
Published: December 2020

A novel SCM oxide preparation technique using a low temperature O2 plasma treatment is presented. Experimental results demonstrated that oxides of sufficient quality for scanning capacitance measurement analysis can be obtained on both top down and epoxy potted polished cross sections. SCM results obtained from samples processed using the plasma process were comparable to those obtained using more common thermal oxide growth techniques.
X-Sectional Scanning Capacitance Microscopy (SCM) Applications on Deep Submicron Devices at Specific Sites
Authors: Wang Xiang-Dong , Tsang Yuk , Howard Clifford
Published: December 2020

In this paper, we present our recent applications of scanning capacitance microscopy (SCM) on specific devices with sampling window as small as 100nm. The dopant related root causes were successfully identified on those devices fabricated with 90nm CMOS technology. The key step in our approach is the development of a sample preparation technique that allows us to precisely x-section through a transistor without being affected by focused ion beam (FIB) artifacts. FIB was used to mark the area of interest with high precision, but it did not expose the devices of interest. Optical microscope and atomic force microscope (AFM) were used to inspect the mechanically polished surface, thus avoiding beam effects from FIB or SEM. In the first application, a doping anomaly was identified in a PFET poly gate, in a single bit failed SRAM cell. In the second application, an asymmetry of a PWell implant profile in a window of 150nm was identified as the cause of leakage in a capacitor array. Our approach may be applied to other scanning probe microscopy (SPM) techniques in the same category, i.e., scanning spreading resistance microscopy (SSRM) or scanning microwave microscopy (SMM).
Product Debug: Speed Problem Related to Unexpected RC Delay
Authors: van Hassel J.G. , Zachariasse F.
Published: December 2020

In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.
Detecting Internal “ESD-Like” Damage on CMOS Gates
Authors: Gores M. , Dicken H.
Published: December 2020

Normally, ESD-type of damage will be located near the bonding pads for the input pins. However, there have been several cases where ESD-type damage has been detected on CMOS gates at internal locations on the die, two or more transistors away from any input or output pin. This paper describes two examples of this type of failure and the unique approaches to the analysis and the special procedures needed to locate the damage sites. It shows some possible approaches to apply to device failures, which do not follow the typical pattern. One of the approaches is a sequence of steps ranging from benign to destructive as shown. The special conditions are usually: the device has functionally failed; curve tracing of the external pins shows no abnormalities; optical and/or SEM inspection of the die will not show any damage sites; and liquid crystal or other thermal techniques will not be effective.
Fundamental Study of Al Pad Grain Size Measurement and Its Effectiveness
Authors: Zhao Yaobin , Dai Haibo , Gao Baolin , Wu Linfeng , Liang Sanan , Niou Chorng , Guo Qiang
Published: December 2020

Grain size monitor of Al pad is necessary to assure pad quality and electrical performance in IC manufacturing. Currently, the sample is prepared either without pretreatment or with 4.9% HF stain or ion milling before grain size measurement. In this paper, we demonstrate the pretreatment has a pronounced effect on the grain size measurement and the method with ion milling pretreatment shows more reliable results. The mechanism is further discussed.
Correcting for Spherical Aberrations in Solid Immersion Microscopy Using a Deformable Mirror
Authors: Lu Y. , Ramsay E. , Stockbridge C. , Koklu F. H. , Yurt A. , Mertz J. , Bifano T. G. , Ünlü M. S. , Goldberg B. B.
Published: December 2020

We present a method for correcting spherical aberrations in solid immersion microscopy through the use of a deformable mirror. Aberrations in solid immersion imaging for failure analysis can be induced through off-axis imaging, errors in lens fabrication or mismatch of design and substrate wafer thickness. RMS wavefront error correction of 30% is demonstrated in the case of substrate wafer thickness error.
Development of a Protective Coating for Application of Ion Cross-Section Polishing on Thermal Inkjet Printhead Heater Chips
Authors: Zhang Q. , Wu X. M.
Published: December 2020

Thermal Inkjet printhead heater chips have a unique construction; getting quality cross-sections using traditional methods is very difficult. This paper describes the development of a new protective coating material, which enables the application of Ion cross section polishing technique for Inkjet heater chip analysis. Applications of this technique are also discussed.
Can Illuminated IV-Characteristics of Micro-Regions in Solar Cells be Measured by Laser-Induced Stimulation?
Authors: Boostandoost M. , Glowacki A. , Bakaeva O. , Kerst U. , Boit C.
Published: December 2020

In this paper, IR-LBIC (Infrared Light Beam Induced Current) is applied using the laser wavelength of 1064 nm in order to analyze polycrystalline thin-film solar cells. The spatially high-resolved map of the short circuit current (~3 µm) has been obtained by performing the IR-LBIC measurement. The results of the measurement showed higher signal response from the grain boundary compared to that from the grain interior. This difference has been explained by the light trapping effect due to the trench-shaped grain boundary profile, which is possibly accompanied by two stage excitation effects via electronic grain boundary states. It has been additionally investigated, whether LBIC measurement could be used to extract local illuminated cell characteristics. However, since the dark current, which has a decisive influence on the solar cell characteristic, is flowing in the entire cell area, this is not possible. A circuit network simulation demonstrates that LBIC cannot be used for extraction of the local open circuit voltage, and the short circuit current is the only parameter that can be locally defined and therefore clearly observed.
Design Based Failure Analysis of a Voltage Sensitive Memory Defect
Authors: Bowsher Andrew , Gloor Cary A. , Griffiths Bruce , McMahon Chris
Published: December 2020

The semiconductor failure analyst’s tool box is a vast and resourceful set of capabilities that more than ever needs meaningful Memory Failure Signature Analysis (Memory FSA) as an important part of that suite. Today, this is driven by advanced process technology nodes that are producing virtually invisible defects to confound manufacturing and reliability. This demands greater attention to characterizing memory failures in order to theorize causes for failure and to implement suitable FA approaches and corrective action plans. Design Based FA (DBFA) techniques aim to extend this philosophy by focusing on a deep understanding of the chip’s Intellectual Property (IP), in terms of both content and architecture. It uses this knowledge to gain important insights into the behavior of the failure that otherwise may have been hidden or unobservable. This disciplined methodology leads to quicker closure for problems through implementing improved test screens, providing recommendations under a closed-loop Design for Manufacturing (DFM) system, enacting process enhancements, or some combination of all these areas. Here we present a clever technique to further aid in the failure signature analysis process and use it as an example for this Design Based FA methodology.
Novel Plasma FIB/SEM for High Speed Failure Analysis and Real Time Imaging of Large Volume Removal
Authors: Hrnčíř T. , Lopour F. , Zadražil M. , Delobbe A. , Salord O. , Sudraud P.
Published: December 2020

The standard Ga focused ion beam (FIB) technology is facing challenges because of a request for large volume removal. This is true in the field of failure analysis. This article presents the first combined tool which can fulfill this requirement. This tool offers the combination of a high resolution scanning electron microscope (SEM) and a high current FIB with Xe plasma ion source. The article focuses on failure analysis examples and discusses the different steps of extra large cross sections (deposition of protective layer, rough milling, and polishing). Several applications of the novel Xe plasma FIB/SEM instrument are shown with respect to the failure analysis. The performance of the instrument is tested and discussed in comparison to gallium liquid metal ion source FIB systems. Results show that the Xe plasma FIB offers much higher milling rate, greatly reducing the time necessary for many failure analysis tasks.
Failure Analysis Using Scanning Acoustic Microscopy for Diagnostics of Electronic Devices and 3D System Integration Technologies
Authors: Czurratis Peter , Hoffrogge Peter , Brand Sebastian , Altmann Frank , Petzold Matthias
Published: December 2020

New semiconductor chip technologies and technologies for 3D integration require information’s of packaging and interface defects in 3 dimensions, that means the lateral dimension of the defect and the location inside the device or package must be defined. In this paper, new methodical approaches for non destructive failure analysis on 3D integrated TSV samples are introduced. The concepts combine improved scanning acoustic microscopy (SAM) imaging hardware with unique software solutions for defect identification and quantitative analysis of mechanical properties using scanning acoustic investigations. In case of MEMS 3D integration, e.g. based on direct bonding, related interface defects must be investigated by SAM. With respect to 3D integration applications, the potential of recent SAM improvements applying specifically adapted hardware and custom-made signal processing algorithms will be discussed. Examples of SAM-based failure detection techniques for the application in 3D integration are demonstrated. New technologies are shown to improve the through put of fully wafer scanning using scanning acoustic microscopy. To improve the defect resolution, a new transducer design was developed to increase defect resolution and signal to noise for interface characterisation.
SIMS Analysis for the Threshold Voltage Shift of Power MOS Caused by Abnormal Dopant Diffusion
Authors: Huang Yanhua , Zhu Lei , Ong Kenny , Teo Hanwei , Chen Shuting , Hua Younan , Shen Miao , Gong Hao
Published: December 2020

Threshold Voltage (Vt) of MOSFET controls transistor’s on and off state. Vt is usually depends on gate oxide thickness and operating temperature. Systematic failure analysis for a Vt shift issue, should also consider the channel doping which affects the inversion layer formation. In this article, the failure case of a shift in the Vt of a Power MOSFET V is studied. Secondary Ion Mass Spectrometry (SIMS) is found to be the most direct way for detecting any abnormality in the channel doping profiles. A comprehensive simulation is performed showing that the Phosphorus level diffusion from substrate was so high that it affects the doping concentration of channel.
Lock-in Thermography for Flip-Chip Package Failure Analysis
Authors: Cao Lihong , Venkata Manasa , Huynh Jeffery , Tan Joseph , Tay Meng-Yeow , Qiu Wen , Wadhwa Kannu , Schlangen Rudolf
Published: December 2020

This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.
Metallic Nanoneedles Arrays for TEM Sample Preparation “Lift-Out”
Authors: Jalilian Romaneh , Mudd David , Torrez Neil , Rivera Jose , Yazdanpanah Mehdi M. , Miller Brian
Published: December 2020

The sample preparation for transmission electron microscope can be done using a method known as "lift-out". This paper demonstrates a method of using a silver-gallium nanoneedle array for a quicker sharpening process of tungsten probes with better sample viewing, covering the fabrication steps and performance of needle-tipped probes for lift-out process. First, an array of high aspect ratio silver-gallium nanoneedles was fabricated and coated to improve their conductivity and strength. Then, the nanoneedles were welded to a regular tungsten probe in the focused ion beam system at the desired angle, and used as a sharp probe for lift-out. The paper demonstrates the superior mechanical properties of crystalline silver-gallium metallic nanoneedles. Finally, a weldless lift-out process is described whereby a nano-fork gripper was fabricated by attaching two nanoneedles to a tungsten probe.
Failure Analysis of Nickel Silicide Piping Failures: A Case Study
Authors: Howard Clifford , Tsang Yuk , Subramanian Sam , Ly Khiem , Chrastecky Tony , Erington Kent , Ybarra Juan
Published: December 2020

As semiconductor geometries decrease, the size of a defect that leads to circuit failure also decreases. While many defects will cause photoemission or observable leakage paths, occasionally a defect will occur in an area that cannot be easily analyzed. In this analysis, a yield issue in nickel-silicide (NiSi) piping is investigated. The failure had characteristics that fell into areas that avoided detection. A planar transmission electron microscope of the substrate at the defect site was performed to look for evidence of crystalline defects that would allow a conduction path across the channel. This analysis found that NiSi encroachment was the root cause of the yield issue. All analyzed units had the defect between stacked nFET transistors. Because the defect was between stacked nFET gates, the results show that the failure characterization required control of multiple gates to measure the transistor off-state drain to source current.
A Novel Scan-Based Yield Enhancement Methodology for Faster Yield Ramp
Authors: Goh S.H. , Lee H.C. , Lim T.Y. , Ting Fei , Ngow Y.T. , Ng J.H. , Kong F.L. , Lau W.Y. , Lim S.K. , Lam Jeffrey , Yan Pan , Liu Y.J.
Published: December 2020

Scan chain integrity yield loss is a common concern, especially in early stage of product yield ramp. Typically, scan chain failure diagnosis can only proceed upon full silicon build and structural test. In this work, we propose a proactive methodology which enables failure debug step to be initiated as early as the onset of device fabrication, to bring forward yield learning. Scan chain cells and nets information are extracted from design data file and converted to inline optical wafer inspection care areas. In this way, the inspection recipe can be optimized for the detection of scan chain related defects. It is shown experimentally that such approach can potentially enhance general defect detection sensitivity by 50% and increase the defect hit probability on scan chain nets. Any findings serve as useful early data for process improvement feedback. Furthermore, marginal defects, which otherwise are not easily revealed using conventional approach, can also be detected to provide early warning for process drifts or variations.
Thermal Investigations on CMOS Integrated Micro-Hot-Plates Using IR Thermography
Authors: Schmidt Christian , Altmann Frank , Mutinati Giorgio C. , Brunet Elise , Steinhauer Stephan , Koeck Anton , Siegele Martin , Gamauf Christoph , Nemecek Alexander , Teva J. , Kraft J. , Siegert J. , Schrank F. , Kruschke Hans
Published: December 2020

In this paper, investigations on absolute temperature measurements using IR-Thermography of CMOS integrated micro-hot-plates (μHP) are presented. The results of using two different approaches, emissivity correction and black paint coating, are presented and compared with respect to simulation and electrical testing results. In addition, FIB/SEM investigations were used for surface investigations and determination of possible influences to the thermal behaviour by black paint coating process.
Studies of Buried Voids Capturing with e-Beam Inspection System and Confirmation with Physical Failure Analysis
Authors: Xiao Hong , Jiang Ximan
Published: December 2020

In this paper, a novel inspection mode of electron beam inspection (EBI) that can effectively detect buried voids in tungsten (W) plugs is reported for the first time. Buried voids in metal are a defect of interest (DOI) that cannot be captured by either optical inspection or traditional EBI modes. The detection of buried voids is achieved by using energetic electron beam (e-beam) with energy high enough to penetrate into metal and reach the buried void. By selecting desired secondary electrons to form the inspection images, strong contrast between the defective tungsten plugs and normal ones can be achieved. Failure analysis was performed on the DOI that is unique to this new EBI mode. After optical microscope locating and laser marking, we successfully recaptured DOI with scanning electron microscope (SEM) and capped the DOI with e-beam assisted platinum (Pt) deposition. Later a dual-beam focused ion beam (FIB) system was used to re-locate the Pt-capped DOI and prepare samples for transmission electron microscope (TEM). TEM images confirmed the unique DOI were buried voids in the metal plugs, which could affect resistance of interconnect in integrated circuit (IC) chip and impact the IC yield.
Conversion of a D-Mode FET to an E-Mode FET via Electrostatic Discharge in a GaAs Power Amplifier Duplexer Module
Authors: Emergo Rose , Brockett Steve
Published: December 2020

This paper outlines the systematic isolation of an electrostatic discharge defect on a depletion-mode FET. Topics covered are fault isolation, FIB-STEM cross-section and EDS analysis, and defect simulation. Multiple GaAs PA devices were submitted for analysis after failing different reliability stresses. Fault isolation revealed ESD damage on a DFET connected to the VMODE0 pin. Simulation of the failure showed that, most likely, the defect was caused by CDM stress. A design change of inserting a resistor between the VMODE0 pin and the DFET made the device more robust against CDM stress.
Pump-Probe Imaging of Integrated Circuits
Authors: Stoker David , Bruce Michael , Lavelle Eric , Matlin Erik , Potthast James , Sakai Christopher , Troy Neil
Published: December 2020

We present a new method of imaging integrated circuits (ICs) using a dual-laser scanning confocal microscope. In this method we introduce physical and/or functional changes to the integrated circuit using the first ‘pump’ laser and then image the response of the circuit using the second ‘probe’ laser. We propose several novel applications of this imaging method. Specifically, we show how to image the flow of injected charge carriers and use the derived images to improve the resolution of material interfaces. We also show how to image changes to activity and laser voltage-probed waveforms and use the information to discover electrical connections between logic cells.
Tester-Based Methods to Enhance Spatial Resolvability and Interpretation of Time-Integrated and Time-Resolved Emission Measurements
Authors: Stellari Franco , Song Peilin , Weger Alan J. , Maliuk Dzmitry , Ainspan Herschel A. , Kim Seongwon , Kwark Young , Baks Christian W.
Published: December 2020

In this paper, we discuss the use of a tester-based methodology to enhance the spatial resolvability and interpretation of time-integrated and time-resolved emission measurements. This technique, first presented at [1] for chip diagnostics and failure localization, is very powerful for extending the capability of modern analytical tools beyond the limits of existing optics and detectors. In particular, we will discuss how the proposed method works and present several test cases for both static and dynamic emission measurements that allow signals from gates 150 nm apart to be resolved.
Advanced FIB CE Combined with Static Analysis for Functional Failure Analysis
Authors: Loh S.K. , Chen C.Q. , Yip K.H. , Quah A.C.T. , Tao X. , Ng P.T. , Ang G.B. , Zhao S.P.
Published: December 2020

It is difficult to simulate functional failures using static analysis tools, therefore, debugging and troubleshooting devices with functional failures present a special challenge for failure analysis (FA) work and often result in a root-cause success rate is quite low. In this paper, the application of advanced FIB circuit edit (CE) processes combined the static FA analysis yielded successful localization of a bipolar junction transistor (BJT) device soft failure. Additional FA techniques were incorporated within the FA flow, resulting in characterization of the electrical behavior of a suspected transistor and detection of an abnormal implant profile within the active area.
Application of AFP in Resolving Systematic Issue in Wafer Fabrication
Authors: Ng Hui Peng , Ang Ghim Boon , Chen Chang Qing , Quah Alfred , Teo Angela , Lee Mern Tat , Indahwan Jony , Zhao Si Ping
Published: December 2020

With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]
Memory Address Verification Using NIR Laser
Authors: Hoe Wilson Lee Cheng , Saku Leena , Kok Ong Wei , Kian Yau Moi , Ren Felix Yue
Published: December 2020

The upward trend in memory to chip ratio in novel chip design had increase the possibility of a defect to fall on the memory area. There are a number of ways of performing memory address verification in the industry. This paper describes some of the methodologies as well as introduces an efficient approach using near infra-red (NIR) laser to perform the memory address verification. Current methodologies include analyzing physical chip with memory hard failure, the green laser (532nm) method, and the focus ion beam method. The advantages and disadvantages of each methodology are mentioned. As long as the failing orientation is correct and the test program failing address is within the NIR laser damage zone, a failure analyst can have more confidence to analyze a real chip with memory failure without any doubt that he/she might be looking at the wrong location.
TEM Sample Preparation Methods for MEMS Floating Structure Analysis
Authors: Yu Huisheng , Duan Shuqing , Li Ming
Published: December 2020

The MEMS structure has its particular character like hollow areas inside, and “floating” structures. Traditional TEM sample preparation method usually leads to distortion and dissociation defects of the floating structure. This paper introduces two innovative practical methods of TEM sample preparation using focused ion beam (FIB) for MEMS floating structure analysis. Method 1 used glass needle to lift out the separated film onto glue coated blank wafer; method 2 used in situ pick up system to lift out L- or C-shaped cut film onto TEM half-grid. And then the sample can be applied to normal TEM membrane preparation procedure.
Design Debug for Intermittent Power up Failure in Analog/Mixed Signal Devices
Authors: Karki Sagar , Sule Oladele , Zhihong You
Published: December 2020

To maintain product reliability and robustness, current generation submicron integrated circuits need to pass high quality and exhaustive testing programs before being shipped off to the customer or released into the market. Precise and reliable silicon debug is essential to the semiconductor industry. It identifies problems caused by design changes, process anomalies and rarely used applications. This is essential to drive the corrective action at the earliest stage of production. This paper describes the systematic approach of a complex design debug in one of the ASIC device.
Optical Fault Isolation and Nanoprobing Techniques for the 10 nm Technology Node and Beyond
Authors: von Haartman Martin , Rahman Samia , Ganguly Satyaki , Verma Jai , Umair Ahmad , Deborde Tristan
Published: December 2020

Resolution of optical fault isolation (FI) and nanoprobing tools needs to keep pace with the device downscaling to be effective for semiconductor process development. In this paper we present and discuss state-of-the-art FI and nanoprobing techniques evaluated on Intel test-chips fabricated on next generation process technology. Promising results were obtained but further improvements are necessary for the 7nm node and beyond.
Device Ioff Mapping—Analysis of Ring Oscillator by Optical Beam Induced Resistance Change
Authors: Johnson Greg M. , Xu Ziyan , D’Aleo Christopher
Published: December 2020

The ring oscillator is an important tool for inline monitoring during technology development, as it contains the most important front end of line technology features, is testable at first metal, and generally shows a good correlation to SRAM yield. This work explores various failure analysis techniques for the ring oscillator, during the development of 14 nm FinFET technology. OBIRCH, which is typically a DC technique, was operated with voltages as low as 0.15 V to find multiple defect mechanisms affecting the yield of ring oscillators, which operate at a frequencies in the GHz range. In contrast to typical photon emission analysis of ring oscillators, examines the devices which are flipping on, it is here proposed that the OBIRCH spots which are generated are indications of the Ioff, or the leakage of devices in the inverter stages across the ring. The results from this failure analysis approach enabled a rapid improvement in yield not only of the ring oscillator itself but of the SRAM.
2015 ISTFA Presentation #1: 2010–2015—The Evolving Counterfeit Machine
Authors: Sharpe Thomas
Published: December 2020

This presentation is chronologically-progressive to the author's ISTFA Keynote given in 2010: "Counterfeiters' Techniques: Constantly Improving to Avoid Detection - National Security Depends on Us to Keep Up". It shares, in detail, the forensic test methodologies utilized by SMT and ultimately the research breakthroughs which gave the labs crystal-clear insight into the counterfeiters specific step-by-step rework process. The presentation includes all forensic work utilized in exposing the "Micro-blast" & "Flat-Lap" counterfeit processes identified at SMT labs during 2011, as well as unpublished novel process threats and refinements identified in 2013 & 2014. It also covers the counterfeit mitigation work that SMT supported with the GAO and Senate Armed Services Committee's investigation into counterfeits within DoD supply chains during the 2011-2012 time period.
Techniques for Reverse Engineering and Functionality Extraction of Mixed-Signal ICs for Security Applications
Authors: Stellari Franco , Lin Chung-Ching , Gignac Lynne , Robertazzi Raphael , Weger Alan , Song Peilin
Published: December 2020

In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.
Root Cause Analysis for Pin Leakage
Authors: Song Zhigang , Nxumalo Jochonia , Villalobos Manuel , Pendyala Sweta
Published: December 2020

Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.
Gate-Level Netlist Reverse Engineering Tool Set for Functionality Recovery and Malicious Logic Detection
Authors: Meade Travis , Zhang Shaojie , Jin Yier , Zhao Zheng , Pan David
Published: December 2020

Reliance on third-party resources, including thirdparty IP cores and fabrication foundries, as well as wide usage of commercial-off-the-shelf (COTS) components has raised concerns that backdoors and/or hardware Trojans may be inserted into fabricated chips. Defending against hardware backdoors and/or Trojans has primarily focused on detection at various stages in the supply chain. Netlist reverse engineering tools have been investigated as an alternative to existing chip-level reverse engineering methods which can help recover functional netlists from fabricated chips, but fall short of detecting malicious logic or recovering high-level functionality. In this work, we develop a netlist reverse engineering tool-set which recovers high-level functionality from the netlist, thereby aiding malicious logic detection. The tool-set performs state register identification, control logic recovery and datapath tracking, which facilitates validation of encrypted/obfuscated hardware IP cores. Relying on 3-SAT algorithms and topology-based computational methods, we demonstrate that the developed tool-set can handle netlists of various complexities.