bluuebunny/crossref_metadata_2025 huggingface dataset:
Rheed Observations of Silicon (100) Surface Reconstruction after Remote Hydrogen Plasma Cleaning
Authors: Hsu T. , Breaux L. , Anthony B. , Banerjee S. , Tasch A.
Published: March 2011

Low temperature silicon epitaxy is critical to novel silicon-based devices requiring hyper-abrupt transitions in doping profiles or heterointerfaces. Epitaxy by Remote Plasma-Enhanced Chemical Vapor Deposition (RPCVD) consists of an in situ remote hydrogen plasma clean of the silicon surface followed by growth of silicon from silane at 220° - 400°C. Reconstruction of the silicon (100) surface from a (1×1) to a (2×1) structure after cleaning at 310°C is observed by RHEED, indicating an atomically clean surface. The removal of carbon and oxygen has been further substantiated by Auger Electron Spectroscopy (AES) and growth on these atomically clean substrates has produced good quality epitaxial films. Using remote hydrogen plasma cleans at lower temperature we report the first observation of third-order silicon surface reconstruction on a Si(100) surface, where two faint fractional order streaks between the sharp integral order streaks are observed. After a short (5 minute), low temperature (300-400 °C) anneal the third order pattern transforms rather quickly to a strong (2×1) reconstruction pattern. The third order pattern can then be restored by following the anneal with a repeat of the lower temperature hydrogen clean. Although the origin of the third order pattern is unclear at this time, we believe it is due to a Si-H complex formation at the silicon surface.
Stress Gradients in SIO2 Thin Films Prepared by Thermal Oxidation and Subjected to Rapid Thermal Annealing
Authors: Bjorkman C.H. , Fitch J.T. , Lucovsky G.
Published: March 2011

We have studied stress gradients in thermally grown SiO2 thin films and relaxation of the stress by rapid thermal annealing. These properties were examined by incrementally etching back the SiO2 films and performing infrared spectroscopy and beam-bending measurements at each thickness. The thickness-averaged values measured were then deconvoluted to obtain stress values for thin layers of the SiO2 films. We observed steep stress gradients close to the Si/SiO2 interface for wet oxides which were similar to those previously studied in dry oxides. The stress gradients were steeper for films grown or annealed at high temperatures. In addition, we have been able to show that thin films (= 200 Å) relax more freely than thicker films (= 1000 Å), in which oxide close to the interface is prevented from relaxing by the oxide on top of it.
Optimization of a Tin/TiSi2 p+ Diffusion Barrier Process
Authors: Lee S.S. , Galovich C.S. , Fuchs K.P. , Kwong D.L. , Hirvonen J. , Huang J.
Published: March 2011

The TiN/TiSi2 structure, formed by rapid thermal nitridation of a spatter-deposited titanium film, has been demonstrated to be effective as a diffusion barrier and as a low resistance contact material for VLSI submicron metallization. An optimization experiment, designed using the RS/Discover software package, was used to identify a metallization process that minimized p+ resistance as well as maximized barrier capability. Source/drain implant doses, as-deposited titanium film thickness, and rapid thermal processing parameters were the factors varied in the experiment. Of particular significance is a comparison of the effects of a two-step versus one-step rapid thermal anneal on control of the TiN/TiSi2 thickness ratio. A TiN layer of sufficient thickness for barrier integrity and adequate consumption of implant damage in the formation of the TiSi2 layer are desired. Electrical and thermal stability measuremints of the resultant AlSiCu/TiN/TiSi2 p+ contact system are presented.
Thin Silicon Epitaxial Layer Deposition with Reduced Pressure RTP-CVD
Authors: Wong Fred , Chen Charles Y. , Ku Yen-Hui
Published: March 2011

Designs of the advanced integrated circuit devices now require much thinner epitaxial films to achieve superior performance. The capability of depositing thin silicon epitaxial layers which have sharp transition width, well-controlled dopant level, high crystallographic quality, and good growth uniformity across the wafer is essential for high speed bipolar and submicron CMOS technologies. This paper describes a thin silicon epitaxial growth process using a recently developed low pressure CVD silicon epitaxial reactor employing rapid thermal processing with incoherent light source. Crystallographic quality, slip formation, transition width, growth uniformity, and dopant uniformity were investigated using TEM, spreading resistance measurements, SIMS, sheet resistance measurements, and FTIR. The SIMS and spreading resistance measurements revealed that auto-doping effect has been minimized. The transition width can be controlled to 10% of the film thickness while maintaining the growth rate up to 1 μm/min at a deposition temperature in the range of 900 - 1000°C. The growth and dopant uniformities across the wafer as determined by FTIR and Prometrix RS-30 Omnimap are better than 1% and 3% per sigma for epitaxial layer thickness under 2 μm. Initial results on selective epitaxial growth was discussed.
The Effect of Post-Growth Anneals on Nitroxide Films
Authors: Wright Peter J. , Kermani Ahmad , Saraswat Krishna C.
Published: March 2011

A new technique of post-oxidation annealing has been introduced to improve the properties and long term reliability of ultrathin (<100 Å) MOS gate dielectrics. In this technique, after oxidation, nitridation is done in NH3 followed by a light reoxidation in O2 and then an inert anneal in Ar or N2. Using this technique both optimum performance as well as reliability can be obtained without sacrificing either. NH3 anneal of SiO2 improved the hot electron immunity, but degraded the interface quality. Good properties could be obtained by a strong reoxidation of the nitrided films, however, at the expense of a substantial increase in the film thickness. Nitrogen and argon ambients were found to be equally effective at improving film properties. By annealing the film in an inert ambient following reoxidation of the nitroxide, fixed charge can be further decreased with little oxide grown, electron mobility in NMOS FETs increases further, and the hot electron lifetime is much longer than that of the starting oxide.
The Kinetics of Low Pressure Rapid Thermal Oxidation of Silicon
Authors: Lassig Stephan E , L John
Published: March 2011

A study of the oxidation kinetics of lightly doped (100) silicon in dry oxygen has been carried out at different pressures (0.03 atm. to 1.0 atm.) and temperatures (900ºC to 1200ºC) for short times (< 500 seconds). The data can be fit equally well to the parabolic model as it can to the linearparabolic or parallel oxidation models. The activation energy derived from analysis of the parabolic rate constant is 0.94 eVand is the same at 1.0 and 0.1 atmosphere dry O2. It was also found that the parabolic rate constant displayed a linear dependence on the O2 pressure.
Advanced Excimer Laser Annealing of Thin Poly Si Films after Solid Phase Grain Growth
Authors: Noguchi Takashi , Tajima Kazuhiro , Morita Yasushi
Published: March 2011

Thin silicon films with dendritic large grains can be obtained by Si+ or P+ implantation and subsequent low temperature annealing of the silicon film. We tried further exposing the films with an excimer laser after the grain growth. As a result, improvement of electronic properties such as high carrier mobility or low resistivity were obtained. By TEM observation, polycrystalline grains with a dendritic structure did not melt after laser annealing and it was found that the improvement of electronic properties were achieved mainly due to the improvement of crystallinity by U-V(Ultra-Violet) reflectance, ESR(Electron Spin Resonance) analysis and TFT characteristics. We are convinced that this advanced laser pulse annealing method is an ideal RTA process in the near future and is expected to be applicable to ULSI processes for inter connects, high density stacked SRAM and for large area electronics on glass such as a contact line sensor or LCD(Liquid Crystal Display).
Ultra-Shallow Diffused Emitter-Base Profiles Fabricated by Rapid Thermal Processing for High Speed Bipolar Devices
Authors: Urner J. E. , Drowley C. I. , Voorde P. Vande , Kermani A.
Published: March 2011

The development of next-generation high-speed bipolar devices depends critically on reproducible shallow dopant profiles, with base and emitter widths considerably less than 1000 Angstroms. Sequential diffusion of boron and arsenic from implanted polysilicon is a promising means of producing such shallow emitter-base profiles. The restricted thermal budget required to reproducibly form such shallow junctions severely limits the use of conventional furnaces. We report the formation of extremely shallow emitter-base profiles using rapid thermal processing (RTP) in a double-diffused polysilicon emitter process. Polysilicon was implanted with various doses of BF2 and subjected to a conventional furnace anneal at 900ºC. This process was followed by As implantation and furnace anneal at 900ºC or RTP at 10500C or 1100ºC. A range of emitter-base profiles was generated with emitter and base widths ranging from 350-800A. Emitter-base profiles were measured using low-energy Secondary Ion Mass Spectrometry (SIMS), after removal of the polysilicon to improve depth resolution. Deconvolution of the instrumental broadening function allowed extraction of base and emitter widths as well as the boron concentration in the base. Variation of the profiles is discussed as a function of anneal times and implant dose. Modified SUPREM III parameters are obtained for diffusivities under these RTP conditions. The implications for high speed bipolar device fabrication will be presented.
Pt/Ti Low Resistance Non-Alloyed Ohmic Contacts to InP-Based Photonic Devices
Authors: Katz A. , Chu S. N. G. , Thomas P. M. , Dautremont-Smith W. C.
Published: March 2011

Pt/ri low resistance non-alloyed ohmic contacts to p-InP-based contact layers in photonic devices, which were formed by rapid thermal processing (RTP), were studied. E-gun evaporated Pt/Ti metallization deposited onto 1.5· 1019 cm−3 Zn doped In0.53Ga0.47 As yielded the best electrical performance. These contacts were ohmic as deposited with a specific contact resistance value of 3.0 · 10−4 Ωcm2. RTP at higher temperatures led to decrease of the specific contact resistance to 3.4 · 10−8 Ωcm2 (0.08Ωmm) as a result of heating at 450°C for 30 sec. This heat treatment caused only a limited interfacial reaction (about 20 nm thick) between the Ti and the InGaAs, resulted in a thermally stable contact and induced tensile stress of 5.6 · 109 dyne · cm−2 at the metal layer but without degrading the adhesion. Heating at temperatures higher than 500°C resulted in an extensive interaction and degradation of the contact.
Deep-Level Transient Spectroscopy Studies of Rapid Thermal Processed GaAs with Sio2 Encapsulant
Authors: Katayama Masayuki , Tokuda Yutaka , Ando Nobuo , Kitagawa Akio , Usami Akira , Inoue Yajiro , Wada Takao
Published: March 2011

Effects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been studied with X-ray photoelectron spectroscopy, capacitance-voltage measurements and deep-level transient spectroscopy. SiO2 films of 50, 200 and 1250 nim thickness have been deposited on GaAs. RTP has been performed at 760 and 910°C for 9 s. The rapid diffusion of Ga through the SiO2 film occurs, and the As loss and the formation of the As layer near the interface are observed. The decrease of the carrier concentration occurs in all RTP samples. Five electron traps EAI (Ec – 0.27 eV), EA2 (Ec – 0.32 eV), EA3 (Ec – 0.47 eV), EA4 (Ec – 0.58 eV) and EL2 (Ec – 0.78 eV) are produced by RTP. It is considered that the production of the trap EL2 is closely related to the Ga outdiffusion into the SiO2 film and the As indiffusion from the pile-up of elemental As near the interface. Effects of SiO2 film thickness on RTP-SiO2/GaAs are also reported.
Effects of Wafer Backside Emissivity Variation and System Control for Low Temperature Applications
Authors: Pelletier Jay J. , Winter Thomsa E.
Published: March 2011

Rapid thermal processing technology is being investigated for many uses such as shallow junction diffusion and implant annealing. Most of these processes are done at temperatures above 700 C. It is desirable to use the rapid thermal processor for some low temperature applications such as hillock reduction because of the systems ability to heat up and cool down almost instantaneously as compared to conventional furnaces. Machine control for low temperature processing is more difficult than high temperature processing dur to the optical pyrometers inability to perform at its lower limit. Well documented nonlinear effects of wafer backside emissivity over a temperature range of 400C to 600C will also contribute to wafer to wafer temperature instability. In order to fully utilize the advantages of rapid thermal processing technology, it is imperative that the RTPs performance and repeatability at low temperatures be understood.

This paper will discuss the effect of wafer to wafer backside emissivity differences on wafer temperature for low temperature applications. Typical wafer to wafer backside emissivity variation is presented as well as the measurement error of the Peak “ACE” system. “ACE” (Automatic Compensation for Emissivity) can be used to correct for emissivity differences from wafer to wafer.

Effect of improper emissivity selection on actual wafer temperature is presented. Also actual wafer temperature sensitivity to changes in programmed temperature with constant, uncompensated emissivity is demonstrated.

Lamp current monitoring is discussed with supporting data to show the ability of it to be used as a day to day monitor of system performance. Also, The effects of lamp problems associated with idle current.
Simulation of Temperature Effects during Rapid Thermal Processing
Authors: Kakoschek R. , BuβMann E.
Published: March 2011

A complete theory of wafer heating during rapid thermal processing (RTP) is presented. Excellent agreement with experimental results of two commercial RTP systems is obtained. The temperature uniformity is limited by radiation loss at the wafer edge in the stationary state and by nonuniform illumination of the wafer during ramp-up. Structures on wafers are also potential sources for nonuniform heating. Considerable dynamic temperature inhomogeneities during rap-up might limitfu ture applications of RTPe specially when wafer sizes become larger. Possible improvements are suggested regarding adequate process cycling, chip and equipment design.
Properties of Thin Inter-Polysilicon Reoxidized Nitrided Oxides Prepared by Rapid Thermal Processing (RTO/RTN/RTO)
Authors: Cheung Andrew W. , Lo G. Q. , Kwong Dim-Lee , Alvi N. S. , Kermani A.
Published: March 2011

In the search of a high quality thin inter-polysilicon dielectric which has high breakdown voltage and low leakage current for high density non-volatile memory applications, thin (150±) inter-polysilicon reoxidized nitrided oxide capacitors were fabricated with multiple rapid thermal processing. While rapid thermal nitridation degraded the breakdown field if compared to the rapid thermal oxide capacitors, rapid thermal reoxidation greatly enhanced the dielectric strength of the rapid thermal nitrided samples. The short reoxidations increased the film thickness by less than 10 \. Breakdown field of optimized inter-polysilicon RTO/RTN/RTO capacitors up to 14 MV/cm has been measured.
Chemical Vapor Deposition of Polycrystalline Silicon in a Rapid Thermal Processor
Authors: Liao Jimmy C. , Crowley John L. , Kamins Ted I.
Published: March 2011

The deposition of polycrystalline silicon in a rapid thermal processor was studied in the temperature range of 600-1100°C using a mixture of silane and argon at reduced pressures. The amorphous-to-polycrystalline transition temperature was determined by X-ray diffraction and UV-visible spectrophotometry to be between 650 and 700°C. The activation energy of the deposition was found to be approximately 1.5 eV in the temperature range of 600 to 800°C, in reasonable agreement with LPCVD and APCVD results. At 800°C and above, the deposition rate depended only weakly on temperature, as is characteristic of mass-transport-fimited processes. The partial pressure of silane was found to affect the deposition rate in both surface-limited and gas-transport-limited depositions. A UV-visible spectrophotometer was used as a reflectometer to measure the surface roughness of the samples, which in general increased with increasing deposition temperature and film thickness. At the lower deposition temperatures, the surfaces were very smooth, as is characteristic of amorphous-silicon films. Furthermore, the ability to change temperature rapidly appears to allow smoother films to be obtained by initially depositing at lower temperatures, and then ramping to a higher temperature to increase the deposition rate.
Damage Growth in Si During Self-Ion Irradiation: a Study of Ion Effects Over an Extended Energy Range
Authors: Holland O. W. , El-Ghor M. K. , White C. W.
Published: March 2011

Damage nucleation/growth in single-crystal Si during ion irradiation is discussed. For MeV ions, the rate of growth as was well as the damage morphology are shown to vary widely along the track of the ion. This is attributed to a change in the dominant, defect-related reactions as the ion penetrates the crystal. The nature of these reactions were elucidated by studying the interaction of MeV ions with different types of defects. The defects were introduced into the Si crystal prior to high-energy irradiation by self-ion implantation at a medium energy (100 keV). Varied damage morphologies were produced by implanting different ion fluences. Electron microscopy and ion-channeling measurements, in conjunction with annealing studies, were used to characterize the damage. Subtle changes in the predamage morphology are shown to result in markedly different responses to the high-energy irradiation, ranging from complete annealing of the damage to rapid growth. These divergent responses occur over a narrow range of dose (2–3 × 1014 cm-2) of the medium-energy ions; this range also marks a transition in the growth behavior of the damage during the predamaging implantation. A model is proposed which accounts for these observations and provides insight into ion-induced growth of amorphous layers in Si and the role of the amorphous/crystalline interface in this process.
Shallow Junction Formation in As-Implanted Si by Low-Temperature Rapid Thermal Annealing
Authors: El-Ghor M. K. , Pennycook S. J. , Zuhr R. A.
Published: March 2011

Shallow junctions were formed in single-crystal Si(100) by implantation of As at energies between 2 and 17.5 keV followed by conventional furnace annealing or by rapid thermal annealing (RTA). Cross-sectional transmission electron microscopy (XTEM) showed that defect-free shallow junctions could be formed at temperatures as low as 700 °C by RTA, with about 60% dopant activation. From a comparison of short-time and long-time annealing, it is proposed that surface image forces are responsible for the efficient removal of end-of-range (EOR) dislocation loops
On the Formation of Thick and Multiple Layer Simox Structures and their Applications
Authors: Namavar F. , Cortesi E. , Soref R. A. , Sioshansi P.
Published: March 2011

This paper will address the formation of SIMOX structures with thick and multiple buried SiO2 layers by multiple oxygen implantation and growth of epitaxial Si by chemical vapor deposition (CVD). Our results indicate that SIMOX material can be produced with a buried layer of any thickness or with any number of distinct buried oxide layers and distinct silicon layers. Thick and double buried SiO2 layer material may be useful for high voltage isolation and electric field shielding.

In addition, we have demonstrated optical waveguide action in SIMOX wafers. This suggests that in a double buried SiO2 layer system, three dimensional stacked integration of silicon waveguides is possible, including two level optical interconnects.
Study of Stress and Morphology of Silicon–On–Insulator by Means of Ultraviolet Reflectance Spectroscopy
Authors: Lacquet Bea M , Swart Pieter L
Published: March 2011

SOI material was prepared by implanting a high dose of nitrogen into crystalline silicon at an energy of 160 keY to form a buried layer of silicon nitride. Ultraviolet reflectance spectroscopy was employed to characterize the material. In the current presentation the isothermal annealing behaviour of the surface material was investigated with regard to amorphization and stress. Measured UV–reflectance of the samples are compared to simulated reflectance data which were obtained by presenting the implanted material as a layered structure with the surface layer consisting of a mixed layer of amorphous and crystalline silicon. From these simulations the percentage amorphization at each stage during the annealing cycle is quantitatively determined. Stress is qualitatively determined by considering the shift in the position of the frequencies at which reflectance maxima associated with Van Hove singularities are observed in the ultraviolet range. The annealing cycle used in this work proved to be adequate for returning the material back to single crystal status and relieving the initial stress in this layer.
Enhanced Interdiffusion of GaAs-AlgaAs Interfaces Following Ion Implantation and Rapid Thermal Annealing
Authors: Kahen K. B. , Rajeswaran G. , Peterson D. L. , Zheng L. R. , Ott N. L.
Published: March 2011

The interdiffusion of GaAs-AlGaAs interfaces has been shown to be enhanced following ion implantation and rapid thermal annealing at approximately 950°C. A model is presented which explains this phenomenon. It is based on the solution of coupled diffusion equations involving the excess vacancy and Al distributions following ion implantation. Both initial distributions are obtained from the solution of a three-dimensional Monte Carlo simulation of ion implantation into a heterostructure sample. The model is found to be in excellent agreement with several sets of experimental data. More specifically, the model is shown to be valid for ions which do not diffuse appreciably in the time frame of the rapid thermal annealing and for as-implanted vacancy concentrations below ∼6×1019 cm−3. Above that concentration, some vacancies are hypothesized to coalesce, thus being unavailable to assist in the enhanced interdiffusion process.
Ion Beam Mixing of GaAs/AlGaAs Superlattice and ITS Relationship to Amorphization
Authors: Pronko P. P. , McCormick A. W. , Patrizio D. B. , Rai A. K. , Kolbas R. M. , Frank B. S.
Published: March 2011

This work is part of a study to understand the process by which energetic ion bombardment can be used to mix the chemical components of AlGaAs and GaAs superlattice (S/I.) layers of nominal 35 to 50Å thickness. Data reported here involve the retention and build-up of collision cascade damage in the S/I. and its relationship to amorphization and chemical mixing in these systems.
Point Defect Engineering Applied to Shallow Junction ULSI Processing
Authors: Rozgonyi George A. , Honeycutt J. W.
Published: March 2011

We describe how a simple qualitative understanding of the interfacial reactions occurring during typical ULSI processes for junction formation, dopant activation, and contact silicidation can be used to eliminate end-of-range interstitial dislocation loops and beneficially impact the diffusion of dopants. Following a brief discussion of the well-documented effects of oxidation and nitridation on extended defects and dopant diffusion, conditions for elimination of implantation-induced defects are specified. Cross-section and plan-view TEM along with angle lapping and chemical etching of implanted and diffused junctions are presented to illustrate the application of point defect engineering to process technology.
New Features of Dark and Photoconductivity Response of Low Energy Ar+ Ion bombarded GaAs
Authors: Vaseashta A. , Burton L. C.
Published: March 2011

Photoconductivity measurements have been made on three SI GaAs sample types: Ar+ ion etched at leV, 3keV, and unetched. Measurements were made versus time, wavelength, and temperature. Photoquenching was done at 1.19 and 2.0eV energy.

Some distinct changes in photoconductive properties are caused by the ion etch: 1) Increase in dark resistance; 2) presence of persistent photoconductivity; 3) increased photosensitivity; 4) increase In quenching rate under 2eV illumination; 5) destruction of the 0.47eV thermally activated photoconductivity.

All samples exhibit Shockley-Read recombination controlled photoconductivity below a temperature of 125K, with the same apparent trap location, at 0.26eV above EF.
Si Ion Implantation in InAlAs/InGaAs Heterostructures
Authors: Descouts B. , Duhamel N. , Rao E. V. K. , Gao Y. , Praseuth J. P.
Published: March 2011

Si29 implants have been performed in InGaAs and InAlAs single layers as well as in InGaAs/InAlAs heterostructures. Nearly 100% activation has been obtained in InGaAs after conventional furnace annealing or rapid thermal annealing. On the other hand, a low activation efficiency (30%) has been observed in InAlAs. A preliminary photoluminescence measurements study shows that an appreciable fraction of Si exists in the form of complex centers. Hall effect and specific contact resistivity maps carried out in the heterostructures indicate a very good homogeneity of the electrical parameters over a 4 cm2 sample and give a satisfactory value of the specific contact resistivity (10−7 ω.cm2)
Studies on Phosphorus-Implantation and the Annealing of Cadmium Telluride and Copper Indium Disulfide
Authors: Hsu Y. J. , Hwang H. L. , Ueng H. Y.
Published: March 2011

The doping efficiencies obtained in phosphorus-implanted cadmium telluride and copper indium disulfide annealed by pulse electron beam were higher than those annealed by conventional thermal method. To get insights into this phenomenon, electron paramagnetic resonance measurements were performed for both crystals at various stages during the doping process. The results indicated that the pulse electron beam annealing could effectively eliminate the phosphorus interstitials in the implanted crystals but the thermal annealing could not. This shows the significant effect of melting crystals by pulse electron beam annealing to obtain high doping efficiencies.
ION Induced Crystallization and Amorphization of Silicon
Authors: Jackson Kenneth A.
Published: March 2011

Extensive experimental investigations which have been reported on the ion-induced motion of the interface between the crystalline and amorphous phases of silicon are shown to fit a model based on a single defect. The model accounts for the temperature and flux dependence of the interface motion. The defects annihilate each other by binary recombination, and have a motion energy of 1.2 eV. The defect is believed to be the dangling bond in the amorphous phase.
Effect of Recoil Implantation of Oxygen on Boron Enhanced Diffusion in Silicon
Authors: Fan D. , Jaccodine R. J.
Published: March 2011

In device fabrication, dopants are frequently implanted into silicon through silicon dioxide masks. A consequence of this technique is the co-implantation of recoiled oxygen into the substrate. This study investigates the effect of recoiled oxygen on the widely observed transient enhanced boron diffusion. Comparison of the spreading resistance profiles of annealed through-oxide and directly implanted samples reveals that transient enhanced diffusion of boron can be suppressed by the former process. Continued annealing of the through-oxide implanted silicon recovers the enhanced diffusion of boron. This behavior is believed to be due to precipitation of recoiled oxygen. The mechanisms leading to the above observations are discussed and transmission electron microscopy support presented.
Plasma Immersion Ion Implantation for Impurity Gettering in Silicon
Authors: Wong H. , Qian X. Y. , Carl D. , Cheung N. W. , Lieberman M. A. , Brown I. G. , Yu K. M.
Published: March 2011

We have utilized plasma immersion ion implantation (PIII) to demonstrate effective gettering of metallic impurities in silicon wafers. Metallic impurities such as Ni, Cu or Au were intentionally diffused into Si as marker impurities. The Ar or Ne atoms were ionized in an electron cyclotron resonance (ECR) plasma chamber. The ions were accelerated by a negative voltage applied to the wafer and implanted into the wafer. The as-implanted saturation dose can be as high as 5×1016cm−2. After an annealing step at 1000°C for 1 hour in a N2 ambient, the retained doses and the amount of gettered impurities were measured with Rutherford backscattering spectrometry (RBS). With a retained Ar dose in 1015cm−2 range after annealing, the gettered Ni, Cu and Au were 3.0×1014cm−2, 3.0×1014cm−2 and 4.4×1013cm−2 respectively.
Electrical Study of Metal/Gaas Interfaces
Authors: Newman N. , Spicer W.E. , Weber E.R. , Liliental-Weber Z.
Published: March 2011

We have carried out a systematic study of the electrical properties of Schottky barriers formed on atomically-clean and contaminated n-type and p-type GaAs surfaces[1-11]. Diodes were fabricated by in-situ deposition on clean GaAs (110) surfaces prepared by cleavage in ultrahigh vacuum and on contaminated surfaces prepared by cleavage and exposure to the atmosphere[1-4]. The consistent and reproducible barrier height determinations from the electrical measurements of unannealed and annealed diodes, when combined with results of transmission electron microscopy (TEM)[5,6] and surface sensitive studies on identically prepared samples[7,8], are found to be a particularly critical test of models of Schottky barrier formation. A strong correlation between annealing-induced changes in the Schottky barrier height and the stoichiometry of the near interfacial GaAs is found.
Metal-Semiconductor Interfaces with Novel Structural and Electrical Properties: Metal Cluster Deposition
Authors: Waddill G.D. , Vitomirov I.M. , Aldao C.M. , Anderson Steven G. , Capasso C. , Weaver J.H.
Published: March 2011

Studies of Schottky barrier formation at metal-semiconductor interfaces have been complicated by the difficulty of producing an abrupt, “ideal” interface. The commonly used methods of producing metal-semiconductor interfaces result in complex interfacial morphology and chemistry including substrate disruption, atomic interdiffusion, alloy or compound formation, and substrate surface structural changes. The complicated nature of such interfaces makes it difficult from a fundamental point of view to identify the mechanisms dominating Schottky barrier formation for the various stages of development.
Effect of Si and Ge Interface Layers on the Schottky Barrier Height of Metal Contacts to GaAs
Authors: Waldrop J.R. , Grant R.W.
Published: March 2011

A new approach for extending the range of the Schottky barrier height ϕB of metal contacts to (100) GaAs is described. Very thin (∼ 10-30Å) heavily n-type and p-type Si or Ge interlayers are found to directly alter the GaAi interface Fermi energy EF. X-ray photoemission spectroscopy is used to determine EF during contact formation and the corresponding ϕB for thick contacts is measured by electrical methods. In an appropriate structure the ϕB range for contacts to n-type GaAs is ∼ 0.25 to 1.0 eV. For p-type GaAs ϕB has been increased to as much as 0.9 eV. This method of ϕBcontrol can be used for both Schottky barrier contact and nonalloyed ohmic contact applications. The results are interpreted in terms of a simple heterojunction model.
Defect Reactions at Metal-Semiconductor and Semiconductor-Semiconductor Interfaces
Authors: Walukiewicz W.
Published: March 2011

A recently proposed, new approach to the problem of native defect formation in compound semiconductors is presented. The approach is based on the concept of amphoteric native defects. It is shown that the defect formation energy as well as structure and properties of simple native defects depend on the location of the Fermi level with respect to an internal energy reference: the Fermi level stabilization energy. The known location of the stabilization energy determines the electronic part of the defect formation energy and allows for a quantitative description of a variety of phenomena including: the formation of defects at metal-semiconductor interfaces, doping induced superlattice intermixing and limitations of free carrier concentrations in semiconductors.
Ohmic Contact Formation Mechanism in the Ge/Pd/N-GaAs System
Authors: Marshall E.D. , Lau S.S. , Palmstrøm C.J. , Sands T. , Schwartz C.L. , Schwarz S.A. , Harbison J.P. , Florez L.T.
Published: March 2011

Annealed Ge/Pd/n-GaAs samples utilizing substrates with superlattice marker layers have been analyzed using high resolution backside secondary ion mass spectrometry and cross-sectional transmission electron microscopy. Interfacial compositional and microstructural changes have been correlated with changes in contact resistivity. The onset of good ohmic behavior is correlated with the decomposition of an intermediate epitaxial Pd4(GaAs,Ge2) phase and solid-phase regrowth of Ge-incorporated GaAs followed by growth of a thin Ge epitaxial layer.
Equilibrium Phase Diagrams for Analysis of the Oxidation of III-V Compound Semiconductors
Authors: Schwartz G. P.
Published: March 2011

The phases which result from the oxidation of III-V compound semiconductors can be predicted from a knowledge of the condensed phase portion of their equilibrium phase diagrams. Examples will be shown for arsenides, antimonides, and phosphides. Use of these diagrams explicitly presumes equilibrium growth conditions, and that assumption often fails. In such cases kinetic rather than thermodynamic factors dominate the determination of the observed phases. Examples of this phenomenon for anodic oxidation will be presented. Recent interest in high pressure oxidation conditions as a means of alleviating kinetic limitations will be discussed for InP. The phase diagrams can also be used to predict interfacial reactions under certain conditions and data for GaAs will serve to illustrate this point.
Mbe Growth pf Ca5Sr5F2 on (100), (111), (511), and (711) GaAs Surfaces
Authors: Young K. , Horng S. , Kahn A. , Phillips Julia M.
Published: March 2011

We have used molecular beam epitaxy to grow CaxSr1−xF2 films of various thicknesses on GaAs substrates with different orientations, i.e. (100), (111)A, (511)A, (511)B, (711)A and (711)B. On all orientations, the same crystallographic direction is normal to the surface in both the substrate and fluoride film. For all orientations except (111), the fluoride surface is reconstructed with (111) facets. Without annealing, the best crystallinity is obtained for the (100), (111) and (511)B orientations.
The “Buffer” Layer in the Cvd Growth of β-SiC on (001) Silicon
Authors: Cheng T. T. , Pirouz P. , Powell J. A.
Published: March 2011

The concept of a “buffer” layer in the epitaxial growth of compound semiconductors on (001) silicon substrate is discussed on the basis of homogeneous and heterogeneous surface nucleation. Experimental results on the nucleation of β-SiC on (001) Si by Chemical Vapor Deposition (CVD) are presented and they are discussed in terms of the model for the growth of the buffer layer.
Characterization of Gaas/Si/GaAs Heterointerfaces
Authors: Liliental-Weber Zuzanna , Mariella Raymond P.
Published: March 2011

Transmission electron microscopy of GaAs grown on Si for metal-semiconductor-metal photodetectors is presented in this paper. Two kinds of samples are compared: GaAs grown on a 15 Å Si epilayer grown on GaAs, and GaAs grown at low temperature (300°C) on Si substrates. It is shown that the GaAs epitaxial layer grown on thin Si layer has reverse polarity to the substrate (antiphase relation). Higher defect density is observed for GaAs grown on Si substrate. This higher defect density correlates with an increased device speed, but with reduced sensitivity.
Coherency Strain of an Overgrown Island
Authors: Lee J. K. , Hackney S. A.
Published: March 2011

The lattice misfit strain in an overgrown island is considered to be accommodated by twodistinctive domains; a pure coherency domain (ε domain) and a domain of misfit dislocations (δ domain). By introducing such two different constituents, the model predicts the transition condition from a “single phase” state (ε phase) to a “two-phase mixture” (ε+δ) as a function of misfit strain. Further, as in the chemical thermodynamics of a binary alloy system, energy vs. misfit strain diagrams allow us to understand possible existence of various metastable states which may be associated with an overgrowth.
Rheed Observation of Lattice Relaxation During Ge/Si(O01) Heteroepitaxy
Authors: Miki Kazushi , Sakamoto Kunihiro , Sakamoto Tsunenori
Published: March 2011

We report the dynamic RHEED (reflection high energy electron diffraction) observation during Ge/Si(001) heteroepitaxy at various growth temperatures. The RHEED intensityanalysis and the in-plane lattice constant analysis reveal a growth fashion and lattice relaxation. Both of them depend strongly on growth temperature.
Defects and Strain in GexSi1−x Layers Grown by Rapid Thermal Processing Chemical Vapor Deposition
Authors: Jung K. H. , Kim Y. M. , Chun H. G. , Kwong D. L. , Rabenberg L.
Published: March 2011

We have grown single and multi-layer epitaxial GexSi1−x/Si structures by RTPCVD on (100)Si substrates using GeH4 and SiH2Cl2 at 900°C and 1000°C with SiH2Cl2:GeHH4 ratios of 14:1 to 95:1 at 5 Torr. Plane view TEM micrographs indicate misfit dislocation free layers were grown for Ge concentrations of up to 13%. Misfit dislocation networks aligned along <110> were formed at the interface of films with higher Ge concentrations. Plane view TEM micrographs also showed dislocation loops at the interface. When the SiH2C12:GeH4 ratio used was less than 25:1, the GexSil−x layer grew by three-dimensional nucleation, resulting in a high density of defects.
Creation of Interface States at the Silicon/Silicon Dioxide Interface by UV Light Without Hole Trapping
Authors: Schubert W. K. , Seager C. H. , Brower K. L.
Published: March 2011

Photoinjection of electrons into silicon dioxide in metal-oxide-semiconductor (MOS) capacitors with 3.5 eV light is shown to create interface states with no apparent hole trapping precursor. The creation rate of these interface states depends strongly upon whether injection is from the gate metal or the silicon substrate, and on the forming gas annealing sequence used to passivate growth-induced interface states. A mechanism involving electron-induced release of hydrogen in the oxide is consistent with some aspects of the data.
Molecular Beam Epitaxy on the (NH4)2Sx-Treated Surface of GaAs
Authors: Oigawa H. , Kawabe M. , Fan J.-F. , Nannichi Y.
Published: March 2011

We have found that treatment with a solution of ammonium sulfide containing excess sulfur [(NH4) 2Sx] produced a stabilized surface of GaAs. The treated surface is covered with a monomolecular layer of sulfur, and oxygen atoms are prohibited from adsorbing chemically on this surface. We checked the durability of the treated surface to heat treatment to find that it was stable up to more than 500 °C. Epitaxial growth of an Al film was demonstrated on the (NH4) 2Sx-treated surface. The presence of sulfur atoms at the interface by this treatment was found to suppress the chemical reaction between the metal and GaAs. Low temperature GaAs epitaxy was demonstrated on the sulfide treated surface without conventional heat treatment. The surface treatment correlates with changes in Schottky barrier height with various metals, which suggests that the surface states of GaAs are decreased remarkably.
Preparation of Si Thin Films by Spontaneous Chemical Deposition
Authors: Hanna Jun-Ichi , Kamo Akira , Komiya Tohru , Nguyen Hien D. , Shimizu Isamu , Kokado Hiroshi
Published: March 2011

A novel method for preparing photoconductive Si thin films termed “Spontaneous Chemical Deposition”, is proposed, in which silane is decomposed spontaneously by gas phase reactions with fluorine at reduced pressure. With the external parameters in the gas phase reaction such as a gas flow ratio of SiH4 to F2 and the reaction pressure and temperature, the Si-network structure of the films can be controlled intentionally, resulting in a reduction of the hydrogen content, CH and a variety of the films from “amorphous” to “microcrystalline”.
Equilibration Kinetics in Interstitially Doped a-Si:H
Authors: Winer K. , Street R. A.
Published: March 2011

The time dependence of the dc conductivity of Li- and Be-doped a-Si:H after thermal quenching is reported. The equilibration kinetics, similar to that observed in substitutionally-doped a-Si:H, is characterized by stretched exponential decays and activated time constants. The equilibration times for Bedoped a-Si:H were too short (< 1 min) for the kinetics of equilibration to be accurately measured. In Li-doped a-Si:H, the equilibration time constants were longer than those in 1% P-doped a-Si:H, which is due to the smaller carrier concentrations in the Li-doped a-Si:H films.
Growth of Crystalline Silicon, Microcrystalline and Epitaxial at Low Substrate Temperature
Authors: Tanabe H. , Azuma M. , Uematsu T. , Shirai H. , Hanna J. , Shimizu I
Published: March 2011

Both microcrystalline and epitaxially grown Si thin films were prepared at low substrate temperature from different precursors under control of atomic hydrogen. With the precursors, SiHn (n≤3), generated by plasma-induced decomposition of Sil4, microcrystalline Si was formed through the island-like clusters with the aid of atomic hydrogen, while two-dimensional growth was caused with the precursors, SiHnFm (n+m≤3) generated from SiF4.
Steady-State Photoconductivity in Undoped Amorphous Silicon
Authors: Liu Jeffrey Zhaohuai , Wagner S.
Published: March 2011

An analytical expression for the thermal activation energy of the steady-state photoconductivity is shown to agree with experimental data in a range of temperature and generation rate for undoped hydrogenated amorphous silicon (a-Si:H). This agreement supports our suggestion that the commonly observed small activation energy of the photoconductivity in undoped a-Si:H originates in the strong temperature dependence of the quasi-Fermi level for electrons.
Development of Spice Models for Amorphous Silicon Thin-Film Transistors
Authors: Hack M. , Shaw J. G. , Shur M.
Published: March 2011

In this paper we describe a new analytic model for both the current-voltage and capacitance-voltage characteristics of amorphous-silicon thin-film transistors. This analytic model has been incorporated into a circuit simulation program (SPICE) to provide an accurate comprehensive three terminal model for amorphous-silicon thin-film transistors. We present results showing good agreement between circuit simulations based on this new device model and experimental data. The development of amorphous silicon SPICE simulation tools increases the design accuracy of advanced analog and digital circuits.
A-Si FETs With Improved On/Off Characteristics
Authors: Uchida Yasutaka , Matsumura Masakiyo
Published: March 2011

This paper describes the experimental and theoretical results of Distributed Threshold Voltage FETs. Based on these results important advantages of DTV FET are clarify and a novel device structure has been proposed.
Theory of Vertical Amorphous Silicon Thin-Film Transistors
Authors: Shaw J. G. , Hack M.
Published: March 2011

We describe a vertical amorphous silicon thin-film transistor which is easy to fabricate and has a very short channel length that is determined by deposition, not lithography. Our vertical TFTs are compatible with large-area processing techniques andd have suitable terminal characteristics for use in practical circuits. Unlike a conventional thin-film transistor, the current path is primarily parallel to the electric field created by an insulated gate electrode. A two-dimensional computer program is used to analyze these devices and guide their design and optimization. We show how to suppress excessive leakage currents and improve the saturation of the output characteristics by a novel current-blocking technique.
Degradation of High and Low Voltage Amorphous Silicon Thin Film Transistors Due to Air Leak
Authors: Martin Russel A. , Tsai C. C.
Published: March 2011

Amorphous Silicon TFT performance is shown to be strongly affected by an air leak into a plasma deposition system during film growth. The introduction of a controlled air leak into the system raises the oxygen content of the active layer. For both high and low voltage transistors (HVTFT & LVTFT) the drive current, FET mobility, and threshold voltage are degraded with increasing leak rate. Moreover, the stability of HVTFTs containing a space charge limited region is adversely affected by increasing leak rate.
Geometry Dependence of the Transport Parameters in Field Effect Transistors Made from Amorphous Silicon
Authors: Griep S.
Published: March 2011

Field effect transistors (TFTs) with different channel lengths L and widths W have been prepared to study the influence of the geometry on the characteristics of the transistors. The mobility μ and the threshold voltage Vth are determined from the √Ids (Uds) plot. Effective values of L and W can be determined by analyzing their dependence on geometry. It can be shown that parts of the amorphous silicon which are outside the area between the source and drain contacts contribute to the current. The reason for this is that the drain-source field spreads out into these regions. Taking this effect into account we obtain the values for the mobility μ. The part of the overlap contributing to the transistor current is smaller than 2 μm.
The Internal Photoemission of Electrons and Holes from Metals into Hydrogenated Amorphous Silicon
Authors: Hicks M. , Lee S. , Kumar Satyendra , Wronski C. R. , Pinarbasi M.
Published: March 2011

Internal photoemission is used to investigate the mobility edges in high quality, undoped, hydrogenated amorphous silicon (a-Si:H). The detailed studies carried out on intimate metal/ a- Si:H Schottky barriers are described and results on the electron barrier heights of these contacts formed on a-Si:H having different bandgaps are presented. The observed dependence of the barrier heights on changes in the optical gap due to hydrogen incorporation indicates that not all of these changes are due to the shifts of the valence band edges. The first results on the injection of holes into the valence band of a-Si:H are reported.
Detailed Study of Ion Bombardment in Rf Glow Discharge Deposition Systems: The Role of Helium Dilution
Authors: Cabarrocas P. Roca I
Published: March 2011

We present a detailed study of the variables (reactor geometry, gas pressure, rf power and silane dilution) which control the flux and energy of the ions impinging on the substrate in capacitively-coupled rf glow discharge systems. The ion flux and ion energy, measured with an electrostatic energy analyzer, were found to be largely dependent on the reactor geometry, which was quantified by the ratio of the area of the grounded surfaces Sg to the area of the rf electrode Sc. Special attention was paid to the effects of the dilution of silane in hydrogen, helium and argon. Helium and hydrogen dilution were found the most effective means to increase ion bombardment while argon dilution has little effect on the ion energy distribution. Furthermore, it is likely that ion bombardment at moderate energy (Eion < 70 eV) does not induce any serious degradation of the electronic properties of a-Si:H films.