Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern
Authors: Goto Tetsuya , Kuroda Rihito , Suwa Tomoyuki , Teramoto Akinobu , Akagawa Naoya , Kimoto Daiki , Sugawa Shigetoshi , Ohmi Tadahiro , Kamata Yutaka , Kumagai Yuki , Shibusawa Katsuhiko 
Published: February 2020

Atomically flattening of semiconductor/gate insulator interface has received much attention for complementary metal oxide semiconductor (CMOS) devices, because such smooth interface can increase field effect mobility by reducing interface roughness scattering of carriers [1,2], improve gate insulator reliability [3] and reduce amplitudes of low frequency noise such as 1/f noise and random telegraph noise (RTN) [3,4]. Because these improvements of CMOS device performances can be obtained independent of device miniaturization, the atomically flattening technology becomes increasingly important as the device miniaturization approaches its physical limit. Atomically flat Si surface having atomic terraces and steps is known to be obtained by Ar or Ar/H2 annealing at temperature of 1100 ºC or higher [5]. However, such high temperature annealing leads to the reaction between Si and SiO2 [6], and thus, is not adequate to device fabrications where the device isolation pattern with thick SiO2 film exists on Si wafer. To introduce the atomically flattening technology to the existing CMOS process, low temperature atomically flattening Ar annealing has been developed, where flattening temperature could be decreased down to 850ºC or less by reducing O2 and H2O residue gases down to less than 30 ppb [7]. Recently, we reported that by introducing this low temperature Ar annealing at 850ºC, atomically flat Si surfaces of shallow trench isolation (STI)-patterned wafers was obtained, and not only the gate oxide reliability was improved, but also the RTN amplitude was reduced in nMOS transistors [4]. In this report, relating to the results obtained in Ref. 4, the atomically flattening effect of Si surface of device active patterns having STI edge was investigated in more detail.

Figs 1(a)-1(c) show atomic force spectroscopy (AFM) images of the Si surface of large active region (p-well, 500mm × 600mm), where (a) the controlled sample (without Ar annealing), (b) the sample with Ar annealing at 900 ºC and that at (c) 850 ºC are shown. The images were obtained just after the atomic flattening Ar annealing which was applied to the samples having STI pattern. Atomically flat Si surface was successfully obtained for 850 ºC annealing, while that was not obtained for 900 ºC annealing. The results suggest that, in the case of 900 ºC annealing, O2 and/or H2O were emitted from the SiO2 film and reacted with Si surface, degrading flattening effect. The results suggested the importance of lowering of annealing temperature to obtain atomically flat Si surface when SiO2 film exists on the wafer. Relatively smaller active areas with a size of 1.26mm × 3.03mm were also measured. Figs 2(a) – 2(c) shows bird’s eye views of isolation patterns obtained by AFM for (a) the controlled sample, (b) the sample with Ar annealing at 900 ºC and that at (c) 850 ºC. Also, Figs 2(d) – 2(f) shows the AFM images of Si surface of the inside of these active areas for (d) the controlled sample, (e) the sample with Ar annealing at 900 ºC and that at (f) 850 ºC. It was found from bird’s eye’s views that the shape anomaly at the active edge was not observed, demonstrating the advantage of the low temperature annealing which can suppress reaction between Si and isolation SiO2film.  Furthermore, in the case of 850 ºC annealing, atomically flat surface could be obtained. The surface roughness at the atomic terrace was the same level as the noise level (approximately 0.04 nm), while that was 0.07 nm for 900 ºC annealing and 0.13 nm for the controlled sample. The results demonstrated that the proposed low temperature and high purity atomically flattening Ar annealing is applicable to the existing CMOS process.

[1] S.Takagi et al., IEEE Trans. Electron Devices, 41 (1994) 2357.

[2] C. H. Lee et al., Tech. Dig., IEDM (2013) 13-32.

[3] R. Kuroda et al., IEEE Trans. Electron Devices, 56 (2009) 291.

[4] T. Goto et al., Extended Abstracts of SSDM2014 (2014) 670.

[5] Y. Matsushita et al., ECS Trans. 3 (2006) 159.

[6] R. Tromp et al., Phys. Rev. Lett. 55 (1985) 2332.

[7] X. Li et al., ECS Trans. 28 (2010) 299.

Figure 1