(Invited) In-Depth Understanding of the Key Contributors to the Total Flicker Noise in Advanced Logic Devices
Authors: Cretu Bogdan , Tahiat Abderrahim , Veloso Anabela , Simoen Eddy 
Published: February 2024

The aim of this work is to perform an in-depth analysis in order to identify the key contributors to the total flicker noise in advanced MOSFET technologies, e.g. UTBOX, FinFET or Gate-all-around (GAA) nanowire or nanosheet FET devices.

In this abstract, as an example, we will focus on p-type gate all around silicon vertical nanowire devices fabricated at imec. The transistors have a fixed gate length (LG) of 50 nm and 1200 nanowires in parallel (N), each nanowire (NW) having a diameter (WNW) of 20 nm. The total width (W) of the device is calculated as . The gate stack corresponds to an equivalent oxide thickness (EOT) of 0.9 nm. A full description of the process flow of the devices is presented in [1]. Comparison between the Y-function strategy of [2] and McLarty methodology [3] permits to estimate with accuracy the DC parameters necessary for low frequency noise modelling, which are summarized in Table 1.

Typical low frequency noise spectra are shown in Figure 1. The methodology for the estimation of the low frequency noise parameters is described in [4], but it is obvious that the noise spectra are dominated by 1/f noise and only few Lorentzian contributions appear for some gate voltage polarization. As the corresponding flicker noise levels (K
f
), plotted in Figure 2 present a plateau and rise with the increase of the applied gate voltage, the responsible 1/f noise mechanism should be related to the carrier number or correlated carrier number fluctuations mechanism, with a possible contribution of the access resistance 1/f noise.

Firstly, the model described in [5-9] expressed as in equation (1) is employed. A linear dependence of the square root of the 1/f noise levels on the measured Id/gm is observed in Figure 3, permitting to estimate from the intercept and slope the flat-band noise level (Svfb) and the W coefficient, respectively. Using the methodology of [9] the estimated W parameter is corrected by the access resistance influence. Good agreement with experimental data in strong inversion may be observed in both cases (Figure 4).

Secondly, the model which considers the small signal model of the MOSFET is used, assuming that the channel resistance noise and access resistances noise are uncorrelated noise sources [2,10,11]. The model may be expressed by equation (2) ((13) of [11]), in order to make no assumption concerning the gm/gch ratio. Beyond the threshold voltage, the impact of the cannot be neglected, as observed from Figure 5. It may be observed from Figure 6 that the correlated number fluctuation and mobility noise mechanism cannot explain the flicker noise behavior in very strong inversion, and an additional contribution of the access resistances noise may be considered in order to agree with the experimental data.

The noise parameters estimated to agree with the experimental data for both models are summarized in Table 2. It is interesting to note that the experimental data may be explained by both models, but the key contributors are not the same: only correlated number fluctuations and mobility noise mechanism for the first model, and correlated number fluctuations and mobility and access resistance noise mechanisms contribution for the second one. Moreover, the estimated flat-band noise levels are not the same, a much lower Svfb is obtained when the first model is employed. Considering the access resistance impact may correct the W coefficient, but leads to even lower flat-band noise levels, as already reported in [9].

These results lead to some questioning about which of these two models is most accurate and give good indications on the key contributors and estimated parameters of the total flicker noise.

References:

[1] E. Simoen et al., Solid-State Electron, 2023, 200, DOI: 10.1016/j.sse.2022.108576.

[2] B. Cretu et al., IEEE Trans. Electron Dev., 2023, 70(1), 254-260, DOI: 10.1109/TED.2022.3225248.

[3] P.K. McLarty et al., Solid-State Electron, 1995, 6, 1175-1177, DOI: 10.1016/0038-1101(94)00248-E

[4] D. Boudier et al., Solid-State Electronics, 2019, 168, DOI : 10.1016/j.sse.2019.107732.

[5] E. G. Ioannidis et al., Solid-State Electron., 2012, 76, 54–59, DOI: : 10.1016/j.sse.2012.05.035.

[6] C. G. Theodorou et al., IEEE Trans. Electron Dev., 2014, 61(2), 1161-1167, DOI: 10.1109/TED.2014.2307201.

[7] E. G. Ioannidis et al., IEEE Trans. Electron Dev., 2015, 62(5), 1574-1579, DOI: 10.1109/TED.2015.2411678.

[8] A. Tataridou et al., in Proc. IEEE 33rd Int. Conf. Microelectron. Test Struct. (ICMTS), 2020, DOI: 10.1109/ICMTS48187.2020.9107908.

[9] A. Tataridou et al., IEEE Trans. Electron Dev., 2020, 67(11), 4568-4572, DOI: 10.1109/TED.2020.3026612.

[10] D. Boudier et al., Solid-State Electron, 2017, 128, 102-108, DOI: 10.1016/j.sse.2016.10.012.

[11] B. Cretu et al., Solid-State Electron, 2023, 201, DOI: 10.1016/j.sse.2023.108591

Figure 1