bluuebunny/crossref_metadata_2025 huggingface dataset:
(ZrO2)x(La2O3)1-x Alloy as High-k Gate Dielectric for Advanced CMOS Devices
Authors: Chen Lun-Lun , Hou Chin-Yao , Wu Jia-Rong , Wu Min-Lin , Lyu Rong-Jhe , Wu Yung-Hsien
Published: October 2010

An amorphous (ZrO2)x(La2O3)1-x alloy formed by deposition of ZrO2/La2O3/ZrO2 laminate and a subsequent annealing was employed as the gate dielectric for MOS devices and the impact of a SiON interfacial layer on device performance was also explored in this work. The (ZrO2)x(La2O3)1-x alloy is found to have a high k value of 26.9 and tiny amount of bulk traps, both of which are very desirable for advanced high-k gate dielectrics. In addition, it is observed that the thermally grown SiON interfacial layer can prevent the formation of a silicide (ZrSi) and/or lower-k silicate (ZrSiO4) film during the subsequent annealing, which would cause poor interfacial qualities. By integrating the (ZrO2)x(La2O3)1-x alloy and SiON interfacial layer, MOS devices demonstrate a leakage current of 3×10-9 A/cm2 at gate voltage (Vg) of -1 V with EOT of 2.31 nm and this performance is superior to other high-k gate dielectrics.
Liquid Injection MOCVD Grown Binary Oxides and Ternary Rare-Earth Oxide as Alternate Gate-Oxides for Logic Devices
Authors: Thomas Reji , Ehrhart Peter , Waser Rainer , Schubert Jürgen , Devi Anjana , Katiyar R.S.
Published: October 2010

ZrO2, HfO2 and DyScO3 thin films having thickness in the range 2-20 nm were grown on SiOx/Si(100) substrates in a multi-wafer planetary MOCVD reactor combined with a liquid delivery system using engineered precursors. Growth rate, surface morphology, crystal structure, crystal density of the as-deposited films were analysed as a function of deposition temperature. The influence of post deposition annealing on the densification and crystallization was studied. Electrical properties of MIS capacitor structures are also discussed. Results on the optimised gate stack of Pt/ZrO2/SiOx/Si, Pt/HfO2/SiOx/Si, Pt/DyScO3/SiOx/Si are finally compared; and DyScO3 seems to be promising high-k material candidate compared to Group-IVB oxides for the coming technology nodes.
Electrical Properties of LaLuO3/Si(100) Structures Prepared by Molecular Beam Deposition
Authors: Gomeniuk Yuri Y. , Gomeniuk Yuri V. , Nazarov Alexei N. , Hurley Paul K. , Cherkaoui Karim , Monaghan Scott , Gottlob Heiner , Schmidt Mathias , Schubert Jürgen , Lopes J. Marcelo. J , Engström Olof
Published: October 2010

The paper presents the results of electrical characterization in the wide temperature range (120 - 320 K) of the interface and bulk properties of high-k LaLuO3 dielectric deposited by molecular beam deposition (MBD) on silicon substrate. The energy distribution of interface state density is presented and typical maxima of 1.2×1011 and 2.5×1011 eV-1cm-2 were found at about 0.25 - 0.3 eV from the silicon valence band. The charge carrier transport through the dielectric at the forward bias was found to occur via Poole-Frenkel mechanism, while variable range hopping conduction (Mott's law) controls the current at the reverse bias.
The Effect of Hf/(Hf+Si) Ratios in Hf1-xSixOy Dielectric Film on Physical and Electrical Stabilities
Authors: Kim Hyo Kyeom , Jung Hyung-Suk , Jang Jae Hyuck , Lee Sang Young , Hwang Cheol Seong
Published: October 2010

Hf1-xSixOy (HfSiO) gate dielectrics with a wide range of Si composition are grown by an atomic layer deposition (ALD). The Si composition in HfSiO films can be tailored with precision by manipulating the ALD sub-cycle sequence of Hf and Si precursors. Through this method, the effects of Si composition of HfSiO films on the physical and electrical properties are investigated with different thermal budget. Si incorporation into HfO2 delays the crystallization of the films, which improved the leakage current characteristics. However, it also increases capacitance equivalent oxide thickness values due to the increased SiO2 content which has a relatively lower dielectric constant. By optimizing the Si composition, high quality HfSiO gate dielectrics having comparable insulator properties to HfO2 but improved thermal stability were achieved
Effect of Remote-Surface-Roughness Scattering on Electron Mobility in MOSFETs with High-k Dielectrics
Authors: Mamatrishat Mamat , Kouda Miyuki , Kawanago Takamasa , Kakushima K. , Ahmet P. , Aierken Abuliemu , Tsutsui K. , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Iwai H.
Published: October 2010

In this paper, we developed a model for remote surface roughness scattering (RSR)-limited electron mobility in the inversion layer of nMOSFETs with high-k dielectrics. A Numerical method is applied to calculate RSR-limited electron mobility. It has been demonstrated that the RSR-limited electron mobility is highly degraded in the high electric field region.
(Invited) Electron Spectroscopic Measurements of Band Alignment in Metal/Oxide/Semiconductor Stacks
Authors: Rangan Sylvie , Bersch Eric , Bartynski Robert , Garfunkel Eric , Vescovo Elio
Published: October 2010

Valence and conduction band edges of ultra-thin oxides (SiO2, HfO2, Hf0.7Si0.3O2 and Al2O3 grown on silicon) and their shifts upon sequential metallization with three metals (Ru, Ti and Al) have been measured using synchrotron radiation-excited x-ray photoemission, ultra-violet photoemission and inverse photoemission. From these techniques, the offsets between the valence and conduction band edges of the oxides and the metal gate Fermi edge have been directly measured. Upon metallization, consistent shifts of the oxides band edges and core levels are measured, due to the creation of interface dipoles at the metal/oxide interfaces. Using the energy gap, the electron affinity of the oxides and the metal workfunctions that have been directly measured on theses samples, the experimental band offsets are compared to those predicted by the induced gap states model.
Electrical Characterization of ALD ZnO and HfO2 Thin Films
Authors: Tapily Kandabara , Raj A. Sneha , Gu Diefeng , Baumgart Helmut , Rozgonyi George
Published: October 2010

ALD ZnO was deposited at 150oC and HfO2 was deposited at 250oC. The deposition rate for ZnO was calculated to be 2 Aå/cycle and that of HfO2 was found to be 1 Aå/cycle. A 4nm thick film of HfO2 was deposited on 400 nm of ALD ZnO as well as on a reference bulk single crystal ZnO. The Hall measurements revealed an n-type carrier concentration of~1.7 x1019cm-3 and a mobility of 24cm2/V-s for the 400nm as-deposited ALD ZnO. Four-point was used to measure the electrical properties of ALD ZnO.
(Invited) Identity of the Conducting Nanofilaments in TiO2 and the Resistance Switching Mechanism of TiO2/NiO Stacked Layers
Authors: Kim Kyung Min , Kwon Deok Hwang , Jang Jae Hyuck , Lee Min Hwan , Song Seul Jie , Kim Gun Hwan , Seok Jun Yeong , Lee Bora , Han Seungwu , Kim Miyoung , Hwang Cheol Seong
Published: October 2010

The resistance switching (RS) behaviors of TiO2 and TiO2/NiO thin films were examined. The presence of conductive nano-filaments was confirmed directly by high-resolution transmission electron microscopy (HRTEM) in a Pt/TiO2/Pt system. The HRTEM images identified Magnéli structured filaments (mostly Ti4O7 phase) of both set and reset states. The local electrical properties were confirmed by in-situ current-voltage measurements in HRTEM. The in-situ HRTEM observation confirmed the structural change of the filament during set and reset switching. The RS behaviour of a stacked material composed of n-type TiO2 and p-type NiO was also examined. The switching time could be decreased by ~ 1,000 times compared to the single layer material by stacking the two layers.
Interface Analysis of MIM Capacitor Using ZrN Electrodes and ALD-ZrO2 Dielectrics
Authors: Choi Jae Hyoung , Kim Younsoo , Lim Jae Soon , Park Min Young , Chung Suk-Jin , Kang Sang Yeol , Cho Kyuho , Yoo Cha Young , Moon Joo Tae , Lee Hyung Ik , Kim Ki Hong , Choi Hye Ran , Chung Jaekwan
Published: October 2010

New Metal/Insulator/Metal (MIM) capacitors using ZrN electrode and ALD-ZrO2 dielectric were examined for future DRAM capacitor application. The leakage current density of the capacitors using ZrN bottom electrodes shows no degradation compared to the capacitors using TiN bottom electrodes. However, equivalent oxide thickness (Toxeq.) value of TIZ capacitor was increased about 60% compared to that of TIT capacitor. Although the calculating dielectric constant values of ZrO2 on TiN and ZrN electrode showed no significant difference, the non-zero y-axis intersect around 5.5Aå from Toxeq. variation as a function of the physical thickness of the ZrO2 films suggests an interfacial layer with the low dielectric constant at the interface. XRD and HRTEM image showed that an interfacial Zr2ON2 layer was formed at the ZrN/ZrO2 interface, which might contribute the Toxeq. increase of TIZ-ZrO2 capacitor during the ALD-ZrO2 deposition and rapid thermal anneal step.
Combinatorial Investigation of ZrO2-Based Dielectric Materials for DRAM Capacitors
Authors: Kiyota Yuji , Iwashita Yuji , Itaka Kenji , Adachi Tetsuya , Chikyow Toyohiro , Ogura Atsushi
Published: October 2010

We investigated ZrO2-based new dielectric materials for random access memory by pulsed laser deposition (combi-PLD). We found that substitution of yttrium (Y) to ZrO2 system suppressed the leakage current effectively. MIM capacitor property of the promising composition candidates found in this system showed leakage current density less than 5×10-7 A/cm2 and the dielectric constant was 20. In addition, substitution of titanium (Ti) and tantalum (Ta) caused the dielectric constant up to ~ 22 within the allowed leakage level as well as 5×10-7 A/cm2 . Zr-Y-Ti-O and Zr-Y-Ta-O system have a potential for high dielectric materials as a new material of DRAM capacitors instead of SiO2.
(Invited) Buried-Channel In0.7Ga0.3As MOSFETs and Vertical In0.7Ga0.3As Tunneling FETs for beyond CMOS Applications
Authors: Lee Jack , Zhao Han , Chen Yen-Ting , Wang Yanzhen , Xue Fei , Zhou Fei
Published: October 2010

We have fabricated buried-channel In0.7Ga0.3As MOSFETs with Al2O3 and HfO2 gate oxide. In0.7Ga0.3As MOSFETs using InP/InAlAs double-barrier achieve mobility enhancement at both low-field (68% at peak ueff) and high-field (55%) compared to no barrier. High channel mobility of 4889 cm2/Vs has been obtained using Al2O3 oxide and 3722 cm2/Vs using HfO2 gate oxide, which is amongst the highest ueff reported. We have also demonstrated vertical In0.7Ga0.3As tunneling FETs (TFETs) with SS of 96mV/dec, Ion/Ioff>106 and Ion of 55uA/um with HfO2 oxide (EOT=1.4 nm).
(Invited) First-Principles Investigation of High-k Dielectrics for Nonvolatile Memories
Authors: Pourtois Geoffrey , Sankaran Kiroubanand , Radu Iuliana , Degraeve Robin , Zahid Mohammed B. , Van Elshocht S. , Adelmann Christoph , De Gendt S. , Heyns Marc M. , Wouters Dirk J. , Kittl Jorge A. , Jurczak Malgorzata , Rignanese Gian-Marco , Van Houdt Jan
Published: October 2010

Using first-principles simulations, we investigate the electronic and dielectric properties of a set of oxides eligible for non-volatile memory applications. We show that aluminum oxide and rare earth based aluminates have promising properties in terms of band gap, dielectric constant and are potential candidates for the replacement of SiO2 for flash applications.
(Invited) Performance and Reliability of Nanocrystals Embedded High-k Nonvolatile Memories
Authors: Kuo Y.
Published: October 2010

The nanocrystals embedded high-k dielectric structure is promising for the high-density nonvolatile memories. In this paper, the author discussed the performance and reliability of MOS capacitors composed of various nanocrystalline ITO, ZnO, and RuO embedded zirconium doped HfO2 high-k dielectrics. This kind of device is easily fabricated with thin film deposition methods. Material properties of the embedded nanocrystals are critical to device's memory functions and reliability, such as the charge trapping characteristics and the breakdown mechanism.
(Invited) Identification of Intrinsic Point Defects at GexSi1-x/Oxide Interfaces by ESR Probing
Authors: Stesmans André , Nguyen A. P. D. , Afanas'ev Valeri V. , Lieten R. R. , Borghs Gustaaf
Published: October 2010

We report on the obvervation by electron spin resonance (ESR) of two paramagnetic Ge dangling bond (DB)-type defects at Ge/oxide interfaces. One, detected in SiO2/(100)GexSi1-x/SiO2/Si hetero-structures grown by the condensation method, exhibits monoc-linic-I (C2v) symmetry, with principal g values g1=2.0338(3), g2=2.0386(6), g3=2.0054 and g3 axis (DB) direction 24{plus minus} 2{degree sign} off a <111> direction towards the [100] interface normal. The defect reaches maximum densities for x~0.7, to disappear for x{less than or equal to}0.45 and x{greater than or equal to}0.87. It is suggested to concern a Ge Pb1-type center, i.e., not a trigonal basic Ge Pb(0)-type center (Ge3≡Ge•), thus exposing a unique interface mismatch adaptation as function of substrate Ge fraction. The second one, observed at the interface of epitaxially grown Ge3N4/(111)Ge entities with nm-thin Ge3N4 layers, shows trigonal (C3v) symmetry characterized by g//~2.0023 and g⊥~2.0032. Based on comparision of its salient ESR features with previous theoretical results, the defect is suggested to concern the Ge K center.
Study of HfO2/Si/Strained-Ge/SiGe Using Angle Resolved X-ray Photoelectron Spectroscopy
Authors: Komatsu Arata , Nasu Kentarou , Hoshi Yusuke , Kurebayashi Toru , Sawano Kentarou , Myronov Maksym , Nohira Hiroshi , Shiraki Yasuhiro
Published: October 2010

We have investigated the influence of Si-cap layer and the post deposition annealing (PDA) on compositional depth profiles and chemical structures of HfO2/Si-cap/strained Ge/SiGe/Si interfaces by angle-resolved X-ray photoemission spectroscopy. Analyses of Ge 2p, Si 1s and O 1s spectra show that strained-Ge layer was oxidized during the deposition of HfO2 in the case of 1 nm in thickness of the Si cap layer and that Ge layer was not oxidized in the case of 3nm and 5nm in thickness of the Si cap layer.
Effect of Thermal Treatments on HfO2/In0.7Ga0.3As Metal-Oxide-Semiconductor Capacitor Characteristics
Authors: Chang Chia-Hua , Shie Tin-En , Lin Yueh-Chin , Kakushima K. , Iwai H. , Lu Po-Ching , Lin Ting-Chun , Huang Guan Ning , Chang Edward Yi
Published: October 2010

Post deposition annealing is a critical process for the quality improvement of gate oxides on - MOS capacitors. Though high temperature annealing would effectively repair defects, it could also induce undesired electrical characteristics due to the crystallization of the gate oxide. In this work, we investigate the novel two steps annealing technique to improve the HfO2/In0.7Ga0.3As MOSCAP properties. The two steps process takes advantage of 1st high temperature annealing (550°) to improve the interface quality and 2nd low temperature annealing (450°) for curing bulk oxide without oxide crystallization. The two steps annealing technique greatly improves the HfO2/In0.7Ga0.3As properties as compared to single step process and is expected to be helpful for future - MOSFET development.
Investigation of Surface Channel InGaAs MOSFETs with Al2O3 and ZrO2 ALD Gate Dielectric
Authors: Xue Fei , Zhao Han , Chen Yen-Ting , Wang Yanzhen , Zhou Fei , Lee Jack
Published: October 2010

This paper studies In0.53Ga0.47As and In0.7Ga0.3As surface channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with atomic layer deposition (ALD) of Al2O3 and ZrO2. This work systematically compared performance of InGaAs channel device with different Indium percentage. This includes drain current, transconductance, subthreshold swing, interface trap density and reliability. For both oxide systems, In0.53Ga0.47As channel MOSFETs show better subthreshold swing (125mV/dec versus 160mV/dec for Al2O3 EOT=4.4nm) and higher transconductance than In0.7Ga0.3As channel MOSFETs. Interface trap density measured by conductance method (1.08×1012 eV-1cm-2 versus 3.24×1012 eV-1cm-2 for Al2O3) also suggests that interface between In0.53Ga0.47As substrate and Al2O3 (or ZrO2) high-k dielectric is better than that of In0.7Ga0.3As.
Atomic-Layer-Deposition HfO2-Based InP n-Channel Metal-Oxide-Semiconductor Field Effect Transistor Using Different Thicknesses of Al2O3 as Interfacial Passivation Layer
Authors: Wang Yanzhen , Zhao Han , Chen Yen-Ting , Xue Fei , Zhou Fei , Lee Jack
Published: October 2010

The effects of ALD deposited HfO2 as the gate dielectric devices on InP substrate using different thicknesses of Al2O3 (5 cycles and 10 cycles respectively) as interfacial passivation layer (IPL) have been investigated. Without Al2O3 as the IPL, MOSFET devices with 50 cycles of HfO2 gate dielectric (with an EOT about 1.3 nm) has a subthreshold swing about 108 mV/dec and drive current 7.87 mV/mm at Vd= 2.5 V, and Vg=Vth+2 V for 20 μm gate length. Compared with single HfO2, the use of Al2O3 as interfacial layer results in better interface quality with the InP substrate. For stacked 10 cycles Al2O3/18 cycles HfO2 devices (EOT also about 1.3 nm), substhreshold swing is decreased to 92.5 mV/dec, and drive current is increased to 20.59 mA/mm at Vd= 2.5 V, and Vg=Vth+2 V for 20 μm gate length.
(Invited) A Study of Dielectric Breakdown Mechanisms in MG/HK MISFETs: From the Viewpoint of TDDB Statistics
Authors: Hirano Izumi , Kato Koichi , Nakasaki Yasushi , Fukatsu Shigeto , Sato Motoyuki , Inumiya Seiji , Goto Masakazu , Sekine Katsuyuki , Mitani Yuichiro
Published: October 2010

The Time Dependent Dielectric Breakdown mechanisms of n/p-FETs having high-k gate dielectrics have been studied through the Weibull distribution. From the thickness dependence of Weibull beta, it is found that the breakdown in n-FETs and p-FETs is mostly determined by the breakdown of high-k layer and interfacial layer (I.L.), respectively. Furthermore, Weibull beta in p-FETs is found to be independent of the injected carrier ratio (Jhole/Jelectron) while those in n-FETs strongly depend on this ratio. Improvement of Weibull beta through the control of the injected carrier ratio together with metal gate application leads to extremely longer lifetime in n-FETs. Improvement of average Tbd through the control of hydrogen concentration in high-k leads to longer life time also in p-FETs.
The Effect of Nitrogen in HfOxNy and ZrOxNy on Dielectric Properties and BTI Characteristics
Authors: Jung Hyung-Suk , Kim Hyo Kyeom , Kim Jeong Hwan , Lee Sang Young , Park Jung-Min , Kim Weon-Hong , Song Min-Woo , Lee Nae-In , Hwang Cheol Seong
Published: October 2010

The effect of nitrogen incorporation on the dielectric properties and bias temperature instability characteristics of HfOxNy and ZrOxNy were investigated. The incorporated nitrogen induces a reduction in the capacitance equivalent oxide thickness value, increases the leakage current, and causes the turn around of Vth shift under the positive bias stress in nMOSFET. In addition, compared to HfOxNy, ZrOxNy shows a significantly lower initial Vth shift under positive gate stress due to the lower number of shallow bulk traps related to oxygen vacancies.
TiN Capping Effect on High Temperature Annealed RE-Oxide MOS Capacitors for Scaled EOT
Authors: Kitayama Daisuke , Koyanagi Tomotsune , Kakushima K. , Ahmet P. , Tsutsui K. , Nishiyama Akira , Sugii Nobuyuki , Natori Kenji , Hattori T. , Iwai H.
Published: October 2010

The effect of TiN capping on high temperature annealed W gated La2O3 dielectrics capacitors has been characterized. The increase in EOT has been well suppressed with TiN capping and a 0.55 nm EOT has been achieved even after an 900 oC annealing. The electrical characterization has revealed a significant reduction in the capacitance-voltage (C-V) hysteresis and leakage current density when the annealing temperature is 900 oC or higher.
Leakage Current in TiN/HfO2/TiN MIM Capacitors and Degradation Due to Electrical Stress
Authors: Cimino Salvatore , Padovani Andrea , Larcher Luca , Afanas'ev Valeri V. , Hwang Hyeon Jun , Lee Young Gon , Jurczak Malgorzata , Wouters Dirk J. , Lee Byoung Hun , Hwang Hyunsang , Pantisano Luigi
Published: October 2010

Electrical characteristics of TiN/HfO2/TiN capacitors have been investigated by means of leakage current and Random Telegraph Noise measurements. Trap assisted transport simulation allowed the extraction of relevant parameters like trap density and trap energy position. The extracted parameters show striking similarities with those reported for HfO2 deposited on a Si surface (i.e., MOSFET applications). Additionally, even low bias Constant Voltage Stress was found to induce leakage current degradation on current vs voltage characteristics, preferentially at low voltage. The leakage current degradation is explained by preexisting defect precursors or by involvement of hydrogen in creating defects as observed on thermal SiO2 layers.
(Invited) An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization
Authors: Di Cioccio Lea , Gueguen P. , Taibi R. , Landru Didier , Gaudin G. , Chappaz C. , Rieutord François , De Crecy F. , Radu Ionut , Chapelon L. , Clavelier Laurent
Published: October 2010

An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, XRR, XRD and TEM analysis. Dedicated characterization techniques for such bonding are presented.
3D Assembly Using Au-Si Eutectic and Au-Au Thermocompression Wafer Level Bonding for M(O)EMS Device Fabrication
Authors: Lani Sebastien , Canonica Michael , Bayat Dara , Ataman Caglar , Noell Wilfried , De Rooij Nico
Published: October 2010

The purpose of this study was to determine solutions of 3D wafer level assembly for M(O)EMS structures. Validation of the concept will be done by realizing the assembly of a micro mirrors array which is at the present time assembled at chip level with silver glue (assembly and electrical interconnection). The actual bonding surface is around 5x8 μm2 and the release of mirrors is done before assembly. In this study we will first identify a wafer bonding solution that is compatible with the release process and later applying it to the mirror bonding design in order to verify the compatibility. Two bonding processes were identified as good candidate for this application: Au/Si eutectic and Au/Au thermocompression bonding. For the two processes, a preliminary study was realized to determine bonding parameters, design possibility (minimum bonding surface, density, pitch size) and compatibility with release process (SiO2 etching).
Characterization and Mechanical Reliability Evaluation of Gold Polysilicon Eutectic Bonded Wafers
Authors: Flynn Michael , Saeidi Nooshin , Byun Ki Yeol , Yu Ran , Ferain Isabelle , Colinge C. , Demosthenous A. , Donaldson N.
Published: October 2010

Reliability characterization is a key component to transfer any technology to volume manufacturing. To ensure a product meets quoted lifetimes, reliability characterization must be carried out thus testing both the package and the encapsulated system. Several packaging technologies have been developed for hermetic sealing of sensors or micro mechanical systems to protect them from the environment in which they operate. Gold (Au) - Polysilicon (pSi) eutectic bonding is a process used to hermetically seal such sensitive microelectronic devices at a wafer level prior to standard assembly. In this paper the analysis undertaken on wafers bonded using the Au-pSi technique are presented and the results examined.
Novel Test Structures for Hermeticity Testing of Wafer Bonding Technologies
Authors: Schneider Arnold , Rank Holger , Müller-Fiedler Roland , Wittler Olaf , Reichl Herbert
Published: October 2010

Many Micro-Electro-Mechanical System (MEMS) devices such as gyroscopes, accelerometers, infrared uncooled arrays, radio frequency (RF) resonators etc. require vacuum packaging. In this paper novel MEMS resonators designed as double ended tuning forks (DETF) with pressure sensitive quality factor are presented. The study of different DETF-designs clearly identified the strucutres' ability to monitor the inside cavity pressure of hermetically sealed micro packages. Therefore a new test vehicle for the development and long-time reliability of hermetic wafer bonding technologies can be provided.
Bonding of ALD Alumina for Advanced SOI Substrates
Authors: Suni Tommi , Puurunen Riikka L. , Ylivaara Oili , Kattelus Hannu , Henttinen Kimmo , Ishida Tadashi , Fujita Hiroyuki
Published: October 2010

Silicon-on-insulator (SOI) substrates have become important starting materials for IC and MEMS fabrication. In some cases, it would be beneficial to add another buried material(s) or to replace the silicon dioxide film. Atomic layer deposition (ALD) is a method to fabricate uniform thin films with well defined thickness. We have studied direct bonding of ALD alumina (Al2O3) thin films and possibilities to use it as an insulating material in tailored SOI wafers. From bonded wafer pairs the amount of voids and bond strength were measured. We also observed the bonded interface with cross sectional transmission electron microscopy (TEM). It appears that ALD Al2O3 can be used as a buried layer in novel SOI substrates.
Novel Application of Wafer-Bonded MultiSOI: Junctionless Nanowire Transistors for CMOS Logic
Authors: Wessely Frank , Krauss Tillmann , Schwalke Udo
Published: October 2010

In this paper, we report on the fabrication and characterization of voltage-programmable (VP) nanowire (NW) field-effect-transistor (FET) devices suitable to enhance the flexibility in circuit design, such as of reconfigurable logic. Silicon NW-structures with mid-gap Schottky S/D junctions on silicon-on-insulator (SOI) substrate were fabricated performing as unipolar CMOS-like transistors. The desired device type, i.e. NMOS or PMOS, is programmed by application of a certain back-gate voltage. The programming capabilities of the devices fabricated using this approach are demonstrated experimentally using a VP-NW-CMOS inverter circuit on a multi-SOI-substrate like set-up.
(Invited) Techniques for the Dry Transfer of Epitaxial Graphene onto Arbitrary Substrates
Authors: Caldwell Joshua D. , Anderson Travis , Hobart K. D. , Jernigan Glenn , Culbertson James , Kub Fritz , Tedesco Joseph , Hite Jennifer , Mastro Michael , Tadjer M. J. , Myers-Ward Rachael , Eddy Charles , Campbell Paul , Gaskill D. Kurt
Published: October 2010

Graphene can be formed via a variety of methods, each providing various benefits. Epitaxial graphene (EG) grown on the carbon-face of SiC has been shown to exhibit high carrier mobilities, in comparison to other growth techniques, while remaining amenable to wafer-scale graphene fabrication. Therefore, the transfer of large area (>mm2) graphene films to substrates amenable for specific applications is desirable. We demonstrate the dry transfer of EG from the C-face of 4H-SiC onto SiO2, GaN and Al2O3 substrates via two approaches using either 1) thermal release tape, 2) a PMMA/thermal release tape bilayer or 3) a spin-on, chemically-etchable dielectric. We will report on the impact that these transfer processes has upon the electrical properties of the transferred EG films.
Pattern Stamping Using Exfoliation for Heterogeneous Integration
Authors: Byun Ki Yeol , Yu Ran , Saeidi Nooshin , Flynn Michael , Ferain Isabelle , Colinge C.
Published: October 2010

In this work, an alternative method of hybrid pattern stamping for heterogeneous integration based on the low thermal budget smart-cutTM technique was investigated. Thanks to enhanced surface activation by remote oxygen plasma treatment prior to bonding, the thermal budget for that experiment has been maintained below 400°C while ensuring high bond strength and single crystalline Si and Ge pattern stamping. The bonded interface was characterized by means of advanced imaging techniques.
Porous Silicon Films for Thin Film Layer Transfer Applications and Wafer Bonding
Authors: Joshi Monali , Hu Song Jun , Goorsky Mark S.
Published: October 2010

Porous silicon films were fabricated from p+-Si (0.001-0.005 Ω cm) for their applicability to wafer bonding and layer transfer. Wafer bonding of porous silicon surfaces using silicon nitride interlayers was demonstrated, without the use of high temperature annealing. Conditions for producing porous silicon films compatible with both a) bonding surface requirements and b) layer transfer mechanical requirements were investigated. Nanoindentation showed quadratic dependence of Young's Modulus on relative density; films with mid-range Young's moduli were selected for layer transfer applications. Microstructural changes in annealed porous silicon films were studied using scanning electron microscopy and high resolution x-ray diffraction. Coarsening was observed at temperatures as low as 300 °C, the films remained pseudomorphic after annealing at all temperatures. After subsequent higher temperature annealing, mechanical fracture of the bonded stack occurred through the porous layer. The fracture mechanism for these structures is proposed.
Dielectric Layer Transfer by Low-Temperature Wafer Bonding for Optical Characterization
Authors: Knechtel Roy , Gäbler Daniel
Published: October 2010

The optical properties of dielectric layers on top of photodiodes processed in mixed signal CMOS processes significantly influence the characteristics of these light sensitive elements. This paper describes the transfer of this type of layer from silicon to a quartz wafer, in order to allow their optical characterization.
(Invited) Adhesive Wafer Bonding, Applications and Trends
Authors: Niklaus Frank
Published: October 2010

Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronics, micro- and nano-electromechanical systems (MEMS / NEMS) and packaging applications. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures (between room temperature and 450{degree sign}C, depending on the polymer adhesive), the compatibility with standard CMOS integrated circuit wafers and the ability to join different types of materials. While adhesive wafer bonding is a comparably simple, robust and low-cost process, concerns need to be considered such as the permeability of polymers for gasses and moisture, limited temperature stability and limited data about long-term stability of many polymers in demanding environments. This paper reviews the state-of-the-art of adhesive wafer bonding technologies, applications and future trends.
Atmospheric-Pressure Plasma Activation for Low Temperature Bonding
Authors: Low Yian Wei , Rainey Paul V. , Baine Paul B. , Montgomery John H. , Mitchell Neil S. , McNeill David W. , Gamble Harold S. , Armstrong Mervyn
Published: October 2010

An atmospheric plasma activation system has been employed to study its application on low temperature wafer bonding. Oxygen activation on PECVD oxide for bonding of temperature sensitive materials shows no pin hole when activating oxide with thickness more than 0.25 microns. Activation on thermal oxide by helium plasma also shows a pin hole free oxide. Bond strength approximately 1000 mJ/m2 is achieved after 250 degree celcius post-bond anneal which is about twice the bond strength of non-activated samples. Multiple UV components from the helium plasma were detected by spectograph. These UV spectra might have contributed to the bond strength enhancement in Si-SiO2 bonding.
Low-Temperature Direct Bonding of Borosilicate, Fused Silica, and Functional Coatings
Authors: Eichler Marko , Michel Benedikt , Hennecke Philipp , Gabriel Markus , Klages Claus-Peter
Published: October 2010

An experimental study of low-temperature bonding of plasma-treated borosilicate glass and fused silica wafers as well as silicon substrates carrying thin films of silicon dioxide, silicon nitride, silicon oxynitride, and indium tin oxide, respectively, is reported. Plasma process parameters were optimized in order to maximize bond energy. Surface energy measurements were carried out in situ during annealing, helping to understand the kinetics of the bonding process. Power spectral density measurements on debonded wafers support the idea of the strong impact of micro-contact formation on bonding kinetics.
Direct Bonding of Glass Substrates
Authors: Kalkowski Gerhard , Rohde Mathias , Risse Stefan , Eberhardt Ramona , Tünnermann Andreas
Published: October 2010

We report on investigations of direct bonding of glass materials for application as optical devices or high precision mechanical stages under vacuum. SiO2 (fused silica) wafers of about 0.8 mm thickness and 200mm diameter were bonded to massive SiO2 substrates of up to 20 mm thickness. With suitable wet cleaning and a low pressure Nitrogen plasma surface activation, rather high quality (optically transparent) bonds were obtained. Successful bonding was achieved at relatively low temperatures of about 250°Celsius in vacuum under compressive forces of several tens of kN, using a commercial bond equipment. Remaining bonding defects were analyzed by transmitting polarized light and measuring stress birefringence. At particle related defects in the bonding area, stress levels of the order of 0.2 MPa were discerned. Small unbound regions typically emerged at locations where no significant pressure was applied during the bonding process. Crack-opening indicated a bonding strength of about 0.6 J/m².
(Invited) III-V-On-Insulator MOSFETs on Si Substrates Fabricated by Direct Bonding Technique
Authors: Takagi Shinichi , Yokoyama Masafumi , Takagi Hideki , Urabe Yuji , Yasuda Tetsuji , Yamada Hisashi , Hata Masahiko , Takenaka Mitsuru
Published: October 2010

The heterogeneous integration of III-V semiconductors and Ge with Si wafers is expected to provide high performance logic CMOS under future technology nodes and other novel system-on-a -chip (SoC) applications. The III-V-On-Insulator (III-V-OI) structure fabricated by the wafer bonding technique is quite promising for realizing this heterogeneous integration for future LSIs. In this paper, we introduce our fabrication of InGaAs-OI structures with buried oxides (BOX) of ECR-SiO2 and ALD-Al2O3 by the direct wafer bonding and demonstrate the InGaAs-OI MOSFET operation on the Si substrates. The importance of the interface quality between InGaAs and BOX is addressed through the electron mobility behaviors. This technique is quite promising for the fabrication of novel CMOS device application under the 15 nm technology node and beyond.
Interface Morphology Investigation of Bonded p-GaAs/p-Si Wafers
Authors: Hsieh Cheng-Yu , Wu YewChung S.
Published: October 2010

The integration of GaAs and Si can combine the superior electrical and optical properties of GaAs with the mechanical and economical advantages of Si. It presents great potential for OEICs applications. In this study, direct wafer bonding was applied to combine bulk p-Si and p-GaAs. Interface morphologies of bonded p-GaAs/p-Si wafers were investigated by TEM.
Investigation of Sulfur Passivation Treatments for Direct Wafer Bonding of III-V Materials
Authors: Jackson Michael , Jackson Biyun L. , Goorsky Mark S.
Published: October 2010

Bonding techniques for direct wafer bonding of III-V materials by various sulfur passivation treatments are presented. A dry sulfur passivation method utilizing elemental sulfur vapor activated by ultraviolet light in high vacuum is adapted for use in wafer bonding. Large area bonding is achieved for GaAs/GaAs and InP/InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively without large compressive forces. X-ray photoelectron spectroscopy measurements of the treated GaAs surface show the reduction of oxide and creation of sulfide bonds prior to bonding. The electrical conductivity across a sulfur bonded GaAs/GaAs interface is greatly improved with a short anneal (1-2 minutes) at elevated temperatures (500-600 °C) and HRTEM images reveal the interface is restructuring at lower temperatures than reported for other bonding techniques.
Chemical-Mechanical Polishing for III-V Wafer Bonding Applications: Polishing, Roughness, and an Abrasive-Free Polishing Model
Authors: Brightup Steven , Goorsky Mark S.
Published: October 2010

Chemical mechanical polishing (CMP) of III-V (and other materials) is an important component of subsequent wafer bonding or epitaxial growth. For example, transferred exfoliated layers possess roughness on the order of tens of nanometers and epitaxial layers may possess surface roughness that prevents subsequent bonding. Standard polishing processes are too aggressive and remove material at rates on the order of microns per minute. This paper develops a more controlled CMP process for Indium Phosphide (InP), which removes the RMS roughness to below 1 nm with a removal rate of 5 nm per minute. The technique is characterized at different time intervals and roughness values. A model for abrasive-free CMP is also developed to expand upon current models.
Direct and Polymer Bonding of III-V to Processed Silicon-On-Insulator for Hybrid Silicon Evanescent Lasers Fabrication
Authors: Bordel Damien , Argoud Maxime , Augendre Emmanuel , Harduin Julie , Philippe Paul , Olivier Nicolas , Messaoudène Sonia , Gilbert Karen , Grosse Philippe , Ben Bakir Badhise , Fedeli Jean-Marc
Published: October 2010

We report the use of both direct and polymer bonding for the fabrication of Silicon/III-V evanescent laser. III-V structure is transferred to processed silicon-on-insulator (SOI) substrate at low temperature with a yield over 98%. We demonstrated the advantage of using a thick oxide layer (>100 nm), allowed by the innovative design, for limiting the void formation at the bonding interface. Silicon/III-V evanescent laser have been realized. The investigated device operates under quasi-continuous wave regime. The room temperature threshold current is 100 mA, the side mode suppression ratio is as high as 20dB, and the fiber-coupled output power is ~7mW.
Demonstration of Enhanced III-V-On-Silicon Hybrid Integration by Using a Strained Superlattice as a Defect Blocking Layer
Authors: Liang Di , Srinivasan Sudharsanan , Peters Jon , Fang Alexander , Bowers John E.
Published: October 2010

Enhanced III-V epitaxial transfer through a low-temperature direct wafer bonding process was observed by including a strained superlattice (SSL) layer right above the bonding layer in III-V to block bonding-induced defects. Compared to previously-used unstrained SL, SSL shows better capacity to pin thermal defects at the bonding interface, preventing them from propagating upwards to the active region. Higher photoluminescence response and lower dark current from fabricated photodetectors (PDs) proved the theory. Compared with SL-free sample, both USL and SSL samples demonstrated much better uniformity in PL response and PD dark current, and well-preserved quantum-well satellite peaks and fringes in X-ray diffraction rocking curve measurement. The employment of SSL is useful to many dissimilar material hybrid integrations.
(Invited) Wafer Bonding: A Retrospective
Authors: Bengtsson Stefan
Published: October 2010

Wafer bonding has become well-known and widely used as the process of adhesion of two flat mirror-polished wafers without the use of any intermediate adhesive layer. Today, it is used as a versatile tool in a wide variety of scientific fields and the technique has reach industrial maturity in particular for the manufacturing of Silicon-On-Insulator (SOI) materials, but also in other fields, such as for sensors, microsystems, optics and photonics. The early development of wafer bonding is reviewed and a retrospective view is taken on wafer bonding, addressing some of the critical research achievements and breakthroughs over the last three decades. The focus is limited to wafer bonding without the use of adhesive layers or electrostatic fields, and will hence not discuss related techniques, such as anodic bonding.
Silicon Nitride Surface Conversion into Oxide to Enable Hydrophilic Bonding
Authors: Usenko Alex , Senawiratne Jayantha
Published: October 2010

Oxygen plasma was used to convert the top part of Si3N4 film into SiO2. Surface roughness remarkably improves because of the process. SiO2, at surface now allows rendering surface hydrophilic. Both effects - smoothening and conversion - are favorable for further wafer bonding. Silicon wafers with the top-reoxidized nitride film successfully bond to glass substrates. The bonding allowed layer transfer. Silicon-on-glass substrates with a barrier nitride film between the silicon and glass were fabricated.
Wafer Bonding Process Selection
Authors: Dragoi Viorel , Pabo Eric
Published: October 2010

Wafer bonding processes offer valuable solutions not only for MEMS devices but more recently for wafer-level 3D interconnects, advanced packaging and LED applications. The increased complexity of the wafer bonding based applications requires very accurate process design. Unfortunately bonding process selection and design is not always well documented or understood and some important details may not be considered, possibly resulting in major issues during product prototyping or even manufacturing. The main topics to be considered for wafer bonding process selection are summarized and explained.
Finite Element Modeling and Raman Study of Strain Distribution in Patterned Device Islands on Strained Silicon-on-Insulator (sSOI) Substrates
Authors: Gu Diefeng , Baumgart Helmut , Naumann F. , Petzold Matthias
Published: October 2010

Finite Element (FE) Analysis was performed to study the strain relaxation of the strained Si on insulator (sSOI) wafers with different patterned size and thickness of the sSi layer. The results from FE simulation corroborate the experimental results from Raman microprobe spectroscopy. For patterned device islands without capping the biaxial tensile strain (in-plane strain either in X or Y direction) in the sSOI layer may relax completely when the sSOI device island size shrinks below a critical geometry. As the size of quadratic device islands is steadily decreased, the dominant relaxation effects at the corners overlap and spread until they span the entire device structure. Finite Element Analysis provides a detailed understanding of the strain distribution and demonstrates the evolution of strain relaxation from the pattern corners and island edges to eventually encompass the entire device island for very small subcritical geometries.
Inspection of Bonded Interfaces Using Scanning Infrared Interferometry
Authors: Poduje Noel , Kerr William , Turner Kevin T.
Published: October 2010

Detecting voids in bonded wafer pairs is critical for ensuring robust bonding processes and managing yield. Here, a new measurement technique to detect voids in bonded using scanning infrared (IR) interferometry is described and used to detect voids in direct-bonded silicon wafer pairs. The void measurements obtained with the scanning IR interferometry technique are compared to measurements made on the same wafers using IR transmission imaging and scanning acoustic microscopy.
Process Induced Stresses in Cavity SOI Wafers
Authors: Elkhatib Osama , Makinen Jari , Palokangas Martti , Lin Tung-Wei , Johnson Harley T. , Horn Gavin P.
Published: October 2010

Silicon-on-insulator wafers with buried cavities have been utilized in recent applications ranging from MEMS based resonator devices to double gate MOS devices. The objective of this study is to determine whether the magnitude and orientation of residual stress concentrations generated by the etched silicon cavities, which can introduce reliability issues for these devices, particularly if a large tensile stress results from this processing. The results of this study show that the residual stress state of the bonded wafers may be tensile or compressive and the magnitude and orientation of these stresses depend on both the etched cavity geometry and the oxidation process, which can be verified in the development phase with an infrared polariscope. There is evidence that the stress in the handle wafer prior to bonding is maintained even after high temperature annealing and wafer thinning. Thus, residual stresses may be controllable prior to bonding.
Intercomparison of Methods for Detecting and Characterizing Voids in Bonded Wafer Pairs
Authors: Allen Richard A. , Rudack Andrew , Read David , Baylies Winthrop
Published: October 2010

The Wafer Bond Task Force of the SEMI MEMS Standards Committee has begun a round robin experiment to evaluate methods for identifying and characterizing voids in bonded wafer pairs for three-dimensional integrated circuit (3D IC) applications. Due to the numerous process steps that the wafers have undergone and the presence of Through-Silicon Vias (TSVs), bonded wafers containing 3D ICs are expected to suffer a higher rate of postbonding voids than other bonding applications. In addition, 3D ICs will likely be more sensitive to small voids than other bond applications. In this round robin experiment eight approaches to void metrology are being compared by 13 participating laboratories to highlight the relative abilities of each of these metrologies to identify potentially killer defects.
(Invited) In Memoriam Ulrich Gösele: Wafer Bonding à la Carte
Authors: Radu Ionut
Published: October 2010

The modern day wafer bonding is inspired by the pioneering work of Prof. Dr. Ulrich Gösele in science and technology of direct bonding. Gösele's research helped in understanding of the fundamental mechanisms and thus revealing the technological interest of this technology. The paper reviews the results of basic studies in the area of wafer direct bonding of semiconductor and ferroelectric materials. Recent advances of the wafer bonding technology for the fabrication of advanced engineered substrates and 3D stacking are discussed.
(Invited) Wafer Bonding for the Manufacture of High-Brightness and High-Efficiency Light-Emitting Diodes
Authors: Plößl Andreas E. , Baur Johannes , Eißler Dieter , Engl Karl , Härle Volker , Hahn Berthold , Heindl Alexander , Illek Stefan , Klemp Christoph , Rode Patrick , Streubel Klaus , Tangrin Ivar
Published: October 2010

Wafer bonding based layer transfer approaches permit the fabrication of powerful volume or surface-emitting light-emitting diodes (LEDs). Here we briefly review the basic approaches taken and show some exemplary results of our metal-bonded UX:3-LEDs with buried mirror and buried metallic current distribution for both polarities, . The overall device performance benefits from the UX:3 variant of our ThinGaN technology: (i) at a drive current of 350 mA, a 5 % brightness increase for blue and green emission; through improved interaction of chip and phosphor coating, a 10-20% brightness increase for white LEDs; (iii) when trebling the current from 350 mA to 1 A, the sublinear brightness increase, called droop, is reduced to only 15%; (iv) at a 1 A drive current, a drop in forward voltage of only 200 mV occurs.
Effects of Surface Phage Coverage on the Performance of Wireless Phage-Immobilized Magnetoelastic Biosensors
Authors: Horikawa Shin , Li Suiqiong , Bedi Deepa , Shen Wen , Chen I-Hsuan , Chai Yating , Auad Maria , Bozack Michael , Barbaree James , Petrenko Valery , Chin Bryan
Published: October 2010

One of the important applications for which wireless phage-immobilized magnetoelastic (ME) biosensors are being developed is the real-time detection of pathogenic bacteria for bio-security and food safety. Until now, such ME biosensors have been manufactured by immobilizing a phage probe on gold-coated ME sensor platforms via physical adsorption. Although the physical adsorption method is simple, the surface coverage as well as immobilization stability of phage probes must be evaluated as a potential way to enhance the performance of the ME biosensors. In addition, recent studies have shown that chemical immobilization of phage probes potentially improves the performance of phage-based bio/chemical sensors. Hence, we here present performance comparisons between phage-immobilized ME biosensors manufactured by different phage immobilization methods: physical adsorption and covalent attachment. The biosensor's performance was found to be directly related to the surface phage coverage.