(Plenary) Physical Insights on the Design of UTB Devices, Including FinFETs
Authors: Fossum Jerry G. 
Published: February 2020

A revolution in device design for nanoscale CMOS is now occurring because the conventional bulk-Si MOSFET can no longer be scaled due to channel-doping limitations. Two novel devices with undoped ultra-thin bodies (UTBs), the quasi-planar FinFET, on bulk Si or SOI, and the planar fully depleted (FD) SOI MOSFET, are now the prime candidates for nanoscale CMOS. This paper, based on our recently published textbook on UTB devices [1], overviews the unique physics of these new CMOS devices, and offers insights on their designs, scalabilities, and performance potentials.

The characterization of the threshold voltage of the FinFET and the FD-SOI MOSFET is unique and generally complex, but generic, following from the application of Poisson's Equation and Gauss's Law in the undoped UTB. It simplifies for the long symmetrical double-gate (DG) FinFET (Vt ≈ ΦMSf + φc where φc ≈ 0.4V is the surface potential at the threshold condition), and, for the FD-SOI MOSFET, yields Vt(VGbS, ΦMSb) which shows how Vt can be varied via substrate bias and/or doping. Also, Vt is increased by energy quantization, dependent on UTB thickness (tSi, with tSi < 4nm being prohibitive) and transverse electric field, and it is decreased by short-channel effects (SCEs), dependent strongly on tSi. Regarding SCE control, the DG FinFET is superior to the FD-SOI MOSFET which requires substantially thinner tSi. The triple-gate (TG, with a fin-top gate) device is not much better than the DG device in this regard, nor does it offer much Ion improvement due to the prevalent bulk inversion in the undoped UTB. The SCE control is dramatically improved by a gate-source/drain underlap, defined by the source/drain lateral doping profile, that implies an effective channel length (Leff) longer than the gate length (Lg) for weak inversion, but Leff ≈ Lgfor strong inversion. Such optimal design is peculiar to undoped channels.

The superior SCE control with FinFETs implies better scalability, and Intel Corp. has chosen [2] this device for its nanoscale CMOS. For vague reasons, it chose bulk Si for the substrate as opposed to SOI. Nonetheless, it appears that SOI will ultimately be needed (for Lg → <10nm), mainly because of unavoidable random variations in the high doping (PTS) density needed at the base of the fin to stop drain-source punch-through leakage. This leakage current is examined, in terms of the PTS doping density (~1018cm-3 is optimal), and variations in Vt and Iondue to the random PTS variations clearly imply problems in nanoscale bulk-Si FinFETs. Further, the PTS variations can undermine the control of the G-S/D underlap. The examination of the bulk-Si vs. SOI FinFET issue is concluded by noting a processing issue for FinFETs on SOI wafers, and suggesting that a local-SOI structure in bulk Si could be the ultimate solution.

The physical insights overviewed herein imply a set of pragmatic FinFET design criteria that, we believe, can simplify the technology without undermining the CMOS performance much. They include the following: use an SOI structure (e.g., local in bulk Si); use an undoped UTB/channel with tSi > 4nm; use DG as opposed to TG; use no high-k dielectric (as implied by effects of strong bulk inversion); use one ~midgap metal gate for LP, and perhaps dual gates for HP; use optimal G-S/D underlap; use no channel strain (carrier mobilities can be high without it); and possibly use optimal S/D processing for Vtcontrol (and underlap). SRAM simulations demonstrate the viability of such pragmatic FinFET design.

References:

[1] J. G. Fossum and V. P. Trivedi, Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs. Cambridge, U.K.: Cambridge Univ. Press, 2013.

[2] C. Auth et al., Proc. Symp. VLSI Tech., pp. 131-132, June 2012.