bluuebunny/crossref_metadata_2025 huggingface dataset:
Full Band S-Parameter Generation Methodology for High Speed Package Interconnect Modeling
Authors: Zeng Xiangyin , He Jiangqi , Xu Baoshu
Published: April 2009

Beyond GHz operation frequency and Gb/s transfer rate bring a big challenge to high speed package interconnect designs. To make sure the product meets the specifications, signal integrity analysis has to be done carefully for critical signals before tape out for manufacturing. In order to obtain an accurate signal integrity modeling, the package interconnect must be accurately modeled. Frequency domain S-parameter has been widely used to replace the traditional package lumped model characterized by the fixed values of R, L, and C, which is no longer accurate. To facilitate the time domain analysis, equivalent circuits or behavioral macro models can be established based on the frequency domain S-parameter. In order to obtain a stable, casual and accurate time domain response, the S-parameter should be accurate in the full frequency band from DC to the interested maximum frequency. Usually full wave electromagnetic simulators are used to obtain the package S-parameter. The obtained S-parameter is very accurate in high frequency band, but unfortunately poor in low frequency band which is usually an extrapolation of the high frequency results. Improper use of such EM tools will result in wrong S-parameter, which may sometimes bring instability to the final results in a time-domain simulator based on direct convolution. The equivalent circuit synthesized from the high frequency S-parameter may also generate poor result due to lack of accurate information in the low frequency band. In this paper, we first address the theoretic al reason for the inaccurate low frequency result from the full wave electromagnetic simulators. Then we introduce a new process to generate accurate S-parameter in the full interested frequency band. In the process, the frequency band is divided into three parts, the low frequency range, middle frequency range, and the high frequency range. Skin effect phenomenon is found to be the physical explanation for the frequency band division. It is found that properly choosing EM tools in the proper frequency band is the key to get accurate full band S-parameters.
Thermal Simulation and Experimental Validation for TEC Design
Authors: Shi Peter , Wong Stephen , Tan Yeow Meng , Sunappan Vasudivan , Fan Wei , Chua Kai Meng , Freeman Bill , Jiang Hongjin
Published: April 2009

We proposed a methodology for simulation and design of thermoelectric coolers based on the energy balance among the Peltier heat, Joule heat, conduction heat, radiation heat and convection heat and by using the Computational Fluid Dynamics software. Thermal index was proposed for easy prediction of a TEC module efficiency. The prototype of the TEC module was fabricated after the design optimization. Experimental validation was performed by using a thermal characterization system including a chiller and a thermal analyzer. It was found that the simulation and experimental results agreed well.
Integration of RF Inductors and Baluns in Multilayer Organic Substrates
Authors: Kamgaing Telesphor , Lee Chee Hoo , Hwang Kyu-Pyung , Zeng Xiang Yin , He Jiangqi , Hsu Rockwell , Min Yongki , Ihm Jae-Yong
Published: April 2009

This paper discusses the design, modeling and characterization of RF inductors and baluns in a multilayer organic substrate. In the first part of the paper, we systematically look at two types of spiral inductors for RF applications. More than 40 multi-turn spiral inductors covering inductance values from a few nH to 20 nH have been fabricated and fully characterized. Single turn inductors suitable for high-frequency applications with inductance values in the sub-nH range have also been fabricated and evaluated. In the second part of the paper, we discuss the design of a Marchand-type balun for 2.4 GHz Bluetooth and WLAN application. This 50:100-Ohm balun design employs staggered trace arrangement which results in improved insertion loss and robust performance. Both measurement and simulation data are presented to validate the package-embedded components.
SnAgCu Micro-Ball Grid Array (BGA) Solder Joint Evaluation Using a Torsion Mechanical Fatigue Test Method
Authors: Ryan Claire , Rodgers Bryan A. , Punch Jeff M.
Published: April 2009

Due to the hazard which lead poses to health and the environment the EU is banning its use in electrical and electronic equipment from July 2006. This ban along with the market drive to more environmentally friendly products means that tin-lead solders must be replaced with lead-free alternatives. This paper presents the results of an experimental investigation of the mechanical fatigue properties of tin-silver-copper (SnAgCu) solder joints with a baseline of tin-lead (SnPb). The test vehicle comprised of an 8-layer FR4 printed circuit board (PCB) mounted with four micro-ball grid array (BGA) components — each with a total of 100 solder balls in a 10×10 array. The solder joints were formed using surface mount reflow processes optimised for both solder types. A torsion mechanical fatigue test was employed to evaluate the solder joints — the principle of which was to stress the solder joints repetitively in order to determine the number of cycles to failure. The BGA components were daisy-chained — the resistance across each daisy-chain was monitored continuously during the cyclic defection of the test board. A profile of the increase in resistance with cycle number was established and the number of cycles to failure determined. The failure mechanism induced by the cycling was examined using cross-section and scanning electron microscopy (SEM) techniques. The results for SnAgCu joints show a superior performance during torsion mechanical fatigue testing than SnPb joints; giving a greater number of cycles to failure. The results from the tests presented in this paper show that the torsion test method provides a viable alternative to ATC as a qualification method for solder joints, while also providing substantial time savings — taking weeks rather than months to complete.
Laser-Induced Damage of Polycrystalline Silicon Optically Powered MEMS Actuators
Authors: Serrano Justin R. , Phinney Leslie M. , Brooks Carlton F.
Published: April 2009

Optical MEMS devices are commonly interfaced with lasers for communication, switching, or imaging applications. Dissipation of the absorbed energy in such devices is often limited by dimensional constraints which may lead to overheating and damage of the component. Surface micromachined, optically powered thermal actuators fabricated from two 2.25 μm thick polycrystalline silicon layers were irradiated with 808 nm continuous wave laser light with a 100 μm diameter spot under increasing power levels to assess their resistance to laser-induced damage. Damage occurred immediately after laser irradiation at laser powers above 275 mW and 295 mW for 150 μm diameter circular and 194 μm by 150 μm oval targets, respectively. At laser powers below these thresholds, the exposure time required to damage the actuators increased linearly and steeply as the incident laser power decreased. Increasing the area of the connections between the two polycrystalline silicon layers of the actuator target decreases the extent of the laser damage. Additionally, an optical thermal actuator target with 15 μm × 15 μm posts withstood 326 mW for over 16 minutes without exhibiting damage to the surface.
Analytical and Experimental Characterization of Bonding Over Active Circuitry
Authors: Zhang Li , Gumaste Vijaylaxmi , Poddar Anindya , Nguyen Luu , Schulze Gary
Published: April 2009

Placing active circuitry directly underneath the bond pads is an effective way to reduce the die size, and hence to achieve lower cost per chip. The main concern with such design is the possible mechanical damage to the underlying circuitry during the wire bonding process. For example, the initial bond force and subsequent ultrasonic vibration may cause cracks within the dielectric layer. The cracks can penetrate through the active circuitry underneath, resulting in electrical failures to the silicon device. At the present time, most studies found in the literature rely heavily on experimental characterization to study pad integrity. The characterization typically involves building test devices and conducting real-life bonding test. On the other hand, while there are few studies attempting to describe the stress-strain behavior of the process by numerical simulations, most are based on either over-simplified models or incomplete analysis. Furthermore, nearly all of these studies failed to provide any correlation with real test data, and hence the accuracy of the analysis becomes questionable. In this paper, we have developed a finite element based methodology to study the stress behavior of bond pad structures during thermo-sonic wire bonding. Unlike most previous studies, which used 2-D models and plane-strain assumption, the current model captures the 3-D structure of the bond pad and gold ball. The incremental principal stress at the dielectric layer was used as the stress criterion to correlate with dielectric cracking, which is the dominant failure mode during our bonding experiments. The dynamic friction coefficient at the gold-aluminum interface is found to be responsible to the change in magnitude and location of the peak stress. To validate the simulation results, two engineering test chips were built and bonded. The dielectric cracks were found to correlate well with the incremental principal stress. Furthermore, we have shown that the interfacial friction model was able to account for the difference in crack pattern. The FE model is expected to study the relative crack resistance for other bonding over active circuitry pad structures currently under consideration.
A New Method for Evaluating Fatigue Life of Micro-Solder Joints in Semiconductor Structures
Authors: Tanie Hisashi , Terasaki Takeshi , Naka Yasuhiro
Published: April 2009

Conventionally, the fatigue life of solder joints in semiconductor structures is estimated using Coffin-Manson’s law. However, as the structures have become miniaturized or thinner, accurately estimate fatigue life has become difficult using conventional methods. This is because the fatigue life is strongly affected by crack propagation in miniaturized or thinner joints, and the conventional methods cannot evaluate this phenomenon well. We have therefore developed a new method for evaluating fatigue life that takes into account the influence of crack propagation in micro-solder joints. In micro-solder joints, a solder crack path might propagate not only at the solder and land interface itself, but also near the interface. Many crack-propagation have been proposed, but a model that can reproduce a crack path has yet to be proposed. The fatigue life of a solder in our crack-propagation model is evaluated based on the damage that accumulates during crack propagation, and the crack paths are automatically calculated. Using this model, we analyzed the crack path of a ball grid array (BGA) structure, and we determined that the model could reproduce the above-mentioned characteristic crack paths. When the fatigue life is calculated using a finite element method, one of the most difficult issues is correcting for the effect of element size. We determined the calculated life dependency on element size, and we developed a formula for approximating this dependency in the proposed model. We then used this formula to calculate the fatigue life of three different size BGA solder joints that were subjected to mechanical fatigue testing. The calculated lives were found to correspond with the measured lives. Furthermore, we applied this method to evaluate the differences in the fatigue life of a solder-mask-defined (SMD) structure and a non-solder-mask-defined (NSMD) structure. Both are typical structures of BGA solder joints. We determined that the fatigue life of the NSMD structure was longer than that of the SMD structure. The main cause for this difference is that the crack-propagation life of the NSMD structure was longer than that of the SMD structure, even though the crack-initiation lives of both structures were the same.
The Study of the Design in Micro Modal Actuators Using the Holographic Interferometry
Authors: Gau Wei-Hsin , Hu Yuh-Chung , Peng Yen-Yi
Published: April 2009

A novel electrostatic micro modal actuator adopted the orthogonality of the mode shape of the microstructure is created. By using the design of the shape of the modal electrode, the stability of the actuator can be improved and the driving voltage can be reduced by controlling the actuated modes precisely. In the analysis in this investigation, the equations of motion considering the effect of the coupling between the flexibility and the electrostatic field of the micro actuator are developed. The modal equations derived by the modal expansion indicate that distributed electrostatic modal actuators can be realized through the constructed correctly modal electrodes and the specific excited mode. The developed electrostatic modal actuator can reduce the driven voltage and eliminate the spillover phenomenon. Since, the stiffness, the dynamic properties, and the stability of the system can be affected by the changes of the electric field, the effect of the electrostatic field and the shape of the electrode on the actuator are also investigated. The experimental modifications of the modes caused by different shapes of the actuators are examined by using the time-average Holographic interferometry. Concerning to the electrostatic modal actuator, the design concepts can be realized through the combination of the modal electrode and the design of controlling circuits. The analytical model considering the coupling effect between the structure and electrostatic field can be established in the form of the linear periodically time-varying function and the relationship between the full field mode and the driven voltage can be obtained.
Reliability and Characterization of Micro-Packages in a Wafer Level Au-Si Eutectic Vacuum Bonding Process
Authors: Mitchell Jay S. , Lahiji Gholamhassan R. , Najafi Khalil
Published: April 2009

A Au-Si eutectic vacuum packaging process was evaluated using high sensitivity poly-Si Pirani vacuum sensors. Encapsulation of devices was achieved by bonding a silicon cap wafer to a device wafer using a Au-Si eutectic solder at above 390°C in a vacuum bonder. The Au-Si eutectic solder encircled the devices, providing an airtight seal. The Pirani gauges were encapsulated and tested over a period of several months in order to determine base pressures and leak/outgassing rates of the micro-cavities. Packaged devices without getters showed initial pressures from 2 to 12 Torr with initial leak/outgassing rates of −0.073 to 80 Torr/year. Using getters, pressures as low as 5 mTorr have been achieved with leak/outgassing rates of <10 mTorr/year. Trends in pressure over time seem to indicate outgassing (desorption of atoms from inside of the microcavity) as the primary mechanism for pressure change over time.
Evolution of Die Stress and Delamination During Thermal Cycling of Flip Chip Assemblies
Authors: Rahim M. Kaysar , Suhling Jeffrey C. , Jaeger Richard C. , Lall Pradeep
Published: April 2009

Underfill encapsulation is used with flip chip die assembled to laminate substrates to distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. Any delaminations that occur at the underfill/die interface will propagate to the neighboring solder bumps and lead to solder joint fatigue and failure. The onset and propagation of delaminations in flip chip assemblies exposed to thermal cycling are governed by the cyclic stresses and damage occurring at the underfill to die interface. For this reason, underfills are optimized by increasing their adhesion strength, interfacial fracture toughness, and resistance to thermal aging. In this work, we have sought to develop a fundamental understanding of delamination initiation and growth in flip chip assemblies through simultaneous characterization of the stress and delamination states at the die to underfill interface. Mechanical stresses on the device side of the flip chip die have been measured using special (111) silicon stress test chips containing piezoresistive sensor rosettes that are capable of measuring the complete three-dimensional silicon surface stress state in the silicon (including the interfacial shear and normal stresses at the die to underfill interface). By continuous monitoring of the sensor resistances, the die surface stresses were measured during post-assembly thermal cycling environmental testing from −40 to 125 C. With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of three-dimensional die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. Through these measurements, we have been able to identify the stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most important discoveries is that the shear stresses occurring at the corners of flip chip die have been demonstrated to be a suitable proxy for prognostic determination of future delamination initiations and growth.
Measurement of Electronic Packaging Material Behavior and Flip Chip Die Stresses at Extreme Low Temperatures
Authors: Rahim M. Kaysar , Suhling Jeffrey C. , Jaeger Richard C. , Islam M. Saiful , Ma Hongtao , Lin Chang , Lall Pradeep , Knight Roy , Strickland Mark , Blanche Jim
Published: April 2009

High stresses in semiconductor die and other packaging elements can be developed in electronic assemblies subjected to extremely low ambient temperatures leading to reliability concerns. In this work, we have characterized and modeled the silicon die stresses occurring in flip chip assemblies at low temperatures. Stress measurements have been made at temperatures down to −180°C using test chips incorporating piezoresistive sensor rosettes. The obtained stress measurement data have been correlated with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solders and encapsulants from −180 to +150°C to aid in this modeling effort.
A Rapid Method to Measure Thermal Conductivity of Dielectric Thin Films: Thermal Resistance Method
Authors: Yao Da-Jeng , Chien Heng-Chieh , Tseng Ming-Hsi
Published: April 2009

A new and relatively simple method, described for thermal conductivity measurement of dielectric thin films, is presented in this paper. This new technique, the thermal resistance method, can be applied to determine cross-plane thermal conductivity of thin film by electrical heating and sensing techniques without traditional free standing structure design. A slender metal line, deposited on top of dielectric film, is used to measure and extract thermal resistance (Rc) of composite structure, including substrate and dielectric film. A 2-D analytical solution is derived to get thermal resistance (Rs) of substrate. Therefore, the thermal resistance of thin film (Rf) is calculated by subtracting Rs form Rc and thermal conductivity of thin film can also be extracted from thermal resistance. The measurement data of silicon dioxide with difference thickness are verified by using previous scientific literatures. In addition, the measuring results also show good agreement with those measured by 3 omega method. According to advantages of rather rapid and accuracy, this new technique has potential to develop to be an in-line test key for MEMS and IC relative industries.
Prolonged Steady-State Exposure of Printed Wiring Boards Under Conditions of Temperature Humidity and Bias
Authors: Reid M. , Punch J. , Rodgers B. , Galkin T. , Stenberg T. , Rusanenc O. , Elonen E. , Vile`n M. , Va¨keva¨inen K.
Published: April 2009

Ionic migration has been the subject of intensive study, both theoretical and experimental, over the past 40 years. It is known as a reliability concern for printed wiring boards (PWBs) in high density microelectronic packaging and power electronic packaging. Ionic migration is an electrochemical phenomena that occurs primarily under normal ambient conditions: i.e. when the local temperatures and current densities are low enough to allow moisture on the surface. Standardised test 85°C/85%RH is typically used for accelerating and predicting ionic migration failure, however, the possibility of moisture condensation — a prerequisite for ionic migration — at a relatively high temperature and low relative humidity is unlikely. In order to assess more realistic and less thermally severe environments, this work examines prolonged steady state exposure of PWBs. Steady-state conditions of 90%RH at 30°C under a bias of 5V DC were tested over a 210 day period with continuous in-situ monitoring of dendritic growth. Investigative techniques were conducted to evaluate the migration development on the PWBs after testing using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDS). This paper will demonstrate that steady-state thermal humidity bias (THB) tests appear to provide ionic migration behaviour similar in service conditions, however, do not demonstrate the dramatic failure associated with ionic migration.
Thermal Gradient in Solder Joints Under Electrical Current Stressing
Authors: Yao Da-Jeng , Hsu Chung-Yi , Chen Chih , Chiu Sheng-Hsiang
Published: April 2009

Thermal gradient phenomena in SnAg3.5 solder joints under high current density operating were both acquired from whole device simulation and observed from experiments. A series of structural solder bump models were created and simulated by finite element software under different current density. The thermal gradient and temperature increasing were investigated under current stressing of 103 A/cm2 to 104 A/cm2 at 70°C by infrared microscopy. The magnitude of the thermal gradient is increased by increasing the applied current. The measured temperature increase due to Joule heating is as high as 55.9°C, and the thermal gradient reached 333°C/cm when stressed by 104 A/cm2, yet only 8.3°C temperature increased and the thermal gradient reached 83°C/cm when stressed by 103 A/cm2. The temperature increasing in this model is 53.1°C and thermal gradient in the solder is 168°C/cm under 104 A/cm2 current stressing, yet only 10.4°C temperature increased and thermal gradient decreased to 35°C/cm under 103 A/cm2. After verification, only less than 0.5% error is achieved between simulation results and experiment results. It proves this built model can be used to project thermal characteristic of different module designs.
Thermal-Fatigue Life Prediction Equation for Plastic Ball Grid Array (PBGA) SnAgCu Lead-Free Solder Joints
Authors: Lau John , Lee S. W. Ricky , Song Fubin , Shangguan Dongkai , Lau Dennis C. , Dauksher Walter
Published: April 2009

A new thermal-fatigue life prediction equation for a class of lead-free solder alloys, 95.5wt%Sn4.0wt%Ag0.5wt%Cu, is proposed in this investigation. The test vehicle consists of a lead-free solder plastic ball grid array (PBGA) package, a lead-free PCB, and lead-free solder paste (95.5wt%Sn3.9wt%Ag0.6wt%Cu). The coefficients of the fatigue equation presented herein are determined by best fit of the test vehicle’s isothermal fatigue data. Failure modes and locations of the failed samples are discussed.
Ceramic Via Wafer-Level Packaging for MEMS
Authors: Heck John M. , Arana Leonel R. , Read Bill , Dory Thomas S.
Published: April 2009

We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic gold-tin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.
A Paradigm Shift in the Development of Chemical Mechanical Polishing (CMP): Cost-Effective CMP Planarization in Next Generation Substrate/Package Design and Manufacturing
Authors: Lotz Stefanie , Baresel Robert , Thakurta Dipto , Jiang Lei , Ghosh Tuhin
Published: April 2009

This paper discusses an on-going research effort to investigate planarization strategies capable of meeting next generation high density package performance and cost requirements. The approach entails the development of an ultra-high removal rate (∼15 μm/min) copper CMP process used in the fabrication of package substrate inter-connects. Initial slurry recycling feasibility has also been investigated as part of the strategy to further reduce operating costs. A recent key thrust in advanced packaging interconnects necessitates the use of damascene-like processing techniques to fabricate build-up substrate layers having high-aspect ratio conductor traces. Inherent thickness variations resulting from the feature forming and copper electroplating processes require subsequent planarization to preserve design requirements for critical trace and ground plane uniformities. The removal rates that have been achieved are nearly one order of magnitude greater than any known ‘high removal rate’ copper slurries commercially available today. Slurry re-use feasibility evaluations were performed using a series of tests designed to characterize the slurry solubility limits. Preliminary data collection indicates promising results for recirculation/recycling of copper slurries without compromise of removal rate stability. CMP process modeling using CAD simulation tools have been shown to be successful in validating the slurry recirculation model with the experimental polish data collected.
An Efficient Numerical Procedure for Solving Microscale Heat Transport Equation During Femtosecond Laser Heating of Nanoscale Metal Films
Authors: Kunadian Illayathambi , McDonough J. M. , Kumar Ravi Ranjan
Published: April 2009

An alternative discretization and solution procedure is developed for implicitly solving a microscale heat transport equation during femtosecond laser heating of nanoscale metal films. The proposed numerical technique directly solves a single partial differential equation, unlike other techniques available in the literature which split the equation into a system of two equations and then apply discretization. It is shown by von Neumann stability analysis that the proposed numerical method is unconditionally stable. The numerical technique is then extended to three space dimensions, and an overall procedure for computing the transient temperature distribution during short-pulse laser heating of thin metal films is presented. Douglas-Gunn time-splitting and delta-form Douglas-Gunn time-splitting methods are employed to solve the discretized 3-D equations; a simple argument for stability is given for the split equation. The performance of the proposed numerical scheme will be compared with the numerical techniques available in the literature and it is shown that the new formulation is comparably accurate and significantly more efficient. Finally, it is shown that numerical predictions agree with available experimental data during sub-picosecond laser heating.
Wafer Level Bonding of MEMS Devices Using Ceramic Lids
Authors: Dory Thomas S. , Read Bill , Arana Leonel R. , Heck John M.
Published: April 2009

Wafer level bonding of MEMS devices is becoming an important packaging technique for small die. Wafer lid bonding simplifies and provides an economical assembly process. One requirement for RF MEMS devices is a hermetic lid, seal material, and sealing process for device reliability. A challenge of this packaging technique is the difference between the lid material CTE, coefficient of thermal expansion, and the silicon device wafer. We selected low temperature co-fired ceramics, LTCC, to evaluate as a potential MEMS lid material for wafer level bonding. This report covers the use of LTCC ceramic lids having CTE values of 5.5, 4.0, and 3.4ppm with thickness of 0.5 and 0.3mm. Different bonding recipes using an inert atmosphere were developed to manage warpage after bonding. Cooling ramp rates, dwell times at elevated temperatures, and lid scoring methods were investigated. A hold time at an elevated temperature was required for the ceramic lids with higher CTE values. With the low CTE ceramic lids, no hold time was required. We found successful RF MEMS wafer level bonding, WLB, can be achieved using low CTE ceramic lids.
Thermal Resistance of Bond-Lines Formed With Composite Thermal Interface Materials
Authors: Lehmann Gary , Zhang Hao , Gowda Arun , Esler David
Published: April 2009

Measurements and modeling of the thermal resistance of thin (< 100 microns) bond-lines are reported for composite thermal interface materials (TIMs). The composite TIMs consist of alumina particles dispersed in a polymer matrix to form six different adhesive materials. These model TIMs have a common matrix material and are distinguished by their particle size distributions. Bond-lines are formed in a three-layer assembly consisting of a substrate-TIM-substrate structure. The thermal resistance of the bond-line is measured, as a function of bond-line thickness, using the laser flash-technique. A linear variation of resistance with bond-line thickness is observed; Rbl = β · Lbl + Ro. A model is presented that predicts the effective thermal conductivity of the composite as a function of the particle and matrix conductivity, the particle-matrix surface conductance, the particle volume fraction and the particle size distribution. Specifically a method is introduced to account for a broad, continuous size distribution. A particle-matrix surface conductance value of ∼10W/mm2K is found to give good agreement between the measured and predicted effective thermal conductivity values of the composite TIMs.
Development of Latching Type Large Vertical-Travel Microactuator
Authors: Toda Risaku , Yang Eui-Hyeok
Published: April 2009

This paper describes design, fabrication and preliminary characterization of a proof-of-concept vertical-travel microactuator, providing linear motion and high precision positioning in space. The microactuator is capable of providing latching function when it is un-powered to maintain its position. The microactuator consists of two opposing comb drive actuator dies, a slider and bulk PZT actuators sandwiched between the dies. The slider is inserted between clutches. Comb drives are connected to the clutches to engage/disengage clutching. Sequential activation of the comb drives (in-plane motion) and the PZT actuator (out-of-plane motion) provides cumulative linear travel of the slider. The novelty of the slider insertion approach include (1) post-fabrication engagement of comb teeth enabling thick wafer DRIE process for comb drive actuators and (2) stressed tethers enabling zero-power latching. A test device was fabricated and assembled. By applying 100V∼300V DC to the electrostatic comb drive, lateral actuation of clutches was observed. Vertical actuation by PZT was also confirmed using WYKO RST plus interferometer.
Dual Die Package Design Strategy and Performance
Authors: Suryakumar Mahadevan , Phan Lu-Vong T. , Ma Mathew , Ahmed Wajahat
Published: April 2009

The alarming growth of power increase has presented numerous packaging challenges for high performance processors. The average power consumed by a processor is the sum of dynamic and leakage power. The dynamic power is proportional to V^2, while the leakage current (therefore leakage power) is proportional to V^b where V is the voltage and b>1 for modern processes. This means lowering voltage reduces energy consumed per clock cycle but reduces the maximum frequency at which the processor can operate at. Since reducing voltage reduces power faster than it does frequency, integrating more cores into the processor would result in better performance/power efficiency but would generate more memory accesses, driving a need for larger cache and high speed signaling [1]. In addition, the design goal to create unified package pinout for both single core and multicore product flavors adds additional constraint to create a cost effective package solution for both market segments. This paper discusses the design strategy and performance of dual die package to optimize package performance for cost.
Improving the Performance of the Micro Jet Array Air Cooling MEMS Device Using CFD
Authors: Jung Yangki , Selvam R. Panneer
Published: April 2009

In this work ways to improve the performance of the MJA is investigated using computer modeling. Finite-difference method is used to analyze and understand the heat transfer mechanism in the MEMS based air micro-jet array (MJA) impinging cooling device. The three-dimensional Navier-Stokes (NS) equations using the compressible flow are solved. The computed temperature distribution at the bottom of the MJA is in good agreement with the experimental measurement data. To improve the heat transfer performance, an optimum model is developed. This enhances the heat removal capacity about 100% (0.5 W/cm2°C). The details of computer modeling and the flow visualization to understand the flow and heat transfer in the MJA are presented.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.
Squeeze Flow Study of a Colloidal Paste
Authors: Davidson Drew A. , Lehmann Gary L.
Published: April 2009

Crucial to the development and characterization of thermal interface materials (TIMs) is an understanding of the squeeze flow process that is commonly used to form thin bond layers in micro-electronic assemblies. A single model TIM, a dense, fairly monomodal suspension of submicron alumina particles suspended in a silicone-based resin, is first characterized as a Bingham fluid using a parallel disk rotational viscometer. Next, the model TIM is squeezed from ∼1 mm initial thickness to ∼.01 mm limiting thickness under nominally constant applied load (68 to 345 kPa) between 20 mm diameter aluminum plates in an axial compression test apparatus (the type commonly used for materials testing). The test plates are flat (∼10 μm flatness deviation over the plate) and smooth (Ra ∼ 20 nm), and are fixed in the test column with epoxy for optimum parallelism. Bond layer thickness is estimated using the LVDT built into the compression tester. The thickness measurement resolution is limited by LVDT noise of 10–20 microns. Squeezing forces are well above the ∼.02 N noise level of the 100 N load cell. Of the test system compliance, inertia, and friction, only the compliance is significant to our testing, and is corrected for. Squeeze flow tests of Newtonian standards are used to qualify the test process. In the case of the model paste, Bingham fluid model parameters from rotational viscometry are used in a lubrication model of squeeze flow that shows good agreement with the measured gap vs. time behavior during squeezing. Improved agreement is obtained by including plate flatness deviation and time-dependent force in the lubrication model. Parallel disk viscometry and squeeze flow testing of the base resin of the model TIM shows Newtonian behavior.
Experimental Validation of Macro-Models for Simulating Capillary Driven Multiphase Flows Used for Micro-Chamber Filling
Authors: Banerjee Debjyoti
Published: April 2009

Macro-models (also called “reduced-order-models”, “lumped parameter models”, etc.) are convenient and efficient design tools that afford reasonable simulation accuracy by replacing the governing physical equations with behavioral models. Such models are easy to implement, usually do not require grid formulations, employ simple numerical schemes (systems of ordinary differential equations or algebraic equations), and have robust numerical convergence. In this study macro-models were developed for predicting the filling of micro-chambers for capillary driven flows as a function of geometric parameters and fluid properties (viscosity, surface tension and contact angle). It was found that bubble formation in filling of micro-chambers is a strong function of wall contact angles. A region of wall influence parameter was identified which was found to be relatively insensitive to flow parameters (flow rate, viscosity, etc.) and depends strongly on the wettability of the side walls of the micro-chambers.
Effect of Filler Geometry on the Conduction of Isotropically Conductive Adhesives
Authors: Su Bin , Qu Jianmin
Published: April 2009

The effect of the geometry of conductive fillers on the conduction of conductive adhesives is studied. 3-D microstructure models of conductive adhesives are built to describe the positions and connections of the conductive fillers. Both rectangular flakes and spherical particles are studied. The total resistance of conductive adhesive is calculated by solving the resistor network formed by all particle connections. The method of full factorial design at two levels is used, and the geometric parameters are set at high and low level to study their effects on the resistivity of the conductive adhesive. Pareto chart of standardized effects of factors are examined for different configurations. Factors with significant effects are found. Main effect plots are used to study how significant factors affect the resistivity. Monte Carlo simulations are used for each configuration. Radius mean has the most significant effect for spherical particles, while the alignment angle is most significant for flakes.
Lead-Free and PbSn Bump Electromigration Testing
Authors: Gee Stephen , Kelkar Nikhil , Huang Joanne , Tu King-Ning
Published: April 2009

As the electronics industry continues to push for miniaturization, several reliability factors become vital issues. The demand for a high population of smaller and smaller solder bumps, while also increasing the current, have resulted in a significant increase in the current density. As outlined in the International Technology of Roadmap for Semiconductors (ITRS), this trend makes electromigration the limiting factor in high density packages. The heightened current density and correspondingly elevated operating temperatures are a critical issue in reliability since these factors facilitate the effects of electromigration. Therefore, as bump sizes continue to decrease, the study of electromigration reliability becomes crucial in order to understand and possibly prevent the causes of failure. A systematic study of electromigration in eutectic SnPb and Pb-free solder bumps was conducted in order to characterize the reliability of the Micro SMD package family. The testing includes both eutectic 63Sn-37Pb and 95.5Sn4.0Ag-0.5Cu solder bumps on an Al/Ni(V)/Cu under-bump-metallization. Mean-time-to-failure results are compared to Black’s Equation and cross-sections of the solder bumps are shown to analyze the mechanisms that led to failure.
Exploration of Thermolithography for Micro- and Nano-Manufacturing
Authors: Hung Ming-Tsung , Ju Y. Sungtaek
Published: April 2009

Lithography is a critical enabling technology for manufacturing micro- and nano-scale devices and structures. The manuscript presents our recent progress in the exploration of a new lithography technique that employs localized heating to induce thermo-chemical crosslinking of photoresist layers. The thermal transport properties of photoresist layers are measured and kinetics of cross-linking reactions is studied using microfabricated heaters as localized heat sources. It is demonstrated that polymer films can be patterned in a controlled manner using heater temperature, heating duration, as well as UV exposure dose as control variables. The data and experimental approaches presented here will help systematic evaluation and development of thermolithography schemes.
Models for Shock and Vibration Survivability of Electronic and MEMS Packaging
Authors: Lall Pradeep , Panchagade Dhananjay , Choudhary Prakriti , Suhling Jeff , Gupte Sameep
Published: April 2009

Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state-of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method. In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging. Data on damage progression under transient-shock and vibration in both 95.5Sn4.0Ag0.5Cu and 63Sn37Pb ball-grid arrays has been presented. Component types examined include — flex-substrate and rigid substrate ball-grid arrays. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using high-speed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video at 150,000 fps per second has been used to capture the deformation kinematics. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confidence level. The approach is scalable to application at system-level. Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope. Model predictions have been correlated with experimental data for both leaded and leadfree ball-grid arrays.
The Characterization of Damage Propagation in BGA’s on Flip-Chip Electronic Packages
Authors: Helms Kayleen L. E. , Phillips Betty
Published: April 2009

A characterization study is undertaken to monitor damage progression at the second-level interconnect in BGA’s on flip-chip electronic packages. Specifically, the progression of solder joint cracking under use conditions (thermal and combined thermomechanical loading) is investigated. The study uses a multi-color dye and peel failure analysis technique to track the initiation and propagation of solder joint cracks under loading. The approach being used differs from conventional failure analysis techniques in that multiple measurements of damage growth are obtained from the same part providing a full damage history. By using multiple dye colors, all crack initiation points, directions of propagation, and surface crack areas are obtainable experimentally. The scope of the study includes investigating the impact of such factors as die size, package size, BGA size, BGA pitch, enabling load, and internal heat spreaders (IHS’s) on the damage history observed. Based on this study, investigation of sequential loading can be pursued to identify directions and design guidelines for improving solder joint reliability of future BGA’s on flip-chip electronic packages.
Deformation Analysis of Center-Anchored Square Plate Induced by Residual Gradient Stress
Authors: Chang Pen-Lun , Lin Meng-Ju , Fan Tsung-Li
Published: April 2009

For optical MEMS or Micro-Electro-Mechanical-Optical System (MEMOS) devices, as depositing metal on the structure plate, the mismatch of thermal expansion coefficients between the metal layer and structure layer will induce residual gradient stress after release. Therefore, the residual gradient stress will deform the structure layer. The deformation could be used as profile of micro focusing mirror due to its parabolic-like shape. In this work, the effect of structure sizes and material properties on residual stress for center-anchored square plate focusing mirror is investigated. The center-anchored circular plate focusing mirror is designed and analyzed. In numerical analysis using finite element method, it is found that the deformation is circular shape in axial direction and parabolic-like profile in the radial direction, even the mirror being square shape. And the radial shape determines the focal length. In general, the thinner plate and the thicker metal layer will cause larger deformation. The larger square sizes will cause larger deformation. However, it is found that the effect of anchor sizes on deformation could be neglected. Only in the anchor near region, the deformation would be affected. And the depositing temperature will have obvious effect on deformation. It is also found in literature review, the deformation would be unsymmetrical and called warpage. Warpage is a serious problem to destroy the devices. Therefore, the warpage is also discussed. The thicker structure layer and thinner metal layer need higher temperature to cause warpage phenomena. The warpage temperature increases nonlinearly as the structure layer increasing. However, in thinner structure layer condition, the warpage temperature decreases first and increases following. In general, from the results it could be considered that as the ratio of structure and depositing metal layer thickness increasing, the deformation will reach to a limit value due to the saturation of stress gradient.
Flow Boiling Heat Transfer to a Dielectric Coolant in a Microchannel Heat Sink
Authors: Chen Tailian , Garimella Suresh V.
Published: April 2009

This paper presents an experimental study of flow boiling heat transfer in a microchannel heat sink. The dielectric fluid Fluorinert FC-77 is used as the boiling liquid after it is fully degassed. The experiments were performed at three flow rates ranging from 30 to 50 ml/min. The heat transfer coefficients, as well as the critical heat flux, were found to increase with flow rate. Wall temperature measurements at three locations (near the inlet, near the exit, and in the middle of heat sink) reveal that wall dryout first occurs near the exit of the microchannels. The ratio of heat transfer rate under critical heat flux conditions to the limiting evaporation rate was found to decrease with increasing flow rate, asymptotically approaching unity. Predictions from a number of correlations for nucleate boiling heat transfer in the literature are compared against the experimental results to identify those that provide a good match. The results of this work provide guidelines for the thermal design of microchannel heat sinks in two-phase flow.   This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference.