bluuebunny/crossref_metadata_2025 huggingface dataset:
Processing, Bumping and Assembly of Single Chip Plated Ni/Pd over ALCAP Bond Pads for Flip Chip Applications and Prototyping
Authors: Lewis Brian J. , Baldwin Daniel F. , Houston Paul N. , La Le hang , Spark Tim
Published: October 2015

For Designer and Engineers, it is common during the process development cycle for new products to have limitations on the materials that are available for the prototype work. Most SMT devices are readily available in different formats/solder alloys to satisfy most of the needs for passive needs. However, many times IC devices are limited to what is available from the fab or an IC broker. These limitations can mean that die only come in aluminum, wirebond ready I/O metallization or that the silicon wafers already sawn and in single die formats. For applications where advancement in performance or miniaturization is needed, and the benefits of flip chip technology are attractive, then it is not trivial to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate single chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads.

The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this plating technology and plating over gold or copper stud bumps, are evaluated. A process for bumping the flip chips is also detailed. The data for shear testing of the 10 variations before and after 500 liquid thermal shock cycles is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the selective plating process, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto single, ALCAP bare die can allow for these typical wirebond die can be used in a practical approach solder flip chip process and provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die.
ChipsetT: Embedded Die Substrate Applications
Authors: Aday Jon G. , Tessier Ted , Itoi Kazuhisa , Okude Satoshi
Published: October 2015

Embedded die substrate technologies are being developed in an assortment of configurations and for different market segments. The technology being discussed in this paper will be focused on both a fan out technology – ChipsetT Fan-Out and a system in package approach (ChipsetT SiP) in which a multiple component bill of materials (BOM) is used. The Chipset process is based on the WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multilayer polyimide flex wiring and conductive z-axis sintered metal interconnections.

This ChipsetT Fan Out technology allows for large scale production of fan out type solutions which can allow for very thin packages in addition to unique pin out solutions such as pin compatibility for a competitor part.

The ChipsetT SiP also allows embedding of single or multiple silicon die and/or components. Additional components can also be placed using conventional SMT on the top or bottom side of the package. There is a great deal of design flexibility with this technology which makes it a great solution for applications trying to reduce their x-y size or z-height. When utilizing RDL technology on the embedded die we are able to do the fine pitch routing in order to allow the substrate to route at larger pitches ensuring an overall cost effective solution.

This paper will focus on the different classes of applications that have benefited from this technology and will discuss the benefits and tradeoffs of the different solutions that have been engineered. Assembly and reliability data will be presented on several of the applications showing a robust solution set.
Spheron Fan-In WLCSP Technology Qualification and Scale Up - 200 mm to 300 mm
Authors: Cardoso Andre , Almeida Rui , Fernandes Felandorio , Tessier Ted , Curtis Anthony
Published: October 2015

Overview: Fan-In WLP plays crucial role on today's high density, high performance IC Packaging. 300 mm wafer processing addresses cost-per-unit reduction and volume demand. Results of Spheron Fan-In WLCSP Technology Qualification and 200 mm to 300 mm Scale Up at Nanium, using FlipChipInternational Technology Licensing
RF devices: from WLSCP to smart interposers
Authors: LAMY Yann , Bouayadi O. El , Ferrandon C. , Joblot S. , Jouve A. , Dussopt L. , Lacrevaz T. , Bermond C. , Fléchet B. , Simon G.
Published: October 2015

RF wireless devices such as 3G/4G, Wifi, Bluethooth etc... represent today 32% of the whole WLCSP products which know a steady grow above 10% per year [1]. However, a clear trend of combining multi RF chips in one WLCSP module is emerging. This allows shorter RF connections, reduction of BOM and diminution of the overall cost. Complex and heterogeneous RF systems will become possible allowing soon tunability. A silicon package directly reported on board is a good candidate to meet these next challenges of RF WLCSP. Indeed, low cost and multi-chips interposers will soon be produced by TSV fabs or OSATs and tunables devices could be reported on them. But the direct report on board as well as the high frequency signal integrity must be first evaluated carefully.

In this work, we describe promising results of silicon package based on high resistive silicon interposer encompassing 2 levels of Cu Damascene, Tx/Rx antenna, one RF chip and TSV last for 60GHz applications. A new wafer-level molding [2] is performed on front side by lamination at wafer level. On the backside of the interposer, thick Cu RDL and soft layer passivation is deposited before the balling. Just like in WLSCP, different kinds of solder balls are mounted and analyzed with respect to their size (350 or 400 μm) or type (solder or polymer/solder). The passivated interposers are diced and then reported on a PCB, thus forming the silicon package. Low Rf loss (<1dB) attenuation is demonstrated for the routing layers while the antennas exhibit a suitable gain of 5dBi over the 55–65 GHz band. The assembly characteristics between the silicon package and the board will be discussed with respect to the different chosen design rules.

These first results pave the way to a new kind of smart package based on Si interposers, moving forward to more complex WLCSP RF devices.
Electrical Characterization on a High-Speed Wafer-Level Package
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Hlaing MaPhooPwint , Park Susan , Ahn Billy
Published: October 2015

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package
Semiconductor Fluxes for Wafer Bumping in 3D Assembly
Authors: Durham Maria , Mauer Laura , Mackie Andy
Published: October 2015

Spin-coating is an important processing technique used in several industries, whereby a centrifugal force is used to produce a uniform thickness of fluid material on a rotating surface. In particular, spin-coating is being used throughout the electronics industry to coat silicon wafers with different materials such as photoresist (semiconductor fabrication) and bump fusion fluxes (in semiconductor assembly). In this paper the spin coating process for bump fusion fluxes is examined. A mathematical model has been developed for a flux spin-coating process based on material and process variables, the results of which are then compared experimentally with data. The theoretical analysis of a spin coating process is physically and mathematically complex but nevertheless even partial analysis provides insight into the effectiveness and limitations of the process. Variables studied include viscosity, initial dispensed volume, rotational speed, and time.
Lead Free Paste with under 3um Solder Particles for Fine Pitch C4 bumping and pre-coating solder applications
Authors: Uno Hironori , Ishikawa Masayuki , Masuda Akihiro , Muraoka Hiroki , Kuba Kanji
Published: October 2015

The work to be detailed in this paper is our development of 96.5mass%Sn-3.0mass%Ag-0.5mass%Cu fine solder particles with an average particle size of under 3um (D50), using a chemical reduction method. An evaluation was conducted on the properties of the particles. The average size of particles appeared to be under 3um with a higher yield compared to particles using the conventional gas atomization method. The melting temperature of fine solder particles using this method was its eutectic temperature, which is same as using the gas–atomized particles.

120um pitch solder bumps from the solder paste using the above mentioned fine solder particles were created on the substrate. As a result of property evaluation, it was turned out that the solder paste created a superior printing shape and coplanarity compared to the conventional paste with gas-atomized particles.

In order to investigate the superior printing property generated by the paste with fine solder particles, the rheology of the paste was evaluated.It was verified that the anisotropic shape of particles has contributed to prevent the printed paste from slumping, which has resulted in the improvement of printed shape. It also shows that the filling characteristic of the paste was improved by the smaller particles and the better coplanarity was observed. The importance of finer solder particles for finer pitch assembly will be presented.
From Mechanical to Chemical Adhesion
Authors: Hsieh Meng , Libman Ellina , Brandt Lutz
Published: October 2015

In the development of electronic systems, the miniaturization of electronic devices is strongly driven by the market and technology demands within the portable electronics sector. This size reduction affects all subsystems and components. Such reduction is observed in circuitry as the conductor lines and space dimensions are now aiming at dimensions significantly below ten microns. This continuing trend in miniaturization leads to challenges as printed circuits (typically copper) must adhere to a new generation of dielectric substrates, typically highly filled organic resins, for performance and reliability reasons.

Good adhesion of chemically deposited copper to the dielectric surface is currently achieved through mechanical means. The dielectric surface is typically chemically roughened or desmeared. Copper deposited onto the roughened surface will have good adhesion as surface features act as anchoring points. As the dimensions of the circuitry are reduced, a highly roughened surface becomes increasingly undesirable, as it will ultimately create poor line definition or even shorts in the circuit. On the other hand insufficient roughness will result in poor adhesion. It is evident that other means of adhesion (for example, chemical) will become necessary for smaller line widths.

This paper will review the current process for treating the dielectric surface for the subsequent deposition of electroless copper and will compare it to new treatments. The data presented will show that improved copper-to-dielectric adhesion with minimal roughening can be achieved with the new treatments. The origin of the improvement in adhesion is attributed to chemical bonding.
LEDs for SSL - Market Review and Forecast
Authors: Bhandarkar Vrinda
Published: October 2015

This presentation presents an analysis of the worldwide market for LED packages and a market forecast for 2013 through 2016. It attempts to capture the adaptation of LEDs in various lighting applications and the transformation of the marketplace as it shifts to the new lighting technology.

We will also provide an overview of the structure of the lighting industry, the drivers for growth of the lighting market, the specific drivers for growth of LED lighting, and the challenges to further development of the LED lighting market.

The analyses of the top applications for LED in lighting — including 2012 market data and a forecast are presented.
Lithography for Wafer Level Packaging for LED Manufacturing
Authors: Hornung Michael
Published: October 2015

Since LED became an attractive alternative for general lighting, the market demand for higher brightness, higher efficiency and lower costs was the motivation for improving the LED technology. Locking in on the LED manufacturing process, most steps are on die-level after chip singularizing and therefore the costs are dominated by the huge number of dies which could often reach several thousand dies on one wafer. It's obvious that WLP has a clear benefit for LED packaging and it is also the path to success for LED manufacturing. Moreover, it also allows the implementation and integration of additional functionalities to the LED chip module, e.g. electrical connects, Zener-Diode, mirrors, optics drivers etc.

Nonetheless, a clear important aspect to adopt WLP for LED manufacturing is to benefit from existing know-how of the IC manufacturing technology and of the experience of the equipment suppliers for this industry. However, the equipment needs to be optimized for the dedicated LED-WLP application. For example, microlithography with mask aligners is widely used for LED chip manufacturing, but the illumination system of these mask aligner are typically optimized for highest resolution which means contact lithography. For LED-WLP the optical systems must be capable for customized illumination for proximity lithography, where the photo mask and the wafer are separated by a proximity gap of typically 30 to 200 microns. Here, diffraction effects limit the resolution and fidelity of the pattern generated or printed in the photoresist. These diffraction effects are related to the mask pattern and the angular spectrum of the illumination light.

The requirements on the lithography process for LED-WLP will be explained and discussed. Experimental results of perfect 3D patterning on topographies up to several hundred microns will be shown.
Advanced Passive Thermal Management for LED Bulb Systems
Authors: Petroski James
Published: October 2015

The movement to LED lighting systems worldwide is accelerating quickly as energy savings and reduction of hazardous substances (RoHS) increase in importance. Furthering this trend are government regulations, rebate programs and declining prices. The market drive today is to replace light bulbs of common outputs (60W, 75W and 100W) without resorting to Compact Fluorescent (CFL) bulbs containing mercury while maintaining the standard industry bulb size and shape referred to as A19 for fixture retrofitting. This A19 size and shape restriction causes a small heat sink which is only capable of dissipating heat for 60W equivalent LED bulbs with natural convection. 75W and 100W equivalent bulbs require larger sizes, some method of forced cooling, or some unusual liquid cooling system; generally none of these approaches are desirable for light bulbs from a consumer point of view. Thus, there is interest in developing natural convection cooled A19 light bulb designs for LEDs that cool far more effectively than today's current designs. Current A19 size heat sink designs typically have thermal resistances of 5–7 °C/W. A more efficient method of cooling can be created using a chimney-based design to lower system thermal resistances below 4 °C/W while meeting all other requirements for bulb system design. Numerical studies and test data are in good agreement for various orientations including methods for keeping the chimney partially active in horizontal orientations. Such chimney-based designs are capable of cooling 75W and 100W equivalent LED light bulbs in the limited volume constraints of A19-size devices.
A New Embedded Package Structure and Technology for the Next Generation of WLP, the Wafer level Fun-Out Package - WFOP (TM)
Authors: Katsumata Akio
Published: October 2015

Presenting a new embedded package structure and technology for the next generation of WLP, the Wafer level Fun-Out Package – WFOPTM. A face-down mounting style, it has a metal stainless or copper plate as a base plate of redistributed interconnection layer. The redistributed layer is fabricated with a semi-additive method of copper plating. The contact between the die pads and distributed layer is the lead type. With this structure we hope to reduce fabrication cost by using large scale panels and precise redistribution interconnect controls, and its design rule does not depend on the die size. Moreover, WFOPTM has several benefits – applicable to 50μm pad pitch, excellent thermal characteristics and noise shield by attaching the metal plate. We obtained fine reliability test results. In this paper, we report its package structure, process flow, package characteristics and reliability test results and discussion.
A Process Dependent Warpage and Stress Model for 3D Packages Considering Incoming Die/Substrate Warpage and Assembly Process Impacts
Authors: Lin Wei , Syed Ahmer , Lee KiWook , Dhandapani Karthikeyan
Published: October 2015

Warpage control and die stress are critical for 3D package assembly. Currently most of the warpage studies, either measurements or simulations, are mainly evaluated at the end-of-line (EOL) for the finished package. However, for 3D packaging such as multiple die stacking or through-silicon-via (TSV), the interaction between warpage and assembly process steps becomes far more important because: (1) Warpage at each single process step will impact the yield of the next process step. (2) Process induced warpage will accumulated and affect the final end-of-line package warpage, and (3) Die stress in the end-of-line package is highly dependent on the incoming die alone residual stress and the assembly process flow. It is required to develop capability to evaluate warpage at each process step following the process flow.

In this paper, we use a 2-die TSV package as a test vehicle to collect warpage data at each assembly step. A process dependent finite element model (FEM) method is developed which is capable of capturing the process induced warpage and stress at each process step based on the process condition.

Shadow moire is used to measure warpage data at following check points: (1) Incoming bare dies and bare substrate warpage; (2) Die 1 warpage after underfilled on substrate; (3) Die 2 warpage after TCNCP on Die 1; (4) Completed package after molding (end-of-line).

Element birth and kill approach is developed in the FEM model to simulate the assembly process flow. In each process step, only the presented components and materials in the model are active while the others are killed. When new parts or materials are added through the assembly flow, they are activated in the model and the related process condition is applied for each step. Using this process dependent modeling approach, excellent correlation of the model results with the actual measured warpage data is achieved at each process step.

One factor often been ignored is the incoming bare die warpage and bare substrate warpage effect. They are often assumed flat and stress free. However, as die and substrate become thinner and thinner, their incoming initial warpage or residual stress plays an important role. In this paper, the measured incoming substrate and die warpage data are presented, their impacts to the warpage and stress evolution through the process flow are evaluated. A novel method is also developed in the simulation model which is able to study the incoming die/substrate warpage and residual stress effect.
ADVANCED ORGANIC SUBSTRATE TECHNOLOGIES FOR HIGH PERFORMANCE, HIGH RELIABILITY ELECTRONICS MINIATURIZATION
Authors: Bagen Susan , Alcoe Dave , Blackwell Kim , Egitto Frank
Published: October 2015

High reliability applications for high performance computing, military, medical and industrial applications are driving electronics packaging advancements toward increased functionality with decreasing degrees of size, weight and power (SWaP) The substrate technology selected for the electronics package is a key enabling technology towards achieving SWaP. Standard printed circuit boards (PWBs) utilize dielectric materials containing glass cloth, which can limit circuit density and performance, as well as inhibit the ability to achieve reliable assemblies with bare semiconductor die components. Ceramic substrates often used in lieu of PWBs for chip packaging have disadvantages of weight, marginal electrical performance and reliability as compared to organic technologies. Alternative materials including thin, particle-containing organic substrates, liquid crystal polymer (LCP) and microflex enable SWaP, while overcoming the limitations of PWBs and ceramic.

This paper will discuss the use of these alternative organic substrate materials to achieve extreme electronics miniaturization with outstanding electrical performance and high reliability. The effect of substrate type on chip-package interaction and resulting reliability will be discussed in detail, and compared to standard PWB and ceramic. Microflex assemblies to achieve extreme miniaturization and atypical form factors driven by implantable and in vivo medical applications are also shown.
Adhesive Enabling Technology for Directly Plating Copper onto Glass
Authors: Brandt Lutz , Liu Zhiming , Fu Hailuo , Hunegnaw Sara , Magaya Tafadzwa
Published: October 2015

Reliable adhesion of copper to glass is a major hurdle for the entry of glass substrates into the electronic packaging market. Otherwise, glass is a strong competitor to organic substrates due to its superior flatness, thermal and dielectric properties. These are essential requirements for high density interconnects, high speed signal transfer and IC substrate packaging.

Typically, adhesion on glass is achieved by sputtering a thin metallic adhesive (Ti) and copper seed layer followed by galvanic plating.

This paper presents a promising wet-chemical alternative to sputtering. In this new approach a 50-200 nm thick adhesive metal oxide layer is deposited by a modified sol gel process followed by sintering, thus enabling electroless, and galvanic metal plating directly on glass.

Formerly the thickness of the galvanic copper layer constituted a major challenge leading to its facile delamination from the glass. With the new approach, Cu film thickness of over 50 μm can be applied without delamination. Adhesion at 15 μm Cu thickness as measured by 90o peel strength tests can achieve 5 N/cm or even higher values, while 2 N/cm appear to be sufficient to prevent delamination. In comparison, Ti/Cu sputtered glass substrates achieve at best 1.5 N/cm at the same copper thickness, while electroless Cu seeded glass substrates without the adhesive metal oxide layer show no adhesion.

The effect of glass roughness on adhesion was also studied. It does appear to have only a marginal impact on adhesion. On the other hand, the glass type has bearing on the achievable adhesion values. The plated layer stands up well to reflow shock (260C) and HAST without significant loss of adhesion. Good adhesion has been also demonstrated inside the via holes of patterned substrates without indication of blockages by the process.

The process is versatile in that it is also applicable to ceramic substrates such as aluminum oxide.
Pulsed 2 Micron Wavelength Fiber Lasers for Packaging
Authors: Jiang Shibin
Published: October 2015

Fiber laser sources near 2um wavelength have attracted intense interest in recent years because of the combination of high laser efficiency, strong absorption of many visible transparent materials, outstanding reliability, as well as retina safety. In this presentation, we report our latest developments of various 2um fiber lasers at AdValue Photonics for packaging applications, especially Q-switched and mode-locked 2um fiber lasers using our proprietary infrared glass fiber technology.

We demonstrated and commercialized the first all-fiber Q-switched single-frequency laser at a wavelength near 2um using our proprietary rare-earth doped gain fibers. The laser pulsewidth can be 20ns and 180ns, and the peak power can be more than 10kW. Most transparent plastic materials have a relatively strong absorption near 2 micron wavelength, so 2 micron Q-switched fiber laser is one of the ideal laser for transparent plastic welding, marking, cutting, and drilling. Silicon has a good optical transmission near 2 micron wavelength, which allows 2 micron Q-switched to process the material after pass through the silicon wafer as well as remove residual materials containing any organic components. In this presentation we will describe detailed experimental results and present material processing samples for packaging applications.
Dielectric Laser Via Drilling for Next Generation Wafer Level Processing
Authors: Zaccardi Jim , Burgess Guy , Tessier Theodore , Lafenhagen Ken , Souter Matt
Published: October 2015

The common via formation processes used today for dielectrics in WLCSP RDL and flipchip products typically rely on standard photolithography processing using stepper and 1x aligner equipment and processes. There is considerable interest in using laser via drilling (ablation) in dielectrics for flipchip, RDL inner layer, and WLCSP processing for reduced via dimensions and enabling a broader range of dielectric materials, including inherently non-photosensitive options. This presentation will demonstrate “state of the art” laser ablation process results, through different dielectrics showing improved feature resolution and reduced via opening sizes resulting in significantly improved interconnect density. Laser via drilling is a more simplified process compared to traditional photolithography methods. This presentation will demonstrate how using laser via drilling could dramatically improve the design rules for next generation RDL designs.
Patterned Permanent Bonding of Benzocyclobutene Based Dielectric Materials for Advanced Wafer Level Packaging
Authors: Kim Jong-Uk , Choubey Anupam , Bell Rosemary , Dong Hua , Gallagher Michael , Lachowski Joe , Kondo Masaki , O'Connor Corey , Prokopowicz Greg , Barr Bob , Materials Dow Electronic , Zoschke Kai , Wegner Matthias , Lopper Christina , Toepper Michael , IZM Fraunhofer
Published: October 2015

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.
TSV technology embedding high density capacitors for Advanced 3D packaging solutions
Authors: Bunel Catherine , Lallemand Florent
Published: October 2015

TSV is one of the key technologies for 3D integration . TSVs co-integrated with passives including high density capacitors enable highly integrated heterogeneous solutions required because of the smaller size of the electronic modules . Even if there is still a lot to do , significant progress has already been done on the process , on the testability , on the performances of these smart interposers .The major progress is in the adoption of the technology .In this paper we'll expose some examples where the adoption was driven by cost, performances & miniaturization. Emphasis will be placed on the performances of the new generation of 3D Silicon capacitors, using key enabling technology like ALD and amazing architecture that allow impressive capacitance density increase.
Progress in Fabrication and Test of Glass Interposer Substrates
Authors: Shorey Aric , Pollard Scott
Published: October 2015

There is growing interest in applying glass as an interposer substrate for 2.5D/3D applications. Advantages of glass based solutions include significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness.

A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass.

Progress in the ability to fabricate wafers and panels fully populated with through and blind holes has been reported. We describe the ability to leverage existing downstream processes such as via filling of both through and blind vias, as well as novel handling techniques to enable processing of thin glass. We also report progress in evaluating reliability through thermal cycle tests.
Precise solder dispensing in high-throughput micro-device packaging applications
Authors: Liang Hanzhuang , Rolland Linh , Suriawidjaja Floriana , Ahmadi Mani , Park Heakyoung
Published: October 2015

Advanced micro-device packaging sets high and dynamic standard for its supplier industries for speed, precision and flexibility. A high-precision and high-throughput solder paste dispensing process has been developed to fill the gap between novel packaging design and traditional processes of stencil printing and slow dispensing. This process is being used in 25 PCBA production lines to package smart phones, MEMS devices and automobile control panels. These production lines are in full service 24/6 with each dispense system running at 2500unit per hour for simple MEMS patterns, 144uph for complex smart phone patterns and 6uph of full automobile control panels. A well-controlled valve design is applied to achieve high dispensing accuracy at fast speeds. This has removed process design barriers related to dispensing and has matched the high-end platform capability. This process also provides packaging designers with a flexibility superior to the existing solder printing process. The dispense pattern and route can be modified at cost, in minutes and during any step in the design or the assembly stage. Dispensed shapes include dots, lines, rectangle frames and annular rings, with fine edge definition 40um or less. This process can cover a wide range of pattern dimensions between 0.18mm and 100mm. Solder pastes that can be dispensed during this process have 80~90% metal content, type 4 to 6 mesh size. New processes are under development to further push limitations on throughput, dimension, flexibility and material dispensability.
Packaging Materials for Flip Chip and WLP: Underfill Design Using FEM for FC-BGA, FC-CSP, and Moving Towards 2.5/3D.
Authors: Schmaltz Brian , Abe Yukinari , Kohara Kazuyuki
Published: October 2015

As technology nodes progress to 16/14nm and beyond underfill materials are presented with the significantly challenging task of maintaining bump protection while ensuring low warpage for ultra low-K dielectric (ULK/ELK) integrity. This challenge is further complicated by the trend toward RoHS compliancy (lead-free) and an ever increasing die size (beyond 25x25mm). Through extensive research and testing, several specifically formulated underfill materials were determined acceptable solutions for these complex issues. As technology nodes progress to smaller processes high stress concentrations are seen at the dielectric layer during thermal cycling. This stress is a typical result of a high glass transition temperature (Tg) / high strength material that often leads delamination or a cracking failure mode of the thin dielectric layer. Too low of a Tg presents a high stress concentration on the bumps which once again constitutes failure, this time, however, the crack is typically seen at the bump location. This high stress concentration seen at the bumps is more significant when lead free bumps are considered due to their inherent fragile nature. Underfill materials must now be specifically optimized for variable package conditions to solve these failure modes for a large variation of package designs. Desired material properties must be quickly calculated using finite element methods. This paper will discuss solutions to typical failure modes currently seen in reliability testing of present and future technologies.
Design Considerations and Ring-down Characteristics of Micromachined, High Current Density Capacitors
Authors: Beal Aubrey N. , Tatarchuk John , Stevens Colin , Baginski Thomas , Hamilton Michael , Dean Robert N.
Published: October 2015

The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.
Development of Passives on Sapphire Backside
Authors: Ahmad Syed Sajid , Bauer-Reich Cherish , Haring Fred , Strommen Greg , Mattson Kevin , Reinholz Aaron
Published: October 2015

This work is an effort to demonstrate the convenient use of sapphire backside for placing support circuitry for device densification. Laser micromachining is used to form capacitors and inductors on the backside of sapphire. After their fabrication, they can be connected to the circuitry on the front side of sapphire using through-sapphire vias. Antenna, inductor and capacitor design variations have been formed on the backside of sapphire. Here we describe the development work carried out to form such elements on sapphire backside.

Elements were designed and their electrical attributes were simulated. The designed elements were then fabricated on sapphire by laser patterning sputtered and plated surfaces. Physical dimensions of the fabricated elements were compared with designed elements. Electrical measurements on the fabricated elements were compared with initial designs and simulations.
Through-Sapphire Via Filling Process Development for Backside Interconnect and Chip Stacking and Front-to-Back Daisy Chain Chip
Authors: Ahmad Syed Sajid , Haring Fred , Reinholz Aaron , Schneck Nathan
Published: October 2015

With increasing need for electronic systems miniaturization to provide greater functionality in hand-held devices, through-sapphire via paves a way for the greater densification of silicon-on-sapphire devices and systems. Evaluations of two laser systems for via drilling in blank and device sapphire are outlined. Designed experiments were conducted to optimize the process and to minimize sapphire-via parasites (debris and heat-affected zone). Optical and electron microscope observations and measurements were conducted. Effects of varying via drilling techniques were evaluated for via shape and amount of parasitic effects. Laser via-drilling parameters were also evaluated for their effect on via quality. Results of the study show that acceptable through-sapphire via can be achieved and the parasites minimized with the selection of proper equipment and optimization of the drilling process.
Adhesive Enabling Technology for Direct Metal Deposition on Molding Resin
Authors: Mukai Kenichiroh , Kim Kwonil , Eastep Brian , Gaherty Lee , Kashyap Anirudh , Brandt Lutz
Published: October 2015

Plating on molding resin is a relatively new field with many possible applications. One possible application is magnetic or electrical EMI shielding of active components. This is currently done mostly by metallic shells or “caps”. However, this technique also increases spatial requirements and reduces flexibility with respect to component layout on the PCB.

An alternative and more space saving approach is plated EMI shielding. While sputtering a metallic seed layer in preparation of plating is feasible – this process step is not very cost effective or suitable for mass production. In this respect, classical electroless metallization would be much more desirable but has been so far limited by insufficient adhesion.

In this paper we will present a new approach, where components encased by molding resin are directly coated with an electroless copper or nickel layer using an adhesion promoter. By this method spatial requirements are minimized. Also, this process fits into the existing infrastructure within the PCB industry.

Due to the extremely high filler content (70-90% wt.) and the wide size distribution (from tens of nm to tens of μm) of fillers, classical Desmear followed by electroless seeding can get a maximum adhesion of only 2-3N/cm. In contrast, with chemical bonding adhesion promoters as presented in this paper, we are able to get up to 5N/cm of peel strength. The plated layer stands up well to reflow shock (260C) and HAST without delamination or significant loss of adhesion – key requirements for this application.

These adhesion promoters are applicable to various kinds of molding resins. Extending this technology to embedded components can be another far reaching application.
Advanced Electronic Packaging Options for Miniaturization of Complex Medical Devices
Authors: Bagen Susan , Subrahmanyan Ravi , Perrone Ruben , Schulze Daniel
Published: October 2015

Electronics packaging for complex medical devices demands innovation and advanced capabilities, but achieved in a manner which ensures reliability and performance. The evolution of
Highly tunable Mn-doped PZT thin films for integrated RF devices
Authors: Benhadjala Warda , Sonnerat Florence , Guillaume Jennifer , Dieppedale Christel , Renaux Philippe , Le Rhun Gwenaël , Sibuet Henri , Billard Christophe
Published: October 2015

Modern RF systems have triggered an important and urgent demand for inexpensive voltage controlled capacitors used for a wide range of applications such as tunable antennas or low-noise voltage-controlled oscillators (VCO). Ferroelectric materials have received considerable interest for electrically tunable dielectrics due to their high dielectric constant and large dielectric nonlinearity under dc bias field. Lead zirconate titanate (PZT) ceramics which have been under intense investigation for various industrial domains including micro-electro-mechanical systems (MEMS), non-volatile memories, and high-k capacitors, are especially well-known candidate materials due to their unequalled ferroelectric properties and stability in device operating ranges. However, reported voltage tunability of PZT films is relatively low (~35%@4GHz) and remains insufficient for microwave tunable devices. Therefore, much attention has been focused on the PZT modification by adding a small amount of dopants. Shao et al., studied strontium-doped PZT (PSZT) thin films and achieved a tunability of 48% @1MHz. More recently, Hu et al. reported a tunability of 65%@10kHz for lanthanum-modified PZT (PLZT) films. In the presented study, effect of manganese (Mn) doping on electrical properties of PZT (PMZT) thin films has been investigated.

Metal/insulator/metal (MIM) capacitors using PZT-based thin films and ruthenium (Ru) top electrodes were processed on platinized (Pt) silicon wafers by a sol gel method. Dielectric properties of PMZT thin films were studied by varying the dopant amount and compared to those of pure PZT layers. At this end, on-wafer electrical measurements were conducted with a particular attention on leakage current characterization and RF measurements under DC bias voltage. We have shown that leakage current density decreased from 6.5 μA/cm2 to 1 μA/cm2 at 850kV/cm by doping PZT with Mn. Observed conduction mechanisms will be discussed in detail in the full-length paper. Moreover, developed PZT-based thin films exhibit high dielectric strengths achieving 2.1MV/cm and outstanding tunability as high as 85% (~7:1) @1GHz at bias voltage of 20V. Thus, PMZT tunability is among the highest ones reported in the literature for PZT-derived thin films but also for other piezoelectric materials. Indeed, in comparison, the tunability of BST-based materials, typically studied for voltage tunable applications, does not exceed 5:1. These remarkable results indicate that Mn-doped PZT thin films are promising candidates for RF tunable capacitors.
Temporary Bonding of Wafers, Displays, and Components
Authors: Moore John , Pettit Jared , Brewer Alex , Law Alman
Published: October 2015

Packaging practices are conducted on work unit substrates while they are temporarily held in place. This requires a simple adhesion process that enables easy removal without the burdens of complex cleaning. Substrates may be wafers, flexible displays, or components, organic or inorganic, and may contain topography such as solder bumps. The choice of a temporary bonding medium is dependent upon its ability to resist exposure to heat and chemicals. Thermal resistant materials as polyimide (PI), bisbenzocyclobutene (BCB, DOW CycloteneTM), or silicone can support processes that exceed 300°C, depending upon exposure conditions. In building flexible displays, PI materials are popular choices as a substrate processed from liquid and film forms. [1] These products may use silicone polymers, providing low outgas and inert character with an adhesive force tuned to allow substrate removal by peeling without a loss of integrity. Similar approaches are used for discrete, thin, fragile components, attached by dry bonding, processed, and removed by simple peeling practices without observed residue. Examples of die temporary bonding include encapsulation during bumping, permanent bonding, or vacuum deposition of EMI/RFI shielding. [2] The success in these and other technologies depend upon the use of the proper adhesive but most importantly, the tuning of the adhesion force. Successful tuning depends upon many factors, including substrate surface energy, texture, and the bonding process. Daetec has created adhesives used in temporary bonding processes for nearly 20yrs, applying to multiple wafer types, OLED and TFT displays, printed electronics, solar, thinning down to 4um, and thermal resistance >600°C. [3] Our experience in creating solutions for these and other industry needs will be discussed as well as the criteria to temporarily support flexible and rigid substrates of all types, sizes, and shapes.
Cu electroplating chemistry and process enabling rapid TSV filling with long bath life
Authors: Thorseth Matthew A , Gomez Luis , Scalisi Mark , Lieb Bryan , Lefebvre Mark , Calvert Jeff , Erickson Dave , Mikkola Bob , Hoerner Bridger , Burnham James
Published: October 2015

Through-silicon via (TSV) filling with electroplated Cu with short plating times and long bath life remains a challenge within the semiconductor and electronic packaging industries. TSVs are the primary enabler for advanced 3D architectures such as hybrid memory cubes, wide IO DDR memory, as well as chip interconnections through interposers. The TSV needs to be completely filled with void-free Cu for high reliability. Organic additives are used to achieve a bottom-up, superconformal filling profile, required for void-free filling in high aspect ratio vias. The development and selection of the proper organic additives, optimized plating process, and implementation of advanced bath control techniques enable short TSV electroplating times, while also allowing for robust operation and high bath stability. Dow's INTERLINK™ 9200 Cu TSV plating bath with the Applied Materials TSPlus plating system allows 10×100 μm vias to be filled in less than 1 hour and 5×50 μm vias filled in under 20 minutes while having a bath life greater than 40 A hr L-1 in continuous operation. This combination also exhibits low overburden for stress management, CMP cost reductions, and high reliability.