Formation of Low-Resistivity Metal/Germanium Contact with Ultra-Thin Interlayer and Plasma Oxidation for n-Channel Germanium FET
Authors: Kim Gwang-Sik , Kim Seung-Hwan , Park June , Kim Sun-Woo , Yu Hyun-Yong 
Published: February 2020

Germanium (Ge) has emerged as a new channel material substituting traditional silicon (Si) in CMOS technology due to its high carrier mobility and process compatibility with Si. However, n-channel Ge MOSFET has not exhibited high performance because of some bottlenecks. High source/drain (S/D) contact resistance resulted from Fermi-level pinning (FLP) between the metal and Ge is the most serious obstacle for the development of Ge n-MOSFET. The metal/n-Ge contact has very large Schottky barrier height, approximately 0.55eV, regardless of metal work function because the Fermi-level on the metal side is strongly pinned to the edge of the valence band of Ge. Metal-induced gap states (MIGS) are the main cause of Fermi-level pinning, however, effect of interface states at the Ge surface on FLP is turned out to be not small by previous researches [1, 2]. Therefore, it is important to reduce both MIGS and interface states in order to alleviate FLP and form low-resistance Ge S/D contact.

In this work, moderately-doped n-Ge wafer (N
d = 1×1017 cm–3) was used as a substrate. In order to alleviate FLP of metal/n-Ge contact, 1.5 nm-thick ultra-thin TiO2 layer is inserted between the metal and n-Ge to block MIGS penetration into the energy gap of Ge, and plasma oxidation process is introduced before and after TiO2 deposition, respectively, to passivate Ge surface and reduce interface states [3]. Two approaches of plasma oxidation are applied; pre-oxidation and post-oxidation. The plasma oxidation process was carried out using ICP-RIE system. For pre-oxidation process, Ge substrate was oxidized prior to the TiO2 deposition with source power of 500 W, no bias power, gas flow of O2 40 sccm/Ar 5 sccm, pressure of 10 mTorr, and process time of 70 sec. For post-oxidation process, Ge substrate was oxidized after the TiO2 deposition with bias power of 50 W and process time of 30 sec with other plasma conditions not changed. The TiO2interlayer was deposited using atomic layer deposition (ALD) system at process temperature of 250 °C.

As a result, a back-to-back reverse current density of Ti/TiO2/GeOx/n-Ge structure is improved compared to that of Ti/TiO2/n-Ge structure for both pre-oxidation and post-oxidation as shown in Fig. 1, which means Fermi-level on the metal side was more unpinned due to the GeOx passivation layer. It exhibits 4 orders of magnitude of reverse current improvement than the Ti/n-Ge structure does. Besides, the TiO2/GeOx stack shows better electrical properties than single TiO2 does when they have the same total thickness, approximately 2.1 nm (not shown here). It means an increase of single interlayer thickness in metal-interlayer-semiconductor (M-I-S) structure cannot be the best solution for FLP, and multi-layered structure should be introduced to reduce both MIGS and interface states. The Ti/TiO2/pre-GeOx/n-Ge shows slightly better performance than the Ti/TiO2/post-GeOx/n-Ge does. This is because the amount of GeOx formed by post-plasma oxidation process is smaller than that formed by pre-oxidation process due to the presence of TiO2 interlayer as shown in Fig. 2. Thicker GeOx can block MIGS more resulting in slight increase of reverse current density, however, GeOx layer formed by post-oxidation process has more GeO2-like characteristics which can passivate Ge surface better. For this reason, the Ti/TiO2/post-GeOx/n-Ge structure exhibits more ohmic-like (i.e., more linear) I–V characteristics, and post-oxidation process is considered to have more potential to plasma passivation process for the M-I-S structure.

In conclusion, we successfully demonstrate the effect of pre- and post-oxidation process on Ge M-I-S structure. The GeOx layer formed by plasma oxidation between the metal and the TiO2 interlayer can reduce interface state density resulting in additional Fermi-level unpinning. Therefore, this plasma oxidation process with M-I-S structure can be a key technology to overcome the bottleneck of Ge n-channel MOSFET development by alleviating FLP effectively and reducing S/D contact resistance.

[1] G.-S. Kim et al., IEEE Electron Device Lett., 36, 8 (2015)

[2] J.-R. Wu et al., Appl. Phys. Lett., 99, 25 (2011)

[3] J. Kang et al., Opt. Express, 23, 13 (2015)

Figure 1