bluuebunny/crossref_metadata_2025 huggingface dataset:
Estimation of the species richness of hyperdiverse beetles (Coleoptera: Cerambycidae) in an area of Atlantic Forest, Minas Gerais, southeastern Brazil
Authors: Gatti Felipe Donateli , Carneiro Marco Antonio Alves
Published: December 2019

Species are elementary units in community ecology studies. However, sample limitations obstruct the elaboration of accurate faunistic inventories, especially in biodiversity hotspots, such as tropical forests. In this way, the objective of this research was to describe the richness, using different non-parametric estimators of richness, in the family Cerambycidade, a group of hyperdiverse insects in the Atlantic Forest. Five hundred and eighty-one specimens belonging to 145 species and 3 subfamilies were collected. Among the species sampled, 46.2% were considered singletons, 13.8% doubletons, 48.95% unicates, 15.15% duplicates and 90.3% ecologically rare. The species accumulation curves did not stabilize, which was already expected considering that more species and individuals were sampled in the last months of collection. The estimated richness presented values much higher than the observed richness. This was a reflect of the high proportion of ecologically rare species present in the sample. This work showed that faunistic inventories of hyperdiverse groups, with only one year of collection and a single sampling methodology may underestimate the species richness of a region. Thus, larger time series associated with different collection methods are essential for a more accurate survey of biodiversity in the Atlantic Forest.
Contraphe der abgeleibten fürstlichen Bischöff zu Seccau. K portretni galeriji sekovskih škofov v gradu Seggau
Authors: Lein Edgar
Published: December 2019

V škofovski galeriji v reprezentančnih prostorih gradu Seggau je razstavljenih 58 dopasnih portretov sekovskih škofov. Portretna galerija je bila prvič omenjena v in- ventarju, ki je bil spisan leta 1675, v času škofa Venclja Viljema Hofkirchna (1670–1679). Portreti so bili prvo- tno nameščeni v prostoru, imenovanem velika dvorana (großer Saal) ali škofova soba (Bischofszimmer). Okrog leta 1830 je mogoče škofovo sobo locirati v prvo grajsko nadstropje. Med letoma 1835 in 1867 so portrete prenesli v dve sobi v drugem nadstropju, kjer so še sedaj. Vzor za škofovsko portretno galerijo so bile freske v škofovski kapeli samostana Seckau, ki jo je zasnoval škof Martin Brenner. Galerija je primerljiva z drugimi škofovskimi portretnimi galerijami v Salzburgu, Augsburgu, Dillin- genu, Kroměřížu in Šentandražu (danes v Mariboru). Paradigmatični za portretne galerije so trije temeljni koncepti: tradicija, nasledstvo in memoria.
Grofje Brandis – umetnostni naročniki na Štajerskem
Authors: Lazarini Franci
Published: December 2019

Prispevek govori o umetnostnem naročništvu grofov Brandis, tirolske plemiške rodbine, ki je v 18. in prvih treh četrtinah 19. stoletja imela v lasti več posestev na Štajerskem. Avtor analizira pomen članov naročniško precej aktivne rodbine, ki je med drugim zaslužna za barokizacijo mariborskega mestnega gradu in dvorca Betnave, porušitev gradu Gornji Maribor in postavitev klasicistične piramide ter kasneje kapele Brezmadežne na njegovem mestu, temeljito prezidavo dvorca Slivnica in izgradnjo grobne kapele na pobreškem pokopališču.
IMF, World Bank, and the European Union With the Perspective of New Institutional Economics
Authors: Tatar Havanur Ergün
Published: December 2019

According to New Institutional Economics, the GDP per capita has significantly improved in the countries where the institutional quality has been improved. In addition to this information, the increase in the quality of institutional determinants has positive effect on economic performance. In this chapter, after the structures of IMF, World Bank, and European Union have been discussed, the governance debate will be made on the aforementioned institutional. Concepts about new institutional economics are discussed, as are the improvement of institutional quality and the relationship of economic development within the frame of IMF, World Bank, and European Union.
Structural Shifts and Patterns in Turkey's Foreign Trade
Authors: Muratoğlu Gönül Dinçer
Published: December 2019

Foreign trade has been a principal tool of the economic policies implemented in Turkey since the foundation of the Republic in 1923. In parallel with the significant developments in the national and global economies, several structural transformations occurred in foreign trade patterns and policies of Turkey. Political approaches varied from strictly protectionist trade regimes to semi-open models and free trade regimes. Previously implemented protectionist trade policies were abandoned in the 1980s for the current open economic policy based on export-led growth model. All these facts led to drastic changes in the composition of goods subject to both Turkey's exports and imports. This chapter examines the fundamental shifts and changes in Turkey's foreign trade by reviewing historical developments, and specifies the existing structural problems in Turkey's foreign trade by analyzing detailed trade data.
Analysis of the Heat Affected Zone and Surface Roughness during Laser Micromachining of Metals
Authors: Kaselouris Evaggelos , Skoulakis A. , Orphanos Yannis , Kosma K. , Papadoulis T. , Fitilis I. , Clark E. , Markopoulos Angelos P. , Bakarezos M. , Papadogiannis Nektarios A. , Tatarakis Michael , Dimitriou Vasilios
Published: December 2019

The current research focuses on the characterization of the produced heat affected zone when laser heats AISI H13 steel, AISI 1045 steel and Ti6Al4V alloy workpieces via finite element simulations and experimental investigation. The surface roughness designedly varies on the surface of the samples and its influence on the absorption of laser light is investigated. Experiments are conducted at 1-4 W laser power and for two scanning speeds of 2 and 100 mm/min. A 3D transient thermo-structural finite element model for a moving Gaussian laser heat source is developed to simulate the micromachining process and predict the depth and width of the heat affected zone. The Johnson-Cook material model that takes into account the effect of plastic strain, strain rate and temperature, along with a fracture model, is adapted to the simulations. A good agreement between the experimental data and the simulation results is found. The depth and width of the heat affected zone strongly depend on the laser parameters and material properties of the irradiated samples. This study constitutes the basis to the optimization and improvement of the laser assisted micromachining process parameters and provides key insights on the roughness-absorptivity relation for the three metallic materials.
Analysis of Maximal Operation Amplitudes of Piezoelectric Vibration Energy Harvesters
Authors: Majer Zdeněk , Ševeček Oldřich , Štegnerová Kateřina , Rubeš Ondřej , Tofel Pavel , Hadas Zdenek
Published: December 2019

The paper deals with an analysis of maximal operation amplitudes of piezoelectric energy harvesting systems generating electrical energy from ambient vibrations. Energy harvesting systems could be very interesting alternative for autonomous powering of ultra-low power electronics, sensors and wireless communication. A design of piezoelectric vibration energy harvester is based on the cantilever beam design with active piezoelectric layers. The output power is proportional to an amplitude of relative oscillation of this resonance mechanism. This paper presents an analysis based on the simulation model of multidisciplinary piezoelectric energy harvesting device, enabling an optimization of its key parameters ensuring a maximal efficiency of the system. Such analysis is also essential for development of new energy harvesting systems formed of new smart materials and structures which could be integrated in future development processes.
Smart Bondline Monitoring of an Efficient Industrial Thermoplastic Aircraft Window Frame
Authors: Bekas D.G. , Saenz-Castillo D. , Sharif Khodaei Zahra , Alonso F.J. Chamorro , Aliabadi M.H.
Published: December 2019

In this work, a smart thermoplastic window frame for a regional aircraft has been designed and manufactured. The aim of the work was to design a smart sensing system for monitoring of a bonded thermoplastic aircraft window frame in operation. The conductive tracks were designed and inkjet-printed onto the window frame and their disruption was used as an indication of a damage event created within the bondline. Based on the electrical resistance measurements, the method was able to detect a damage that was created in the bondline due to an impact event. To verify the proposed methodology, ultrasonic C-scan inspection was also performed.
Acute Pain Management for Patients Receiving Medication-Assisted Therapy
Authors: Compton Peggy
Published: December 2019

Evidence-based approaches for the treatment of opioid use disorder include the use of opioid medications (methadone, buprenorphine, or naltrexone), collectively referred to as medication-assisted therapy. Patients receiving medication-assisted therapy may present in the acute care setting with pain, often related to planned surgical procedures to treat health issues that were not addressed before entering treatment. Because these medications act on the same receptors as do analgesic opioids—and, in the cases of methadone and buprenorphine, have analgesic properties — managing acute pain in these patients can be challenging. Principles of effective pain management for these patients include continuing the usual medication-assisted therapy dose; using nonpharmacological and nonopioid pain management strategies as possible and immediate-release opioids, titrating to effect and monitoring for toxicity; anticipating tolerance and hyperalgesia; and establishing a collaborative treatment relationship with the medication-assisted therapy provider. Providing effective pain treatment supports ongoing recovery in patients with opioid use disorder.
Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules
Authors: Singh Akhilesh K , Sullivan Kevin M , Leal George R , Gong Tony
Published: December 2019

System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity of packages increases (multi die, large number of passives, through mold via interposer for external memory, convergence of different technologies). This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. The prototype test package with three flip chip die was processed using different bump structures with bump height variation and differences in coplanarity. The underfill dispense pattern was optimized to eliminate underfill creep to the top of passive components that could lead to interfacial delamination. The interposer solder had no reliability risk due to the added mechanical strength of the underfill. Laser ablation formed through mold vias (TMV) on top of the interposers to connect to a package on package memory device. Partially defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination concerns were mitigated by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).
Prospects for automotive SiP modules applying IC assembly and packaging technology
Authors: Furukawa Tomohiro , Kasuga Takahiro , Umehara Masato , Tamadate Yuka
Published: December 2019

We develop a package that ensures quality complying with AEC-Q 100 Grade 2 which is in-vehicle quality from various flip chip mounting methods and bump sealing technology with underfill resin and mold resin. FC CSP with heat spreader mounted on the product which has started mass production since last year is in the lineup, The heat dissipation can be improved by attaching the heat spreader directly to the chip backside which are heat sources and the Thermal Interface Material (TIM), using our assembly technology of flip chip mounting and molding the periphery while exposing the chip backside. By adjusting the Coefficient of Thermal Expansion (CTE) and thickness of the material, we realize low warpage and low coplanarity at reflow temperature and product use temperature environment and reduce package displacement behavior, we will improve the secondary mountability to the motherboard and provide reliable packages. Furthermore, it can be applied to SiP modules.

It is also possible to construct multiple chip modules by mounting multiple ICs or placing low-passive components around them. We will consider heat spreader mounting on multiple ICs that generate heat, and metal coating on the entire SiP module to have a structure that achieves both heat dissipation and electromagnetic shielding as a future idea.
Package Reliability and Integrity Improvements for a Thermally Enhance Non-Conductive Die Attach Adhesive for ASIC Devices on Exposed Pad Packages
Authors: Denoyo Alvin , De Lazo Darwin , Costa Ivan , Menor Allen
Published: December 2019

Polymers being used in a plastic-encapsulated integrated circuit (IC) package exposed to a humid environment absorbed moisture and expand resulting to a so called delamination failure. Weak or imperfect adhesions between the interfaces of the mold compound and adhesive unto the leadframe surface are often the main sources of these failures. In response to automotive requirements and to ensure excellent package reliability and integrity, delamination in all interfaces should then be eliminated. Thus the primary objective of this work is to fulfill the no delamination criteria in all interfaces after moisture soak for an exposed pad package. To satisfy these requirements, activities includes leadframe design improvements, surface enhancement and bill-of-material changes. With the design improvements implemented, still the material compatibility plays an important role in achieving improved package reliability.
Flip-Chip Flux Evolution
Authors: Mackie Andy , Jo Hyoryoon , Lim Sze Pei
Published: December 2019

Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage.

This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.
Low thermal resistance packaging for high power electronics
Authors: Shashidhar Nagaraja , Rao Abhijit
Published: December 2019

Alumina and aluminum nitride substrates are routinely used in micro-electronic packaging where large quantity of heat needs to be dissipated, such as in LED packaging, high power electronics and laser packaging. Heat management in high power electronics or LED's is crucial for their lifespan and reliability. The ever-increasing need for higher power keeps challenging the packaging engineers to become more sophisticated in their packaging.

With the availability of a 40 μm thick, high thermal conductivity ribbon alumina from Corning, the options available for packaging engineers has widened. This product has very high dielectric breakdown (~10kV at 40 μm thick), high thermal conductivity (>36 W/mK) and is rugged enough to be handled (with components attached) during packaging. These characteristics make ribbon alumina a cost-effective alternative to incumbent materials such as thick aluminum nitride, for use in high power microelectronics packaging.

In this paper, high power LED and IGBT modules are modeled using commercially available code from ANSYS®. A geometry representative of typical LED packaging and IGBT packaging is constructed with Ansys Design Modeler platform and the allied meshing is done employing in-built Meshing tool in ANSYS Workbench®. We show that packaging with ~40 μm ribbon alumina delivers performance on par with or better than packaging with thicker aluminum nitride substrates.
Reliability of screen-printed conductors and resistors during fatigue cycling on flexible substrate
Authors: Garakani Behnam , Sandakelum Somarathna K Udara , Weerawarne Darshana L , Poliks Mark D , Alizadeh Azar
Published: December 2019

Scalable printing of conductor and resistor components has revolutionized the field of flexible electronics by enabling a myriad of low cost highly conformable devices. Flexible electronic devices need to exhibit reliable performance under strenuous mechanical deformations to be adopted in applications such as human and asset monitoring. The reliability of the devices is in turn affected by the microstructure of the materials, manufacturing processes, and conditions of use.

In this research, the mechanical behavior and microstructural properties of stretchable silver conductor and stretchable carbon conductor inks on flexible substrate are studied. The test vehicles (such as 4- point probe structures are screen printed on thermoplastic polyurethane (TPU) and cured in a convection oven. The quality of the printed traces including the resolution and thickness profile are measured by Confocal Laser Scanning microscope. The microstructure of the sample including particle/nanoparticles morphology is studied by Scanning Electron Microscopy (SEM). The electrical resistance is measured by 4-point probes method and the sheet resistance of the printed samples is calculated. The mechanical and electrical reliability of the samples are investigated by fatigue-cycling and in-situ measuring of the electrical resistance. In terms of electrical conductivity, the silver printed traces show different behavior compared to the carbon printed samples when exposed to fatigue cycling. The electrical resistance of the printed silver trace increases during the fatigue cycling. Higher extension rate along with higher strain magnitude accelerate the rate of increase in the electrical resistance. The relative electrical resistance of the carbon trace initially drops to 0.7 after 40 cycles and remains constant for the rest of the cycles. The extension rate does not considerably change the electrical resistance of carbon trace. The stability in electrical resistance is crucial in applications where electrical shielding is concerned.
Ultra-Thin Wafer-Level Chip Scale Packaging
Authors: Hackler Douglas , Wilson Dale , Prack Edward
Published: December 2019

IC packages are getting thinner to facilitate thinner electronics products. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer™ (SoP) Chip Scale Packaging (CSP) is enabling ultra-thin flexible hybrid electronics and sensors today. This presentation shares the development, of SoP application to flexible hybrid electronics (FHE), and where SoP fits in IC packaging technologies. SoP CSP facilitates more functionality for hybrid approaches with printed electronics by allowing seamless integration of thin die into flexible/printed electronics with high reliability. Reliable thin die are an enabler for thinner conventional IC packages and potentially for thinner embedded packages (both FO and substrate based). The presentation also shows the technology roadmap for SoP application to IC packaging.
Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization
Authors: Evans Tristan M. , Le Quang , Narayanasamy Balaji , Peng Yarui , Luo Fang , Mantooth H. Alan
Published: December 2019

The design of power electronics modules is undergoing renewed interest as new challenges and technologies emerge in the realm of wide bandgap (WBG) power device packaging. In order to meet the demands of these high-speed transistors, novel techniques are required to produce modules with reduced parasitics and noise generation without exceeding the operating temperature of the devices or their packaging materials. Traditionally, power module design has been a highly iterative process—repeatedly reworking and simulating designs using finite element analysis (FEA) tools that require considerable time in terms of both labor and computation. To overcome these issues, an electronic design automation tool (EDA) known as PowerSynth is ongoing in its development toward power module layout synthesis and optimization based on electrical and thermal criteria. In this paper, work to extend the capabilities of PowerSynth to optimize layouts with reduced electromagnetic interference (EMI) is presented. Optimization strategies based on the transfer functions of noise propagation paths are introduced and results showing layouts with reduced noise generation are compared with FEA simulations.
Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection
Authors: Chien Chun-Hsien , Chen Chien-Chou , Yeh Wen-Liang , Lin Wei-Ti , Wu Cheng-Hui , Chen Fu-Yang , Lin Yi-Cheng , Wang Po-Chiang , Li Jeng-Ting , Lin Bo Cheng , Chen Yu-Hua , Tseng Tzyy-Jang
Published: December 2019

In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.
LTCC slot array antenna for 5G application
Authors: Takahashi Hiroyuki , Hirano Satoshi , Yamashita Daisuke
Published: December 2019

We develop the antenna module substrate which is broadband and large gain using an LTCC technology in a 28GHz band in this study. We used LTCC materials (dielectric constant 5.8, Dielectric loss 0.002@28GHz) which we developed for materials originally. First of all, we confirmed ability of slot array antenna made by LTCC for 5G application to get broadband property. The structure of designed array antenna became 40mm × 3.2mm × t1.6mm. We confirmed that this antenna has wider bandwidth (2.2GHz) and higher gain (6dBi). But this antenna size is too large for applying mobile device. Therefore we redesigned to reduce antenna size without specification degradation. The structure of redesigned antenna element becomes basically 4.8mm × 6.7mm × t1.0mm. This antenna has wider bandwidth (2.7GHz). The gains are more than 5dBi for the characteristic of this element in a band. Assume this antenna a fabric; 2 × 2 (4 elements: for mobile device) and 4 × 4 (16 elements: for small cell base station) we make an array antenna for Small cell base station and for mobile device. We will evaluate a beam steering examination with emission properties (gain, beam angle).
Non-destructive In-line IMC Thickness Measurement Using Acoustic Metrology for 3D Stacking
Authors: Mehendale M. , Hou L. , Mair R. , Kotelyanskii M. , Liebens M. , Derakhshandeh J. , Mukundhan P. , Miller A. , Beyne E. , Kryman T.
Published: December 2019

The constant demand for small-feature-size, high performance and dense I/O applications have necessitated the development of fine-pitch vertical interconnects for 3-D integration. Microbumps and through silicon vias enable the high-density vertical interconnects. As microbumps scale, intermetallic compound formation during thermocompression bonding and its impact on reliability is a concern. In this paper, we describe the application of picosecond acoustic metrology technology as a viable option for non-destructive characterization of the intermetallic compounds. The small spot size technology allows measurement on small bumps, with very good accuracy and repeatability.
Contact Electroplating Technology (CET)
Authors: Kadija Igor V.
Published: December 2019

Whenever possible electroplating is the most preferred method of metallizing interconnects and devices in electronics. It delivers metals and alloys with their physical and chemical properties closest to the ideally attainable level. To do so the-state-of-the-art electroplating processes in electronics rely entirely on making direct contact of the power supply to the electroplated part. This is done either by having a heavier gauge clamp attached to one end of the object to be plated or with a, sometime intricate, conductive path or seed layer capable of delivering adequate electroplating polarization to the electroplated parts of the pattern. In most instances that type of direct link to the power supply presents a nuisance, forcing the designer of electronics to cope with the introduction of non-functional patterns, such as seed layers, taking space from the precious real-estate of the electronic substrate. Therefore, it is desirable to have an efficient way to enable metallization of isolated electronic patterns by electroplating, without sacrificing the substrate real-estate for establishing direct contact to the power supply. More recently a novel and potentially practical approach was introduced by ECSI Fibrotools. This process is the subject of this article. By applying the Contact Electroplating Technology (CET), US Patent #10,184,189, with up to several million electrical contacts per square inch, each isolated structure is simultaneously contacted and charged by the main power supply via the CET's working electrode. CET technique has been demonstrated with actual patterned structures of various substrates such as PWB surface finishing, flexible electronics, and various small electronic devices. CET technology enables completing or upgrading the electronic structures by electroplating of pure metal or alloy of desired thickness up to 10 microns or thicker if needed. Electroplating occurs directly on thin seed layer, laser ablated, or toner drawn patterns enabling well-defined metal plating. Completely isolated electronic interconnects were uniformly electroplated for surface finishing with Cu, Ni, Ag and Au.
Low Profile and Large Size WLCSP in IoT Applications
Authors: Tang Tom , Kuo Kuei Hsiao , Lin Victor , Chen Kelly , Chen J.Y. , Ma B.H. , Wang Yu-Po
Published: December 2019

Recently, Wafer Level Chip Scale Package (WLCSP) Package is being rapidly adopted in Internet of Things (IoT) and consumer mobile electronics due to its low profile, small form factor and relatively easy assembly process. WLCSP with large die size becomes the trend in fulfilling high performance product demands. However, the solder joint reliability performances of WLCSP is the key challenge and becomes critical as increasing die size, especially the size is larger than 6 × 6 mm2.

There is also growing interest in low profile WLCSP packages to less than 300 microns, especially when they are placed in a limited space inside IoT devices. Thin wafers are fragile and must be supported over their full dimensions to prevent cracking and breakage. An increasingly popular approach to thin wafer handling involves grinding and taping thin wafers with in-line machines. A specific carry tape have been also developed for transferring thin wafers after thinning.

In this paper, WLCSP board level reliability for both large die size and low profile was studied, a test vehicle used for the large WLCSP package testing has 350um ball pitch and fully populated array. In addition to board level reliability test simulation and data collection, processing challenges were discussed, as well as processing solutions for thin wafer handling.
A Novel Dicing tape for WLCSP Using Stealth Dicing Through Dicing tape and Back Side Protection-Film
Authors: Furuno Kenta , Yamashita Shigeyuki , Wakayama Yoji , Saiki Naoya , Takyu Shinya
Published: December 2019

Market demand of information terminals for Internet of Things (IoT) is increasing. So market situation requires various semiconductor packages. Wafer Level Chip Size Package (WLCSP) is one of the most important technology among them. We selected stealth dicing (SD) as a manufacturing method for WLCSP because the cutting speed is higher than blade dicing and the yield of semiconductor chip is higher than blade dicing. But, SD process still has some technical issues. In some cases, when the laser is irradiated from circuit side (from surface side of Si wafer), the metal pattern in circuit might prevent the laser focusing. In this case, the laser should be irradiated from backside of Si wafer through dicing tape. We have already developed a transparency suitable dicing tape for the SD process, but the base film material of the dicing tape is poly vinyl chloride (PVC) which is not becoming to conform with some of recent environmental standard. Market situation requires poly olefin (PO) dicing tape because of global environmental consideration. We developed PO dicing tape for SD process through dicing tape by conducting various evaluations. In this study, we report details of the development process of novel PO base film dicing tape with the same performance as PVC base film dicing tape and successfully separated a 12 inch silicon mirror wafer into 1 mm die squares and 12 inch silicon mirror wafer with the back side protection-film into 6 mm die squares.
How to secure the fabrication of Gallium Nitride on Si wafers
Authors: Alliata D. , Anderson N. , de Gevigney M. Durand , Bergoend I. , Gastaldo P.
Published: December 2019

Process control solutions to secure the High-Volume Manufacturing of Gallium Nitride (GaN) devices for power applications are a must today. Unity recently developed and introduced on the market a total control solution that address both defectivity and metrology needs of GaN industry. Proprietary technologies like Phase Shift Deflectometry, darkfield inspection, confocal chromatic imaging and infrared interferometry are here explored to detect killer defects potentially affecting the gallium nitride wafer. More in detail, we characterized Gallium nitride on Silicon substrate before and after the fabrication of the final device and demonstrated how the fabrication process can be optimized.
Optimizing the Within Wafer Non-Uniformity at the Chemical Mechanical Planarization step in Interposers and RDL fabrication process for 3D IC stacking
Authors: Kumar Amit , Chacon Jose , Gelzinis Peter , Velaga Ankineedu
Published: December 2019

Chemical Mechanical Planarization (CMP) is an integral step in fabrication processes of through silicon via based Interposer and Redistribution layer for routing. The key motivation in the CMP process is to achieve planarization with minimum recess and dishing on the metal routing sites. In this work we established the metrics for Within-wafer non-uniformity (WIWNU) and optimized the CMP parameters. Currently, there is no standard guideline for reporting the WIWNU during CMP and thus a better understanding and practice is needed to enhance post CMP uniformity across the wafer. The work reported in this article were conducted on 200 mm silicon wafers with either Copper or Tungsten to optimize the uniformity of removal rate with respect to polishing parameters, such as slurry flow, slurry composition, down force, relative velocity of wafer surface with pad, etc. With optimized CMP parameters for blank wafer, the WIWNU in patterned wafer were evaluated and analyzed for additional optimization in non-uniformity.
Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration
Authors: Liu Wei-Wei (Xenia) , Weng Berdy , Lai Lu-Ming , Chen Kuang-Hsiung
Published: December 2019

Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..
Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study
Authors: Bernhard T. , Gregoriades L. , Branagan S. , Stamp L. , Steinhäuser E. , Schulz R. , Brüning F.
Published: December 2019

A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.
A Wirebonding Instrument for Insulated and Coaxial Wires
Authors: Meinhold Mitchell , Gray Caprice , Delisio Jeffery , Kim Ernest , Wells Christian , Torres Daniela , Lewis Peter , Hagerstrom David
Published: December 2019

A tool has been developed that supports a novel microelectronic integration paradigm whereby interconnects between components are directly established by way of micro-coax wirebonds. A near term use-case of the tool is to facilitate rapid prototyping of high-bandwidth systems. When further matured, it will lead to the ability to rapidly integrate complex systems with hundreds or thousands of interconnects with minimal design time. Automatic stripping and bonding of coax wires having overall diameters between 50 to 150μm presents an array of process challenges that pose interesting demands on the material system of the wire and the bonding tool. This paper will review a micro-coax bonding system that is currently in development at Draper which is able to strip, feed and bond micro coax wire. The system utilizes a combination of electric-flame-off (EFO) and thermal reflow to strip outer metal shielding and polymer dielectric layers respectively. It leverages a rotary wire feed mechanism to precisely control wire position so that pre-determined wire-lengths can be established. Progress in design of the wires, tooling and software control architecture are reviewed.
Controlling Surface Sensitive Processes in Microelectronics Manufacturing to Improve Wire Bonded Joint Reliability
Authors: Kidd E.J. , Campbell Brooke , Dillingham R. Giles
Published: December 2019

Validating surface chemical composition and properties of die pad surfaces is crucial for achieving joint reliability in microelectronic wire bonding operations. Die pad surfaces undergo a number of surface sensitive manufacturing steps prior to bonding that will affect joint performance; contact and environmental contaminants from process aids, shipping, handling, storage and out time are all key players in surface degradation. Microelectronics manufacturers may implement cleaning and/or surface activation operations to remediate surfaces from upstream contaminants, however, understanding and quantifying the effect of such processes requires the ability to manipulate and monitor the top few molecular layers of a material responsible for adhesion—the surface.

This presentation will investigate surface chemistries of atmospheric plasma cleaned and non-cleaned die pad surfaces as determined by X-ray photoelectron spectroscopy (XPS) and surface energy measurements via contact angle techniques.
Process advantages of thermosonic wedge-wedge bonding using dosed tool heating
Authors: Hunstig Matthias , Unger Andreas , Brökelmann Michael , Hesse Hans J.
Published: December 2019

Thermosonic wire bonding has a number of advantages over “cold” ultrasonic wire bonding. Despite these potential advantages, it is rarely used besides ball-wedge and gold wedge-wedge applications, mostly due to the drawbacks and limitations of available heating technology. A recently introduced novel thermosonic process using a laser-heated bonding tool avoids most of these drawbacks. This contribution presents the results of two series of bonding tests which have used this novel process to bond aluminium and copper heavy wire to sheets of the same metal.

The bond test results prove that thermosonic wedge-wedge bonding with a laser-heated tool has a number of significant advantages in both aluminium and copper wire bonding. It can be used to reduce the process time, to decrease the mechanical stress in the substrate by reducing ultrasound vibration amplitude and/or normal force, and to increase bond strength. These advantages are the same as in classic thermosonic wire bonding, but without the major disadvantage of having to heat to whole package. Because of the high thermal conductivity and capacity of the investigated metal sheet substrates, the observed positive effects of a heated tool are expected to be significantly higher on real-world substrates such as power semiconductors.
Three-Dimensional Thermal Modeling and Management of System on Package with Gold and Nano Based Material
Authors: Khan Be-nazir
Published: December 2019

A detailed computational fluid dynamic based thermal model and simulation of exposed pad SOIC package on PCB is developed with Nano and gold-based material to characterize the thermal behavior or cooling capability of the package. Achieving lower thermal resistance of electronic packaging is one of the important points of interest in electronic application. In this paper, exposed small outline IC package on PCB is compared with different composition of Au-Sn die attach materials and Nano-foil preform material to understand the thermal behavior of the package which will provide cooling through low thermal resistance between junction-to-case. Thermal reliability of electronic packaging depends on the package design and selection of materials. Package material design plays an important role in thermal management of the product. Nano-based package material can be a good choice to improve the thermal performance of system on package. Developed a 3 D model of exposed small outline IC (E-SOIC) package on a printed circuit board (PCB). Au-Sn solder paste is used as die attach material and Nano-Foil preform is used to develop the system on package (SOP) model of exposed pad SOIC package on PWB. Different types of composition of Au-Sn solder paste, such as 78Au22Sn and 80Au20Sn are considered for die attach purpose. The reason for choosing the AuSn solder paste is good reliability and performance. Au-Sn has higher thermal conductivity than other solder materials, such as Pb-free solder paste, 96.5Sn3.5Ag and leaded solder paste, 37Pb63Sn. Two types of thermal model developed to compare the package material and design of the different die attach materials and Nano-Foil preforms. In this paper simulation and data analysis will show how the optimum thermal management depends on the material selection and design of the system on package (SOP). Surface mount type SOIC package with exposed pad design is selected to enhance the thermal purpose. Gold-tin and Nano-Foil preform will be used as alternative of lead-free package materials.
Mechanical Insertion and Reliability Testing of Thermal Interface Materials for Semiconductor Test and Burn-in Applications
Authors: Saums Dave , Jensen Tim , Gowans Carol , Homer Seth , Hunadi Ron
Published: December 2019

Very challenging requirements exist for thermal interface materials (TIMs) for demanding applications I semiconductor testing. Reliability requirements and multiple contact cycling requirements are substantially different and do not exist in traditional applications for TIMs. Developing new material types to meet these very exacting and unusual requirements has been a long-term goal and requires development of an unusual series of test procedures to demonstrate whether the desired reliability goals have been met. Use of a servo-driven, commercial test stand that has unique features for operation and control is described as the basis for a reliability and performance test program developed for these new materials in three phases, with new data for a fourth test phase added, and comparative values for material performance.
Design and Fabrication of 3D Printed Reconfigurable Metamaterial-inspired Structures
Authors: Karuppuswami Saranraj , Rajendra-Nicolucci Avi , Mondal Saikat , Ghazali Mohd Ifwat Mohd , Chahal Premjeet
Published: December 2019

In this paper, 3D printing is used as an alternative manufacturing technique to fabricate metamaterial-inspired RF structures for liquid profiling. A dual split-ring resonator (SRR) based sensor tag is designed and integrated with a microfluidic channel for detecting different liquid samples. The sensor is 3D printed using a high-temperature resin and metallized using a custom developed metal patterning process. The sensor requires a very small volume of 8.6 μL of sample under test for detection. The resonance frequency of the SRR changes with change in sample loading and the shift is monitored for sample profiling. Different volatile organic compounds are introduced and the shift is monitored demonstrating the sensitivity of the proposed tag. The low-cost, real-time nature of the tag makes it an ideal choice for monitoring liquids along the supply chain.
Computational Engineering
Authors: Allix Olivier , Buffa Annalisa , Carstensen Carsten , Schröder Jörg
Published: December 2019

This Workshop treated a variety of finite element methods and applications in computational engineering and expanded their mathematical foundation in engineering analysis. Among the 53 participants were mathematicians and engineers with focus on mixed and nonstandard finite element schemes and their applications.
Sounding Diversities. Towards an Open Online Archive of Migrants’ Musical Lives
Authors: Caruso Fulvia
Published: December 2019

Since 2014, in an area between Lombardy and Emilia Romagna, participatory action research about music and migration is being conducted. Music is a significant medium not only for shaping a new understanding of a transnational cultural identity, but also for intervening creatively to shape public opinion about cultural, ethnic, and religious diversity in contemporary Italy. Collecting data on musical practices and cultural exchanges, we are also organizing occasions of dissemination and intend to realize a database online.
Qual o argumento para a Atitude Ontológica Natural?
Authors: Silva Bruno Malavolta e
Published: December 2019

Arthur Fine presented the Natural Ontological Attitude (NOA) as a third alternative between scientific realism and anti-realism by identifying a core position contained in both and rejecting any philosophical addition to this core. At first, Fine’s proposal was understood as offering a doxastic middle ground between believing in the truth of a theory and believing in its empirical adequacy. In this reading, NOA was widely disregarded after Alan Musgrave’s criticisms of it, which characterized Fine’s proposal as a form of realism. After that, NOA was reinterpreted as a local variety of realism focused in changing the attitude used to settle the scientific realism debate, by rejecting global philosophies with an approach external to science, and by considering only the scientific evidence with a contextualist mood. Although this reading clarifies how to understand NOA, there is still no consensus about what is Fine’s argument to support it. I organize the four main interpretations of Fine’s defense and point their main flaws. Finally, I develop some clarifications about NOA in order to solve the flaws of the preceding interpretations, defending that NOA is based upon a prevalence of the epistemic values actually used in scientific practice.