bluuebunny/crossref_metadata_2025 huggingface dataset:
Crystal Defect Analysis of Latent Scratch Induced during CMP Process on 4H-SiC Wafer Using Electron Microscopy
Authors: Sato Takahiro , Matsumoto Hiroaki , Suzuki Seiichi , Isshiki Toshiyuki , Kuniyasu Nakamura
Published: June 2018

The dislocation analysis of latent scratch induced chemical mechanical polishing process on 4H-silicon carbide (SiC) using the multi directional scanning transmission electron microscopy (STEM) method and elastic stain measurement were performed. A scanning electron microscope image shows that a latent scratch extended toward the [30] direction and the width is about 50 nm. Cross sectional STEM images shows that the depth of latent scratch due to distortion is about 20 nm. From the result of plan view STEM observation along [000] direction, it was observed that a latent scratch had two defect lines toward the [30] direction, which were a loop type on upper side and a linear type on the lower side. The Burgers vector of each defect have a component in basal plane. Elastic strain mapping was performed using transmission electron microscope equipped with a procession diffraction system. Inside the latent scratch indicates stain-free field, however around latent scratch indicates compressive strain field. About 1.5 % compressive strain field x, y direction and shear strain along latent scratch exists on typical area. As a results of STEM and elastic strain analysis, the atomic arrangement in basal plane seems to be related with the compressive strain around latent scratch.
Stress Relaxation Mechanism after Thinning Process on 4H-SiC Substrate
Authors: Anzalone Ruggero , Piluso Nicolo , Litrico Grazia , Lorenti Simona , Arena Giuseppe , Coffa Salvo , La Via Francesco
Published: June 2018

In this work a comparison between different 6 inches 4H-SiC commercial substrates after post processing has been shown. The main comparison was done between two different suppliers after a thinning process that leaves the sample with a final thickness of 150 microns. After the processing the two substrates show different behavior with different curvature and residual stress. X-Ray diffraction show different crystal quality and curvature values of the substrates. Micro-Raman show different residual stress of the substrates before and after the thinning process. Moreover, molten KOH etching for dislocation detection also show different value of dislocation density for both substrates.
Observation of a Latent Scratch on Chemo-Mechanical Polished 4H-SiC Wafer by Mirror Projection Electron Microscopy
Authors: Isshiki Toshiyuki , Hasegawa Masaki , Sato Takahiro , Kobayashi Kenji , Miyaki Atsushi , Iyoki Masato , Yamaoka Takehiro , Onuki Katsunori
Published: June 2018

A latent scratch which is an extremely shallow scratch induced on a SiC wafer during chemo-mechanical polishing (CMP) has been investigate by mirror projection electron microscopy (MPJ), low-energy scanning electron microscopy (LESEM), atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM). The latent scratch, which is difficult to detect by using optical microscopes, was easily visualized by MPJ as a high contrast dark line. The morphology of detected latent scratch is less than 1nm in depth and about 30nm in full width at half depth by AFM evaluation. The STEM observation revealed the latent scratch was accompanied two dislocation arrays. One contains loop-like dislocations and the other contains spiky dislocations, both lying in the wafer at a few ten nm in depth.
TLS-Dicing for SiC - Latest Assessment Results
Authors: Lewke Dirk , Cerezuela Barreto Mercedes , Dohnke Karl Otto , Zühlke Hans Ulrich , Belgardt Christian , Schellenberger Martin
Published: June 2018

With the gaining demand for SiC semiconductor devices it is more and more challenging to meet the requirements for SiC volume production with the state of the art wafer dicing technology. In order to overcome this challenge the laser based dicing technology Thermal Laser Separation (TLS-DicingTM) was assessed for SiC volume production within the European project SEA4KET. This paper presents the key results of this project. It could be demonstrated that the demand of SiC volume production regarding throughput and cost as well as edge quality and electrical performance of diced chips can be met with TLS-DicingTM.
Influence of Additives on Surface Smoothness and Polytype Stability in Solution Growth of n-Type 4H-SiC
Authors: Komatsu Naoyoshi , Mitani Takeshi , Hayashi Yuichiro , Kato Tomohisa , Okumura Hajime
Published: June 2018

We have investigated the dependence of the macrostep height on various additives in solution growth of n-type 4H-SiC. Surface modification by adding transition elements in periods 4‒6 (Sc, Ti, V, Mn, Fe, Co, Ni, Cu, Y, Nb, Mo, Ce, and W) and group 13‒14 elements (B, Al, Ga, Ge, Sn) was systematically studied to find additives improving smoothness of the growth surface. We found that Sc, Co, Mo, and Ge improved surface smoothness in addition to the already-known additives, such as Al, B, and Sn. Besides, these additives (Sc, Co, Mo, Ge) give no measurable influence on the conductivity of n-type grown crystals. These results demonstrated that Sc, Co, Mo, Ge and Sn are useful additives for solution growth of n-type 4H-SiC.
Reliability of SiC Power Devices against Cosmic Ray Neutron Single-Event Burnout
Authors: Lichtenwalner Daniel J. , Akturk Akin , McGarrity James , Richmond Jim , Barbieri Thomas , Hull Brett , Grider David , Allen Scott , Palmour John W.
Published: June 2018

High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.
Practical Design of 4H-SiC Superjunction Devices in the Presence of Charge Imbalance
Authors: Alam Md Monzurul , Morisette Dallas , Cooper James A.
Published: June 2018

In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance Ron,sp and blocking voltage VBR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.
Conductivity Modulated and Implantation-Free 4H-SiC Ultra-High-Voltage PiN Diodes
Authors: Salemi Arash , Elahipanah Hossein , Zetterling Carl Mikael , Östling Mikael
Published: June 2018

Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.
Fabrication of 2.5kV 4H-SiC PiN Diodes with High Energy Implantation (>12MeV) of Al+ and B+
Authors: Ghandi Reza , Losee Peter , Bolotnikov Alexander , Lilienfeld David
Published: June 2018

In this work, >2kV PiN diodes with >10um deep implant of B+ and 6um deep implant of Al+ have been fabricated to evaluate the quality of resulting pn junction after high-energy implantation. Acceptable low leakage currents at reverse bias and stable avalanche breakdown were observed for high energy implanted diodes (HEI-diodes) when compared to No-HEI-diodes that suggests minimal defect sites present after activation anneal.
Study of Temperature-Dependent Mechanisms and Characteristics of 4H-SiC Junction Barrier Schottky Rectifiers
Authors: Tang Yi Dan , Liu Xin Yu , Bai Yun , Dong Sheng Xu , Xu Shao Dong
Published: June 2018

Temperature-dependent mechanisms and characteristics of 4H-SiC JBS rectifiers were described by theoretical and experimental results. The forward on-resistance of 4H-SiC JBS rectifier consists of several components, the drift region resistance is most sensitive to temperature than others. Comparing theoretical results with experimental data indicates that the leakage current is mainly affected by the thermionic emission, the image force barrier height lowering and tunneling. At different temperatures and reverse bias, the contribution of barrier lowering and the tunneling to leakage current is not the same. The temperature of critical point decreases with the increasing of the concentration of ND or the reverse bias voltage VR. Samples with the doping concentration of ND=6.5E15cm-3 and ND=1E16cm-3 were manufactured in the same process. The forward I–V-T and reverse I–V-T characteristics of the JBS samples were measured at different temperatures (300K to 523K), and temperature-dependent ideality factor, barrier height and resistance were also analyzed, which are in good agreement with simulation results.
Surge Driven Evolution of Schottky Barrier Height on 4H-SiC JBS Diodes
Authors: Asllani Besar , Fonder Jean Baptiste , Bevilacqua Pascal , Planson Dominique , Phung Luong Viet , Brosselard Pierre
Published: June 2018

In this paper we will present the results of repetitive surge stress carried out on six 3.3 kV-5A Ti/Ni 4H-SiC JBS diodes. Repetitive current peaks between 10 A and 24 A have been applied and some diodes were able to endure 100,000 cycles while others failed before. The causes of failure have not been determined but a correlation between peak surge current and physical parameters evolution rate has been proven. Simulations show that contact temperature during surge can reach 300 °C, which is very close to Schottky contact annealing temperatures.
Performance Evaluation of SiC JBS Diodes Rated for 6.5kV Applications
Authors: Mihaila Andrei , Knoll Lars , Kranz Lukas , Bianda Enea , Alfieri Giovanni , Bellini Marco , Papadopoulos Charalampos , Rahimo Munaf
Published: June 2018

This paper presents an investigation into the performance of SiC JBS diodes rated for 6.5kV applications. For the active area layout, two hexagonal cell designs with different ASchottky/ATotal ratios have been considered. For completeness, the JBS performance is compared to that of SiC PiN diodes, fabricated on the same wafer. A benchmark against state of the art PiN diodes in Si technology is also provided.
Suppression of Polytype Transformation with Extremely Low-Dislocation-Density 4H-SiC Crystal in Two-Step Solution Method
Authors: Murayama Kenta , Harada Shunta , Fujie Fumihiro , Liu Xin Bo , Murai Ryota , Zhu Can , Hanada Kenji , Tagawa Miho , Ujihara Toru
Published: June 2018

We achieved the growth of extremely-high quality SiC crystal with two-step solution method with specially-designed seed crystals. The two-step growth consists of 1st step growth on Si-face for the reduction of threading dislocations and 2nd step growth on C-face for the reduction of basal plane dislocations and thickening. In this method, we can make the dislocation density extremely low, while the polytype easily changes during growth due to the absence of spiral hillocks originating from threading screw dislocation (TSD). In this study, we prepared specially designed seed crystals for both 1st and 2nd growth steps to provide steps continuously. In the seeds, a few TSDs exist at the upper-side of the step structure. Consequently, we demonstrated the suppression of the polytype transformation during the C-face growth with extremely low-dislocation-density crystal. Accordingly, we successfully obtained extremely low-dislocation density 4H-SiC with TSD, TED and BPD density of 11, 385 and 28 cm-2.
Multi-Level Trap Assisted Tunneling Model for the Field and Temperature Dependence of SiC-JBS Reverse Leakage Current
Authors: Dolny Gary , Sheng Yang , Fu Yue , Li Zhangmi , Radhakrishnan Rahul , Woodin Richard L.
Published: June 2018

The reverse-bias current-voltage characteristics of commercial 1200 V 4H-silicon-carbide junction barrier Schottky (SiC-JBS) rectifiers are studied both experimentally and through numerical simulation. The reverse leakage current measured from physical devices is observed to display both a strong temperature and field dependence. A model is presented to explain the observed behavior based on a combination of trap-assisted tunneling and a thermionic-emission mechanism through a potential barrier located at the metal-SiC interface. The study shows that a two-level trapping model can be necessary to properly explain the measured data. Excellent agreement between the models and the measurements is obtained over a wide range of bias and temperature.
SiC MPS Devices: One Step Closer to the Ideal Diode
Authors: Elpelt Rudolf , Draghici Mihai , Gerlach Rolf , Rupp Roland , Schörner Reinhold
Published: June 2018

We report on the development of a new generation of SiC Schottky rectifier devices employing a Molybdenum based barrier metal system and a new stripe cell design for field shielding and optimized area utilization. The Schottky barrier height is reduced and thus the conduction losses are decreased significantly. The balance between forward conduction and reverse leakage losses as well as the homogeneity and stability of the new barrier system are investigated carefully.
Design and Manufacturing of 1200V SiC JBS Diodes with Low On-State Voltage Drop and Reverse Blocking Leakage Current
Authors: Sung Woong Je , Han Ki Jeong , Baliga B. Jayant
Published: June 2018

This paper presents the design and fabrication of 1200V-rated SiC JBS diodes in a manufacturing environment. Various designs of p+-grids and edge termination structures were proposed and fabricated on 6-inch SiC substrates. Experimental results show that deeper p+ n junctions are necessary to reduce the leakage current in blocking mode of operation. It was also demonstrated that the hybrid-JTE edge termination structure is very efficient to provide a near-ideal breakdown voltage. Ti and Ni Schottky metals were compared with respect to forward voltage drops and reverse blocking behaviors at high temperatures up to 200 °C.
Breakdown Field Model for 3C-SiC Power Device Simulations
Authors: Fardi Hamid , Van Zeghbroeck Bart J.
Published: June 2018

Modeling and simulation of 3C-SiC power devices such as MOSFETs and diodes requires a model for the breakdown field that is consistent with the Monte-Carlo-simulated ionization rates of electron and holes and supported by experimental results. The challenge one faces is the limited number of publications reporting such calculations and the limited availability of high-quality ionization breakdown data for 3C-SiC diodes. We therefore performed a series of 2D simulations of both n-type and p-type Schottky diodes and p+-n diodes that confirms the general breakdown field trend with doping density obtained from experiments. We uncovered a difference between n-type and p-type diode breakdown behavior, identified the discrepancy between the calculations and the experimental data, and extracted a simple breakdown field model, useful for further 3C-SiC device design and simulation.
Analysis of Forward Surge Performance of SiC Schottky Diodes
Authors: Radhakrishnan Rahul , Cueva Nathanael , Witt Tony , Woodin Richard L.
Published: June 2018

Silicon Carbide JBS diodes are capable, in forward bias, of carrying surge current of magnitude significantly higher than their rated current, for short periods. In this work, we examine the mechanisms of device failure due to excess surge current by analyzing variation of failure current with device current and voltage ratings, as well as duration of current surge. Physical failure analysis is carried out to correlate to electrical failure signature. We also quantify the impact, on surge current capability, of the resistance of the anode ohmic contact to the p-shielding region.
Blocking Performance Improvements for 4H-SiC P-GTO Thyristors with Carrier Lifetime Enhancement Processes
Authors: Ryu Sei Hyung , Lichtenwalner Daniel J. , O'Loughlin Michael , van Brunt Edward , Capell Craig , Jonas Charlotte , Lemma Yemane , Zhang Qing Chun , Richmond Jim , Burk Albert , Hull Brett , McCain Matthew , Sabri Shadi , O'Brien Heather , Ogunniyi Aderinto , Lelis Aivars J. , Casady Jeff , Grider David , Allen Scott , Palmour John W.
Published: June 2018

An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2 between amorphous SiO2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VF over the 1300°C oxidized devices, without any impact on blocking characteristics.
High Workfunction, Compound Gate Metal Engineering for Low DIBL, High Gain, High Density Advanced RF Power Static Induction Transistor (SIT) and HV Schottky Diode in 4H Silicon Carbide
Authors: Pan James , Afroz Shamima , Suko Scott , Oliver James D. , Knight Thomas
Published: June 2018

Wide bandgap semiconductors, such as 4H SiC, are suitable for power regulating devices, due to compatibility with conventional process integration, high breakdown voltage and thermal conductivity [1]. For RF applications, in order to achieve better switching speed, high cut off frequency, and low series resistance (Rdson), it is essential to choose the right gate metals [2]. Engineering of the gate metals not only improves the critical device parameters by adjustment of the metal workfunction, but also affects how the high aspect ratio trenches are filled for a next generation SIT device configuration [3] - [5].
Investigation of 4H-SiC Extraction-Enhanced Vertical Insulated-Gate Bipolar Transistor with Lightly Doped Extractor in Collector Region
Authors: Tang Guannan , Tang Xiao Yan , Song Qing Wen , Zhang Yi Meng , Zhang Yi Men , Zhang Yu Ming
Published: June 2018

This paper proposes a new N-type 4H-SiC extraction-enhanced vertical insulated-gate bipolar transistor (E2VIGBT), which uses a partial Schottky contact to the collector region bottom surface as a carrier extractor to enhance the carrier extraction, so that the switching performance will be improved. TCAD simulation shows that, at an operation frequency of 250 kHz, the E2VIGBT offers a turn-off loss decrease of 69.2% and a total energy loss in a single period reduction of 34.4% when compared with conventional field-stop 4H-SiC IGBTs. With further specific optimization, the proposed structure consumes less energy in a much wider frequency range. The simulation results indicate that this new type of IGBT performs better in high frequency applications.
A Continuous Semi-Empirical VJFET Capacitance Model from Sub to above Threshold Regime
Authors: Makris Nikolaos , Kayambaki Maria , Stavrinidis Antonis , Konstantinidis George , Zekentes Konstantinos
Published: June 2018

This paper presents and discusses the depletion mechanisms that dominate in a TSI-VJFET under different bias conditions as expressed by the gate-source (CGS) and gate-drain (CGD) capacitances. It is shown that at pinch off the dominant capacitance is the drift capacitance and that in conduction the drain source voltage plays a significant role in channel’s formation. Furthermore a semi empirical capacitance model is introduced. CGS and CGD are modeled below and above threshold voltage by considering parallel plate capacitors with different plate configuration in te two cases. Then, the derived expressions are unified using a transition function that preserves the continuity of the model. The model was adjusted and fitted adequately to measured CV data from fabricated TSI-VJFET.
Cross-Section Doping Topography of 4H-SiC VJFETs by Various Techniques
Authors: Tsagaraki Katerina , Nafouti Maher , Peyre Herve , Vamvoukakis Konstantinos , Makris Nikolaos , Kayambaki Maria , Stavrinidis Antonis , Konstantinidis George , Panagopoulou Marianthi , Alquier Daniel , Zekentes Konstantinos
Published: June 2018

Different methods for cross-section characterization of SiC Trenched-singly-implanted vertical junction field effect transistors (TSI-VJFETs) are presented with the purpose to determine the epitaxial structure in terms of doping topography.
On the Optimum Determination and Use of SiC VJFET Threshold Voltage
Authors: Kayambaki Maria , Makris Nikolaos , Stavrinidis Antonis , Konstantinidis George , Zekentes Konstantinos
Published: June 2018

The threshold voltage of SiC JFETs has been determined from transfer characteristics by employing methods commonly used in the case of MOSFETs. The extracted values have been compared with the value determined from the fitting of experimental transfer characteristics with the Schockley model equation. Moreover, the variation of the extracted threshold voltage values with respect to channel width has been employed to determine the channel concentration without taking into account the Vbi value.
Hole Trapping in the NBTI Characteristic of SiC MOSFETs
Authors: He Yan Jing , Lv Hong Liang , Tang Xiao Yan , Song Qing Wen , Zhang Yi Meng , Zhang Yu Ming
Published: June 2018

P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.
Status and Trends in Epitaxy and Defects
Authors: Osawa Hiroshi , Mabuchi Y. , Nishihara Yoshitaka , Guo L. , Ishibashi N. , Fukada K. , Kamei Koji , Momose Kenji
Published: June 2018

SiC-powered devices which reduce the power loss, size, and weight of power converters are gradually appearing in the power electronics market. From now on, cost reduction and quality improvement of SiC epitaxial wafers is required to further increase their popularity. This paper describes the state of development of mass production of the epi-wafer at Showa Denko K. K.
Comprehensive Evaluation of Bias Temperature Instabilities on 4H-SiC MOSFETs Using Device Preconditioning
Authors: Rescher Gerald , Pobegen Gregor , Aichinger Thomas , Grasser Tibor
Published: June 2018

In comparison to silicon based devices, MOSFETs based on silicon carbide show more complex threshold voltage variations caused by positive and negative gate bias stress. We show that the majority of the voltage shift in standard JEDEC-like bias temperature instability measurements originates from stress independent measurement parameters like timing and switching conditions. A more sophisticated bias temperature instability measurement technique using device preconditioning is presented allowing for more accurate and nearly delay time independent extraction of the permanent voltage shift component within typical industrial timescales.
Switching Reliability of SiC-MOSFETs Containing Expanded Stacking Faults
Authors: Fujita Ryusei , Tani Kazuki , Konishi Kumiko , Shima Akio
Published: June 2018

To investigate effect of stacking faults (SFs) on switching reliability, we carried out switching tests using SiC-MOSFETs containing expanded SFs. Before the switching test, current stress was applied to the internal body-diode devices under test (DUTs) to expand SFs. The circuit configuration of the switching test we used was a half-bridge type and a double-pulse gate signal was applied to the lower arm DUT. The switching-voltage was 1.8kV and switching-current increased in about 8A steps to breakdown. Reverse recovery safety operation area (RRSOA) breakdown switching-current decreased dependently on the degree of SiC-MOSFET degradation. Reverse bias SOA (RBSOA) did not decrease even if degraded SiC-MOSFETs were used.
Vertical Tri-Gate Power MOSFETs in 4H-SiC
Authors: Cooper James A. , Islam Naeem , Ramamurthy Rahul P. , Sampath Madankumar , Morisette Dallas
Published: June 2018

A new class of power MOSFET, the vertical tri-gate MOSFET, is described and analyzed. The structure can reduce the 4H-SiC MOS channel resistance by up to an order-of-magnitude, producing the same benefit as if the mobility were increased by the same factor. In this paper we outline the fabrication procedure and describe the unit processes unique to this structure.
1.2 kV 4H-SiC Split-Gate Power MOSFET: Analysis and Experimental Results
Authors: Han Ki Jeong , Baliga B. Jayant , Sung Woong Je
Published: June 2018

This paper presents a 1.2kV-rated 4H-SiC Split-Gate power MOSFET (SG-MOSFET) with superior high frequency figures-of-merit (HF-FOM). Electrical characteristics including reverse transfer capacitance and gate-to-drain charge are measured from fabricated devices on a 6-inch SiC wafer, demonstrating excellent performance. Compared to the conventional MOSFETs, the SG-MOSFET provides about 7x smaller HF-FOM [RonxCgd] and 2x smaller HF-FOM [RonxQgd] with improved reverse transfer capacitance and gate-to-drain charge.
Reliability and Ruggedness of 1200V SiC Planar Gate MOSFETs Fabricated in a High Volume CMOS Foundry
Authors: Chowdhury Sauvik , Gant Levi , Powell Blake , Rangaswamy Kasturirangan , Matocha Kevin
Published: June 2018

This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm2 at room temperature, increasing to 7.5 mΩ.cm2 at 175 °C. Total switching losses were less than 300μJ (VDD = 800V, ID = 20A). The devices showed excellent gate oxide reliability with VTH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (VGS = 25V) and 2500 hours (VGS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.
Suppression of PBTI of SiC-MOSFETs under 100 kHz Gate-Switching Operation by Using a Gate Off-Voltage of -5 V
Authors: Murakami Eiichi , Furuichi Takahiro , Takeshita Tatsuya , Oda Kazuhiro
Published: June 2018

Positive bias temperature instability (PBTI) is one of the crucial issues in SiC-MOSFETs’ introduction to automotive applications. We have investigated PBTI of commercially available SiC-MOSFETs under gate-switching operation to consider real power circuits operation. The use of negative gate off-voltage (Vgs(OFF)~-5 V) is shown to suppress Vth shift (ΔVth) under 100 kHz gate-switching operation. This gate voltage corresponds to the flat band condition, under which the electrons trapped by the near-interfacial traps are effectively detrapped through the interface states around the conduction band edge.
Electrical Performances and Physics Based Analysis of 10kV SiC Power MOSFETs at High Temperatures
Authors: Liu Si Yang , Baliga B. Jayant , Jiang Yi Fan , Sun Wei Feng , Bhattacharya Subhashish , Huang Alex Q.
Published: June 2018

Silicon Carbide (SiC) power MOSFETs become more important in 10kV industrial application level, beginning to replace the silicon devices. Due to the harsh environments, high temperature performances of 10kV SiC MOSFETs must be concerned and understood. In this paper, comprehensive static and dynamic parameters of 10kV SiC MOSFETs have been measured up to 225°C. The device physics behind high temperature behaviors has been analyzed by using the basic analytical models.
Impact of a Kelvin Source Connection on Discrete High Power SiC-MOSFETs
Authors: Bödeker Christian , Ayerbe Edgar , Kaminski Nando
Published: June 2018

Standard packages like the TO-247-3L impose a strong restriction on the performance of SiC-transistors. The limitation arises predominantly from the common source inductance LS that is shared between the gate loop and the load circuit. To avoid this parasitic influence, advanced packages like the TO-247-4L or TO-263-7L offering a Kelvin source connection have been introduced. In this work, the influence of a Kelvin source connection on the switching behavior of a high power SiC-MOSFET is investigated.
Suppression of Short-Circuit Current with Embedded Source Resistance in SiC-MOSFET
Authors: Hatta Hideyuki , Tominaga Takaaki , Hino Shiro , Miura Naruhisa , Tomohisa Shingo , Yamakawa Satoshi
Published: June 2018

This work reports an SiC-MOSFET which replaces a part of the channel resistance with an additional embedded resistance, called a source resistance (Rs). MOSFETs with Rs have higher resistance during short circuit compared with MOSFETs without Rs and suppress short-circuit currents. An improvement of the trade-off relationship between short-circuit capability and on-resistance was obtained with MOSFETs including embedded Rs.
Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs
Authors: Nida Selamnesh , Ziemann Thomas , Kakarla Bhagyalakshmi , Grossner Ulrike
Published: June 2018

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mÎ© planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.
Static and Dynamic Characterization of a 3.3 Kv, 45 A 4H-Sic MOSFET
Authors: Anurag Anup , Gohil Ghanshyamsinh , Acharya Sayan , Han Ki Jeong , Vechalapu Kasunaidu , Baliga B. Jayant , Bhattacharya Subhashish , van Brunt Edward , Sabri Shadi , Hull Brett , Grider David
Published: June 2018

Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test. Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances.
Influences of Bias Interruption and Reapplication on High-Temperature Threshold-Voltage Shifts of SiC DMOSFETs
Authors: Habersat Daniel B. , Lelis Aivars J. , Green Ronald
Published: June 2018

For the paper, we studied how bias stress interruption and reapplication influences threshold voltage (VT) drift results in SiC DMOSFETs during 175°C bias-temperature instability (BTI) tests. Bias interruptions of even short durations were found to result in significant loss of observed VT drift, although reapplying the stress bias for a short time immediately before making the post-stress measurement resulted in a significant recovery of the lost drift. The fractional VT drift (i.e., the ratio of “observed” to “actual” drift) was found to behave similarly to the case of 25°C bias stressing, with an apparent empirical relationship relating to the square of the reapply time, divided by interrupt time. Although questions of bias-stressing at high temperature with room-temperature measurement remain unresolved for now, these results continue to support the feasibility of stress bias reapplication to counteract the loss in VT drift due to delays or interruptions between stressing and measurement (which are a practical limitation imposed by the necessities of batch testing for qualification in a production environment).
Comparison of Single- and Double-Trench UMOSFETs in 4H-SiC
Authors: Sampath Madankumar , Morisette Dallas , Cooper James A.
Published: June 2018

Silicon carbide (SiC) trench MOSFETs, or UMOSFETs, generally exhibit lower specific on-resistance than planar DMOSFETs due to a more compact unit cell, higher electron mobility on the a-face surface, and the absence of a JFET region. In this paper we compare the performance of two types of trench UMOSFETs based on 2-D SentaurusTM Device simulations, and show that the single-trench oxide-protected structure exhibits ~40% lower specific on-resistance and half the peak oxide field of the double-trench design when both are optimized for maximum figure of merit.
Impact of Stripe Trench-Gate Structure for 4H-SiC Trench MOSFET with Bottom Oxide Protection Layer
Authors: Fukui Yutaka , Sugawara Katsutoshi , Adachi Kohei , Hatta Hideyuki , Konishi Kazuya , Sadamatsu Koji , Fujiwara Nobuo , Tomohisa Shingo , Yamakawa Satoshi
Published: June 2018

An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (dBPWs). For the stripe structure, more significant improvements on the specific on-resistance (Ron,sp), gate-source threshold voltage (Vth) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the depletion layer and the channel planes in the device.
Development of a High-Performance 3,300V Silicon Carbide MOSFET
Authors: Fursin Leonid , Li Xue Qing , Huang Xing , Zhu Ke , Simon William , Bhalla Anup
Published: June 2018

To address stringent performance and reliability requirements of industrial and traction power conversion systems we have developed planar 3,300V MOSFETs at a 6-inch SiC-compatible silicon CMOS foundry. By optimizing the unit cell structure and using a deep current-spreading layer we demonstrated a low MOSFET specific on-resistance RDSA=11.2 mΩ·cm2 (ID=5A, VGS=15V) and fast switching for the baseline design. Robust short-circuit handling (7.5μs at Vds=1500V and 5.0μs at Vds=2200V) was demonstrated with an alternative unit cell design with RDSA=14.8 mΩ·cm2 (ID=5A, VGS=15V).
Comparison of 3C-SiC and 4H-SiC Power MOSFETs
Authors: Van Zeghbroeck Bart J. , Fardi Hamid
Published: June 2018

A comprehensive comparison of 3C-SiC and 4H-SiC power MOSFETs was performed, aimed at quantifying and comparing the devices’ on-resistance and switching loss. To this end, the relevant material parameters were collected using experimental data where available, or those obtained by simulation. This includes the bulk mobility as a function of doping density, the breakdown field as a function of doping and the MOSFET channel mobility. A device model was constructed and then used to calculate the on-resistance and breakdown voltage of a properly scaled device as a function of the doping density of the blocking layer. A SPICE model was constructed to explore the switching transients and switching losses. The simulations indicate that, for the chosen material parameters, a 600 V 3C-SiC MOSFET has an on-resistance, which is less than half that of a 4H-SiC MOSFET as are the switching losses in the device.
Investigation of the Robust Edge Termination Applied to 6.5kV SiC MOSFET
Authors: Ebihara Kohei , Kawahara Koutarou , Hino Shiro , Sadamatsu Koji , Nagae Akemi , Nakao Yukiyasu , Watanabe Hiroshi , Yamakawa Satoshi
Published: June 2018

High breakdown voltage and smaller size of edge termination are required in SiC power devices. We simulated reverse bias characteristics of a variety of edge terminations targeting 6.5 kV MOSFET and the FLR showed the best trade-off between the size and the implanted Al dose. Fabricated pn diode TEGs with a FLR demonstrated over 6.5 kV breakdown voltage. We observed the avalanche breakdown visually by light emission and it corresponded to the simulated electric field. These indicate that we can fabricate the desirable FLR for 6.5 kV MOSFET.
Continuous Compact Model of a SiC VDMOSFET Based on Surface Potential Theory
Authors: Jäger Beat , Ju Yan Rui , Stark Roger , Grossner Ulrike
Published: June 2018

Fast and accurate compact models of Silicon Carbide (SiC) power semiconductors are necessary for the development and optimization of SiC power integrated circuits. This paper presents a new physics based compact model for vertical SiC MOSFETs. The proposed model is able to accurately simulate device characteristics by iteratively calculating the surface potential under consideration of important material and geometry effects.
Power Electronic Devices and Systems Based on Bulk GaN Substrates
Authors: Carlson Eric P. , Cunningham Daniel W. , Xu Yan Zhi , Kizilyalli Isik C.
Published: June 2018

Wide-bandgap power semiconductor devices offer enormous energy efficiency gains in a wide range of potential applications. As silicon-based semiconductors are fast approaching their performance limits for high power requirements, wide-bandgap semiconductors such as gallium nitride (GaN) and silicon carbide (SiC) with their superior electrical properties are likely candidates to replace silicon in the near future. Along with higher blocking voltages wide-bandgap semiconductors offer breakthrough relative circuit performance enabling low losses, high switching frequencies, and high temperature operation. ARPA-E’s SWITCHES program, started in 2014, set out to catalyze the development of vertical GaN devices using innovations in materials and device architectures to achieve three key aggressive targets: 1200V breakdown voltage (BV), 100A single-die diode and transistor current, and a packaged device cost of no more than ȼ10/A. The program is drawing to a close by the end of 2017 and while no individual project has yet to achieve all the targets of the program, they have made tremendous advances and technical breakthroughs in vertical device architecture and materials development. GaN crystals have been grown by the ammonothermal technique and 2-inch GaN wafers have been fabricated from them. Near theoretical, high-voltage (1700-4000V) and high current (up to 400A pulsed) vertical GaN diodes have been demonstrated along with innovative vertical GaN transistor structures capable of high voltage (800-1500V) and low RON (0.36-2.6 mΩ-cm2). The challenge of selective area doping, needed in order to move to higher voltage transistor devices has been identified. Furthermore, a roadmap has been developed that will allow high voltage/current vertical GaN devices to reach ȼ5/A to ȼ7/A, realizing functional cost parity with high voltage silicon power transistors.
Glide of Basal Plane Dislocations during 150 mm 4H-SiC Epitaxial Growth by a Hot-Wall Reactor
Authors: Feng Gan , Qian Wei Ning , Sun Yong Qiang , Chen Zhi Xia , Zhao Jian Hui
Published: June 2018

The glide of basal plane dislocations (BPDs) during 150 mm 4H-SiC epitaxial growth by a hot-wall reactor is characterized, and its formation mechanisms are discussed. The reason for the glide of BPDs during 150 mm 4H-SiC epitaxial growth is believed to be due to the strain related to the strain originally in the 150 mm substrate and the strain generated during the epitaxial growth. After the epitaxial growth process is optimized, it is possible to suppress the glide of BPDs, as a result of the effective relaxation of the strain.
Reliability Challenges for SiC Power Devices in Systems and the Impact on Reliability Testing
Authors: Kaminski Nando
Published: June 2018

The reliability of SiC devices remains to be a field of hectic activity because it is one of the obstacles for the ubiquitous application of SiC devices. Without decades of field experience, reliability testing, especially accelerated testing, is the only way to obtain information on reliability during the projected lifespan of the devices. For silicon devices, such tests exist and they are canonized in internationally recognized test standards. For SiC devices, these standards have to be revised and/or supplemented with tests to capture SiC specific degradation mechanisms. On the one hand, this requires a detailed knowledge about the mechanisms but on the other hand, this also requires the mission profile of the devices. In fact, it is not the mission profile of the device that determines its reliability but the mission profile of the chip. This contribution reviews the standard silicon tests useful for SiC devices and looks into additional, SiC specific tests that have been proposed but not yet been recognized as standards.
SiC MOSFET Device Parameter Spread and Ruggedness of Parallel Multichip Structures
Authors: Castellazzi Alberto , Fayyaz Asad , Kraus Rainer
Published: June 2018

This paper presents a preliminary study of the impact of device electro-thermal parameter spread and temperature variation on the robustness of SiC MOSFET parallel multi-chip power switch architectures. Reference is made to 1200 V – 80 mΩ rated commercial devices. Some major parameters are identified and selected, presenting experimental evidence of their impact during transient overload events. An advanced physics-based simulation model is then employed to extend the analysis to a more comprehensive set of parameters and operational conditions.
650 V, 7 mΩ 4H-SiC DMOSFETs for Dual-Side Sintered Power Modules
Authors: Zhang Qing Chun , McCain Matthew , Hull Brett , Casady Jeff , Allen Scott , Palmour John W. , Hayes Monty , Neelakantan Aditya , Fruth John
Published: June 2018

In this paper, we present our latest results on 650 V 4H-SiC DMOSFET developments for dual-side sintered power modules in electric drive vehicles. A low specific on-resistance (Rsp,on) of 1.8 mΩ⋅cm2 has been achieved on 650 V, 7 mΩ 4H-SiC DMOSFETs at 25°C, which increases to 2.4 mΩ⋅cm2 at 150°C. For the first time, the DMOSFET chip is designed specifically for use in dual-side soldering and sintering processes, and a 650 V, 1.7 mΩ SiC DMOSFET multichip half bridge power module has been built using the wirebond-free assembly. Compared to a similarly rated Si IGBT module, the conduction and switching losses were reduced by 80% and ~50%, respectively.
Characterization and Modeling of a SiC MOSFET’s Turn-Off Overvoltage
Authors: Zhang Wen , Zhang Zhe Yu , Wang Fred , Tolbert Leon M. , Costinett Daniel , Blalock Benjamin
Published: June 2018

The overvoltage during hard switching limits the full utilization of devices due to higher blocking voltage requirement. The faster switching speed of SiC MOSFET worsens the trade-off, and the understanding of the overvoltage’s mechanism is crucial for the better utilization. In this paper, experimental characterizations on the influence of circuit parasitic parameters and gate resistances on overvoltage are performed. Furthermore, a SPICE-based device behavioral model is built and found to able to accurately predict the overvoltage. The same method could be applied to device rating selection in converter design.
1MHz Switching Operation of 1200V Full SiC Power Module
Authors: Hayashi Kei , Funaki Tsuyoshi , Michikoshi Hisato , Fukuda Kenji
Published: June 2018

This paper develops 1200V, 50A full SiC half bridge power module, which embeds C snubber and gate resistors. Embedded C snubber suppresses surge voltage in fast switching operation, and gate resistors avoid gate oscillation of parallel connected SiC MOSFET in the module. 1MHz switching operation of developed module with 600V DC-link voltage is experimentally confirmed.
An Auxiliary Power Supply for Gate Drive of Medium Voltage SiC Devices in High Voltage Applications
Authors: Hu Bo Xue , Li He , Wei Zhuo , Wang Ya Feng , Xing Diang , Na Ri Sha , Wang Jin
Published: June 2018

A high-reliability auxiliary power supply (APS) for gate drive circuits is crucial to utilization of emerging medium voltage (MV ≥ 10 kV) Silicon Carbide (SiC) devices in high voltage applications. This paper proposes an active voltage divider based APS with lower arm voltage regulation. The proposed APS circuit is targeting the application of MV SiC devices in modular multilevel converters (MMCs). It can harvest energy from a MV (≥ 7 kV) dc bus to provide an isolated low voltage output to gate drive circuits of MV SiC devices. Compared to existing APS solutions, it can achieve a high input voltage (≥ 7 kV) with simple circuit structure and control scheme. In this paper, the working principle of the proposed APS is presented and a circuit design example is shown. A circuit prototype with 7 kV input and 15 V/10 W output has been built and tested to verify the effectiveness of the proposed solution.
Growth of 4H-SiC Epitaxial Layer through Optimization of Buffer Layer
Authors: Piluso Nicolo , Severino Andrea , Anzalone Ruggero , di Stefano Maria Ausilia , Fontana Enzo , Salanitri Marco , Lorenti Simona , Campione Alberto , Fiorenza Patrick , La Via Francesco
Published: June 2018

In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.
30-kW All-SiC Inverter with 3D-Printed Air-Cooled Heatsinks for Plug-In and Full Electric Vehicle Applications
Authors: Chinthavali Madhu Sudhan , Wang Zhi Qiang
Published: June 2018

This paper presents the design and development of a 30-kW 3D printed based air-cooled silicon carbide (SiC) inverter for electric vehicle application. Specifically, an all-SiC air-cooled power module is designed, aiming at reduced thermal resistance for high temperature and high power density operation. The module assembly incorporates three major parts: an optimized 3D printed heat sink, a SiC MOSFET phase leg module, and a two-channel gate driver. The electrical and thermal performance of the power module is evaluated through double pulse test and continuous operation. Based on the air-cooled power module, a three-phase half-bridge voltage source inverter with 3D-printed air duct is built and tested to further verify the performance of the power module.