Capping Layer Effect on Lifetime of Plasma Etched Copper Lines
Authors: Li Mingqian , Su Jia Quan , Kuo Yue 
Published: February 2020

Cu is the most popular interconnect material in high-density ICs. However, it cannot be etched with the conventional plasma etching process because it does not form volatile products with halogen elements. Kuo’s group reported a room temperature plasma-based Cu etch process, which converted Cu into a chloride or bromide compound in a RIE reactor followed by the HCl dissolution [1,2,3]. This method has been used in ICs and TFT LCDs [4]. An adhesion/barrier layer between the Cu line and the underneath substrate is required to increase its adhesion and to prevent its diffusion to the adjacent film and substrate. A capping layer is often needed for the same purpose as well as to prevent its oxidation or contamination from air exposure. Previously, we have studied the geometry and bending effect on the Cu line lifetime using the electromigration (EM) method [5,6,7]. In this study, the capping layer effect on the lifetime is studied.

Two types of structures, i.e., TiW (10 nm)/Cu (280 nm) and TiW (10 nm)/Cu (280 nm)/TiW (10 nm), were deposited on the Corning glass. All films were sputter deposited. The sample was patterned with a lithography step using a line-and-space mask. Next, the sample was loaded in the PlasmaTherm 700C system. For the TiW/Cu/TiW sample, the TiW capping layer was etched in the RIE mode with CF4 10 sccm at 60 mTorr, 600W for 2 minutes. subsequently, the Cu layer was converted into CuClx by exposed to the plasma of HCl/CF4 20/5 sccm, at 70mTorr, 600 W for 2 minutes. The sample was removed from the RIE chamber and dipped in an 8:1 diluted HCl solution to remove the CuClx. Finally, the TiW barrier layer was etched with the CF4 plasma. For the TiW/Cu sample, the patterned sample was dipped in a 4:1 diluted HCl solution to remove the surface residue. The Cu and TiW layers were etched with the same method as described before. The Cu sample was tested for the EM lifetime under the condition of the constant current density at room temperature.

Figure 1 shows the relationship between the stress current density (J) and the failure time (tfail
). Samples were of 800 µm long. The failure time is shortened with the increase of the current density. This is consistent with the previous report that the lifetime decreased with the current density exponentially [8]. The 30 µm wide line has a shorter lifetime than the 10 µm wide line independent of the existence or absence of the TiW capping layer. This is consistent with the previous report that the wide line was subject to earlier failure than the narrow line was due to the larger number of grain boundary joints for the electromigration failure to occur [7]. Based on the same line width, Cu with the TiW capping layer has a shorter lifetime than that without the capping layer. A non-optimized layer deposition process has critical effect on the void formation sites, which can lead to the reduction of the EM lifetime [9].

Figure 2 shows the resistance (R) change of 10 µm lines with the stress time (tstress
) at the fixed current density of 2.06×106 A/cm2. The resistance of the line changes smoothly with the increase of time until closing to the broken point. The resistance of the sample with the TiW capping layer is slightly larger than that without the capping layer. The strong metallic bonding at the interface can increase the adhesion resistivity and the EM resistivity [10]. For lines without the TiW capping layer, the resistance increases appreciably at about half of the breakdown time. For lines with the TiW capping layer, the increase of resistance with time is not obvious until close to the broken point.

More results on the lifetime of samples with narrower widths and stressed at larger stress current densities will also be reported.

Authors acknowledge the financial support of this work through NSF CMMI project 1633580.

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[9] X. Lu, et al., Proc. IEEE Intl., 33 (2005).

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Figure 1