Investigation of Arsenic Transient Enhanced Diffusion From Emitter Process at 550 °C Si:As RP-CVD Epitaxy Using Disilane Precursor
Authors: Deprat Fabien , Vives Jérémy , Juhel Marc , Valery Alexia , Lespiaux Justine , Baron Alain , Brezza Edoardo , Gauthier Alexis 
Published: November 2022

Reduced Pressure Chemical Vapor Deposition (RP-CVD) Epitaxy bellow 600 °C is studied for 3D sequential integration [1] where cyclic deposition is needed. Another approach can be useful with Si epitaxy at temperature bellow 600 °C : the deposition of amorphous Si on dielectric during non-selective epitaxy combined with solid phase epitaxy regrowth (SPER) to extend the monocrystalline area. Indeed, using temperature above 600 °C during non-selective epitaxy, a polycrystalline Si film is formed on dielectric. This technique has been used in heterojunction bipolar transistor for the non-selective base deposition [2] and can also be used to ensure a fully monocrystalline emitter.

Si:As process has been developed at 550 °C using disilane (Si2H6) as Si precursor and Arsine (AsH3) for As precursor. At this temperature, disilane is mandatory to ensure a sufficient growth rate. The disilane process will be compared to a process of reference, using silane (SiH4) precursor at 620 °C. The As dopant concentration targeted is between 1x20 at.cm-3 and 5x20 at.cm-3. Finally, the dopant diffusion is controlled on non-productive Si(100) wafer (NPW), without pattern, by SIMS for both processes before and after thermal budget (720 °C, 1 h + high temperature Spike anneal) to simulate the thermal budget undergone by the emitter.

Thanks to the ASTAR system [3] from NanoMEGAS, the crystal orientation and phase maps of the emitter are extracted for both processes (Fig 1.a). ASTAR system is based on the Automated Crystal Orientation Mappings technique used on a Transmission Electron Microscope (ACOM-TEM). With silane precursor, a poly-emitter is generated whereas the emitter is fully monocrystalline with disilane. The amorphous deposition coupled with SPER ensure a fully monocrystalline emitter. SIMS analysis have been performed and show abnormal diffusion of As with disilane process. To understand the causes of the diffusion, both Si:As processes have been reproduced on NPW by full sheet epitaxy. The abnormal diffusion is still observed with the disilane process (Fig 1.b). Compared to diffusion length extracted from [4] (19nm) the diffusion of As is enhanced. Moreover, As enhanced diffusion occurs for low temperature thermal budget (Fig. 1.c).

Historically, defects generated from implantation are known to enhance the diffusion length of the dopant. This phenomenon is called Transient Enhanced Diffusion (TED) and it has been studied and observed from dopant implantation [5]. The implantations generate a supersaturation of interstitials defects (such as auto-interstitial) which enhance the dopant diffusion for low temperature thermal budgets. This is a transient effect because the enhanced diffusion occurs in a short time [5]. In our case, several anneal at 720 °C were applied on the disilane Si:As layer from 1 h to 24 h (Fig. 1.d). Most of the diffusion occurs after the annealing at 720 °C, 1 h. These results highlight the transient effect of the As diffusion using disilane process. With the disilane process, TED of As occurs. Indeed, enhanced diffusion of Arsenic appears only for low temperature annealing and the effect is also transient. Compared to implantation which generates defects during the bombardment, low temperature epitaxy generates defects when the growth rate is too high. The molecules from the gas phase are adsorbed on the surface and break down on atoms (called adatom). The adatoms diffuse on the surface to find a suitable site. During low temperature epitaxy, when the growth rate is too high, the adatom don’t have enough time to diffuse on a suitable site and generate defects.

Finally, dopant profile analysis will be completed by atomic force microscopy (AFM) and sheet resistance measurement. The AFM will provide an evolution of the surface topography with the annealing. The sheet resistance, coupling with SIMS, will help to extract the deactivation of dopant. The causes of the TED from disilane process at 550 °C will be discussed and experimental results will be provided.

[1] L. Brunet et al., IEEE International Electron Devices Meeting (IEDM), 2018

[2] Holger Rücker and Bernd Heinemann, Semicond. Sci. Technology, 2018

[3] A. Valery, Doctoral dissertation. Université Grenoble Alpes, 2017

[4] S. W. Jones, "Diffusion in silicon". IC Knowledge LLC, 2008

[5] S. C. Jain, et al., Journal of applied physics, 2002

Figure 1