(Invited) Gate-All-Around Nanosheet Field-Effect Transistors for Advanced Logic and Memory Applications: Integration and Device Features
Authors: Veloso Anabela , Matagne Philippe , Eneman Geert , Mertens Hans , Chasin Adrian , Simoen Eddy , Horiguchi Naoto 
Published: May 2020

As conventional CMOS scaling is reaching its physical limits with ever more constraining design restrictions, new device architectures are being explored as potential fin-field-effect-transistor (finFET) replacements for future technology nodes. Among the various options, vertically stacked lateral nanosheet (NS) FETs with a gate-all-around (GAA) configuration are considered the most promising and mature candidates to use next to help preserve the overall power-performance logic roadmap [1-5]. These devices offer improved electrostatics control and allow additional design flexibility for applications-driven power and performance tuning. Indeed, the possibility to fabricate on the same wafer varying NS widths, enabling devices with a wide range of effective widths (Weff), is one of their key attractive features. Wider GAA NS FETs enable higher drive current (ION) gains. However, as shown in ref. [2], these can be compromised for shrinking gate length (Lgate) due to degraded electrostatics, e.g., worst subthreshold slope (SS) values. As for narrower NS FETs, despite their lower ION, they also correspond to decreased channel, overlap and fringe capacitance values. In addition, as extension and contact resistances can also depend substantially on the NS cross-sectional areas [2], several trade-offs will ultimately determine the NS device configuration that best fulfills the requirements for a given application.

Fabrication-wise, GAA lateral NS FET devices can be regarded as a natural extension of finFETs sharing many of their building blocks. Some of the key process steps are illustrated in Fig. 1, wherein Si/SiGe multi-layers are epitaxially grown prior to fin patterning to form vertically stacked silicon lateral NS. At replacement metal gate (RMG) module, prior to gate stack deposition, NS are released by implementing a selective removal of the SiGe from the Si/SiGe multi-layer fins. This is a key step, critical for preserving the integrity of the Si channels in terms of shape, dimensions and quality of the NS surfaces. Another crucial step occurs earlier on in the flow at STI module, where insertion of a thin nitride liner prior to STI oxide fill and densification anneal can prevent Si/SiGe fin oxidation and Ge diffusion. Such processing helps preserving the fins profile while also protecting them from irreversible strain modifications [4]. Fig. 2 shows an example of a TEM image from a device built with two vertically stacked NS. The well-preserved shape of the NS also enables implementation of a highly uniform and scaled gate stack on all NS surfaces with smooth interfaces [6]. This is of increased importance for scaled GAA NS FETs where reduced vertical distance between the stacked NS is required to minimize device parasitics.

Another type of GAA NS transistors are the vertical NS (VNS) FETs for which Lgate is defined vertically and hence can be relaxed without impacting the device footprint. Representing a more disruptive technological transition, both in terms of device fabrication and circuit layout design, these devices have nevertheless the potential to open up new scaling paths and enable denser, better performing circuits, e.g., for SRAM (as the cell transistors) or MRAM (as the cell selector) memories [7,8].

Fig. 3 illustrates some of the key steps followed to implement an RMG module in GAA vertical nanowire (VNW) or VNS FETs. A layout dependence for some of the processes used in this block can be seen to impact DC characteristics such as VT, ION. The VNW/VNS doping vs. wire/sheet dimensions also needs to be accounted for in case of junctionless devices [8, 9]. RMG can also be used to enable a scheme that boosts the mobility in vertical channels via process-induced stress as described in Fig. 4 for NMOS. Here, a SiGe stressor is epitaxially grown around the Si channel after spacers formation. This stressor is removed at RMG module, after dummy gate removal, with stress memorization into its surroundings enabled by the fact that the layer encapsulating the top of the pillars remains connected (at some places) to the bottom isolation layer. Stress and ballistic current simulations indicate that up to ~19% higher ION can hence be obtained [8].

References

[1] H. Mertens et al., VLSI Tech. Dig., 158 (2016).

[2] D. Jang et al., IEEE Trans. Elec. Dev., 64(6), 2707 (2017).

[3] N. Loubet et al., VLSI Tech. Dig., 230 (2017).

[4] H. Mertens et al., IEDM Tech. Dig., 828 (2017).

[5] P. Weckx et al., IEDM Tech. Dig., 505 (2017).

[6] A. Veloso et al., SSDM Tech. Dig., 559 (2019).

[7] T. Huynh-Bao et al., SPIE Proc., 978102 (2016).

[8] A. Veloso et al., IEDM 2019 (in press).

[9] A. Veloso et al., SSDM Tech. Dig., 221 (2017).

Figure 1