bluuebunny/crossref_metadata_2025 huggingface dataset:
New GaN Power-Electronics Packaging Solutions: A Thermal Analysis using Raman Thermography
Authors: Faqir M. , Manoi A. , Mrotzek T. , Knippscheer S. , Massiot M. , Buchta M. , Blanck H. , Rochette S. , Vendier O. , Kuball M.
Published: October 2015

Raman thermography measurements were performed on AlGaN/GaN multi-finger high electron mobility transistors (HEMTs) to determine their channel temperature at various power levels. The devices were mounted on both silver diamond composite and CuW base plates, in order to benchmark the thermal performance of novel diamond composite base plates compared to traditional materials. We illustrate that AlGaN/GaN HEMT devices mounted on silver diamond composite base plates show peak temperatures which are 50% lower than the peak temperatures exhibited by devices mounted on traditional CuW base plates. This is a dramatic improvement in terms of heat extraction, as basis to enabling longer device life-times and better performances. In addition, time-resolved Raman thermography measurements were carrier out to obtain thermal dynamics of devices on the silver-diamond base plate and on heat diffusion during pulsed device operation. This time-dependent information is of great importance for reliability and failure analyses, as pulsed operation of a HEMT is a typically device operation condition. Finite-element thermal simulations were performed for comparison with the experimental results, and good agreement with the experimental data was obtained.
Study on Thermal Proof of SnO2 Protection Thin Film for Ultra High Reflective Film Ag System
Authors: Miyagawa H. , Satoh R. , Iwata Y. , Morinaga E. , Kamo S.
Published: October 2015

Because it has longer life and uses much less power than filament lighting, LED is expected to be the next-generation lighting device. Moreover, taking advantage of its special properties, LED's are not limited to general lighting. There have been advances in the application of LED's to LCD's and car headlamps. To raise the luminosity efficiency of LED's, the metallic reflective film with the highest reflectivity is used. As a reflective film material, Ag has the highest reflectivity in the visual light range (400–800nm) and is used in many cases. However, Ag is a thermally active material and we have concerns about the decrease in reflectivity by aggregation and heat treatment sulfuration. In this study we investigate an ultra high heat proof protective film for a thin Ag reflective film. Conventionally, SiO2 thin film is used as a protective film for Ag reflective film, but it is difficult to obtain heat proofing > 473K. In this research we consider a SnO2 protective film which combines high heat proofing and high crystallinity. We formed a SnO2 protective film on an Ag thin film under various conditions, and investigated its heat proofing characteristics. We succeeded in obtaining ultra-high heat proofing exceeding 773K using several 10 nm protective film. Furthermore, in trying to understand the mechanism of this outstanding high heat proofing reflective film system, it became clear that the crystallinity in high temperature diffusion plays a major role. In addition, we have found the possible beginnings of a general theory for high temperature stability for nanotechnology.
A Systematic Approach for Creating a System-In-Package (SIP)
Authors: Sadri Sam , Le Tri , Althouse Stephanie A.
Published: October 2015

Over the past several decades the quest to design electronics that boast ever increasing capabilities while continuously decreasing their size and weight has led to the development of a series of new packaging solutions. As the need for more functionality in less real estate increased, Multiple Chip Modules (MCM) were no longer satisfactory in many applications. Today, these applications call for a highly integrated packaging approach which often incorporates multiple functionalities into one package. In situations where time to the market for SOC (System on a Chip) is too slow or too costly the approach of System-in-a-package (SIP) can be the ideal solution.

One element in modern packaging is the use of new 3D structures and high-k dielectric materials. The second element is advanced packaging methods. New technologies such as chip-on-chip assemblies have been developed. The third element has been the progression in design tools that allow engineers to seamlessly design an overall, highly integrated system. The forth element, testing, is often an expensive part of product development. With SIP technology that cost can be significantly lowered, making new product development economically more feasible.

In this paper we present a systematic approach to designing highly integrated and miniaturized SIP packages. This approach enables rapid design, prototyping and time to production while achieving a new level of integration, miniaturization and reliability.

Finally, a case study is presented to demonstrate a typical maturity cycle of a SIP, in this case for a wireless application.
Laser Patterning and Via Drilling of Sapphire Wafers and Die
Authors: Vignes Justin , Haring Fred , Ahmad Syed Sajid , Gerstner Kaycie , Reinholz Aaron
Published: October 2015

As proliferation of handheld devices drives 3D packaging to achieve densification, embedding increased functionality into a chip is a natural complementary advancement in miniaturization. Ever increasing complexity of microelectronic design and functionality leads to the use of multiple surfaces for circuit development on wafers or individual die. Through-silicon vias, stacked die and stacked wafers, along with circuitry deposited on multiple surfaces and irregular shaped structures are some examples of 3D packaging. Laser patterning and via drilling on sapphire wafers and die with a 532 nm green laser has shown significant capabilities to make micro-features on and in the sapphire. Current structures include vias for die and wafer level interconnects, and patterned grooves for circuitry and antenna patterns. Other possibilities include pocket or trench patterning for adding passive components to the back of die or wafers. Backside patterning may be used for nano-imprinting of inks and other liquids. These grooves may also be used as micro-mixing or dispensing channels for use with nano-materials or liquids. All of these techniques may be applied to 3D die or wafer assembly and packaging.
Hardware Design for Novel Packaging of Multi-Cellular Meta-Processing Unit
Authors: Nguyen Son , Delalic Joan , Gruenwald Bjorn
Published: October 2015

Multi-cellular meta-processing unit is an assembly of a large number of small processors organized in self-similarity configurations, together capable of executing trillions of instructions per second. Multiple cells (small processors) are self-organizing processes that are inherently self-similar. Each cell has multiple independent, high speed serial I/O channels. Each cell has its own internal clock, so each cell runs at a slightly different speed as there is no synchronization between any of the cells. Each cell in an n-order system is connected to n−1 peers (neighbors at its own level) and one to the next higher level. This paper presents a package of 9 computing cells (PC/104-Plus LX800 SBC) grouped in three. So each cell is connected to 2 peers and 1 next higher level, and each loaded with its own operating system (Hilbert Engine). The 9 cells can work independently without a centralized control unit. The advantage of this new approach lies in extremely high execution capability in processing a given program. Additionally, the system is self-organizing, which means that the multitude of computing cells is transparent to the user. The system can be treated as a single or few input entities. The advantages of this system include scalability, ultra-high throughput, and fabrication of a large number of small computing cells on single or multiple Si wafers, and multiple wafers will be stacked together to enlarge the capability of the computing system.
The performance over the frequency range 140GHz–220GHz of thick-film CPW lines fabricated from nano-particle silver
Authors: Alshehri A. , Horaczek M. , Rudka D. , Leigh R.J. , Jakubowska M. , Sloma M. , Free C.E.
Published: October 2015

Coplanar waveguide lines fabricated using thick-films of pure silver paste (Ag) and also pastes containing silver nano-particles (nAg) were measured in the high frequency range 110GHz–220GHz. Suitable feed lines and pads were designed and fabricated using photoimageable silver ink, to allow measurements to be performed using a wafer-probing station with 75μm pitch CPW probes. Silver nano-particle materials have a particular benefit in the higher frequency ranges due to the high bulk conductivity, resulting in lower bulk loss. Different lengths of CPW lines were fabricated, to allow subtraction of the mismatches between the feeding pads and the coplanar lines under test. The CPW lines were fabricated on various alumina substrates, with purities of 96%. The pastes were prepared at Warsaw University of Technology (Poland), and tested at the University of Surrey (UK).
Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration
Authors: Li Zhaozhi , Lewis Brian J. , Houston Paul N. , Baldwin Daniel F. , Stout Eugene A. , Tessier Theodore G. , Evans John L.
Published: October 2015

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced.

Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer.

100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.
Fine Pitch 3D Dispensable Electrical Interconnects for System In Package Solutions
Authors: Leal Jeff S. , Pangrle Suzette K. , Whyte Charles , Barrie Keith , Leff Jeff , McGrath Scott , Ayala Gerardo
Published: October 2015

The use of dispensable conductive materials to create fine pitch 3D electrical interconnects has been proven by Vertical Circuits Inc. as a low cost, high reliability alternative to create System in Package (SIP) solutions.

This paper discusses the benefits of dispensing the 3D electrical interconnects instead of using traditional wire bond or high cost TSV processes to create a System in Package. Pad pitches achieved are typically less than 65um. A conformal coating of a dielectric material with the subsequent selective laser ablation of the dielectric over the die pads allows all interconnect lines to be dispensed in a single application adjacent to each other. Compared to traditional wire bond applications, the overall interconnect inductance is lower with comparable capacitive and resistance values enabling higher frequencies to be achieved.

Using this process, complex multi-step stacking and bonding applications that jeopardize known good die (KGD) and increase the XY footprint of the System in Package are eliminated. Furthermore, the entire die stacking process can be executed as a single step before the application of the electrical interconnect material. This method minimizes the overall material handling and repetitive die stack processes that increase the probability of defects leading to expensive yield losses.

Methods for matching the Coefficient of Thermal Expansion (CTE) for the stacked components within a System in Package will be demonstrated as well as surface treatments to enable fine pitch dispense that result in increased product reliability. JEDEC L3 reliability data will be presented to demonstrate SIP robustness using this technology.
Custom Test Fixture Design and Measurement Correlation of Differential Pairs in a Flip-Chip Organic Buildup Package Using Measurement Based De-embedding
Authors: Lambalot Daniel , Gupta Sanjeev
Published: October 2015

The design of a custom test fixture to measure the 4-port S-Parameters of a flip-chip substrate using 4-port network analyzer and fixture de-embedding is presented. Fixture effects for probes and SMA to microstrip launches are removed using measurement based de-embedding through adapter characterization removal. Residual error of de-embedding is presented along with correlation of the model to measurement.
Implementation of a Virtual EMI Lab to Cost-Effectively Tackle Multi-Gigahertz EMI Challenges
Authors: Fahmy Hany , Wang Chen , Pissoort Davy , Badesha Amolak
Published: October 2015

Due to the increasing overall complexity and integration, electronic engineers are faced every day with ever more complicated ElectroMagnetic Interference (EMI) issues. As a result many first prototypes fail to pass all EMI certification tests causing a big loss of time and profit. Up to now, debugging EMI issues has mostly been done in costly EMI chambers. Moreover these tests are done rather late in the design cycle when there is not much flexibility left to implement the optimal and most cost-efficient EMI mitigation methods. Simulations offer a lot a flexibility when estimating the EMI impact of different elements in the electronic system and can really help to find the real sources for possible EMI issues. By having this knowledge very early in the design stage, one can implement cheap, yet effective EMI mitigation methods without resorting to more costly EMI suppressors like shielded connectors, chokes, or specially-designed enclosures. Unfortunately, due to the complexity, most of EMI problems require excessive computer resources both in terms of simulation time as computer memory. However, thanks to recent advances in the adoption of GPU parallel processing technology to modern EM simulation tools, it becomes feasible to accurately solve complex EMI problems within a reasonable amount of time. This paper gives an overview of some efficient methodologies that are currently used by within Nvidia for cost-effective EMI suppression techniques by means of a virtual EMI lab and this both early in the design process or after physically testing a first prototype . The challenges that were successfully tackled include (i) the optimal routing of on a multi-layered Printed Circuit Board (PCB), (ii) the use of on-board shielding, (iii) the influence of grounding to a connector-to-PCB transition, (iv) simultaneous switching output (SSO) noise emission reduction, and (v) estimating the influence of the exact location of an ESD diode.
Pinout Optimization for 10 Gbps+ Serial Link Routing
Authors: Siadat David , Priest Judy
Published: October 2015

Definition and optimization a BGA (ball grid array) package pinout is a complicated process. Multiple factors must be considered, such as chip level floorplan, board placement of the component, the board stackup, escape routability, and signal and power integrity constraints. These tradeoffs and decisions impact package body size and board real estate, therefore overall system cost.

At high frequencies, such as >10 Gbps, the BGA to board via transitions cause visible impedance and noise mismatches and becomes a critical factor in the end to end channel design. Determining BGA pin assignments and their PCB transitions must meet the package crosstalk constraints within the required commodity PCB technology manufacturing rules. This paper describes a methodology of extracting 4 differential signal pairs in the board file from BGA ball to its PCB via transitions through BGA pin field into 3D field solver. The extracted geometry is simulated to determine near-end and far-end crosstalk noise levels between a single victim pair and its associated aggressors. Different pin assignment designs will have different number of aggressors to consider. Different routing layers will also produce different signal via stub lengths (specific resonant frequency) and signal via coupling contributing to far-end crosstalk noise. This may require back drilling of differential signal via stubs to minimize this noise.

The aggregated crosstalk noise level must be equal to or better than what the package can deliver. Once these design rules are determined, they can be leveraged across all channels running at the same frequency.
Accurate and Efficient BER Calculation by Statistical Simulation Based on Physical Transmit Jitter Model
Authors: Rao Fangyi , Gupta Sanjeev
Published: October 2015

Statistical analysis provides an efficient alternative to the traditional Monte Carlo simulation for extremely low BER calculation in high speed serial link designs. Transmitter (TX) jitter posts a huge challenge in statistical simulation due to its pattern- and time-dependent nature and the resulting computational complexity. This paper presents a fast yet rigorous approach to calculate TX jitter in statistical simulation based on physical models of various jitter components. The approach accurately captures effects of uncorrelated random jitters, jitter amplification by channel dispersion, frequency dependency of periodic jitter and data duty-cycle-distortion.
High via density thin metal-core PCB using electro-coated dielectric
Authors: Scholz Bernd , Pekmic Ismir , Ahmad Syed Sajid , Reinholz Aaron
Published: October 2015

Conventional printed circuit boards (PCBs) may be replaced by thinner metalcore boards for some applications, as well as for package substrates. Using thin, metalcore technology may provide advantages for radio frequency (RF) circuits and packages, and increase heat dissipation for high power applications.

The metalcore technology has several layers including the metal core, electrocoated dielectric, sputtered metal layers, and electroplated copper. Especially for RF application and automotive electronics printed circuit boards with a metal core is gaining interest. The advantage of metal core PCB is the low thermal coefficient as well as the possibility to achieve a high density of vias and electronic component assembly.

This paper describes the realization of metal core PCB with a dense array of vias and with a low thermal coefficient. The dielectric layer is applied after vias have been formed providing a high density electronics assembly on a double sided PCB which exhibits the heat dissipation of a metal core with minimal thermal expansion. After photochemically etching an array of vias, the metal core can be optionally plated with copper. The insulating dielectric is applied using a highly reliable electrodeposited coating. Metal core substrate provides the opportunity to form a via to the metal core to provide electrical grounding. The final traces are fabricated on top and bottom and can be interconnected through via openings.
Dynamic Mechanical Analysis of Printed Circuit Board Laminates
Authors: Kuczynski J.
Published: October 2015

Printed circuit boards must meet stringent requirements imposed by elevated temperature processes required for mixed-solder and/or Pb-free assembly. To meet these requirements, laminate manufacturers offer a variety of resin formulations, reactive additives, and glass styles designed to impart specific properties. Both the coefficient of thermal expansion (CTE) and the glass transition temperature (Tg) have received considerable attention with respect to design of high-temperature laminates. CTE mismatch between the copper and the laminate within a PCB results in stress upon the copper that may manifest itself as opens within vias, at the interfaces between internal lands and plated-through hole barrels, as well as open traces. Since the CTE of resin materials below the Tg is typically on the order of 5X lower than the CTE above Tg, a typical laminate design strategy is to produce a resin that exhibits a high Tg without adversely impacting other properties. Numerous factors affect the ultimate Tg of the resin, including the functionality of the monomer(s), crosslink density, the cure profile, and absorbed moisture. Within the electronics industry, Tg is determined via differential scanning calorimetry (DSC) as per IPC-TM-650. However, due to the multilayer construction of current circuit boards coupled with sample size limitations, DSC has been shown to be an inadequate technique for measurement of the glass transition temperature. The endotherm in the DSC is often ill defined, of marginal quality, and may be convoluted with stress relaxation and/or volatile outgassing at elevated temperature. Dynamic mechanical analysis (DMA) has been demonstrated to provide far greater information relative to not only the Tg, but also physical property depression due to moisture plasticization and incomplete resin conversion in various high-Tg laminate systems. Several case studies regarding phenolic-cured epoxy resins, cyanate ester/epoxy blends, and/or polyphenylene oxide/triallylisocyanurate blends will be discussed.
BRAIDED ELECTRICAL CONTACT ELEMENT BASED HIGH PERFORMANCE CONNECTORS
Authors: Salloum Michael , Li Che-Yu
Published: October 2015

Braided Electrical Contact Element or BeCe is high performance mechanically and electrically. It can be used in a variety of connector and interposer applications. This presentation discusses the use of BeCe in board-to-board, flex-to-board, and equivalent connectors. BeCe is typically braided with 6–12 wires and has OD 0.125–0.9 mm and height 1–4 mm. Because of the high elastic compliance, 25–30 % of the uncompressed height, a BeCe height of 2 mm is adequate for a array of 2000 I/O. The contact pitch has a range 0.2–2.0 mm. The average contact force for an array is 5–20 gr. per I/O. The contact resistance of 1 mm BeCe is 5–20 milliohm depending on the wire used. If copper plated stainless steel wire is used the service temperature can be > 250 C. Typical board-to-board connector is constructed by inserting BeCe array in a carrier for adhesive retention. Alternately, the BeCe is cut into two equal heights and each segment is solder attached to the top and bottom side of the FR-4 carrier. Only both ends of BeCe are exposed the remainder part of BeCe is inserted in the spacer above and below the carrier for hard sop to avoid overloading and for buckling prevention. When electrically connecting two parts it can be done with externally applied contact force and with both ends mating in a demuntable way. Alternatively, the mounting can be done in a self-assembled mode, which will be detailed in the presentation. In the presentation the design, construction, and performance of board-to-board connector will be discussed in detail with performance data.
Fine Pitch Cu Wire Bonding – As Good As Gold
Authors: Appelt Bernd K. , Chen William T. , Tseng Andy , Lai Yi-Shao
Published: October 2015

Fine pitch wire bonding has traditionally been the domain of gold wires. The significant increase in gold commodity prices has driven a continuous reduction in wire diameters to minimize the impact of the raw materials cost of the wire. This has reached a point now where copper wires are beginning to displace gold wires despite the technical challenges associated with copper wires. The basic challenges like propensity for oxidation, hardness and propensity for corrosion can be managed with the appropriate investment in tooling and infrastructure. Doubts are persisting about yield and reliability. With a very methodical approach to developing the process controls, it can be demonstrated that yields are as good as those for gold despite the fact that copper bonds are not reworkable. Likewise, the typical JEDEC reliability tests can be full filled. Here, an extensive effort has been placed on extended JEDEC testing to demonstrate that with good process control and proper materials choices, test durations of more than 2x can be passed. This excellent performance demonstrates that copper wire bonding can be as good as or better than gold wire bonding.
Pure Palladium and Palladium Phosphorus Depositions Used in ENEPIG and ENEP Surface Finishes – Comparison of Physical Properties and Their Influence on Soldering and Au Wire Bonding
Authors: Oezkoek Mustafa , Roberts Hugh , McGurran Joe
Published: October 2015

As a surface finish, electroless nickel / electroless palladium / immersion gold (ENEPIG) has received increased attention for both packaging/IC-substrate and PWB applications. With a lower gold thickness compared to conventional electroless nickel / immersion gold (ENIG) the ENEPIG finish offers the potential for higher reliability, better performance and reduced cost.[1,2]

This paper shows the benefits of using a pure palladium layer in ENEPIG and ENEP (Electroless Nickel / Electroless Palladium) surface finishes in terms of physical properties and in terms of gold wire bonding and solder joint integrity.
Sensor Packaging: New Challenges for New Applications
Authors: Beelen-Hendrikx Caroline , Tak Coen
Published: October 2015

Advantages of silicon-based sensors are compatibility with CMOS, improved robustness and reliability, smaller size and reflow compatibility.

Biosensors that use an electrical measurement principle need electrical connections and fluidic access to the die. This only works when the electrical interconnects are kept clean of biofluid and when the package is compatible with the biofluids, receptor chemicals and other sensor elements. In addition, the package needs to be very cheap. A simple plastic overmolded package with a hole in the compound at the sensor location is an effective solution.

RFID sensors also need direct die access for gass and pH sensing. They require the integration of processor, memory, clock, battery and antenna. The package format depends on the application. For checking the quality of perishables during transport or in a store, a disposable flexible tag is needed whereas for smart building sensors, a plastic module is more appropriate. For the sensor tag, a flexible substrate and flip chip bare dies are used. Direct die access is realized by an opening in the flex. Battery and antenna are printed on the flex.

Automotive sensors that are used under the hood need to cope with very high operating temperatures with peak temperatures of up to 200 °C and they need to be delamination free. The critical points in the standard plastic packages used today are the molding compound and the wire-bonds. Standard packages can be used up to 150 °C. For higher temperatures, the molding compound and the wire-bond interconnect are being improved.
The Use of Metallographic and SEM Analysis for Characterization of Sidewall Surfaces in MEMS Devices with DRIE Processing
Authors: Stevens Colin , Dean Robert , Lawrence Samuel , Levine Lee
Published: October 2015

The Bosch Deep Reactive Ion Etch Process is commonly used for the manufacture of MEMS and MOEMS devices that require deep high aspect ratio trenches. In many cases fully released, high aspect ratio features can be generated in one pass. However the process must be understood to avoid generating some of the defect structures that are characteristic of the process. Defects such as scalloping, silicon grass, and undercutting at the interface of a nonconductive layer can be controlled by process parameters and optimization. Measurement and characterization of the defective structures is a key element of controlling them. The use of SEM measurement techniques for characterizing the small features associated with scalloping and silicon grass is essential. No other technique is capable of providing the large depth of focus required to visualize these features. The use of metallographic techniques furthers understanding of the surface conditions on the side walls of these deep trenches.
Wafer Level Package with Y shaped TSV and Vacuum Sealing by Cu-Sn Isothermal Solidification for MEMS Resonator
Authors: Cao Yuhan , Luo Le
Published: October 2015

A novel WL- CSP structure for MEMS device is proposed. Key features are: “Y-shaped” TSV is fabricated to reduce cost; Cu-Sn isothermal solidification is used to achieve lower temperature bonding; I/O interconnection and vacuum sealing are achieved simultaneously simplifying the whole process. Average shear strength of 25.5 MPa and excellent leak rate of around 1.9×10−9atm cc/s have been achieved, which meet the requirements of MIL-STD-883E. Four point probe setup is used to measure the resistance of the “Y shaped”-TSV and the contact resistance of the Cu/Sn IMC bond joint. “Q factor extraction method” is used to monitor the vacuum property of the packaging structure by integrating a MEMS resonator with a resonant frequency of 1.3 KHz. Reliability tests such as long-term and accelerated life testing are also performed both achieving good results.
Hermetic Sealing of Stainless Steel Packages by Seam Seal Welding
Authors: Marinis Thomas , Nercessian Berj
Published: October 2015

Welded stainless steel packages offer a number of advantages relative to those fabricated from kovar or aluminum metals and braze sealed. They are highly resistant to corrosion, especially in aqueous or elevated temperature environments, are mechanically stronger, dramatically so at temperatures above 100°C, exhibit lower outgassing rates, and have better vibration characteristics. Since welded stainless steel packages do not require over plating to facilitate braze sealing, combined material and fabrication costs are lower than kovar or aluminum packages. Also, unlike kovar, stainless steel is nonmagnetic, which is advantageous in many electronic applications.

For sealing stainless steel packages, we elected to use seam sealing rather than laser welding for two reasons. Seam sealing subjects the package contents to lower thermal excursions than laser welding because less material is melted to achieve a weld in seam sealing. Second, seam sealing confines the molten material between the cover and package, where as laser welding produces a surface filet. Consequently, there is more opportunity for molten metal to splatter or react with the atmosphere in laser welding than in seam sealing.

We successfully developed a process to weld a 2 millimeter thick cover onto a box with dimensions of 75 mm long by 50 mm wide by 15 mm deep using a seam sealer. The box walls were 1 mm thick and were penetrated by a dozen glass insulated feedthrus on one side. Both cover and box were fabricated from 316L stainless steel. A combination of analytical and finite element modeling were used in conjunction with a designed experiment to optimize the process variables of roller angle, speed and pressure, weld current, pulse shape, duration and spacing, number of weld passes, and sealing atmosphere. Weld quality and seal integrity were evaluated by leak testing before and after environmental stressing, mechanical testing and metallographic cross sectioning. The effects of component dimensions and tolerances on seal integrity were also investigated. Particular attention was paid to cover flatness, flange thickness, and tightness of fit between the cover and box. The process development was concluded by conducting a qualification experiment that used the optimized process parameters with controlled variation about their nominal values. A 100% yield of sealed boxes was obtained. These test articles were then subjected to various environmental screening tests, which were all passed with no failures.
Modeling of a heterojunction bipolar transistor based AlGaAs / GaAs
Authors: Bedia A. , Ghaffour D. , Guen-Bouazza A. , Bouazza B. , Ghaffour K.
Published: October 2015

The simulation of the physical components semiconductor uses approximations varied depending on the type of devices to study and expected effects. Also, the systems obtained are rarely simple to solve. Numerically, the transportation problems are most difficult to discrete. It should also be noted that the problem is strongly nonlinear, coupling quantities very heterogeneous and are not at all in the same order of size. It should be noted moreover than the exploitation of the physical models can be conceived only if the computing times remain reasonable.

The physical model as simple implemented for HBT transistors is the model of drift diffusion. This model is given in the form of differential equations in partial derivatives, describing the physical behavior of charges and currents in each part of the device.

The objective of our work consists in studying the electronic properties of a heterojunction bipolar transistor based AlxGa1-xAs /GaAs, and the distribution of electric potential, of the field electric thus the concentration of the electrons and the holes.
Inkjet Printing of Thick-Film Resistors
Authors: Wassmer Marcel , Diel Waldemar , Krueger Klaus
Published: October 2015

The integration of passive components directly into circuit board is an efficient alternative to surface mounted devices. Inkjet printing is the emerging technology for the deposition of a variety of particles and therefore for digital fabrication of microelectronic circuits. Resistors are one of the most frequently required passive components in electronic circuits. In LTCC-technology the integration and additionally the embedding of resistors promises new applications. Integrated resistors are usually screen printed. Inkjet printing has several advantages to compete seriously with screen printing as production method. This study investigates the possibilities and reliability of inkjet printing of thick-film resistors.

In a first step, different resistive compositions are characterised towards compatibility with a commercial inkjet print head. The reliability and long term stability in drop formation are fundamental for production process. Further on, the interaction between ink and substrate has to be taken into account to reach the desired morphology. In a second step, the advantages of using inkjet for printing resistors are shown. A measure of ink amount is introduced for exact dosing of the ink. Afterwards, compositions with a wide resistivity range are printed with different print heads. The printed resistors are further passed alternatively through a post-fire or through a co-fire process. The effect of variations in particle composition and ink amount are characterized towards the change in electrical behaviour. Further, the influences of printing conditions on morphology and resistivity are discussed.
A Path Toward Non-Destructive 3D Metrology for Through-Silicon Vias
Authors: Gelb Jeff , Kong LayWai , Hunter Luke , Gu Allen , Fong Tiffany , Diebold Alain C. , Lau S. H. , Yun Wenbing
Published: October 2015

As integrated circuit designs are pushed to tighter dimensions, chip real-estate is becoming of increasing value. Much like the growth of a developing city, a common modern approach is to grow the circuits upwards, building one layer on top of another. In this 3D stacking approach, the common issue lies in how to connect the multiple layers, for which direct connections through the silicon substrates have been found to produce the smallest footprint. These through-silicon vias (TSVs) are currently the subject of heavy research and development (R&D) investigation and their efficiencies are, in part, directly related to the occurrence or absence of voids within the metal structures.

3D x-ray microscopy (XRM) has recently been pushed to unprecedented resolution levels and may fit the inspection needs of the TSV R&D community. Using a unique projection-based micro-CT imaging geometry, entire packages may be inspected with as high as 1 μm resolution. This technique delivers non-destructive metrology of the metal fills as well as the post-etch regions in 3D, without the need for physical cutting or sectioning. By employing x-ray optics, resolution as high as 50 nm is now routinely achievable, allowing the detection of far sub-micron voids within the post-metallization TSV structures. These results may be further analyzed for void sizes and void volume fractions per via. Post-etch samples are also well-visualized using this technique, which allows high-resolution inspection of the side walls as well as measurement of the critical dimensions using the same system as for the post-metallization structures.
Studying the Impact of Return Current Path on the EM Simulation of High-speed Package Designs
Authors: Kostka Darryl , Scogna Antonio Ciccomancini
Published: October 2015

Three-dimensional electromagnetic simulation models are often simplified in order to reduce the simulation time and memory requirements without sacrificing the accuracy of the results. A commonly adopted methodology in the simulation of electronic package designs is to truncate the size of the package model leaving only a few important features surrounding the nets of interest. In this paper we demonstrate that this simplification can have a significant impact of the simulation results if it is not performed carefully and it can introduce spurious/non physical resonances. The interaction between cavities and signals is first studied using a simple coupled differential via test structure. It is demonstrated that the return currents generated by these vias excite cavity resonances in power-ground plane pairs causing them to behave as parallel-plate waveguides. The role of interplane shorting vias in suppressing cavity resonances is then investigated and the impact of boundary conditions on the simulation results of package models is also shown and discussed. Finally, a realistic complex multilayer package model is analyzed and it is demonstrate that through proper truncation of the geometry, accurate results can be obtained.
An Innovative Printed Circuit Board Power Delivery Scheme
Authors: Cheng Zhenggang , Gunadisastra Peter , Agrawal Amit
Published: October 2015

In this paper, an innovative board power delivery scheme with two separate power planes merging at VRM (voltage regulator modular) has been studied. The two separate power planes provide power for two different core power rails with the same value. Compared to traditional board power delivery schemes such as two separate power planes with two VRMs or one shared power plane with one VRM, the new power delivery scheme has been found to be cost effective and have good performance for our application by using system level transient power noise simulation and analysis.
4-PAM System Simulation for 25 Gbps Designs
Authors: Gupta Sanjeev , Lu Dingqing , Kladopoulos Konstantinos
Published: October 2015

This paper proposes to estimate very low PAM system BER using the Improved Importance Sampling (IIs) method The results from both theoretical analysis and simulation show that the IIS estimation is unbiased. Based on calculation of the simulation variance and improvement ratio for IIS estimation, the IIS method is very effective for estimation of very low BER for PAM systems with intersymbol interference (ISI), jitter, crosstalk and additive noise.
Enhancing Reliability of LEDs and other Display Devices
Authors: Kumar Rakesh
Published: October 2015

Organic materials have played significant role in advancing sensor & display technologies for the past couple of years. Reliability and protection of various electronic components that are used in aircraft, artificial satellites and spacecraft for communications, navigation and the display and management of multiple systems are becoming more challenging due to their long-term performance requirements. In the recent years, organic polymers, particularly those deposited through vapor phase polymerization, have found an increasing role in the fabrication of display devices (including LED, OLED and FOLED), sensors, MEMS and optical windows and enhancing their overall reliability. Para-xylylene family of vapor phase polymers, particularly fluorinated Parylene (Parylene HT) offers unique characteristics for sensor, optical windows and display applications that are not available by other polymeric materials. This presentation describes a new development in the area of Parylenes and its role to advance the effectiveness of various types of LEDs, sensors, optical windows and display electronics. In addition, it highlights some characteristics for protection of various LEDs, sensors and their packaging components from solvent, gasoline, corrosive vapors, moisture and other harsh environmental effects including high temperature environments.
Substrate Transfer for GaN based LEDs grown on Silicon
Authors: Pham Nga P. , Rosmeulen Maarten , Demeulemeester Cindy , Motsnyi Vasyl , Tezcan Deniz S. , Osman Haris
Published: October 2015

This paper focuses on the substrate transfer process which is applied after the fabrication of LEDs on 4 inch Si (111) wafers comprising p and n contact formation to the GaN layer. After applying a passivation layer, a bonding metal is deposited. The wafer is then bonded to a Si carrier substrate using metallic bonding. Next, the original Si (111) substrate is completely removed by grinding and wet etching. GaN-LEDs are thus transferred to a new carrier substrate. The last step is etching of the transferred GaN layer from the back to open the contacts. A surface roughening technique on the backside of the transferred GaN layer to improve the light extraction efficiency of GaN-LEDs is also investigated. All the issues of the substrate transfer process steps such as permanent Cu/Sn bonding, thinning by grinding and wet etching will be discussed in detailed. A typical issue occurring during processing of GaN-LEDs on Si substrates is high stress and related large wafer bow originating from the GaN layer and the thick Cu/Sn metal bonding layer. Such a large wafer bow causes problems for some automatic handling tools and processes like lithography. Solutions to manage the stress and wafer bow have been investigated.
Heterogeneous integration – packaging on and in organic substrates
Authors: Becker Karl-F. , Braun T. , Bauer J. , Böttcher L. , Ostmann A. , Pahl B. , Haberland J. , Kallmayer C. , Aschenbrenner R. , Schneider-Ramelow M. , Lang K.-D.
Published: October 2015

Decreasing the bill of materials for an electronic device saves development time, money and space. The integration of more and more functions not only on the chip (SoC; system on chip) but also in the package (SiP; system in package) is therefore a natural and very important step in the devolvement of micro electronics. Realizing the goal of Ambient Intelligence requires low cost system solutions where all necessary components are integrated. The future will be a combination of “System on Chip”- and “System in Package” solution called as “Heterogeneous Integration”.

As far as technical and economical feasible “System on Chip” solutions will be chosen, the adoption to various applications and the integration of highly complex systems containing non-electronic functions will be carried out more cost efficiently, with a high degree of miniaturization and flexibility in “Heterogeneous Integration”. “Heterogeneous Integration” integrates several chips or components in one package (system in package or SiP) and carries out the interface to the application environment.

This paper will summarize a variety of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers – looking also on the requirements of sensor packaging. Not only the technological principles but also specific material demands and necessary processes as 3D routing and also 3D interconnection will be discussed in detail. Application examples and technology demonstrators from will be shown to demonstrate technological potential and challenges of miniaturized heterogeneous integration by embedding from a European perspective.
Design and characterization of a biocompatible packaging concept for implantable electronic devices
Authors: Op de Beeck Maaike , Qian Karen , Fiorini Paolo , Malachowski Karl , Van Hoof Chris
Published: October 2015

A biocompatible packaging process for implantable electronic systems is described, combining biocompatibility and hermeticity with extreme miniaturization. In a first phase of the total packaging sequence, all chips are encapsulated in order to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this hermetic chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, diffusion barrier properties and sensitivity to corrosion.

In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme using eg. gold or platinum. For electrodes being in direct contact with the tissue after implantation, IrOx metallization is proposed.

Device assembly is the final packaging step, during which all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all these components are embedded using a biocompatible elastomer such as PDMS.
LÉTI’S TWO STEP APPROACH IN THE DOMAIN OF 3D INTEGRATION
Authors: Rouzaud André , Sillon Nicolas , Scannell Mark , Henry David , Mourier T.
Published: October 2015

In a first time confined to labs and then R&D centers, 3D integration technologies have now gained maturity and are now penetrating the industrial world. More and more, R&D centers are approached to back the industrial developments with associated constraints of swift product development, prototyping, and short time-to- market. To face this paradigm, Léti has developed a specific two-step approach in the field of 3D integration, including both a very advanced R&D part focused on the most promising technologies and integration flows, and the industrial validation of the most mature process flows already assessed at the laboratory scale or on specific industrial themes. This talk aims to detail the two aspects of this dual approach:-In the first part, we will give an overview of the innovative R&D performed on the still nascent and most promising integration flows, as well as the associated technological means.-in the second part, we will present the prototyping activities that Léti is now offering. Based on a limited number of mature and already validated process steps (bonding and thinning, TSV, bumping, stacking) this generic integration scheme allows industrial customers to assess on their own wafers the benefits of an innovative 3D integration.
Mobile Device Passive Integration from Wafer Process
Authors: Liu Kai , Lee YongTaek , Kim HyunTai , Hlaing MaPhooPwint
Published: October 2015

In this paper, we present some passive components made from silicon substrate technology (Integrated Passive Device process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process are characterized on ESR and ESL performance. Functional blocks (filters, baluns, diplexers, matching, etc) made from the IPD process, have shown good electrical performance with small form-factor features. The thin profiles from the IPDs make them very suitable to be used inside laminate and QFN packages. System-in-Packages or multiple-chip-modules using IPD approaches may have significant size reduction. The low profiles and the small form-factors of the IPDs result in less cross-talk between the IPDs and their nearby components (chips, SMDs, and routing traces, etc), and therefore it is easier to maintain signal integrity for packages.