bluuebunny/crossref_metadata_2025 huggingface dataset:
The Complete Water-Based Ceramic Coating Process for Lithium Secondary Batteries By Plasma Treatment
Authors: Jeon Hyunkyu , Lee Hongkyung , Kim Hee-Tak , Lee Yong Min , Ryou Myung-Hyun
Published: February 2020

Abstract

Numerous numbers of polyolefin-based microporous separators containing thermally stable inorganic/polymer composite layers have been developed to improve safety of lithium-ion batteries [1-3]. Because of hydrophobic surface property of polyolefin-based separators, the use of non-polar organic solvent, which is generally toxic and expensive, is prerequisite to introduce ceramic coating layers containing polymeric binders. Not only to price down the coating process but also to guarantee an environmentally friendly coating process, an aqueous ceramic coating process should be developed.

Herein, we developed the complete water-based ceramic coating process to prepare inorganic/polymer composite coating layers on commercial polyethylene (PE) separators using plasma treatment. The plasma treatment introduced polar functional groups onto the surface of PE separators, thereby changed the surface properties of the PE separators from hydrophobic to hydrophilic. Consequently, the coating solution based on water uniformly covered the plasma treated PE separator surfaces without defects. We investigated the physical properties of ceramic-coated separators (CCSs), including their morphology changes, gurley number, thickness, and ionic conductivity. We also studied the electrochemical properties of cells containing the CCSs. CCS exhibits superior power capability and cycle performance compared to bare PE in unit cells based on lithium metal anodes.

Acknowledges

This research was supported by the Ministry of Trade, Industry & Energy (MOTIE), Korea Institute for Advancement of Technology (KIAT) through the Encouragement Program for The Industries of Economic Cooperation Region (G02A01280032701)

Reference

[1] Y. Lee, H. Lee, T. Lee, M.-H. Ryou, Y.M. Lee, J. Power Sources 294 (2015) 537-544.

[2] D. Yeon, Y. Lee, M.-H. Ryou, Y.M. Lee, Electrochim. Acta 157 (2015) 282-289.

[3] H. Jeon, D. Yeon, T. Lee, J. Park, M.-H. Ryou, Y.M. Lee, J. Power Sources 315 (2016) 161-168.
Localized Electrochemical Analysis of Polyacrylate Binders on Graphite-Silicon Negative Electrodes in Lithium-Ion Batteries
Authors: Kumatani Akichika , Watanabe Tetsuya , Yasufumi Takahashi , Kubota Kei , Ida Hiroki , Shiku Hitoshi , Komaba Shinichi , Matsue Tomokazu
Published: February 2020

Graphite-silicon composite negative electrodes are expected to satisfy one of recent demands for creation of high performance lithium-ion batteries because of their high-capacity (above 1000 mAh/g). A major issue for their practical application is a control of large volume expansion/shrinkage of silicon materials, which is a key to realize their good reversible cyclability. Recently, Komaba et al. reported that polyacrylate binders improve their cyclability because of well-dispersion of graphite/silicon materials by coating them with polyacrylate homogeniously.1,2 Also, polyacrylate can suppress a formation of decomposition of organic electrolyte during lithiation process, which induces poor cyclability. For further investigation of existence of the decomposition, we have applied a scanning electrochemical cell microscopy with single barrel nano-pipette filled with organic electrolyte and a reference electrode, called nanoSECCM in Figure 1 a.3NanoSECCM can measure electrochemical properties (such by cyclic voltammetry, CV) with sub-micrometer scale locally. From localized CV results (scan rate at 100 mV/s) as shown in Figure 1 b, we have observed current response related to the formation of decomposition. This response was not observed by typical bulk CV measurement, suggesting that our technique is sensitive to investigate graphite-silicon composite negative electrodes for realization of high performance electrodes in lithium-ion batteries.

[1] N. Yabuuchi et al., Adv. Energy Mater., 2011, 1, 759.

[2] Z-J. Han et al., Phys. Chem. Chem. Phys., 2015, 17, 3783.

[3] Y. Takahashi et al., Nat. Commun. 2014, 5, 6450.

Figure 1
Melt Synthesis of LiFePO4: Fundamentals, Versatility and Application
Authors: Talebi-Esfandarani Majid , Rousselot Steeve , Jin Liling , Bibienne Thomas , Gauthier Michel , Chartrand Patrice , Sauriol Pierre , Seifitokaldani Ali , Liang Guoxian , Dollé Mickael
Published: February 2020

With its good thermal stability, abundance in nature and benign environmental impact, LiFePO4 (LFP) cathode material is seen as one of the most promising candidate for the next generation of Li-ion batteries. Many synthetic routes have already been used for preparing LFP material, best known being solid state, sol-gel, hydrothermal, co-precipitation and microwave preparations. All of them are performed at moderate temperature and/or in a wide range of pressures. Melt process of LFP, advanced by Gauthier et al. in 2003[1], operates in the liquid phase above 1000⁰C and then benefits from increased reaction kinetics and from the thermodynamic stability of LFP in a mild reducing atmosphere. The melt synthesis allows the use of a wide range of simple raw materials as well as a possible purification strategy during the melt step or upon solidification, potentially enabling for usage of less pure non-expensive raw materials.

In this work, thermodynamic considerations are first addressed for deep understanding of the Li-Fe-P-O systems. A model has recently been developed and is supported by experimental data. On this basis, recent experimental observations and progress on raw material selection (including direct use of iron ore concentrates) and systems will be reported. Eventually, melt-synthesis conditions and the latest results in controlling the purification of LiFePO4 from major phase impurities will also be covered. All these considerations allow the selection of the best conditions to prepare a high purity LiFePO4 by melt-process.

This work is part of an Automotive Partnership of Canada supported program to develop and pilot the molten-synthesis process to make high purity C-LiFePO4with excellent electrochemical properties for using as a cathode material in Li-ion batteries for EVs and PHEVs application.

[1] M. Gauthier, L. Gauthier, D. Lavoie, C. Michot, N. Ravet, US Patent 7,534,408 B2. (2003).
Electrochemical Properties of Nickel Oxide Nanostructures Grown Using a Low Pressure Chemical Vapor Deposition Process As Anode in Lithium Ion Batteries
Authors: Puli Venkata Sreenivas , Adkins Joshua , Arnold Corey L , Meda Lamartine
Published: February 2020

Nanostructure transition metal oxides (MO-type M = Fe, Co, Ni, Cu, . . . ) with rock-salt structure are promising anode materials to be used in lithium ion batteries, when compared to conventional graphite anodes due to their superior Li- ions storage capability. NiO nanostructures were successfully grown onto stainless steel 304 substrates using a low pressure chemical vapor deposition process at 600°C and characterize their morphology-dependent electrochemical behavior at room temperature. Structure and elemental analysis of the NiO nanostructures were confirmed using X-ray diffraction and EDS. Oxidation states and elemental analysis was confirmed with XPS analysis. The electrochemical performances of the NiO electrode were studied using cyclic voltammetry (CV) and galvanostatic charge/discharge (GCD) techniques in LiPF6 with in 1:1:1: EC, DMC, and DC electrolyte in the voltage range of 0.1 - 4.0 V at a constant current of 0.1 mA vs Li/Li+. Solid electrolyte interface (SEI) appeared at the first cycle and disappeared in the subsequent cycles, however two oxidation peaks were observed at 1.63 V and 2.23 V which have been assigned to the depletion of the electrolyte and oxidation of Ni+2, respectively. NiO nanostructures have shown a first-cycle capacity of about 782 mAh/g, which is more than the expected theoretical capacity of 718 mAh/g after the conversion reaction. The origin of the excess capacity is due to the Pseudo-capacitive nature of the materials at low voltages and interfacial charge storage. A loss in capacity in the second discharge is observed which is due to loss of materials. The electrochemical properties of the as synthesized NiO nanostructures were investigated to determine their suitability as anode materials for lithium-ion batteries.
(Invited) Epitaxial Transition Metal Nitrides for III-Nitride Devices: Application for Epitaxial Lift-Off and Transfer
Authors: Downey Brian P. , Meyer David J. , Katzer D. Scott , Nepal Neeraj , Wheeler Virginia D. , Storm David F. , Anderson Travis J , Hardy Matthew T
Published: February 2020

Integration of epitaxial metallic layers within a semiconductor device structure has long been desired for a variety of applications; however, the practical realization of this goal has remained elusive. We have recently demonstrated the epitaxial growth of a transition metal nitride, Nb2N, on 6H-SiC substrates using plasma-assisted molecular beam epitaxy [1]. The films, ranging from 4 to 100 nm in thickness, exhibited single phase, sub-nm rms roughness, and low resistivity. Furthermore, high quality III-nitride layers can be grown on the Nb2N/SiC templates, either in a continuous growth run or after removing and re-loading the Nb2N/SiC template [2], without observable reaction between any of the layers. III-nitride material quality has been verified by growing a high-electron-mobility transistor (HEMT) device structure on a Nb2N/SiC template, achieving a two-dimensional electron gas (2DEG) mobility of 1400 cm2/V-s, a sheet carrier density of 1.2x1013 cm-2, and a maximum drain current in excess of 1 A/mm [3]. One unique application of this HEMT/Nb2N/SiC structure is utilizing the Nb2N layer as a sacrificial release layer for HEMT lift-off and transfer to alternative substrates of interest [4]. We have found that the intact HEMT structure can be released from the substrate without observable degradation of the 2DEG electrical properties by selective etching of the buried Nb2N layer using XeF2 vapor phase etching [3]. This process opens the door for the integration of GaN devices with various other technological platforms (heterogeneous integration) or onto alternative substrates such as plastic or diamond. Additionally, this process could allow for the reuse of SiC substrates after device lift-off. This presentation will focus on the materials development of epitaxial Nb2N layers and their use as a sacrificial release layer for III-nitride device transfer from SiC substrates.

[1] D.S. Katzer et al., Appl. Phys. Express, vol. 8, no. 8, 085501 (2015).

[2] N. Nepal et al., Appl. Phys. Express, vol. 9, no. 2, 021003 (2016).

[3] D.J. Meyer et al., CS MANTECH Conference, May 16 – 19, Miami, USA (2016).

[4] D.J. Meyer and B.P. Downey, “Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates,” US patent application no. 14/331,440. PCT application no. PCT/US14/46609.
(Invited) Displacement Damage and Single Event Effects in AlGaN/GaN HEMTs
Authors: Koehler Andrew D. , Anderson Travis J , Khachatrian Ani , Roche Nicolas J.-H. , Buchner Stephen , Weaver Brad D , Hobart Karl D , Kub Francis J
Published: February 2020

Superior advantages of AlGaN/GaN high electron mobility transistors (HEMTs) from a size, weight, and power perspective make this technology desirable for use in outer space applications. However, the harsh environment in space includes bombardment of various types of radiation, which can degrade the performance and reliability of these devices. Displacement damage refers to atomic displacement within the semiconductor crystal lattice. This is permanent damage that permanently impacts the device characteristics. High-energy (2 meV) protons at various fluences, up to 6 x 1014 H+/cm2 were used to investigate the impact of displacement damage on AlGaN/GaN HEMTs. A reduction in the maximum drain current is observed, which is also attributed to a decrease in the two-dimensional electron gas (2DEG) mobility and sheet carrier density. A roughened interface between the AlGaN and GaN layers from atomic recoiling during irradiation has been identified as the mechanism for this mobility decrease. We have attributed the change in sheet carrier density to radiation-induced recombination centers created within the GaN. This results in a decrease in the Fermi level of the GaN, which also decreases the number of mobile electrons in 2DEG. Single event transients generated from energetic particles passing through the device create electrons and holes, which are collected at the terminals, are a potential reliability issue for the GaN HEMTs. A nondestructive focused pulsed-laser technique is used to investigate single event effects in the GaN HEMT devices, both before and after proton irradiation. Characteristics such as the peak amplitude, width, and total charge collected are investigated at various bias conditions and at different locations in the GaN HEMTs. The maximum charge collected is identified to be at the location corresponding to the peak electric field within the device. Defects within the GaN HEMTs induced by proton irradiation increase the time constant of the single event decay. Three distinct trapping time constants have been identified from extracted curve fits to the single event decay transient.
Band Gap Engineering of Wurtzite-Type Narrow Band Gap Oxide Semiconductor β-CuGaO2
Authors: Omata Takahisa , Mizuno Yuki , Nagatani Hiraku , Suzuki Issei , Kita Masao
Published: February 2020

β-CuGaO2 is an oxide semiconductor possessing wurtzite-derived β-NaFeO2 structure. Its band gap is 1.47 eV in near-infrared region, and the first principles calculation indicates that it is a direct band gap semiconductor. Therefore, this material is expected to be applicable to optoelectronic devices working in near-infrared region. When the band gap of β-CuGaO2 is widened into visible region, the material is expected to be applicable to visible LEDs and lasers, photocatalyst and so on. In the present study, we demonstrated band gap engineering of β-CuGaO2 by alloying with β-CuAlO2 and β-LiGaO2 possessing wurtzite-derived β-NaFeO2 structure in order to widen the band gap. Cu(Ga1-xAlx)O2 alloys were prepared by ion-exchange of Na+ ions in β-Na(Ga1-xAlx)O2 with Cu+ ions in CuCl at 250 °C for 48 h under vacuum. (Cu1-xLix)GaO2 alloys were prepared by ion-exchange of Cu+ ions in β-CuGaO2 with Li+ ions in LiCl at 300 °C for 48 h under vacuum. Wurtzite-type β-phases were obtained in 0≤x≤0.7 for Cu(Ga1-xAlx)O2 system and in 0≤x≤1 for (Cu1-xLix)GaO2 system.

In β-Cu(Ga1-xAlx)O2, the optical band gap increased linearly with the increasing alloying level; no band gap bowing appeared in the present system. The band gap of β-CuGaO2 was widened up to 2.1 eV at β-Cu(Ga0.3Al0.7)O2; this energy corresponds to red light. In β-(Cu1-xLix)GaO2, the energy band gap increased almost linearly with the increasing alloying level up to x~0.9; the largest band gap in this composition range was 3.0 eV corresponding to violet light at β-(Cu0.11Li0.89)GaO2. When the alloying level increased further, the band gap steeply increased from 3.0 eV at x=0.89 to 5.6 eV at x=1. The valence band X-ray photoelectron spectra of β-(Cu1-xLix)GaO2 indicated that the steep increase in energy band gap from x~0.9 to 1 is attributed to that the Cu 3d contribution around the top of the valence band electronic states vanishes for the alloys with x>0.9. These results indicate that the energy band gap of β-CuGaO2 is highly controllable in the wavelength region from near-infrared to entire visible lights. Thus, it is expected that β-CuGaO2 opens new applications of oxide semiconductors in devices working in visible region.
Necessary Thickness of Au Capping Layers for Room Temperature Bonding of Wafers in Air Using Thin Metal Films with Au Capping Layers
Authors: Uomoto Miyuki , Shimatsu Takehito
Published: February 2020

Room temperature bonding of wafers using thin metal films is applicable to any mirror-polished wafers, moreover, the bonded metal films can be used for electrical/thermal conductions and optical reflections. For this study, room temperature bonding of wafers in air using 10~300 nm-thick Ag, Cu, Al films with 2~30 nm-thick thin Au capping layers was examined, and necessary thickness of Au capping layer to bond wafers in air was discussed.

2-inch diameter micro-polished quarts glass wafers were used for this study. The Ti films (1 nm thickness) were used as underlayers to enhance the adhesion strength of the deposited films on the wafer surface. After the sputter film deposition on the surfaces of two wafers, bonding was accomplished in air of a clean room (20°C, 50% moisture level, class 100). No substrate heating was conducted during deposition or the bonding processes.

Bonding in air could be accomplished using 20 nm-thick Ag, Cu films with 2 nm-thick Au capping layers without any loading pressure: once the nucleation of recrystallization at Au–Au interface of capping layers was formed, the recrystallization was propagated immediately, and the bonding was completed over the entire bonded area. 2 nm-thick Au capping layer was effective to avoid oxidation of the surfaces of these metal films in air and to nucleate the recrystallization between the connected films in the bonding process. Actually the surface energy at the bonded interface, evaluated using the blade method, was much higher than the surface energy of Au films.

Necessary thickness of Au capping layer for 20 nm-thick Al films was 6 nm or more, which is 3 times thicker than those for Ag and Cu films. It is reasonable to infer that the small surface energy of Al films caused island-like initial film-growth of Au films deposited on Al films, resulting in the increase of Au capping layer thickness. Actually AMF images supported this consideration.

Au capping layer thickness necessary for bonding increased as the thickness of metal films increased. For instance, 20 nm-thick Au capping layer was necessary for bonding using 300 nm-thick Al films. Moreover, loading pressure was necessary for bonding using thick metal films. These were mainly caused by an increase of the surface roughness of the metal films. Necessary thickness of Au capping layer depended on materials of metal films, however, was 1/10 or less of the thicknesses of the metal films in the present thickness range.
Combined Surface Activated Bonding Technique for Hydrophilic SiO2-SiO2 and Cu-Cu Bonding
Authors: He Ran , Fujino Masahisa , Yamauchi Akira , Suga Tadatomo
Published: February 2020

As an evolution of the Cu-Cu bonding and SiO2-SiO2 bonding, Cu/SiO2 hybrid bonding is a promising approach to the emerging three-dimensional (3D) integration of microelectronic/photonic systems, since it obtains both direct metal interconnection and enhanced thermal/mechanical stability with a seamless bonding structure during the single bonding process.1,2 However, because of the different features of Cu-Cu and SiO2-SiO2 bonding, Cu/SiO2 hybrid bonding at low temperatures of no more than 200 °C remains challenging. For instance, the Cu-Cu thermo-compression bonding is typically conducted in vacuum or dry protecting/reducing atmospheres after removal of surface oxides,3–7 while the SiO2-SiO2 bonding needs a humid environment to facilitate termination of Si-OH bonding sites.8–12 It is highly desired to develop a new bonding process that is effective for both Cu-Cu and SiO2-SiO2 bonding in H2O-free ambient, such as vacuum, for improvement of the Cu/SiO2 hybrid bonding.

Recently, we proposed a combined surface-activated bonding (SAB) method, which involves a combination of surface bombardment using a Si-containing Ar beam and prebonding attach-detach procedure prior to bonding in vacuum. High SiO2-SiO2 bonding strength of close to the Si bulk fracture strength has been realized at 200 °C. In this paper, we report our recent results of Cu-Cu and SiO2-SiO2 bonding by using the combined SAB method. The mechanism is discussed to understand the present low-temperature bonding technique.

References

1. L. D. Cioccio et al., J. Electrochem. Soc., 158, P81–P86 (2011).

2. H. Moriceau et al., Microelectron. Reliab., 52, 331–341 (2012).

3. W. Yang, M. Akaike, M. Fujino, and T. Suga, ECS J. Solid State Sci. Technol., 2, P271–P274 (2013).

4. W. Yang, M. Akaike, and T. Suga, IEEE Trans. Compon. Packag. Manuf. Technol., 4, 951–956 (2014).

5. B. Rebhan and K. Hingerl, J. Appl. Phys., 118, 135301 (2015).

6. T. H. Kim, M. M. R. Howlader, T. Itoh, and T. Suga, J. Vac. Sci. Technol. A, 21, 449–453 (2003).

7. A. Shigetou, T. Itoh, K. Sawada, and T. Suga, IEEE Trans. Adv. Packag., 31, 473–478 (2008).

8. Q.-Y. Tong and U. M. Gösele, Adv. Mater., 11, 1409–1425 (1999).

9. T. Suni, K. Henttinen, I. Suni, and J. Mäkinen, J. Electrochem. Soc., 149, G348–G351 (2002).

10. F. Fournel et al., ECS J. Solid State Sci. Technol., 4, P124–P130 (2015).

11. H. Takagi, J. Utsumi, M. Takahashi, and R. Maeda, ECS Trans., 16, 531–537 (2008).

12. R. He, M. Fujino, A. Yamauchi, and T. Suga, Jpn. J. Appl. Phys., 54, 030218 (2015).
Edge Water Penetration in Direct Bonding Interface
Authors: Rieutord François , Tardif Samuel , Landru Didier , Kononchuk Oleg , Larrey Vincent , Moriceau Hubert , Tedjini Marwan , Fournel Frank
Published: February 2020

A bonding interface between wafers usually exhibits a narrow gap due to the imperfect compression and matching of the facing wafer surface asperities. When hydrophilic bonding is considered, this gap can be partly filled with water originating from the adsorbed water before bonding or entering the gap from the surrounding atmosphere when bonded. The kinetics of water diffusion through the gap has been studied using two different techniques: X-ray reflectivity is able to monitor the interface density changes associated to the water front progression. The water intake is also revealed through defect creation upon annealing, creating a rim-like pattern whose extent also gives the water diffusion law. At room temperature, the kinetics observed by either techniques is consistent with Lucas-Washburn law for diffusion through a gap width smaller than 1nm. The distinction between adsorbed solid-like water and the additional water drawn in the assembly by capillarity will be discussed.
(Invited) Low-Temperature Processed and Self-Aligned InGaZnO Thin-Film Transistor with an Organic Gate Insulator for Flexible Device Applications
Authors: Furuta Mamoru , Toda Tatsuya , Tatsuoka Gengo , Magari Yusaku
Published: February 2020

Recently, metal-oxide thin-film transistors (TFTs) have attracted considerable attention for use in next-generation flat panel displays. An amorphous InGaZnO (IGZO) semiconductor is widely accepted as a promising channel material for TFT applications owing to its outstanding electrical properties. Moreover, since oxide semiconductor can be deposited even at room temperature by sputtering, it is recognized as a promising material for flexible device applications. From the standpoint of flexible devices, an organic insulating material is a good candidate for gate insulator (GI) even for the oxide thin-film transistors (TFTs).

In this presentation, a self-aligned and top-gated IGZO TFT with an organic gate insulator was demonstrated at a maximum processing temperature of 150 ºC. First, the controlling methods of the hybrid interface between the InGaZnO channel and the organic gate insulator were investigated. It was demonstrated that an organic protection layer of the IGZO channel and controlling the oxygen content in the IGZO channel are effective to achieve good performance TFTs at low processing temperature; however, it was also revealed that an excess oxygen acted as an electron trap existing at the IGZO/GI interface and degraded the TFT’s reliability. Second, carrier concentration in the IGZO was selectively controlled by helium plasma treatment with a substrate bias for source and drain (S/D) regions of self-aligned TFT. It was revealed that lateral diffusion from S/D extension to the IGZO channel was influenced by the doping methods.

We achieved a self-aligned and top-gated IGZO TFT with an organic gate insulator that was fabricated at a maximum processing temperature of 150 ºC. Field effect mobility of over 10 cm2/Vs and subthreshold swing of below 0.2 V/dec. have been obtained. Details will be discussed at the conference.
(Invited) Selection of Channel Layer for the Vertical Oxide TFT
Authors: Park Sang-Hee Ko , Yeom Hye-In , Hwang Chi-Sun , Moon Geumbi , Ko Jong-Beom , Nam Yunyong
Published: February 2020

With the development of the virtual reality and augmented reality displays, ultra-high resolution displays become one of the big concerns. People would not be bothered by display pixels when taking closer look at display with the resolution higher than 2000 ppi. The most important factor in the ultra-high resolution display is the pixel area and the smallest TFT size would be the first criteria in the TFT point of view.

Although back channel etch (BCE) TFT and self-aligned (SA) TFT have been used for driving high resolution LCD and OLED, respectively, typical planar structured TFT would not permit display with ultra-high resolution. The vertical TFT with the smallest pixel pitch value among the TFT structures is suitable candidate. Furthermore, channel length of the vertical TFT can be precisely controlled by the thin film thickness of spacer. This results in high and uniform on-current of TFT. Meanwhile, vertical TFT can also provide channel length longer than the sub-pixel length. When we have to apply high gate voltage depending on the display mode, TFT with longer channel length within smaller sub-pixel size would be necessary.

One of the advantages of oxide TFTs lies in the freedom of selection of architecture, materials, and process depending on the device application. Considering the main issue in the vertical TFT, the step coverage of active layer, oxide TFT seems to be the best selection. Oxide semiconductor and gate insulator used for the oxide TFT can be deposited by means of plasma enhanced atomic layer deposition (PEALD), which provides excellent step coverage of films.

One of the issues in vertical oxide TFT is the relatively high off-current depending on the mobility of TFT due to the short channel length. Here, we compare the performance of vertical oxide TFTs with the variation of semiconductor’s carrier density. By virtue of the easiness for the modifying carrier concentration of InOx based semiconductor, we could adjust the mobility of vertical TFT with low off-current. Vertical TFT with InOx shows 1.26 mA at Vg = 5 V and Vds = 2.1 V, S.S of 0.14 V/dec., on/off ratio of 107, and Von of -1.8V. Meanwhile at the same driving condition, IGZO shows on-current of 0.23 mA, S.S of 0.12 V/dec., on/off ratio of 108 and Von of -0.2V.

We will discuss the best selection for the channel layer of vertical TFT depending on the display mode and show the optimized TFT performance depending on the carrier concentration of semiconductors.
Stretched-Exponential Trends in a-Igzo Tfts
Authors: Zhou Fan , Chiang Tsung Han , Wager John F
Published: February 2020

A bias temperature stress (BTS) investigation of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) is undertaken using the stretched-exponential (SE) relation to model the threshold voltage shift (ΔVTH) as a function of time, temperature, and applied gate voltage. Explicitly, the SE equation employed herein is described as ΔVTH (t, T, VG) = (VG-VTH0) (1-exp(-(t/τ)β)), where VTH0 is the initial unstressed TFT threshold voltage, τ is a trapping time, τ = τ0exp(Eτ/kBT), where τ0 is a trapping time prefactor, Eτ is an energy barrier, and β is an energy barrier parameter [1, 2]. Simulation indicates that a larger τ and/or β results in less ΔVTH, i.e., a more stable a-IGZO TFT. An alternate form of the SE voltage prefactor (VG-VTH0) involves the use of V0, which is identified as a saturation voltage [3, 4]. Either prefactor formulation can be used to accurately fit ΔVTH trends for stress times less than ~3 hours. However, as shown in Fig. 1, fitting of a sample data set restricted to stress times less than 3 hours leads to dramatically different saturated threshold voltage shifts, even though both prefactors precisely fit the initial 2 hours of data (see insert of Fig. 1). Physically, this is associated with the fact that the (VG-VTH0) prefactor corresponds to the applied overvoltage which explicitly depends on VG, while V0 is independent of VG. Simulation is useful for revealing various kinds of ΔVTH (t, T, VG) trends. For example, Fig. 2(a) shows that the relevant energy barrier, Eτ, associated with ΔVTH (10-5 s, 300 K, VG = 30 V) is very narrow for β = 1 and broadens dramatically as β → 0. The Eτ-β relationship is better represented by taking the derivative of ΔVTH with respect to Eτ, as shown in Fig. 2(b), where the magnitude of the peak increases and the distribution of Eτ narrows as β increases. As a larger β is indicative of a more stable TFT, it is reasonable to theorize that a narrow Eτ distribution is meaningful in predicting stable long-term TFT reliability.

[1] M. Mativenga, et al., “High stable amorphous indium-gallium-zinc-oxide thin-film transistor using an etch-stopper and a via-hole structure,” Journal of Information Display, Vol. 12, No. 1, 47-50 (2011)

[2] T. Y. Hsieh, et al., “Investigating degradation behavior of InGaZnO thin-film transistors induced by charge-trapping effect under DC and AC gate bias stress,” Thin Solid Films, 528, 53-56 (2013)

[3] J. M. Lee, et al., “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Applied Physics Letters, 93, 093304 (2008)

[4] S. Park, et al., “Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors,” Microelectronics Reliability, 52, 2215-2219 (2012)

Figure 1
Comprehensive Depletion-Mode Model for TFT Assessment
Authors: Zhou Fan , Chiang Tsung Han , Wager John F
Published: February 2020

A comprehensive depletion-mode model is developed to describe depletion-mode thin-film transistor (TFT) behavior [1]. This model is distinctly different than the square-law model, which accurately describes enhancement-mode TFT behavior and establishes the equations normally employed for carrier mobility extraction. In the comprehensive depletion-mode model, bulk mobility (μBULK) and interface mobility (μINT) are distinguished based on the assumption that carrier transport can occur within an accumulation layer and/or within the ‘bulk’ of the channel. In this work, the comprehensive depletion-mode model is used to estimate the mobility of p-channel TFTs and solution-processed n-channel TFTs, and also to estimate the free carrier concentration of within the ‘bulk’ of the channel when a TFT exhibits depletion-mode behavior. Simulation reveals that the estimated interface mobility of a depletion-mode TFT is often overestimated when mobility is improperly extracted using the square-law model.

[1] F. Zhou et al., “Mobility assessment of depletion-mode oxide thin-film transistors using the comprehensive depletion-mode model,” ECS Journal of Solid State Science and Technology, 3(9), Q3027-Q3031 (2014)
Enhancement of Field-Effect Mobility By Controlling the Surface Potential of PVP Insulator in Pentacene-Based Thin Film Transistors
Authors: Jang Yunseok , Kim Kwang-Young
Published: February 2020

In recent years, the surface potential at insulator/semiconductor interface has received considerable attention for improving the electrical performance of various electronic and optoelectronic device. Many studies of the effect of a surface potential at insulator/semiconductor interface have been carried out. Most of these studies have focused on achieving efficient hole or electron injection at the inorganic insulator (i.e., such as SiO2)/ semiconductor interface. But the surface potential effects at the polymer insulator/semiconductor interface of organic thin-film transistors have not been sufficiently studied. In this presentation, we focus in particular on the effects of varying the surface potential on the polymer insulator/semiconductor interface.

We demonstrated a method of reducing the surface energy in a polymer insulator for use in high-performance OTFTs. The surface energy of a poly(4-vinyl phenol) insulator was reduced from 45 mJ/m2 to 32 mJ/m2 through treatment with UV/ozone and ODTS. These treatments facilitated the deposition of the pentacene film onto the ODTS-treated poly(4-vinyl phenol) insulator to prepare a single phase that showed better π-orbital overlap among the pentacene molecules. As a result, the field-effect mobility in the insulator increased by 209 %. These results demonstrated that adjusting the surface energy of a polymer insulator provided a suitable approach to enhancing the performances of OTFTs.

Acknowledgments

This study was supported by the R&D program of the Korea Research Council for Industrial Science and Technology of Republic of Korea (Grant 2015K000217/ 10052802/ KM3710/ NK186C/ SC1130/ MO5970/ NM8270).
Solution-Processed Nanoscale Carbon Nanotube Thin-Film Transistors Fabricated By Electromigration
Authors: Jeon Jun-Young , Ha Tae-Jun
Published: February 2020

Solution-processed carbon nanotube thin-film transistors (CNT-TFTs) have been of great scientific and technological attention due to the merits of fabrication processes and structual integration. Significant improvements in material design and process optimization have resulted in high performance CNT-TFTs which are comparable to or better than conventional ones. However, it is still difficult to realize sub-nano-scaled solution-processed CNT-TFTs suitable for integrated circuits and systems. In order to fabricate a sub-nm gap between source and drain electrodes in the channel region of the solution-processed CNT-TFTs, the DC breakjunction method by applying the electric field to trap Au nanoparticles and to form a short bridge was investigated through electromigration. A gradually ramping electric bias was imposed on the contact junctions, thereby breaking the bridge into a sub-nm gap in TFTs. The combination of surface treatment and vacuum thermal annealing increased the density of the nanotubes in the channel region and improved charge injection between the channel and the source electrode. In this presentation, we will demonstrate the process optimization to realize high-performance solution-processed CNT-TFTs with a channel length of ~20 nm and discuss the effect of surface treatment and vacuum thermal annealing on device performance.
(Invited) Growth of Transfer-Free 2D Materials: From Controllable Growth to Material Characterizations and Device Applications
Authors: Chueh Yu-Lun
Published: February 2020

Novel condensed matter systems can be understood as new compositions of elements or old materials in new forms. According to the definition, various new condensed matter systems have been developed or are under development in the recent years. 2D layered materials, including graphene, transition metal dichalcogenides (TMDs) allow the scaling down to atomically thin thicknesses and possess unique physical properties under dimensionality confinement. Chemical vapor deposition (CVD) process is the most popular approach for all kind of 2D materials due to its high yield and quality. Nevertheless, the need of high temperature and the relative long process time within each cycle hinders for commercial development in terms of production cost. However, the transfer procedure has become one of the major limitations of the overall performance.

In the first part of my talk, I will present several approaches, including ultra-fast microwave heating, plasma selective reaction, controlled segregation process by laser irradiation and metal vapers-assisted growth processes developed in my lab these years to directly grow graphene with controllable thicknesses on arbitrary substrates without any extra transfer process. In the 2nd part of my talk, I will also introduce development of various methods, including laser irradiation assisted-selenization (LIAS) process, fast microwave annealing and plasms enhance selenization processes on different two dimensional transition metal dichalcogenides materials in my lab. The detailed formation mechanisms, microstructures and physical performances as well as its applications on field emission and gas sensors based on these two 2D materials were reported and investigated.
High Aspect Ratio Single Crystal of Cesium Iodide Column
Authors: Chen Chien Chon , Chen Shih Hsun , Yang Jheng En , Huang Ker Jer , Jheng Wern Dare
Published: February 2020

Cesium iodide (CsI), which is used in the phosphor layer of a scintillator plate, exhibits a relatively high conversion rate of X- or g-rays to visible light. Important requirements for the scintillator materials used in the applications include high light output, transparency to the light it produces, high stopping efficiency, fast response, good proportionality, low cost, and availability in large volume In order to simplify and reduce the cost of the scintillator deposition process, we deposit the scintillator of a CsI into a high aspect ratio anodic aluminum oxide (AAO) template to produce CsI columns of nano and submicron sizes. The scintillator material of CsI columns were formed in the AAO template by a non-vacuum method. When the CsI melt is injected a confined to an AAO channel with a high aspect ratio, it grows as a stable single-crystal column with smooth surfaces, free of dendrites and grain boundaries. In this research, we design a novel cooling-function of electrochemical mold for a high quality AAO fabrication and compare the CsI wire and column formation by non-vacuum injection method in a AAO template.
Fluorescence Microscopy Characterization of Patterned Nano-Crystalline Quantum Dot Films
Authors: Sabeeh Ala , Price Jared , Ruzyllo Jerzy
Published: February 2020

This experiment is a continuation of the study concerned with the lift-off based patterning of nanocrystaline quantum dot (NQD) films [1]. The ultra-thin films formed using colloidal solutions of nanocrystalline quantum dots show good promise in display/LED, as well as nano-labeling applications between others. Regardless of application, to become a part of the functional device the NQD film must be patterned accordingly.

Following on the experiments demonstrating effectiveness of the lift-off process in patterning NQD films with resolution down to 1 µm [1] further investigation of the performance of the proposed patterning scheme needed to be carried out. The goal of this contribution is to study uniformity of surface coverage with lift-off patterned NQD films by means of fluorescence microscopy.

When exposed to UV light the NQDs feature high photoluminescence with intensity depending on the dots size. The fluorescence microscopy allows capturing the intensity to obtain information about the NQD film uniformity. As a result, using images obtained by means of fluorescence microscopy and employing dedicated image processing tools information regarding film uniformity, pattern definition accuracy, and average intensity can be derived. Also, the fluorescence image can be transferred into grey scale to study its histogram plot and get information about intensity distribution across the NQD patterns.

In this study silicon wafers used as substrates are first covered by spin coating with a layer of positive 1805 photoresist to the thickness of about 420 nm and then cured at 100oC. The resist covered wafers were subsequently exposed through the standard Cr-photomask in an aligner/exposure and developed in photoresist developer (351) to create the required patterns [1]. After that, NQDs were blanked deposited using mist deposition technique. The NQD deposited were CdSe/ZnS core/shell featuring average diameter of 6.5 nm and corresponding red (620 nm) emission wavelength. Then, the photoresist removal performed using either dry or wet lift-off. The dry lift-off applied using O2 plasma system and the wet lift-off used acetone dissolution [2].

Figure 1 demonstrates the fluorescence image for NQD patterned film and its intensity distribution. The intensity analysis of the patterns after the lift-off process is considered in terms of an average intensity. The results obtained in this study give further insights into the process of lift-off patterning of nano-crytalline quantum dot films and demonstrate feasibility of the proposed approach.

In the full account of this work a complete set of experimental results obtained in the course of this investigation is presented and more detailed analysis of fluorescence images provided.

References [1] A. Sabeeh, Y.Thakur, and J. Ruzyllo, ECS Transactions 69.12 (2015): 53-57. [2] J. C. Chao, A. Kshirsagar, and J. Ruzyllo, ECS Trans., 58(6), 311 (2013).

Figure 1
(Invited) High Density Individually Addressable Nanowire Arrays for Intracellular Mapping of Neuronal Activity
Authors: Dayeh Shadi
Published: February 2020

Critical to the large scale mapping of neuronal activity is the ability to develop neurotechnologies that can interface with neurons at nanometer scales and that can measure the smallest potential fluctuations of each cell in a neuronal network and the response of these cells to added chemicals and drugs. We developed a robust and scalable fabrication process for ultra-high density neuronal probes on insulating substrates. Arrays at an electrode density of 10 million/cm2 enabled recording of single unit and subthreshold activity in both intracellular and extracellular configurations from rat, human induced pluripotent stem cells and cortical neurons. We validated by transmission electron microscopy that positively measured potentials corresponded to intracellular penetrating nanowires and that the cells survived the natural nanowire penetration for 6 weeks. This exhibits the longest ever intracellular recording with subthreshold sensitivity from neuronal cultures and have implications for highly predictive drug screening applications.
(Invited) Layered (III-Se) Photodetectors
Authors: Wang Kaiyou
Published: February 2020

Due to the unique properties of the 2D materials, the photodetectors based on two dimensional (2D) materials have attracted considerable attentions.

For both the bottom and top Ti/Au contacted metal-semiconductor-metal (MSM) photodetectors in using layered GaSe and InSe devices, we systematically investigate the dependence of the photoresponsivity on the spacing distance. Through spatially resolved photocurrent measurements, we find the photocurrent active region is always close to the Schottky barrier with higher electrical potential. A theoretical model has also been developed to well explain for the underlying physics for the photoresponse [1]. The response time can be further reduced down to a few hundreds of microseconds for the devices with single layer graphene as metallic electrodes [2].

References

(1)  Y. F. Cao, K. M Cai, P. A. HU, L. X. Zhao, T. F. Yan, W. G. Luo, X. H. Zhang, X. G. Wu, K. Y. Wang and H. Z. Zheng, Scientific Reports, 5, 8130 (2015).

(2) W. G. Luo, Y. F.  Cao, P. A. Hu, K. M. Cai, Q. Feng, F. G. Yan, T. F. Yan, X. H. Zhang and K. Y. Wang, Adv. Opt. Mater., 3,(2015)1418.
Chemical Vapor Deposition Growth of High Density Perovskite Nanowire Arrays and Their Applications in Optoelectronic Devices
Authors: Zhang Daquan , Gu Leilei , Tavakoli Mohammad Mahdi , Fan Zhiyong
Published: February 2020

Organic-inorganic halide perovskite materials have emerged as one kind of promising optoelectronic materials with greatly attractive performance in corresponding devices because of their unique and excellent optoelectronic properties. In this work, we developed a novel chemical vapor deposition (CVD) method using the metal nanoclusters to grow three-dimensional (3-D) arrays of single crystalline perovskite nanowires (NWs) with well-defined geometry. By utilizing different anodic aluminum oxide (AAO) templates, we can precisely control the diameter, pitch, and depth of NWs. The as-obtained NWs are well-embedded in the optically transparent and mechanically robust templates, and thus can significantly improve the stability of materials. The NW arrays have been fabricated into optoelectronic devices including photodetectors and solar cells and their device performance has been systematically investigated. Finally, combining the intriguing electrical and optical properties of perovskite materials, such 3-D nanowire arrays may find a broad spectrum of applications for high performance electronics and optoelectronics.
Flexible High Performance Hybrid Azo/Ag-Nanowire/Azo Sandwich Structured Transparent Conductors for Flexible Cu(In,Ga)Se2 Solar Cell Applications
Authors: Thomas Stuart Richard , Chueh Yu-Lun , Tsai Wen-Chi , Wang Zhiming
Published: February 2020

Transparent conducting oxides (TCOs) are an important class of materials used in a wide range of optoelectronic technologies, including solar cells, flat-panel displays and organic light emitting diodes, and presently there is a strong drive toward the development of solar cell technologies on flexible platforms that are robust, portable and flexible enough to conform to unusual shapes, particularly building structures. Tin-doped indium oxide (ITO) is currently the commonly chosen TCO for use in non-flexible applications; however, its brittleness limits its application on flexible substrates, whilst the scarcity of indium maintains an undesirably high cost for use in solar cell applications. As such, it is important that ITO alternatives are developed with suitably flexible mechanical and electronic properties, which can also be fabricated at reasonable costs. The chalcopyrite absorber, copper indium gallium selenide, Cu(In,Ga)Se2, has a very high absorption coefficient (~104 cm-1), requiring only thin-films (~1 μm) for efficient solar cell fabrication, making it thin enough for flexible applications. However the lack of a high quality flexible TCO has, to date, limited its use in such applications.

In this work, we present a new approach for the fabrication of high performance transparent electrodes suitable for flexible CIGS solar cell applications, using a stacked Al-doped ZnO/Ag-nanowire/Al-doped ZnO (AAA) sandwich structure.1 In our AAA electrode the Al-doped ZnO (AZO) layers act as a broad area charge carrier collector and protective encapsulant for the Ag-nanowire network. Concurrently, the Ag-nanowires provide low-resistance, long-range pathways that aid the extraction of charge carriers, but more importantly, they aid in maintaining a low resistivity for our total electrode structure, by maintaining charge transport pathways across cracks that develop in the AZO during repeated strenuous bending. By optimising of our Ag-nanowire network density, AZO deposition and AAA stack structure we are able produce a transparent electrode with comparable resistivity and transparency performance to that of ITO. These combined benefits enable us to fabricate CIGS solar cells that are able to maintain 95% of their initial power conversion efficiency, following 1000 bending cycles. In comparison, devices fabricated using equivalent thickness AZO and ITO electrodes are only able to maintain 57 and 5%, respectively, due to crack formation and delamination of the films. This AAA sandwich structure electrode could therefore serve as a high-performance electrode for numerous flexible optoelectronic applications.

1. W.-C. Tsai, S. R. Thomas, C.-H. Hsu, Y.-C. Huang, J.-Y. Tseng, T.-T. Wu, C.-h. Chang, Z. M. Wang, J.-M. Shieh, C.-H. Shen and Y.-L. Chueh, Journal of Materials Chemistry A, 2016.