Flip chip reliability and intermetallic compounds for SIP module
Authors: Morard Adrien , Riou Jean-Christophe , Pares Gabriel 
Published: December 2018

In the aeronautical field, the electronic integration roadmaps show that the weight and the volume dedicated to on-board electronics must be reduced by a factor of 4 to 10 compared to the existing ones for the most recurrent functions in the next years.

This work is an opening to new technological solutions to increase our ability to save space while improving the overall reliability of the system.

The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by our laboratory have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits provided by this substrate is the possibility to embed some surface mount technologies (SMT), some bare chips or some integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of I/Os interconnection pitches leading to very aggressive integration down to 50μm.

Secondly, a 3D stack with 3 levels of components, as described above, leads to 2 or 3 REACH compliant sequential assembly processes, depending of the needs. In order to consider all the solutions for an optimized overall integration with high reliability, this work focuse on the study one simple SIP which includes the top die assembled by flip-chip. For the flip chip hybridization on organic interposers copper pillars technologies will be studied. The objective is to understand in depth the processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly.

Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chip's thicknesses (50 to 200 μm), chip's sizes (2 to 8 mm), bump structures (diameter), the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip chip on the silicon and on the organic substrate. We are also designing the both configurations of substrates. Only the production of the organics part is outsourced.

Fourth, for all assemblies thermos-cycling test results will be evaluated with thermo mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivated. The aim is to obtain dimensional criteria based on stress versus deformation responses.

Lastly intermetallic formation will be evaluated using EBSD analysis to obtain better understanding of copper pillar failures for this specific bumps size. Issued information's will be exploited for designing the future functional SIP.

The ultimate goal of this work is finally to define mechanical design rules that can then be used in functional SiP modules.